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Commit | Line | Data |
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2c0262af FB |
1 | /* |
2 | * ARM virtual CPU header | |
5fafdf24 | 3 | * |
2c0262af FB |
4 | * Copyright (c) 2003 Fabrice Bellard |
5 | * | |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
9 | * version 2 of the License, or (at your option) any later version. | |
10 | * | |
11 | * This library is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU Lesser General Public | |
8167ee88 | 17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. |
2c0262af FB |
18 | */ |
19 | #ifndef CPU_ARM_H | |
20 | #define CPU_ARM_H | |
21 | ||
3cf1e035 FB |
22 | #define TARGET_LONG_BITS 32 |
23 | ||
9042c0e2 TS |
24 | #define ELF_MACHINE EM_ARM |
25 | ||
9349b4f9 | 26 | #define CPUArchState struct CPUARMState |
c2764719 | 27 | |
9a78eead SW |
28 | #include "config.h" |
29 | #include "qemu-common.h" | |
022c62cb | 30 | #include "exec/cpu-defs.h" |
2c0262af | 31 | |
6b4c305c | 32 | #include "fpu/softfloat.h" |
53cd6637 | 33 | |
1fddef4b FB |
34 | #define TARGET_HAS_ICE 1 |
35 | ||
b8a9e8f1 FB |
36 | #define EXCP_UDEF 1 /* undefined instruction */ |
37 | #define EXCP_SWI 2 /* software interrupt */ | |
38 | #define EXCP_PREFETCH_ABORT 3 | |
39 | #define EXCP_DATA_ABORT 4 | |
b5ff1b31 FB |
40 | #define EXCP_IRQ 5 |
41 | #define EXCP_FIQ 6 | |
06c949e6 | 42 | #define EXCP_BKPT 7 |
9ee6e8bb | 43 | #define EXCP_EXCEPTION_EXIT 8 /* Return from v7M exception. */ |
fbb4a2e3 | 44 | #define EXCP_KERNEL_TRAP 9 /* Jumped to kernel code page. */ |
426f5abc | 45 | #define EXCP_STREX 10 |
9ee6e8bb PB |
46 | |
47 | #define ARMV7M_EXCP_RESET 1 | |
48 | #define ARMV7M_EXCP_NMI 2 | |
49 | #define ARMV7M_EXCP_HARD 3 | |
50 | #define ARMV7M_EXCP_MEM 4 | |
51 | #define ARMV7M_EXCP_BUS 5 | |
52 | #define ARMV7M_EXCP_USAGE 6 | |
53 | #define ARMV7M_EXCP_SVC 11 | |
54 | #define ARMV7M_EXCP_DEBUG 12 | |
55 | #define ARMV7M_EXCP_PENDSV 14 | |
56 | #define ARMV7M_EXCP_SYSTICK 15 | |
2c0262af | 57 | |
403946c0 RH |
58 | /* ARM-specific interrupt pending bits. */ |
59 | #define CPU_INTERRUPT_FIQ CPU_INTERRUPT_TGT_EXT_1 | |
60 | ||
7c1840b6 PM |
61 | /* Meanings of the ARMCPU object's two inbound GPIO lines */ |
62 | #define ARM_CPU_IRQ 0 | |
63 | #define ARM_CPU_FIQ 1 | |
403946c0 | 64 | |
c1713132 AZ |
65 | typedef void ARMWriteCPFunc(void *opaque, int cp_info, |
66 | int srcreg, int operand, uint32_t value); | |
67 | typedef uint32_t ARMReadCPFunc(void *opaque, int cp_info, | |
68 | int dstreg, int operand); | |
69 | ||
f93eb9ff AZ |
70 | struct arm_boot_info; |
71 | ||
6ebbf390 JM |
72 | #define NB_MMU_MODES 2 |
73 | ||
b7bcbe95 FB |
74 | /* We currently assume float and double are IEEE single and double |
75 | precision respectively. | |
76 | Doing runtime conversions is tricky because VFP registers may contain | |
77 | integer values (eg. as the result of a FTOSI instruction). | |
8e96005d FB |
78 | s<2n> maps to the least significant half of d<n> |
79 | s<2n+1> maps to the most significant half of d<n> | |
80 | */ | |
b7bcbe95 | 81 | |
2c0262af | 82 | typedef struct CPUARMState { |
b5ff1b31 | 83 | /* Regs for current mode. */ |
2c0262af | 84 | uint32_t regs[16]; |
b90372ad | 85 | /* Frequently accessed CPSR bits are stored separately for efficiency. |
d37aca66 | 86 | This contains all the other bits. Use cpsr_{read,write} to access |
b5ff1b31 FB |
87 | the whole CPSR. */ |
88 | uint32_t uncached_cpsr; | |
89 | uint32_t spsr; | |
90 | ||
91 | /* Banked registers. */ | |
92 | uint32_t banked_spsr[6]; | |
93 | uint32_t banked_r13[6]; | |
94 | uint32_t banked_r14[6]; | |
3b46e624 | 95 | |
b5ff1b31 FB |
96 | /* These hold r8-r12. */ |
97 | uint32_t usr_regs[5]; | |
98 | uint32_t fiq_regs[5]; | |
3b46e624 | 99 | |
2c0262af FB |
100 | /* cpsr flag cache for faster execution */ |
101 | uint32_t CF; /* 0 or 1 */ | |
102 | uint32_t VF; /* V is the bit 31. All other bits are undefined */ | |
6fbe23d5 PB |
103 | uint32_t NF; /* N is bit 31. All other bits are undefined. */ |
104 | uint32_t ZF; /* Z set if zero. */ | |
99c475ab | 105 | uint32_t QF; /* 0 or 1 */ |
9ee6e8bb | 106 | uint32_t GE; /* cpsr[19:16] */ |
b26eefb6 | 107 | uint32_t thumb; /* cpsr[5]. 0 = arm mode, 1 = thumb mode. */ |
9ee6e8bb | 108 | uint32_t condexec_bits; /* IT bits. cpsr[15:10,26:25]. */ |
2c0262af | 109 | |
b5ff1b31 FB |
110 | /* System control coprocessor (cp15) */ |
111 | struct { | |
40f137e1 | 112 | uint32_t c0_cpuid; |
a49ea279 | 113 | uint32_t c0_cssel; /* Cache size selection. */ |
b5ff1b31 FB |
114 | uint32_t c1_sys; /* System control register. */ |
115 | uint32_t c1_coproc; /* Coprocessor access register. */ | |
610c3c8a | 116 | uint32_t c1_xscaleauxcr; /* XScale auxiliary control register. */ |
2be27624 | 117 | uint32_t c1_scr; /* secure config register. */ |
9ee6e8bb | 118 | uint32_t c2_base0; /* MMU translation table base 0. */ |
891a2fe7 PM |
119 | uint32_t c2_base0_hi; /* MMU translation table base 0, high 32 bits */ |
120 | uint32_t c2_base1; /* MMU translation table base 0. */ | |
121 | uint32_t c2_base1_hi; /* MMU translation table base 1, high 32 bits */ | |
b2fa1797 PB |
122 | uint32_t c2_control; /* MMU translation table base control. */ |
123 | uint32_t c2_mask; /* MMU translation table base selection mask. */ | |
124 | uint32_t c2_base_mask; /* MMU translation table base 0 mask. */ | |
ce819861 PB |
125 | uint32_t c2_data; /* MPU data cachable bits. */ |
126 | uint32_t c2_insn; /* MPU instruction cachable bits. */ | |
127 | uint32_t c3; /* MMU domain access control register | |
128 | MPU write buffer control. */ | |
b5ff1b31 FB |
129 | uint32_t c5_insn; /* Fault status registers. */ |
130 | uint32_t c5_data; | |
ce819861 | 131 | uint32_t c6_region[8]; /* MPU base/size registers. */ |
b5ff1b31 FB |
132 | uint32_t c6_insn; /* Fault address registers. */ |
133 | uint32_t c6_data; | |
f8bf8606 | 134 | uint32_t c7_par; /* Translation result. */ |
891a2fe7 | 135 | uint32_t c7_par_hi; /* Translation result, high 32 bits */ |
b5ff1b31 FB |
136 | uint32_t c9_insn; /* Cache lockdown registers. */ |
137 | uint32_t c9_data; | |
74594c9d PM |
138 | uint32_t c9_pmcr; /* performance monitor control register */ |
139 | uint32_t c9_pmcnten; /* perf monitor counter enables */ | |
140 | uint32_t c9_pmovsr; /* perf monitor overflow status */ | |
141 | uint32_t c9_pmxevtyper; /* perf monitor event type */ | |
142 | uint32_t c9_pmuserenr; /* perf monitor user enable */ | |
143 | uint32_t c9_pminten; /* perf monitor interrupt enables */ | |
b5ff1b31 FB |
144 | uint32_t c13_fcse; /* FCSE PID. */ |
145 | uint32_t c13_context; /* Context ID. */ | |
9ee6e8bb PB |
146 | uint32_t c13_tls1; /* User RW Thread register. */ |
147 | uint32_t c13_tls2; /* User RO Thread register. */ | |
148 | uint32_t c13_tls3; /* Privileged Thread register. */ | |
c1713132 | 149 | uint32_t c15_cpar; /* XScale Coprocessor Access Register */ |
c3d2689d AZ |
150 | uint32_t c15_ticonfig; /* TI925T configuration byte. */ |
151 | uint32_t c15_i_max; /* Maximum D-cache dirty line index. */ | |
152 | uint32_t c15_i_min; /* Minimum D-cache dirty line index. */ | |
153 | uint32_t c15_threadid; /* TI debugger thread-ID. */ | |
7da362d0 ML |
154 | uint32_t c15_config_base_address; /* SCU base address. */ |
155 | uint32_t c15_diagnostic; /* diagnostic register */ | |
156 | uint32_t c15_power_diagnostic; | |
157 | uint32_t c15_power_control; /* power control */ | |
b5ff1b31 | 158 | } cp15; |
40f137e1 | 159 | |
9ee6e8bb PB |
160 | struct { |
161 | uint32_t other_sp; | |
162 | uint32_t vecbase; | |
163 | uint32_t basepri; | |
164 | uint32_t control; | |
165 | int current_sp; | |
166 | int exception; | |
167 | int pending_exception; | |
9ee6e8bb PB |
168 | } v7m; |
169 | ||
fe1479c3 PB |
170 | /* Thumb-2 EE state. */ |
171 | uint32_t teecr; | |
172 | uint32_t teehbr; | |
173 | ||
b7bcbe95 FB |
174 | /* VFP coprocessor state. */ |
175 | struct { | |
9ee6e8bb | 176 | float64 regs[32]; |
b7bcbe95 | 177 | |
40f137e1 | 178 | uint32_t xregs[16]; |
b7bcbe95 FB |
179 | /* We store these fpcsr fields separately for convenience. */ |
180 | int vec_len; | |
181 | int vec_stride; | |
182 | ||
9ee6e8bb PB |
183 | /* scratch space when Tn are not sufficient. */ |
184 | uint32_t scratch[8]; | |
3b46e624 | 185 | |
3a492f3a PM |
186 | /* fp_status is the "normal" fp status. standard_fp_status retains |
187 | * values corresponding to the ARM "Standard FPSCR Value", ie | |
188 | * default-NaN, flush-to-zero, round-to-nearest and is used by | |
189 | * any operations (generally Neon) which the architecture defines | |
190 | * as controlled by the standard FPSCR value rather than the FPSCR. | |
191 | * | |
192 | * To avoid having to transfer exception bits around, we simply | |
193 | * say that the FPSCR cumulative exception flags are the logical | |
194 | * OR of the flags in the two fp statuses. This relies on the | |
195 | * only thing which needs to read the exception flags being | |
196 | * an explicit FPSCR read. | |
197 | */ | |
53cd6637 | 198 | float_status fp_status; |
3a492f3a | 199 | float_status standard_fp_status; |
b7bcbe95 | 200 | } vfp; |
426f5abc PB |
201 | uint32_t exclusive_addr; |
202 | uint32_t exclusive_val; | |
203 | uint32_t exclusive_high; | |
9ee6e8bb | 204 | #if defined(CONFIG_USER_ONLY) |
426f5abc PB |
205 | uint32_t exclusive_test; |
206 | uint32_t exclusive_info; | |
9ee6e8bb | 207 | #endif |
b7bcbe95 | 208 | |
18c9b560 AZ |
209 | /* iwMMXt coprocessor state. */ |
210 | struct { | |
211 | uint64_t regs[16]; | |
212 | uint64_t val; | |
213 | ||
214 | uint32_t cregs[16]; | |
215 | } iwmmxt; | |
216 | ||
d8fd2954 PB |
217 | /* For mixed endian mode. */ |
218 | bool bswap_code; | |
219 | ||
ce4defa0 PB |
220 | #if defined(CONFIG_USER_ONLY) |
221 | /* For usermode syscall translation. */ | |
222 | int eabi; | |
223 | #endif | |
224 | ||
a316d335 FB |
225 | CPU_COMMON |
226 | ||
9d551997 | 227 | /* These fields after the common ones so they are preserved on reset. */ |
9ba8c3f4 | 228 | |
581be094 | 229 | /* Internal CPU feature flags. */ |
918f5dca | 230 | uint64_t features; |
581be094 | 231 | |
983fe826 | 232 | void *nvic; |
462a8bc6 | 233 | const struct arm_boot_info *boot_info; |
2c0262af FB |
234 | } CPUARMState; |
235 | ||
778c3a06 AF |
236 | #include "cpu-qom.h" |
237 | ||
238 | ARMCPU *cpu_arm_init(const char *cpu_model); | |
b26eefb6 | 239 | void arm_translate_init(void); |
14969266 | 240 | void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu); |
2c0262af | 241 | int cpu_arm_exec(CPUARMState *s); |
494b00c7 | 242 | int bank_number(int mode); |
b5ff1b31 | 243 | void switch_mode(CPUARMState *, int); |
9ee6e8bb | 244 | uint32_t do_arm_semihosting(CPUARMState *env); |
b5ff1b31 | 245 | |
2c0262af FB |
246 | /* you can call this signal handler from your SIGBUS and SIGSEGV |
247 | signal handlers to inform the virtual CPU of exceptions. non zero | |
248 | is returned if the signal was handled by the virtual CPU. */ | |
5fafdf24 | 249 | int cpu_arm_signal_handler(int host_signum, void *pinfo, |
2c0262af | 250 | void *puc); |
84a031c6 | 251 | int cpu_arm_handle_mmu_fault (CPUARMState *env, target_ulong address, int rw, |
97b348e7 | 252 | int mmu_idx); |
0b5c1ce8 | 253 | #define cpu_handle_mmu_fault cpu_arm_handle_mmu_fault |
2c0262af | 254 | |
b5ff1b31 FB |
255 | #define CPSR_M (0x1f) |
256 | #define CPSR_T (1 << 5) | |
257 | #define CPSR_F (1 << 6) | |
258 | #define CPSR_I (1 << 7) | |
259 | #define CPSR_A (1 << 8) | |
260 | #define CPSR_E (1 << 9) | |
261 | #define CPSR_IT_2_7 (0xfc00) | |
9ee6e8bb PB |
262 | #define CPSR_GE (0xf << 16) |
263 | #define CPSR_RESERVED (0xf << 20) | |
b5ff1b31 FB |
264 | #define CPSR_J (1 << 24) |
265 | #define CPSR_IT_0_1 (3 << 25) | |
266 | #define CPSR_Q (1 << 27) | |
9ee6e8bb PB |
267 | #define CPSR_V (1 << 28) |
268 | #define CPSR_C (1 << 29) | |
269 | #define CPSR_Z (1 << 30) | |
270 | #define CPSR_N (1 << 31) | |
271 | #define CPSR_NZCV (CPSR_N | CPSR_Z | CPSR_C | CPSR_V) | |
272 | ||
273 | #define CPSR_IT (CPSR_IT_0_1 | CPSR_IT_2_7) | |
274 | #define CACHED_CPSR_BITS (CPSR_T | CPSR_GE | CPSR_IT | CPSR_Q | CPSR_NZCV) | |
275 | /* Bits writable in user mode. */ | |
276 | #define CPSR_USER (CPSR_NZCV | CPSR_Q | CPSR_GE) | |
277 | /* Execution state bits. MRS read as zero, MSR writes ignored. */ | |
278 | #define CPSR_EXEC (CPSR_T | CPSR_IT | CPSR_J) | |
b5ff1b31 | 279 | |
b5ff1b31 | 280 | /* Return the current CPSR value. */ |
2f4a40e5 AZ |
281 | uint32_t cpsr_read(CPUARMState *env); |
282 | /* Set the CPSR. Note that some bits of mask must be all-set or all-clear. */ | |
283 | void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask); | |
9ee6e8bb PB |
284 | |
285 | /* Return the current xPSR value. */ | |
286 | static inline uint32_t xpsr_read(CPUARMState *env) | |
287 | { | |
288 | int ZF; | |
6fbe23d5 PB |
289 | ZF = (env->ZF == 0); |
290 | return (env->NF & 0x80000000) | (ZF << 30) | |
9ee6e8bb PB |
291 | | (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27) |
292 | | (env->thumb << 24) | ((env->condexec_bits & 3) << 25) | |
293 | | ((env->condexec_bits & 0xfc) << 8) | |
294 | | env->v7m.exception; | |
b5ff1b31 FB |
295 | } |
296 | ||
9ee6e8bb PB |
297 | /* Set the xPSR. Note that some bits of mask must be all-set or all-clear. */ |
298 | static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask) | |
299 | { | |
9ee6e8bb | 300 | if (mask & CPSR_NZCV) { |
6fbe23d5 PB |
301 | env->ZF = (~val) & CPSR_Z; |
302 | env->NF = val; | |
9ee6e8bb PB |
303 | env->CF = (val >> 29) & 1; |
304 | env->VF = (val << 3) & 0x80000000; | |
305 | } | |
306 | if (mask & CPSR_Q) | |
307 | env->QF = ((val & CPSR_Q) != 0); | |
308 | if (mask & (1 << 24)) | |
309 | env->thumb = ((val & (1 << 24)) != 0); | |
310 | if (mask & CPSR_IT_0_1) { | |
311 | env->condexec_bits &= ~3; | |
312 | env->condexec_bits |= (val >> 25) & 3; | |
313 | } | |
314 | if (mask & CPSR_IT_2_7) { | |
315 | env->condexec_bits &= 3; | |
316 | env->condexec_bits |= (val >> 8) & 0xfc; | |
317 | } | |
318 | if (mask & 0x1ff) { | |
319 | env->v7m.exception = val & 0x1ff; | |
320 | } | |
321 | } | |
322 | ||
01653295 PM |
323 | /* Return the current FPSCR value. */ |
324 | uint32_t vfp_get_fpscr(CPUARMState *env); | |
325 | void vfp_set_fpscr(CPUARMState *env, uint32_t val); | |
326 | ||
b5ff1b31 FB |
327 | enum arm_cpu_mode { |
328 | ARM_CPU_MODE_USR = 0x10, | |
329 | ARM_CPU_MODE_FIQ = 0x11, | |
330 | ARM_CPU_MODE_IRQ = 0x12, | |
331 | ARM_CPU_MODE_SVC = 0x13, | |
332 | ARM_CPU_MODE_ABT = 0x17, | |
333 | ARM_CPU_MODE_UND = 0x1b, | |
334 | ARM_CPU_MODE_SYS = 0x1f | |
335 | }; | |
336 | ||
40f137e1 PB |
337 | /* VFP system registers. */ |
338 | #define ARM_VFP_FPSID 0 | |
339 | #define ARM_VFP_FPSCR 1 | |
9ee6e8bb PB |
340 | #define ARM_VFP_MVFR1 6 |
341 | #define ARM_VFP_MVFR0 7 | |
40f137e1 PB |
342 | #define ARM_VFP_FPEXC 8 |
343 | #define ARM_VFP_FPINST 9 | |
344 | #define ARM_VFP_FPINST2 10 | |
345 | ||
18c9b560 AZ |
346 | /* iwMMXt coprocessor control registers. */ |
347 | #define ARM_IWMMXT_wCID 0 | |
348 | #define ARM_IWMMXT_wCon 1 | |
349 | #define ARM_IWMMXT_wCSSF 2 | |
350 | #define ARM_IWMMXT_wCASF 3 | |
351 | #define ARM_IWMMXT_wCGR0 8 | |
352 | #define ARM_IWMMXT_wCGR1 9 | |
353 | #define ARM_IWMMXT_wCGR2 10 | |
354 | #define ARM_IWMMXT_wCGR3 11 | |
355 | ||
ce854d7c BC |
356 | /* If adding a feature bit which corresponds to a Linux ELF |
357 | * HWCAP bit, remember to update the feature-bit-to-hwcap | |
358 | * mapping in linux-user/elfload.c:get_elf_hwcap(). | |
359 | */ | |
40f137e1 PB |
360 | enum arm_features { |
361 | ARM_FEATURE_VFP, | |
c1713132 AZ |
362 | ARM_FEATURE_AUXCR, /* ARM1026 Auxiliary control register. */ |
363 | ARM_FEATURE_XSCALE, /* Intel XScale extensions. */ | |
ce819861 | 364 | ARM_FEATURE_IWMMXT, /* Intel iwMMXt extension. */ |
9ee6e8bb PB |
365 | ARM_FEATURE_V6, |
366 | ARM_FEATURE_V6K, | |
367 | ARM_FEATURE_V7, | |
368 | ARM_FEATURE_THUMB2, | |
c3d2689d | 369 | ARM_FEATURE_MPU, /* Only has Memory Protection Unit, not full MMU. */ |
9ee6e8bb | 370 | ARM_FEATURE_VFP3, |
60011498 | 371 | ARM_FEATURE_VFP_FP16, |
9ee6e8bb | 372 | ARM_FEATURE_NEON, |
47789990 | 373 | ARM_FEATURE_THUMB_DIV, /* divide supported in Thumb encoding */ |
9ee6e8bb | 374 | ARM_FEATURE_M, /* Microcontroller profile. */ |
fe1479c3 | 375 | ARM_FEATURE_OMAPCP, /* OMAP specific CP15 ops handling. */ |
e1bbf446 | 376 | ARM_FEATURE_THUMB2EE, |
be5e7a76 DES |
377 | ARM_FEATURE_V7MP, /* v7 Multiprocessing Extensions */ |
378 | ARM_FEATURE_V4T, | |
379 | ARM_FEATURE_V5, | |
5bc95aa2 | 380 | ARM_FEATURE_STRONGARM, |
906879a9 | 381 | ARM_FEATURE_VAPA, /* cp15 VA to PA lookups */ |
b8b8ea05 | 382 | ARM_FEATURE_ARM_DIV, /* divide supported in ARM encoding */ |
da97f52c | 383 | ARM_FEATURE_VFP4, /* VFPv4 (implies that NEON is v2) */ |
0383ac00 | 384 | ARM_FEATURE_GENERIC_TIMER, |
06ed5d66 | 385 | ARM_FEATURE_MVFR, /* Media and VFP Feature Registers 0 and 1 */ |
1047b9d7 | 386 | ARM_FEATURE_DUMMY_C15_REGS, /* RAZ/WI all of cp15 crn=15 */ |
c4804214 PM |
387 | ARM_FEATURE_CACHE_TEST_CLEAN, /* 926/1026 style test-and-clean ops */ |
388 | ARM_FEATURE_CACHE_DIRTY_REG, /* 1136/1176 cache dirty status register */ | |
389 | ARM_FEATURE_CACHE_BLOCK_OPS, /* v6 optional cache block operations */ | |
81bdde9d | 390 | ARM_FEATURE_MPIDR, /* has cp15 MPIDR */ |
de9b05b8 PM |
391 | ARM_FEATURE_PXN, /* has Privileged Execute Never bit */ |
392 | ARM_FEATURE_LPAE, /* has Large Physical Address Extension */ | |
81e69fb0 | 393 | ARM_FEATURE_V8, |
40f137e1 PB |
394 | }; |
395 | ||
396 | static inline int arm_feature(CPUARMState *env, int feature) | |
397 | { | |
918f5dca | 398 | return (env->features & (1ULL << feature)) != 0; |
40f137e1 PB |
399 | } |
400 | ||
9a78eead | 401 | void arm_cpu_list(FILE *f, fprintf_function cpu_fprintf); |
40f137e1 | 402 | |
9ee6e8bb PB |
403 | /* Interface between CPU and Interrupt controller. */ |
404 | void armv7m_nvic_set_pending(void *opaque, int irq); | |
405 | int armv7m_nvic_acknowledge_irq(void *opaque); | |
406 | void armv7m_nvic_complete_irq(void *opaque, int irq); | |
407 | ||
4b6a83fb PM |
408 | /* Interface for defining coprocessor registers. |
409 | * Registers are defined in tables of arm_cp_reginfo structs | |
410 | * which are passed to define_arm_cp_regs(). | |
411 | */ | |
412 | ||
413 | /* When looking up a coprocessor register we look for it | |
414 | * via an integer which encodes all of: | |
415 | * coprocessor number | |
416 | * Crn, Crm, opc1, opc2 fields | |
417 | * 32 or 64 bit register (ie is it accessed via MRC/MCR | |
418 | * or via MRRC/MCRR?) | |
419 | * We allow 4 bits for opc1 because MRRC/MCRR have a 4 bit field. | |
420 | * (In this case crn and opc2 should be zero.) | |
421 | */ | |
422 | #define ENCODE_CP_REG(cp, is64, crn, crm, opc1, opc2) \ | |
423 | (((cp) << 16) | ((is64) << 15) | ((crn) << 11) | \ | |
424 | ((crm) << 7) | ((opc1) << 3) | (opc2)) | |
425 | ||
721fae12 PM |
426 | /* Note that these must line up with the KVM/ARM register |
427 | * ID field definitions (kvm.c will check this, but we | |
428 | * can't just use the KVM defines here as the kvm headers | |
429 | * are unavailable to non-KVM-specific files) | |
430 | */ | |
431 | #define CP_REG_SIZE_SHIFT 52 | |
432 | #define CP_REG_SIZE_MASK 0x00f0000000000000ULL | |
433 | #define CP_REG_SIZE_U32 0x0020000000000000ULL | |
434 | #define CP_REG_SIZE_U64 0x0030000000000000ULL | |
435 | #define CP_REG_ARM 0x4000000000000000ULL | |
436 | ||
437 | /* Convert a full 64 bit KVM register ID to the truncated 32 bit | |
438 | * version used as a key for the coprocessor register hashtable | |
439 | */ | |
440 | static inline uint32_t kvm_to_cpreg_id(uint64_t kvmid) | |
441 | { | |
442 | uint32_t cpregid = kvmid; | |
443 | if ((kvmid & CP_REG_SIZE_MASK) == CP_REG_SIZE_U64) { | |
444 | cpregid |= (1 << 15); | |
445 | } | |
446 | return cpregid; | |
447 | } | |
448 | ||
449 | /* Convert a truncated 32 bit hashtable key into the full | |
450 | * 64 bit KVM register ID. | |
451 | */ | |
452 | static inline uint64_t cpreg_to_kvm_id(uint32_t cpregid) | |
453 | { | |
454 | uint64_t kvmid = cpregid & ~(1 << 15); | |
455 | if (cpregid & (1 << 15)) { | |
456 | kvmid |= CP_REG_SIZE_U64 | CP_REG_ARM; | |
457 | } else { | |
458 | kvmid |= CP_REG_SIZE_U32 | CP_REG_ARM; | |
459 | } | |
460 | return kvmid; | |
461 | } | |
462 | ||
4b6a83fb PM |
463 | /* ARMCPRegInfo type field bits. If the SPECIAL bit is set this is a |
464 | * special-behaviour cp reg and bits [15..8] indicate what behaviour | |
465 | * it has. Otherwise it is a simple cp reg, where CONST indicates that | |
466 | * TCG can assume the value to be constant (ie load at translate time) | |
467 | * and 64BIT indicates a 64 bit wide coprocessor register. SUPPRESS_TB_END | |
468 | * indicates that the TB should not be ended after a write to this register | |
469 | * (the default is that the TB ends after cp writes). OVERRIDE permits | |
470 | * a register definition to override a previous definition for the | |
471 | * same (cp, is64, crn, crm, opc1, opc2) tuple: either the new or the | |
472 | * old must have the OVERRIDE bit set. | |
7023ec7e PM |
473 | * NO_MIGRATE indicates that this register should be ignored for migration; |
474 | * (eg because any state is accessed via some other coprocessor register). | |
2452731c PM |
475 | * IO indicates that this register does I/O and therefore its accesses |
476 | * need to be surrounded by gen_io_start()/gen_io_end(). In particular, | |
477 | * registers which implement clocks or timers require this. | |
4b6a83fb PM |
478 | */ |
479 | #define ARM_CP_SPECIAL 1 | |
480 | #define ARM_CP_CONST 2 | |
481 | #define ARM_CP_64BIT 4 | |
482 | #define ARM_CP_SUPPRESS_TB_END 8 | |
483 | #define ARM_CP_OVERRIDE 16 | |
7023ec7e | 484 | #define ARM_CP_NO_MIGRATE 32 |
2452731c | 485 | #define ARM_CP_IO 64 |
4b6a83fb PM |
486 | #define ARM_CP_NOP (ARM_CP_SPECIAL | (1 << 8)) |
487 | #define ARM_CP_WFI (ARM_CP_SPECIAL | (2 << 8)) | |
488 | #define ARM_LAST_SPECIAL ARM_CP_WFI | |
489 | /* Used only as a terminator for ARMCPRegInfo lists */ | |
490 | #define ARM_CP_SENTINEL 0xffff | |
491 | /* Mask of only the flag bits in a type field */ | |
2452731c | 492 | #define ARM_CP_FLAG_MASK 0x7f |
4b6a83fb PM |
493 | |
494 | /* Return true if cptype is a valid type field. This is used to try to | |
495 | * catch errors where the sentinel has been accidentally left off the end | |
496 | * of a list of registers. | |
497 | */ | |
498 | static inline bool cptype_valid(int cptype) | |
499 | { | |
500 | return ((cptype & ~ARM_CP_FLAG_MASK) == 0) | |
501 | || ((cptype & ARM_CP_SPECIAL) && | |
34affeef | 502 | ((cptype & ~ARM_CP_FLAG_MASK) <= ARM_LAST_SPECIAL)); |
4b6a83fb PM |
503 | } |
504 | ||
505 | /* Access rights: | |
506 | * We define bits for Read and Write access for what rev C of the v7-AR ARM ARM | |
507 | * defines as PL0 (user), PL1 (fiq/irq/svc/abt/und/sys, ie privileged), and | |
508 | * PL2 (hyp). The other level which has Read and Write bits is Secure PL1 | |
509 | * (ie any of the privileged modes in Secure state, or Monitor mode). | |
510 | * If a register is accessible in one privilege level it's always accessible | |
511 | * in higher privilege levels too. Since "Secure PL1" also follows this rule | |
512 | * (ie anything visible in PL2 is visible in S-PL1, some things are only | |
513 | * visible in S-PL1) but "Secure PL1" is a bit of a mouthful, we bend the | |
514 | * terminology a little and call this PL3. | |
515 | * | |
516 | * If access permissions for a register are more complex than can be | |
517 | * described with these bits, then use a laxer set of restrictions, and | |
518 | * do the more restrictive/complex check inside a helper function. | |
519 | */ | |
520 | #define PL3_R 0x80 | |
521 | #define PL3_W 0x40 | |
522 | #define PL2_R (0x20 | PL3_R) | |
523 | #define PL2_W (0x10 | PL3_W) | |
524 | #define PL1_R (0x08 | PL2_R) | |
525 | #define PL1_W (0x04 | PL2_W) | |
526 | #define PL0_R (0x02 | PL1_R) | |
527 | #define PL0_W (0x01 | PL1_W) | |
528 | ||
529 | #define PL3_RW (PL3_R | PL3_W) | |
530 | #define PL2_RW (PL2_R | PL2_W) | |
531 | #define PL1_RW (PL1_R | PL1_W) | |
532 | #define PL0_RW (PL0_R | PL0_W) | |
533 | ||
534 | static inline int arm_current_pl(CPUARMState *env) | |
535 | { | |
536 | if ((env->uncached_cpsr & 0x1f) == ARM_CPU_MODE_USR) { | |
537 | return 0; | |
538 | } | |
539 | /* We don't currently implement the Virtualization or TrustZone | |
540 | * extensions, so PL2 and PL3 don't exist for us. | |
541 | */ | |
542 | return 1; | |
543 | } | |
544 | ||
545 | typedef struct ARMCPRegInfo ARMCPRegInfo; | |
546 | ||
547 | /* Access functions for coprocessor registers. These should return | |
548 | * 0 on success, or one of the EXCP_* constants if access should cause | |
549 | * an exception (in which case *value is not written). | |
550 | */ | |
551 | typedef int CPReadFn(CPUARMState *env, const ARMCPRegInfo *opaque, | |
552 | uint64_t *value); | |
553 | typedef int CPWriteFn(CPUARMState *env, const ARMCPRegInfo *opaque, | |
554 | uint64_t value); | |
555 | /* Hook function for register reset */ | |
556 | typedef void CPResetFn(CPUARMState *env, const ARMCPRegInfo *opaque); | |
557 | ||
558 | #define CP_ANY 0xff | |
559 | ||
560 | /* Definition of an ARM coprocessor register */ | |
561 | struct ARMCPRegInfo { | |
562 | /* Name of register (useful mainly for debugging, need not be unique) */ | |
563 | const char *name; | |
564 | /* Location of register: coprocessor number and (crn,crm,opc1,opc2) | |
565 | * tuple. Any of crm, opc1 and opc2 may be CP_ANY to indicate a | |
566 | * 'wildcard' field -- any value of that field in the MRC/MCR insn | |
567 | * will be decoded to this register. The register read and write | |
568 | * callbacks will be passed an ARMCPRegInfo with the crn/crm/opc1/opc2 | |
569 | * used by the program, so it is possible to register a wildcard and | |
570 | * then behave differently on read/write if necessary. | |
571 | * For 64 bit registers, only crm and opc1 are relevant; crn and opc2 | |
572 | * must both be zero. | |
573 | */ | |
574 | uint8_t cp; | |
575 | uint8_t crn; | |
576 | uint8_t crm; | |
577 | uint8_t opc1; | |
578 | uint8_t opc2; | |
579 | /* Register type: ARM_CP_* bits/values */ | |
580 | int type; | |
581 | /* Access rights: PL*_[RW] */ | |
582 | int access; | |
583 | /* The opaque pointer passed to define_arm_cp_regs_with_opaque() when | |
584 | * this register was defined: can be used to hand data through to the | |
585 | * register read/write functions, since they are passed the ARMCPRegInfo*. | |
586 | */ | |
587 | void *opaque; | |
588 | /* Value of this register, if it is ARM_CP_CONST. Otherwise, if | |
589 | * fieldoffset is non-zero, the reset value of the register. | |
590 | */ | |
591 | uint64_t resetvalue; | |
592 | /* Offset of the field in CPUARMState for this register. This is not | |
593 | * needed if either: | |
594 | * 1. type is ARM_CP_CONST or one of the ARM_CP_SPECIALs | |
595 | * 2. both readfn and writefn are specified | |
596 | */ | |
597 | ptrdiff_t fieldoffset; /* offsetof(CPUARMState, field) */ | |
598 | /* Function for handling reads of this register. If NULL, then reads | |
599 | * will be done by loading from the offset into CPUARMState specified | |
600 | * by fieldoffset. | |
601 | */ | |
602 | CPReadFn *readfn; | |
603 | /* Function for handling writes of this register. If NULL, then writes | |
604 | * will be done by writing to the offset into CPUARMState specified | |
605 | * by fieldoffset. | |
606 | */ | |
607 | CPWriteFn *writefn; | |
7023ec7e PM |
608 | /* Function for doing a "raw" read; used when we need to copy |
609 | * coprocessor state to the kernel for KVM or out for | |
610 | * migration. This only needs to be provided if there is also a | |
611 | * readfn and it makes an access permission check. | |
612 | */ | |
613 | CPReadFn *raw_readfn; | |
614 | /* Function for doing a "raw" write; used when we need to copy KVM | |
615 | * kernel coprocessor state into userspace, or for inbound | |
616 | * migration. This only needs to be provided if there is also a | |
617 | * writefn and it makes an access permission check or masks out | |
618 | * "unwritable" bits or has write-one-to-clear or similar behaviour. | |
619 | */ | |
620 | CPWriteFn *raw_writefn; | |
4b6a83fb PM |
621 | /* Function for resetting the register. If NULL, then reset will be done |
622 | * by writing resetvalue to the field specified in fieldoffset. If | |
623 | * fieldoffset is 0 then no reset will be done. | |
624 | */ | |
625 | CPResetFn *resetfn; | |
626 | }; | |
627 | ||
628 | /* Macros which are lvalues for the field in CPUARMState for the | |
629 | * ARMCPRegInfo *ri. | |
630 | */ | |
631 | #define CPREG_FIELD32(env, ri) \ | |
632 | (*(uint32_t *)((char *)(env) + (ri)->fieldoffset)) | |
633 | #define CPREG_FIELD64(env, ri) \ | |
634 | (*(uint64_t *)((char *)(env) + (ri)->fieldoffset)) | |
635 | ||
636 | #define REGINFO_SENTINEL { .type = ARM_CP_SENTINEL } | |
637 | ||
638 | void define_arm_cp_regs_with_opaque(ARMCPU *cpu, | |
639 | const ARMCPRegInfo *regs, void *opaque); | |
640 | void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu, | |
641 | const ARMCPRegInfo *regs, void *opaque); | |
642 | static inline void define_arm_cp_regs(ARMCPU *cpu, const ARMCPRegInfo *regs) | |
643 | { | |
644 | define_arm_cp_regs_with_opaque(cpu, regs, 0); | |
645 | } | |
646 | static inline void define_one_arm_cp_reg(ARMCPU *cpu, const ARMCPRegInfo *regs) | |
647 | { | |
648 | define_one_arm_cp_reg_with_opaque(cpu, regs, 0); | |
649 | } | |
650 | const ARMCPRegInfo *get_arm_cp_reginfo(ARMCPU *cpu, uint32_t encoded_cp); | |
651 | ||
652 | /* CPWriteFn that can be used to implement writes-ignored behaviour */ | |
653 | int arm_cp_write_ignore(CPUARMState *env, const ARMCPRegInfo *ri, | |
654 | uint64_t value); | |
655 | /* CPReadFn that can be used for read-as-zero behaviour */ | |
656 | int arm_cp_read_zero(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t *value); | |
657 | ||
658 | static inline bool cp_access_ok(CPUARMState *env, | |
659 | const ARMCPRegInfo *ri, int isread) | |
660 | { | |
661 | return (ri->access >> ((arm_current_pl(env) * 2) + isread)) & 1; | |
662 | } | |
663 | ||
721fae12 PM |
664 | /** |
665 | * write_list_to_cpustate | |
666 | * @cpu: ARMCPU | |
667 | * | |
668 | * For each register listed in the ARMCPU cpreg_indexes list, write | |
669 | * its value from the cpreg_values list into the ARMCPUState structure. | |
670 | * This updates TCG's working data structures from KVM data or | |
671 | * from incoming migration state. | |
672 | * | |
673 | * Returns: true if all register values were updated correctly, | |
674 | * false if some register was unknown or could not be written. | |
675 | * Note that we do not stop early on failure -- we will attempt | |
676 | * writing all registers in the list. | |
677 | */ | |
678 | bool write_list_to_cpustate(ARMCPU *cpu); | |
679 | ||
680 | /** | |
681 | * write_cpustate_to_list: | |
682 | * @cpu: ARMCPU | |
683 | * | |
684 | * For each register listed in the ARMCPU cpreg_indexes list, write | |
685 | * its value from the ARMCPUState structure into the cpreg_values list. | |
686 | * This is used to copy info from TCG's working data structures into | |
687 | * KVM or for outbound migration. | |
688 | * | |
689 | * Returns: true if all register values were read correctly, | |
690 | * false if some register was unknown or could not be read. | |
691 | * Note that we do not stop early on failure -- we will attempt | |
692 | * reading all registers in the list. | |
693 | */ | |
694 | bool write_cpustate_to_list(ARMCPU *cpu); | |
695 | ||
9ee6e8bb PB |
696 | /* Does the core conform to the the "MicroController" profile. e.g. Cortex-M3. |
697 | Note the M in older cores (eg. ARM7TDMI) stands for Multiply. These are | |
698 | conventional cores (ie. Application or Realtime profile). */ | |
699 | ||
700 | #define IS_M(env) arm_feature(env, ARM_FEATURE_M) | |
9ee6e8bb | 701 | |
9ee6e8bb PB |
702 | #define ARM_CPUID_TI915T 0x54029152 |
703 | #define ARM_CPUID_TI925T 0x54029252 | |
40f137e1 | 704 | |
b5ff1b31 | 705 | #if defined(CONFIG_USER_ONLY) |
2c0262af | 706 | #define TARGET_PAGE_BITS 12 |
b5ff1b31 FB |
707 | #else |
708 | /* The ARM MMU allows 1k pages. */ | |
709 | /* ??? Linux doesn't actually use these, and they're deprecated in recent | |
82d17978 | 710 | architecture revisions. Maybe a configure option to disable them. */ |
b5ff1b31 FB |
711 | #define TARGET_PAGE_BITS 10 |
712 | #endif | |
9467d44c | 713 | |
3cc0cd61 | 714 | #define TARGET_PHYS_ADDR_SPACE_BITS 40 |
52705890 RH |
715 | #define TARGET_VIRT_ADDR_SPACE_BITS 32 |
716 | ||
ad37ad5b PM |
717 | static inline CPUARMState *cpu_init(const char *cpu_model) |
718 | { | |
719 | ARMCPU *cpu = cpu_arm_init(cpu_model); | |
720 | if (cpu) { | |
721 | return &cpu->env; | |
722 | } | |
723 | return NULL; | |
724 | } | |
725 | ||
9467d44c TS |
726 | #define cpu_exec cpu_arm_exec |
727 | #define cpu_gen_code cpu_arm_gen_code | |
728 | #define cpu_signal_handler cpu_arm_signal_handler | |
c732abe2 | 729 | #define cpu_list arm_cpu_list |
9467d44c | 730 | |
6ebbf390 JM |
731 | /* MMU modes definitions */ |
732 | #define MMU_MODE0_SUFFIX _kernel | |
733 | #define MMU_MODE1_SUFFIX _user | |
734 | #define MMU_USER_IDX 1 | |
0ecb72a5 | 735 | static inline int cpu_mmu_index (CPUARMState *env) |
6ebbf390 JM |
736 | { |
737 | return (env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_USR ? 1 : 0; | |
738 | } | |
739 | ||
022c62cb | 740 | #include "exec/cpu-all.h" |
622ed360 | 741 | |
a1705768 PM |
742 | /* Bit usage in the TB flags field: */ |
743 | #define ARM_TBFLAG_THUMB_SHIFT 0 | |
744 | #define ARM_TBFLAG_THUMB_MASK (1 << ARM_TBFLAG_THUMB_SHIFT) | |
745 | #define ARM_TBFLAG_VECLEN_SHIFT 1 | |
746 | #define ARM_TBFLAG_VECLEN_MASK (0x7 << ARM_TBFLAG_VECLEN_SHIFT) | |
747 | #define ARM_TBFLAG_VECSTRIDE_SHIFT 4 | |
748 | #define ARM_TBFLAG_VECSTRIDE_MASK (0x3 << ARM_TBFLAG_VECSTRIDE_SHIFT) | |
749 | #define ARM_TBFLAG_PRIV_SHIFT 6 | |
750 | #define ARM_TBFLAG_PRIV_MASK (1 << ARM_TBFLAG_PRIV_SHIFT) | |
751 | #define ARM_TBFLAG_VFPEN_SHIFT 7 | |
752 | #define ARM_TBFLAG_VFPEN_MASK (1 << ARM_TBFLAG_VFPEN_SHIFT) | |
753 | #define ARM_TBFLAG_CONDEXEC_SHIFT 8 | |
754 | #define ARM_TBFLAG_CONDEXEC_MASK (0xff << ARM_TBFLAG_CONDEXEC_SHIFT) | |
d8fd2954 PB |
755 | #define ARM_TBFLAG_BSWAP_CODE_SHIFT 16 |
756 | #define ARM_TBFLAG_BSWAP_CODE_MASK (1 << ARM_TBFLAG_BSWAP_CODE_SHIFT) | |
757 | /* Bits 31..17 are currently unused. */ | |
a1705768 PM |
758 | |
759 | /* some convenience accessor macros */ | |
760 | #define ARM_TBFLAG_THUMB(F) \ | |
761 | (((F) & ARM_TBFLAG_THUMB_MASK) >> ARM_TBFLAG_THUMB_SHIFT) | |
762 | #define ARM_TBFLAG_VECLEN(F) \ | |
763 | (((F) & ARM_TBFLAG_VECLEN_MASK) >> ARM_TBFLAG_VECLEN_SHIFT) | |
764 | #define ARM_TBFLAG_VECSTRIDE(F) \ | |
765 | (((F) & ARM_TBFLAG_VECSTRIDE_MASK) >> ARM_TBFLAG_VECSTRIDE_SHIFT) | |
766 | #define ARM_TBFLAG_PRIV(F) \ | |
767 | (((F) & ARM_TBFLAG_PRIV_MASK) >> ARM_TBFLAG_PRIV_SHIFT) | |
768 | #define ARM_TBFLAG_VFPEN(F) \ | |
769 | (((F) & ARM_TBFLAG_VFPEN_MASK) >> ARM_TBFLAG_VFPEN_SHIFT) | |
770 | #define ARM_TBFLAG_CONDEXEC(F) \ | |
771 | (((F) & ARM_TBFLAG_CONDEXEC_MASK) >> ARM_TBFLAG_CONDEXEC_SHIFT) | |
d8fd2954 PB |
772 | #define ARM_TBFLAG_BSWAP_CODE(F) \ |
773 | (((F) & ARM_TBFLAG_BSWAP_CODE_MASK) >> ARM_TBFLAG_BSWAP_CODE_SHIFT) | |
a1705768 | 774 | |
0ecb72a5 | 775 | static inline void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, |
6b917547 AL |
776 | target_ulong *cs_base, int *flags) |
777 | { | |
05ed9a99 | 778 | int privmode; |
6b917547 AL |
779 | *pc = env->regs[15]; |
780 | *cs_base = 0; | |
a1705768 PM |
781 | *flags = (env->thumb << ARM_TBFLAG_THUMB_SHIFT) |
782 | | (env->vfp.vec_len << ARM_TBFLAG_VECLEN_SHIFT) | |
783 | | (env->vfp.vec_stride << ARM_TBFLAG_VECSTRIDE_SHIFT) | |
d8fd2954 PB |
784 | | (env->condexec_bits << ARM_TBFLAG_CONDEXEC_SHIFT) |
785 | | (env->bswap_code << ARM_TBFLAG_BSWAP_CODE_SHIFT); | |
05ed9a99 PM |
786 | if (arm_feature(env, ARM_FEATURE_M)) { |
787 | privmode = !((env->v7m.exception == 0) && (env->v7m.control & 1)); | |
788 | } else { | |
789 | privmode = (env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR; | |
790 | } | |
791 | if (privmode) { | |
a1705768 PM |
792 | *flags |= ARM_TBFLAG_PRIV_MASK; |
793 | } | |
794 | if (env->vfp.xregs[ARM_VFP_FPEXC] & (1 << 30)) { | |
795 | *flags |= ARM_TBFLAG_VFPEN_MASK; | |
796 | } | |
6b917547 AL |
797 | } |
798 | ||
3993c6bd | 799 | static inline bool cpu_has_work(CPUState *cpu) |
f081c76c | 800 | { |
259186a7 | 801 | return cpu->interrupt_request & |
f081c76c BS |
802 | (CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD | CPU_INTERRUPT_EXITTB); |
803 | } | |
804 | ||
022c62cb | 805 | #include "exec/exec-all.h" |
f081c76c | 806 | |
d8fd2954 | 807 | /* Load an instruction and return it in the standard little-endian order */ |
d31dd73e BS |
808 | static inline uint32_t arm_ldl_code(CPUARMState *env, uint32_t addr, |
809 | bool do_swap) | |
d8fd2954 | 810 | { |
d31dd73e | 811 | uint32_t insn = cpu_ldl_code(env, addr); |
d8fd2954 PB |
812 | if (do_swap) { |
813 | return bswap32(insn); | |
814 | } | |
815 | return insn; | |
816 | } | |
817 | ||
818 | /* Ditto, for a halfword (Thumb) instruction */ | |
d31dd73e BS |
819 | static inline uint16_t arm_lduw_code(CPUARMState *env, uint32_t addr, |
820 | bool do_swap) | |
d8fd2954 | 821 | { |
d31dd73e | 822 | uint16_t insn = cpu_lduw_code(env, addr); |
d8fd2954 PB |
823 | if (do_swap) { |
824 | return bswap16(insn); | |
825 | } | |
826 | return insn; | |
827 | } | |
828 | ||
2c0262af | 829 | #endif |