]>
Commit | Line | Data |
---|---|---|
2c0262af FB |
1 | /* |
2 | * ARM virtual CPU header | |
5fafdf24 | 3 | * |
2c0262af FB |
4 | * Copyright (c) 2003 Fabrice Bellard |
5 | * | |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
9 | * version 2 of the License, or (at your option) any later version. | |
10 | * | |
11 | * This library is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU Lesser General Public | |
8167ee88 | 17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. |
2c0262af FB |
18 | */ |
19 | #ifndef CPU_ARM_H | |
20 | #define CPU_ARM_H | |
21 | ||
3926cc84 | 22 | #include "config.h" |
3cf1e035 | 23 | |
72b0cd35 PM |
24 | #include "kvm-consts.h" |
25 | ||
3926cc84 AG |
26 | #if defined(TARGET_AARCH64) |
27 | /* AArch64 definitions */ | |
28 | # define TARGET_LONG_BITS 64 | |
29 | # define ELF_MACHINE EM_AARCH64 | |
30 | #else | |
31 | # define TARGET_LONG_BITS 32 | |
32 | # define ELF_MACHINE EM_ARM | |
33 | #endif | |
9042c0e2 | 34 | |
9349b4f9 | 35 | #define CPUArchState struct CPUARMState |
c2764719 | 36 | |
9a78eead | 37 | #include "qemu-common.h" |
022c62cb | 38 | #include "exec/cpu-defs.h" |
2c0262af | 39 | |
6b4c305c | 40 | #include "fpu/softfloat.h" |
53cd6637 | 41 | |
1fddef4b FB |
42 | #define TARGET_HAS_ICE 1 |
43 | ||
b8a9e8f1 FB |
44 | #define EXCP_UDEF 1 /* undefined instruction */ |
45 | #define EXCP_SWI 2 /* software interrupt */ | |
46 | #define EXCP_PREFETCH_ABORT 3 | |
47 | #define EXCP_DATA_ABORT 4 | |
b5ff1b31 FB |
48 | #define EXCP_IRQ 5 |
49 | #define EXCP_FIQ 6 | |
06c949e6 | 50 | #define EXCP_BKPT 7 |
9ee6e8bb | 51 | #define EXCP_EXCEPTION_EXIT 8 /* Return from v7M exception. */ |
fbb4a2e3 | 52 | #define EXCP_KERNEL_TRAP 9 /* Jumped to kernel code page. */ |
426f5abc | 53 | #define EXCP_STREX 10 |
35979d71 | 54 | #define EXCP_HVC 11 /* HyperVisor Call */ |
607d98b8 | 55 | #define EXCP_HYP_TRAP 12 |
e0d6e6a5 | 56 | #define EXCP_SMC 13 /* Secure Monitor Call */ |
136e67e9 EI |
57 | #define EXCP_VIRQ 14 |
58 | #define EXCP_VFIQ 15 | |
9ee6e8bb PB |
59 | |
60 | #define ARMV7M_EXCP_RESET 1 | |
61 | #define ARMV7M_EXCP_NMI 2 | |
62 | #define ARMV7M_EXCP_HARD 3 | |
63 | #define ARMV7M_EXCP_MEM 4 | |
64 | #define ARMV7M_EXCP_BUS 5 | |
65 | #define ARMV7M_EXCP_USAGE 6 | |
66 | #define ARMV7M_EXCP_SVC 11 | |
67 | #define ARMV7M_EXCP_DEBUG 12 | |
68 | #define ARMV7M_EXCP_PENDSV 14 | |
69 | #define ARMV7M_EXCP_SYSTICK 15 | |
2c0262af | 70 | |
403946c0 RH |
71 | /* ARM-specific interrupt pending bits. */ |
72 | #define CPU_INTERRUPT_FIQ CPU_INTERRUPT_TGT_EXT_1 | |
136e67e9 EI |
73 | #define CPU_INTERRUPT_VIRQ CPU_INTERRUPT_TGT_EXT_2 |
74 | #define CPU_INTERRUPT_VFIQ CPU_INTERRUPT_TGT_EXT_3 | |
403946c0 | 75 | |
e4fe830b PM |
76 | /* The usual mapping for an AArch64 system register to its AArch32 |
77 | * counterpart is for the 32 bit world to have access to the lower | |
78 | * half only (with writes leaving the upper half untouched). It's | |
79 | * therefore useful to be able to pass TCG the offset of the least | |
80 | * significant half of a uint64_t struct member. | |
81 | */ | |
82 | #ifdef HOST_WORDS_BIGENDIAN | |
5cd8a118 | 83 | #define offsetoflow32(S, M) (offsetof(S, M) + sizeof(uint32_t)) |
b0fe2427 | 84 | #define offsetofhigh32(S, M) offsetof(S, M) |
e4fe830b PM |
85 | #else |
86 | #define offsetoflow32(S, M) offsetof(S, M) | |
b0fe2427 | 87 | #define offsetofhigh32(S, M) (offsetof(S, M) + sizeof(uint32_t)) |
e4fe830b PM |
88 | #endif |
89 | ||
136e67e9 | 90 | /* Meanings of the ARMCPU object's four inbound GPIO lines */ |
7c1840b6 PM |
91 | #define ARM_CPU_IRQ 0 |
92 | #define ARM_CPU_FIQ 1 | |
136e67e9 EI |
93 | #define ARM_CPU_VIRQ 2 |
94 | #define ARM_CPU_VFIQ 3 | |
403946c0 | 95 | |
c1713132 AZ |
96 | typedef void ARMWriteCPFunc(void *opaque, int cp_info, |
97 | int srcreg, int operand, uint32_t value); | |
98 | typedef uint32_t ARMReadCPFunc(void *opaque, int cp_info, | |
99 | int dstreg, int operand); | |
100 | ||
f93eb9ff AZ |
101 | struct arm_boot_info; |
102 | ||
592125f8 | 103 | #define NB_MMU_MODES 4 |
6ebbf390 | 104 | |
b7bcbe95 FB |
105 | /* We currently assume float and double are IEEE single and double |
106 | precision respectively. | |
107 | Doing runtime conversions is tricky because VFP registers may contain | |
108 | integer values (eg. as the result of a FTOSI instruction). | |
8e96005d FB |
109 | s<2n> maps to the least significant half of d<n> |
110 | s<2n+1> maps to the most significant half of d<n> | |
111 | */ | |
b7bcbe95 | 112 | |
55d284af PM |
113 | /* CPU state for each instance of a generic timer (in cp15 c14) */ |
114 | typedef struct ARMGenericTimer { | |
115 | uint64_t cval; /* Timer CompareValue register */ | |
a7adc4b7 | 116 | uint64_t ctl; /* Timer Control register */ |
55d284af PM |
117 | } ARMGenericTimer; |
118 | ||
119 | #define GTIMER_PHYS 0 | |
120 | #define GTIMER_VIRT 1 | |
121 | #define NUM_GTIMERS 2 | |
122 | ||
2c0262af | 123 | typedef struct CPUARMState { |
b5ff1b31 | 124 | /* Regs for current mode. */ |
2c0262af | 125 | uint32_t regs[16]; |
3926cc84 AG |
126 | |
127 | /* 32/64 switch only happens when taking and returning from | |
128 | * exceptions so the overlap semantics are taken care of then | |
129 | * instead of having a complicated union. | |
130 | */ | |
131 | /* Regs for A64 mode. */ | |
132 | uint64_t xregs[32]; | |
133 | uint64_t pc; | |
d356312f PM |
134 | /* PSTATE isn't an architectural register for ARMv8. However, it is |
135 | * convenient for us to assemble the underlying state into a 32 bit format | |
136 | * identical to the architectural format used for the SPSR. (This is also | |
137 | * what the Linux kernel's 'pstate' field in signal handlers and KVM's | |
138 | * 'pstate' register are.) Of the PSTATE bits: | |
139 | * NZCV are kept in the split out env->CF/VF/NF/ZF, (which have the same | |
140 | * semantics as for AArch32, as described in the comments on each field) | |
141 | * nRW (also known as M[4]) is kept, inverted, in env->aarch64 | |
4cc35614 | 142 | * DAIF (exception masks) are kept in env->daif |
d356312f | 143 | * all other bits are stored in their correct places in env->pstate |
3926cc84 AG |
144 | */ |
145 | uint32_t pstate; | |
146 | uint32_t aarch64; /* 1 if CPU is in aarch64 state; inverse of PSTATE.nRW */ | |
147 | ||
b90372ad | 148 | /* Frequently accessed CPSR bits are stored separately for efficiency. |
d37aca66 | 149 | This contains all the other bits. Use cpsr_{read,write} to access |
b5ff1b31 FB |
150 | the whole CPSR. */ |
151 | uint32_t uncached_cpsr; | |
152 | uint32_t spsr; | |
153 | ||
154 | /* Banked registers. */ | |
28c9457d | 155 | uint64_t banked_spsr[8]; |
0b7d409d FA |
156 | uint32_t banked_r13[8]; |
157 | uint32_t banked_r14[8]; | |
3b46e624 | 158 | |
b5ff1b31 FB |
159 | /* These hold r8-r12. */ |
160 | uint32_t usr_regs[5]; | |
161 | uint32_t fiq_regs[5]; | |
3b46e624 | 162 | |
2c0262af FB |
163 | /* cpsr flag cache for faster execution */ |
164 | uint32_t CF; /* 0 or 1 */ | |
165 | uint32_t VF; /* V is the bit 31. All other bits are undefined */ | |
6fbe23d5 PB |
166 | uint32_t NF; /* N is bit 31. All other bits are undefined. */ |
167 | uint32_t ZF; /* Z set if zero. */ | |
99c475ab | 168 | uint32_t QF; /* 0 or 1 */ |
9ee6e8bb | 169 | uint32_t GE; /* cpsr[19:16] */ |
b26eefb6 | 170 | uint32_t thumb; /* cpsr[5]. 0 = arm mode, 1 = thumb mode. */ |
9ee6e8bb | 171 | uint32_t condexec_bits; /* IT bits. cpsr[15:10,26:25]. */ |
c2b820fe | 172 | uint64_t daif; /* exception masks, in the bits they are in in PSTATE */ |
2c0262af | 173 | |
1b174238 | 174 | uint64_t elr_el[4]; /* AArch64 exception link regs */ |
73fb3b76 | 175 | uint64_t sp_el[4]; /* AArch64 banked stack pointers */ |
a0618a19 | 176 | |
b5ff1b31 FB |
177 | /* System control coprocessor (cp15) */ |
178 | struct { | |
40f137e1 | 179 | uint32_t c0_cpuid; |
b85a1fd6 FA |
180 | union { /* Cache size selection */ |
181 | struct { | |
182 | uint64_t _unused_csselr0; | |
183 | uint64_t csselr_ns; | |
184 | uint64_t _unused_csselr1; | |
185 | uint64_t csselr_s; | |
186 | }; | |
187 | uint64_t csselr_el[4]; | |
188 | }; | |
137feaa9 FA |
189 | union { /* System control register. */ |
190 | struct { | |
191 | uint64_t _unused_sctlr; | |
192 | uint64_t sctlr_ns; | |
193 | uint64_t hsctlr; | |
194 | uint64_t sctlr_s; | |
195 | }; | |
196 | uint64_t sctlr_el[4]; | |
197 | }; | |
34222fb8 | 198 | uint64_t c1_coproc; /* Coprocessor access register. */ |
610c3c8a | 199 | uint32_t c1_xscaleauxcr; /* XScale auxiliary control register. */ |
144634ae | 200 | uint64_t sder; /* Secure debug enable register. */ |
77022576 | 201 | uint32_t nsacr; /* Non-secure access control register. */ |
7dd8c9af FA |
202 | union { /* MMU translation table base 0. */ |
203 | struct { | |
204 | uint64_t _unused_ttbr0_0; | |
205 | uint64_t ttbr0_ns; | |
206 | uint64_t _unused_ttbr0_1; | |
207 | uint64_t ttbr0_s; | |
208 | }; | |
209 | uint64_t ttbr0_el[4]; | |
210 | }; | |
211 | union { /* MMU translation table base 1. */ | |
212 | struct { | |
213 | uint64_t _unused_ttbr1_0; | |
214 | uint64_t ttbr1_ns; | |
215 | uint64_t _unused_ttbr1_1; | |
216 | uint64_t ttbr1_s; | |
217 | }; | |
218 | uint64_t ttbr1_el[4]; | |
219 | }; | |
cb2e37df | 220 | uint64_t c2_control; /* MMU translation table base control. */ |
b2fa1797 PB |
221 | uint32_t c2_mask; /* MMU translation table base selection mask. */ |
222 | uint32_t c2_base_mask; /* MMU translation table base 0 mask. */ | |
ce819861 PB |
223 | uint32_t c2_data; /* MPU data cachable bits. */ |
224 | uint32_t c2_insn; /* MPU instruction cachable bits. */ | |
225 | uint32_t c3; /* MMU domain access control register | |
226 | MPU write buffer control. */ | |
7e09797c PM |
227 | uint32_t pmsav5_data_ap; /* PMSAv5 MPU data access permissions */ |
228 | uint32_t pmsav5_insn_ap; /* PMSAv5 MPU insn access permissions */ | |
f149e3e8 | 229 | uint64_t hcr_el2; /* Hypervisor configuration register */ |
64e0e2de | 230 | uint64_t scr_el3; /* Secure configuration register. */ |
6cd8a264 | 231 | uint32_t ifsr_el2; /* Fault status registers. */ |
f2c30f42 | 232 | uint64_t esr_el[4]; |
ce819861 | 233 | uint32_t c6_region[8]; /* MPU base/size registers. */ |
63b60551 | 234 | uint64_t far_el[4]; /* Fault address registers. */ |
19525524 | 235 | uint64_t par_el1; /* Translation result. */ |
b5ff1b31 FB |
236 | uint32_t c9_insn; /* Cache lockdown registers. */ |
237 | uint32_t c9_data; | |
8521466b AF |
238 | uint64_t c9_pmcr; /* performance monitor control register */ |
239 | uint64_t c9_pmcnten; /* perf monitor counter enables */ | |
74594c9d PM |
240 | uint32_t c9_pmovsr; /* perf monitor overflow status */ |
241 | uint32_t c9_pmxevtyper; /* perf monitor event type */ | |
242 | uint32_t c9_pmuserenr; /* perf monitor user enable */ | |
243 | uint32_t c9_pminten; /* perf monitor interrupt enables */ | |
b0fe2427 | 244 | uint64_t mair_el1; |
a1ba125c | 245 | uint64_t vbar_el[4]; /* vector base address register */ |
e89e51a1 | 246 | uint32_t mvbar; /* (monitor) vector base address register */ |
b5ff1b31 | 247 | uint32_t c13_fcse; /* FCSE PID. */ |
014406b5 | 248 | uint64_t contextidr_el1; /* Context ID. */ |
e4fe830b PM |
249 | uint64_t tpidr_el0; /* User RW Thread register. */ |
250 | uint64_t tpidrro_el0; /* User RO Thread register. */ | |
251 | uint64_t tpidr_el1; /* Privileged Thread register. */ | |
a7adc4b7 PM |
252 | uint64_t c14_cntfrq; /* Counter Frequency register */ |
253 | uint64_t c14_cntkctl; /* Timer Control register */ | |
55d284af | 254 | ARMGenericTimer c14_timer[NUM_GTIMERS]; |
c1713132 | 255 | uint32_t c15_cpar; /* XScale Coprocessor Access Register */ |
c3d2689d AZ |
256 | uint32_t c15_ticonfig; /* TI925T configuration byte. */ |
257 | uint32_t c15_i_max; /* Maximum D-cache dirty line index. */ | |
258 | uint32_t c15_i_min; /* Minimum D-cache dirty line index. */ | |
259 | uint32_t c15_threadid; /* TI debugger thread-ID. */ | |
7da362d0 ML |
260 | uint32_t c15_config_base_address; /* SCU base address. */ |
261 | uint32_t c15_diagnostic; /* diagnostic register */ | |
262 | uint32_t c15_power_diagnostic; | |
263 | uint32_t c15_power_control; /* power control */ | |
0b45451e PM |
264 | uint64_t dbgbvr[16]; /* breakpoint value registers */ |
265 | uint64_t dbgbcr[16]; /* breakpoint control registers */ | |
266 | uint64_t dbgwvr[16]; /* watchpoint value registers */ | |
267 | uint64_t dbgwcr[16]; /* watchpoint control registers */ | |
3a298203 | 268 | uint64_t mdscr_el1; |
7c2cb42b AF |
269 | /* If the counter is enabled, this stores the last time the counter |
270 | * was reset. Otherwise it stores the counter value | |
271 | */ | |
c92c0687 | 272 | uint64_t c15_ccnt; |
8521466b | 273 | uint64_t pmccfiltr_el0; /* Performance Monitor Filter Register */ |
b5ff1b31 | 274 | } cp15; |
40f137e1 | 275 | |
9ee6e8bb PB |
276 | struct { |
277 | uint32_t other_sp; | |
278 | uint32_t vecbase; | |
279 | uint32_t basepri; | |
280 | uint32_t control; | |
281 | int current_sp; | |
282 | int exception; | |
283 | int pending_exception; | |
9ee6e8bb PB |
284 | } v7m; |
285 | ||
abf1172f PM |
286 | /* Information associated with an exception about to be taken: |
287 | * code which raises an exception must set cs->exception_index and | |
288 | * the relevant parts of this structure; the cpu_do_interrupt function | |
289 | * will then set the guest-visible registers as part of the exception | |
290 | * entry process. | |
291 | */ | |
292 | struct { | |
293 | uint32_t syndrome; /* AArch64 format syndrome register */ | |
294 | uint32_t fsr; /* AArch32 format fault status register info */ | |
295 | uint64_t vaddress; /* virtual addr associated with exception, if any */ | |
296 | /* If we implement EL2 we will also need to store information | |
297 | * about the intermediate physical address for stage 2 faults. | |
298 | */ | |
299 | } exception; | |
300 | ||
fe1479c3 PB |
301 | /* Thumb-2 EE state. */ |
302 | uint32_t teecr; | |
303 | uint32_t teehbr; | |
304 | ||
b7bcbe95 FB |
305 | /* VFP coprocessor state. */ |
306 | struct { | |
3926cc84 AG |
307 | /* VFP/Neon register state. Note that the mapping between S, D and Q |
308 | * views of the register bank differs between AArch64 and AArch32: | |
309 | * In AArch32: | |
310 | * Qn = regs[2n+1]:regs[2n] | |
311 | * Dn = regs[n] | |
312 | * Sn = regs[n/2] bits 31..0 for even n, and bits 63..32 for odd n | |
313 | * (and regs[32] to regs[63] are inaccessible) | |
314 | * In AArch64: | |
315 | * Qn = regs[2n+1]:regs[2n] | |
316 | * Dn = regs[2n] | |
317 | * Sn = regs[2n] bits 31..0 | |
318 | * This corresponds to the architecturally defined mapping between | |
319 | * the two execution states, and means we do not need to explicitly | |
320 | * map these registers when changing states. | |
321 | */ | |
322 | float64 regs[64]; | |
b7bcbe95 | 323 | |
40f137e1 | 324 | uint32_t xregs[16]; |
b7bcbe95 FB |
325 | /* We store these fpcsr fields separately for convenience. */ |
326 | int vec_len; | |
327 | int vec_stride; | |
328 | ||
9ee6e8bb PB |
329 | /* scratch space when Tn are not sufficient. */ |
330 | uint32_t scratch[8]; | |
3b46e624 | 331 | |
3a492f3a PM |
332 | /* fp_status is the "normal" fp status. standard_fp_status retains |
333 | * values corresponding to the ARM "Standard FPSCR Value", ie | |
334 | * default-NaN, flush-to-zero, round-to-nearest and is used by | |
335 | * any operations (generally Neon) which the architecture defines | |
336 | * as controlled by the standard FPSCR value rather than the FPSCR. | |
337 | * | |
338 | * To avoid having to transfer exception bits around, we simply | |
339 | * say that the FPSCR cumulative exception flags are the logical | |
340 | * OR of the flags in the two fp statuses. This relies on the | |
341 | * only thing which needs to read the exception flags being | |
342 | * an explicit FPSCR read. | |
343 | */ | |
53cd6637 | 344 | float_status fp_status; |
3a492f3a | 345 | float_status standard_fp_status; |
b7bcbe95 | 346 | } vfp; |
03d05e2d PM |
347 | uint64_t exclusive_addr; |
348 | uint64_t exclusive_val; | |
349 | uint64_t exclusive_high; | |
9ee6e8bb | 350 | #if defined(CONFIG_USER_ONLY) |
03d05e2d | 351 | uint64_t exclusive_test; |
426f5abc | 352 | uint32_t exclusive_info; |
9ee6e8bb | 353 | #endif |
b7bcbe95 | 354 | |
18c9b560 AZ |
355 | /* iwMMXt coprocessor state. */ |
356 | struct { | |
357 | uint64_t regs[16]; | |
358 | uint64_t val; | |
359 | ||
360 | uint32_t cregs[16]; | |
361 | } iwmmxt; | |
362 | ||
d8fd2954 PB |
363 | /* For mixed endian mode. */ |
364 | bool bswap_code; | |
365 | ||
ce4defa0 PB |
366 | #if defined(CONFIG_USER_ONLY) |
367 | /* For usermode syscall translation. */ | |
368 | int eabi; | |
369 | #endif | |
370 | ||
46747d15 | 371 | struct CPUBreakpoint *cpu_breakpoint[16]; |
9ee98ce8 PM |
372 | struct CPUWatchpoint *cpu_watchpoint[16]; |
373 | ||
a316d335 FB |
374 | CPU_COMMON |
375 | ||
9d551997 | 376 | /* These fields after the common ones so they are preserved on reset. */ |
9ba8c3f4 | 377 | |
581be094 | 378 | /* Internal CPU feature flags. */ |
918f5dca | 379 | uint64_t features; |
581be094 | 380 | |
983fe826 | 381 | void *nvic; |
462a8bc6 | 382 | const struct arm_boot_info *boot_info; |
2c0262af FB |
383 | } CPUARMState; |
384 | ||
778c3a06 AF |
385 | #include "cpu-qom.h" |
386 | ||
387 | ARMCPU *cpu_arm_init(const char *cpu_model); | |
2c0262af | 388 | int cpu_arm_exec(CPUARMState *s); |
9ee6e8bb | 389 | uint32_t do_arm_semihosting(CPUARMState *env); |
b5ff1b31 | 390 | |
3926cc84 AG |
391 | static inline bool is_a64(CPUARMState *env) |
392 | { | |
393 | return env->aarch64; | |
394 | } | |
395 | ||
2c0262af FB |
396 | /* you can call this signal handler from your SIGBUS and SIGSEGV |
397 | signal handlers to inform the virtual CPU of exceptions. non zero | |
398 | is returned if the signal was handled by the virtual CPU. */ | |
5fafdf24 | 399 | int cpu_arm_signal_handler(int host_signum, void *pinfo, |
2c0262af | 400 | void *puc); |
7510454e AF |
401 | int arm_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int rw, |
402 | int mmu_idx); | |
2c0262af | 403 | |
ec7b4ce4 AF |
404 | /** |
405 | * pmccntr_sync | |
406 | * @env: CPUARMState | |
407 | * | |
408 | * Synchronises the counter in the PMCCNTR. This must always be called twice, | |
409 | * once before any action that might affect the timer and again afterwards. | |
410 | * The function is used to swap the state of the register if required. | |
411 | * This only happens when not in user mode (!CONFIG_USER_ONLY) | |
412 | */ | |
413 | void pmccntr_sync(CPUARMState *env); | |
414 | ||
76e3e1bc PM |
415 | /* SCTLR bit meanings. Several bits have been reused in newer |
416 | * versions of the architecture; in that case we define constants | |
417 | * for both old and new bit meanings. Code which tests against those | |
418 | * bits should probably check or otherwise arrange that the CPU | |
419 | * is the architectural version it expects. | |
420 | */ | |
421 | #define SCTLR_M (1U << 0) | |
422 | #define SCTLR_A (1U << 1) | |
423 | #define SCTLR_C (1U << 2) | |
424 | #define SCTLR_W (1U << 3) /* up to v6; RAO in v7 */ | |
425 | #define SCTLR_SA (1U << 3) | |
426 | #define SCTLR_P (1U << 4) /* up to v5; RAO in v6 and v7 */ | |
427 | #define SCTLR_SA0 (1U << 4) /* v8 onward, AArch64 only */ | |
428 | #define SCTLR_D (1U << 5) /* up to v5; RAO in v6 */ | |
429 | #define SCTLR_CP15BEN (1U << 5) /* v7 onward */ | |
430 | #define SCTLR_L (1U << 6) /* up to v5; RAO in v6 and v7; RAZ in v8 */ | |
431 | #define SCTLR_B (1U << 7) /* up to v6; RAZ in v7 */ | |
432 | #define SCTLR_ITD (1U << 7) /* v8 onward */ | |
433 | #define SCTLR_S (1U << 8) /* up to v6; RAZ in v7 */ | |
434 | #define SCTLR_SED (1U << 8) /* v8 onward */ | |
435 | #define SCTLR_R (1U << 9) /* up to v6; RAZ in v7 */ | |
436 | #define SCTLR_UMA (1U << 9) /* v8 onward, AArch64 only */ | |
437 | #define SCTLR_F (1U << 10) /* up to v6 */ | |
438 | #define SCTLR_SW (1U << 10) /* v7 onward */ | |
439 | #define SCTLR_Z (1U << 11) | |
440 | #define SCTLR_I (1U << 12) | |
441 | #define SCTLR_V (1U << 13) | |
442 | #define SCTLR_RR (1U << 14) /* up to v7 */ | |
443 | #define SCTLR_DZE (1U << 14) /* v8 onward, AArch64 only */ | |
444 | #define SCTLR_L4 (1U << 15) /* up to v6; RAZ in v7 */ | |
445 | #define SCTLR_UCT (1U << 15) /* v8 onward, AArch64 only */ | |
446 | #define SCTLR_DT (1U << 16) /* up to ??, RAO in v6 and v7 */ | |
447 | #define SCTLR_nTWI (1U << 16) /* v8 onward */ | |
448 | #define SCTLR_HA (1U << 17) | |
449 | #define SCTLR_IT (1U << 18) /* up to ??, RAO in v6 and v7 */ | |
450 | #define SCTLR_nTWE (1U << 18) /* v8 onward */ | |
451 | #define SCTLR_WXN (1U << 19) | |
452 | #define SCTLR_ST (1U << 20) /* up to ??, RAZ in v6 */ | |
453 | #define SCTLR_UWXN (1U << 20) /* v7 onward */ | |
454 | #define SCTLR_FI (1U << 21) | |
455 | #define SCTLR_U (1U << 22) | |
456 | #define SCTLR_XP (1U << 23) /* up to v6; v7 onward RAO */ | |
457 | #define SCTLR_VE (1U << 24) /* up to v7 */ | |
458 | #define SCTLR_E0E (1U << 24) /* v8 onward, AArch64 only */ | |
459 | #define SCTLR_EE (1U << 25) | |
460 | #define SCTLR_L2 (1U << 26) /* up to v6, RAZ in v7 */ | |
461 | #define SCTLR_UCI (1U << 26) /* v8 onward, AArch64 only */ | |
462 | #define SCTLR_NMFI (1U << 27) | |
463 | #define SCTLR_TRE (1U << 28) | |
464 | #define SCTLR_AFE (1U << 29) | |
465 | #define SCTLR_TE (1U << 30) | |
466 | ||
78dbbbe4 PM |
467 | #define CPSR_M (0x1fU) |
468 | #define CPSR_T (1U << 5) | |
469 | #define CPSR_F (1U << 6) | |
470 | #define CPSR_I (1U << 7) | |
471 | #define CPSR_A (1U << 8) | |
472 | #define CPSR_E (1U << 9) | |
473 | #define CPSR_IT_2_7 (0xfc00U) | |
474 | #define CPSR_GE (0xfU << 16) | |
4051e12c PM |
475 | #define CPSR_IL (1U << 20) |
476 | /* Note that the RESERVED bits include bit 21, which is PSTATE_SS in | |
477 | * an AArch64 SPSR but RES0 in AArch32 SPSR and CPSR. In QEMU we use | |
478 | * env->uncached_cpsr bit 21 to store PSTATE.SS when executing in AArch32, | |
479 | * where it is live state but not accessible to the AArch32 code. | |
480 | */ | |
481 | #define CPSR_RESERVED (0x7U << 21) | |
78dbbbe4 PM |
482 | #define CPSR_J (1U << 24) |
483 | #define CPSR_IT_0_1 (3U << 25) | |
484 | #define CPSR_Q (1U << 27) | |
485 | #define CPSR_V (1U << 28) | |
486 | #define CPSR_C (1U << 29) | |
487 | #define CPSR_Z (1U << 30) | |
488 | #define CPSR_N (1U << 31) | |
9ee6e8bb | 489 | #define CPSR_NZCV (CPSR_N | CPSR_Z | CPSR_C | CPSR_V) |
4cc35614 | 490 | #define CPSR_AIF (CPSR_A | CPSR_I | CPSR_F) |
9ee6e8bb PB |
491 | |
492 | #define CPSR_IT (CPSR_IT_0_1 | CPSR_IT_2_7) | |
4cc35614 PM |
493 | #define CACHED_CPSR_BITS (CPSR_T | CPSR_AIF | CPSR_GE | CPSR_IT | CPSR_Q \ |
494 | | CPSR_NZCV) | |
9ee6e8bb PB |
495 | /* Bits writable in user mode. */ |
496 | #define CPSR_USER (CPSR_NZCV | CPSR_Q | CPSR_GE) | |
497 | /* Execution state bits. MRS read as zero, MSR writes ignored. */ | |
4051e12c PM |
498 | #define CPSR_EXEC (CPSR_T | CPSR_IT | CPSR_J | CPSR_IL) |
499 | /* Mask of bits which may be set by exception return copying them from SPSR */ | |
500 | #define CPSR_ERET_MASK (~CPSR_RESERVED) | |
b5ff1b31 | 501 | |
e389be16 FA |
502 | #define TTBCR_N (7U << 0) /* TTBCR.EAE==0 */ |
503 | #define TTBCR_T0SZ (7U << 0) /* TTBCR.EAE==1 */ | |
504 | #define TTBCR_PD0 (1U << 4) | |
505 | #define TTBCR_PD1 (1U << 5) | |
506 | #define TTBCR_EPD0 (1U << 7) | |
507 | #define TTBCR_IRGN0 (3U << 8) | |
508 | #define TTBCR_ORGN0 (3U << 10) | |
509 | #define TTBCR_SH0 (3U << 12) | |
510 | #define TTBCR_T1SZ (3U << 16) | |
511 | #define TTBCR_A1 (1U << 22) | |
512 | #define TTBCR_EPD1 (1U << 23) | |
513 | #define TTBCR_IRGN1 (3U << 24) | |
514 | #define TTBCR_ORGN1 (3U << 26) | |
515 | #define TTBCR_SH1 (1U << 28) | |
516 | #define TTBCR_EAE (1U << 31) | |
517 | ||
d356312f PM |
518 | /* Bit definitions for ARMv8 SPSR (PSTATE) format. |
519 | * Only these are valid when in AArch64 mode; in | |
520 | * AArch32 mode SPSRs are basically CPSR-format. | |
521 | */ | |
f502cfc2 | 522 | #define PSTATE_SP (1U) |
d356312f PM |
523 | #define PSTATE_M (0xFU) |
524 | #define PSTATE_nRW (1U << 4) | |
525 | #define PSTATE_F (1U << 6) | |
526 | #define PSTATE_I (1U << 7) | |
527 | #define PSTATE_A (1U << 8) | |
528 | #define PSTATE_D (1U << 9) | |
529 | #define PSTATE_IL (1U << 20) | |
530 | #define PSTATE_SS (1U << 21) | |
531 | #define PSTATE_V (1U << 28) | |
532 | #define PSTATE_C (1U << 29) | |
533 | #define PSTATE_Z (1U << 30) | |
534 | #define PSTATE_N (1U << 31) | |
535 | #define PSTATE_NZCV (PSTATE_N | PSTATE_Z | PSTATE_C | PSTATE_V) | |
4cc35614 PM |
536 | #define PSTATE_DAIF (PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F) |
537 | #define CACHED_PSTATE_BITS (PSTATE_NZCV | PSTATE_DAIF) | |
d356312f PM |
538 | /* Mode values for AArch64 */ |
539 | #define PSTATE_MODE_EL3h 13 | |
540 | #define PSTATE_MODE_EL3t 12 | |
541 | #define PSTATE_MODE_EL2h 9 | |
542 | #define PSTATE_MODE_EL2t 8 | |
543 | #define PSTATE_MODE_EL1h 5 | |
544 | #define PSTATE_MODE_EL1t 4 | |
545 | #define PSTATE_MODE_EL0t 0 | |
546 | ||
9e729b57 EI |
547 | /* Map EL and handler into a PSTATE_MODE. */ |
548 | static inline unsigned int aarch64_pstate_mode(unsigned int el, bool handler) | |
549 | { | |
550 | return (el << 2) | handler; | |
551 | } | |
552 | ||
d356312f PM |
553 | /* Return the current PSTATE value. For the moment we don't support 32<->64 bit |
554 | * interprocessing, so we don't attempt to sync with the cpsr state used by | |
555 | * the 32 bit decoder. | |
556 | */ | |
557 | static inline uint32_t pstate_read(CPUARMState *env) | |
558 | { | |
559 | int ZF; | |
560 | ||
561 | ZF = (env->ZF == 0); | |
562 | return (env->NF & 0x80000000) | (ZF << 30) | |
563 | | (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | |
4cc35614 | 564 | | env->pstate | env->daif; |
d356312f PM |
565 | } |
566 | ||
567 | static inline void pstate_write(CPUARMState *env, uint32_t val) | |
568 | { | |
569 | env->ZF = (~val) & PSTATE_Z; | |
570 | env->NF = val; | |
571 | env->CF = (val >> 29) & 1; | |
572 | env->VF = (val << 3) & 0x80000000; | |
4cc35614 | 573 | env->daif = val & PSTATE_DAIF; |
d356312f PM |
574 | env->pstate = val & ~CACHED_PSTATE_BITS; |
575 | } | |
576 | ||
b5ff1b31 | 577 | /* Return the current CPSR value. */ |
2f4a40e5 AZ |
578 | uint32_t cpsr_read(CPUARMState *env); |
579 | /* Set the CPSR. Note that some bits of mask must be all-set or all-clear. */ | |
580 | void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask); | |
9ee6e8bb PB |
581 | |
582 | /* Return the current xPSR value. */ | |
583 | static inline uint32_t xpsr_read(CPUARMState *env) | |
584 | { | |
585 | int ZF; | |
6fbe23d5 PB |
586 | ZF = (env->ZF == 0); |
587 | return (env->NF & 0x80000000) | (ZF << 30) | |
9ee6e8bb PB |
588 | | (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27) |
589 | | (env->thumb << 24) | ((env->condexec_bits & 3) << 25) | |
590 | | ((env->condexec_bits & 0xfc) << 8) | |
591 | | env->v7m.exception; | |
b5ff1b31 FB |
592 | } |
593 | ||
9ee6e8bb PB |
594 | /* Set the xPSR. Note that some bits of mask must be all-set or all-clear. */ |
595 | static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask) | |
596 | { | |
9ee6e8bb | 597 | if (mask & CPSR_NZCV) { |
6fbe23d5 PB |
598 | env->ZF = (~val) & CPSR_Z; |
599 | env->NF = val; | |
9ee6e8bb PB |
600 | env->CF = (val >> 29) & 1; |
601 | env->VF = (val << 3) & 0x80000000; | |
602 | } | |
603 | if (mask & CPSR_Q) | |
604 | env->QF = ((val & CPSR_Q) != 0); | |
605 | if (mask & (1 << 24)) | |
606 | env->thumb = ((val & (1 << 24)) != 0); | |
607 | if (mask & CPSR_IT_0_1) { | |
608 | env->condexec_bits &= ~3; | |
609 | env->condexec_bits |= (val >> 25) & 3; | |
610 | } | |
611 | if (mask & CPSR_IT_2_7) { | |
612 | env->condexec_bits &= 3; | |
613 | env->condexec_bits |= (val >> 8) & 0xfc; | |
614 | } | |
615 | if (mask & 0x1ff) { | |
616 | env->v7m.exception = val & 0x1ff; | |
617 | } | |
618 | } | |
619 | ||
f149e3e8 EI |
620 | #define HCR_VM (1ULL << 0) |
621 | #define HCR_SWIO (1ULL << 1) | |
622 | #define HCR_PTW (1ULL << 2) | |
623 | #define HCR_FMO (1ULL << 3) | |
624 | #define HCR_IMO (1ULL << 4) | |
625 | #define HCR_AMO (1ULL << 5) | |
626 | #define HCR_VF (1ULL << 6) | |
627 | #define HCR_VI (1ULL << 7) | |
628 | #define HCR_VSE (1ULL << 8) | |
629 | #define HCR_FB (1ULL << 9) | |
630 | #define HCR_BSU_MASK (3ULL << 10) | |
631 | #define HCR_DC (1ULL << 12) | |
632 | #define HCR_TWI (1ULL << 13) | |
633 | #define HCR_TWE (1ULL << 14) | |
634 | #define HCR_TID0 (1ULL << 15) | |
635 | #define HCR_TID1 (1ULL << 16) | |
636 | #define HCR_TID2 (1ULL << 17) | |
637 | #define HCR_TID3 (1ULL << 18) | |
638 | #define HCR_TSC (1ULL << 19) | |
639 | #define HCR_TIDCP (1ULL << 20) | |
640 | #define HCR_TACR (1ULL << 21) | |
641 | #define HCR_TSW (1ULL << 22) | |
642 | #define HCR_TPC (1ULL << 23) | |
643 | #define HCR_TPU (1ULL << 24) | |
644 | #define HCR_TTLB (1ULL << 25) | |
645 | #define HCR_TVM (1ULL << 26) | |
646 | #define HCR_TGE (1ULL << 27) | |
647 | #define HCR_TDZ (1ULL << 28) | |
648 | #define HCR_HCD (1ULL << 29) | |
649 | #define HCR_TRVM (1ULL << 30) | |
650 | #define HCR_RW (1ULL << 31) | |
651 | #define HCR_CD (1ULL << 32) | |
652 | #define HCR_ID (1ULL << 33) | |
653 | #define HCR_MASK ((1ULL << 34) - 1) | |
654 | ||
64e0e2de EI |
655 | #define SCR_NS (1U << 0) |
656 | #define SCR_IRQ (1U << 1) | |
657 | #define SCR_FIQ (1U << 2) | |
658 | #define SCR_EA (1U << 3) | |
659 | #define SCR_FW (1U << 4) | |
660 | #define SCR_AW (1U << 5) | |
661 | #define SCR_NET (1U << 6) | |
662 | #define SCR_SMD (1U << 7) | |
663 | #define SCR_HCE (1U << 8) | |
664 | #define SCR_SIF (1U << 9) | |
665 | #define SCR_RW (1U << 10) | |
666 | #define SCR_ST (1U << 11) | |
667 | #define SCR_TWI (1U << 12) | |
668 | #define SCR_TWE (1U << 13) | |
669 | #define SCR_AARCH32_MASK (0x3fff & ~(SCR_RW | SCR_ST)) | |
670 | #define SCR_AARCH64_MASK (0x3fff & ~SCR_NET) | |
671 | ||
01653295 PM |
672 | /* Return the current FPSCR value. */ |
673 | uint32_t vfp_get_fpscr(CPUARMState *env); | |
674 | void vfp_set_fpscr(CPUARMState *env, uint32_t val); | |
675 | ||
f903fa22 PM |
676 | /* For A64 the FPSCR is split into two logically distinct registers, |
677 | * FPCR and FPSR. However since they still use non-overlapping bits | |
678 | * we store the underlying state in fpscr and just mask on read/write. | |
679 | */ | |
680 | #define FPSR_MASK 0xf800009f | |
681 | #define FPCR_MASK 0x07f79f00 | |
682 | static inline uint32_t vfp_get_fpsr(CPUARMState *env) | |
683 | { | |
684 | return vfp_get_fpscr(env) & FPSR_MASK; | |
685 | } | |
686 | ||
687 | static inline void vfp_set_fpsr(CPUARMState *env, uint32_t val) | |
688 | { | |
689 | uint32_t new_fpscr = (vfp_get_fpscr(env) & ~FPSR_MASK) | (val & FPSR_MASK); | |
690 | vfp_set_fpscr(env, new_fpscr); | |
691 | } | |
692 | ||
693 | static inline uint32_t vfp_get_fpcr(CPUARMState *env) | |
694 | { | |
695 | return vfp_get_fpscr(env) & FPCR_MASK; | |
696 | } | |
697 | ||
698 | static inline void vfp_set_fpcr(CPUARMState *env, uint32_t val) | |
699 | { | |
700 | uint32_t new_fpscr = (vfp_get_fpscr(env) & ~FPCR_MASK) | (val & FPCR_MASK); | |
701 | vfp_set_fpscr(env, new_fpscr); | |
702 | } | |
703 | ||
b5ff1b31 FB |
704 | enum arm_cpu_mode { |
705 | ARM_CPU_MODE_USR = 0x10, | |
706 | ARM_CPU_MODE_FIQ = 0x11, | |
707 | ARM_CPU_MODE_IRQ = 0x12, | |
708 | ARM_CPU_MODE_SVC = 0x13, | |
28c9457d | 709 | ARM_CPU_MODE_MON = 0x16, |
b5ff1b31 | 710 | ARM_CPU_MODE_ABT = 0x17, |
28c9457d | 711 | ARM_CPU_MODE_HYP = 0x1a, |
b5ff1b31 FB |
712 | ARM_CPU_MODE_UND = 0x1b, |
713 | ARM_CPU_MODE_SYS = 0x1f | |
714 | }; | |
715 | ||
40f137e1 PB |
716 | /* VFP system registers. */ |
717 | #define ARM_VFP_FPSID 0 | |
718 | #define ARM_VFP_FPSCR 1 | |
a50c0f51 | 719 | #define ARM_VFP_MVFR2 5 |
9ee6e8bb PB |
720 | #define ARM_VFP_MVFR1 6 |
721 | #define ARM_VFP_MVFR0 7 | |
40f137e1 PB |
722 | #define ARM_VFP_FPEXC 8 |
723 | #define ARM_VFP_FPINST 9 | |
724 | #define ARM_VFP_FPINST2 10 | |
725 | ||
18c9b560 AZ |
726 | /* iwMMXt coprocessor control registers. */ |
727 | #define ARM_IWMMXT_wCID 0 | |
728 | #define ARM_IWMMXT_wCon 1 | |
729 | #define ARM_IWMMXT_wCSSF 2 | |
730 | #define ARM_IWMMXT_wCASF 3 | |
731 | #define ARM_IWMMXT_wCGR0 8 | |
732 | #define ARM_IWMMXT_wCGR1 9 | |
733 | #define ARM_IWMMXT_wCGR2 10 | |
734 | #define ARM_IWMMXT_wCGR3 11 | |
735 | ||
ce854d7c BC |
736 | /* If adding a feature bit which corresponds to a Linux ELF |
737 | * HWCAP bit, remember to update the feature-bit-to-hwcap | |
738 | * mapping in linux-user/elfload.c:get_elf_hwcap(). | |
739 | */ | |
40f137e1 PB |
740 | enum arm_features { |
741 | ARM_FEATURE_VFP, | |
c1713132 AZ |
742 | ARM_FEATURE_AUXCR, /* ARM1026 Auxiliary control register. */ |
743 | ARM_FEATURE_XSCALE, /* Intel XScale extensions. */ | |
ce819861 | 744 | ARM_FEATURE_IWMMXT, /* Intel iwMMXt extension. */ |
9ee6e8bb PB |
745 | ARM_FEATURE_V6, |
746 | ARM_FEATURE_V6K, | |
747 | ARM_FEATURE_V7, | |
748 | ARM_FEATURE_THUMB2, | |
c3d2689d | 749 | ARM_FEATURE_MPU, /* Only has Memory Protection Unit, not full MMU. */ |
9ee6e8bb | 750 | ARM_FEATURE_VFP3, |
60011498 | 751 | ARM_FEATURE_VFP_FP16, |
9ee6e8bb | 752 | ARM_FEATURE_NEON, |
47789990 | 753 | ARM_FEATURE_THUMB_DIV, /* divide supported in Thumb encoding */ |
9ee6e8bb | 754 | ARM_FEATURE_M, /* Microcontroller profile. */ |
fe1479c3 | 755 | ARM_FEATURE_OMAPCP, /* OMAP specific CP15 ops handling. */ |
e1bbf446 | 756 | ARM_FEATURE_THUMB2EE, |
be5e7a76 DES |
757 | ARM_FEATURE_V7MP, /* v7 Multiprocessing Extensions */ |
758 | ARM_FEATURE_V4T, | |
759 | ARM_FEATURE_V5, | |
5bc95aa2 | 760 | ARM_FEATURE_STRONGARM, |
906879a9 | 761 | ARM_FEATURE_VAPA, /* cp15 VA to PA lookups */ |
b8b8ea05 | 762 | ARM_FEATURE_ARM_DIV, /* divide supported in ARM encoding */ |
da97f52c | 763 | ARM_FEATURE_VFP4, /* VFPv4 (implies that NEON is v2) */ |
0383ac00 | 764 | ARM_FEATURE_GENERIC_TIMER, |
06ed5d66 | 765 | ARM_FEATURE_MVFR, /* Media and VFP Feature Registers 0 and 1 */ |
1047b9d7 | 766 | ARM_FEATURE_DUMMY_C15_REGS, /* RAZ/WI all of cp15 crn=15 */ |
c4804214 PM |
767 | ARM_FEATURE_CACHE_TEST_CLEAN, /* 926/1026 style test-and-clean ops */ |
768 | ARM_FEATURE_CACHE_DIRTY_REG, /* 1136/1176 cache dirty status register */ | |
769 | ARM_FEATURE_CACHE_BLOCK_OPS, /* v6 optional cache block operations */ | |
81bdde9d | 770 | ARM_FEATURE_MPIDR, /* has cp15 MPIDR */ |
de9b05b8 PM |
771 | ARM_FEATURE_PXN, /* has Privileged Execute Never bit */ |
772 | ARM_FEATURE_LPAE, /* has Large Physical Address Extension */ | |
81e69fb0 | 773 | ARM_FEATURE_V8, |
3926cc84 | 774 | ARM_FEATURE_AARCH64, /* supports 64 bit mode */ |
9d935509 | 775 | ARM_FEATURE_V8_AES, /* implements AES part of v8 Crypto Extensions */ |
d8ba780b | 776 | ARM_FEATURE_CBAR, /* has cp15 CBAR */ |
eb0ecd5a | 777 | ARM_FEATURE_CRC, /* ARMv8 CRC instructions */ |
f318cec6 | 778 | ARM_FEATURE_CBAR_RO, /* has cp15 CBAR and it is read-only */ |
cca7c2f5 | 779 | ARM_FEATURE_EL2, /* has EL2 Virtualization support */ |
1fe8141e | 780 | ARM_FEATURE_EL3, /* has EL3 Secure monitor support */ |
f1ecb913 AB |
781 | ARM_FEATURE_V8_SHA1, /* implements SHA1 part of v8 Crypto Extensions */ |
782 | ARM_FEATURE_V8_SHA256, /* implements SHA256 part of v8 Crypto Extensions */ | |
4e624eda | 783 | ARM_FEATURE_V8_PMULL, /* implements PMULL part of v8 Crypto Extensions */ |
40f137e1 PB |
784 | }; |
785 | ||
786 | static inline int arm_feature(CPUARMState *env, int feature) | |
787 | { | |
918f5dca | 788 | return (env->features & (1ULL << feature)) != 0; |
40f137e1 PB |
789 | } |
790 | ||
19e0fefa FA |
791 | #if !defined(CONFIG_USER_ONLY) |
792 | /* Return true if exception levels below EL3 are in secure state, | |
793 | * or would be following an exception return to that level. | |
794 | * Unlike arm_is_secure() (which is always a question about the | |
795 | * _current_ state of the CPU) this doesn't care about the current | |
796 | * EL or mode. | |
797 | */ | |
798 | static inline bool arm_is_secure_below_el3(CPUARMState *env) | |
799 | { | |
800 | if (arm_feature(env, ARM_FEATURE_EL3)) { | |
801 | return !(env->cp15.scr_el3 & SCR_NS); | |
802 | } else { | |
803 | /* If EL2 is not supported then the secure state is implementation | |
804 | * defined, in which case QEMU defaults to non-secure. | |
805 | */ | |
806 | return false; | |
807 | } | |
808 | } | |
809 | ||
810 | /* Return true if the processor is in secure state */ | |
811 | static inline bool arm_is_secure(CPUARMState *env) | |
812 | { | |
813 | if (arm_feature(env, ARM_FEATURE_EL3)) { | |
814 | if (is_a64(env) && extract32(env->pstate, 2, 2) == 3) { | |
815 | /* CPU currently in AArch64 state and EL3 */ | |
816 | return true; | |
817 | } else if (!is_a64(env) && | |
818 | (env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_MON) { | |
819 | /* CPU currently in AArch32 state and monitor mode */ | |
820 | return true; | |
821 | } | |
822 | } | |
823 | return arm_is_secure_below_el3(env); | |
824 | } | |
825 | ||
826 | #else | |
827 | static inline bool arm_is_secure_below_el3(CPUARMState *env) | |
828 | { | |
829 | return false; | |
830 | } | |
831 | ||
832 | static inline bool arm_is_secure(CPUARMState *env) | |
833 | { | |
834 | return false; | |
835 | } | |
836 | #endif | |
837 | ||
1f79ee32 PM |
838 | /* Return true if the specified exception level is running in AArch64 state. */ |
839 | static inline bool arm_el_is_aa64(CPUARMState *env, int el) | |
840 | { | |
592125f8 | 841 | /* We don't currently support EL2, and this isn't valid for EL0 |
1f79ee32 PM |
842 | * (if we're in EL0, is_a64() is what you want, and if we're not in EL0 |
843 | * then the state of EL0 isn't well defined.) | |
844 | */ | |
592125f8 FA |
845 | assert(el == 1 || el == 3); |
846 | ||
1f79ee32 PM |
847 | /* AArch64-capable CPUs always run with EL1 in AArch64 mode. This |
848 | * is a QEMU-imposed simplification which we may wish to change later. | |
849 | * If we in future support EL2 and/or EL3, then the state of lower | |
850 | * exception levels is controlled by the HCR.RW and SCR.RW bits. | |
851 | */ | |
852 | return arm_feature(env, ARM_FEATURE_AARCH64); | |
853 | } | |
854 | ||
3f342b9e SF |
855 | /* Function for determing whether guest cp register reads and writes should |
856 | * access the secure or non-secure bank of a cp register. When EL3 is | |
857 | * operating in AArch32 state, the NS-bit determines whether the secure | |
858 | * instance of a cp register should be used. When EL3 is AArch64 (or if | |
859 | * it doesn't exist at all) then there is no register banking, and all | |
860 | * accesses are to the non-secure version. | |
861 | */ | |
862 | static inline bool access_secure_reg(CPUARMState *env) | |
863 | { | |
864 | bool ret = (arm_feature(env, ARM_FEATURE_EL3) && | |
865 | !arm_el_is_aa64(env, 3) && | |
866 | !(env->cp15.scr_el3 & SCR_NS)); | |
867 | ||
868 | return ret; | |
869 | } | |
870 | ||
ea30a4b8 FA |
871 | /* Macros for accessing a specified CP register bank */ |
872 | #define A32_BANKED_REG_GET(_env, _regname, _secure) \ | |
873 | ((_secure) ? (_env)->cp15._regname##_s : (_env)->cp15._regname##_ns) | |
874 | ||
875 | #define A32_BANKED_REG_SET(_env, _regname, _secure, _val) \ | |
876 | do { \ | |
877 | if (_secure) { \ | |
878 | (_env)->cp15._regname##_s = (_val); \ | |
879 | } else { \ | |
880 | (_env)->cp15._regname##_ns = (_val); \ | |
881 | } \ | |
882 | } while (0) | |
883 | ||
884 | /* Macros for automatically accessing a specific CP register bank depending on | |
885 | * the current secure state of the system. These macros are not intended for | |
886 | * supporting instruction translation reads/writes as these are dependent | |
887 | * solely on the SCR.NS bit and not the mode. | |
888 | */ | |
889 | #define A32_BANKED_CURRENT_REG_GET(_env, _regname) \ | |
890 | A32_BANKED_REG_GET((_env), _regname, \ | |
891 | ((!arm_el_is_aa64((_env), 3) && arm_is_secure(_env)))) | |
892 | ||
893 | #define A32_BANKED_CURRENT_REG_SET(_env, _regname, _val) \ | |
894 | A32_BANKED_REG_SET((_env), _regname, \ | |
895 | ((!arm_el_is_aa64((_env), 3) && arm_is_secure(_env))), \ | |
896 | (_val)) | |
897 | ||
9a78eead | 898 | void arm_cpu_list(FILE *f, fprintf_function cpu_fprintf); |
9e729b57 | 899 | unsigned int arm_excp_target_el(CPUState *cs, unsigned int excp_idx); |
40f137e1 | 900 | |
9ee6e8bb PB |
901 | /* Interface between CPU and Interrupt controller. */ |
902 | void armv7m_nvic_set_pending(void *opaque, int irq); | |
903 | int armv7m_nvic_acknowledge_irq(void *opaque); | |
904 | void armv7m_nvic_complete_irq(void *opaque, int irq); | |
905 | ||
4b6a83fb PM |
906 | /* Interface for defining coprocessor registers. |
907 | * Registers are defined in tables of arm_cp_reginfo structs | |
908 | * which are passed to define_arm_cp_regs(). | |
909 | */ | |
910 | ||
911 | /* When looking up a coprocessor register we look for it | |
912 | * via an integer which encodes all of: | |
913 | * coprocessor number | |
914 | * Crn, Crm, opc1, opc2 fields | |
915 | * 32 or 64 bit register (ie is it accessed via MRC/MCR | |
916 | * or via MRRC/MCRR?) | |
51a79b03 | 917 | * non-secure/secure bank (AArch32 only) |
4b6a83fb PM |
918 | * We allow 4 bits for opc1 because MRRC/MCRR have a 4 bit field. |
919 | * (In this case crn and opc2 should be zero.) | |
f5a0a5a5 PM |
920 | * For AArch64, there is no 32/64 bit size distinction; |
921 | * instead all registers have a 2 bit op0, 3 bit op1 and op2, | |
922 | * and 4 bit CRn and CRm. The encoding patterns are chosen | |
923 | * to be easy to convert to and from the KVM encodings, and also | |
924 | * so that the hashtable can contain both AArch32 and AArch64 | |
925 | * registers (to allow for interprocessing where we might run | |
926 | * 32 bit code on a 64 bit core). | |
4b6a83fb | 927 | */ |
f5a0a5a5 PM |
928 | /* This bit is private to our hashtable cpreg; in KVM register |
929 | * IDs the AArch64/32 distinction is the KVM_REG_ARM/ARM64 | |
930 | * in the upper bits of the 64 bit ID. | |
931 | */ | |
932 | #define CP_REG_AA64_SHIFT 28 | |
933 | #define CP_REG_AA64_MASK (1 << CP_REG_AA64_SHIFT) | |
934 | ||
51a79b03 PM |
935 | /* To enable banking of coprocessor registers depending on ns-bit we |
936 | * add a bit to distinguish between secure and non-secure cpregs in the | |
937 | * hashtable. | |
938 | */ | |
939 | #define CP_REG_NS_SHIFT 29 | |
940 | #define CP_REG_NS_MASK (1 << CP_REG_NS_SHIFT) | |
941 | ||
942 | #define ENCODE_CP_REG(cp, is64, ns, crn, crm, opc1, opc2) \ | |
943 | ((ns) << CP_REG_NS_SHIFT | ((cp) << 16) | ((is64) << 15) | \ | |
944 | ((crn) << 11) | ((crm) << 7) | ((opc1) << 3) | (opc2)) | |
4b6a83fb | 945 | |
f5a0a5a5 PM |
946 | #define ENCODE_AA64_CP_REG(cp, crn, crm, op0, op1, op2) \ |
947 | (CP_REG_AA64_MASK | \ | |
948 | ((cp) << CP_REG_ARM_COPROC_SHIFT) | \ | |
949 | ((op0) << CP_REG_ARM64_SYSREG_OP0_SHIFT) | \ | |
950 | ((op1) << CP_REG_ARM64_SYSREG_OP1_SHIFT) | \ | |
951 | ((crn) << CP_REG_ARM64_SYSREG_CRN_SHIFT) | \ | |
952 | ((crm) << CP_REG_ARM64_SYSREG_CRM_SHIFT) | \ | |
953 | ((op2) << CP_REG_ARM64_SYSREG_OP2_SHIFT)) | |
954 | ||
721fae12 PM |
955 | /* Convert a full 64 bit KVM register ID to the truncated 32 bit |
956 | * version used as a key for the coprocessor register hashtable | |
957 | */ | |
958 | static inline uint32_t kvm_to_cpreg_id(uint64_t kvmid) | |
959 | { | |
960 | uint32_t cpregid = kvmid; | |
f5a0a5a5 PM |
961 | if ((kvmid & CP_REG_ARCH_MASK) == CP_REG_ARM64) { |
962 | cpregid |= CP_REG_AA64_MASK; | |
51a79b03 PM |
963 | } else { |
964 | if ((kvmid & CP_REG_SIZE_MASK) == CP_REG_SIZE_U64) { | |
965 | cpregid |= (1 << 15); | |
966 | } | |
967 | ||
968 | /* KVM is always non-secure so add the NS flag on AArch32 register | |
969 | * entries. | |
970 | */ | |
971 | cpregid |= 1 << CP_REG_NS_SHIFT; | |
721fae12 PM |
972 | } |
973 | return cpregid; | |
974 | } | |
975 | ||
976 | /* Convert a truncated 32 bit hashtable key into the full | |
977 | * 64 bit KVM register ID. | |
978 | */ | |
979 | static inline uint64_t cpreg_to_kvm_id(uint32_t cpregid) | |
980 | { | |
f5a0a5a5 PM |
981 | uint64_t kvmid; |
982 | ||
983 | if (cpregid & CP_REG_AA64_MASK) { | |
984 | kvmid = cpregid & ~CP_REG_AA64_MASK; | |
985 | kvmid |= CP_REG_SIZE_U64 | CP_REG_ARM64; | |
721fae12 | 986 | } else { |
f5a0a5a5 PM |
987 | kvmid = cpregid & ~(1 << 15); |
988 | if (cpregid & (1 << 15)) { | |
989 | kvmid |= CP_REG_SIZE_U64 | CP_REG_ARM; | |
990 | } else { | |
991 | kvmid |= CP_REG_SIZE_U32 | CP_REG_ARM; | |
992 | } | |
721fae12 PM |
993 | } |
994 | return kvmid; | |
995 | } | |
996 | ||
4b6a83fb PM |
997 | /* ARMCPRegInfo type field bits. If the SPECIAL bit is set this is a |
998 | * special-behaviour cp reg and bits [15..8] indicate what behaviour | |
999 | * it has. Otherwise it is a simple cp reg, where CONST indicates that | |
1000 | * TCG can assume the value to be constant (ie load at translate time) | |
1001 | * and 64BIT indicates a 64 bit wide coprocessor register. SUPPRESS_TB_END | |
1002 | * indicates that the TB should not be ended after a write to this register | |
1003 | * (the default is that the TB ends after cp writes). OVERRIDE permits | |
1004 | * a register definition to override a previous definition for the | |
1005 | * same (cp, is64, crn, crm, opc1, opc2) tuple: either the new or the | |
1006 | * old must have the OVERRIDE bit set. | |
7023ec7e PM |
1007 | * NO_MIGRATE indicates that this register should be ignored for migration; |
1008 | * (eg because any state is accessed via some other coprocessor register). | |
2452731c PM |
1009 | * IO indicates that this register does I/O and therefore its accesses |
1010 | * need to be surrounded by gen_io_start()/gen_io_end(). In particular, | |
1011 | * registers which implement clocks or timers require this. | |
4b6a83fb PM |
1012 | */ |
1013 | #define ARM_CP_SPECIAL 1 | |
1014 | #define ARM_CP_CONST 2 | |
1015 | #define ARM_CP_64BIT 4 | |
1016 | #define ARM_CP_SUPPRESS_TB_END 8 | |
1017 | #define ARM_CP_OVERRIDE 16 | |
7023ec7e | 1018 | #define ARM_CP_NO_MIGRATE 32 |
2452731c | 1019 | #define ARM_CP_IO 64 |
4b6a83fb PM |
1020 | #define ARM_CP_NOP (ARM_CP_SPECIAL | (1 << 8)) |
1021 | #define ARM_CP_WFI (ARM_CP_SPECIAL | (2 << 8)) | |
b0d2b7d0 | 1022 | #define ARM_CP_NZCV (ARM_CP_SPECIAL | (3 << 8)) |
0eef9d98 | 1023 | #define ARM_CP_CURRENTEL (ARM_CP_SPECIAL | (4 << 8)) |
aca3f40b PM |
1024 | #define ARM_CP_DC_ZVA (ARM_CP_SPECIAL | (5 << 8)) |
1025 | #define ARM_LAST_SPECIAL ARM_CP_DC_ZVA | |
4b6a83fb PM |
1026 | /* Used only as a terminator for ARMCPRegInfo lists */ |
1027 | #define ARM_CP_SENTINEL 0xffff | |
1028 | /* Mask of only the flag bits in a type field */ | |
2452731c | 1029 | #define ARM_CP_FLAG_MASK 0x7f |
4b6a83fb | 1030 | |
f5a0a5a5 PM |
1031 | /* Valid values for ARMCPRegInfo state field, indicating which of |
1032 | * the AArch32 and AArch64 execution states this register is visible in. | |
1033 | * If the reginfo doesn't explicitly specify then it is AArch32 only. | |
1034 | * If the reginfo is declared to be visible in both states then a second | |
1035 | * reginfo is synthesised for the AArch32 view of the AArch64 register, | |
1036 | * such that the AArch32 view is the lower 32 bits of the AArch64 one. | |
1037 | * Note that we rely on the values of these enums as we iterate through | |
1038 | * the various states in some places. | |
1039 | */ | |
1040 | enum { | |
1041 | ARM_CP_STATE_AA32 = 0, | |
1042 | ARM_CP_STATE_AA64 = 1, | |
1043 | ARM_CP_STATE_BOTH = 2, | |
1044 | }; | |
1045 | ||
c3e30260 FA |
1046 | /* ARM CP register secure state flags. These flags identify security state |
1047 | * attributes for a given CP register entry. | |
1048 | * The existence of both or neither secure and non-secure flags indicates that | |
1049 | * the register has both a secure and non-secure hash entry. A single one of | |
1050 | * these flags causes the register to only be hashed for the specified | |
1051 | * security state. | |
1052 | * Although definitions may have any combination of the S/NS bits, each | |
1053 | * registered entry will only have one to identify whether the entry is secure | |
1054 | * or non-secure. | |
1055 | */ | |
1056 | enum { | |
1057 | ARM_CP_SECSTATE_S = (1 << 0), /* bit[0]: Secure state register */ | |
1058 | ARM_CP_SECSTATE_NS = (1 << 1), /* bit[1]: Non-secure state register */ | |
1059 | }; | |
1060 | ||
4b6a83fb PM |
1061 | /* Return true if cptype is a valid type field. This is used to try to |
1062 | * catch errors where the sentinel has been accidentally left off the end | |
1063 | * of a list of registers. | |
1064 | */ | |
1065 | static inline bool cptype_valid(int cptype) | |
1066 | { | |
1067 | return ((cptype & ~ARM_CP_FLAG_MASK) == 0) | |
1068 | || ((cptype & ARM_CP_SPECIAL) && | |
34affeef | 1069 | ((cptype & ~ARM_CP_FLAG_MASK) <= ARM_LAST_SPECIAL)); |
4b6a83fb PM |
1070 | } |
1071 | ||
1072 | /* Access rights: | |
1073 | * We define bits for Read and Write access for what rev C of the v7-AR ARM ARM | |
1074 | * defines as PL0 (user), PL1 (fiq/irq/svc/abt/und/sys, ie privileged), and | |
1075 | * PL2 (hyp). The other level which has Read and Write bits is Secure PL1 | |
1076 | * (ie any of the privileged modes in Secure state, or Monitor mode). | |
1077 | * If a register is accessible in one privilege level it's always accessible | |
1078 | * in higher privilege levels too. Since "Secure PL1" also follows this rule | |
1079 | * (ie anything visible in PL2 is visible in S-PL1, some things are only | |
1080 | * visible in S-PL1) but "Secure PL1" is a bit of a mouthful, we bend the | |
1081 | * terminology a little and call this PL3. | |
f5a0a5a5 PM |
1082 | * In AArch64 things are somewhat simpler as the PLx bits line up exactly |
1083 | * with the ELx exception levels. | |
4b6a83fb PM |
1084 | * |
1085 | * If access permissions for a register are more complex than can be | |
1086 | * described with these bits, then use a laxer set of restrictions, and | |
1087 | * do the more restrictive/complex check inside a helper function. | |
1088 | */ | |
1089 | #define PL3_R 0x80 | |
1090 | #define PL3_W 0x40 | |
1091 | #define PL2_R (0x20 | PL3_R) | |
1092 | #define PL2_W (0x10 | PL3_W) | |
1093 | #define PL1_R (0x08 | PL2_R) | |
1094 | #define PL1_W (0x04 | PL2_W) | |
1095 | #define PL0_R (0x02 | PL1_R) | |
1096 | #define PL0_W (0x01 | PL1_W) | |
1097 | ||
1098 | #define PL3_RW (PL3_R | PL3_W) | |
1099 | #define PL2_RW (PL2_R | PL2_W) | |
1100 | #define PL1_RW (PL1_R | PL1_W) | |
1101 | #define PL0_RW (PL0_R | PL0_W) | |
1102 | ||
dcbff19b GB |
1103 | /* Return the current Exception Level (as per ARMv8; note that this differs |
1104 | * from the ARMv7 Privilege Level). | |
1105 | */ | |
1106 | static inline int arm_current_el(CPUARMState *env) | |
4b6a83fb | 1107 | { |
592125f8 | 1108 | if (is_a64(env)) { |
f5a0a5a5 PM |
1109 | return extract32(env->pstate, 2, 2); |
1110 | } | |
1111 | ||
592125f8 FA |
1112 | switch (env->uncached_cpsr & 0x1f) { |
1113 | case ARM_CPU_MODE_USR: | |
4b6a83fb | 1114 | return 0; |
592125f8 FA |
1115 | case ARM_CPU_MODE_HYP: |
1116 | return 2; | |
1117 | case ARM_CPU_MODE_MON: | |
1118 | return 3; | |
1119 | default: | |
1120 | if (arm_is_secure(env) && !arm_el_is_aa64(env, 3)) { | |
1121 | /* If EL3 is 32-bit then all secure privileged modes run in | |
1122 | * EL3 | |
1123 | */ | |
1124 | return 3; | |
1125 | } | |
1126 | ||
1127 | return 1; | |
4b6a83fb | 1128 | } |
4b6a83fb PM |
1129 | } |
1130 | ||
1131 | typedef struct ARMCPRegInfo ARMCPRegInfo; | |
1132 | ||
f59df3f2 PM |
1133 | typedef enum CPAccessResult { |
1134 | /* Access is permitted */ | |
1135 | CP_ACCESS_OK = 0, | |
1136 | /* Access fails due to a configurable trap or enable which would | |
1137 | * result in a categorized exception syndrome giving information about | |
1138 | * the failing instruction (ie syndrome category 0x3, 0x4, 0x5, 0x6, | |
1139 | * 0xc or 0x18). | |
1140 | */ | |
1141 | CP_ACCESS_TRAP = 1, | |
1142 | /* Access fails and results in an exception syndrome 0x0 ("uncategorized"). | |
1143 | * Note that this is not a catch-all case -- the set of cases which may | |
1144 | * result in this failure is specifically defined by the architecture. | |
1145 | */ | |
1146 | CP_ACCESS_TRAP_UNCATEGORIZED = 2, | |
1147 | } CPAccessResult; | |
1148 | ||
c4241c7d PM |
1149 | /* Access functions for coprocessor registers. These cannot fail and |
1150 | * may not raise exceptions. | |
1151 | */ | |
1152 | typedef uint64_t CPReadFn(CPUARMState *env, const ARMCPRegInfo *opaque); | |
1153 | typedef void CPWriteFn(CPUARMState *env, const ARMCPRegInfo *opaque, | |
1154 | uint64_t value); | |
f59df3f2 PM |
1155 | /* Access permission check functions for coprocessor registers. */ |
1156 | typedef CPAccessResult CPAccessFn(CPUARMState *env, const ARMCPRegInfo *opaque); | |
4b6a83fb PM |
1157 | /* Hook function for register reset */ |
1158 | typedef void CPResetFn(CPUARMState *env, const ARMCPRegInfo *opaque); | |
1159 | ||
1160 | #define CP_ANY 0xff | |
1161 | ||
1162 | /* Definition of an ARM coprocessor register */ | |
1163 | struct ARMCPRegInfo { | |
1164 | /* Name of register (useful mainly for debugging, need not be unique) */ | |
1165 | const char *name; | |
1166 | /* Location of register: coprocessor number and (crn,crm,opc1,opc2) | |
1167 | * tuple. Any of crm, opc1 and opc2 may be CP_ANY to indicate a | |
1168 | * 'wildcard' field -- any value of that field in the MRC/MCR insn | |
1169 | * will be decoded to this register. The register read and write | |
1170 | * callbacks will be passed an ARMCPRegInfo with the crn/crm/opc1/opc2 | |
1171 | * used by the program, so it is possible to register a wildcard and | |
1172 | * then behave differently on read/write if necessary. | |
1173 | * For 64 bit registers, only crm and opc1 are relevant; crn and opc2 | |
1174 | * must both be zero. | |
f5a0a5a5 PM |
1175 | * For AArch64-visible registers, opc0 is also used. |
1176 | * Since there are no "coprocessors" in AArch64, cp is purely used as a | |
1177 | * way to distinguish (for KVM's benefit) guest-visible system registers | |
1178 | * from demuxed ones provided to preserve the "no side effects on | |
1179 | * KVM register read/write from QEMU" semantics. cp==0x13 is guest | |
1180 | * visible (to match KVM's encoding); cp==0 will be converted to | |
1181 | * cp==0x13 when the ARMCPRegInfo is registered, for convenience. | |
4b6a83fb PM |
1182 | */ |
1183 | uint8_t cp; | |
1184 | uint8_t crn; | |
1185 | uint8_t crm; | |
f5a0a5a5 | 1186 | uint8_t opc0; |
4b6a83fb PM |
1187 | uint8_t opc1; |
1188 | uint8_t opc2; | |
f5a0a5a5 PM |
1189 | /* Execution state in which this register is visible: ARM_CP_STATE_* */ |
1190 | int state; | |
4b6a83fb PM |
1191 | /* Register type: ARM_CP_* bits/values */ |
1192 | int type; | |
1193 | /* Access rights: PL*_[RW] */ | |
1194 | int access; | |
c3e30260 FA |
1195 | /* Security state: ARM_CP_SECSTATE_* bits/values */ |
1196 | int secure; | |
4b6a83fb PM |
1197 | /* The opaque pointer passed to define_arm_cp_regs_with_opaque() when |
1198 | * this register was defined: can be used to hand data through to the | |
1199 | * register read/write functions, since they are passed the ARMCPRegInfo*. | |
1200 | */ | |
1201 | void *opaque; | |
1202 | /* Value of this register, if it is ARM_CP_CONST. Otherwise, if | |
1203 | * fieldoffset is non-zero, the reset value of the register. | |
1204 | */ | |
1205 | uint64_t resetvalue; | |
c3e30260 FA |
1206 | /* Offset of the field in CPUARMState for this register. |
1207 | * | |
1208 | * This is not needed if either: | |
4b6a83fb PM |
1209 | * 1. type is ARM_CP_CONST or one of the ARM_CP_SPECIALs |
1210 | * 2. both readfn and writefn are specified | |
1211 | */ | |
1212 | ptrdiff_t fieldoffset; /* offsetof(CPUARMState, field) */ | |
c3e30260 FA |
1213 | |
1214 | /* Offsets of the secure and non-secure fields in CPUARMState for the | |
1215 | * register if it is banked. These fields are only used during the static | |
1216 | * registration of a register. During hashing the bank associated | |
1217 | * with a given security state is copied to fieldoffset which is used from | |
1218 | * there on out. | |
1219 | * | |
1220 | * It is expected that register definitions use either fieldoffset or | |
1221 | * bank_fieldoffsets in the definition but not both. It is also expected | |
1222 | * that both bank offsets are set when defining a banked register. This | |
1223 | * use indicates that a register is banked. | |
1224 | */ | |
1225 | ptrdiff_t bank_fieldoffsets[2]; | |
1226 | ||
f59df3f2 PM |
1227 | /* Function for making any access checks for this register in addition to |
1228 | * those specified by the 'access' permissions bits. If NULL, no extra | |
1229 | * checks required. The access check is performed at runtime, not at | |
1230 | * translate time. | |
1231 | */ | |
1232 | CPAccessFn *accessfn; | |
4b6a83fb PM |
1233 | /* Function for handling reads of this register. If NULL, then reads |
1234 | * will be done by loading from the offset into CPUARMState specified | |
1235 | * by fieldoffset. | |
1236 | */ | |
1237 | CPReadFn *readfn; | |
1238 | /* Function for handling writes of this register. If NULL, then writes | |
1239 | * will be done by writing to the offset into CPUARMState specified | |
1240 | * by fieldoffset. | |
1241 | */ | |
1242 | CPWriteFn *writefn; | |
7023ec7e PM |
1243 | /* Function for doing a "raw" read; used when we need to copy |
1244 | * coprocessor state to the kernel for KVM or out for | |
1245 | * migration. This only needs to be provided if there is also a | |
c4241c7d | 1246 | * readfn and it has side effects (for instance clear-on-read bits). |
7023ec7e PM |
1247 | */ |
1248 | CPReadFn *raw_readfn; | |
1249 | /* Function for doing a "raw" write; used when we need to copy KVM | |
1250 | * kernel coprocessor state into userspace, or for inbound | |
1251 | * migration. This only needs to be provided if there is also a | |
c4241c7d PM |
1252 | * writefn and it masks out "unwritable" bits or has write-one-to-clear |
1253 | * or similar behaviour. | |
7023ec7e PM |
1254 | */ |
1255 | CPWriteFn *raw_writefn; | |
4b6a83fb PM |
1256 | /* Function for resetting the register. If NULL, then reset will be done |
1257 | * by writing resetvalue to the field specified in fieldoffset. If | |
1258 | * fieldoffset is 0 then no reset will be done. | |
1259 | */ | |
1260 | CPResetFn *resetfn; | |
1261 | }; | |
1262 | ||
1263 | /* Macros which are lvalues for the field in CPUARMState for the | |
1264 | * ARMCPRegInfo *ri. | |
1265 | */ | |
1266 | #define CPREG_FIELD32(env, ri) \ | |
1267 | (*(uint32_t *)((char *)(env) + (ri)->fieldoffset)) | |
1268 | #define CPREG_FIELD64(env, ri) \ | |
1269 | (*(uint64_t *)((char *)(env) + (ri)->fieldoffset)) | |
1270 | ||
1271 | #define REGINFO_SENTINEL { .type = ARM_CP_SENTINEL } | |
1272 | ||
1273 | void define_arm_cp_regs_with_opaque(ARMCPU *cpu, | |
1274 | const ARMCPRegInfo *regs, void *opaque); | |
1275 | void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu, | |
1276 | const ARMCPRegInfo *regs, void *opaque); | |
1277 | static inline void define_arm_cp_regs(ARMCPU *cpu, const ARMCPRegInfo *regs) | |
1278 | { | |
1279 | define_arm_cp_regs_with_opaque(cpu, regs, 0); | |
1280 | } | |
1281 | static inline void define_one_arm_cp_reg(ARMCPU *cpu, const ARMCPRegInfo *regs) | |
1282 | { | |
1283 | define_one_arm_cp_reg_with_opaque(cpu, regs, 0); | |
1284 | } | |
60322b39 | 1285 | const ARMCPRegInfo *get_arm_cp_reginfo(GHashTable *cpregs, uint32_t encoded_cp); |
4b6a83fb PM |
1286 | |
1287 | /* CPWriteFn that can be used to implement writes-ignored behaviour */ | |
c4241c7d PM |
1288 | void arm_cp_write_ignore(CPUARMState *env, const ARMCPRegInfo *ri, |
1289 | uint64_t value); | |
4b6a83fb | 1290 | /* CPReadFn that can be used for read-as-zero behaviour */ |
c4241c7d | 1291 | uint64_t arm_cp_read_zero(CPUARMState *env, const ARMCPRegInfo *ri); |
4b6a83fb | 1292 | |
f5a0a5a5 PM |
1293 | /* CPResetFn that does nothing, for use if no reset is required even |
1294 | * if fieldoffset is non zero. | |
1295 | */ | |
1296 | void arm_cp_reset_ignore(CPUARMState *env, const ARMCPRegInfo *opaque); | |
1297 | ||
67ed771d PM |
1298 | /* Return true if this reginfo struct's field in the cpu state struct |
1299 | * is 64 bits wide. | |
1300 | */ | |
1301 | static inline bool cpreg_field_is_64bit(const ARMCPRegInfo *ri) | |
1302 | { | |
1303 | return (ri->state == ARM_CP_STATE_AA64) || (ri->type & ARM_CP_64BIT); | |
1304 | } | |
1305 | ||
dcbff19b | 1306 | static inline bool cp_access_ok(int current_el, |
4b6a83fb PM |
1307 | const ARMCPRegInfo *ri, int isread) |
1308 | { | |
dcbff19b | 1309 | return (ri->access >> ((current_el * 2) + isread)) & 1; |
4b6a83fb PM |
1310 | } |
1311 | ||
721fae12 PM |
1312 | /** |
1313 | * write_list_to_cpustate | |
1314 | * @cpu: ARMCPU | |
1315 | * | |
1316 | * For each register listed in the ARMCPU cpreg_indexes list, write | |
1317 | * its value from the cpreg_values list into the ARMCPUState structure. | |
1318 | * This updates TCG's working data structures from KVM data or | |
1319 | * from incoming migration state. | |
1320 | * | |
1321 | * Returns: true if all register values were updated correctly, | |
1322 | * false if some register was unknown or could not be written. | |
1323 | * Note that we do not stop early on failure -- we will attempt | |
1324 | * writing all registers in the list. | |
1325 | */ | |
1326 | bool write_list_to_cpustate(ARMCPU *cpu); | |
1327 | ||
1328 | /** | |
1329 | * write_cpustate_to_list: | |
1330 | * @cpu: ARMCPU | |
1331 | * | |
1332 | * For each register listed in the ARMCPU cpreg_indexes list, write | |
1333 | * its value from the ARMCPUState structure into the cpreg_values list. | |
1334 | * This is used to copy info from TCG's working data structures into | |
1335 | * KVM or for outbound migration. | |
1336 | * | |
1337 | * Returns: true if all register values were read correctly, | |
1338 | * false if some register was unknown or could not be read. | |
1339 | * Note that we do not stop early on failure -- we will attempt | |
1340 | * reading all registers in the list. | |
1341 | */ | |
1342 | bool write_cpustate_to_list(ARMCPU *cpu); | |
1343 | ||
9ee6e8bb PB |
1344 | /* Does the core conform to the the "MicroController" profile. e.g. Cortex-M3. |
1345 | Note the M in older cores (eg. ARM7TDMI) stands for Multiply. These are | |
1346 | conventional cores (ie. Application or Realtime profile). */ | |
1347 | ||
1348 | #define IS_M(env) arm_feature(env, ARM_FEATURE_M) | |
9ee6e8bb | 1349 | |
9ee6e8bb PB |
1350 | #define ARM_CPUID_TI915T 0x54029152 |
1351 | #define ARM_CPUID_TI925T 0x54029252 | |
40f137e1 | 1352 | |
b5ff1b31 | 1353 | #if defined(CONFIG_USER_ONLY) |
2c0262af | 1354 | #define TARGET_PAGE_BITS 12 |
b5ff1b31 FB |
1355 | #else |
1356 | /* The ARM MMU allows 1k pages. */ | |
1357 | /* ??? Linux doesn't actually use these, and they're deprecated in recent | |
82d17978 | 1358 | architecture revisions. Maybe a configure option to disable them. */ |
b5ff1b31 FB |
1359 | #define TARGET_PAGE_BITS 10 |
1360 | #endif | |
9467d44c | 1361 | |
3926cc84 AG |
1362 | #if defined(TARGET_AARCH64) |
1363 | # define TARGET_PHYS_ADDR_SPACE_BITS 48 | |
1364 | # define TARGET_VIRT_ADDR_SPACE_BITS 64 | |
1365 | #else | |
1366 | # define TARGET_PHYS_ADDR_SPACE_BITS 40 | |
1367 | # define TARGET_VIRT_ADDR_SPACE_BITS 32 | |
1368 | #endif | |
52705890 | 1369 | |
043b7f8d EI |
1370 | static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx) |
1371 | { | |
1372 | CPUARMState *env = cs->env_ptr; | |
dcbff19b | 1373 | unsigned int cur_el = arm_current_el(env); |
dfafd090 | 1374 | unsigned int target_el = arm_excp_target_el(cs, excp_idx); |
57e3a0c7 GB |
1375 | bool secure = arm_is_secure(env); |
1376 | uint32_t scr; | |
1377 | uint32_t hcr; | |
1378 | bool pstate_unmasked; | |
1379 | int8_t unmasked = 0; | |
1380 | ||
1381 | /* Don't take exceptions if they target a lower EL. | |
1382 | * This check should catch any exceptions that would not be taken but left | |
1383 | * pending. | |
1384 | */ | |
dfafd090 EI |
1385 | if (cur_el > target_el) { |
1386 | return false; | |
1387 | } | |
043b7f8d EI |
1388 | |
1389 | switch (excp_idx) { | |
1390 | case EXCP_FIQ: | |
57e3a0c7 GB |
1391 | /* If FIQs are routed to EL3 or EL2 then there are cases where we |
1392 | * override the CPSR.F in determining if the exception is masked or | |
1393 | * not. If neither of these are set then we fall back to the CPSR.F | |
1394 | * setting otherwise we further assess the state below. | |
1395 | */ | |
1396 | hcr = (env->cp15.hcr_el2 & HCR_FMO); | |
1397 | scr = (env->cp15.scr_el3 & SCR_FIQ); | |
1398 | ||
1399 | /* When EL3 is 32-bit, the SCR.FW bit controls whether the CPSR.F bit | |
1400 | * masks FIQ interrupts when taken in non-secure state. If SCR.FW is | |
1401 | * set then FIQs can be masked by CPSR.F when non-secure but only | |
1402 | * when FIQs are only routed to EL3. | |
1403 | */ | |
1404 | scr &= !((env->cp15.scr_el3 & SCR_FW) && !hcr); | |
1405 | pstate_unmasked = !(env->daif & PSTATE_F); | |
1406 | break; | |
1407 | ||
043b7f8d | 1408 | case EXCP_IRQ: |
57e3a0c7 GB |
1409 | /* When EL3 execution state is 32-bit, if HCR.IMO is set then we may |
1410 | * override the CPSR.I masking when in non-secure state. The SCR.IRQ | |
1411 | * setting has already been taken into consideration when setting the | |
1412 | * target EL, so it does not have a further affect here. | |
1413 | */ | |
1414 | hcr = (env->cp15.hcr_el2 & HCR_IMO); | |
1415 | scr = false; | |
1416 | pstate_unmasked = !(env->daif & PSTATE_I); | |
1417 | break; | |
1418 | ||
136e67e9 | 1419 | case EXCP_VFIQ: |
9fae24f5 | 1420 | if (secure || !(env->cp15.hcr_el2 & HCR_FMO)) { |
136e67e9 EI |
1421 | /* VFIQs are only taken when hypervized and non-secure. */ |
1422 | return false; | |
1423 | } | |
1424 | return !(env->daif & PSTATE_F); | |
1425 | case EXCP_VIRQ: | |
9fae24f5 | 1426 | if (secure || !(env->cp15.hcr_el2 & HCR_IMO)) { |
136e67e9 EI |
1427 | /* VIRQs are only taken when hypervized and non-secure. */ |
1428 | return false; | |
1429 | } | |
b5c633c5 | 1430 | return !(env->daif & PSTATE_I); |
043b7f8d EI |
1431 | default: |
1432 | g_assert_not_reached(); | |
1433 | } | |
57e3a0c7 GB |
1434 | |
1435 | /* Use the target EL, current execution state and SCR/HCR settings to | |
1436 | * determine whether the corresponding CPSR bit is used to mask the | |
1437 | * interrupt. | |
1438 | */ | |
1439 | if ((target_el > cur_el) && (target_el != 1)) { | |
1440 | if (arm_el_is_aa64(env, 3) || ((scr || hcr) && (!secure))) { | |
1441 | unmasked = 1; | |
1442 | } | |
1443 | } | |
1444 | ||
1445 | /* The PSTATE bits only mask the interrupt if we have not overriden the | |
1446 | * ability above. | |
1447 | */ | |
1448 | return unmasked || pstate_unmasked; | |
043b7f8d EI |
1449 | } |
1450 | ||
ad37ad5b PM |
1451 | static inline CPUARMState *cpu_init(const char *cpu_model) |
1452 | { | |
1453 | ARMCPU *cpu = cpu_arm_init(cpu_model); | |
1454 | if (cpu) { | |
1455 | return &cpu->env; | |
1456 | } | |
1457 | return NULL; | |
1458 | } | |
1459 | ||
9467d44c TS |
1460 | #define cpu_exec cpu_arm_exec |
1461 | #define cpu_gen_code cpu_arm_gen_code | |
1462 | #define cpu_signal_handler cpu_arm_signal_handler | |
c732abe2 | 1463 | #define cpu_list arm_cpu_list |
9467d44c | 1464 | |
6ebbf390 | 1465 | /* MMU modes definitions */ |
f79fbf39 EI |
1466 | #define MMU_MODE0_SUFFIX _user |
1467 | #define MMU_MODE1_SUFFIX _kernel | |
1468 | #define MMU_USER_IDX 0 | |
0ecb72a5 | 1469 | static inline int cpu_mmu_index (CPUARMState *env) |
6ebbf390 | 1470 | { |
dcbff19b | 1471 | return arm_current_el(env); |
6ebbf390 JM |
1472 | } |
1473 | ||
3a298203 PM |
1474 | /* Return the Exception Level targeted by debug exceptions; |
1475 | * currently always EL1 since we don't implement EL2 or EL3. | |
1476 | */ | |
1477 | static inline int arm_debug_target_el(CPUARMState *env) | |
1478 | { | |
1479 | return 1; | |
1480 | } | |
1481 | ||
1482 | static inline bool aa64_generate_debug_exceptions(CPUARMState *env) | |
1483 | { | |
dcbff19b | 1484 | if (arm_current_el(env) == arm_debug_target_el(env)) { |
3a298203 PM |
1485 | if ((extract32(env->cp15.mdscr_el1, 13, 1) == 0) |
1486 | || (env->daif & PSTATE_D)) { | |
1487 | return false; | |
1488 | } | |
1489 | } | |
1490 | return true; | |
1491 | } | |
1492 | ||
1493 | static inline bool aa32_generate_debug_exceptions(CPUARMState *env) | |
1494 | { | |
dcbff19b | 1495 | if (arm_current_el(env) == 0 && arm_el_is_aa64(env, 1)) { |
3a298203 PM |
1496 | return aa64_generate_debug_exceptions(env); |
1497 | } | |
dcbff19b | 1498 | return arm_current_el(env) != 2; |
3a298203 PM |
1499 | } |
1500 | ||
1501 | /* Return true if debugging exceptions are currently enabled. | |
1502 | * This corresponds to what in ARM ARM pseudocode would be | |
1503 | * if UsingAArch32() then | |
1504 | * return AArch32.GenerateDebugExceptions() | |
1505 | * else | |
1506 | * return AArch64.GenerateDebugExceptions() | |
1507 | * We choose to push the if() down into this function for clarity, | |
1508 | * since the pseudocode has it at all callsites except for the one in | |
1509 | * CheckSoftwareStep(), where it is elided because both branches would | |
1510 | * always return the same value. | |
1511 | * | |
1512 | * Parts of the pseudocode relating to EL2 and EL3 are omitted because we | |
1513 | * don't yet implement those exception levels or their associated trap bits. | |
1514 | */ | |
1515 | static inline bool arm_generate_debug_exceptions(CPUARMState *env) | |
1516 | { | |
1517 | if (env->aarch64) { | |
1518 | return aa64_generate_debug_exceptions(env); | |
1519 | } else { | |
1520 | return aa32_generate_debug_exceptions(env); | |
1521 | } | |
1522 | } | |
1523 | ||
1524 | /* Is single-stepping active? (Note that the "is EL_D AArch64?" check | |
1525 | * implicitly means this always returns false in pre-v8 CPUs.) | |
1526 | */ | |
1527 | static inline bool arm_singlestep_active(CPUARMState *env) | |
1528 | { | |
1529 | return extract32(env->cp15.mdscr_el1, 0, 1) | |
1530 | && arm_el_is_aa64(env, arm_debug_target_el(env)) | |
1531 | && arm_generate_debug_exceptions(env); | |
1532 | } | |
1533 | ||
022c62cb | 1534 | #include "exec/cpu-all.h" |
622ed360 | 1535 | |
3926cc84 AG |
1536 | /* Bit usage in the TB flags field: bit 31 indicates whether we are |
1537 | * in 32 or 64 bit mode. The meaning of the other bits depends on that. | |
1538 | */ | |
1539 | #define ARM_TBFLAG_AARCH64_STATE_SHIFT 31 | |
1540 | #define ARM_TBFLAG_AARCH64_STATE_MASK (1U << ARM_TBFLAG_AARCH64_STATE_SHIFT) | |
1541 | ||
1542 | /* Bit usage when in AArch32 state: */ | |
a1705768 PM |
1543 | #define ARM_TBFLAG_THUMB_SHIFT 0 |
1544 | #define ARM_TBFLAG_THUMB_MASK (1 << ARM_TBFLAG_THUMB_SHIFT) | |
1545 | #define ARM_TBFLAG_VECLEN_SHIFT 1 | |
1546 | #define ARM_TBFLAG_VECLEN_MASK (0x7 << ARM_TBFLAG_VECLEN_SHIFT) | |
1547 | #define ARM_TBFLAG_VECSTRIDE_SHIFT 4 | |
1548 | #define ARM_TBFLAG_VECSTRIDE_MASK (0x3 << ARM_TBFLAG_VECSTRIDE_SHIFT) | |
1549 | #define ARM_TBFLAG_PRIV_SHIFT 6 | |
1550 | #define ARM_TBFLAG_PRIV_MASK (1 << ARM_TBFLAG_PRIV_SHIFT) | |
1551 | #define ARM_TBFLAG_VFPEN_SHIFT 7 | |
1552 | #define ARM_TBFLAG_VFPEN_MASK (1 << ARM_TBFLAG_VFPEN_SHIFT) | |
1553 | #define ARM_TBFLAG_CONDEXEC_SHIFT 8 | |
1554 | #define ARM_TBFLAG_CONDEXEC_MASK (0xff << ARM_TBFLAG_CONDEXEC_SHIFT) | |
d8fd2954 PB |
1555 | #define ARM_TBFLAG_BSWAP_CODE_SHIFT 16 |
1556 | #define ARM_TBFLAG_BSWAP_CODE_MASK (1 << ARM_TBFLAG_BSWAP_CODE_SHIFT) | |
2c7ffc41 PM |
1557 | #define ARM_TBFLAG_CPACR_FPEN_SHIFT 17 |
1558 | #define ARM_TBFLAG_CPACR_FPEN_MASK (1 << ARM_TBFLAG_CPACR_FPEN_SHIFT) | |
50225ad0 PM |
1559 | #define ARM_TBFLAG_SS_ACTIVE_SHIFT 18 |
1560 | #define ARM_TBFLAG_SS_ACTIVE_MASK (1 << ARM_TBFLAG_SS_ACTIVE_SHIFT) | |
1561 | #define ARM_TBFLAG_PSTATE_SS_SHIFT 19 | |
1562 | #define ARM_TBFLAG_PSTATE_SS_MASK (1 << ARM_TBFLAG_PSTATE_SS_SHIFT) | |
c0f4af17 PM |
1563 | /* We store the bottom two bits of the CPAR as TB flags and handle |
1564 | * checks on the other bits at runtime | |
1565 | */ | |
1566 | #define ARM_TBFLAG_XSCALE_CPAR_SHIFT 20 | |
1567 | #define ARM_TBFLAG_XSCALE_CPAR_MASK (3 << ARM_TBFLAG_XSCALE_CPAR_SHIFT) | |
3f342b9e SF |
1568 | /* Indicates whether cp register reads and writes by guest code should access |
1569 | * the secure or nonsecure bank of banked registers; note that this is not | |
1570 | * the same thing as the current security state of the processor! | |
1571 | */ | |
1572 | #define ARM_TBFLAG_NS_SHIFT 22 | |
1573 | #define ARM_TBFLAG_NS_MASK (1 << ARM_TBFLAG_NS_SHIFT) | |
3926cc84 | 1574 | |
d9ea7d29 PM |
1575 | /* Bit usage when in AArch64 state */ |
1576 | #define ARM_TBFLAG_AA64_EL_SHIFT 0 | |
1577 | #define ARM_TBFLAG_AA64_EL_MASK (0x3 << ARM_TBFLAG_AA64_EL_SHIFT) | |
8c6afa6a PM |
1578 | #define ARM_TBFLAG_AA64_FPEN_SHIFT 2 |
1579 | #define ARM_TBFLAG_AA64_FPEN_MASK (1 << ARM_TBFLAG_AA64_FPEN_SHIFT) | |
7ea47fe7 PM |
1580 | #define ARM_TBFLAG_AA64_SS_ACTIVE_SHIFT 3 |
1581 | #define ARM_TBFLAG_AA64_SS_ACTIVE_MASK (1 << ARM_TBFLAG_AA64_SS_ACTIVE_SHIFT) | |
1582 | #define ARM_TBFLAG_AA64_PSTATE_SS_SHIFT 4 | |
1583 | #define ARM_TBFLAG_AA64_PSTATE_SS_MASK (1 << ARM_TBFLAG_AA64_PSTATE_SS_SHIFT) | |
a1705768 PM |
1584 | |
1585 | /* some convenience accessor macros */ | |
3926cc84 AG |
1586 | #define ARM_TBFLAG_AARCH64_STATE(F) \ |
1587 | (((F) & ARM_TBFLAG_AARCH64_STATE_MASK) >> ARM_TBFLAG_AARCH64_STATE_SHIFT) | |
a1705768 PM |
1588 | #define ARM_TBFLAG_THUMB(F) \ |
1589 | (((F) & ARM_TBFLAG_THUMB_MASK) >> ARM_TBFLAG_THUMB_SHIFT) | |
1590 | #define ARM_TBFLAG_VECLEN(F) \ | |
1591 | (((F) & ARM_TBFLAG_VECLEN_MASK) >> ARM_TBFLAG_VECLEN_SHIFT) | |
1592 | #define ARM_TBFLAG_VECSTRIDE(F) \ | |
1593 | (((F) & ARM_TBFLAG_VECSTRIDE_MASK) >> ARM_TBFLAG_VECSTRIDE_SHIFT) | |
1594 | #define ARM_TBFLAG_PRIV(F) \ | |
1595 | (((F) & ARM_TBFLAG_PRIV_MASK) >> ARM_TBFLAG_PRIV_SHIFT) | |
1596 | #define ARM_TBFLAG_VFPEN(F) \ | |
1597 | (((F) & ARM_TBFLAG_VFPEN_MASK) >> ARM_TBFLAG_VFPEN_SHIFT) | |
1598 | #define ARM_TBFLAG_CONDEXEC(F) \ | |
1599 | (((F) & ARM_TBFLAG_CONDEXEC_MASK) >> ARM_TBFLAG_CONDEXEC_SHIFT) | |
d8fd2954 PB |
1600 | #define ARM_TBFLAG_BSWAP_CODE(F) \ |
1601 | (((F) & ARM_TBFLAG_BSWAP_CODE_MASK) >> ARM_TBFLAG_BSWAP_CODE_SHIFT) | |
2c7ffc41 PM |
1602 | #define ARM_TBFLAG_CPACR_FPEN(F) \ |
1603 | (((F) & ARM_TBFLAG_CPACR_FPEN_MASK) >> ARM_TBFLAG_CPACR_FPEN_SHIFT) | |
50225ad0 PM |
1604 | #define ARM_TBFLAG_SS_ACTIVE(F) \ |
1605 | (((F) & ARM_TBFLAG_SS_ACTIVE_MASK) >> ARM_TBFLAG_SS_ACTIVE_SHIFT) | |
1606 | #define ARM_TBFLAG_PSTATE_SS(F) \ | |
1607 | (((F) & ARM_TBFLAG_PSTATE_SS_MASK) >> ARM_TBFLAG_PSTATE_SS_SHIFT) | |
c0f4af17 PM |
1608 | #define ARM_TBFLAG_XSCALE_CPAR(F) \ |
1609 | (((F) & ARM_TBFLAG_XSCALE_CPAR_MASK) >> ARM_TBFLAG_XSCALE_CPAR_SHIFT) | |
d9ea7d29 PM |
1610 | #define ARM_TBFLAG_AA64_EL(F) \ |
1611 | (((F) & ARM_TBFLAG_AA64_EL_MASK) >> ARM_TBFLAG_AA64_EL_SHIFT) | |
8c6afa6a PM |
1612 | #define ARM_TBFLAG_AA64_FPEN(F) \ |
1613 | (((F) & ARM_TBFLAG_AA64_FPEN_MASK) >> ARM_TBFLAG_AA64_FPEN_SHIFT) | |
7ea47fe7 PM |
1614 | #define ARM_TBFLAG_AA64_SS_ACTIVE(F) \ |
1615 | (((F) & ARM_TBFLAG_AA64_SS_ACTIVE_MASK) >> ARM_TBFLAG_AA64_SS_ACTIVE_SHIFT) | |
1616 | #define ARM_TBFLAG_AA64_PSTATE_SS(F) \ | |
1617 | (((F) & ARM_TBFLAG_AA64_PSTATE_SS_MASK) >> ARM_TBFLAG_AA64_PSTATE_SS_SHIFT) | |
3f342b9e SF |
1618 | #define ARM_TBFLAG_NS(F) \ |
1619 | (((F) & ARM_TBFLAG_NS_MASK) >> ARM_TBFLAG_NS_SHIFT) | |
a1705768 | 1620 | |
0ecb72a5 | 1621 | static inline void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, |
6b917547 AL |
1622 | target_ulong *cs_base, int *flags) |
1623 | { | |
ed1f13d6 PM |
1624 | int fpen; |
1625 | ||
1626 | if (arm_feature(env, ARM_FEATURE_V6)) { | |
1627 | fpen = extract32(env->cp15.c1_coproc, 20, 2); | |
1628 | } else { | |
1629 | /* CPACR doesn't exist before v6, so VFP is always accessible */ | |
1630 | fpen = 3; | |
1631 | } | |
8c6afa6a | 1632 | |
3926cc84 AG |
1633 | if (is_a64(env)) { |
1634 | *pc = env->pc; | |
d9ea7d29 | 1635 | *flags = ARM_TBFLAG_AARCH64_STATE_MASK |
dcbff19b GB |
1636 | | (arm_current_el(env) << ARM_TBFLAG_AA64_EL_SHIFT); |
1637 | if (fpen == 3 || (fpen == 1 && arm_current_el(env) != 0)) { | |
8c6afa6a PM |
1638 | *flags |= ARM_TBFLAG_AA64_FPEN_MASK; |
1639 | } | |
7ea47fe7 PM |
1640 | /* The SS_ACTIVE and PSTATE_SS bits correspond to the state machine |
1641 | * states defined in the ARM ARM for software singlestep: | |
1642 | * SS_ACTIVE PSTATE.SS State | |
1643 | * 0 x Inactive (the TB flag for SS is always 0) | |
1644 | * 1 0 Active-pending | |
1645 | * 1 1 Active-not-pending | |
1646 | */ | |
1647 | if (arm_singlestep_active(env)) { | |
1648 | *flags |= ARM_TBFLAG_AA64_SS_ACTIVE_MASK; | |
1649 | if (env->pstate & PSTATE_SS) { | |
1650 | *flags |= ARM_TBFLAG_AA64_PSTATE_SS_MASK; | |
1651 | } | |
1652 | } | |
05ed9a99 | 1653 | } else { |
3926cc84 AG |
1654 | int privmode; |
1655 | *pc = env->regs[15]; | |
1656 | *flags = (env->thumb << ARM_TBFLAG_THUMB_SHIFT) | |
1657 | | (env->vfp.vec_len << ARM_TBFLAG_VECLEN_SHIFT) | |
1658 | | (env->vfp.vec_stride << ARM_TBFLAG_VECSTRIDE_SHIFT) | |
1659 | | (env->condexec_bits << ARM_TBFLAG_CONDEXEC_SHIFT) | |
1660 | | (env->bswap_code << ARM_TBFLAG_BSWAP_CODE_SHIFT); | |
1661 | if (arm_feature(env, ARM_FEATURE_M)) { | |
1662 | privmode = !((env->v7m.exception == 0) && (env->v7m.control & 1)); | |
1663 | } else { | |
1664 | privmode = (env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR; | |
1665 | } | |
1666 | if (privmode) { | |
1667 | *flags |= ARM_TBFLAG_PRIV_MASK; | |
1668 | } | |
3f342b9e SF |
1669 | if (!(access_secure_reg(env))) { |
1670 | *flags |= ARM_TBFLAG_NS_MASK; | |
1671 | } | |
2c7ffc41 PM |
1672 | if (env->vfp.xregs[ARM_VFP_FPEXC] & (1 << 30) |
1673 | || arm_el_is_aa64(env, 1)) { | |
3926cc84 AG |
1674 | *flags |= ARM_TBFLAG_VFPEN_MASK; |
1675 | } | |
dcbff19b | 1676 | if (fpen == 3 || (fpen == 1 && arm_current_el(env) != 0)) { |
2c7ffc41 PM |
1677 | *flags |= ARM_TBFLAG_CPACR_FPEN_MASK; |
1678 | } | |
50225ad0 PM |
1679 | /* The SS_ACTIVE and PSTATE_SS bits correspond to the state machine |
1680 | * states defined in the ARM ARM for software singlestep: | |
1681 | * SS_ACTIVE PSTATE.SS State | |
1682 | * 0 x Inactive (the TB flag for SS is always 0) | |
1683 | * 1 0 Active-pending | |
1684 | * 1 1 Active-not-pending | |
1685 | */ | |
1686 | if (arm_singlestep_active(env)) { | |
1687 | *flags |= ARM_TBFLAG_SS_ACTIVE_MASK; | |
1688 | if (env->uncached_cpsr & PSTATE_SS) { | |
1689 | *flags |= ARM_TBFLAG_PSTATE_SS_MASK; | |
1690 | } | |
1691 | } | |
c0f4af17 PM |
1692 | *flags |= (extract32(env->cp15.c15_cpar, 0, 2) |
1693 | << ARM_TBFLAG_XSCALE_CPAR_SHIFT); | |
a1705768 | 1694 | } |
3926cc84 AG |
1695 | |
1696 | *cs_base = 0; | |
6b917547 AL |
1697 | } |
1698 | ||
022c62cb | 1699 | #include "exec/exec-all.h" |
f081c76c | 1700 | |
3926cc84 AG |
1701 | static inline void cpu_pc_from_tb(CPUARMState *env, TranslationBlock *tb) |
1702 | { | |
1703 | if (ARM_TBFLAG_AARCH64_STATE(tb->flags)) { | |
1704 | env->pc = tb->pc; | |
1705 | } else { | |
1706 | env->regs[15] = tb->pc; | |
1707 | } | |
1708 | } | |
1709 | ||
98128601 RH |
1710 | enum { |
1711 | QEMU_PSCI_CONDUIT_DISABLED = 0, | |
1712 | QEMU_PSCI_CONDUIT_SMC = 1, | |
1713 | QEMU_PSCI_CONDUIT_HVC = 2, | |
1714 | }; | |
1715 | ||
2c0262af | 1716 | #endif |