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2c0262af FB |
1 | /* |
2 | * ARM virtual CPU header | |
5fafdf24 | 3 | * |
2c0262af FB |
4 | * Copyright (c) 2003 Fabrice Bellard |
5 | * | |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
9 | * version 2 of the License, or (at your option) any later version. | |
10 | * | |
11 | * This library is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU Lesser General Public | |
8167ee88 | 17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. |
2c0262af FB |
18 | */ |
19 | #ifndef CPU_ARM_H | |
20 | #define CPU_ARM_H | |
21 | ||
3926cc84 | 22 | #include "config.h" |
3cf1e035 | 23 | |
72b0cd35 PM |
24 | #include "kvm-consts.h" |
25 | ||
3926cc84 AG |
26 | #if defined(TARGET_AARCH64) |
27 | /* AArch64 definitions */ | |
28 | # define TARGET_LONG_BITS 64 | |
29 | # define ELF_MACHINE EM_AARCH64 | |
30 | #else | |
31 | # define TARGET_LONG_BITS 32 | |
32 | # define ELF_MACHINE EM_ARM | |
33 | #endif | |
9042c0e2 | 34 | |
9349b4f9 | 35 | #define CPUArchState struct CPUARMState |
c2764719 | 36 | |
9a78eead | 37 | #include "qemu-common.h" |
022c62cb | 38 | #include "exec/cpu-defs.h" |
2c0262af | 39 | |
6b4c305c | 40 | #include "fpu/softfloat.h" |
53cd6637 | 41 | |
1fddef4b FB |
42 | #define TARGET_HAS_ICE 1 |
43 | ||
b8a9e8f1 FB |
44 | #define EXCP_UDEF 1 /* undefined instruction */ |
45 | #define EXCP_SWI 2 /* software interrupt */ | |
46 | #define EXCP_PREFETCH_ABORT 3 | |
47 | #define EXCP_DATA_ABORT 4 | |
b5ff1b31 FB |
48 | #define EXCP_IRQ 5 |
49 | #define EXCP_FIQ 6 | |
06c949e6 | 50 | #define EXCP_BKPT 7 |
9ee6e8bb | 51 | #define EXCP_EXCEPTION_EXIT 8 /* Return from v7M exception. */ |
fbb4a2e3 | 52 | #define EXCP_KERNEL_TRAP 9 /* Jumped to kernel code page. */ |
426f5abc | 53 | #define EXCP_STREX 10 |
9ee6e8bb PB |
54 | |
55 | #define ARMV7M_EXCP_RESET 1 | |
56 | #define ARMV7M_EXCP_NMI 2 | |
57 | #define ARMV7M_EXCP_HARD 3 | |
58 | #define ARMV7M_EXCP_MEM 4 | |
59 | #define ARMV7M_EXCP_BUS 5 | |
60 | #define ARMV7M_EXCP_USAGE 6 | |
61 | #define ARMV7M_EXCP_SVC 11 | |
62 | #define ARMV7M_EXCP_DEBUG 12 | |
63 | #define ARMV7M_EXCP_PENDSV 14 | |
64 | #define ARMV7M_EXCP_SYSTICK 15 | |
2c0262af | 65 | |
403946c0 RH |
66 | /* ARM-specific interrupt pending bits. */ |
67 | #define CPU_INTERRUPT_FIQ CPU_INTERRUPT_TGT_EXT_1 | |
68 | ||
e4fe830b PM |
69 | /* The usual mapping for an AArch64 system register to its AArch32 |
70 | * counterpart is for the 32 bit world to have access to the lower | |
71 | * half only (with writes leaving the upper half untouched). It's | |
72 | * therefore useful to be able to pass TCG the offset of the least | |
73 | * significant half of a uint64_t struct member. | |
74 | */ | |
75 | #ifdef HOST_WORDS_BIGENDIAN | |
5cd8a118 | 76 | #define offsetoflow32(S, M) (offsetof(S, M) + sizeof(uint32_t)) |
e4fe830b PM |
77 | #else |
78 | #define offsetoflow32(S, M) offsetof(S, M) | |
79 | #endif | |
80 | ||
7c1840b6 PM |
81 | /* Meanings of the ARMCPU object's two inbound GPIO lines */ |
82 | #define ARM_CPU_IRQ 0 | |
83 | #define ARM_CPU_FIQ 1 | |
403946c0 | 84 | |
c1713132 AZ |
85 | typedef void ARMWriteCPFunc(void *opaque, int cp_info, |
86 | int srcreg, int operand, uint32_t value); | |
87 | typedef uint32_t ARMReadCPFunc(void *opaque, int cp_info, | |
88 | int dstreg, int operand); | |
89 | ||
f93eb9ff AZ |
90 | struct arm_boot_info; |
91 | ||
6ebbf390 JM |
92 | #define NB_MMU_MODES 2 |
93 | ||
b7bcbe95 FB |
94 | /* We currently assume float and double are IEEE single and double |
95 | precision respectively. | |
96 | Doing runtime conversions is tricky because VFP registers may contain | |
97 | integer values (eg. as the result of a FTOSI instruction). | |
8e96005d FB |
98 | s<2n> maps to the least significant half of d<n> |
99 | s<2n+1> maps to the most significant half of d<n> | |
100 | */ | |
b7bcbe95 | 101 | |
55d284af PM |
102 | /* CPU state for each instance of a generic timer (in cp15 c14) */ |
103 | typedef struct ARMGenericTimer { | |
104 | uint64_t cval; /* Timer CompareValue register */ | |
105 | uint32_t ctl; /* Timer Control register */ | |
106 | } ARMGenericTimer; | |
107 | ||
108 | #define GTIMER_PHYS 0 | |
109 | #define GTIMER_VIRT 1 | |
110 | #define NUM_GTIMERS 2 | |
111 | ||
112 | /* Scale factor for generic timers, ie number of ns per tick. | |
113 | * This gives a 62.5MHz timer. | |
114 | */ | |
115 | #define GTIMER_SCALE 16 | |
116 | ||
2c0262af | 117 | typedef struct CPUARMState { |
b5ff1b31 | 118 | /* Regs for current mode. */ |
2c0262af | 119 | uint32_t regs[16]; |
3926cc84 AG |
120 | |
121 | /* 32/64 switch only happens when taking and returning from | |
122 | * exceptions so the overlap semantics are taken care of then | |
123 | * instead of having a complicated union. | |
124 | */ | |
125 | /* Regs for A64 mode. */ | |
126 | uint64_t xregs[32]; | |
127 | uint64_t pc; | |
d356312f PM |
128 | /* PSTATE isn't an architectural register for ARMv8. However, it is |
129 | * convenient for us to assemble the underlying state into a 32 bit format | |
130 | * identical to the architectural format used for the SPSR. (This is also | |
131 | * what the Linux kernel's 'pstate' field in signal handlers and KVM's | |
132 | * 'pstate' register are.) Of the PSTATE bits: | |
133 | * NZCV are kept in the split out env->CF/VF/NF/ZF, (which have the same | |
134 | * semantics as for AArch32, as described in the comments on each field) | |
135 | * nRW (also known as M[4]) is kept, inverted, in env->aarch64 | |
136 | * all other bits are stored in their correct places in env->pstate | |
3926cc84 AG |
137 | */ |
138 | uint32_t pstate; | |
139 | uint32_t aarch64; /* 1 if CPU is in aarch64 state; inverse of PSTATE.nRW */ | |
140 | ||
b90372ad | 141 | /* Frequently accessed CPSR bits are stored separately for efficiency. |
d37aca66 | 142 | This contains all the other bits. Use cpsr_{read,write} to access |
b5ff1b31 FB |
143 | the whole CPSR. */ |
144 | uint32_t uncached_cpsr; | |
145 | uint32_t spsr; | |
146 | ||
147 | /* Banked registers. */ | |
148 | uint32_t banked_spsr[6]; | |
149 | uint32_t banked_r13[6]; | |
150 | uint32_t banked_r14[6]; | |
3b46e624 | 151 | |
b5ff1b31 FB |
152 | /* These hold r8-r12. */ |
153 | uint32_t usr_regs[5]; | |
154 | uint32_t fiq_regs[5]; | |
3b46e624 | 155 | |
2c0262af FB |
156 | /* cpsr flag cache for faster execution */ |
157 | uint32_t CF; /* 0 or 1 */ | |
158 | uint32_t VF; /* V is the bit 31. All other bits are undefined */ | |
6fbe23d5 PB |
159 | uint32_t NF; /* N is bit 31. All other bits are undefined. */ |
160 | uint32_t ZF; /* Z set if zero. */ | |
99c475ab | 161 | uint32_t QF; /* 0 or 1 */ |
9ee6e8bb | 162 | uint32_t GE; /* cpsr[19:16] */ |
b26eefb6 | 163 | uint32_t thumb; /* cpsr[5]. 0 = arm mode, 1 = thumb mode. */ |
9ee6e8bb | 164 | uint32_t condexec_bits; /* IT bits. cpsr[15:10,26:25]. */ |
2c0262af | 165 | |
b5ff1b31 FB |
166 | /* System control coprocessor (cp15) */ |
167 | struct { | |
40f137e1 | 168 | uint32_t c0_cpuid; |
a49ea279 | 169 | uint32_t c0_cssel; /* Cache size selection. */ |
b5ff1b31 FB |
170 | uint32_t c1_sys; /* System control register. */ |
171 | uint32_t c1_coproc; /* Coprocessor access register. */ | |
610c3c8a | 172 | uint32_t c1_xscaleauxcr; /* XScale auxiliary control register. */ |
2be27624 | 173 | uint32_t c1_scr; /* secure config register. */ |
9ee6e8bb | 174 | uint32_t c2_base0; /* MMU translation table base 0. */ |
891a2fe7 PM |
175 | uint32_t c2_base0_hi; /* MMU translation table base 0, high 32 bits */ |
176 | uint32_t c2_base1; /* MMU translation table base 0. */ | |
177 | uint32_t c2_base1_hi; /* MMU translation table base 1, high 32 bits */ | |
b2fa1797 PB |
178 | uint32_t c2_control; /* MMU translation table base control. */ |
179 | uint32_t c2_mask; /* MMU translation table base selection mask. */ | |
180 | uint32_t c2_base_mask; /* MMU translation table base 0 mask. */ | |
ce819861 PB |
181 | uint32_t c2_data; /* MPU data cachable bits. */ |
182 | uint32_t c2_insn; /* MPU instruction cachable bits. */ | |
183 | uint32_t c3; /* MMU domain access control register | |
184 | MPU write buffer control. */ | |
b5ff1b31 FB |
185 | uint32_t c5_insn; /* Fault status registers. */ |
186 | uint32_t c5_data; | |
ce819861 | 187 | uint32_t c6_region[8]; /* MPU base/size registers. */ |
b5ff1b31 FB |
188 | uint32_t c6_insn; /* Fault address registers. */ |
189 | uint32_t c6_data; | |
f8bf8606 | 190 | uint32_t c7_par; /* Translation result. */ |
891a2fe7 | 191 | uint32_t c7_par_hi; /* Translation result, high 32 bits */ |
b5ff1b31 FB |
192 | uint32_t c9_insn; /* Cache lockdown registers. */ |
193 | uint32_t c9_data; | |
74594c9d PM |
194 | uint32_t c9_pmcr; /* performance monitor control register */ |
195 | uint32_t c9_pmcnten; /* perf monitor counter enables */ | |
196 | uint32_t c9_pmovsr; /* perf monitor overflow status */ | |
197 | uint32_t c9_pmxevtyper; /* perf monitor event type */ | |
198 | uint32_t c9_pmuserenr; /* perf monitor user enable */ | |
199 | uint32_t c9_pminten; /* perf monitor interrupt enables */ | |
8641136c | 200 | uint32_t c12_vbar; /* vector base address register */ |
b5ff1b31 FB |
201 | uint32_t c13_fcse; /* FCSE PID. */ |
202 | uint32_t c13_context; /* Context ID. */ | |
e4fe830b PM |
203 | uint64_t tpidr_el0; /* User RW Thread register. */ |
204 | uint64_t tpidrro_el0; /* User RO Thread register. */ | |
205 | uint64_t tpidr_el1; /* Privileged Thread register. */ | |
55d284af PM |
206 | uint32_t c14_cntfrq; /* Counter Frequency register */ |
207 | uint32_t c14_cntkctl; /* Timer Control register */ | |
208 | ARMGenericTimer c14_timer[NUM_GTIMERS]; | |
c1713132 | 209 | uint32_t c15_cpar; /* XScale Coprocessor Access Register */ |
c3d2689d AZ |
210 | uint32_t c15_ticonfig; /* TI925T configuration byte. */ |
211 | uint32_t c15_i_max; /* Maximum D-cache dirty line index. */ | |
212 | uint32_t c15_i_min; /* Minimum D-cache dirty line index. */ | |
213 | uint32_t c15_threadid; /* TI debugger thread-ID. */ | |
7da362d0 ML |
214 | uint32_t c15_config_base_address; /* SCU base address. */ |
215 | uint32_t c15_diagnostic; /* diagnostic register */ | |
216 | uint32_t c15_power_diagnostic; | |
217 | uint32_t c15_power_control; /* power control */ | |
b5ff1b31 | 218 | } cp15; |
40f137e1 | 219 | |
9ee6e8bb PB |
220 | struct { |
221 | uint32_t other_sp; | |
222 | uint32_t vecbase; | |
223 | uint32_t basepri; | |
224 | uint32_t control; | |
225 | int current_sp; | |
226 | int exception; | |
227 | int pending_exception; | |
9ee6e8bb PB |
228 | } v7m; |
229 | ||
fe1479c3 PB |
230 | /* Thumb-2 EE state. */ |
231 | uint32_t teecr; | |
232 | uint32_t teehbr; | |
233 | ||
b7bcbe95 FB |
234 | /* VFP coprocessor state. */ |
235 | struct { | |
3926cc84 AG |
236 | /* VFP/Neon register state. Note that the mapping between S, D and Q |
237 | * views of the register bank differs between AArch64 and AArch32: | |
238 | * In AArch32: | |
239 | * Qn = regs[2n+1]:regs[2n] | |
240 | * Dn = regs[n] | |
241 | * Sn = regs[n/2] bits 31..0 for even n, and bits 63..32 for odd n | |
242 | * (and regs[32] to regs[63] are inaccessible) | |
243 | * In AArch64: | |
244 | * Qn = regs[2n+1]:regs[2n] | |
245 | * Dn = regs[2n] | |
246 | * Sn = regs[2n] bits 31..0 | |
247 | * This corresponds to the architecturally defined mapping between | |
248 | * the two execution states, and means we do not need to explicitly | |
249 | * map these registers when changing states. | |
250 | */ | |
251 | float64 regs[64]; | |
b7bcbe95 | 252 | |
40f137e1 | 253 | uint32_t xregs[16]; |
b7bcbe95 FB |
254 | /* We store these fpcsr fields separately for convenience. */ |
255 | int vec_len; | |
256 | int vec_stride; | |
257 | ||
9ee6e8bb PB |
258 | /* scratch space when Tn are not sufficient. */ |
259 | uint32_t scratch[8]; | |
3b46e624 | 260 | |
3a492f3a PM |
261 | /* fp_status is the "normal" fp status. standard_fp_status retains |
262 | * values corresponding to the ARM "Standard FPSCR Value", ie | |
263 | * default-NaN, flush-to-zero, round-to-nearest and is used by | |
264 | * any operations (generally Neon) which the architecture defines | |
265 | * as controlled by the standard FPSCR value rather than the FPSCR. | |
266 | * | |
267 | * To avoid having to transfer exception bits around, we simply | |
268 | * say that the FPSCR cumulative exception flags are the logical | |
269 | * OR of the flags in the two fp statuses. This relies on the | |
270 | * only thing which needs to read the exception flags being | |
271 | * an explicit FPSCR read. | |
272 | */ | |
53cd6637 | 273 | float_status fp_status; |
3a492f3a | 274 | float_status standard_fp_status; |
b7bcbe95 | 275 | } vfp; |
03d05e2d PM |
276 | uint64_t exclusive_addr; |
277 | uint64_t exclusive_val; | |
278 | uint64_t exclusive_high; | |
9ee6e8bb | 279 | #if defined(CONFIG_USER_ONLY) |
03d05e2d | 280 | uint64_t exclusive_test; |
426f5abc | 281 | uint32_t exclusive_info; |
9ee6e8bb | 282 | #endif |
b7bcbe95 | 283 | |
18c9b560 AZ |
284 | /* iwMMXt coprocessor state. */ |
285 | struct { | |
286 | uint64_t regs[16]; | |
287 | uint64_t val; | |
288 | ||
289 | uint32_t cregs[16]; | |
290 | } iwmmxt; | |
291 | ||
d8fd2954 PB |
292 | /* For mixed endian mode. */ |
293 | bool bswap_code; | |
294 | ||
ce4defa0 PB |
295 | #if defined(CONFIG_USER_ONLY) |
296 | /* For usermode syscall translation. */ | |
297 | int eabi; | |
298 | #endif | |
299 | ||
a316d335 FB |
300 | CPU_COMMON |
301 | ||
9d551997 | 302 | /* These fields after the common ones so they are preserved on reset. */ |
9ba8c3f4 | 303 | |
581be094 | 304 | /* Internal CPU feature flags. */ |
918f5dca | 305 | uint64_t features; |
581be094 | 306 | |
983fe826 | 307 | void *nvic; |
462a8bc6 | 308 | const struct arm_boot_info *boot_info; |
2c0262af FB |
309 | } CPUARMState; |
310 | ||
778c3a06 AF |
311 | #include "cpu-qom.h" |
312 | ||
313 | ARMCPU *cpu_arm_init(const char *cpu_model); | |
b26eefb6 | 314 | void arm_translate_init(void); |
14969266 | 315 | void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu); |
2c0262af | 316 | int cpu_arm_exec(CPUARMState *s); |
494b00c7 | 317 | int bank_number(int mode); |
b5ff1b31 | 318 | void switch_mode(CPUARMState *, int); |
9ee6e8bb | 319 | uint32_t do_arm_semihosting(CPUARMState *env); |
b5ff1b31 | 320 | |
3926cc84 AG |
321 | static inline bool is_a64(CPUARMState *env) |
322 | { | |
323 | return env->aarch64; | |
324 | } | |
325 | ||
2c0262af FB |
326 | /* you can call this signal handler from your SIGBUS and SIGSEGV |
327 | signal handlers to inform the virtual CPU of exceptions. non zero | |
328 | is returned if the signal was handled by the virtual CPU. */ | |
5fafdf24 | 329 | int cpu_arm_signal_handler(int host_signum, void *pinfo, |
2c0262af | 330 | void *puc); |
84a031c6 | 331 | int cpu_arm_handle_mmu_fault (CPUARMState *env, target_ulong address, int rw, |
97b348e7 | 332 | int mmu_idx); |
0b5c1ce8 | 333 | #define cpu_handle_mmu_fault cpu_arm_handle_mmu_fault |
2c0262af | 334 | |
76e3e1bc PM |
335 | /* SCTLR bit meanings. Several bits have been reused in newer |
336 | * versions of the architecture; in that case we define constants | |
337 | * for both old and new bit meanings. Code which tests against those | |
338 | * bits should probably check or otherwise arrange that the CPU | |
339 | * is the architectural version it expects. | |
340 | */ | |
341 | #define SCTLR_M (1U << 0) | |
342 | #define SCTLR_A (1U << 1) | |
343 | #define SCTLR_C (1U << 2) | |
344 | #define SCTLR_W (1U << 3) /* up to v6; RAO in v7 */ | |
345 | #define SCTLR_SA (1U << 3) | |
346 | #define SCTLR_P (1U << 4) /* up to v5; RAO in v6 and v7 */ | |
347 | #define SCTLR_SA0 (1U << 4) /* v8 onward, AArch64 only */ | |
348 | #define SCTLR_D (1U << 5) /* up to v5; RAO in v6 */ | |
349 | #define SCTLR_CP15BEN (1U << 5) /* v7 onward */ | |
350 | #define SCTLR_L (1U << 6) /* up to v5; RAO in v6 and v7; RAZ in v8 */ | |
351 | #define SCTLR_B (1U << 7) /* up to v6; RAZ in v7 */ | |
352 | #define SCTLR_ITD (1U << 7) /* v8 onward */ | |
353 | #define SCTLR_S (1U << 8) /* up to v6; RAZ in v7 */ | |
354 | #define SCTLR_SED (1U << 8) /* v8 onward */ | |
355 | #define SCTLR_R (1U << 9) /* up to v6; RAZ in v7 */ | |
356 | #define SCTLR_UMA (1U << 9) /* v8 onward, AArch64 only */ | |
357 | #define SCTLR_F (1U << 10) /* up to v6 */ | |
358 | #define SCTLR_SW (1U << 10) /* v7 onward */ | |
359 | #define SCTLR_Z (1U << 11) | |
360 | #define SCTLR_I (1U << 12) | |
361 | #define SCTLR_V (1U << 13) | |
362 | #define SCTLR_RR (1U << 14) /* up to v7 */ | |
363 | #define SCTLR_DZE (1U << 14) /* v8 onward, AArch64 only */ | |
364 | #define SCTLR_L4 (1U << 15) /* up to v6; RAZ in v7 */ | |
365 | #define SCTLR_UCT (1U << 15) /* v8 onward, AArch64 only */ | |
366 | #define SCTLR_DT (1U << 16) /* up to ??, RAO in v6 and v7 */ | |
367 | #define SCTLR_nTWI (1U << 16) /* v8 onward */ | |
368 | #define SCTLR_HA (1U << 17) | |
369 | #define SCTLR_IT (1U << 18) /* up to ??, RAO in v6 and v7 */ | |
370 | #define SCTLR_nTWE (1U << 18) /* v8 onward */ | |
371 | #define SCTLR_WXN (1U << 19) | |
372 | #define SCTLR_ST (1U << 20) /* up to ??, RAZ in v6 */ | |
373 | #define SCTLR_UWXN (1U << 20) /* v7 onward */ | |
374 | #define SCTLR_FI (1U << 21) | |
375 | #define SCTLR_U (1U << 22) | |
376 | #define SCTLR_XP (1U << 23) /* up to v6; v7 onward RAO */ | |
377 | #define SCTLR_VE (1U << 24) /* up to v7 */ | |
378 | #define SCTLR_E0E (1U << 24) /* v8 onward, AArch64 only */ | |
379 | #define SCTLR_EE (1U << 25) | |
380 | #define SCTLR_L2 (1U << 26) /* up to v6, RAZ in v7 */ | |
381 | #define SCTLR_UCI (1U << 26) /* v8 onward, AArch64 only */ | |
382 | #define SCTLR_NMFI (1U << 27) | |
383 | #define SCTLR_TRE (1U << 28) | |
384 | #define SCTLR_AFE (1U << 29) | |
385 | #define SCTLR_TE (1U << 30) | |
386 | ||
78dbbbe4 PM |
387 | #define CPSR_M (0x1fU) |
388 | #define CPSR_T (1U << 5) | |
389 | #define CPSR_F (1U << 6) | |
390 | #define CPSR_I (1U << 7) | |
391 | #define CPSR_A (1U << 8) | |
392 | #define CPSR_E (1U << 9) | |
393 | #define CPSR_IT_2_7 (0xfc00U) | |
394 | #define CPSR_GE (0xfU << 16) | |
395 | #define CPSR_RESERVED (0xfU << 20) | |
396 | #define CPSR_J (1U << 24) | |
397 | #define CPSR_IT_0_1 (3U << 25) | |
398 | #define CPSR_Q (1U << 27) | |
399 | #define CPSR_V (1U << 28) | |
400 | #define CPSR_C (1U << 29) | |
401 | #define CPSR_Z (1U << 30) | |
402 | #define CPSR_N (1U << 31) | |
9ee6e8bb PB |
403 | #define CPSR_NZCV (CPSR_N | CPSR_Z | CPSR_C | CPSR_V) |
404 | ||
405 | #define CPSR_IT (CPSR_IT_0_1 | CPSR_IT_2_7) | |
406 | #define CACHED_CPSR_BITS (CPSR_T | CPSR_GE | CPSR_IT | CPSR_Q | CPSR_NZCV) | |
407 | /* Bits writable in user mode. */ | |
408 | #define CPSR_USER (CPSR_NZCV | CPSR_Q | CPSR_GE) | |
409 | /* Execution state bits. MRS read as zero, MSR writes ignored. */ | |
410 | #define CPSR_EXEC (CPSR_T | CPSR_IT | CPSR_J) | |
b5ff1b31 | 411 | |
d356312f PM |
412 | /* Bit definitions for ARMv8 SPSR (PSTATE) format. |
413 | * Only these are valid when in AArch64 mode; in | |
414 | * AArch32 mode SPSRs are basically CPSR-format. | |
415 | */ | |
416 | #define PSTATE_M (0xFU) | |
417 | #define PSTATE_nRW (1U << 4) | |
418 | #define PSTATE_F (1U << 6) | |
419 | #define PSTATE_I (1U << 7) | |
420 | #define PSTATE_A (1U << 8) | |
421 | #define PSTATE_D (1U << 9) | |
422 | #define PSTATE_IL (1U << 20) | |
423 | #define PSTATE_SS (1U << 21) | |
424 | #define PSTATE_V (1U << 28) | |
425 | #define PSTATE_C (1U << 29) | |
426 | #define PSTATE_Z (1U << 30) | |
427 | #define PSTATE_N (1U << 31) | |
428 | #define PSTATE_NZCV (PSTATE_N | PSTATE_Z | PSTATE_C | PSTATE_V) | |
429 | #define CACHED_PSTATE_BITS (PSTATE_NZCV) | |
430 | /* Mode values for AArch64 */ | |
431 | #define PSTATE_MODE_EL3h 13 | |
432 | #define PSTATE_MODE_EL3t 12 | |
433 | #define PSTATE_MODE_EL2h 9 | |
434 | #define PSTATE_MODE_EL2t 8 | |
435 | #define PSTATE_MODE_EL1h 5 | |
436 | #define PSTATE_MODE_EL1t 4 | |
437 | #define PSTATE_MODE_EL0t 0 | |
438 | ||
439 | /* Return the current PSTATE value. For the moment we don't support 32<->64 bit | |
440 | * interprocessing, so we don't attempt to sync with the cpsr state used by | |
441 | * the 32 bit decoder. | |
442 | */ | |
443 | static inline uint32_t pstate_read(CPUARMState *env) | |
444 | { | |
445 | int ZF; | |
446 | ||
447 | ZF = (env->ZF == 0); | |
448 | return (env->NF & 0x80000000) | (ZF << 30) | |
449 | | (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | |
450 | | env->pstate; | |
451 | } | |
452 | ||
453 | static inline void pstate_write(CPUARMState *env, uint32_t val) | |
454 | { | |
455 | env->ZF = (~val) & PSTATE_Z; | |
456 | env->NF = val; | |
457 | env->CF = (val >> 29) & 1; | |
458 | env->VF = (val << 3) & 0x80000000; | |
459 | env->pstate = val & ~CACHED_PSTATE_BITS; | |
460 | } | |
461 | ||
b5ff1b31 | 462 | /* Return the current CPSR value. */ |
2f4a40e5 AZ |
463 | uint32_t cpsr_read(CPUARMState *env); |
464 | /* Set the CPSR. Note that some bits of mask must be all-set or all-clear. */ | |
465 | void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask); | |
9ee6e8bb PB |
466 | |
467 | /* Return the current xPSR value. */ | |
468 | static inline uint32_t xpsr_read(CPUARMState *env) | |
469 | { | |
470 | int ZF; | |
6fbe23d5 PB |
471 | ZF = (env->ZF == 0); |
472 | return (env->NF & 0x80000000) | (ZF << 30) | |
9ee6e8bb PB |
473 | | (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27) |
474 | | (env->thumb << 24) | ((env->condexec_bits & 3) << 25) | |
475 | | ((env->condexec_bits & 0xfc) << 8) | |
476 | | env->v7m.exception; | |
b5ff1b31 FB |
477 | } |
478 | ||
9ee6e8bb PB |
479 | /* Set the xPSR. Note that some bits of mask must be all-set or all-clear. */ |
480 | static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask) | |
481 | { | |
9ee6e8bb | 482 | if (mask & CPSR_NZCV) { |
6fbe23d5 PB |
483 | env->ZF = (~val) & CPSR_Z; |
484 | env->NF = val; | |
9ee6e8bb PB |
485 | env->CF = (val >> 29) & 1; |
486 | env->VF = (val << 3) & 0x80000000; | |
487 | } | |
488 | if (mask & CPSR_Q) | |
489 | env->QF = ((val & CPSR_Q) != 0); | |
490 | if (mask & (1 << 24)) | |
491 | env->thumb = ((val & (1 << 24)) != 0); | |
492 | if (mask & CPSR_IT_0_1) { | |
493 | env->condexec_bits &= ~3; | |
494 | env->condexec_bits |= (val >> 25) & 3; | |
495 | } | |
496 | if (mask & CPSR_IT_2_7) { | |
497 | env->condexec_bits &= 3; | |
498 | env->condexec_bits |= (val >> 8) & 0xfc; | |
499 | } | |
500 | if (mask & 0x1ff) { | |
501 | env->v7m.exception = val & 0x1ff; | |
502 | } | |
503 | } | |
504 | ||
01653295 PM |
505 | /* Return the current FPSCR value. */ |
506 | uint32_t vfp_get_fpscr(CPUARMState *env); | |
507 | void vfp_set_fpscr(CPUARMState *env, uint32_t val); | |
508 | ||
f903fa22 PM |
509 | /* For A64 the FPSCR is split into two logically distinct registers, |
510 | * FPCR and FPSR. However since they still use non-overlapping bits | |
511 | * we store the underlying state in fpscr and just mask on read/write. | |
512 | */ | |
513 | #define FPSR_MASK 0xf800009f | |
514 | #define FPCR_MASK 0x07f79f00 | |
515 | static inline uint32_t vfp_get_fpsr(CPUARMState *env) | |
516 | { | |
517 | return vfp_get_fpscr(env) & FPSR_MASK; | |
518 | } | |
519 | ||
520 | static inline void vfp_set_fpsr(CPUARMState *env, uint32_t val) | |
521 | { | |
522 | uint32_t new_fpscr = (vfp_get_fpscr(env) & ~FPSR_MASK) | (val & FPSR_MASK); | |
523 | vfp_set_fpscr(env, new_fpscr); | |
524 | } | |
525 | ||
526 | static inline uint32_t vfp_get_fpcr(CPUARMState *env) | |
527 | { | |
528 | return vfp_get_fpscr(env) & FPCR_MASK; | |
529 | } | |
530 | ||
531 | static inline void vfp_set_fpcr(CPUARMState *env, uint32_t val) | |
532 | { | |
533 | uint32_t new_fpscr = (vfp_get_fpscr(env) & ~FPCR_MASK) | (val & FPCR_MASK); | |
534 | vfp_set_fpscr(env, new_fpscr); | |
535 | } | |
536 | ||
4d3da0f3 AG |
537 | enum arm_fprounding { |
538 | FPROUNDING_TIEEVEN, | |
539 | FPROUNDING_POSINF, | |
540 | FPROUNDING_NEGINF, | |
541 | FPROUNDING_ZERO, | |
542 | FPROUNDING_TIEAWAY, | |
543 | FPROUNDING_ODD | |
544 | }; | |
545 | ||
9972da66 WN |
546 | int arm_rmode_to_sf(int rmode); |
547 | ||
b5ff1b31 FB |
548 | enum arm_cpu_mode { |
549 | ARM_CPU_MODE_USR = 0x10, | |
550 | ARM_CPU_MODE_FIQ = 0x11, | |
551 | ARM_CPU_MODE_IRQ = 0x12, | |
552 | ARM_CPU_MODE_SVC = 0x13, | |
553 | ARM_CPU_MODE_ABT = 0x17, | |
554 | ARM_CPU_MODE_UND = 0x1b, | |
555 | ARM_CPU_MODE_SYS = 0x1f | |
556 | }; | |
557 | ||
40f137e1 PB |
558 | /* VFP system registers. */ |
559 | #define ARM_VFP_FPSID 0 | |
560 | #define ARM_VFP_FPSCR 1 | |
9ee6e8bb PB |
561 | #define ARM_VFP_MVFR1 6 |
562 | #define ARM_VFP_MVFR0 7 | |
40f137e1 PB |
563 | #define ARM_VFP_FPEXC 8 |
564 | #define ARM_VFP_FPINST 9 | |
565 | #define ARM_VFP_FPINST2 10 | |
566 | ||
18c9b560 AZ |
567 | /* iwMMXt coprocessor control registers. */ |
568 | #define ARM_IWMMXT_wCID 0 | |
569 | #define ARM_IWMMXT_wCon 1 | |
570 | #define ARM_IWMMXT_wCSSF 2 | |
571 | #define ARM_IWMMXT_wCASF 3 | |
572 | #define ARM_IWMMXT_wCGR0 8 | |
573 | #define ARM_IWMMXT_wCGR1 9 | |
574 | #define ARM_IWMMXT_wCGR2 10 | |
575 | #define ARM_IWMMXT_wCGR3 11 | |
576 | ||
ce854d7c BC |
577 | /* If adding a feature bit which corresponds to a Linux ELF |
578 | * HWCAP bit, remember to update the feature-bit-to-hwcap | |
579 | * mapping in linux-user/elfload.c:get_elf_hwcap(). | |
580 | */ | |
40f137e1 PB |
581 | enum arm_features { |
582 | ARM_FEATURE_VFP, | |
c1713132 AZ |
583 | ARM_FEATURE_AUXCR, /* ARM1026 Auxiliary control register. */ |
584 | ARM_FEATURE_XSCALE, /* Intel XScale extensions. */ | |
ce819861 | 585 | ARM_FEATURE_IWMMXT, /* Intel iwMMXt extension. */ |
9ee6e8bb PB |
586 | ARM_FEATURE_V6, |
587 | ARM_FEATURE_V6K, | |
588 | ARM_FEATURE_V7, | |
589 | ARM_FEATURE_THUMB2, | |
c3d2689d | 590 | ARM_FEATURE_MPU, /* Only has Memory Protection Unit, not full MMU. */ |
9ee6e8bb | 591 | ARM_FEATURE_VFP3, |
60011498 | 592 | ARM_FEATURE_VFP_FP16, |
9ee6e8bb | 593 | ARM_FEATURE_NEON, |
47789990 | 594 | ARM_FEATURE_THUMB_DIV, /* divide supported in Thumb encoding */ |
9ee6e8bb | 595 | ARM_FEATURE_M, /* Microcontroller profile. */ |
fe1479c3 | 596 | ARM_FEATURE_OMAPCP, /* OMAP specific CP15 ops handling. */ |
e1bbf446 | 597 | ARM_FEATURE_THUMB2EE, |
be5e7a76 DES |
598 | ARM_FEATURE_V7MP, /* v7 Multiprocessing Extensions */ |
599 | ARM_FEATURE_V4T, | |
600 | ARM_FEATURE_V5, | |
5bc95aa2 | 601 | ARM_FEATURE_STRONGARM, |
906879a9 | 602 | ARM_FEATURE_VAPA, /* cp15 VA to PA lookups */ |
b8b8ea05 | 603 | ARM_FEATURE_ARM_DIV, /* divide supported in ARM encoding */ |
da97f52c | 604 | ARM_FEATURE_VFP4, /* VFPv4 (implies that NEON is v2) */ |
0383ac00 | 605 | ARM_FEATURE_GENERIC_TIMER, |
06ed5d66 | 606 | ARM_FEATURE_MVFR, /* Media and VFP Feature Registers 0 and 1 */ |
1047b9d7 | 607 | ARM_FEATURE_DUMMY_C15_REGS, /* RAZ/WI all of cp15 crn=15 */ |
c4804214 PM |
608 | ARM_FEATURE_CACHE_TEST_CLEAN, /* 926/1026 style test-and-clean ops */ |
609 | ARM_FEATURE_CACHE_DIRTY_REG, /* 1136/1176 cache dirty status register */ | |
610 | ARM_FEATURE_CACHE_BLOCK_OPS, /* v6 optional cache block operations */ | |
81bdde9d | 611 | ARM_FEATURE_MPIDR, /* has cp15 MPIDR */ |
de9b05b8 PM |
612 | ARM_FEATURE_PXN, /* has Privileged Execute Never bit */ |
613 | ARM_FEATURE_LPAE, /* has Large Physical Address Extension */ | |
81e69fb0 | 614 | ARM_FEATURE_V8, |
3926cc84 | 615 | ARM_FEATURE_AARCH64, /* supports 64 bit mode */ |
9d935509 | 616 | ARM_FEATURE_V8_AES, /* implements AES part of v8 Crypto Extensions */ |
d8ba780b | 617 | ARM_FEATURE_CBAR, /* has cp15 CBAR */ |
40f137e1 PB |
618 | }; |
619 | ||
620 | static inline int arm_feature(CPUARMState *env, int feature) | |
621 | { | |
918f5dca | 622 | return (env->features & (1ULL << feature)) != 0; |
40f137e1 PB |
623 | } |
624 | ||
9a78eead | 625 | void arm_cpu_list(FILE *f, fprintf_function cpu_fprintf); |
40f137e1 | 626 | |
9ee6e8bb PB |
627 | /* Interface between CPU and Interrupt controller. */ |
628 | void armv7m_nvic_set_pending(void *opaque, int irq); | |
629 | int armv7m_nvic_acknowledge_irq(void *opaque); | |
630 | void armv7m_nvic_complete_irq(void *opaque, int irq); | |
631 | ||
4b6a83fb PM |
632 | /* Interface for defining coprocessor registers. |
633 | * Registers are defined in tables of arm_cp_reginfo structs | |
634 | * which are passed to define_arm_cp_regs(). | |
635 | */ | |
636 | ||
637 | /* When looking up a coprocessor register we look for it | |
638 | * via an integer which encodes all of: | |
639 | * coprocessor number | |
640 | * Crn, Crm, opc1, opc2 fields | |
641 | * 32 or 64 bit register (ie is it accessed via MRC/MCR | |
642 | * or via MRRC/MCRR?) | |
643 | * We allow 4 bits for opc1 because MRRC/MCRR have a 4 bit field. | |
644 | * (In this case crn and opc2 should be zero.) | |
f5a0a5a5 PM |
645 | * For AArch64, there is no 32/64 bit size distinction; |
646 | * instead all registers have a 2 bit op0, 3 bit op1 and op2, | |
647 | * and 4 bit CRn and CRm. The encoding patterns are chosen | |
648 | * to be easy to convert to and from the KVM encodings, and also | |
649 | * so that the hashtable can contain both AArch32 and AArch64 | |
650 | * registers (to allow for interprocessing where we might run | |
651 | * 32 bit code on a 64 bit core). | |
4b6a83fb | 652 | */ |
f5a0a5a5 PM |
653 | /* This bit is private to our hashtable cpreg; in KVM register |
654 | * IDs the AArch64/32 distinction is the KVM_REG_ARM/ARM64 | |
655 | * in the upper bits of the 64 bit ID. | |
656 | */ | |
657 | #define CP_REG_AA64_SHIFT 28 | |
658 | #define CP_REG_AA64_MASK (1 << CP_REG_AA64_SHIFT) | |
659 | ||
4b6a83fb PM |
660 | #define ENCODE_CP_REG(cp, is64, crn, crm, opc1, opc2) \ |
661 | (((cp) << 16) | ((is64) << 15) | ((crn) << 11) | \ | |
662 | ((crm) << 7) | ((opc1) << 3) | (opc2)) | |
663 | ||
f5a0a5a5 PM |
664 | #define ENCODE_AA64_CP_REG(cp, crn, crm, op0, op1, op2) \ |
665 | (CP_REG_AA64_MASK | \ | |
666 | ((cp) << CP_REG_ARM_COPROC_SHIFT) | \ | |
667 | ((op0) << CP_REG_ARM64_SYSREG_OP0_SHIFT) | \ | |
668 | ((op1) << CP_REG_ARM64_SYSREG_OP1_SHIFT) | \ | |
669 | ((crn) << CP_REG_ARM64_SYSREG_CRN_SHIFT) | \ | |
670 | ((crm) << CP_REG_ARM64_SYSREG_CRM_SHIFT) | \ | |
671 | ((op2) << CP_REG_ARM64_SYSREG_OP2_SHIFT)) | |
672 | ||
721fae12 PM |
673 | /* Convert a full 64 bit KVM register ID to the truncated 32 bit |
674 | * version used as a key for the coprocessor register hashtable | |
675 | */ | |
676 | static inline uint32_t kvm_to_cpreg_id(uint64_t kvmid) | |
677 | { | |
678 | uint32_t cpregid = kvmid; | |
f5a0a5a5 PM |
679 | if ((kvmid & CP_REG_ARCH_MASK) == CP_REG_ARM64) { |
680 | cpregid |= CP_REG_AA64_MASK; | |
681 | } else if ((kvmid & CP_REG_SIZE_MASK) == CP_REG_SIZE_U64) { | |
721fae12 PM |
682 | cpregid |= (1 << 15); |
683 | } | |
684 | return cpregid; | |
685 | } | |
686 | ||
687 | /* Convert a truncated 32 bit hashtable key into the full | |
688 | * 64 bit KVM register ID. | |
689 | */ | |
690 | static inline uint64_t cpreg_to_kvm_id(uint32_t cpregid) | |
691 | { | |
f5a0a5a5 PM |
692 | uint64_t kvmid; |
693 | ||
694 | if (cpregid & CP_REG_AA64_MASK) { | |
695 | kvmid = cpregid & ~CP_REG_AA64_MASK; | |
696 | kvmid |= CP_REG_SIZE_U64 | CP_REG_ARM64; | |
721fae12 | 697 | } else { |
f5a0a5a5 PM |
698 | kvmid = cpregid & ~(1 << 15); |
699 | if (cpregid & (1 << 15)) { | |
700 | kvmid |= CP_REG_SIZE_U64 | CP_REG_ARM; | |
701 | } else { | |
702 | kvmid |= CP_REG_SIZE_U32 | CP_REG_ARM; | |
703 | } | |
721fae12 PM |
704 | } |
705 | return kvmid; | |
706 | } | |
707 | ||
4b6a83fb PM |
708 | /* ARMCPRegInfo type field bits. If the SPECIAL bit is set this is a |
709 | * special-behaviour cp reg and bits [15..8] indicate what behaviour | |
710 | * it has. Otherwise it is a simple cp reg, where CONST indicates that | |
711 | * TCG can assume the value to be constant (ie load at translate time) | |
712 | * and 64BIT indicates a 64 bit wide coprocessor register. SUPPRESS_TB_END | |
713 | * indicates that the TB should not be ended after a write to this register | |
714 | * (the default is that the TB ends after cp writes). OVERRIDE permits | |
715 | * a register definition to override a previous definition for the | |
716 | * same (cp, is64, crn, crm, opc1, opc2) tuple: either the new or the | |
717 | * old must have the OVERRIDE bit set. | |
7023ec7e PM |
718 | * NO_MIGRATE indicates that this register should be ignored for migration; |
719 | * (eg because any state is accessed via some other coprocessor register). | |
2452731c PM |
720 | * IO indicates that this register does I/O and therefore its accesses |
721 | * need to be surrounded by gen_io_start()/gen_io_end(). In particular, | |
722 | * registers which implement clocks or timers require this. | |
4b6a83fb PM |
723 | */ |
724 | #define ARM_CP_SPECIAL 1 | |
725 | #define ARM_CP_CONST 2 | |
726 | #define ARM_CP_64BIT 4 | |
727 | #define ARM_CP_SUPPRESS_TB_END 8 | |
728 | #define ARM_CP_OVERRIDE 16 | |
7023ec7e | 729 | #define ARM_CP_NO_MIGRATE 32 |
2452731c | 730 | #define ARM_CP_IO 64 |
4b6a83fb PM |
731 | #define ARM_CP_NOP (ARM_CP_SPECIAL | (1 << 8)) |
732 | #define ARM_CP_WFI (ARM_CP_SPECIAL | (2 << 8)) | |
b0d2b7d0 PM |
733 | #define ARM_CP_NZCV (ARM_CP_SPECIAL | (3 << 8)) |
734 | #define ARM_LAST_SPECIAL ARM_CP_NZCV | |
4b6a83fb PM |
735 | /* Used only as a terminator for ARMCPRegInfo lists */ |
736 | #define ARM_CP_SENTINEL 0xffff | |
737 | /* Mask of only the flag bits in a type field */ | |
2452731c | 738 | #define ARM_CP_FLAG_MASK 0x7f |
4b6a83fb | 739 | |
f5a0a5a5 PM |
740 | /* Valid values for ARMCPRegInfo state field, indicating which of |
741 | * the AArch32 and AArch64 execution states this register is visible in. | |
742 | * If the reginfo doesn't explicitly specify then it is AArch32 only. | |
743 | * If the reginfo is declared to be visible in both states then a second | |
744 | * reginfo is synthesised for the AArch32 view of the AArch64 register, | |
745 | * such that the AArch32 view is the lower 32 bits of the AArch64 one. | |
746 | * Note that we rely on the values of these enums as we iterate through | |
747 | * the various states in some places. | |
748 | */ | |
749 | enum { | |
750 | ARM_CP_STATE_AA32 = 0, | |
751 | ARM_CP_STATE_AA64 = 1, | |
752 | ARM_CP_STATE_BOTH = 2, | |
753 | }; | |
754 | ||
4b6a83fb PM |
755 | /* Return true if cptype is a valid type field. This is used to try to |
756 | * catch errors where the sentinel has been accidentally left off the end | |
757 | * of a list of registers. | |
758 | */ | |
759 | static inline bool cptype_valid(int cptype) | |
760 | { | |
761 | return ((cptype & ~ARM_CP_FLAG_MASK) == 0) | |
762 | || ((cptype & ARM_CP_SPECIAL) && | |
34affeef | 763 | ((cptype & ~ARM_CP_FLAG_MASK) <= ARM_LAST_SPECIAL)); |
4b6a83fb PM |
764 | } |
765 | ||
766 | /* Access rights: | |
767 | * We define bits for Read and Write access for what rev C of the v7-AR ARM ARM | |
768 | * defines as PL0 (user), PL1 (fiq/irq/svc/abt/und/sys, ie privileged), and | |
769 | * PL2 (hyp). The other level which has Read and Write bits is Secure PL1 | |
770 | * (ie any of the privileged modes in Secure state, or Monitor mode). | |
771 | * If a register is accessible in one privilege level it's always accessible | |
772 | * in higher privilege levels too. Since "Secure PL1" also follows this rule | |
773 | * (ie anything visible in PL2 is visible in S-PL1, some things are only | |
774 | * visible in S-PL1) but "Secure PL1" is a bit of a mouthful, we bend the | |
775 | * terminology a little and call this PL3. | |
f5a0a5a5 PM |
776 | * In AArch64 things are somewhat simpler as the PLx bits line up exactly |
777 | * with the ELx exception levels. | |
4b6a83fb PM |
778 | * |
779 | * If access permissions for a register are more complex than can be | |
780 | * described with these bits, then use a laxer set of restrictions, and | |
781 | * do the more restrictive/complex check inside a helper function. | |
782 | */ | |
783 | #define PL3_R 0x80 | |
784 | #define PL3_W 0x40 | |
785 | #define PL2_R (0x20 | PL3_R) | |
786 | #define PL2_W (0x10 | PL3_W) | |
787 | #define PL1_R (0x08 | PL2_R) | |
788 | #define PL1_W (0x04 | PL2_W) | |
789 | #define PL0_R (0x02 | PL1_R) | |
790 | #define PL0_W (0x01 | PL1_W) | |
791 | ||
792 | #define PL3_RW (PL3_R | PL3_W) | |
793 | #define PL2_RW (PL2_R | PL2_W) | |
794 | #define PL1_RW (PL1_R | PL1_W) | |
795 | #define PL0_RW (PL0_R | PL0_W) | |
796 | ||
797 | static inline int arm_current_pl(CPUARMState *env) | |
798 | { | |
f5a0a5a5 PM |
799 | if (env->aarch64) { |
800 | return extract32(env->pstate, 2, 2); | |
801 | } | |
802 | ||
4b6a83fb PM |
803 | if ((env->uncached_cpsr & 0x1f) == ARM_CPU_MODE_USR) { |
804 | return 0; | |
805 | } | |
806 | /* We don't currently implement the Virtualization or TrustZone | |
807 | * extensions, so PL2 and PL3 don't exist for us. | |
808 | */ | |
809 | return 1; | |
810 | } | |
811 | ||
812 | typedef struct ARMCPRegInfo ARMCPRegInfo; | |
813 | ||
f59df3f2 PM |
814 | typedef enum CPAccessResult { |
815 | /* Access is permitted */ | |
816 | CP_ACCESS_OK = 0, | |
817 | /* Access fails due to a configurable trap or enable which would | |
818 | * result in a categorized exception syndrome giving information about | |
819 | * the failing instruction (ie syndrome category 0x3, 0x4, 0x5, 0x6, | |
820 | * 0xc or 0x18). | |
821 | */ | |
822 | CP_ACCESS_TRAP = 1, | |
823 | /* Access fails and results in an exception syndrome 0x0 ("uncategorized"). | |
824 | * Note that this is not a catch-all case -- the set of cases which may | |
825 | * result in this failure is specifically defined by the architecture. | |
826 | */ | |
827 | CP_ACCESS_TRAP_UNCATEGORIZED = 2, | |
828 | } CPAccessResult; | |
829 | ||
c4241c7d PM |
830 | /* Access functions for coprocessor registers. These cannot fail and |
831 | * may not raise exceptions. | |
832 | */ | |
833 | typedef uint64_t CPReadFn(CPUARMState *env, const ARMCPRegInfo *opaque); | |
834 | typedef void CPWriteFn(CPUARMState *env, const ARMCPRegInfo *opaque, | |
835 | uint64_t value); | |
f59df3f2 PM |
836 | /* Access permission check functions for coprocessor registers. */ |
837 | typedef CPAccessResult CPAccessFn(CPUARMState *env, const ARMCPRegInfo *opaque); | |
4b6a83fb PM |
838 | /* Hook function for register reset */ |
839 | typedef void CPResetFn(CPUARMState *env, const ARMCPRegInfo *opaque); | |
840 | ||
841 | #define CP_ANY 0xff | |
842 | ||
843 | /* Definition of an ARM coprocessor register */ | |
844 | struct ARMCPRegInfo { | |
845 | /* Name of register (useful mainly for debugging, need not be unique) */ | |
846 | const char *name; | |
847 | /* Location of register: coprocessor number and (crn,crm,opc1,opc2) | |
848 | * tuple. Any of crm, opc1 and opc2 may be CP_ANY to indicate a | |
849 | * 'wildcard' field -- any value of that field in the MRC/MCR insn | |
850 | * will be decoded to this register. The register read and write | |
851 | * callbacks will be passed an ARMCPRegInfo with the crn/crm/opc1/opc2 | |
852 | * used by the program, so it is possible to register a wildcard and | |
853 | * then behave differently on read/write if necessary. | |
854 | * For 64 bit registers, only crm and opc1 are relevant; crn and opc2 | |
855 | * must both be zero. | |
f5a0a5a5 PM |
856 | * For AArch64-visible registers, opc0 is also used. |
857 | * Since there are no "coprocessors" in AArch64, cp is purely used as a | |
858 | * way to distinguish (for KVM's benefit) guest-visible system registers | |
859 | * from demuxed ones provided to preserve the "no side effects on | |
860 | * KVM register read/write from QEMU" semantics. cp==0x13 is guest | |
861 | * visible (to match KVM's encoding); cp==0 will be converted to | |
862 | * cp==0x13 when the ARMCPRegInfo is registered, for convenience. | |
4b6a83fb PM |
863 | */ |
864 | uint8_t cp; | |
865 | uint8_t crn; | |
866 | uint8_t crm; | |
f5a0a5a5 | 867 | uint8_t opc0; |
4b6a83fb PM |
868 | uint8_t opc1; |
869 | uint8_t opc2; | |
f5a0a5a5 PM |
870 | /* Execution state in which this register is visible: ARM_CP_STATE_* */ |
871 | int state; | |
4b6a83fb PM |
872 | /* Register type: ARM_CP_* bits/values */ |
873 | int type; | |
874 | /* Access rights: PL*_[RW] */ | |
875 | int access; | |
876 | /* The opaque pointer passed to define_arm_cp_regs_with_opaque() when | |
877 | * this register was defined: can be used to hand data through to the | |
878 | * register read/write functions, since they are passed the ARMCPRegInfo*. | |
879 | */ | |
880 | void *opaque; | |
881 | /* Value of this register, if it is ARM_CP_CONST. Otherwise, if | |
882 | * fieldoffset is non-zero, the reset value of the register. | |
883 | */ | |
884 | uint64_t resetvalue; | |
885 | /* Offset of the field in CPUARMState for this register. This is not | |
886 | * needed if either: | |
887 | * 1. type is ARM_CP_CONST or one of the ARM_CP_SPECIALs | |
888 | * 2. both readfn and writefn are specified | |
889 | */ | |
890 | ptrdiff_t fieldoffset; /* offsetof(CPUARMState, field) */ | |
f59df3f2 PM |
891 | /* Function for making any access checks for this register in addition to |
892 | * those specified by the 'access' permissions bits. If NULL, no extra | |
893 | * checks required. The access check is performed at runtime, not at | |
894 | * translate time. | |
895 | */ | |
896 | CPAccessFn *accessfn; | |
4b6a83fb PM |
897 | /* Function for handling reads of this register. If NULL, then reads |
898 | * will be done by loading from the offset into CPUARMState specified | |
899 | * by fieldoffset. | |
900 | */ | |
901 | CPReadFn *readfn; | |
902 | /* Function for handling writes of this register. If NULL, then writes | |
903 | * will be done by writing to the offset into CPUARMState specified | |
904 | * by fieldoffset. | |
905 | */ | |
906 | CPWriteFn *writefn; | |
7023ec7e PM |
907 | /* Function for doing a "raw" read; used when we need to copy |
908 | * coprocessor state to the kernel for KVM or out for | |
909 | * migration. This only needs to be provided if there is also a | |
c4241c7d | 910 | * readfn and it has side effects (for instance clear-on-read bits). |
7023ec7e PM |
911 | */ |
912 | CPReadFn *raw_readfn; | |
913 | /* Function for doing a "raw" write; used when we need to copy KVM | |
914 | * kernel coprocessor state into userspace, or for inbound | |
915 | * migration. This only needs to be provided if there is also a | |
c4241c7d PM |
916 | * writefn and it masks out "unwritable" bits or has write-one-to-clear |
917 | * or similar behaviour. | |
7023ec7e PM |
918 | */ |
919 | CPWriteFn *raw_writefn; | |
4b6a83fb PM |
920 | /* Function for resetting the register. If NULL, then reset will be done |
921 | * by writing resetvalue to the field specified in fieldoffset. If | |
922 | * fieldoffset is 0 then no reset will be done. | |
923 | */ | |
924 | CPResetFn *resetfn; | |
925 | }; | |
926 | ||
927 | /* Macros which are lvalues for the field in CPUARMState for the | |
928 | * ARMCPRegInfo *ri. | |
929 | */ | |
930 | #define CPREG_FIELD32(env, ri) \ | |
931 | (*(uint32_t *)((char *)(env) + (ri)->fieldoffset)) | |
932 | #define CPREG_FIELD64(env, ri) \ | |
933 | (*(uint64_t *)((char *)(env) + (ri)->fieldoffset)) | |
934 | ||
935 | #define REGINFO_SENTINEL { .type = ARM_CP_SENTINEL } | |
936 | ||
937 | void define_arm_cp_regs_with_opaque(ARMCPU *cpu, | |
938 | const ARMCPRegInfo *regs, void *opaque); | |
939 | void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu, | |
940 | const ARMCPRegInfo *regs, void *opaque); | |
941 | static inline void define_arm_cp_regs(ARMCPU *cpu, const ARMCPRegInfo *regs) | |
942 | { | |
943 | define_arm_cp_regs_with_opaque(cpu, regs, 0); | |
944 | } | |
945 | static inline void define_one_arm_cp_reg(ARMCPU *cpu, const ARMCPRegInfo *regs) | |
946 | { | |
947 | define_one_arm_cp_reg_with_opaque(cpu, regs, 0); | |
948 | } | |
60322b39 | 949 | const ARMCPRegInfo *get_arm_cp_reginfo(GHashTable *cpregs, uint32_t encoded_cp); |
4b6a83fb PM |
950 | |
951 | /* CPWriteFn that can be used to implement writes-ignored behaviour */ | |
c4241c7d PM |
952 | void arm_cp_write_ignore(CPUARMState *env, const ARMCPRegInfo *ri, |
953 | uint64_t value); | |
4b6a83fb | 954 | /* CPReadFn that can be used for read-as-zero behaviour */ |
c4241c7d | 955 | uint64_t arm_cp_read_zero(CPUARMState *env, const ARMCPRegInfo *ri); |
4b6a83fb | 956 | |
f5a0a5a5 PM |
957 | /* CPResetFn that does nothing, for use if no reset is required even |
958 | * if fieldoffset is non zero. | |
959 | */ | |
960 | void arm_cp_reset_ignore(CPUARMState *env, const ARMCPRegInfo *opaque); | |
961 | ||
60322b39 | 962 | static inline bool cp_access_ok(int current_pl, |
4b6a83fb PM |
963 | const ARMCPRegInfo *ri, int isread) |
964 | { | |
60322b39 | 965 | return (ri->access >> ((current_pl * 2) + isread)) & 1; |
4b6a83fb PM |
966 | } |
967 | ||
721fae12 PM |
968 | /** |
969 | * write_list_to_cpustate | |
970 | * @cpu: ARMCPU | |
971 | * | |
972 | * For each register listed in the ARMCPU cpreg_indexes list, write | |
973 | * its value from the cpreg_values list into the ARMCPUState structure. | |
974 | * This updates TCG's working data structures from KVM data or | |
975 | * from incoming migration state. | |
976 | * | |
977 | * Returns: true if all register values were updated correctly, | |
978 | * false if some register was unknown or could not be written. | |
979 | * Note that we do not stop early on failure -- we will attempt | |
980 | * writing all registers in the list. | |
981 | */ | |
982 | bool write_list_to_cpustate(ARMCPU *cpu); | |
983 | ||
984 | /** | |
985 | * write_cpustate_to_list: | |
986 | * @cpu: ARMCPU | |
987 | * | |
988 | * For each register listed in the ARMCPU cpreg_indexes list, write | |
989 | * its value from the ARMCPUState structure into the cpreg_values list. | |
990 | * This is used to copy info from TCG's working data structures into | |
991 | * KVM or for outbound migration. | |
992 | * | |
993 | * Returns: true if all register values were read correctly, | |
994 | * false if some register was unknown or could not be read. | |
995 | * Note that we do not stop early on failure -- we will attempt | |
996 | * reading all registers in the list. | |
997 | */ | |
998 | bool write_cpustate_to_list(ARMCPU *cpu); | |
999 | ||
9ee6e8bb PB |
1000 | /* Does the core conform to the the "MicroController" profile. e.g. Cortex-M3. |
1001 | Note the M in older cores (eg. ARM7TDMI) stands for Multiply. These are | |
1002 | conventional cores (ie. Application or Realtime profile). */ | |
1003 | ||
1004 | #define IS_M(env) arm_feature(env, ARM_FEATURE_M) | |
9ee6e8bb | 1005 | |
9ee6e8bb PB |
1006 | #define ARM_CPUID_TI915T 0x54029152 |
1007 | #define ARM_CPUID_TI925T 0x54029252 | |
40f137e1 | 1008 | |
b5ff1b31 | 1009 | #if defined(CONFIG_USER_ONLY) |
2c0262af | 1010 | #define TARGET_PAGE_BITS 12 |
b5ff1b31 FB |
1011 | #else |
1012 | /* The ARM MMU allows 1k pages. */ | |
1013 | /* ??? Linux doesn't actually use these, and they're deprecated in recent | |
82d17978 | 1014 | architecture revisions. Maybe a configure option to disable them. */ |
b5ff1b31 FB |
1015 | #define TARGET_PAGE_BITS 10 |
1016 | #endif | |
9467d44c | 1017 | |
3926cc84 AG |
1018 | #if defined(TARGET_AARCH64) |
1019 | # define TARGET_PHYS_ADDR_SPACE_BITS 48 | |
1020 | # define TARGET_VIRT_ADDR_SPACE_BITS 64 | |
1021 | #else | |
1022 | # define TARGET_PHYS_ADDR_SPACE_BITS 40 | |
1023 | # define TARGET_VIRT_ADDR_SPACE_BITS 32 | |
1024 | #endif | |
52705890 | 1025 | |
ad37ad5b PM |
1026 | static inline CPUARMState *cpu_init(const char *cpu_model) |
1027 | { | |
1028 | ARMCPU *cpu = cpu_arm_init(cpu_model); | |
1029 | if (cpu) { | |
1030 | return &cpu->env; | |
1031 | } | |
1032 | return NULL; | |
1033 | } | |
1034 | ||
9467d44c TS |
1035 | #define cpu_exec cpu_arm_exec |
1036 | #define cpu_gen_code cpu_arm_gen_code | |
1037 | #define cpu_signal_handler cpu_arm_signal_handler | |
c732abe2 | 1038 | #define cpu_list arm_cpu_list |
9467d44c | 1039 | |
6ebbf390 JM |
1040 | /* MMU modes definitions */ |
1041 | #define MMU_MODE0_SUFFIX _kernel | |
1042 | #define MMU_MODE1_SUFFIX _user | |
1043 | #define MMU_USER_IDX 1 | |
0ecb72a5 | 1044 | static inline int cpu_mmu_index (CPUARMState *env) |
6ebbf390 JM |
1045 | { |
1046 | return (env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_USR ? 1 : 0; | |
1047 | } | |
1048 | ||
022c62cb | 1049 | #include "exec/cpu-all.h" |
622ed360 | 1050 | |
3926cc84 AG |
1051 | /* Bit usage in the TB flags field: bit 31 indicates whether we are |
1052 | * in 32 or 64 bit mode. The meaning of the other bits depends on that. | |
1053 | */ | |
1054 | #define ARM_TBFLAG_AARCH64_STATE_SHIFT 31 | |
1055 | #define ARM_TBFLAG_AARCH64_STATE_MASK (1U << ARM_TBFLAG_AARCH64_STATE_SHIFT) | |
1056 | ||
1057 | /* Bit usage when in AArch32 state: */ | |
a1705768 PM |
1058 | #define ARM_TBFLAG_THUMB_SHIFT 0 |
1059 | #define ARM_TBFLAG_THUMB_MASK (1 << ARM_TBFLAG_THUMB_SHIFT) | |
1060 | #define ARM_TBFLAG_VECLEN_SHIFT 1 | |
1061 | #define ARM_TBFLAG_VECLEN_MASK (0x7 << ARM_TBFLAG_VECLEN_SHIFT) | |
1062 | #define ARM_TBFLAG_VECSTRIDE_SHIFT 4 | |
1063 | #define ARM_TBFLAG_VECSTRIDE_MASK (0x3 << ARM_TBFLAG_VECSTRIDE_SHIFT) | |
1064 | #define ARM_TBFLAG_PRIV_SHIFT 6 | |
1065 | #define ARM_TBFLAG_PRIV_MASK (1 << ARM_TBFLAG_PRIV_SHIFT) | |
1066 | #define ARM_TBFLAG_VFPEN_SHIFT 7 | |
1067 | #define ARM_TBFLAG_VFPEN_MASK (1 << ARM_TBFLAG_VFPEN_SHIFT) | |
1068 | #define ARM_TBFLAG_CONDEXEC_SHIFT 8 | |
1069 | #define ARM_TBFLAG_CONDEXEC_MASK (0xff << ARM_TBFLAG_CONDEXEC_SHIFT) | |
d8fd2954 PB |
1070 | #define ARM_TBFLAG_BSWAP_CODE_SHIFT 16 |
1071 | #define ARM_TBFLAG_BSWAP_CODE_MASK (1 << ARM_TBFLAG_BSWAP_CODE_SHIFT) | |
3926cc84 AG |
1072 | |
1073 | /* Bit usage when in AArch64 state: currently no bits defined */ | |
a1705768 PM |
1074 | |
1075 | /* some convenience accessor macros */ | |
3926cc84 AG |
1076 | #define ARM_TBFLAG_AARCH64_STATE(F) \ |
1077 | (((F) & ARM_TBFLAG_AARCH64_STATE_MASK) >> ARM_TBFLAG_AARCH64_STATE_SHIFT) | |
a1705768 PM |
1078 | #define ARM_TBFLAG_THUMB(F) \ |
1079 | (((F) & ARM_TBFLAG_THUMB_MASK) >> ARM_TBFLAG_THUMB_SHIFT) | |
1080 | #define ARM_TBFLAG_VECLEN(F) \ | |
1081 | (((F) & ARM_TBFLAG_VECLEN_MASK) >> ARM_TBFLAG_VECLEN_SHIFT) | |
1082 | #define ARM_TBFLAG_VECSTRIDE(F) \ | |
1083 | (((F) & ARM_TBFLAG_VECSTRIDE_MASK) >> ARM_TBFLAG_VECSTRIDE_SHIFT) | |
1084 | #define ARM_TBFLAG_PRIV(F) \ | |
1085 | (((F) & ARM_TBFLAG_PRIV_MASK) >> ARM_TBFLAG_PRIV_SHIFT) | |
1086 | #define ARM_TBFLAG_VFPEN(F) \ | |
1087 | (((F) & ARM_TBFLAG_VFPEN_MASK) >> ARM_TBFLAG_VFPEN_SHIFT) | |
1088 | #define ARM_TBFLAG_CONDEXEC(F) \ | |
1089 | (((F) & ARM_TBFLAG_CONDEXEC_MASK) >> ARM_TBFLAG_CONDEXEC_SHIFT) | |
d8fd2954 PB |
1090 | #define ARM_TBFLAG_BSWAP_CODE(F) \ |
1091 | (((F) & ARM_TBFLAG_BSWAP_CODE_MASK) >> ARM_TBFLAG_BSWAP_CODE_SHIFT) | |
a1705768 | 1092 | |
0ecb72a5 | 1093 | static inline void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, |
6b917547 AL |
1094 | target_ulong *cs_base, int *flags) |
1095 | { | |
3926cc84 AG |
1096 | if (is_a64(env)) { |
1097 | *pc = env->pc; | |
1098 | *flags = ARM_TBFLAG_AARCH64_STATE_MASK; | |
05ed9a99 | 1099 | } else { |
3926cc84 AG |
1100 | int privmode; |
1101 | *pc = env->regs[15]; | |
1102 | *flags = (env->thumb << ARM_TBFLAG_THUMB_SHIFT) | |
1103 | | (env->vfp.vec_len << ARM_TBFLAG_VECLEN_SHIFT) | |
1104 | | (env->vfp.vec_stride << ARM_TBFLAG_VECSTRIDE_SHIFT) | |
1105 | | (env->condexec_bits << ARM_TBFLAG_CONDEXEC_SHIFT) | |
1106 | | (env->bswap_code << ARM_TBFLAG_BSWAP_CODE_SHIFT); | |
1107 | if (arm_feature(env, ARM_FEATURE_M)) { | |
1108 | privmode = !((env->v7m.exception == 0) && (env->v7m.control & 1)); | |
1109 | } else { | |
1110 | privmode = (env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR; | |
1111 | } | |
1112 | if (privmode) { | |
1113 | *flags |= ARM_TBFLAG_PRIV_MASK; | |
1114 | } | |
1115 | if (env->vfp.xregs[ARM_VFP_FPEXC] & (1 << 30)) { | |
1116 | *flags |= ARM_TBFLAG_VFPEN_MASK; | |
1117 | } | |
a1705768 | 1118 | } |
3926cc84 AG |
1119 | |
1120 | *cs_base = 0; | |
6b917547 AL |
1121 | } |
1122 | ||
3993c6bd | 1123 | static inline bool cpu_has_work(CPUState *cpu) |
f081c76c | 1124 | { |
259186a7 | 1125 | return cpu->interrupt_request & |
f081c76c BS |
1126 | (CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD | CPU_INTERRUPT_EXITTB); |
1127 | } | |
1128 | ||
022c62cb | 1129 | #include "exec/exec-all.h" |
f081c76c | 1130 | |
3926cc84 AG |
1131 | static inline void cpu_pc_from_tb(CPUARMState *env, TranslationBlock *tb) |
1132 | { | |
1133 | if (ARM_TBFLAG_AARCH64_STATE(tb->flags)) { | |
1134 | env->pc = tb->pc; | |
1135 | } else { | |
1136 | env->regs[15] = tb->pc; | |
1137 | } | |
1138 | } | |
1139 | ||
d8fd2954 | 1140 | /* Load an instruction and return it in the standard little-endian order */ |
0a2461fa | 1141 | static inline uint32_t arm_ldl_code(CPUARMState *env, target_ulong addr, |
d31dd73e | 1142 | bool do_swap) |
d8fd2954 | 1143 | { |
d31dd73e | 1144 | uint32_t insn = cpu_ldl_code(env, addr); |
d8fd2954 PB |
1145 | if (do_swap) { |
1146 | return bswap32(insn); | |
1147 | } | |
1148 | return insn; | |
1149 | } | |
1150 | ||
1151 | /* Ditto, for a halfword (Thumb) instruction */ | |
0a2461fa | 1152 | static inline uint16_t arm_lduw_code(CPUARMState *env, target_ulong addr, |
d31dd73e | 1153 | bool do_swap) |
d8fd2954 | 1154 | { |
d31dd73e | 1155 | uint16_t insn = cpu_lduw_code(env, addr); |
d8fd2954 PB |
1156 | if (do_swap) { |
1157 | return bswap16(insn); | |
1158 | } | |
1159 | return insn; | |
1160 | } | |
1161 | ||
2c0262af | 1162 | #endif |