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2c0262af FB |
1 | /* |
2 | * ARM virtual CPU header | |
5fafdf24 | 3 | * |
2c0262af FB |
4 | * Copyright (c) 2003 Fabrice Bellard |
5 | * | |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
9 | * version 2 of the License, or (at your option) any later version. | |
10 | * | |
11 | * This library is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU Lesser General Public | |
8167ee88 | 17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. |
2c0262af FB |
18 | */ |
19 | #ifndef CPU_ARM_H | |
20 | #define CPU_ARM_H | |
21 | ||
3926cc84 | 22 | #include "config.h" |
3cf1e035 | 23 | |
72b0cd35 PM |
24 | #include "kvm-consts.h" |
25 | ||
3926cc84 AG |
26 | #if defined(TARGET_AARCH64) |
27 | /* AArch64 definitions */ | |
28 | # define TARGET_LONG_BITS 64 | |
29 | # define ELF_MACHINE EM_AARCH64 | |
30 | #else | |
31 | # define TARGET_LONG_BITS 32 | |
32 | # define ELF_MACHINE EM_ARM | |
33 | #endif | |
9042c0e2 | 34 | |
9349b4f9 | 35 | #define CPUArchState struct CPUARMState |
c2764719 | 36 | |
9a78eead | 37 | #include "qemu-common.h" |
022c62cb | 38 | #include "exec/cpu-defs.h" |
2c0262af | 39 | |
6b4c305c | 40 | #include "fpu/softfloat.h" |
53cd6637 | 41 | |
1fddef4b FB |
42 | #define TARGET_HAS_ICE 1 |
43 | ||
b8a9e8f1 FB |
44 | #define EXCP_UDEF 1 /* undefined instruction */ |
45 | #define EXCP_SWI 2 /* software interrupt */ | |
46 | #define EXCP_PREFETCH_ABORT 3 | |
47 | #define EXCP_DATA_ABORT 4 | |
b5ff1b31 FB |
48 | #define EXCP_IRQ 5 |
49 | #define EXCP_FIQ 6 | |
06c949e6 | 50 | #define EXCP_BKPT 7 |
9ee6e8bb | 51 | #define EXCP_EXCEPTION_EXIT 8 /* Return from v7M exception. */ |
fbb4a2e3 | 52 | #define EXCP_KERNEL_TRAP 9 /* Jumped to kernel code page. */ |
426f5abc | 53 | #define EXCP_STREX 10 |
9ee6e8bb PB |
54 | |
55 | #define ARMV7M_EXCP_RESET 1 | |
56 | #define ARMV7M_EXCP_NMI 2 | |
57 | #define ARMV7M_EXCP_HARD 3 | |
58 | #define ARMV7M_EXCP_MEM 4 | |
59 | #define ARMV7M_EXCP_BUS 5 | |
60 | #define ARMV7M_EXCP_USAGE 6 | |
61 | #define ARMV7M_EXCP_SVC 11 | |
62 | #define ARMV7M_EXCP_DEBUG 12 | |
63 | #define ARMV7M_EXCP_PENDSV 14 | |
64 | #define ARMV7M_EXCP_SYSTICK 15 | |
2c0262af | 65 | |
403946c0 RH |
66 | /* ARM-specific interrupt pending bits. */ |
67 | #define CPU_INTERRUPT_FIQ CPU_INTERRUPT_TGT_EXT_1 | |
68 | ||
e4fe830b PM |
69 | /* The usual mapping for an AArch64 system register to its AArch32 |
70 | * counterpart is for the 32 bit world to have access to the lower | |
71 | * half only (with writes leaving the upper half untouched). It's | |
72 | * therefore useful to be able to pass TCG the offset of the least | |
73 | * significant half of a uint64_t struct member. | |
74 | */ | |
75 | #ifdef HOST_WORDS_BIGENDIAN | |
5cd8a118 | 76 | #define offsetoflow32(S, M) (offsetof(S, M) + sizeof(uint32_t)) |
b0fe2427 | 77 | #define offsetofhigh32(S, M) offsetof(S, M) |
e4fe830b PM |
78 | #else |
79 | #define offsetoflow32(S, M) offsetof(S, M) | |
b0fe2427 | 80 | #define offsetofhigh32(S, M) (offsetof(S, M) + sizeof(uint32_t)) |
e4fe830b PM |
81 | #endif |
82 | ||
7c1840b6 PM |
83 | /* Meanings of the ARMCPU object's two inbound GPIO lines */ |
84 | #define ARM_CPU_IRQ 0 | |
85 | #define ARM_CPU_FIQ 1 | |
403946c0 | 86 | |
c1713132 AZ |
87 | typedef void ARMWriteCPFunc(void *opaque, int cp_info, |
88 | int srcreg, int operand, uint32_t value); | |
89 | typedef uint32_t ARMReadCPFunc(void *opaque, int cp_info, | |
90 | int dstreg, int operand); | |
91 | ||
f93eb9ff AZ |
92 | struct arm_boot_info; |
93 | ||
6ebbf390 JM |
94 | #define NB_MMU_MODES 2 |
95 | ||
b7bcbe95 FB |
96 | /* We currently assume float and double are IEEE single and double |
97 | precision respectively. | |
98 | Doing runtime conversions is tricky because VFP registers may contain | |
99 | integer values (eg. as the result of a FTOSI instruction). | |
8e96005d FB |
100 | s<2n> maps to the least significant half of d<n> |
101 | s<2n+1> maps to the most significant half of d<n> | |
102 | */ | |
b7bcbe95 | 103 | |
55d284af PM |
104 | /* CPU state for each instance of a generic timer (in cp15 c14) */ |
105 | typedef struct ARMGenericTimer { | |
106 | uint64_t cval; /* Timer CompareValue register */ | |
107 | uint32_t ctl; /* Timer Control register */ | |
108 | } ARMGenericTimer; | |
109 | ||
110 | #define GTIMER_PHYS 0 | |
111 | #define GTIMER_VIRT 1 | |
112 | #define NUM_GTIMERS 2 | |
113 | ||
114 | /* Scale factor for generic timers, ie number of ns per tick. | |
115 | * This gives a 62.5MHz timer. | |
116 | */ | |
117 | #define GTIMER_SCALE 16 | |
118 | ||
2c0262af | 119 | typedef struct CPUARMState { |
b5ff1b31 | 120 | /* Regs for current mode. */ |
2c0262af | 121 | uint32_t regs[16]; |
3926cc84 AG |
122 | |
123 | /* 32/64 switch only happens when taking and returning from | |
124 | * exceptions so the overlap semantics are taken care of then | |
125 | * instead of having a complicated union. | |
126 | */ | |
127 | /* Regs for A64 mode. */ | |
128 | uint64_t xregs[32]; | |
129 | uint64_t pc; | |
d356312f PM |
130 | /* PSTATE isn't an architectural register for ARMv8. However, it is |
131 | * convenient for us to assemble the underlying state into a 32 bit format | |
132 | * identical to the architectural format used for the SPSR. (This is also | |
133 | * what the Linux kernel's 'pstate' field in signal handlers and KVM's | |
134 | * 'pstate' register are.) Of the PSTATE bits: | |
135 | * NZCV are kept in the split out env->CF/VF/NF/ZF, (which have the same | |
136 | * semantics as for AArch32, as described in the comments on each field) | |
137 | * nRW (also known as M[4]) is kept, inverted, in env->aarch64 | |
138 | * all other bits are stored in their correct places in env->pstate | |
3926cc84 AG |
139 | */ |
140 | uint32_t pstate; | |
141 | uint32_t aarch64; /* 1 if CPU is in aarch64 state; inverse of PSTATE.nRW */ | |
142 | ||
b90372ad | 143 | /* Frequently accessed CPSR bits are stored separately for efficiency. |
d37aca66 | 144 | This contains all the other bits. Use cpsr_{read,write} to access |
b5ff1b31 FB |
145 | the whole CPSR. */ |
146 | uint32_t uncached_cpsr; | |
147 | uint32_t spsr; | |
148 | ||
149 | /* Banked registers. */ | |
150 | uint32_t banked_spsr[6]; | |
151 | uint32_t banked_r13[6]; | |
152 | uint32_t banked_r14[6]; | |
3b46e624 | 153 | |
b5ff1b31 FB |
154 | /* These hold r8-r12. */ |
155 | uint32_t usr_regs[5]; | |
156 | uint32_t fiq_regs[5]; | |
3b46e624 | 157 | |
2c0262af FB |
158 | /* cpsr flag cache for faster execution */ |
159 | uint32_t CF; /* 0 or 1 */ | |
160 | uint32_t VF; /* V is the bit 31. All other bits are undefined */ | |
6fbe23d5 PB |
161 | uint32_t NF; /* N is bit 31. All other bits are undefined. */ |
162 | uint32_t ZF; /* Z set if zero. */ | |
99c475ab | 163 | uint32_t QF; /* 0 or 1 */ |
9ee6e8bb | 164 | uint32_t GE; /* cpsr[19:16] */ |
b26eefb6 | 165 | uint32_t thumb; /* cpsr[5]. 0 = arm mode, 1 = thumb mode. */ |
9ee6e8bb | 166 | uint32_t condexec_bits; /* IT bits. cpsr[15:10,26:25]. */ |
2c0262af | 167 | |
b5ff1b31 FB |
168 | /* System control coprocessor (cp15) */ |
169 | struct { | |
40f137e1 | 170 | uint32_t c0_cpuid; |
7da845b0 | 171 | uint64_t c0_cssel; /* Cache size selection. */ |
b5ff1b31 FB |
172 | uint32_t c1_sys; /* System control register. */ |
173 | uint32_t c1_coproc; /* Coprocessor access register. */ | |
610c3c8a | 174 | uint32_t c1_xscaleauxcr; /* XScale auxiliary control register. */ |
2be27624 | 175 | uint32_t c1_scr; /* secure config register. */ |
9ee6e8bb | 176 | uint32_t c2_base0; /* MMU translation table base 0. */ |
891a2fe7 PM |
177 | uint32_t c2_base0_hi; /* MMU translation table base 0, high 32 bits */ |
178 | uint32_t c2_base1; /* MMU translation table base 0. */ | |
179 | uint32_t c2_base1_hi; /* MMU translation table base 1, high 32 bits */ | |
b2fa1797 PB |
180 | uint32_t c2_control; /* MMU translation table base control. */ |
181 | uint32_t c2_mask; /* MMU translation table base selection mask. */ | |
182 | uint32_t c2_base_mask; /* MMU translation table base 0 mask. */ | |
ce819861 PB |
183 | uint32_t c2_data; /* MPU data cachable bits. */ |
184 | uint32_t c2_insn; /* MPU instruction cachable bits. */ | |
185 | uint32_t c3; /* MMU domain access control register | |
186 | MPU write buffer control. */ | |
b5ff1b31 FB |
187 | uint32_t c5_insn; /* Fault status registers. */ |
188 | uint32_t c5_data; | |
ce819861 | 189 | uint32_t c6_region[8]; /* MPU base/size registers. */ |
b5ff1b31 FB |
190 | uint32_t c6_insn; /* Fault address registers. */ |
191 | uint32_t c6_data; | |
f8bf8606 | 192 | uint32_t c7_par; /* Translation result. */ |
891a2fe7 | 193 | uint32_t c7_par_hi; /* Translation result, high 32 bits */ |
b5ff1b31 FB |
194 | uint32_t c9_insn; /* Cache lockdown registers. */ |
195 | uint32_t c9_data; | |
74594c9d PM |
196 | uint32_t c9_pmcr; /* performance monitor control register */ |
197 | uint32_t c9_pmcnten; /* perf monitor counter enables */ | |
198 | uint32_t c9_pmovsr; /* perf monitor overflow status */ | |
199 | uint32_t c9_pmxevtyper; /* perf monitor event type */ | |
200 | uint32_t c9_pmuserenr; /* perf monitor user enable */ | |
201 | uint32_t c9_pminten; /* perf monitor interrupt enables */ | |
b0fe2427 | 202 | uint64_t mair_el1; |
8641136c | 203 | uint32_t c12_vbar; /* vector base address register */ |
b5ff1b31 FB |
204 | uint32_t c13_fcse; /* FCSE PID. */ |
205 | uint32_t c13_context; /* Context ID. */ | |
e4fe830b PM |
206 | uint64_t tpidr_el0; /* User RW Thread register. */ |
207 | uint64_t tpidrro_el0; /* User RO Thread register. */ | |
208 | uint64_t tpidr_el1; /* Privileged Thread register. */ | |
55d284af PM |
209 | uint32_t c14_cntfrq; /* Counter Frequency register */ |
210 | uint32_t c14_cntkctl; /* Timer Control register */ | |
211 | ARMGenericTimer c14_timer[NUM_GTIMERS]; | |
c1713132 | 212 | uint32_t c15_cpar; /* XScale Coprocessor Access Register */ |
c3d2689d AZ |
213 | uint32_t c15_ticonfig; /* TI925T configuration byte. */ |
214 | uint32_t c15_i_max; /* Maximum D-cache dirty line index. */ | |
215 | uint32_t c15_i_min; /* Minimum D-cache dirty line index. */ | |
216 | uint32_t c15_threadid; /* TI debugger thread-ID. */ | |
7da362d0 ML |
217 | uint32_t c15_config_base_address; /* SCU base address. */ |
218 | uint32_t c15_diagnostic; /* diagnostic register */ | |
219 | uint32_t c15_power_diagnostic; | |
220 | uint32_t c15_power_control; /* power control */ | |
b5ff1b31 | 221 | } cp15; |
40f137e1 | 222 | |
9ee6e8bb PB |
223 | struct { |
224 | uint32_t other_sp; | |
225 | uint32_t vecbase; | |
226 | uint32_t basepri; | |
227 | uint32_t control; | |
228 | int current_sp; | |
229 | int exception; | |
230 | int pending_exception; | |
9ee6e8bb PB |
231 | } v7m; |
232 | ||
fe1479c3 PB |
233 | /* Thumb-2 EE state. */ |
234 | uint32_t teecr; | |
235 | uint32_t teehbr; | |
236 | ||
b7bcbe95 FB |
237 | /* VFP coprocessor state. */ |
238 | struct { | |
3926cc84 AG |
239 | /* VFP/Neon register state. Note that the mapping between S, D and Q |
240 | * views of the register bank differs between AArch64 and AArch32: | |
241 | * In AArch32: | |
242 | * Qn = regs[2n+1]:regs[2n] | |
243 | * Dn = regs[n] | |
244 | * Sn = regs[n/2] bits 31..0 for even n, and bits 63..32 for odd n | |
245 | * (and regs[32] to regs[63] are inaccessible) | |
246 | * In AArch64: | |
247 | * Qn = regs[2n+1]:regs[2n] | |
248 | * Dn = regs[2n] | |
249 | * Sn = regs[2n] bits 31..0 | |
250 | * This corresponds to the architecturally defined mapping between | |
251 | * the two execution states, and means we do not need to explicitly | |
252 | * map these registers when changing states. | |
253 | */ | |
254 | float64 regs[64]; | |
b7bcbe95 | 255 | |
40f137e1 | 256 | uint32_t xregs[16]; |
b7bcbe95 FB |
257 | /* We store these fpcsr fields separately for convenience. */ |
258 | int vec_len; | |
259 | int vec_stride; | |
260 | ||
9ee6e8bb PB |
261 | /* scratch space when Tn are not sufficient. */ |
262 | uint32_t scratch[8]; | |
3b46e624 | 263 | |
3a492f3a PM |
264 | /* fp_status is the "normal" fp status. standard_fp_status retains |
265 | * values corresponding to the ARM "Standard FPSCR Value", ie | |
266 | * default-NaN, flush-to-zero, round-to-nearest and is used by | |
267 | * any operations (generally Neon) which the architecture defines | |
268 | * as controlled by the standard FPSCR value rather than the FPSCR. | |
269 | * | |
270 | * To avoid having to transfer exception bits around, we simply | |
271 | * say that the FPSCR cumulative exception flags are the logical | |
272 | * OR of the flags in the two fp statuses. This relies on the | |
273 | * only thing which needs to read the exception flags being | |
274 | * an explicit FPSCR read. | |
275 | */ | |
53cd6637 | 276 | float_status fp_status; |
3a492f3a | 277 | float_status standard_fp_status; |
b7bcbe95 | 278 | } vfp; |
03d05e2d PM |
279 | uint64_t exclusive_addr; |
280 | uint64_t exclusive_val; | |
281 | uint64_t exclusive_high; | |
9ee6e8bb | 282 | #if defined(CONFIG_USER_ONLY) |
03d05e2d | 283 | uint64_t exclusive_test; |
426f5abc | 284 | uint32_t exclusive_info; |
9ee6e8bb | 285 | #endif |
b7bcbe95 | 286 | |
18c9b560 AZ |
287 | /* iwMMXt coprocessor state. */ |
288 | struct { | |
289 | uint64_t regs[16]; | |
290 | uint64_t val; | |
291 | ||
292 | uint32_t cregs[16]; | |
293 | } iwmmxt; | |
294 | ||
d8fd2954 PB |
295 | /* For mixed endian mode. */ |
296 | bool bswap_code; | |
297 | ||
ce4defa0 PB |
298 | #if defined(CONFIG_USER_ONLY) |
299 | /* For usermode syscall translation. */ | |
300 | int eabi; | |
301 | #endif | |
302 | ||
a316d335 FB |
303 | CPU_COMMON |
304 | ||
9d551997 | 305 | /* These fields after the common ones so they are preserved on reset. */ |
9ba8c3f4 | 306 | |
581be094 | 307 | /* Internal CPU feature flags. */ |
918f5dca | 308 | uint64_t features; |
581be094 | 309 | |
983fe826 | 310 | void *nvic; |
462a8bc6 | 311 | const struct arm_boot_info *boot_info; |
2c0262af FB |
312 | } CPUARMState; |
313 | ||
778c3a06 AF |
314 | #include "cpu-qom.h" |
315 | ||
316 | ARMCPU *cpu_arm_init(const char *cpu_model); | |
b26eefb6 | 317 | void arm_translate_init(void); |
14969266 | 318 | void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu); |
2c0262af | 319 | int cpu_arm_exec(CPUARMState *s); |
494b00c7 | 320 | int bank_number(int mode); |
b5ff1b31 | 321 | void switch_mode(CPUARMState *, int); |
9ee6e8bb | 322 | uint32_t do_arm_semihosting(CPUARMState *env); |
b5ff1b31 | 323 | |
3926cc84 AG |
324 | static inline bool is_a64(CPUARMState *env) |
325 | { | |
326 | return env->aarch64; | |
327 | } | |
328 | ||
2c0262af FB |
329 | /* you can call this signal handler from your SIGBUS and SIGSEGV |
330 | signal handlers to inform the virtual CPU of exceptions. non zero | |
331 | is returned if the signal was handled by the virtual CPU. */ | |
5fafdf24 | 332 | int cpu_arm_signal_handler(int host_signum, void *pinfo, |
2c0262af | 333 | void *puc); |
84a031c6 | 334 | int cpu_arm_handle_mmu_fault (CPUARMState *env, target_ulong address, int rw, |
97b348e7 | 335 | int mmu_idx); |
0b5c1ce8 | 336 | #define cpu_handle_mmu_fault cpu_arm_handle_mmu_fault |
2c0262af | 337 | |
76e3e1bc PM |
338 | /* SCTLR bit meanings. Several bits have been reused in newer |
339 | * versions of the architecture; in that case we define constants | |
340 | * for both old and new bit meanings. Code which tests against those | |
341 | * bits should probably check or otherwise arrange that the CPU | |
342 | * is the architectural version it expects. | |
343 | */ | |
344 | #define SCTLR_M (1U << 0) | |
345 | #define SCTLR_A (1U << 1) | |
346 | #define SCTLR_C (1U << 2) | |
347 | #define SCTLR_W (1U << 3) /* up to v6; RAO in v7 */ | |
348 | #define SCTLR_SA (1U << 3) | |
349 | #define SCTLR_P (1U << 4) /* up to v5; RAO in v6 and v7 */ | |
350 | #define SCTLR_SA0 (1U << 4) /* v8 onward, AArch64 only */ | |
351 | #define SCTLR_D (1U << 5) /* up to v5; RAO in v6 */ | |
352 | #define SCTLR_CP15BEN (1U << 5) /* v7 onward */ | |
353 | #define SCTLR_L (1U << 6) /* up to v5; RAO in v6 and v7; RAZ in v8 */ | |
354 | #define SCTLR_B (1U << 7) /* up to v6; RAZ in v7 */ | |
355 | #define SCTLR_ITD (1U << 7) /* v8 onward */ | |
356 | #define SCTLR_S (1U << 8) /* up to v6; RAZ in v7 */ | |
357 | #define SCTLR_SED (1U << 8) /* v8 onward */ | |
358 | #define SCTLR_R (1U << 9) /* up to v6; RAZ in v7 */ | |
359 | #define SCTLR_UMA (1U << 9) /* v8 onward, AArch64 only */ | |
360 | #define SCTLR_F (1U << 10) /* up to v6 */ | |
361 | #define SCTLR_SW (1U << 10) /* v7 onward */ | |
362 | #define SCTLR_Z (1U << 11) | |
363 | #define SCTLR_I (1U << 12) | |
364 | #define SCTLR_V (1U << 13) | |
365 | #define SCTLR_RR (1U << 14) /* up to v7 */ | |
366 | #define SCTLR_DZE (1U << 14) /* v8 onward, AArch64 only */ | |
367 | #define SCTLR_L4 (1U << 15) /* up to v6; RAZ in v7 */ | |
368 | #define SCTLR_UCT (1U << 15) /* v8 onward, AArch64 only */ | |
369 | #define SCTLR_DT (1U << 16) /* up to ??, RAO in v6 and v7 */ | |
370 | #define SCTLR_nTWI (1U << 16) /* v8 onward */ | |
371 | #define SCTLR_HA (1U << 17) | |
372 | #define SCTLR_IT (1U << 18) /* up to ??, RAO in v6 and v7 */ | |
373 | #define SCTLR_nTWE (1U << 18) /* v8 onward */ | |
374 | #define SCTLR_WXN (1U << 19) | |
375 | #define SCTLR_ST (1U << 20) /* up to ??, RAZ in v6 */ | |
376 | #define SCTLR_UWXN (1U << 20) /* v7 onward */ | |
377 | #define SCTLR_FI (1U << 21) | |
378 | #define SCTLR_U (1U << 22) | |
379 | #define SCTLR_XP (1U << 23) /* up to v6; v7 onward RAO */ | |
380 | #define SCTLR_VE (1U << 24) /* up to v7 */ | |
381 | #define SCTLR_E0E (1U << 24) /* v8 onward, AArch64 only */ | |
382 | #define SCTLR_EE (1U << 25) | |
383 | #define SCTLR_L2 (1U << 26) /* up to v6, RAZ in v7 */ | |
384 | #define SCTLR_UCI (1U << 26) /* v8 onward, AArch64 only */ | |
385 | #define SCTLR_NMFI (1U << 27) | |
386 | #define SCTLR_TRE (1U << 28) | |
387 | #define SCTLR_AFE (1U << 29) | |
388 | #define SCTLR_TE (1U << 30) | |
389 | ||
78dbbbe4 PM |
390 | #define CPSR_M (0x1fU) |
391 | #define CPSR_T (1U << 5) | |
392 | #define CPSR_F (1U << 6) | |
393 | #define CPSR_I (1U << 7) | |
394 | #define CPSR_A (1U << 8) | |
395 | #define CPSR_E (1U << 9) | |
396 | #define CPSR_IT_2_7 (0xfc00U) | |
397 | #define CPSR_GE (0xfU << 16) | |
398 | #define CPSR_RESERVED (0xfU << 20) | |
399 | #define CPSR_J (1U << 24) | |
400 | #define CPSR_IT_0_1 (3U << 25) | |
401 | #define CPSR_Q (1U << 27) | |
402 | #define CPSR_V (1U << 28) | |
403 | #define CPSR_C (1U << 29) | |
404 | #define CPSR_Z (1U << 30) | |
405 | #define CPSR_N (1U << 31) | |
9ee6e8bb PB |
406 | #define CPSR_NZCV (CPSR_N | CPSR_Z | CPSR_C | CPSR_V) |
407 | ||
408 | #define CPSR_IT (CPSR_IT_0_1 | CPSR_IT_2_7) | |
409 | #define CACHED_CPSR_BITS (CPSR_T | CPSR_GE | CPSR_IT | CPSR_Q | CPSR_NZCV) | |
410 | /* Bits writable in user mode. */ | |
411 | #define CPSR_USER (CPSR_NZCV | CPSR_Q | CPSR_GE) | |
412 | /* Execution state bits. MRS read as zero, MSR writes ignored. */ | |
413 | #define CPSR_EXEC (CPSR_T | CPSR_IT | CPSR_J) | |
b5ff1b31 | 414 | |
d356312f PM |
415 | /* Bit definitions for ARMv8 SPSR (PSTATE) format. |
416 | * Only these are valid when in AArch64 mode; in | |
417 | * AArch32 mode SPSRs are basically CPSR-format. | |
418 | */ | |
419 | #define PSTATE_M (0xFU) | |
420 | #define PSTATE_nRW (1U << 4) | |
421 | #define PSTATE_F (1U << 6) | |
422 | #define PSTATE_I (1U << 7) | |
423 | #define PSTATE_A (1U << 8) | |
424 | #define PSTATE_D (1U << 9) | |
425 | #define PSTATE_IL (1U << 20) | |
426 | #define PSTATE_SS (1U << 21) | |
427 | #define PSTATE_V (1U << 28) | |
428 | #define PSTATE_C (1U << 29) | |
429 | #define PSTATE_Z (1U << 30) | |
430 | #define PSTATE_N (1U << 31) | |
431 | #define PSTATE_NZCV (PSTATE_N | PSTATE_Z | PSTATE_C | PSTATE_V) | |
432 | #define CACHED_PSTATE_BITS (PSTATE_NZCV) | |
433 | /* Mode values for AArch64 */ | |
434 | #define PSTATE_MODE_EL3h 13 | |
435 | #define PSTATE_MODE_EL3t 12 | |
436 | #define PSTATE_MODE_EL2h 9 | |
437 | #define PSTATE_MODE_EL2t 8 | |
438 | #define PSTATE_MODE_EL1h 5 | |
439 | #define PSTATE_MODE_EL1t 4 | |
440 | #define PSTATE_MODE_EL0t 0 | |
441 | ||
442 | /* Return the current PSTATE value. For the moment we don't support 32<->64 bit | |
443 | * interprocessing, so we don't attempt to sync with the cpsr state used by | |
444 | * the 32 bit decoder. | |
445 | */ | |
446 | static inline uint32_t pstate_read(CPUARMState *env) | |
447 | { | |
448 | int ZF; | |
449 | ||
450 | ZF = (env->ZF == 0); | |
451 | return (env->NF & 0x80000000) | (ZF << 30) | |
452 | | (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | |
453 | | env->pstate; | |
454 | } | |
455 | ||
456 | static inline void pstate_write(CPUARMState *env, uint32_t val) | |
457 | { | |
458 | env->ZF = (~val) & PSTATE_Z; | |
459 | env->NF = val; | |
460 | env->CF = (val >> 29) & 1; | |
461 | env->VF = (val << 3) & 0x80000000; | |
462 | env->pstate = val & ~CACHED_PSTATE_BITS; | |
463 | } | |
464 | ||
b5ff1b31 | 465 | /* Return the current CPSR value. */ |
2f4a40e5 AZ |
466 | uint32_t cpsr_read(CPUARMState *env); |
467 | /* Set the CPSR. Note that some bits of mask must be all-set or all-clear. */ | |
468 | void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask); | |
9ee6e8bb PB |
469 | |
470 | /* Return the current xPSR value. */ | |
471 | static inline uint32_t xpsr_read(CPUARMState *env) | |
472 | { | |
473 | int ZF; | |
6fbe23d5 PB |
474 | ZF = (env->ZF == 0); |
475 | return (env->NF & 0x80000000) | (ZF << 30) | |
9ee6e8bb PB |
476 | | (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27) |
477 | | (env->thumb << 24) | ((env->condexec_bits & 3) << 25) | |
478 | | ((env->condexec_bits & 0xfc) << 8) | |
479 | | env->v7m.exception; | |
b5ff1b31 FB |
480 | } |
481 | ||
9ee6e8bb PB |
482 | /* Set the xPSR. Note that some bits of mask must be all-set or all-clear. */ |
483 | static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask) | |
484 | { | |
9ee6e8bb | 485 | if (mask & CPSR_NZCV) { |
6fbe23d5 PB |
486 | env->ZF = (~val) & CPSR_Z; |
487 | env->NF = val; | |
9ee6e8bb PB |
488 | env->CF = (val >> 29) & 1; |
489 | env->VF = (val << 3) & 0x80000000; | |
490 | } | |
491 | if (mask & CPSR_Q) | |
492 | env->QF = ((val & CPSR_Q) != 0); | |
493 | if (mask & (1 << 24)) | |
494 | env->thumb = ((val & (1 << 24)) != 0); | |
495 | if (mask & CPSR_IT_0_1) { | |
496 | env->condexec_bits &= ~3; | |
497 | env->condexec_bits |= (val >> 25) & 3; | |
498 | } | |
499 | if (mask & CPSR_IT_2_7) { | |
500 | env->condexec_bits &= 3; | |
501 | env->condexec_bits |= (val >> 8) & 0xfc; | |
502 | } | |
503 | if (mask & 0x1ff) { | |
504 | env->v7m.exception = val & 0x1ff; | |
505 | } | |
506 | } | |
507 | ||
01653295 PM |
508 | /* Return the current FPSCR value. */ |
509 | uint32_t vfp_get_fpscr(CPUARMState *env); | |
510 | void vfp_set_fpscr(CPUARMState *env, uint32_t val); | |
511 | ||
f903fa22 PM |
512 | /* For A64 the FPSCR is split into two logically distinct registers, |
513 | * FPCR and FPSR. However since they still use non-overlapping bits | |
514 | * we store the underlying state in fpscr and just mask on read/write. | |
515 | */ | |
516 | #define FPSR_MASK 0xf800009f | |
517 | #define FPCR_MASK 0x07f79f00 | |
518 | static inline uint32_t vfp_get_fpsr(CPUARMState *env) | |
519 | { | |
520 | return vfp_get_fpscr(env) & FPSR_MASK; | |
521 | } | |
522 | ||
523 | static inline void vfp_set_fpsr(CPUARMState *env, uint32_t val) | |
524 | { | |
525 | uint32_t new_fpscr = (vfp_get_fpscr(env) & ~FPSR_MASK) | (val & FPSR_MASK); | |
526 | vfp_set_fpscr(env, new_fpscr); | |
527 | } | |
528 | ||
529 | static inline uint32_t vfp_get_fpcr(CPUARMState *env) | |
530 | { | |
531 | return vfp_get_fpscr(env) & FPCR_MASK; | |
532 | } | |
533 | ||
534 | static inline void vfp_set_fpcr(CPUARMState *env, uint32_t val) | |
535 | { | |
536 | uint32_t new_fpscr = (vfp_get_fpscr(env) & ~FPCR_MASK) | (val & FPCR_MASK); | |
537 | vfp_set_fpscr(env, new_fpscr); | |
538 | } | |
539 | ||
4d3da0f3 AG |
540 | enum arm_fprounding { |
541 | FPROUNDING_TIEEVEN, | |
542 | FPROUNDING_POSINF, | |
543 | FPROUNDING_NEGINF, | |
544 | FPROUNDING_ZERO, | |
545 | FPROUNDING_TIEAWAY, | |
546 | FPROUNDING_ODD | |
547 | }; | |
548 | ||
9972da66 WN |
549 | int arm_rmode_to_sf(int rmode); |
550 | ||
b5ff1b31 FB |
551 | enum arm_cpu_mode { |
552 | ARM_CPU_MODE_USR = 0x10, | |
553 | ARM_CPU_MODE_FIQ = 0x11, | |
554 | ARM_CPU_MODE_IRQ = 0x12, | |
555 | ARM_CPU_MODE_SVC = 0x13, | |
556 | ARM_CPU_MODE_ABT = 0x17, | |
557 | ARM_CPU_MODE_UND = 0x1b, | |
558 | ARM_CPU_MODE_SYS = 0x1f | |
559 | }; | |
560 | ||
40f137e1 PB |
561 | /* VFP system registers. */ |
562 | #define ARM_VFP_FPSID 0 | |
563 | #define ARM_VFP_FPSCR 1 | |
9ee6e8bb PB |
564 | #define ARM_VFP_MVFR1 6 |
565 | #define ARM_VFP_MVFR0 7 | |
40f137e1 PB |
566 | #define ARM_VFP_FPEXC 8 |
567 | #define ARM_VFP_FPINST 9 | |
568 | #define ARM_VFP_FPINST2 10 | |
569 | ||
18c9b560 AZ |
570 | /* iwMMXt coprocessor control registers. */ |
571 | #define ARM_IWMMXT_wCID 0 | |
572 | #define ARM_IWMMXT_wCon 1 | |
573 | #define ARM_IWMMXT_wCSSF 2 | |
574 | #define ARM_IWMMXT_wCASF 3 | |
575 | #define ARM_IWMMXT_wCGR0 8 | |
576 | #define ARM_IWMMXT_wCGR1 9 | |
577 | #define ARM_IWMMXT_wCGR2 10 | |
578 | #define ARM_IWMMXT_wCGR3 11 | |
579 | ||
ce854d7c BC |
580 | /* If adding a feature bit which corresponds to a Linux ELF |
581 | * HWCAP bit, remember to update the feature-bit-to-hwcap | |
582 | * mapping in linux-user/elfload.c:get_elf_hwcap(). | |
583 | */ | |
40f137e1 PB |
584 | enum arm_features { |
585 | ARM_FEATURE_VFP, | |
c1713132 AZ |
586 | ARM_FEATURE_AUXCR, /* ARM1026 Auxiliary control register. */ |
587 | ARM_FEATURE_XSCALE, /* Intel XScale extensions. */ | |
ce819861 | 588 | ARM_FEATURE_IWMMXT, /* Intel iwMMXt extension. */ |
9ee6e8bb PB |
589 | ARM_FEATURE_V6, |
590 | ARM_FEATURE_V6K, | |
591 | ARM_FEATURE_V7, | |
592 | ARM_FEATURE_THUMB2, | |
c3d2689d | 593 | ARM_FEATURE_MPU, /* Only has Memory Protection Unit, not full MMU. */ |
9ee6e8bb | 594 | ARM_FEATURE_VFP3, |
60011498 | 595 | ARM_FEATURE_VFP_FP16, |
9ee6e8bb | 596 | ARM_FEATURE_NEON, |
47789990 | 597 | ARM_FEATURE_THUMB_DIV, /* divide supported in Thumb encoding */ |
9ee6e8bb | 598 | ARM_FEATURE_M, /* Microcontroller profile. */ |
fe1479c3 | 599 | ARM_FEATURE_OMAPCP, /* OMAP specific CP15 ops handling. */ |
e1bbf446 | 600 | ARM_FEATURE_THUMB2EE, |
be5e7a76 DES |
601 | ARM_FEATURE_V7MP, /* v7 Multiprocessing Extensions */ |
602 | ARM_FEATURE_V4T, | |
603 | ARM_FEATURE_V5, | |
5bc95aa2 | 604 | ARM_FEATURE_STRONGARM, |
906879a9 | 605 | ARM_FEATURE_VAPA, /* cp15 VA to PA lookups */ |
b8b8ea05 | 606 | ARM_FEATURE_ARM_DIV, /* divide supported in ARM encoding */ |
da97f52c | 607 | ARM_FEATURE_VFP4, /* VFPv4 (implies that NEON is v2) */ |
0383ac00 | 608 | ARM_FEATURE_GENERIC_TIMER, |
06ed5d66 | 609 | ARM_FEATURE_MVFR, /* Media and VFP Feature Registers 0 and 1 */ |
1047b9d7 | 610 | ARM_FEATURE_DUMMY_C15_REGS, /* RAZ/WI all of cp15 crn=15 */ |
c4804214 PM |
611 | ARM_FEATURE_CACHE_TEST_CLEAN, /* 926/1026 style test-and-clean ops */ |
612 | ARM_FEATURE_CACHE_DIRTY_REG, /* 1136/1176 cache dirty status register */ | |
613 | ARM_FEATURE_CACHE_BLOCK_OPS, /* v6 optional cache block operations */ | |
81bdde9d | 614 | ARM_FEATURE_MPIDR, /* has cp15 MPIDR */ |
de9b05b8 PM |
615 | ARM_FEATURE_PXN, /* has Privileged Execute Never bit */ |
616 | ARM_FEATURE_LPAE, /* has Large Physical Address Extension */ | |
81e69fb0 | 617 | ARM_FEATURE_V8, |
3926cc84 | 618 | ARM_FEATURE_AARCH64, /* supports 64 bit mode */ |
9d935509 | 619 | ARM_FEATURE_V8_AES, /* implements AES part of v8 Crypto Extensions */ |
d8ba780b | 620 | ARM_FEATURE_CBAR, /* has cp15 CBAR */ |
40f137e1 PB |
621 | }; |
622 | ||
623 | static inline int arm_feature(CPUARMState *env, int feature) | |
624 | { | |
918f5dca | 625 | return (env->features & (1ULL << feature)) != 0; |
40f137e1 PB |
626 | } |
627 | ||
9a78eead | 628 | void arm_cpu_list(FILE *f, fprintf_function cpu_fprintf); |
40f137e1 | 629 | |
9ee6e8bb PB |
630 | /* Interface between CPU and Interrupt controller. */ |
631 | void armv7m_nvic_set_pending(void *opaque, int irq); | |
632 | int armv7m_nvic_acknowledge_irq(void *opaque); | |
633 | void armv7m_nvic_complete_irq(void *opaque, int irq); | |
634 | ||
4b6a83fb PM |
635 | /* Interface for defining coprocessor registers. |
636 | * Registers are defined in tables of arm_cp_reginfo structs | |
637 | * which are passed to define_arm_cp_regs(). | |
638 | */ | |
639 | ||
640 | /* When looking up a coprocessor register we look for it | |
641 | * via an integer which encodes all of: | |
642 | * coprocessor number | |
643 | * Crn, Crm, opc1, opc2 fields | |
644 | * 32 or 64 bit register (ie is it accessed via MRC/MCR | |
645 | * or via MRRC/MCRR?) | |
646 | * We allow 4 bits for opc1 because MRRC/MCRR have a 4 bit field. | |
647 | * (In this case crn and opc2 should be zero.) | |
f5a0a5a5 PM |
648 | * For AArch64, there is no 32/64 bit size distinction; |
649 | * instead all registers have a 2 bit op0, 3 bit op1 and op2, | |
650 | * and 4 bit CRn and CRm. The encoding patterns are chosen | |
651 | * to be easy to convert to and from the KVM encodings, and also | |
652 | * so that the hashtable can contain both AArch32 and AArch64 | |
653 | * registers (to allow for interprocessing where we might run | |
654 | * 32 bit code on a 64 bit core). | |
4b6a83fb | 655 | */ |
f5a0a5a5 PM |
656 | /* This bit is private to our hashtable cpreg; in KVM register |
657 | * IDs the AArch64/32 distinction is the KVM_REG_ARM/ARM64 | |
658 | * in the upper bits of the 64 bit ID. | |
659 | */ | |
660 | #define CP_REG_AA64_SHIFT 28 | |
661 | #define CP_REG_AA64_MASK (1 << CP_REG_AA64_SHIFT) | |
662 | ||
4b6a83fb PM |
663 | #define ENCODE_CP_REG(cp, is64, crn, crm, opc1, opc2) \ |
664 | (((cp) << 16) | ((is64) << 15) | ((crn) << 11) | \ | |
665 | ((crm) << 7) | ((opc1) << 3) | (opc2)) | |
666 | ||
f5a0a5a5 PM |
667 | #define ENCODE_AA64_CP_REG(cp, crn, crm, op0, op1, op2) \ |
668 | (CP_REG_AA64_MASK | \ | |
669 | ((cp) << CP_REG_ARM_COPROC_SHIFT) | \ | |
670 | ((op0) << CP_REG_ARM64_SYSREG_OP0_SHIFT) | \ | |
671 | ((op1) << CP_REG_ARM64_SYSREG_OP1_SHIFT) | \ | |
672 | ((crn) << CP_REG_ARM64_SYSREG_CRN_SHIFT) | \ | |
673 | ((crm) << CP_REG_ARM64_SYSREG_CRM_SHIFT) | \ | |
674 | ((op2) << CP_REG_ARM64_SYSREG_OP2_SHIFT)) | |
675 | ||
721fae12 PM |
676 | /* Convert a full 64 bit KVM register ID to the truncated 32 bit |
677 | * version used as a key for the coprocessor register hashtable | |
678 | */ | |
679 | static inline uint32_t kvm_to_cpreg_id(uint64_t kvmid) | |
680 | { | |
681 | uint32_t cpregid = kvmid; | |
f5a0a5a5 PM |
682 | if ((kvmid & CP_REG_ARCH_MASK) == CP_REG_ARM64) { |
683 | cpregid |= CP_REG_AA64_MASK; | |
684 | } else if ((kvmid & CP_REG_SIZE_MASK) == CP_REG_SIZE_U64) { | |
721fae12 PM |
685 | cpregid |= (1 << 15); |
686 | } | |
687 | return cpregid; | |
688 | } | |
689 | ||
690 | /* Convert a truncated 32 bit hashtable key into the full | |
691 | * 64 bit KVM register ID. | |
692 | */ | |
693 | static inline uint64_t cpreg_to_kvm_id(uint32_t cpregid) | |
694 | { | |
f5a0a5a5 PM |
695 | uint64_t kvmid; |
696 | ||
697 | if (cpregid & CP_REG_AA64_MASK) { | |
698 | kvmid = cpregid & ~CP_REG_AA64_MASK; | |
699 | kvmid |= CP_REG_SIZE_U64 | CP_REG_ARM64; | |
721fae12 | 700 | } else { |
f5a0a5a5 PM |
701 | kvmid = cpregid & ~(1 << 15); |
702 | if (cpregid & (1 << 15)) { | |
703 | kvmid |= CP_REG_SIZE_U64 | CP_REG_ARM; | |
704 | } else { | |
705 | kvmid |= CP_REG_SIZE_U32 | CP_REG_ARM; | |
706 | } | |
721fae12 PM |
707 | } |
708 | return kvmid; | |
709 | } | |
710 | ||
4b6a83fb PM |
711 | /* ARMCPRegInfo type field bits. If the SPECIAL bit is set this is a |
712 | * special-behaviour cp reg and bits [15..8] indicate what behaviour | |
713 | * it has. Otherwise it is a simple cp reg, where CONST indicates that | |
714 | * TCG can assume the value to be constant (ie load at translate time) | |
715 | * and 64BIT indicates a 64 bit wide coprocessor register. SUPPRESS_TB_END | |
716 | * indicates that the TB should not be ended after a write to this register | |
717 | * (the default is that the TB ends after cp writes). OVERRIDE permits | |
718 | * a register definition to override a previous definition for the | |
719 | * same (cp, is64, crn, crm, opc1, opc2) tuple: either the new or the | |
720 | * old must have the OVERRIDE bit set. | |
7023ec7e PM |
721 | * NO_MIGRATE indicates that this register should be ignored for migration; |
722 | * (eg because any state is accessed via some other coprocessor register). | |
2452731c PM |
723 | * IO indicates that this register does I/O and therefore its accesses |
724 | * need to be surrounded by gen_io_start()/gen_io_end(). In particular, | |
725 | * registers which implement clocks or timers require this. | |
4b6a83fb PM |
726 | */ |
727 | #define ARM_CP_SPECIAL 1 | |
728 | #define ARM_CP_CONST 2 | |
729 | #define ARM_CP_64BIT 4 | |
730 | #define ARM_CP_SUPPRESS_TB_END 8 | |
731 | #define ARM_CP_OVERRIDE 16 | |
7023ec7e | 732 | #define ARM_CP_NO_MIGRATE 32 |
2452731c | 733 | #define ARM_CP_IO 64 |
4b6a83fb PM |
734 | #define ARM_CP_NOP (ARM_CP_SPECIAL | (1 << 8)) |
735 | #define ARM_CP_WFI (ARM_CP_SPECIAL | (2 << 8)) | |
b0d2b7d0 | 736 | #define ARM_CP_NZCV (ARM_CP_SPECIAL | (3 << 8)) |
0eef9d98 PM |
737 | #define ARM_CP_CURRENTEL (ARM_CP_SPECIAL | (4 << 8)) |
738 | #define ARM_LAST_SPECIAL ARM_CP_CURRENTEL | |
4b6a83fb PM |
739 | /* Used only as a terminator for ARMCPRegInfo lists */ |
740 | #define ARM_CP_SENTINEL 0xffff | |
741 | /* Mask of only the flag bits in a type field */ | |
2452731c | 742 | #define ARM_CP_FLAG_MASK 0x7f |
4b6a83fb | 743 | |
f5a0a5a5 PM |
744 | /* Valid values for ARMCPRegInfo state field, indicating which of |
745 | * the AArch32 and AArch64 execution states this register is visible in. | |
746 | * If the reginfo doesn't explicitly specify then it is AArch32 only. | |
747 | * If the reginfo is declared to be visible in both states then a second | |
748 | * reginfo is synthesised for the AArch32 view of the AArch64 register, | |
749 | * such that the AArch32 view is the lower 32 bits of the AArch64 one. | |
750 | * Note that we rely on the values of these enums as we iterate through | |
751 | * the various states in some places. | |
752 | */ | |
753 | enum { | |
754 | ARM_CP_STATE_AA32 = 0, | |
755 | ARM_CP_STATE_AA64 = 1, | |
756 | ARM_CP_STATE_BOTH = 2, | |
757 | }; | |
758 | ||
4b6a83fb PM |
759 | /* Return true if cptype is a valid type field. This is used to try to |
760 | * catch errors where the sentinel has been accidentally left off the end | |
761 | * of a list of registers. | |
762 | */ | |
763 | static inline bool cptype_valid(int cptype) | |
764 | { | |
765 | return ((cptype & ~ARM_CP_FLAG_MASK) == 0) | |
766 | || ((cptype & ARM_CP_SPECIAL) && | |
34affeef | 767 | ((cptype & ~ARM_CP_FLAG_MASK) <= ARM_LAST_SPECIAL)); |
4b6a83fb PM |
768 | } |
769 | ||
770 | /* Access rights: | |
771 | * We define bits for Read and Write access for what rev C of the v7-AR ARM ARM | |
772 | * defines as PL0 (user), PL1 (fiq/irq/svc/abt/und/sys, ie privileged), and | |
773 | * PL2 (hyp). The other level which has Read and Write bits is Secure PL1 | |
774 | * (ie any of the privileged modes in Secure state, or Monitor mode). | |
775 | * If a register is accessible in one privilege level it's always accessible | |
776 | * in higher privilege levels too. Since "Secure PL1" also follows this rule | |
777 | * (ie anything visible in PL2 is visible in S-PL1, some things are only | |
778 | * visible in S-PL1) but "Secure PL1" is a bit of a mouthful, we bend the | |
779 | * terminology a little and call this PL3. | |
f5a0a5a5 PM |
780 | * In AArch64 things are somewhat simpler as the PLx bits line up exactly |
781 | * with the ELx exception levels. | |
4b6a83fb PM |
782 | * |
783 | * If access permissions for a register are more complex than can be | |
784 | * described with these bits, then use a laxer set of restrictions, and | |
785 | * do the more restrictive/complex check inside a helper function. | |
786 | */ | |
787 | #define PL3_R 0x80 | |
788 | #define PL3_W 0x40 | |
789 | #define PL2_R (0x20 | PL3_R) | |
790 | #define PL2_W (0x10 | PL3_W) | |
791 | #define PL1_R (0x08 | PL2_R) | |
792 | #define PL1_W (0x04 | PL2_W) | |
793 | #define PL0_R (0x02 | PL1_R) | |
794 | #define PL0_W (0x01 | PL1_W) | |
795 | ||
796 | #define PL3_RW (PL3_R | PL3_W) | |
797 | #define PL2_RW (PL2_R | PL2_W) | |
798 | #define PL1_RW (PL1_R | PL1_W) | |
799 | #define PL0_RW (PL0_R | PL0_W) | |
800 | ||
801 | static inline int arm_current_pl(CPUARMState *env) | |
802 | { | |
f5a0a5a5 PM |
803 | if (env->aarch64) { |
804 | return extract32(env->pstate, 2, 2); | |
805 | } | |
806 | ||
4b6a83fb PM |
807 | if ((env->uncached_cpsr & 0x1f) == ARM_CPU_MODE_USR) { |
808 | return 0; | |
809 | } | |
810 | /* We don't currently implement the Virtualization or TrustZone | |
811 | * extensions, so PL2 and PL3 don't exist for us. | |
812 | */ | |
813 | return 1; | |
814 | } | |
815 | ||
816 | typedef struct ARMCPRegInfo ARMCPRegInfo; | |
817 | ||
f59df3f2 PM |
818 | typedef enum CPAccessResult { |
819 | /* Access is permitted */ | |
820 | CP_ACCESS_OK = 0, | |
821 | /* Access fails due to a configurable trap or enable which would | |
822 | * result in a categorized exception syndrome giving information about | |
823 | * the failing instruction (ie syndrome category 0x3, 0x4, 0x5, 0x6, | |
824 | * 0xc or 0x18). | |
825 | */ | |
826 | CP_ACCESS_TRAP = 1, | |
827 | /* Access fails and results in an exception syndrome 0x0 ("uncategorized"). | |
828 | * Note that this is not a catch-all case -- the set of cases which may | |
829 | * result in this failure is specifically defined by the architecture. | |
830 | */ | |
831 | CP_ACCESS_TRAP_UNCATEGORIZED = 2, | |
832 | } CPAccessResult; | |
833 | ||
c4241c7d PM |
834 | /* Access functions for coprocessor registers. These cannot fail and |
835 | * may not raise exceptions. | |
836 | */ | |
837 | typedef uint64_t CPReadFn(CPUARMState *env, const ARMCPRegInfo *opaque); | |
838 | typedef void CPWriteFn(CPUARMState *env, const ARMCPRegInfo *opaque, | |
839 | uint64_t value); | |
f59df3f2 PM |
840 | /* Access permission check functions for coprocessor registers. */ |
841 | typedef CPAccessResult CPAccessFn(CPUARMState *env, const ARMCPRegInfo *opaque); | |
4b6a83fb PM |
842 | /* Hook function for register reset */ |
843 | typedef void CPResetFn(CPUARMState *env, const ARMCPRegInfo *opaque); | |
844 | ||
845 | #define CP_ANY 0xff | |
846 | ||
847 | /* Definition of an ARM coprocessor register */ | |
848 | struct ARMCPRegInfo { | |
849 | /* Name of register (useful mainly for debugging, need not be unique) */ | |
850 | const char *name; | |
851 | /* Location of register: coprocessor number and (crn,crm,opc1,opc2) | |
852 | * tuple. Any of crm, opc1 and opc2 may be CP_ANY to indicate a | |
853 | * 'wildcard' field -- any value of that field in the MRC/MCR insn | |
854 | * will be decoded to this register. The register read and write | |
855 | * callbacks will be passed an ARMCPRegInfo with the crn/crm/opc1/opc2 | |
856 | * used by the program, so it is possible to register a wildcard and | |
857 | * then behave differently on read/write if necessary. | |
858 | * For 64 bit registers, only crm and opc1 are relevant; crn and opc2 | |
859 | * must both be zero. | |
f5a0a5a5 PM |
860 | * For AArch64-visible registers, opc0 is also used. |
861 | * Since there are no "coprocessors" in AArch64, cp is purely used as a | |
862 | * way to distinguish (for KVM's benefit) guest-visible system registers | |
863 | * from demuxed ones provided to preserve the "no side effects on | |
864 | * KVM register read/write from QEMU" semantics. cp==0x13 is guest | |
865 | * visible (to match KVM's encoding); cp==0 will be converted to | |
866 | * cp==0x13 when the ARMCPRegInfo is registered, for convenience. | |
4b6a83fb PM |
867 | */ |
868 | uint8_t cp; | |
869 | uint8_t crn; | |
870 | uint8_t crm; | |
f5a0a5a5 | 871 | uint8_t opc0; |
4b6a83fb PM |
872 | uint8_t opc1; |
873 | uint8_t opc2; | |
f5a0a5a5 PM |
874 | /* Execution state in which this register is visible: ARM_CP_STATE_* */ |
875 | int state; | |
4b6a83fb PM |
876 | /* Register type: ARM_CP_* bits/values */ |
877 | int type; | |
878 | /* Access rights: PL*_[RW] */ | |
879 | int access; | |
880 | /* The opaque pointer passed to define_arm_cp_regs_with_opaque() when | |
881 | * this register was defined: can be used to hand data through to the | |
882 | * register read/write functions, since they are passed the ARMCPRegInfo*. | |
883 | */ | |
884 | void *opaque; | |
885 | /* Value of this register, if it is ARM_CP_CONST. Otherwise, if | |
886 | * fieldoffset is non-zero, the reset value of the register. | |
887 | */ | |
888 | uint64_t resetvalue; | |
889 | /* Offset of the field in CPUARMState for this register. This is not | |
890 | * needed if either: | |
891 | * 1. type is ARM_CP_CONST or one of the ARM_CP_SPECIALs | |
892 | * 2. both readfn and writefn are specified | |
893 | */ | |
894 | ptrdiff_t fieldoffset; /* offsetof(CPUARMState, field) */ | |
f59df3f2 PM |
895 | /* Function for making any access checks for this register in addition to |
896 | * those specified by the 'access' permissions bits. If NULL, no extra | |
897 | * checks required. The access check is performed at runtime, not at | |
898 | * translate time. | |
899 | */ | |
900 | CPAccessFn *accessfn; | |
4b6a83fb PM |
901 | /* Function for handling reads of this register. If NULL, then reads |
902 | * will be done by loading from the offset into CPUARMState specified | |
903 | * by fieldoffset. | |
904 | */ | |
905 | CPReadFn *readfn; | |
906 | /* Function for handling writes of this register. If NULL, then writes | |
907 | * will be done by writing to the offset into CPUARMState specified | |
908 | * by fieldoffset. | |
909 | */ | |
910 | CPWriteFn *writefn; | |
7023ec7e PM |
911 | /* Function for doing a "raw" read; used when we need to copy |
912 | * coprocessor state to the kernel for KVM or out for | |
913 | * migration. This only needs to be provided if there is also a | |
c4241c7d | 914 | * readfn and it has side effects (for instance clear-on-read bits). |
7023ec7e PM |
915 | */ |
916 | CPReadFn *raw_readfn; | |
917 | /* Function for doing a "raw" write; used when we need to copy KVM | |
918 | * kernel coprocessor state into userspace, or for inbound | |
919 | * migration. This only needs to be provided if there is also a | |
c4241c7d PM |
920 | * writefn and it masks out "unwritable" bits or has write-one-to-clear |
921 | * or similar behaviour. | |
7023ec7e PM |
922 | */ |
923 | CPWriteFn *raw_writefn; | |
4b6a83fb PM |
924 | /* Function for resetting the register. If NULL, then reset will be done |
925 | * by writing resetvalue to the field specified in fieldoffset. If | |
926 | * fieldoffset is 0 then no reset will be done. | |
927 | */ | |
928 | CPResetFn *resetfn; | |
929 | }; | |
930 | ||
931 | /* Macros which are lvalues for the field in CPUARMState for the | |
932 | * ARMCPRegInfo *ri. | |
933 | */ | |
934 | #define CPREG_FIELD32(env, ri) \ | |
935 | (*(uint32_t *)((char *)(env) + (ri)->fieldoffset)) | |
936 | #define CPREG_FIELD64(env, ri) \ | |
937 | (*(uint64_t *)((char *)(env) + (ri)->fieldoffset)) | |
938 | ||
939 | #define REGINFO_SENTINEL { .type = ARM_CP_SENTINEL } | |
940 | ||
941 | void define_arm_cp_regs_with_opaque(ARMCPU *cpu, | |
942 | const ARMCPRegInfo *regs, void *opaque); | |
943 | void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu, | |
944 | const ARMCPRegInfo *regs, void *opaque); | |
945 | static inline void define_arm_cp_regs(ARMCPU *cpu, const ARMCPRegInfo *regs) | |
946 | { | |
947 | define_arm_cp_regs_with_opaque(cpu, regs, 0); | |
948 | } | |
949 | static inline void define_one_arm_cp_reg(ARMCPU *cpu, const ARMCPRegInfo *regs) | |
950 | { | |
951 | define_one_arm_cp_reg_with_opaque(cpu, regs, 0); | |
952 | } | |
60322b39 | 953 | const ARMCPRegInfo *get_arm_cp_reginfo(GHashTable *cpregs, uint32_t encoded_cp); |
4b6a83fb PM |
954 | |
955 | /* CPWriteFn that can be used to implement writes-ignored behaviour */ | |
c4241c7d PM |
956 | void arm_cp_write_ignore(CPUARMState *env, const ARMCPRegInfo *ri, |
957 | uint64_t value); | |
4b6a83fb | 958 | /* CPReadFn that can be used for read-as-zero behaviour */ |
c4241c7d | 959 | uint64_t arm_cp_read_zero(CPUARMState *env, const ARMCPRegInfo *ri); |
4b6a83fb | 960 | |
f5a0a5a5 PM |
961 | /* CPResetFn that does nothing, for use if no reset is required even |
962 | * if fieldoffset is non zero. | |
963 | */ | |
964 | void arm_cp_reset_ignore(CPUARMState *env, const ARMCPRegInfo *opaque); | |
965 | ||
67ed771d PM |
966 | /* Return true if this reginfo struct's field in the cpu state struct |
967 | * is 64 bits wide. | |
968 | */ | |
969 | static inline bool cpreg_field_is_64bit(const ARMCPRegInfo *ri) | |
970 | { | |
971 | return (ri->state == ARM_CP_STATE_AA64) || (ri->type & ARM_CP_64BIT); | |
972 | } | |
973 | ||
60322b39 | 974 | static inline bool cp_access_ok(int current_pl, |
4b6a83fb PM |
975 | const ARMCPRegInfo *ri, int isread) |
976 | { | |
60322b39 | 977 | return (ri->access >> ((current_pl * 2) + isread)) & 1; |
4b6a83fb PM |
978 | } |
979 | ||
721fae12 PM |
980 | /** |
981 | * write_list_to_cpustate | |
982 | * @cpu: ARMCPU | |
983 | * | |
984 | * For each register listed in the ARMCPU cpreg_indexes list, write | |
985 | * its value from the cpreg_values list into the ARMCPUState structure. | |
986 | * This updates TCG's working data structures from KVM data or | |
987 | * from incoming migration state. | |
988 | * | |
989 | * Returns: true if all register values were updated correctly, | |
990 | * false if some register was unknown or could not be written. | |
991 | * Note that we do not stop early on failure -- we will attempt | |
992 | * writing all registers in the list. | |
993 | */ | |
994 | bool write_list_to_cpustate(ARMCPU *cpu); | |
995 | ||
996 | /** | |
997 | * write_cpustate_to_list: | |
998 | * @cpu: ARMCPU | |
999 | * | |
1000 | * For each register listed in the ARMCPU cpreg_indexes list, write | |
1001 | * its value from the ARMCPUState structure into the cpreg_values list. | |
1002 | * This is used to copy info from TCG's working data structures into | |
1003 | * KVM or for outbound migration. | |
1004 | * | |
1005 | * Returns: true if all register values were read correctly, | |
1006 | * false if some register was unknown or could not be read. | |
1007 | * Note that we do not stop early on failure -- we will attempt | |
1008 | * reading all registers in the list. | |
1009 | */ | |
1010 | bool write_cpustate_to_list(ARMCPU *cpu); | |
1011 | ||
9ee6e8bb PB |
1012 | /* Does the core conform to the the "MicroController" profile. e.g. Cortex-M3. |
1013 | Note the M in older cores (eg. ARM7TDMI) stands for Multiply. These are | |
1014 | conventional cores (ie. Application or Realtime profile). */ | |
1015 | ||
1016 | #define IS_M(env) arm_feature(env, ARM_FEATURE_M) | |
9ee6e8bb | 1017 | |
9ee6e8bb PB |
1018 | #define ARM_CPUID_TI915T 0x54029152 |
1019 | #define ARM_CPUID_TI925T 0x54029252 | |
40f137e1 | 1020 | |
b5ff1b31 | 1021 | #if defined(CONFIG_USER_ONLY) |
2c0262af | 1022 | #define TARGET_PAGE_BITS 12 |
b5ff1b31 FB |
1023 | #else |
1024 | /* The ARM MMU allows 1k pages. */ | |
1025 | /* ??? Linux doesn't actually use these, and they're deprecated in recent | |
82d17978 | 1026 | architecture revisions. Maybe a configure option to disable them. */ |
b5ff1b31 FB |
1027 | #define TARGET_PAGE_BITS 10 |
1028 | #endif | |
9467d44c | 1029 | |
3926cc84 AG |
1030 | #if defined(TARGET_AARCH64) |
1031 | # define TARGET_PHYS_ADDR_SPACE_BITS 48 | |
1032 | # define TARGET_VIRT_ADDR_SPACE_BITS 64 | |
1033 | #else | |
1034 | # define TARGET_PHYS_ADDR_SPACE_BITS 40 | |
1035 | # define TARGET_VIRT_ADDR_SPACE_BITS 32 | |
1036 | #endif | |
52705890 | 1037 | |
ad37ad5b PM |
1038 | static inline CPUARMState *cpu_init(const char *cpu_model) |
1039 | { | |
1040 | ARMCPU *cpu = cpu_arm_init(cpu_model); | |
1041 | if (cpu) { | |
1042 | return &cpu->env; | |
1043 | } | |
1044 | return NULL; | |
1045 | } | |
1046 | ||
9467d44c TS |
1047 | #define cpu_exec cpu_arm_exec |
1048 | #define cpu_gen_code cpu_arm_gen_code | |
1049 | #define cpu_signal_handler cpu_arm_signal_handler | |
c732abe2 | 1050 | #define cpu_list arm_cpu_list |
9467d44c | 1051 | |
6ebbf390 JM |
1052 | /* MMU modes definitions */ |
1053 | #define MMU_MODE0_SUFFIX _kernel | |
1054 | #define MMU_MODE1_SUFFIX _user | |
1055 | #define MMU_USER_IDX 1 | |
0ecb72a5 | 1056 | static inline int cpu_mmu_index (CPUARMState *env) |
6ebbf390 JM |
1057 | { |
1058 | return (env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_USR ? 1 : 0; | |
1059 | } | |
1060 | ||
022c62cb | 1061 | #include "exec/cpu-all.h" |
622ed360 | 1062 | |
3926cc84 AG |
1063 | /* Bit usage in the TB flags field: bit 31 indicates whether we are |
1064 | * in 32 or 64 bit mode. The meaning of the other bits depends on that. | |
1065 | */ | |
1066 | #define ARM_TBFLAG_AARCH64_STATE_SHIFT 31 | |
1067 | #define ARM_TBFLAG_AARCH64_STATE_MASK (1U << ARM_TBFLAG_AARCH64_STATE_SHIFT) | |
1068 | ||
1069 | /* Bit usage when in AArch32 state: */ | |
a1705768 PM |
1070 | #define ARM_TBFLAG_THUMB_SHIFT 0 |
1071 | #define ARM_TBFLAG_THUMB_MASK (1 << ARM_TBFLAG_THUMB_SHIFT) | |
1072 | #define ARM_TBFLAG_VECLEN_SHIFT 1 | |
1073 | #define ARM_TBFLAG_VECLEN_MASK (0x7 << ARM_TBFLAG_VECLEN_SHIFT) | |
1074 | #define ARM_TBFLAG_VECSTRIDE_SHIFT 4 | |
1075 | #define ARM_TBFLAG_VECSTRIDE_MASK (0x3 << ARM_TBFLAG_VECSTRIDE_SHIFT) | |
1076 | #define ARM_TBFLAG_PRIV_SHIFT 6 | |
1077 | #define ARM_TBFLAG_PRIV_MASK (1 << ARM_TBFLAG_PRIV_SHIFT) | |
1078 | #define ARM_TBFLAG_VFPEN_SHIFT 7 | |
1079 | #define ARM_TBFLAG_VFPEN_MASK (1 << ARM_TBFLAG_VFPEN_SHIFT) | |
1080 | #define ARM_TBFLAG_CONDEXEC_SHIFT 8 | |
1081 | #define ARM_TBFLAG_CONDEXEC_MASK (0xff << ARM_TBFLAG_CONDEXEC_SHIFT) | |
d8fd2954 PB |
1082 | #define ARM_TBFLAG_BSWAP_CODE_SHIFT 16 |
1083 | #define ARM_TBFLAG_BSWAP_CODE_MASK (1 << ARM_TBFLAG_BSWAP_CODE_SHIFT) | |
3926cc84 AG |
1084 | |
1085 | /* Bit usage when in AArch64 state: currently no bits defined */ | |
a1705768 PM |
1086 | |
1087 | /* some convenience accessor macros */ | |
3926cc84 AG |
1088 | #define ARM_TBFLAG_AARCH64_STATE(F) \ |
1089 | (((F) & ARM_TBFLAG_AARCH64_STATE_MASK) >> ARM_TBFLAG_AARCH64_STATE_SHIFT) | |
a1705768 PM |
1090 | #define ARM_TBFLAG_THUMB(F) \ |
1091 | (((F) & ARM_TBFLAG_THUMB_MASK) >> ARM_TBFLAG_THUMB_SHIFT) | |
1092 | #define ARM_TBFLAG_VECLEN(F) \ | |
1093 | (((F) & ARM_TBFLAG_VECLEN_MASK) >> ARM_TBFLAG_VECLEN_SHIFT) | |
1094 | #define ARM_TBFLAG_VECSTRIDE(F) \ | |
1095 | (((F) & ARM_TBFLAG_VECSTRIDE_MASK) >> ARM_TBFLAG_VECSTRIDE_SHIFT) | |
1096 | #define ARM_TBFLAG_PRIV(F) \ | |
1097 | (((F) & ARM_TBFLAG_PRIV_MASK) >> ARM_TBFLAG_PRIV_SHIFT) | |
1098 | #define ARM_TBFLAG_VFPEN(F) \ | |
1099 | (((F) & ARM_TBFLAG_VFPEN_MASK) >> ARM_TBFLAG_VFPEN_SHIFT) | |
1100 | #define ARM_TBFLAG_CONDEXEC(F) \ | |
1101 | (((F) & ARM_TBFLAG_CONDEXEC_MASK) >> ARM_TBFLAG_CONDEXEC_SHIFT) | |
d8fd2954 PB |
1102 | #define ARM_TBFLAG_BSWAP_CODE(F) \ |
1103 | (((F) & ARM_TBFLAG_BSWAP_CODE_MASK) >> ARM_TBFLAG_BSWAP_CODE_SHIFT) | |
a1705768 | 1104 | |
0ecb72a5 | 1105 | static inline void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, |
6b917547 AL |
1106 | target_ulong *cs_base, int *flags) |
1107 | { | |
3926cc84 AG |
1108 | if (is_a64(env)) { |
1109 | *pc = env->pc; | |
1110 | *flags = ARM_TBFLAG_AARCH64_STATE_MASK; | |
05ed9a99 | 1111 | } else { |
3926cc84 AG |
1112 | int privmode; |
1113 | *pc = env->regs[15]; | |
1114 | *flags = (env->thumb << ARM_TBFLAG_THUMB_SHIFT) | |
1115 | | (env->vfp.vec_len << ARM_TBFLAG_VECLEN_SHIFT) | |
1116 | | (env->vfp.vec_stride << ARM_TBFLAG_VECSTRIDE_SHIFT) | |
1117 | | (env->condexec_bits << ARM_TBFLAG_CONDEXEC_SHIFT) | |
1118 | | (env->bswap_code << ARM_TBFLAG_BSWAP_CODE_SHIFT); | |
1119 | if (arm_feature(env, ARM_FEATURE_M)) { | |
1120 | privmode = !((env->v7m.exception == 0) && (env->v7m.control & 1)); | |
1121 | } else { | |
1122 | privmode = (env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR; | |
1123 | } | |
1124 | if (privmode) { | |
1125 | *flags |= ARM_TBFLAG_PRIV_MASK; | |
1126 | } | |
1127 | if (env->vfp.xregs[ARM_VFP_FPEXC] & (1 << 30)) { | |
1128 | *flags |= ARM_TBFLAG_VFPEN_MASK; | |
1129 | } | |
a1705768 | 1130 | } |
3926cc84 AG |
1131 | |
1132 | *cs_base = 0; | |
6b917547 AL |
1133 | } |
1134 | ||
3993c6bd | 1135 | static inline bool cpu_has_work(CPUState *cpu) |
f081c76c | 1136 | { |
259186a7 | 1137 | return cpu->interrupt_request & |
f081c76c BS |
1138 | (CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD | CPU_INTERRUPT_EXITTB); |
1139 | } | |
1140 | ||
022c62cb | 1141 | #include "exec/exec-all.h" |
f081c76c | 1142 | |
3926cc84 AG |
1143 | static inline void cpu_pc_from_tb(CPUARMState *env, TranslationBlock *tb) |
1144 | { | |
1145 | if (ARM_TBFLAG_AARCH64_STATE(tb->flags)) { | |
1146 | env->pc = tb->pc; | |
1147 | } else { | |
1148 | env->regs[15] = tb->pc; | |
1149 | } | |
1150 | } | |
1151 | ||
d8fd2954 | 1152 | /* Load an instruction and return it in the standard little-endian order */ |
0a2461fa | 1153 | static inline uint32_t arm_ldl_code(CPUARMState *env, target_ulong addr, |
d31dd73e | 1154 | bool do_swap) |
d8fd2954 | 1155 | { |
d31dd73e | 1156 | uint32_t insn = cpu_ldl_code(env, addr); |
d8fd2954 PB |
1157 | if (do_swap) { |
1158 | return bswap32(insn); | |
1159 | } | |
1160 | return insn; | |
1161 | } | |
1162 | ||
1163 | /* Ditto, for a halfword (Thumb) instruction */ | |
0a2461fa | 1164 | static inline uint16_t arm_lduw_code(CPUARMState *env, target_ulong addr, |
d31dd73e | 1165 | bool do_swap) |
d8fd2954 | 1166 | { |
d31dd73e | 1167 | uint16_t insn = cpu_lduw_code(env, addr); |
d8fd2954 PB |
1168 | if (do_swap) { |
1169 | return bswap16(insn); | |
1170 | } | |
1171 | return insn; | |
1172 | } | |
1173 | ||
2c0262af | 1174 | #endif |