[mirror_qemu.git] / target-arm / cpu64.c

/*
 * QEMU AArch64 CPU
 *
 * Copyright (c) 2013 Linaro Ltd
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version 2
 * of the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, see
 * <http://www.gnu.org/licenses/gpl-2.0.html>
 */

#include "cpu.h"
#include "qemu-common.h"
#if !defined(CONFIG_USER_ONLY)
#include "hw/loader.h"
#endif
#include "hw/arm/arm.h"
#include "sysemu/sysemu.h"
#include "sysemu/kvm.h"

static inline void set_feature(CPUARMState *env, int feature)
{
    env->features |= 1ULL << feature;
}

#ifndef CONFIG_USER_ONLY
static uint64_t a57_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri)
{
    /* Number of processors is in [25:24]; otherwise we RAZ */
    return (smp_cpus - 1) << 24;
}
#endif

static const ARMCPRegInfo cortexa57_cp_reginfo[] = {
#ifndef CONFIG_USER_ONLY
    { .name = "L2CTLR_EL1", .state = ARM_CP_STATE_AA64,
      .opc0 = 3, .opc1 = 1, .crn = 11, .crm = 0, .opc2 = 2,
      .access = PL1_RW, .readfn = a57_l2ctlr_read,
      .writefn = arm_cp_write_ignore },
    { .name = "L2CTLR",
      .cp = 15, .opc1 = 1, .crn = 9, .crm = 0, .opc2 = 2,
      .access = PL1_RW, .readfn = a57_l2ctlr_read,
      .writefn = arm_cp_write_ignore },
#endif
    { .name = "L2ECTLR_EL1", .state = ARM_CP_STATE_AA64,
      .opc0 = 3, .opc1 = 1, .crn = 11, .crm = 0, .opc2 = 3,
      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
    { .name = "L2ECTLR",
      .cp = 15, .opc1 = 1, .crn = 9, .crm = 0, .opc2 = 3,
      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
    { .name = "L2ACTLR", .state = ARM_CP_STATE_BOTH,
      .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 0, .opc2 = 0,
      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
    { .name = "CPUACTLR_EL1", .state = ARM_CP_STATE_AA64,
      .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 0,
      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
    { .name = "CPUACTLR",
      .cp = 15, .opc1 = 0, .crm = 15,
      .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
    { .name = "CPUECTLR_EL1", .state = ARM_CP_STATE_AA64,
      .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 1,
      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
    { .name = "CPUECTLR",
      .cp = 15, .opc1 = 1, .crm = 15,
      .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
    { .name = "CPUMERRSR_EL1", .state = ARM_CP_STATE_AA64,
      .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 2,
      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
    { .name = "CPUMERRSR",
      .cp = 15, .opc1 = 2, .crm = 15,
      .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
    { .name = "L2MERRSR_EL1", .state = ARM_CP_STATE_AA64,
      .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 3,
      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
    { .name = "L2MERRSR",
      .cp = 15, .opc1 = 3, .crm = 15,
      .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
    REGINFO_SENTINEL
};

static void aarch64_a57_initfn(Object *obj)
{
    ARMCPU *cpu = ARM_CPU(obj);

    set_feature(&cpu->env, ARM_FEATURE_V8);
    set_feature(&cpu->env, ARM_FEATURE_VFP4);
    set_feature(&cpu->env, ARM_FEATURE_NEON);
    set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
    set_feature(&cpu->env, ARM_FEATURE_AARCH64);
    set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
    set_feature(&cpu->env, ARM_FEATURE_V8_AES);
    set_feature(&cpu->env, ARM_FEATURE_V8_SHA1);
    set_feature(&cpu->env, ARM_FEATURE_V8_SHA256);
    set_feature(&cpu->env, ARM_FEATURE_V8_PMULL);
    set_feature(&cpu->env, ARM_FEATURE_CRC);
    cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A57;
    cpu->midr = 0x411fd070;
    cpu->reset_fpsid = 0x41034070;
    cpu->mvfr0 = 0x10110222;
    cpu->mvfr1 = 0x12111111;
    cpu->mvfr2 = 0x00000043;
    cpu->ctr = 0x8444c004;
    cpu->reset_sctlr = 0x00c50838;
    cpu->id_pfr0 = 0x00000131;
    cpu->id_pfr1 = 0x00011011;
    cpu->id_dfr0 = 0x03010066;
    cpu->id_afr0 = 0x00000000;
    cpu->id_mmfr0 = 0x10101105;
    cpu->id_mmfr1 = 0x40000000;
    cpu->id_mmfr2 = 0x01260000;
    cpu->id_mmfr3 = 0x02102211;
    cpu->id_isar0 = 0x02101110;
    cpu->id_isar1 = 0x13112111;
    cpu->id_isar2 = 0x21232042;
    cpu->id_isar3 = 0x01112131;
    cpu->id_isar4 = 0x00011142;
    cpu->id_aa64pfr0 = 0x00002222;
    cpu->id_aa64dfr0 = 0x10305106;
    cpu->id_aa64isar0 = 0x00010000;
    cpu->id_aa64mmfr0 = 0x00001124;
    cpu->clidr = 0x0a200023;
    cpu->ccsidr[0] = 0x701fe00a; /* 32KB L1 dcache */
    cpu->ccsidr[1] = 0x201fe012; /* 48KB L1 icache */
    cpu->ccsidr[2] = 0x70ffe07a; /* 2048KB L2 cache */
    cpu->dcz_blocksize = 4; /* 64 bytes */
    define_arm_cp_regs(cpu, cortexa57_cp_reginfo);
}

#ifdef CONFIG_USER_ONLY
static void aarch64_any_initfn(Object *obj)
{
    ARMCPU *cpu = ARM_CPU(obj);

    set_feature(&cpu->env, ARM_FEATURE_V8);
    set_feature(&cpu->env, ARM_FEATURE_VFP4);
    set_feature(&cpu->env, ARM_FEATURE_NEON);
    set_feature(&cpu->env, ARM_FEATURE_AARCH64);
    set_feature(&cpu->env, ARM_FEATURE_V8_AES);
    set_feature(&cpu->env, ARM_FEATURE_V8_SHA1);
    set_feature(&cpu->env, ARM_FEATURE_V8_SHA256);
    set_feature(&cpu->env, ARM_FEATURE_V8_PMULL);
    set_feature(&cpu->env, ARM_FEATURE_CRC);
    cpu->ctr = 0x80030003; /* 32 byte I and D cacheline size, VIPT icache */
    cpu->dcz_blocksize = 7; /*  512 bytes */
}
#endif

typedef struct ARMCPUInfo {
    const char *name;
    void (*initfn)(Object *obj);
    void (*class_init)(ObjectClass *oc, void *data);
} ARMCPUInfo;

static const ARMCPUInfo aarch64_cpus[] = {
    { .name = "cortex-a57",         .initfn = aarch64_a57_initfn },
#ifdef CONFIG_USER_ONLY
    { .name = "any",         .initfn = aarch64_any_initfn },
#endif
    { .name = NULL }
};

static void aarch64_cpu_initfn(Object *obj)
{
}

static void aarch64_cpu_finalizefn(Object *obj)
{
}

static void aarch64_cpu_set_pc(CPUState *cs, vaddr value)
{
    ARMCPU *cpu = ARM_CPU(cs);
    /* It's OK to look at env for the current mode here, because it's
     * never possible for an AArch64 TB to chain to an AArch32 TB.
     * (Otherwise we would need to use synchronize_from_tb instead.)
     */
    if (is_a64(&cpu->env)) {
        cpu->env.pc = value;
    } else {
        cpu->env.regs[15] = value;
    }
}

static void aarch64_cpu_class_init(ObjectClass *oc, void *data)
{
    CPUClass *cc = CPU_CLASS(oc);

    cc->do_interrupt = aarch64_cpu_do_interrupt;
    cc->set_pc = aarch64_cpu_set_pc;
    cc->gdb_read_register = aarch64_cpu_gdb_read_register;
    cc->gdb_write_register = aarch64_cpu_gdb_write_register;
    cc->gdb_num_core_regs = 34;
    cc->gdb_core_xml_file = "aarch64-core.xml";
}

static void aarch64_cpu_register(const ARMCPUInfo *info)
{
    TypeInfo type_info = {
        .parent = TYPE_AARCH64_CPU,
        .instance_size = sizeof(ARMCPU),
        .instance_init = info->initfn,
        .class_size = sizeof(ARMCPUClass),
        .class_init = info->class_init,
    };

    type_info.name = g_strdup_printf("%s-" TYPE_ARM_CPU, info->name);
    type_register(&type_info);
    g_free((void *)type_info.name);
}

static const TypeInfo aarch64_cpu_type_info = {
    .name = TYPE_AARCH64_CPU,
    .parent = TYPE_ARM_CPU,
    .instance_size = sizeof(ARMCPU),
    .instance_init = aarch64_cpu_initfn,
    .instance_finalize = aarch64_cpu_finalizefn,
    .abstract = true,
    .class_size = sizeof(AArch64CPUClass),
    .class_init = aarch64_cpu_class_init,
};

static void aarch64_cpu_register_types(void)
{
    const ARMCPUInfo *info = aarch64_cpus;

    type_register_static(&aarch64_cpu_type_info);

    while (info->name) {
        aarch64_cpu_register(info);
        info++;
    }
}

type_init(aarch64_cpu_register_types)
Commit	Line	Data
d14d42f1 PM	1	/*
	2	* QEMU AArch64 CPU
	3	*
	4	* Copyright (c) 2013 Linaro Ltd
	5	*
	6	* This program is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU General Public License
	8	* as published by the Free Software Foundation; either version 2
	9	* of the License, or (at your option) any later version.
	10	*
	11	* This program is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	* GNU General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU General Public License
	17	* along with this program; if not, see
	18	* <http://www.gnu.org/licenses/gpl-2.0.html>
	19	*/
	20
	21	#include "cpu.h"
	22	#include "qemu-common.h"
	23	#if !defined(CONFIG_USER_ONLY)
	24	#include "hw/loader.h"
	25	#endif
	26	#include "hw/arm/arm.h"
	27	#include "sysemu/sysemu.h"
	28	#include "sysemu/kvm.h"
	29
	30	static inline void set_feature(CPUARMState *env, int feature)
	31	{
	32	env->features \|= 1ULL << feature;
	33	}
	34
377a44ec PM	35	#ifndef CONFIG_USER_ONLY
	36	static uint64_t a57_l2ctlr_read(CPUARMState env, const ARMCPRegInfo ri)
	37	{
	38	/* Number of processors is in [25:24]; otherwise we RAZ */
	39	return (smp_cpus - 1) << 24;
	40	}
	41	#endif
	42
	43	static const ARMCPRegInfo cortexa57_cp_reginfo[] = {
	44	#ifndef CONFIG_USER_ONLY
	45	{ .name = "L2CTLR_EL1", .state = ARM_CP_STATE_AA64,
	46	.opc0 = 3, .opc1 = 1, .crn = 11, .crm = 0, .opc2 = 2,
	47	.access = PL1_RW, .readfn = a57_l2ctlr_read,
	48	.writefn = arm_cp_write_ignore },
	49	{ .name = "L2CTLR",
	50	.cp = 15, .opc1 = 1, .crn = 9, .crm = 0, .opc2 = 2,
	51	.access = PL1_RW, .readfn = a57_l2ctlr_read,
	52	.writefn = arm_cp_write_ignore },
	53	#endif
	54	{ .name = "L2ECTLR_EL1", .state = ARM_CP_STATE_AA64,
	55	.opc0 = 3, .opc1 = 1, .crn = 11, .crm = 0, .opc2 = 3,
	56	.access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
	57	{ .name = "L2ECTLR",
	58	.cp = 15, .opc1 = 1, .crn = 9, .crm = 0, .opc2 = 3,
	59	.access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
	60	{ .name = "L2ACTLR", .state = ARM_CP_STATE_BOTH,
	61	.opc0 = 3, .opc1 = 1, .crn = 15, .crm = 0, .opc2 = 0,
	62	.access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
	63	{ .name = "CPUACTLR_EL1", .state = ARM_CP_STATE_AA64,
	64	.opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 0,
	65	.access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
	66	{ .name = "CPUACTLR",
	67	.cp = 15, .opc1 = 0, .crm = 15,
	68	.access = PL1_RW, .type = ARM_CP_CONST \| ARM_CP_64BIT, .resetvalue = 0 },
	69	{ .name = "CPUECTLR_EL1", .state = ARM_CP_STATE_AA64,
	70	.opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 1,
	71	.access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
	72	{ .name = "CPUECTLR",
	73	.cp = 15, .opc1 = 1, .crm = 15,
	74	.access = PL1_RW, .type = ARM_CP_CONST \| ARM_CP_64BIT, .resetvalue = 0 },
	75	{ .name = "CPUMERRSR_EL1", .state = ARM_CP_STATE_AA64,
	76	.opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 2,
	77	.access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
	78	{ .name = "CPUMERRSR",
	79	.cp = 15, .opc1 = 2, .crm = 15,
	80	.access = PL1_RW, .type = ARM_CP_CONST \| ARM_CP_64BIT, .resetvalue = 0 },
	81	{ .name = "L2MERRSR_EL1", .state = ARM_CP_STATE_AA64,
	82	.opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 3,
	83	.access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
	84	{ .name = "L2MERRSR",
	85	.cp = 15, .opc1 = 3, .crm = 15,
	86	.access = PL1_RW, .type = ARM_CP_CONST \| ARM_CP_64BIT, .resetvalue = 0 },
	87	REGINFO_SENTINEL
	88	};
	89
cb1fa941 PM	90	static void aarch64_a57_initfn(Object *obj)
	91	{
	92	ARMCPU *cpu = ARM_CPU(obj);
	93
	94	set_feature(&cpu->env, ARM_FEATURE_V8);
	95	set_feature(&cpu->env, ARM_FEATURE_VFP4);
cb1fa941 PM	96	set_feature(&cpu->env, ARM_FEATURE_NEON);
	97	set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
	98	set_feature(&cpu->env, ARM_FEATURE_AARCH64);
f318cec6	99	set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
25f748e3 PM	100	set_feature(&cpu->env, ARM_FEATURE_V8_AES);
	101	set_feature(&cpu->env, ARM_FEATURE_V8_SHA1);
	102	set_feature(&cpu->env, ARM_FEATURE_V8_SHA256);
	103	set_feature(&cpu->env, ARM_FEATURE_V8_PMULL);
	104	set_feature(&cpu->env, ARM_FEATURE_CRC);
cb1fa941 PM	105	cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A57;
	106	cpu->midr = 0x411fd070;
	107	cpu->reset_fpsid = 0x41034070;
	108	cpu->mvfr0 = 0x10110222;
	109	cpu->mvfr1 = 0x12111111;
	110	cpu->mvfr2 = 0x00000043;
	111	cpu->ctr = 0x8444c004;
	112	cpu->reset_sctlr = 0x00c50838;
	113	cpu->id_pfr0 = 0x00000131;
	114	cpu->id_pfr1 = 0x00011011;
	115	cpu->id_dfr0 = 0x03010066;
	116	cpu->id_afr0 = 0x00000000;
	117	cpu->id_mmfr0 = 0x10101105;
	118	cpu->id_mmfr1 = 0x40000000;
	119	cpu->id_mmfr2 = 0x01260000;
	120	cpu->id_mmfr3 = 0x02102211;
	121	cpu->id_isar0 = 0x02101110;
	122	cpu->id_isar1 = 0x13112111;
	123	cpu->id_isar2 = 0x21232042;
	124	cpu->id_isar3 = 0x01112131;
	125	cpu->id_isar4 = 0x00011142;
	126	cpu->id_aa64pfr0 = 0x00002222;
	127	cpu->id_aa64dfr0 = 0x10305106;
	128	cpu->id_aa64isar0 = 0x00010000;
	129	cpu->id_aa64mmfr0 = 0x00001124;
	130	cpu->clidr = 0x0a200023;
	131	cpu->ccsidr[0] = 0x701fe00a; /* 32KB L1 dcache */
	132	cpu->ccsidr[1] = 0x201fe012; /* 48KB L1 icache */
	133	cpu->ccsidr[2] = 0x70ffe07a; /* 2048KB L2 cache */
	134	cpu->dcz_blocksize = 4; /* 64 bytes */
bf016017	135	define_arm_cp_regs(cpu, cortexa57_cp_reginfo);
cb1fa941 PM	136	}
cb1fa941 PM	137
d14d42f1 PM	138	#ifdef CONFIG_USER_ONLY
	139	static void aarch64_any_initfn(Object *obj)
	140	{
	141	ARMCPU *cpu = ARM_CPU(obj);
	142
	143	set_feature(&cpu->env, ARM_FEATURE_V8);
	144	set_feature(&cpu->env, ARM_FEATURE_VFP4);
d14d42f1	145	set_feature(&cpu->env, ARM_FEATURE_NEON);
d14d42f1	146	set_feature(&cpu->env, ARM_FEATURE_AARCH64);
25f748e3 PM	147	set_feature(&cpu->env, ARM_FEATURE_V8_AES);
	148	set_feature(&cpu->env, ARM_FEATURE_V8_SHA1);
	149	set_feature(&cpu->env, ARM_FEATURE_V8_SHA256);
	150	set_feature(&cpu->env, ARM_FEATURE_V8_PMULL);
	151	set_feature(&cpu->env, ARM_FEATURE_CRC);
7da845b0	152	cpu->ctr = 0x80030003; /* 32 byte I and D cacheline size, VIPT icache */
aca3f40b	153	cpu->dcz_blocksize = 7; /* 512 bytes */
d14d42f1 PM	154	}
	155	#endif
	156
	157	typedef struct ARMCPUInfo {
	158	const char *name;
	159	void (initfn)(Object obj);
	160	void (class_init)(ObjectClass oc, void *data);
	161	} ARMCPUInfo;
	162
	163	static const ARMCPUInfo aarch64_cpus[] = {
cb1fa941	164	{ .name = "cortex-a57", .initfn = aarch64_a57_initfn },
d14d42f1 PM	165	#ifdef CONFIG_USER_ONLY
	166	{ .name = "any", .initfn = aarch64_any_initfn },
	167	#endif
83e6813a	168	{ .name = NULL }
d14d42f1 PM	169	};
	170
	171	static void aarch64_cpu_initfn(Object *obj)
	172	{
	173	}
	174
	175	static void aarch64_cpu_finalizefn(Object *obj)
	176	{
	177	}
	178
5ce4f357 AG	179	static void aarch64_cpu_set_pc(CPUState *cs, vaddr value)
	180	{
	181	ARMCPU *cpu = ARM_CPU(cs);
7633378d PM	182	/* It's OK to look at env for the current mode here, because it's
	183	* never possible for an AArch64 TB to chain to an AArch32 TB.
	184	* (Otherwise we would need to use synchronize_from_tb instead.)
5ce4f357	185	*/
7633378d PM	186	if (is_a64(&cpu->env)) {
	187	cpu->env.pc = value;
	188	} else {
	189	cpu->env.regs[15] = value;
	190	}
5ce4f357 AG	191	}
5ce4f357 AG	192
d14d42f1 PM	193	static void aarch64_cpu_class_init(ObjectClass oc, void data)
d14d42f1 PM	194	{
14ade10f AG	195	CPUClass *cc = CPU_CLASS(oc);
14ade10f AG	196
52e60cdd	197	cc->do_interrupt = aarch64_cpu_do_interrupt;
5ce4f357	198	cc->set_pc = aarch64_cpu_set_pc;
96c04212 AG	199	cc->gdb_read_register = aarch64_cpu_gdb_read_register;
	200	cc->gdb_write_register = aarch64_cpu_gdb_write_register;
	201	cc->gdb_num_core_regs = 34;
	202	cc->gdb_core_xml_file = "aarch64-core.xml";
d14d42f1 PM	203	}
	204
	205	static void aarch64_cpu_register(const ARMCPUInfo *info)
	206	{
	207	TypeInfo type_info = {
	208	.parent = TYPE_AARCH64_CPU,
	209	.instance_size = sizeof(ARMCPU),
	210	.instance_init = info->initfn,
	211	.class_size = sizeof(ARMCPUClass),
	212	.class_init = info->class_init,
	213	};
	214
	215	type_info.name = g_strdup_printf("%s-" TYPE_ARM_CPU, info->name);
	216	type_register(&type_info);
	217	g_free((void *)type_info.name);
	218	}
	219
	220	static const TypeInfo aarch64_cpu_type_info = {
	221	.name = TYPE_AARCH64_CPU,
	222	.parent = TYPE_ARM_CPU,
	223	.instance_size = sizeof(ARMCPU),
	224	.instance_init = aarch64_cpu_initfn,
	225	.instance_finalize = aarch64_cpu_finalizefn,
	226	.abstract = true,
	227	.class_size = sizeof(AArch64CPUClass),
	228	.class_init = aarch64_cpu_class_init,
	229	};
	230
	231	static void aarch64_cpu_register_types(void)
	232	{
83e6813a	233	const ARMCPUInfo *info = aarch64_cpus;
d14d42f1 PM	234
d14d42f1 PM	235	type_register_static(&aarch64_cpu_type_info);
83e6813a PM	236
	237	while (info->name) {
	238	aarch64_cpu_register(info);
	239	info++;
d14d42f1 PM	240	}
	241	}
	242
	243	type_init(aarch64_cpu_register_types)