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d3e35a1f AG |
1 | /* |
2 | * AArch64 specific helpers | |
3 | * | |
4 | * Copyright (c) 2013 Alexander Graf <agraf@suse.de> | |
5 | * | |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
9 | * version 2 of the License, or (at your option) any later version. | |
10 | * | |
11 | * This library is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU Lesser General Public | |
17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. | |
18 | */ | |
19 | ||
20 | #include "cpu.h" | |
21 | #include "exec/gdbstub.h" | |
2ef6175a | 22 | #include "exec/helper-proto.h" |
d3e35a1f AG |
23 | #include "qemu/host-utils.h" |
24 | #include "sysemu/sysemu.h" | |
25 | #include "qemu/bitops.h" | |
52e60cdd | 26 | #include "internals.h" |
130f2e7d | 27 | #include "qemu/crc32c.h" |
34c45d53 | 28 | #include "sysemu/kvm.h" |
130f2e7d | 29 | #include <zlib.h> /* For crc32 */ |
8220e911 AG |
30 | |
31 | /* C2.4.7 Multiply and divide */ | |
32 | /* special cases for 0 and LLONG_MIN are mandated by the standard */ | |
33 | uint64_t HELPER(udiv64)(uint64_t num, uint64_t den) | |
34 | { | |
35 | if (den == 0) { | |
36 | return 0; | |
37 | } | |
38 | return num / den; | |
39 | } | |
40 | ||
41 | int64_t HELPER(sdiv64)(int64_t num, int64_t den) | |
42 | { | |
43 | if (den == 0) { | |
44 | return 0; | |
45 | } | |
46 | if (num == LLONG_MIN && den == -1) { | |
47 | return LLONG_MIN; | |
48 | } | |
49 | return num / den; | |
50 | } | |
680ead21 CF |
51 | |
52 | uint64_t HELPER(clz64)(uint64_t x) | |
53 | { | |
54 | return clz64(x); | |
55 | } | |
82e14b02 | 56 | |
e80c5020 CF |
57 | uint64_t HELPER(cls64)(uint64_t x) |
58 | { | |
59 | return clrsb64(x); | |
60 | } | |
61 | ||
62 | uint32_t HELPER(cls32)(uint32_t x) | |
63 | { | |
64 | return clrsb32(x); | |
65 | } | |
66 | ||
b05c3068 AB |
67 | uint32_t HELPER(clz32)(uint32_t x) |
68 | { | |
69 | return clz32(x); | |
70 | } | |
71 | ||
82e14b02 AG |
72 | uint64_t HELPER(rbit64)(uint64_t x) |
73 | { | |
42fedbca | 74 | return revbit64(x); |
82e14b02 | 75 | } |
da7dafe7 CF |
76 | |
77 | /* Convert a softfloat float_relation_ (as returned by | |
78 | * the float*_compare functions) to the correct ARM | |
79 | * NZCV flag state. | |
80 | */ | |
81 | static inline uint32_t float_rel_to_flags(int res) | |
82 | { | |
83 | uint64_t flags; | |
84 | switch (res) { | |
85 | case float_relation_equal: | |
86 | flags = PSTATE_Z | PSTATE_C; | |
87 | break; | |
88 | case float_relation_less: | |
89 | flags = PSTATE_N; | |
90 | break; | |
91 | case float_relation_greater: | |
92 | flags = PSTATE_C; | |
93 | break; | |
94 | case float_relation_unordered: | |
95 | default: | |
96 | flags = PSTATE_C | PSTATE_V; | |
97 | break; | |
98 | } | |
99 | return flags; | |
100 | } | |
101 | ||
102 | uint64_t HELPER(vfp_cmps_a64)(float32 x, float32 y, void *fp_status) | |
103 | { | |
104 | return float_rel_to_flags(float32_compare_quiet(x, y, fp_status)); | |
105 | } | |
106 | ||
107 | uint64_t HELPER(vfp_cmpes_a64)(float32 x, float32 y, void *fp_status) | |
108 | { | |
109 | return float_rel_to_flags(float32_compare(x, y, fp_status)); | |
110 | } | |
111 | ||
112 | uint64_t HELPER(vfp_cmpd_a64)(float64 x, float64 y, void *fp_status) | |
113 | { | |
114 | return float_rel_to_flags(float64_compare_quiet(x, y, fp_status)); | |
115 | } | |
116 | ||
117 | uint64_t HELPER(vfp_cmped_a64)(float64 x, float64 y, void *fp_status) | |
118 | { | |
119 | return float_rel_to_flags(float64_compare(x, y, fp_status)); | |
120 | } | |
7c51048f | 121 | |
f5e51e7f PM |
122 | float32 HELPER(vfp_mulxs)(float32 a, float32 b, void *fpstp) |
123 | { | |
124 | float_status *fpst = fpstp; | |
125 | ||
dabf0058 XH |
126 | a = float32_squash_input_denormal(a, fpst); |
127 | b = float32_squash_input_denormal(b, fpst); | |
128 | ||
f5e51e7f PM |
129 | if ((float32_is_zero(a) && float32_is_infinity(b)) || |
130 | (float32_is_infinity(a) && float32_is_zero(b))) { | |
131 | /* 2.0 with the sign bit set to sign(A) XOR sign(B) */ | |
132 | return make_float32((1U << 30) | | |
133 | ((float32_val(a) ^ float32_val(b)) & (1U << 31))); | |
134 | } | |
135 | return float32_mul(a, b, fpst); | |
136 | } | |
137 | ||
138 | float64 HELPER(vfp_mulxd)(float64 a, float64 b, void *fpstp) | |
139 | { | |
140 | float_status *fpst = fpstp; | |
141 | ||
dabf0058 XH |
142 | a = float64_squash_input_denormal(a, fpst); |
143 | b = float64_squash_input_denormal(b, fpst); | |
144 | ||
f5e51e7f PM |
145 | if ((float64_is_zero(a) && float64_is_infinity(b)) || |
146 | (float64_is_infinity(a) && float64_is_zero(b))) { | |
147 | /* 2.0 with the sign bit set to sign(A) XOR sign(B) */ | |
148 | return make_float64((1ULL << 62) | | |
149 | ((float64_val(a) ^ float64_val(b)) & (1ULL << 63))); | |
150 | } | |
151 | return float64_mul(a, b, fpst); | |
152 | } | |
153 | ||
7c51048f MM |
154 | uint64_t HELPER(simd_tbl)(CPUARMState *env, uint64_t result, uint64_t indices, |
155 | uint32_t rn, uint32_t numregs) | |
156 | { | |
157 | /* Helper function for SIMD TBL and TBX. We have to do the table | |
158 | * lookup part for the 64 bits worth of indices we're passed in. | |
159 | * result is the initial results vector (either zeroes for TBL | |
160 | * or some guest values for TBX), rn the register number where | |
161 | * the table starts, and numregs the number of registers in the table. | |
162 | * We return the results of the lookups. | |
163 | */ | |
164 | int shift; | |
165 | ||
166 | for (shift = 0; shift < 64; shift += 8) { | |
167 | int index = extract64(indices, shift, 8); | |
168 | if (index < 16 * numregs) { | |
169 | /* Convert index (a byte offset into the virtual table | |
170 | * which is a series of 128-bit vectors concatenated) | |
171 | * into the correct vfp.regs[] element plus a bit offset | |
172 | * into that element, bearing in mind that the table | |
173 | * can wrap around from V31 to V0. | |
174 | */ | |
175 | int elt = (rn * 2 + (index >> 3)) % 64; | |
176 | int bitidx = (index & 7) * 8; | |
177 | uint64_t val = extract64(env->vfp.regs[elt], bitidx, 8); | |
178 | ||
179 | result = deposit64(result, shift, 8, val); | |
180 | } | |
181 | } | |
182 | return result; | |
183 | } | |
8908f4d1 AB |
184 | |
185 | /* 64bit/double versions of the neon float compare functions */ | |
186 | uint64_t HELPER(neon_ceq_f64)(float64 a, float64 b, void *fpstp) | |
187 | { | |
188 | float_status *fpst = fpstp; | |
189 | return -float64_eq_quiet(a, b, fpst); | |
190 | } | |
191 | ||
192 | uint64_t HELPER(neon_cge_f64)(float64 a, float64 b, void *fpstp) | |
193 | { | |
194 | float_status *fpst = fpstp; | |
195 | return -float64_le(b, a, fpst); | |
196 | } | |
197 | ||
198 | uint64_t HELPER(neon_cgt_f64)(float64 a, float64 b, void *fpstp) | |
199 | { | |
200 | float_status *fpst = fpstp; | |
201 | return -float64_lt(b, a, fpst); | |
202 | } | |
057d5f62 PM |
203 | |
204 | /* Reciprocal step and sqrt step. Note that unlike the A32/T32 | |
205 | * versions, these do a fully fused multiply-add or | |
206 | * multiply-add-and-halve. | |
207 | */ | |
208 | #define float32_two make_float32(0x40000000) | |
209 | #define float32_three make_float32(0x40400000) | |
210 | #define float32_one_point_five make_float32(0x3fc00000) | |
211 | ||
212 | #define float64_two make_float64(0x4000000000000000ULL) | |
213 | #define float64_three make_float64(0x4008000000000000ULL) | |
214 | #define float64_one_point_five make_float64(0x3FF8000000000000ULL) | |
215 | ||
216 | float32 HELPER(recpsf_f32)(float32 a, float32 b, void *fpstp) | |
217 | { | |
218 | float_status *fpst = fpstp; | |
219 | ||
a8eb6e19 PM |
220 | a = float32_squash_input_denormal(a, fpst); |
221 | b = float32_squash_input_denormal(b, fpst); | |
222 | ||
057d5f62 PM |
223 | a = float32_chs(a); |
224 | if ((float32_is_infinity(a) && float32_is_zero(b)) || | |
225 | (float32_is_infinity(b) && float32_is_zero(a))) { | |
226 | return float32_two; | |
227 | } | |
228 | return float32_muladd(a, b, float32_two, 0, fpst); | |
229 | } | |
230 | ||
231 | float64 HELPER(recpsf_f64)(float64 a, float64 b, void *fpstp) | |
232 | { | |
233 | float_status *fpst = fpstp; | |
234 | ||
a8eb6e19 PM |
235 | a = float64_squash_input_denormal(a, fpst); |
236 | b = float64_squash_input_denormal(b, fpst); | |
237 | ||
057d5f62 PM |
238 | a = float64_chs(a); |
239 | if ((float64_is_infinity(a) && float64_is_zero(b)) || | |
240 | (float64_is_infinity(b) && float64_is_zero(a))) { | |
241 | return float64_two; | |
242 | } | |
243 | return float64_muladd(a, b, float64_two, 0, fpst); | |
244 | } | |
245 | ||
246 | float32 HELPER(rsqrtsf_f32)(float32 a, float32 b, void *fpstp) | |
247 | { | |
248 | float_status *fpst = fpstp; | |
249 | ||
a8eb6e19 PM |
250 | a = float32_squash_input_denormal(a, fpst); |
251 | b = float32_squash_input_denormal(b, fpst); | |
252 | ||
057d5f62 PM |
253 | a = float32_chs(a); |
254 | if ((float32_is_infinity(a) && float32_is_zero(b)) || | |
255 | (float32_is_infinity(b) && float32_is_zero(a))) { | |
256 | return float32_one_point_five; | |
257 | } | |
258 | return float32_muladd(a, b, float32_three, float_muladd_halve_result, fpst); | |
259 | } | |
260 | ||
261 | float64 HELPER(rsqrtsf_f64)(float64 a, float64 b, void *fpstp) | |
262 | { | |
263 | float_status *fpst = fpstp; | |
264 | ||
a8eb6e19 PM |
265 | a = float64_squash_input_denormal(a, fpst); |
266 | b = float64_squash_input_denormal(b, fpst); | |
267 | ||
057d5f62 PM |
268 | a = float64_chs(a); |
269 | if ((float64_is_infinity(a) && float64_is_zero(b)) || | |
270 | (float64_is_infinity(b) && float64_is_zero(a))) { | |
271 | return float64_one_point_five; | |
272 | } | |
273 | return float64_muladd(a, b, float64_three, float_muladd_halve_result, fpst); | |
274 | } | |
6781fa11 PM |
275 | |
276 | /* Pairwise long add: add pairs of adjacent elements into | |
277 | * double-width elements in the result (eg _s8 is an 8x8->16 op) | |
278 | */ | |
279 | uint64_t HELPER(neon_addlp_s8)(uint64_t a) | |
280 | { | |
281 | uint64_t nsignmask = 0x0080008000800080ULL; | |
282 | uint64_t wsignmask = 0x8000800080008000ULL; | |
283 | uint64_t elementmask = 0x00ff00ff00ff00ffULL; | |
284 | uint64_t tmp1, tmp2; | |
285 | uint64_t res, signres; | |
286 | ||
287 | /* Extract odd elements, sign extend each to a 16 bit field */ | |
288 | tmp1 = a & elementmask; | |
289 | tmp1 ^= nsignmask; | |
290 | tmp1 |= wsignmask; | |
291 | tmp1 = (tmp1 - nsignmask) ^ wsignmask; | |
292 | /* Ditto for the even elements */ | |
293 | tmp2 = (a >> 8) & elementmask; | |
294 | tmp2 ^= nsignmask; | |
295 | tmp2 |= wsignmask; | |
296 | tmp2 = (tmp2 - nsignmask) ^ wsignmask; | |
297 | ||
298 | /* calculate the result by summing bits 0..14, 16..22, etc, | |
299 | * and then adjusting the sign bits 15, 23, etc manually. | |
300 | * This ensures the addition can't overflow the 16 bit field. | |
301 | */ | |
302 | signres = (tmp1 ^ tmp2) & wsignmask; | |
303 | res = (tmp1 & ~wsignmask) + (tmp2 & ~wsignmask); | |
304 | res ^= signres; | |
305 | ||
306 | return res; | |
307 | } | |
308 | ||
309 | uint64_t HELPER(neon_addlp_u8)(uint64_t a) | |
310 | { | |
311 | uint64_t tmp; | |
312 | ||
313 | tmp = a & 0x00ff00ff00ff00ffULL; | |
314 | tmp += (a >> 8) & 0x00ff00ff00ff00ffULL; | |
315 | return tmp; | |
316 | } | |
317 | ||
318 | uint64_t HELPER(neon_addlp_s16)(uint64_t a) | |
319 | { | |
320 | int32_t reslo, reshi; | |
321 | ||
322 | reslo = (int32_t)(int16_t)a + (int32_t)(int16_t)(a >> 16); | |
323 | reshi = (int32_t)(int16_t)(a >> 32) + (int32_t)(int16_t)(a >> 48); | |
324 | ||
325 | return (uint32_t)reslo | (((uint64_t)reshi) << 32); | |
326 | } | |
327 | ||
328 | uint64_t HELPER(neon_addlp_u16)(uint64_t a) | |
329 | { | |
330 | uint64_t tmp; | |
331 | ||
332 | tmp = a & 0x0000ffff0000ffffULL; | |
333 | tmp += (a >> 16) & 0x0000ffff0000ffffULL; | |
334 | return tmp; | |
335 | } | |
8f0c6758 AB |
336 | |
337 | /* Floating-point reciprocal exponent - see FPRecpX in ARM ARM */ | |
338 | float32 HELPER(frecpx_f32)(float32 a, void *fpstp) | |
339 | { | |
340 | float_status *fpst = fpstp; | |
341 | uint32_t val32, sbit; | |
342 | int32_t exp; | |
343 | ||
344 | if (float32_is_any_nan(a)) { | |
345 | float32 nan = a; | |
346 | if (float32_is_signaling_nan(a)) { | |
347 | float_raise(float_flag_invalid, fpst); | |
348 | nan = float32_maybe_silence_nan(a); | |
349 | } | |
350 | if (fpst->default_nan_mode) { | |
351 | nan = float32_default_nan; | |
352 | } | |
353 | return nan; | |
354 | } | |
355 | ||
356 | val32 = float32_val(a); | |
357 | sbit = 0x80000000ULL & val32; | |
358 | exp = extract32(val32, 23, 8); | |
359 | ||
360 | if (exp == 0) { | |
361 | return make_float32(sbit | (0xfe << 23)); | |
362 | } else { | |
363 | return make_float32(sbit | (~exp & 0xff) << 23); | |
364 | } | |
365 | } | |
366 | ||
367 | float64 HELPER(frecpx_f64)(float64 a, void *fpstp) | |
368 | { | |
369 | float_status *fpst = fpstp; | |
370 | uint64_t val64, sbit; | |
371 | int64_t exp; | |
372 | ||
373 | if (float64_is_any_nan(a)) { | |
374 | float64 nan = a; | |
375 | if (float64_is_signaling_nan(a)) { | |
376 | float_raise(float_flag_invalid, fpst); | |
377 | nan = float64_maybe_silence_nan(a); | |
378 | } | |
379 | if (fpst->default_nan_mode) { | |
380 | nan = float64_default_nan; | |
381 | } | |
382 | return nan; | |
383 | } | |
384 | ||
385 | val64 = float64_val(a); | |
386 | sbit = 0x8000000000000000ULL & val64; | |
387 | exp = extract64(float64_val(a), 52, 11); | |
388 | ||
389 | if (exp == 0) { | |
390 | return make_float64(sbit | (0x7feULL << 52)); | |
391 | } else { | |
392 | return make_float64(sbit | (~exp & 0x7ffULL) << 52); | |
393 | } | |
394 | } | |
5553955e PM |
395 | |
396 | float32 HELPER(fcvtx_f64_to_f32)(float64 a, CPUARMState *env) | |
397 | { | |
398 | /* Von Neumann rounding is implemented by using round-to-zero | |
399 | * and then setting the LSB of the result if Inexact was raised. | |
400 | */ | |
401 | float32 r; | |
402 | float_status *fpst = &env->vfp.fp_status; | |
403 | float_status tstat = *fpst; | |
404 | int exflags; | |
405 | ||
406 | set_float_rounding_mode(float_round_to_zero, &tstat); | |
407 | set_float_exception_flags(0, &tstat); | |
408 | r = float64_to_float32(a, &tstat); | |
409 | r = float32_maybe_silence_nan(r); | |
410 | exflags = get_float_exception_flags(&tstat); | |
411 | if (exflags & float_flag_inexact) { | |
412 | r = make_float32(float32_val(r) | 1); | |
413 | } | |
414 | exflags |= get_float_exception_flags(fpst); | |
415 | set_float_exception_flags(exflags, fpst); | |
416 | return r; | |
417 | } | |
52e60cdd | 418 | |
130f2e7d PM |
419 | /* 64-bit versions of the CRC helpers. Note that although the operation |
420 | * (and the prototypes of crc32c() and crc32() mean that only the bottom | |
421 | * 32 bits of the accumulator and result are used, we pass and return | |
422 | * uint64_t for convenience of the generated code. Unlike the 32-bit | |
423 | * instruction set versions, val may genuinely have 64 bits of data in it. | |
424 | * The upper bytes of val (above the number specified by 'bytes') must have | |
425 | * been zeroed out by the caller. | |
426 | */ | |
427 | uint64_t HELPER(crc32_64)(uint64_t acc, uint64_t val, uint32_t bytes) | |
428 | { | |
429 | uint8_t buf[8]; | |
430 | ||
431 | stq_le_p(buf, val); | |
432 | ||
433 | /* zlib crc32 converts the accumulator and output to one's complement. */ | |
434 | return crc32(acc ^ 0xffffffff, buf, bytes) ^ 0xffffffff; | |
435 | } | |
436 | ||
437 | uint64_t HELPER(crc32c_64)(uint64_t acc, uint64_t val, uint32_t bytes) | |
438 | { | |
439 | uint8_t buf[8]; | |
440 | ||
441 | stq_le_p(buf, val); | |
442 | ||
443 | /* Linux crc32c converts the output to one's complement. */ | |
444 | return crc32c(acc, buf, bytes) ^ 0xffffffff; | |
445 | } | |
446 | ||
0adf7d3c RH |
447 | #if !defined(CONFIG_USER_ONLY) |
448 | ||
52e60cdd RH |
449 | /* Handle a CPU exception. */ |
450 | void aarch64_cpu_do_interrupt(CPUState *cs) | |
451 | { | |
452 | ARMCPU *cpu = ARM_CPU(cs); | |
453 | CPUARMState *env = &cpu->env; | |
012a906b | 454 | unsigned int new_el = env->exception.target_el; |
9e729b57 EI |
455 | target_ulong addr = env->cp15.vbar_el[new_el]; |
456 | unsigned int new_mode = aarch64_pstate_mode(new_el, true); | |
52e60cdd | 457 | |
dcbff19b | 458 | if (arm_current_el(env) < new_el) { |
52e60cdd RH |
459 | if (env->aarch64) { |
460 | addr += 0x400; | |
461 | } else { | |
462 | addr += 0x600; | |
463 | } | |
464 | } else if (pstate_read(env) & PSTATE_SP) { | |
465 | addr += 0x200; | |
466 | } | |
467 | ||
468 | arm_log_exception(cs->exception_index); | |
dbc29a86 EI |
469 | qemu_log_mask(CPU_LOG_INT, "...from EL%d to EL%d\n", arm_current_el(env), |
470 | new_el); | |
52e60cdd RH |
471 | if (qemu_loglevel_mask(CPU_LOG_INT) |
472 | && !excp_is_internal(cs->exception_index)) { | |
34c45d53 AB |
473 | qemu_log_mask(CPU_LOG_INT, "...with ESR %x/0x%" PRIx32 "\n", |
474 | env->exception.syndrome >> ARM_EL_EC_SHIFT, | |
52e60cdd RH |
475 | env->exception.syndrome); |
476 | } | |
477 | ||
98128601 RH |
478 | if (arm_is_psci_call(cpu, cs->exception_index)) { |
479 | arm_handle_psci_call(cpu); | |
480 | qemu_log_mask(CPU_LOG_INT, "...handled as PSCI call\n"); | |
481 | return; | |
482 | } | |
483 | ||
52e60cdd RH |
484 | switch (cs->exception_index) { |
485 | case EXCP_PREFETCH_ABORT: | |
486 | case EXCP_DATA_ABORT: | |
2dd081ae | 487 | env->cp15.far_el[new_el] = env->exception.vaddress; |
52e60cdd | 488 | qemu_log_mask(CPU_LOG_INT, "...with FAR 0x%" PRIx64 "\n", |
9e729b57 | 489 | env->cp15.far_el[new_el]); |
2dd081ae | 490 | /* fall through */ |
52e60cdd RH |
491 | case EXCP_BKPT: |
492 | case EXCP_UDEF: | |
493 | case EXCP_SWI: | |
35979d71 | 494 | case EXCP_HVC: |
607d98b8 | 495 | case EXCP_HYP_TRAP: |
e0d6e6a5 | 496 | case EXCP_SMC: |
2dd081ae | 497 | env->cp15.esr_el[new_el] = env->exception.syndrome; |
52e60cdd RH |
498 | break; |
499 | case EXCP_IRQ: | |
136e67e9 | 500 | case EXCP_VIRQ: |
52e60cdd RH |
501 | addr += 0x80; |
502 | break; | |
503 | case EXCP_FIQ: | |
136e67e9 | 504 | case EXCP_VFIQ: |
52e60cdd RH |
505 | addr += 0x100; |
506 | break; | |
8012c84f PM |
507 | case EXCP_SEMIHOST: |
508 | qemu_log_mask(CPU_LOG_INT, | |
509 | "...handling as semihosting call 0x%" PRIx64 "\n", | |
510 | env->xregs[0]); | |
511 | env->xregs[0] = do_arm_semihosting(env); | |
512 | return; | |
52e60cdd RH |
513 | default: |
514 | cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index); | |
515 | } | |
516 | ||
517 | if (is_a64(env)) { | |
9e729b57 | 518 | env->banked_spsr[aarch64_banked_spsr_index(new_el)] = pstate_read(env); |
dcbff19b | 519 | aarch64_save_sp(env, arm_current_el(env)); |
9e729b57 | 520 | env->elr_el[new_el] = env->pc; |
52e60cdd | 521 | } else { |
7847f9ea | 522 | env->banked_spsr[aarch64_banked_spsr_index(new_el)] = cpsr_read(env); |
52e60cdd | 523 | if (!env->thumb) { |
9e729b57 | 524 | env->cp15.esr_el[new_el] |= 1 << 25; |
52e60cdd | 525 | } |
9e729b57 | 526 | env->elr_el[new_el] = env->regs[15]; |
52e60cdd | 527 | |
ce02049d | 528 | aarch64_sync_32_to_64(env); |
52e60cdd RH |
529 | |
530 | env->condexec_bits = 0; | |
531 | } | |
b21ab1fc SB |
532 | qemu_log_mask(CPU_LOG_INT, "...with ELR 0x%" PRIx64 "\n", |
533 | env->elr_el[new_el]); | |
52e60cdd | 534 | |
9e729b57 | 535 | pstate_write(env, PSTATE_DAIF | new_mode); |
52e60cdd | 536 | env->aarch64 = 1; |
9e729b57 | 537 | aarch64_restore_sp(env, new_el); |
52e60cdd RH |
538 | |
539 | env->pc = addr; | |
34c45d53 AB |
540 | |
541 | qemu_log_mask(CPU_LOG_INT, "...to EL%d PC 0x%" PRIx64 " PSTATE 0x%x\n", | |
542 | new_el, env->pc, pstate_read(env)); | |
543 | ||
544 | if (!kvm_enabled()) { | |
545 | cs->interrupt_request |= CPU_INTERRUPT_EXITTB; | |
546 | } | |
52e60cdd | 547 | } |
0adf7d3c | 548 | #endif |