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Commit | Line | Data |
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b5ff1b31 | 1 | #include "cpu.h" |
ccd38087 | 2 | #include "internals.h" |
022c62cb | 3 | #include "exec/gdbstub.h" |
2ef6175a | 4 | #include "exec/helper-proto.h" |
1de7afc9 | 5 | #include "qemu/host-utils.h" |
78027bb6 | 6 | #include "sysemu/arch_init.h" |
9c17d615 | 7 | #include "sysemu/sysemu.h" |
1de7afc9 | 8 | #include "qemu/bitops.h" |
eb0ecd5a | 9 | #include "qemu/crc32c.h" |
f08b6170 | 10 | #include "exec/cpu_ldst.h" |
1d854765 | 11 | #include "arm_ldst.h" |
eb0ecd5a | 12 | #include <zlib.h> /* For crc32 */ |
0b03bdfc | 13 | |
4a501606 | 14 | #ifndef CONFIG_USER_ONLY |
2c8dd318 | 15 | static inline int get_phys_addr(CPUARMState *env, target_ulong address, |
4a501606 | 16 | int access_type, int is_user, |
a8170e5e | 17 | hwaddr *phys_ptr, int *prot, |
4a501606 | 18 | target_ulong *page_size); |
7c2cb42b AF |
19 | |
20 | /* Definitions for the PMCCNTR and PMCR registers */ | |
21 | #define PMCRD 0x8 | |
22 | #define PMCRC 0x4 | |
23 | #define PMCRE 0x1 | |
4a501606 PM |
24 | #endif |
25 | ||
0ecb72a5 | 26 | static int vfp_gdb_get_reg(CPUARMState *env, uint8_t *buf, int reg) |
56aebc89 PB |
27 | { |
28 | int nregs; | |
29 | ||
30 | /* VFP data registers are always little-endian. */ | |
31 | nregs = arm_feature(env, ARM_FEATURE_VFP3) ? 32 : 16; | |
32 | if (reg < nregs) { | |
33 | stfq_le_p(buf, env->vfp.regs[reg]); | |
34 | return 8; | |
35 | } | |
36 | if (arm_feature(env, ARM_FEATURE_NEON)) { | |
37 | /* Aliases for Q regs. */ | |
38 | nregs += 16; | |
39 | if (reg < nregs) { | |
40 | stfq_le_p(buf, env->vfp.regs[(reg - 32) * 2]); | |
41 | stfq_le_p(buf + 8, env->vfp.regs[(reg - 32) * 2 + 1]); | |
42 | return 16; | |
43 | } | |
44 | } | |
45 | switch (reg - nregs) { | |
46 | case 0: stl_p(buf, env->vfp.xregs[ARM_VFP_FPSID]); return 4; | |
47 | case 1: stl_p(buf, env->vfp.xregs[ARM_VFP_FPSCR]); return 4; | |
48 | case 2: stl_p(buf, env->vfp.xregs[ARM_VFP_FPEXC]); return 4; | |
49 | } | |
50 | return 0; | |
51 | } | |
52 | ||
0ecb72a5 | 53 | static int vfp_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg) |
56aebc89 PB |
54 | { |
55 | int nregs; | |
56 | ||
57 | nregs = arm_feature(env, ARM_FEATURE_VFP3) ? 32 : 16; | |
58 | if (reg < nregs) { | |
59 | env->vfp.regs[reg] = ldfq_le_p(buf); | |
60 | return 8; | |
61 | } | |
62 | if (arm_feature(env, ARM_FEATURE_NEON)) { | |
63 | nregs += 16; | |
64 | if (reg < nregs) { | |
65 | env->vfp.regs[(reg - 32) * 2] = ldfq_le_p(buf); | |
66 | env->vfp.regs[(reg - 32) * 2 + 1] = ldfq_le_p(buf + 8); | |
67 | return 16; | |
68 | } | |
69 | } | |
70 | switch (reg - nregs) { | |
71 | case 0: env->vfp.xregs[ARM_VFP_FPSID] = ldl_p(buf); return 4; | |
72 | case 1: env->vfp.xregs[ARM_VFP_FPSCR] = ldl_p(buf); return 4; | |
71b3c3de | 73 | case 2: env->vfp.xregs[ARM_VFP_FPEXC] = ldl_p(buf) & (1 << 30); return 4; |
56aebc89 PB |
74 | } |
75 | return 0; | |
76 | } | |
77 | ||
6a669427 PM |
78 | static int aarch64_fpu_gdb_get_reg(CPUARMState *env, uint8_t *buf, int reg) |
79 | { | |
80 | switch (reg) { | |
81 | case 0 ... 31: | |
82 | /* 128 bit FP register */ | |
83 | stfq_le_p(buf, env->vfp.regs[reg * 2]); | |
84 | stfq_le_p(buf + 8, env->vfp.regs[reg * 2 + 1]); | |
85 | return 16; | |
86 | case 32: | |
87 | /* FPSR */ | |
88 | stl_p(buf, vfp_get_fpsr(env)); | |
89 | return 4; | |
90 | case 33: | |
91 | /* FPCR */ | |
92 | stl_p(buf, vfp_get_fpcr(env)); | |
93 | return 4; | |
94 | default: | |
95 | return 0; | |
96 | } | |
97 | } | |
98 | ||
99 | static int aarch64_fpu_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg) | |
100 | { | |
101 | switch (reg) { | |
102 | case 0 ... 31: | |
103 | /* 128 bit FP register */ | |
104 | env->vfp.regs[reg * 2] = ldfq_le_p(buf); | |
105 | env->vfp.regs[reg * 2 + 1] = ldfq_le_p(buf + 8); | |
106 | return 16; | |
107 | case 32: | |
108 | /* FPSR */ | |
109 | vfp_set_fpsr(env, ldl_p(buf)); | |
110 | return 4; | |
111 | case 33: | |
112 | /* FPCR */ | |
113 | vfp_set_fpcr(env, ldl_p(buf)); | |
114 | return 4; | |
115 | default: | |
116 | return 0; | |
117 | } | |
118 | } | |
119 | ||
c4241c7d | 120 | static uint64_t raw_read(CPUARMState *env, const ARMCPRegInfo *ri) |
d4e6df63 | 121 | { |
67ed771d | 122 | if (cpreg_field_is_64bit(ri)) { |
c4241c7d | 123 | return CPREG_FIELD64(env, ri); |
22d9e1a9 | 124 | } else { |
c4241c7d | 125 | return CPREG_FIELD32(env, ri); |
22d9e1a9 | 126 | } |
d4e6df63 PM |
127 | } |
128 | ||
c4241c7d PM |
129 | static void raw_write(CPUARMState *env, const ARMCPRegInfo *ri, |
130 | uint64_t value) | |
d4e6df63 | 131 | { |
67ed771d | 132 | if (cpreg_field_is_64bit(ri)) { |
22d9e1a9 PM |
133 | CPREG_FIELD64(env, ri) = value; |
134 | } else { | |
135 | CPREG_FIELD32(env, ri) = value; | |
136 | } | |
d4e6df63 PM |
137 | } |
138 | ||
59a1c327 | 139 | static uint64_t read_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri) |
721fae12 | 140 | { |
59a1c327 | 141 | /* Raw read of a coprocessor register (as needed for migration, etc). */ |
721fae12 | 142 | if (ri->type & ARM_CP_CONST) { |
59a1c327 | 143 | return ri->resetvalue; |
721fae12 | 144 | } else if (ri->raw_readfn) { |
59a1c327 | 145 | return ri->raw_readfn(env, ri); |
721fae12 | 146 | } else if (ri->readfn) { |
59a1c327 | 147 | return ri->readfn(env, ri); |
721fae12 | 148 | } else { |
59a1c327 | 149 | return raw_read(env, ri); |
721fae12 | 150 | } |
721fae12 PM |
151 | } |
152 | ||
59a1c327 | 153 | static void write_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri, |
7900e9f1 | 154 | uint64_t v) |
721fae12 PM |
155 | { |
156 | /* Raw write of a coprocessor register (as needed for migration, etc). | |
721fae12 PM |
157 | * Note that constant registers are treated as write-ignored; the |
158 | * caller should check for success by whether a readback gives the | |
159 | * value written. | |
160 | */ | |
161 | if (ri->type & ARM_CP_CONST) { | |
59a1c327 | 162 | return; |
721fae12 | 163 | } else if (ri->raw_writefn) { |
c4241c7d | 164 | ri->raw_writefn(env, ri, v); |
721fae12 | 165 | } else if (ri->writefn) { |
c4241c7d | 166 | ri->writefn(env, ri, v); |
721fae12 | 167 | } else { |
afb2530f | 168 | raw_write(env, ri, v); |
721fae12 | 169 | } |
721fae12 PM |
170 | } |
171 | ||
172 | bool write_cpustate_to_list(ARMCPU *cpu) | |
173 | { | |
174 | /* Write the coprocessor state from cpu->env to the (index,value) list. */ | |
175 | int i; | |
176 | bool ok = true; | |
177 | ||
178 | for (i = 0; i < cpu->cpreg_array_len; i++) { | |
179 | uint32_t regidx = kvm_to_cpreg_id(cpu->cpreg_indexes[i]); | |
180 | const ARMCPRegInfo *ri; | |
59a1c327 | 181 | |
60322b39 | 182 | ri = get_arm_cp_reginfo(cpu->cp_regs, regidx); |
721fae12 PM |
183 | if (!ri) { |
184 | ok = false; | |
185 | continue; | |
186 | } | |
187 | if (ri->type & ARM_CP_NO_MIGRATE) { | |
188 | continue; | |
189 | } | |
59a1c327 | 190 | cpu->cpreg_values[i] = read_raw_cp_reg(&cpu->env, ri); |
721fae12 PM |
191 | } |
192 | return ok; | |
193 | } | |
194 | ||
195 | bool write_list_to_cpustate(ARMCPU *cpu) | |
196 | { | |
197 | int i; | |
198 | bool ok = true; | |
199 | ||
200 | for (i = 0; i < cpu->cpreg_array_len; i++) { | |
201 | uint32_t regidx = kvm_to_cpreg_id(cpu->cpreg_indexes[i]); | |
202 | uint64_t v = cpu->cpreg_values[i]; | |
721fae12 PM |
203 | const ARMCPRegInfo *ri; |
204 | ||
60322b39 | 205 | ri = get_arm_cp_reginfo(cpu->cp_regs, regidx); |
721fae12 PM |
206 | if (!ri) { |
207 | ok = false; | |
208 | continue; | |
209 | } | |
210 | if (ri->type & ARM_CP_NO_MIGRATE) { | |
211 | continue; | |
212 | } | |
213 | /* Write value and confirm it reads back as written | |
214 | * (to catch read-only registers and partially read-only | |
215 | * registers where the incoming migration value doesn't match) | |
216 | */ | |
59a1c327 PM |
217 | write_raw_cp_reg(&cpu->env, ri, v); |
218 | if (read_raw_cp_reg(&cpu->env, ri) != v) { | |
721fae12 PM |
219 | ok = false; |
220 | } | |
221 | } | |
222 | return ok; | |
223 | } | |
224 | ||
225 | static void add_cpreg_to_list(gpointer key, gpointer opaque) | |
226 | { | |
227 | ARMCPU *cpu = opaque; | |
228 | uint64_t regidx; | |
229 | const ARMCPRegInfo *ri; | |
230 | ||
231 | regidx = *(uint32_t *)key; | |
60322b39 | 232 | ri = get_arm_cp_reginfo(cpu->cp_regs, regidx); |
721fae12 PM |
233 | |
234 | if (!(ri->type & ARM_CP_NO_MIGRATE)) { | |
235 | cpu->cpreg_indexes[cpu->cpreg_array_len] = cpreg_to_kvm_id(regidx); | |
236 | /* The value array need not be initialized at this point */ | |
237 | cpu->cpreg_array_len++; | |
238 | } | |
239 | } | |
240 | ||
241 | static void count_cpreg(gpointer key, gpointer opaque) | |
242 | { | |
243 | ARMCPU *cpu = opaque; | |
244 | uint64_t regidx; | |
245 | const ARMCPRegInfo *ri; | |
246 | ||
247 | regidx = *(uint32_t *)key; | |
60322b39 | 248 | ri = get_arm_cp_reginfo(cpu->cp_regs, regidx); |
721fae12 PM |
249 | |
250 | if (!(ri->type & ARM_CP_NO_MIGRATE)) { | |
251 | cpu->cpreg_array_len++; | |
252 | } | |
253 | } | |
254 | ||
255 | static gint cpreg_key_compare(gconstpointer a, gconstpointer b) | |
256 | { | |
cbf239b7 AR |
257 | uint64_t aidx = cpreg_to_kvm_id(*(uint32_t *)a); |
258 | uint64_t bidx = cpreg_to_kvm_id(*(uint32_t *)b); | |
721fae12 | 259 | |
cbf239b7 AR |
260 | if (aidx > bidx) { |
261 | return 1; | |
262 | } | |
263 | if (aidx < bidx) { | |
264 | return -1; | |
265 | } | |
266 | return 0; | |
721fae12 PM |
267 | } |
268 | ||
82a3a118 PM |
269 | static void cpreg_make_keylist(gpointer key, gpointer value, gpointer udata) |
270 | { | |
271 | GList **plist = udata; | |
272 | ||
273 | *plist = g_list_prepend(*plist, key); | |
274 | } | |
275 | ||
721fae12 PM |
276 | void init_cpreg_list(ARMCPU *cpu) |
277 | { | |
278 | /* Initialise the cpreg_tuples[] array based on the cp_regs hash. | |
279 | * Note that we require cpreg_tuples[] to be sorted by key ID. | |
280 | */ | |
82a3a118 | 281 | GList *keys = NULL; |
721fae12 PM |
282 | int arraylen; |
283 | ||
82a3a118 PM |
284 | g_hash_table_foreach(cpu->cp_regs, cpreg_make_keylist, &keys); |
285 | ||
721fae12 PM |
286 | keys = g_list_sort(keys, cpreg_key_compare); |
287 | ||
288 | cpu->cpreg_array_len = 0; | |
289 | ||
290 | g_list_foreach(keys, count_cpreg, cpu); | |
291 | ||
292 | arraylen = cpu->cpreg_array_len; | |
293 | cpu->cpreg_indexes = g_new(uint64_t, arraylen); | |
294 | cpu->cpreg_values = g_new(uint64_t, arraylen); | |
295 | cpu->cpreg_vmstate_indexes = g_new(uint64_t, arraylen); | |
296 | cpu->cpreg_vmstate_values = g_new(uint64_t, arraylen); | |
297 | cpu->cpreg_vmstate_array_len = cpu->cpreg_array_len; | |
298 | cpu->cpreg_array_len = 0; | |
299 | ||
300 | g_list_foreach(keys, add_cpreg_to_list, cpu); | |
301 | ||
302 | assert(cpu->cpreg_array_len == arraylen); | |
303 | ||
304 | g_list_free(keys); | |
305 | } | |
306 | ||
014406b5 PM |
307 | /* Return true if extended addresses are enabled. |
308 | * This is always the case if our translation regime is 64 bit, | |
309 | * but depends on TTBCR.EAE for 32 bit. | |
310 | */ | |
311 | static inline bool extended_addresses_enabled(CPUARMState *env) | |
312 | { | |
313 | return arm_el_is_aa64(env, 1) | |
314 | || ((arm_feature(env, ARM_FEATURE_LPAE) | |
e389be16 | 315 | && (env->cp15.c2_control & TTBCR_EAE))); |
014406b5 PM |
316 | } |
317 | ||
c4241c7d | 318 | static void dacr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) |
c983fe6c | 319 | { |
00c8cb0a AF |
320 | ARMCPU *cpu = arm_env_get_cpu(env); |
321 | ||
8d5c773e | 322 | raw_write(env, ri, value); |
00c8cb0a | 323 | tlb_flush(CPU(cpu), 1); /* Flush TLB as domain not tracked in TLB */ |
c983fe6c PM |
324 | } |
325 | ||
c4241c7d | 326 | static void fcse_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) |
08de207b | 327 | { |
00c8cb0a AF |
328 | ARMCPU *cpu = arm_env_get_cpu(env); |
329 | ||
8d5c773e | 330 | if (raw_read(env, ri) != value) { |
08de207b PM |
331 | /* Unlike real hardware the qemu TLB uses virtual addresses, |
332 | * not modified virtual addresses, so this causes a TLB flush. | |
333 | */ | |
00c8cb0a | 334 | tlb_flush(CPU(cpu), 1); |
8d5c773e | 335 | raw_write(env, ri, value); |
08de207b | 336 | } |
08de207b | 337 | } |
c4241c7d PM |
338 | |
339 | static void contextidr_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
340 | uint64_t value) | |
08de207b | 341 | { |
00c8cb0a AF |
342 | ARMCPU *cpu = arm_env_get_cpu(env); |
343 | ||
8d5c773e | 344 | if (raw_read(env, ri) != value && !arm_feature(env, ARM_FEATURE_MPU) |
014406b5 | 345 | && !extended_addresses_enabled(env)) { |
08de207b PM |
346 | /* For VMSA (when not using the LPAE long descriptor page table |
347 | * format) this register includes the ASID, so do a TLB flush. | |
348 | * For PMSA it is purely a process ID and no action is needed. | |
349 | */ | |
00c8cb0a | 350 | tlb_flush(CPU(cpu), 1); |
08de207b | 351 | } |
8d5c773e | 352 | raw_write(env, ri, value); |
08de207b PM |
353 | } |
354 | ||
c4241c7d PM |
355 | static void tlbiall_write(CPUARMState *env, const ARMCPRegInfo *ri, |
356 | uint64_t value) | |
d929823f PM |
357 | { |
358 | /* Invalidate all (TLBIALL) */ | |
00c8cb0a AF |
359 | ARMCPU *cpu = arm_env_get_cpu(env); |
360 | ||
361 | tlb_flush(CPU(cpu), 1); | |
d929823f PM |
362 | } |
363 | ||
c4241c7d PM |
364 | static void tlbimva_write(CPUARMState *env, const ARMCPRegInfo *ri, |
365 | uint64_t value) | |
d929823f PM |
366 | { |
367 | /* Invalidate single TLB entry by MVA and ASID (TLBIMVA) */ | |
31b030d4 AF |
368 | ARMCPU *cpu = arm_env_get_cpu(env); |
369 | ||
370 | tlb_flush_page(CPU(cpu), value & TARGET_PAGE_MASK); | |
d929823f PM |
371 | } |
372 | ||
c4241c7d PM |
373 | static void tlbiasid_write(CPUARMState *env, const ARMCPRegInfo *ri, |
374 | uint64_t value) | |
d929823f PM |
375 | { |
376 | /* Invalidate by ASID (TLBIASID) */ | |
00c8cb0a AF |
377 | ARMCPU *cpu = arm_env_get_cpu(env); |
378 | ||
379 | tlb_flush(CPU(cpu), value == 0); | |
d929823f PM |
380 | } |
381 | ||
c4241c7d PM |
382 | static void tlbimvaa_write(CPUARMState *env, const ARMCPRegInfo *ri, |
383 | uint64_t value) | |
d929823f PM |
384 | { |
385 | /* Invalidate single entry by MVA, all ASIDs (TLBIMVAA) */ | |
31b030d4 AF |
386 | ARMCPU *cpu = arm_env_get_cpu(env); |
387 | ||
388 | tlb_flush_page(CPU(cpu), value & TARGET_PAGE_MASK); | |
d929823f PM |
389 | } |
390 | ||
e9aa6c21 PM |
391 | static const ARMCPRegInfo cp_reginfo[] = { |
392 | /* DBGDIDR: just RAZ. In particular this means the "debug architecture | |
393 | * version" bits will read as a reserved value, which should cause | |
394 | * Linux to not try to use the debug hardware. | |
395 | */ | |
396 | { .name = "DBGDIDR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 0, | |
397 | .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
08de207b PM |
398 | { .name = "FCSEIDR", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 0, |
399 | .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c13_fcse), | |
d4e6df63 | 400 | .resetvalue = 0, .writefn = fcse_write, .raw_writefn = raw_write, }, |
014406b5 PM |
401 | { .name = "CONTEXTIDR", .state = ARM_CP_STATE_BOTH, |
402 | .opc0 = 3, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 1, | |
403 | .access = PL1_RW, | |
404 | .fieldoffset = offsetof(CPUARMState, cp15.contextidr_el1), | |
d4e6df63 | 405 | .resetvalue = 0, .writefn = contextidr_write, .raw_writefn = raw_write, }, |
9449fdf6 PM |
406 | REGINFO_SENTINEL |
407 | }; | |
408 | ||
409 | static const ARMCPRegInfo not_v8_cp_reginfo[] = { | |
410 | /* NB: Some of these registers exist in v8 but with more precise | |
411 | * definitions that don't use CP_ANY wildcards (mostly in v8_cp_reginfo[]). | |
412 | */ | |
413 | /* MMU Domain access control / MPU write buffer control */ | |
414 | { .name = "DACR", .cp = 15, | |
415 | .crn = 3, .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY, | |
416 | .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c3), | |
417 | .resetvalue = 0, .writefn = dacr_write, .raw_writefn = raw_write, }, | |
4fdd17dd PM |
418 | /* ??? This covers not just the impdef TLB lockdown registers but also |
419 | * some v7VMSA registers relating to TEX remap, so it is overly broad. | |
420 | */ | |
421 | { .name = "TLB_LOCKDOWN", .cp = 15, .crn = 10, .crm = CP_ANY, | |
422 | .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_NOP }, | |
d929823f PM |
423 | /* MMU TLB control. Note that the wildcarding means we cover not just |
424 | * the unified TLB ops but also the dside/iside/inner-shareable variants. | |
425 | */ | |
426 | { .name = "TLBIALL", .cp = 15, .crn = 8, .crm = CP_ANY, | |
d4e6df63 PM |
427 | .opc1 = CP_ANY, .opc2 = 0, .access = PL1_W, .writefn = tlbiall_write, |
428 | .type = ARM_CP_NO_MIGRATE }, | |
d929823f | 429 | { .name = "TLBIMVA", .cp = 15, .crn = 8, .crm = CP_ANY, |
d4e6df63 PM |
430 | .opc1 = CP_ANY, .opc2 = 1, .access = PL1_W, .writefn = tlbimva_write, |
431 | .type = ARM_CP_NO_MIGRATE }, | |
d929823f | 432 | { .name = "TLBIASID", .cp = 15, .crn = 8, .crm = CP_ANY, |
d4e6df63 PM |
433 | .opc1 = CP_ANY, .opc2 = 2, .access = PL1_W, .writefn = tlbiasid_write, |
434 | .type = ARM_CP_NO_MIGRATE }, | |
d929823f | 435 | { .name = "TLBIMVAA", .cp = 15, .crn = 8, .crm = CP_ANY, |
d4e6df63 PM |
436 | .opc1 = CP_ANY, .opc2 = 3, .access = PL1_W, .writefn = tlbimvaa_write, |
437 | .type = ARM_CP_NO_MIGRATE }, | |
c4804214 PM |
438 | /* Cache maintenance ops; some of this space may be overridden later. */ |
439 | { .name = "CACHEMAINT", .cp = 15, .crn = 7, .crm = CP_ANY, | |
440 | .opc1 = 0, .opc2 = CP_ANY, .access = PL1_W, | |
441 | .type = ARM_CP_NOP | ARM_CP_OVERRIDE }, | |
e9aa6c21 PM |
442 | REGINFO_SENTINEL |
443 | }; | |
444 | ||
7d57f408 PM |
445 | static const ARMCPRegInfo not_v6_cp_reginfo[] = { |
446 | /* Not all pre-v6 cores implemented this WFI, so this is slightly | |
447 | * over-broad. | |
448 | */ | |
449 | { .name = "WFI_v5", .cp = 15, .crn = 7, .crm = 8, .opc1 = 0, .opc2 = 2, | |
450 | .access = PL1_W, .type = ARM_CP_WFI }, | |
451 | REGINFO_SENTINEL | |
452 | }; | |
453 | ||
454 | static const ARMCPRegInfo not_v7_cp_reginfo[] = { | |
455 | /* Standard v6 WFI (also used in some pre-v6 cores); not in v7 (which | |
456 | * is UNPREDICTABLE; we choose to NOP as most implementations do). | |
457 | */ | |
458 | { .name = "WFI_v6", .cp = 15, .crn = 7, .crm = 0, .opc1 = 0, .opc2 = 4, | |
459 | .access = PL1_W, .type = ARM_CP_WFI }, | |
34f90529 PM |
460 | /* L1 cache lockdown. Not architectural in v6 and earlier but in practice |
461 | * implemented in 926, 946, 1026, 1136, 1176 and 11MPCore. StrongARM and | |
462 | * OMAPCP will override this space. | |
463 | */ | |
464 | { .name = "DLOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 0, .opc2 = 0, | |
465 | .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_data), | |
466 | .resetvalue = 0 }, | |
467 | { .name = "ILOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 0, .opc2 = 1, | |
468 | .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_insn), | |
469 | .resetvalue = 0 }, | |
776d4e5c PM |
470 | /* v6 doesn't have the cache ID registers but Linux reads them anyway */ |
471 | { .name = "DUMMY", .cp = 15, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = CP_ANY, | |
d4e6df63 PM |
472 | .access = PL1_R, .type = ARM_CP_CONST | ARM_CP_NO_MIGRATE, |
473 | .resetvalue = 0 }, | |
7d57f408 PM |
474 | REGINFO_SENTINEL |
475 | }; | |
476 | ||
c4241c7d PM |
477 | static void cpacr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
478 | uint64_t value) | |
2771db27 | 479 | { |
f0aff255 FA |
480 | uint32_t mask = 0; |
481 | ||
482 | /* In ARMv8 most bits of CPACR_EL1 are RES0. */ | |
483 | if (!arm_feature(env, ARM_FEATURE_V8)) { | |
484 | /* ARMv7 defines bits for unimplemented coprocessors as RAZ/WI. | |
485 | * ASEDIS [31] and D32DIS [30] are both UNK/SBZP without VFP. | |
486 | * TRCDIS [28] is RAZ/WI since we do not implement a trace macrocell. | |
487 | */ | |
488 | if (arm_feature(env, ARM_FEATURE_VFP)) { | |
489 | /* VFP coprocessor: cp10 & cp11 [23:20] */ | |
490 | mask |= (1 << 31) | (1 << 30) | (0xf << 20); | |
491 | ||
492 | if (!arm_feature(env, ARM_FEATURE_NEON)) { | |
493 | /* ASEDIS [31] bit is RAO/WI */ | |
494 | value |= (1 << 31); | |
495 | } | |
496 | ||
497 | /* VFPv3 and upwards with NEON implement 32 double precision | |
498 | * registers (D0-D31). | |
499 | */ | |
500 | if (!arm_feature(env, ARM_FEATURE_NEON) || | |
501 | !arm_feature(env, ARM_FEATURE_VFP3)) { | |
502 | /* D32DIS [30] is RAO/WI if D16-31 are not implemented. */ | |
503 | value |= (1 << 30); | |
504 | } | |
505 | } | |
506 | value &= mask; | |
2771db27 | 507 | } |
f0aff255 | 508 | env->cp15.c1_coproc = value; |
2771db27 PM |
509 | } |
510 | ||
7d57f408 PM |
511 | static const ARMCPRegInfo v6_cp_reginfo[] = { |
512 | /* prefetch by MVA in v6, NOP in v7 */ | |
513 | { .name = "MVA_prefetch", | |
514 | .cp = 15, .crn = 7, .crm = 13, .opc1 = 0, .opc2 = 1, | |
515 | .access = PL1_W, .type = ARM_CP_NOP }, | |
516 | { .name = "ISB", .cp = 15, .crn = 7, .crm = 5, .opc1 = 0, .opc2 = 4, | |
517 | .access = PL0_W, .type = ARM_CP_NOP }, | |
091fd17c | 518 | { .name = "DSB", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 4, |
7d57f408 | 519 | .access = PL0_W, .type = ARM_CP_NOP }, |
091fd17c | 520 | { .name = "DMB", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 5, |
7d57f408 | 521 | .access = PL0_W, .type = ARM_CP_NOP }, |
06d76f31 | 522 | { .name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 2, |
6cd8a264 RH |
523 | .access = PL1_RW, |
524 | .fieldoffset = offsetofhigh32(CPUARMState, cp15.far_el1), | |
06d76f31 PM |
525 | .resetvalue = 0, }, |
526 | /* Watchpoint Fault Address Register : should actually only be present | |
527 | * for 1136, 1176, 11MPCore. | |
528 | */ | |
529 | { .name = "WFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1, | |
530 | .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0, }, | |
34222fb8 PM |
531 | { .name = "CPACR", .state = ARM_CP_STATE_BOTH, .opc0 = 3, |
532 | .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 2, | |
2771db27 PM |
533 | .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c1_coproc), |
534 | .resetvalue = 0, .writefn = cpacr_write }, | |
7d57f408 PM |
535 | REGINFO_SENTINEL |
536 | }; | |
537 | ||
fcd25206 | 538 | static CPAccessResult pmreg_access(CPUARMState *env, const ARMCPRegInfo *ri) |
200ac0ef | 539 | { |
3b163b01 | 540 | /* Performance monitor registers user accessibility is controlled |
fcd25206 | 541 | * by PMUSERENR. |
200ac0ef PM |
542 | */ |
543 | if (arm_current_pl(env) == 0 && !env->cp15.c9_pmuserenr) { | |
fcd25206 | 544 | return CP_ACCESS_TRAP; |
200ac0ef | 545 | } |
fcd25206 | 546 | return CP_ACCESS_OK; |
200ac0ef PM |
547 | } |
548 | ||
7c2cb42b | 549 | #ifndef CONFIG_USER_ONLY |
c4241c7d PM |
550 | static void pmcr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
551 | uint64_t value) | |
200ac0ef | 552 | { |
7c2cb42b AF |
553 | /* Don't computer the number of ticks in user mode */ |
554 | uint32_t temp_ticks; | |
555 | ||
556 | temp_ticks = qemu_clock_get_us(QEMU_CLOCK_VIRTUAL) * | |
557 | get_ticks_per_sec() / 1000000; | |
558 | ||
559 | if (env->cp15.c9_pmcr & PMCRE) { | |
560 | /* If the counter is enabled */ | |
561 | if (env->cp15.c9_pmcr & PMCRD) { | |
562 | /* Increment once every 64 processor clock cycles */ | |
563 | env->cp15.c15_ccnt = (temp_ticks/64) - env->cp15.c15_ccnt; | |
564 | } else { | |
565 | env->cp15.c15_ccnt = temp_ticks - env->cp15.c15_ccnt; | |
566 | } | |
567 | } | |
568 | ||
569 | if (value & PMCRC) { | |
570 | /* The counter has been reset */ | |
571 | env->cp15.c15_ccnt = 0; | |
572 | } | |
573 | ||
200ac0ef PM |
574 | /* only the DP, X, D and E bits are writable */ |
575 | env->cp15.c9_pmcr &= ~0x39; | |
576 | env->cp15.c9_pmcr |= (value & 0x39); | |
7c2cb42b AF |
577 | |
578 | if (env->cp15.c9_pmcr & PMCRE) { | |
579 | if (env->cp15.c9_pmcr & PMCRD) { | |
580 | /* Increment once every 64 processor clock cycles */ | |
581 | temp_ticks /= 64; | |
582 | } | |
583 | env->cp15.c15_ccnt = temp_ticks - env->cp15.c15_ccnt; | |
584 | } | |
585 | } | |
586 | ||
587 | static uint64_t pmccntr_read(CPUARMState *env, const ARMCPRegInfo *ri) | |
588 | { | |
589 | uint32_t total_ticks; | |
590 | ||
591 | if (!(env->cp15.c9_pmcr & PMCRE)) { | |
592 | /* Counter is disabled, do not change value */ | |
593 | return env->cp15.c15_ccnt; | |
594 | } | |
595 | ||
596 | total_ticks = qemu_clock_get_us(QEMU_CLOCK_VIRTUAL) * | |
597 | get_ticks_per_sec() / 1000000; | |
598 | ||
599 | if (env->cp15.c9_pmcr & PMCRD) { | |
600 | /* Increment once every 64 processor clock cycles */ | |
601 | total_ticks /= 64; | |
602 | } | |
603 | return total_ticks - env->cp15.c15_ccnt; | |
604 | } | |
605 | ||
606 | static void pmccntr_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
607 | uint64_t value) | |
608 | { | |
609 | uint32_t total_ticks; | |
610 | ||
611 | if (!(env->cp15.c9_pmcr & PMCRE)) { | |
612 | /* Counter is disabled, set the absolute value */ | |
613 | env->cp15.c15_ccnt = value; | |
614 | return; | |
615 | } | |
616 | ||
617 | total_ticks = qemu_clock_get_us(QEMU_CLOCK_VIRTUAL) * | |
618 | get_ticks_per_sec() / 1000000; | |
619 | ||
620 | if (env->cp15.c9_pmcr & PMCRD) { | |
621 | /* Increment once every 64 processor clock cycles */ | |
622 | total_ticks /= 64; | |
623 | } | |
624 | env->cp15.c15_ccnt = total_ticks - value; | |
200ac0ef | 625 | } |
7c2cb42b | 626 | #endif |
200ac0ef | 627 | |
c4241c7d | 628 | static void pmcntenset_write(CPUARMState *env, const ARMCPRegInfo *ri, |
200ac0ef PM |
629 | uint64_t value) |
630 | { | |
200ac0ef PM |
631 | value &= (1 << 31); |
632 | env->cp15.c9_pmcnten |= value; | |
200ac0ef PM |
633 | } |
634 | ||
c4241c7d PM |
635 | static void pmcntenclr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
636 | uint64_t value) | |
200ac0ef | 637 | { |
200ac0ef PM |
638 | value &= (1 << 31); |
639 | env->cp15.c9_pmcnten &= ~value; | |
200ac0ef PM |
640 | } |
641 | ||
c4241c7d PM |
642 | static void pmovsr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
643 | uint64_t value) | |
200ac0ef | 644 | { |
200ac0ef | 645 | env->cp15.c9_pmovsr &= ~value; |
200ac0ef PM |
646 | } |
647 | ||
c4241c7d PM |
648 | static void pmxevtyper_write(CPUARMState *env, const ARMCPRegInfo *ri, |
649 | uint64_t value) | |
200ac0ef | 650 | { |
200ac0ef | 651 | env->cp15.c9_pmxevtyper = value & 0xff; |
200ac0ef PM |
652 | } |
653 | ||
c4241c7d | 654 | static void pmuserenr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
200ac0ef PM |
655 | uint64_t value) |
656 | { | |
657 | env->cp15.c9_pmuserenr = value & 1; | |
200ac0ef PM |
658 | } |
659 | ||
c4241c7d PM |
660 | static void pmintenset_write(CPUARMState *env, const ARMCPRegInfo *ri, |
661 | uint64_t value) | |
200ac0ef PM |
662 | { |
663 | /* We have no event counters so only the C bit can be changed */ | |
664 | value &= (1 << 31); | |
665 | env->cp15.c9_pminten |= value; | |
200ac0ef PM |
666 | } |
667 | ||
c4241c7d PM |
668 | static void pmintenclr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
669 | uint64_t value) | |
200ac0ef PM |
670 | { |
671 | value &= (1 << 31); | |
672 | env->cp15.c9_pminten &= ~value; | |
200ac0ef PM |
673 | } |
674 | ||
c4241c7d PM |
675 | static void vbar_write(CPUARMState *env, const ARMCPRegInfo *ri, |
676 | uint64_t value) | |
8641136c | 677 | { |
a505d7fe PM |
678 | /* Note that even though the AArch64 view of this register has bits |
679 | * [10:0] all RES0 we can only mask the bottom 5, to comply with the | |
680 | * architectural requirements for bits which are RES0 only in some | |
681 | * contexts. (ARMv8 would permit us to do no masking at all, but ARMv7 | |
682 | * requires the bottom five bits to be RAZ/WI because they're UNK/SBZP.) | |
683 | */ | |
855ea66d | 684 | raw_write(env, ri, value & ~0x1FULL); |
8641136c NR |
685 | } |
686 | ||
c4241c7d | 687 | static uint64_t ccsidr_read(CPUARMState *env, const ARMCPRegInfo *ri) |
776d4e5c PM |
688 | { |
689 | ARMCPU *cpu = arm_env_get_cpu(env); | |
c4241c7d | 690 | return cpu->ccsidr[env->cp15.c0_cssel]; |
776d4e5c PM |
691 | } |
692 | ||
c4241c7d PM |
693 | static void csselr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
694 | uint64_t value) | |
776d4e5c | 695 | { |
8d5c773e | 696 | raw_write(env, ri, value & 0xf); |
776d4e5c PM |
697 | } |
698 | ||
1090b9c6 PM |
699 | static uint64_t isr_read(CPUARMState *env, const ARMCPRegInfo *ri) |
700 | { | |
701 | CPUState *cs = ENV_GET_CPU(env); | |
702 | uint64_t ret = 0; | |
703 | ||
704 | if (cs->interrupt_request & CPU_INTERRUPT_HARD) { | |
705 | ret |= CPSR_I; | |
706 | } | |
707 | if (cs->interrupt_request & CPU_INTERRUPT_FIQ) { | |
708 | ret |= CPSR_F; | |
709 | } | |
710 | /* External aborts are not possible in QEMU so A bit is always clear */ | |
711 | return ret; | |
712 | } | |
713 | ||
e9aa6c21 PM |
714 | static const ARMCPRegInfo v7_cp_reginfo[] = { |
715 | /* DBGDRAR, DBGDSAR: always RAZ since we don't implement memory mapped | |
716 | * debug components | |
717 | */ | |
718 | { .name = "DBGDRAR", .cp = 14, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 0, | |
719 | .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
091fd17c | 720 | { .name = "DBGDSAR", .cp = 14, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 0, |
e9aa6c21 | 721 | .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 }, |
7d57f408 PM |
722 | /* the old v6 WFI, UNPREDICTABLE in v7 but we choose to NOP */ |
723 | { .name = "NOP", .cp = 15, .crn = 7, .crm = 0, .opc1 = 0, .opc2 = 4, | |
724 | .access = PL1_W, .type = ARM_CP_NOP }, | |
200ac0ef PM |
725 | /* Performance monitors are implementation defined in v7, |
726 | * but with an ARM recommended set of registers, which we | |
727 | * follow (although we don't actually implement any counters) | |
728 | * | |
729 | * Performance registers fall into three categories: | |
730 | * (a) always UNDEF in PL0, RW in PL1 (PMINTENSET, PMINTENCLR) | |
731 | * (b) RO in PL0 (ie UNDEF on write), RW in PL1 (PMUSERENR) | |
732 | * (c) UNDEF in PL0 if PMUSERENR.EN==0, otherwise accessible (all others) | |
733 | * For the cases controlled by PMUSERENR we must set .access to PL0_RW | |
734 | * or PL0_RO as appropriate and then check PMUSERENR in the helper fn. | |
735 | */ | |
736 | { .name = "PMCNTENSET", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 1, | |
737 | .access = PL0_RW, .resetvalue = 0, | |
738 | .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcnten), | |
fcd25206 PM |
739 | .writefn = pmcntenset_write, |
740 | .accessfn = pmreg_access, | |
741 | .raw_writefn = raw_write }, | |
200ac0ef PM |
742 | { .name = "PMCNTENCLR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 2, |
743 | .access = PL0_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcnten), | |
fcd25206 PM |
744 | .accessfn = pmreg_access, |
745 | .writefn = pmcntenclr_write, | |
d4e6df63 | 746 | .type = ARM_CP_NO_MIGRATE }, |
200ac0ef PM |
747 | { .name = "PMOVSR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 3, |
748 | .access = PL0_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_pmovsr), | |
fcd25206 PM |
749 | .accessfn = pmreg_access, |
750 | .writefn = pmovsr_write, | |
751 | .raw_writefn = raw_write }, | |
752 | /* Unimplemented so WI. */ | |
200ac0ef | 753 | { .name = "PMSWINC", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 4, |
fcd25206 | 754 | .access = PL0_W, .accessfn = pmreg_access, .type = ARM_CP_NOP }, |
200ac0ef | 755 | /* Since we don't implement any events, writing to PMSELR is UNPREDICTABLE. |
fcd25206 | 756 | * We choose to RAZ/WI. |
200ac0ef PM |
757 | */ |
758 | { .name = "PMSELR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 5, | |
fcd25206 PM |
759 | .access = PL0_RW, .type = ARM_CP_CONST, .resetvalue = 0, |
760 | .accessfn = pmreg_access }, | |
7c2cb42b | 761 | #ifndef CONFIG_USER_ONLY |
200ac0ef | 762 | { .name = "PMCCNTR", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 0, |
7c2cb42b AF |
763 | .access = PL0_RW, .resetvalue = 0, .type = ARM_CP_IO, |
764 | .readfn = pmccntr_read, .writefn = pmccntr_write, | |
fcd25206 | 765 | .accessfn = pmreg_access }, |
7c2cb42b | 766 | #endif |
200ac0ef PM |
767 | { .name = "PMXEVTYPER", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 1, |
768 | .access = PL0_RW, | |
769 | .fieldoffset = offsetof(CPUARMState, cp15.c9_pmxevtyper), | |
fcd25206 PM |
770 | .accessfn = pmreg_access, .writefn = pmxevtyper_write, |
771 | .raw_writefn = raw_write }, | |
772 | /* Unimplemented, RAZ/WI. */ | |
200ac0ef | 773 | { .name = "PMXEVCNTR", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 2, |
fcd25206 PM |
774 | .access = PL0_RW, .type = ARM_CP_CONST, .resetvalue = 0, |
775 | .accessfn = pmreg_access }, | |
200ac0ef PM |
776 | { .name = "PMUSERENR", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 0, |
777 | .access = PL0_R | PL1_RW, | |
778 | .fieldoffset = offsetof(CPUARMState, cp15.c9_pmuserenr), | |
779 | .resetvalue = 0, | |
d4e6df63 | 780 | .writefn = pmuserenr_write, .raw_writefn = raw_write }, |
200ac0ef PM |
781 | { .name = "PMINTENSET", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 1, |
782 | .access = PL1_RW, | |
783 | .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten), | |
784 | .resetvalue = 0, | |
d4e6df63 | 785 | .writefn = pmintenset_write, .raw_writefn = raw_write }, |
200ac0ef | 786 | { .name = "PMINTENCLR", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 2, |
d4e6df63 | 787 | .access = PL1_RW, .type = ARM_CP_NO_MIGRATE, |
200ac0ef | 788 | .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten), |
d4e6df63 | 789 | .resetvalue = 0, .writefn = pmintenclr_write, }, |
a505d7fe PM |
790 | { .name = "VBAR", .state = ARM_CP_STATE_BOTH, |
791 | .opc0 = 3, .crn = 12, .crm = 0, .opc1 = 0, .opc2 = 0, | |
8641136c | 792 | .access = PL1_RW, .writefn = vbar_write, |
68fdb6c5 | 793 | .fieldoffset = offsetof(CPUARMState, cp15.vbar_el[1]), |
8641136c | 794 | .resetvalue = 0 }, |
2771db27 PM |
795 | { .name = "SCR", .cp = 15, .crn = 1, .crm = 1, .opc1 = 0, .opc2 = 0, |
796 | .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c1_scr), | |
797 | .resetvalue = 0, }, | |
7da845b0 PM |
798 | { .name = "CCSIDR", .state = ARM_CP_STATE_BOTH, |
799 | .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 0, | |
d4e6df63 | 800 | .access = PL1_R, .readfn = ccsidr_read, .type = ARM_CP_NO_MIGRATE }, |
7da845b0 PM |
801 | { .name = "CSSELR", .state = ARM_CP_STATE_BOTH, |
802 | .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 2, .opc2 = 0, | |
776d4e5c PM |
803 | .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c0_cssel), |
804 | .writefn = csselr_write, .resetvalue = 0 }, | |
805 | /* Auxiliary ID register: this actually has an IMPDEF value but for now | |
806 | * just RAZ for all cores: | |
807 | */ | |
0ff644a7 PM |
808 | { .name = "AIDR", .state = ARM_CP_STATE_BOTH, |
809 | .opc0 = 3, .opc1 = 1, .crn = 0, .crm = 0, .opc2 = 7, | |
776d4e5c | 810 | .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 }, |
f32cdad5 PM |
811 | /* Auxiliary fault status registers: these also are IMPDEF, and we |
812 | * choose to RAZ/WI for all cores. | |
813 | */ | |
814 | { .name = "AFSR0_EL1", .state = ARM_CP_STATE_BOTH, | |
815 | .opc0 = 3, .opc1 = 0, .crn = 5, .crm = 1, .opc2 = 0, | |
816 | .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
817 | { .name = "AFSR1_EL1", .state = ARM_CP_STATE_BOTH, | |
818 | .opc0 = 3, .opc1 = 0, .crn = 5, .crm = 1, .opc2 = 1, | |
819 | .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
b0fe2427 PM |
820 | /* MAIR can just read-as-written because we don't implement caches |
821 | * and so don't need to care about memory attributes. | |
822 | */ | |
823 | { .name = "MAIR_EL1", .state = ARM_CP_STATE_AA64, | |
824 | .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 2, .opc2 = 0, | |
825 | .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.mair_el1), | |
826 | .resetvalue = 0 }, | |
827 | /* For non-long-descriptor page tables these are PRRR and NMRR; | |
828 | * regardless they still act as reads-as-written for QEMU. | |
829 | * The override is necessary because of the overly-broad TLB_LOCKDOWN | |
830 | * definition. | |
831 | */ | |
832 | { .name = "MAIR0", .state = ARM_CP_STATE_AA32, .type = ARM_CP_OVERRIDE, | |
833 | .cp = 15, .opc1 = 0, .crn = 10, .crm = 2, .opc2 = 0, .access = PL1_RW, | |
834 | .fieldoffset = offsetoflow32(CPUARMState, cp15.mair_el1), | |
835 | .resetfn = arm_cp_reset_ignore }, | |
836 | { .name = "MAIR1", .state = ARM_CP_STATE_AA32, .type = ARM_CP_OVERRIDE, | |
837 | .cp = 15, .opc1 = 0, .crn = 10, .crm = 2, .opc2 = 1, .access = PL1_RW, | |
838 | .fieldoffset = offsetofhigh32(CPUARMState, cp15.mair_el1), | |
839 | .resetfn = arm_cp_reset_ignore }, | |
1090b9c6 PM |
840 | { .name = "ISR_EL1", .state = ARM_CP_STATE_BOTH, |
841 | .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 1, .opc2 = 0, | |
842 | .type = ARM_CP_NO_MIGRATE, .access = PL1_R, .readfn = isr_read }, | |
e9aa6c21 PM |
843 | REGINFO_SENTINEL |
844 | }; | |
845 | ||
c4241c7d PM |
846 | static void teecr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
847 | uint64_t value) | |
c326b979 PM |
848 | { |
849 | value &= 1; | |
850 | env->teecr = value; | |
c326b979 PM |
851 | } |
852 | ||
c4241c7d | 853 | static CPAccessResult teehbr_access(CPUARMState *env, const ARMCPRegInfo *ri) |
c326b979 | 854 | { |
c326b979 | 855 | if (arm_current_pl(env) == 0 && (env->teecr & 1)) { |
92611c00 | 856 | return CP_ACCESS_TRAP; |
c326b979 | 857 | } |
92611c00 | 858 | return CP_ACCESS_OK; |
c326b979 PM |
859 | } |
860 | ||
861 | static const ARMCPRegInfo t2ee_cp_reginfo[] = { | |
862 | { .name = "TEECR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 6, .opc2 = 0, | |
863 | .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, teecr), | |
864 | .resetvalue = 0, | |
865 | .writefn = teecr_write }, | |
866 | { .name = "TEEHBR", .cp = 14, .crn = 1, .crm = 0, .opc1 = 6, .opc2 = 0, | |
867 | .access = PL0_RW, .fieldoffset = offsetof(CPUARMState, teehbr), | |
92611c00 | 868 | .accessfn = teehbr_access, .resetvalue = 0 }, |
c326b979 PM |
869 | REGINFO_SENTINEL |
870 | }; | |
871 | ||
4d31c596 | 872 | static const ARMCPRegInfo v6k_cp_reginfo[] = { |
e4fe830b PM |
873 | { .name = "TPIDR_EL0", .state = ARM_CP_STATE_AA64, |
874 | .opc0 = 3, .opc1 = 3, .opc2 = 2, .crn = 13, .crm = 0, | |
875 | .access = PL0_RW, | |
876 | .fieldoffset = offsetof(CPUARMState, cp15.tpidr_el0), .resetvalue = 0 }, | |
4d31c596 PM |
877 | { .name = "TPIDRURW", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 2, |
878 | .access = PL0_RW, | |
e4fe830b PM |
879 | .fieldoffset = offsetoflow32(CPUARMState, cp15.tpidr_el0), |
880 | .resetfn = arm_cp_reset_ignore }, | |
881 | { .name = "TPIDRRO_EL0", .state = ARM_CP_STATE_AA64, | |
882 | .opc0 = 3, .opc1 = 3, .opc2 = 3, .crn = 13, .crm = 0, | |
883 | .access = PL0_R|PL1_W, | |
884 | .fieldoffset = offsetof(CPUARMState, cp15.tpidrro_el0), .resetvalue = 0 }, | |
4d31c596 PM |
885 | { .name = "TPIDRURO", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 3, |
886 | .access = PL0_R|PL1_W, | |
e4fe830b PM |
887 | .fieldoffset = offsetoflow32(CPUARMState, cp15.tpidrro_el0), |
888 | .resetfn = arm_cp_reset_ignore }, | |
889 | { .name = "TPIDR_EL1", .state = ARM_CP_STATE_BOTH, | |
890 | .opc0 = 3, .opc1 = 0, .opc2 = 4, .crn = 13, .crm = 0, | |
4d31c596 | 891 | .access = PL1_RW, |
e4fe830b | 892 | .fieldoffset = offsetof(CPUARMState, cp15.tpidr_el1), .resetvalue = 0 }, |
4d31c596 PM |
893 | REGINFO_SENTINEL |
894 | }; | |
895 | ||
55d284af PM |
896 | #ifndef CONFIG_USER_ONLY |
897 | ||
00108f2d PM |
898 | static CPAccessResult gt_cntfrq_access(CPUARMState *env, const ARMCPRegInfo *ri) |
899 | { | |
900 | /* CNTFRQ: not visible from PL0 if both PL0PCTEN and PL0VCTEN are zero */ | |
901 | if (arm_current_pl(env) == 0 && !extract32(env->cp15.c14_cntkctl, 0, 2)) { | |
902 | return CP_ACCESS_TRAP; | |
903 | } | |
904 | return CP_ACCESS_OK; | |
905 | } | |
906 | ||
907 | static CPAccessResult gt_counter_access(CPUARMState *env, int timeridx) | |
908 | { | |
909 | /* CNT[PV]CT: not visible from PL0 if ELO[PV]CTEN is zero */ | |
910 | if (arm_current_pl(env) == 0 && | |
911 | !extract32(env->cp15.c14_cntkctl, timeridx, 1)) { | |
912 | return CP_ACCESS_TRAP; | |
913 | } | |
914 | return CP_ACCESS_OK; | |
915 | } | |
916 | ||
917 | static CPAccessResult gt_timer_access(CPUARMState *env, int timeridx) | |
918 | { | |
919 | /* CNT[PV]_CVAL, CNT[PV]_CTL, CNT[PV]_TVAL: not visible from PL0 if | |
920 | * EL0[PV]TEN is zero. | |
921 | */ | |
922 | if (arm_current_pl(env) == 0 && | |
923 | !extract32(env->cp15.c14_cntkctl, 9 - timeridx, 1)) { | |
924 | return CP_ACCESS_TRAP; | |
925 | } | |
926 | return CP_ACCESS_OK; | |
927 | } | |
928 | ||
929 | static CPAccessResult gt_pct_access(CPUARMState *env, | |
930 | const ARMCPRegInfo *ri) | |
931 | { | |
932 | return gt_counter_access(env, GTIMER_PHYS); | |
933 | } | |
934 | ||
935 | static CPAccessResult gt_vct_access(CPUARMState *env, | |
936 | const ARMCPRegInfo *ri) | |
937 | { | |
938 | return gt_counter_access(env, GTIMER_VIRT); | |
939 | } | |
940 | ||
941 | static CPAccessResult gt_ptimer_access(CPUARMState *env, const ARMCPRegInfo *ri) | |
942 | { | |
943 | return gt_timer_access(env, GTIMER_PHYS); | |
944 | } | |
945 | ||
946 | static CPAccessResult gt_vtimer_access(CPUARMState *env, const ARMCPRegInfo *ri) | |
947 | { | |
948 | return gt_timer_access(env, GTIMER_VIRT); | |
949 | } | |
950 | ||
55d284af PM |
951 | static uint64_t gt_get_countervalue(CPUARMState *env) |
952 | { | |
bc72ad67 | 953 | return qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) / GTIMER_SCALE; |
55d284af PM |
954 | } |
955 | ||
956 | static void gt_recalc_timer(ARMCPU *cpu, int timeridx) | |
957 | { | |
958 | ARMGenericTimer *gt = &cpu->env.cp15.c14_timer[timeridx]; | |
959 | ||
960 | if (gt->ctl & 1) { | |
961 | /* Timer enabled: calculate and set current ISTATUS, irq, and | |
962 | * reset timer to when ISTATUS next has to change | |
963 | */ | |
964 | uint64_t count = gt_get_countervalue(&cpu->env); | |
965 | /* Note that this must be unsigned 64 bit arithmetic: */ | |
966 | int istatus = count >= gt->cval; | |
967 | uint64_t nexttick; | |
968 | ||
969 | gt->ctl = deposit32(gt->ctl, 2, 1, istatus); | |
970 | qemu_set_irq(cpu->gt_timer_outputs[timeridx], | |
971 | (istatus && !(gt->ctl & 2))); | |
972 | if (istatus) { | |
973 | /* Next transition is when count rolls back over to zero */ | |
974 | nexttick = UINT64_MAX; | |
975 | } else { | |
976 | /* Next transition is when we hit cval */ | |
977 | nexttick = gt->cval; | |
978 | } | |
979 | /* Note that the desired next expiry time might be beyond the | |
980 | * signed-64-bit range of a QEMUTimer -- in this case we just | |
981 | * set the timer for as far in the future as possible. When the | |
982 | * timer expires we will reset the timer for any remaining period. | |
983 | */ | |
984 | if (nexttick > INT64_MAX / GTIMER_SCALE) { | |
985 | nexttick = INT64_MAX / GTIMER_SCALE; | |
986 | } | |
bc72ad67 | 987 | timer_mod(cpu->gt_timer[timeridx], nexttick); |
55d284af PM |
988 | } else { |
989 | /* Timer disabled: ISTATUS and timer output always clear */ | |
990 | gt->ctl &= ~4; | |
991 | qemu_set_irq(cpu->gt_timer_outputs[timeridx], 0); | |
bc72ad67 | 992 | timer_del(cpu->gt_timer[timeridx]); |
55d284af PM |
993 | } |
994 | } | |
995 | ||
55d284af PM |
996 | static void gt_cnt_reset(CPUARMState *env, const ARMCPRegInfo *ri) |
997 | { | |
998 | ARMCPU *cpu = arm_env_get_cpu(env); | |
999 | int timeridx = ri->opc1 & 1; | |
1000 | ||
bc72ad67 | 1001 | timer_del(cpu->gt_timer[timeridx]); |
55d284af PM |
1002 | } |
1003 | ||
c4241c7d | 1004 | static uint64_t gt_cnt_read(CPUARMState *env, const ARMCPRegInfo *ri) |
55d284af | 1005 | { |
c4241c7d | 1006 | return gt_get_countervalue(env); |
55d284af PM |
1007 | } |
1008 | ||
c4241c7d PM |
1009 | static void gt_cval_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1010 | uint64_t value) | |
55d284af PM |
1011 | { |
1012 | int timeridx = ri->opc1 & 1; | |
1013 | ||
1014 | env->cp15.c14_timer[timeridx].cval = value; | |
1015 | gt_recalc_timer(arm_env_get_cpu(env), timeridx); | |
55d284af | 1016 | } |
c4241c7d PM |
1017 | |
1018 | static uint64_t gt_tval_read(CPUARMState *env, const ARMCPRegInfo *ri) | |
55d284af PM |
1019 | { |
1020 | int timeridx = ri->crm & 1; | |
1021 | ||
c4241c7d PM |
1022 | return (uint32_t)(env->cp15.c14_timer[timeridx].cval - |
1023 | gt_get_countervalue(env)); | |
55d284af PM |
1024 | } |
1025 | ||
c4241c7d PM |
1026 | static void gt_tval_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1027 | uint64_t value) | |
55d284af PM |
1028 | { |
1029 | int timeridx = ri->crm & 1; | |
1030 | ||
1031 | env->cp15.c14_timer[timeridx].cval = gt_get_countervalue(env) + | |
1032 | + sextract64(value, 0, 32); | |
1033 | gt_recalc_timer(arm_env_get_cpu(env), timeridx); | |
55d284af PM |
1034 | } |
1035 | ||
c4241c7d PM |
1036 | static void gt_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1037 | uint64_t value) | |
55d284af PM |
1038 | { |
1039 | ARMCPU *cpu = arm_env_get_cpu(env); | |
1040 | int timeridx = ri->crm & 1; | |
1041 | uint32_t oldval = env->cp15.c14_timer[timeridx].ctl; | |
1042 | ||
d3afacc7 | 1043 | env->cp15.c14_timer[timeridx].ctl = deposit64(oldval, 0, 2, value); |
55d284af PM |
1044 | if ((oldval ^ value) & 1) { |
1045 | /* Enable toggled */ | |
1046 | gt_recalc_timer(cpu, timeridx); | |
d3afacc7 | 1047 | } else if ((oldval ^ value) & 2) { |
55d284af PM |
1048 | /* IMASK toggled: don't need to recalculate, |
1049 | * just set the interrupt line based on ISTATUS | |
1050 | */ | |
1051 | qemu_set_irq(cpu->gt_timer_outputs[timeridx], | |
d3afacc7 | 1052 | (oldval & 4) && !(value & 2)); |
55d284af | 1053 | } |
55d284af PM |
1054 | } |
1055 | ||
1056 | void arm_gt_ptimer_cb(void *opaque) | |
1057 | { | |
1058 | ARMCPU *cpu = opaque; | |
1059 | ||
1060 | gt_recalc_timer(cpu, GTIMER_PHYS); | |
1061 | } | |
1062 | ||
1063 | void arm_gt_vtimer_cb(void *opaque) | |
1064 | { | |
1065 | ARMCPU *cpu = opaque; | |
1066 | ||
1067 | gt_recalc_timer(cpu, GTIMER_VIRT); | |
1068 | } | |
1069 | ||
1070 | static const ARMCPRegInfo generic_timer_cp_reginfo[] = { | |
1071 | /* Note that CNTFRQ is purely reads-as-written for the benefit | |
1072 | * of software; writing it doesn't actually change the timer frequency. | |
1073 | * Our reset value matches the fixed frequency we implement the timer at. | |
1074 | */ | |
1075 | { .name = "CNTFRQ", .cp = 15, .crn = 14, .crm = 0, .opc1 = 0, .opc2 = 0, | |
a7adc4b7 PM |
1076 | .type = ARM_CP_NO_MIGRATE, |
1077 | .access = PL1_RW | PL0_R, .accessfn = gt_cntfrq_access, | |
1078 | .fieldoffset = offsetoflow32(CPUARMState, cp15.c14_cntfrq), | |
1079 | .resetfn = arm_cp_reset_ignore, | |
1080 | }, | |
1081 | { .name = "CNTFRQ_EL0", .state = ARM_CP_STATE_AA64, | |
1082 | .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 0, | |
1083 | .access = PL1_RW | PL0_R, .accessfn = gt_cntfrq_access, | |
55d284af PM |
1084 | .fieldoffset = offsetof(CPUARMState, cp15.c14_cntfrq), |
1085 | .resetvalue = (1000 * 1000 * 1000) / GTIMER_SCALE, | |
55d284af PM |
1086 | }, |
1087 | /* overall control: mostly access permissions */ | |
a7adc4b7 PM |
1088 | { .name = "CNTKCTL", .state = ARM_CP_STATE_BOTH, |
1089 | .opc0 = 3, .opc1 = 0, .crn = 14, .crm = 1, .opc2 = 0, | |
55d284af PM |
1090 | .access = PL1_RW, |
1091 | .fieldoffset = offsetof(CPUARMState, cp15.c14_cntkctl), | |
1092 | .resetvalue = 0, | |
1093 | }, | |
1094 | /* per-timer control */ | |
1095 | { .name = "CNTP_CTL", .cp = 15, .crn = 14, .crm = 2, .opc1 = 0, .opc2 = 1, | |
a7adc4b7 PM |
1096 | .type = ARM_CP_IO | ARM_CP_NO_MIGRATE, .access = PL1_RW | PL0_R, |
1097 | .accessfn = gt_ptimer_access, | |
1098 | .fieldoffset = offsetoflow32(CPUARMState, | |
1099 | cp15.c14_timer[GTIMER_PHYS].ctl), | |
1100 | .resetfn = arm_cp_reset_ignore, | |
1101 | .writefn = gt_ctl_write, .raw_writefn = raw_write, | |
1102 | }, | |
1103 | { .name = "CNTP_CTL_EL0", .state = ARM_CP_STATE_AA64, | |
1104 | .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 2, .opc2 = 1, | |
55d284af | 1105 | .type = ARM_CP_IO, .access = PL1_RW | PL0_R, |
a7adc4b7 | 1106 | .accessfn = gt_ptimer_access, |
55d284af PM |
1107 | .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].ctl), |
1108 | .resetvalue = 0, | |
00108f2d | 1109 | .writefn = gt_ctl_write, .raw_writefn = raw_write, |
55d284af PM |
1110 | }, |
1111 | { .name = "CNTV_CTL", .cp = 15, .crn = 14, .crm = 3, .opc1 = 0, .opc2 = 1, | |
a7adc4b7 PM |
1112 | .type = ARM_CP_IO | ARM_CP_NO_MIGRATE, .access = PL1_RW | PL0_R, |
1113 | .accessfn = gt_vtimer_access, | |
1114 | .fieldoffset = offsetoflow32(CPUARMState, | |
1115 | cp15.c14_timer[GTIMER_VIRT].ctl), | |
1116 | .resetfn = arm_cp_reset_ignore, | |
1117 | .writefn = gt_ctl_write, .raw_writefn = raw_write, | |
1118 | }, | |
1119 | { .name = "CNTV_CTL_EL0", .state = ARM_CP_STATE_AA64, | |
1120 | .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 3, .opc2 = 1, | |
55d284af | 1121 | .type = ARM_CP_IO, .access = PL1_RW | PL0_R, |
a7adc4b7 | 1122 | .accessfn = gt_vtimer_access, |
55d284af PM |
1123 | .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].ctl), |
1124 | .resetvalue = 0, | |
00108f2d | 1125 | .writefn = gt_ctl_write, .raw_writefn = raw_write, |
55d284af PM |
1126 | }, |
1127 | /* TimerValue views: a 32 bit downcounting view of the underlying state */ | |
1128 | { .name = "CNTP_TVAL", .cp = 15, .crn = 14, .crm = 2, .opc1 = 0, .opc2 = 0, | |
1129 | .type = ARM_CP_NO_MIGRATE | ARM_CP_IO, .access = PL1_RW | PL0_R, | |
00108f2d | 1130 | .accessfn = gt_ptimer_access, |
55d284af PM |
1131 | .readfn = gt_tval_read, .writefn = gt_tval_write, |
1132 | }, | |
a7adc4b7 PM |
1133 | { .name = "CNTP_TVAL_EL0", .state = ARM_CP_STATE_AA64, |
1134 | .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 2, .opc2 = 0, | |
1135 | .type = ARM_CP_NO_MIGRATE | ARM_CP_IO, .access = PL1_RW | PL0_R, | |
1136 | .readfn = gt_tval_read, .writefn = gt_tval_write, | |
1137 | }, | |
55d284af PM |
1138 | { .name = "CNTV_TVAL", .cp = 15, .crn = 14, .crm = 3, .opc1 = 0, .opc2 = 0, |
1139 | .type = ARM_CP_NO_MIGRATE | ARM_CP_IO, .access = PL1_RW | PL0_R, | |
00108f2d | 1140 | .accessfn = gt_vtimer_access, |
55d284af PM |
1141 | .readfn = gt_tval_read, .writefn = gt_tval_write, |
1142 | }, | |
a7adc4b7 PM |
1143 | { .name = "CNTV_TVAL_EL0", .state = ARM_CP_STATE_AA64, |
1144 | .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 3, .opc2 = 0, | |
1145 | .type = ARM_CP_NO_MIGRATE | ARM_CP_IO, .access = PL1_RW | PL0_R, | |
1146 | .readfn = gt_tval_read, .writefn = gt_tval_write, | |
1147 | }, | |
55d284af PM |
1148 | /* The counter itself */ |
1149 | { .name = "CNTPCT", .cp = 15, .crm = 14, .opc1 = 0, | |
1150 | .access = PL0_R, .type = ARM_CP_64BIT | ARM_CP_NO_MIGRATE | ARM_CP_IO, | |
00108f2d | 1151 | .accessfn = gt_pct_access, |
a7adc4b7 PM |
1152 | .readfn = gt_cnt_read, .resetfn = arm_cp_reset_ignore, |
1153 | }, | |
1154 | { .name = "CNTPCT_EL0", .state = ARM_CP_STATE_AA64, | |
1155 | .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 1, | |
1156 | .access = PL0_R, .type = ARM_CP_NO_MIGRATE | ARM_CP_IO, | |
1157 | .accessfn = gt_pct_access, | |
55d284af PM |
1158 | .readfn = gt_cnt_read, .resetfn = gt_cnt_reset, |
1159 | }, | |
1160 | { .name = "CNTVCT", .cp = 15, .crm = 14, .opc1 = 1, | |
1161 | .access = PL0_R, .type = ARM_CP_64BIT | ARM_CP_NO_MIGRATE | ARM_CP_IO, | |
00108f2d | 1162 | .accessfn = gt_vct_access, |
a7adc4b7 PM |
1163 | .readfn = gt_cnt_read, .resetfn = arm_cp_reset_ignore, |
1164 | }, | |
1165 | { .name = "CNTVCT_EL0", .state = ARM_CP_STATE_AA64, | |
1166 | .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 2, | |
1167 | .access = PL0_R, .type = ARM_CP_NO_MIGRATE | ARM_CP_IO, | |
1168 | .accessfn = gt_vct_access, | |
55d284af PM |
1169 | .readfn = gt_cnt_read, .resetfn = gt_cnt_reset, |
1170 | }, | |
1171 | /* Comparison value, indicating when the timer goes off */ | |
1172 | { .name = "CNTP_CVAL", .cp = 15, .crm = 14, .opc1 = 2, | |
1173 | .access = PL1_RW | PL0_R, | |
a7adc4b7 | 1174 | .type = ARM_CP_64BIT | ARM_CP_IO | ARM_CP_NO_MIGRATE, |
55d284af | 1175 | .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].cval), |
a7adc4b7 PM |
1176 | .accessfn = gt_ptimer_access, .resetfn = arm_cp_reset_ignore, |
1177 | .writefn = gt_cval_write, .raw_writefn = raw_write, | |
1178 | }, | |
1179 | { .name = "CNTP_CVAL_EL0", .state = ARM_CP_STATE_AA64, | |
1180 | .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 2, .opc2 = 2, | |
1181 | .access = PL1_RW | PL0_R, | |
1182 | .type = ARM_CP_IO, | |
1183 | .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].cval), | |
1184 | .resetvalue = 0, .accessfn = gt_vtimer_access, | |
00108f2d | 1185 | .writefn = gt_cval_write, .raw_writefn = raw_write, |
55d284af PM |
1186 | }, |
1187 | { .name = "CNTV_CVAL", .cp = 15, .crm = 14, .opc1 = 3, | |
1188 | .access = PL1_RW | PL0_R, | |
a7adc4b7 | 1189 | .type = ARM_CP_64BIT | ARM_CP_IO | ARM_CP_NO_MIGRATE, |
55d284af | 1190 | .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].cval), |
a7adc4b7 PM |
1191 | .accessfn = gt_vtimer_access, .resetfn = arm_cp_reset_ignore, |
1192 | .writefn = gt_cval_write, .raw_writefn = raw_write, | |
1193 | }, | |
1194 | { .name = "CNTV_CVAL_EL0", .state = ARM_CP_STATE_AA64, | |
1195 | .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 3, .opc2 = 2, | |
1196 | .access = PL1_RW | PL0_R, | |
1197 | .type = ARM_CP_IO, | |
1198 | .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].cval), | |
1199 | .resetvalue = 0, .accessfn = gt_vtimer_access, | |
00108f2d | 1200 | .writefn = gt_cval_write, .raw_writefn = raw_write, |
55d284af PM |
1201 | }, |
1202 | REGINFO_SENTINEL | |
1203 | }; | |
1204 | ||
1205 | #else | |
1206 | /* In user-mode none of the generic timer registers are accessible, | |
bc72ad67 | 1207 | * and their implementation depends on QEMU_CLOCK_VIRTUAL and qdev gpio outputs, |
55d284af PM |
1208 | * so instead just don't register any of them. |
1209 | */ | |
6cc7a3ae | 1210 | static const ARMCPRegInfo generic_timer_cp_reginfo[] = { |
6cc7a3ae PM |
1211 | REGINFO_SENTINEL |
1212 | }; | |
1213 | ||
55d284af PM |
1214 | #endif |
1215 | ||
c4241c7d | 1216 | static void par_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) |
4a501606 | 1217 | { |
891a2fe7 | 1218 | if (arm_feature(env, ARM_FEATURE_LPAE)) { |
8d5c773e | 1219 | raw_write(env, ri, value); |
891a2fe7 | 1220 | } else if (arm_feature(env, ARM_FEATURE_V7)) { |
8d5c773e | 1221 | raw_write(env, ri, value & 0xfffff6ff); |
4a501606 | 1222 | } else { |
8d5c773e | 1223 | raw_write(env, ri, value & 0xfffff1ff); |
4a501606 | 1224 | } |
4a501606 PM |
1225 | } |
1226 | ||
1227 | #ifndef CONFIG_USER_ONLY | |
1228 | /* get_phys_addr() isn't present for user-mode-only targets */ | |
702a9357 | 1229 | |
92611c00 PM |
1230 | static CPAccessResult ats_access(CPUARMState *env, const ARMCPRegInfo *ri) |
1231 | { | |
1232 | if (ri->opc2 & 4) { | |
1233 | /* Other states are only available with TrustZone; in | |
1234 | * a non-TZ implementation these registers don't exist | |
1235 | * at all, which is an Uncategorized trap. This underdecoding | |
1236 | * is safe because the reginfo is NO_MIGRATE. | |
1237 | */ | |
1238 | return CP_ACCESS_TRAP_UNCATEGORIZED; | |
1239 | } | |
1240 | return CP_ACCESS_OK; | |
1241 | } | |
1242 | ||
c4241c7d | 1243 | static void ats_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) |
4a501606 | 1244 | { |
a8170e5e | 1245 | hwaddr phys_addr; |
4a501606 PM |
1246 | target_ulong page_size; |
1247 | int prot; | |
1248 | int ret, is_user = ri->opc2 & 2; | |
1249 | int access_type = ri->opc2 & 1; | |
1250 | ||
4a501606 PM |
1251 | ret = get_phys_addr(env, value, access_type, is_user, |
1252 | &phys_addr, &prot, &page_size); | |
702a9357 PM |
1253 | if (extended_addresses_enabled(env)) { |
1254 | /* ret is a DFSR/IFSR value for the long descriptor | |
1255 | * translation table format, but with WnR always clear. | |
1256 | * Convert it to a 64-bit PAR. | |
1257 | */ | |
1258 | uint64_t par64 = (1 << 11); /* LPAE bit always set */ | |
1259 | if (ret == 0) { | |
1260 | par64 |= phys_addr & ~0xfffULL; | |
1261 | /* We don't set the ATTR or SH fields in the PAR. */ | |
4a501606 | 1262 | } else { |
702a9357 PM |
1263 | par64 |= 1; /* F */ |
1264 | par64 |= (ret & 0x3f) << 1; /* FS */ | |
1265 | /* Note that S2WLK and FSTAGE are always zero, because we don't | |
1266 | * implement virtualization and therefore there can't be a stage 2 | |
1267 | * fault. | |
1268 | */ | |
4a501606 | 1269 | } |
19525524 | 1270 | env->cp15.par_el1 = par64; |
4a501606 | 1271 | } else { |
702a9357 PM |
1272 | /* ret is a DFSR/IFSR value for the short descriptor |
1273 | * translation table format (with WnR always clear). | |
1274 | * Convert it to a 32-bit PAR. | |
1275 | */ | |
1276 | if (ret == 0) { | |
1277 | /* We do not set any attribute bits in the PAR */ | |
1278 | if (page_size == (1 << 24) | |
1279 | && arm_feature(env, ARM_FEATURE_V7)) { | |
19525524 | 1280 | env->cp15.par_el1 = (phys_addr & 0xff000000) | 1 << 1; |
702a9357 | 1281 | } else { |
19525524 | 1282 | env->cp15.par_el1 = phys_addr & 0xfffff000; |
702a9357 PM |
1283 | } |
1284 | } else { | |
19525524 | 1285 | env->cp15.par_el1 = ((ret & (1 << 10)) >> 5) | |
775fda92 | 1286 | ((ret & (1 << 12)) >> 6) | |
702a9357 PM |
1287 | ((ret & 0xf) << 1) | 1; |
1288 | } | |
4a501606 | 1289 | } |
4a501606 PM |
1290 | } |
1291 | #endif | |
1292 | ||
1293 | static const ARMCPRegInfo vapa_cp_reginfo[] = { | |
1294 | { .name = "PAR", .cp = 15, .crn = 7, .crm = 4, .opc1 = 0, .opc2 = 0, | |
1295 | .access = PL1_RW, .resetvalue = 0, | |
19525524 | 1296 | .fieldoffset = offsetoflow32(CPUARMState, cp15.par_el1), |
4a501606 PM |
1297 | .writefn = par_write }, |
1298 | #ifndef CONFIG_USER_ONLY | |
1299 | { .name = "ATS", .cp = 15, .crn = 7, .crm = 8, .opc1 = 0, .opc2 = CP_ANY, | |
92611c00 PM |
1300 | .access = PL1_W, .accessfn = ats_access, |
1301 | .writefn = ats_write, .type = ARM_CP_NO_MIGRATE }, | |
4a501606 PM |
1302 | #endif |
1303 | REGINFO_SENTINEL | |
1304 | }; | |
1305 | ||
18032bec PM |
1306 | /* Return basic MPU access permission bits. */ |
1307 | static uint32_t simple_mpu_ap_bits(uint32_t val) | |
1308 | { | |
1309 | uint32_t ret; | |
1310 | uint32_t mask; | |
1311 | int i; | |
1312 | ret = 0; | |
1313 | mask = 3; | |
1314 | for (i = 0; i < 16; i += 2) { | |
1315 | ret |= (val >> i) & mask; | |
1316 | mask <<= 2; | |
1317 | } | |
1318 | return ret; | |
1319 | } | |
1320 | ||
1321 | /* Pad basic MPU access permission bits to extended format. */ | |
1322 | static uint32_t extended_mpu_ap_bits(uint32_t val) | |
1323 | { | |
1324 | uint32_t ret; | |
1325 | uint32_t mask; | |
1326 | int i; | |
1327 | ret = 0; | |
1328 | mask = 3; | |
1329 | for (i = 0; i < 16; i += 2) { | |
1330 | ret |= (val & mask) << i; | |
1331 | mask <<= 2; | |
1332 | } | |
1333 | return ret; | |
1334 | } | |
1335 | ||
c4241c7d PM |
1336 | static void pmsav5_data_ap_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1337 | uint64_t value) | |
18032bec | 1338 | { |
7e09797c | 1339 | env->cp15.pmsav5_data_ap = extended_mpu_ap_bits(value); |
18032bec PM |
1340 | } |
1341 | ||
c4241c7d | 1342 | static uint64_t pmsav5_data_ap_read(CPUARMState *env, const ARMCPRegInfo *ri) |
18032bec | 1343 | { |
7e09797c | 1344 | return simple_mpu_ap_bits(env->cp15.pmsav5_data_ap); |
18032bec PM |
1345 | } |
1346 | ||
c4241c7d PM |
1347 | static void pmsav5_insn_ap_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1348 | uint64_t value) | |
18032bec | 1349 | { |
7e09797c | 1350 | env->cp15.pmsav5_insn_ap = extended_mpu_ap_bits(value); |
18032bec PM |
1351 | } |
1352 | ||
c4241c7d | 1353 | static uint64_t pmsav5_insn_ap_read(CPUARMState *env, const ARMCPRegInfo *ri) |
18032bec | 1354 | { |
7e09797c | 1355 | return simple_mpu_ap_bits(env->cp15.pmsav5_insn_ap); |
18032bec PM |
1356 | } |
1357 | ||
1358 | static const ARMCPRegInfo pmsav5_cp_reginfo[] = { | |
1359 | { .name = "DATA_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 0, | |
d4e6df63 | 1360 | .access = PL1_RW, .type = ARM_CP_NO_MIGRATE, |
7e09797c PM |
1361 | .fieldoffset = offsetof(CPUARMState, cp15.pmsav5_data_ap), |
1362 | .resetvalue = 0, | |
18032bec PM |
1363 | .readfn = pmsav5_data_ap_read, .writefn = pmsav5_data_ap_write, }, |
1364 | { .name = "INSN_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 1, | |
d4e6df63 | 1365 | .access = PL1_RW, .type = ARM_CP_NO_MIGRATE, |
7e09797c PM |
1366 | .fieldoffset = offsetof(CPUARMState, cp15.pmsav5_insn_ap), |
1367 | .resetvalue = 0, | |
18032bec PM |
1368 | .readfn = pmsav5_insn_ap_read, .writefn = pmsav5_insn_ap_write, }, |
1369 | { .name = "DATA_EXT_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 2, | |
1370 | .access = PL1_RW, | |
7e09797c PM |
1371 | .fieldoffset = offsetof(CPUARMState, cp15.pmsav5_data_ap), |
1372 | .resetvalue = 0, }, | |
18032bec PM |
1373 | { .name = "INSN_EXT_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 3, |
1374 | .access = PL1_RW, | |
7e09797c PM |
1375 | .fieldoffset = offsetof(CPUARMState, cp15.pmsav5_insn_ap), |
1376 | .resetvalue = 0, }, | |
ecce5c3c PM |
1377 | { .name = "DCACHE_CFG", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 0, |
1378 | .access = PL1_RW, | |
1379 | .fieldoffset = offsetof(CPUARMState, cp15.c2_data), .resetvalue = 0, }, | |
1380 | { .name = "ICACHE_CFG", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 1, | |
1381 | .access = PL1_RW, | |
1382 | .fieldoffset = offsetof(CPUARMState, cp15.c2_insn), .resetvalue = 0, }, | |
06d76f31 | 1383 | /* Protection region base and size registers */ |
e508a92b PM |
1384 | { .name = "946_PRBS0", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, |
1385 | .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0, | |
1386 | .fieldoffset = offsetof(CPUARMState, cp15.c6_region[0]) }, | |
1387 | { .name = "946_PRBS1", .cp = 15, .crn = 6, .crm = 1, .opc1 = 0, | |
1388 | .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0, | |
1389 | .fieldoffset = offsetof(CPUARMState, cp15.c6_region[1]) }, | |
1390 | { .name = "946_PRBS2", .cp = 15, .crn = 6, .crm = 2, .opc1 = 0, | |
1391 | .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0, | |
1392 | .fieldoffset = offsetof(CPUARMState, cp15.c6_region[2]) }, | |
1393 | { .name = "946_PRBS3", .cp = 15, .crn = 6, .crm = 3, .opc1 = 0, | |
1394 | .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0, | |
1395 | .fieldoffset = offsetof(CPUARMState, cp15.c6_region[3]) }, | |
1396 | { .name = "946_PRBS4", .cp = 15, .crn = 6, .crm = 4, .opc1 = 0, | |
1397 | .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0, | |
1398 | .fieldoffset = offsetof(CPUARMState, cp15.c6_region[4]) }, | |
1399 | { .name = "946_PRBS5", .cp = 15, .crn = 6, .crm = 5, .opc1 = 0, | |
1400 | .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0, | |
1401 | .fieldoffset = offsetof(CPUARMState, cp15.c6_region[5]) }, | |
1402 | { .name = "946_PRBS6", .cp = 15, .crn = 6, .crm = 6, .opc1 = 0, | |
1403 | .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0, | |
1404 | .fieldoffset = offsetof(CPUARMState, cp15.c6_region[6]) }, | |
1405 | { .name = "946_PRBS7", .cp = 15, .crn = 6, .crm = 7, .opc1 = 0, | |
1406 | .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0, | |
1407 | .fieldoffset = offsetof(CPUARMState, cp15.c6_region[7]) }, | |
18032bec PM |
1408 | REGINFO_SENTINEL |
1409 | }; | |
1410 | ||
c4241c7d PM |
1411 | static void vmsa_ttbcr_raw_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1412 | uint64_t value) | |
ecce5c3c | 1413 | { |
2ebcebe2 PM |
1414 | int maskshift = extract32(value, 0, 3); |
1415 | ||
e389be16 FA |
1416 | if (!arm_feature(env, ARM_FEATURE_V8)) { |
1417 | if (arm_feature(env, ARM_FEATURE_LPAE) && (value & TTBCR_EAE)) { | |
1418 | /* Pre ARMv8 bits [21:19], [15:14] and [6:3] are UNK/SBZP when | |
1419 | * using Long-desciptor translation table format */ | |
1420 | value &= ~((7 << 19) | (3 << 14) | (0xf << 3)); | |
1421 | } else if (arm_feature(env, ARM_FEATURE_EL3)) { | |
1422 | /* In an implementation that includes the Security Extensions | |
1423 | * TTBCR has additional fields PD0 [4] and PD1 [5] for | |
1424 | * Short-descriptor translation table format. | |
1425 | */ | |
1426 | value &= TTBCR_PD1 | TTBCR_PD0 | TTBCR_N; | |
1427 | } else { | |
1428 | value &= TTBCR_N; | |
1429 | } | |
e42c4db3 | 1430 | } |
e389be16 | 1431 | |
e42c4db3 PM |
1432 | /* Note that we always calculate c2_mask and c2_base_mask, but |
1433 | * they are only used for short-descriptor tables (ie if EAE is 0); | |
1434 | * for long-descriptor tables the TTBCR fields are used differently | |
1435 | * and the c2_mask and c2_base_mask values are meaningless. | |
1436 | */ | |
8d5c773e | 1437 | raw_write(env, ri, value); |
2ebcebe2 PM |
1438 | env->cp15.c2_mask = ~(((uint32_t)0xffffffffu) >> maskshift); |
1439 | env->cp15.c2_base_mask = ~((uint32_t)0x3fffu >> maskshift); | |
ecce5c3c PM |
1440 | } |
1441 | ||
c4241c7d PM |
1442 | static void vmsa_ttbcr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1443 | uint64_t value) | |
d4e6df63 | 1444 | { |
00c8cb0a AF |
1445 | ARMCPU *cpu = arm_env_get_cpu(env); |
1446 | ||
d4e6df63 PM |
1447 | if (arm_feature(env, ARM_FEATURE_LPAE)) { |
1448 | /* With LPAE the TTBCR could result in a change of ASID | |
1449 | * via the TTBCR.A1 bit, so do a TLB flush. | |
1450 | */ | |
00c8cb0a | 1451 | tlb_flush(CPU(cpu), 1); |
d4e6df63 | 1452 | } |
c4241c7d | 1453 | vmsa_ttbcr_raw_write(env, ri, value); |
d4e6df63 PM |
1454 | } |
1455 | ||
ecce5c3c PM |
1456 | static void vmsa_ttbcr_reset(CPUARMState *env, const ARMCPRegInfo *ri) |
1457 | { | |
1458 | env->cp15.c2_base_mask = 0xffffc000u; | |
8d5c773e | 1459 | raw_write(env, ri, 0); |
ecce5c3c PM |
1460 | env->cp15.c2_mask = 0; |
1461 | } | |
1462 | ||
cb2e37df PM |
1463 | static void vmsa_tcr_el1_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1464 | uint64_t value) | |
1465 | { | |
00c8cb0a AF |
1466 | ARMCPU *cpu = arm_env_get_cpu(env); |
1467 | ||
cb2e37df | 1468 | /* For AArch64 the A1 bit could result in a change of ASID, so TLB flush. */ |
00c8cb0a | 1469 | tlb_flush(CPU(cpu), 1); |
8d5c773e | 1470 | raw_write(env, ri, value); |
cb2e37df PM |
1471 | } |
1472 | ||
327ed10f PM |
1473 | static void vmsa_ttbr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1474 | uint64_t value) | |
1475 | { | |
1476 | /* 64 bit accesses to the TTBRs can change the ASID and so we | |
1477 | * must flush the TLB. | |
1478 | */ | |
1479 | if (cpreg_field_is_64bit(ri)) { | |
00c8cb0a AF |
1480 | ARMCPU *cpu = arm_env_get_cpu(env); |
1481 | ||
1482 | tlb_flush(CPU(cpu), 1); | |
327ed10f PM |
1483 | } |
1484 | raw_write(env, ri, value); | |
1485 | } | |
1486 | ||
18032bec PM |
1487 | static const ARMCPRegInfo vmsa_cp_reginfo[] = { |
1488 | { .name = "DFSR", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 0, | |
6cd8a264 | 1489 | .access = PL1_RW, .type = ARM_CP_NO_MIGRATE, |
d81c519c | 1490 | .fieldoffset = offsetoflow32(CPUARMState, cp15.esr_el[1]), |
6cd8a264 | 1491 | .resetfn = arm_cp_reset_ignore, }, |
18032bec PM |
1492 | { .name = "IFSR", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 1, |
1493 | .access = PL1_RW, | |
6cd8a264 RH |
1494 | .fieldoffset = offsetof(CPUARMState, cp15.ifsr_el2), .resetvalue = 0, }, |
1495 | { .name = "ESR_EL1", .state = ARM_CP_STATE_AA64, | |
1496 | .opc0 = 3, .crn = 5, .crm = 2, .opc1 = 0, .opc2 = 0, | |
1497 | .access = PL1_RW, | |
d81c519c | 1498 | .fieldoffset = offsetof(CPUARMState, cp15.esr_el[1]), .resetvalue = 0, }, |
327ed10f PM |
1499 | { .name = "TTBR0_EL1", .state = ARM_CP_STATE_BOTH, |
1500 | .opc0 = 3, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 0, | |
1501 | .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.ttbr0_el1), | |
1502 | .writefn = vmsa_ttbr_write, .resetvalue = 0 }, | |
1503 | { .name = "TTBR1_EL1", .state = ARM_CP_STATE_BOTH, | |
1504 | .opc0 = 3, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 1, | |
1505 | .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.ttbr1_el1), | |
1506 | .writefn = vmsa_ttbr_write, .resetvalue = 0 }, | |
cb2e37df PM |
1507 | { .name = "TCR_EL1", .state = ARM_CP_STATE_AA64, |
1508 | .opc0 = 3, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 2, | |
1509 | .access = PL1_RW, .writefn = vmsa_tcr_el1_write, | |
1510 | .resetfn = vmsa_ttbcr_reset, .raw_writefn = raw_write, | |
ecce5c3c | 1511 | .fieldoffset = offsetof(CPUARMState, cp15.c2_control) }, |
cb2e37df PM |
1512 | { .name = "TTBCR", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 2, |
1513 | .access = PL1_RW, .type = ARM_CP_NO_MIGRATE, .writefn = vmsa_ttbcr_write, | |
1514 | .resetfn = arm_cp_reset_ignore, .raw_writefn = vmsa_ttbcr_raw_write, | |
1515 | .fieldoffset = offsetoflow32(CPUARMState, cp15.c2_control) }, | |
6cd8a264 RH |
1516 | /* 64-bit FAR; this entry also gives us the AArch32 DFAR */ |
1517 | { .name = "FAR_EL1", .state = ARM_CP_STATE_BOTH, | |
1518 | .opc0 = 3, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 0, | |
1519 | .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.far_el1), | |
06d76f31 | 1520 | .resetvalue = 0, }, |
18032bec PM |
1521 | REGINFO_SENTINEL |
1522 | }; | |
1523 | ||
c4241c7d PM |
1524 | static void omap_ticonfig_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1525 | uint64_t value) | |
1047b9d7 PM |
1526 | { |
1527 | env->cp15.c15_ticonfig = value & 0xe7; | |
1528 | /* The OS_TYPE bit in this register changes the reported CPUID! */ | |
1529 | env->cp15.c0_cpuid = (value & (1 << 5)) ? | |
1530 | ARM_CPUID_TI915T : ARM_CPUID_TI925T; | |
1047b9d7 PM |
1531 | } |
1532 | ||
c4241c7d PM |
1533 | static void omap_threadid_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1534 | uint64_t value) | |
1047b9d7 PM |
1535 | { |
1536 | env->cp15.c15_threadid = value & 0xffff; | |
1047b9d7 PM |
1537 | } |
1538 | ||
c4241c7d PM |
1539 | static void omap_wfi_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1540 | uint64_t value) | |
1047b9d7 PM |
1541 | { |
1542 | /* Wait-for-interrupt (deprecated) */ | |
c3affe56 | 1543 | cpu_interrupt(CPU(arm_env_get_cpu(env)), CPU_INTERRUPT_HALT); |
1047b9d7 PM |
1544 | } |
1545 | ||
c4241c7d PM |
1546 | static void omap_cachemaint_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1547 | uint64_t value) | |
c4804214 PM |
1548 | { |
1549 | /* On OMAP there are registers indicating the max/min index of dcache lines | |
1550 | * containing a dirty line; cache flush operations have to reset these. | |
1551 | */ | |
1552 | env->cp15.c15_i_max = 0x000; | |
1553 | env->cp15.c15_i_min = 0xff0; | |
c4804214 PM |
1554 | } |
1555 | ||
18032bec PM |
1556 | static const ARMCPRegInfo omap_cp_reginfo[] = { |
1557 | { .name = "DFSR", .cp = 15, .crn = 5, .crm = CP_ANY, | |
1558 | .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_OVERRIDE, | |
d81c519c | 1559 | .fieldoffset = offsetoflow32(CPUARMState, cp15.esr_el[1]), |
6cd8a264 | 1560 | .resetvalue = 0, }, |
1047b9d7 PM |
1561 | { .name = "", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0, |
1562 | .access = PL1_RW, .type = ARM_CP_NOP }, | |
1563 | { .name = "TICONFIG", .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0, | |
1564 | .access = PL1_RW, | |
1565 | .fieldoffset = offsetof(CPUARMState, cp15.c15_ticonfig), .resetvalue = 0, | |
1566 | .writefn = omap_ticonfig_write }, | |
1567 | { .name = "IMAX", .cp = 15, .crn = 15, .crm = 2, .opc1 = 0, .opc2 = 0, | |
1568 | .access = PL1_RW, | |
1569 | .fieldoffset = offsetof(CPUARMState, cp15.c15_i_max), .resetvalue = 0, }, | |
1570 | { .name = "IMIN", .cp = 15, .crn = 15, .crm = 3, .opc1 = 0, .opc2 = 0, | |
1571 | .access = PL1_RW, .resetvalue = 0xff0, | |
1572 | .fieldoffset = offsetof(CPUARMState, cp15.c15_i_min) }, | |
1573 | { .name = "THREADID", .cp = 15, .crn = 15, .crm = 4, .opc1 = 0, .opc2 = 0, | |
1574 | .access = PL1_RW, | |
1575 | .fieldoffset = offsetof(CPUARMState, cp15.c15_threadid), .resetvalue = 0, | |
1576 | .writefn = omap_threadid_write }, | |
1577 | { .name = "TI925T_STATUS", .cp = 15, .crn = 15, | |
1578 | .crm = 8, .opc1 = 0, .opc2 = 0, .access = PL1_RW, | |
d4e6df63 | 1579 | .type = ARM_CP_NO_MIGRATE, |
1047b9d7 PM |
1580 | .readfn = arm_cp_read_zero, .writefn = omap_wfi_write, }, |
1581 | /* TODO: Peripheral port remap register: | |
1582 | * On OMAP2 mcr p15, 0, rn, c15, c2, 4 sets up the interrupt controller | |
1583 | * base address at $rn & ~0xfff and map size of 0x200 << ($rn & 0xfff), | |
1584 | * when MMU is off. | |
1585 | */ | |
c4804214 | 1586 | { .name = "OMAP_CACHEMAINT", .cp = 15, .crn = 7, .crm = CP_ANY, |
d4e6df63 PM |
1587 | .opc1 = 0, .opc2 = CP_ANY, .access = PL1_W, |
1588 | .type = ARM_CP_OVERRIDE | ARM_CP_NO_MIGRATE, | |
c4804214 | 1589 | .writefn = omap_cachemaint_write }, |
34f90529 PM |
1590 | { .name = "C9", .cp = 15, .crn = 9, |
1591 | .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, | |
1592 | .type = ARM_CP_CONST | ARM_CP_OVERRIDE, .resetvalue = 0 }, | |
1047b9d7 PM |
1593 | REGINFO_SENTINEL |
1594 | }; | |
1595 | ||
c4241c7d PM |
1596 | static void xscale_cpar_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1597 | uint64_t value) | |
1047b9d7 PM |
1598 | { |
1599 | value &= 0x3fff; | |
1600 | if (env->cp15.c15_cpar != value) { | |
1601 | /* Changes cp0 to cp13 behavior, so needs a TB flush. */ | |
1602 | tb_flush(env); | |
1603 | env->cp15.c15_cpar = value; | |
1604 | } | |
1047b9d7 PM |
1605 | } |
1606 | ||
1607 | static const ARMCPRegInfo xscale_cp_reginfo[] = { | |
1608 | { .name = "XSCALE_CPAR", | |
1609 | .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0, .access = PL1_RW, | |
1610 | .fieldoffset = offsetof(CPUARMState, cp15.c15_cpar), .resetvalue = 0, | |
1611 | .writefn = xscale_cpar_write, }, | |
2771db27 PM |
1612 | { .name = "XSCALE_AUXCR", |
1613 | .cp = 15, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 1, .access = PL1_RW, | |
1614 | .fieldoffset = offsetof(CPUARMState, cp15.c1_xscaleauxcr), | |
1615 | .resetvalue = 0, }, | |
3b771579 PM |
1616 | /* XScale specific cache-lockdown: since we have no cache we NOP these |
1617 | * and hope the guest does not really rely on cache behaviour. | |
1618 | */ | |
1619 | { .name = "XSCALE_LOCK_ICACHE_LINE", | |
1620 | .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 0, | |
1621 | .access = PL1_W, .type = ARM_CP_NOP }, | |
1622 | { .name = "XSCALE_UNLOCK_ICACHE", | |
1623 | .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 1, | |
1624 | .access = PL1_W, .type = ARM_CP_NOP }, | |
1625 | { .name = "XSCALE_DCACHE_LOCK", | |
1626 | .cp = 15, .opc1 = 0, .crn = 9, .crm = 2, .opc2 = 0, | |
1627 | .access = PL1_RW, .type = ARM_CP_NOP }, | |
1628 | { .name = "XSCALE_UNLOCK_DCACHE", | |
1629 | .cp = 15, .opc1 = 0, .crn = 9, .crm = 2, .opc2 = 1, | |
1630 | .access = PL1_W, .type = ARM_CP_NOP }, | |
1047b9d7 PM |
1631 | REGINFO_SENTINEL |
1632 | }; | |
1633 | ||
1634 | static const ARMCPRegInfo dummy_c15_cp_reginfo[] = { | |
1635 | /* RAZ/WI the whole crn=15 space, when we don't have a more specific | |
1636 | * implementation of this implementation-defined space. | |
1637 | * Ideally this should eventually disappear in favour of actually | |
1638 | * implementing the correct behaviour for all cores. | |
1639 | */ | |
1640 | { .name = "C15_IMPDEF", .cp = 15, .crn = 15, | |
1641 | .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY, | |
3671cd87 PC |
1642 | .access = PL1_RW, |
1643 | .type = ARM_CP_CONST | ARM_CP_NO_MIGRATE | ARM_CP_OVERRIDE, | |
d4e6df63 | 1644 | .resetvalue = 0 }, |
18032bec PM |
1645 | REGINFO_SENTINEL |
1646 | }; | |
1647 | ||
c4804214 PM |
1648 | static const ARMCPRegInfo cache_dirty_status_cp_reginfo[] = { |
1649 | /* Cache status: RAZ because we have no cache so it's always clean */ | |
1650 | { .name = "CDSR", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 6, | |
d4e6df63 PM |
1651 | .access = PL1_R, .type = ARM_CP_CONST | ARM_CP_NO_MIGRATE, |
1652 | .resetvalue = 0 }, | |
c4804214 PM |
1653 | REGINFO_SENTINEL |
1654 | }; | |
1655 | ||
1656 | static const ARMCPRegInfo cache_block_ops_cp_reginfo[] = { | |
1657 | /* We never have a a block transfer operation in progress */ | |
1658 | { .name = "BXSR", .cp = 15, .crn = 7, .crm = 12, .opc1 = 0, .opc2 = 4, | |
d4e6df63 PM |
1659 | .access = PL0_R, .type = ARM_CP_CONST | ARM_CP_NO_MIGRATE, |
1660 | .resetvalue = 0 }, | |
30b05bba PM |
1661 | /* The cache ops themselves: these all NOP for QEMU */ |
1662 | { .name = "IICR", .cp = 15, .crm = 5, .opc1 = 0, | |
1663 | .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT }, | |
1664 | { .name = "IDCR", .cp = 15, .crm = 6, .opc1 = 0, | |
1665 | .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT }, | |
1666 | { .name = "CDCR", .cp = 15, .crm = 12, .opc1 = 0, | |
1667 | .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT }, | |
1668 | { .name = "PIR", .cp = 15, .crm = 12, .opc1 = 1, | |
1669 | .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT }, | |
1670 | { .name = "PDR", .cp = 15, .crm = 12, .opc1 = 2, | |
1671 | .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT }, | |
1672 | { .name = "CIDCR", .cp = 15, .crm = 14, .opc1 = 0, | |
1673 | .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT }, | |
c4804214 PM |
1674 | REGINFO_SENTINEL |
1675 | }; | |
1676 | ||
1677 | static const ARMCPRegInfo cache_test_clean_cp_reginfo[] = { | |
1678 | /* The cache test-and-clean instructions always return (1 << 30) | |
1679 | * to indicate that there are no dirty cache lines. | |
1680 | */ | |
1681 | { .name = "TC_DCACHE", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 3, | |
d4e6df63 PM |
1682 | .access = PL0_R, .type = ARM_CP_CONST | ARM_CP_NO_MIGRATE, |
1683 | .resetvalue = (1 << 30) }, | |
c4804214 | 1684 | { .name = "TCI_DCACHE", .cp = 15, .crn = 7, .crm = 14, .opc1 = 0, .opc2 = 3, |
d4e6df63 PM |
1685 | .access = PL0_R, .type = ARM_CP_CONST | ARM_CP_NO_MIGRATE, |
1686 | .resetvalue = (1 << 30) }, | |
c4804214 PM |
1687 | REGINFO_SENTINEL |
1688 | }; | |
1689 | ||
34f90529 PM |
1690 | static const ARMCPRegInfo strongarm_cp_reginfo[] = { |
1691 | /* Ignore ReadBuffer accesses */ | |
1692 | { .name = "C9_READBUFFER", .cp = 15, .crn = 9, | |
1693 | .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY, | |
d4e6df63 PM |
1694 | .access = PL1_RW, .resetvalue = 0, |
1695 | .type = ARM_CP_CONST | ARM_CP_OVERRIDE | ARM_CP_NO_MIGRATE }, | |
34f90529 PM |
1696 | REGINFO_SENTINEL |
1697 | }; | |
1698 | ||
c4241c7d | 1699 | static uint64_t mpidr_read(CPUARMState *env, const ARMCPRegInfo *ri) |
81bdde9d | 1700 | { |
55e5c285 AF |
1701 | CPUState *cs = CPU(arm_env_get_cpu(env)); |
1702 | uint32_t mpidr = cs->cpu_index; | |
4b7fff2f PM |
1703 | /* We don't support setting cluster ID ([8..11]) (known as Aff1 |
1704 | * in later ARM ARM versions), or any of the higher affinity level fields, | |
81bdde9d PM |
1705 | * so these bits always RAZ. |
1706 | */ | |
1707 | if (arm_feature(env, ARM_FEATURE_V7MP)) { | |
78dbbbe4 | 1708 | mpidr |= (1U << 31); |
81bdde9d PM |
1709 | /* Cores which are uniprocessor (non-coherent) |
1710 | * but still implement the MP extensions set | |
1711 | * bit 30. (For instance, A9UP.) However we do | |
1712 | * not currently model any of those cores. | |
1713 | */ | |
1714 | } | |
c4241c7d | 1715 | return mpidr; |
81bdde9d PM |
1716 | } |
1717 | ||
1718 | static const ARMCPRegInfo mpidr_cp_reginfo[] = { | |
4b7fff2f PM |
1719 | { .name = "MPIDR", .state = ARM_CP_STATE_BOTH, |
1720 | .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 5, | |
d4e6df63 | 1721 | .access = PL1_R, .readfn = mpidr_read, .type = ARM_CP_NO_MIGRATE }, |
81bdde9d PM |
1722 | REGINFO_SENTINEL |
1723 | }; | |
1724 | ||
7ac681cf | 1725 | static const ARMCPRegInfo lpae_cp_reginfo[] = { |
b90372ad | 1726 | /* NOP AMAIR0/1: the override is because these clash with the rather |
7ac681cf PM |
1727 | * broadly specified TLB_LOCKDOWN entry in the generic cp_reginfo. |
1728 | */ | |
b0fe2427 PM |
1729 | { .name = "AMAIR0", .state = ARM_CP_STATE_BOTH, |
1730 | .opc0 = 3, .crn = 10, .crm = 3, .opc1 = 0, .opc2 = 0, | |
7ac681cf PM |
1731 | .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_OVERRIDE, |
1732 | .resetvalue = 0 }, | |
b0fe2427 | 1733 | /* AMAIR1 is mapped to AMAIR_EL1[63:32] */ |
7ac681cf PM |
1734 | { .name = "AMAIR1", .cp = 15, .crn = 10, .crm = 3, .opc1 = 0, .opc2 = 1, |
1735 | .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_OVERRIDE, | |
1736 | .resetvalue = 0 }, | |
f9fc619a PM |
1737 | /* 64 bit access versions of the (dummy) debug registers */ |
1738 | { .name = "DBGDRAR", .cp = 14, .crm = 1, .opc1 = 0, | |
1739 | .access = PL0_R, .type = ARM_CP_CONST|ARM_CP_64BIT, .resetvalue = 0 }, | |
1740 | { .name = "DBGDSAR", .cp = 14, .crm = 2, .opc1 = 0, | |
1741 | .access = PL0_R, .type = ARM_CP_CONST|ARM_CP_64BIT, .resetvalue = 0 }, | |
891a2fe7 PM |
1742 | { .name = "PAR", .cp = 15, .crm = 7, .opc1 = 0, |
1743 | .access = PL1_RW, .type = ARM_CP_64BIT, | |
19525524 | 1744 | .fieldoffset = offsetof(CPUARMState, cp15.par_el1), .resetvalue = 0 }, |
891a2fe7 | 1745 | { .name = "TTBR0", .cp = 15, .crm = 2, .opc1 = 0, |
327ed10f PM |
1746 | .access = PL1_RW, .type = ARM_CP_64BIT | ARM_CP_NO_MIGRATE, |
1747 | .fieldoffset = offsetof(CPUARMState, cp15.ttbr0_el1), | |
1748 | .writefn = vmsa_ttbr_write, .resetfn = arm_cp_reset_ignore }, | |
891a2fe7 | 1749 | { .name = "TTBR1", .cp = 15, .crm = 2, .opc1 = 1, |
327ed10f PM |
1750 | .access = PL1_RW, .type = ARM_CP_64BIT | ARM_CP_NO_MIGRATE, |
1751 | .fieldoffset = offsetof(CPUARMState, cp15.ttbr1_el1), | |
1752 | .writefn = vmsa_ttbr_write, .resetfn = arm_cp_reset_ignore }, | |
7ac681cf PM |
1753 | REGINFO_SENTINEL |
1754 | }; | |
1755 | ||
c4241c7d | 1756 | static uint64_t aa64_fpcr_read(CPUARMState *env, const ARMCPRegInfo *ri) |
b0d2b7d0 | 1757 | { |
c4241c7d | 1758 | return vfp_get_fpcr(env); |
b0d2b7d0 PM |
1759 | } |
1760 | ||
c4241c7d PM |
1761 | static void aa64_fpcr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1762 | uint64_t value) | |
b0d2b7d0 PM |
1763 | { |
1764 | vfp_set_fpcr(env, value); | |
b0d2b7d0 PM |
1765 | } |
1766 | ||
c4241c7d | 1767 | static uint64_t aa64_fpsr_read(CPUARMState *env, const ARMCPRegInfo *ri) |
b0d2b7d0 | 1768 | { |
c4241c7d | 1769 | return vfp_get_fpsr(env); |
b0d2b7d0 PM |
1770 | } |
1771 | ||
c4241c7d PM |
1772 | static void aa64_fpsr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1773 | uint64_t value) | |
b0d2b7d0 PM |
1774 | { |
1775 | vfp_set_fpsr(env, value); | |
b0d2b7d0 PM |
1776 | } |
1777 | ||
c2b820fe PM |
1778 | static CPAccessResult aa64_daif_access(CPUARMState *env, const ARMCPRegInfo *ri) |
1779 | { | |
1780 | if (arm_current_pl(env) == 0 && !(env->cp15.c1_sys & SCTLR_UMA)) { | |
1781 | return CP_ACCESS_TRAP; | |
1782 | } | |
1783 | return CP_ACCESS_OK; | |
1784 | } | |
1785 | ||
1786 | static void aa64_daif_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
1787 | uint64_t value) | |
1788 | { | |
1789 | env->daif = value & PSTATE_DAIF; | |
1790 | } | |
1791 | ||
8af35c37 PM |
1792 | static CPAccessResult aa64_cacheop_access(CPUARMState *env, |
1793 | const ARMCPRegInfo *ri) | |
1794 | { | |
1795 | /* Cache invalidate/clean: NOP, but EL0 must UNDEF unless | |
1796 | * SCTLR_EL1.UCI is set. | |
1797 | */ | |
1798 | if (arm_current_pl(env) == 0 && !(env->cp15.c1_sys & SCTLR_UCI)) { | |
1799 | return CP_ACCESS_TRAP; | |
1800 | } | |
1801 | return CP_ACCESS_OK; | |
1802 | } | |
1803 | ||
168aa23b PM |
1804 | static void tlbi_aa64_va_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1805 | uint64_t value) | |
1806 | { | |
1807 | /* Invalidate by VA (AArch64 version) */ | |
31b030d4 | 1808 | ARMCPU *cpu = arm_env_get_cpu(env); |
168aa23b | 1809 | uint64_t pageaddr = value << 12; |
31b030d4 | 1810 | tlb_flush_page(CPU(cpu), pageaddr); |
168aa23b PM |
1811 | } |
1812 | ||
1813 | static void tlbi_aa64_vaa_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
1814 | uint64_t value) | |
1815 | { | |
1816 | /* Invalidate by VA, all ASIDs (AArch64 version) */ | |
31b030d4 | 1817 | ARMCPU *cpu = arm_env_get_cpu(env); |
168aa23b | 1818 | uint64_t pageaddr = value << 12; |
31b030d4 | 1819 | tlb_flush_page(CPU(cpu), pageaddr); |
168aa23b PM |
1820 | } |
1821 | ||
1822 | static void tlbi_aa64_asid_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
1823 | uint64_t value) | |
1824 | { | |
1825 | /* Invalidate by ASID (AArch64 version) */ | |
00c8cb0a | 1826 | ARMCPU *cpu = arm_env_get_cpu(env); |
168aa23b | 1827 | int asid = extract64(value, 48, 16); |
00c8cb0a | 1828 | tlb_flush(CPU(cpu), asid == 0); |
168aa23b PM |
1829 | } |
1830 | ||
aca3f40b PM |
1831 | static CPAccessResult aa64_zva_access(CPUARMState *env, const ARMCPRegInfo *ri) |
1832 | { | |
1833 | /* We don't implement EL2, so the only control on DC ZVA is the | |
1834 | * bit in the SCTLR which can prohibit access for EL0. | |
1835 | */ | |
1836 | if (arm_current_pl(env) == 0 && !(env->cp15.c1_sys & SCTLR_DZE)) { | |
1837 | return CP_ACCESS_TRAP; | |
1838 | } | |
1839 | return CP_ACCESS_OK; | |
1840 | } | |
1841 | ||
1842 | static uint64_t aa64_dczid_read(CPUARMState *env, const ARMCPRegInfo *ri) | |
1843 | { | |
1844 | ARMCPU *cpu = arm_env_get_cpu(env); | |
1845 | int dzp_bit = 1 << 4; | |
1846 | ||
1847 | /* DZP indicates whether DC ZVA access is allowed */ | |
1848 | if (aa64_zva_access(env, NULL) != CP_ACCESS_OK) { | |
1849 | dzp_bit = 0; | |
1850 | } | |
1851 | return cpu->dcz_blocksize | dzp_bit; | |
1852 | } | |
1853 | ||
f502cfc2 PM |
1854 | static CPAccessResult sp_el0_access(CPUARMState *env, const ARMCPRegInfo *ri) |
1855 | { | |
1856 | if (!env->pstate & PSTATE_SP) { | |
1857 | /* Access to SP_EL0 is undefined if it's being used as | |
1858 | * the stack pointer. | |
1859 | */ | |
1860 | return CP_ACCESS_TRAP_UNCATEGORIZED; | |
1861 | } | |
1862 | return CP_ACCESS_OK; | |
1863 | } | |
1864 | ||
1865 | static uint64_t spsel_read(CPUARMState *env, const ARMCPRegInfo *ri) | |
1866 | { | |
1867 | return env->pstate & PSTATE_SP; | |
1868 | } | |
1869 | ||
1870 | static void spsel_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t val) | |
1871 | { | |
1872 | update_spsel(env, val); | |
1873 | } | |
1874 | ||
b0d2b7d0 PM |
1875 | static const ARMCPRegInfo v8_cp_reginfo[] = { |
1876 | /* Minimal set of EL0-visible registers. This will need to be expanded | |
1877 | * significantly for system emulation of AArch64 CPUs. | |
1878 | */ | |
1879 | { .name = "NZCV", .state = ARM_CP_STATE_AA64, | |
1880 | .opc0 = 3, .opc1 = 3, .opc2 = 0, .crn = 4, .crm = 2, | |
1881 | .access = PL0_RW, .type = ARM_CP_NZCV }, | |
c2b820fe PM |
1882 | { .name = "DAIF", .state = ARM_CP_STATE_AA64, |
1883 | .opc0 = 3, .opc1 = 3, .opc2 = 1, .crn = 4, .crm = 2, | |
1884 | .type = ARM_CP_NO_MIGRATE, | |
1885 | .access = PL0_RW, .accessfn = aa64_daif_access, | |
1886 | .fieldoffset = offsetof(CPUARMState, daif), | |
1887 | .writefn = aa64_daif_write, .resetfn = arm_cp_reset_ignore }, | |
b0d2b7d0 PM |
1888 | { .name = "FPCR", .state = ARM_CP_STATE_AA64, |
1889 | .opc0 = 3, .opc1 = 3, .opc2 = 0, .crn = 4, .crm = 4, | |
1890 | .access = PL0_RW, .readfn = aa64_fpcr_read, .writefn = aa64_fpcr_write }, | |
1891 | { .name = "FPSR", .state = ARM_CP_STATE_AA64, | |
1892 | .opc0 = 3, .opc1 = 3, .opc2 = 1, .crn = 4, .crm = 4, | |
1893 | .access = PL0_RW, .readfn = aa64_fpsr_read, .writefn = aa64_fpsr_write }, | |
b0d2b7d0 PM |
1894 | { .name = "DCZID_EL0", .state = ARM_CP_STATE_AA64, |
1895 | .opc0 = 3, .opc1 = 3, .opc2 = 7, .crn = 0, .crm = 0, | |
aca3f40b PM |
1896 | .access = PL0_R, .type = ARM_CP_NO_MIGRATE, |
1897 | .readfn = aa64_dczid_read }, | |
1898 | { .name = "DC_ZVA", .state = ARM_CP_STATE_AA64, | |
1899 | .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 4, .opc2 = 1, | |
1900 | .access = PL0_W, .type = ARM_CP_DC_ZVA, | |
1901 | #ifndef CONFIG_USER_ONLY | |
1902 | /* Avoid overhead of an access check that always passes in user-mode */ | |
1903 | .accessfn = aa64_zva_access, | |
1904 | #endif | |
1905 | }, | |
0eef9d98 PM |
1906 | { .name = "CURRENTEL", .state = ARM_CP_STATE_AA64, |
1907 | .opc0 = 3, .opc1 = 0, .opc2 = 2, .crn = 4, .crm = 2, | |
1908 | .access = PL1_R, .type = ARM_CP_CURRENTEL }, | |
8af35c37 PM |
1909 | /* Cache ops: all NOPs since we don't emulate caches */ |
1910 | { .name = "IC_IALLUIS", .state = ARM_CP_STATE_AA64, | |
1911 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 1, .opc2 = 0, | |
1912 | .access = PL1_W, .type = ARM_CP_NOP }, | |
1913 | { .name = "IC_IALLU", .state = ARM_CP_STATE_AA64, | |
1914 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 0, | |
1915 | .access = PL1_W, .type = ARM_CP_NOP }, | |
1916 | { .name = "IC_IVAU", .state = ARM_CP_STATE_AA64, | |
1917 | .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 5, .opc2 = 1, | |
1918 | .access = PL0_W, .type = ARM_CP_NOP, | |
1919 | .accessfn = aa64_cacheop_access }, | |
1920 | { .name = "DC_IVAC", .state = ARM_CP_STATE_AA64, | |
1921 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 1, | |
1922 | .access = PL1_W, .type = ARM_CP_NOP }, | |
1923 | { .name = "DC_ISW", .state = ARM_CP_STATE_AA64, | |
1924 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 2, | |
1925 | .access = PL1_W, .type = ARM_CP_NOP }, | |
1926 | { .name = "DC_CVAC", .state = ARM_CP_STATE_AA64, | |
1927 | .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 10, .opc2 = 1, | |
1928 | .access = PL0_W, .type = ARM_CP_NOP, | |
1929 | .accessfn = aa64_cacheop_access }, | |
1930 | { .name = "DC_CSW", .state = ARM_CP_STATE_AA64, | |
1931 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 2, | |
1932 | .access = PL1_W, .type = ARM_CP_NOP }, | |
1933 | { .name = "DC_CVAU", .state = ARM_CP_STATE_AA64, | |
1934 | .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 11, .opc2 = 1, | |
1935 | .access = PL0_W, .type = ARM_CP_NOP, | |
1936 | .accessfn = aa64_cacheop_access }, | |
1937 | { .name = "DC_CIVAC", .state = ARM_CP_STATE_AA64, | |
1938 | .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 14, .opc2 = 1, | |
1939 | .access = PL0_W, .type = ARM_CP_NOP, | |
1940 | .accessfn = aa64_cacheop_access }, | |
1941 | { .name = "DC_CISW", .state = ARM_CP_STATE_AA64, | |
1942 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 2, | |
1943 | .access = PL1_W, .type = ARM_CP_NOP }, | |
168aa23b PM |
1944 | /* TLBI operations */ |
1945 | { .name = "TLBI_VMALLE1IS", .state = ARM_CP_STATE_AA64, | |
6ab9f499 | 1946 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 0, |
168aa23b PM |
1947 | .access = PL1_W, .type = ARM_CP_NO_MIGRATE, |
1948 | .writefn = tlbiall_write }, | |
1949 | { .name = "TLBI_VAE1IS", .state = ARM_CP_STATE_AA64, | |
6ab9f499 | 1950 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 1, |
168aa23b PM |
1951 | .access = PL1_W, .type = ARM_CP_NO_MIGRATE, |
1952 | .writefn = tlbi_aa64_va_write }, | |
1953 | { .name = "TLBI_ASIDE1IS", .state = ARM_CP_STATE_AA64, | |
6ab9f499 | 1954 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 2, |
168aa23b PM |
1955 | .access = PL1_W, .type = ARM_CP_NO_MIGRATE, |
1956 | .writefn = tlbi_aa64_asid_write }, | |
1957 | { .name = "TLBI_VAAE1IS", .state = ARM_CP_STATE_AA64, | |
6ab9f499 | 1958 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 3, |
168aa23b PM |
1959 | .access = PL1_W, .type = ARM_CP_NO_MIGRATE, |
1960 | .writefn = tlbi_aa64_vaa_write }, | |
1961 | { .name = "TLBI_VALE1IS", .state = ARM_CP_STATE_AA64, | |
6ab9f499 | 1962 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 5, |
168aa23b PM |
1963 | .access = PL1_W, .type = ARM_CP_NO_MIGRATE, |
1964 | .writefn = tlbi_aa64_va_write }, | |
1965 | { .name = "TLBI_VAALE1IS", .state = ARM_CP_STATE_AA64, | |
6ab9f499 | 1966 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 7, |
168aa23b PM |
1967 | .access = PL1_W, .type = ARM_CP_NO_MIGRATE, |
1968 | .writefn = tlbi_aa64_vaa_write }, | |
1969 | { .name = "TLBI_VMALLE1", .state = ARM_CP_STATE_AA64, | |
6ab9f499 | 1970 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 0, |
168aa23b PM |
1971 | .access = PL1_W, .type = ARM_CP_NO_MIGRATE, |
1972 | .writefn = tlbiall_write }, | |
1973 | { .name = "TLBI_VAE1", .state = ARM_CP_STATE_AA64, | |
6ab9f499 | 1974 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 1, |
168aa23b PM |
1975 | .access = PL1_W, .type = ARM_CP_NO_MIGRATE, |
1976 | .writefn = tlbi_aa64_va_write }, | |
1977 | { .name = "TLBI_ASIDE1", .state = ARM_CP_STATE_AA64, | |
6ab9f499 | 1978 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 2, |
168aa23b PM |
1979 | .access = PL1_W, .type = ARM_CP_NO_MIGRATE, |
1980 | .writefn = tlbi_aa64_asid_write }, | |
1981 | { .name = "TLBI_VAAE1", .state = ARM_CP_STATE_AA64, | |
6ab9f499 | 1982 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 3, |
168aa23b PM |
1983 | .access = PL1_W, .type = ARM_CP_NO_MIGRATE, |
1984 | .writefn = tlbi_aa64_vaa_write }, | |
1985 | { .name = "TLBI_VALE1", .state = ARM_CP_STATE_AA64, | |
6ab9f499 | 1986 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 5, |
168aa23b PM |
1987 | .access = PL1_W, .type = ARM_CP_NO_MIGRATE, |
1988 | .writefn = tlbi_aa64_va_write }, | |
1989 | { .name = "TLBI_VAALE1", .state = ARM_CP_STATE_AA64, | |
6ab9f499 | 1990 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 7, |
168aa23b PM |
1991 | .access = PL1_W, .type = ARM_CP_NO_MIGRATE, |
1992 | .writefn = tlbi_aa64_vaa_write }, | |
19525524 PM |
1993 | #ifndef CONFIG_USER_ONLY |
1994 | /* 64 bit address translation operations */ | |
1995 | { .name = "AT_S1E1R", .state = ARM_CP_STATE_AA64, | |
1996 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 0, | |
1997 | .access = PL1_W, .type = ARM_CP_NO_MIGRATE, .writefn = ats_write }, | |
1998 | { .name = "AT_S1E1W", .state = ARM_CP_STATE_AA64, | |
1999 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 1, | |
2000 | .access = PL1_W, .type = ARM_CP_NO_MIGRATE, .writefn = ats_write }, | |
2001 | { .name = "AT_S1E0R", .state = ARM_CP_STATE_AA64, | |
2002 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 2, | |
2003 | .access = PL1_W, .type = ARM_CP_NO_MIGRATE, .writefn = ats_write }, | |
2004 | { .name = "AT_S1E0W", .state = ARM_CP_STATE_AA64, | |
2005 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 3, | |
2006 | .access = PL1_W, .type = ARM_CP_NO_MIGRATE, .writefn = ats_write }, | |
2007 | #endif | |
9449fdf6 PM |
2008 | /* 32 bit TLB invalidates, Inner Shareable */ |
2009 | { .name = "TLBIALLIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 0, | |
2010 | .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn = tlbiall_write }, | |
2011 | { .name = "TLBIMVAIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 1, | |
2012 | .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn = tlbimva_write }, | |
2013 | { .name = "TLBIASIDIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 2, | |
2014 | .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn = tlbiasid_write }, | |
2015 | { .name = "TLBIMVAAIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 3, | |
2016 | .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn = tlbimvaa_write }, | |
2017 | { .name = "TLBIMVALIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 5, | |
2018 | .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn = tlbimva_write }, | |
2019 | { .name = "TLBIMVAALIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 7, | |
2020 | .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn = tlbimvaa_write }, | |
2021 | /* 32 bit ITLB invalidates */ | |
2022 | { .name = "ITLBIALL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 0, | |
2023 | .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn = tlbiall_write }, | |
2024 | { .name = "ITLBIMVA", .cp = 15, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 1, | |
2025 | .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn = tlbimva_write }, | |
2026 | { .name = "ITLBIASID", .cp = 15, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 2, | |
2027 | .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn = tlbiasid_write }, | |
2028 | /* 32 bit DTLB invalidates */ | |
2029 | { .name = "DTLBIALL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 0, | |
2030 | .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn = tlbiall_write }, | |
2031 | { .name = "DTLBIMVA", .cp = 15, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 1, | |
2032 | .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn = tlbimva_write }, | |
2033 | { .name = "DTLBIASID", .cp = 15, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 2, | |
2034 | .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn = tlbiasid_write }, | |
2035 | /* 32 bit TLB invalidates */ | |
2036 | { .name = "TLBIALL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 0, | |
2037 | .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn = tlbiall_write }, | |
2038 | { .name = "TLBIMVA", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 1, | |
2039 | .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn = tlbimva_write }, | |
2040 | { .name = "TLBIASID", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 2, | |
2041 | .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn = tlbiasid_write }, | |
2042 | { .name = "TLBIMVAA", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 3, | |
2043 | .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn = tlbimvaa_write }, | |
2044 | { .name = "TLBIMVAL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 5, | |
2045 | .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn = tlbimva_write }, | |
2046 | { .name = "TLBIMVAAL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 7, | |
2047 | .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn = tlbimvaa_write }, | |
2048 | /* 32 bit cache operations */ | |
2049 | { .name = "ICIALLUIS", .cp = 15, .opc1 = 0, .crn = 7, .crm = 1, .opc2 = 0, | |
2050 | .type = ARM_CP_NOP, .access = PL1_W }, | |
2051 | { .name = "BPIALLUIS", .cp = 15, .opc1 = 0, .crn = 7, .crm = 1, .opc2 = 6, | |
2052 | .type = ARM_CP_NOP, .access = PL1_W }, | |
2053 | { .name = "ICIALLU", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 0, | |
2054 | .type = ARM_CP_NOP, .access = PL1_W }, | |
2055 | { .name = "ICIMVAU", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 1, | |
2056 | .type = ARM_CP_NOP, .access = PL1_W }, | |
2057 | { .name = "BPIALL", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 6, | |
2058 | .type = ARM_CP_NOP, .access = PL1_W }, | |
2059 | { .name = "BPIMVA", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 7, | |
2060 | .type = ARM_CP_NOP, .access = PL1_W }, | |
2061 | { .name = "DCIMVAC", .cp = 15, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 1, | |
2062 | .type = ARM_CP_NOP, .access = PL1_W }, | |
2063 | { .name = "DCISW", .cp = 15, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 2, | |
2064 | .type = ARM_CP_NOP, .access = PL1_W }, | |
2065 | { .name = "DCCMVAC", .cp = 15, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 1, | |
2066 | .type = ARM_CP_NOP, .access = PL1_W }, | |
2067 | { .name = "DCCSW", .cp = 15, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 2, | |
2068 | .type = ARM_CP_NOP, .access = PL1_W }, | |
2069 | { .name = "DCCMVAU", .cp = 15, .opc1 = 0, .crn = 7, .crm = 11, .opc2 = 1, | |
2070 | .type = ARM_CP_NOP, .access = PL1_W }, | |
2071 | { .name = "DCCIMVAC", .cp = 15, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 1, | |
2072 | .type = ARM_CP_NOP, .access = PL1_W }, | |
2073 | { .name = "DCCISW", .cp = 15, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 2, | |
2074 | .type = ARM_CP_NOP, .access = PL1_W }, | |
2075 | /* MMU Domain access control / MPU write buffer control */ | |
2076 | { .name = "DACR", .cp = 15, | |
2077 | .opc1 = 0, .crn = 3, .crm = 0, .opc2 = 0, | |
2078 | .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c3), | |
2079 | .resetvalue = 0, .writefn = dacr_write, .raw_writefn = raw_write, }, | |
91e24069 PM |
2080 | /* Dummy implementation of monitor debug system control register: |
2081 | * we don't support debug. | |
2082 | */ | |
2083 | { .name = "MDSCR_EL1", .state = ARM_CP_STATE_AA64, | |
2084 | .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 2, | |
2085 | .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
cd5c11b8 PM |
2086 | /* We define a dummy WI OSLAR_EL1, because Linux writes to it. */ |
2087 | { .name = "OSLAR_EL1", .state = ARM_CP_STATE_AA64, | |
2088 | .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 4, | |
2089 | .access = PL1_W, .type = ARM_CP_NOP }, | |
a0618a19 PM |
2090 | { .name = "ELR_EL1", .state = ARM_CP_STATE_AA64, |
2091 | .type = ARM_CP_NO_MIGRATE, | |
2092 | .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 0, .opc2 = 1, | |
6947f059 EI |
2093 | .access = PL1_RW, |
2094 | .fieldoffset = offsetof(CPUARMState, elr_el[1]) }, | |
a65f1de9 PM |
2095 | { .name = "SPSR_EL1", .state = ARM_CP_STATE_AA64, |
2096 | .type = ARM_CP_NO_MIGRATE, | |
2097 | .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 0, .opc2 = 0, | |
2098 | .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, banked_spsr[0]) }, | |
f502cfc2 PM |
2099 | /* We rely on the access checks not allowing the guest to write to the |
2100 | * state field when SPSel indicates that it's being used as the stack | |
2101 | * pointer. | |
2102 | */ | |
2103 | { .name = "SP_EL0", .state = ARM_CP_STATE_AA64, | |
2104 | .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 1, .opc2 = 0, | |
2105 | .access = PL1_RW, .accessfn = sp_el0_access, | |
2106 | .type = ARM_CP_NO_MIGRATE, | |
2107 | .fieldoffset = offsetof(CPUARMState, sp_el[0]) }, | |
2108 | { .name = "SPSel", .state = ARM_CP_STATE_AA64, | |
2109 | .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 2, .opc2 = 0, | |
2110 | .type = ARM_CP_NO_MIGRATE, | |
2111 | .access = PL1_RW, .readfn = spsel_read, .writefn = spsel_write }, | |
b0d2b7d0 PM |
2112 | REGINFO_SENTINEL |
2113 | }; | |
2114 | ||
d42e3c26 EI |
2115 | /* Used to describe the behaviour of EL2 regs when EL2 does not exist. */ |
2116 | static const ARMCPRegInfo v8_el3_no_el2_cp_reginfo[] = { | |
2117 | { .name = "VBAR_EL2", .state = ARM_CP_STATE_AA64, | |
2118 | .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 0, .opc2 = 0, | |
2119 | .access = PL2_RW, | |
2120 | .readfn = arm_cp_read_zero, .writefn = arm_cp_write_ignore }, | |
2121 | REGINFO_SENTINEL | |
2122 | }; | |
2123 | ||
3b685ba7 EI |
2124 | static const ARMCPRegInfo v8_el2_cp_reginfo[] = { |
2125 | { .name = "ELR_EL2", .state = ARM_CP_STATE_AA64, | |
2126 | .type = ARM_CP_NO_MIGRATE, | |
2127 | .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 0, .opc2 = 1, | |
2128 | .access = PL2_RW, | |
2129 | .fieldoffset = offsetof(CPUARMState, elr_el[2]) }, | |
2130 | { .name = "SPSR_EL2", .state = ARM_CP_STATE_AA64, | |
2131 | .type = ARM_CP_NO_MIGRATE, | |
2132 | .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 0, .opc2 = 0, | |
2133 | .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, banked_spsr[6]) }, | |
d42e3c26 EI |
2134 | { .name = "VBAR_EL2", .state = ARM_CP_STATE_AA64, |
2135 | .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 0, .opc2 = 0, | |
2136 | .access = PL2_RW, .writefn = vbar_write, | |
2137 | .fieldoffset = offsetof(CPUARMState, cp15.vbar_el[2]), | |
2138 | .resetvalue = 0 }, | |
3b685ba7 EI |
2139 | REGINFO_SENTINEL |
2140 | }; | |
2141 | ||
81547d66 EI |
2142 | static const ARMCPRegInfo v8_el3_cp_reginfo[] = { |
2143 | { .name = "ELR_EL3", .state = ARM_CP_STATE_AA64, | |
2144 | .type = ARM_CP_NO_MIGRATE, | |
2145 | .opc0 = 3, .opc1 = 6, .crn = 4, .crm = 0, .opc2 = 1, | |
2146 | .access = PL3_RW, | |
2147 | .fieldoffset = offsetof(CPUARMState, elr_el[3]) }, | |
2148 | { .name = "SPSR_EL3", .state = ARM_CP_STATE_AA64, | |
2149 | .type = ARM_CP_NO_MIGRATE, | |
2150 | .opc0 = 3, .opc1 = 6, .crn = 4, .crm = 0, .opc2 = 0, | |
2151 | .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, banked_spsr[7]) }, | |
a1ba125c EI |
2152 | { .name = "VBAR_EL3", .state = ARM_CP_STATE_AA64, |
2153 | .opc0 = 3, .opc1 = 6, .crn = 12, .crm = 0, .opc2 = 0, | |
2154 | .access = PL3_RW, .writefn = vbar_write, | |
2155 | .fieldoffset = offsetof(CPUARMState, cp15.vbar_el[3]), | |
2156 | .resetvalue = 0 }, | |
81547d66 EI |
2157 | REGINFO_SENTINEL |
2158 | }; | |
2159 | ||
c4241c7d PM |
2160 | static void sctlr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
2161 | uint64_t value) | |
2771db27 | 2162 | { |
00c8cb0a AF |
2163 | ARMCPU *cpu = arm_env_get_cpu(env); |
2164 | ||
8d5c773e | 2165 | if (raw_read(env, ri) == value) { |
2f0d8631 PM |
2166 | /* Skip the TLB flush if nothing actually changed; Linux likes |
2167 | * to do a lot of pointless SCTLR writes. | |
2168 | */ | |
2169 | return; | |
2170 | } | |
2171 | ||
8d5c773e | 2172 | raw_write(env, ri, value); |
2771db27 PM |
2173 | /* ??? Lots of these bits are not implemented. */ |
2174 | /* This may enable/disable the MMU, so do a TLB flush. */ | |
00c8cb0a | 2175 | tlb_flush(CPU(cpu), 1); |
2771db27 PM |
2176 | } |
2177 | ||
7da845b0 PM |
2178 | static CPAccessResult ctr_el0_access(CPUARMState *env, const ARMCPRegInfo *ri) |
2179 | { | |
2180 | /* Only accessible in EL0 if SCTLR.UCT is set (and only in AArch64, | |
2181 | * but the AArch32 CTR has its own reginfo struct) | |
2182 | */ | |
2183 | if (arm_current_pl(env) == 0 && !(env->cp15.c1_sys & SCTLR_UCT)) { | |
2184 | return CP_ACCESS_TRAP; | |
2185 | } | |
2186 | return CP_ACCESS_OK; | |
2187 | } | |
2188 | ||
0b45451e PM |
2189 | static void define_aarch64_debug_regs(ARMCPU *cpu) |
2190 | { | |
2191 | /* Define breakpoint and watchpoint registers. These do nothing | |
2192 | * but read as written, for now. | |
2193 | */ | |
2194 | int i; | |
2195 | ||
2196 | for (i = 0; i < 16; i++) { | |
2197 | ARMCPRegInfo dbgregs[] = { | |
2198 | { .name = "DBGBVR", .state = ARM_CP_STATE_AA64, | |
2199 | .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 4, | |
2200 | .access = PL1_RW, | |
2201 | .fieldoffset = offsetof(CPUARMState, cp15.dbgbvr[i]) }, | |
2202 | { .name = "DBGBCR", .state = ARM_CP_STATE_AA64, | |
2203 | .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 5, | |
2204 | .access = PL1_RW, | |
2205 | .fieldoffset = offsetof(CPUARMState, cp15.dbgbcr[i]) }, | |
2206 | { .name = "DBGWVR", .state = ARM_CP_STATE_AA64, | |
2207 | .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 6, | |
2208 | .access = PL1_RW, | |
2209 | .fieldoffset = offsetof(CPUARMState, cp15.dbgwvr[i]) }, | |
2210 | { .name = "DBGWCR", .state = ARM_CP_STATE_AA64, | |
2211 | .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 7, | |
2212 | .access = PL1_RW, | |
2213 | .fieldoffset = offsetof(CPUARMState, cp15.dbgwcr[i]) }, | |
2214 | REGINFO_SENTINEL | |
2215 | }; | |
2216 | define_arm_cp_regs(cpu, dbgregs); | |
2217 | } | |
2218 | } | |
2219 | ||
2ceb98c0 PM |
2220 | void register_cp_regs_for_features(ARMCPU *cpu) |
2221 | { | |
2222 | /* Register all the coprocessor registers based on feature bits */ | |
2223 | CPUARMState *env = &cpu->env; | |
2224 | if (arm_feature(env, ARM_FEATURE_M)) { | |
2225 | /* M profile has no coprocessor registers */ | |
2226 | return; | |
2227 | } | |
2228 | ||
e9aa6c21 | 2229 | define_arm_cp_regs(cpu, cp_reginfo); |
9449fdf6 PM |
2230 | if (!arm_feature(env, ARM_FEATURE_V8)) { |
2231 | /* Must go early as it is full of wildcards that may be | |
2232 | * overridden by later definitions. | |
2233 | */ | |
2234 | define_arm_cp_regs(cpu, not_v8_cp_reginfo); | |
2235 | } | |
2236 | ||
7d57f408 | 2237 | if (arm_feature(env, ARM_FEATURE_V6)) { |
8515a092 PM |
2238 | /* The ID registers all have impdef reset values */ |
2239 | ARMCPRegInfo v6_idregs[] = { | |
0ff644a7 PM |
2240 | { .name = "ID_PFR0", .state = ARM_CP_STATE_BOTH, |
2241 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 0, | |
2242 | .access = PL1_R, .type = ARM_CP_CONST, | |
8515a092 | 2243 | .resetvalue = cpu->id_pfr0 }, |
0ff644a7 PM |
2244 | { .name = "ID_PFR1", .state = ARM_CP_STATE_BOTH, |
2245 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 1, | |
2246 | .access = PL1_R, .type = ARM_CP_CONST, | |
8515a092 | 2247 | .resetvalue = cpu->id_pfr1 }, |
0ff644a7 PM |
2248 | { .name = "ID_DFR0", .state = ARM_CP_STATE_BOTH, |
2249 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 2, | |
2250 | .access = PL1_R, .type = ARM_CP_CONST, | |
8515a092 | 2251 | .resetvalue = cpu->id_dfr0 }, |
0ff644a7 PM |
2252 | { .name = "ID_AFR0", .state = ARM_CP_STATE_BOTH, |
2253 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 3, | |
2254 | .access = PL1_R, .type = ARM_CP_CONST, | |
8515a092 | 2255 | .resetvalue = cpu->id_afr0 }, |
0ff644a7 PM |
2256 | { .name = "ID_MMFR0", .state = ARM_CP_STATE_BOTH, |
2257 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 4, | |
2258 | .access = PL1_R, .type = ARM_CP_CONST, | |
8515a092 | 2259 | .resetvalue = cpu->id_mmfr0 }, |
0ff644a7 PM |
2260 | { .name = "ID_MMFR1", .state = ARM_CP_STATE_BOTH, |
2261 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 5, | |
2262 | .access = PL1_R, .type = ARM_CP_CONST, | |
8515a092 | 2263 | .resetvalue = cpu->id_mmfr1 }, |
0ff644a7 PM |
2264 | { .name = "ID_MMFR2", .state = ARM_CP_STATE_BOTH, |
2265 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 6, | |
2266 | .access = PL1_R, .type = ARM_CP_CONST, | |
8515a092 | 2267 | .resetvalue = cpu->id_mmfr2 }, |
0ff644a7 PM |
2268 | { .name = "ID_MMFR3", .state = ARM_CP_STATE_BOTH, |
2269 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 7, | |
2270 | .access = PL1_R, .type = ARM_CP_CONST, | |
8515a092 | 2271 | .resetvalue = cpu->id_mmfr3 }, |
0ff644a7 PM |
2272 | { .name = "ID_ISAR0", .state = ARM_CP_STATE_BOTH, |
2273 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 0, | |
2274 | .access = PL1_R, .type = ARM_CP_CONST, | |
8515a092 | 2275 | .resetvalue = cpu->id_isar0 }, |
0ff644a7 PM |
2276 | { .name = "ID_ISAR1", .state = ARM_CP_STATE_BOTH, |
2277 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 1, | |
2278 | .access = PL1_R, .type = ARM_CP_CONST, | |
8515a092 | 2279 | .resetvalue = cpu->id_isar1 }, |
0ff644a7 PM |
2280 | { .name = "ID_ISAR2", .state = ARM_CP_STATE_BOTH, |
2281 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 2, | |
2282 | .access = PL1_R, .type = ARM_CP_CONST, | |
8515a092 | 2283 | .resetvalue = cpu->id_isar2 }, |
0ff644a7 PM |
2284 | { .name = "ID_ISAR3", .state = ARM_CP_STATE_BOTH, |
2285 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 3, | |
2286 | .access = PL1_R, .type = ARM_CP_CONST, | |
8515a092 | 2287 | .resetvalue = cpu->id_isar3 }, |
0ff644a7 PM |
2288 | { .name = "ID_ISAR4", .state = ARM_CP_STATE_BOTH, |
2289 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 4, | |
2290 | .access = PL1_R, .type = ARM_CP_CONST, | |
8515a092 | 2291 | .resetvalue = cpu->id_isar4 }, |
0ff644a7 PM |
2292 | { .name = "ID_ISAR5", .state = ARM_CP_STATE_BOTH, |
2293 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 5, | |
2294 | .access = PL1_R, .type = ARM_CP_CONST, | |
8515a092 PM |
2295 | .resetvalue = cpu->id_isar5 }, |
2296 | /* 6..7 are as yet unallocated and must RAZ */ | |
2297 | { .name = "ID_ISAR6", .cp = 15, .crn = 0, .crm = 2, | |
2298 | .opc1 = 0, .opc2 = 6, .access = PL1_R, .type = ARM_CP_CONST, | |
2299 | .resetvalue = 0 }, | |
2300 | { .name = "ID_ISAR7", .cp = 15, .crn = 0, .crm = 2, | |
2301 | .opc1 = 0, .opc2 = 7, .access = PL1_R, .type = ARM_CP_CONST, | |
2302 | .resetvalue = 0 }, | |
2303 | REGINFO_SENTINEL | |
2304 | }; | |
2305 | define_arm_cp_regs(cpu, v6_idregs); | |
7d57f408 PM |
2306 | define_arm_cp_regs(cpu, v6_cp_reginfo); |
2307 | } else { | |
2308 | define_arm_cp_regs(cpu, not_v6_cp_reginfo); | |
2309 | } | |
4d31c596 PM |
2310 | if (arm_feature(env, ARM_FEATURE_V6K)) { |
2311 | define_arm_cp_regs(cpu, v6k_cp_reginfo); | |
2312 | } | |
e9aa6c21 | 2313 | if (arm_feature(env, ARM_FEATURE_V7)) { |
200ac0ef | 2314 | /* v7 performance monitor control register: same implementor |
7c2cb42b AF |
2315 | * field as main ID register, and we implement only the cycle |
2316 | * count register. | |
200ac0ef | 2317 | */ |
7c2cb42b | 2318 | #ifndef CONFIG_USER_ONLY |
200ac0ef PM |
2319 | ARMCPRegInfo pmcr = { |
2320 | .name = "PMCR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 0, | |
2321 | .access = PL0_RW, .resetvalue = cpu->midr & 0xff000000, | |
d6d60581 | 2322 | .type = ARM_CP_IO, |
200ac0ef | 2323 | .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcr), |
fcd25206 PM |
2324 | .accessfn = pmreg_access, .writefn = pmcr_write, |
2325 | .raw_writefn = raw_write, | |
200ac0ef | 2326 | }; |
7c2cb42b AF |
2327 | define_one_arm_cp_reg(cpu, &pmcr); |
2328 | #endif | |
776d4e5c | 2329 | ARMCPRegInfo clidr = { |
7da845b0 PM |
2330 | .name = "CLIDR", .state = ARM_CP_STATE_BOTH, |
2331 | .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 1, | |
776d4e5c PM |
2332 | .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = cpu->clidr |
2333 | }; | |
776d4e5c | 2334 | define_one_arm_cp_reg(cpu, &clidr); |
e9aa6c21 | 2335 | define_arm_cp_regs(cpu, v7_cp_reginfo); |
7d57f408 PM |
2336 | } else { |
2337 | define_arm_cp_regs(cpu, not_v7_cp_reginfo); | |
e9aa6c21 | 2338 | } |
b0d2b7d0 | 2339 | if (arm_feature(env, ARM_FEATURE_V8)) { |
e60cef86 PM |
2340 | /* AArch64 ID registers, which all have impdef reset values */ |
2341 | ARMCPRegInfo v8_idregs[] = { | |
2342 | { .name = "ID_AA64PFR0_EL1", .state = ARM_CP_STATE_AA64, | |
2343 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 0, | |
2344 | .access = PL1_R, .type = ARM_CP_CONST, | |
2345 | .resetvalue = cpu->id_aa64pfr0 }, | |
2346 | { .name = "ID_AA64PFR1_EL1", .state = ARM_CP_STATE_AA64, | |
2347 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 1, | |
2348 | .access = PL1_R, .type = ARM_CP_CONST, | |
2349 | .resetvalue = cpu->id_aa64pfr1}, | |
2350 | { .name = "ID_AA64DFR0_EL1", .state = ARM_CP_STATE_AA64, | |
2351 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 0, | |
2352 | .access = PL1_R, .type = ARM_CP_CONST, | |
9225d739 PM |
2353 | /* We mask out the PMUVer field, beacuse we don't currently |
2354 | * implement the PMU. Not advertising it prevents the guest | |
2355 | * from trying to use it and getting UNDEFs on registers we | |
2356 | * don't implement. | |
2357 | */ | |
2358 | .resetvalue = cpu->id_aa64dfr0 & ~0xf00 }, | |
e60cef86 PM |
2359 | { .name = "ID_AA64DFR1_EL1", .state = ARM_CP_STATE_AA64, |
2360 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 1, | |
2361 | .access = PL1_R, .type = ARM_CP_CONST, | |
2362 | .resetvalue = cpu->id_aa64dfr1 }, | |
2363 | { .name = "ID_AA64AFR0_EL1", .state = ARM_CP_STATE_AA64, | |
2364 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 4, | |
2365 | .access = PL1_R, .type = ARM_CP_CONST, | |
2366 | .resetvalue = cpu->id_aa64afr0 }, | |
2367 | { .name = "ID_AA64AFR1_EL1", .state = ARM_CP_STATE_AA64, | |
2368 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 5, | |
2369 | .access = PL1_R, .type = ARM_CP_CONST, | |
2370 | .resetvalue = cpu->id_aa64afr1 }, | |
2371 | { .name = "ID_AA64ISAR0_EL1", .state = ARM_CP_STATE_AA64, | |
2372 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 0, | |
2373 | .access = PL1_R, .type = ARM_CP_CONST, | |
2374 | .resetvalue = cpu->id_aa64isar0 }, | |
2375 | { .name = "ID_AA64ISAR1_EL1", .state = ARM_CP_STATE_AA64, | |
2376 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 1, | |
2377 | .access = PL1_R, .type = ARM_CP_CONST, | |
2378 | .resetvalue = cpu->id_aa64isar1 }, | |
2379 | { .name = "ID_AA64MMFR0_EL1", .state = ARM_CP_STATE_AA64, | |
2380 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 0, | |
2381 | .access = PL1_R, .type = ARM_CP_CONST, | |
2382 | .resetvalue = cpu->id_aa64mmfr0 }, | |
2383 | { .name = "ID_AA64MMFR1_EL1", .state = ARM_CP_STATE_AA64, | |
2384 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 1, | |
2385 | .access = PL1_R, .type = ARM_CP_CONST, | |
2386 | .resetvalue = cpu->id_aa64mmfr1 }, | |
a50c0f51 PM |
2387 | { .name = "MVFR0_EL1", .state = ARM_CP_STATE_AA64, |
2388 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 0, | |
2389 | .access = PL1_R, .type = ARM_CP_CONST, | |
2390 | .resetvalue = cpu->mvfr0 }, | |
2391 | { .name = "MVFR1_EL1", .state = ARM_CP_STATE_AA64, | |
2392 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 1, | |
2393 | .access = PL1_R, .type = ARM_CP_CONST, | |
2394 | .resetvalue = cpu->mvfr1 }, | |
2395 | { .name = "MVFR2_EL1", .state = ARM_CP_STATE_AA64, | |
2396 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 2, | |
2397 | .access = PL1_R, .type = ARM_CP_CONST, | |
2398 | .resetvalue = cpu->mvfr2 }, | |
e60cef86 PM |
2399 | REGINFO_SENTINEL |
2400 | }; | |
3933443e PM |
2401 | ARMCPRegInfo rvbar = { |
2402 | .name = "RVBAR_EL1", .state = ARM_CP_STATE_AA64, | |
2403 | .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 0, .opc2 = 2, | |
2404 | .type = ARM_CP_CONST, .access = PL1_R, .resetvalue = cpu->rvbar | |
2405 | }; | |
2406 | define_one_arm_cp_reg(cpu, &rvbar); | |
e60cef86 | 2407 | define_arm_cp_regs(cpu, v8_idregs); |
b0d2b7d0 | 2408 | define_arm_cp_regs(cpu, v8_cp_reginfo); |
0b45451e | 2409 | define_aarch64_debug_regs(cpu); |
b0d2b7d0 | 2410 | } |
3b685ba7 EI |
2411 | if (arm_feature(env, ARM_FEATURE_EL2)) { |
2412 | define_arm_cp_regs(cpu, v8_el2_cp_reginfo); | |
d42e3c26 EI |
2413 | } else { |
2414 | /* If EL2 is missing but higher ELs are enabled, we need to | |
2415 | * register the no_el2 reginfos. | |
2416 | */ | |
2417 | if (arm_feature(env, ARM_FEATURE_EL3)) { | |
2418 | define_arm_cp_regs(cpu, v8_el3_no_el2_cp_reginfo); | |
2419 | } | |
3b685ba7 | 2420 | } |
81547d66 EI |
2421 | if (arm_feature(env, ARM_FEATURE_EL3)) { |
2422 | define_arm_cp_regs(cpu, v8_el3_cp_reginfo); | |
2423 | } | |
18032bec PM |
2424 | if (arm_feature(env, ARM_FEATURE_MPU)) { |
2425 | /* These are the MPU registers prior to PMSAv6. Any new | |
2426 | * PMSA core later than the ARM946 will require that we | |
2427 | * implement the PMSAv6 or PMSAv7 registers, which are | |
2428 | * completely different. | |
2429 | */ | |
2430 | assert(!arm_feature(env, ARM_FEATURE_V6)); | |
2431 | define_arm_cp_regs(cpu, pmsav5_cp_reginfo); | |
2432 | } else { | |
2433 | define_arm_cp_regs(cpu, vmsa_cp_reginfo); | |
2434 | } | |
c326b979 PM |
2435 | if (arm_feature(env, ARM_FEATURE_THUMB2EE)) { |
2436 | define_arm_cp_regs(cpu, t2ee_cp_reginfo); | |
2437 | } | |
6cc7a3ae PM |
2438 | if (arm_feature(env, ARM_FEATURE_GENERIC_TIMER)) { |
2439 | define_arm_cp_regs(cpu, generic_timer_cp_reginfo); | |
2440 | } | |
4a501606 PM |
2441 | if (arm_feature(env, ARM_FEATURE_VAPA)) { |
2442 | define_arm_cp_regs(cpu, vapa_cp_reginfo); | |
2443 | } | |
c4804214 PM |
2444 | if (arm_feature(env, ARM_FEATURE_CACHE_TEST_CLEAN)) { |
2445 | define_arm_cp_regs(cpu, cache_test_clean_cp_reginfo); | |
2446 | } | |
2447 | if (arm_feature(env, ARM_FEATURE_CACHE_DIRTY_REG)) { | |
2448 | define_arm_cp_regs(cpu, cache_dirty_status_cp_reginfo); | |
2449 | } | |
2450 | if (arm_feature(env, ARM_FEATURE_CACHE_BLOCK_OPS)) { | |
2451 | define_arm_cp_regs(cpu, cache_block_ops_cp_reginfo); | |
2452 | } | |
18032bec PM |
2453 | if (arm_feature(env, ARM_FEATURE_OMAPCP)) { |
2454 | define_arm_cp_regs(cpu, omap_cp_reginfo); | |
2455 | } | |
34f90529 PM |
2456 | if (arm_feature(env, ARM_FEATURE_STRONGARM)) { |
2457 | define_arm_cp_regs(cpu, strongarm_cp_reginfo); | |
2458 | } | |
1047b9d7 PM |
2459 | if (arm_feature(env, ARM_FEATURE_XSCALE)) { |
2460 | define_arm_cp_regs(cpu, xscale_cp_reginfo); | |
2461 | } | |
2462 | if (arm_feature(env, ARM_FEATURE_DUMMY_C15_REGS)) { | |
2463 | define_arm_cp_regs(cpu, dummy_c15_cp_reginfo); | |
2464 | } | |
7ac681cf PM |
2465 | if (arm_feature(env, ARM_FEATURE_LPAE)) { |
2466 | define_arm_cp_regs(cpu, lpae_cp_reginfo); | |
2467 | } | |
7884849c PM |
2468 | /* Slightly awkwardly, the OMAP and StrongARM cores need all of |
2469 | * cp15 crn=0 to be writes-ignored, whereas for other cores they should | |
2470 | * be read-only (ie write causes UNDEF exception). | |
2471 | */ | |
2472 | { | |
00a29f3d PM |
2473 | ARMCPRegInfo id_pre_v8_midr_cp_reginfo[] = { |
2474 | /* Pre-v8 MIDR space. | |
2475 | * Note that the MIDR isn't a simple constant register because | |
7884849c PM |
2476 | * of the TI925 behaviour where writes to another register can |
2477 | * cause the MIDR value to change. | |
97ce8d61 PC |
2478 | * |
2479 | * Unimplemented registers in the c15 0 0 0 space default to | |
2480 | * MIDR. Define MIDR first as this entire space, then CTR, TCMTR | |
2481 | * and friends override accordingly. | |
7884849c PM |
2482 | */ |
2483 | { .name = "MIDR", | |
97ce8d61 | 2484 | .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = CP_ANY, |
7884849c | 2485 | .access = PL1_R, .resetvalue = cpu->midr, |
d4e6df63 | 2486 | .writefn = arm_cp_write_ignore, .raw_writefn = raw_write, |
97ce8d61 PC |
2487 | .fieldoffset = offsetof(CPUARMState, cp15.c0_cpuid), |
2488 | .type = ARM_CP_OVERRIDE }, | |
7884849c PM |
2489 | /* crn = 0 op1 = 0 crm = 3..7 : currently unassigned; we RAZ. */ |
2490 | { .name = "DUMMY", | |
2491 | .cp = 15, .crn = 0, .crm = 3, .opc1 = 0, .opc2 = CP_ANY, | |
2492 | .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
2493 | { .name = "DUMMY", | |
2494 | .cp = 15, .crn = 0, .crm = 4, .opc1 = 0, .opc2 = CP_ANY, | |
2495 | .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
2496 | { .name = "DUMMY", | |
2497 | .cp = 15, .crn = 0, .crm = 5, .opc1 = 0, .opc2 = CP_ANY, | |
2498 | .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
2499 | { .name = "DUMMY", | |
2500 | .cp = 15, .crn = 0, .crm = 6, .opc1 = 0, .opc2 = CP_ANY, | |
2501 | .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
2502 | { .name = "DUMMY", | |
2503 | .cp = 15, .crn = 0, .crm = 7, .opc1 = 0, .opc2 = CP_ANY, | |
2504 | .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
2505 | REGINFO_SENTINEL | |
2506 | }; | |
00a29f3d PM |
2507 | ARMCPRegInfo id_v8_midr_cp_reginfo[] = { |
2508 | /* v8 MIDR -- the wildcard isn't necessary, and nor is the | |
2509 | * variable-MIDR TI925 behaviour. Instead we have a single | |
2510 | * (strictly speaking IMPDEF) alias of the MIDR, REVIDR. | |
2511 | */ | |
2512 | { .name = "MIDR_EL1", .state = ARM_CP_STATE_BOTH, | |
2513 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 0, .opc2 = 0, | |
2514 | .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = cpu->midr }, | |
2515 | { .name = "REVIDR_EL1", .state = ARM_CP_STATE_BOTH, | |
2516 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 0, .opc2 = 6, | |
2517 | .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = cpu->midr }, | |
2518 | REGINFO_SENTINEL | |
2519 | }; | |
2520 | ARMCPRegInfo id_cp_reginfo[] = { | |
2521 | /* These are common to v8 and pre-v8 */ | |
2522 | { .name = "CTR", | |
2523 | .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 1, | |
2524 | .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = cpu->ctr }, | |
2525 | { .name = "CTR_EL0", .state = ARM_CP_STATE_AA64, | |
2526 | .opc0 = 3, .opc1 = 3, .opc2 = 1, .crn = 0, .crm = 0, | |
2527 | .access = PL0_R, .accessfn = ctr_el0_access, | |
2528 | .type = ARM_CP_CONST, .resetvalue = cpu->ctr }, | |
2529 | /* TCMTR and TLBTR exist in v8 but have no 64-bit versions */ | |
2530 | { .name = "TCMTR", | |
2531 | .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 2, | |
2532 | .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
2533 | { .name = "TLBTR", | |
2534 | .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 3, | |
2535 | .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
2536 | REGINFO_SENTINEL | |
2537 | }; | |
7884849c PM |
2538 | ARMCPRegInfo crn0_wi_reginfo = { |
2539 | .name = "CRN0_WI", .cp = 15, .crn = 0, .crm = CP_ANY, | |
2540 | .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_W, | |
2541 | .type = ARM_CP_NOP | ARM_CP_OVERRIDE | |
2542 | }; | |
2543 | if (arm_feature(env, ARM_FEATURE_OMAPCP) || | |
2544 | arm_feature(env, ARM_FEATURE_STRONGARM)) { | |
2545 | ARMCPRegInfo *r; | |
2546 | /* Register the blanket "writes ignored" value first to cover the | |
a703eda1 PC |
2547 | * whole space. Then update the specific ID registers to allow write |
2548 | * access, so that they ignore writes rather than causing them to | |
2549 | * UNDEF. | |
7884849c PM |
2550 | */ |
2551 | define_one_arm_cp_reg(cpu, &crn0_wi_reginfo); | |
00a29f3d PM |
2552 | for (r = id_pre_v8_midr_cp_reginfo; |
2553 | r->type != ARM_CP_SENTINEL; r++) { | |
2554 | r->access = PL1_RW; | |
2555 | } | |
7884849c PM |
2556 | for (r = id_cp_reginfo; r->type != ARM_CP_SENTINEL; r++) { |
2557 | r->access = PL1_RW; | |
7884849c | 2558 | } |
7884849c | 2559 | } |
00a29f3d PM |
2560 | if (arm_feature(env, ARM_FEATURE_V8)) { |
2561 | define_arm_cp_regs(cpu, id_v8_midr_cp_reginfo); | |
2562 | } else { | |
2563 | define_arm_cp_regs(cpu, id_pre_v8_midr_cp_reginfo); | |
2564 | } | |
a703eda1 | 2565 | define_arm_cp_regs(cpu, id_cp_reginfo); |
7884849c PM |
2566 | } |
2567 | ||
97ce8d61 PC |
2568 | if (arm_feature(env, ARM_FEATURE_MPIDR)) { |
2569 | define_arm_cp_regs(cpu, mpidr_cp_reginfo); | |
2570 | } | |
2571 | ||
2771db27 PM |
2572 | if (arm_feature(env, ARM_FEATURE_AUXCR)) { |
2573 | ARMCPRegInfo auxcr = { | |
2eef0bf8 PM |
2574 | .name = "ACTLR_EL1", .state = ARM_CP_STATE_BOTH, |
2575 | .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 1, | |
2771db27 PM |
2576 | .access = PL1_RW, .type = ARM_CP_CONST, |
2577 | .resetvalue = cpu->reset_auxcr | |
2578 | }; | |
2579 | define_one_arm_cp_reg(cpu, &auxcr); | |
2580 | } | |
2581 | ||
d8ba780b | 2582 | if (arm_feature(env, ARM_FEATURE_CBAR)) { |
f318cec6 PM |
2583 | if (arm_feature(env, ARM_FEATURE_AARCH64)) { |
2584 | /* 32 bit view is [31:18] 0...0 [43:32]. */ | |
2585 | uint32_t cbar32 = (extract64(cpu->reset_cbar, 18, 14) << 18) | |
2586 | | extract64(cpu->reset_cbar, 32, 12); | |
2587 | ARMCPRegInfo cbar_reginfo[] = { | |
2588 | { .name = "CBAR", | |
2589 | .type = ARM_CP_CONST, | |
2590 | .cp = 15, .crn = 15, .crm = 0, .opc1 = 4, .opc2 = 0, | |
2591 | .access = PL1_R, .resetvalue = cpu->reset_cbar }, | |
2592 | { .name = "CBAR_EL1", .state = ARM_CP_STATE_AA64, | |
2593 | .type = ARM_CP_CONST, | |
2594 | .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 3, .opc2 = 0, | |
2595 | .access = PL1_R, .resetvalue = cbar32 }, | |
2596 | REGINFO_SENTINEL | |
2597 | }; | |
2598 | /* We don't implement a r/w 64 bit CBAR currently */ | |
2599 | assert(arm_feature(env, ARM_FEATURE_CBAR_RO)); | |
2600 | define_arm_cp_regs(cpu, cbar_reginfo); | |
2601 | } else { | |
2602 | ARMCPRegInfo cbar = { | |
2603 | .name = "CBAR", | |
2604 | .cp = 15, .crn = 15, .crm = 0, .opc1 = 4, .opc2 = 0, | |
2605 | .access = PL1_R|PL3_W, .resetvalue = cpu->reset_cbar, | |
2606 | .fieldoffset = offsetof(CPUARMState, | |
2607 | cp15.c15_config_base_address) | |
2608 | }; | |
2609 | if (arm_feature(env, ARM_FEATURE_CBAR_RO)) { | |
2610 | cbar.access = PL1_R; | |
2611 | cbar.fieldoffset = 0; | |
2612 | cbar.type = ARM_CP_CONST; | |
2613 | } | |
2614 | define_one_arm_cp_reg(cpu, &cbar); | |
2615 | } | |
d8ba780b PC |
2616 | } |
2617 | ||
2771db27 PM |
2618 | /* Generic registers whose values depend on the implementation */ |
2619 | { | |
2620 | ARMCPRegInfo sctlr = { | |
5ebafdf3 PM |
2621 | .name = "SCTLR", .state = ARM_CP_STATE_BOTH, |
2622 | .opc0 = 3, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 0, | |
2771db27 | 2623 | .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c1_sys), |
d4e6df63 PM |
2624 | .writefn = sctlr_write, .resetvalue = cpu->reset_sctlr, |
2625 | .raw_writefn = raw_write, | |
2771db27 PM |
2626 | }; |
2627 | if (arm_feature(env, ARM_FEATURE_XSCALE)) { | |
2628 | /* Normally we would always end the TB on an SCTLR write, but Linux | |
2629 | * arch/arm/mach-pxa/sleep.S expects two instructions following | |
2630 | * an MMU enable to execute from cache. Imitate this behaviour. | |
2631 | */ | |
2632 | sctlr.type |= ARM_CP_SUPPRESS_TB_END; | |
2633 | } | |
2634 | define_one_arm_cp_reg(cpu, &sctlr); | |
2635 | } | |
2ceb98c0 PM |
2636 | } |
2637 | ||
778c3a06 | 2638 | ARMCPU *cpu_arm_init(const char *cpu_model) |
40f137e1 | 2639 | { |
9262685b | 2640 | return ARM_CPU(cpu_generic_init(TYPE_ARM_CPU, cpu_model)); |
14969266 AF |
2641 | } |
2642 | ||
2643 | void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu) | |
2644 | { | |
22169d41 | 2645 | CPUState *cs = CPU(cpu); |
14969266 AF |
2646 | CPUARMState *env = &cpu->env; |
2647 | ||
6a669427 PM |
2648 | if (arm_feature(env, ARM_FEATURE_AARCH64)) { |
2649 | gdb_register_coprocessor(cs, aarch64_fpu_gdb_get_reg, | |
2650 | aarch64_fpu_gdb_set_reg, | |
2651 | 34, "aarch64-fpu.xml", 0); | |
2652 | } else if (arm_feature(env, ARM_FEATURE_NEON)) { | |
22169d41 | 2653 | gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg, |
56aebc89 PB |
2654 | 51, "arm-neon.xml", 0); |
2655 | } else if (arm_feature(env, ARM_FEATURE_VFP3)) { | |
22169d41 | 2656 | gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg, |
56aebc89 PB |
2657 | 35, "arm-vfp3.xml", 0); |
2658 | } else if (arm_feature(env, ARM_FEATURE_VFP)) { | |
22169d41 | 2659 | gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg, |
56aebc89 PB |
2660 | 19, "arm-vfp.xml", 0); |
2661 | } | |
40f137e1 PB |
2662 | } |
2663 | ||
777dc784 PM |
2664 | /* Sort alphabetically by type name, except for "any". */ |
2665 | static gint arm_cpu_list_compare(gconstpointer a, gconstpointer b) | |
5adb4839 | 2666 | { |
777dc784 PM |
2667 | ObjectClass *class_a = (ObjectClass *)a; |
2668 | ObjectClass *class_b = (ObjectClass *)b; | |
2669 | const char *name_a, *name_b; | |
5adb4839 | 2670 | |
777dc784 PM |
2671 | name_a = object_class_get_name(class_a); |
2672 | name_b = object_class_get_name(class_b); | |
51492fd1 | 2673 | if (strcmp(name_a, "any-" TYPE_ARM_CPU) == 0) { |
777dc784 | 2674 | return 1; |
51492fd1 | 2675 | } else if (strcmp(name_b, "any-" TYPE_ARM_CPU) == 0) { |
777dc784 PM |
2676 | return -1; |
2677 | } else { | |
2678 | return strcmp(name_a, name_b); | |
5adb4839 PB |
2679 | } |
2680 | } | |
2681 | ||
777dc784 | 2682 | static void arm_cpu_list_entry(gpointer data, gpointer user_data) |
40f137e1 | 2683 | { |
777dc784 | 2684 | ObjectClass *oc = data; |
92a31361 | 2685 | CPUListState *s = user_data; |
51492fd1 AF |
2686 | const char *typename; |
2687 | char *name; | |
3371d272 | 2688 | |
51492fd1 AF |
2689 | typename = object_class_get_name(oc); |
2690 | name = g_strndup(typename, strlen(typename) - strlen("-" TYPE_ARM_CPU)); | |
777dc784 | 2691 | (*s->cpu_fprintf)(s->file, " %s\n", |
51492fd1 AF |
2692 | name); |
2693 | g_free(name); | |
777dc784 PM |
2694 | } |
2695 | ||
2696 | void arm_cpu_list(FILE *f, fprintf_function cpu_fprintf) | |
2697 | { | |
92a31361 | 2698 | CPUListState s = { |
777dc784 PM |
2699 | .file = f, |
2700 | .cpu_fprintf = cpu_fprintf, | |
2701 | }; | |
2702 | GSList *list; | |
2703 | ||
2704 | list = object_class_get_list(TYPE_ARM_CPU, false); | |
2705 | list = g_slist_sort(list, arm_cpu_list_compare); | |
2706 | (*cpu_fprintf)(f, "Available CPUs:\n"); | |
2707 | g_slist_foreach(list, arm_cpu_list_entry, &s); | |
2708 | g_slist_free(list); | |
a96c0514 PM |
2709 | #ifdef CONFIG_KVM |
2710 | /* The 'host' CPU type is dynamically registered only if KVM is | |
2711 | * enabled, so we have to special-case it here: | |
2712 | */ | |
2713 | (*cpu_fprintf)(f, " host (only available in KVM mode)\n"); | |
2714 | #endif | |
40f137e1 PB |
2715 | } |
2716 | ||
78027bb6 CR |
2717 | static void arm_cpu_add_definition(gpointer data, gpointer user_data) |
2718 | { | |
2719 | ObjectClass *oc = data; | |
2720 | CpuDefinitionInfoList **cpu_list = user_data; | |
2721 | CpuDefinitionInfoList *entry; | |
2722 | CpuDefinitionInfo *info; | |
2723 | const char *typename; | |
2724 | ||
2725 | typename = object_class_get_name(oc); | |
2726 | info = g_malloc0(sizeof(*info)); | |
2727 | info->name = g_strndup(typename, | |
2728 | strlen(typename) - strlen("-" TYPE_ARM_CPU)); | |
2729 | ||
2730 | entry = g_malloc0(sizeof(*entry)); | |
2731 | entry->value = info; | |
2732 | entry->next = *cpu_list; | |
2733 | *cpu_list = entry; | |
2734 | } | |
2735 | ||
2736 | CpuDefinitionInfoList *arch_query_cpu_definitions(Error **errp) | |
2737 | { | |
2738 | CpuDefinitionInfoList *cpu_list = NULL; | |
2739 | GSList *list; | |
2740 | ||
2741 | list = object_class_get_list(TYPE_ARM_CPU, false); | |
2742 | g_slist_foreach(list, arm_cpu_add_definition, &cpu_list); | |
2743 | g_slist_free(list); | |
2744 | ||
2745 | return cpu_list; | |
2746 | } | |
2747 | ||
6e6efd61 | 2748 | static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r, |
f5a0a5a5 PM |
2749 | void *opaque, int state, |
2750 | int crm, int opc1, int opc2) | |
6e6efd61 PM |
2751 | { |
2752 | /* Private utility function for define_one_arm_cp_reg_with_opaque(): | |
2753 | * add a single reginfo struct to the hash table. | |
2754 | */ | |
2755 | uint32_t *key = g_new(uint32_t, 1); | |
2756 | ARMCPRegInfo *r2 = g_memdup(r, sizeof(ARMCPRegInfo)); | |
2757 | int is64 = (r->type & ARM_CP_64BIT) ? 1 : 0; | |
f5a0a5a5 PM |
2758 | if (r->state == ARM_CP_STATE_BOTH && state == ARM_CP_STATE_AA32) { |
2759 | /* The AArch32 view of a shared register sees the lower 32 bits | |
2760 | * of a 64 bit backing field. It is not migratable as the AArch64 | |
2761 | * view handles that. AArch64 also handles reset. | |
2762 | * We assume it is a cp15 register. | |
2763 | */ | |
2764 | r2->cp = 15; | |
2765 | r2->type |= ARM_CP_NO_MIGRATE; | |
2766 | r2->resetfn = arm_cp_reset_ignore; | |
2767 | #ifdef HOST_WORDS_BIGENDIAN | |
2768 | if (r2->fieldoffset) { | |
2769 | r2->fieldoffset += sizeof(uint32_t); | |
2770 | } | |
2771 | #endif | |
2772 | } | |
2773 | if (state == ARM_CP_STATE_AA64) { | |
2774 | /* To allow abbreviation of ARMCPRegInfo | |
2775 | * definitions, we treat cp == 0 as equivalent to | |
2776 | * the value for "standard guest-visible sysreg". | |
2777 | */ | |
2778 | if (r->cp == 0) { | |
2779 | r2->cp = CP_REG_ARM64_SYSREG_CP; | |
2780 | } | |
2781 | *key = ENCODE_AA64_CP_REG(r2->cp, r2->crn, crm, | |
2782 | r2->opc0, opc1, opc2); | |
2783 | } else { | |
2784 | *key = ENCODE_CP_REG(r2->cp, is64, r2->crn, crm, opc1, opc2); | |
2785 | } | |
6e6efd61 PM |
2786 | if (opaque) { |
2787 | r2->opaque = opaque; | |
2788 | } | |
67ed771d PM |
2789 | /* reginfo passed to helpers is correct for the actual access, |
2790 | * and is never ARM_CP_STATE_BOTH: | |
2791 | */ | |
2792 | r2->state = state; | |
6e6efd61 PM |
2793 | /* Make sure reginfo passed to helpers for wildcarded regs |
2794 | * has the correct crm/opc1/opc2 for this reg, not CP_ANY: | |
2795 | */ | |
2796 | r2->crm = crm; | |
2797 | r2->opc1 = opc1; | |
2798 | r2->opc2 = opc2; | |
2799 | /* By convention, for wildcarded registers only the first | |
2800 | * entry is used for migration; the others are marked as | |
2801 | * NO_MIGRATE so we don't try to transfer the register | |
2802 | * multiple times. Special registers (ie NOP/WFI) are | |
2803 | * never migratable. | |
2804 | */ | |
2805 | if ((r->type & ARM_CP_SPECIAL) || | |
2806 | ((r->crm == CP_ANY) && crm != 0) || | |
2807 | ((r->opc1 == CP_ANY) && opc1 != 0) || | |
2808 | ((r->opc2 == CP_ANY) && opc2 != 0)) { | |
2809 | r2->type |= ARM_CP_NO_MIGRATE; | |
2810 | } | |
2811 | ||
2812 | /* Overriding of an existing definition must be explicitly | |
2813 | * requested. | |
2814 | */ | |
2815 | if (!(r->type & ARM_CP_OVERRIDE)) { | |
2816 | ARMCPRegInfo *oldreg; | |
2817 | oldreg = g_hash_table_lookup(cpu->cp_regs, key); | |
2818 | if (oldreg && !(oldreg->type & ARM_CP_OVERRIDE)) { | |
2819 | fprintf(stderr, "Register redefined: cp=%d %d bit " | |
2820 | "crn=%d crm=%d opc1=%d opc2=%d, " | |
2821 | "was %s, now %s\n", r2->cp, 32 + 32 * is64, | |
2822 | r2->crn, r2->crm, r2->opc1, r2->opc2, | |
2823 | oldreg->name, r2->name); | |
2824 | g_assert_not_reached(); | |
2825 | } | |
2826 | } | |
2827 | g_hash_table_insert(cpu->cp_regs, key, r2); | |
2828 | } | |
2829 | ||
2830 | ||
4b6a83fb PM |
2831 | void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu, |
2832 | const ARMCPRegInfo *r, void *opaque) | |
2833 | { | |
2834 | /* Define implementations of coprocessor registers. | |
2835 | * We store these in a hashtable because typically | |
2836 | * there are less than 150 registers in a space which | |
2837 | * is 16*16*16*8*8 = 262144 in size. | |
2838 | * Wildcarding is supported for the crm, opc1 and opc2 fields. | |
2839 | * If a register is defined twice then the second definition is | |
2840 | * used, so this can be used to define some generic registers and | |
2841 | * then override them with implementation specific variations. | |
2842 | * At least one of the original and the second definition should | |
2843 | * include ARM_CP_OVERRIDE in its type bits -- this is just a guard | |
2844 | * against accidental use. | |
f5a0a5a5 PM |
2845 | * |
2846 | * The state field defines whether the register is to be | |
2847 | * visible in the AArch32 or AArch64 execution state. If the | |
2848 | * state is set to ARM_CP_STATE_BOTH then we synthesise a | |
2849 | * reginfo structure for the AArch32 view, which sees the lower | |
2850 | * 32 bits of the 64 bit register. | |
2851 | * | |
2852 | * Only registers visible in AArch64 may set r->opc0; opc0 cannot | |
2853 | * be wildcarded. AArch64 registers are always considered to be 64 | |
2854 | * bits; the ARM_CP_64BIT* flag applies only to the AArch32 view of | |
2855 | * the register, if any. | |
4b6a83fb | 2856 | */ |
f5a0a5a5 | 2857 | int crm, opc1, opc2, state; |
4b6a83fb PM |
2858 | int crmmin = (r->crm == CP_ANY) ? 0 : r->crm; |
2859 | int crmmax = (r->crm == CP_ANY) ? 15 : r->crm; | |
2860 | int opc1min = (r->opc1 == CP_ANY) ? 0 : r->opc1; | |
2861 | int opc1max = (r->opc1 == CP_ANY) ? 7 : r->opc1; | |
2862 | int opc2min = (r->opc2 == CP_ANY) ? 0 : r->opc2; | |
2863 | int opc2max = (r->opc2 == CP_ANY) ? 7 : r->opc2; | |
2864 | /* 64 bit registers have only CRm and Opc1 fields */ | |
2865 | assert(!((r->type & ARM_CP_64BIT) && (r->opc2 || r->crn))); | |
f5a0a5a5 PM |
2866 | /* op0 only exists in the AArch64 encodings */ |
2867 | assert((r->state != ARM_CP_STATE_AA32) || (r->opc0 == 0)); | |
2868 | /* AArch64 regs are all 64 bit so ARM_CP_64BIT is meaningless */ | |
2869 | assert((r->state != ARM_CP_STATE_AA64) || !(r->type & ARM_CP_64BIT)); | |
2870 | /* The AArch64 pseudocode CheckSystemAccess() specifies that op1 | |
2871 | * encodes a minimum access level for the register. We roll this | |
2872 | * runtime check into our general permission check code, so check | |
2873 | * here that the reginfo's specified permissions are strict enough | |
2874 | * to encompass the generic architectural permission check. | |
2875 | */ | |
2876 | if (r->state != ARM_CP_STATE_AA32) { | |
2877 | int mask = 0; | |
2878 | switch (r->opc1) { | |
2879 | case 0: case 1: case 2: | |
2880 | /* min_EL EL1 */ | |
2881 | mask = PL1_RW; | |
2882 | break; | |
2883 | case 3: | |
2884 | /* min_EL EL0 */ | |
2885 | mask = PL0_RW; | |
2886 | break; | |
2887 | case 4: | |
2888 | /* min_EL EL2 */ | |
2889 | mask = PL2_RW; | |
2890 | break; | |
2891 | case 5: | |
2892 | /* unallocated encoding, so not possible */ | |
2893 | assert(false); | |
2894 | break; | |
2895 | case 6: | |
2896 | /* min_EL EL3 */ | |
2897 | mask = PL3_RW; | |
2898 | break; | |
2899 | case 7: | |
2900 | /* min_EL EL1, secure mode only (we don't check the latter) */ | |
2901 | mask = PL1_RW; | |
2902 | break; | |
2903 | default: | |
2904 | /* broken reginfo with out-of-range opc1 */ | |
2905 | assert(false); | |
2906 | break; | |
2907 | } | |
2908 | /* assert our permissions are not too lax (stricter is fine) */ | |
2909 | assert((r->access & ~mask) == 0); | |
2910 | } | |
2911 | ||
4b6a83fb PM |
2912 | /* Check that the register definition has enough info to handle |
2913 | * reads and writes if they are permitted. | |
2914 | */ | |
2915 | if (!(r->type & (ARM_CP_SPECIAL|ARM_CP_CONST))) { | |
2916 | if (r->access & PL3_R) { | |
2917 | assert(r->fieldoffset || r->readfn); | |
2918 | } | |
2919 | if (r->access & PL3_W) { | |
2920 | assert(r->fieldoffset || r->writefn); | |
2921 | } | |
2922 | } | |
2923 | /* Bad type field probably means missing sentinel at end of reg list */ | |
2924 | assert(cptype_valid(r->type)); | |
2925 | for (crm = crmmin; crm <= crmmax; crm++) { | |
2926 | for (opc1 = opc1min; opc1 <= opc1max; opc1++) { | |
2927 | for (opc2 = opc2min; opc2 <= opc2max; opc2++) { | |
f5a0a5a5 PM |
2928 | for (state = ARM_CP_STATE_AA32; |
2929 | state <= ARM_CP_STATE_AA64; state++) { | |
2930 | if (r->state != state && r->state != ARM_CP_STATE_BOTH) { | |
2931 | continue; | |
2932 | } | |
2933 | add_cpreg_to_hashtable(cpu, r, opaque, state, | |
2934 | crm, opc1, opc2); | |
2935 | } | |
4b6a83fb PM |
2936 | } |
2937 | } | |
2938 | } | |
2939 | } | |
2940 | ||
2941 | void define_arm_cp_regs_with_opaque(ARMCPU *cpu, | |
2942 | const ARMCPRegInfo *regs, void *opaque) | |
2943 | { | |
2944 | /* Define a whole list of registers */ | |
2945 | const ARMCPRegInfo *r; | |
2946 | for (r = regs; r->type != ARM_CP_SENTINEL; r++) { | |
2947 | define_one_arm_cp_reg_with_opaque(cpu, r, opaque); | |
2948 | } | |
2949 | } | |
2950 | ||
60322b39 | 2951 | const ARMCPRegInfo *get_arm_cp_reginfo(GHashTable *cpregs, uint32_t encoded_cp) |
4b6a83fb | 2952 | { |
60322b39 | 2953 | return g_hash_table_lookup(cpregs, &encoded_cp); |
4b6a83fb PM |
2954 | } |
2955 | ||
c4241c7d PM |
2956 | void arm_cp_write_ignore(CPUARMState *env, const ARMCPRegInfo *ri, |
2957 | uint64_t value) | |
4b6a83fb PM |
2958 | { |
2959 | /* Helper coprocessor write function for write-ignore registers */ | |
4b6a83fb PM |
2960 | } |
2961 | ||
c4241c7d | 2962 | uint64_t arm_cp_read_zero(CPUARMState *env, const ARMCPRegInfo *ri) |
4b6a83fb PM |
2963 | { |
2964 | /* Helper coprocessor write function for read-as-zero registers */ | |
4b6a83fb PM |
2965 | return 0; |
2966 | } | |
2967 | ||
f5a0a5a5 PM |
2968 | void arm_cp_reset_ignore(CPUARMState *env, const ARMCPRegInfo *opaque) |
2969 | { | |
2970 | /* Helper coprocessor reset function for do-nothing-on-reset registers */ | |
2971 | } | |
2972 | ||
0ecb72a5 | 2973 | static int bad_mode_switch(CPUARMState *env, int mode) |
37064a8b PM |
2974 | { |
2975 | /* Return true if it is not valid for us to switch to | |
2976 | * this CPU mode (ie all the UNPREDICTABLE cases in | |
2977 | * the ARM ARM CPSRWriteByInstr pseudocode). | |
2978 | */ | |
2979 | switch (mode) { | |
2980 | case ARM_CPU_MODE_USR: | |
2981 | case ARM_CPU_MODE_SYS: | |
2982 | case ARM_CPU_MODE_SVC: | |
2983 | case ARM_CPU_MODE_ABT: | |
2984 | case ARM_CPU_MODE_UND: | |
2985 | case ARM_CPU_MODE_IRQ: | |
2986 | case ARM_CPU_MODE_FIQ: | |
2987 | return 0; | |
2988 | default: | |
2989 | return 1; | |
2990 | } | |
2991 | } | |
2992 | ||
2f4a40e5 AZ |
2993 | uint32_t cpsr_read(CPUARMState *env) |
2994 | { | |
2995 | int ZF; | |
6fbe23d5 PB |
2996 | ZF = (env->ZF == 0); |
2997 | return env->uncached_cpsr | (env->NF & 0x80000000) | (ZF << 30) | | |
2f4a40e5 AZ |
2998 | (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27) |
2999 | | (env->thumb << 5) | ((env->condexec_bits & 3) << 25) | |
3000 | | ((env->condexec_bits & 0xfc) << 8) | |
af519934 | 3001 | | (env->GE << 16) | (env->daif & CPSR_AIF); |
2f4a40e5 AZ |
3002 | } |
3003 | ||
3004 | void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask) | |
3005 | { | |
2f4a40e5 | 3006 | if (mask & CPSR_NZCV) { |
6fbe23d5 PB |
3007 | env->ZF = (~val) & CPSR_Z; |
3008 | env->NF = val; | |
2f4a40e5 AZ |
3009 | env->CF = (val >> 29) & 1; |
3010 | env->VF = (val << 3) & 0x80000000; | |
3011 | } | |
3012 | if (mask & CPSR_Q) | |
3013 | env->QF = ((val & CPSR_Q) != 0); | |
3014 | if (mask & CPSR_T) | |
3015 | env->thumb = ((val & CPSR_T) != 0); | |
3016 | if (mask & CPSR_IT_0_1) { | |
3017 | env->condexec_bits &= ~3; | |
3018 | env->condexec_bits |= (val >> 25) & 3; | |
3019 | } | |
3020 | if (mask & CPSR_IT_2_7) { | |
3021 | env->condexec_bits &= 3; | |
3022 | env->condexec_bits |= (val >> 8) & 0xfc; | |
3023 | } | |
3024 | if (mask & CPSR_GE) { | |
3025 | env->GE = (val >> 16) & 0xf; | |
3026 | } | |
3027 | ||
4cc35614 PM |
3028 | env->daif &= ~(CPSR_AIF & mask); |
3029 | env->daif |= val & CPSR_AIF & mask; | |
3030 | ||
2f4a40e5 | 3031 | if ((env->uncached_cpsr ^ val) & mask & CPSR_M) { |
37064a8b PM |
3032 | if (bad_mode_switch(env, val & CPSR_M)) { |
3033 | /* Attempt to switch to an invalid mode: this is UNPREDICTABLE. | |
3034 | * We choose to ignore the attempt and leave the CPSR M field | |
3035 | * untouched. | |
3036 | */ | |
3037 | mask &= ~CPSR_M; | |
3038 | } else { | |
3039 | switch_mode(env, val & CPSR_M); | |
3040 | } | |
2f4a40e5 AZ |
3041 | } |
3042 | mask &= ~CACHED_CPSR_BITS; | |
3043 | env->uncached_cpsr = (env->uncached_cpsr & ~mask) | (val & mask); | |
3044 | } | |
3045 | ||
b26eefb6 PB |
3046 | /* Sign/zero extend */ |
3047 | uint32_t HELPER(sxtb16)(uint32_t x) | |
3048 | { | |
3049 | uint32_t res; | |
3050 | res = (uint16_t)(int8_t)x; | |
3051 | res |= (uint32_t)(int8_t)(x >> 16) << 16; | |
3052 | return res; | |
3053 | } | |
3054 | ||
3055 | uint32_t HELPER(uxtb16)(uint32_t x) | |
3056 | { | |
3057 | uint32_t res; | |
3058 | res = (uint16_t)(uint8_t)x; | |
3059 | res |= (uint32_t)(uint8_t)(x >> 16) << 16; | |
3060 | return res; | |
3061 | } | |
3062 | ||
f51bbbfe PB |
3063 | uint32_t HELPER(clz)(uint32_t x) |
3064 | { | |
7bbcb0af | 3065 | return clz32(x); |
f51bbbfe PB |
3066 | } |
3067 | ||
3670669c PB |
3068 | int32_t HELPER(sdiv)(int32_t num, int32_t den) |
3069 | { | |
3070 | if (den == 0) | |
3071 | return 0; | |
686eeb93 AJ |
3072 | if (num == INT_MIN && den == -1) |
3073 | return INT_MIN; | |
3670669c PB |
3074 | return num / den; |
3075 | } | |
3076 | ||
3077 | uint32_t HELPER(udiv)(uint32_t num, uint32_t den) | |
3078 | { | |
3079 | if (den == 0) | |
3080 | return 0; | |
3081 | return num / den; | |
3082 | } | |
3083 | ||
3084 | uint32_t HELPER(rbit)(uint32_t x) | |
3085 | { | |
3086 | x = ((x & 0xff000000) >> 24) | |
3087 | | ((x & 0x00ff0000) >> 8) | |
3088 | | ((x & 0x0000ff00) << 8) | |
3089 | | ((x & 0x000000ff) << 24); | |
3090 | x = ((x & 0xf0f0f0f0) >> 4) | |
3091 | | ((x & 0x0f0f0f0f) << 4); | |
3092 | x = ((x & 0x88888888) >> 3) | |
3093 | | ((x & 0x44444444) >> 1) | |
3094 | | ((x & 0x22222222) << 1) | |
3095 | | ((x & 0x11111111) << 3); | |
3096 | return x; | |
3097 | } | |
3098 | ||
5fafdf24 | 3099 | #if defined(CONFIG_USER_ONLY) |
b5ff1b31 | 3100 | |
97a8ea5a | 3101 | void arm_cpu_do_interrupt(CPUState *cs) |
b5ff1b31 | 3102 | { |
27103424 | 3103 | cs->exception_index = -1; |
b5ff1b31 FB |
3104 | } |
3105 | ||
7510454e AF |
3106 | int arm_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw, |
3107 | int mmu_idx) | |
b5ff1b31 | 3108 | { |
7510454e AF |
3109 | ARMCPU *cpu = ARM_CPU(cs); |
3110 | CPUARMState *env = &cpu->env; | |
3111 | ||
abf1172f | 3112 | env->exception.vaddress = address; |
b5ff1b31 | 3113 | if (rw == 2) { |
27103424 | 3114 | cs->exception_index = EXCP_PREFETCH_ABORT; |
b5ff1b31 | 3115 | } else { |
27103424 | 3116 | cs->exception_index = EXCP_DATA_ABORT; |
b5ff1b31 FB |
3117 | } |
3118 | return 1; | |
3119 | } | |
3120 | ||
9ee6e8bb | 3121 | /* These should probably raise undefined insn exceptions. */ |
0ecb72a5 | 3122 | void HELPER(v7m_msr)(CPUARMState *env, uint32_t reg, uint32_t val) |
9ee6e8bb | 3123 | { |
a47dddd7 AF |
3124 | ARMCPU *cpu = arm_env_get_cpu(env); |
3125 | ||
3126 | cpu_abort(CPU(cpu), "v7m_msr %d\n", reg); | |
9ee6e8bb PB |
3127 | } |
3128 | ||
0ecb72a5 | 3129 | uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg) |
9ee6e8bb | 3130 | { |
a47dddd7 AF |
3131 | ARMCPU *cpu = arm_env_get_cpu(env); |
3132 | ||
3133 | cpu_abort(CPU(cpu), "v7m_mrs %d\n", reg); | |
9ee6e8bb PB |
3134 | return 0; |
3135 | } | |
3136 | ||
0ecb72a5 | 3137 | void switch_mode(CPUARMState *env, int mode) |
b5ff1b31 | 3138 | { |
a47dddd7 AF |
3139 | ARMCPU *cpu = arm_env_get_cpu(env); |
3140 | ||
3141 | if (mode != ARM_CPU_MODE_USR) { | |
3142 | cpu_abort(CPU(cpu), "Tried to switch out of user mode\n"); | |
3143 | } | |
b5ff1b31 FB |
3144 | } |
3145 | ||
0ecb72a5 | 3146 | void HELPER(set_r13_banked)(CPUARMState *env, uint32_t mode, uint32_t val) |
9ee6e8bb | 3147 | { |
a47dddd7 AF |
3148 | ARMCPU *cpu = arm_env_get_cpu(env); |
3149 | ||
3150 | cpu_abort(CPU(cpu), "banked r13 write\n"); | |
9ee6e8bb PB |
3151 | } |
3152 | ||
0ecb72a5 | 3153 | uint32_t HELPER(get_r13_banked)(CPUARMState *env, uint32_t mode) |
9ee6e8bb | 3154 | { |
a47dddd7 AF |
3155 | ARMCPU *cpu = arm_env_get_cpu(env); |
3156 | ||
3157 | cpu_abort(CPU(cpu), "banked r13 read\n"); | |
9ee6e8bb PB |
3158 | return 0; |
3159 | } | |
3160 | ||
b5ff1b31 FB |
3161 | #else |
3162 | ||
3163 | /* Map CPU modes onto saved register banks. */ | |
494b00c7 | 3164 | int bank_number(int mode) |
b5ff1b31 FB |
3165 | { |
3166 | switch (mode) { | |
3167 | case ARM_CPU_MODE_USR: | |
3168 | case ARM_CPU_MODE_SYS: | |
3169 | return 0; | |
3170 | case ARM_CPU_MODE_SVC: | |
3171 | return 1; | |
3172 | case ARM_CPU_MODE_ABT: | |
3173 | return 2; | |
3174 | case ARM_CPU_MODE_UND: | |
3175 | return 3; | |
3176 | case ARM_CPU_MODE_IRQ: | |
3177 | return 4; | |
3178 | case ARM_CPU_MODE_FIQ: | |
3179 | return 5; | |
28c9457d EI |
3180 | case ARM_CPU_MODE_HYP: |
3181 | return 6; | |
3182 | case ARM_CPU_MODE_MON: | |
3183 | return 7; | |
b5ff1b31 | 3184 | } |
f5206413 | 3185 | hw_error("bank number requested for bad CPSR mode value 0x%x\n", mode); |
b5ff1b31 FB |
3186 | } |
3187 | ||
0ecb72a5 | 3188 | void switch_mode(CPUARMState *env, int mode) |
b5ff1b31 FB |
3189 | { |
3190 | int old_mode; | |
3191 | int i; | |
3192 | ||
3193 | old_mode = env->uncached_cpsr & CPSR_M; | |
3194 | if (mode == old_mode) | |
3195 | return; | |
3196 | ||
3197 | if (old_mode == ARM_CPU_MODE_FIQ) { | |
3198 | memcpy (env->fiq_regs, env->regs + 8, 5 * sizeof(uint32_t)); | |
8637c67f | 3199 | memcpy (env->regs + 8, env->usr_regs, 5 * sizeof(uint32_t)); |
b5ff1b31 FB |
3200 | } else if (mode == ARM_CPU_MODE_FIQ) { |
3201 | memcpy (env->usr_regs, env->regs + 8, 5 * sizeof(uint32_t)); | |
8637c67f | 3202 | memcpy (env->regs + 8, env->fiq_regs, 5 * sizeof(uint32_t)); |
b5ff1b31 FB |
3203 | } |
3204 | ||
f5206413 | 3205 | i = bank_number(old_mode); |
b5ff1b31 FB |
3206 | env->banked_r13[i] = env->regs[13]; |
3207 | env->banked_r14[i] = env->regs[14]; | |
3208 | env->banked_spsr[i] = env->spsr; | |
3209 | ||
f5206413 | 3210 | i = bank_number(mode); |
b5ff1b31 FB |
3211 | env->regs[13] = env->banked_r13[i]; |
3212 | env->regs[14] = env->banked_r14[i]; | |
3213 | env->spsr = env->banked_spsr[i]; | |
3214 | } | |
3215 | ||
9ee6e8bb PB |
3216 | static void v7m_push(CPUARMState *env, uint32_t val) |
3217 | { | |
70d74660 AF |
3218 | CPUState *cs = CPU(arm_env_get_cpu(env)); |
3219 | ||
9ee6e8bb | 3220 | env->regs[13] -= 4; |
ab1da857 | 3221 | stl_phys(cs->as, env->regs[13], val); |
9ee6e8bb PB |
3222 | } |
3223 | ||
3224 | static uint32_t v7m_pop(CPUARMState *env) | |
3225 | { | |
70d74660 | 3226 | CPUState *cs = CPU(arm_env_get_cpu(env)); |
9ee6e8bb | 3227 | uint32_t val; |
70d74660 | 3228 | |
fdfba1a2 | 3229 | val = ldl_phys(cs->as, env->regs[13]); |
9ee6e8bb PB |
3230 | env->regs[13] += 4; |
3231 | return val; | |
3232 | } | |
3233 | ||
3234 | /* Switch to V7M main or process stack pointer. */ | |
3235 | static void switch_v7m_sp(CPUARMState *env, int process) | |
3236 | { | |
3237 | uint32_t tmp; | |
3238 | if (env->v7m.current_sp != process) { | |
3239 | tmp = env->v7m.other_sp; | |
3240 | env->v7m.other_sp = env->regs[13]; | |
3241 | env->regs[13] = tmp; | |
3242 | env->v7m.current_sp = process; | |
3243 | } | |
3244 | } | |
3245 | ||
3246 | static void do_v7m_exception_exit(CPUARMState *env) | |
3247 | { | |
3248 | uint32_t type; | |
3249 | uint32_t xpsr; | |
3250 | ||
3251 | type = env->regs[15]; | |
3252 | if (env->v7m.exception != 0) | |
983fe826 | 3253 | armv7m_nvic_complete_irq(env->nvic, env->v7m.exception); |
9ee6e8bb PB |
3254 | |
3255 | /* Switch to the target stack. */ | |
3256 | switch_v7m_sp(env, (type & 4) != 0); | |
3257 | /* Pop registers. */ | |
3258 | env->regs[0] = v7m_pop(env); | |
3259 | env->regs[1] = v7m_pop(env); | |
3260 | env->regs[2] = v7m_pop(env); | |
3261 | env->regs[3] = v7m_pop(env); | |
3262 | env->regs[12] = v7m_pop(env); | |
3263 | env->regs[14] = v7m_pop(env); | |
3264 | env->regs[15] = v7m_pop(env); | |
3265 | xpsr = v7m_pop(env); | |
3266 | xpsr_write(env, xpsr, 0xfffffdff); | |
3267 | /* Undo stack alignment. */ | |
3268 | if (xpsr & 0x200) | |
3269 | env->regs[13] |= 4; | |
3270 | /* ??? The exception return type specifies Thread/Handler mode. However | |
3271 | this is also implied by the xPSR value. Not sure what to do | |
3272 | if there is a mismatch. */ | |
3273 | /* ??? Likewise for mismatches between the CONTROL register and the stack | |
3274 | pointer. */ | |
3275 | } | |
3276 | ||
e6f010cc | 3277 | void arm_v7m_cpu_do_interrupt(CPUState *cs) |
9ee6e8bb | 3278 | { |
e6f010cc AF |
3279 | ARMCPU *cpu = ARM_CPU(cs); |
3280 | CPUARMState *env = &cpu->env; | |
9ee6e8bb PB |
3281 | uint32_t xpsr = xpsr_read(env); |
3282 | uint32_t lr; | |
3283 | uint32_t addr; | |
3284 | ||
27103424 | 3285 | arm_log_exception(cs->exception_index); |
3f1beaca | 3286 | |
9ee6e8bb PB |
3287 | lr = 0xfffffff1; |
3288 | if (env->v7m.current_sp) | |
3289 | lr |= 4; | |
3290 | if (env->v7m.exception == 0) | |
3291 | lr |= 8; | |
3292 | ||
3293 | /* For exceptions we just mark as pending on the NVIC, and let that | |
3294 | handle it. */ | |
3295 | /* TODO: Need to escalate if the current priority is higher than the | |
3296 | one we're raising. */ | |
27103424 | 3297 | switch (cs->exception_index) { |
9ee6e8bb | 3298 | case EXCP_UDEF: |
983fe826 | 3299 | armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE); |
9ee6e8bb PB |
3300 | return; |
3301 | case EXCP_SWI: | |
314e2296 | 3302 | /* The PC already points to the next instruction. */ |
983fe826 | 3303 | armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_SVC); |
9ee6e8bb PB |
3304 | return; |
3305 | case EXCP_PREFETCH_ABORT: | |
3306 | case EXCP_DATA_ABORT: | |
abf1172f PM |
3307 | /* TODO: if we implemented the MPU registers, this is where we |
3308 | * should set the MMFAR, etc from exception.fsr and exception.vaddress. | |
3309 | */ | |
983fe826 | 3310 | armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_MEM); |
9ee6e8bb PB |
3311 | return; |
3312 | case EXCP_BKPT: | |
2ad207d4 PB |
3313 | if (semihosting_enabled) { |
3314 | int nr; | |
d31dd73e | 3315 | nr = arm_lduw_code(env, env->regs[15], env->bswap_code) & 0xff; |
2ad207d4 PB |
3316 | if (nr == 0xab) { |
3317 | env->regs[15] += 2; | |
3318 | env->regs[0] = do_arm_semihosting(env); | |
3f1beaca | 3319 | qemu_log_mask(CPU_LOG_INT, "...handled as semihosting call\n"); |
2ad207d4 PB |
3320 | return; |
3321 | } | |
3322 | } | |
983fe826 | 3323 | armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_DEBUG); |
9ee6e8bb PB |
3324 | return; |
3325 | case EXCP_IRQ: | |
983fe826 | 3326 | env->v7m.exception = armv7m_nvic_acknowledge_irq(env->nvic); |
9ee6e8bb PB |
3327 | break; |
3328 | case EXCP_EXCEPTION_EXIT: | |
3329 | do_v7m_exception_exit(env); | |
3330 | return; | |
3331 | default: | |
a47dddd7 | 3332 | cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index); |
9ee6e8bb PB |
3333 | return; /* Never happens. Keep compiler happy. */ |
3334 | } | |
3335 | ||
3336 | /* Align stack pointer. */ | |
3337 | /* ??? Should only do this if Configuration Control Register | |
3338 | STACKALIGN bit is set. */ | |
3339 | if (env->regs[13] & 4) { | |
ab19b0ec | 3340 | env->regs[13] -= 4; |
9ee6e8bb PB |
3341 | xpsr |= 0x200; |
3342 | } | |
6c95676b | 3343 | /* Switch to the handler mode. */ |
9ee6e8bb PB |
3344 | v7m_push(env, xpsr); |
3345 | v7m_push(env, env->regs[15]); | |
3346 | v7m_push(env, env->regs[14]); | |
3347 | v7m_push(env, env->regs[12]); | |
3348 | v7m_push(env, env->regs[3]); | |
3349 | v7m_push(env, env->regs[2]); | |
3350 | v7m_push(env, env->regs[1]); | |
3351 | v7m_push(env, env->regs[0]); | |
3352 | switch_v7m_sp(env, 0); | |
c98d174c PM |
3353 | /* Clear IT bits */ |
3354 | env->condexec_bits = 0; | |
9ee6e8bb | 3355 | env->regs[14] = lr; |
fdfba1a2 | 3356 | addr = ldl_phys(cs->as, env->v7m.vecbase + env->v7m.exception * 4); |
9ee6e8bb PB |
3357 | env->regs[15] = addr & 0xfffffffe; |
3358 | env->thumb = addr & 1; | |
3359 | } | |
3360 | ||
b5ff1b31 | 3361 | /* Handle a CPU exception. */ |
97a8ea5a | 3362 | void arm_cpu_do_interrupt(CPUState *cs) |
b5ff1b31 | 3363 | { |
97a8ea5a AF |
3364 | ARMCPU *cpu = ARM_CPU(cs); |
3365 | CPUARMState *env = &cpu->env; | |
b5ff1b31 FB |
3366 | uint32_t addr; |
3367 | uint32_t mask; | |
3368 | int new_mode; | |
3369 | uint32_t offset; | |
3370 | ||
e6f010cc AF |
3371 | assert(!IS_M(env)); |
3372 | ||
27103424 | 3373 | arm_log_exception(cs->exception_index); |
3f1beaca | 3374 | |
b5ff1b31 | 3375 | /* TODO: Vectored interrupt controller. */ |
27103424 | 3376 | switch (cs->exception_index) { |
b5ff1b31 FB |
3377 | case EXCP_UDEF: |
3378 | new_mode = ARM_CPU_MODE_UND; | |
3379 | addr = 0x04; | |
3380 | mask = CPSR_I; | |
3381 | if (env->thumb) | |
3382 | offset = 2; | |
3383 | else | |
3384 | offset = 4; | |
3385 | break; | |
3386 | case EXCP_SWI: | |
8e71621f PB |
3387 | if (semihosting_enabled) { |
3388 | /* Check for semihosting interrupt. */ | |
3389 | if (env->thumb) { | |
d31dd73e BS |
3390 | mask = arm_lduw_code(env, env->regs[15] - 2, env->bswap_code) |
3391 | & 0xff; | |
8e71621f | 3392 | } else { |
d31dd73e | 3393 | mask = arm_ldl_code(env, env->regs[15] - 4, env->bswap_code) |
d8fd2954 | 3394 | & 0xffffff; |
8e71621f PB |
3395 | } |
3396 | /* Only intercept calls from privileged modes, to provide some | |
3397 | semblance of security. */ | |
3398 | if (((mask == 0x123456 && !env->thumb) | |
3399 | || (mask == 0xab && env->thumb)) | |
3400 | && (env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR) { | |
3401 | env->regs[0] = do_arm_semihosting(env); | |
3f1beaca | 3402 | qemu_log_mask(CPU_LOG_INT, "...handled as semihosting call\n"); |
8e71621f PB |
3403 | return; |
3404 | } | |
3405 | } | |
b5ff1b31 FB |
3406 | new_mode = ARM_CPU_MODE_SVC; |
3407 | addr = 0x08; | |
3408 | mask = CPSR_I; | |
601d70b9 | 3409 | /* The PC already points to the next instruction. */ |
b5ff1b31 FB |
3410 | offset = 0; |
3411 | break; | |
06c949e6 | 3412 | case EXCP_BKPT: |
9ee6e8bb | 3413 | /* See if this is a semihosting syscall. */ |
2ad207d4 | 3414 | if (env->thumb && semihosting_enabled) { |
d31dd73e | 3415 | mask = arm_lduw_code(env, env->regs[15], env->bswap_code) & 0xff; |
9ee6e8bb PB |
3416 | if (mask == 0xab |
3417 | && (env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR) { | |
3418 | env->regs[15] += 2; | |
3419 | env->regs[0] = do_arm_semihosting(env); | |
3f1beaca | 3420 | qemu_log_mask(CPU_LOG_INT, "...handled as semihosting call\n"); |
9ee6e8bb PB |
3421 | return; |
3422 | } | |
3423 | } | |
abf1172f | 3424 | env->exception.fsr = 2; |
9ee6e8bb PB |
3425 | /* Fall through to prefetch abort. */ |
3426 | case EXCP_PREFETCH_ABORT: | |
6cd8a264 RH |
3427 | env->cp15.ifsr_el2 = env->exception.fsr; |
3428 | env->cp15.far_el1 = deposit64(env->cp15.far_el1, 32, 32, | |
3429 | env->exception.vaddress); | |
3f1beaca | 3430 | qemu_log_mask(CPU_LOG_INT, "...with IFSR 0x%x IFAR 0x%x\n", |
6cd8a264 | 3431 | env->cp15.ifsr_el2, (uint32_t)env->exception.vaddress); |
b5ff1b31 FB |
3432 | new_mode = ARM_CPU_MODE_ABT; |
3433 | addr = 0x0c; | |
3434 | mask = CPSR_A | CPSR_I; | |
3435 | offset = 4; | |
3436 | break; | |
3437 | case EXCP_DATA_ABORT: | |
d81c519c | 3438 | env->cp15.esr_el[1] = env->exception.fsr; |
6cd8a264 RH |
3439 | env->cp15.far_el1 = deposit64(env->cp15.far_el1, 0, 32, |
3440 | env->exception.vaddress); | |
3f1beaca | 3441 | qemu_log_mask(CPU_LOG_INT, "...with DFSR 0x%x DFAR 0x%x\n", |
d81c519c | 3442 | (uint32_t)env->cp15.esr_el[1], |
6cd8a264 | 3443 | (uint32_t)env->exception.vaddress); |
b5ff1b31 FB |
3444 | new_mode = ARM_CPU_MODE_ABT; |
3445 | addr = 0x10; | |
3446 | mask = CPSR_A | CPSR_I; | |
3447 | offset = 8; | |
3448 | break; | |
3449 | case EXCP_IRQ: | |
3450 | new_mode = ARM_CPU_MODE_IRQ; | |
3451 | addr = 0x18; | |
3452 | /* Disable IRQ and imprecise data aborts. */ | |
3453 | mask = CPSR_A | CPSR_I; | |
3454 | offset = 4; | |
3455 | break; | |
3456 | case EXCP_FIQ: | |
3457 | new_mode = ARM_CPU_MODE_FIQ; | |
3458 | addr = 0x1c; | |
3459 | /* Disable FIQ, IRQ and imprecise data aborts. */ | |
3460 | mask = CPSR_A | CPSR_I | CPSR_F; | |
3461 | offset = 4; | |
3462 | break; | |
3463 | default: | |
a47dddd7 | 3464 | cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index); |
b5ff1b31 FB |
3465 | return; /* Never happens. Keep compiler happy. */ |
3466 | } | |
3467 | /* High vectors. */ | |
76e3e1bc | 3468 | if (env->cp15.c1_sys & SCTLR_V) { |
8641136c | 3469 | /* when enabled, base address cannot be remapped. */ |
b5ff1b31 | 3470 | addr += 0xffff0000; |
8641136c NR |
3471 | } else { |
3472 | /* ARM v7 architectures provide a vector base address register to remap | |
3473 | * the interrupt vector table. | |
3474 | * This register is only followed in non-monitor mode, and has a secure | |
3475 | * and un-secure copy. Since the cpu is always in a un-secure operation | |
3476 | * and is never in monitor mode this feature is always active. | |
3477 | * Note: only bits 31:5 are valid. | |
3478 | */ | |
68fdb6c5 | 3479 | addr += env->cp15.vbar_el[1]; |
b5ff1b31 FB |
3480 | } |
3481 | switch_mode (env, new_mode); | |
3482 | env->spsr = cpsr_read(env); | |
9ee6e8bb PB |
3483 | /* Clear IT bits. */ |
3484 | env->condexec_bits = 0; | |
30a8cac1 | 3485 | /* Switch to the new mode, and to the correct instruction set. */ |
6d7e6326 | 3486 | env->uncached_cpsr = (env->uncached_cpsr & ~CPSR_M) | new_mode; |
4cc35614 | 3487 | env->daif |= mask; |
be5e7a76 DES |
3488 | /* this is a lie, as the was no c1_sys on V4T/V5, but who cares |
3489 | * and we should just guard the thumb mode on V4 */ | |
3490 | if (arm_feature(env, ARM_FEATURE_V4T)) { | |
76e3e1bc | 3491 | env->thumb = (env->cp15.c1_sys & SCTLR_TE) != 0; |
be5e7a76 | 3492 | } |
b5ff1b31 FB |
3493 | env->regs[14] = env->regs[15] + offset; |
3494 | env->regs[15] = addr; | |
259186a7 | 3495 | cs->interrupt_request |= CPU_INTERRUPT_EXITTB; |
b5ff1b31 FB |
3496 | } |
3497 | ||
3498 | /* Check section/page access permissions. | |
3499 | Returns the page protection flags, or zero if the access is not | |
3500 | permitted. */ | |
0ecb72a5 | 3501 | static inline int check_ap(CPUARMState *env, int ap, int domain_prot, |
dd4ebc2e | 3502 | int access_type, int is_user) |
b5ff1b31 | 3503 | { |
9ee6e8bb PB |
3504 | int prot_ro; |
3505 | ||
dd4ebc2e | 3506 | if (domain_prot == 3) { |
b5ff1b31 | 3507 | return PAGE_READ | PAGE_WRITE; |
dd4ebc2e | 3508 | } |
b5ff1b31 | 3509 | |
9ee6e8bb PB |
3510 | if (access_type == 1) |
3511 | prot_ro = 0; | |
3512 | else | |
3513 | prot_ro = PAGE_READ; | |
3514 | ||
b5ff1b31 FB |
3515 | switch (ap) { |
3516 | case 0: | |
99f678a6 PM |
3517 | if (arm_feature(env, ARM_FEATURE_V7)) { |
3518 | return 0; | |
3519 | } | |
78600320 | 3520 | if (access_type == 1) |
b5ff1b31 | 3521 | return 0; |
76e3e1bc PM |
3522 | switch (env->cp15.c1_sys & (SCTLR_S | SCTLR_R)) { |
3523 | case SCTLR_S: | |
b5ff1b31 | 3524 | return is_user ? 0 : PAGE_READ; |
76e3e1bc | 3525 | case SCTLR_R: |
b5ff1b31 FB |
3526 | return PAGE_READ; |
3527 | default: | |
3528 | return 0; | |
3529 | } | |
3530 | case 1: | |
3531 | return is_user ? 0 : PAGE_READ | PAGE_WRITE; | |
3532 | case 2: | |
3533 | if (is_user) | |
9ee6e8bb | 3534 | return prot_ro; |
b5ff1b31 FB |
3535 | else |
3536 | return PAGE_READ | PAGE_WRITE; | |
3537 | case 3: | |
3538 | return PAGE_READ | PAGE_WRITE; | |
d4934d18 | 3539 | case 4: /* Reserved. */ |
9ee6e8bb PB |
3540 | return 0; |
3541 | case 5: | |
3542 | return is_user ? 0 : prot_ro; | |
3543 | case 6: | |
3544 | return prot_ro; | |
d4934d18 | 3545 | case 7: |
0ab06d83 | 3546 | if (!arm_feature (env, ARM_FEATURE_V6K)) |
d4934d18 PB |
3547 | return 0; |
3548 | return prot_ro; | |
b5ff1b31 FB |
3549 | default: |
3550 | abort(); | |
3551 | } | |
3552 | } | |
3553 | ||
e389be16 FA |
3554 | static bool get_level1_table_address(CPUARMState *env, uint32_t *table, |
3555 | uint32_t address) | |
b2fa1797 | 3556 | { |
e389be16 FA |
3557 | if (address & env->cp15.c2_mask) { |
3558 | if ((env->cp15.c2_control & TTBCR_PD1)) { | |
3559 | /* Translation table walk disabled for TTBR1 */ | |
3560 | return false; | |
3561 | } | |
3562 | *table = env->cp15.ttbr1_el1 & 0xffffc000; | |
3563 | } else { | |
3564 | if ((env->cp15.c2_control & TTBCR_PD0)) { | |
3565 | /* Translation table walk disabled for TTBR0 */ | |
3566 | return false; | |
3567 | } | |
3568 | *table = env->cp15.ttbr0_el1 & env->cp15.c2_base_mask; | |
3569 | } | |
3570 | *table |= (address >> 18) & 0x3ffc; | |
3571 | return true; | |
b2fa1797 PB |
3572 | } |
3573 | ||
0ecb72a5 | 3574 | static int get_phys_addr_v5(CPUARMState *env, uint32_t address, int access_type, |
a8170e5e | 3575 | int is_user, hwaddr *phys_ptr, |
77a71dd1 | 3576 | int *prot, target_ulong *page_size) |
b5ff1b31 | 3577 | { |
70d74660 | 3578 | CPUState *cs = CPU(arm_env_get_cpu(env)); |
b5ff1b31 FB |
3579 | int code; |
3580 | uint32_t table; | |
3581 | uint32_t desc; | |
3582 | int type; | |
3583 | int ap; | |
e389be16 | 3584 | int domain = 0; |
dd4ebc2e | 3585 | int domain_prot; |
a8170e5e | 3586 | hwaddr phys_addr; |
b5ff1b31 | 3587 | |
9ee6e8bb PB |
3588 | /* Pagetable walk. */ |
3589 | /* Lookup l1 descriptor. */ | |
e389be16 FA |
3590 | if (!get_level1_table_address(env, &table, address)) { |
3591 | /* Section translation fault if page walk is disabled by PD0 or PD1 */ | |
3592 | code = 5; | |
3593 | goto do_fault; | |
3594 | } | |
fdfba1a2 | 3595 | desc = ldl_phys(cs->as, table); |
9ee6e8bb | 3596 | type = (desc & 3); |
dd4ebc2e JCD |
3597 | domain = (desc >> 5) & 0x0f; |
3598 | domain_prot = (env->cp15.c3 >> (domain * 2)) & 3; | |
9ee6e8bb | 3599 | if (type == 0) { |
601d70b9 | 3600 | /* Section translation fault. */ |
9ee6e8bb PB |
3601 | code = 5; |
3602 | goto do_fault; | |
3603 | } | |
dd4ebc2e | 3604 | if (domain_prot == 0 || domain_prot == 2) { |
9ee6e8bb PB |
3605 | if (type == 2) |
3606 | code = 9; /* Section domain fault. */ | |
3607 | else | |
3608 | code = 11; /* Page domain fault. */ | |
3609 | goto do_fault; | |
3610 | } | |
3611 | if (type == 2) { | |
3612 | /* 1Mb section. */ | |
3613 | phys_addr = (desc & 0xfff00000) | (address & 0x000fffff); | |
3614 | ap = (desc >> 10) & 3; | |
3615 | code = 13; | |
d4c430a8 | 3616 | *page_size = 1024 * 1024; |
9ee6e8bb PB |
3617 | } else { |
3618 | /* Lookup l2 entry. */ | |
3619 | if (type == 1) { | |
3620 | /* Coarse pagetable. */ | |
3621 | table = (desc & 0xfffffc00) | ((address >> 10) & 0x3fc); | |
3622 | } else { | |
3623 | /* Fine pagetable. */ | |
3624 | table = (desc & 0xfffff000) | ((address >> 8) & 0xffc); | |
3625 | } | |
fdfba1a2 | 3626 | desc = ldl_phys(cs->as, table); |
9ee6e8bb PB |
3627 | switch (desc & 3) { |
3628 | case 0: /* Page translation fault. */ | |
3629 | code = 7; | |
3630 | goto do_fault; | |
3631 | case 1: /* 64k page. */ | |
3632 | phys_addr = (desc & 0xffff0000) | (address & 0xffff); | |
3633 | ap = (desc >> (4 + ((address >> 13) & 6))) & 3; | |
d4c430a8 | 3634 | *page_size = 0x10000; |
ce819861 | 3635 | break; |
9ee6e8bb PB |
3636 | case 2: /* 4k page. */ |
3637 | phys_addr = (desc & 0xfffff000) | (address & 0xfff); | |
c10f7fc3 | 3638 | ap = (desc >> (4 + ((address >> 9) & 6))) & 3; |
d4c430a8 | 3639 | *page_size = 0x1000; |
ce819861 | 3640 | break; |
9ee6e8bb PB |
3641 | case 3: /* 1k page. */ |
3642 | if (type == 1) { | |
3643 | if (arm_feature(env, ARM_FEATURE_XSCALE)) { | |
3644 | phys_addr = (desc & 0xfffff000) | (address & 0xfff); | |
3645 | } else { | |
3646 | /* Page translation fault. */ | |
3647 | code = 7; | |
3648 | goto do_fault; | |
3649 | } | |
3650 | } else { | |
3651 | phys_addr = (desc & 0xfffffc00) | (address & 0x3ff); | |
3652 | } | |
3653 | ap = (desc >> 4) & 3; | |
d4c430a8 | 3654 | *page_size = 0x400; |
ce819861 PB |
3655 | break; |
3656 | default: | |
9ee6e8bb PB |
3657 | /* Never happens, but compiler isn't smart enough to tell. */ |
3658 | abort(); | |
ce819861 | 3659 | } |
9ee6e8bb PB |
3660 | code = 15; |
3661 | } | |
dd4ebc2e | 3662 | *prot = check_ap(env, ap, domain_prot, access_type, is_user); |
9ee6e8bb PB |
3663 | if (!*prot) { |
3664 | /* Access permission fault. */ | |
3665 | goto do_fault; | |
3666 | } | |
3ad493fc | 3667 | *prot |= PAGE_EXEC; |
9ee6e8bb PB |
3668 | *phys_ptr = phys_addr; |
3669 | return 0; | |
3670 | do_fault: | |
3671 | return code | (domain << 4); | |
3672 | } | |
3673 | ||
0ecb72a5 | 3674 | static int get_phys_addr_v6(CPUARMState *env, uint32_t address, int access_type, |
a8170e5e | 3675 | int is_user, hwaddr *phys_ptr, |
77a71dd1 | 3676 | int *prot, target_ulong *page_size) |
9ee6e8bb | 3677 | { |
70d74660 | 3678 | CPUState *cs = CPU(arm_env_get_cpu(env)); |
9ee6e8bb PB |
3679 | int code; |
3680 | uint32_t table; | |
3681 | uint32_t desc; | |
3682 | uint32_t xn; | |
de9b05b8 | 3683 | uint32_t pxn = 0; |
9ee6e8bb PB |
3684 | int type; |
3685 | int ap; | |
de9b05b8 | 3686 | int domain = 0; |
dd4ebc2e | 3687 | int domain_prot; |
a8170e5e | 3688 | hwaddr phys_addr; |
9ee6e8bb PB |
3689 | |
3690 | /* Pagetable walk. */ | |
3691 | /* Lookup l1 descriptor. */ | |
e389be16 FA |
3692 | if (!get_level1_table_address(env, &table, address)) { |
3693 | /* Section translation fault if page walk is disabled by PD0 or PD1 */ | |
3694 | code = 5; | |
3695 | goto do_fault; | |
3696 | } | |
fdfba1a2 | 3697 | desc = ldl_phys(cs->as, table); |
9ee6e8bb | 3698 | type = (desc & 3); |
de9b05b8 PM |
3699 | if (type == 0 || (type == 3 && !arm_feature(env, ARM_FEATURE_PXN))) { |
3700 | /* Section translation fault, or attempt to use the encoding | |
3701 | * which is Reserved on implementations without PXN. | |
3702 | */ | |
9ee6e8bb | 3703 | code = 5; |
9ee6e8bb | 3704 | goto do_fault; |
de9b05b8 PM |
3705 | } |
3706 | if ((type == 1) || !(desc & (1 << 18))) { | |
3707 | /* Page or Section. */ | |
dd4ebc2e | 3708 | domain = (desc >> 5) & 0x0f; |
9ee6e8bb | 3709 | } |
dd4ebc2e JCD |
3710 | domain_prot = (env->cp15.c3 >> (domain * 2)) & 3; |
3711 | if (domain_prot == 0 || domain_prot == 2) { | |
de9b05b8 | 3712 | if (type != 1) { |
9ee6e8bb | 3713 | code = 9; /* Section domain fault. */ |
de9b05b8 | 3714 | } else { |
9ee6e8bb | 3715 | code = 11; /* Page domain fault. */ |
de9b05b8 | 3716 | } |
9ee6e8bb PB |
3717 | goto do_fault; |
3718 | } | |
de9b05b8 | 3719 | if (type != 1) { |
9ee6e8bb PB |
3720 | if (desc & (1 << 18)) { |
3721 | /* Supersection. */ | |
3722 | phys_addr = (desc & 0xff000000) | (address & 0x00ffffff); | |
d4c430a8 | 3723 | *page_size = 0x1000000; |
b5ff1b31 | 3724 | } else { |
9ee6e8bb PB |
3725 | /* Section. */ |
3726 | phys_addr = (desc & 0xfff00000) | (address & 0x000fffff); | |
d4c430a8 | 3727 | *page_size = 0x100000; |
b5ff1b31 | 3728 | } |
9ee6e8bb PB |
3729 | ap = ((desc >> 10) & 3) | ((desc >> 13) & 4); |
3730 | xn = desc & (1 << 4); | |
de9b05b8 | 3731 | pxn = desc & 1; |
9ee6e8bb PB |
3732 | code = 13; |
3733 | } else { | |
de9b05b8 PM |
3734 | if (arm_feature(env, ARM_FEATURE_PXN)) { |
3735 | pxn = (desc >> 2) & 1; | |
3736 | } | |
9ee6e8bb PB |
3737 | /* Lookup l2 entry. */ |
3738 | table = (desc & 0xfffffc00) | ((address >> 10) & 0x3fc); | |
fdfba1a2 | 3739 | desc = ldl_phys(cs->as, table); |
9ee6e8bb PB |
3740 | ap = ((desc >> 4) & 3) | ((desc >> 7) & 4); |
3741 | switch (desc & 3) { | |
3742 | case 0: /* Page translation fault. */ | |
3743 | code = 7; | |
b5ff1b31 | 3744 | goto do_fault; |
9ee6e8bb PB |
3745 | case 1: /* 64k page. */ |
3746 | phys_addr = (desc & 0xffff0000) | (address & 0xffff); | |
3747 | xn = desc & (1 << 15); | |
d4c430a8 | 3748 | *page_size = 0x10000; |
9ee6e8bb PB |
3749 | break; |
3750 | case 2: case 3: /* 4k page. */ | |
3751 | phys_addr = (desc & 0xfffff000) | (address & 0xfff); | |
3752 | xn = desc & 1; | |
d4c430a8 | 3753 | *page_size = 0x1000; |
9ee6e8bb PB |
3754 | break; |
3755 | default: | |
3756 | /* Never happens, but compiler isn't smart enough to tell. */ | |
3757 | abort(); | |
b5ff1b31 | 3758 | } |
9ee6e8bb PB |
3759 | code = 15; |
3760 | } | |
dd4ebc2e | 3761 | if (domain_prot == 3) { |
c0034328 JR |
3762 | *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; |
3763 | } else { | |
de9b05b8 PM |
3764 | if (pxn && !is_user) { |
3765 | xn = 1; | |
3766 | } | |
c0034328 JR |
3767 | if (xn && access_type == 2) |
3768 | goto do_fault; | |
9ee6e8bb | 3769 | |
c0034328 | 3770 | /* The simplified model uses AP[0] as an access control bit. */ |
76e3e1bc | 3771 | if ((env->cp15.c1_sys & SCTLR_AFE) && (ap & 1) == 0) { |
c0034328 JR |
3772 | /* Access flag fault. */ |
3773 | code = (code == 15) ? 6 : 3; | |
3774 | goto do_fault; | |
3775 | } | |
dd4ebc2e | 3776 | *prot = check_ap(env, ap, domain_prot, access_type, is_user); |
c0034328 JR |
3777 | if (!*prot) { |
3778 | /* Access permission fault. */ | |
3779 | goto do_fault; | |
3780 | } | |
3781 | if (!xn) { | |
3782 | *prot |= PAGE_EXEC; | |
3783 | } | |
3ad493fc | 3784 | } |
9ee6e8bb | 3785 | *phys_ptr = phys_addr; |
b5ff1b31 FB |
3786 | return 0; |
3787 | do_fault: | |
3788 | return code | (domain << 4); | |
3789 | } | |
3790 | ||
3dde962f PM |
3791 | /* Fault type for long-descriptor MMU fault reporting; this corresponds |
3792 | * to bits [5..2] in the STATUS field in long-format DFSR/IFSR. | |
3793 | */ | |
3794 | typedef enum { | |
3795 | translation_fault = 1, | |
3796 | access_fault = 2, | |
3797 | permission_fault = 3, | |
3798 | } MMUFaultType; | |
3799 | ||
2c8dd318 | 3800 | static int get_phys_addr_lpae(CPUARMState *env, target_ulong address, |
3dde962f | 3801 | int access_type, int is_user, |
a8170e5e | 3802 | hwaddr *phys_ptr, int *prot, |
3dde962f PM |
3803 | target_ulong *page_size_ptr) |
3804 | { | |
70d74660 | 3805 | CPUState *cs = CPU(arm_env_get_cpu(env)); |
3dde962f PM |
3806 | /* Read an LPAE long-descriptor translation table. */ |
3807 | MMUFaultType fault_type = translation_fault; | |
3808 | uint32_t level = 1; | |
3809 | uint32_t epd; | |
2c8dd318 RH |
3810 | int32_t tsz; |
3811 | uint32_t tg; | |
3dde962f PM |
3812 | uint64_t ttbr; |
3813 | int ttbr_select; | |
2c8dd318 | 3814 | hwaddr descaddr, descmask; |
3dde962f PM |
3815 | uint32_t tableattrs; |
3816 | target_ulong page_size; | |
3817 | uint32_t attrs; | |
2c8dd318 RH |
3818 | int32_t granule_sz = 9; |
3819 | int32_t va_size = 32; | |
3820 | int32_t tbi = 0; | |
3821 | ||
3822 | if (arm_el_is_aa64(env, 1)) { | |
3823 | va_size = 64; | |
3824 | if (extract64(address, 55, 1)) | |
3825 | tbi = extract64(env->cp15.c2_control, 38, 1); | |
3826 | else | |
3827 | tbi = extract64(env->cp15.c2_control, 37, 1); | |
3828 | tbi *= 8; | |
3829 | } | |
3dde962f PM |
3830 | |
3831 | /* Determine whether this address is in the region controlled by | |
3832 | * TTBR0 or TTBR1 (or if it is in neither region and should fault). | |
3833 | * This is a Non-secure PL0/1 stage 1 translation, so controlled by | |
3834 | * TTBCR/TTBR0/TTBR1 in accordance with ARM ARM DDI0406C table B-32: | |
3835 | */ | |
2c8dd318 RH |
3836 | uint32_t t0sz = extract32(env->cp15.c2_control, 0, 6); |
3837 | if (arm_el_is_aa64(env, 1)) { | |
3838 | t0sz = MIN(t0sz, 39); | |
3839 | t0sz = MAX(t0sz, 16); | |
3840 | } | |
3841 | uint32_t t1sz = extract32(env->cp15.c2_control, 16, 6); | |
3842 | if (arm_el_is_aa64(env, 1)) { | |
3843 | t1sz = MIN(t1sz, 39); | |
3844 | t1sz = MAX(t1sz, 16); | |
3845 | } | |
3846 | if (t0sz && !extract64(address, va_size - t0sz, t0sz - tbi)) { | |
3dde962f PM |
3847 | /* there is a ttbr0 region and we are in it (high bits all zero) */ |
3848 | ttbr_select = 0; | |
2c8dd318 | 3849 | } else if (t1sz && !extract64(~address, va_size - t1sz, t1sz - tbi)) { |
3dde962f PM |
3850 | /* there is a ttbr1 region and we are in it (high bits all one) */ |
3851 | ttbr_select = 1; | |
3852 | } else if (!t0sz) { | |
3853 | /* ttbr0 region is "everything not in the ttbr1 region" */ | |
3854 | ttbr_select = 0; | |
3855 | } else if (!t1sz) { | |
3856 | /* ttbr1 region is "everything not in the ttbr0 region" */ | |
3857 | ttbr_select = 1; | |
3858 | } else { | |
3859 | /* in the gap between the two regions, this is a Translation fault */ | |
3860 | fault_type = translation_fault; | |
3861 | goto do_fault; | |
3862 | } | |
3863 | ||
3864 | /* Note that QEMU ignores shareability and cacheability attributes, | |
3865 | * so we don't need to do anything with the SH, ORGN, IRGN fields | |
3866 | * in the TTBCR. Similarly, TTBCR:A1 selects whether we get the | |
3867 | * ASID from TTBR0 or TTBR1, but QEMU's TLB doesn't currently | |
3868 | * implement any ASID-like capability so we can ignore it (instead | |
3869 | * we will always flush the TLB any time the ASID is changed). | |
3870 | */ | |
3871 | if (ttbr_select == 0) { | |
327ed10f | 3872 | ttbr = env->cp15.ttbr0_el1; |
3dde962f PM |
3873 | epd = extract32(env->cp15.c2_control, 7, 1); |
3874 | tsz = t0sz; | |
2c8dd318 RH |
3875 | |
3876 | tg = extract32(env->cp15.c2_control, 14, 2); | |
3877 | if (tg == 1) { /* 64KB pages */ | |
3878 | granule_sz = 13; | |
3879 | } | |
3880 | if (tg == 2) { /* 16KB pages */ | |
3881 | granule_sz = 11; | |
3882 | } | |
3dde962f | 3883 | } else { |
327ed10f | 3884 | ttbr = env->cp15.ttbr1_el1; |
3dde962f PM |
3885 | epd = extract32(env->cp15.c2_control, 23, 1); |
3886 | tsz = t1sz; | |
2c8dd318 RH |
3887 | |
3888 | tg = extract32(env->cp15.c2_control, 30, 2); | |
3889 | if (tg == 3) { /* 64KB pages */ | |
3890 | granule_sz = 13; | |
3891 | } | |
3892 | if (tg == 1) { /* 16KB pages */ | |
3893 | granule_sz = 11; | |
3894 | } | |
3dde962f PM |
3895 | } |
3896 | ||
3897 | if (epd) { | |
3898 | /* Translation table walk disabled => Translation fault on TLB miss */ | |
3899 | goto do_fault; | |
3900 | } | |
3901 | ||
2c8dd318 RH |
3902 | /* The starting level depends on the virtual address size which can be |
3903 | * up to 48-bits and the translation granule size. | |
3dde962f | 3904 | */ |
2c8dd318 RH |
3905 | if ((va_size - tsz) > (granule_sz * 4 + 3)) { |
3906 | level = 0; | |
3907 | } else if ((va_size - tsz) > (granule_sz * 3 + 3)) { | |
3908 | level = 1; | |
3dde962f | 3909 | } else { |
2c8dd318 | 3910 | level = 2; |
3dde962f PM |
3911 | } |
3912 | ||
3913 | /* Clear the vaddr bits which aren't part of the within-region address, | |
3914 | * so that we don't have to special case things when calculating the | |
3915 | * first descriptor address. | |
3916 | */ | |
2c8dd318 RH |
3917 | if (tsz) { |
3918 | address &= (1ULL << (va_size - tsz)) - 1; | |
3919 | } | |
3920 | ||
3921 | descmask = (1ULL << (granule_sz + 3)) - 1; | |
3dde962f PM |
3922 | |
3923 | /* Now we can extract the actual base address from the TTBR */ | |
2c8dd318 RH |
3924 | descaddr = extract64(ttbr, 0, 48); |
3925 | descaddr &= ~((1ULL << (va_size - tsz - (granule_sz * (4 - level)))) - 1); | |
3dde962f PM |
3926 | |
3927 | tableattrs = 0; | |
3928 | for (;;) { | |
3929 | uint64_t descriptor; | |
3930 | ||
2c8dd318 RH |
3931 | descaddr |= (address >> (granule_sz * (4 - level))) & descmask; |
3932 | descaddr &= ~7ULL; | |
2c17449b | 3933 | descriptor = ldq_phys(cs->as, descaddr); |
3dde962f PM |
3934 | if (!(descriptor & 1) || |
3935 | (!(descriptor & 2) && (level == 3))) { | |
3936 | /* Invalid, or the Reserved level 3 encoding */ | |
3937 | goto do_fault; | |
3938 | } | |
3939 | descaddr = descriptor & 0xfffffff000ULL; | |
3940 | ||
3941 | if ((descriptor & 2) && (level < 3)) { | |
3942 | /* Table entry. The top five bits are attributes which may | |
3943 | * propagate down through lower levels of the table (and | |
3944 | * which are all arranged so that 0 means "no effect", so | |
3945 | * we can gather them up by ORing in the bits at each level). | |
3946 | */ | |
3947 | tableattrs |= extract64(descriptor, 59, 5); | |
3948 | level++; | |
3949 | continue; | |
3950 | } | |
3951 | /* Block entry at level 1 or 2, or page entry at level 3. | |
3952 | * These are basically the same thing, although the number | |
3953 | * of bits we pull in from the vaddr varies. | |
3954 | */ | |
5661ae6b | 3955 | page_size = (1ULL << ((granule_sz * (4 - level)) + 3)); |
3dde962f PM |
3956 | descaddr |= (address & (page_size - 1)); |
3957 | /* Extract attributes from the descriptor and merge with table attrs */ | |
d615efac IC |
3958 | attrs = extract64(descriptor, 2, 10) |
3959 | | (extract64(descriptor, 52, 12) << 10); | |
3dde962f PM |
3960 | attrs |= extract32(tableattrs, 0, 2) << 11; /* XN, PXN */ |
3961 | attrs |= extract32(tableattrs, 3, 1) << 5; /* APTable[1] => AP[2] */ | |
3962 | /* The sense of AP[1] vs APTable[0] is reversed, as APTable[0] == 1 | |
3963 | * means "force PL1 access only", which means forcing AP[1] to 0. | |
3964 | */ | |
3965 | if (extract32(tableattrs, 2, 1)) { | |
3966 | attrs &= ~(1 << 4); | |
3967 | } | |
3968 | /* Since we're always in the Non-secure state, NSTable is ignored. */ | |
3969 | break; | |
3970 | } | |
3971 | /* Here descaddr is the final physical address, and attributes | |
3972 | * are all in attrs. | |
3973 | */ | |
3974 | fault_type = access_fault; | |
3975 | if ((attrs & (1 << 8)) == 0) { | |
3976 | /* Access flag */ | |
3977 | goto do_fault; | |
3978 | } | |
3979 | fault_type = permission_fault; | |
3980 | if (is_user && !(attrs & (1 << 4))) { | |
3981 | /* Unprivileged access not enabled */ | |
3982 | goto do_fault; | |
3983 | } | |
3984 | *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; | |
d615efac IC |
3985 | if ((arm_feature(env, ARM_FEATURE_V8) && is_user && (attrs & (1 << 12))) || |
3986 | (!arm_feature(env, ARM_FEATURE_V8) && (attrs & (1 << 12))) || | |
3987 | (!is_user && (attrs & (1 << 11)))) { | |
3988 | /* XN/UXN or PXN. Since we only implement EL0/EL1 we unconditionally | |
3989 | * treat XN/UXN as UXN for v8. | |
3990 | */ | |
3dde962f PM |
3991 | if (access_type == 2) { |
3992 | goto do_fault; | |
3993 | } | |
3994 | *prot &= ~PAGE_EXEC; | |
3995 | } | |
3996 | if (attrs & (1 << 5)) { | |
3997 | /* Write access forbidden */ | |
3998 | if (access_type == 1) { | |
3999 | goto do_fault; | |
4000 | } | |
4001 | *prot &= ~PAGE_WRITE; | |
4002 | } | |
4003 | ||
4004 | *phys_ptr = descaddr; | |
4005 | *page_size_ptr = page_size; | |
4006 | return 0; | |
4007 | ||
4008 | do_fault: | |
4009 | /* Long-descriptor format IFSR/DFSR value */ | |
4010 | return (1 << 9) | (fault_type << 2) | level; | |
4011 | } | |
4012 | ||
77a71dd1 PM |
4013 | static int get_phys_addr_mpu(CPUARMState *env, uint32_t address, |
4014 | int access_type, int is_user, | |
a8170e5e | 4015 | hwaddr *phys_ptr, int *prot) |
9ee6e8bb PB |
4016 | { |
4017 | int n; | |
4018 | uint32_t mask; | |
4019 | uint32_t base; | |
4020 | ||
4021 | *phys_ptr = address; | |
4022 | for (n = 7; n >= 0; n--) { | |
4023 | base = env->cp15.c6_region[n]; | |
4024 | if ((base & 1) == 0) | |
4025 | continue; | |
4026 | mask = 1 << ((base >> 1) & 0x1f); | |
4027 | /* Keep this shift separate from the above to avoid an | |
4028 | (undefined) << 32. */ | |
4029 | mask = (mask << 1) - 1; | |
4030 | if (((base ^ address) & ~mask) == 0) | |
4031 | break; | |
4032 | } | |
4033 | if (n < 0) | |
4034 | return 2; | |
4035 | ||
4036 | if (access_type == 2) { | |
7e09797c | 4037 | mask = env->cp15.pmsav5_insn_ap; |
9ee6e8bb | 4038 | } else { |
7e09797c | 4039 | mask = env->cp15.pmsav5_data_ap; |
9ee6e8bb PB |
4040 | } |
4041 | mask = (mask >> (n * 4)) & 0xf; | |
4042 | switch (mask) { | |
4043 | case 0: | |
4044 | return 1; | |
4045 | case 1: | |
4046 | if (is_user) | |
4047 | return 1; | |
4048 | *prot = PAGE_READ | PAGE_WRITE; | |
4049 | break; | |
4050 | case 2: | |
4051 | *prot = PAGE_READ; | |
4052 | if (!is_user) | |
4053 | *prot |= PAGE_WRITE; | |
4054 | break; | |
4055 | case 3: | |
4056 | *prot = PAGE_READ | PAGE_WRITE; | |
4057 | break; | |
4058 | case 5: | |
4059 | if (is_user) | |
4060 | return 1; | |
4061 | *prot = PAGE_READ; | |
4062 | break; | |
4063 | case 6: | |
4064 | *prot = PAGE_READ; | |
4065 | break; | |
4066 | default: | |
4067 | /* Bad permission. */ | |
4068 | return 1; | |
4069 | } | |
3ad493fc | 4070 | *prot |= PAGE_EXEC; |
9ee6e8bb PB |
4071 | return 0; |
4072 | } | |
4073 | ||
702a9357 PM |
4074 | /* get_phys_addr - get the physical address for this virtual address |
4075 | * | |
4076 | * Find the physical address corresponding to the given virtual address, | |
4077 | * by doing a translation table walk on MMU based systems or using the | |
4078 | * MPU state on MPU based systems. | |
4079 | * | |
4080 | * Returns 0 if the translation was successful. Otherwise, phys_ptr, | |
4081 | * prot and page_size are not filled in, and the return value provides | |
4082 | * information on why the translation aborted, in the format of a | |
4083 | * DFSR/IFSR fault register, with the following caveats: | |
4084 | * * we honour the short vs long DFSR format differences. | |
4085 | * * the WnR bit is never set (the caller must do this). | |
4086 | * * for MPU based systems we don't bother to return a full FSR format | |
4087 | * value. | |
4088 | * | |
4089 | * @env: CPUARMState | |
4090 | * @address: virtual address to get physical address for | |
4091 | * @access_type: 0 for read, 1 for write, 2 for execute | |
4092 | * @is_user: 0 for privileged access, 1 for user | |
4093 | * @phys_ptr: set to the physical address corresponding to the virtual address | |
4094 | * @prot: set to the permissions for the page containing phys_ptr | |
4095 | * @page_size: set to the size of the page containing phys_ptr | |
4096 | */ | |
2c8dd318 | 4097 | static inline int get_phys_addr(CPUARMState *env, target_ulong address, |
9ee6e8bb | 4098 | int access_type, int is_user, |
a8170e5e | 4099 | hwaddr *phys_ptr, int *prot, |
d4c430a8 | 4100 | target_ulong *page_size) |
9ee6e8bb PB |
4101 | { |
4102 | /* Fast Context Switch Extension. */ | |
4103 | if (address < 0x02000000) | |
4104 | address += env->cp15.c13_fcse; | |
4105 | ||
76e3e1bc | 4106 | if ((env->cp15.c1_sys & SCTLR_M) == 0) { |
9ee6e8bb PB |
4107 | /* MMU/MPU disabled. */ |
4108 | *phys_ptr = address; | |
3ad493fc | 4109 | *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; |
d4c430a8 | 4110 | *page_size = TARGET_PAGE_SIZE; |
9ee6e8bb PB |
4111 | return 0; |
4112 | } else if (arm_feature(env, ARM_FEATURE_MPU)) { | |
d4c430a8 | 4113 | *page_size = TARGET_PAGE_SIZE; |
9ee6e8bb PB |
4114 | return get_phys_addr_mpu(env, address, access_type, is_user, phys_ptr, |
4115 | prot); | |
3dde962f PM |
4116 | } else if (extended_addresses_enabled(env)) { |
4117 | return get_phys_addr_lpae(env, address, access_type, is_user, phys_ptr, | |
4118 | prot, page_size); | |
76e3e1bc | 4119 | } else if (env->cp15.c1_sys & SCTLR_XP) { |
9ee6e8bb | 4120 | return get_phys_addr_v6(env, address, access_type, is_user, phys_ptr, |
d4c430a8 | 4121 | prot, page_size); |
9ee6e8bb PB |
4122 | } else { |
4123 | return get_phys_addr_v5(env, address, access_type, is_user, phys_ptr, | |
d4c430a8 | 4124 | prot, page_size); |
9ee6e8bb PB |
4125 | } |
4126 | } | |
4127 | ||
7510454e AF |
4128 | int arm_cpu_handle_mmu_fault(CPUState *cs, vaddr address, |
4129 | int access_type, int mmu_idx) | |
b5ff1b31 | 4130 | { |
7510454e AF |
4131 | ARMCPU *cpu = ARM_CPU(cs); |
4132 | CPUARMState *env = &cpu->env; | |
a8170e5e | 4133 | hwaddr phys_addr; |
d4c430a8 | 4134 | target_ulong page_size; |
b5ff1b31 | 4135 | int prot; |
6ebbf390 | 4136 | int ret, is_user; |
00892383 RH |
4137 | uint32_t syn; |
4138 | bool same_el = (arm_current_pl(env) != 0); | |
b5ff1b31 | 4139 | |
6ebbf390 | 4140 | is_user = mmu_idx == MMU_USER_IDX; |
d4c430a8 PB |
4141 | ret = get_phys_addr(env, address, access_type, is_user, &phys_addr, &prot, |
4142 | &page_size); | |
b5ff1b31 FB |
4143 | if (ret == 0) { |
4144 | /* Map a single [sub]page. */ | |
a8170e5e | 4145 | phys_addr &= ~(hwaddr)0x3ff; |
2c8dd318 | 4146 | address &= ~(target_ulong)0x3ff; |
0c591eb0 | 4147 | tlb_set_page(cs, address, phys_addr, prot, mmu_idx, page_size); |
d4c430a8 | 4148 | return 0; |
b5ff1b31 FB |
4149 | } |
4150 | ||
00892383 RH |
4151 | /* AArch64 syndrome does not have an LPAE bit */ |
4152 | syn = ret & ~(1 << 9); | |
4153 | ||
4154 | /* For insn and data aborts we assume there is no instruction syndrome | |
4155 | * information; this is always true for exceptions reported to EL1. | |
4156 | */ | |
b5ff1b31 | 4157 | if (access_type == 2) { |
00892383 | 4158 | syn = syn_insn_abort(same_el, 0, 0, syn); |
27103424 | 4159 | cs->exception_index = EXCP_PREFETCH_ABORT; |
b5ff1b31 | 4160 | } else { |
00892383 | 4161 | syn = syn_data_abort(same_el, 0, 0, 0, access_type == 1, syn); |
abf1172f PM |
4162 | if (access_type == 1 && arm_feature(env, ARM_FEATURE_V6)) { |
4163 | ret |= (1 << 11); | |
4164 | } | |
27103424 | 4165 | cs->exception_index = EXCP_DATA_ABORT; |
b5ff1b31 | 4166 | } |
00892383 RH |
4167 | |
4168 | env->exception.syndrome = syn; | |
abf1172f PM |
4169 | env->exception.vaddress = address; |
4170 | env->exception.fsr = ret; | |
b5ff1b31 FB |
4171 | return 1; |
4172 | } | |
4173 | ||
00b941e5 | 4174 | hwaddr arm_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) |
b5ff1b31 | 4175 | { |
00b941e5 | 4176 | ARMCPU *cpu = ARM_CPU(cs); |
a8170e5e | 4177 | hwaddr phys_addr; |
d4c430a8 | 4178 | target_ulong page_size; |
b5ff1b31 FB |
4179 | int prot; |
4180 | int ret; | |
4181 | ||
00b941e5 | 4182 | ret = get_phys_addr(&cpu->env, addr, 0, 0, &phys_addr, &prot, &page_size); |
b5ff1b31 | 4183 | |
00b941e5 | 4184 | if (ret != 0) { |
b5ff1b31 | 4185 | return -1; |
00b941e5 | 4186 | } |
b5ff1b31 FB |
4187 | |
4188 | return phys_addr; | |
4189 | } | |
4190 | ||
0ecb72a5 | 4191 | void HELPER(set_r13_banked)(CPUARMState *env, uint32_t mode, uint32_t val) |
9ee6e8bb | 4192 | { |
39ea3d4e PM |
4193 | if ((env->uncached_cpsr & CPSR_M) == mode) { |
4194 | env->regs[13] = val; | |
4195 | } else { | |
f5206413 | 4196 | env->banked_r13[bank_number(mode)] = val; |
39ea3d4e | 4197 | } |
9ee6e8bb PB |
4198 | } |
4199 | ||
0ecb72a5 | 4200 | uint32_t HELPER(get_r13_banked)(CPUARMState *env, uint32_t mode) |
9ee6e8bb | 4201 | { |
39ea3d4e PM |
4202 | if ((env->uncached_cpsr & CPSR_M) == mode) { |
4203 | return env->regs[13]; | |
4204 | } else { | |
f5206413 | 4205 | return env->banked_r13[bank_number(mode)]; |
39ea3d4e | 4206 | } |
9ee6e8bb PB |
4207 | } |
4208 | ||
0ecb72a5 | 4209 | uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg) |
9ee6e8bb | 4210 | { |
a47dddd7 AF |
4211 | ARMCPU *cpu = arm_env_get_cpu(env); |
4212 | ||
9ee6e8bb PB |
4213 | switch (reg) { |
4214 | case 0: /* APSR */ | |
4215 | return xpsr_read(env) & 0xf8000000; | |
4216 | case 1: /* IAPSR */ | |
4217 | return xpsr_read(env) & 0xf80001ff; | |
4218 | case 2: /* EAPSR */ | |
4219 | return xpsr_read(env) & 0xff00fc00; | |
4220 | case 3: /* xPSR */ | |
4221 | return xpsr_read(env) & 0xff00fdff; | |
4222 | case 5: /* IPSR */ | |
4223 | return xpsr_read(env) & 0x000001ff; | |
4224 | case 6: /* EPSR */ | |
4225 | return xpsr_read(env) & 0x0700fc00; | |
4226 | case 7: /* IEPSR */ | |
4227 | return xpsr_read(env) & 0x0700edff; | |
4228 | case 8: /* MSP */ | |
4229 | return env->v7m.current_sp ? env->v7m.other_sp : env->regs[13]; | |
4230 | case 9: /* PSP */ | |
4231 | return env->v7m.current_sp ? env->regs[13] : env->v7m.other_sp; | |
4232 | case 16: /* PRIMASK */ | |
4cc35614 | 4233 | return (env->daif & PSTATE_I) != 0; |
82845826 SH |
4234 | case 17: /* BASEPRI */ |
4235 | case 18: /* BASEPRI_MAX */ | |
9ee6e8bb | 4236 | return env->v7m.basepri; |
82845826 | 4237 | case 19: /* FAULTMASK */ |
4cc35614 | 4238 | return (env->daif & PSTATE_F) != 0; |
9ee6e8bb PB |
4239 | case 20: /* CONTROL */ |
4240 | return env->v7m.control; | |
4241 | default: | |
4242 | /* ??? For debugging only. */ | |
a47dddd7 | 4243 | cpu_abort(CPU(cpu), "Unimplemented system register read (%d)\n", reg); |
9ee6e8bb PB |
4244 | return 0; |
4245 | } | |
4246 | } | |
4247 | ||
0ecb72a5 | 4248 | void HELPER(v7m_msr)(CPUARMState *env, uint32_t reg, uint32_t val) |
9ee6e8bb | 4249 | { |
a47dddd7 AF |
4250 | ARMCPU *cpu = arm_env_get_cpu(env); |
4251 | ||
9ee6e8bb PB |
4252 | switch (reg) { |
4253 | case 0: /* APSR */ | |
4254 | xpsr_write(env, val, 0xf8000000); | |
4255 | break; | |
4256 | case 1: /* IAPSR */ | |
4257 | xpsr_write(env, val, 0xf8000000); | |
4258 | break; | |
4259 | case 2: /* EAPSR */ | |
4260 | xpsr_write(env, val, 0xfe00fc00); | |
4261 | break; | |
4262 | case 3: /* xPSR */ | |
4263 | xpsr_write(env, val, 0xfe00fc00); | |
4264 | break; | |
4265 | case 5: /* IPSR */ | |
4266 | /* IPSR bits are readonly. */ | |
4267 | break; | |
4268 | case 6: /* EPSR */ | |
4269 | xpsr_write(env, val, 0x0600fc00); | |
4270 | break; | |
4271 | case 7: /* IEPSR */ | |
4272 | xpsr_write(env, val, 0x0600fc00); | |
4273 | break; | |
4274 | case 8: /* MSP */ | |
4275 | if (env->v7m.current_sp) | |
4276 | env->v7m.other_sp = val; | |
4277 | else | |
4278 | env->regs[13] = val; | |
4279 | break; | |
4280 | case 9: /* PSP */ | |
4281 | if (env->v7m.current_sp) | |
4282 | env->regs[13] = val; | |
4283 | else | |
4284 | env->v7m.other_sp = val; | |
4285 | break; | |
4286 | case 16: /* PRIMASK */ | |
4cc35614 PM |
4287 | if (val & 1) { |
4288 | env->daif |= PSTATE_I; | |
4289 | } else { | |
4290 | env->daif &= ~PSTATE_I; | |
4291 | } | |
9ee6e8bb | 4292 | break; |
82845826 | 4293 | case 17: /* BASEPRI */ |
9ee6e8bb PB |
4294 | env->v7m.basepri = val & 0xff; |
4295 | break; | |
82845826 | 4296 | case 18: /* BASEPRI_MAX */ |
9ee6e8bb PB |
4297 | val &= 0xff; |
4298 | if (val != 0 && (val < env->v7m.basepri || env->v7m.basepri == 0)) | |
4299 | env->v7m.basepri = val; | |
4300 | break; | |
82845826 | 4301 | case 19: /* FAULTMASK */ |
4cc35614 PM |
4302 | if (val & 1) { |
4303 | env->daif |= PSTATE_F; | |
4304 | } else { | |
4305 | env->daif &= ~PSTATE_F; | |
4306 | } | |
82845826 | 4307 | break; |
9ee6e8bb PB |
4308 | case 20: /* CONTROL */ |
4309 | env->v7m.control = val & 3; | |
4310 | switch_v7m_sp(env, (val & 2) != 0); | |
4311 | break; | |
4312 | default: | |
4313 | /* ??? For debugging only. */ | |
a47dddd7 | 4314 | cpu_abort(CPU(cpu), "Unimplemented system register write (%d)\n", reg); |
9ee6e8bb PB |
4315 | return; |
4316 | } | |
4317 | } | |
4318 | ||
b5ff1b31 | 4319 | #endif |
6ddbc6e4 | 4320 | |
aca3f40b PM |
4321 | void HELPER(dc_zva)(CPUARMState *env, uint64_t vaddr_in) |
4322 | { | |
4323 | /* Implement DC ZVA, which zeroes a fixed-length block of memory. | |
4324 | * Note that we do not implement the (architecturally mandated) | |
4325 | * alignment fault for attempts to use this on Device memory | |
4326 | * (which matches the usual QEMU behaviour of not implementing either | |
4327 | * alignment faults or any memory attribute handling). | |
4328 | */ | |
4329 | ||
4330 | ARMCPU *cpu = arm_env_get_cpu(env); | |
4331 | uint64_t blocklen = 4 << cpu->dcz_blocksize; | |
4332 | uint64_t vaddr = vaddr_in & ~(blocklen - 1); | |
4333 | ||
4334 | #ifndef CONFIG_USER_ONLY | |
4335 | { | |
4336 | /* Slightly awkwardly, QEMU's TARGET_PAGE_SIZE may be less than | |
4337 | * the block size so we might have to do more than one TLB lookup. | |
4338 | * We know that in fact for any v8 CPU the page size is at least 4K | |
4339 | * and the block size must be 2K or less, but TARGET_PAGE_SIZE is only | |
4340 | * 1K as an artefact of legacy v5 subpage support being present in the | |
4341 | * same QEMU executable. | |
4342 | */ | |
4343 | int maxidx = DIV_ROUND_UP(blocklen, TARGET_PAGE_SIZE); | |
4344 | void *hostaddr[maxidx]; | |
4345 | int try, i; | |
4346 | ||
4347 | for (try = 0; try < 2; try++) { | |
4348 | ||
4349 | for (i = 0; i < maxidx; i++) { | |
4350 | hostaddr[i] = tlb_vaddr_to_host(env, | |
4351 | vaddr + TARGET_PAGE_SIZE * i, | |
4352 | 1, cpu_mmu_index(env)); | |
4353 | if (!hostaddr[i]) { | |
4354 | break; | |
4355 | } | |
4356 | } | |
4357 | if (i == maxidx) { | |
4358 | /* If it's all in the TLB it's fair game for just writing to; | |
4359 | * we know we don't need to update dirty status, etc. | |
4360 | */ | |
4361 | for (i = 0; i < maxidx - 1; i++) { | |
4362 | memset(hostaddr[i], 0, TARGET_PAGE_SIZE); | |
4363 | } | |
4364 | memset(hostaddr[i], 0, blocklen - (i * TARGET_PAGE_SIZE)); | |
4365 | return; | |
4366 | } | |
4367 | /* OK, try a store and see if we can populate the tlb. This | |
4368 | * might cause an exception if the memory isn't writable, | |
4369 | * in which case we will longjmp out of here. We must for | |
4370 | * this purpose use the actual register value passed to us | |
4371 | * so that we get the fault address right. | |
4372 | */ | |
4373 | helper_ret_stb_mmu(env, vaddr_in, 0, cpu_mmu_index(env), GETRA()); | |
4374 | /* Now we can populate the other TLB entries, if any */ | |
4375 | for (i = 0; i < maxidx; i++) { | |
4376 | uint64_t va = vaddr + TARGET_PAGE_SIZE * i; | |
4377 | if (va != (vaddr_in & TARGET_PAGE_MASK)) { | |
4378 | helper_ret_stb_mmu(env, va, 0, cpu_mmu_index(env), GETRA()); | |
4379 | } | |
4380 | } | |
4381 | } | |
4382 | ||
4383 | /* Slow path (probably attempt to do this to an I/O device or | |
4384 | * similar, or clearing of a block of code we have translations | |
4385 | * cached for). Just do a series of byte writes as the architecture | |
4386 | * demands. It's not worth trying to use a cpu_physical_memory_map(), | |
4387 | * memset(), unmap() sequence here because: | |
4388 | * + we'd need to account for the blocksize being larger than a page | |
4389 | * + the direct-RAM access case is almost always going to be dealt | |
4390 | * with in the fastpath code above, so there's no speed benefit | |
4391 | * + we would have to deal with the map returning NULL because the | |
4392 | * bounce buffer was in use | |
4393 | */ | |
4394 | for (i = 0; i < blocklen; i++) { | |
4395 | helper_ret_stb_mmu(env, vaddr + i, 0, cpu_mmu_index(env), GETRA()); | |
4396 | } | |
4397 | } | |
4398 | #else | |
4399 | memset(g2h(vaddr), 0, blocklen); | |
4400 | #endif | |
4401 | } | |
4402 | ||
6ddbc6e4 PB |
4403 | /* Note that signed overflow is undefined in C. The following routines are |
4404 | careful to use unsigned types where modulo arithmetic is required. | |
4405 | Failure to do so _will_ break on newer gcc. */ | |
4406 | ||
4407 | /* Signed saturating arithmetic. */ | |
4408 | ||
1654b2d6 | 4409 | /* Perform 16-bit signed saturating addition. */ |
6ddbc6e4 PB |
4410 | static inline uint16_t add16_sat(uint16_t a, uint16_t b) |
4411 | { | |
4412 | uint16_t res; | |
4413 | ||
4414 | res = a + b; | |
4415 | if (((res ^ a) & 0x8000) && !((a ^ b) & 0x8000)) { | |
4416 | if (a & 0x8000) | |
4417 | res = 0x8000; | |
4418 | else | |
4419 | res = 0x7fff; | |
4420 | } | |
4421 | return res; | |
4422 | } | |
4423 | ||
1654b2d6 | 4424 | /* Perform 8-bit signed saturating addition. */ |
6ddbc6e4 PB |
4425 | static inline uint8_t add8_sat(uint8_t a, uint8_t b) |
4426 | { | |
4427 | uint8_t res; | |
4428 | ||
4429 | res = a + b; | |
4430 | if (((res ^ a) & 0x80) && !((a ^ b) & 0x80)) { | |
4431 | if (a & 0x80) | |
4432 | res = 0x80; | |
4433 | else | |
4434 | res = 0x7f; | |
4435 | } | |
4436 | return res; | |
4437 | } | |
4438 | ||
1654b2d6 | 4439 | /* Perform 16-bit signed saturating subtraction. */ |
6ddbc6e4 PB |
4440 | static inline uint16_t sub16_sat(uint16_t a, uint16_t b) |
4441 | { | |
4442 | uint16_t res; | |
4443 | ||
4444 | res = a - b; | |
4445 | if (((res ^ a) & 0x8000) && ((a ^ b) & 0x8000)) { | |
4446 | if (a & 0x8000) | |
4447 | res = 0x8000; | |
4448 | else | |
4449 | res = 0x7fff; | |
4450 | } | |
4451 | return res; | |
4452 | } | |
4453 | ||
1654b2d6 | 4454 | /* Perform 8-bit signed saturating subtraction. */ |
6ddbc6e4 PB |
4455 | static inline uint8_t sub8_sat(uint8_t a, uint8_t b) |
4456 | { | |
4457 | uint8_t res; | |
4458 | ||
4459 | res = a - b; | |
4460 | if (((res ^ a) & 0x80) && ((a ^ b) & 0x80)) { | |
4461 | if (a & 0x80) | |
4462 | res = 0x80; | |
4463 | else | |
4464 | res = 0x7f; | |
4465 | } | |
4466 | return res; | |
4467 | } | |
4468 | ||
4469 | #define ADD16(a, b, n) RESULT(add16_sat(a, b), n, 16); | |
4470 | #define SUB16(a, b, n) RESULT(sub16_sat(a, b), n, 16); | |
4471 | #define ADD8(a, b, n) RESULT(add8_sat(a, b), n, 8); | |
4472 | #define SUB8(a, b, n) RESULT(sub8_sat(a, b), n, 8); | |
4473 | #define PFX q | |
4474 | ||
4475 | #include "op_addsub.h" | |
4476 | ||
4477 | /* Unsigned saturating arithmetic. */ | |
460a09c1 | 4478 | static inline uint16_t add16_usat(uint16_t a, uint16_t b) |
6ddbc6e4 PB |
4479 | { |
4480 | uint16_t res; | |
4481 | res = a + b; | |
4482 | if (res < a) | |
4483 | res = 0xffff; | |
4484 | return res; | |
4485 | } | |
4486 | ||
460a09c1 | 4487 | static inline uint16_t sub16_usat(uint16_t a, uint16_t b) |
6ddbc6e4 | 4488 | { |
4c4fd3f8 | 4489 | if (a > b) |
6ddbc6e4 PB |
4490 | return a - b; |
4491 | else | |
4492 | return 0; | |
4493 | } | |
4494 | ||
4495 | static inline uint8_t add8_usat(uint8_t a, uint8_t b) | |
4496 | { | |
4497 | uint8_t res; | |
4498 | res = a + b; | |
4499 | if (res < a) | |
4500 | res = 0xff; | |
4501 | return res; | |
4502 | } | |
4503 | ||
4504 | static inline uint8_t sub8_usat(uint8_t a, uint8_t b) | |
4505 | { | |
4c4fd3f8 | 4506 | if (a > b) |
6ddbc6e4 PB |
4507 | return a - b; |
4508 | else | |
4509 | return 0; | |
4510 | } | |
4511 | ||
4512 | #define ADD16(a, b, n) RESULT(add16_usat(a, b), n, 16); | |
4513 | #define SUB16(a, b, n) RESULT(sub16_usat(a, b), n, 16); | |
4514 | #define ADD8(a, b, n) RESULT(add8_usat(a, b), n, 8); | |
4515 | #define SUB8(a, b, n) RESULT(sub8_usat(a, b), n, 8); | |
4516 | #define PFX uq | |
4517 | ||
4518 | #include "op_addsub.h" | |
4519 | ||
4520 | /* Signed modulo arithmetic. */ | |
4521 | #define SARITH16(a, b, n, op) do { \ | |
4522 | int32_t sum; \ | |
db6e2e65 | 4523 | sum = (int32_t)(int16_t)(a) op (int32_t)(int16_t)(b); \ |
6ddbc6e4 PB |
4524 | RESULT(sum, n, 16); \ |
4525 | if (sum >= 0) \ | |
4526 | ge |= 3 << (n * 2); \ | |
4527 | } while(0) | |
4528 | ||
4529 | #define SARITH8(a, b, n, op) do { \ | |
4530 | int32_t sum; \ | |
db6e2e65 | 4531 | sum = (int32_t)(int8_t)(a) op (int32_t)(int8_t)(b); \ |
6ddbc6e4 PB |
4532 | RESULT(sum, n, 8); \ |
4533 | if (sum >= 0) \ | |
4534 | ge |= 1 << n; \ | |
4535 | } while(0) | |
4536 | ||
4537 | ||
4538 | #define ADD16(a, b, n) SARITH16(a, b, n, +) | |
4539 | #define SUB16(a, b, n) SARITH16(a, b, n, -) | |
4540 | #define ADD8(a, b, n) SARITH8(a, b, n, +) | |
4541 | #define SUB8(a, b, n) SARITH8(a, b, n, -) | |
4542 | #define PFX s | |
4543 | #define ARITH_GE | |
4544 | ||
4545 | #include "op_addsub.h" | |
4546 | ||
4547 | /* Unsigned modulo arithmetic. */ | |
4548 | #define ADD16(a, b, n) do { \ | |
4549 | uint32_t sum; \ | |
4550 | sum = (uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b); \ | |
4551 | RESULT(sum, n, 16); \ | |
a87aa10b | 4552 | if ((sum >> 16) == 1) \ |
6ddbc6e4 PB |
4553 | ge |= 3 << (n * 2); \ |
4554 | } while(0) | |
4555 | ||
4556 | #define ADD8(a, b, n) do { \ | |
4557 | uint32_t sum; \ | |
4558 | sum = (uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b); \ | |
4559 | RESULT(sum, n, 8); \ | |
a87aa10b AZ |
4560 | if ((sum >> 8) == 1) \ |
4561 | ge |= 1 << n; \ | |
6ddbc6e4 PB |
4562 | } while(0) |
4563 | ||
4564 | #define SUB16(a, b, n) do { \ | |
4565 | uint32_t sum; \ | |
4566 | sum = (uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b); \ | |
4567 | RESULT(sum, n, 16); \ | |
4568 | if ((sum >> 16) == 0) \ | |
4569 | ge |= 3 << (n * 2); \ | |
4570 | } while(0) | |
4571 | ||
4572 | #define SUB8(a, b, n) do { \ | |
4573 | uint32_t sum; \ | |
4574 | sum = (uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b); \ | |
4575 | RESULT(sum, n, 8); \ | |
4576 | if ((sum >> 8) == 0) \ | |
a87aa10b | 4577 | ge |= 1 << n; \ |
6ddbc6e4 PB |
4578 | } while(0) |
4579 | ||
4580 | #define PFX u | |
4581 | #define ARITH_GE | |
4582 | ||
4583 | #include "op_addsub.h" | |
4584 | ||
4585 | /* Halved signed arithmetic. */ | |
4586 | #define ADD16(a, b, n) \ | |
4587 | RESULT(((int32_t)(int16_t)(a) + (int32_t)(int16_t)(b)) >> 1, n, 16) | |
4588 | #define SUB16(a, b, n) \ | |
4589 | RESULT(((int32_t)(int16_t)(a) - (int32_t)(int16_t)(b)) >> 1, n, 16) | |
4590 | #define ADD8(a, b, n) \ | |
4591 | RESULT(((int32_t)(int8_t)(a) + (int32_t)(int8_t)(b)) >> 1, n, 8) | |
4592 | #define SUB8(a, b, n) \ | |
4593 | RESULT(((int32_t)(int8_t)(a) - (int32_t)(int8_t)(b)) >> 1, n, 8) | |
4594 | #define PFX sh | |
4595 | ||
4596 | #include "op_addsub.h" | |
4597 | ||
4598 | /* Halved unsigned arithmetic. */ | |
4599 | #define ADD16(a, b, n) \ | |
4600 | RESULT(((uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b)) >> 1, n, 16) | |
4601 | #define SUB16(a, b, n) \ | |
4602 | RESULT(((uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b)) >> 1, n, 16) | |
4603 | #define ADD8(a, b, n) \ | |
4604 | RESULT(((uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b)) >> 1, n, 8) | |
4605 | #define SUB8(a, b, n) \ | |
4606 | RESULT(((uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b)) >> 1, n, 8) | |
4607 | #define PFX uh | |
4608 | ||
4609 | #include "op_addsub.h" | |
4610 | ||
4611 | static inline uint8_t do_usad(uint8_t a, uint8_t b) | |
4612 | { | |
4613 | if (a > b) | |
4614 | return a - b; | |
4615 | else | |
4616 | return b - a; | |
4617 | } | |
4618 | ||
4619 | /* Unsigned sum of absolute byte differences. */ | |
4620 | uint32_t HELPER(usad8)(uint32_t a, uint32_t b) | |
4621 | { | |
4622 | uint32_t sum; | |
4623 | sum = do_usad(a, b); | |
4624 | sum += do_usad(a >> 8, b >> 8); | |
4625 | sum += do_usad(a >> 16, b >>16); | |
4626 | sum += do_usad(a >> 24, b >> 24); | |
4627 | return sum; | |
4628 | } | |
4629 | ||
4630 | /* For ARMv6 SEL instruction. */ | |
4631 | uint32_t HELPER(sel_flags)(uint32_t flags, uint32_t a, uint32_t b) | |
4632 | { | |
4633 | uint32_t mask; | |
4634 | ||
4635 | mask = 0; | |
4636 | if (flags & 1) | |
4637 | mask |= 0xff; | |
4638 | if (flags & 2) | |
4639 | mask |= 0xff00; | |
4640 | if (flags & 4) | |
4641 | mask |= 0xff0000; | |
4642 | if (flags & 8) | |
4643 | mask |= 0xff000000; | |
4644 | return (a & mask) | (b & ~mask); | |
4645 | } | |
4646 | ||
b90372ad PM |
4647 | /* VFP support. We follow the convention used for VFP instructions: |
4648 | Single precision routines have a "s" suffix, double precision a | |
4373f3ce PB |
4649 | "d" suffix. */ |
4650 | ||
4651 | /* Convert host exception flags to vfp form. */ | |
4652 | static inline int vfp_exceptbits_from_host(int host_bits) | |
4653 | { | |
4654 | int target_bits = 0; | |
4655 | ||
4656 | if (host_bits & float_flag_invalid) | |
4657 | target_bits |= 1; | |
4658 | if (host_bits & float_flag_divbyzero) | |
4659 | target_bits |= 2; | |
4660 | if (host_bits & float_flag_overflow) | |
4661 | target_bits |= 4; | |
36802b6b | 4662 | if (host_bits & (float_flag_underflow | float_flag_output_denormal)) |
4373f3ce PB |
4663 | target_bits |= 8; |
4664 | if (host_bits & float_flag_inexact) | |
4665 | target_bits |= 0x10; | |
cecd8504 PM |
4666 | if (host_bits & float_flag_input_denormal) |
4667 | target_bits |= 0x80; | |
4373f3ce PB |
4668 | return target_bits; |
4669 | } | |
4670 | ||
0ecb72a5 | 4671 | uint32_t HELPER(vfp_get_fpscr)(CPUARMState *env) |
4373f3ce PB |
4672 | { |
4673 | int i; | |
4674 | uint32_t fpscr; | |
4675 | ||
4676 | fpscr = (env->vfp.xregs[ARM_VFP_FPSCR] & 0xffc8ffff) | |
4677 | | (env->vfp.vec_len << 16) | |
4678 | | (env->vfp.vec_stride << 20); | |
4679 | i = get_float_exception_flags(&env->vfp.fp_status); | |
3a492f3a | 4680 | i |= get_float_exception_flags(&env->vfp.standard_fp_status); |
4373f3ce PB |
4681 | fpscr |= vfp_exceptbits_from_host(i); |
4682 | return fpscr; | |
4683 | } | |
4684 | ||
0ecb72a5 | 4685 | uint32_t vfp_get_fpscr(CPUARMState *env) |
01653295 PM |
4686 | { |
4687 | return HELPER(vfp_get_fpscr)(env); | |
4688 | } | |
4689 | ||
4373f3ce PB |
4690 | /* Convert vfp exception flags to target form. */ |
4691 | static inline int vfp_exceptbits_to_host(int target_bits) | |
4692 | { | |
4693 | int host_bits = 0; | |
4694 | ||
4695 | if (target_bits & 1) | |
4696 | host_bits |= float_flag_invalid; | |
4697 | if (target_bits & 2) | |
4698 | host_bits |= float_flag_divbyzero; | |
4699 | if (target_bits & 4) | |
4700 | host_bits |= float_flag_overflow; | |
4701 | if (target_bits & 8) | |
4702 | host_bits |= float_flag_underflow; | |
4703 | if (target_bits & 0x10) | |
4704 | host_bits |= float_flag_inexact; | |
cecd8504 PM |
4705 | if (target_bits & 0x80) |
4706 | host_bits |= float_flag_input_denormal; | |
4373f3ce PB |
4707 | return host_bits; |
4708 | } | |
4709 | ||
0ecb72a5 | 4710 | void HELPER(vfp_set_fpscr)(CPUARMState *env, uint32_t val) |
4373f3ce PB |
4711 | { |
4712 | int i; | |
4713 | uint32_t changed; | |
4714 | ||
4715 | changed = env->vfp.xregs[ARM_VFP_FPSCR]; | |
4716 | env->vfp.xregs[ARM_VFP_FPSCR] = (val & 0xffc8ffff); | |
4717 | env->vfp.vec_len = (val >> 16) & 7; | |
4718 | env->vfp.vec_stride = (val >> 20) & 3; | |
4719 | ||
4720 | changed ^= val; | |
4721 | if (changed & (3 << 22)) { | |
4722 | i = (val >> 22) & 3; | |
4723 | switch (i) { | |
4d3da0f3 | 4724 | case FPROUNDING_TIEEVEN: |
4373f3ce PB |
4725 | i = float_round_nearest_even; |
4726 | break; | |
4d3da0f3 | 4727 | case FPROUNDING_POSINF: |
4373f3ce PB |
4728 | i = float_round_up; |
4729 | break; | |
4d3da0f3 | 4730 | case FPROUNDING_NEGINF: |
4373f3ce PB |
4731 | i = float_round_down; |
4732 | break; | |
4d3da0f3 | 4733 | case FPROUNDING_ZERO: |
4373f3ce PB |
4734 | i = float_round_to_zero; |
4735 | break; | |
4736 | } | |
4737 | set_float_rounding_mode(i, &env->vfp.fp_status); | |
4738 | } | |
cecd8504 | 4739 | if (changed & (1 << 24)) { |
fe76d976 | 4740 | set_flush_to_zero((val & (1 << 24)) != 0, &env->vfp.fp_status); |
cecd8504 PM |
4741 | set_flush_inputs_to_zero((val & (1 << 24)) != 0, &env->vfp.fp_status); |
4742 | } | |
5c7908ed PB |
4743 | if (changed & (1 << 25)) |
4744 | set_default_nan_mode((val & (1 << 25)) != 0, &env->vfp.fp_status); | |
4373f3ce | 4745 | |
b12c390b | 4746 | i = vfp_exceptbits_to_host(val); |
4373f3ce | 4747 | set_float_exception_flags(i, &env->vfp.fp_status); |
3a492f3a | 4748 | set_float_exception_flags(0, &env->vfp.standard_fp_status); |
4373f3ce PB |
4749 | } |
4750 | ||
0ecb72a5 | 4751 | void vfp_set_fpscr(CPUARMState *env, uint32_t val) |
01653295 PM |
4752 | { |
4753 | HELPER(vfp_set_fpscr)(env, val); | |
4754 | } | |
4755 | ||
4373f3ce PB |
4756 | #define VFP_HELPER(name, p) HELPER(glue(glue(vfp_,name),p)) |
4757 | ||
4758 | #define VFP_BINOP(name) \ | |
ae1857ec | 4759 | float32 VFP_HELPER(name, s)(float32 a, float32 b, void *fpstp) \ |
4373f3ce | 4760 | { \ |
ae1857ec PM |
4761 | float_status *fpst = fpstp; \ |
4762 | return float32_ ## name(a, b, fpst); \ | |
4373f3ce | 4763 | } \ |
ae1857ec | 4764 | float64 VFP_HELPER(name, d)(float64 a, float64 b, void *fpstp) \ |
4373f3ce | 4765 | { \ |
ae1857ec PM |
4766 | float_status *fpst = fpstp; \ |
4767 | return float64_ ## name(a, b, fpst); \ | |
4373f3ce PB |
4768 | } |
4769 | VFP_BINOP(add) | |
4770 | VFP_BINOP(sub) | |
4771 | VFP_BINOP(mul) | |
4772 | VFP_BINOP(div) | |
f71a2ae5 PM |
4773 | VFP_BINOP(min) |
4774 | VFP_BINOP(max) | |
4775 | VFP_BINOP(minnum) | |
4776 | VFP_BINOP(maxnum) | |
4373f3ce PB |
4777 | #undef VFP_BINOP |
4778 | ||
4779 | float32 VFP_HELPER(neg, s)(float32 a) | |
4780 | { | |
4781 | return float32_chs(a); | |
4782 | } | |
4783 | ||
4784 | float64 VFP_HELPER(neg, d)(float64 a) | |
4785 | { | |
66230e0d | 4786 | return float64_chs(a); |
4373f3ce PB |
4787 | } |
4788 | ||
4789 | float32 VFP_HELPER(abs, s)(float32 a) | |
4790 | { | |
4791 | return float32_abs(a); | |
4792 | } | |
4793 | ||
4794 | float64 VFP_HELPER(abs, d)(float64 a) | |
4795 | { | |
66230e0d | 4796 | return float64_abs(a); |
4373f3ce PB |
4797 | } |
4798 | ||
0ecb72a5 | 4799 | float32 VFP_HELPER(sqrt, s)(float32 a, CPUARMState *env) |
4373f3ce PB |
4800 | { |
4801 | return float32_sqrt(a, &env->vfp.fp_status); | |
4802 | } | |
4803 | ||
0ecb72a5 | 4804 | float64 VFP_HELPER(sqrt, d)(float64 a, CPUARMState *env) |
4373f3ce PB |
4805 | { |
4806 | return float64_sqrt(a, &env->vfp.fp_status); | |
4807 | } | |
4808 | ||
4809 | /* XXX: check quiet/signaling case */ | |
4810 | #define DO_VFP_cmp(p, type) \ | |
0ecb72a5 | 4811 | void VFP_HELPER(cmp, p)(type a, type b, CPUARMState *env) \ |
4373f3ce PB |
4812 | { \ |
4813 | uint32_t flags; \ | |
4814 | switch(type ## _compare_quiet(a, b, &env->vfp.fp_status)) { \ | |
4815 | case 0: flags = 0x6; break; \ | |
4816 | case -1: flags = 0x8; break; \ | |
4817 | case 1: flags = 0x2; break; \ | |
4818 | default: case 2: flags = 0x3; break; \ | |
4819 | } \ | |
4820 | env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \ | |
4821 | | (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \ | |
4822 | } \ | |
0ecb72a5 | 4823 | void VFP_HELPER(cmpe, p)(type a, type b, CPUARMState *env) \ |
4373f3ce PB |
4824 | { \ |
4825 | uint32_t flags; \ | |
4826 | switch(type ## _compare(a, b, &env->vfp.fp_status)) { \ | |
4827 | case 0: flags = 0x6; break; \ | |
4828 | case -1: flags = 0x8; break; \ | |
4829 | case 1: flags = 0x2; break; \ | |
4830 | default: case 2: flags = 0x3; break; \ | |
4831 | } \ | |
4832 | env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \ | |
4833 | | (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \ | |
4834 | } | |
4835 | DO_VFP_cmp(s, float32) | |
4836 | DO_VFP_cmp(d, float64) | |
4837 | #undef DO_VFP_cmp | |
4838 | ||
5500b06c | 4839 | /* Integer to float and float to integer conversions */ |
4373f3ce | 4840 | |
5500b06c PM |
4841 | #define CONV_ITOF(name, fsz, sign) \ |
4842 | float##fsz HELPER(name)(uint32_t x, void *fpstp) \ | |
4843 | { \ | |
4844 | float_status *fpst = fpstp; \ | |
85836979 | 4845 | return sign##int32_to_##float##fsz((sign##int32_t)x, fpst); \ |
4373f3ce PB |
4846 | } |
4847 | ||
5500b06c PM |
4848 | #define CONV_FTOI(name, fsz, sign, round) \ |
4849 | uint32_t HELPER(name)(float##fsz x, void *fpstp) \ | |
4850 | { \ | |
4851 | float_status *fpst = fpstp; \ | |
4852 | if (float##fsz##_is_any_nan(x)) { \ | |
4853 | float_raise(float_flag_invalid, fpst); \ | |
4854 | return 0; \ | |
4855 | } \ | |
4856 | return float##fsz##_to_##sign##int32##round(x, fpst); \ | |
4373f3ce PB |
4857 | } |
4858 | ||
5500b06c PM |
4859 | #define FLOAT_CONVS(name, p, fsz, sign) \ |
4860 | CONV_ITOF(vfp_##name##to##p, fsz, sign) \ | |
4861 | CONV_FTOI(vfp_to##name##p, fsz, sign, ) \ | |
4862 | CONV_FTOI(vfp_to##name##z##p, fsz, sign, _round_to_zero) | |
4373f3ce | 4863 | |
5500b06c PM |
4864 | FLOAT_CONVS(si, s, 32, ) |
4865 | FLOAT_CONVS(si, d, 64, ) | |
4866 | FLOAT_CONVS(ui, s, 32, u) | |
4867 | FLOAT_CONVS(ui, d, 64, u) | |
4373f3ce | 4868 | |
5500b06c PM |
4869 | #undef CONV_ITOF |
4870 | #undef CONV_FTOI | |
4871 | #undef FLOAT_CONVS | |
4373f3ce PB |
4872 | |
4873 | /* floating point conversion */ | |
0ecb72a5 | 4874 | float64 VFP_HELPER(fcvtd, s)(float32 x, CPUARMState *env) |
4373f3ce | 4875 | { |
2d627737 PM |
4876 | float64 r = float32_to_float64(x, &env->vfp.fp_status); |
4877 | /* ARM requires that S<->D conversion of any kind of NaN generates | |
4878 | * a quiet NaN by forcing the most significant frac bit to 1. | |
4879 | */ | |
4880 | return float64_maybe_silence_nan(r); | |
4373f3ce PB |
4881 | } |
4882 | ||
0ecb72a5 | 4883 | float32 VFP_HELPER(fcvts, d)(float64 x, CPUARMState *env) |
4373f3ce | 4884 | { |
2d627737 PM |
4885 | float32 r = float64_to_float32(x, &env->vfp.fp_status); |
4886 | /* ARM requires that S<->D conversion of any kind of NaN generates | |
4887 | * a quiet NaN by forcing the most significant frac bit to 1. | |
4888 | */ | |
4889 | return float32_maybe_silence_nan(r); | |
4373f3ce PB |
4890 | } |
4891 | ||
4892 | /* VFP3 fixed point conversion. */ | |
16d5b3ca | 4893 | #define VFP_CONV_FIX_FLOAT(name, p, fsz, isz, itype) \ |
8ed697e8 WN |
4894 | float##fsz HELPER(vfp_##name##to##p)(uint##isz##_t x, uint32_t shift, \ |
4895 | void *fpstp) \ | |
4373f3ce | 4896 | { \ |
5500b06c | 4897 | float_status *fpst = fpstp; \ |
622465e1 | 4898 | float##fsz tmp; \ |
8ed697e8 | 4899 | tmp = itype##_to_##float##fsz(x, fpst); \ |
5500b06c | 4900 | return float##fsz##_scalbn(tmp, -(int)shift, fpst); \ |
16d5b3ca WN |
4901 | } |
4902 | ||
abe66f70 PM |
4903 | /* Notice that we want only input-denormal exception flags from the |
4904 | * scalbn operation: the other possible flags (overflow+inexact if | |
4905 | * we overflow to infinity, output-denormal) aren't correct for the | |
4906 | * complete scale-and-convert operation. | |
4907 | */ | |
16d5b3ca WN |
4908 | #define VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, round) \ |
4909 | uint##isz##_t HELPER(vfp_to##name##p##round)(float##fsz x, \ | |
4910 | uint32_t shift, \ | |
4911 | void *fpstp) \ | |
4373f3ce | 4912 | { \ |
5500b06c | 4913 | float_status *fpst = fpstp; \ |
abe66f70 | 4914 | int old_exc_flags = get_float_exception_flags(fpst); \ |
622465e1 PM |
4915 | float##fsz tmp; \ |
4916 | if (float##fsz##_is_any_nan(x)) { \ | |
5500b06c | 4917 | float_raise(float_flag_invalid, fpst); \ |
622465e1 | 4918 | return 0; \ |
09d9487f | 4919 | } \ |
5500b06c | 4920 | tmp = float##fsz##_scalbn(x, shift, fpst); \ |
abe66f70 PM |
4921 | old_exc_flags |= get_float_exception_flags(fpst) \ |
4922 | & float_flag_input_denormal; \ | |
4923 | set_float_exception_flags(old_exc_flags, fpst); \ | |
16d5b3ca | 4924 | return float##fsz##_to_##itype##round(tmp, fpst); \ |
622465e1 PM |
4925 | } |
4926 | ||
16d5b3ca WN |
4927 | #define VFP_CONV_FIX(name, p, fsz, isz, itype) \ |
4928 | VFP_CONV_FIX_FLOAT(name, p, fsz, isz, itype) \ | |
3c6a074a WN |
4929 | VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, _round_to_zero) \ |
4930 | VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, ) | |
4931 | ||
4932 | #define VFP_CONV_FIX_A64(name, p, fsz, isz, itype) \ | |
4933 | VFP_CONV_FIX_FLOAT(name, p, fsz, isz, itype) \ | |
4934 | VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, ) | |
16d5b3ca | 4935 | |
8ed697e8 WN |
4936 | VFP_CONV_FIX(sh, d, 64, 64, int16) |
4937 | VFP_CONV_FIX(sl, d, 64, 64, int32) | |
3c6a074a | 4938 | VFP_CONV_FIX_A64(sq, d, 64, 64, int64) |
8ed697e8 WN |
4939 | VFP_CONV_FIX(uh, d, 64, 64, uint16) |
4940 | VFP_CONV_FIX(ul, d, 64, 64, uint32) | |
3c6a074a | 4941 | VFP_CONV_FIX_A64(uq, d, 64, 64, uint64) |
8ed697e8 WN |
4942 | VFP_CONV_FIX(sh, s, 32, 32, int16) |
4943 | VFP_CONV_FIX(sl, s, 32, 32, int32) | |
3c6a074a | 4944 | VFP_CONV_FIX_A64(sq, s, 32, 64, int64) |
8ed697e8 WN |
4945 | VFP_CONV_FIX(uh, s, 32, 32, uint16) |
4946 | VFP_CONV_FIX(ul, s, 32, 32, uint32) | |
3c6a074a | 4947 | VFP_CONV_FIX_A64(uq, s, 32, 64, uint64) |
4373f3ce | 4948 | #undef VFP_CONV_FIX |
16d5b3ca WN |
4949 | #undef VFP_CONV_FIX_FLOAT |
4950 | #undef VFP_CONV_FLOAT_FIX_ROUND | |
4373f3ce | 4951 | |
52a1f6a3 AG |
4952 | /* Set the current fp rounding mode and return the old one. |
4953 | * The argument is a softfloat float_round_ value. | |
4954 | */ | |
4955 | uint32_t HELPER(set_rmode)(uint32_t rmode, CPUARMState *env) | |
4956 | { | |
4957 | float_status *fp_status = &env->vfp.fp_status; | |
4958 | ||
4959 | uint32_t prev_rmode = get_float_rounding_mode(fp_status); | |
4960 | set_float_rounding_mode(rmode, fp_status); | |
4961 | ||
4962 | return prev_rmode; | |
4963 | } | |
4964 | ||
43630e58 WN |
4965 | /* Set the current fp rounding mode in the standard fp status and return |
4966 | * the old one. This is for NEON instructions that need to change the | |
4967 | * rounding mode but wish to use the standard FPSCR values for everything | |
4968 | * else. Always set the rounding mode back to the correct value after | |
4969 | * modifying it. | |
4970 | * The argument is a softfloat float_round_ value. | |
4971 | */ | |
4972 | uint32_t HELPER(set_neon_rmode)(uint32_t rmode, CPUARMState *env) | |
4973 | { | |
4974 | float_status *fp_status = &env->vfp.standard_fp_status; | |
4975 | ||
4976 | uint32_t prev_rmode = get_float_rounding_mode(fp_status); | |
4977 | set_float_rounding_mode(rmode, fp_status); | |
4978 | ||
4979 | return prev_rmode; | |
4980 | } | |
4981 | ||
60011498 | 4982 | /* Half precision conversions. */ |
0ecb72a5 | 4983 | static float32 do_fcvt_f16_to_f32(uint32_t a, CPUARMState *env, float_status *s) |
60011498 | 4984 | { |
60011498 | 4985 | int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0; |
fb91678d PM |
4986 | float32 r = float16_to_float32(make_float16(a), ieee, s); |
4987 | if (ieee) { | |
4988 | return float32_maybe_silence_nan(r); | |
4989 | } | |
4990 | return r; | |
60011498 PB |
4991 | } |
4992 | ||
0ecb72a5 | 4993 | static uint32_t do_fcvt_f32_to_f16(float32 a, CPUARMState *env, float_status *s) |
60011498 | 4994 | { |
60011498 | 4995 | int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0; |
fb91678d PM |
4996 | float16 r = float32_to_float16(a, ieee, s); |
4997 | if (ieee) { | |
4998 | r = float16_maybe_silence_nan(r); | |
4999 | } | |
5000 | return float16_val(r); | |
60011498 PB |
5001 | } |
5002 | ||
0ecb72a5 | 5003 | float32 HELPER(neon_fcvt_f16_to_f32)(uint32_t a, CPUARMState *env) |
2d981da7 PM |
5004 | { |
5005 | return do_fcvt_f16_to_f32(a, env, &env->vfp.standard_fp_status); | |
5006 | } | |
5007 | ||
0ecb72a5 | 5008 | uint32_t HELPER(neon_fcvt_f32_to_f16)(float32 a, CPUARMState *env) |
2d981da7 PM |
5009 | { |
5010 | return do_fcvt_f32_to_f16(a, env, &env->vfp.standard_fp_status); | |
5011 | } | |
5012 | ||
0ecb72a5 | 5013 | float32 HELPER(vfp_fcvt_f16_to_f32)(uint32_t a, CPUARMState *env) |
2d981da7 PM |
5014 | { |
5015 | return do_fcvt_f16_to_f32(a, env, &env->vfp.fp_status); | |
5016 | } | |
5017 | ||
0ecb72a5 | 5018 | uint32_t HELPER(vfp_fcvt_f32_to_f16)(float32 a, CPUARMState *env) |
2d981da7 PM |
5019 | { |
5020 | return do_fcvt_f32_to_f16(a, env, &env->vfp.fp_status); | |
5021 | } | |
5022 | ||
8900aad2 PM |
5023 | float64 HELPER(vfp_fcvt_f16_to_f64)(uint32_t a, CPUARMState *env) |
5024 | { | |
5025 | int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0; | |
5026 | float64 r = float16_to_float64(make_float16(a), ieee, &env->vfp.fp_status); | |
5027 | if (ieee) { | |
5028 | return float64_maybe_silence_nan(r); | |
5029 | } | |
5030 | return r; | |
5031 | } | |
5032 | ||
5033 | uint32_t HELPER(vfp_fcvt_f64_to_f16)(float64 a, CPUARMState *env) | |
5034 | { | |
5035 | int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0; | |
5036 | float16 r = float64_to_float16(a, ieee, &env->vfp.fp_status); | |
5037 | if (ieee) { | |
5038 | r = float16_maybe_silence_nan(r); | |
5039 | } | |
5040 | return float16_val(r); | |
5041 | } | |
5042 | ||
dda3ec49 | 5043 | #define float32_two make_float32(0x40000000) |
6aae3df1 PM |
5044 | #define float32_three make_float32(0x40400000) |
5045 | #define float32_one_point_five make_float32(0x3fc00000) | |
dda3ec49 | 5046 | |
0ecb72a5 | 5047 | float32 HELPER(recps_f32)(float32 a, float32 b, CPUARMState *env) |
4373f3ce | 5048 | { |
dda3ec49 PM |
5049 | float_status *s = &env->vfp.standard_fp_status; |
5050 | if ((float32_is_infinity(a) && float32_is_zero_or_denormal(b)) || | |
5051 | (float32_is_infinity(b) && float32_is_zero_or_denormal(a))) { | |
43fe9bdb PM |
5052 | if (!(float32_is_zero(a) || float32_is_zero(b))) { |
5053 | float_raise(float_flag_input_denormal, s); | |
5054 | } | |
dda3ec49 PM |
5055 | return float32_two; |
5056 | } | |
5057 | return float32_sub(float32_two, float32_mul(a, b, s), s); | |
4373f3ce PB |
5058 | } |
5059 | ||
0ecb72a5 | 5060 | float32 HELPER(rsqrts_f32)(float32 a, float32 b, CPUARMState *env) |
4373f3ce | 5061 | { |
71826966 | 5062 | float_status *s = &env->vfp.standard_fp_status; |
9ea62f57 PM |
5063 | float32 product; |
5064 | if ((float32_is_infinity(a) && float32_is_zero_or_denormal(b)) || | |
5065 | (float32_is_infinity(b) && float32_is_zero_or_denormal(a))) { | |
43fe9bdb PM |
5066 | if (!(float32_is_zero(a) || float32_is_zero(b))) { |
5067 | float_raise(float_flag_input_denormal, s); | |
5068 | } | |
6aae3df1 | 5069 | return float32_one_point_five; |
9ea62f57 | 5070 | } |
6aae3df1 PM |
5071 | product = float32_mul(a, b, s); |
5072 | return float32_div(float32_sub(float32_three, product, s), float32_two, s); | |
4373f3ce PB |
5073 | } |
5074 | ||
8f8e3aa4 PB |
5075 | /* NEON helpers. */ |
5076 | ||
56bf4fe2 CL |
5077 | /* Constants 256 and 512 are used in some helpers; we avoid relying on |
5078 | * int->float conversions at run-time. */ | |
5079 | #define float64_256 make_float64(0x4070000000000000LL) | |
5080 | #define float64_512 make_float64(0x4080000000000000LL) | |
b6d4443a AB |
5081 | #define float32_maxnorm make_float32(0x7f7fffff) |
5082 | #define float64_maxnorm make_float64(0x7fefffffffffffffLL) | |
56bf4fe2 | 5083 | |
b6d4443a AB |
5084 | /* Reciprocal functions |
5085 | * | |
5086 | * The algorithm that must be used to calculate the estimate | |
5087 | * is specified by the ARM ARM, see FPRecipEstimate() | |
fe0e4872 | 5088 | */ |
b6d4443a AB |
5089 | |
5090 | static float64 recip_estimate(float64 a, float_status *real_fp_status) | |
fe0e4872 | 5091 | { |
1146a817 PM |
5092 | /* These calculations mustn't set any fp exception flags, |
5093 | * so we use a local copy of the fp_status. | |
5094 | */ | |
b6d4443a | 5095 | float_status dummy_status = *real_fp_status; |
1146a817 | 5096 | float_status *s = &dummy_status; |
fe0e4872 CL |
5097 | /* q = (int)(a * 512.0) */ |
5098 | float64 q = float64_mul(float64_512, a, s); | |
5099 | int64_t q_int = float64_to_int64_round_to_zero(q, s); | |
5100 | ||
5101 | /* r = 1.0 / (((double)q + 0.5) / 512.0) */ | |
5102 | q = int64_to_float64(q_int, s); | |
5103 | q = float64_add(q, float64_half, s); | |
5104 | q = float64_div(q, float64_512, s); | |
5105 | q = float64_div(float64_one, q, s); | |
5106 | ||
5107 | /* s = (int)(256.0 * r + 0.5) */ | |
5108 | q = float64_mul(q, float64_256, s); | |
5109 | q = float64_add(q, float64_half, s); | |
5110 | q_int = float64_to_int64_round_to_zero(q, s); | |
5111 | ||
5112 | /* return (double)s / 256.0 */ | |
5113 | return float64_div(int64_to_float64(q_int, s), float64_256, s); | |
5114 | } | |
5115 | ||
b6d4443a AB |
5116 | /* Common wrapper to call recip_estimate */ |
5117 | static float64 call_recip_estimate(float64 num, int off, float_status *fpst) | |
4373f3ce | 5118 | { |
b6d4443a AB |
5119 | uint64_t val64 = float64_val(num); |
5120 | uint64_t frac = extract64(val64, 0, 52); | |
5121 | int64_t exp = extract64(val64, 52, 11); | |
5122 | uint64_t sbit; | |
5123 | float64 scaled, estimate; | |
fe0e4872 | 5124 | |
b6d4443a AB |
5125 | /* Generate the scaled number for the estimate function */ |
5126 | if (exp == 0) { | |
5127 | if (extract64(frac, 51, 1) == 0) { | |
5128 | exp = -1; | |
5129 | frac = extract64(frac, 0, 50) << 2; | |
5130 | } else { | |
5131 | frac = extract64(frac, 0, 51) << 1; | |
5132 | } | |
5133 | } | |
fe0e4872 | 5134 | |
b6d4443a AB |
5135 | /* scaled = '0' : '01111111110' : fraction<51:44> : Zeros(44); */ |
5136 | scaled = make_float64((0x3feULL << 52) | |
5137 | | extract64(frac, 44, 8) << 44); | |
5138 | ||
5139 | estimate = recip_estimate(scaled, fpst); | |
5140 | ||
5141 | /* Build new result */ | |
5142 | val64 = float64_val(estimate); | |
5143 | sbit = 0x8000000000000000ULL & val64; | |
5144 | exp = off - exp; | |
5145 | frac = extract64(val64, 0, 52); | |
5146 | ||
5147 | if (exp == 0) { | |
5148 | frac = 1ULL << 51 | extract64(frac, 1, 51); | |
5149 | } else if (exp == -1) { | |
5150 | frac = 1ULL << 50 | extract64(frac, 2, 50); | |
5151 | exp = 0; | |
5152 | } | |
5153 | ||
5154 | return make_float64(sbit | (exp << 52) | frac); | |
5155 | } | |
5156 | ||
5157 | static bool round_to_inf(float_status *fpst, bool sign_bit) | |
5158 | { | |
5159 | switch (fpst->float_rounding_mode) { | |
5160 | case float_round_nearest_even: /* Round to Nearest */ | |
5161 | return true; | |
5162 | case float_round_up: /* Round to +Inf */ | |
5163 | return !sign_bit; | |
5164 | case float_round_down: /* Round to -Inf */ | |
5165 | return sign_bit; | |
5166 | case float_round_to_zero: /* Round to Zero */ | |
5167 | return false; | |
5168 | } | |
5169 | ||
5170 | g_assert_not_reached(); | |
5171 | } | |
5172 | ||
5173 | float32 HELPER(recpe_f32)(float32 input, void *fpstp) | |
5174 | { | |
5175 | float_status *fpst = fpstp; | |
5176 | float32 f32 = float32_squash_input_denormal(input, fpst); | |
5177 | uint32_t f32_val = float32_val(f32); | |
5178 | uint32_t f32_sbit = 0x80000000ULL & f32_val; | |
5179 | int32_t f32_exp = extract32(f32_val, 23, 8); | |
5180 | uint32_t f32_frac = extract32(f32_val, 0, 23); | |
5181 | float64 f64, r64; | |
5182 | uint64_t r64_val; | |
5183 | int64_t r64_exp; | |
5184 | uint64_t r64_frac; | |
5185 | ||
5186 | if (float32_is_any_nan(f32)) { | |
5187 | float32 nan = f32; | |
5188 | if (float32_is_signaling_nan(f32)) { | |
5189 | float_raise(float_flag_invalid, fpst); | |
5190 | nan = float32_maybe_silence_nan(f32); | |
fe0e4872 | 5191 | } |
b6d4443a AB |
5192 | if (fpst->default_nan_mode) { |
5193 | nan = float32_default_nan; | |
43fe9bdb | 5194 | } |
b6d4443a AB |
5195 | return nan; |
5196 | } else if (float32_is_infinity(f32)) { | |
5197 | return float32_set_sign(float32_zero, float32_is_neg(f32)); | |
5198 | } else if (float32_is_zero(f32)) { | |
5199 | float_raise(float_flag_divbyzero, fpst); | |
5200 | return float32_set_sign(float32_infinity, float32_is_neg(f32)); | |
5201 | } else if ((f32_val & ~(1ULL << 31)) < (1ULL << 21)) { | |
5202 | /* Abs(value) < 2.0^-128 */ | |
5203 | float_raise(float_flag_overflow | float_flag_inexact, fpst); | |
5204 | if (round_to_inf(fpst, f32_sbit)) { | |
5205 | return float32_set_sign(float32_infinity, float32_is_neg(f32)); | |
5206 | } else { | |
5207 | return float32_set_sign(float32_maxnorm, float32_is_neg(f32)); | |
5208 | } | |
5209 | } else if (f32_exp >= 253 && fpst->flush_to_zero) { | |
5210 | float_raise(float_flag_underflow, fpst); | |
5211 | return float32_set_sign(float32_zero, float32_is_neg(f32)); | |
fe0e4872 CL |
5212 | } |
5213 | ||
fe0e4872 | 5214 | |
b6d4443a AB |
5215 | f64 = make_float64(((int64_t)(f32_exp) << 52) | (int64_t)(f32_frac) << 29); |
5216 | r64 = call_recip_estimate(f64, 253, fpst); | |
5217 | r64_val = float64_val(r64); | |
5218 | r64_exp = extract64(r64_val, 52, 11); | |
5219 | r64_frac = extract64(r64_val, 0, 52); | |
5220 | ||
5221 | /* result = sign : result_exp<7:0> : fraction<51:29>; */ | |
5222 | return make_float32(f32_sbit | | |
5223 | (r64_exp & 0xff) << 23 | | |
5224 | extract64(r64_frac, 29, 24)); | |
5225 | } | |
5226 | ||
5227 | float64 HELPER(recpe_f64)(float64 input, void *fpstp) | |
5228 | { | |
5229 | float_status *fpst = fpstp; | |
5230 | float64 f64 = float64_squash_input_denormal(input, fpst); | |
5231 | uint64_t f64_val = float64_val(f64); | |
5232 | uint64_t f64_sbit = 0x8000000000000000ULL & f64_val; | |
5233 | int64_t f64_exp = extract64(f64_val, 52, 11); | |
5234 | float64 r64; | |
5235 | uint64_t r64_val; | |
5236 | int64_t r64_exp; | |
5237 | uint64_t r64_frac; | |
5238 | ||
5239 | /* Deal with any special cases */ | |
5240 | if (float64_is_any_nan(f64)) { | |
5241 | float64 nan = f64; | |
5242 | if (float64_is_signaling_nan(f64)) { | |
5243 | float_raise(float_flag_invalid, fpst); | |
5244 | nan = float64_maybe_silence_nan(f64); | |
5245 | } | |
5246 | if (fpst->default_nan_mode) { | |
5247 | nan = float64_default_nan; | |
5248 | } | |
5249 | return nan; | |
5250 | } else if (float64_is_infinity(f64)) { | |
5251 | return float64_set_sign(float64_zero, float64_is_neg(f64)); | |
5252 | } else if (float64_is_zero(f64)) { | |
5253 | float_raise(float_flag_divbyzero, fpst); | |
5254 | return float64_set_sign(float64_infinity, float64_is_neg(f64)); | |
5255 | } else if ((f64_val & ~(1ULL << 63)) < (1ULL << 50)) { | |
5256 | /* Abs(value) < 2.0^-1024 */ | |
5257 | float_raise(float_flag_overflow | float_flag_inexact, fpst); | |
5258 | if (round_to_inf(fpst, f64_sbit)) { | |
5259 | return float64_set_sign(float64_infinity, float64_is_neg(f64)); | |
5260 | } else { | |
5261 | return float64_set_sign(float64_maxnorm, float64_is_neg(f64)); | |
5262 | } | |
5263 | } else if (f64_exp >= 1023 && fpst->flush_to_zero) { | |
5264 | float_raise(float_flag_underflow, fpst); | |
5265 | return float64_set_sign(float64_zero, float64_is_neg(f64)); | |
5266 | } | |
fe0e4872 | 5267 | |
b6d4443a AB |
5268 | r64 = call_recip_estimate(f64, 2045, fpst); |
5269 | r64_val = float64_val(r64); | |
5270 | r64_exp = extract64(r64_val, 52, 11); | |
5271 | r64_frac = extract64(r64_val, 0, 52); | |
fe0e4872 | 5272 | |
b6d4443a AB |
5273 | /* result = sign : result_exp<10:0> : fraction<51:0> */ |
5274 | return make_float64(f64_sbit | | |
5275 | ((r64_exp & 0x7ff) << 52) | | |
5276 | r64_frac); | |
4373f3ce PB |
5277 | } |
5278 | ||
e07be5d2 CL |
5279 | /* The algorithm that must be used to calculate the estimate |
5280 | * is specified by the ARM ARM. | |
5281 | */ | |
c2fb418e | 5282 | static float64 recip_sqrt_estimate(float64 a, float_status *real_fp_status) |
e07be5d2 | 5283 | { |
1146a817 PM |
5284 | /* These calculations mustn't set any fp exception flags, |
5285 | * so we use a local copy of the fp_status. | |
5286 | */ | |
c2fb418e | 5287 | float_status dummy_status = *real_fp_status; |
1146a817 | 5288 | float_status *s = &dummy_status; |
e07be5d2 CL |
5289 | float64 q; |
5290 | int64_t q_int; | |
5291 | ||
5292 | if (float64_lt(a, float64_half, s)) { | |
5293 | /* range 0.25 <= a < 0.5 */ | |
5294 | ||
5295 | /* a in units of 1/512 rounded down */ | |
5296 | /* q0 = (int)(a * 512.0); */ | |
5297 | q = float64_mul(float64_512, a, s); | |
5298 | q_int = float64_to_int64_round_to_zero(q, s); | |
5299 | ||
5300 | /* reciprocal root r */ | |
5301 | /* r = 1.0 / sqrt(((double)q0 + 0.5) / 512.0); */ | |
5302 | q = int64_to_float64(q_int, s); | |
5303 | q = float64_add(q, float64_half, s); | |
5304 | q = float64_div(q, float64_512, s); | |
5305 | q = float64_sqrt(q, s); | |
5306 | q = float64_div(float64_one, q, s); | |
5307 | } else { | |
5308 | /* range 0.5 <= a < 1.0 */ | |
5309 | ||
5310 | /* a in units of 1/256 rounded down */ | |
5311 | /* q1 = (int)(a * 256.0); */ | |
5312 | q = float64_mul(float64_256, a, s); | |
5313 | int64_t q_int = float64_to_int64_round_to_zero(q, s); | |
5314 | ||
5315 | /* reciprocal root r */ | |
5316 | /* r = 1.0 /sqrt(((double)q1 + 0.5) / 256); */ | |
5317 | q = int64_to_float64(q_int, s); | |
5318 | q = float64_add(q, float64_half, s); | |
5319 | q = float64_div(q, float64_256, s); | |
5320 | q = float64_sqrt(q, s); | |
5321 | q = float64_div(float64_one, q, s); | |
5322 | } | |
5323 | /* r in units of 1/256 rounded to nearest */ | |
5324 | /* s = (int)(256.0 * r + 0.5); */ | |
5325 | ||
5326 | q = float64_mul(q, float64_256,s ); | |
5327 | q = float64_add(q, float64_half, s); | |
5328 | q_int = float64_to_int64_round_to_zero(q, s); | |
5329 | ||
5330 | /* return (double)s / 256.0;*/ | |
5331 | return float64_div(int64_to_float64(q_int, s), float64_256, s); | |
5332 | } | |
5333 | ||
c2fb418e | 5334 | float32 HELPER(rsqrte_f32)(float32 input, void *fpstp) |
4373f3ce | 5335 | { |
c2fb418e AB |
5336 | float_status *s = fpstp; |
5337 | float32 f32 = float32_squash_input_denormal(input, s); | |
5338 | uint32_t val = float32_val(f32); | |
5339 | uint32_t f32_sbit = 0x80000000 & val; | |
5340 | int32_t f32_exp = extract32(val, 23, 8); | |
5341 | uint32_t f32_frac = extract32(val, 0, 23); | |
5342 | uint64_t f64_frac; | |
5343 | uint64_t val64; | |
e07be5d2 CL |
5344 | int result_exp; |
5345 | float64 f64; | |
e07be5d2 | 5346 | |
c2fb418e AB |
5347 | if (float32_is_any_nan(f32)) { |
5348 | float32 nan = f32; | |
5349 | if (float32_is_signaling_nan(f32)) { | |
e07be5d2 | 5350 | float_raise(float_flag_invalid, s); |
c2fb418e | 5351 | nan = float32_maybe_silence_nan(f32); |
e07be5d2 | 5352 | } |
c2fb418e AB |
5353 | if (s->default_nan_mode) { |
5354 | nan = float32_default_nan; | |
43fe9bdb | 5355 | } |
c2fb418e AB |
5356 | return nan; |
5357 | } else if (float32_is_zero(f32)) { | |
e07be5d2 | 5358 | float_raise(float_flag_divbyzero, s); |
c2fb418e AB |
5359 | return float32_set_sign(float32_infinity, float32_is_neg(f32)); |
5360 | } else if (float32_is_neg(f32)) { | |
e07be5d2 CL |
5361 | float_raise(float_flag_invalid, s); |
5362 | return float32_default_nan; | |
c2fb418e | 5363 | } else if (float32_is_infinity(f32)) { |
e07be5d2 CL |
5364 | return float32_zero; |
5365 | } | |
5366 | ||
c2fb418e | 5367 | /* Scale and normalize to a double-precision value between 0.25 and 1.0, |
e07be5d2 | 5368 | * preserving the parity of the exponent. */ |
c2fb418e AB |
5369 | |
5370 | f64_frac = ((uint64_t) f32_frac) << 29; | |
5371 | if (f32_exp == 0) { | |
5372 | while (extract64(f64_frac, 51, 1) == 0) { | |
5373 | f64_frac = f64_frac << 1; | |
5374 | f32_exp = f32_exp-1; | |
5375 | } | |
5376 | f64_frac = extract64(f64_frac, 0, 51) << 1; | |
5377 | } | |
5378 | ||
5379 | if (extract64(f32_exp, 0, 1) == 0) { | |
5380 | f64 = make_float64(((uint64_t) f32_sbit) << 32 | |
e07be5d2 | 5381 | | (0x3feULL << 52) |
c2fb418e | 5382 | | f64_frac); |
e07be5d2 | 5383 | } else { |
c2fb418e | 5384 | f64 = make_float64(((uint64_t) f32_sbit) << 32 |
e07be5d2 | 5385 | | (0x3fdULL << 52) |
c2fb418e | 5386 | | f64_frac); |
e07be5d2 CL |
5387 | } |
5388 | ||
c2fb418e | 5389 | result_exp = (380 - f32_exp) / 2; |
e07be5d2 | 5390 | |
c2fb418e | 5391 | f64 = recip_sqrt_estimate(f64, s); |
e07be5d2 CL |
5392 | |
5393 | val64 = float64_val(f64); | |
5394 | ||
26cc6abf | 5395 | val = ((result_exp & 0xff) << 23) |
e07be5d2 CL |
5396 | | ((val64 >> 29) & 0x7fffff); |
5397 | return make_float32(val); | |
4373f3ce PB |
5398 | } |
5399 | ||
c2fb418e AB |
5400 | float64 HELPER(rsqrte_f64)(float64 input, void *fpstp) |
5401 | { | |
5402 | float_status *s = fpstp; | |
5403 | float64 f64 = float64_squash_input_denormal(input, s); | |
5404 | uint64_t val = float64_val(f64); | |
5405 | uint64_t f64_sbit = 0x8000000000000000ULL & val; | |
5406 | int64_t f64_exp = extract64(val, 52, 11); | |
5407 | uint64_t f64_frac = extract64(val, 0, 52); | |
5408 | int64_t result_exp; | |
5409 | uint64_t result_frac; | |
5410 | ||
5411 | if (float64_is_any_nan(f64)) { | |
5412 | float64 nan = f64; | |
5413 | if (float64_is_signaling_nan(f64)) { | |
5414 | float_raise(float_flag_invalid, s); | |
5415 | nan = float64_maybe_silence_nan(f64); | |
5416 | } | |
5417 | if (s->default_nan_mode) { | |
5418 | nan = float64_default_nan; | |
5419 | } | |
5420 | return nan; | |
5421 | } else if (float64_is_zero(f64)) { | |
5422 | float_raise(float_flag_divbyzero, s); | |
5423 | return float64_set_sign(float64_infinity, float64_is_neg(f64)); | |
5424 | } else if (float64_is_neg(f64)) { | |
5425 | float_raise(float_flag_invalid, s); | |
5426 | return float64_default_nan; | |
5427 | } else if (float64_is_infinity(f64)) { | |
5428 | return float64_zero; | |
5429 | } | |
5430 | ||
5431 | /* Scale and normalize to a double-precision value between 0.25 and 1.0, | |
5432 | * preserving the parity of the exponent. */ | |
5433 | ||
5434 | if (f64_exp == 0) { | |
5435 | while (extract64(f64_frac, 51, 1) == 0) { | |
5436 | f64_frac = f64_frac << 1; | |
5437 | f64_exp = f64_exp - 1; | |
5438 | } | |
5439 | f64_frac = extract64(f64_frac, 0, 51) << 1; | |
5440 | } | |
5441 | ||
5442 | if (extract64(f64_exp, 0, 1) == 0) { | |
5443 | f64 = make_float64(f64_sbit | |
5444 | | (0x3feULL << 52) | |
5445 | | f64_frac); | |
5446 | } else { | |
5447 | f64 = make_float64(f64_sbit | |
5448 | | (0x3fdULL << 52) | |
5449 | | f64_frac); | |
5450 | } | |
5451 | ||
5452 | result_exp = (3068 - f64_exp) / 2; | |
5453 | ||
5454 | f64 = recip_sqrt_estimate(f64, s); | |
5455 | ||
5456 | result_frac = extract64(float64_val(f64), 0, 52); | |
5457 | ||
5458 | return make_float64(f64_sbit | | |
5459 | ((result_exp & 0x7ff) << 52) | | |
5460 | result_frac); | |
5461 | } | |
5462 | ||
b6d4443a | 5463 | uint32_t HELPER(recpe_u32)(uint32_t a, void *fpstp) |
4373f3ce | 5464 | { |
b6d4443a | 5465 | float_status *s = fpstp; |
fe0e4872 CL |
5466 | float64 f64; |
5467 | ||
5468 | if ((a & 0x80000000) == 0) { | |
5469 | return 0xffffffff; | |
5470 | } | |
5471 | ||
5472 | f64 = make_float64((0x3feULL << 52) | |
5473 | | ((int64_t)(a & 0x7fffffff) << 21)); | |
5474 | ||
b6d4443a | 5475 | f64 = recip_estimate(f64, s); |
fe0e4872 CL |
5476 | |
5477 | return 0x80000000 | ((float64_val(f64) >> 21) & 0x7fffffff); | |
4373f3ce PB |
5478 | } |
5479 | ||
c2fb418e | 5480 | uint32_t HELPER(rsqrte_u32)(uint32_t a, void *fpstp) |
4373f3ce | 5481 | { |
c2fb418e | 5482 | float_status *fpst = fpstp; |
e07be5d2 CL |
5483 | float64 f64; |
5484 | ||
5485 | if ((a & 0xc0000000) == 0) { | |
5486 | return 0xffffffff; | |
5487 | } | |
5488 | ||
5489 | if (a & 0x80000000) { | |
5490 | f64 = make_float64((0x3feULL << 52) | |
5491 | | ((uint64_t)(a & 0x7fffffff) << 21)); | |
5492 | } else { /* bits 31-30 == '01' */ | |
5493 | f64 = make_float64((0x3fdULL << 52) | |
5494 | | ((uint64_t)(a & 0x3fffffff) << 22)); | |
5495 | } | |
5496 | ||
c2fb418e | 5497 | f64 = recip_sqrt_estimate(f64, fpst); |
e07be5d2 CL |
5498 | |
5499 | return 0x80000000 | ((float64_val(f64) >> 21) & 0x7fffffff); | |
4373f3ce | 5500 | } |
fe1479c3 | 5501 | |
da97f52c PM |
5502 | /* VFPv4 fused multiply-accumulate */ |
5503 | float32 VFP_HELPER(muladd, s)(float32 a, float32 b, float32 c, void *fpstp) | |
5504 | { | |
5505 | float_status *fpst = fpstp; | |
5506 | return float32_muladd(a, b, c, 0, fpst); | |
5507 | } | |
5508 | ||
5509 | float64 VFP_HELPER(muladd, d)(float64 a, float64 b, float64 c, void *fpstp) | |
5510 | { | |
5511 | float_status *fpst = fpstp; | |
5512 | return float64_muladd(a, b, c, 0, fpst); | |
5513 | } | |
d9b0848d PM |
5514 | |
5515 | /* ARMv8 round to integral */ | |
5516 | float32 HELPER(rints_exact)(float32 x, void *fp_status) | |
5517 | { | |
5518 | return float32_round_to_int(x, fp_status); | |
5519 | } | |
5520 | ||
5521 | float64 HELPER(rintd_exact)(float64 x, void *fp_status) | |
5522 | { | |
5523 | return float64_round_to_int(x, fp_status); | |
5524 | } | |
5525 | ||
5526 | float32 HELPER(rints)(float32 x, void *fp_status) | |
5527 | { | |
5528 | int old_flags = get_float_exception_flags(fp_status), new_flags; | |
5529 | float32 ret; | |
5530 | ||
5531 | ret = float32_round_to_int(x, fp_status); | |
5532 | ||
5533 | /* Suppress any inexact exceptions the conversion produced */ | |
5534 | if (!(old_flags & float_flag_inexact)) { | |
5535 | new_flags = get_float_exception_flags(fp_status); | |
5536 | set_float_exception_flags(new_flags & ~float_flag_inexact, fp_status); | |
5537 | } | |
5538 | ||
5539 | return ret; | |
5540 | } | |
5541 | ||
5542 | float64 HELPER(rintd)(float64 x, void *fp_status) | |
5543 | { | |
5544 | int old_flags = get_float_exception_flags(fp_status), new_flags; | |
5545 | float64 ret; | |
5546 | ||
5547 | ret = float64_round_to_int(x, fp_status); | |
5548 | ||
5549 | new_flags = get_float_exception_flags(fp_status); | |
5550 | ||
5551 | /* Suppress any inexact exceptions the conversion produced */ | |
5552 | if (!(old_flags & float_flag_inexact)) { | |
5553 | new_flags = get_float_exception_flags(fp_status); | |
5554 | set_float_exception_flags(new_flags & ~float_flag_inexact, fp_status); | |
5555 | } | |
5556 | ||
5557 | return ret; | |
5558 | } | |
9972da66 WN |
5559 | |
5560 | /* Convert ARM rounding mode to softfloat */ | |
5561 | int arm_rmode_to_sf(int rmode) | |
5562 | { | |
5563 | switch (rmode) { | |
5564 | case FPROUNDING_TIEAWAY: | |
5565 | rmode = float_round_ties_away; | |
5566 | break; | |
5567 | case FPROUNDING_ODD: | |
5568 | /* FIXME: add support for TIEAWAY and ODD */ | |
5569 | qemu_log_mask(LOG_UNIMP, "arm: unimplemented rounding mode: %d\n", | |
5570 | rmode); | |
5571 | case FPROUNDING_TIEEVEN: | |
5572 | default: | |
5573 | rmode = float_round_nearest_even; | |
5574 | break; | |
5575 | case FPROUNDING_POSINF: | |
5576 | rmode = float_round_up; | |
5577 | break; | |
5578 | case FPROUNDING_NEGINF: | |
5579 | rmode = float_round_down; | |
5580 | break; | |
5581 | case FPROUNDING_ZERO: | |
5582 | rmode = float_round_to_zero; | |
5583 | break; | |
5584 | } | |
5585 | return rmode; | |
5586 | } | |
eb0ecd5a | 5587 | |
aa633469 PM |
5588 | /* CRC helpers. |
5589 | * The upper bytes of val (above the number specified by 'bytes') must have | |
5590 | * been zeroed out by the caller. | |
5591 | */ | |
eb0ecd5a WN |
5592 | uint32_t HELPER(crc32)(uint32_t acc, uint32_t val, uint32_t bytes) |
5593 | { | |
5594 | uint8_t buf[4]; | |
5595 | ||
aa633469 | 5596 | stl_le_p(buf, val); |
eb0ecd5a WN |
5597 | |
5598 | /* zlib crc32 converts the accumulator and output to one's complement. */ | |
5599 | return crc32(acc ^ 0xffffffff, buf, bytes) ^ 0xffffffff; | |
5600 | } | |
5601 | ||
5602 | uint32_t HELPER(crc32c)(uint32_t acc, uint32_t val, uint32_t bytes) | |
5603 | { | |
5604 | uint8_t buf[4]; | |
5605 | ||
aa633469 | 5606 | stl_le_p(buf, val); |
eb0ecd5a WN |
5607 | |
5608 | /* Linux crc32c converts the output to one's complement. */ | |
5609 | return crc32c(acc, buf, bytes) ^ 0xffffffff; | |
5610 | } |