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Commit | Line | Data |
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b5ff1b31 | 1 | #include "cpu.h" |
ccd38087 | 2 | #include "internals.h" |
022c62cb | 3 | #include "exec/gdbstub.h" |
2ef6175a | 4 | #include "exec/helper-proto.h" |
1de7afc9 | 5 | #include "qemu/host-utils.h" |
78027bb6 | 6 | #include "sysemu/arch_init.h" |
9c17d615 | 7 | #include "sysemu/sysemu.h" |
1de7afc9 | 8 | #include "qemu/bitops.h" |
eb0ecd5a | 9 | #include "qemu/crc32c.h" |
f08b6170 | 10 | #include "exec/cpu_ldst.h" |
1d854765 | 11 | #include "arm_ldst.h" |
eb0ecd5a | 12 | #include <zlib.h> /* For crc32 */ |
0b03bdfc | 13 | |
4a501606 | 14 | #ifndef CONFIG_USER_ONLY |
2c8dd318 | 15 | static inline int get_phys_addr(CPUARMState *env, target_ulong address, |
4a501606 | 16 | int access_type, int is_user, |
a8170e5e | 17 | hwaddr *phys_ptr, int *prot, |
4a501606 | 18 | target_ulong *page_size); |
7c2cb42b AF |
19 | |
20 | /* Definitions for the PMCCNTR and PMCR registers */ | |
21 | #define PMCRD 0x8 | |
22 | #define PMCRC 0x4 | |
23 | #define PMCRE 0x1 | |
4a501606 PM |
24 | #endif |
25 | ||
0ecb72a5 | 26 | static int vfp_gdb_get_reg(CPUARMState *env, uint8_t *buf, int reg) |
56aebc89 PB |
27 | { |
28 | int nregs; | |
29 | ||
30 | /* VFP data registers are always little-endian. */ | |
31 | nregs = arm_feature(env, ARM_FEATURE_VFP3) ? 32 : 16; | |
32 | if (reg < nregs) { | |
33 | stfq_le_p(buf, env->vfp.regs[reg]); | |
34 | return 8; | |
35 | } | |
36 | if (arm_feature(env, ARM_FEATURE_NEON)) { | |
37 | /* Aliases for Q regs. */ | |
38 | nregs += 16; | |
39 | if (reg < nregs) { | |
40 | stfq_le_p(buf, env->vfp.regs[(reg - 32) * 2]); | |
41 | stfq_le_p(buf + 8, env->vfp.regs[(reg - 32) * 2 + 1]); | |
42 | return 16; | |
43 | } | |
44 | } | |
45 | switch (reg - nregs) { | |
46 | case 0: stl_p(buf, env->vfp.xregs[ARM_VFP_FPSID]); return 4; | |
47 | case 1: stl_p(buf, env->vfp.xregs[ARM_VFP_FPSCR]); return 4; | |
48 | case 2: stl_p(buf, env->vfp.xregs[ARM_VFP_FPEXC]); return 4; | |
49 | } | |
50 | return 0; | |
51 | } | |
52 | ||
0ecb72a5 | 53 | static int vfp_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg) |
56aebc89 PB |
54 | { |
55 | int nregs; | |
56 | ||
57 | nregs = arm_feature(env, ARM_FEATURE_VFP3) ? 32 : 16; | |
58 | if (reg < nregs) { | |
59 | env->vfp.regs[reg] = ldfq_le_p(buf); | |
60 | return 8; | |
61 | } | |
62 | if (arm_feature(env, ARM_FEATURE_NEON)) { | |
63 | nregs += 16; | |
64 | if (reg < nregs) { | |
65 | env->vfp.regs[(reg - 32) * 2] = ldfq_le_p(buf); | |
66 | env->vfp.regs[(reg - 32) * 2 + 1] = ldfq_le_p(buf + 8); | |
67 | return 16; | |
68 | } | |
69 | } | |
70 | switch (reg - nregs) { | |
71 | case 0: env->vfp.xregs[ARM_VFP_FPSID] = ldl_p(buf); return 4; | |
72 | case 1: env->vfp.xregs[ARM_VFP_FPSCR] = ldl_p(buf); return 4; | |
71b3c3de | 73 | case 2: env->vfp.xregs[ARM_VFP_FPEXC] = ldl_p(buf) & (1 << 30); return 4; |
56aebc89 PB |
74 | } |
75 | return 0; | |
76 | } | |
77 | ||
6a669427 PM |
78 | static int aarch64_fpu_gdb_get_reg(CPUARMState *env, uint8_t *buf, int reg) |
79 | { | |
80 | switch (reg) { | |
81 | case 0 ... 31: | |
82 | /* 128 bit FP register */ | |
83 | stfq_le_p(buf, env->vfp.regs[reg * 2]); | |
84 | stfq_le_p(buf + 8, env->vfp.regs[reg * 2 + 1]); | |
85 | return 16; | |
86 | case 32: | |
87 | /* FPSR */ | |
88 | stl_p(buf, vfp_get_fpsr(env)); | |
89 | return 4; | |
90 | case 33: | |
91 | /* FPCR */ | |
92 | stl_p(buf, vfp_get_fpcr(env)); | |
93 | return 4; | |
94 | default: | |
95 | return 0; | |
96 | } | |
97 | } | |
98 | ||
99 | static int aarch64_fpu_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg) | |
100 | { | |
101 | switch (reg) { | |
102 | case 0 ... 31: | |
103 | /* 128 bit FP register */ | |
104 | env->vfp.regs[reg * 2] = ldfq_le_p(buf); | |
105 | env->vfp.regs[reg * 2 + 1] = ldfq_le_p(buf + 8); | |
106 | return 16; | |
107 | case 32: | |
108 | /* FPSR */ | |
109 | vfp_set_fpsr(env, ldl_p(buf)); | |
110 | return 4; | |
111 | case 33: | |
112 | /* FPCR */ | |
113 | vfp_set_fpcr(env, ldl_p(buf)); | |
114 | return 4; | |
115 | default: | |
116 | return 0; | |
117 | } | |
118 | } | |
119 | ||
c4241c7d | 120 | static uint64_t raw_read(CPUARMState *env, const ARMCPRegInfo *ri) |
d4e6df63 | 121 | { |
67ed771d | 122 | if (cpreg_field_is_64bit(ri)) { |
c4241c7d | 123 | return CPREG_FIELD64(env, ri); |
22d9e1a9 | 124 | } else { |
c4241c7d | 125 | return CPREG_FIELD32(env, ri); |
22d9e1a9 | 126 | } |
d4e6df63 PM |
127 | } |
128 | ||
c4241c7d PM |
129 | static void raw_write(CPUARMState *env, const ARMCPRegInfo *ri, |
130 | uint64_t value) | |
d4e6df63 | 131 | { |
67ed771d | 132 | if (cpreg_field_is_64bit(ri)) { |
22d9e1a9 PM |
133 | CPREG_FIELD64(env, ri) = value; |
134 | } else { | |
135 | CPREG_FIELD32(env, ri) = value; | |
136 | } | |
d4e6df63 PM |
137 | } |
138 | ||
11f136ee FA |
139 | static void *raw_ptr(CPUARMState *env, const ARMCPRegInfo *ri) |
140 | { | |
141 | return (char *)env + ri->fieldoffset; | |
142 | } | |
143 | ||
59a1c327 | 144 | static uint64_t read_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri) |
721fae12 | 145 | { |
59a1c327 | 146 | /* Raw read of a coprocessor register (as needed for migration, etc). */ |
721fae12 | 147 | if (ri->type & ARM_CP_CONST) { |
59a1c327 | 148 | return ri->resetvalue; |
721fae12 | 149 | } else if (ri->raw_readfn) { |
59a1c327 | 150 | return ri->raw_readfn(env, ri); |
721fae12 | 151 | } else if (ri->readfn) { |
59a1c327 | 152 | return ri->readfn(env, ri); |
721fae12 | 153 | } else { |
59a1c327 | 154 | return raw_read(env, ri); |
721fae12 | 155 | } |
721fae12 PM |
156 | } |
157 | ||
59a1c327 | 158 | static void write_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri, |
7900e9f1 | 159 | uint64_t v) |
721fae12 PM |
160 | { |
161 | /* Raw write of a coprocessor register (as needed for migration, etc). | |
721fae12 PM |
162 | * Note that constant registers are treated as write-ignored; the |
163 | * caller should check for success by whether a readback gives the | |
164 | * value written. | |
165 | */ | |
166 | if (ri->type & ARM_CP_CONST) { | |
59a1c327 | 167 | return; |
721fae12 | 168 | } else if (ri->raw_writefn) { |
c4241c7d | 169 | ri->raw_writefn(env, ri, v); |
721fae12 | 170 | } else if (ri->writefn) { |
c4241c7d | 171 | ri->writefn(env, ri, v); |
721fae12 | 172 | } else { |
afb2530f | 173 | raw_write(env, ri, v); |
721fae12 | 174 | } |
721fae12 PM |
175 | } |
176 | ||
177 | bool write_cpustate_to_list(ARMCPU *cpu) | |
178 | { | |
179 | /* Write the coprocessor state from cpu->env to the (index,value) list. */ | |
180 | int i; | |
181 | bool ok = true; | |
182 | ||
183 | for (i = 0; i < cpu->cpreg_array_len; i++) { | |
184 | uint32_t regidx = kvm_to_cpreg_id(cpu->cpreg_indexes[i]); | |
185 | const ARMCPRegInfo *ri; | |
59a1c327 | 186 | |
60322b39 | 187 | ri = get_arm_cp_reginfo(cpu->cp_regs, regidx); |
721fae12 PM |
188 | if (!ri) { |
189 | ok = false; | |
190 | continue; | |
191 | } | |
192 | if (ri->type & ARM_CP_NO_MIGRATE) { | |
193 | continue; | |
194 | } | |
59a1c327 | 195 | cpu->cpreg_values[i] = read_raw_cp_reg(&cpu->env, ri); |
721fae12 PM |
196 | } |
197 | return ok; | |
198 | } | |
199 | ||
200 | bool write_list_to_cpustate(ARMCPU *cpu) | |
201 | { | |
202 | int i; | |
203 | bool ok = true; | |
204 | ||
205 | for (i = 0; i < cpu->cpreg_array_len; i++) { | |
206 | uint32_t regidx = kvm_to_cpreg_id(cpu->cpreg_indexes[i]); | |
207 | uint64_t v = cpu->cpreg_values[i]; | |
721fae12 PM |
208 | const ARMCPRegInfo *ri; |
209 | ||
60322b39 | 210 | ri = get_arm_cp_reginfo(cpu->cp_regs, regidx); |
721fae12 PM |
211 | if (!ri) { |
212 | ok = false; | |
213 | continue; | |
214 | } | |
215 | if (ri->type & ARM_CP_NO_MIGRATE) { | |
216 | continue; | |
217 | } | |
218 | /* Write value and confirm it reads back as written | |
219 | * (to catch read-only registers and partially read-only | |
220 | * registers where the incoming migration value doesn't match) | |
221 | */ | |
59a1c327 PM |
222 | write_raw_cp_reg(&cpu->env, ri, v); |
223 | if (read_raw_cp_reg(&cpu->env, ri) != v) { | |
721fae12 PM |
224 | ok = false; |
225 | } | |
226 | } | |
227 | return ok; | |
228 | } | |
229 | ||
230 | static void add_cpreg_to_list(gpointer key, gpointer opaque) | |
231 | { | |
232 | ARMCPU *cpu = opaque; | |
233 | uint64_t regidx; | |
234 | const ARMCPRegInfo *ri; | |
235 | ||
236 | regidx = *(uint32_t *)key; | |
60322b39 | 237 | ri = get_arm_cp_reginfo(cpu->cp_regs, regidx); |
721fae12 PM |
238 | |
239 | if (!(ri->type & ARM_CP_NO_MIGRATE)) { | |
240 | cpu->cpreg_indexes[cpu->cpreg_array_len] = cpreg_to_kvm_id(regidx); | |
241 | /* The value array need not be initialized at this point */ | |
242 | cpu->cpreg_array_len++; | |
243 | } | |
244 | } | |
245 | ||
246 | static void count_cpreg(gpointer key, gpointer opaque) | |
247 | { | |
248 | ARMCPU *cpu = opaque; | |
249 | uint64_t regidx; | |
250 | const ARMCPRegInfo *ri; | |
251 | ||
252 | regidx = *(uint32_t *)key; | |
60322b39 | 253 | ri = get_arm_cp_reginfo(cpu->cp_regs, regidx); |
721fae12 PM |
254 | |
255 | if (!(ri->type & ARM_CP_NO_MIGRATE)) { | |
256 | cpu->cpreg_array_len++; | |
257 | } | |
258 | } | |
259 | ||
260 | static gint cpreg_key_compare(gconstpointer a, gconstpointer b) | |
261 | { | |
cbf239b7 AR |
262 | uint64_t aidx = cpreg_to_kvm_id(*(uint32_t *)a); |
263 | uint64_t bidx = cpreg_to_kvm_id(*(uint32_t *)b); | |
721fae12 | 264 | |
cbf239b7 AR |
265 | if (aidx > bidx) { |
266 | return 1; | |
267 | } | |
268 | if (aidx < bidx) { | |
269 | return -1; | |
270 | } | |
271 | return 0; | |
721fae12 PM |
272 | } |
273 | ||
82a3a118 PM |
274 | static void cpreg_make_keylist(gpointer key, gpointer value, gpointer udata) |
275 | { | |
276 | GList **plist = udata; | |
277 | ||
278 | *plist = g_list_prepend(*plist, key); | |
279 | } | |
280 | ||
721fae12 PM |
281 | void init_cpreg_list(ARMCPU *cpu) |
282 | { | |
283 | /* Initialise the cpreg_tuples[] array based on the cp_regs hash. | |
284 | * Note that we require cpreg_tuples[] to be sorted by key ID. | |
285 | */ | |
82a3a118 | 286 | GList *keys = NULL; |
721fae12 PM |
287 | int arraylen; |
288 | ||
82a3a118 PM |
289 | g_hash_table_foreach(cpu->cp_regs, cpreg_make_keylist, &keys); |
290 | ||
721fae12 PM |
291 | keys = g_list_sort(keys, cpreg_key_compare); |
292 | ||
293 | cpu->cpreg_array_len = 0; | |
294 | ||
295 | g_list_foreach(keys, count_cpreg, cpu); | |
296 | ||
297 | arraylen = cpu->cpreg_array_len; | |
298 | cpu->cpreg_indexes = g_new(uint64_t, arraylen); | |
299 | cpu->cpreg_values = g_new(uint64_t, arraylen); | |
300 | cpu->cpreg_vmstate_indexes = g_new(uint64_t, arraylen); | |
301 | cpu->cpreg_vmstate_values = g_new(uint64_t, arraylen); | |
302 | cpu->cpreg_vmstate_array_len = cpu->cpreg_array_len; | |
303 | cpu->cpreg_array_len = 0; | |
304 | ||
305 | g_list_foreach(keys, add_cpreg_to_list, cpu); | |
306 | ||
307 | assert(cpu->cpreg_array_len == arraylen); | |
308 | ||
309 | g_list_free(keys); | |
310 | } | |
311 | ||
c4241c7d | 312 | static void dacr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) |
c983fe6c | 313 | { |
00c8cb0a AF |
314 | ARMCPU *cpu = arm_env_get_cpu(env); |
315 | ||
8d5c773e | 316 | raw_write(env, ri, value); |
00c8cb0a | 317 | tlb_flush(CPU(cpu), 1); /* Flush TLB as domain not tracked in TLB */ |
c983fe6c PM |
318 | } |
319 | ||
c4241c7d | 320 | static void fcse_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) |
08de207b | 321 | { |
00c8cb0a AF |
322 | ARMCPU *cpu = arm_env_get_cpu(env); |
323 | ||
8d5c773e | 324 | if (raw_read(env, ri) != value) { |
08de207b PM |
325 | /* Unlike real hardware the qemu TLB uses virtual addresses, |
326 | * not modified virtual addresses, so this causes a TLB flush. | |
327 | */ | |
00c8cb0a | 328 | tlb_flush(CPU(cpu), 1); |
8d5c773e | 329 | raw_write(env, ri, value); |
08de207b | 330 | } |
08de207b | 331 | } |
c4241c7d PM |
332 | |
333 | static void contextidr_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
334 | uint64_t value) | |
08de207b | 335 | { |
00c8cb0a AF |
336 | ARMCPU *cpu = arm_env_get_cpu(env); |
337 | ||
8d5c773e | 338 | if (raw_read(env, ri) != value && !arm_feature(env, ARM_FEATURE_MPU) |
014406b5 | 339 | && !extended_addresses_enabled(env)) { |
08de207b PM |
340 | /* For VMSA (when not using the LPAE long descriptor page table |
341 | * format) this register includes the ASID, so do a TLB flush. | |
342 | * For PMSA it is purely a process ID and no action is needed. | |
343 | */ | |
00c8cb0a | 344 | tlb_flush(CPU(cpu), 1); |
08de207b | 345 | } |
8d5c773e | 346 | raw_write(env, ri, value); |
08de207b PM |
347 | } |
348 | ||
c4241c7d PM |
349 | static void tlbiall_write(CPUARMState *env, const ARMCPRegInfo *ri, |
350 | uint64_t value) | |
d929823f PM |
351 | { |
352 | /* Invalidate all (TLBIALL) */ | |
00c8cb0a AF |
353 | ARMCPU *cpu = arm_env_get_cpu(env); |
354 | ||
355 | tlb_flush(CPU(cpu), 1); | |
d929823f PM |
356 | } |
357 | ||
c4241c7d PM |
358 | static void tlbimva_write(CPUARMState *env, const ARMCPRegInfo *ri, |
359 | uint64_t value) | |
d929823f PM |
360 | { |
361 | /* Invalidate single TLB entry by MVA and ASID (TLBIMVA) */ | |
31b030d4 AF |
362 | ARMCPU *cpu = arm_env_get_cpu(env); |
363 | ||
364 | tlb_flush_page(CPU(cpu), value & TARGET_PAGE_MASK); | |
d929823f PM |
365 | } |
366 | ||
c4241c7d PM |
367 | static void tlbiasid_write(CPUARMState *env, const ARMCPRegInfo *ri, |
368 | uint64_t value) | |
d929823f PM |
369 | { |
370 | /* Invalidate by ASID (TLBIASID) */ | |
00c8cb0a AF |
371 | ARMCPU *cpu = arm_env_get_cpu(env); |
372 | ||
373 | tlb_flush(CPU(cpu), value == 0); | |
d929823f PM |
374 | } |
375 | ||
c4241c7d PM |
376 | static void tlbimvaa_write(CPUARMState *env, const ARMCPRegInfo *ri, |
377 | uint64_t value) | |
d929823f PM |
378 | { |
379 | /* Invalidate single entry by MVA, all ASIDs (TLBIMVAA) */ | |
31b030d4 AF |
380 | ARMCPU *cpu = arm_env_get_cpu(env); |
381 | ||
382 | tlb_flush_page(CPU(cpu), value & TARGET_PAGE_MASK); | |
d929823f PM |
383 | } |
384 | ||
fa439fc5 PM |
385 | /* IS variants of TLB operations must affect all cores */ |
386 | static void tlbiall_is_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
387 | uint64_t value) | |
388 | { | |
389 | CPUState *other_cs; | |
390 | ||
391 | CPU_FOREACH(other_cs) { | |
392 | tlb_flush(other_cs, 1); | |
393 | } | |
394 | } | |
395 | ||
396 | static void tlbiasid_is_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
397 | uint64_t value) | |
398 | { | |
399 | CPUState *other_cs; | |
400 | ||
401 | CPU_FOREACH(other_cs) { | |
402 | tlb_flush(other_cs, value == 0); | |
403 | } | |
404 | } | |
405 | ||
406 | static void tlbimva_is_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
407 | uint64_t value) | |
408 | { | |
409 | CPUState *other_cs; | |
410 | ||
411 | CPU_FOREACH(other_cs) { | |
412 | tlb_flush_page(other_cs, value & TARGET_PAGE_MASK); | |
413 | } | |
414 | } | |
415 | ||
416 | static void tlbimvaa_is_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
417 | uint64_t value) | |
418 | { | |
419 | CPUState *other_cs; | |
420 | ||
421 | CPU_FOREACH(other_cs) { | |
422 | tlb_flush_page(other_cs, value & TARGET_PAGE_MASK); | |
423 | } | |
424 | } | |
425 | ||
e9aa6c21 | 426 | static const ARMCPRegInfo cp_reginfo[] = { |
54bf36ed FA |
427 | /* Define the secure and non-secure FCSE identifier CP registers |
428 | * separately because there is no secure bank in V8 (no _EL3). This allows | |
429 | * the secure register to be properly reset and migrated. There is also no | |
430 | * v8 EL1 version of the register so the non-secure instance stands alone. | |
431 | */ | |
432 | { .name = "FCSEIDR(NS)", | |
433 | .cp = 15, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 0, | |
434 | .access = PL1_RW, .secure = ARM_CP_SECSTATE_NS, | |
435 | .fieldoffset = offsetof(CPUARMState, cp15.fcseidr_ns), | |
436 | .resetvalue = 0, .writefn = fcse_write, .raw_writefn = raw_write, }, | |
437 | { .name = "FCSEIDR(S)", | |
438 | .cp = 15, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 0, | |
439 | .access = PL1_RW, .secure = ARM_CP_SECSTATE_S, | |
440 | .fieldoffset = offsetof(CPUARMState, cp15.fcseidr_s), | |
d4e6df63 | 441 | .resetvalue = 0, .writefn = fcse_write, .raw_writefn = raw_write, }, |
54bf36ed FA |
442 | /* Define the secure and non-secure context identifier CP registers |
443 | * separately because there is no secure bank in V8 (no _EL3). This allows | |
444 | * the secure register to be properly reset and migrated. In the | |
445 | * non-secure case, the 32-bit register will have reset and migration | |
446 | * disabled during registration as it is handled by the 64-bit instance. | |
447 | */ | |
448 | { .name = "CONTEXTIDR_EL1", .state = ARM_CP_STATE_BOTH, | |
014406b5 | 449 | .opc0 = 3, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 1, |
54bf36ed FA |
450 | .access = PL1_RW, .secure = ARM_CP_SECSTATE_NS, |
451 | .fieldoffset = offsetof(CPUARMState, cp15.contextidr_el[1]), | |
452 | .resetvalue = 0, .writefn = contextidr_write, .raw_writefn = raw_write, }, | |
453 | { .name = "CONTEXTIDR(S)", .state = ARM_CP_STATE_AA32, | |
454 | .cp = 15, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 1, | |
455 | .access = PL1_RW, .secure = ARM_CP_SECSTATE_S, | |
456 | .fieldoffset = offsetof(CPUARMState, cp15.contextidr_s), | |
d4e6df63 | 457 | .resetvalue = 0, .writefn = contextidr_write, .raw_writefn = raw_write, }, |
9449fdf6 PM |
458 | REGINFO_SENTINEL |
459 | }; | |
460 | ||
461 | static const ARMCPRegInfo not_v8_cp_reginfo[] = { | |
462 | /* NB: Some of these registers exist in v8 but with more precise | |
463 | * definitions that don't use CP_ANY wildcards (mostly in v8_cp_reginfo[]). | |
464 | */ | |
465 | /* MMU Domain access control / MPU write buffer control */ | |
0c17d68c FA |
466 | { .name = "DACR", |
467 | .cp = 15, .opc1 = CP_ANY, .crn = 3, .crm = CP_ANY, .opc2 = CP_ANY, | |
468 | .access = PL1_RW, .resetvalue = 0, | |
469 | .writefn = dacr_write, .raw_writefn = raw_write, | |
470 | .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.dacr_s), | |
471 | offsetoflow32(CPUARMState, cp15.dacr_ns) } }, | |
4fdd17dd PM |
472 | /* ??? This covers not just the impdef TLB lockdown registers but also |
473 | * some v7VMSA registers relating to TEX remap, so it is overly broad. | |
474 | */ | |
475 | { .name = "TLB_LOCKDOWN", .cp = 15, .crn = 10, .crm = CP_ANY, | |
476 | .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_NOP }, | |
c4804214 PM |
477 | /* Cache maintenance ops; some of this space may be overridden later. */ |
478 | { .name = "CACHEMAINT", .cp = 15, .crn = 7, .crm = CP_ANY, | |
479 | .opc1 = 0, .opc2 = CP_ANY, .access = PL1_W, | |
480 | .type = ARM_CP_NOP | ARM_CP_OVERRIDE }, | |
e9aa6c21 PM |
481 | REGINFO_SENTINEL |
482 | }; | |
483 | ||
7d57f408 PM |
484 | static const ARMCPRegInfo not_v6_cp_reginfo[] = { |
485 | /* Not all pre-v6 cores implemented this WFI, so this is slightly | |
486 | * over-broad. | |
487 | */ | |
488 | { .name = "WFI_v5", .cp = 15, .crn = 7, .crm = 8, .opc1 = 0, .opc2 = 2, | |
489 | .access = PL1_W, .type = ARM_CP_WFI }, | |
490 | REGINFO_SENTINEL | |
491 | }; | |
492 | ||
493 | static const ARMCPRegInfo not_v7_cp_reginfo[] = { | |
494 | /* Standard v6 WFI (also used in some pre-v6 cores); not in v7 (which | |
495 | * is UNPREDICTABLE; we choose to NOP as most implementations do). | |
496 | */ | |
497 | { .name = "WFI_v6", .cp = 15, .crn = 7, .crm = 0, .opc1 = 0, .opc2 = 4, | |
498 | .access = PL1_W, .type = ARM_CP_WFI }, | |
34f90529 PM |
499 | /* L1 cache lockdown. Not architectural in v6 and earlier but in practice |
500 | * implemented in 926, 946, 1026, 1136, 1176 and 11MPCore. StrongARM and | |
501 | * OMAPCP will override this space. | |
502 | */ | |
503 | { .name = "DLOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 0, .opc2 = 0, | |
504 | .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_data), | |
505 | .resetvalue = 0 }, | |
506 | { .name = "ILOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 0, .opc2 = 1, | |
507 | .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_insn), | |
508 | .resetvalue = 0 }, | |
776d4e5c PM |
509 | /* v6 doesn't have the cache ID registers but Linux reads them anyway */ |
510 | { .name = "DUMMY", .cp = 15, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = CP_ANY, | |
d4e6df63 PM |
511 | .access = PL1_R, .type = ARM_CP_CONST | ARM_CP_NO_MIGRATE, |
512 | .resetvalue = 0 }, | |
50300698 PM |
513 | /* We don't implement pre-v7 debug but most CPUs had at least a DBGDIDR; |
514 | * implementing it as RAZ means the "debug architecture version" bits | |
515 | * will read as a reserved value, which should cause Linux to not try | |
516 | * to use the debug hardware. | |
517 | */ | |
518 | { .name = "DBGDIDR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 0, | |
519 | .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
995939a6 PM |
520 | /* MMU TLB control. Note that the wildcarding means we cover not just |
521 | * the unified TLB ops but also the dside/iside/inner-shareable variants. | |
522 | */ | |
523 | { .name = "TLBIALL", .cp = 15, .crn = 8, .crm = CP_ANY, | |
524 | .opc1 = CP_ANY, .opc2 = 0, .access = PL1_W, .writefn = tlbiall_write, | |
525 | .type = ARM_CP_NO_MIGRATE }, | |
526 | { .name = "TLBIMVA", .cp = 15, .crn = 8, .crm = CP_ANY, | |
527 | .opc1 = CP_ANY, .opc2 = 1, .access = PL1_W, .writefn = tlbimva_write, | |
528 | .type = ARM_CP_NO_MIGRATE }, | |
529 | { .name = "TLBIASID", .cp = 15, .crn = 8, .crm = CP_ANY, | |
530 | .opc1 = CP_ANY, .opc2 = 2, .access = PL1_W, .writefn = tlbiasid_write, | |
531 | .type = ARM_CP_NO_MIGRATE }, | |
532 | { .name = "TLBIMVAA", .cp = 15, .crn = 8, .crm = CP_ANY, | |
533 | .opc1 = CP_ANY, .opc2 = 3, .access = PL1_W, .writefn = tlbimvaa_write, | |
534 | .type = ARM_CP_NO_MIGRATE }, | |
7d57f408 PM |
535 | REGINFO_SENTINEL |
536 | }; | |
537 | ||
c4241c7d PM |
538 | static void cpacr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
539 | uint64_t value) | |
2771db27 | 540 | { |
f0aff255 FA |
541 | uint32_t mask = 0; |
542 | ||
543 | /* In ARMv8 most bits of CPACR_EL1 are RES0. */ | |
544 | if (!arm_feature(env, ARM_FEATURE_V8)) { | |
545 | /* ARMv7 defines bits for unimplemented coprocessors as RAZ/WI. | |
546 | * ASEDIS [31] and D32DIS [30] are both UNK/SBZP without VFP. | |
547 | * TRCDIS [28] is RAZ/WI since we do not implement a trace macrocell. | |
548 | */ | |
549 | if (arm_feature(env, ARM_FEATURE_VFP)) { | |
550 | /* VFP coprocessor: cp10 & cp11 [23:20] */ | |
551 | mask |= (1 << 31) | (1 << 30) | (0xf << 20); | |
552 | ||
553 | if (!arm_feature(env, ARM_FEATURE_NEON)) { | |
554 | /* ASEDIS [31] bit is RAO/WI */ | |
555 | value |= (1 << 31); | |
556 | } | |
557 | ||
558 | /* VFPv3 and upwards with NEON implement 32 double precision | |
559 | * registers (D0-D31). | |
560 | */ | |
561 | if (!arm_feature(env, ARM_FEATURE_NEON) || | |
562 | !arm_feature(env, ARM_FEATURE_VFP3)) { | |
563 | /* D32DIS [30] is RAO/WI if D16-31 are not implemented. */ | |
564 | value |= (1 << 30); | |
565 | } | |
566 | } | |
567 | value &= mask; | |
2771db27 | 568 | } |
f0aff255 | 569 | env->cp15.c1_coproc = value; |
2771db27 PM |
570 | } |
571 | ||
7d57f408 PM |
572 | static const ARMCPRegInfo v6_cp_reginfo[] = { |
573 | /* prefetch by MVA in v6, NOP in v7 */ | |
574 | { .name = "MVA_prefetch", | |
575 | .cp = 15, .crn = 7, .crm = 13, .opc1 = 0, .opc2 = 1, | |
576 | .access = PL1_W, .type = ARM_CP_NOP }, | |
577 | { .name = "ISB", .cp = 15, .crn = 7, .crm = 5, .opc1 = 0, .opc2 = 4, | |
578 | .access = PL0_W, .type = ARM_CP_NOP }, | |
091fd17c | 579 | { .name = "DSB", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 4, |
7d57f408 | 580 | .access = PL0_W, .type = ARM_CP_NOP }, |
091fd17c | 581 | { .name = "DMB", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 5, |
7d57f408 | 582 | .access = PL0_W, .type = ARM_CP_NOP }, |
06d76f31 | 583 | { .name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 2, |
6cd8a264 | 584 | .access = PL1_RW, |
b848ce2b FA |
585 | .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ifar_s), |
586 | offsetof(CPUARMState, cp15.ifar_ns) }, | |
06d76f31 PM |
587 | .resetvalue = 0, }, |
588 | /* Watchpoint Fault Address Register : should actually only be present | |
589 | * for 1136, 1176, 11MPCore. | |
590 | */ | |
591 | { .name = "WFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1, | |
592 | .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0, }, | |
34222fb8 PM |
593 | { .name = "CPACR", .state = ARM_CP_STATE_BOTH, .opc0 = 3, |
594 | .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 2, | |
2771db27 PM |
595 | .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c1_coproc), |
596 | .resetvalue = 0, .writefn = cpacr_write }, | |
7d57f408 PM |
597 | REGINFO_SENTINEL |
598 | }; | |
599 | ||
fcd25206 | 600 | static CPAccessResult pmreg_access(CPUARMState *env, const ARMCPRegInfo *ri) |
200ac0ef | 601 | { |
3b163b01 | 602 | /* Performance monitor registers user accessibility is controlled |
fcd25206 | 603 | * by PMUSERENR. |
200ac0ef | 604 | */ |
dcbff19b | 605 | if (arm_current_el(env) == 0 && !env->cp15.c9_pmuserenr) { |
fcd25206 | 606 | return CP_ACCESS_TRAP; |
200ac0ef | 607 | } |
fcd25206 | 608 | return CP_ACCESS_OK; |
200ac0ef PM |
609 | } |
610 | ||
7c2cb42b | 611 | #ifndef CONFIG_USER_ONLY |
87124fde AF |
612 | |
613 | static inline bool arm_ccnt_enabled(CPUARMState *env) | |
614 | { | |
615 | /* This does not support checking PMCCFILTR_EL0 register */ | |
616 | ||
617 | if (!(env->cp15.c9_pmcr & PMCRE)) { | |
618 | return false; | |
619 | } | |
620 | ||
621 | return true; | |
622 | } | |
623 | ||
ec7b4ce4 AF |
624 | void pmccntr_sync(CPUARMState *env) |
625 | { | |
626 | uint64_t temp_ticks; | |
627 | ||
628 | temp_ticks = muldiv64(qemu_clock_get_us(QEMU_CLOCK_VIRTUAL), | |
629 | get_ticks_per_sec(), 1000000); | |
630 | ||
631 | if (env->cp15.c9_pmcr & PMCRD) { | |
632 | /* Increment once every 64 processor clock cycles */ | |
633 | temp_ticks /= 64; | |
634 | } | |
635 | ||
636 | if (arm_ccnt_enabled(env)) { | |
637 | env->cp15.c15_ccnt = temp_ticks - env->cp15.c15_ccnt; | |
638 | } | |
639 | } | |
640 | ||
c4241c7d PM |
641 | static void pmcr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
642 | uint64_t value) | |
200ac0ef | 643 | { |
942a155b | 644 | pmccntr_sync(env); |
7c2cb42b AF |
645 | |
646 | if (value & PMCRC) { | |
647 | /* The counter has been reset */ | |
648 | env->cp15.c15_ccnt = 0; | |
649 | } | |
650 | ||
200ac0ef PM |
651 | /* only the DP, X, D and E bits are writable */ |
652 | env->cp15.c9_pmcr &= ~0x39; | |
653 | env->cp15.c9_pmcr |= (value & 0x39); | |
7c2cb42b | 654 | |
942a155b | 655 | pmccntr_sync(env); |
7c2cb42b AF |
656 | } |
657 | ||
658 | static uint64_t pmccntr_read(CPUARMState *env, const ARMCPRegInfo *ri) | |
659 | { | |
c92c0687 | 660 | uint64_t total_ticks; |
7c2cb42b | 661 | |
942a155b | 662 | if (!arm_ccnt_enabled(env)) { |
7c2cb42b AF |
663 | /* Counter is disabled, do not change value */ |
664 | return env->cp15.c15_ccnt; | |
665 | } | |
666 | ||
c92c0687 AF |
667 | total_ticks = muldiv64(qemu_clock_get_us(QEMU_CLOCK_VIRTUAL), |
668 | get_ticks_per_sec(), 1000000); | |
7c2cb42b AF |
669 | |
670 | if (env->cp15.c9_pmcr & PMCRD) { | |
671 | /* Increment once every 64 processor clock cycles */ | |
672 | total_ticks /= 64; | |
673 | } | |
674 | return total_ticks - env->cp15.c15_ccnt; | |
675 | } | |
676 | ||
677 | static void pmccntr_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
678 | uint64_t value) | |
679 | { | |
c92c0687 | 680 | uint64_t total_ticks; |
7c2cb42b | 681 | |
942a155b | 682 | if (!arm_ccnt_enabled(env)) { |
7c2cb42b AF |
683 | /* Counter is disabled, set the absolute value */ |
684 | env->cp15.c15_ccnt = value; | |
685 | return; | |
686 | } | |
687 | ||
c92c0687 AF |
688 | total_ticks = muldiv64(qemu_clock_get_us(QEMU_CLOCK_VIRTUAL), |
689 | get_ticks_per_sec(), 1000000); | |
7c2cb42b AF |
690 | |
691 | if (env->cp15.c9_pmcr & PMCRD) { | |
692 | /* Increment once every 64 processor clock cycles */ | |
693 | total_ticks /= 64; | |
694 | } | |
695 | env->cp15.c15_ccnt = total_ticks - value; | |
200ac0ef | 696 | } |
421c7ebd PC |
697 | |
698 | static void pmccntr_write32(CPUARMState *env, const ARMCPRegInfo *ri, | |
699 | uint64_t value) | |
700 | { | |
701 | uint64_t cur_val = pmccntr_read(env, NULL); | |
702 | ||
703 | pmccntr_write(env, ri, deposit64(cur_val, 0, 32, value)); | |
704 | } | |
705 | ||
ec7b4ce4 AF |
706 | #else /* CONFIG_USER_ONLY */ |
707 | ||
708 | void pmccntr_sync(CPUARMState *env) | |
709 | { | |
710 | } | |
711 | ||
7c2cb42b | 712 | #endif |
200ac0ef | 713 | |
0614601c AF |
714 | static void pmccfiltr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
715 | uint64_t value) | |
716 | { | |
717 | pmccntr_sync(env); | |
718 | env->cp15.pmccfiltr_el0 = value & 0x7E000000; | |
719 | pmccntr_sync(env); | |
720 | } | |
721 | ||
c4241c7d | 722 | static void pmcntenset_write(CPUARMState *env, const ARMCPRegInfo *ri, |
200ac0ef PM |
723 | uint64_t value) |
724 | { | |
200ac0ef PM |
725 | value &= (1 << 31); |
726 | env->cp15.c9_pmcnten |= value; | |
200ac0ef PM |
727 | } |
728 | ||
c4241c7d PM |
729 | static void pmcntenclr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
730 | uint64_t value) | |
200ac0ef | 731 | { |
200ac0ef PM |
732 | value &= (1 << 31); |
733 | env->cp15.c9_pmcnten &= ~value; | |
200ac0ef PM |
734 | } |
735 | ||
c4241c7d PM |
736 | static void pmovsr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
737 | uint64_t value) | |
200ac0ef | 738 | { |
200ac0ef | 739 | env->cp15.c9_pmovsr &= ~value; |
200ac0ef PM |
740 | } |
741 | ||
c4241c7d PM |
742 | static void pmxevtyper_write(CPUARMState *env, const ARMCPRegInfo *ri, |
743 | uint64_t value) | |
200ac0ef | 744 | { |
200ac0ef | 745 | env->cp15.c9_pmxevtyper = value & 0xff; |
200ac0ef PM |
746 | } |
747 | ||
c4241c7d | 748 | static void pmuserenr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
200ac0ef PM |
749 | uint64_t value) |
750 | { | |
751 | env->cp15.c9_pmuserenr = value & 1; | |
200ac0ef PM |
752 | } |
753 | ||
c4241c7d PM |
754 | static void pmintenset_write(CPUARMState *env, const ARMCPRegInfo *ri, |
755 | uint64_t value) | |
200ac0ef PM |
756 | { |
757 | /* We have no event counters so only the C bit can be changed */ | |
758 | value &= (1 << 31); | |
759 | env->cp15.c9_pminten |= value; | |
200ac0ef PM |
760 | } |
761 | ||
c4241c7d PM |
762 | static void pmintenclr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
763 | uint64_t value) | |
200ac0ef PM |
764 | { |
765 | value &= (1 << 31); | |
766 | env->cp15.c9_pminten &= ~value; | |
200ac0ef PM |
767 | } |
768 | ||
c4241c7d PM |
769 | static void vbar_write(CPUARMState *env, const ARMCPRegInfo *ri, |
770 | uint64_t value) | |
8641136c | 771 | { |
a505d7fe PM |
772 | /* Note that even though the AArch64 view of this register has bits |
773 | * [10:0] all RES0 we can only mask the bottom 5, to comply with the | |
774 | * architectural requirements for bits which are RES0 only in some | |
775 | * contexts. (ARMv8 would permit us to do no masking at all, but ARMv7 | |
776 | * requires the bottom five bits to be RAZ/WI because they're UNK/SBZP.) | |
777 | */ | |
855ea66d | 778 | raw_write(env, ri, value & ~0x1FULL); |
8641136c NR |
779 | } |
780 | ||
64e0e2de EI |
781 | static void scr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) |
782 | { | |
783 | /* We only mask off bits that are RES0 both for AArch64 and AArch32. | |
784 | * For bits that vary between AArch32/64, code needs to check the | |
785 | * current execution mode before directly using the feature bit. | |
786 | */ | |
787 | uint32_t valid_mask = SCR_AARCH64_MASK | SCR_AARCH32_MASK; | |
788 | ||
789 | if (!arm_feature(env, ARM_FEATURE_EL2)) { | |
790 | valid_mask &= ~SCR_HCE; | |
791 | ||
792 | /* On ARMv7, SMD (or SCD as it is called in v7) is only | |
793 | * supported if EL2 exists. The bit is UNK/SBZP when | |
794 | * EL2 is unavailable. In QEMU ARMv7, we force it to always zero | |
795 | * when EL2 is unavailable. | |
796 | */ | |
797 | if (arm_feature(env, ARM_FEATURE_V7)) { | |
798 | valid_mask &= ~SCR_SMD; | |
799 | } | |
800 | } | |
801 | ||
802 | /* Clear all-context RES0 bits. */ | |
803 | value &= valid_mask; | |
804 | raw_write(env, ri, value); | |
805 | } | |
806 | ||
c4241c7d | 807 | static uint64_t ccsidr_read(CPUARMState *env, const ARMCPRegInfo *ri) |
776d4e5c PM |
808 | { |
809 | ARMCPU *cpu = arm_env_get_cpu(env); | |
b85a1fd6 FA |
810 | |
811 | /* Acquire the CSSELR index from the bank corresponding to the CCSIDR | |
812 | * bank | |
813 | */ | |
814 | uint32_t index = A32_BANKED_REG_GET(env, csselr, | |
815 | ri->secure & ARM_CP_SECSTATE_S); | |
816 | ||
817 | return cpu->ccsidr[index]; | |
776d4e5c PM |
818 | } |
819 | ||
c4241c7d PM |
820 | static void csselr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
821 | uint64_t value) | |
776d4e5c | 822 | { |
8d5c773e | 823 | raw_write(env, ri, value & 0xf); |
776d4e5c PM |
824 | } |
825 | ||
1090b9c6 PM |
826 | static uint64_t isr_read(CPUARMState *env, const ARMCPRegInfo *ri) |
827 | { | |
828 | CPUState *cs = ENV_GET_CPU(env); | |
829 | uint64_t ret = 0; | |
830 | ||
831 | if (cs->interrupt_request & CPU_INTERRUPT_HARD) { | |
832 | ret |= CPSR_I; | |
833 | } | |
834 | if (cs->interrupt_request & CPU_INTERRUPT_FIQ) { | |
835 | ret |= CPSR_F; | |
836 | } | |
837 | /* External aborts are not possible in QEMU so A bit is always clear */ | |
838 | return ret; | |
839 | } | |
840 | ||
e9aa6c21 | 841 | static const ARMCPRegInfo v7_cp_reginfo[] = { |
7d57f408 PM |
842 | /* the old v6 WFI, UNPREDICTABLE in v7 but we choose to NOP */ |
843 | { .name = "NOP", .cp = 15, .crn = 7, .crm = 0, .opc1 = 0, .opc2 = 4, | |
844 | .access = PL1_W, .type = ARM_CP_NOP }, | |
200ac0ef PM |
845 | /* Performance monitors are implementation defined in v7, |
846 | * but with an ARM recommended set of registers, which we | |
847 | * follow (although we don't actually implement any counters) | |
848 | * | |
849 | * Performance registers fall into three categories: | |
850 | * (a) always UNDEF in PL0, RW in PL1 (PMINTENSET, PMINTENCLR) | |
851 | * (b) RO in PL0 (ie UNDEF on write), RW in PL1 (PMUSERENR) | |
852 | * (c) UNDEF in PL0 if PMUSERENR.EN==0, otherwise accessible (all others) | |
853 | * For the cases controlled by PMUSERENR we must set .access to PL0_RW | |
854 | * or PL0_RO as appropriate and then check PMUSERENR in the helper fn. | |
855 | */ | |
856 | { .name = "PMCNTENSET", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 1, | |
8521466b AF |
857 | .access = PL0_RW, .type = ARM_CP_NO_MIGRATE, |
858 | .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmcnten), | |
fcd25206 PM |
859 | .writefn = pmcntenset_write, |
860 | .accessfn = pmreg_access, | |
861 | .raw_writefn = raw_write }, | |
8521466b AF |
862 | { .name = "PMCNTENSET_EL0", .state = ARM_CP_STATE_AA64, |
863 | .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 1, | |
864 | .access = PL0_RW, .accessfn = pmreg_access, | |
865 | .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcnten), .resetvalue = 0, | |
866 | .writefn = pmcntenset_write, .raw_writefn = raw_write }, | |
200ac0ef | 867 | { .name = "PMCNTENCLR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 2, |
8521466b AF |
868 | .access = PL0_RW, |
869 | .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmcnten), | |
fcd25206 PM |
870 | .accessfn = pmreg_access, |
871 | .writefn = pmcntenclr_write, | |
d4e6df63 | 872 | .type = ARM_CP_NO_MIGRATE }, |
8521466b AF |
873 | { .name = "PMCNTENCLR_EL0", .state = ARM_CP_STATE_AA64, |
874 | .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 2, | |
875 | .access = PL0_RW, .accessfn = pmreg_access, | |
876 | .type = ARM_CP_NO_MIGRATE, | |
877 | .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcnten), | |
878 | .writefn = pmcntenclr_write }, | |
200ac0ef PM |
879 | { .name = "PMOVSR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 3, |
880 | .access = PL0_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_pmovsr), | |
fcd25206 PM |
881 | .accessfn = pmreg_access, |
882 | .writefn = pmovsr_write, | |
883 | .raw_writefn = raw_write }, | |
884 | /* Unimplemented so WI. */ | |
200ac0ef | 885 | { .name = "PMSWINC", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 4, |
fcd25206 | 886 | .access = PL0_W, .accessfn = pmreg_access, .type = ARM_CP_NOP }, |
200ac0ef | 887 | /* Since we don't implement any events, writing to PMSELR is UNPREDICTABLE. |
fcd25206 | 888 | * We choose to RAZ/WI. |
200ac0ef PM |
889 | */ |
890 | { .name = "PMSELR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 5, | |
fcd25206 PM |
891 | .access = PL0_RW, .type = ARM_CP_CONST, .resetvalue = 0, |
892 | .accessfn = pmreg_access }, | |
7c2cb42b | 893 | #ifndef CONFIG_USER_ONLY |
200ac0ef | 894 | { .name = "PMCCNTR", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 0, |
7c2cb42b | 895 | .access = PL0_RW, .resetvalue = 0, .type = ARM_CP_IO, |
421c7ebd | 896 | .readfn = pmccntr_read, .writefn = pmccntr_write32, |
fcd25206 | 897 | .accessfn = pmreg_access }, |
8521466b AF |
898 | { .name = "PMCCNTR_EL0", .state = ARM_CP_STATE_AA64, |
899 | .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 13, .opc2 = 0, | |
900 | .access = PL0_RW, .accessfn = pmreg_access, | |
901 | .type = ARM_CP_IO, | |
902 | .readfn = pmccntr_read, .writefn = pmccntr_write, }, | |
7c2cb42b | 903 | #endif |
8521466b AF |
904 | { .name = "PMCCFILTR_EL0", .state = ARM_CP_STATE_AA64, |
905 | .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 15, .opc2 = 7, | |
0614601c | 906 | .writefn = pmccfiltr_write, |
8521466b AF |
907 | .access = PL0_RW, .accessfn = pmreg_access, |
908 | .type = ARM_CP_IO, | |
909 | .fieldoffset = offsetof(CPUARMState, cp15.pmccfiltr_el0), | |
910 | .resetvalue = 0, }, | |
200ac0ef PM |
911 | { .name = "PMXEVTYPER", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 1, |
912 | .access = PL0_RW, | |
913 | .fieldoffset = offsetof(CPUARMState, cp15.c9_pmxevtyper), | |
fcd25206 PM |
914 | .accessfn = pmreg_access, .writefn = pmxevtyper_write, |
915 | .raw_writefn = raw_write }, | |
916 | /* Unimplemented, RAZ/WI. */ | |
200ac0ef | 917 | { .name = "PMXEVCNTR", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 2, |
fcd25206 PM |
918 | .access = PL0_RW, .type = ARM_CP_CONST, .resetvalue = 0, |
919 | .accessfn = pmreg_access }, | |
200ac0ef PM |
920 | { .name = "PMUSERENR", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 0, |
921 | .access = PL0_R | PL1_RW, | |
922 | .fieldoffset = offsetof(CPUARMState, cp15.c9_pmuserenr), | |
923 | .resetvalue = 0, | |
d4e6df63 | 924 | .writefn = pmuserenr_write, .raw_writefn = raw_write }, |
200ac0ef PM |
925 | { .name = "PMINTENSET", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 1, |
926 | .access = PL1_RW, | |
927 | .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten), | |
928 | .resetvalue = 0, | |
d4e6df63 | 929 | .writefn = pmintenset_write, .raw_writefn = raw_write }, |
200ac0ef | 930 | { .name = "PMINTENCLR", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 2, |
d4e6df63 | 931 | .access = PL1_RW, .type = ARM_CP_NO_MIGRATE, |
200ac0ef | 932 | .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten), |
d4e6df63 | 933 | .resetvalue = 0, .writefn = pmintenclr_write, }, |
a505d7fe PM |
934 | { .name = "VBAR", .state = ARM_CP_STATE_BOTH, |
935 | .opc0 = 3, .crn = 12, .crm = 0, .opc1 = 0, .opc2 = 0, | |
8641136c | 936 | .access = PL1_RW, .writefn = vbar_write, |
fb6c91ba GB |
937 | .bank_fieldoffsets = { offsetof(CPUARMState, cp15.vbar_s), |
938 | offsetof(CPUARMState, cp15.vbar_ns) }, | |
8641136c | 939 | .resetvalue = 0 }, |
7da845b0 PM |
940 | { .name = "CCSIDR", .state = ARM_CP_STATE_BOTH, |
941 | .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 0, | |
d4e6df63 | 942 | .access = PL1_R, .readfn = ccsidr_read, .type = ARM_CP_NO_MIGRATE }, |
7da845b0 PM |
943 | { .name = "CSSELR", .state = ARM_CP_STATE_BOTH, |
944 | .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 2, .opc2 = 0, | |
b85a1fd6 FA |
945 | .access = PL1_RW, .writefn = csselr_write, .resetvalue = 0, |
946 | .bank_fieldoffsets = { offsetof(CPUARMState, cp15.csselr_s), | |
947 | offsetof(CPUARMState, cp15.csselr_ns) } }, | |
776d4e5c PM |
948 | /* Auxiliary ID register: this actually has an IMPDEF value but for now |
949 | * just RAZ for all cores: | |
950 | */ | |
0ff644a7 PM |
951 | { .name = "AIDR", .state = ARM_CP_STATE_BOTH, |
952 | .opc0 = 3, .opc1 = 1, .crn = 0, .crm = 0, .opc2 = 7, | |
776d4e5c | 953 | .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 }, |
f32cdad5 PM |
954 | /* Auxiliary fault status registers: these also are IMPDEF, and we |
955 | * choose to RAZ/WI for all cores. | |
956 | */ | |
957 | { .name = "AFSR0_EL1", .state = ARM_CP_STATE_BOTH, | |
958 | .opc0 = 3, .opc1 = 0, .crn = 5, .crm = 1, .opc2 = 0, | |
959 | .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
960 | { .name = "AFSR1_EL1", .state = ARM_CP_STATE_BOTH, | |
961 | .opc0 = 3, .opc1 = 0, .crn = 5, .crm = 1, .opc2 = 1, | |
962 | .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
b0fe2427 PM |
963 | /* MAIR can just read-as-written because we don't implement caches |
964 | * and so don't need to care about memory attributes. | |
965 | */ | |
966 | { .name = "MAIR_EL1", .state = ARM_CP_STATE_AA64, | |
967 | .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 2, .opc2 = 0, | |
968 | .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.mair_el1), | |
969 | .resetvalue = 0 }, | |
970 | /* For non-long-descriptor page tables these are PRRR and NMRR; | |
971 | * regardless they still act as reads-as-written for QEMU. | |
972 | * The override is necessary because of the overly-broad TLB_LOCKDOWN | |
973 | * definition. | |
974 | */ | |
975 | { .name = "MAIR0", .state = ARM_CP_STATE_AA32, .type = ARM_CP_OVERRIDE, | |
976 | .cp = 15, .opc1 = 0, .crn = 10, .crm = 2, .opc2 = 0, .access = PL1_RW, | |
977 | .fieldoffset = offsetoflow32(CPUARMState, cp15.mair_el1), | |
978 | .resetfn = arm_cp_reset_ignore }, | |
979 | { .name = "MAIR1", .state = ARM_CP_STATE_AA32, .type = ARM_CP_OVERRIDE, | |
980 | .cp = 15, .opc1 = 0, .crn = 10, .crm = 2, .opc2 = 1, .access = PL1_RW, | |
981 | .fieldoffset = offsetofhigh32(CPUARMState, cp15.mair_el1), | |
982 | .resetfn = arm_cp_reset_ignore }, | |
1090b9c6 PM |
983 | { .name = "ISR_EL1", .state = ARM_CP_STATE_BOTH, |
984 | .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 1, .opc2 = 0, | |
985 | .type = ARM_CP_NO_MIGRATE, .access = PL1_R, .readfn = isr_read }, | |
995939a6 PM |
986 | /* 32 bit ITLB invalidates */ |
987 | { .name = "ITLBIALL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 0, | |
988 | .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn = tlbiall_write }, | |
989 | { .name = "ITLBIMVA", .cp = 15, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 1, | |
990 | .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn = tlbimva_write }, | |
991 | { .name = "ITLBIASID", .cp = 15, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 2, | |
992 | .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn = tlbiasid_write }, | |
993 | /* 32 bit DTLB invalidates */ | |
994 | { .name = "DTLBIALL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 0, | |
995 | .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn = tlbiall_write }, | |
996 | { .name = "DTLBIMVA", .cp = 15, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 1, | |
997 | .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn = tlbimva_write }, | |
998 | { .name = "DTLBIASID", .cp = 15, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 2, | |
999 | .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn = tlbiasid_write }, | |
1000 | /* 32 bit TLB invalidates */ | |
1001 | { .name = "TLBIALL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 0, | |
1002 | .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn = tlbiall_write }, | |
1003 | { .name = "TLBIMVA", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 1, | |
1004 | .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn = tlbimva_write }, | |
1005 | { .name = "TLBIASID", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 2, | |
1006 | .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn = tlbiasid_write }, | |
1007 | { .name = "TLBIMVAA", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 3, | |
1008 | .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn = tlbimvaa_write }, | |
1009 | REGINFO_SENTINEL | |
1010 | }; | |
1011 | ||
1012 | static const ARMCPRegInfo v7mp_cp_reginfo[] = { | |
1013 | /* 32 bit TLB invalidates, Inner Shareable */ | |
1014 | { .name = "TLBIALLIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 0, | |
fa439fc5 | 1015 | .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn = tlbiall_is_write }, |
995939a6 | 1016 | { .name = "TLBIMVAIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 1, |
fa439fc5 | 1017 | .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn = tlbimva_is_write }, |
995939a6 | 1018 | { .name = "TLBIASIDIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 2, |
fa439fc5 PM |
1019 | .type = ARM_CP_NO_MIGRATE, .access = PL1_W, |
1020 | .writefn = tlbiasid_is_write }, | |
995939a6 | 1021 | { .name = "TLBIMVAAIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 3, |
fa439fc5 PM |
1022 | .type = ARM_CP_NO_MIGRATE, .access = PL1_W, |
1023 | .writefn = tlbimvaa_is_write }, | |
e9aa6c21 PM |
1024 | REGINFO_SENTINEL |
1025 | }; | |
1026 | ||
c4241c7d PM |
1027 | static void teecr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1028 | uint64_t value) | |
c326b979 PM |
1029 | { |
1030 | value &= 1; | |
1031 | env->teecr = value; | |
c326b979 PM |
1032 | } |
1033 | ||
c4241c7d | 1034 | static CPAccessResult teehbr_access(CPUARMState *env, const ARMCPRegInfo *ri) |
c326b979 | 1035 | { |
dcbff19b | 1036 | if (arm_current_el(env) == 0 && (env->teecr & 1)) { |
92611c00 | 1037 | return CP_ACCESS_TRAP; |
c326b979 | 1038 | } |
92611c00 | 1039 | return CP_ACCESS_OK; |
c326b979 PM |
1040 | } |
1041 | ||
1042 | static const ARMCPRegInfo t2ee_cp_reginfo[] = { | |
1043 | { .name = "TEECR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 6, .opc2 = 0, | |
1044 | .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, teecr), | |
1045 | .resetvalue = 0, | |
1046 | .writefn = teecr_write }, | |
1047 | { .name = "TEEHBR", .cp = 14, .crn = 1, .crm = 0, .opc1 = 6, .opc2 = 0, | |
1048 | .access = PL0_RW, .fieldoffset = offsetof(CPUARMState, teehbr), | |
92611c00 | 1049 | .accessfn = teehbr_access, .resetvalue = 0 }, |
c326b979 PM |
1050 | REGINFO_SENTINEL |
1051 | }; | |
1052 | ||
4d31c596 | 1053 | static const ARMCPRegInfo v6k_cp_reginfo[] = { |
e4fe830b PM |
1054 | { .name = "TPIDR_EL0", .state = ARM_CP_STATE_AA64, |
1055 | .opc0 = 3, .opc1 = 3, .opc2 = 2, .crn = 13, .crm = 0, | |
1056 | .access = PL0_RW, | |
54bf36ed | 1057 | .fieldoffset = offsetof(CPUARMState, cp15.tpidr_el[0]), .resetvalue = 0 }, |
4d31c596 PM |
1058 | { .name = "TPIDRURW", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 2, |
1059 | .access = PL0_RW, | |
54bf36ed FA |
1060 | .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.tpidrurw_s), |
1061 | offsetoflow32(CPUARMState, cp15.tpidrurw_ns) }, | |
e4fe830b PM |
1062 | .resetfn = arm_cp_reset_ignore }, |
1063 | { .name = "TPIDRRO_EL0", .state = ARM_CP_STATE_AA64, | |
1064 | .opc0 = 3, .opc1 = 3, .opc2 = 3, .crn = 13, .crm = 0, | |
1065 | .access = PL0_R|PL1_W, | |
54bf36ed FA |
1066 | .fieldoffset = offsetof(CPUARMState, cp15.tpidrro_el[0]), |
1067 | .resetvalue = 0}, | |
4d31c596 PM |
1068 | { .name = "TPIDRURO", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 3, |
1069 | .access = PL0_R|PL1_W, | |
54bf36ed FA |
1070 | .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.tpidruro_s), |
1071 | offsetoflow32(CPUARMState, cp15.tpidruro_ns) }, | |
e4fe830b | 1072 | .resetfn = arm_cp_reset_ignore }, |
54bf36ed | 1073 | { .name = "TPIDR_EL1", .state = ARM_CP_STATE_AA64, |
e4fe830b | 1074 | .opc0 = 3, .opc1 = 0, .opc2 = 4, .crn = 13, .crm = 0, |
4d31c596 | 1075 | .access = PL1_RW, |
54bf36ed FA |
1076 | .fieldoffset = offsetof(CPUARMState, cp15.tpidr_el[1]), .resetvalue = 0 }, |
1077 | { .name = "TPIDRPRW", .opc1 = 0, .cp = 15, .crn = 13, .crm = 0, .opc2 = 4, | |
1078 | .access = PL1_RW, | |
1079 | .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.tpidrprw_s), | |
1080 | offsetoflow32(CPUARMState, cp15.tpidrprw_ns) }, | |
1081 | .resetvalue = 0 }, | |
4d31c596 PM |
1082 | REGINFO_SENTINEL |
1083 | }; | |
1084 | ||
55d284af PM |
1085 | #ifndef CONFIG_USER_ONLY |
1086 | ||
00108f2d PM |
1087 | static CPAccessResult gt_cntfrq_access(CPUARMState *env, const ARMCPRegInfo *ri) |
1088 | { | |
1089 | /* CNTFRQ: not visible from PL0 if both PL0PCTEN and PL0VCTEN are zero */ | |
dcbff19b | 1090 | if (arm_current_el(env) == 0 && !extract32(env->cp15.c14_cntkctl, 0, 2)) { |
00108f2d PM |
1091 | return CP_ACCESS_TRAP; |
1092 | } | |
1093 | return CP_ACCESS_OK; | |
1094 | } | |
1095 | ||
1096 | static CPAccessResult gt_counter_access(CPUARMState *env, int timeridx) | |
1097 | { | |
1098 | /* CNT[PV]CT: not visible from PL0 if ELO[PV]CTEN is zero */ | |
dcbff19b | 1099 | if (arm_current_el(env) == 0 && |
00108f2d PM |
1100 | !extract32(env->cp15.c14_cntkctl, timeridx, 1)) { |
1101 | return CP_ACCESS_TRAP; | |
1102 | } | |
1103 | return CP_ACCESS_OK; | |
1104 | } | |
1105 | ||
1106 | static CPAccessResult gt_timer_access(CPUARMState *env, int timeridx) | |
1107 | { | |
1108 | /* CNT[PV]_CVAL, CNT[PV]_CTL, CNT[PV]_TVAL: not visible from PL0 if | |
1109 | * EL0[PV]TEN is zero. | |
1110 | */ | |
dcbff19b | 1111 | if (arm_current_el(env) == 0 && |
00108f2d PM |
1112 | !extract32(env->cp15.c14_cntkctl, 9 - timeridx, 1)) { |
1113 | return CP_ACCESS_TRAP; | |
1114 | } | |
1115 | return CP_ACCESS_OK; | |
1116 | } | |
1117 | ||
1118 | static CPAccessResult gt_pct_access(CPUARMState *env, | |
1119 | const ARMCPRegInfo *ri) | |
1120 | { | |
1121 | return gt_counter_access(env, GTIMER_PHYS); | |
1122 | } | |
1123 | ||
1124 | static CPAccessResult gt_vct_access(CPUARMState *env, | |
1125 | const ARMCPRegInfo *ri) | |
1126 | { | |
1127 | return gt_counter_access(env, GTIMER_VIRT); | |
1128 | } | |
1129 | ||
1130 | static CPAccessResult gt_ptimer_access(CPUARMState *env, const ARMCPRegInfo *ri) | |
1131 | { | |
1132 | return gt_timer_access(env, GTIMER_PHYS); | |
1133 | } | |
1134 | ||
1135 | static CPAccessResult gt_vtimer_access(CPUARMState *env, const ARMCPRegInfo *ri) | |
1136 | { | |
1137 | return gt_timer_access(env, GTIMER_VIRT); | |
1138 | } | |
1139 | ||
55d284af PM |
1140 | static uint64_t gt_get_countervalue(CPUARMState *env) |
1141 | { | |
bc72ad67 | 1142 | return qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) / GTIMER_SCALE; |
55d284af PM |
1143 | } |
1144 | ||
1145 | static void gt_recalc_timer(ARMCPU *cpu, int timeridx) | |
1146 | { | |
1147 | ARMGenericTimer *gt = &cpu->env.cp15.c14_timer[timeridx]; | |
1148 | ||
1149 | if (gt->ctl & 1) { | |
1150 | /* Timer enabled: calculate and set current ISTATUS, irq, and | |
1151 | * reset timer to when ISTATUS next has to change | |
1152 | */ | |
1153 | uint64_t count = gt_get_countervalue(&cpu->env); | |
1154 | /* Note that this must be unsigned 64 bit arithmetic: */ | |
1155 | int istatus = count >= gt->cval; | |
1156 | uint64_t nexttick; | |
1157 | ||
1158 | gt->ctl = deposit32(gt->ctl, 2, 1, istatus); | |
1159 | qemu_set_irq(cpu->gt_timer_outputs[timeridx], | |
1160 | (istatus && !(gt->ctl & 2))); | |
1161 | if (istatus) { | |
1162 | /* Next transition is when count rolls back over to zero */ | |
1163 | nexttick = UINT64_MAX; | |
1164 | } else { | |
1165 | /* Next transition is when we hit cval */ | |
1166 | nexttick = gt->cval; | |
1167 | } | |
1168 | /* Note that the desired next expiry time might be beyond the | |
1169 | * signed-64-bit range of a QEMUTimer -- in this case we just | |
1170 | * set the timer for as far in the future as possible. When the | |
1171 | * timer expires we will reset the timer for any remaining period. | |
1172 | */ | |
1173 | if (nexttick > INT64_MAX / GTIMER_SCALE) { | |
1174 | nexttick = INT64_MAX / GTIMER_SCALE; | |
1175 | } | |
bc72ad67 | 1176 | timer_mod(cpu->gt_timer[timeridx], nexttick); |
55d284af PM |
1177 | } else { |
1178 | /* Timer disabled: ISTATUS and timer output always clear */ | |
1179 | gt->ctl &= ~4; | |
1180 | qemu_set_irq(cpu->gt_timer_outputs[timeridx], 0); | |
bc72ad67 | 1181 | timer_del(cpu->gt_timer[timeridx]); |
55d284af PM |
1182 | } |
1183 | } | |
1184 | ||
55d284af PM |
1185 | static void gt_cnt_reset(CPUARMState *env, const ARMCPRegInfo *ri) |
1186 | { | |
1187 | ARMCPU *cpu = arm_env_get_cpu(env); | |
1188 | int timeridx = ri->opc1 & 1; | |
1189 | ||
bc72ad67 | 1190 | timer_del(cpu->gt_timer[timeridx]); |
55d284af PM |
1191 | } |
1192 | ||
c4241c7d | 1193 | static uint64_t gt_cnt_read(CPUARMState *env, const ARMCPRegInfo *ri) |
55d284af | 1194 | { |
c4241c7d | 1195 | return gt_get_countervalue(env); |
55d284af PM |
1196 | } |
1197 | ||
c4241c7d PM |
1198 | static void gt_cval_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1199 | uint64_t value) | |
55d284af PM |
1200 | { |
1201 | int timeridx = ri->opc1 & 1; | |
1202 | ||
1203 | env->cp15.c14_timer[timeridx].cval = value; | |
1204 | gt_recalc_timer(arm_env_get_cpu(env), timeridx); | |
55d284af | 1205 | } |
c4241c7d PM |
1206 | |
1207 | static uint64_t gt_tval_read(CPUARMState *env, const ARMCPRegInfo *ri) | |
55d284af PM |
1208 | { |
1209 | int timeridx = ri->crm & 1; | |
1210 | ||
c4241c7d PM |
1211 | return (uint32_t)(env->cp15.c14_timer[timeridx].cval - |
1212 | gt_get_countervalue(env)); | |
55d284af PM |
1213 | } |
1214 | ||
c4241c7d PM |
1215 | static void gt_tval_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1216 | uint64_t value) | |
55d284af PM |
1217 | { |
1218 | int timeridx = ri->crm & 1; | |
1219 | ||
1220 | env->cp15.c14_timer[timeridx].cval = gt_get_countervalue(env) + | |
1221 | + sextract64(value, 0, 32); | |
1222 | gt_recalc_timer(arm_env_get_cpu(env), timeridx); | |
55d284af PM |
1223 | } |
1224 | ||
c4241c7d PM |
1225 | static void gt_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1226 | uint64_t value) | |
55d284af PM |
1227 | { |
1228 | ARMCPU *cpu = arm_env_get_cpu(env); | |
1229 | int timeridx = ri->crm & 1; | |
1230 | uint32_t oldval = env->cp15.c14_timer[timeridx].ctl; | |
1231 | ||
d3afacc7 | 1232 | env->cp15.c14_timer[timeridx].ctl = deposit64(oldval, 0, 2, value); |
55d284af PM |
1233 | if ((oldval ^ value) & 1) { |
1234 | /* Enable toggled */ | |
1235 | gt_recalc_timer(cpu, timeridx); | |
d3afacc7 | 1236 | } else if ((oldval ^ value) & 2) { |
55d284af PM |
1237 | /* IMASK toggled: don't need to recalculate, |
1238 | * just set the interrupt line based on ISTATUS | |
1239 | */ | |
1240 | qemu_set_irq(cpu->gt_timer_outputs[timeridx], | |
d3afacc7 | 1241 | (oldval & 4) && !(value & 2)); |
55d284af | 1242 | } |
55d284af PM |
1243 | } |
1244 | ||
1245 | void arm_gt_ptimer_cb(void *opaque) | |
1246 | { | |
1247 | ARMCPU *cpu = opaque; | |
1248 | ||
1249 | gt_recalc_timer(cpu, GTIMER_PHYS); | |
1250 | } | |
1251 | ||
1252 | void arm_gt_vtimer_cb(void *opaque) | |
1253 | { | |
1254 | ARMCPU *cpu = opaque; | |
1255 | ||
1256 | gt_recalc_timer(cpu, GTIMER_VIRT); | |
1257 | } | |
1258 | ||
1259 | static const ARMCPRegInfo generic_timer_cp_reginfo[] = { | |
1260 | /* Note that CNTFRQ is purely reads-as-written for the benefit | |
1261 | * of software; writing it doesn't actually change the timer frequency. | |
1262 | * Our reset value matches the fixed frequency we implement the timer at. | |
1263 | */ | |
1264 | { .name = "CNTFRQ", .cp = 15, .crn = 14, .crm = 0, .opc1 = 0, .opc2 = 0, | |
a7adc4b7 PM |
1265 | .type = ARM_CP_NO_MIGRATE, |
1266 | .access = PL1_RW | PL0_R, .accessfn = gt_cntfrq_access, | |
1267 | .fieldoffset = offsetoflow32(CPUARMState, cp15.c14_cntfrq), | |
1268 | .resetfn = arm_cp_reset_ignore, | |
1269 | }, | |
1270 | { .name = "CNTFRQ_EL0", .state = ARM_CP_STATE_AA64, | |
1271 | .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 0, | |
1272 | .access = PL1_RW | PL0_R, .accessfn = gt_cntfrq_access, | |
55d284af PM |
1273 | .fieldoffset = offsetof(CPUARMState, cp15.c14_cntfrq), |
1274 | .resetvalue = (1000 * 1000 * 1000) / GTIMER_SCALE, | |
55d284af PM |
1275 | }, |
1276 | /* overall control: mostly access permissions */ | |
a7adc4b7 PM |
1277 | { .name = "CNTKCTL", .state = ARM_CP_STATE_BOTH, |
1278 | .opc0 = 3, .opc1 = 0, .crn = 14, .crm = 1, .opc2 = 0, | |
55d284af PM |
1279 | .access = PL1_RW, |
1280 | .fieldoffset = offsetof(CPUARMState, cp15.c14_cntkctl), | |
1281 | .resetvalue = 0, | |
1282 | }, | |
1283 | /* per-timer control */ | |
1284 | { .name = "CNTP_CTL", .cp = 15, .crn = 14, .crm = 2, .opc1 = 0, .opc2 = 1, | |
a7adc4b7 PM |
1285 | .type = ARM_CP_IO | ARM_CP_NO_MIGRATE, .access = PL1_RW | PL0_R, |
1286 | .accessfn = gt_ptimer_access, | |
1287 | .fieldoffset = offsetoflow32(CPUARMState, | |
1288 | cp15.c14_timer[GTIMER_PHYS].ctl), | |
1289 | .resetfn = arm_cp_reset_ignore, | |
1290 | .writefn = gt_ctl_write, .raw_writefn = raw_write, | |
1291 | }, | |
1292 | { .name = "CNTP_CTL_EL0", .state = ARM_CP_STATE_AA64, | |
1293 | .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 2, .opc2 = 1, | |
55d284af | 1294 | .type = ARM_CP_IO, .access = PL1_RW | PL0_R, |
a7adc4b7 | 1295 | .accessfn = gt_ptimer_access, |
55d284af PM |
1296 | .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].ctl), |
1297 | .resetvalue = 0, | |
00108f2d | 1298 | .writefn = gt_ctl_write, .raw_writefn = raw_write, |
55d284af PM |
1299 | }, |
1300 | { .name = "CNTV_CTL", .cp = 15, .crn = 14, .crm = 3, .opc1 = 0, .opc2 = 1, | |
a7adc4b7 PM |
1301 | .type = ARM_CP_IO | ARM_CP_NO_MIGRATE, .access = PL1_RW | PL0_R, |
1302 | .accessfn = gt_vtimer_access, | |
1303 | .fieldoffset = offsetoflow32(CPUARMState, | |
1304 | cp15.c14_timer[GTIMER_VIRT].ctl), | |
1305 | .resetfn = arm_cp_reset_ignore, | |
1306 | .writefn = gt_ctl_write, .raw_writefn = raw_write, | |
1307 | }, | |
1308 | { .name = "CNTV_CTL_EL0", .state = ARM_CP_STATE_AA64, | |
1309 | .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 3, .opc2 = 1, | |
55d284af | 1310 | .type = ARM_CP_IO, .access = PL1_RW | PL0_R, |
a7adc4b7 | 1311 | .accessfn = gt_vtimer_access, |
55d284af PM |
1312 | .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].ctl), |
1313 | .resetvalue = 0, | |
00108f2d | 1314 | .writefn = gt_ctl_write, .raw_writefn = raw_write, |
55d284af PM |
1315 | }, |
1316 | /* TimerValue views: a 32 bit downcounting view of the underlying state */ | |
1317 | { .name = "CNTP_TVAL", .cp = 15, .crn = 14, .crm = 2, .opc1 = 0, .opc2 = 0, | |
1318 | .type = ARM_CP_NO_MIGRATE | ARM_CP_IO, .access = PL1_RW | PL0_R, | |
00108f2d | 1319 | .accessfn = gt_ptimer_access, |
55d284af PM |
1320 | .readfn = gt_tval_read, .writefn = gt_tval_write, |
1321 | }, | |
a7adc4b7 PM |
1322 | { .name = "CNTP_TVAL_EL0", .state = ARM_CP_STATE_AA64, |
1323 | .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 2, .opc2 = 0, | |
1324 | .type = ARM_CP_NO_MIGRATE | ARM_CP_IO, .access = PL1_RW | PL0_R, | |
1325 | .readfn = gt_tval_read, .writefn = gt_tval_write, | |
1326 | }, | |
55d284af PM |
1327 | { .name = "CNTV_TVAL", .cp = 15, .crn = 14, .crm = 3, .opc1 = 0, .opc2 = 0, |
1328 | .type = ARM_CP_NO_MIGRATE | ARM_CP_IO, .access = PL1_RW | PL0_R, | |
00108f2d | 1329 | .accessfn = gt_vtimer_access, |
55d284af PM |
1330 | .readfn = gt_tval_read, .writefn = gt_tval_write, |
1331 | }, | |
a7adc4b7 PM |
1332 | { .name = "CNTV_TVAL_EL0", .state = ARM_CP_STATE_AA64, |
1333 | .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 3, .opc2 = 0, | |
1334 | .type = ARM_CP_NO_MIGRATE | ARM_CP_IO, .access = PL1_RW | PL0_R, | |
1335 | .readfn = gt_tval_read, .writefn = gt_tval_write, | |
1336 | }, | |
55d284af PM |
1337 | /* The counter itself */ |
1338 | { .name = "CNTPCT", .cp = 15, .crm = 14, .opc1 = 0, | |
1339 | .access = PL0_R, .type = ARM_CP_64BIT | ARM_CP_NO_MIGRATE | ARM_CP_IO, | |
00108f2d | 1340 | .accessfn = gt_pct_access, |
a7adc4b7 PM |
1341 | .readfn = gt_cnt_read, .resetfn = arm_cp_reset_ignore, |
1342 | }, | |
1343 | { .name = "CNTPCT_EL0", .state = ARM_CP_STATE_AA64, | |
1344 | .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 1, | |
1345 | .access = PL0_R, .type = ARM_CP_NO_MIGRATE | ARM_CP_IO, | |
1346 | .accessfn = gt_pct_access, | |
55d284af PM |
1347 | .readfn = gt_cnt_read, .resetfn = gt_cnt_reset, |
1348 | }, | |
1349 | { .name = "CNTVCT", .cp = 15, .crm = 14, .opc1 = 1, | |
1350 | .access = PL0_R, .type = ARM_CP_64BIT | ARM_CP_NO_MIGRATE | ARM_CP_IO, | |
00108f2d | 1351 | .accessfn = gt_vct_access, |
a7adc4b7 PM |
1352 | .readfn = gt_cnt_read, .resetfn = arm_cp_reset_ignore, |
1353 | }, | |
1354 | { .name = "CNTVCT_EL0", .state = ARM_CP_STATE_AA64, | |
1355 | .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 2, | |
1356 | .access = PL0_R, .type = ARM_CP_NO_MIGRATE | ARM_CP_IO, | |
1357 | .accessfn = gt_vct_access, | |
55d284af PM |
1358 | .readfn = gt_cnt_read, .resetfn = gt_cnt_reset, |
1359 | }, | |
1360 | /* Comparison value, indicating when the timer goes off */ | |
1361 | { .name = "CNTP_CVAL", .cp = 15, .crm = 14, .opc1 = 2, | |
1362 | .access = PL1_RW | PL0_R, | |
a7adc4b7 | 1363 | .type = ARM_CP_64BIT | ARM_CP_IO | ARM_CP_NO_MIGRATE, |
55d284af | 1364 | .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].cval), |
a7adc4b7 PM |
1365 | .accessfn = gt_ptimer_access, .resetfn = arm_cp_reset_ignore, |
1366 | .writefn = gt_cval_write, .raw_writefn = raw_write, | |
1367 | }, | |
1368 | { .name = "CNTP_CVAL_EL0", .state = ARM_CP_STATE_AA64, | |
1369 | .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 2, .opc2 = 2, | |
1370 | .access = PL1_RW | PL0_R, | |
1371 | .type = ARM_CP_IO, | |
1372 | .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].cval), | |
1373 | .resetvalue = 0, .accessfn = gt_vtimer_access, | |
00108f2d | 1374 | .writefn = gt_cval_write, .raw_writefn = raw_write, |
55d284af PM |
1375 | }, |
1376 | { .name = "CNTV_CVAL", .cp = 15, .crm = 14, .opc1 = 3, | |
1377 | .access = PL1_RW | PL0_R, | |
a7adc4b7 | 1378 | .type = ARM_CP_64BIT | ARM_CP_IO | ARM_CP_NO_MIGRATE, |
55d284af | 1379 | .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].cval), |
a7adc4b7 PM |
1380 | .accessfn = gt_vtimer_access, .resetfn = arm_cp_reset_ignore, |
1381 | .writefn = gt_cval_write, .raw_writefn = raw_write, | |
1382 | }, | |
1383 | { .name = "CNTV_CVAL_EL0", .state = ARM_CP_STATE_AA64, | |
1384 | .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 3, .opc2 = 2, | |
1385 | .access = PL1_RW | PL0_R, | |
1386 | .type = ARM_CP_IO, | |
1387 | .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].cval), | |
1388 | .resetvalue = 0, .accessfn = gt_vtimer_access, | |
00108f2d | 1389 | .writefn = gt_cval_write, .raw_writefn = raw_write, |
55d284af PM |
1390 | }, |
1391 | REGINFO_SENTINEL | |
1392 | }; | |
1393 | ||
1394 | #else | |
1395 | /* In user-mode none of the generic timer registers are accessible, | |
bc72ad67 | 1396 | * and their implementation depends on QEMU_CLOCK_VIRTUAL and qdev gpio outputs, |
55d284af PM |
1397 | * so instead just don't register any of them. |
1398 | */ | |
6cc7a3ae | 1399 | static const ARMCPRegInfo generic_timer_cp_reginfo[] = { |
6cc7a3ae PM |
1400 | REGINFO_SENTINEL |
1401 | }; | |
1402 | ||
55d284af PM |
1403 | #endif |
1404 | ||
c4241c7d | 1405 | static void par_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) |
4a501606 | 1406 | { |
891a2fe7 | 1407 | if (arm_feature(env, ARM_FEATURE_LPAE)) { |
8d5c773e | 1408 | raw_write(env, ri, value); |
891a2fe7 | 1409 | } else if (arm_feature(env, ARM_FEATURE_V7)) { |
8d5c773e | 1410 | raw_write(env, ri, value & 0xfffff6ff); |
4a501606 | 1411 | } else { |
8d5c773e | 1412 | raw_write(env, ri, value & 0xfffff1ff); |
4a501606 | 1413 | } |
4a501606 PM |
1414 | } |
1415 | ||
1416 | #ifndef CONFIG_USER_ONLY | |
1417 | /* get_phys_addr() isn't present for user-mode-only targets */ | |
702a9357 | 1418 | |
92611c00 PM |
1419 | static CPAccessResult ats_access(CPUARMState *env, const ARMCPRegInfo *ri) |
1420 | { | |
1421 | if (ri->opc2 & 4) { | |
1422 | /* Other states are only available with TrustZone; in | |
1423 | * a non-TZ implementation these registers don't exist | |
1424 | * at all, which is an Uncategorized trap. This underdecoding | |
1425 | * is safe because the reginfo is NO_MIGRATE. | |
1426 | */ | |
1427 | return CP_ACCESS_TRAP_UNCATEGORIZED; | |
1428 | } | |
1429 | return CP_ACCESS_OK; | |
1430 | } | |
1431 | ||
c4241c7d | 1432 | static void ats_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) |
4a501606 | 1433 | { |
a8170e5e | 1434 | hwaddr phys_addr; |
4a501606 PM |
1435 | target_ulong page_size; |
1436 | int prot; | |
1437 | int ret, is_user = ri->opc2 & 2; | |
1438 | int access_type = ri->opc2 & 1; | |
01c097f7 | 1439 | uint64_t par64; |
4a501606 | 1440 | |
4a501606 PM |
1441 | ret = get_phys_addr(env, value, access_type, is_user, |
1442 | &phys_addr, &prot, &page_size); | |
702a9357 PM |
1443 | if (extended_addresses_enabled(env)) { |
1444 | /* ret is a DFSR/IFSR value for the long descriptor | |
1445 | * translation table format, but with WnR always clear. | |
1446 | * Convert it to a 64-bit PAR. | |
1447 | */ | |
01c097f7 | 1448 | par64 = (1 << 11); /* LPAE bit always set */ |
702a9357 PM |
1449 | if (ret == 0) { |
1450 | par64 |= phys_addr & ~0xfffULL; | |
1451 | /* We don't set the ATTR or SH fields in the PAR. */ | |
4a501606 | 1452 | } else { |
702a9357 PM |
1453 | par64 |= 1; /* F */ |
1454 | par64 |= (ret & 0x3f) << 1; /* FS */ | |
1455 | /* Note that S2WLK and FSTAGE are always zero, because we don't | |
1456 | * implement virtualization and therefore there can't be a stage 2 | |
1457 | * fault. | |
1458 | */ | |
4a501606 PM |
1459 | } |
1460 | } else { | |
702a9357 PM |
1461 | /* ret is a DFSR/IFSR value for the short descriptor |
1462 | * translation table format (with WnR always clear). | |
1463 | * Convert it to a 32-bit PAR. | |
1464 | */ | |
1465 | if (ret == 0) { | |
1466 | /* We do not set any attribute bits in the PAR */ | |
1467 | if (page_size == (1 << 24) | |
1468 | && arm_feature(env, ARM_FEATURE_V7)) { | |
01c097f7 | 1469 | par64 = (phys_addr & 0xff000000) | (1 << 1); |
702a9357 | 1470 | } else { |
01c097f7 | 1471 | par64 = phys_addr & 0xfffff000; |
702a9357 PM |
1472 | } |
1473 | } else { | |
01c097f7 FA |
1474 | par64 = ((ret & (1 << 10)) >> 5) | ((ret & (1 << 12)) >> 6) | |
1475 | ((ret & 0xf) << 1) | 1; | |
702a9357 | 1476 | } |
4a501606 | 1477 | } |
01c097f7 FA |
1478 | |
1479 | A32_BANKED_CURRENT_REG_SET(env, par, par64); | |
4a501606 PM |
1480 | } |
1481 | #endif | |
1482 | ||
1483 | static const ARMCPRegInfo vapa_cp_reginfo[] = { | |
1484 | { .name = "PAR", .cp = 15, .crn = 7, .crm = 4, .opc1 = 0, .opc2 = 0, | |
1485 | .access = PL1_RW, .resetvalue = 0, | |
01c097f7 FA |
1486 | .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.par_s), |
1487 | offsetoflow32(CPUARMState, cp15.par_ns) }, | |
4a501606 PM |
1488 | .writefn = par_write }, |
1489 | #ifndef CONFIG_USER_ONLY | |
1490 | { .name = "ATS", .cp = 15, .crn = 7, .crm = 8, .opc1 = 0, .opc2 = CP_ANY, | |
92611c00 PM |
1491 | .access = PL1_W, .accessfn = ats_access, |
1492 | .writefn = ats_write, .type = ARM_CP_NO_MIGRATE }, | |
4a501606 PM |
1493 | #endif |
1494 | REGINFO_SENTINEL | |
1495 | }; | |
1496 | ||
18032bec PM |
1497 | /* Return basic MPU access permission bits. */ |
1498 | static uint32_t simple_mpu_ap_bits(uint32_t val) | |
1499 | { | |
1500 | uint32_t ret; | |
1501 | uint32_t mask; | |
1502 | int i; | |
1503 | ret = 0; | |
1504 | mask = 3; | |
1505 | for (i = 0; i < 16; i += 2) { | |
1506 | ret |= (val >> i) & mask; | |
1507 | mask <<= 2; | |
1508 | } | |
1509 | return ret; | |
1510 | } | |
1511 | ||
1512 | /* Pad basic MPU access permission bits to extended format. */ | |
1513 | static uint32_t extended_mpu_ap_bits(uint32_t val) | |
1514 | { | |
1515 | uint32_t ret; | |
1516 | uint32_t mask; | |
1517 | int i; | |
1518 | ret = 0; | |
1519 | mask = 3; | |
1520 | for (i = 0; i < 16; i += 2) { | |
1521 | ret |= (val & mask) << i; | |
1522 | mask <<= 2; | |
1523 | } | |
1524 | return ret; | |
1525 | } | |
1526 | ||
c4241c7d PM |
1527 | static void pmsav5_data_ap_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1528 | uint64_t value) | |
18032bec | 1529 | { |
7e09797c | 1530 | env->cp15.pmsav5_data_ap = extended_mpu_ap_bits(value); |
18032bec PM |
1531 | } |
1532 | ||
c4241c7d | 1533 | static uint64_t pmsav5_data_ap_read(CPUARMState *env, const ARMCPRegInfo *ri) |
18032bec | 1534 | { |
7e09797c | 1535 | return simple_mpu_ap_bits(env->cp15.pmsav5_data_ap); |
18032bec PM |
1536 | } |
1537 | ||
c4241c7d PM |
1538 | static void pmsav5_insn_ap_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1539 | uint64_t value) | |
18032bec | 1540 | { |
7e09797c | 1541 | env->cp15.pmsav5_insn_ap = extended_mpu_ap_bits(value); |
18032bec PM |
1542 | } |
1543 | ||
c4241c7d | 1544 | static uint64_t pmsav5_insn_ap_read(CPUARMState *env, const ARMCPRegInfo *ri) |
18032bec | 1545 | { |
7e09797c | 1546 | return simple_mpu_ap_bits(env->cp15.pmsav5_insn_ap); |
18032bec PM |
1547 | } |
1548 | ||
1549 | static const ARMCPRegInfo pmsav5_cp_reginfo[] = { | |
1550 | { .name = "DATA_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 0, | |
d4e6df63 | 1551 | .access = PL1_RW, .type = ARM_CP_NO_MIGRATE, |
7e09797c PM |
1552 | .fieldoffset = offsetof(CPUARMState, cp15.pmsav5_data_ap), |
1553 | .resetvalue = 0, | |
18032bec PM |
1554 | .readfn = pmsav5_data_ap_read, .writefn = pmsav5_data_ap_write, }, |
1555 | { .name = "INSN_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 1, | |
d4e6df63 | 1556 | .access = PL1_RW, .type = ARM_CP_NO_MIGRATE, |
7e09797c PM |
1557 | .fieldoffset = offsetof(CPUARMState, cp15.pmsav5_insn_ap), |
1558 | .resetvalue = 0, | |
18032bec PM |
1559 | .readfn = pmsav5_insn_ap_read, .writefn = pmsav5_insn_ap_write, }, |
1560 | { .name = "DATA_EXT_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 2, | |
1561 | .access = PL1_RW, | |
7e09797c PM |
1562 | .fieldoffset = offsetof(CPUARMState, cp15.pmsav5_data_ap), |
1563 | .resetvalue = 0, }, | |
18032bec PM |
1564 | { .name = "INSN_EXT_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 3, |
1565 | .access = PL1_RW, | |
7e09797c PM |
1566 | .fieldoffset = offsetof(CPUARMState, cp15.pmsav5_insn_ap), |
1567 | .resetvalue = 0, }, | |
ecce5c3c PM |
1568 | { .name = "DCACHE_CFG", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 0, |
1569 | .access = PL1_RW, | |
1570 | .fieldoffset = offsetof(CPUARMState, cp15.c2_data), .resetvalue = 0, }, | |
1571 | { .name = "ICACHE_CFG", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 1, | |
1572 | .access = PL1_RW, | |
1573 | .fieldoffset = offsetof(CPUARMState, cp15.c2_insn), .resetvalue = 0, }, | |
06d76f31 | 1574 | /* Protection region base and size registers */ |
e508a92b PM |
1575 | { .name = "946_PRBS0", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, |
1576 | .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0, | |
1577 | .fieldoffset = offsetof(CPUARMState, cp15.c6_region[0]) }, | |
1578 | { .name = "946_PRBS1", .cp = 15, .crn = 6, .crm = 1, .opc1 = 0, | |
1579 | .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0, | |
1580 | .fieldoffset = offsetof(CPUARMState, cp15.c6_region[1]) }, | |
1581 | { .name = "946_PRBS2", .cp = 15, .crn = 6, .crm = 2, .opc1 = 0, | |
1582 | .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0, | |
1583 | .fieldoffset = offsetof(CPUARMState, cp15.c6_region[2]) }, | |
1584 | { .name = "946_PRBS3", .cp = 15, .crn = 6, .crm = 3, .opc1 = 0, | |
1585 | .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0, | |
1586 | .fieldoffset = offsetof(CPUARMState, cp15.c6_region[3]) }, | |
1587 | { .name = "946_PRBS4", .cp = 15, .crn = 6, .crm = 4, .opc1 = 0, | |
1588 | .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0, | |
1589 | .fieldoffset = offsetof(CPUARMState, cp15.c6_region[4]) }, | |
1590 | { .name = "946_PRBS5", .cp = 15, .crn = 6, .crm = 5, .opc1 = 0, | |
1591 | .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0, | |
1592 | .fieldoffset = offsetof(CPUARMState, cp15.c6_region[5]) }, | |
1593 | { .name = "946_PRBS6", .cp = 15, .crn = 6, .crm = 6, .opc1 = 0, | |
1594 | .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0, | |
1595 | .fieldoffset = offsetof(CPUARMState, cp15.c6_region[6]) }, | |
1596 | { .name = "946_PRBS7", .cp = 15, .crn = 6, .crm = 7, .opc1 = 0, | |
1597 | .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0, | |
1598 | .fieldoffset = offsetof(CPUARMState, cp15.c6_region[7]) }, | |
18032bec PM |
1599 | REGINFO_SENTINEL |
1600 | }; | |
1601 | ||
c4241c7d PM |
1602 | static void vmsa_ttbcr_raw_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1603 | uint64_t value) | |
ecce5c3c | 1604 | { |
11f136ee | 1605 | TCR *tcr = raw_ptr(env, ri); |
2ebcebe2 PM |
1606 | int maskshift = extract32(value, 0, 3); |
1607 | ||
e389be16 FA |
1608 | if (!arm_feature(env, ARM_FEATURE_V8)) { |
1609 | if (arm_feature(env, ARM_FEATURE_LPAE) && (value & TTBCR_EAE)) { | |
1610 | /* Pre ARMv8 bits [21:19], [15:14] and [6:3] are UNK/SBZP when | |
1611 | * using Long-desciptor translation table format */ | |
1612 | value &= ~((7 << 19) | (3 << 14) | (0xf << 3)); | |
1613 | } else if (arm_feature(env, ARM_FEATURE_EL3)) { | |
1614 | /* In an implementation that includes the Security Extensions | |
1615 | * TTBCR has additional fields PD0 [4] and PD1 [5] for | |
1616 | * Short-descriptor translation table format. | |
1617 | */ | |
1618 | value &= TTBCR_PD1 | TTBCR_PD0 | TTBCR_N; | |
1619 | } else { | |
1620 | value &= TTBCR_N; | |
1621 | } | |
e42c4db3 | 1622 | } |
e389be16 | 1623 | |
11f136ee FA |
1624 | /* Update the masks corresponding to the the TCR bank being written |
1625 | * Note that we always calculate mask and base_mask, but | |
e42c4db3 | 1626 | * they are only used for short-descriptor tables (ie if EAE is 0); |
11f136ee FA |
1627 | * for long-descriptor tables the TCR fields are used differently |
1628 | * and the mask and base_mask values are meaningless. | |
e42c4db3 | 1629 | */ |
11f136ee FA |
1630 | tcr->raw_tcr = value; |
1631 | tcr->mask = ~(((uint32_t)0xffffffffu) >> maskshift); | |
1632 | tcr->base_mask = ~((uint32_t)0x3fffu >> maskshift); | |
ecce5c3c PM |
1633 | } |
1634 | ||
c4241c7d PM |
1635 | static void vmsa_ttbcr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1636 | uint64_t value) | |
d4e6df63 | 1637 | { |
00c8cb0a AF |
1638 | ARMCPU *cpu = arm_env_get_cpu(env); |
1639 | ||
d4e6df63 PM |
1640 | if (arm_feature(env, ARM_FEATURE_LPAE)) { |
1641 | /* With LPAE the TTBCR could result in a change of ASID | |
1642 | * via the TTBCR.A1 bit, so do a TLB flush. | |
1643 | */ | |
00c8cb0a | 1644 | tlb_flush(CPU(cpu), 1); |
d4e6df63 | 1645 | } |
c4241c7d | 1646 | vmsa_ttbcr_raw_write(env, ri, value); |
d4e6df63 PM |
1647 | } |
1648 | ||
ecce5c3c PM |
1649 | static void vmsa_ttbcr_reset(CPUARMState *env, const ARMCPRegInfo *ri) |
1650 | { | |
11f136ee FA |
1651 | TCR *tcr = raw_ptr(env, ri); |
1652 | ||
1653 | /* Reset both the TCR as well as the masks corresponding to the bank of | |
1654 | * the TCR being reset. | |
1655 | */ | |
1656 | tcr->raw_tcr = 0; | |
1657 | tcr->mask = 0; | |
1658 | tcr->base_mask = 0xffffc000u; | |
ecce5c3c PM |
1659 | } |
1660 | ||
cb2e37df PM |
1661 | static void vmsa_tcr_el1_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1662 | uint64_t value) | |
1663 | { | |
00c8cb0a | 1664 | ARMCPU *cpu = arm_env_get_cpu(env); |
11f136ee | 1665 | TCR *tcr = raw_ptr(env, ri); |
00c8cb0a | 1666 | |
cb2e37df | 1667 | /* For AArch64 the A1 bit could result in a change of ASID, so TLB flush. */ |
00c8cb0a | 1668 | tlb_flush(CPU(cpu), 1); |
11f136ee | 1669 | tcr->raw_tcr = value; |
cb2e37df PM |
1670 | } |
1671 | ||
327ed10f PM |
1672 | static void vmsa_ttbr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1673 | uint64_t value) | |
1674 | { | |
1675 | /* 64 bit accesses to the TTBRs can change the ASID and so we | |
1676 | * must flush the TLB. | |
1677 | */ | |
1678 | if (cpreg_field_is_64bit(ri)) { | |
00c8cb0a AF |
1679 | ARMCPU *cpu = arm_env_get_cpu(env); |
1680 | ||
1681 | tlb_flush(CPU(cpu), 1); | |
327ed10f PM |
1682 | } |
1683 | raw_write(env, ri, value); | |
1684 | } | |
1685 | ||
18032bec PM |
1686 | static const ARMCPRegInfo vmsa_cp_reginfo[] = { |
1687 | { .name = "DFSR", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 0, | |
6cd8a264 | 1688 | .access = PL1_RW, .type = ARM_CP_NO_MIGRATE, |
4a7e2d73 FA |
1689 | .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.dfsr_s), |
1690 | offsetoflow32(CPUARMState, cp15.dfsr_ns) }, | |
6cd8a264 | 1691 | .resetfn = arm_cp_reset_ignore, }, |
18032bec | 1692 | { .name = "IFSR", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 1, |
88ca1c2d FA |
1693 | .access = PL1_RW, .resetvalue = 0, |
1694 | .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.ifsr_s), | |
1695 | offsetoflow32(CPUARMState, cp15.ifsr_ns) } }, | |
6cd8a264 RH |
1696 | { .name = "ESR_EL1", .state = ARM_CP_STATE_AA64, |
1697 | .opc0 = 3, .crn = 5, .crm = 2, .opc1 = 0, .opc2 = 0, | |
1698 | .access = PL1_RW, | |
d81c519c | 1699 | .fieldoffset = offsetof(CPUARMState, cp15.esr_el[1]), .resetvalue = 0, }, |
327ed10f | 1700 | { .name = "TTBR0_EL1", .state = ARM_CP_STATE_BOTH, |
7dd8c9af FA |
1701 | .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 0, .opc2 = 0, |
1702 | .access = PL1_RW, .writefn = vmsa_ttbr_write, .resetvalue = 0, | |
1703 | .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ttbr0_s), | |
1704 | offsetof(CPUARMState, cp15.ttbr0_ns) } }, | |
327ed10f | 1705 | { .name = "TTBR1_EL1", .state = ARM_CP_STATE_BOTH, |
7dd8c9af FA |
1706 | .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 0, .opc2 = 1, |
1707 | .access = PL1_RW, .writefn = vmsa_ttbr_write, .resetvalue = 0, | |
1708 | .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ttbr1_s), | |
1709 | offsetof(CPUARMState, cp15.ttbr1_ns) } }, | |
cb2e37df PM |
1710 | { .name = "TCR_EL1", .state = ARM_CP_STATE_AA64, |
1711 | .opc0 = 3, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 2, | |
1712 | .access = PL1_RW, .writefn = vmsa_tcr_el1_write, | |
1713 | .resetfn = vmsa_ttbcr_reset, .raw_writefn = raw_write, | |
11f136ee | 1714 | .fieldoffset = offsetof(CPUARMState, cp15.tcr_el[1]) }, |
cb2e37df PM |
1715 | { .name = "TTBCR", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 2, |
1716 | .access = PL1_RW, .type = ARM_CP_NO_MIGRATE, .writefn = vmsa_ttbcr_write, | |
1717 | .resetfn = arm_cp_reset_ignore, .raw_writefn = vmsa_ttbcr_raw_write, | |
11f136ee FA |
1718 | .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.tcr_el[3]), |
1719 | offsetoflow32(CPUARMState, cp15.tcr_el[1])} }, | |
b848ce2b | 1720 | { .name = "FAR_EL1", .state = ARM_CP_STATE_AA64, |
6cd8a264 | 1721 | .opc0 = 3, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 0, |
2f0180c5 | 1722 | .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.far_el[1]), |
06d76f31 | 1723 | .resetvalue = 0, }, |
b848ce2b FA |
1724 | { .name = "DFAR", .cp = 15, .opc1 = 0, .crn = 6, .crm = 0, .opc2 = 0, |
1725 | .access = PL1_RW, .resetvalue = 0, | |
1726 | .bank_fieldoffsets = { offsetof(CPUARMState, cp15.dfar_s), | |
1727 | offsetof(CPUARMState, cp15.dfar_ns) } }, | |
18032bec PM |
1728 | REGINFO_SENTINEL |
1729 | }; | |
1730 | ||
c4241c7d PM |
1731 | static void omap_ticonfig_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1732 | uint64_t value) | |
1047b9d7 PM |
1733 | { |
1734 | env->cp15.c15_ticonfig = value & 0xe7; | |
1735 | /* The OS_TYPE bit in this register changes the reported CPUID! */ | |
1736 | env->cp15.c0_cpuid = (value & (1 << 5)) ? | |
1737 | ARM_CPUID_TI915T : ARM_CPUID_TI925T; | |
1047b9d7 PM |
1738 | } |
1739 | ||
c4241c7d PM |
1740 | static void omap_threadid_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1741 | uint64_t value) | |
1047b9d7 PM |
1742 | { |
1743 | env->cp15.c15_threadid = value & 0xffff; | |
1047b9d7 PM |
1744 | } |
1745 | ||
c4241c7d PM |
1746 | static void omap_wfi_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1747 | uint64_t value) | |
1047b9d7 PM |
1748 | { |
1749 | /* Wait-for-interrupt (deprecated) */ | |
c3affe56 | 1750 | cpu_interrupt(CPU(arm_env_get_cpu(env)), CPU_INTERRUPT_HALT); |
1047b9d7 PM |
1751 | } |
1752 | ||
c4241c7d PM |
1753 | static void omap_cachemaint_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1754 | uint64_t value) | |
c4804214 PM |
1755 | { |
1756 | /* On OMAP there are registers indicating the max/min index of dcache lines | |
1757 | * containing a dirty line; cache flush operations have to reset these. | |
1758 | */ | |
1759 | env->cp15.c15_i_max = 0x000; | |
1760 | env->cp15.c15_i_min = 0xff0; | |
c4804214 PM |
1761 | } |
1762 | ||
18032bec PM |
1763 | static const ARMCPRegInfo omap_cp_reginfo[] = { |
1764 | { .name = "DFSR", .cp = 15, .crn = 5, .crm = CP_ANY, | |
1765 | .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_OVERRIDE, | |
d81c519c | 1766 | .fieldoffset = offsetoflow32(CPUARMState, cp15.esr_el[1]), |
6cd8a264 | 1767 | .resetvalue = 0, }, |
1047b9d7 PM |
1768 | { .name = "", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0, |
1769 | .access = PL1_RW, .type = ARM_CP_NOP }, | |
1770 | { .name = "TICONFIG", .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0, | |
1771 | .access = PL1_RW, | |
1772 | .fieldoffset = offsetof(CPUARMState, cp15.c15_ticonfig), .resetvalue = 0, | |
1773 | .writefn = omap_ticonfig_write }, | |
1774 | { .name = "IMAX", .cp = 15, .crn = 15, .crm = 2, .opc1 = 0, .opc2 = 0, | |
1775 | .access = PL1_RW, | |
1776 | .fieldoffset = offsetof(CPUARMState, cp15.c15_i_max), .resetvalue = 0, }, | |
1777 | { .name = "IMIN", .cp = 15, .crn = 15, .crm = 3, .opc1 = 0, .opc2 = 0, | |
1778 | .access = PL1_RW, .resetvalue = 0xff0, | |
1779 | .fieldoffset = offsetof(CPUARMState, cp15.c15_i_min) }, | |
1780 | { .name = "THREADID", .cp = 15, .crn = 15, .crm = 4, .opc1 = 0, .opc2 = 0, | |
1781 | .access = PL1_RW, | |
1782 | .fieldoffset = offsetof(CPUARMState, cp15.c15_threadid), .resetvalue = 0, | |
1783 | .writefn = omap_threadid_write }, | |
1784 | { .name = "TI925T_STATUS", .cp = 15, .crn = 15, | |
1785 | .crm = 8, .opc1 = 0, .opc2 = 0, .access = PL1_RW, | |
d4e6df63 | 1786 | .type = ARM_CP_NO_MIGRATE, |
1047b9d7 PM |
1787 | .readfn = arm_cp_read_zero, .writefn = omap_wfi_write, }, |
1788 | /* TODO: Peripheral port remap register: | |
1789 | * On OMAP2 mcr p15, 0, rn, c15, c2, 4 sets up the interrupt controller | |
1790 | * base address at $rn & ~0xfff and map size of 0x200 << ($rn & 0xfff), | |
1791 | * when MMU is off. | |
1792 | */ | |
c4804214 | 1793 | { .name = "OMAP_CACHEMAINT", .cp = 15, .crn = 7, .crm = CP_ANY, |
d4e6df63 PM |
1794 | .opc1 = 0, .opc2 = CP_ANY, .access = PL1_W, |
1795 | .type = ARM_CP_OVERRIDE | ARM_CP_NO_MIGRATE, | |
c4804214 | 1796 | .writefn = omap_cachemaint_write }, |
34f90529 PM |
1797 | { .name = "C9", .cp = 15, .crn = 9, |
1798 | .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, | |
1799 | .type = ARM_CP_CONST | ARM_CP_OVERRIDE, .resetvalue = 0 }, | |
1047b9d7 PM |
1800 | REGINFO_SENTINEL |
1801 | }; | |
1802 | ||
c4241c7d PM |
1803 | static void xscale_cpar_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1804 | uint64_t value) | |
1047b9d7 | 1805 | { |
c0f4af17 | 1806 | env->cp15.c15_cpar = value & 0x3fff; |
1047b9d7 PM |
1807 | } |
1808 | ||
1809 | static const ARMCPRegInfo xscale_cp_reginfo[] = { | |
1810 | { .name = "XSCALE_CPAR", | |
1811 | .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0, .access = PL1_RW, | |
1812 | .fieldoffset = offsetof(CPUARMState, cp15.c15_cpar), .resetvalue = 0, | |
1813 | .writefn = xscale_cpar_write, }, | |
2771db27 PM |
1814 | { .name = "XSCALE_AUXCR", |
1815 | .cp = 15, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 1, .access = PL1_RW, | |
1816 | .fieldoffset = offsetof(CPUARMState, cp15.c1_xscaleauxcr), | |
1817 | .resetvalue = 0, }, | |
3b771579 PM |
1818 | /* XScale specific cache-lockdown: since we have no cache we NOP these |
1819 | * and hope the guest does not really rely on cache behaviour. | |
1820 | */ | |
1821 | { .name = "XSCALE_LOCK_ICACHE_LINE", | |
1822 | .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 0, | |
1823 | .access = PL1_W, .type = ARM_CP_NOP }, | |
1824 | { .name = "XSCALE_UNLOCK_ICACHE", | |
1825 | .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 1, | |
1826 | .access = PL1_W, .type = ARM_CP_NOP }, | |
1827 | { .name = "XSCALE_DCACHE_LOCK", | |
1828 | .cp = 15, .opc1 = 0, .crn = 9, .crm = 2, .opc2 = 0, | |
1829 | .access = PL1_RW, .type = ARM_CP_NOP }, | |
1830 | { .name = "XSCALE_UNLOCK_DCACHE", | |
1831 | .cp = 15, .opc1 = 0, .crn = 9, .crm = 2, .opc2 = 1, | |
1832 | .access = PL1_W, .type = ARM_CP_NOP }, | |
1047b9d7 PM |
1833 | REGINFO_SENTINEL |
1834 | }; | |
1835 | ||
1836 | static const ARMCPRegInfo dummy_c15_cp_reginfo[] = { | |
1837 | /* RAZ/WI the whole crn=15 space, when we don't have a more specific | |
1838 | * implementation of this implementation-defined space. | |
1839 | * Ideally this should eventually disappear in favour of actually | |
1840 | * implementing the correct behaviour for all cores. | |
1841 | */ | |
1842 | { .name = "C15_IMPDEF", .cp = 15, .crn = 15, | |
1843 | .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY, | |
3671cd87 PC |
1844 | .access = PL1_RW, |
1845 | .type = ARM_CP_CONST | ARM_CP_NO_MIGRATE | ARM_CP_OVERRIDE, | |
d4e6df63 | 1846 | .resetvalue = 0 }, |
18032bec PM |
1847 | REGINFO_SENTINEL |
1848 | }; | |
1849 | ||
c4804214 PM |
1850 | static const ARMCPRegInfo cache_dirty_status_cp_reginfo[] = { |
1851 | /* Cache status: RAZ because we have no cache so it's always clean */ | |
1852 | { .name = "CDSR", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 6, | |
d4e6df63 PM |
1853 | .access = PL1_R, .type = ARM_CP_CONST | ARM_CP_NO_MIGRATE, |
1854 | .resetvalue = 0 }, | |
c4804214 PM |
1855 | REGINFO_SENTINEL |
1856 | }; | |
1857 | ||
1858 | static const ARMCPRegInfo cache_block_ops_cp_reginfo[] = { | |
1859 | /* We never have a a block transfer operation in progress */ | |
1860 | { .name = "BXSR", .cp = 15, .crn = 7, .crm = 12, .opc1 = 0, .opc2 = 4, | |
d4e6df63 PM |
1861 | .access = PL0_R, .type = ARM_CP_CONST | ARM_CP_NO_MIGRATE, |
1862 | .resetvalue = 0 }, | |
30b05bba PM |
1863 | /* The cache ops themselves: these all NOP for QEMU */ |
1864 | { .name = "IICR", .cp = 15, .crm = 5, .opc1 = 0, | |
1865 | .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT }, | |
1866 | { .name = "IDCR", .cp = 15, .crm = 6, .opc1 = 0, | |
1867 | .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT }, | |
1868 | { .name = "CDCR", .cp = 15, .crm = 12, .opc1 = 0, | |
1869 | .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT }, | |
1870 | { .name = "PIR", .cp = 15, .crm = 12, .opc1 = 1, | |
1871 | .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT }, | |
1872 | { .name = "PDR", .cp = 15, .crm = 12, .opc1 = 2, | |
1873 | .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT }, | |
1874 | { .name = "CIDCR", .cp = 15, .crm = 14, .opc1 = 0, | |
1875 | .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT }, | |
c4804214 PM |
1876 | REGINFO_SENTINEL |
1877 | }; | |
1878 | ||
1879 | static const ARMCPRegInfo cache_test_clean_cp_reginfo[] = { | |
1880 | /* The cache test-and-clean instructions always return (1 << 30) | |
1881 | * to indicate that there are no dirty cache lines. | |
1882 | */ | |
1883 | { .name = "TC_DCACHE", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 3, | |
d4e6df63 PM |
1884 | .access = PL0_R, .type = ARM_CP_CONST | ARM_CP_NO_MIGRATE, |
1885 | .resetvalue = (1 << 30) }, | |
c4804214 | 1886 | { .name = "TCI_DCACHE", .cp = 15, .crn = 7, .crm = 14, .opc1 = 0, .opc2 = 3, |
d4e6df63 PM |
1887 | .access = PL0_R, .type = ARM_CP_CONST | ARM_CP_NO_MIGRATE, |
1888 | .resetvalue = (1 << 30) }, | |
c4804214 PM |
1889 | REGINFO_SENTINEL |
1890 | }; | |
1891 | ||
34f90529 PM |
1892 | static const ARMCPRegInfo strongarm_cp_reginfo[] = { |
1893 | /* Ignore ReadBuffer accesses */ | |
1894 | { .name = "C9_READBUFFER", .cp = 15, .crn = 9, | |
1895 | .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY, | |
d4e6df63 PM |
1896 | .access = PL1_RW, .resetvalue = 0, |
1897 | .type = ARM_CP_CONST | ARM_CP_OVERRIDE | ARM_CP_NO_MIGRATE }, | |
34f90529 PM |
1898 | REGINFO_SENTINEL |
1899 | }; | |
1900 | ||
c4241c7d | 1901 | static uint64_t mpidr_read(CPUARMState *env, const ARMCPRegInfo *ri) |
81bdde9d | 1902 | { |
55e5c285 AF |
1903 | CPUState *cs = CPU(arm_env_get_cpu(env)); |
1904 | uint32_t mpidr = cs->cpu_index; | |
4b7fff2f PM |
1905 | /* We don't support setting cluster ID ([8..11]) (known as Aff1 |
1906 | * in later ARM ARM versions), or any of the higher affinity level fields, | |
81bdde9d PM |
1907 | * so these bits always RAZ. |
1908 | */ | |
1909 | if (arm_feature(env, ARM_FEATURE_V7MP)) { | |
78dbbbe4 | 1910 | mpidr |= (1U << 31); |
81bdde9d PM |
1911 | /* Cores which are uniprocessor (non-coherent) |
1912 | * but still implement the MP extensions set | |
1913 | * bit 30. (For instance, A9UP.) However we do | |
1914 | * not currently model any of those cores. | |
1915 | */ | |
1916 | } | |
c4241c7d | 1917 | return mpidr; |
81bdde9d PM |
1918 | } |
1919 | ||
1920 | static const ARMCPRegInfo mpidr_cp_reginfo[] = { | |
4b7fff2f PM |
1921 | { .name = "MPIDR", .state = ARM_CP_STATE_BOTH, |
1922 | .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 5, | |
d4e6df63 | 1923 | .access = PL1_R, .readfn = mpidr_read, .type = ARM_CP_NO_MIGRATE }, |
81bdde9d PM |
1924 | REGINFO_SENTINEL |
1925 | }; | |
1926 | ||
7ac681cf | 1927 | static const ARMCPRegInfo lpae_cp_reginfo[] = { |
b90372ad | 1928 | /* NOP AMAIR0/1: the override is because these clash with the rather |
7ac681cf PM |
1929 | * broadly specified TLB_LOCKDOWN entry in the generic cp_reginfo. |
1930 | */ | |
b0fe2427 PM |
1931 | { .name = "AMAIR0", .state = ARM_CP_STATE_BOTH, |
1932 | .opc0 = 3, .crn = 10, .crm = 3, .opc1 = 0, .opc2 = 0, | |
7ac681cf PM |
1933 | .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_OVERRIDE, |
1934 | .resetvalue = 0 }, | |
b0fe2427 | 1935 | /* AMAIR1 is mapped to AMAIR_EL1[63:32] */ |
7ac681cf PM |
1936 | { .name = "AMAIR1", .cp = 15, .crn = 10, .crm = 3, .opc1 = 0, .opc2 = 1, |
1937 | .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_OVERRIDE, | |
1938 | .resetvalue = 0 }, | |
891a2fe7 | 1939 | { .name = "PAR", .cp = 15, .crm = 7, .opc1 = 0, |
01c097f7 FA |
1940 | .access = PL1_RW, .type = ARM_CP_64BIT, .resetvalue = 0, |
1941 | .bank_fieldoffsets = { offsetof(CPUARMState, cp15.par_s), | |
1942 | offsetof(CPUARMState, cp15.par_ns)} }, | |
891a2fe7 | 1943 | { .name = "TTBR0", .cp = 15, .crm = 2, .opc1 = 0, |
327ed10f | 1944 | .access = PL1_RW, .type = ARM_CP_64BIT | ARM_CP_NO_MIGRATE, |
7dd8c9af FA |
1945 | .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ttbr0_s), |
1946 | offsetof(CPUARMState, cp15.ttbr0_ns) }, | |
327ed10f | 1947 | .writefn = vmsa_ttbr_write, .resetfn = arm_cp_reset_ignore }, |
891a2fe7 | 1948 | { .name = "TTBR1", .cp = 15, .crm = 2, .opc1 = 1, |
327ed10f | 1949 | .access = PL1_RW, .type = ARM_CP_64BIT | ARM_CP_NO_MIGRATE, |
7dd8c9af FA |
1950 | .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ttbr1_s), |
1951 | offsetof(CPUARMState, cp15.ttbr1_ns) }, | |
327ed10f | 1952 | .writefn = vmsa_ttbr_write, .resetfn = arm_cp_reset_ignore }, |
7ac681cf PM |
1953 | REGINFO_SENTINEL |
1954 | }; | |
1955 | ||
c4241c7d | 1956 | static uint64_t aa64_fpcr_read(CPUARMState *env, const ARMCPRegInfo *ri) |
b0d2b7d0 | 1957 | { |
c4241c7d | 1958 | return vfp_get_fpcr(env); |
b0d2b7d0 PM |
1959 | } |
1960 | ||
c4241c7d PM |
1961 | static void aa64_fpcr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1962 | uint64_t value) | |
b0d2b7d0 PM |
1963 | { |
1964 | vfp_set_fpcr(env, value); | |
b0d2b7d0 PM |
1965 | } |
1966 | ||
c4241c7d | 1967 | static uint64_t aa64_fpsr_read(CPUARMState *env, const ARMCPRegInfo *ri) |
b0d2b7d0 | 1968 | { |
c4241c7d | 1969 | return vfp_get_fpsr(env); |
b0d2b7d0 PM |
1970 | } |
1971 | ||
c4241c7d PM |
1972 | static void aa64_fpsr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1973 | uint64_t value) | |
b0d2b7d0 PM |
1974 | { |
1975 | vfp_set_fpsr(env, value); | |
b0d2b7d0 PM |
1976 | } |
1977 | ||
c2b820fe PM |
1978 | static CPAccessResult aa64_daif_access(CPUARMState *env, const ARMCPRegInfo *ri) |
1979 | { | |
137feaa9 | 1980 | if (arm_current_el(env) == 0 && !(env->cp15.sctlr_el[1] & SCTLR_UMA)) { |
c2b820fe PM |
1981 | return CP_ACCESS_TRAP; |
1982 | } | |
1983 | return CP_ACCESS_OK; | |
1984 | } | |
1985 | ||
1986 | static void aa64_daif_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
1987 | uint64_t value) | |
1988 | { | |
1989 | env->daif = value & PSTATE_DAIF; | |
1990 | } | |
1991 | ||
8af35c37 PM |
1992 | static CPAccessResult aa64_cacheop_access(CPUARMState *env, |
1993 | const ARMCPRegInfo *ri) | |
1994 | { | |
1995 | /* Cache invalidate/clean: NOP, but EL0 must UNDEF unless | |
1996 | * SCTLR_EL1.UCI is set. | |
1997 | */ | |
137feaa9 | 1998 | if (arm_current_el(env) == 0 && !(env->cp15.sctlr_el[1] & SCTLR_UCI)) { |
8af35c37 PM |
1999 | return CP_ACCESS_TRAP; |
2000 | } | |
2001 | return CP_ACCESS_OK; | |
2002 | } | |
2003 | ||
dbb1fb27 AB |
2004 | /* See: D4.7.2 TLB maintenance requirements and the TLB maintenance instructions |
2005 | * Page D4-1736 (DDI0487A.b) | |
2006 | */ | |
2007 | ||
168aa23b PM |
2008 | static void tlbi_aa64_va_write(CPUARMState *env, const ARMCPRegInfo *ri, |
2009 | uint64_t value) | |
2010 | { | |
2011 | /* Invalidate by VA (AArch64 version) */ | |
31b030d4 | 2012 | ARMCPU *cpu = arm_env_get_cpu(env); |
dbb1fb27 AB |
2013 | uint64_t pageaddr = sextract64(value << 12, 0, 56); |
2014 | ||
31b030d4 | 2015 | tlb_flush_page(CPU(cpu), pageaddr); |
168aa23b PM |
2016 | } |
2017 | ||
2018 | static void tlbi_aa64_vaa_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
2019 | uint64_t value) | |
2020 | { | |
2021 | /* Invalidate by VA, all ASIDs (AArch64 version) */ | |
31b030d4 | 2022 | ARMCPU *cpu = arm_env_get_cpu(env); |
dbb1fb27 AB |
2023 | uint64_t pageaddr = sextract64(value << 12, 0, 56); |
2024 | ||
31b030d4 | 2025 | tlb_flush_page(CPU(cpu), pageaddr); |
168aa23b PM |
2026 | } |
2027 | ||
2028 | static void tlbi_aa64_asid_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
2029 | uint64_t value) | |
2030 | { | |
2031 | /* Invalidate by ASID (AArch64 version) */ | |
00c8cb0a | 2032 | ARMCPU *cpu = arm_env_get_cpu(env); |
168aa23b | 2033 | int asid = extract64(value, 48, 16); |
00c8cb0a | 2034 | tlb_flush(CPU(cpu), asid == 0); |
168aa23b PM |
2035 | } |
2036 | ||
fa439fc5 PM |
2037 | static void tlbi_aa64_va_is_write(CPUARMState *env, const ARMCPRegInfo *ri, |
2038 | uint64_t value) | |
2039 | { | |
2040 | CPUState *other_cs; | |
2041 | uint64_t pageaddr = sextract64(value << 12, 0, 56); | |
2042 | ||
2043 | CPU_FOREACH(other_cs) { | |
2044 | tlb_flush_page(other_cs, pageaddr); | |
2045 | } | |
2046 | } | |
2047 | ||
2048 | static void tlbi_aa64_vaa_is_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
2049 | uint64_t value) | |
2050 | { | |
2051 | CPUState *other_cs; | |
2052 | uint64_t pageaddr = sextract64(value << 12, 0, 56); | |
2053 | ||
2054 | CPU_FOREACH(other_cs) { | |
2055 | tlb_flush_page(other_cs, pageaddr); | |
2056 | } | |
2057 | } | |
2058 | ||
2059 | static void tlbi_aa64_asid_is_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
2060 | uint64_t value) | |
2061 | { | |
2062 | CPUState *other_cs; | |
2063 | int asid = extract64(value, 48, 16); | |
2064 | ||
2065 | CPU_FOREACH(other_cs) { | |
2066 | tlb_flush(other_cs, asid == 0); | |
2067 | } | |
2068 | } | |
2069 | ||
aca3f40b PM |
2070 | static CPAccessResult aa64_zva_access(CPUARMState *env, const ARMCPRegInfo *ri) |
2071 | { | |
2072 | /* We don't implement EL2, so the only control on DC ZVA is the | |
2073 | * bit in the SCTLR which can prohibit access for EL0. | |
2074 | */ | |
137feaa9 | 2075 | if (arm_current_el(env) == 0 && !(env->cp15.sctlr_el[1] & SCTLR_DZE)) { |
aca3f40b PM |
2076 | return CP_ACCESS_TRAP; |
2077 | } | |
2078 | return CP_ACCESS_OK; | |
2079 | } | |
2080 | ||
2081 | static uint64_t aa64_dczid_read(CPUARMState *env, const ARMCPRegInfo *ri) | |
2082 | { | |
2083 | ARMCPU *cpu = arm_env_get_cpu(env); | |
2084 | int dzp_bit = 1 << 4; | |
2085 | ||
2086 | /* DZP indicates whether DC ZVA access is allowed */ | |
14e5f106 | 2087 | if (aa64_zva_access(env, NULL) == CP_ACCESS_OK) { |
aca3f40b PM |
2088 | dzp_bit = 0; |
2089 | } | |
2090 | return cpu->dcz_blocksize | dzp_bit; | |
2091 | } | |
2092 | ||
f502cfc2 PM |
2093 | static CPAccessResult sp_el0_access(CPUARMState *env, const ARMCPRegInfo *ri) |
2094 | { | |
cdcf1405 | 2095 | if (!(env->pstate & PSTATE_SP)) { |
f502cfc2 PM |
2096 | /* Access to SP_EL0 is undefined if it's being used as |
2097 | * the stack pointer. | |
2098 | */ | |
2099 | return CP_ACCESS_TRAP_UNCATEGORIZED; | |
2100 | } | |
2101 | return CP_ACCESS_OK; | |
2102 | } | |
2103 | ||
2104 | static uint64_t spsel_read(CPUARMState *env, const ARMCPRegInfo *ri) | |
2105 | { | |
2106 | return env->pstate & PSTATE_SP; | |
2107 | } | |
2108 | ||
2109 | static void spsel_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t val) | |
2110 | { | |
2111 | update_spsel(env, val); | |
2112 | } | |
2113 | ||
137feaa9 FA |
2114 | static void sctlr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
2115 | uint64_t value) | |
2116 | { | |
2117 | ARMCPU *cpu = arm_env_get_cpu(env); | |
2118 | ||
2119 | if (raw_read(env, ri) == value) { | |
2120 | /* Skip the TLB flush if nothing actually changed; Linux likes | |
2121 | * to do a lot of pointless SCTLR writes. | |
2122 | */ | |
2123 | return; | |
2124 | } | |
2125 | ||
2126 | raw_write(env, ri, value); | |
2127 | /* ??? Lots of these bits are not implemented. */ | |
2128 | /* This may enable/disable the MMU, so do a TLB flush. */ | |
2129 | tlb_flush(CPU(cpu), 1); | |
2130 | } | |
2131 | ||
b0d2b7d0 PM |
2132 | static const ARMCPRegInfo v8_cp_reginfo[] = { |
2133 | /* Minimal set of EL0-visible registers. This will need to be expanded | |
2134 | * significantly for system emulation of AArch64 CPUs. | |
2135 | */ | |
2136 | { .name = "NZCV", .state = ARM_CP_STATE_AA64, | |
2137 | .opc0 = 3, .opc1 = 3, .opc2 = 0, .crn = 4, .crm = 2, | |
2138 | .access = PL0_RW, .type = ARM_CP_NZCV }, | |
c2b820fe PM |
2139 | { .name = "DAIF", .state = ARM_CP_STATE_AA64, |
2140 | .opc0 = 3, .opc1 = 3, .opc2 = 1, .crn = 4, .crm = 2, | |
2141 | .type = ARM_CP_NO_MIGRATE, | |
2142 | .access = PL0_RW, .accessfn = aa64_daif_access, | |
2143 | .fieldoffset = offsetof(CPUARMState, daif), | |
2144 | .writefn = aa64_daif_write, .resetfn = arm_cp_reset_ignore }, | |
b0d2b7d0 PM |
2145 | { .name = "FPCR", .state = ARM_CP_STATE_AA64, |
2146 | .opc0 = 3, .opc1 = 3, .opc2 = 0, .crn = 4, .crm = 4, | |
2147 | .access = PL0_RW, .readfn = aa64_fpcr_read, .writefn = aa64_fpcr_write }, | |
2148 | { .name = "FPSR", .state = ARM_CP_STATE_AA64, | |
2149 | .opc0 = 3, .opc1 = 3, .opc2 = 1, .crn = 4, .crm = 4, | |
2150 | .access = PL0_RW, .readfn = aa64_fpsr_read, .writefn = aa64_fpsr_write }, | |
b0d2b7d0 PM |
2151 | { .name = "DCZID_EL0", .state = ARM_CP_STATE_AA64, |
2152 | .opc0 = 3, .opc1 = 3, .opc2 = 7, .crn = 0, .crm = 0, | |
aca3f40b PM |
2153 | .access = PL0_R, .type = ARM_CP_NO_MIGRATE, |
2154 | .readfn = aa64_dczid_read }, | |
2155 | { .name = "DC_ZVA", .state = ARM_CP_STATE_AA64, | |
2156 | .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 4, .opc2 = 1, | |
2157 | .access = PL0_W, .type = ARM_CP_DC_ZVA, | |
2158 | #ifndef CONFIG_USER_ONLY | |
2159 | /* Avoid overhead of an access check that always passes in user-mode */ | |
2160 | .accessfn = aa64_zva_access, | |
2161 | #endif | |
2162 | }, | |
0eef9d98 PM |
2163 | { .name = "CURRENTEL", .state = ARM_CP_STATE_AA64, |
2164 | .opc0 = 3, .opc1 = 0, .opc2 = 2, .crn = 4, .crm = 2, | |
2165 | .access = PL1_R, .type = ARM_CP_CURRENTEL }, | |
8af35c37 PM |
2166 | /* Cache ops: all NOPs since we don't emulate caches */ |
2167 | { .name = "IC_IALLUIS", .state = ARM_CP_STATE_AA64, | |
2168 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 1, .opc2 = 0, | |
2169 | .access = PL1_W, .type = ARM_CP_NOP }, | |
2170 | { .name = "IC_IALLU", .state = ARM_CP_STATE_AA64, | |
2171 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 0, | |
2172 | .access = PL1_W, .type = ARM_CP_NOP }, | |
2173 | { .name = "IC_IVAU", .state = ARM_CP_STATE_AA64, | |
2174 | .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 5, .opc2 = 1, | |
2175 | .access = PL0_W, .type = ARM_CP_NOP, | |
2176 | .accessfn = aa64_cacheop_access }, | |
2177 | { .name = "DC_IVAC", .state = ARM_CP_STATE_AA64, | |
2178 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 1, | |
2179 | .access = PL1_W, .type = ARM_CP_NOP }, | |
2180 | { .name = "DC_ISW", .state = ARM_CP_STATE_AA64, | |
2181 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 2, | |
2182 | .access = PL1_W, .type = ARM_CP_NOP }, | |
2183 | { .name = "DC_CVAC", .state = ARM_CP_STATE_AA64, | |
2184 | .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 10, .opc2 = 1, | |
2185 | .access = PL0_W, .type = ARM_CP_NOP, | |
2186 | .accessfn = aa64_cacheop_access }, | |
2187 | { .name = "DC_CSW", .state = ARM_CP_STATE_AA64, | |
2188 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 2, | |
2189 | .access = PL1_W, .type = ARM_CP_NOP }, | |
2190 | { .name = "DC_CVAU", .state = ARM_CP_STATE_AA64, | |
2191 | .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 11, .opc2 = 1, | |
2192 | .access = PL0_W, .type = ARM_CP_NOP, | |
2193 | .accessfn = aa64_cacheop_access }, | |
2194 | { .name = "DC_CIVAC", .state = ARM_CP_STATE_AA64, | |
2195 | .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 14, .opc2 = 1, | |
2196 | .access = PL0_W, .type = ARM_CP_NOP, | |
2197 | .accessfn = aa64_cacheop_access }, | |
2198 | { .name = "DC_CISW", .state = ARM_CP_STATE_AA64, | |
2199 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 2, | |
2200 | .access = PL1_W, .type = ARM_CP_NOP }, | |
168aa23b PM |
2201 | /* TLBI operations */ |
2202 | { .name = "TLBI_VMALLE1IS", .state = ARM_CP_STATE_AA64, | |
6ab9f499 | 2203 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 0, |
168aa23b | 2204 | .access = PL1_W, .type = ARM_CP_NO_MIGRATE, |
fa439fc5 | 2205 | .writefn = tlbiall_is_write }, |
168aa23b | 2206 | { .name = "TLBI_VAE1IS", .state = ARM_CP_STATE_AA64, |
6ab9f499 | 2207 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 1, |
168aa23b | 2208 | .access = PL1_W, .type = ARM_CP_NO_MIGRATE, |
fa439fc5 | 2209 | .writefn = tlbi_aa64_va_is_write }, |
168aa23b | 2210 | { .name = "TLBI_ASIDE1IS", .state = ARM_CP_STATE_AA64, |
6ab9f499 | 2211 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 2, |
168aa23b | 2212 | .access = PL1_W, .type = ARM_CP_NO_MIGRATE, |
fa439fc5 | 2213 | .writefn = tlbi_aa64_asid_is_write }, |
168aa23b | 2214 | { .name = "TLBI_VAAE1IS", .state = ARM_CP_STATE_AA64, |
6ab9f499 | 2215 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 3, |
168aa23b | 2216 | .access = PL1_W, .type = ARM_CP_NO_MIGRATE, |
fa439fc5 | 2217 | .writefn = tlbi_aa64_vaa_is_write }, |
168aa23b | 2218 | { .name = "TLBI_VALE1IS", .state = ARM_CP_STATE_AA64, |
6ab9f499 | 2219 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 5, |
168aa23b | 2220 | .access = PL1_W, .type = ARM_CP_NO_MIGRATE, |
fa439fc5 | 2221 | .writefn = tlbi_aa64_va_is_write }, |
168aa23b | 2222 | { .name = "TLBI_VAALE1IS", .state = ARM_CP_STATE_AA64, |
6ab9f499 | 2223 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 7, |
168aa23b | 2224 | .access = PL1_W, .type = ARM_CP_NO_MIGRATE, |
fa439fc5 | 2225 | .writefn = tlbi_aa64_vaa_is_write }, |
168aa23b | 2226 | { .name = "TLBI_VMALLE1", .state = ARM_CP_STATE_AA64, |
6ab9f499 | 2227 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 0, |
168aa23b PM |
2228 | .access = PL1_W, .type = ARM_CP_NO_MIGRATE, |
2229 | .writefn = tlbiall_write }, | |
2230 | { .name = "TLBI_VAE1", .state = ARM_CP_STATE_AA64, | |
6ab9f499 | 2231 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 1, |
168aa23b PM |
2232 | .access = PL1_W, .type = ARM_CP_NO_MIGRATE, |
2233 | .writefn = tlbi_aa64_va_write }, | |
2234 | { .name = "TLBI_ASIDE1", .state = ARM_CP_STATE_AA64, | |
6ab9f499 | 2235 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 2, |
168aa23b PM |
2236 | .access = PL1_W, .type = ARM_CP_NO_MIGRATE, |
2237 | .writefn = tlbi_aa64_asid_write }, | |
2238 | { .name = "TLBI_VAAE1", .state = ARM_CP_STATE_AA64, | |
6ab9f499 | 2239 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 3, |
168aa23b PM |
2240 | .access = PL1_W, .type = ARM_CP_NO_MIGRATE, |
2241 | .writefn = tlbi_aa64_vaa_write }, | |
2242 | { .name = "TLBI_VALE1", .state = ARM_CP_STATE_AA64, | |
6ab9f499 | 2243 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 5, |
168aa23b PM |
2244 | .access = PL1_W, .type = ARM_CP_NO_MIGRATE, |
2245 | .writefn = tlbi_aa64_va_write }, | |
2246 | { .name = "TLBI_VAALE1", .state = ARM_CP_STATE_AA64, | |
6ab9f499 | 2247 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 7, |
168aa23b PM |
2248 | .access = PL1_W, .type = ARM_CP_NO_MIGRATE, |
2249 | .writefn = tlbi_aa64_vaa_write }, | |
19525524 PM |
2250 | #ifndef CONFIG_USER_ONLY |
2251 | /* 64 bit address translation operations */ | |
2252 | { .name = "AT_S1E1R", .state = ARM_CP_STATE_AA64, | |
2253 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 0, | |
2254 | .access = PL1_W, .type = ARM_CP_NO_MIGRATE, .writefn = ats_write }, | |
2255 | { .name = "AT_S1E1W", .state = ARM_CP_STATE_AA64, | |
2256 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 1, | |
2257 | .access = PL1_W, .type = ARM_CP_NO_MIGRATE, .writefn = ats_write }, | |
2258 | { .name = "AT_S1E0R", .state = ARM_CP_STATE_AA64, | |
2259 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 2, | |
2260 | .access = PL1_W, .type = ARM_CP_NO_MIGRATE, .writefn = ats_write }, | |
2261 | { .name = "AT_S1E0W", .state = ARM_CP_STATE_AA64, | |
2262 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 3, | |
2263 | .access = PL1_W, .type = ARM_CP_NO_MIGRATE, .writefn = ats_write }, | |
2264 | #endif | |
995939a6 | 2265 | /* TLB invalidate last level of translation table walk */ |
9449fdf6 | 2266 | { .name = "TLBIMVALIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 5, |
fa439fc5 | 2267 | .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn = tlbimva_is_write }, |
9449fdf6 | 2268 | { .name = "TLBIMVAALIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 7, |
fa439fc5 PM |
2269 | .type = ARM_CP_NO_MIGRATE, .access = PL1_W, |
2270 | .writefn = tlbimvaa_is_write }, | |
9449fdf6 PM |
2271 | { .name = "TLBIMVAL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 5, |
2272 | .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn = tlbimva_write }, | |
2273 | { .name = "TLBIMVAAL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 7, | |
2274 | .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn = tlbimvaa_write }, | |
2275 | /* 32 bit cache operations */ | |
2276 | { .name = "ICIALLUIS", .cp = 15, .opc1 = 0, .crn = 7, .crm = 1, .opc2 = 0, | |
2277 | .type = ARM_CP_NOP, .access = PL1_W }, | |
2278 | { .name = "BPIALLUIS", .cp = 15, .opc1 = 0, .crn = 7, .crm = 1, .opc2 = 6, | |
2279 | .type = ARM_CP_NOP, .access = PL1_W }, | |
2280 | { .name = "ICIALLU", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 0, | |
2281 | .type = ARM_CP_NOP, .access = PL1_W }, | |
2282 | { .name = "ICIMVAU", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 1, | |
2283 | .type = ARM_CP_NOP, .access = PL1_W }, | |
2284 | { .name = "BPIALL", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 6, | |
2285 | .type = ARM_CP_NOP, .access = PL1_W }, | |
2286 | { .name = "BPIMVA", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 7, | |
2287 | .type = ARM_CP_NOP, .access = PL1_W }, | |
2288 | { .name = "DCIMVAC", .cp = 15, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 1, | |
2289 | .type = ARM_CP_NOP, .access = PL1_W }, | |
2290 | { .name = "DCISW", .cp = 15, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 2, | |
2291 | .type = ARM_CP_NOP, .access = PL1_W }, | |
2292 | { .name = "DCCMVAC", .cp = 15, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 1, | |
2293 | .type = ARM_CP_NOP, .access = PL1_W }, | |
2294 | { .name = "DCCSW", .cp = 15, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 2, | |
2295 | .type = ARM_CP_NOP, .access = PL1_W }, | |
2296 | { .name = "DCCMVAU", .cp = 15, .opc1 = 0, .crn = 7, .crm = 11, .opc2 = 1, | |
2297 | .type = ARM_CP_NOP, .access = PL1_W }, | |
2298 | { .name = "DCCIMVAC", .cp = 15, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 1, | |
2299 | .type = ARM_CP_NOP, .access = PL1_W }, | |
2300 | { .name = "DCCISW", .cp = 15, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 2, | |
2301 | .type = ARM_CP_NOP, .access = PL1_W }, | |
2302 | /* MMU Domain access control / MPU write buffer control */ | |
0c17d68c FA |
2303 | { .name = "DACR", .cp = 15, .opc1 = 0, .crn = 3, .crm = 0, .opc2 = 0, |
2304 | .access = PL1_RW, .resetvalue = 0, | |
2305 | .writefn = dacr_write, .raw_writefn = raw_write, | |
2306 | .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.dacr_s), | |
2307 | offsetoflow32(CPUARMState, cp15.dacr_ns) } }, | |
a0618a19 PM |
2308 | { .name = "ELR_EL1", .state = ARM_CP_STATE_AA64, |
2309 | .type = ARM_CP_NO_MIGRATE, | |
2310 | .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 0, .opc2 = 1, | |
6947f059 EI |
2311 | .access = PL1_RW, |
2312 | .fieldoffset = offsetof(CPUARMState, elr_el[1]) }, | |
a65f1de9 PM |
2313 | { .name = "SPSR_EL1", .state = ARM_CP_STATE_AA64, |
2314 | .type = ARM_CP_NO_MIGRATE, | |
2315 | .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 0, .opc2 = 0, | |
2316 | .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, banked_spsr[0]) }, | |
f502cfc2 PM |
2317 | /* We rely on the access checks not allowing the guest to write to the |
2318 | * state field when SPSel indicates that it's being used as the stack | |
2319 | * pointer. | |
2320 | */ | |
2321 | { .name = "SP_EL0", .state = ARM_CP_STATE_AA64, | |
2322 | .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 1, .opc2 = 0, | |
2323 | .access = PL1_RW, .accessfn = sp_el0_access, | |
2324 | .type = ARM_CP_NO_MIGRATE, | |
2325 | .fieldoffset = offsetof(CPUARMState, sp_el[0]) }, | |
2326 | { .name = "SPSel", .state = ARM_CP_STATE_AA64, | |
2327 | .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 2, .opc2 = 0, | |
2328 | .type = ARM_CP_NO_MIGRATE, | |
2329 | .access = PL1_RW, .readfn = spsel_read, .writefn = spsel_write }, | |
b0d2b7d0 PM |
2330 | REGINFO_SENTINEL |
2331 | }; | |
2332 | ||
d42e3c26 EI |
2333 | /* Used to describe the behaviour of EL2 regs when EL2 does not exist. */ |
2334 | static const ARMCPRegInfo v8_el3_no_el2_cp_reginfo[] = { | |
2335 | { .name = "VBAR_EL2", .state = ARM_CP_STATE_AA64, | |
2336 | .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 0, .opc2 = 0, | |
2337 | .access = PL2_RW, | |
2338 | .readfn = arm_cp_read_zero, .writefn = arm_cp_write_ignore }, | |
f149e3e8 EI |
2339 | { .name = "HCR_EL2", .state = ARM_CP_STATE_AA64, |
2340 | .type = ARM_CP_NO_MIGRATE, | |
2341 | .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 0, | |
2342 | .access = PL2_RW, | |
2343 | .readfn = arm_cp_read_zero, .writefn = arm_cp_write_ignore }, | |
d42e3c26 EI |
2344 | REGINFO_SENTINEL |
2345 | }; | |
2346 | ||
f149e3e8 EI |
2347 | static void hcr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) |
2348 | { | |
2349 | ARMCPU *cpu = arm_env_get_cpu(env); | |
2350 | uint64_t valid_mask = HCR_MASK; | |
2351 | ||
2352 | if (arm_feature(env, ARM_FEATURE_EL3)) { | |
2353 | valid_mask &= ~HCR_HCD; | |
2354 | } else { | |
2355 | valid_mask &= ~HCR_TSC; | |
2356 | } | |
2357 | ||
2358 | /* Clear RES0 bits. */ | |
2359 | value &= valid_mask; | |
2360 | ||
2361 | /* These bits change the MMU setup: | |
2362 | * HCR_VM enables stage 2 translation | |
2363 | * HCR_PTW forbids certain page-table setups | |
2364 | * HCR_DC Disables stage1 and enables stage2 translation | |
2365 | */ | |
2366 | if ((raw_read(env, ri) ^ value) & (HCR_VM | HCR_PTW | HCR_DC)) { | |
2367 | tlb_flush(CPU(cpu), 1); | |
2368 | } | |
2369 | raw_write(env, ri, value); | |
2370 | } | |
2371 | ||
3b685ba7 | 2372 | static const ARMCPRegInfo v8_el2_cp_reginfo[] = { |
f149e3e8 EI |
2373 | { .name = "HCR_EL2", .state = ARM_CP_STATE_AA64, |
2374 | .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 0, | |
2375 | .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.hcr_el2), | |
2376 | .writefn = hcr_write }, | |
0c17d68c FA |
2377 | { .name = "DACR32_EL2", .state = ARM_CP_STATE_AA64, |
2378 | .opc0 = 3, .opc1 = 4, .crn = 3, .crm = 0, .opc2 = 0, | |
2379 | .access = PL2_RW, .resetvalue = 0, | |
2380 | .writefn = dacr_write, .raw_writefn = raw_write, | |
2381 | .fieldoffset = offsetof(CPUARMState, cp15.dacr32_el2) }, | |
3b685ba7 EI |
2382 | { .name = "ELR_EL2", .state = ARM_CP_STATE_AA64, |
2383 | .type = ARM_CP_NO_MIGRATE, | |
2384 | .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 0, .opc2 = 1, | |
2385 | .access = PL2_RW, | |
2386 | .fieldoffset = offsetof(CPUARMState, elr_el[2]) }, | |
f2c30f42 EI |
2387 | { .name = "ESR_EL2", .state = ARM_CP_STATE_AA64, |
2388 | .type = ARM_CP_NO_MIGRATE, | |
2389 | .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 2, .opc2 = 0, | |
2390 | .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.esr_el[2]) }, | |
88ca1c2d FA |
2391 | { .name = "IFSR32_EL2", .state = ARM_CP_STATE_AA64, |
2392 | .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 0, .opc2 = 1, | |
2393 | .access = PL2_RW, .resetvalue = 0, | |
2394 | .fieldoffset = offsetof(CPUARMState, cp15.ifsr32_el2) }, | |
63b60551 EI |
2395 | { .name = "FAR_EL2", .state = ARM_CP_STATE_AA64, |
2396 | .opc0 = 3, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 0, | |
2397 | .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.far_el[2]) }, | |
3b685ba7 EI |
2398 | { .name = "SPSR_EL2", .state = ARM_CP_STATE_AA64, |
2399 | .type = ARM_CP_NO_MIGRATE, | |
2400 | .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 0, .opc2 = 0, | |
2401 | .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, banked_spsr[6]) }, | |
d42e3c26 EI |
2402 | { .name = "VBAR_EL2", .state = ARM_CP_STATE_AA64, |
2403 | .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 0, .opc2 = 0, | |
2404 | .access = PL2_RW, .writefn = vbar_write, | |
2405 | .fieldoffset = offsetof(CPUARMState, cp15.vbar_el[2]), | |
2406 | .resetvalue = 0 }, | |
3b685ba7 EI |
2407 | REGINFO_SENTINEL |
2408 | }; | |
2409 | ||
81547d66 | 2410 | static const ARMCPRegInfo v8_el3_cp_reginfo[] = { |
137feaa9 FA |
2411 | { .name = "SCTLR_EL3", .state = ARM_CP_STATE_AA64, |
2412 | .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 0, .opc2 = 0, | |
2413 | .access = PL3_RW, .raw_writefn = raw_write, .writefn = sctlr_write, | |
2414 | .fieldoffset = offsetof(CPUARMState, cp15.sctlr_el[3]) }, | |
7dd8c9af FA |
2415 | { .name = "TTBR0_EL3", .state = ARM_CP_STATE_AA64, |
2416 | .opc0 = 3, .opc1 = 6, .crn = 2, .crm = 0, .opc2 = 0, | |
2417 | .access = PL3_RW, .writefn = vmsa_ttbr_write, .resetvalue = 0, | |
2418 | .fieldoffset = offsetof(CPUARMState, cp15.ttbr0_el[3]) }, | |
11f136ee FA |
2419 | { .name = "TCR_EL3", .state = ARM_CP_STATE_AA64, |
2420 | .opc0 = 3, .opc1 = 6, .crn = 2, .crm = 0, .opc2 = 2, | |
2421 | .access = PL3_RW, .writefn = vmsa_tcr_el1_write, | |
2422 | .resetfn = vmsa_ttbcr_reset, .raw_writefn = raw_write, | |
2423 | .fieldoffset = offsetof(CPUARMState, cp15.tcr_el[3]) }, | |
81547d66 EI |
2424 | { .name = "ELR_EL3", .state = ARM_CP_STATE_AA64, |
2425 | .type = ARM_CP_NO_MIGRATE, | |
2426 | .opc0 = 3, .opc1 = 6, .crn = 4, .crm = 0, .opc2 = 1, | |
2427 | .access = PL3_RW, | |
2428 | .fieldoffset = offsetof(CPUARMState, elr_el[3]) }, | |
f2c30f42 EI |
2429 | { .name = "ESR_EL3", .state = ARM_CP_STATE_AA64, |
2430 | .type = ARM_CP_NO_MIGRATE, | |
2431 | .opc0 = 3, .opc1 = 6, .crn = 5, .crm = 2, .opc2 = 0, | |
2432 | .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.esr_el[3]) }, | |
63b60551 EI |
2433 | { .name = "FAR_EL3", .state = ARM_CP_STATE_AA64, |
2434 | .opc0 = 3, .opc1 = 6, .crn = 6, .crm = 0, .opc2 = 0, | |
2435 | .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.far_el[3]) }, | |
81547d66 EI |
2436 | { .name = "SPSR_EL3", .state = ARM_CP_STATE_AA64, |
2437 | .type = ARM_CP_NO_MIGRATE, | |
2438 | .opc0 = 3, .opc1 = 6, .crn = 4, .crm = 0, .opc2 = 0, | |
2439 | .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, banked_spsr[7]) }, | |
a1ba125c EI |
2440 | { .name = "VBAR_EL3", .state = ARM_CP_STATE_AA64, |
2441 | .opc0 = 3, .opc1 = 6, .crn = 12, .crm = 0, .opc2 = 0, | |
2442 | .access = PL3_RW, .writefn = vbar_write, | |
2443 | .fieldoffset = offsetof(CPUARMState, cp15.vbar_el[3]), | |
2444 | .resetvalue = 0 }, | |
0f1a3b24 FA |
2445 | REGINFO_SENTINEL |
2446 | }; | |
2447 | ||
2448 | static const ARMCPRegInfo el3_cp_reginfo[] = { | |
64e0e2de | 2449 | { .name = "SCR_EL3", .state = ARM_CP_STATE_AA64, |
64e0e2de EI |
2450 | .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 1, .opc2 = 0, |
2451 | .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.scr_el3), | |
0f1a3b24 FA |
2452 | .resetvalue = 0, .writefn = scr_write }, |
2453 | { .name = "SCR", .type = ARM_CP_NO_MIGRATE, | |
2454 | .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 0, | |
2455 | .access = PL3_RW, .fieldoffset = offsetoflow32(CPUARMState, cp15.scr_el3), | |
2456 | .resetfn = arm_cp_reset_ignore, .writefn = scr_write }, | |
144634ae GB |
2457 | { .name = "SDER32_EL3", .state = ARM_CP_STATE_AA64, |
2458 | .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 1, .opc2 = 1, | |
2459 | .access = PL3_RW, .resetvalue = 0, | |
2460 | .fieldoffset = offsetof(CPUARMState, cp15.sder) }, | |
2461 | { .name = "SDER", | |
2462 | .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 1, | |
2463 | .access = PL3_RW, .resetvalue = 0, | |
2464 | .fieldoffset = offsetoflow32(CPUARMState, cp15.sder) }, | |
77022576 FA |
2465 | /* TODO: Implement NSACR trapping of secure EL1 accesses to EL3 */ |
2466 | { .name = "NSACR", .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 2, | |
2467 | .access = PL3_W | PL1_R, .resetvalue = 0, | |
2468 | .fieldoffset = offsetof(CPUARMState, cp15.nsacr) }, | |
e89e51a1 FA |
2469 | { .name = "MVBAR", .cp = 15, .opc1 = 0, .crn = 12, .crm = 0, .opc2 = 1, |
2470 | .access = PL3_RW, .writefn = vbar_write, .resetvalue = 0, | |
2471 | .fieldoffset = offsetof(CPUARMState, cp15.mvbar) }, | |
81547d66 EI |
2472 | REGINFO_SENTINEL |
2473 | }; | |
2474 | ||
7da845b0 PM |
2475 | static CPAccessResult ctr_el0_access(CPUARMState *env, const ARMCPRegInfo *ri) |
2476 | { | |
2477 | /* Only accessible in EL0 if SCTLR.UCT is set (and only in AArch64, | |
2478 | * but the AArch32 CTR has its own reginfo struct) | |
2479 | */ | |
137feaa9 | 2480 | if (arm_current_el(env) == 0 && !(env->cp15.sctlr_el[1] & SCTLR_UCT)) { |
7da845b0 PM |
2481 | return CP_ACCESS_TRAP; |
2482 | } | |
2483 | return CP_ACCESS_OK; | |
2484 | } | |
2485 | ||
50300698 | 2486 | static const ARMCPRegInfo debug_cp_reginfo[] = { |
50300698 | 2487 | /* DBGDRAR, DBGDSAR: always RAZ since we don't implement memory mapped |
10aae104 PM |
2488 | * debug components. The AArch64 version of DBGDRAR is named MDRAR_EL1; |
2489 | * unlike DBGDRAR it is never accessible from EL0. | |
2490 | * DBGDSAR is deprecated and must RAZ from v8 anyway, so it has no AArch64 | |
2491 | * accessor. | |
50300698 PM |
2492 | */ |
2493 | { .name = "DBGDRAR", .cp = 14, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 0, | |
2494 | .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
10aae104 PM |
2495 | { .name = "MDRAR_EL1", .state = ARM_CP_STATE_AA64, |
2496 | .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 0, | |
2497 | .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
50300698 PM |
2498 | { .name = "DBGDSAR", .cp = 14, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 0, |
2499 | .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
17a9eb53 | 2500 | /* Monitor debug system control register; the 32-bit alias is DBGDSCRext. */ |
10aae104 PM |
2501 | { .name = "MDSCR_EL1", .state = ARM_CP_STATE_BOTH, |
2502 | .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 2, | |
0e5e8935 PM |
2503 | .access = PL1_RW, |
2504 | .fieldoffset = offsetof(CPUARMState, cp15.mdscr_el1), | |
2505 | .resetvalue = 0 }, | |
5e8b12ff PM |
2506 | /* MDCCSR_EL0, aka DBGDSCRint. This is a read-only mirror of MDSCR_EL1. |
2507 | * We don't implement the configurable EL0 access. | |
2508 | */ | |
2509 | { .name = "MDCCSR_EL0", .state = ARM_CP_STATE_BOTH, | |
2510 | .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 0, | |
2511 | .type = ARM_CP_NO_MIGRATE, | |
2512 | .access = PL1_R, | |
2513 | .fieldoffset = offsetof(CPUARMState, cp15.mdscr_el1), | |
2514 | .resetfn = arm_cp_reset_ignore }, | |
50300698 | 2515 | /* We define a dummy WI OSLAR_EL1, because Linux writes to it. */ |
10aae104 PM |
2516 | { .name = "OSLAR_EL1", .state = ARM_CP_STATE_BOTH, |
2517 | .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 4, | |
50300698 | 2518 | .access = PL1_W, .type = ARM_CP_NOP }, |
5e8b12ff PM |
2519 | /* Dummy OSDLR_EL1: 32-bit Linux will read this */ |
2520 | { .name = "OSDLR_EL1", .state = ARM_CP_STATE_BOTH, | |
2521 | .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 3, .opc2 = 4, | |
2522 | .access = PL1_RW, .type = ARM_CP_NOP }, | |
2523 | /* Dummy DBGVCR: Linux wants to clear this on startup, but we don't | |
2524 | * implement vector catch debug events yet. | |
2525 | */ | |
2526 | { .name = "DBGVCR", | |
2527 | .cp = 14, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 0, | |
2528 | .access = PL1_RW, .type = ARM_CP_NOP }, | |
50300698 PM |
2529 | REGINFO_SENTINEL |
2530 | }; | |
2531 | ||
2532 | static const ARMCPRegInfo debug_lpae_cp_reginfo[] = { | |
2533 | /* 64 bit access versions of the (dummy) debug registers */ | |
2534 | { .name = "DBGDRAR", .cp = 14, .crm = 1, .opc1 = 0, | |
2535 | .access = PL0_R, .type = ARM_CP_CONST|ARM_CP_64BIT, .resetvalue = 0 }, | |
2536 | { .name = "DBGDSAR", .cp = 14, .crm = 2, .opc1 = 0, | |
2537 | .access = PL0_R, .type = ARM_CP_CONST|ARM_CP_64BIT, .resetvalue = 0 }, | |
2538 | REGINFO_SENTINEL | |
2539 | }; | |
2540 | ||
9ee98ce8 PM |
2541 | void hw_watchpoint_update(ARMCPU *cpu, int n) |
2542 | { | |
2543 | CPUARMState *env = &cpu->env; | |
2544 | vaddr len = 0; | |
2545 | vaddr wvr = env->cp15.dbgwvr[n]; | |
2546 | uint64_t wcr = env->cp15.dbgwcr[n]; | |
2547 | int mask; | |
2548 | int flags = BP_CPU | BP_STOP_BEFORE_ACCESS; | |
2549 | ||
2550 | if (env->cpu_watchpoint[n]) { | |
2551 | cpu_watchpoint_remove_by_ref(CPU(cpu), env->cpu_watchpoint[n]); | |
2552 | env->cpu_watchpoint[n] = NULL; | |
2553 | } | |
2554 | ||
2555 | if (!extract64(wcr, 0, 1)) { | |
2556 | /* E bit clear : watchpoint disabled */ | |
2557 | return; | |
2558 | } | |
2559 | ||
2560 | switch (extract64(wcr, 3, 2)) { | |
2561 | case 0: | |
2562 | /* LSC 00 is reserved and must behave as if the wp is disabled */ | |
2563 | return; | |
2564 | case 1: | |
2565 | flags |= BP_MEM_READ; | |
2566 | break; | |
2567 | case 2: | |
2568 | flags |= BP_MEM_WRITE; | |
2569 | break; | |
2570 | case 3: | |
2571 | flags |= BP_MEM_ACCESS; | |
2572 | break; | |
2573 | } | |
2574 | ||
2575 | /* Attempts to use both MASK and BAS fields simultaneously are | |
2576 | * CONSTRAINED UNPREDICTABLE; we opt to ignore BAS in this case, | |
2577 | * thus generating a watchpoint for every byte in the masked region. | |
2578 | */ | |
2579 | mask = extract64(wcr, 24, 4); | |
2580 | if (mask == 1 || mask == 2) { | |
2581 | /* Reserved values of MASK; we must act as if the mask value was | |
2582 | * some non-reserved value, or as if the watchpoint were disabled. | |
2583 | * We choose the latter. | |
2584 | */ | |
2585 | return; | |
2586 | } else if (mask) { | |
2587 | /* Watchpoint covers an aligned area up to 2GB in size */ | |
2588 | len = 1ULL << mask; | |
2589 | /* If masked bits in WVR are not zero it's CONSTRAINED UNPREDICTABLE | |
2590 | * whether the watchpoint fires when the unmasked bits match; we opt | |
2591 | * to generate the exceptions. | |
2592 | */ | |
2593 | wvr &= ~(len - 1); | |
2594 | } else { | |
2595 | /* Watchpoint covers bytes defined by the byte address select bits */ | |
2596 | int bas = extract64(wcr, 5, 8); | |
2597 | int basstart; | |
2598 | ||
2599 | if (bas == 0) { | |
2600 | /* This must act as if the watchpoint is disabled */ | |
2601 | return; | |
2602 | } | |
2603 | ||
2604 | if (extract64(wvr, 2, 1)) { | |
2605 | /* Deprecated case of an only 4-aligned address. BAS[7:4] are | |
2606 | * ignored, and BAS[3:0] define which bytes to watch. | |
2607 | */ | |
2608 | bas &= 0xf; | |
2609 | } | |
2610 | /* The BAS bits are supposed to be programmed to indicate a contiguous | |
2611 | * range of bytes. Otherwise it is CONSTRAINED UNPREDICTABLE whether | |
2612 | * we fire for each byte in the word/doubleword addressed by the WVR. | |
2613 | * We choose to ignore any non-zero bits after the first range of 1s. | |
2614 | */ | |
2615 | basstart = ctz32(bas); | |
2616 | len = cto32(bas >> basstart); | |
2617 | wvr += basstart; | |
2618 | } | |
2619 | ||
2620 | cpu_watchpoint_insert(CPU(cpu), wvr, len, flags, | |
2621 | &env->cpu_watchpoint[n]); | |
2622 | } | |
2623 | ||
2624 | void hw_watchpoint_update_all(ARMCPU *cpu) | |
2625 | { | |
2626 | int i; | |
2627 | CPUARMState *env = &cpu->env; | |
2628 | ||
2629 | /* Completely clear out existing QEMU watchpoints and our array, to | |
2630 | * avoid possible stale entries following migration load. | |
2631 | */ | |
2632 | cpu_watchpoint_remove_all(CPU(cpu), BP_CPU); | |
2633 | memset(env->cpu_watchpoint, 0, sizeof(env->cpu_watchpoint)); | |
2634 | ||
2635 | for (i = 0; i < ARRAY_SIZE(cpu->env.cpu_watchpoint); i++) { | |
2636 | hw_watchpoint_update(cpu, i); | |
2637 | } | |
2638 | } | |
2639 | ||
2640 | static void dbgwvr_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
2641 | uint64_t value) | |
2642 | { | |
2643 | ARMCPU *cpu = arm_env_get_cpu(env); | |
2644 | int i = ri->crm; | |
2645 | ||
2646 | /* Bits [63:49] are hardwired to the value of bit [48]; that is, the | |
2647 | * register reads and behaves as if values written are sign extended. | |
2648 | * Bits [1:0] are RES0. | |
2649 | */ | |
2650 | value = sextract64(value, 0, 49) & ~3ULL; | |
2651 | ||
2652 | raw_write(env, ri, value); | |
2653 | hw_watchpoint_update(cpu, i); | |
2654 | } | |
2655 | ||
2656 | static void dbgwcr_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
2657 | uint64_t value) | |
2658 | { | |
2659 | ARMCPU *cpu = arm_env_get_cpu(env); | |
2660 | int i = ri->crm; | |
2661 | ||
2662 | raw_write(env, ri, value); | |
2663 | hw_watchpoint_update(cpu, i); | |
2664 | } | |
2665 | ||
46747d15 PM |
2666 | void hw_breakpoint_update(ARMCPU *cpu, int n) |
2667 | { | |
2668 | CPUARMState *env = &cpu->env; | |
2669 | uint64_t bvr = env->cp15.dbgbvr[n]; | |
2670 | uint64_t bcr = env->cp15.dbgbcr[n]; | |
2671 | vaddr addr; | |
2672 | int bt; | |
2673 | int flags = BP_CPU; | |
2674 | ||
2675 | if (env->cpu_breakpoint[n]) { | |
2676 | cpu_breakpoint_remove_by_ref(CPU(cpu), env->cpu_breakpoint[n]); | |
2677 | env->cpu_breakpoint[n] = NULL; | |
2678 | } | |
2679 | ||
2680 | if (!extract64(bcr, 0, 1)) { | |
2681 | /* E bit clear : watchpoint disabled */ | |
2682 | return; | |
2683 | } | |
2684 | ||
2685 | bt = extract64(bcr, 20, 4); | |
2686 | ||
2687 | switch (bt) { | |
2688 | case 4: /* unlinked address mismatch (reserved if AArch64) */ | |
2689 | case 5: /* linked address mismatch (reserved if AArch64) */ | |
2690 | qemu_log_mask(LOG_UNIMP, | |
2691 | "arm: address mismatch breakpoint types not implemented"); | |
2692 | return; | |
2693 | case 0: /* unlinked address match */ | |
2694 | case 1: /* linked address match */ | |
2695 | { | |
2696 | /* Bits [63:49] are hardwired to the value of bit [48]; that is, | |
2697 | * we behave as if the register was sign extended. Bits [1:0] are | |
2698 | * RES0. The BAS field is used to allow setting breakpoints on 16 | |
2699 | * bit wide instructions; it is CONSTRAINED UNPREDICTABLE whether | |
2700 | * a bp will fire if the addresses covered by the bp and the addresses | |
2701 | * covered by the insn overlap but the insn doesn't start at the | |
2702 | * start of the bp address range. We choose to require the insn and | |
2703 | * the bp to have the same address. The constraints on writing to | |
2704 | * BAS enforced in dbgbcr_write mean we have only four cases: | |
2705 | * 0b0000 => no breakpoint | |
2706 | * 0b0011 => breakpoint on addr | |
2707 | * 0b1100 => breakpoint on addr + 2 | |
2708 | * 0b1111 => breakpoint on addr | |
2709 | * See also figure D2-3 in the v8 ARM ARM (DDI0487A.c). | |
2710 | */ | |
2711 | int bas = extract64(bcr, 5, 4); | |
2712 | addr = sextract64(bvr, 0, 49) & ~3ULL; | |
2713 | if (bas == 0) { | |
2714 | return; | |
2715 | } | |
2716 | if (bas == 0xc) { | |
2717 | addr += 2; | |
2718 | } | |
2719 | break; | |
2720 | } | |
2721 | case 2: /* unlinked context ID match */ | |
2722 | case 8: /* unlinked VMID match (reserved if no EL2) */ | |
2723 | case 10: /* unlinked context ID and VMID match (reserved if no EL2) */ | |
2724 | qemu_log_mask(LOG_UNIMP, | |
2725 | "arm: unlinked context breakpoint types not implemented"); | |
2726 | return; | |
2727 | case 9: /* linked VMID match (reserved if no EL2) */ | |
2728 | case 11: /* linked context ID and VMID match (reserved if no EL2) */ | |
2729 | case 3: /* linked context ID match */ | |
2730 | default: | |
2731 | /* We must generate no events for Linked context matches (unless | |
2732 | * they are linked to by some other bp/wp, which is handled in | |
2733 | * updates for the linking bp/wp). We choose to also generate no events | |
2734 | * for reserved values. | |
2735 | */ | |
2736 | return; | |
2737 | } | |
2738 | ||
2739 | cpu_breakpoint_insert(CPU(cpu), addr, flags, &env->cpu_breakpoint[n]); | |
2740 | } | |
2741 | ||
2742 | void hw_breakpoint_update_all(ARMCPU *cpu) | |
2743 | { | |
2744 | int i; | |
2745 | CPUARMState *env = &cpu->env; | |
2746 | ||
2747 | /* Completely clear out existing QEMU breakpoints and our array, to | |
2748 | * avoid possible stale entries following migration load. | |
2749 | */ | |
2750 | cpu_breakpoint_remove_all(CPU(cpu), BP_CPU); | |
2751 | memset(env->cpu_breakpoint, 0, sizeof(env->cpu_breakpoint)); | |
2752 | ||
2753 | for (i = 0; i < ARRAY_SIZE(cpu->env.cpu_breakpoint); i++) { | |
2754 | hw_breakpoint_update(cpu, i); | |
2755 | } | |
2756 | } | |
2757 | ||
2758 | static void dbgbvr_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
2759 | uint64_t value) | |
2760 | { | |
2761 | ARMCPU *cpu = arm_env_get_cpu(env); | |
2762 | int i = ri->crm; | |
2763 | ||
2764 | raw_write(env, ri, value); | |
2765 | hw_breakpoint_update(cpu, i); | |
2766 | } | |
2767 | ||
2768 | static void dbgbcr_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
2769 | uint64_t value) | |
2770 | { | |
2771 | ARMCPU *cpu = arm_env_get_cpu(env); | |
2772 | int i = ri->crm; | |
2773 | ||
2774 | /* BAS[3] is a read-only copy of BAS[2], and BAS[1] a read-only | |
2775 | * copy of BAS[0]. | |
2776 | */ | |
2777 | value = deposit64(value, 6, 1, extract64(value, 5, 1)); | |
2778 | value = deposit64(value, 8, 1, extract64(value, 7, 1)); | |
2779 | ||
2780 | raw_write(env, ri, value); | |
2781 | hw_breakpoint_update(cpu, i); | |
2782 | } | |
2783 | ||
50300698 | 2784 | static void define_debug_regs(ARMCPU *cpu) |
0b45451e | 2785 | { |
50300698 PM |
2786 | /* Define v7 and v8 architectural debug registers. |
2787 | * These are just dummy implementations for now. | |
0b45451e PM |
2788 | */ |
2789 | int i; | |
3ff6fc91 | 2790 | int wrps, brps, ctx_cmps; |
48eb3ae6 PM |
2791 | ARMCPRegInfo dbgdidr = { |
2792 | .name = "DBGDIDR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 0, | |
2793 | .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = cpu->dbgdidr, | |
2794 | }; | |
2795 | ||
3ff6fc91 | 2796 | /* Note that all these register fields hold "number of Xs minus 1". */ |
48eb3ae6 PM |
2797 | brps = extract32(cpu->dbgdidr, 24, 4); |
2798 | wrps = extract32(cpu->dbgdidr, 28, 4); | |
3ff6fc91 PM |
2799 | ctx_cmps = extract32(cpu->dbgdidr, 20, 4); |
2800 | ||
2801 | assert(ctx_cmps <= brps); | |
48eb3ae6 PM |
2802 | |
2803 | /* The DBGDIDR and ID_AA64DFR0_EL1 define various properties | |
2804 | * of the debug registers such as number of breakpoints; | |
2805 | * check that if they both exist then they agree. | |
2806 | */ | |
2807 | if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { | |
2808 | assert(extract32(cpu->id_aa64dfr0, 12, 4) == brps); | |
2809 | assert(extract32(cpu->id_aa64dfr0, 20, 4) == wrps); | |
3ff6fc91 | 2810 | assert(extract32(cpu->id_aa64dfr0, 28, 4) == ctx_cmps); |
48eb3ae6 | 2811 | } |
0b45451e | 2812 | |
48eb3ae6 | 2813 | define_one_arm_cp_reg(cpu, &dbgdidr); |
50300698 PM |
2814 | define_arm_cp_regs(cpu, debug_cp_reginfo); |
2815 | ||
2816 | if (arm_feature(&cpu->env, ARM_FEATURE_LPAE)) { | |
2817 | define_arm_cp_regs(cpu, debug_lpae_cp_reginfo); | |
2818 | } | |
2819 | ||
48eb3ae6 | 2820 | for (i = 0; i < brps + 1; i++) { |
0b45451e | 2821 | ARMCPRegInfo dbgregs[] = { |
10aae104 PM |
2822 | { .name = "DBGBVR", .state = ARM_CP_STATE_BOTH, |
2823 | .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 4, | |
0b45451e | 2824 | .access = PL1_RW, |
46747d15 PM |
2825 | .fieldoffset = offsetof(CPUARMState, cp15.dbgbvr[i]), |
2826 | .writefn = dbgbvr_write, .raw_writefn = raw_write | |
2827 | }, | |
10aae104 PM |
2828 | { .name = "DBGBCR", .state = ARM_CP_STATE_BOTH, |
2829 | .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 5, | |
0b45451e | 2830 | .access = PL1_RW, |
46747d15 PM |
2831 | .fieldoffset = offsetof(CPUARMState, cp15.dbgbcr[i]), |
2832 | .writefn = dbgbcr_write, .raw_writefn = raw_write | |
2833 | }, | |
48eb3ae6 PM |
2834 | REGINFO_SENTINEL |
2835 | }; | |
2836 | define_arm_cp_regs(cpu, dbgregs); | |
2837 | } | |
2838 | ||
2839 | for (i = 0; i < wrps + 1; i++) { | |
2840 | ARMCPRegInfo dbgregs[] = { | |
10aae104 PM |
2841 | { .name = "DBGWVR", .state = ARM_CP_STATE_BOTH, |
2842 | .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 6, | |
0b45451e | 2843 | .access = PL1_RW, |
9ee98ce8 PM |
2844 | .fieldoffset = offsetof(CPUARMState, cp15.dbgwvr[i]), |
2845 | .writefn = dbgwvr_write, .raw_writefn = raw_write | |
2846 | }, | |
10aae104 PM |
2847 | { .name = "DBGWCR", .state = ARM_CP_STATE_BOTH, |
2848 | .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 7, | |
0b45451e | 2849 | .access = PL1_RW, |
9ee98ce8 PM |
2850 | .fieldoffset = offsetof(CPUARMState, cp15.dbgwcr[i]), |
2851 | .writefn = dbgwcr_write, .raw_writefn = raw_write | |
2852 | }, | |
2853 | REGINFO_SENTINEL | |
0b45451e PM |
2854 | }; |
2855 | define_arm_cp_regs(cpu, dbgregs); | |
2856 | } | |
2857 | } | |
2858 | ||
2ceb98c0 PM |
2859 | void register_cp_regs_for_features(ARMCPU *cpu) |
2860 | { | |
2861 | /* Register all the coprocessor registers based on feature bits */ | |
2862 | CPUARMState *env = &cpu->env; | |
2863 | if (arm_feature(env, ARM_FEATURE_M)) { | |
2864 | /* M profile has no coprocessor registers */ | |
2865 | return; | |
2866 | } | |
2867 | ||
e9aa6c21 | 2868 | define_arm_cp_regs(cpu, cp_reginfo); |
9449fdf6 PM |
2869 | if (!arm_feature(env, ARM_FEATURE_V8)) { |
2870 | /* Must go early as it is full of wildcards that may be | |
2871 | * overridden by later definitions. | |
2872 | */ | |
2873 | define_arm_cp_regs(cpu, not_v8_cp_reginfo); | |
2874 | } | |
2875 | ||
7d57f408 | 2876 | if (arm_feature(env, ARM_FEATURE_V6)) { |
8515a092 PM |
2877 | /* The ID registers all have impdef reset values */ |
2878 | ARMCPRegInfo v6_idregs[] = { | |
0ff644a7 PM |
2879 | { .name = "ID_PFR0", .state = ARM_CP_STATE_BOTH, |
2880 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 0, | |
2881 | .access = PL1_R, .type = ARM_CP_CONST, | |
8515a092 | 2882 | .resetvalue = cpu->id_pfr0 }, |
0ff644a7 PM |
2883 | { .name = "ID_PFR1", .state = ARM_CP_STATE_BOTH, |
2884 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 1, | |
2885 | .access = PL1_R, .type = ARM_CP_CONST, | |
8515a092 | 2886 | .resetvalue = cpu->id_pfr1 }, |
0ff644a7 PM |
2887 | { .name = "ID_DFR0", .state = ARM_CP_STATE_BOTH, |
2888 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 2, | |
2889 | .access = PL1_R, .type = ARM_CP_CONST, | |
8515a092 | 2890 | .resetvalue = cpu->id_dfr0 }, |
0ff644a7 PM |
2891 | { .name = "ID_AFR0", .state = ARM_CP_STATE_BOTH, |
2892 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 3, | |
2893 | .access = PL1_R, .type = ARM_CP_CONST, | |
8515a092 | 2894 | .resetvalue = cpu->id_afr0 }, |
0ff644a7 PM |
2895 | { .name = "ID_MMFR0", .state = ARM_CP_STATE_BOTH, |
2896 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 4, | |
2897 | .access = PL1_R, .type = ARM_CP_CONST, | |
8515a092 | 2898 | .resetvalue = cpu->id_mmfr0 }, |
0ff644a7 PM |
2899 | { .name = "ID_MMFR1", .state = ARM_CP_STATE_BOTH, |
2900 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 5, | |
2901 | .access = PL1_R, .type = ARM_CP_CONST, | |
8515a092 | 2902 | .resetvalue = cpu->id_mmfr1 }, |
0ff644a7 PM |
2903 | { .name = "ID_MMFR2", .state = ARM_CP_STATE_BOTH, |
2904 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 6, | |
2905 | .access = PL1_R, .type = ARM_CP_CONST, | |
8515a092 | 2906 | .resetvalue = cpu->id_mmfr2 }, |
0ff644a7 PM |
2907 | { .name = "ID_MMFR3", .state = ARM_CP_STATE_BOTH, |
2908 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 7, | |
2909 | .access = PL1_R, .type = ARM_CP_CONST, | |
8515a092 | 2910 | .resetvalue = cpu->id_mmfr3 }, |
0ff644a7 PM |
2911 | { .name = "ID_ISAR0", .state = ARM_CP_STATE_BOTH, |
2912 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 0, | |
2913 | .access = PL1_R, .type = ARM_CP_CONST, | |
8515a092 | 2914 | .resetvalue = cpu->id_isar0 }, |
0ff644a7 PM |
2915 | { .name = "ID_ISAR1", .state = ARM_CP_STATE_BOTH, |
2916 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 1, | |
2917 | .access = PL1_R, .type = ARM_CP_CONST, | |
8515a092 | 2918 | .resetvalue = cpu->id_isar1 }, |
0ff644a7 PM |
2919 | { .name = "ID_ISAR2", .state = ARM_CP_STATE_BOTH, |
2920 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 2, | |
2921 | .access = PL1_R, .type = ARM_CP_CONST, | |
8515a092 | 2922 | .resetvalue = cpu->id_isar2 }, |
0ff644a7 PM |
2923 | { .name = "ID_ISAR3", .state = ARM_CP_STATE_BOTH, |
2924 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 3, | |
2925 | .access = PL1_R, .type = ARM_CP_CONST, | |
8515a092 | 2926 | .resetvalue = cpu->id_isar3 }, |
0ff644a7 PM |
2927 | { .name = "ID_ISAR4", .state = ARM_CP_STATE_BOTH, |
2928 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 4, | |
2929 | .access = PL1_R, .type = ARM_CP_CONST, | |
8515a092 | 2930 | .resetvalue = cpu->id_isar4 }, |
0ff644a7 PM |
2931 | { .name = "ID_ISAR5", .state = ARM_CP_STATE_BOTH, |
2932 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 5, | |
2933 | .access = PL1_R, .type = ARM_CP_CONST, | |
8515a092 PM |
2934 | .resetvalue = cpu->id_isar5 }, |
2935 | /* 6..7 are as yet unallocated and must RAZ */ | |
2936 | { .name = "ID_ISAR6", .cp = 15, .crn = 0, .crm = 2, | |
2937 | .opc1 = 0, .opc2 = 6, .access = PL1_R, .type = ARM_CP_CONST, | |
2938 | .resetvalue = 0 }, | |
2939 | { .name = "ID_ISAR7", .cp = 15, .crn = 0, .crm = 2, | |
2940 | .opc1 = 0, .opc2 = 7, .access = PL1_R, .type = ARM_CP_CONST, | |
2941 | .resetvalue = 0 }, | |
2942 | REGINFO_SENTINEL | |
2943 | }; | |
2944 | define_arm_cp_regs(cpu, v6_idregs); | |
7d57f408 PM |
2945 | define_arm_cp_regs(cpu, v6_cp_reginfo); |
2946 | } else { | |
2947 | define_arm_cp_regs(cpu, not_v6_cp_reginfo); | |
2948 | } | |
4d31c596 PM |
2949 | if (arm_feature(env, ARM_FEATURE_V6K)) { |
2950 | define_arm_cp_regs(cpu, v6k_cp_reginfo); | |
2951 | } | |
995939a6 PM |
2952 | if (arm_feature(env, ARM_FEATURE_V7MP)) { |
2953 | define_arm_cp_regs(cpu, v7mp_cp_reginfo); | |
2954 | } | |
e9aa6c21 | 2955 | if (arm_feature(env, ARM_FEATURE_V7)) { |
200ac0ef | 2956 | /* v7 performance monitor control register: same implementor |
7c2cb42b AF |
2957 | * field as main ID register, and we implement only the cycle |
2958 | * count register. | |
200ac0ef | 2959 | */ |
7c2cb42b | 2960 | #ifndef CONFIG_USER_ONLY |
200ac0ef PM |
2961 | ARMCPRegInfo pmcr = { |
2962 | .name = "PMCR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 0, | |
8521466b AF |
2963 | .access = PL0_RW, |
2964 | .type = ARM_CP_IO | ARM_CP_NO_MIGRATE, | |
2965 | .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmcr), | |
fcd25206 PM |
2966 | .accessfn = pmreg_access, .writefn = pmcr_write, |
2967 | .raw_writefn = raw_write, | |
200ac0ef | 2968 | }; |
8521466b AF |
2969 | ARMCPRegInfo pmcr64 = { |
2970 | .name = "PMCR_EL0", .state = ARM_CP_STATE_AA64, | |
2971 | .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 0, | |
2972 | .access = PL0_RW, .accessfn = pmreg_access, | |
2973 | .type = ARM_CP_IO, | |
2974 | .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcr), | |
2975 | .resetvalue = cpu->midr & 0xff000000, | |
2976 | .writefn = pmcr_write, .raw_writefn = raw_write, | |
2977 | }; | |
7c2cb42b | 2978 | define_one_arm_cp_reg(cpu, &pmcr); |
8521466b | 2979 | define_one_arm_cp_reg(cpu, &pmcr64); |
7c2cb42b | 2980 | #endif |
776d4e5c | 2981 | ARMCPRegInfo clidr = { |
7da845b0 PM |
2982 | .name = "CLIDR", .state = ARM_CP_STATE_BOTH, |
2983 | .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 1, | |
776d4e5c PM |
2984 | .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = cpu->clidr |
2985 | }; | |
776d4e5c | 2986 | define_one_arm_cp_reg(cpu, &clidr); |
e9aa6c21 | 2987 | define_arm_cp_regs(cpu, v7_cp_reginfo); |
50300698 | 2988 | define_debug_regs(cpu); |
7d57f408 PM |
2989 | } else { |
2990 | define_arm_cp_regs(cpu, not_v7_cp_reginfo); | |
e9aa6c21 | 2991 | } |
b0d2b7d0 | 2992 | if (arm_feature(env, ARM_FEATURE_V8)) { |
e60cef86 PM |
2993 | /* AArch64 ID registers, which all have impdef reset values */ |
2994 | ARMCPRegInfo v8_idregs[] = { | |
2995 | { .name = "ID_AA64PFR0_EL1", .state = ARM_CP_STATE_AA64, | |
2996 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 0, | |
2997 | .access = PL1_R, .type = ARM_CP_CONST, | |
2998 | .resetvalue = cpu->id_aa64pfr0 }, | |
2999 | { .name = "ID_AA64PFR1_EL1", .state = ARM_CP_STATE_AA64, | |
3000 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 1, | |
3001 | .access = PL1_R, .type = ARM_CP_CONST, | |
3002 | .resetvalue = cpu->id_aa64pfr1}, | |
3003 | { .name = "ID_AA64DFR0_EL1", .state = ARM_CP_STATE_AA64, | |
3004 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 0, | |
3005 | .access = PL1_R, .type = ARM_CP_CONST, | |
5d831be2 | 3006 | /* We mask out the PMUVer field, because we don't currently |
9225d739 PM |
3007 | * implement the PMU. Not advertising it prevents the guest |
3008 | * from trying to use it and getting UNDEFs on registers we | |
3009 | * don't implement. | |
3010 | */ | |
3011 | .resetvalue = cpu->id_aa64dfr0 & ~0xf00 }, | |
e60cef86 PM |
3012 | { .name = "ID_AA64DFR1_EL1", .state = ARM_CP_STATE_AA64, |
3013 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 1, | |
3014 | .access = PL1_R, .type = ARM_CP_CONST, | |
3015 | .resetvalue = cpu->id_aa64dfr1 }, | |
3016 | { .name = "ID_AA64AFR0_EL1", .state = ARM_CP_STATE_AA64, | |
3017 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 4, | |
3018 | .access = PL1_R, .type = ARM_CP_CONST, | |
3019 | .resetvalue = cpu->id_aa64afr0 }, | |
3020 | { .name = "ID_AA64AFR1_EL1", .state = ARM_CP_STATE_AA64, | |
3021 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 5, | |
3022 | .access = PL1_R, .type = ARM_CP_CONST, | |
3023 | .resetvalue = cpu->id_aa64afr1 }, | |
3024 | { .name = "ID_AA64ISAR0_EL1", .state = ARM_CP_STATE_AA64, | |
3025 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 0, | |
3026 | .access = PL1_R, .type = ARM_CP_CONST, | |
3027 | .resetvalue = cpu->id_aa64isar0 }, | |
3028 | { .name = "ID_AA64ISAR1_EL1", .state = ARM_CP_STATE_AA64, | |
3029 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 1, | |
3030 | .access = PL1_R, .type = ARM_CP_CONST, | |
3031 | .resetvalue = cpu->id_aa64isar1 }, | |
3032 | { .name = "ID_AA64MMFR0_EL1", .state = ARM_CP_STATE_AA64, | |
3033 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 0, | |
3034 | .access = PL1_R, .type = ARM_CP_CONST, | |
3035 | .resetvalue = cpu->id_aa64mmfr0 }, | |
3036 | { .name = "ID_AA64MMFR1_EL1", .state = ARM_CP_STATE_AA64, | |
3037 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 1, | |
3038 | .access = PL1_R, .type = ARM_CP_CONST, | |
3039 | .resetvalue = cpu->id_aa64mmfr1 }, | |
a50c0f51 PM |
3040 | { .name = "MVFR0_EL1", .state = ARM_CP_STATE_AA64, |
3041 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 0, | |
3042 | .access = PL1_R, .type = ARM_CP_CONST, | |
3043 | .resetvalue = cpu->mvfr0 }, | |
3044 | { .name = "MVFR1_EL1", .state = ARM_CP_STATE_AA64, | |
3045 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 1, | |
3046 | .access = PL1_R, .type = ARM_CP_CONST, | |
3047 | .resetvalue = cpu->mvfr1 }, | |
3048 | { .name = "MVFR2_EL1", .state = ARM_CP_STATE_AA64, | |
3049 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 2, | |
3050 | .access = PL1_R, .type = ARM_CP_CONST, | |
3051 | .resetvalue = cpu->mvfr2 }, | |
e60cef86 PM |
3052 | REGINFO_SENTINEL |
3053 | }; | |
3933443e PM |
3054 | ARMCPRegInfo rvbar = { |
3055 | .name = "RVBAR_EL1", .state = ARM_CP_STATE_AA64, | |
3056 | .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 0, .opc2 = 2, | |
3057 | .type = ARM_CP_CONST, .access = PL1_R, .resetvalue = cpu->rvbar | |
3058 | }; | |
3059 | define_one_arm_cp_reg(cpu, &rvbar); | |
e60cef86 | 3060 | define_arm_cp_regs(cpu, v8_idregs); |
b0d2b7d0 PM |
3061 | define_arm_cp_regs(cpu, v8_cp_reginfo); |
3062 | } | |
3b685ba7 EI |
3063 | if (arm_feature(env, ARM_FEATURE_EL2)) { |
3064 | define_arm_cp_regs(cpu, v8_el2_cp_reginfo); | |
d42e3c26 EI |
3065 | } else { |
3066 | /* If EL2 is missing but higher ELs are enabled, we need to | |
3067 | * register the no_el2 reginfos. | |
3068 | */ | |
3069 | if (arm_feature(env, ARM_FEATURE_EL3)) { | |
3070 | define_arm_cp_regs(cpu, v8_el3_no_el2_cp_reginfo); | |
3071 | } | |
3b685ba7 | 3072 | } |
81547d66 | 3073 | if (arm_feature(env, ARM_FEATURE_EL3)) { |
0f1a3b24 FA |
3074 | if (arm_feature(env, ARM_FEATURE_V8)) { |
3075 | define_arm_cp_regs(cpu, v8_el3_cp_reginfo); | |
3076 | } | |
3077 | define_arm_cp_regs(cpu, el3_cp_reginfo); | |
81547d66 | 3078 | } |
18032bec PM |
3079 | if (arm_feature(env, ARM_FEATURE_MPU)) { |
3080 | /* These are the MPU registers prior to PMSAv6. Any new | |
3081 | * PMSA core later than the ARM946 will require that we | |
3082 | * implement the PMSAv6 or PMSAv7 registers, which are | |
3083 | * completely different. | |
3084 | */ | |
3085 | assert(!arm_feature(env, ARM_FEATURE_V6)); | |
3086 | define_arm_cp_regs(cpu, pmsav5_cp_reginfo); | |
3087 | } else { | |
3088 | define_arm_cp_regs(cpu, vmsa_cp_reginfo); | |
3089 | } | |
c326b979 PM |
3090 | if (arm_feature(env, ARM_FEATURE_THUMB2EE)) { |
3091 | define_arm_cp_regs(cpu, t2ee_cp_reginfo); | |
3092 | } | |
6cc7a3ae PM |
3093 | if (arm_feature(env, ARM_FEATURE_GENERIC_TIMER)) { |
3094 | define_arm_cp_regs(cpu, generic_timer_cp_reginfo); | |
3095 | } | |
4a501606 PM |
3096 | if (arm_feature(env, ARM_FEATURE_VAPA)) { |
3097 | define_arm_cp_regs(cpu, vapa_cp_reginfo); | |
3098 | } | |
c4804214 PM |
3099 | if (arm_feature(env, ARM_FEATURE_CACHE_TEST_CLEAN)) { |
3100 | define_arm_cp_regs(cpu, cache_test_clean_cp_reginfo); | |
3101 | } | |
3102 | if (arm_feature(env, ARM_FEATURE_CACHE_DIRTY_REG)) { | |
3103 | define_arm_cp_regs(cpu, cache_dirty_status_cp_reginfo); | |
3104 | } | |
3105 | if (arm_feature(env, ARM_FEATURE_CACHE_BLOCK_OPS)) { | |
3106 | define_arm_cp_regs(cpu, cache_block_ops_cp_reginfo); | |
3107 | } | |
18032bec PM |
3108 | if (arm_feature(env, ARM_FEATURE_OMAPCP)) { |
3109 | define_arm_cp_regs(cpu, omap_cp_reginfo); | |
3110 | } | |
34f90529 PM |
3111 | if (arm_feature(env, ARM_FEATURE_STRONGARM)) { |
3112 | define_arm_cp_regs(cpu, strongarm_cp_reginfo); | |
3113 | } | |
1047b9d7 PM |
3114 | if (arm_feature(env, ARM_FEATURE_XSCALE)) { |
3115 | define_arm_cp_regs(cpu, xscale_cp_reginfo); | |
3116 | } | |
3117 | if (arm_feature(env, ARM_FEATURE_DUMMY_C15_REGS)) { | |
3118 | define_arm_cp_regs(cpu, dummy_c15_cp_reginfo); | |
3119 | } | |
7ac681cf PM |
3120 | if (arm_feature(env, ARM_FEATURE_LPAE)) { |
3121 | define_arm_cp_regs(cpu, lpae_cp_reginfo); | |
3122 | } | |
7884849c PM |
3123 | /* Slightly awkwardly, the OMAP and StrongARM cores need all of |
3124 | * cp15 crn=0 to be writes-ignored, whereas for other cores they should | |
3125 | * be read-only (ie write causes UNDEF exception). | |
3126 | */ | |
3127 | { | |
00a29f3d PM |
3128 | ARMCPRegInfo id_pre_v8_midr_cp_reginfo[] = { |
3129 | /* Pre-v8 MIDR space. | |
3130 | * Note that the MIDR isn't a simple constant register because | |
7884849c PM |
3131 | * of the TI925 behaviour where writes to another register can |
3132 | * cause the MIDR value to change. | |
97ce8d61 PC |
3133 | * |
3134 | * Unimplemented registers in the c15 0 0 0 space default to | |
3135 | * MIDR. Define MIDR first as this entire space, then CTR, TCMTR | |
3136 | * and friends override accordingly. | |
7884849c PM |
3137 | */ |
3138 | { .name = "MIDR", | |
97ce8d61 | 3139 | .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = CP_ANY, |
7884849c | 3140 | .access = PL1_R, .resetvalue = cpu->midr, |
d4e6df63 | 3141 | .writefn = arm_cp_write_ignore, .raw_writefn = raw_write, |
97ce8d61 PC |
3142 | .fieldoffset = offsetof(CPUARMState, cp15.c0_cpuid), |
3143 | .type = ARM_CP_OVERRIDE }, | |
7884849c PM |
3144 | /* crn = 0 op1 = 0 crm = 3..7 : currently unassigned; we RAZ. */ |
3145 | { .name = "DUMMY", | |
3146 | .cp = 15, .crn = 0, .crm = 3, .opc1 = 0, .opc2 = CP_ANY, | |
3147 | .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
3148 | { .name = "DUMMY", | |
3149 | .cp = 15, .crn = 0, .crm = 4, .opc1 = 0, .opc2 = CP_ANY, | |
3150 | .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
3151 | { .name = "DUMMY", | |
3152 | .cp = 15, .crn = 0, .crm = 5, .opc1 = 0, .opc2 = CP_ANY, | |
3153 | .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
3154 | { .name = "DUMMY", | |
3155 | .cp = 15, .crn = 0, .crm = 6, .opc1 = 0, .opc2 = CP_ANY, | |
3156 | .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
3157 | { .name = "DUMMY", | |
3158 | .cp = 15, .crn = 0, .crm = 7, .opc1 = 0, .opc2 = CP_ANY, | |
3159 | .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
3160 | REGINFO_SENTINEL | |
3161 | }; | |
00a29f3d PM |
3162 | ARMCPRegInfo id_v8_midr_cp_reginfo[] = { |
3163 | /* v8 MIDR -- the wildcard isn't necessary, and nor is the | |
3164 | * variable-MIDR TI925 behaviour. Instead we have a single | |
3165 | * (strictly speaking IMPDEF) alias of the MIDR, REVIDR. | |
3166 | */ | |
3167 | { .name = "MIDR_EL1", .state = ARM_CP_STATE_BOTH, | |
3168 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 0, .opc2 = 0, | |
3169 | .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = cpu->midr }, | |
3170 | { .name = "REVIDR_EL1", .state = ARM_CP_STATE_BOTH, | |
3171 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 0, .opc2 = 6, | |
3172 | .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = cpu->midr }, | |
3173 | REGINFO_SENTINEL | |
3174 | }; | |
3175 | ARMCPRegInfo id_cp_reginfo[] = { | |
3176 | /* These are common to v8 and pre-v8 */ | |
3177 | { .name = "CTR", | |
3178 | .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 1, | |
3179 | .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = cpu->ctr }, | |
3180 | { .name = "CTR_EL0", .state = ARM_CP_STATE_AA64, | |
3181 | .opc0 = 3, .opc1 = 3, .opc2 = 1, .crn = 0, .crm = 0, | |
3182 | .access = PL0_R, .accessfn = ctr_el0_access, | |
3183 | .type = ARM_CP_CONST, .resetvalue = cpu->ctr }, | |
3184 | /* TCMTR and TLBTR exist in v8 but have no 64-bit versions */ | |
3185 | { .name = "TCMTR", | |
3186 | .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 2, | |
3187 | .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
3188 | { .name = "TLBTR", | |
3189 | .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 3, | |
3190 | .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
3191 | REGINFO_SENTINEL | |
3192 | }; | |
7884849c PM |
3193 | ARMCPRegInfo crn0_wi_reginfo = { |
3194 | .name = "CRN0_WI", .cp = 15, .crn = 0, .crm = CP_ANY, | |
3195 | .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_W, | |
3196 | .type = ARM_CP_NOP | ARM_CP_OVERRIDE | |
3197 | }; | |
3198 | if (arm_feature(env, ARM_FEATURE_OMAPCP) || | |
3199 | arm_feature(env, ARM_FEATURE_STRONGARM)) { | |
3200 | ARMCPRegInfo *r; | |
3201 | /* Register the blanket "writes ignored" value first to cover the | |
a703eda1 PC |
3202 | * whole space. Then update the specific ID registers to allow write |
3203 | * access, so that they ignore writes rather than causing them to | |
3204 | * UNDEF. | |
7884849c PM |
3205 | */ |
3206 | define_one_arm_cp_reg(cpu, &crn0_wi_reginfo); | |
00a29f3d PM |
3207 | for (r = id_pre_v8_midr_cp_reginfo; |
3208 | r->type != ARM_CP_SENTINEL; r++) { | |
3209 | r->access = PL1_RW; | |
3210 | } | |
7884849c PM |
3211 | for (r = id_cp_reginfo; r->type != ARM_CP_SENTINEL; r++) { |
3212 | r->access = PL1_RW; | |
7884849c | 3213 | } |
7884849c | 3214 | } |
00a29f3d PM |
3215 | if (arm_feature(env, ARM_FEATURE_V8)) { |
3216 | define_arm_cp_regs(cpu, id_v8_midr_cp_reginfo); | |
3217 | } else { | |
3218 | define_arm_cp_regs(cpu, id_pre_v8_midr_cp_reginfo); | |
3219 | } | |
a703eda1 | 3220 | define_arm_cp_regs(cpu, id_cp_reginfo); |
7884849c PM |
3221 | } |
3222 | ||
97ce8d61 PC |
3223 | if (arm_feature(env, ARM_FEATURE_MPIDR)) { |
3224 | define_arm_cp_regs(cpu, mpidr_cp_reginfo); | |
3225 | } | |
3226 | ||
2771db27 PM |
3227 | if (arm_feature(env, ARM_FEATURE_AUXCR)) { |
3228 | ARMCPRegInfo auxcr = { | |
2eef0bf8 PM |
3229 | .name = "ACTLR_EL1", .state = ARM_CP_STATE_BOTH, |
3230 | .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 1, | |
2771db27 PM |
3231 | .access = PL1_RW, .type = ARM_CP_CONST, |
3232 | .resetvalue = cpu->reset_auxcr | |
3233 | }; | |
3234 | define_one_arm_cp_reg(cpu, &auxcr); | |
3235 | } | |
3236 | ||
d8ba780b | 3237 | if (arm_feature(env, ARM_FEATURE_CBAR)) { |
f318cec6 PM |
3238 | if (arm_feature(env, ARM_FEATURE_AARCH64)) { |
3239 | /* 32 bit view is [31:18] 0...0 [43:32]. */ | |
3240 | uint32_t cbar32 = (extract64(cpu->reset_cbar, 18, 14) << 18) | |
3241 | | extract64(cpu->reset_cbar, 32, 12); | |
3242 | ARMCPRegInfo cbar_reginfo[] = { | |
3243 | { .name = "CBAR", | |
3244 | .type = ARM_CP_CONST, | |
3245 | .cp = 15, .crn = 15, .crm = 0, .opc1 = 4, .opc2 = 0, | |
3246 | .access = PL1_R, .resetvalue = cpu->reset_cbar }, | |
3247 | { .name = "CBAR_EL1", .state = ARM_CP_STATE_AA64, | |
3248 | .type = ARM_CP_CONST, | |
3249 | .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 3, .opc2 = 0, | |
3250 | .access = PL1_R, .resetvalue = cbar32 }, | |
3251 | REGINFO_SENTINEL | |
3252 | }; | |
3253 | /* We don't implement a r/w 64 bit CBAR currently */ | |
3254 | assert(arm_feature(env, ARM_FEATURE_CBAR_RO)); | |
3255 | define_arm_cp_regs(cpu, cbar_reginfo); | |
3256 | } else { | |
3257 | ARMCPRegInfo cbar = { | |
3258 | .name = "CBAR", | |
3259 | .cp = 15, .crn = 15, .crm = 0, .opc1 = 4, .opc2 = 0, | |
3260 | .access = PL1_R|PL3_W, .resetvalue = cpu->reset_cbar, | |
3261 | .fieldoffset = offsetof(CPUARMState, | |
3262 | cp15.c15_config_base_address) | |
3263 | }; | |
3264 | if (arm_feature(env, ARM_FEATURE_CBAR_RO)) { | |
3265 | cbar.access = PL1_R; | |
3266 | cbar.fieldoffset = 0; | |
3267 | cbar.type = ARM_CP_CONST; | |
3268 | } | |
3269 | define_one_arm_cp_reg(cpu, &cbar); | |
3270 | } | |
d8ba780b PC |
3271 | } |
3272 | ||
2771db27 PM |
3273 | /* Generic registers whose values depend on the implementation */ |
3274 | { | |
3275 | ARMCPRegInfo sctlr = { | |
5ebafdf3 | 3276 | .name = "SCTLR", .state = ARM_CP_STATE_BOTH, |
137feaa9 FA |
3277 | .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 0, |
3278 | .access = PL1_RW, | |
3279 | .bank_fieldoffsets = { offsetof(CPUARMState, cp15.sctlr_s), | |
3280 | offsetof(CPUARMState, cp15.sctlr_ns) }, | |
d4e6df63 PM |
3281 | .writefn = sctlr_write, .resetvalue = cpu->reset_sctlr, |
3282 | .raw_writefn = raw_write, | |
2771db27 PM |
3283 | }; |
3284 | if (arm_feature(env, ARM_FEATURE_XSCALE)) { | |
3285 | /* Normally we would always end the TB on an SCTLR write, but Linux | |
3286 | * arch/arm/mach-pxa/sleep.S expects two instructions following | |
3287 | * an MMU enable to execute from cache. Imitate this behaviour. | |
3288 | */ | |
3289 | sctlr.type |= ARM_CP_SUPPRESS_TB_END; | |
3290 | } | |
3291 | define_one_arm_cp_reg(cpu, &sctlr); | |
3292 | } | |
2ceb98c0 PM |
3293 | } |
3294 | ||
778c3a06 | 3295 | ARMCPU *cpu_arm_init(const char *cpu_model) |
40f137e1 | 3296 | { |
9262685b | 3297 | return ARM_CPU(cpu_generic_init(TYPE_ARM_CPU, cpu_model)); |
14969266 AF |
3298 | } |
3299 | ||
3300 | void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu) | |
3301 | { | |
22169d41 | 3302 | CPUState *cs = CPU(cpu); |
14969266 AF |
3303 | CPUARMState *env = &cpu->env; |
3304 | ||
6a669427 PM |
3305 | if (arm_feature(env, ARM_FEATURE_AARCH64)) { |
3306 | gdb_register_coprocessor(cs, aarch64_fpu_gdb_get_reg, | |
3307 | aarch64_fpu_gdb_set_reg, | |
3308 | 34, "aarch64-fpu.xml", 0); | |
3309 | } else if (arm_feature(env, ARM_FEATURE_NEON)) { | |
22169d41 | 3310 | gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg, |
56aebc89 PB |
3311 | 51, "arm-neon.xml", 0); |
3312 | } else if (arm_feature(env, ARM_FEATURE_VFP3)) { | |
22169d41 | 3313 | gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg, |
56aebc89 PB |
3314 | 35, "arm-vfp3.xml", 0); |
3315 | } else if (arm_feature(env, ARM_FEATURE_VFP)) { | |
22169d41 | 3316 | gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg, |
56aebc89 PB |
3317 | 19, "arm-vfp.xml", 0); |
3318 | } | |
40f137e1 PB |
3319 | } |
3320 | ||
777dc784 PM |
3321 | /* Sort alphabetically by type name, except for "any". */ |
3322 | static gint arm_cpu_list_compare(gconstpointer a, gconstpointer b) | |
5adb4839 | 3323 | { |
777dc784 PM |
3324 | ObjectClass *class_a = (ObjectClass *)a; |
3325 | ObjectClass *class_b = (ObjectClass *)b; | |
3326 | const char *name_a, *name_b; | |
5adb4839 | 3327 | |
777dc784 PM |
3328 | name_a = object_class_get_name(class_a); |
3329 | name_b = object_class_get_name(class_b); | |
51492fd1 | 3330 | if (strcmp(name_a, "any-" TYPE_ARM_CPU) == 0) { |
777dc784 | 3331 | return 1; |
51492fd1 | 3332 | } else if (strcmp(name_b, "any-" TYPE_ARM_CPU) == 0) { |
777dc784 PM |
3333 | return -1; |
3334 | } else { | |
3335 | return strcmp(name_a, name_b); | |
5adb4839 PB |
3336 | } |
3337 | } | |
3338 | ||
777dc784 | 3339 | static void arm_cpu_list_entry(gpointer data, gpointer user_data) |
40f137e1 | 3340 | { |
777dc784 | 3341 | ObjectClass *oc = data; |
92a31361 | 3342 | CPUListState *s = user_data; |
51492fd1 AF |
3343 | const char *typename; |
3344 | char *name; | |
3371d272 | 3345 | |
51492fd1 AF |
3346 | typename = object_class_get_name(oc); |
3347 | name = g_strndup(typename, strlen(typename) - strlen("-" TYPE_ARM_CPU)); | |
777dc784 | 3348 | (*s->cpu_fprintf)(s->file, " %s\n", |
51492fd1 AF |
3349 | name); |
3350 | g_free(name); | |
777dc784 PM |
3351 | } |
3352 | ||
3353 | void arm_cpu_list(FILE *f, fprintf_function cpu_fprintf) | |
3354 | { | |
92a31361 | 3355 | CPUListState s = { |
777dc784 PM |
3356 | .file = f, |
3357 | .cpu_fprintf = cpu_fprintf, | |
3358 | }; | |
3359 | GSList *list; | |
3360 | ||
3361 | list = object_class_get_list(TYPE_ARM_CPU, false); | |
3362 | list = g_slist_sort(list, arm_cpu_list_compare); | |
3363 | (*cpu_fprintf)(f, "Available CPUs:\n"); | |
3364 | g_slist_foreach(list, arm_cpu_list_entry, &s); | |
3365 | g_slist_free(list); | |
a96c0514 PM |
3366 | #ifdef CONFIG_KVM |
3367 | /* The 'host' CPU type is dynamically registered only if KVM is | |
3368 | * enabled, so we have to special-case it here: | |
3369 | */ | |
3370 | (*cpu_fprintf)(f, " host (only available in KVM mode)\n"); | |
3371 | #endif | |
40f137e1 PB |
3372 | } |
3373 | ||
78027bb6 CR |
3374 | static void arm_cpu_add_definition(gpointer data, gpointer user_data) |
3375 | { | |
3376 | ObjectClass *oc = data; | |
3377 | CpuDefinitionInfoList **cpu_list = user_data; | |
3378 | CpuDefinitionInfoList *entry; | |
3379 | CpuDefinitionInfo *info; | |
3380 | const char *typename; | |
3381 | ||
3382 | typename = object_class_get_name(oc); | |
3383 | info = g_malloc0(sizeof(*info)); | |
3384 | info->name = g_strndup(typename, | |
3385 | strlen(typename) - strlen("-" TYPE_ARM_CPU)); | |
3386 | ||
3387 | entry = g_malloc0(sizeof(*entry)); | |
3388 | entry->value = info; | |
3389 | entry->next = *cpu_list; | |
3390 | *cpu_list = entry; | |
3391 | } | |
3392 | ||
3393 | CpuDefinitionInfoList *arch_query_cpu_definitions(Error **errp) | |
3394 | { | |
3395 | CpuDefinitionInfoList *cpu_list = NULL; | |
3396 | GSList *list; | |
3397 | ||
3398 | list = object_class_get_list(TYPE_ARM_CPU, false); | |
3399 | g_slist_foreach(list, arm_cpu_add_definition, &cpu_list); | |
3400 | g_slist_free(list); | |
3401 | ||
3402 | return cpu_list; | |
3403 | } | |
3404 | ||
6e6efd61 | 3405 | static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r, |
51a79b03 | 3406 | void *opaque, int state, int secstate, |
f5a0a5a5 | 3407 | int crm, int opc1, int opc2) |
6e6efd61 PM |
3408 | { |
3409 | /* Private utility function for define_one_arm_cp_reg_with_opaque(): | |
3410 | * add a single reginfo struct to the hash table. | |
3411 | */ | |
3412 | uint32_t *key = g_new(uint32_t, 1); | |
3413 | ARMCPRegInfo *r2 = g_memdup(r, sizeof(ARMCPRegInfo)); | |
3414 | int is64 = (r->type & ARM_CP_64BIT) ? 1 : 0; | |
3f3c82a5 FA |
3415 | int ns = (secstate & ARM_CP_SECSTATE_NS) ? 1 : 0; |
3416 | ||
3417 | /* Reset the secure state to the specific incoming state. This is | |
3418 | * necessary as the register may have been defined with both states. | |
3419 | */ | |
3420 | r2->secure = secstate; | |
3421 | ||
3422 | if (r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1]) { | |
3423 | /* Register is banked (using both entries in array). | |
3424 | * Overwriting fieldoffset as the array is only used to define | |
3425 | * banked registers but later only fieldoffset is used. | |
f5a0a5a5 | 3426 | */ |
3f3c82a5 FA |
3427 | r2->fieldoffset = r->bank_fieldoffsets[ns]; |
3428 | } | |
3429 | ||
3430 | if (state == ARM_CP_STATE_AA32) { | |
3431 | if (r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1]) { | |
3432 | /* If the register is banked then we don't need to migrate or | |
3433 | * reset the 32-bit instance in certain cases: | |
3434 | * | |
3435 | * 1) If the register has both 32-bit and 64-bit instances then we | |
3436 | * can count on the 64-bit instance taking care of the | |
3437 | * non-secure bank. | |
3438 | * 2) If ARMv8 is enabled then we can count on a 64-bit version | |
3439 | * taking care of the secure bank. This requires that separate | |
3440 | * 32 and 64-bit definitions are provided. | |
3441 | */ | |
3442 | if ((r->state == ARM_CP_STATE_BOTH && ns) || | |
3443 | (arm_feature(&cpu->env, ARM_FEATURE_V8) && !ns)) { | |
3444 | r2->type |= ARM_CP_NO_MIGRATE; | |
3445 | r2->resetfn = arm_cp_reset_ignore; | |
3446 | } | |
3447 | } else if ((secstate != r->secure) && !ns) { | |
3448 | /* The register is not banked so we only want to allow migration of | |
3449 | * the non-secure instance. | |
3450 | */ | |
3451 | r2->type |= ARM_CP_NO_MIGRATE; | |
3452 | r2->resetfn = arm_cp_reset_ignore; | |
58a1d8ce | 3453 | } |
3f3c82a5 FA |
3454 | |
3455 | if (r->state == ARM_CP_STATE_BOTH) { | |
3456 | /* We assume it is a cp15 register if the .cp field is left unset. | |
3457 | */ | |
3458 | if (r2->cp == 0) { | |
3459 | r2->cp = 15; | |
3460 | } | |
3461 | ||
f5a0a5a5 | 3462 | #ifdef HOST_WORDS_BIGENDIAN |
3f3c82a5 FA |
3463 | if (r2->fieldoffset) { |
3464 | r2->fieldoffset += sizeof(uint32_t); | |
3465 | } | |
f5a0a5a5 | 3466 | #endif |
3f3c82a5 | 3467 | } |
f5a0a5a5 PM |
3468 | } |
3469 | if (state == ARM_CP_STATE_AA64) { | |
3470 | /* To allow abbreviation of ARMCPRegInfo | |
3471 | * definitions, we treat cp == 0 as equivalent to | |
3472 | * the value for "standard guest-visible sysreg". | |
58a1d8ce PM |
3473 | * STATE_BOTH definitions are also always "standard |
3474 | * sysreg" in their AArch64 view (the .cp value may | |
3475 | * be non-zero for the benefit of the AArch32 view). | |
f5a0a5a5 | 3476 | */ |
58a1d8ce | 3477 | if (r->cp == 0 || r->state == ARM_CP_STATE_BOTH) { |
f5a0a5a5 PM |
3478 | r2->cp = CP_REG_ARM64_SYSREG_CP; |
3479 | } | |
3480 | *key = ENCODE_AA64_CP_REG(r2->cp, r2->crn, crm, | |
3481 | r2->opc0, opc1, opc2); | |
3482 | } else { | |
51a79b03 | 3483 | *key = ENCODE_CP_REG(r2->cp, is64, ns, r2->crn, crm, opc1, opc2); |
f5a0a5a5 | 3484 | } |
6e6efd61 PM |
3485 | if (opaque) { |
3486 | r2->opaque = opaque; | |
3487 | } | |
67ed771d PM |
3488 | /* reginfo passed to helpers is correct for the actual access, |
3489 | * and is never ARM_CP_STATE_BOTH: | |
3490 | */ | |
3491 | r2->state = state; | |
6e6efd61 PM |
3492 | /* Make sure reginfo passed to helpers for wildcarded regs |
3493 | * has the correct crm/opc1/opc2 for this reg, not CP_ANY: | |
3494 | */ | |
3495 | r2->crm = crm; | |
3496 | r2->opc1 = opc1; | |
3497 | r2->opc2 = opc2; | |
3498 | /* By convention, for wildcarded registers only the first | |
3499 | * entry is used for migration; the others are marked as | |
3500 | * NO_MIGRATE so we don't try to transfer the register | |
3501 | * multiple times. Special registers (ie NOP/WFI) are | |
3502 | * never migratable. | |
3503 | */ | |
3504 | if ((r->type & ARM_CP_SPECIAL) || | |
3505 | ((r->crm == CP_ANY) && crm != 0) || | |
3506 | ((r->opc1 == CP_ANY) && opc1 != 0) || | |
3507 | ((r->opc2 == CP_ANY) && opc2 != 0)) { | |
3508 | r2->type |= ARM_CP_NO_MIGRATE; | |
3509 | } | |
3510 | ||
3511 | /* Overriding of an existing definition must be explicitly | |
3512 | * requested. | |
3513 | */ | |
3514 | if (!(r->type & ARM_CP_OVERRIDE)) { | |
3515 | ARMCPRegInfo *oldreg; | |
3516 | oldreg = g_hash_table_lookup(cpu->cp_regs, key); | |
3517 | if (oldreg && !(oldreg->type & ARM_CP_OVERRIDE)) { | |
3518 | fprintf(stderr, "Register redefined: cp=%d %d bit " | |
3519 | "crn=%d crm=%d opc1=%d opc2=%d, " | |
3520 | "was %s, now %s\n", r2->cp, 32 + 32 * is64, | |
3521 | r2->crn, r2->crm, r2->opc1, r2->opc2, | |
3522 | oldreg->name, r2->name); | |
3523 | g_assert_not_reached(); | |
3524 | } | |
3525 | } | |
3526 | g_hash_table_insert(cpu->cp_regs, key, r2); | |
3527 | } | |
3528 | ||
3529 | ||
4b6a83fb PM |
3530 | void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu, |
3531 | const ARMCPRegInfo *r, void *opaque) | |
3532 | { | |
3533 | /* Define implementations of coprocessor registers. | |
3534 | * We store these in a hashtable because typically | |
3535 | * there are less than 150 registers in a space which | |
3536 | * is 16*16*16*8*8 = 262144 in size. | |
3537 | * Wildcarding is supported for the crm, opc1 and opc2 fields. | |
3538 | * If a register is defined twice then the second definition is | |
3539 | * used, so this can be used to define some generic registers and | |
3540 | * then override them with implementation specific variations. | |
3541 | * At least one of the original and the second definition should | |
3542 | * include ARM_CP_OVERRIDE in its type bits -- this is just a guard | |
3543 | * against accidental use. | |
f5a0a5a5 PM |
3544 | * |
3545 | * The state field defines whether the register is to be | |
3546 | * visible in the AArch32 or AArch64 execution state. If the | |
3547 | * state is set to ARM_CP_STATE_BOTH then we synthesise a | |
3548 | * reginfo structure for the AArch32 view, which sees the lower | |
3549 | * 32 bits of the 64 bit register. | |
3550 | * | |
3551 | * Only registers visible in AArch64 may set r->opc0; opc0 cannot | |
3552 | * be wildcarded. AArch64 registers are always considered to be 64 | |
3553 | * bits; the ARM_CP_64BIT* flag applies only to the AArch32 view of | |
3554 | * the register, if any. | |
4b6a83fb | 3555 | */ |
f5a0a5a5 | 3556 | int crm, opc1, opc2, state; |
4b6a83fb PM |
3557 | int crmmin = (r->crm == CP_ANY) ? 0 : r->crm; |
3558 | int crmmax = (r->crm == CP_ANY) ? 15 : r->crm; | |
3559 | int opc1min = (r->opc1 == CP_ANY) ? 0 : r->opc1; | |
3560 | int opc1max = (r->opc1 == CP_ANY) ? 7 : r->opc1; | |
3561 | int opc2min = (r->opc2 == CP_ANY) ? 0 : r->opc2; | |
3562 | int opc2max = (r->opc2 == CP_ANY) ? 7 : r->opc2; | |
3563 | /* 64 bit registers have only CRm and Opc1 fields */ | |
3564 | assert(!((r->type & ARM_CP_64BIT) && (r->opc2 || r->crn))); | |
f5a0a5a5 PM |
3565 | /* op0 only exists in the AArch64 encodings */ |
3566 | assert((r->state != ARM_CP_STATE_AA32) || (r->opc0 == 0)); | |
3567 | /* AArch64 regs are all 64 bit so ARM_CP_64BIT is meaningless */ | |
3568 | assert((r->state != ARM_CP_STATE_AA64) || !(r->type & ARM_CP_64BIT)); | |
3569 | /* The AArch64 pseudocode CheckSystemAccess() specifies that op1 | |
3570 | * encodes a minimum access level for the register. We roll this | |
3571 | * runtime check into our general permission check code, so check | |
3572 | * here that the reginfo's specified permissions are strict enough | |
3573 | * to encompass the generic architectural permission check. | |
3574 | */ | |
3575 | if (r->state != ARM_CP_STATE_AA32) { | |
3576 | int mask = 0; | |
3577 | switch (r->opc1) { | |
3578 | case 0: case 1: case 2: | |
3579 | /* min_EL EL1 */ | |
3580 | mask = PL1_RW; | |
3581 | break; | |
3582 | case 3: | |
3583 | /* min_EL EL0 */ | |
3584 | mask = PL0_RW; | |
3585 | break; | |
3586 | case 4: | |
3587 | /* min_EL EL2 */ | |
3588 | mask = PL2_RW; | |
3589 | break; | |
3590 | case 5: | |
3591 | /* unallocated encoding, so not possible */ | |
3592 | assert(false); | |
3593 | break; | |
3594 | case 6: | |
3595 | /* min_EL EL3 */ | |
3596 | mask = PL3_RW; | |
3597 | break; | |
3598 | case 7: | |
3599 | /* min_EL EL1, secure mode only (we don't check the latter) */ | |
3600 | mask = PL1_RW; | |
3601 | break; | |
3602 | default: | |
3603 | /* broken reginfo with out-of-range opc1 */ | |
3604 | assert(false); | |
3605 | break; | |
3606 | } | |
3607 | /* assert our permissions are not too lax (stricter is fine) */ | |
3608 | assert((r->access & ~mask) == 0); | |
3609 | } | |
3610 | ||
4b6a83fb PM |
3611 | /* Check that the register definition has enough info to handle |
3612 | * reads and writes if they are permitted. | |
3613 | */ | |
3614 | if (!(r->type & (ARM_CP_SPECIAL|ARM_CP_CONST))) { | |
3615 | if (r->access & PL3_R) { | |
3f3c82a5 FA |
3616 | assert((r->fieldoffset || |
3617 | (r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1])) || | |
3618 | r->readfn); | |
4b6a83fb PM |
3619 | } |
3620 | if (r->access & PL3_W) { | |
3f3c82a5 FA |
3621 | assert((r->fieldoffset || |
3622 | (r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1])) || | |
3623 | r->writefn); | |
4b6a83fb PM |
3624 | } |
3625 | } | |
3626 | /* Bad type field probably means missing sentinel at end of reg list */ | |
3627 | assert(cptype_valid(r->type)); | |
3628 | for (crm = crmmin; crm <= crmmax; crm++) { | |
3629 | for (opc1 = opc1min; opc1 <= opc1max; opc1++) { | |
3630 | for (opc2 = opc2min; opc2 <= opc2max; opc2++) { | |
f5a0a5a5 PM |
3631 | for (state = ARM_CP_STATE_AA32; |
3632 | state <= ARM_CP_STATE_AA64; state++) { | |
3633 | if (r->state != state && r->state != ARM_CP_STATE_BOTH) { | |
3634 | continue; | |
3635 | } | |
3f3c82a5 FA |
3636 | if (state == ARM_CP_STATE_AA32) { |
3637 | /* Under AArch32 CP registers can be common | |
3638 | * (same for secure and non-secure world) or banked. | |
3639 | */ | |
3640 | switch (r->secure) { | |
3641 | case ARM_CP_SECSTATE_S: | |
3642 | case ARM_CP_SECSTATE_NS: | |
3643 | add_cpreg_to_hashtable(cpu, r, opaque, state, | |
3644 | r->secure, crm, opc1, opc2); | |
3645 | break; | |
3646 | default: | |
3647 | add_cpreg_to_hashtable(cpu, r, opaque, state, | |
3648 | ARM_CP_SECSTATE_S, | |
3649 | crm, opc1, opc2); | |
3650 | add_cpreg_to_hashtable(cpu, r, opaque, state, | |
3651 | ARM_CP_SECSTATE_NS, | |
3652 | crm, opc1, opc2); | |
3653 | break; | |
3654 | } | |
3655 | } else { | |
3656 | /* AArch64 registers get mapped to non-secure instance | |
3657 | * of AArch32 */ | |
3658 | add_cpreg_to_hashtable(cpu, r, opaque, state, | |
3659 | ARM_CP_SECSTATE_NS, | |
3660 | crm, opc1, opc2); | |
3661 | } | |
f5a0a5a5 | 3662 | } |
4b6a83fb PM |
3663 | } |
3664 | } | |
3665 | } | |
3666 | } | |
3667 | ||
3668 | void define_arm_cp_regs_with_opaque(ARMCPU *cpu, | |
3669 | const ARMCPRegInfo *regs, void *opaque) | |
3670 | { | |
3671 | /* Define a whole list of registers */ | |
3672 | const ARMCPRegInfo *r; | |
3673 | for (r = regs; r->type != ARM_CP_SENTINEL; r++) { | |
3674 | define_one_arm_cp_reg_with_opaque(cpu, r, opaque); | |
3675 | } | |
3676 | } | |
3677 | ||
60322b39 | 3678 | const ARMCPRegInfo *get_arm_cp_reginfo(GHashTable *cpregs, uint32_t encoded_cp) |
4b6a83fb | 3679 | { |
60322b39 | 3680 | return g_hash_table_lookup(cpregs, &encoded_cp); |
4b6a83fb PM |
3681 | } |
3682 | ||
c4241c7d PM |
3683 | void arm_cp_write_ignore(CPUARMState *env, const ARMCPRegInfo *ri, |
3684 | uint64_t value) | |
4b6a83fb PM |
3685 | { |
3686 | /* Helper coprocessor write function for write-ignore registers */ | |
4b6a83fb PM |
3687 | } |
3688 | ||
c4241c7d | 3689 | uint64_t arm_cp_read_zero(CPUARMState *env, const ARMCPRegInfo *ri) |
4b6a83fb PM |
3690 | { |
3691 | /* Helper coprocessor write function for read-as-zero registers */ | |
4b6a83fb PM |
3692 | return 0; |
3693 | } | |
3694 | ||
f5a0a5a5 PM |
3695 | void arm_cp_reset_ignore(CPUARMState *env, const ARMCPRegInfo *opaque) |
3696 | { | |
3697 | /* Helper coprocessor reset function for do-nothing-on-reset registers */ | |
3698 | } | |
3699 | ||
0ecb72a5 | 3700 | static int bad_mode_switch(CPUARMState *env, int mode) |
37064a8b PM |
3701 | { |
3702 | /* Return true if it is not valid for us to switch to | |
3703 | * this CPU mode (ie all the UNPREDICTABLE cases in | |
3704 | * the ARM ARM CPSRWriteByInstr pseudocode). | |
3705 | */ | |
3706 | switch (mode) { | |
3707 | case ARM_CPU_MODE_USR: | |
3708 | case ARM_CPU_MODE_SYS: | |
3709 | case ARM_CPU_MODE_SVC: | |
3710 | case ARM_CPU_MODE_ABT: | |
3711 | case ARM_CPU_MODE_UND: | |
3712 | case ARM_CPU_MODE_IRQ: | |
3713 | case ARM_CPU_MODE_FIQ: | |
3714 | return 0; | |
027fc527 SF |
3715 | case ARM_CPU_MODE_MON: |
3716 | return !arm_is_secure(env); | |
37064a8b PM |
3717 | default: |
3718 | return 1; | |
3719 | } | |
3720 | } | |
3721 | ||
2f4a40e5 AZ |
3722 | uint32_t cpsr_read(CPUARMState *env) |
3723 | { | |
3724 | int ZF; | |
6fbe23d5 PB |
3725 | ZF = (env->ZF == 0); |
3726 | return env->uncached_cpsr | (env->NF & 0x80000000) | (ZF << 30) | | |
2f4a40e5 AZ |
3727 | (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27) |
3728 | | (env->thumb << 5) | ((env->condexec_bits & 3) << 25) | |
3729 | | ((env->condexec_bits & 0xfc) << 8) | |
af519934 | 3730 | | (env->GE << 16) | (env->daif & CPSR_AIF); |
2f4a40e5 AZ |
3731 | } |
3732 | ||
3733 | void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask) | |
3734 | { | |
6e8801f9 FA |
3735 | uint32_t changed_daif; |
3736 | ||
2f4a40e5 | 3737 | if (mask & CPSR_NZCV) { |
6fbe23d5 PB |
3738 | env->ZF = (~val) & CPSR_Z; |
3739 | env->NF = val; | |
2f4a40e5 AZ |
3740 | env->CF = (val >> 29) & 1; |
3741 | env->VF = (val << 3) & 0x80000000; | |
3742 | } | |
3743 | if (mask & CPSR_Q) | |
3744 | env->QF = ((val & CPSR_Q) != 0); | |
3745 | if (mask & CPSR_T) | |
3746 | env->thumb = ((val & CPSR_T) != 0); | |
3747 | if (mask & CPSR_IT_0_1) { | |
3748 | env->condexec_bits &= ~3; | |
3749 | env->condexec_bits |= (val >> 25) & 3; | |
3750 | } | |
3751 | if (mask & CPSR_IT_2_7) { | |
3752 | env->condexec_bits &= 3; | |
3753 | env->condexec_bits |= (val >> 8) & 0xfc; | |
3754 | } | |
3755 | if (mask & CPSR_GE) { | |
3756 | env->GE = (val >> 16) & 0xf; | |
3757 | } | |
3758 | ||
6e8801f9 FA |
3759 | /* In a V7 implementation that includes the security extensions but does |
3760 | * not include Virtualization Extensions the SCR.FW and SCR.AW bits control | |
3761 | * whether non-secure software is allowed to change the CPSR_F and CPSR_A | |
3762 | * bits respectively. | |
3763 | * | |
3764 | * In a V8 implementation, it is permitted for privileged software to | |
3765 | * change the CPSR A/F bits regardless of the SCR.AW/FW bits. | |
3766 | */ | |
3767 | if (!arm_feature(env, ARM_FEATURE_V8) && | |
3768 | arm_feature(env, ARM_FEATURE_EL3) && | |
3769 | !arm_feature(env, ARM_FEATURE_EL2) && | |
3770 | !arm_is_secure(env)) { | |
3771 | ||
3772 | changed_daif = (env->daif ^ val) & mask; | |
3773 | ||
3774 | if (changed_daif & CPSR_A) { | |
3775 | /* Check to see if we are allowed to change the masking of async | |
3776 | * abort exceptions from a non-secure state. | |
3777 | */ | |
3778 | if (!(env->cp15.scr_el3 & SCR_AW)) { | |
3779 | qemu_log_mask(LOG_GUEST_ERROR, | |
3780 | "Ignoring attempt to switch CPSR_A flag from " | |
3781 | "non-secure world with SCR.AW bit clear\n"); | |
3782 | mask &= ~CPSR_A; | |
3783 | } | |
3784 | } | |
3785 | ||
3786 | if (changed_daif & CPSR_F) { | |
3787 | /* Check to see if we are allowed to change the masking of FIQ | |
3788 | * exceptions from a non-secure state. | |
3789 | */ | |
3790 | if (!(env->cp15.scr_el3 & SCR_FW)) { | |
3791 | qemu_log_mask(LOG_GUEST_ERROR, | |
3792 | "Ignoring attempt to switch CPSR_F flag from " | |
3793 | "non-secure world with SCR.FW bit clear\n"); | |
3794 | mask &= ~CPSR_F; | |
3795 | } | |
3796 | ||
3797 | /* Check whether non-maskable FIQ (NMFI) support is enabled. | |
3798 | * If this bit is set software is not allowed to mask | |
3799 | * FIQs, but is allowed to set CPSR_F to 0. | |
3800 | */ | |
3801 | if ((A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_NMFI) && | |
3802 | (val & CPSR_F)) { | |
3803 | qemu_log_mask(LOG_GUEST_ERROR, | |
3804 | "Ignoring attempt to enable CPSR_F flag " | |
3805 | "(non-maskable FIQ [NMFI] support enabled)\n"); | |
3806 | mask &= ~CPSR_F; | |
3807 | } | |
3808 | } | |
3809 | } | |
3810 | ||
4cc35614 PM |
3811 | env->daif &= ~(CPSR_AIF & mask); |
3812 | env->daif |= val & CPSR_AIF & mask; | |
3813 | ||
2f4a40e5 | 3814 | if ((env->uncached_cpsr ^ val) & mask & CPSR_M) { |
37064a8b PM |
3815 | if (bad_mode_switch(env, val & CPSR_M)) { |
3816 | /* Attempt to switch to an invalid mode: this is UNPREDICTABLE. | |
3817 | * We choose to ignore the attempt and leave the CPSR M field | |
3818 | * untouched. | |
3819 | */ | |
3820 | mask &= ~CPSR_M; | |
3821 | } else { | |
3822 | switch_mode(env, val & CPSR_M); | |
3823 | } | |
2f4a40e5 AZ |
3824 | } |
3825 | mask &= ~CACHED_CPSR_BITS; | |
3826 | env->uncached_cpsr = (env->uncached_cpsr & ~mask) | (val & mask); | |
3827 | } | |
3828 | ||
b26eefb6 PB |
3829 | /* Sign/zero extend */ |
3830 | uint32_t HELPER(sxtb16)(uint32_t x) | |
3831 | { | |
3832 | uint32_t res; | |
3833 | res = (uint16_t)(int8_t)x; | |
3834 | res |= (uint32_t)(int8_t)(x >> 16) << 16; | |
3835 | return res; | |
3836 | } | |
3837 | ||
3838 | uint32_t HELPER(uxtb16)(uint32_t x) | |
3839 | { | |
3840 | uint32_t res; | |
3841 | res = (uint16_t)(uint8_t)x; | |
3842 | res |= (uint32_t)(uint8_t)(x >> 16) << 16; | |
3843 | return res; | |
3844 | } | |
3845 | ||
f51bbbfe PB |
3846 | uint32_t HELPER(clz)(uint32_t x) |
3847 | { | |
7bbcb0af | 3848 | return clz32(x); |
f51bbbfe PB |
3849 | } |
3850 | ||
3670669c PB |
3851 | int32_t HELPER(sdiv)(int32_t num, int32_t den) |
3852 | { | |
3853 | if (den == 0) | |
3854 | return 0; | |
686eeb93 AJ |
3855 | if (num == INT_MIN && den == -1) |
3856 | return INT_MIN; | |
3670669c PB |
3857 | return num / den; |
3858 | } | |
3859 | ||
3860 | uint32_t HELPER(udiv)(uint32_t num, uint32_t den) | |
3861 | { | |
3862 | if (den == 0) | |
3863 | return 0; | |
3864 | return num / den; | |
3865 | } | |
3866 | ||
3867 | uint32_t HELPER(rbit)(uint32_t x) | |
3868 | { | |
3869 | x = ((x & 0xff000000) >> 24) | |
3870 | | ((x & 0x00ff0000) >> 8) | |
3871 | | ((x & 0x0000ff00) << 8) | |
3872 | | ((x & 0x000000ff) << 24); | |
3873 | x = ((x & 0xf0f0f0f0) >> 4) | |
3874 | | ((x & 0x0f0f0f0f) << 4); | |
3875 | x = ((x & 0x88888888) >> 3) | |
3876 | | ((x & 0x44444444) >> 1) | |
3877 | | ((x & 0x22222222) << 1) | |
3878 | | ((x & 0x11111111) << 3); | |
3879 | return x; | |
3880 | } | |
3881 | ||
5fafdf24 | 3882 | #if defined(CONFIG_USER_ONLY) |
b5ff1b31 | 3883 | |
7510454e AF |
3884 | int arm_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw, |
3885 | int mmu_idx) | |
b5ff1b31 | 3886 | { |
7510454e AF |
3887 | ARMCPU *cpu = ARM_CPU(cs); |
3888 | CPUARMState *env = &cpu->env; | |
3889 | ||
abf1172f | 3890 | env->exception.vaddress = address; |
b5ff1b31 | 3891 | if (rw == 2) { |
27103424 | 3892 | cs->exception_index = EXCP_PREFETCH_ABORT; |
b5ff1b31 | 3893 | } else { |
27103424 | 3894 | cs->exception_index = EXCP_DATA_ABORT; |
b5ff1b31 FB |
3895 | } |
3896 | return 1; | |
3897 | } | |
3898 | ||
9ee6e8bb | 3899 | /* These should probably raise undefined insn exceptions. */ |
0ecb72a5 | 3900 | void HELPER(v7m_msr)(CPUARMState *env, uint32_t reg, uint32_t val) |
9ee6e8bb | 3901 | { |
a47dddd7 AF |
3902 | ARMCPU *cpu = arm_env_get_cpu(env); |
3903 | ||
3904 | cpu_abort(CPU(cpu), "v7m_msr %d\n", reg); | |
9ee6e8bb PB |
3905 | } |
3906 | ||
0ecb72a5 | 3907 | uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg) |
9ee6e8bb | 3908 | { |
a47dddd7 AF |
3909 | ARMCPU *cpu = arm_env_get_cpu(env); |
3910 | ||
3911 | cpu_abort(CPU(cpu), "v7m_mrs %d\n", reg); | |
9ee6e8bb PB |
3912 | return 0; |
3913 | } | |
3914 | ||
0ecb72a5 | 3915 | void switch_mode(CPUARMState *env, int mode) |
b5ff1b31 | 3916 | { |
a47dddd7 AF |
3917 | ARMCPU *cpu = arm_env_get_cpu(env); |
3918 | ||
3919 | if (mode != ARM_CPU_MODE_USR) { | |
3920 | cpu_abort(CPU(cpu), "Tried to switch out of user mode\n"); | |
3921 | } | |
b5ff1b31 FB |
3922 | } |
3923 | ||
0ecb72a5 | 3924 | void HELPER(set_r13_banked)(CPUARMState *env, uint32_t mode, uint32_t val) |
9ee6e8bb | 3925 | { |
a47dddd7 AF |
3926 | ARMCPU *cpu = arm_env_get_cpu(env); |
3927 | ||
3928 | cpu_abort(CPU(cpu), "banked r13 write\n"); | |
9ee6e8bb PB |
3929 | } |
3930 | ||
0ecb72a5 | 3931 | uint32_t HELPER(get_r13_banked)(CPUARMState *env, uint32_t mode) |
9ee6e8bb | 3932 | { |
a47dddd7 AF |
3933 | ARMCPU *cpu = arm_env_get_cpu(env); |
3934 | ||
3935 | cpu_abort(CPU(cpu), "banked r13 read\n"); | |
9ee6e8bb PB |
3936 | return 0; |
3937 | } | |
3938 | ||
9e729b57 EI |
3939 | unsigned int arm_excp_target_el(CPUState *cs, unsigned int excp_idx) |
3940 | { | |
3941 | return 1; | |
3942 | } | |
3943 | ||
b5ff1b31 FB |
3944 | #else |
3945 | ||
3946 | /* Map CPU modes onto saved register banks. */ | |
494b00c7 | 3947 | int bank_number(int mode) |
b5ff1b31 FB |
3948 | { |
3949 | switch (mode) { | |
3950 | case ARM_CPU_MODE_USR: | |
3951 | case ARM_CPU_MODE_SYS: | |
3952 | return 0; | |
3953 | case ARM_CPU_MODE_SVC: | |
3954 | return 1; | |
3955 | case ARM_CPU_MODE_ABT: | |
3956 | return 2; | |
3957 | case ARM_CPU_MODE_UND: | |
3958 | return 3; | |
3959 | case ARM_CPU_MODE_IRQ: | |
3960 | return 4; | |
3961 | case ARM_CPU_MODE_FIQ: | |
3962 | return 5; | |
28c9457d EI |
3963 | case ARM_CPU_MODE_HYP: |
3964 | return 6; | |
3965 | case ARM_CPU_MODE_MON: | |
3966 | return 7; | |
b5ff1b31 | 3967 | } |
f5206413 | 3968 | hw_error("bank number requested for bad CPSR mode value 0x%x\n", mode); |
b5ff1b31 FB |
3969 | } |
3970 | ||
0ecb72a5 | 3971 | void switch_mode(CPUARMState *env, int mode) |
b5ff1b31 FB |
3972 | { |
3973 | int old_mode; | |
3974 | int i; | |
3975 | ||
3976 | old_mode = env->uncached_cpsr & CPSR_M; | |
3977 | if (mode == old_mode) | |
3978 | return; | |
3979 | ||
3980 | if (old_mode == ARM_CPU_MODE_FIQ) { | |
3981 | memcpy (env->fiq_regs, env->regs + 8, 5 * sizeof(uint32_t)); | |
8637c67f | 3982 | memcpy (env->regs + 8, env->usr_regs, 5 * sizeof(uint32_t)); |
b5ff1b31 FB |
3983 | } else if (mode == ARM_CPU_MODE_FIQ) { |
3984 | memcpy (env->usr_regs, env->regs + 8, 5 * sizeof(uint32_t)); | |
8637c67f | 3985 | memcpy (env->regs + 8, env->fiq_regs, 5 * sizeof(uint32_t)); |
b5ff1b31 FB |
3986 | } |
3987 | ||
f5206413 | 3988 | i = bank_number(old_mode); |
b5ff1b31 FB |
3989 | env->banked_r13[i] = env->regs[13]; |
3990 | env->banked_r14[i] = env->regs[14]; | |
3991 | env->banked_spsr[i] = env->spsr; | |
3992 | ||
f5206413 | 3993 | i = bank_number(mode); |
b5ff1b31 FB |
3994 | env->regs[13] = env->banked_r13[i]; |
3995 | env->regs[14] = env->banked_r14[i]; | |
3996 | env->spsr = env->banked_spsr[i]; | |
3997 | } | |
3998 | ||
0eeb17d6 GB |
3999 | /* Physical Interrupt Target EL Lookup Table |
4000 | * | |
4001 | * [ From ARM ARM section G1.13.4 (Table G1-15) ] | |
4002 | * | |
4003 | * The below multi-dimensional table is used for looking up the target | |
4004 | * exception level given numerous condition criteria. Specifically, the | |
4005 | * target EL is based on SCR and HCR routing controls as well as the | |
4006 | * currently executing EL and secure state. | |
4007 | * | |
4008 | * Dimensions: | |
4009 | * target_el_table[2][2][2][2][2][4] | |
4010 | * | | | | | +--- Current EL | |
4011 | * | | | | +------ Non-secure(0)/Secure(1) | |
4012 | * | | | +--------- HCR mask override | |
4013 | * | | +------------ SCR exec state control | |
4014 | * | +--------------- SCR mask override | |
4015 | * +------------------ 32-bit(0)/64-bit(1) EL3 | |
4016 | * | |
4017 | * The table values are as such: | |
4018 | * 0-3 = EL0-EL3 | |
4019 | * -1 = Cannot occur | |
4020 | * | |
4021 | * The ARM ARM target EL table includes entries indicating that an "exception | |
4022 | * is not taken". The two cases where this is applicable are: | |
4023 | * 1) An exception is taken from EL3 but the SCR does not have the exception | |
4024 | * routed to EL3. | |
4025 | * 2) An exception is taken from EL2 but the HCR does not have the exception | |
4026 | * routed to EL2. | |
4027 | * In these two cases, the below table contain a target of EL1. This value is | |
4028 | * returned as it is expected that the consumer of the table data will check | |
4029 | * for "target EL >= current EL" to ensure the exception is not taken. | |
4030 | * | |
4031 | * SCR HCR | |
4032 | * 64 EA AMO From | |
4033 | * BIT IRQ IMO Non-secure Secure | |
4034 | * EL3 FIQ RW FMO EL0 EL1 EL2 EL3 EL0 EL1 EL2 EL3 | |
4035 | */ | |
4036 | const int8_t target_el_table[2][2][2][2][2][4] = { | |
4037 | {{{{/* 0 0 0 0 */{ 1, 1, 2, -1 },{ 3, -1, -1, 3 },}, | |
4038 | {/* 0 0 0 1 */{ 2, 2, 2, -1 },{ 3, -1, -1, 3 },},}, | |
4039 | {{/* 0 0 1 0 */{ 1, 1, 2, -1 },{ 3, -1, -1, 3 },}, | |
4040 | {/* 0 0 1 1 */{ 2, 2, 2, -1 },{ 3, -1, -1, 3 },},},}, | |
4041 | {{{/* 0 1 0 0 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },}, | |
4042 | {/* 0 1 0 1 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },},}, | |
4043 | {{/* 0 1 1 0 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },}, | |
4044 | {/* 0 1 1 1 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },},},},}, | |
4045 | {{{{/* 1 0 0 0 */{ 1, 1, 2, -1 },{ 1, 1, -1, 1 },}, | |
4046 | {/* 1 0 0 1 */{ 2, 2, 2, -1 },{ 1, 1, -1, 1 },},}, | |
4047 | {{/* 1 0 1 0 */{ 1, 1, 1, -1 },{ 1, 1, -1, 1 },}, | |
4048 | {/* 1 0 1 1 */{ 2, 2, 2, -1 },{ 1, 1, -1, 1 },},},}, | |
4049 | {{{/* 1 1 0 0 */{ 3, 3, 3, -1 },{ 3, 3, -1, 3 },}, | |
4050 | {/* 1 1 0 1 */{ 3, 3, 3, -1 },{ 3, 3, -1, 3 },},}, | |
4051 | {{/* 1 1 1 0 */{ 3, 3, 3, -1 },{ 3, 3, -1, 3 },}, | |
4052 | {/* 1 1 1 1 */{ 3, 3, 3, -1 },{ 3, 3, -1, 3 },},},},}, | |
4053 | }; | |
4054 | ||
4055 | /* | |
4056 | * Determine the target EL for physical exceptions | |
4057 | */ | |
4058 | static inline uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx, | |
4059 | uint32_t cur_el, bool secure) | |
4060 | { | |
4061 | CPUARMState *env = cs->env_ptr; | |
4062 | int rw = ((env->cp15.scr_el3 & SCR_RW) == SCR_RW); | |
4063 | int scr; | |
4064 | int hcr; | |
4065 | int target_el; | |
4066 | int is64 = arm_el_is_aa64(env, 3); | |
4067 | ||
4068 | switch (excp_idx) { | |
4069 | case EXCP_IRQ: | |
4070 | scr = ((env->cp15.scr_el3 & SCR_IRQ) == SCR_IRQ); | |
4071 | hcr = ((env->cp15.hcr_el2 & HCR_IMO) == HCR_IMO); | |
4072 | break; | |
4073 | case EXCP_FIQ: | |
4074 | scr = ((env->cp15.scr_el3 & SCR_FIQ) == SCR_FIQ); | |
4075 | hcr = ((env->cp15.hcr_el2 & HCR_FMO) == HCR_FMO); | |
4076 | break; | |
4077 | default: | |
4078 | scr = ((env->cp15.scr_el3 & SCR_EA) == SCR_EA); | |
4079 | hcr = ((env->cp15.hcr_el2 & HCR_AMO) == HCR_AMO); | |
4080 | break; | |
4081 | }; | |
4082 | ||
4083 | /* If HCR.TGE is set then HCR is treated as being 1 */ | |
4084 | hcr |= ((env->cp15.hcr_el2 & HCR_TGE) == HCR_TGE); | |
4085 | ||
4086 | /* Perform a table-lookup for the target EL given the current state */ | |
4087 | target_el = target_el_table[is64][scr][rw][hcr][secure][cur_el]; | |
4088 | ||
4089 | assert(target_el > 0); | |
4090 | ||
4091 | return target_el; | |
4092 | } | |
4093 | ||
9e729b57 EI |
4094 | /* |
4095 | * Determine the target EL for a given exception type. | |
4096 | */ | |
4097 | unsigned int arm_excp_target_el(CPUState *cs, unsigned int excp_idx) | |
4098 | { | |
35979d71 EI |
4099 | ARMCPU *cpu = ARM_CPU(cs); |
4100 | CPUARMState *env = &cpu->env; | |
dcbff19b | 4101 | unsigned int cur_el = arm_current_el(env); |
35979d71 | 4102 | unsigned int target_el; |
0eeb17d6 | 4103 | bool secure = arm_is_secure(env); |
35979d71 EI |
4104 | |
4105 | switch (excp_idx) { | |
4106 | case EXCP_HVC: | |
607d98b8 | 4107 | case EXCP_HYP_TRAP: |
35979d71 EI |
4108 | target_el = 2; |
4109 | break; | |
e0d6e6a5 EI |
4110 | case EXCP_SMC: |
4111 | target_el = 3; | |
4112 | break; | |
041c9666 EI |
4113 | case EXCP_FIQ: |
4114 | case EXCP_IRQ: | |
0eeb17d6 | 4115 | target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure); |
041c9666 | 4116 | break; |
136e67e9 EI |
4117 | case EXCP_VIRQ: |
4118 | case EXCP_VFIQ: | |
4119 | target_el = 1; | |
4120 | break; | |
35979d71 EI |
4121 | default: |
4122 | target_el = MAX(cur_el, 1); | |
4123 | break; | |
4124 | } | |
4125 | return target_el; | |
9e729b57 EI |
4126 | } |
4127 | ||
9ee6e8bb PB |
4128 | static void v7m_push(CPUARMState *env, uint32_t val) |
4129 | { | |
70d74660 AF |
4130 | CPUState *cs = CPU(arm_env_get_cpu(env)); |
4131 | ||
9ee6e8bb | 4132 | env->regs[13] -= 4; |
ab1da857 | 4133 | stl_phys(cs->as, env->regs[13], val); |
9ee6e8bb PB |
4134 | } |
4135 | ||
4136 | static uint32_t v7m_pop(CPUARMState *env) | |
4137 | { | |
70d74660 | 4138 | CPUState *cs = CPU(arm_env_get_cpu(env)); |
9ee6e8bb | 4139 | uint32_t val; |
70d74660 | 4140 | |
fdfba1a2 | 4141 | val = ldl_phys(cs->as, env->regs[13]); |
9ee6e8bb PB |
4142 | env->regs[13] += 4; |
4143 | return val; | |
4144 | } | |
4145 | ||
4146 | /* Switch to V7M main or process stack pointer. */ | |
4147 | static void switch_v7m_sp(CPUARMState *env, int process) | |
4148 | { | |
4149 | uint32_t tmp; | |
4150 | if (env->v7m.current_sp != process) { | |
4151 | tmp = env->v7m.other_sp; | |
4152 | env->v7m.other_sp = env->regs[13]; | |
4153 | env->regs[13] = tmp; | |
4154 | env->v7m.current_sp = process; | |
4155 | } | |
4156 | } | |
4157 | ||
4158 | static void do_v7m_exception_exit(CPUARMState *env) | |
4159 | { | |
4160 | uint32_t type; | |
4161 | uint32_t xpsr; | |
4162 | ||
4163 | type = env->regs[15]; | |
4164 | if (env->v7m.exception != 0) | |
983fe826 | 4165 | armv7m_nvic_complete_irq(env->nvic, env->v7m.exception); |
9ee6e8bb PB |
4166 | |
4167 | /* Switch to the target stack. */ | |
4168 | switch_v7m_sp(env, (type & 4) != 0); | |
4169 | /* Pop registers. */ | |
4170 | env->regs[0] = v7m_pop(env); | |
4171 | env->regs[1] = v7m_pop(env); | |
4172 | env->regs[2] = v7m_pop(env); | |
4173 | env->regs[3] = v7m_pop(env); | |
4174 | env->regs[12] = v7m_pop(env); | |
4175 | env->regs[14] = v7m_pop(env); | |
4176 | env->regs[15] = v7m_pop(env); | |
4177 | xpsr = v7m_pop(env); | |
4178 | xpsr_write(env, xpsr, 0xfffffdff); | |
4179 | /* Undo stack alignment. */ | |
4180 | if (xpsr & 0x200) | |
4181 | env->regs[13] |= 4; | |
4182 | /* ??? The exception return type specifies Thread/Handler mode. However | |
4183 | this is also implied by the xPSR value. Not sure what to do | |
4184 | if there is a mismatch. */ | |
4185 | /* ??? Likewise for mismatches between the CONTROL register and the stack | |
4186 | pointer. */ | |
4187 | } | |
4188 | ||
e6f010cc | 4189 | void arm_v7m_cpu_do_interrupt(CPUState *cs) |
9ee6e8bb | 4190 | { |
e6f010cc AF |
4191 | ARMCPU *cpu = ARM_CPU(cs); |
4192 | CPUARMState *env = &cpu->env; | |
9ee6e8bb PB |
4193 | uint32_t xpsr = xpsr_read(env); |
4194 | uint32_t lr; | |
4195 | uint32_t addr; | |
4196 | ||
27103424 | 4197 | arm_log_exception(cs->exception_index); |
3f1beaca | 4198 | |
9ee6e8bb PB |
4199 | lr = 0xfffffff1; |
4200 | if (env->v7m.current_sp) | |
4201 | lr |= 4; | |
4202 | if (env->v7m.exception == 0) | |
4203 | lr |= 8; | |
4204 | ||
4205 | /* For exceptions we just mark as pending on the NVIC, and let that | |
4206 | handle it. */ | |
4207 | /* TODO: Need to escalate if the current priority is higher than the | |
4208 | one we're raising. */ | |
27103424 | 4209 | switch (cs->exception_index) { |
9ee6e8bb | 4210 | case EXCP_UDEF: |
983fe826 | 4211 | armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE); |
9ee6e8bb PB |
4212 | return; |
4213 | case EXCP_SWI: | |
314e2296 | 4214 | /* The PC already points to the next instruction. */ |
983fe826 | 4215 | armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_SVC); |
9ee6e8bb PB |
4216 | return; |
4217 | case EXCP_PREFETCH_ABORT: | |
4218 | case EXCP_DATA_ABORT: | |
abf1172f PM |
4219 | /* TODO: if we implemented the MPU registers, this is where we |
4220 | * should set the MMFAR, etc from exception.fsr and exception.vaddress. | |
4221 | */ | |
983fe826 | 4222 | armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_MEM); |
9ee6e8bb PB |
4223 | return; |
4224 | case EXCP_BKPT: | |
2ad207d4 PB |
4225 | if (semihosting_enabled) { |
4226 | int nr; | |
d31dd73e | 4227 | nr = arm_lduw_code(env, env->regs[15], env->bswap_code) & 0xff; |
2ad207d4 PB |
4228 | if (nr == 0xab) { |
4229 | env->regs[15] += 2; | |
4230 | env->regs[0] = do_arm_semihosting(env); | |
3f1beaca | 4231 | qemu_log_mask(CPU_LOG_INT, "...handled as semihosting call\n"); |
2ad207d4 PB |
4232 | return; |
4233 | } | |
4234 | } | |
983fe826 | 4235 | armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_DEBUG); |
9ee6e8bb PB |
4236 | return; |
4237 | case EXCP_IRQ: | |
983fe826 | 4238 | env->v7m.exception = armv7m_nvic_acknowledge_irq(env->nvic); |
9ee6e8bb PB |
4239 | break; |
4240 | case EXCP_EXCEPTION_EXIT: | |
4241 | do_v7m_exception_exit(env); | |
4242 | return; | |
4243 | default: | |
a47dddd7 | 4244 | cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index); |
9ee6e8bb PB |
4245 | return; /* Never happens. Keep compiler happy. */ |
4246 | } | |
4247 | ||
4248 | /* Align stack pointer. */ | |
4249 | /* ??? Should only do this if Configuration Control Register | |
4250 | STACKALIGN bit is set. */ | |
4251 | if (env->regs[13] & 4) { | |
ab19b0ec | 4252 | env->regs[13] -= 4; |
9ee6e8bb PB |
4253 | xpsr |= 0x200; |
4254 | } | |
6c95676b | 4255 | /* Switch to the handler mode. */ |
9ee6e8bb PB |
4256 | v7m_push(env, xpsr); |
4257 | v7m_push(env, env->regs[15]); | |
4258 | v7m_push(env, env->regs[14]); | |
4259 | v7m_push(env, env->regs[12]); | |
4260 | v7m_push(env, env->regs[3]); | |
4261 | v7m_push(env, env->regs[2]); | |
4262 | v7m_push(env, env->regs[1]); | |
4263 | v7m_push(env, env->regs[0]); | |
4264 | switch_v7m_sp(env, 0); | |
c98d174c PM |
4265 | /* Clear IT bits */ |
4266 | env->condexec_bits = 0; | |
9ee6e8bb | 4267 | env->regs[14] = lr; |
fdfba1a2 | 4268 | addr = ldl_phys(cs->as, env->v7m.vecbase + env->v7m.exception * 4); |
9ee6e8bb PB |
4269 | env->regs[15] = addr & 0xfffffffe; |
4270 | env->thumb = addr & 1; | |
4271 | } | |
4272 | ||
b5ff1b31 | 4273 | /* Handle a CPU exception. */ |
97a8ea5a | 4274 | void arm_cpu_do_interrupt(CPUState *cs) |
b5ff1b31 | 4275 | { |
97a8ea5a AF |
4276 | ARMCPU *cpu = ARM_CPU(cs); |
4277 | CPUARMState *env = &cpu->env; | |
b5ff1b31 FB |
4278 | uint32_t addr; |
4279 | uint32_t mask; | |
4280 | int new_mode; | |
4281 | uint32_t offset; | |
16a906fd | 4282 | uint32_t moe; |
b5ff1b31 | 4283 | |
e6f010cc AF |
4284 | assert(!IS_M(env)); |
4285 | ||
27103424 | 4286 | arm_log_exception(cs->exception_index); |
3f1beaca | 4287 | |
98128601 RH |
4288 | if (arm_is_psci_call(cpu, cs->exception_index)) { |
4289 | arm_handle_psci_call(cpu); | |
4290 | qemu_log_mask(CPU_LOG_INT, "...handled as PSCI call\n"); | |
4291 | return; | |
4292 | } | |
4293 | ||
16a906fd PM |
4294 | /* If this is a debug exception we must update the DBGDSCR.MOE bits */ |
4295 | switch (env->exception.syndrome >> ARM_EL_EC_SHIFT) { | |
4296 | case EC_BREAKPOINT: | |
4297 | case EC_BREAKPOINT_SAME_EL: | |
4298 | moe = 1; | |
4299 | break; | |
4300 | case EC_WATCHPOINT: | |
4301 | case EC_WATCHPOINT_SAME_EL: | |
4302 | moe = 10; | |
4303 | break; | |
4304 | case EC_AA32_BKPT: | |
4305 | moe = 3; | |
4306 | break; | |
4307 | case EC_VECTORCATCH: | |
4308 | moe = 5; | |
4309 | break; | |
4310 | default: | |
4311 | moe = 0; | |
4312 | break; | |
4313 | } | |
4314 | ||
4315 | if (moe) { | |
4316 | env->cp15.mdscr_el1 = deposit64(env->cp15.mdscr_el1, 2, 4, moe); | |
4317 | } | |
4318 | ||
b5ff1b31 | 4319 | /* TODO: Vectored interrupt controller. */ |
27103424 | 4320 | switch (cs->exception_index) { |
b5ff1b31 FB |
4321 | case EXCP_UDEF: |
4322 | new_mode = ARM_CPU_MODE_UND; | |
4323 | addr = 0x04; | |
4324 | mask = CPSR_I; | |
4325 | if (env->thumb) | |
4326 | offset = 2; | |
4327 | else | |
4328 | offset = 4; | |
4329 | break; | |
4330 | case EXCP_SWI: | |
8e71621f PB |
4331 | if (semihosting_enabled) { |
4332 | /* Check for semihosting interrupt. */ | |
4333 | if (env->thumb) { | |
d31dd73e BS |
4334 | mask = arm_lduw_code(env, env->regs[15] - 2, env->bswap_code) |
4335 | & 0xff; | |
8e71621f | 4336 | } else { |
d31dd73e | 4337 | mask = arm_ldl_code(env, env->regs[15] - 4, env->bswap_code) |
d8fd2954 | 4338 | & 0xffffff; |
8e71621f PB |
4339 | } |
4340 | /* Only intercept calls from privileged modes, to provide some | |
4341 | semblance of security. */ | |
4342 | if (((mask == 0x123456 && !env->thumb) | |
4343 | || (mask == 0xab && env->thumb)) | |
4344 | && (env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR) { | |
4345 | env->regs[0] = do_arm_semihosting(env); | |
3f1beaca | 4346 | qemu_log_mask(CPU_LOG_INT, "...handled as semihosting call\n"); |
8e71621f PB |
4347 | return; |
4348 | } | |
4349 | } | |
b5ff1b31 FB |
4350 | new_mode = ARM_CPU_MODE_SVC; |
4351 | addr = 0x08; | |
4352 | mask = CPSR_I; | |
601d70b9 | 4353 | /* The PC already points to the next instruction. */ |
b5ff1b31 FB |
4354 | offset = 0; |
4355 | break; | |
06c949e6 | 4356 | case EXCP_BKPT: |
9ee6e8bb | 4357 | /* See if this is a semihosting syscall. */ |
2ad207d4 | 4358 | if (env->thumb && semihosting_enabled) { |
d31dd73e | 4359 | mask = arm_lduw_code(env, env->regs[15], env->bswap_code) & 0xff; |
9ee6e8bb PB |
4360 | if (mask == 0xab |
4361 | && (env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR) { | |
4362 | env->regs[15] += 2; | |
4363 | env->regs[0] = do_arm_semihosting(env); | |
3f1beaca | 4364 | qemu_log_mask(CPU_LOG_INT, "...handled as semihosting call\n"); |
9ee6e8bb PB |
4365 | return; |
4366 | } | |
4367 | } | |
abf1172f | 4368 | env->exception.fsr = 2; |
9ee6e8bb PB |
4369 | /* Fall through to prefetch abort. */ |
4370 | case EXCP_PREFETCH_ABORT: | |
88ca1c2d | 4371 | A32_BANKED_CURRENT_REG_SET(env, ifsr, env->exception.fsr); |
b848ce2b | 4372 | A32_BANKED_CURRENT_REG_SET(env, ifar, env->exception.vaddress); |
3f1beaca | 4373 | qemu_log_mask(CPU_LOG_INT, "...with IFSR 0x%x IFAR 0x%x\n", |
88ca1c2d | 4374 | env->exception.fsr, (uint32_t)env->exception.vaddress); |
b5ff1b31 FB |
4375 | new_mode = ARM_CPU_MODE_ABT; |
4376 | addr = 0x0c; | |
4377 | mask = CPSR_A | CPSR_I; | |
4378 | offset = 4; | |
4379 | break; | |
4380 | case EXCP_DATA_ABORT: | |
4a7e2d73 | 4381 | A32_BANKED_CURRENT_REG_SET(env, dfsr, env->exception.fsr); |
b848ce2b | 4382 | A32_BANKED_CURRENT_REG_SET(env, dfar, env->exception.vaddress); |
3f1beaca | 4383 | qemu_log_mask(CPU_LOG_INT, "...with DFSR 0x%x DFAR 0x%x\n", |
4a7e2d73 | 4384 | env->exception.fsr, |
6cd8a264 | 4385 | (uint32_t)env->exception.vaddress); |
b5ff1b31 FB |
4386 | new_mode = ARM_CPU_MODE_ABT; |
4387 | addr = 0x10; | |
4388 | mask = CPSR_A | CPSR_I; | |
4389 | offset = 8; | |
4390 | break; | |
4391 | case EXCP_IRQ: | |
4392 | new_mode = ARM_CPU_MODE_IRQ; | |
4393 | addr = 0x18; | |
4394 | /* Disable IRQ and imprecise data aborts. */ | |
4395 | mask = CPSR_A | CPSR_I; | |
4396 | offset = 4; | |
de38d23b FA |
4397 | if (env->cp15.scr_el3 & SCR_IRQ) { |
4398 | /* IRQ routed to monitor mode */ | |
4399 | new_mode = ARM_CPU_MODE_MON; | |
4400 | mask |= CPSR_F; | |
4401 | } | |
b5ff1b31 FB |
4402 | break; |
4403 | case EXCP_FIQ: | |
4404 | new_mode = ARM_CPU_MODE_FIQ; | |
4405 | addr = 0x1c; | |
4406 | /* Disable FIQ, IRQ and imprecise data aborts. */ | |
4407 | mask = CPSR_A | CPSR_I | CPSR_F; | |
de38d23b FA |
4408 | if (env->cp15.scr_el3 & SCR_FIQ) { |
4409 | /* FIQ routed to monitor mode */ | |
4410 | new_mode = ARM_CPU_MODE_MON; | |
4411 | } | |
b5ff1b31 FB |
4412 | offset = 4; |
4413 | break; | |
dbe9d163 FA |
4414 | case EXCP_SMC: |
4415 | new_mode = ARM_CPU_MODE_MON; | |
4416 | addr = 0x08; | |
4417 | mask = CPSR_A | CPSR_I | CPSR_F; | |
4418 | offset = 0; | |
4419 | break; | |
b5ff1b31 | 4420 | default: |
a47dddd7 | 4421 | cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index); |
b5ff1b31 FB |
4422 | return; /* Never happens. Keep compiler happy. */ |
4423 | } | |
e89e51a1 FA |
4424 | |
4425 | if (new_mode == ARM_CPU_MODE_MON) { | |
4426 | addr += env->cp15.mvbar; | |
137feaa9 | 4427 | } else if (A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_V) { |
e89e51a1 | 4428 | /* High vectors. When enabled, base address cannot be remapped. */ |
b5ff1b31 | 4429 | addr += 0xffff0000; |
8641136c NR |
4430 | } else { |
4431 | /* ARM v7 architectures provide a vector base address register to remap | |
4432 | * the interrupt vector table. | |
e89e51a1 | 4433 | * This register is only followed in non-monitor mode, and is banked. |
8641136c NR |
4434 | * Note: only bits 31:5 are valid. |
4435 | */ | |
fb6c91ba | 4436 | addr += A32_BANKED_CURRENT_REG_GET(env, vbar); |
b5ff1b31 | 4437 | } |
dbe9d163 FA |
4438 | |
4439 | if ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_MON) { | |
4440 | env->cp15.scr_el3 &= ~SCR_NS; | |
4441 | } | |
4442 | ||
b5ff1b31 | 4443 | switch_mode (env, new_mode); |
662cefb7 PM |
4444 | /* For exceptions taken to AArch32 we must clear the SS bit in both |
4445 | * PSTATE and in the old-state value we save to SPSR_<mode>, so zero it now. | |
4446 | */ | |
4447 | env->uncached_cpsr &= ~PSTATE_SS; | |
b5ff1b31 | 4448 | env->spsr = cpsr_read(env); |
9ee6e8bb PB |
4449 | /* Clear IT bits. */ |
4450 | env->condexec_bits = 0; | |
30a8cac1 | 4451 | /* Switch to the new mode, and to the correct instruction set. */ |
6d7e6326 | 4452 | env->uncached_cpsr = (env->uncached_cpsr & ~CPSR_M) | new_mode; |
4cc35614 | 4453 | env->daif |= mask; |
be5e7a76 DES |
4454 | /* this is a lie, as the was no c1_sys on V4T/V5, but who cares |
4455 | * and we should just guard the thumb mode on V4 */ | |
4456 | if (arm_feature(env, ARM_FEATURE_V4T)) { | |
137feaa9 | 4457 | env->thumb = (A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_TE) != 0; |
be5e7a76 | 4458 | } |
b5ff1b31 FB |
4459 | env->regs[14] = env->regs[15] + offset; |
4460 | env->regs[15] = addr; | |
259186a7 | 4461 | cs->interrupt_request |= CPU_INTERRUPT_EXITTB; |
b5ff1b31 FB |
4462 | } |
4463 | ||
4464 | /* Check section/page access permissions. | |
4465 | Returns the page protection flags, or zero if the access is not | |
4466 | permitted. */ | |
0ecb72a5 | 4467 | static inline int check_ap(CPUARMState *env, int ap, int domain_prot, |
dd4ebc2e | 4468 | int access_type, int is_user) |
b5ff1b31 | 4469 | { |
9ee6e8bb PB |
4470 | int prot_ro; |
4471 | ||
dd4ebc2e | 4472 | if (domain_prot == 3) { |
b5ff1b31 | 4473 | return PAGE_READ | PAGE_WRITE; |
dd4ebc2e | 4474 | } |
b5ff1b31 | 4475 | |
9ee6e8bb PB |
4476 | if (access_type == 1) |
4477 | prot_ro = 0; | |
4478 | else | |
4479 | prot_ro = PAGE_READ; | |
4480 | ||
b5ff1b31 FB |
4481 | switch (ap) { |
4482 | case 0: | |
99f678a6 PM |
4483 | if (arm_feature(env, ARM_FEATURE_V7)) { |
4484 | return 0; | |
4485 | } | |
78600320 | 4486 | if (access_type == 1) |
b5ff1b31 | 4487 | return 0; |
137feaa9 | 4488 | switch (A32_BANKED_CURRENT_REG_GET(env, sctlr) & (SCTLR_S | SCTLR_R)) { |
76e3e1bc | 4489 | case SCTLR_S: |
b5ff1b31 | 4490 | return is_user ? 0 : PAGE_READ; |
76e3e1bc | 4491 | case SCTLR_R: |
b5ff1b31 FB |
4492 | return PAGE_READ; |
4493 | default: | |
4494 | return 0; | |
4495 | } | |
4496 | case 1: | |
4497 | return is_user ? 0 : PAGE_READ | PAGE_WRITE; | |
4498 | case 2: | |
4499 | if (is_user) | |
9ee6e8bb | 4500 | return prot_ro; |
b5ff1b31 FB |
4501 | else |
4502 | return PAGE_READ | PAGE_WRITE; | |
4503 | case 3: | |
4504 | return PAGE_READ | PAGE_WRITE; | |
d4934d18 | 4505 | case 4: /* Reserved. */ |
9ee6e8bb PB |
4506 | return 0; |
4507 | case 5: | |
4508 | return is_user ? 0 : prot_ro; | |
4509 | case 6: | |
4510 | return prot_ro; | |
d4934d18 | 4511 | case 7: |
0ab06d83 | 4512 | if (!arm_feature (env, ARM_FEATURE_V6K)) |
d4934d18 PB |
4513 | return 0; |
4514 | return prot_ro; | |
b5ff1b31 FB |
4515 | default: |
4516 | abort(); | |
4517 | } | |
4518 | } | |
4519 | ||
e389be16 FA |
4520 | static bool get_level1_table_address(CPUARMState *env, uint32_t *table, |
4521 | uint32_t address) | |
b2fa1797 | 4522 | { |
11f136ee FA |
4523 | /* Get the TCR bank based on our security state */ |
4524 | TCR *tcr = &env->cp15.tcr_el[arm_is_secure(env) ? 3 : 1]; | |
4525 | ||
7dd8c9af FA |
4526 | /* We only get here if EL1 is running in AArch32. If EL3 is running in |
4527 | * AArch32 there is a secure and non-secure instance of the translation | |
4528 | * table registers. | |
4529 | */ | |
11f136ee FA |
4530 | if (address & tcr->mask) { |
4531 | if (tcr->raw_tcr & TTBCR_PD1) { | |
e389be16 FA |
4532 | /* Translation table walk disabled for TTBR1 */ |
4533 | return false; | |
4534 | } | |
7dd8c9af | 4535 | *table = A32_BANKED_CURRENT_REG_GET(env, ttbr1) & 0xffffc000; |
e389be16 | 4536 | } else { |
11f136ee | 4537 | if (tcr->raw_tcr & TTBCR_PD0) { |
e389be16 FA |
4538 | /* Translation table walk disabled for TTBR0 */ |
4539 | return false; | |
4540 | } | |
11f136ee | 4541 | *table = A32_BANKED_CURRENT_REG_GET(env, ttbr0) & tcr->base_mask; |
e389be16 FA |
4542 | } |
4543 | *table |= (address >> 18) & 0x3ffc; | |
4544 | return true; | |
b2fa1797 PB |
4545 | } |
4546 | ||
0ecb72a5 | 4547 | static int get_phys_addr_v5(CPUARMState *env, uint32_t address, int access_type, |
a8170e5e | 4548 | int is_user, hwaddr *phys_ptr, |
77a71dd1 | 4549 | int *prot, target_ulong *page_size) |
b5ff1b31 | 4550 | { |
70d74660 | 4551 | CPUState *cs = CPU(arm_env_get_cpu(env)); |
b5ff1b31 FB |
4552 | int code; |
4553 | uint32_t table; | |
4554 | uint32_t desc; | |
4555 | int type; | |
4556 | int ap; | |
e389be16 | 4557 | int domain = 0; |
dd4ebc2e | 4558 | int domain_prot; |
a8170e5e | 4559 | hwaddr phys_addr; |
b5ff1b31 | 4560 | |
9ee6e8bb PB |
4561 | /* Pagetable walk. */ |
4562 | /* Lookup l1 descriptor. */ | |
e389be16 FA |
4563 | if (!get_level1_table_address(env, &table, address)) { |
4564 | /* Section translation fault if page walk is disabled by PD0 or PD1 */ | |
4565 | code = 5; | |
4566 | goto do_fault; | |
4567 | } | |
fdfba1a2 | 4568 | desc = ldl_phys(cs->as, table); |
9ee6e8bb | 4569 | type = (desc & 3); |
dd4ebc2e | 4570 | domain = (desc >> 5) & 0x0f; |
0c17d68c | 4571 | domain_prot = (A32_BANKED_CURRENT_REG_GET(env, dacr) >> (domain * 2)) & 3; |
9ee6e8bb | 4572 | if (type == 0) { |
601d70b9 | 4573 | /* Section translation fault. */ |
9ee6e8bb PB |
4574 | code = 5; |
4575 | goto do_fault; | |
4576 | } | |
dd4ebc2e | 4577 | if (domain_prot == 0 || domain_prot == 2) { |
9ee6e8bb PB |
4578 | if (type == 2) |
4579 | code = 9; /* Section domain fault. */ | |
4580 | else | |
4581 | code = 11; /* Page domain fault. */ | |
4582 | goto do_fault; | |
4583 | } | |
4584 | if (type == 2) { | |
4585 | /* 1Mb section. */ | |
4586 | phys_addr = (desc & 0xfff00000) | (address & 0x000fffff); | |
4587 | ap = (desc >> 10) & 3; | |
4588 | code = 13; | |
d4c430a8 | 4589 | *page_size = 1024 * 1024; |
9ee6e8bb PB |
4590 | } else { |
4591 | /* Lookup l2 entry. */ | |
4592 | if (type == 1) { | |
4593 | /* Coarse pagetable. */ | |
4594 | table = (desc & 0xfffffc00) | ((address >> 10) & 0x3fc); | |
4595 | } else { | |
4596 | /* Fine pagetable. */ | |
4597 | table = (desc & 0xfffff000) | ((address >> 8) & 0xffc); | |
4598 | } | |
fdfba1a2 | 4599 | desc = ldl_phys(cs->as, table); |
9ee6e8bb PB |
4600 | switch (desc & 3) { |
4601 | case 0: /* Page translation fault. */ | |
4602 | code = 7; | |
4603 | goto do_fault; | |
4604 | case 1: /* 64k page. */ | |
4605 | phys_addr = (desc & 0xffff0000) | (address & 0xffff); | |
4606 | ap = (desc >> (4 + ((address >> 13) & 6))) & 3; | |
d4c430a8 | 4607 | *page_size = 0x10000; |
ce819861 | 4608 | break; |
9ee6e8bb PB |
4609 | case 2: /* 4k page. */ |
4610 | phys_addr = (desc & 0xfffff000) | (address & 0xfff); | |
c10f7fc3 | 4611 | ap = (desc >> (4 + ((address >> 9) & 6))) & 3; |
d4c430a8 | 4612 | *page_size = 0x1000; |
ce819861 | 4613 | break; |
9ee6e8bb PB |
4614 | case 3: /* 1k page. */ |
4615 | if (type == 1) { | |
4616 | if (arm_feature(env, ARM_FEATURE_XSCALE)) { | |
4617 | phys_addr = (desc & 0xfffff000) | (address & 0xfff); | |
4618 | } else { | |
4619 | /* Page translation fault. */ | |
4620 | code = 7; | |
4621 | goto do_fault; | |
4622 | } | |
4623 | } else { | |
4624 | phys_addr = (desc & 0xfffffc00) | (address & 0x3ff); | |
4625 | } | |
4626 | ap = (desc >> 4) & 3; | |
d4c430a8 | 4627 | *page_size = 0x400; |
ce819861 PB |
4628 | break; |
4629 | default: | |
9ee6e8bb PB |
4630 | /* Never happens, but compiler isn't smart enough to tell. */ |
4631 | abort(); | |
ce819861 | 4632 | } |
9ee6e8bb PB |
4633 | code = 15; |
4634 | } | |
dd4ebc2e | 4635 | *prot = check_ap(env, ap, domain_prot, access_type, is_user); |
9ee6e8bb PB |
4636 | if (!*prot) { |
4637 | /* Access permission fault. */ | |
4638 | goto do_fault; | |
4639 | } | |
3ad493fc | 4640 | *prot |= PAGE_EXEC; |
9ee6e8bb PB |
4641 | *phys_ptr = phys_addr; |
4642 | return 0; | |
4643 | do_fault: | |
4644 | return code | (domain << 4); | |
4645 | } | |
4646 | ||
0ecb72a5 | 4647 | static int get_phys_addr_v6(CPUARMState *env, uint32_t address, int access_type, |
a8170e5e | 4648 | int is_user, hwaddr *phys_ptr, |
77a71dd1 | 4649 | int *prot, target_ulong *page_size) |
9ee6e8bb | 4650 | { |
70d74660 | 4651 | CPUState *cs = CPU(arm_env_get_cpu(env)); |
9ee6e8bb PB |
4652 | int code; |
4653 | uint32_t table; | |
4654 | uint32_t desc; | |
4655 | uint32_t xn; | |
de9b05b8 | 4656 | uint32_t pxn = 0; |
9ee6e8bb PB |
4657 | int type; |
4658 | int ap; | |
de9b05b8 | 4659 | int domain = 0; |
dd4ebc2e | 4660 | int domain_prot; |
a8170e5e | 4661 | hwaddr phys_addr; |
9ee6e8bb PB |
4662 | |
4663 | /* Pagetable walk. */ | |
4664 | /* Lookup l1 descriptor. */ | |
e389be16 FA |
4665 | if (!get_level1_table_address(env, &table, address)) { |
4666 | /* Section translation fault if page walk is disabled by PD0 or PD1 */ | |
4667 | code = 5; | |
4668 | goto do_fault; | |
4669 | } | |
fdfba1a2 | 4670 | desc = ldl_phys(cs->as, table); |
9ee6e8bb | 4671 | type = (desc & 3); |
de9b05b8 PM |
4672 | if (type == 0 || (type == 3 && !arm_feature(env, ARM_FEATURE_PXN))) { |
4673 | /* Section translation fault, or attempt to use the encoding | |
4674 | * which is Reserved on implementations without PXN. | |
4675 | */ | |
9ee6e8bb | 4676 | code = 5; |
9ee6e8bb | 4677 | goto do_fault; |
de9b05b8 PM |
4678 | } |
4679 | if ((type == 1) || !(desc & (1 << 18))) { | |
4680 | /* Page or Section. */ | |
dd4ebc2e | 4681 | domain = (desc >> 5) & 0x0f; |
9ee6e8bb | 4682 | } |
0c17d68c | 4683 | domain_prot = (A32_BANKED_CURRENT_REG_GET(env, dacr) >> (domain * 2)) & 3; |
dd4ebc2e | 4684 | if (domain_prot == 0 || domain_prot == 2) { |
de9b05b8 | 4685 | if (type != 1) { |
9ee6e8bb | 4686 | code = 9; /* Section domain fault. */ |
de9b05b8 | 4687 | } else { |
9ee6e8bb | 4688 | code = 11; /* Page domain fault. */ |
de9b05b8 | 4689 | } |
9ee6e8bb PB |
4690 | goto do_fault; |
4691 | } | |
de9b05b8 | 4692 | if (type != 1) { |
9ee6e8bb PB |
4693 | if (desc & (1 << 18)) { |
4694 | /* Supersection. */ | |
4695 | phys_addr = (desc & 0xff000000) | (address & 0x00ffffff); | |
d4c430a8 | 4696 | *page_size = 0x1000000; |
b5ff1b31 | 4697 | } else { |
9ee6e8bb PB |
4698 | /* Section. */ |
4699 | phys_addr = (desc & 0xfff00000) | (address & 0x000fffff); | |
d4c430a8 | 4700 | *page_size = 0x100000; |
b5ff1b31 | 4701 | } |
9ee6e8bb PB |
4702 | ap = ((desc >> 10) & 3) | ((desc >> 13) & 4); |
4703 | xn = desc & (1 << 4); | |
de9b05b8 | 4704 | pxn = desc & 1; |
9ee6e8bb PB |
4705 | code = 13; |
4706 | } else { | |
de9b05b8 PM |
4707 | if (arm_feature(env, ARM_FEATURE_PXN)) { |
4708 | pxn = (desc >> 2) & 1; | |
4709 | } | |
9ee6e8bb PB |
4710 | /* Lookup l2 entry. */ |
4711 | table = (desc & 0xfffffc00) | ((address >> 10) & 0x3fc); | |
fdfba1a2 | 4712 | desc = ldl_phys(cs->as, table); |
9ee6e8bb PB |
4713 | ap = ((desc >> 4) & 3) | ((desc >> 7) & 4); |
4714 | switch (desc & 3) { | |
4715 | case 0: /* Page translation fault. */ | |
4716 | code = 7; | |
b5ff1b31 | 4717 | goto do_fault; |
9ee6e8bb PB |
4718 | case 1: /* 64k page. */ |
4719 | phys_addr = (desc & 0xffff0000) | (address & 0xffff); | |
4720 | xn = desc & (1 << 15); | |
d4c430a8 | 4721 | *page_size = 0x10000; |
9ee6e8bb PB |
4722 | break; |
4723 | case 2: case 3: /* 4k page. */ | |
4724 | phys_addr = (desc & 0xfffff000) | (address & 0xfff); | |
4725 | xn = desc & 1; | |
d4c430a8 | 4726 | *page_size = 0x1000; |
9ee6e8bb PB |
4727 | break; |
4728 | default: | |
4729 | /* Never happens, but compiler isn't smart enough to tell. */ | |
4730 | abort(); | |
b5ff1b31 | 4731 | } |
9ee6e8bb PB |
4732 | code = 15; |
4733 | } | |
dd4ebc2e | 4734 | if (domain_prot == 3) { |
c0034328 JR |
4735 | *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; |
4736 | } else { | |
de9b05b8 PM |
4737 | if (pxn && !is_user) { |
4738 | xn = 1; | |
4739 | } | |
c0034328 JR |
4740 | if (xn && access_type == 2) |
4741 | goto do_fault; | |
9ee6e8bb | 4742 | |
c0034328 | 4743 | /* The simplified model uses AP[0] as an access control bit. */ |
137feaa9 FA |
4744 | if ((A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_AFE) |
4745 | && (ap & 1) == 0) { | |
c0034328 JR |
4746 | /* Access flag fault. */ |
4747 | code = (code == 15) ? 6 : 3; | |
4748 | goto do_fault; | |
4749 | } | |
dd4ebc2e | 4750 | *prot = check_ap(env, ap, domain_prot, access_type, is_user); |
c0034328 JR |
4751 | if (!*prot) { |
4752 | /* Access permission fault. */ | |
4753 | goto do_fault; | |
4754 | } | |
4755 | if (!xn) { | |
4756 | *prot |= PAGE_EXEC; | |
4757 | } | |
3ad493fc | 4758 | } |
9ee6e8bb | 4759 | *phys_ptr = phys_addr; |
b5ff1b31 FB |
4760 | return 0; |
4761 | do_fault: | |
4762 | return code | (domain << 4); | |
4763 | } | |
4764 | ||
3dde962f PM |
4765 | /* Fault type for long-descriptor MMU fault reporting; this corresponds |
4766 | * to bits [5..2] in the STATUS field in long-format DFSR/IFSR. | |
4767 | */ | |
4768 | typedef enum { | |
4769 | translation_fault = 1, | |
4770 | access_fault = 2, | |
4771 | permission_fault = 3, | |
4772 | } MMUFaultType; | |
4773 | ||
2c8dd318 | 4774 | static int get_phys_addr_lpae(CPUARMState *env, target_ulong address, |
3dde962f | 4775 | int access_type, int is_user, |
a8170e5e | 4776 | hwaddr *phys_ptr, int *prot, |
3dde962f PM |
4777 | target_ulong *page_size_ptr) |
4778 | { | |
70d74660 | 4779 | CPUState *cs = CPU(arm_env_get_cpu(env)); |
3dde962f PM |
4780 | /* Read an LPAE long-descriptor translation table. */ |
4781 | MMUFaultType fault_type = translation_fault; | |
4782 | uint32_t level = 1; | |
4783 | uint32_t epd; | |
2c8dd318 RH |
4784 | int32_t tsz; |
4785 | uint32_t tg; | |
3dde962f PM |
4786 | uint64_t ttbr; |
4787 | int ttbr_select; | |
2c8dd318 | 4788 | hwaddr descaddr, descmask; |
3dde962f PM |
4789 | uint32_t tableattrs; |
4790 | target_ulong page_size; | |
4791 | uint32_t attrs; | |
2c8dd318 RH |
4792 | int32_t granule_sz = 9; |
4793 | int32_t va_size = 32; | |
4794 | int32_t tbi = 0; | |
11f136ee | 4795 | TCR *tcr = &env->cp15.tcr_el[arm_is_secure(env) ? 3 : 1]; |
2c8dd318 RH |
4796 | |
4797 | if (arm_el_is_aa64(env, 1)) { | |
4798 | va_size = 64; | |
4799 | if (extract64(address, 55, 1)) | |
11f136ee | 4800 | tbi = extract64(tcr->raw_tcr, 38, 1); |
2c8dd318 | 4801 | else |
11f136ee | 4802 | tbi = extract64(tcr->raw_tcr, 37, 1); |
2c8dd318 RH |
4803 | tbi *= 8; |
4804 | } | |
3dde962f PM |
4805 | |
4806 | /* Determine whether this address is in the region controlled by | |
4807 | * TTBR0 or TTBR1 (or if it is in neither region and should fault). | |
4808 | * This is a Non-secure PL0/1 stage 1 translation, so controlled by | |
4809 | * TTBCR/TTBR0/TTBR1 in accordance with ARM ARM DDI0406C table B-32: | |
4810 | */ | |
11f136ee | 4811 | uint32_t t0sz = extract32(tcr->raw_tcr, 0, 6); |
2c8dd318 RH |
4812 | if (arm_el_is_aa64(env, 1)) { |
4813 | t0sz = MIN(t0sz, 39); | |
4814 | t0sz = MAX(t0sz, 16); | |
4815 | } | |
11f136ee | 4816 | uint32_t t1sz = extract32(tcr->raw_tcr, 16, 6); |
2c8dd318 RH |
4817 | if (arm_el_is_aa64(env, 1)) { |
4818 | t1sz = MIN(t1sz, 39); | |
4819 | t1sz = MAX(t1sz, 16); | |
4820 | } | |
4821 | if (t0sz && !extract64(address, va_size - t0sz, t0sz - tbi)) { | |
3dde962f PM |
4822 | /* there is a ttbr0 region and we are in it (high bits all zero) */ |
4823 | ttbr_select = 0; | |
2c8dd318 | 4824 | } else if (t1sz && !extract64(~address, va_size - t1sz, t1sz - tbi)) { |
3dde962f PM |
4825 | /* there is a ttbr1 region and we are in it (high bits all one) */ |
4826 | ttbr_select = 1; | |
4827 | } else if (!t0sz) { | |
4828 | /* ttbr0 region is "everything not in the ttbr1 region" */ | |
4829 | ttbr_select = 0; | |
4830 | } else if (!t1sz) { | |
4831 | /* ttbr1 region is "everything not in the ttbr0 region" */ | |
4832 | ttbr_select = 1; | |
4833 | } else { | |
4834 | /* in the gap between the two regions, this is a Translation fault */ | |
4835 | fault_type = translation_fault; | |
4836 | goto do_fault; | |
4837 | } | |
4838 | ||
4839 | /* Note that QEMU ignores shareability and cacheability attributes, | |
4840 | * so we don't need to do anything with the SH, ORGN, IRGN fields | |
4841 | * in the TTBCR. Similarly, TTBCR:A1 selects whether we get the | |
4842 | * ASID from TTBR0 or TTBR1, but QEMU's TLB doesn't currently | |
4843 | * implement any ASID-like capability so we can ignore it (instead | |
4844 | * we will always flush the TLB any time the ASID is changed). | |
4845 | */ | |
4846 | if (ttbr_select == 0) { | |
7dd8c9af | 4847 | ttbr = A32_BANKED_CURRENT_REG_GET(env, ttbr0); |
11f136ee | 4848 | epd = extract32(tcr->raw_tcr, 7, 1); |
3dde962f | 4849 | tsz = t0sz; |
2c8dd318 | 4850 | |
11f136ee | 4851 | tg = extract32(tcr->raw_tcr, 14, 2); |
2c8dd318 RH |
4852 | if (tg == 1) { /* 64KB pages */ |
4853 | granule_sz = 13; | |
4854 | } | |
4855 | if (tg == 2) { /* 16KB pages */ | |
4856 | granule_sz = 11; | |
4857 | } | |
3dde962f | 4858 | } else { |
7dd8c9af | 4859 | ttbr = A32_BANKED_CURRENT_REG_GET(env, ttbr1); |
11f136ee | 4860 | epd = extract32(tcr->raw_tcr, 23, 1); |
3dde962f | 4861 | tsz = t1sz; |
2c8dd318 | 4862 | |
11f136ee | 4863 | tg = extract32(tcr->raw_tcr, 30, 2); |
2c8dd318 RH |
4864 | if (tg == 3) { /* 64KB pages */ |
4865 | granule_sz = 13; | |
4866 | } | |
4867 | if (tg == 1) { /* 16KB pages */ | |
4868 | granule_sz = 11; | |
4869 | } | |
3dde962f PM |
4870 | } |
4871 | ||
4872 | if (epd) { | |
4873 | /* Translation table walk disabled => Translation fault on TLB miss */ | |
4874 | goto do_fault; | |
4875 | } | |
4876 | ||
d6be29e3 PM |
4877 | /* The starting level depends on the virtual address size (which can be |
4878 | * up to 48 bits) and the translation granule size. It indicates the number | |
4879 | * of strides (granule_sz bits at a time) needed to consume the bits | |
4880 | * of the input address. In the pseudocode this is: | |
4881 | * level = 4 - RoundUp((inputsize - grainsize) / stride) | |
4882 | * where their 'inputsize' is our 'va_size - tsz', 'grainsize' is | |
4883 | * our 'granule_sz + 3' and 'stride' is our 'granule_sz'. | |
4884 | * Applying the usual "rounded up m/n is (m+n-1)/n" and simplifying: | |
4885 | * = 4 - (va_size - tsz - granule_sz - 3 + granule_sz - 1) / granule_sz | |
4886 | * = 4 - (va_size - tsz - 4) / granule_sz; | |
3dde962f | 4887 | */ |
d6be29e3 | 4888 | level = 4 - (va_size - tsz - 4) / granule_sz; |
3dde962f PM |
4889 | |
4890 | /* Clear the vaddr bits which aren't part of the within-region address, | |
4891 | * so that we don't have to special case things when calculating the | |
4892 | * first descriptor address. | |
4893 | */ | |
2c8dd318 RH |
4894 | if (tsz) { |
4895 | address &= (1ULL << (va_size - tsz)) - 1; | |
4896 | } | |
4897 | ||
4898 | descmask = (1ULL << (granule_sz + 3)) - 1; | |
3dde962f PM |
4899 | |
4900 | /* Now we can extract the actual base address from the TTBR */ | |
2c8dd318 RH |
4901 | descaddr = extract64(ttbr, 0, 48); |
4902 | descaddr &= ~((1ULL << (va_size - tsz - (granule_sz * (4 - level)))) - 1); | |
3dde962f PM |
4903 | |
4904 | tableattrs = 0; | |
4905 | for (;;) { | |
4906 | uint64_t descriptor; | |
4907 | ||
2c8dd318 RH |
4908 | descaddr |= (address >> (granule_sz * (4 - level))) & descmask; |
4909 | descaddr &= ~7ULL; | |
2c17449b | 4910 | descriptor = ldq_phys(cs->as, descaddr); |
3dde962f PM |
4911 | if (!(descriptor & 1) || |
4912 | (!(descriptor & 2) && (level == 3))) { | |
4913 | /* Invalid, or the Reserved level 3 encoding */ | |
4914 | goto do_fault; | |
4915 | } | |
4916 | descaddr = descriptor & 0xfffffff000ULL; | |
4917 | ||
4918 | if ((descriptor & 2) && (level < 3)) { | |
4919 | /* Table entry. The top five bits are attributes which may | |
4920 | * propagate down through lower levels of the table (and | |
4921 | * which are all arranged so that 0 means "no effect", so | |
4922 | * we can gather them up by ORing in the bits at each level). | |
4923 | */ | |
4924 | tableattrs |= extract64(descriptor, 59, 5); | |
4925 | level++; | |
4926 | continue; | |
4927 | } | |
4928 | /* Block entry at level 1 or 2, or page entry at level 3. | |
4929 | * These are basically the same thing, although the number | |
4930 | * of bits we pull in from the vaddr varies. | |
4931 | */ | |
5661ae6b | 4932 | page_size = (1ULL << ((granule_sz * (4 - level)) + 3)); |
3dde962f PM |
4933 | descaddr |= (address & (page_size - 1)); |
4934 | /* Extract attributes from the descriptor and merge with table attrs */ | |
d615efac IC |
4935 | attrs = extract64(descriptor, 2, 10) |
4936 | | (extract64(descriptor, 52, 12) << 10); | |
3dde962f PM |
4937 | attrs |= extract32(tableattrs, 0, 2) << 11; /* XN, PXN */ |
4938 | attrs |= extract32(tableattrs, 3, 1) << 5; /* APTable[1] => AP[2] */ | |
4939 | /* The sense of AP[1] vs APTable[0] is reversed, as APTable[0] == 1 | |
4940 | * means "force PL1 access only", which means forcing AP[1] to 0. | |
4941 | */ | |
4942 | if (extract32(tableattrs, 2, 1)) { | |
4943 | attrs &= ~(1 << 4); | |
4944 | } | |
4945 | /* Since we're always in the Non-secure state, NSTable is ignored. */ | |
4946 | break; | |
4947 | } | |
4948 | /* Here descaddr is the final physical address, and attributes | |
4949 | * are all in attrs. | |
4950 | */ | |
4951 | fault_type = access_fault; | |
4952 | if ((attrs & (1 << 8)) == 0) { | |
4953 | /* Access flag */ | |
4954 | goto do_fault; | |
4955 | } | |
4956 | fault_type = permission_fault; | |
4957 | if (is_user && !(attrs & (1 << 4))) { | |
4958 | /* Unprivileged access not enabled */ | |
4959 | goto do_fault; | |
4960 | } | |
4961 | *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; | |
d615efac IC |
4962 | if ((arm_feature(env, ARM_FEATURE_V8) && is_user && (attrs & (1 << 12))) || |
4963 | (!arm_feature(env, ARM_FEATURE_V8) && (attrs & (1 << 12))) || | |
4964 | (!is_user && (attrs & (1 << 11)))) { | |
4965 | /* XN/UXN or PXN. Since we only implement EL0/EL1 we unconditionally | |
4966 | * treat XN/UXN as UXN for v8. | |
4967 | */ | |
3dde962f PM |
4968 | if (access_type == 2) { |
4969 | goto do_fault; | |
4970 | } | |
4971 | *prot &= ~PAGE_EXEC; | |
4972 | } | |
4973 | if (attrs & (1 << 5)) { | |
4974 | /* Write access forbidden */ | |
4975 | if (access_type == 1) { | |
4976 | goto do_fault; | |
4977 | } | |
4978 | *prot &= ~PAGE_WRITE; | |
4979 | } | |
4980 | ||
4981 | *phys_ptr = descaddr; | |
4982 | *page_size_ptr = page_size; | |
4983 | return 0; | |
4984 | ||
4985 | do_fault: | |
4986 | /* Long-descriptor format IFSR/DFSR value */ | |
4987 | return (1 << 9) | (fault_type << 2) | level; | |
4988 | } | |
4989 | ||
77a71dd1 PM |
4990 | static int get_phys_addr_mpu(CPUARMState *env, uint32_t address, |
4991 | int access_type, int is_user, | |
a8170e5e | 4992 | hwaddr *phys_ptr, int *prot) |
9ee6e8bb PB |
4993 | { |
4994 | int n; | |
4995 | uint32_t mask; | |
4996 | uint32_t base; | |
4997 | ||
4998 | *phys_ptr = address; | |
4999 | for (n = 7; n >= 0; n--) { | |
5000 | base = env->cp15.c6_region[n]; | |
5001 | if ((base & 1) == 0) | |
5002 | continue; | |
5003 | mask = 1 << ((base >> 1) & 0x1f); | |
5004 | /* Keep this shift separate from the above to avoid an | |
5005 | (undefined) << 32. */ | |
5006 | mask = (mask << 1) - 1; | |
5007 | if (((base ^ address) & ~mask) == 0) | |
5008 | break; | |
5009 | } | |
5010 | if (n < 0) | |
5011 | return 2; | |
5012 | ||
5013 | if (access_type == 2) { | |
7e09797c | 5014 | mask = env->cp15.pmsav5_insn_ap; |
9ee6e8bb | 5015 | } else { |
7e09797c | 5016 | mask = env->cp15.pmsav5_data_ap; |
9ee6e8bb PB |
5017 | } |
5018 | mask = (mask >> (n * 4)) & 0xf; | |
5019 | switch (mask) { | |
5020 | case 0: | |
5021 | return 1; | |
5022 | case 1: | |
5023 | if (is_user) | |
5024 | return 1; | |
5025 | *prot = PAGE_READ | PAGE_WRITE; | |
5026 | break; | |
5027 | case 2: | |
5028 | *prot = PAGE_READ; | |
5029 | if (!is_user) | |
5030 | *prot |= PAGE_WRITE; | |
5031 | break; | |
5032 | case 3: | |
5033 | *prot = PAGE_READ | PAGE_WRITE; | |
5034 | break; | |
5035 | case 5: | |
5036 | if (is_user) | |
5037 | return 1; | |
5038 | *prot = PAGE_READ; | |
5039 | break; | |
5040 | case 6: | |
5041 | *prot = PAGE_READ; | |
5042 | break; | |
5043 | default: | |
5044 | /* Bad permission. */ | |
5045 | return 1; | |
5046 | } | |
3ad493fc | 5047 | *prot |= PAGE_EXEC; |
9ee6e8bb PB |
5048 | return 0; |
5049 | } | |
5050 | ||
702a9357 PM |
5051 | /* get_phys_addr - get the physical address for this virtual address |
5052 | * | |
5053 | * Find the physical address corresponding to the given virtual address, | |
5054 | * by doing a translation table walk on MMU based systems or using the | |
5055 | * MPU state on MPU based systems. | |
5056 | * | |
5057 | * Returns 0 if the translation was successful. Otherwise, phys_ptr, | |
5058 | * prot and page_size are not filled in, and the return value provides | |
5059 | * information on why the translation aborted, in the format of a | |
5060 | * DFSR/IFSR fault register, with the following caveats: | |
5061 | * * we honour the short vs long DFSR format differences. | |
5062 | * * the WnR bit is never set (the caller must do this). | |
5063 | * * for MPU based systems we don't bother to return a full FSR format | |
5064 | * value. | |
5065 | * | |
5066 | * @env: CPUARMState | |
5067 | * @address: virtual address to get physical address for | |
5068 | * @access_type: 0 for read, 1 for write, 2 for execute | |
5069 | * @is_user: 0 for privileged access, 1 for user | |
5070 | * @phys_ptr: set to the physical address corresponding to the virtual address | |
5071 | * @prot: set to the permissions for the page containing phys_ptr | |
5072 | * @page_size: set to the size of the page containing phys_ptr | |
5073 | */ | |
2c8dd318 | 5074 | static inline int get_phys_addr(CPUARMState *env, target_ulong address, |
9ee6e8bb | 5075 | int access_type, int is_user, |
a8170e5e | 5076 | hwaddr *phys_ptr, int *prot, |
d4c430a8 | 5077 | target_ulong *page_size) |
9ee6e8bb | 5078 | { |
137feaa9 FA |
5079 | /* This is not entirely correct as get_phys_addr() can also be called |
5080 | * from ats_write() for an address translation of a specific regime. | |
5081 | */ | |
5082 | uint32_t sctlr = A32_BANKED_CURRENT_REG_GET(env, sctlr); | |
5083 | ||
9ee6e8bb | 5084 | /* Fast Context Switch Extension. */ |
54bf36ed FA |
5085 | if (address < 0x02000000) { |
5086 | address += A32_BANKED_CURRENT_REG_GET(env, fcseidr); | |
5087 | } | |
9ee6e8bb | 5088 | |
137feaa9 | 5089 | if ((sctlr & SCTLR_M) == 0) { |
9ee6e8bb PB |
5090 | /* MMU/MPU disabled. */ |
5091 | *phys_ptr = address; | |
3ad493fc | 5092 | *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; |
d4c430a8 | 5093 | *page_size = TARGET_PAGE_SIZE; |
9ee6e8bb PB |
5094 | return 0; |
5095 | } else if (arm_feature(env, ARM_FEATURE_MPU)) { | |
d4c430a8 | 5096 | *page_size = TARGET_PAGE_SIZE; |
9ee6e8bb PB |
5097 | return get_phys_addr_mpu(env, address, access_type, is_user, phys_ptr, |
5098 | prot); | |
3dde962f PM |
5099 | } else if (extended_addresses_enabled(env)) { |
5100 | return get_phys_addr_lpae(env, address, access_type, is_user, phys_ptr, | |
5101 | prot, page_size); | |
137feaa9 | 5102 | } else if (sctlr & SCTLR_XP) { |
9ee6e8bb | 5103 | return get_phys_addr_v6(env, address, access_type, is_user, phys_ptr, |
d4c430a8 | 5104 | prot, page_size); |
9ee6e8bb PB |
5105 | } else { |
5106 | return get_phys_addr_v5(env, address, access_type, is_user, phys_ptr, | |
d4c430a8 | 5107 | prot, page_size); |
9ee6e8bb PB |
5108 | } |
5109 | } | |
5110 | ||
7510454e AF |
5111 | int arm_cpu_handle_mmu_fault(CPUState *cs, vaddr address, |
5112 | int access_type, int mmu_idx) | |
b5ff1b31 | 5113 | { |
7510454e AF |
5114 | ARMCPU *cpu = ARM_CPU(cs); |
5115 | CPUARMState *env = &cpu->env; | |
a8170e5e | 5116 | hwaddr phys_addr; |
d4c430a8 | 5117 | target_ulong page_size; |
b5ff1b31 | 5118 | int prot; |
6ebbf390 | 5119 | int ret, is_user; |
00892383 | 5120 | uint32_t syn; |
dcbff19b | 5121 | bool same_el = (arm_current_el(env) != 0); |
b5ff1b31 | 5122 | |
6ebbf390 | 5123 | is_user = mmu_idx == MMU_USER_IDX; |
d4c430a8 PB |
5124 | ret = get_phys_addr(env, address, access_type, is_user, &phys_addr, &prot, |
5125 | &page_size); | |
b5ff1b31 FB |
5126 | if (ret == 0) { |
5127 | /* Map a single [sub]page. */ | |
dcd82c11 AB |
5128 | phys_addr &= TARGET_PAGE_MASK; |
5129 | address &= TARGET_PAGE_MASK; | |
0c591eb0 | 5130 | tlb_set_page(cs, address, phys_addr, prot, mmu_idx, page_size); |
d4c430a8 | 5131 | return 0; |
b5ff1b31 FB |
5132 | } |
5133 | ||
00892383 RH |
5134 | /* AArch64 syndrome does not have an LPAE bit */ |
5135 | syn = ret & ~(1 << 9); | |
5136 | ||
5137 | /* For insn and data aborts we assume there is no instruction syndrome | |
5138 | * information; this is always true for exceptions reported to EL1. | |
5139 | */ | |
b5ff1b31 | 5140 | if (access_type == 2) { |
00892383 | 5141 | syn = syn_insn_abort(same_el, 0, 0, syn); |
27103424 | 5142 | cs->exception_index = EXCP_PREFETCH_ABORT; |
b5ff1b31 | 5143 | } else { |
00892383 | 5144 | syn = syn_data_abort(same_el, 0, 0, 0, access_type == 1, syn); |
abf1172f PM |
5145 | if (access_type == 1 && arm_feature(env, ARM_FEATURE_V6)) { |
5146 | ret |= (1 << 11); | |
5147 | } | |
27103424 | 5148 | cs->exception_index = EXCP_DATA_ABORT; |
b5ff1b31 | 5149 | } |
00892383 RH |
5150 | |
5151 | env->exception.syndrome = syn; | |
abf1172f PM |
5152 | env->exception.vaddress = address; |
5153 | env->exception.fsr = ret; | |
b5ff1b31 FB |
5154 | return 1; |
5155 | } | |
5156 | ||
00b941e5 | 5157 | hwaddr arm_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) |
b5ff1b31 | 5158 | { |
00b941e5 | 5159 | ARMCPU *cpu = ARM_CPU(cs); |
a8170e5e | 5160 | hwaddr phys_addr; |
d4c430a8 | 5161 | target_ulong page_size; |
b5ff1b31 FB |
5162 | int prot; |
5163 | int ret; | |
5164 | ||
00b941e5 | 5165 | ret = get_phys_addr(&cpu->env, addr, 0, 0, &phys_addr, &prot, &page_size); |
b5ff1b31 | 5166 | |
00b941e5 | 5167 | if (ret != 0) { |
b5ff1b31 | 5168 | return -1; |
00b941e5 | 5169 | } |
b5ff1b31 FB |
5170 | |
5171 | return phys_addr; | |
5172 | } | |
5173 | ||
0ecb72a5 | 5174 | void HELPER(set_r13_banked)(CPUARMState *env, uint32_t mode, uint32_t val) |
9ee6e8bb | 5175 | { |
39ea3d4e PM |
5176 | if ((env->uncached_cpsr & CPSR_M) == mode) { |
5177 | env->regs[13] = val; | |
5178 | } else { | |
f5206413 | 5179 | env->banked_r13[bank_number(mode)] = val; |
39ea3d4e | 5180 | } |
9ee6e8bb PB |
5181 | } |
5182 | ||
0ecb72a5 | 5183 | uint32_t HELPER(get_r13_banked)(CPUARMState *env, uint32_t mode) |
9ee6e8bb | 5184 | { |
39ea3d4e PM |
5185 | if ((env->uncached_cpsr & CPSR_M) == mode) { |
5186 | return env->regs[13]; | |
5187 | } else { | |
f5206413 | 5188 | return env->banked_r13[bank_number(mode)]; |
39ea3d4e | 5189 | } |
9ee6e8bb PB |
5190 | } |
5191 | ||
0ecb72a5 | 5192 | uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg) |
9ee6e8bb | 5193 | { |
a47dddd7 AF |
5194 | ARMCPU *cpu = arm_env_get_cpu(env); |
5195 | ||
9ee6e8bb PB |
5196 | switch (reg) { |
5197 | case 0: /* APSR */ | |
5198 | return xpsr_read(env) & 0xf8000000; | |
5199 | case 1: /* IAPSR */ | |
5200 | return xpsr_read(env) & 0xf80001ff; | |
5201 | case 2: /* EAPSR */ | |
5202 | return xpsr_read(env) & 0xff00fc00; | |
5203 | case 3: /* xPSR */ | |
5204 | return xpsr_read(env) & 0xff00fdff; | |
5205 | case 5: /* IPSR */ | |
5206 | return xpsr_read(env) & 0x000001ff; | |
5207 | case 6: /* EPSR */ | |
5208 | return xpsr_read(env) & 0x0700fc00; | |
5209 | case 7: /* IEPSR */ | |
5210 | return xpsr_read(env) & 0x0700edff; | |
5211 | case 8: /* MSP */ | |
5212 | return env->v7m.current_sp ? env->v7m.other_sp : env->regs[13]; | |
5213 | case 9: /* PSP */ | |
5214 | return env->v7m.current_sp ? env->regs[13] : env->v7m.other_sp; | |
5215 | case 16: /* PRIMASK */ | |
4cc35614 | 5216 | return (env->daif & PSTATE_I) != 0; |
82845826 SH |
5217 | case 17: /* BASEPRI */ |
5218 | case 18: /* BASEPRI_MAX */ | |
9ee6e8bb | 5219 | return env->v7m.basepri; |
82845826 | 5220 | case 19: /* FAULTMASK */ |
4cc35614 | 5221 | return (env->daif & PSTATE_F) != 0; |
9ee6e8bb PB |
5222 | case 20: /* CONTROL */ |
5223 | return env->v7m.control; | |
5224 | default: | |
5225 | /* ??? For debugging only. */ | |
a47dddd7 | 5226 | cpu_abort(CPU(cpu), "Unimplemented system register read (%d)\n", reg); |
9ee6e8bb PB |
5227 | return 0; |
5228 | } | |
5229 | } | |
5230 | ||
0ecb72a5 | 5231 | void HELPER(v7m_msr)(CPUARMState *env, uint32_t reg, uint32_t val) |
9ee6e8bb | 5232 | { |
a47dddd7 AF |
5233 | ARMCPU *cpu = arm_env_get_cpu(env); |
5234 | ||
9ee6e8bb PB |
5235 | switch (reg) { |
5236 | case 0: /* APSR */ | |
5237 | xpsr_write(env, val, 0xf8000000); | |
5238 | break; | |
5239 | case 1: /* IAPSR */ | |
5240 | xpsr_write(env, val, 0xf8000000); | |
5241 | break; | |
5242 | case 2: /* EAPSR */ | |
5243 | xpsr_write(env, val, 0xfe00fc00); | |
5244 | break; | |
5245 | case 3: /* xPSR */ | |
5246 | xpsr_write(env, val, 0xfe00fc00); | |
5247 | break; | |
5248 | case 5: /* IPSR */ | |
5249 | /* IPSR bits are readonly. */ | |
5250 | break; | |
5251 | case 6: /* EPSR */ | |
5252 | xpsr_write(env, val, 0x0600fc00); | |
5253 | break; | |
5254 | case 7: /* IEPSR */ | |
5255 | xpsr_write(env, val, 0x0600fc00); | |
5256 | break; | |
5257 | case 8: /* MSP */ | |
5258 | if (env->v7m.current_sp) | |
5259 | env->v7m.other_sp = val; | |
5260 | else | |
5261 | env->regs[13] = val; | |
5262 | break; | |
5263 | case 9: /* PSP */ | |
5264 | if (env->v7m.current_sp) | |
5265 | env->regs[13] = val; | |
5266 | else | |
5267 | env->v7m.other_sp = val; | |
5268 | break; | |
5269 | case 16: /* PRIMASK */ | |
4cc35614 PM |
5270 | if (val & 1) { |
5271 | env->daif |= PSTATE_I; | |
5272 | } else { | |
5273 | env->daif &= ~PSTATE_I; | |
5274 | } | |
9ee6e8bb | 5275 | break; |
82845826 | 5276 | case 17: /* BASEPRI */ |
9ee6e8bb PB |
5277 | env->v7m.basepri = val & 0xff; |
5278 | break; | |
82845826 | 5279 | case 18: /* BASEPRI_MAX */ |
9ee6e8bb PB |
5280 | val &= 0xff; |
5281 | if (val != 0 && (val < env->v7m.basepri || env->v7m.basepri == 0)) | |
5282 | env->v7m.basepri = val; | |
5283 | break; | |
82845826 | 5284 | case 19: /* FAULTMASK */ |
4cc35614 PM |
5285 | if (val & 1) { |
5286 | env->daif |= PSTATE_F; | |
5287 | } else { | |
5288 | env->daif &= ~PSTATE_F; | |
5289 | } | |
82845826 | 5290 | break; |
9ee6e8bb PB |
5291 | case 20: /* CONTROL */ |
5292 | env->v7m.control = val & 3; | |
5293 | switch_v7m_sp(env, (val & 2) != 0); | |
5294 | break; | |
5295 | default: | |
5296 | /* ??? For debugging only. */ | |
a47dddd7 | 5297 | cpu_abort(CPU(cpu), "Unimplemented system register write (%d)\n", reg); |
9ee6e8bb PB |
5298 | return; |
5299 | } | |
5300 | } | |
5301 | ||
b5ff1b31 | 5302 | #endif |
6ddbc6e4 | 5303 | |
aca3f40b PM |
5304 | void HELPER(dc_zva)(CPUARMState *env, uint64_t vaddr_in) |
5305 | { | |
5306 | /* Implement DC ZVA, which zeroes a fixed-length block of memory. | |
5307 | * Note that we do not implement the (architecturally mandated) | |
5308 | * alignment fault for attempts to use this on Device memory | |
5309 | * (which matches the usual QEMU behaviour of not implementing either | |
5310 | * alignment faults or any memory attribute handling). | |
5311 | */ | |
5312 | ||
5313 | ARMCPU *cpu = arm_env_get_cpu(env); | |
5314 | uint64_t blocklen = 4 << cpu->dcz_blocksize; | |
5315 | uint64_t vaddr = vaddr_in & ~(blocklen - 1); | |
5316 | ||
5317 | #ifndef CONFIG_USER_ONLY | |
5318 | { | |
5319 | /* Slightly awkwardly, QEMU's TARGET_PAGE_SIZE may be less than | |
5320 | * the block size so we might have to do more than one TLB lookup. | |
5321 | * We know that in fact for any v8 CPU the page size is at least 4K | |
5322 | * and the block size must be 2K or less, but TARGET_PAGE_SIZE is only | |
5323 | * 1K as an artefact of legacy v5 subpage support being present in the | |
5324 | * same QEMU executable. | |
5325 | */ | |
5326 | int maxidx = DIV_ROUND_UP(blocklen, TARGET_PAGE_SIZE); | |
5327 | void *hostaddr[maxidx]; | |
5328 | int try, i; | |
5329 | ||
5330 | for (try = 0; try < 2; try++) { | |
5331 | ||
5332 | for (i = 0; i < maxidx; i++) { | |
5333 | hostaddr[i] = tlb_vaddr_to_host(env, | |
5334 | vaddr + TARGET_PAGE_SIZE * i, | |
5335 | 1, cpu_mmu_index(env)); | |
5336 | if (!hostaddr[i]) { | |
5337 | break; | |
5338 | } | |
5339 | } | |
5340 | if (i == maxidx) { | |
5341 | /* If it's all in the TLB it's fair game for just writing to; | |
5342 | * we know we don't need to update dirty status, etc. | |
5343 | */ | |
5344 | for (i = 0; i < maxidx - 1; i++) { | |
5345 | memset(hostaddr[i], 0, TARGET_PAGE_SIZE); | |
5346 | } | |
5347 | memset(hostaddr[i], 0, blocklen - (i * TARGET_PAGE_SIZE)); | |
5348 | return; | |
5349 | } | |
5350 | /* OK, try a store and see if we can populate the tlb. This | |
5351 | * might cause an exception if the memory isn't writable, | |
5352 | * in which case we will longjmp out of here. We must for | |
5353 | * this purpose use the actual register value passed to us | |
5354 | * so that we get the fault address right. | |
5355 | */ | |
5356 | helper_ret_stb_mmu(env, vaddr_in, 0, cpu_mmu_index(env), GETRA()); | |
5357 | /* Now we can populate the other TLB entries, if any */ | |
5358 | for (i = 0; i < maxidx; i++) { | |
5359 | uint64_t va = vaddr + TARGET_PAGE_SIZE * i; | |
5360 | if (va != (vaddr_in & TARGET_PAGE_MASK)) { | |
5361 | helper_ret_stb_mmu(env, va, 0, cpu_mmu_index(env), GETRA()); | |
5362 | } | |
5363 | } | |
5364 | } | |
5365 | ||
5366 | /* Slow path (probably attempt to do this to an I/O device or | |
5367 | * similar, or clearing of a block of code we have translations | |
5368 | * cached for). Just do a series of byte writes as the architecture | |
5369 | * demands. It's not worth trying to use a cpu_physical_memory_map(), | |
5370 | * memset(), unmap() sequence here because: | |
5371 | * + we'd need to account for the blocksize being larger than a page | |
5372 | * + the direct-RAM access case is almost always going to be dealt | |
5373 | * with in the fastpath code above, so there's no speed benefit | |
5374 | * + we would have to deal with the map returning NULL because the | |
5375 | * bounce buffer was in use | |
5376 | */ | |
5377 | for (i = 0; i < blocklen; i++) { | |
5378 | helper_ret_stb_mmu(env, vaddr + i, 0, cpu_mmu_index(env), GETRA()); | |
5379 | } | |
5380 | } | |
5381 | #else | |
5382 | memset(g2h(vaddr), 0, blocklen); | |
5383 | #endif | |
5384 | } | |
5385 | ||
6ddbc6e4 PB |
5386 | /* Note that signed overflow is undefined in C. The following routines are |
5387 | careful to use unsigned types where modulo arithmetic is required. | |
5388 | Failure to do so _will_ break on newer gcc. */ | |
5389 | ||
5390 | /* Signed saturating arithmetic. */ | |
5391 | ||
1654b2d6 | 5392 | /* Perform 16-bit signed saturating addition. */ |
6ddbc6e4 PB |
5393 | static inline uint16_t add16_sat(uint16_t a, uint16_t b) |
5394 | { | |
5395 | uint16_t res; | |
5396 | ||
5397 | res = a + b; | |
5398 | if (((res ^ a) & 0x8000) && !((a ^ b) & 0x8000)) { | |
5399 | if (a & 0x8000) | |
5400 | res = 0x8000; | |
5401 | else | |
5402 | res = 0x7fff; | |
5403 | } | |
5404 | return res; | |
5405 | } | |
5406 | ||
1654b2d6 | 5407 | /* Perform 8-bit signed saturating addition. */ |
6ddbc6e4 PB |
5408 | static inline uint8_t add8_sat(uint8_t a, uint8_t b) |
5409 | { | |
5410 | uint8_t res; | |
5411 | ||
5412 | res = a + b; | |
5413 | if (((res ^ a) & 0x80) && !((a ^ b) & 0x80)) { | |
5414 | if (a & 0x80) | |
5415 | res = 0x80; | |
5416 | else | |
5417 | res = 0x7f; | |
5418 | } | |
5419 | return res; | |
5420 | } | |
5421 | ||
1654b2d6 | 5422 | /* Perform 16-bit signed saturating subtraction. */ |
6ddbc6e4 PB |
5423 | static inline uint16_t sub16_sat(uint16_t a, uint16_t b) |
5424 | { | |
5425 | uint16_t res; | |
5426 | ||
5427 | res = a - b; | |
5428 | if (((res ^ a) & 0x8000) && ((a ^ b) & 0x8000)) { | |
5429 | if (a & 0x8000) | |
5430 | res = 0x8000; | |
5431 | else | |
5432 | res = 0x7fff; | |
5433 | } | |
5434 | return res; | |
5435 | } | |
5436 | ||
1654b2d6 | 5437 | /* Perform 8-bit signed saturating subtraction. */ |
6ddbc6e4 PB |
5438 | static inline uint8_t sub8_sat(uint8_t a, uint8_t b) |
5439 | { | |
5440 | uint8_t res; | |
5441 | ||
5442 | res = a - b; | |
5443 | if (((res ^ a) & 0x80) && ((a ^ b) & 0x80)) { | |
5444 | if (a & 0x80) | |
5445 | res = 0x80; | |
5446 | else | |
5447 | res = 0x7f; | |
5448 | } | |
5449 | return res; | |
5450 | } | |
5451 | ||
5452 | #define ADD16(a, b, n) RESULT(add16_sat(a, b), n, 16); | |
5453 | #define SUB16(a, b, n) RESULT(sub16_sat(a, b), n, 16); | |
5454 | #define ADD8(a, b, n) RESULT(add8_sat(a, b), n, 8); | |
5455 | #define SUB8(a, b, n) RESULT(sub8_sat(a, b), n, 8); | |
5456 | #define PFX q | |
5457 | ||
5458 | #include "op_addsub.h" | |
5459 | ||
5460 | /* Unsigned saturating arithmetic. */ | |
460a09c1 | 5461 | static inline uint16_t add16_usat(uint16_t a, uint16_t b) |
6ddbc6e4 PB |
5462 | { |
5463 | uint16_t res; | |
5464 | res = a + b; | |
5465 | if (res < a) | |
5466 | res = 0xffff; | |
5467 | return res; | |
5468 | } | |
5469 | ||
460a09c1 | 5470 | static inline uint16_t sub16_usat(uint16_t a, uint16_t b) |
6ddbc6e4 | 5471 | { |
4c4fd3f8 | 5472 | if (a > b) |
6ddbc6e4 PB |
5473 | return a - b; |
5474 | else | |
5475 | return 0; | |
5476 | } | |
5477 | ||
5478 | static inline uint8_t add8_usat(uint8_t a, uint8_t b) | |
5479 | { | |
5480 | uint8_t res; | |
5481 | res = a + b; | |
5482 | if (res < a) | |
5483 | res = 0xff; | |
5484 | return res; | |
5485 | } | |
5486 | ||
5487 | static inline uint8_t sub8_usat(uint8_t a, uint8_t b) | |
5488 | { | |
4c4fd3f8 | 5489 | if (a > b) |
6ddbc6e4 PB |
5490 | return a - b; |
5491 | else | |
5492 | return 0; | |
5493 | } | |
5494 | ||
5495 | #define ADD16(a, b, n) RESULT(add16_usat(a, b), n, 16); | |
5496 | #define SUB16(a, b, n) RESULT(sub16_usat(a, b), n, 16); | |
5497 | #define ADD8(a, b, n) RESULT(add8_usat(a, b), n, 8); | |
5498 | #define SUB8(a, b, n) RESULT(sub8_usat(a, b), n, 8); | |
5499 | #define PFX uq | |
5500 | ||
5501 | #include "op_addsub.h" | |
5502 | ||
5503 | /* Signed modulo arithmetic. */ | |
5504 | #define SARITH16(a, b, n, op) do { \ | |
5505 | int32_t sum; \ | |
db6e2e65 | 5506 | sum = (int32_t)(int16_t)(a) op (int32_t)(int16_t)(b); \ |
6ddbc6e4 PB |
5507 | RESULT(sum, n, 16); \ |
5508 | if (sum >= 0) \ | |
5509 | ge |= 3 << (n * 2); \ | |
5510 | } while(0) | |
5511 | ||
5512 | #define SARITH8(a, b, n, op) do { \ | |
5513 | int32_t sum; \ | |
db6e2e65 | 5514 | sum = (int32_t)(int8_t)(a) op (int32_t)(int8_t)(b); \ |
6ddbc6e4 PB |
5515 | RESULT(sum, n, 8); \ |
5516 | if (sum >= 0) \ | |
5517 | ge |= 1 << n; \ | |
5518 | } while(0) | |
5519 | ||
5520 | ||
5521 | #define ADD16(a, b, n) SARITH16(a, b, n, +) | |
5522 | #define SUB16(a, b, n) SARITH16(a, b, n, -) | |
5523 | #define ADD8(a, b, n) SARITH8(a, b, n, +) | |
5524 | #define SUB8(a, b, n) SARITH8(a, b, n, -) | |
5525 | #define PFX s | |
5526 | #define ARITH_GE | |
5527 | ||
5528 | #include "op_addsub.h" | |
5529 | ||
5530 | /* Unsigned modulo arithmetic. */ | |
5531 | #define ADD16(a, b, n) do { \ | |
5532 | uint32_t sum; \ | |
5533 | sum = (uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b); \ | |
5534 | RESULT(sum, n, 16); \ | |
a87aa10b | 5535 | if ((sum >> 16) == 1) \ |
6ddbc6e4 PB |
5536 | ge |= 3 << (n * 2); \ |
5537 | } while(0) | |
5538 | ||
5539 | #define ADD8(a, b, n) do { \ | |
5540 | uint32_t sum; \ | |
5541 | sum = (uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b); \ | |
5542 | RESULT(sum, n, 8); \ | |
a87aa10b AZ |
5543 | if ((sum >> 8) == 1) \ |
5544 | ge |= 1 << n; \ | |
6ddbc6e4 PB |
5545 | } while(0) |
5546 | ||
5547 | #define SUB16(a, b, n) do { \ | |
5548 | uint32_t sum; \ | |
5549 | sum = (uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b); \ | |
5550 | RESULT(sum, n, 16); \ | |
5551 | if ((sum >> 16) == 0) \ | |
5552 | ge |= 3 << (n * 2); \ | |
5553 | } while(0) | |
5554 | ||
5555 | #define SUB8(a, b, n) do { \ | |
5556 | uint32_t sum; \ | |
5557 | sum = (uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b); \ | |
5558 | RESULT(sum, n, 8); \ | |
5559 | if ((sum >> 8) == 0) \ | |
a87aa10b | 5560 | ge |= 1 << n; \ |
6ddbc6e4 PB |
5561 | } while(0) |
5562 | ||
5563 | #define PFX u | |
5564 | #define ARITH_GE | |
5565 | ||
5566 | #include "op_addsub.h" | |
5567 | ||
5568 | /* Halved signed arithmetic. */ | |
5569 | #define ADD16(a, b, n) \ | |
5570 | RESULT(((int32_t)(int16_t)(a) + (int32_t)(int16_t)(b)) >> 1, n, 16) | |
5571 | #define SUB16(a, b, n) \ | |
5572 | RESULT(((int32_t)(int16_t)(a) - (int32_t)(int16_t)(b)) >> 1, n, 16) | |
5573 | #define ADD8(a, b, n) \ | |
5574 | RESULT(((int32_t)(int8_t)(a) + (int32_t)(int8_t)(b)) >> 1, n, 8) | |
5575 | #define SUB8(a, b, n) \ | |
5576 | RESULT(((int32_t)(int8_t)(a) - (int32_t)(int8_t)(b)) >> 1, n, 8) | |
5577 | #define PFX sh | |
5578 | ||
5579 | #include "op_addsub.h" | |
5580 | ||
5581 | /* Halved unsigned arithmetic. */ | |
5582 | #define ADD16(a, b, n) \ | |
5583 | RESULT(((uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b)) >> 1, n, 16) | |
5584 | #define SUB16(a, b, n) \ | |
5585 | RESULT(((uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b)) >> 1, n, 16) | |
5586 | #define ADD8(a, b, n) \ | |
5587 | RESULT(((uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b)) >> 1, n, 8) | |
5588 | #define SUB8(a, b, n) \ | |
5589 | RESULT(((uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b)) >> 1, n, 8) | |
5590 | #define PFX uh | |
5591 | ||
5592 | #include "op_addsub.h" | |
5593 | ||
5594 | static inline uint8_t do_usad(uint8_t a, uint8_t b) | |
5595 | { | |
5596 | if (a > b) | |
5597 | return a - b; | |
5598 | else | |
5599 | return b - a; | |
5600 | } | |
5601 | ||
5602 | /* Unsigned sum of absolute byte differences. */ | |
5603 | uint32_t HELPER(usad8)(uint32_t a, uint32_t b) | |
5604 | { | |
5605 | uint32_t sum; | |
5606 | sum = do_usad(a, b); | |
5607 | sum += do_usad(a >> 8, b >> 8); | |
5608 | sum += do_usad(a >> 16, b >>16); | |
5609 | sum += do_usad(a >> 24, b >> 24); | |
5610 | return sum; | |
5611 | } | |
5612 | ||
5613 | /* For ARMv6 SEL instruction. */ | |
5614 | uint32_t HELPER(sel_flags)(uint32_t flags, uint32_t a, uint32_t b) | |
5615 | { | |
5616 | uint32_t mask; | |
5617 | ||
5618 | mask = 0; | |
5619 | if (flags & 1) | |
5620 | mask |= 0xff; | |
5621 | if (flags & 2) | |
5622 | mask |= 0xff00; | |
5623 | if (flags & 4) | |
5624 | mask |= 0xff0000; | |
5625 | if (flags & 8) | |
5626 | mask |= 0xff000000; | |
5627 | return (a & mask) | (b & ~mask); | |
5628 | } | |
5629 | ||
b90372ad PM |
5630 | /* VFP support. We follow the convention used for VFP instructions: |
5631 | Single precision routines have a "s" suffix, double precision a | |
4373f3ce PB |
5632 | "d" suffix. */ |
5633 | ||
5634 | /* Convert host exception flags to vfp form. */ | |
5635 | static inline int vfp_exceptbits_from_host(int host_bits) | |
5636 | { | |
5637 | int target_bits = 0; | |
5638 | ||
5639 | if (host_bits & float_flag_invalid) | |
5640 | target_bits |= 1; | |
5641 | if (host_bits & float_flag_divbyzero) | |
5642 | target_bits |= 2; | |
5643 | if (host_bits & float_flag_overflow) | |
5644 | target_bits |= 4; | |
36802b6b | 5645 | if (host_bits & (float_flag_underflow | float_flag_output_denormal)) |
4373f3ce PB |
5646 | target_bits |= 8; |
5647 | if (host_bits & float_flag_inexact) | |
5648 | target_bits |= 0x10; | |
cecd8504 PM |
5649 | if (host_bits & float_flag_input_denormal) |
5650 | target_bits |= 0x80; | |
4373f3ce PB |
5651 | return target_bits; |
5652 | } | |
5653 | ||
0ecb72a5 | 5654 | uint32_t HELPER(vfp_get_fpscr)(CPUARMState *env) |
4373f3ce PB |
5655 | { |
5656 | int i; | |
5657 | uint32_t fpscr; | |
5658 | ||
5659 | fpscr = (env->vfp.xregs[ARM_VFP_FPSCR] & 0xffc8ffff) | |
5660 | | (env->vfp.vec_len << 16) | |
5661 | | (env->vfp.vec_stride << 20); | |
5662 | i = get_float_exception_flags(&env->vfp.fp_status); | |
3a492f3a | 5663 | i |= get_float_exception_flags(&env->vfp.standard_fp_status); |
4373f3ce PB |
5664 | fpscr |= vfp_exceptbits_from_host(i); |
5665 | return fpscr; | |
5666 | } | |
5667 | ||
0ecb72a5 | 5668 | uint32_t vfp_get_fpscr(CPUARMState *env) |
01653295 PM |
5669 | { |
5670 | return HELPER(vfp_get_fpscr)(env); | |
5671 | } | |
5672 | ||
4373f3ce PB |
5673 | /* Convert vfp exception flags to target form. */ |
5674 | static inline int vfp_exceptbits_to_host(int target_bits) | |
5675 | { | |
5676 | int host_bits = 0; | |
5677 | ||
5678 | if (target_bits & 1) | |
5679 | host_bits |= float_flag_invalid; | |
5680 | if (target_bits & 2) | |
5681 | host_bits |= float_flag_divbyzero; | |
5682 | if (target_bits & 4) | |
5683 | host_bits |= float_flag_overflow; | |
5684 | if (target_bits & 8) | |
5685 | host_bits |= float_flag_underflow; | |
5686 | if (target_bits & 0x10) | |
5687 | host_bits |= float_flag_inexact; | |
cecd8504 PM |
5688 | if (target_bits & 0x80) |
5689 | host_bits |= float_flag_input_denormal; | |
4373f3ce PB |
5690 | return host_bits; |
5691 | } | |
5692 | ||
0ecb72a5 | 5693 | void HELPER(vfp_set_fpscr)(CPUARMState *env, uint32_t val) |
4373f3ce PB |
5694 | { |
5695 | int i; | |
5696 | uint32_t changed; | |
5697 | ||
5698 | changed = env->vfp.xregs[ARM_VFP_FPSCR]; | |
5699 | env->vfp.xregs[ARM_VFP_FPSCR] = (val & 0xffc8ffff); | |
5700 | env->vfp.vec_len = (val >> 16) & 7; | |
5701 | env->vfp.vec_stride = (val >> 20) & 3; | |
5702 | ||
5703 | changed ^= val; | |
5704 | if (changed & (3 << 22)) { | |
5705 | i = (val >> 22) & 3; | |
5706 | switch (i) { | |
4d3da0f3 | 5707 | case FPROUNDING_TIEEVEN: |
4373f3ce PB |
5708 | i = float_round_nearest_even; |
5709 | break; | |
4d3da0f3 | 5710 | case FPROUNDING_POSINF: |
4373f3ce PB |
5711 | i = float_round_up; |
5712 | break; | |
4d3da0f3 | 5713 | case FPROUNDING_NEGINF: |
4373f3ce PB |
5714 | i = float_round_down; |
5715 | break; | |
4d3da0f3 | 5716 | case FPROUNDING_ZERO: |
4373f3ce PB |
5717 | i = float_round_to_zero; |
5718 | break; | |
5719 | } | |
5720 | set_float_rounding_mode(i, &env->vfp.fp_status); | |
5721 | } | |
cecd8504 | 5722 | if (changed & (1 << 24)) { |
fe76d976 | 5723 | set_flush_to_zero((val & (1 << 24)) != 0, &env->vfp.fp_status); |
cecd8504 PM |
5724 | set_flush_inputs_to_zero((val & (1 << 24)) != 0, &env->vfp.fp_status); |
5725 | } | |
5c7908ed PB |
5726 | if (changed & (1 << 25)) |
5727 | set_default_nan_mode((val & (1 << 25)) != 0, &env->vfp.fp_status); | |
4373f3ce | 5728 | |
b12c390b | 5729 | i = vfp_exceptbits_to_host(val); |
4373f3ce | 5730 | set_float_exception_flags(i, &env->vfp.fp_status); |
3a492f3a | 5731 | set_float_exception_flags(0, &env->vfp.standard_fp_status); |
4373f3ce PB |
5732 | } |
5733 | ||
0ecb72a5 | 5734 | void vfp_set_fpscr(CPUARMState *env, uint32_t val) |
01653295 PM |
5735 | { |
5736 | HELPER(vfp_set_fpscr)(env, val); | |
5737 | } | |
5738 | ||
4373f3ce PB |
5739 | #define VFP_HELPER(name, p) HELPER(glue(glue(vfp_,name),p)) |
5740 | ||
5741 | #define VFP_BINOP(name) \ | |
ae1857ec | 5742 | float32 VFP_HELPER(name, s)(float32 a, float32 b, void *fpstp) \ |
4373f3ce | 5743 | { \ |
ae1857ec PM |
5744 | float_status *fpst = fpstp; \ |
5745 | return float32_ ## name(a, b, fpst); \ | |
4373f3ce | 5746 | } \ |
ae1857ec | 5747 | float64 VFP_HELPER(name, d)(float64 a, float64 b, void *fpstp) \ |
4373f3ce | 5748 | { \ |
ae1857ec PM |
5749 | float_status *fpst = fpstp; \ |
5750 | return float64_ ## name(a, b, fpst); \ | |
4373f3ce PB |
5751 | } |
5752 | VFP_BINOP(add) | |
5753 | VFP_BINOP(sub) | |
5754 | VFP_BINOP(mul) | |
5755 | VFP_BINOP(div) | |
f71a2ae5 PM |
5756 | VFP_BINOP(min) |
5757 | VFP_BINOP(max) | |
5758 | VFP_BINOP(minnum) | |
5759 | VFP_BINOP(maxnum) | |
4373f3ce PB |
5760 | #undef VFP_BINOP |
5761 | ||
5762 | float32 VFP_HELPER(neg, s)(float32 a) | |
5763 | { | |
5764 | return float32_chs(a); | |
5765 | } | |
5766 | ||
5767 | float64 VFP_HELPER(neg, d)(float64 a) | |
5768 | { | |
66230e0d | 5769 | return float64_chs(a); |
4373f3ce PB |
5770 | } |
5771 | ||
5772 | float32 VFP_HELPER(abs, s)(float32 a) | |
5773 | { | |
5774 | return float32_abs(a); | |
5775 | } | |
5776 | ||
5777 | float64 VFP_HELPER(abs, d)(float64 a) | |
5778 | { | |
66230e0d | 5779 | return float64_abs(a); |
4373f3ce PB |
5780 | } |
5781 | ||
0ecb72a5 | 5782 | float32 VFP_HELPER(sqrt, s)(float32 a, CPUARMState *env) |
4373f3ce PB |
5783 | { |
5784 | return float32_sqrt(a, &env->vfp.fp_status); | |
5785 | } | |
5786 | ||
0ecb72a5 | 5787 | float64 VFP_HELPER(sqrt, d)(float64 a, CPUARMState *env) |
4373f3ce PB |
5788 | { |
5789 | return float64_sqrt(a, &env->vfp.fp_status); | |
5790 | } | |
5791 | ||
5792 | /* XXX: check quiet/signaling case */ | |
5793 | #define DO_VFP_cmp(p, type) \ | |
0ecb72a5 | 5794 | void VFP_HELPER(cmp, p)(type a, type b, CPUARMState *env) \ |
4373f3ce PB |
5795 | { \ |
5796 | uint32_t flags; \ | |
5797 | switch(type ## _compare_quiet(a, b, &env->vfp.fp_status)) { \ | |
5798 | case 0: flags = 0x6; break; \ | |
5799 | case -1: flags = 0x8; break; \ | |
5800 | case 1: flags = 0x2; break; \ | |
5801 | default: case 2: flags = 0x3; break; \ | |
5802 | } \ | |
5803 | env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \ | |
5804 | | (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \ | |
5805 | } \ | |
0ecb72a5 | 5806 | void VFP_HELPER(cmpe, p)(type a, type b, CPUARMState *env) \ |
4373f3ce PB |
5807 | { \ |
5808 | uint32_t flags; \ | |
5809 | switch(type ## _compare(a, b, &env->vfp.fp_status)) { \ | |
5810 | case 0: flags = 0x6; break; \ | |
5811 | case -1: flags = 0x8; break; \ | |
5812 | case 1: flags = 0x2; break; \ | |
5813 | default: case 2: flags = 0x3; break; \ | |
5814 | } \ | |
5815 | env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \ | |
5816 | | (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \ | |
5817 | } | |
5818 | DO_VFP_cmp(s, float32) | |
5819 | DO_VFP_cmp(d, float64) | |
5820 | #undef DO_VFP_cmp | |
5821 | ||
5500b06c | 5822 | /* Integer to float and float to integer conversions */ |
4373f3ce | 5823 | |
5500b06c PM |
5824 | #define CONV_ITOF(name, fsz, sign) \ |
5825 | float##fsz HELPER(name)(uint32_t x, void *fpstp) \ | |
5826 | { \ | |
5827 | float_status *fpst = fpstp; \ | |
85836979 | 5828 | return sign##int32_to_##float##fsz((sign##int32_t)x, fpst); \ |
4373f3ce PB |
5829 | } |
5830 | ||
5500b06c PM |
5831 | #define CONV_FTOI(name, fsz, sign, round) \ |
5832 | uint32_t HELPER(name)(float##fsz x, void *fpstp) \ | |
5833 | { \ | |
5834 | float_status *fpst = fpstp; \ | |
5835 | if (float##fsz##_is_any_nan(x)) { \ | |
5836 | float_raise(float_flag_invalid, fpst); \ | |
5837 | return 0; \ | |
5838 | } \ | |
5839 | return float##fsz##_to_##sign##int32##round(x, fpst); \ | |
4373f3ce PB |
5840 | } |
5841 | ||
5500b06c PM |
5842 | #define FLOAT_CONVS(name, p, fsz, sign) \ |
5843 | CONV_ITOF(vfp_##name##to##p, fsz, sign) \ | |
5844 | CONV_FTOI(vfp_to##name##p, fsz, sign, ) \ | |
5845 | CONV_FTOI(vfp_to##name##z##p, fsz, sign, _round_to_zero) | |
4373f3ce | 5846 | |
5500b06c PM |
5847 | FLOAT_CONVS(si, s, 32, ) |
5848 | FLOAT_CONVS(si, d, 64, ) | |
5849 | FLOAT_CONVS(ui, s, 32, u) | |
5850 | FLOAT_CONVS(ui, d, 64, u) | |
4373f3ce | 5851 | |
5500b06c PM |
5852 | #undef CONV_ITOF |
5853 | #undef CONV_FTOI | |
5854 | #undef FLOAT_CONVS | |
4373f3ce PB |
5855 | |
5856 | /* floating point conversion */ | |
0ecb72a5 | 5857 | float64 VFP_HELPER(fcvtd, s)(float32 x, CPUARMState *env) |
4373f3ce | 5858 | { |
2d627737 PM |
5859 | float64 r = float32_to_float64(x, &env->vfp.fp_status); |
5860 | /* ARM requires that S<->D conversion of any kind of NaN generates | |
5861 | * a quiet NaN by forcing the most significant frac bit to 1. | |
5862 | */ | |
5863 | return float64_maybe_silence_nan(r); | |
4373f3ce PB |
5864 | } |
5865 | ||
0ecb72a5 | 5866 | float32 VFP_HELPER(fcvts, d)(float64 x, CPUARMState *env) |
4373f3ce | 5867 | { |
2d627737 PM |
5868 | float32 r = float64_to_float32(x, &env->vfp.fp_status); |
5869 | /* ARM requires that S<->D conversion of any kind of NaN generates | |
5870 | * a quiet NaN by forcing the most significant frac bit to 1. | |
5871 | */ | |
5872 | return float32_maybe_silence_nan(r); | |
4373f3ce PB |
5873 | } |
5874 | ||
5875 | /* VFP3 fixed point conversion. */ | |
16d5b3ca | 5876 | #define VFP_CONV_FIX_FLOAT(name, p, fsz, isz, itype) \ |
8ed697e8 WN |
5877 | float##fsz HELPER(vfp_##name##to##p)(uint##isz##_t x, uint32_t shift, \ |
5878 | void *fpstp) \ | |
4373f3ce | 5879 | { \ |
5500b06c | 5880 | float_status *fpst = fpstp; \ |
622465e1 | 5881 | float##fsz tmp; \ |
8ed697e8 | 5882 | tmp = itype##_to_##float##fsz(x, fpst); \ |
5500b06c | 5883 | return float##fsz##_scalbn(tmp, -(int)shift, fpst); \ |
16d5b3ca WN |
5884 | } |
5885 | ||
abe66f70 PM |
5886 | /* Notice that we want only input-denormal exception flags from the |
5887 | * scalbn operation: the other possible flags (overflow+inexact if | |
5888 | * we overflow to infinity, output-denormal) aren't correct for the | |
5889 | * complete scale-and-convert operation. | |
5890 | */ | |
16d5b3ca WN |
5891 | #define VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, round) \ |
5892 | uint##isz##_t HELPER(vfp_to##name##p##round)(float##fsz x, \ | |
5893 | uint32_t shift, \ | |
5894 | void *fpstp) \ | |
4373f3ce | 5895 | { \ |
5500b06c | 5896 | float_status *fpst = fpstp; \ |
abe66f70 | 5897 | int old_exc_flags = get_float_exception_flags(fpst); \ |
622465e1 PM |
5898 | float##fsz tmp; \ |
5899 | if (float##fsz##_is_any_nan(x)) { \ | |
5500b06c | 5900 | float_raise(float_flag_invalid, fpst); \ |
622465e1 | 5901 | return 0; \ |
09d9487f | 5902 | } \ |
5500b06c | 5903 | tmp = float##fsz##_scalbn(x, shift, fpst); \ |
abe66f70 PM |
5904 | old_exc_flags |= get_float_exception_flags(fpst) \ |
5905 | & float_flag_input_denormal; \ | |
5906 | set_float_exception_flags(old_exc_flags, fpst); \ | |
16d5b3ca | 5907 | return float##fsz##_to_##itype##round(tmp, fpst); \ |
622465e1 PM |
5908 | } |
5909 | ||
16d5b3ca WN |
5910 | #define VFP_CONV_FIX(name, p, fsz, isz, itype) \ |
5911 | VFP_CONV_FIX_FLOAT(name, p, fsz, isz, itype) \ | |
3c6a074a WN |
5912 | VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, _round_to_zero) \ |
5913 | VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, ) | |
5914 | ||
5915 | #define VFP_CONV_FIX_A64(name, p, fsz, isz, itype) \ | |
5916 | VFP_CONV_FIX_FLOAT(name, p, fsz, isz, itype) \ | |
5917 | VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, ) | |
16d5b3ca | 5918 | |
8ed697e8 WN |
5919 | VFP_CONV_FIX(sh, d, 64, 64, int16) |
5920 | VFP_CONV_FIX(sl, d, 64, 64, int32) | |
3c6a074a | 5921 | VFP_CONV_FIX_A64(sq, d, 64, 64, int64) |
8ed697e8 WN |
5922 | VFP_CONV_FIX(uh, d, 64, 64, uint16) |
5923 | VFP_CONV_FIX(ul, d, 64, 64, uint32) | |
3c6a074a | 5924 | VFP_CONV_FIX_A64(uq, d, 64, 64, uint64) |
8ed697e8 WN |
5925 | VFP_CONV_FIX(sh, s, 32, 32, int16) |
5926 | VFP_CONV_FIX(sl, s, 32, 32, int32) | |
3c6a074a | 5927 | VFP_CONV_FIX_A64(sq, s, 32, 64, int64) |
8ed697e8 WN |
5928 | VFP_CONV_FIX(uh, s, 32, 32, uint16) |
5929 | VFP_CONV_FIX(ul, s, 32, 32, uint32) | |
3c6a074a | 5930 | VFP_CONV_FIX_A64(uq, s, 32, 64, uint64) |
4373f3ce | 5931 | #undef VFP_CONV_FIX |
16d5b3ca WN |
5932 | #undef VFP_CONV_FIX_FLOAT |
5933 | #undef VFP_CONV_FLOAT_FIX_ROUND | |
4373f3ce | 5934 | |
52a1f6a3 AG |
5935 | /* Set the current fp rounding mode and return the old one. |
5936 | * The argument is a softfloat float_round_ value. | |
5937 | */ | |
5938 | uint32_t HELPER(set_rmode)(uint32_t rmode, CPUARMState *env) | |
5939 | { | |
5940 | float_status *fp_status = &env->vfp.fp_status; | |
5941 | ||
5942 | uint32_t prev_rmode = get_float_rounding_mode(fp_status); | |
5943 | set_float_rounding_mode(rmode, fp_status); | |
5944 | ||
5945 | return prev_rmode; | |
5946 | } | |
5947 | ||
43630e58 WN |
5948 | /* Set the current fp rounding mode in the standard fp status and return |
5949 | * the old one. This is for NEON instructions that need to change the | |
5950 | * rounding mode but wish to use the standard FPSCR values for everything | |
5951 | * else. Always set the rounding mode back to the correct value after | |
5952 | * modifying it. | |
5953 | * The argument is a softfloat float_round_ value. | |
5954 | */ | |
5955 | uint32_t HELPER(set_neon_rmode)(uint32_t rmode, CPUARMState *env) | |
5956 | { | |
5957 | float_status *fp_status = &env->vfp.standard_fp_status; | |
5958 | ||
5959 | uint32_t prev_rmode = get_float_rounding_mode(fp_status); | |
5960 | set_float_rounding_mode(rmode, fp_status); | |
5961 | ||
5962 | return prev_rmode; | |
5963 | } | |
5964 | ||
60011498 | 5965 | /* Half precision conversions. */ |
0ecb72a5 | 5966 | static float32 do_fcvt_f16_to_f32(uint32_t a, CPUARMState *env, float_status *s) |
60011498 | 5967 | { |
60011498 | 5968 | int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0; |
fb91678d PM |
5969 | float32 r = float16_to_float32(make_float16(a), ieee, s); |
5970 | if (ieee) { | |
5971 | return float32_maybe_silence_nan(r); | |
5972 | } | |
5973 | return r; | |
60011498 PB |
5974 | } |
5975 | ||
0ecb72a5 | 5976 | static uint32_t do_fcvt_f32_to_f16(float32 a, CPUARMState *env, float_status *s) |
60011498 | 5977 | { |
60011498 | 5978 | int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0; |
fb91678d PM |
5979 | float16 r = float32_to_float16(a, ieee, s); |
5980 | if (ieee) { | |
5981 | r = float16_maybe_silence_nan(r); | |
5982 | } | |
5983 | return float16_val(r); | |
60011498 PB |
5984 | } |
5985 | ||
0ecb72a5 | 5986 | float32 HELPER(neon_fcvt_f16_to_f32)(uint32_t a, CPUARMState *env) |
2d981da7 PM |
5987 | { |
5988 | return do_fcvt_f16_to_f32(a, env, &env->vfp.standard_fp_status); | |
5989 | } | |
5990 | ||
0ecb72a5 | 5991 | uint32_t HELPER(neon_fcvt_f32_to_f16)(float32 a, CPUARMState *env) |
2d981da7 PM |
5992 | { |
5993 | return do_fcvt_f32_to_f16(a, env, &env->vfp.standard_fp_status); | |
5994 | } | |
5995 | ||
0ecb72a5 | 5996 | float32 HELPER(vfp_fcvt_f16_to_f32)(uint32_t a, CPUARMState *env) |
2d981da7 PM |
5997 | { |
5998 | return do_fcvt_f16_to_f32(a, env, &env->vfp.fp_status); | |
5999 | } | |
6000 | ||
0ecb72a5 | 6001 | uint32_t HELPER(vfp_fcvt_f32_to_f16)(float32 a, CPUARMState *env) |
2d981da7 PM |
6002 | { |
6003 | return do_fcvt_f32_to_f16(a, env, &env->vfp.fp_status); | |
6004 | } | |
6005 | ||
8900aad2 PM |
6006 | float64 HELPER(vfp_fcvt_f16_to_f64)(uint32_t a, CPUARMState *env) |
6007 | { | |
6008 | int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0; | |
6009 | float64 r = float16_to_float64(make_float16(a), ieee, &env->vfp.fp_status); | |
6010 | if (ieee) { | |
6011 | return float64_maybe_silence_nan(r); | |
6012 | } | |
6013 | return r; | |
6014 | } | |
6015 | ||
6016 | uint32_t HELPER(vfp_fcvt_f64_to_f16)(float64 a, CPUARMState *env) | |
6017 | { | |
6018 | int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0; | |
6019 | float16 r = float64_to_float16(a, ieee, &env->vfp.fp_status); | |
6020 | if (ieee) { | |
6021 | r = float16_maybe_silence_nan(r); | |
6022 | } | |
6023 | return float16_val(r); | |
6024 | } | |
6025 | ||
dda3ec49 | 6026 | #define float32_two make_float32(0x40000000) |
6aae3df1 PM |
6027 | #define float32_three make_float32(0x40400000) |
6028 | #define float32_one_point_five make_float32(0x3fc00000) | |
dda3ec49 | 6029 | |
0ecb72a5 | 6030 | float32 HELPER(recps_f32)(float32 a, float32 b, CPUARMState *env) |
4373f3ce | 6031 | { |
dda3ec49 PM |
6032 | float_status *s = &env->vfp.standard_fp_status; |
6033 | if ((float32_is_infinity(a) && float32_is_zero_or_denormal(b)) || | |
6034 | (float32_is_infinity(b) && float32_is_zero_or_denormal(a))) { | |
43fe9bdb PM |
6035 | if (!(float32_is_zero(a) || float32_is_zero(b))) { |
6036 | float_raise(float_flag_input_denormal, s); | |
6037 | } | |
dda3ec49 PM |
6038 | return float32_two; |
6039 | } | |
6040 | return float32_sub(float32_two, float32_mul(a, b, s), s); | |
4373f3ce PB |
6041 | } |
6042 | ||
0ecb72a5 | 6043 | float32 HELPER(rsqrts_f32)(float32 a, float32 b, CPUARMState *env) |
4373f3ce | 6044 | { |
71826966 | 6045 | float_status *s = &env->vfp.standard_fp_status; |
9ea62f57 PM |
6046 | float32 product; |
6047 | if ((float32_is_infinity(a) && float32_is_zero_or_denormal(b)) || | |
6048 | (float32_is_infinity(b) && float32_is_zero_or_denormal(a))) { | |
43fe9bdb PM |
6049 | if (!(float32_is_zero(a) || float32_is_zero(b))) { |
6050 | float_raise(float_flag_input_denormal, s); | |
6051 | } | |
6aae3df1 | 6052 | return float32_one_point_five; |
9ea62f57 | 6053 | } |
6aae3df1 PM |
6054 | product = float32_mul(a, b, s); |
6055 | return float32_div(float32_sub(float32_three, product, s), float32_two, s); | |
4373f3ce PB |
6056 | } |
6057 | ||
8f8e3aa4 PB |
6058 | /* NEON helpers. */ |
6059 | ||
56bf4fe2 CL |
6060 | /* Constants 256 and 512 are used in some helpers; we avoid relying on |
6061 | * int->float conversions at run-time. */ | |
6062 | #define float64_256 make_float64(0x4070000000000000LL) | |
6063 | #define float64_512 make_float64(0x4080000000000000LL) | |
b6d4443a AB |
6064 | #define float32_maxnorm make_float32(0x7f7fffff) |
6065 | #define float64_maxnorm make_float64(0x7fefffffffffffffLL) | |
56bf4fe2 | 6066 | |
b6d4443a AB |
6067 | /* Reciprocal functions |
6068 | * | |
6069 | * The algorithm that must be used to calculate the estimate | |
6070 | * is specified by the ARM ARM, see FPRecipEstimate() | |
fe0e4872 | 6071 | */ |
b6d4443a AB |
6072 | |
6073 | static float64 recip_estimate(float64 a, float_status *real_fp_status) | |
fe0e4872 | 6074 | { |
1146a817 PM |
6075 | /* These calculations mustn't set any fp exception flags, |
6076 | * so we use a local copy of the fp_status. | |
6077 | */ | |
b6d4443a | 6078 | float_status dummy_status = *real_fp_status; |
1146a817 | 6079 | float_status *s = &dummy_status; |
fe0e4872 CL |
6080 | /* q = (int)(a * 512.0) */ |
6081 | float64 q = float64_mul(float64_512, a, s); | |
6082 | int64_t q_int = float64_to_int64_round_to_zero(q, s); | |
6083 | ||
6084 | /* r = 1.0 / (((double)q + 0.5) / 512.0) */ | |
6085 | q = int64_to_float64(q_int, s); | |
6086 | q = float64_add(q, float64_half, s); | |
6087 | q = float64_div(q, float64_512, s); | |
6088 | q = float64_div(float64_one, q, s); | |
6089 | ||
6090 | /* s = (int)(256.0 * r + 0.5) */ | |
6091 | q = float64_mul(q, float64_256, s); | |
6092 | q = float64_add(q, float64_half, s); | |
6093 | q_int = float64_to_int64_round_to_zero(q, s); | |
6094 | ||
6095 | /* return (double)s / 256.0 */ | |
6096 | return float64_div(int64_to_float64(q_int, s), float64_256, s); | |
6097 | } | |
6098 | ||
b6d4443a AB |
6099 | /* Common wrapper to call recip_estimate */ |
6100 | static float64 call_recip_estimate(float64 num, int off, float_status *fpst) | |
4373f3ce | 6101 | { |
b6d4443a AB |
6102 | uint64_t val64 = float64_val(num); |
6103 | uint64_t frac = extract64(val64, 0, 52); | |
6104 | int64_t exp = extract64(val64, 52, 11); | |
6105 | uint64_t sbit; | |
6106 | float64 scaled, estimate; | |
fe0e4872 | 6107 | |
b6d4443a AB |
6108 | /* Generate the scaled number for the estimate function */ |
6109 | if (exp == 0) { | |
6110 | if (extract64(frac, 51, 1) == 0) { | |
6111 | exp = -1; | |
6112 | frac = extract64(frac, 0, 50) << 2; | |
6113 | } else { | |
6114 | frac = extract64(frac, 0, 51) << 1; | |
6115 | } | |
6116 | } | |
fe0e4872 | 6117 | |
b6d4443a AB |
6118 | /* scaled = '0' : '01111111110' : fraction<51:44> : Zeros(44); */ |
6119 | scaled = make_float64((0x3feULL << 52) | |
6120 | | extract64(frac, 44, 8) << 44); | |
6121 | ||
6122 | estimate = recip_estimate(scaled, fpst); | |
6123 | ||
6124 | /* Build new result */ | |
6125 | val64 = float64_val(estimate); | |
6126 | sbit = 0x8000000000000000ULL & val64; | |
6127 | exp = off - exp; | |
6128 | frac = extract64(val64, 0, 52); | |
6129 | ||
6130 | if (exp == 0) { | |
6131 | frac = 1ULL << 51 | extract64(frac, 1, 51); | |
6132 | } else if (exp == -1) { | |
6133 | frac = 1ULL << 50 | extract64(frac, 2, 50); | |
6134 | exp = 0; | |
6135 | } | |
6136 | ||
6137 | return make_float64(sbit | (exp << 52) | frac); | |
6138 | } | |
6139 | ||
6140 | static bool round_to_inf(float_status *fpst, bool sign_bit) | |
6141 | { | |
6142 | switch (fpst->float_rounding_mode) { | |
6143 | case float_round_nearest_even: /* Round to Nearest */ | |
6144 | return true; | |
6145 | case float_round_up: /* Round to +Inf */ | |
6146 | return !sign_bit; | |
6147 | case float_round_down: /* Round to -Inf */ | |
6148 | return sign_bit; | |
6149 | case float_round_to_zero: /* Round to Zero */ | |
6150 | return false; | |
6151 | } | |
6152 | ||
6153 | g_assert_not_reached(); | |
6154 | } | |
6155 | ||
6156 | float32 HELPER(recpe_f32)(float32 input, void *fpstp) | |
6157 | { | |
6158 | float_status *fpst = fpstp; | |
6159 | float32 f32 = float32_squash_input_denormal(input, fpst); | |
6160 | uint32_t f32_val = float32_val(f32); | |
6161 | uint32_t f32_sbit = 0x80000000ULL & f32_val; | |
6162 | int32_t f32_exp = extract32(f32_val, 23, 8); | |
6163 | uint32_t f32_frac = extract32(f32_val, 0, 23); | |
6164 | float64 f64, r64; | |
6165 | uint64_t r64_val; | |
6166 | int64_t r64_exp; | |
6167 | uint64_t r64_frac; | |
6168 | ||
6169 | if (float32_is_any_nan(f32)) { | |
6170 | float32 nan = f32; | |
6171 | if (float32_is_signaling_nan(f32)) { | |
6172 | float_raise(float_flag_invalid, fpst); | |
6173 | nan = float32_maybe_silence_nan(f32); | |
fe0e4872 | 6174 | } |
b6d4443a AB |
6175 | if (fpst->default_nan_mode) { |
6176 | nan = float32_default_nan; | |
43fe9bdb | 6177 | } |
b6d4443a AB |
6178 | return nan; |
6179 | } else if (float32_is_infinity(f32)) { | |
6180 | return float32_set_sign(float32_zero, float32_is_neg(f32)); | |
6181 | } else if (float32_is_zero(f32)) { | |
6182 | float_raise(float_flag_divbyzero, fpst); | |
6183 | return float32_set_sign(float32_infinity, float32_is_neg(f32)); | |
6184 | } else if ((f32_val & ~(1ULL << 31)) < (1ULL << 21)) { | |
6185 | /* Abs(value) < 2.0^-128 */ | |
6186 | float_raise(float_flag_overflow | float_flag_inexact, fpst); | |
6187 | if (round_to_inf(fpst, f32_sbit)) { | |
6188 | return float32_set_sign(float32_infinity, float32_is_neg(f32)); | |
6189 | } else { | |
6190 | return float32_set_sign(float32_maxnorm, float32_is_neg(f32)); | |
6191 | } | |
6192 | } else if (f32_exp >= 253 && fpst->flush_to_zero) { | |
6193 | float_raise(float_flag_underflow, fpst); | |
6194 | return float32_set_sign(float32_zero, float32_is_neg(f32)); | |
fe0e4872 CL |
6195 | } |
6196 | ||
fe0e4872 | 6197 | |
b6d4443a AB |
6198 | f64 = make_float64(((int64_t)(f32_exp) << 52) | (int64_t)(f32_frac) << 29); |
6199 | r64 = call_recip_estimate(f64, 253, fpst); | |
6200 | r64_val = float64_val(r64); | |
6201 | r64_exp = extract64(r64_val, 52, 11); | |
6202 | r64_frac = extract64(r64_val, 0, 52); | |
6203 | ||
6204 | /* result = sign : result_exp<7:0> : fraction<51:29>; */ | |
6205 | return make_float32(f32_sbit | | |
6206 | (r64_exp & 0xff) << 23 | | |
6207 | extract64(r64_frac, 29, 24)); | |
6208 | } | |
6209 | ||
6210 | float64 HELPER(recpe_f64)(float64 input, void *fpstp) | |
6211 | { | |
6212 | float_status *fpst = fpstp; | |
6213 | float64 f64 = float64_squash_input_denormal(input, fpst); | |
6214 | uint64_t f64_val = float64_val(f64); | |
6215 | uint64_t f64_sbit = 0x8000000000000000ULL & f64_val; | |
6216 | int64_t f64_exp = extract64(f64_val, 52, 11); | |
6217 | float64 r64; | |
6218 | uint64_t r64_val; | |
6219 | int64_t r64_exp; | |
6220 | uint64_t r64_frac; | |
6221 | ||
6222 | /* Deal with any special cases */ | |
6223 | if (float64_is_any_nan(f64)) { | |
6224 | float64 nan = f64; | |
6225 | if (float64_is_signaling_nan(f64)) { | |
6226 | float_raise(float_flag_invalid, fpst); | |
6227 | nan = float64_maybe_silence_nan(f64); | |
6228 | } | |
6229 | if (fpst->default_nan_mode) { | |
6230 | nan = float64_default_nan; | |
6231 | } | |
6232 | return nan; | |
6233 | } else if (float64_is_infinity(f64)) { | |
6234 | return float64_set_sign(float64_zero, float64_is_neg(f64)); | |
6235 | } else if (float64_is_zero(f64)) { | |
6236 | float_raise(float_flag_divbyzero, fpst); | |
6237 | return float64_set_sign(float64_infinity, float64_is_neg(f64)); | |
6238 | } else if ((f64_val & ~(1ULL << 63)) < (1ULL << 50)) { | |
6239 | /* Abs(value) < 2.0^-1024 */ | |
6240 | float_raise(float_flag_overflow | float_flag_inexact, fpst); | |
6241 | if (round_to_inf(fpst, f64_sbit)) { | |
6242 | return float64_set_sign(float64_infinity, float64_is_neg(f64)); | |
6243 | } else { | |
6244 | return float64_set_sign(float64_maxnorm, float64_is_neg(f64)); | |
6245 | } | |
6246 | } else if (f64_exp >= 1023 && fpst->flush_to_zero) { | |
6247 | float_raise(float_flag_underflow, fpst); | |
6248 | return float64_set_sign(float64_zero, float64_is_neg(f64)); | |
6249 | } | |
fe0e4872 | 6250 | |
b6d4443a AB |
6251 | r64 = call_recip_estimate(f64, 2045, fpst); |
6252 | r64_val = float64_val(r64); | |
6253 | r64_exp = extract64(r64_val, 52, 11); | |
6254 | r64_frac = extract64(r64_val, 0, 52); | |
fe0e4872 | 6255 | |
b6d4443a AB |
6256 | /* result = sign : result_exp<10:0> : fraction<51:0> */ |
6257 | return make_float64(f64_sbit | | |
6258 | ((r64_exp & 0x7ff) << 52) | | |
6259 | r64_frac); | |
4373f3ce PB |
6260 | } |
6261 | ||
e07be5d2 CL |
6262 | /* The algorithm that must be used to calculate the estimate |
6263 | * is specified by the ARM ARM. | |
6264 | */ | |
c2fb418e | 6265 | static float64 recip_sqrt_estimate(float64 a, float_status *real_fp_status) |
e07be5d2 | 6266 | { |
1146a817 PM |
6267 | /* These calculations mustn't set any fp exception flags, |
6268 | * so we use a local copy of the fp_status. | |
6269 | */ | |
c2fb418e | 6270 | float_status dummy_status = *real_fp_status; |
1146a817 | 6271 | float_status *s = &dummy_status; |
e07be5d2 CL |
6272 | float64 q; |
6273 | int64_t q_int; | |
6274 | ||
6275 | if (float64_lt(a, float64_half, s)) { | |
6276 | /* range 0.25 <= a < 0.5 */ | |
6277 | ||
6278 | /* a in units of 1/512 rounded down */ | |
6279 | /* q0 = (int)(a * 512.0); */ | |
6280 | q = float64_mul(float64_512, a, s); | |
6281 | q_int = float64_to_int64_round_to_zero(q, s); | |
6282 | ||
6283 | /* reciprocal root r */ | |
6284 | /* r = 1.0 / sqrt(((double)q0 + 0.5) / 512.0); */ | |
6285 | q = int64_to_float64(q_int, s); | |
6286 | q = float64_add(q, float64_half, s); | |
6287 | q = float64_div(q, float64_512, s); | |
6288 | q = float64_sqrt(q, s); | |
6289 | q = float64_div(float64_one, q, s); | |
6290 | } else { | |
6291 | /* range 0.5 <= a < 1.0 */ | |
6292 | ||
6293 | /* a in units of 1/256 rounded down */ | |
6294 | /* q1 = (int)(a * 256.0); */ | |
6295 | q = float64_mul(float64_256, a, s); | |
6296 | int64_t q_int = float64_to_int64_round_to_zero(q, s); | |
6297 | ||
6298 | /* reciprocal root r */ | |
6299 | /* r = 1.0 /sqrt(((double)q1 + 0.5) / 256); */ | |
6300 | q = int64_to_float64(q_int, s); | |
6301 | q = float64_add(q, float64_half, s); | |
6302 | q = float64_div(q, float64_256, s); | |
6303 | q = float64_sqrt(q, s); | |
6304 | q = float64_div(float64_one, q, s); | |
6305 | } | |
6306 | /* r in units of 1/256 rounded to nearest */ | |
6307 | /* s = (int)(256.0 * r + 0.5); */ | |
6308 | ||
6309 | q = float64_mul(q, float64_256,s ); | |
6310 | q = float64_add(q, float64_half, s); | |
6311 | q_int = float64_to_int64_round_to_zero(q, s); | |
6312 | ||
6313 | /* return (double)s / 256.0;*/ | |
6314 | return float64_div(int64_to_float64(q_int, s), float64_256, s); | |
6315 | } | |
6316 | ||
c2fb418e | 6317 | float32 HELPER(rsqrte_f32)(float32 input, void *fpstp) |
4373f3ce | 6318 | { |
c2fb418e AB |
6319 | float_status *s = fpstp; |
6320 | float32 f32 = float32_squash_input_denormal(input, s); | |
6321 | uint32_t val = float32_val(f32); | |
6322 | uint32_t f32_sbit = 0x80000000 & val; | |
6323 | int32_t f32_exp = extract32(val, 23, 8); | |
6324 | uint32_t f32_frac = extract32(val, 0, 23); | |
6325 | uint64_t f64_frac; | |
6326 | uint64_t val64; | |
e07be5d2 CL |
6327 | int result_exp; |
6328 | float64 f64; | |
e07be5d2 | 6329 | |
c2fb418e AB |
6330 | if (float32_is_any_nan(f32)) { |
6331 | float32 nan = f32; | |
6332 | if (float32_is_signaling_nan(f32)) { | |
e07be5d2 | 6333 | float_raise(float_flag_invalid, s); |
c2fb418e | 6334 | nan = float32_maybe_silence_nan(f32); |
e07be5d2 | 6335 | } |
c2fb418e AB |
6336 | if (s->default_nan_mode) { |
6337 | nan = float32_default_nan; | |
43fe9bdb | 6338 | } |
c2fb418e AB |
6339 | return nan; |
6340 | } else if (float32_is_zero(f32)) { | |
e07be5d2 | 6341 | float_raise(float_flag_divbyzero, s); |
c2fb418e AB |
6342 | return float32_set_sign(float32_infinity, float32_is_neg(f32)); |
6343 | } else if (float32_is_neg(f32)) { | |
e07be5d2 CL |
6344 | float_raise(float_flag_invalid, s); |
6345 | return float32_default_nan; | |
c2fb418e | 6346 | } else if (float32_is_infinity(f32)) { |
e07be5d2 CL |
6347 | return float32_zero; |
6348 | } | |
6349 | ||
c2fb418e | 6350 | /* Scale and normalize to a double-precision value between 0.25 and 1.0, |
e07be5d2 | 6351 | * preserving the parity of the exponent. */ |
c2fb418e AB |
6352 | |
6353 | f64_frac = ((uint64_t) f32_frac) << 29; | |
6354 | if (f32_exp == 0) { | |
6355 | while (extract64(f64_frac, 51, 1) == 0) { | |
6356 | f64_frac = f64_frac << 1; | |
6357 | f32_exp = f32_exp-1; | |
6358 | } | |
6359 | f64_frac = extract64(f64_frac, 0, 51) << 1; | |
6360 | } | |
6361 | ||
6362 | if (extract64(f32_exp, 0, 1) == 0) { | |
6363 | f64 = make_float64(((uint64_t) f32_sbit) << 32 | |
e07be5d2 | 6364 | | (0x3feULL << 52) |
c2fb418e | 6365 | | f64_frac); |
e07be5d2 | 6366 | } else { |
c2fb418e | 6367 | f64 = make_float64(((uint64_t) f32_sbit) << 32 |
e07be5d2 | 6368 | | (0x3fdULL << 52) |
c2fb418e | 6369 | | f64_frac); |
e07be5d2 CL |
6370 | } |
6371 | ||
c2fb418e | 6372 | result_exp = (380 - f32_exp) / 2; |
e07be5d2 | 6373 | |
c2fb418e | 6374 | f64 = recip_sqrt_estimate(f64, s); |
e07be5d2 CL |
6375 | |
6376 | val64 = float64_val(f64); | |
6377 | ||
26cc6abf | 6378 | val = ((result_exp & 0xff) << 23) |
e07be5d2 CL |
6379 | | ((val64 >> 29) & 0x7fffff); |
6380 | return make_float32(val); | |
4373f3ce PB |
6381 | } |
6382 | ||
c2fb418e AB |
6383 | float64 HELPER(rsqrte_f64)(float64 input, void *fpstp) |
6384 | { | |
6385 | float_status *s = fpstp; | |
6386 | float64 f64 = float64_squash_input_denormal(input, s); | |
6387 | uint64_t val = float64_val(f64); | |
6388 | uint64_t f64_sbit = 0x8000000000000000ULL & val; | |
6389 | int64_t f64_exp = extract64(val, 52, 11); | |
6390 | uint64_t f64_frac = extract64(val, 0, 52); | |
6391 | int64_t result_exp; | |
6392 | uint64_t result_frac; | |
6393 | ||
6394 | if (float64_is_any_nan(f64)) { | |
6395 | float64 nan = f64; | |
6396 | if (float64_is_signaling_nan(f64)) { | |
6397 | float_raise(float_flag_invalid, s); | |
6398 | nan = float64_maybe_silence_nan(f64); | |
6399 | } | |
6400 | if (s->default_nan_mode) { | |
6401 | nan = float64_default_nan; | |
6402 | } | |
6403 | return nan; | |
6404 | } else if (float64_is_zero(f64)) { | |
6405 | float_raise(float_flag_divbyzero, s); | |
6406 | return float64_set_sign(float64_infinity, float64_is_neg(f64)); | |
6407 | } else if (float64_is_neg(f64)) { | |
6408 | float_raise(float_flag_invalid, s); | |
6409 | return float64_default_nan; | |
6410 | } else if (float64_is_infinity(f64)) { | |
6411 | return float64_zero; | |
6412 | } | |
6413 | ||
6414 | /* Scale and normalize to a double-precision value between 0.25 and 1.0, | |
6415 | * preserving the parity of the exponent. */ | |
6416 | ||
6417 | if (f64_exp == 0) { | |
6418 | while (extract64(f64_frac, 51, 1) == 0) { | |
6419 | f64_frac = f64_frac << 1; | |
6420 | f64_exp = f64_exp - 1; | |
6421 | } | |
6422 | f64_frac = extract64(f64_frac, 0, 51) << 1; | |
6423 | } | |
6424 | ||
6425 | if (extract64(f64_exp, 0, 1) == 0) { | |
6426 | f64 = make_float64(f64_sbit | |
6427 | | (0x3feULL << 52) | |
6428 | | f64_frac); | |
6429 | } else { | |
6430 | f64 = make_float64(f64_sbit | |
6431 | | (0x3fdULL << 52) | |
6432 | | f64_frac); | |
6433 | } | |
6434 | ||
6435 | result_exp = (3068 - f64_exp) / 2; | |
6436 | ||
6437 | f64 = recip_sqrt_estimate(f64, s); | |
6438 | ||
6439 | result_frac = extract64(float64_val(f64), 0, 52); | |
6440 | ||
6441 | return make_float64(f64_sbit | | |
6442 | ((result_exp & 0x7ff) << 52) | | |
6443 | result_frac); | |
6444 | } | |
6445 | ||
b6d4443a | 6446 | uint32_t HELPER(recpe_u32)(uint32_t a, void *fpstp) |
4373f3ce | 6447 | { |
b6d4443a | 6448 | float_status *s = fpstp; |
fe0e4872 CL |
6449 | float64 f64; |
6450 | ||
6451 | if ((a & 0x80000000) == 0) { | |
6452 | return 0xffffffff; | |
6453 | } | |
6454 | ||
6455 | f64 = make_float64((0x3feULL << 52) | |
6456 | | ((int64_t)(a & 0x7fffffff) << 21)); | |
6457 | ||
b6d4443a | 6458 | f64 = recip_estimate(f64, s); |
fe0e4872 CL |
6459 | |
6460 | return 0x80000000 | ((float64_val(f64) >> 21) & 0x7fffffff); | |
4373f3ce PB |
6461 | } |
6462 | ||
c2fb418e | 6463 | uint32_t HELPER(rsqrte_u32)(uint32_t a, void *fpstp) |
4373f3ce | 6464 | { |
c2fb418e | 6465 | float_status *fpst = fpstp; |
e07be5d2 CL |
6466 | float64 f64; |
6467 | ||
6468 | if ((a & 0xc0000000) == 0) { | |
6469 | return 0xffffffff; | |
6470 | } | |
6471 | ||
6472 | if (a & 0x80000000) { | |
6473 | f64 = make_float64((0x3feULL << 52) | |
6474 | | ((uint64_t)(a & 0x7fffffff) << 21)); | |
6475 | } else { /* bits 31-30 == '01' */ | |
6476 | f64 = make_float64((0x3fdULL << 52) | |
6477 | | ((uint64_t)(a & 0x3fffffff) << 22)); | |
6478 | } | |
6479 | ||
c2fb418e | 6480 | f64 = recip_sqrt_estimate(f64, fpst); |
e07be5d2 CL |
6481 | |
6482 | return 0x80000000 | ((float64_val(f64) >> 21) & 0x7fffffff); | |
4373f3ce | 6483 | } |
fe1479c3 | 6484 | |
da97f52c PM |
6485 | /* VFPv4 fused multiply-accumulate */ |
6486 | float32 VFP_HELPER(muladd, s)(float32 a, float32 b, float32 c, void *fpstp) | |
6487 | { | |
6488 | float_status *fpst = fpstp; | |
6489 | return float32_muladd(a, b, c, 0, fpst); | |
6490 | } | |
6491 | ||
6492 | float64 VFP_HELPER(muladd, d)(float64 a, float64 b, float64 c, void *fpstp) | |
6493 | { | |
6494 | float_status *fpst = fpstp; | |
6495 | return float64_muladd(a, b, c, 0, fpst); | |
6496 | } | |
d9b0848d PM |
6497 | |
6498 | /* ARMv8 round to integral */ | |
6499 | float32 HELPER(rints_exact)(float32 x, void *fp_status) | |
6500 | { | |
6501 | return float32_round_to_int(x, fp_status); | |
6502 | } | |
6503 | ||
6504 | float64 HELPER(rintd_exact)(float64 x, void *fp_status) | |
6505 | { | |
6506 | return float64_round_to_int(x, fp_status); | |
6507 | } | |
6508 | ||
6509 | float32 HELPER(rints)(float32 x, void *fp_status) | |
6510 | { | |
6511 | int old_flags = get_float_exception_flags(fp_status), new_flags; | |
6512 | float32 ret; | |
6513 | ||
6514 | ret = float32_round_to_int(x, fp_status); | |
6515 | ||
6516 | /* Suppress any inexact exceptions the conversion produced */ | |
6517 | if (!(old_flags & float_flag_inexact)) { | |
6518 | new_flags = get_float_exception_flags(fp_status); | |
6519 | set_float_exception_flags(new_flags & ~float_flag_inexact, fp_status); | |
6520 | } | |
6521 | ||
6522 | return ret; | |
6523 | } | |
6524 | ||
6525 | float64 HELPER(rintd)(float64 x, void *fp_status) | |
6526 | { | |
6527 | int old_flags = get_float_exception_flags(fp_status), new_flags; | |
6528 | float64 ret; | |
6529 | ||
6530 | ret = float64_round_to_int(x, fp_status); | |
6531 | ||
6532 | new_flags = get_float_exception_flags(fp_status); | |
6533 | ||
6534 | /* Suppress any inexact exceptions the conversion produced */ | |
6535 | if (!(old_flags & float_flag_inexact)) { | |
6536 | new_flags = get_float_exception_flags(fp_status); | |
6537 | set_float_exception_flags(new_flags & ~float_flag_inexact, fp_status); | |
6538 | } | |
6539 | ||
6540 | return ret; | |
6541 | } | |
9972da66 WN |
6542 | |
6543 | /* Convert ARM rounding mode to softfloat */ | |
6544 | int arm_rmode_to_sf(int rmode) | |
6545 | { | |
6546 | switch (rmode) { | |
6547 | case FPROUNDING_TIEAWAY: | |
6548 | rmode = float_round_ties_away; | |
6549 | break; | |
6550 | case FPROUNDING_ODD: | |
6551 | /* FIXME: add support for TIEAWAY and ODD */ | |
6552 | qemu_log_mask(LOG_UNIMP, "arm: unimplemented rounding mode: %d\n", | |
6553 | rmode); | |
6554 | case FPROUNDING_TIEEVEN: | |
6555 | default: | |
6556 | rmode = float_round_nearest_even; | |
6557 | break; | |
6558 | case FPROUNDING_POSINF: | |
6559 | rmode = float_round_up; | |
6560 | break; | |
6561 | case FPROUNDING_NEGINF: | |
6562 | rmode = float_round_down; | |
6563 | break; | |
6564 | case FPROUNDING_ZERO: | |
6565 | rmode = float_round_to_zero; | |
6566 | break; | |
6567 | } | |
6568 | return rmode; | |
6569 | } | |
eb0ecd5a | 6570 | |
aa633469 PM |
6571 | /* CRC helpers. |
6572 | * The upper bytes of val (above the number specified by 'bytes') must have | |
6573 | * been zeroed out by the caller. | |
6574 | */ | |
eb0ecd5a WN |
6575 | uint32_t HELPER(crc32)(uint32_t acc, uint32_t val, uint32_t bytes) |
6576 | { | |
6577 | uint8_t buf[4]; | |
6578 | ||
aa633469 | 6579 | stl_le_p(buf, val); |
eb0ecd5a WN |
6580 | |
6581 | /* zlib crc32 converts the accumulator and output to one's complement. */ | |
6582 | return crc32(acc ^ 0xffffffff, buf, bytes) ^ 0xffffffff; | |
6583 | } | |
6584 | ||
6585 | uint32_t HELPER(crc32c)(uint32_t acc, uint32_t val, uint32_t bytes) | |
6586 | { | |
6587 | uint8_t buf[4]; | |
6588 | ||
aa633469 | 6589 | stl_le_p(buf, val); |
eb0ecd5a WN |
6590 | |
6591 | /* Linux crc32c converts the output to one's complement. */ | |
6592 | return crc32c(acc, buf, bytes) ^ 0xffffffff; | |
6593 | } |