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Commit | Line | Data |
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b5ff1b31 FB |
1 | #include <stdio.h> |
2 | #include <stdlib.h> | |
3 | #include <string.h> | |
4 | ||
5 | #include "cpu.h" | |
6 | #include "exec-all.h" | |
9ee6e8bb | 7 | #include "gdbstub.h" |
b26eefb6 | 8 | #include "helpers.h" |
9ee6e8bb PB |
9 | |
10 | static uint32_t cortexa8_cp15_c0_c1[8] = | |
11 | { 0x1031, 0x11, 0x400, 0, 0x31100003, 0x20000000, 0x01202000, 0x11 }; | |
12 | ||
13 | static uint32_t cortexa8_cp15_c0_c2[8] = | |
14 | { 0x00101111, 0x12112111, 0x21232031, 0x11112131, 0x00111142, 0, 0, 0 }; | |
15 | ||
16 | static uint32_t mpcore_cp15_c0_c1[8] = | |
17 | { 0x111, 0x1, 0, 0x2, 0x01100103, 0x10020302, 0x01222000, 0 }; | |
18 | ||
19 | static uint32_t mpcore_cp15_c0_c2[8] = | |
20 | { 0x00100011, 0x12002111, 0x11221011, 0x01102131, 0x141, 0, 0, 0 }; | |
21 | ||
22 | static uint32_t arm1136_cp15_c0_c1[8] = | |
23 | { 0x111, 0x1, 0x2, 0x3, 0x01130003, 0x10030302, 0x01222110, 0 }; | |
24 | ||
25 | static uint32_t arm1136_cp15_c0_c2[8] = | |
26 | { 0x00140011, 0x12002111, 0x11231111, 0x01102131, 0x141, 0, 0, 0 }; | |
b5ff1b31 | 27 | |
aaed909a FB |
28 | static uint32_t cpu_arm_find_by_name(const char *name); |
29 | ||
f3d6b95e PB |
30 | static inline void set_feature(CPUARMState *env, int feature) |
31 | { | |
32 | env->features |= 1u << feature; | |
33 | } | |
34 | ||
35 | static void cpu_reset_model_id(CPUARMState *env, uint32_t id) | |
36 | { | |
37 | env->cp15.c0_cpuid = id; | |
38 | switch (id) { | |
39 | case ARM_CPUID_ARM926: | |
40 | set_feature(env, ARM_FEATURE_VFP); | |
41 | env->vfp.xregs[ARM_VFP_FPSID] = 0x41011090; | |
c1713132 | 42 | env->cp15.c0_cachetype = 0x1dd20d2; |
610c3c8a | 43 | env->cp15.c1_sys = 0x00090078; |
f3d6b95e | 44 | break; |
ce819861 PB |
45 | case ARM_CPUID_ARM946: |
46 | set_feature(env, ARM_FEATURE_MPU); | |
47 | env->cp15.c0_cachetype = 0x0f004006; | |
610c3c8a | 48 | env->cp15.c1_sys = 0x00000078; |
ce819861 | 49 | break; |
f3d6b95e PB |
50 | case ARM_CPUID_ARM1026: |
51 | set_feature(env, ARM_FEATURE_VFP); | |
52 | set_feature(env, ARM_FEATURE_AUXCR); | |
53 | env->vfp.xregs[ARM_VFP_FPSID] = 0x410110a0; | |
c1713132 | 54 | env->cp15.c0_cachetype = 0x1dd20d2; |
610c3c8a | 55 | env->cp15.c1_sys = 0x00090078; |
c1713132 | 56 | break; |
9ee6e8bb PB |
57 | case ARM_CPUID_ARM1136: |
58 | set_feature(env, ARM_FEATURE_V6); | |
59 | set_feature(env, ARM_FEATURE_VFP); | |
60 | set_feature(env, ARM_FEATURE_AUXCR); | |
61 | env->vfp.xregs[ARM_VFP_FPSID] = 0x410120b4; | |
62 | env->vfp.xregs[ARM_VFP_MVFR0] = 0x11111111; | |
63 | env->vfp.xregs[ARM_VFP_MVFR1] = 0x00000000; | |
64 | memcpy(env->cp15.c0_c1, arm1136_cp15_c0_c1, 8 * sizeof(uint32_t)); | |
65 | memcpy(env->cp15.c0_c1, arm1136_cp15_c0_c2, 8 * sizeof(uint32_t)); | |
66 | env->cp15.c0_cachetype = 0x1dd20d2; | |
67 | break; | |
68 | case ARM_CPUID_ARM11MPCORE: | |
69 | set_feature(env, ARM_FEATURE_V6); | |
70 | set_feature(env, ARM_FEATURE_V6K); | |
71 | set_feature(env, ARM_FEATURE_VFP); | |
72 | set_feature(env, ARM_FEATURE_AUXCR); | |
73 | env->vfp.xregs[ARM_VFP_FPSID] = 0x410120b4; | |
74 | env->vfp.xregs[ARM_VFP_MVFR0] = 0x11111111; | |
75 | env->vfp.xregs[ARM_VFP_MVFR1] = 0x00000000; | |
76 | memcpy(env->cp15.c0_c1, mpcore_cp15_c0_c1, 8 * sizeof(uint32_t)); | |
77 | memcpy(env->cp15.c0_c1, mpcore_cp15_c0_c2, 8 * sizeof(uint32_t)); | |
78 | env->cp15.c0_cachetype = 0x1dd20d2; | |
79 | break; | |
80 | case ARM_CPUID_CORTEXA8: | |
81 | set_feature(env, ARM_FEATURE_V6); | |
82 | set_feature(env, ARM_FEATURE_V6K); | |
83 | set_feature(env, ARM_FEATURE_V7); | |
84 | set_feature(env, ARM_FEATURE_AUXCR); | |
85 | set_feature(env, ARM_FEATURE_THUMB2); | |
86 | set_feature(env, ARM_FEATURE_VFP); | |
87 | set_feature(env, ARM_FEATURE_VFP3); | |
88 | set_feature(env, ARM_FEATURE_NEON); | |
89 | env->vfp.xregs[ARM_VFP_FPSID] = 0x410330c0; | |
90 | env->vfp.xregs[ARM_VFP_MVFR0] = 0x11110222; | |
91 | env->vfp.xregs[ARM_VFP_MVFR1] = 0x00011100; | |
92 | memcpy(env->cp15.c0_c1, cortexa8_cp15_c0_c1, 8 * sizeof(uint32_t)); | |
93 | memcpy(env->cp15.c0_c1, cortexa8_cp15_c0_c2, 8 * sizeof(uint32_t)); | |
94 | env->cp15.c0_cachetype = 0x1dd20d2; | |
95 | break; | |
96 | case ARM_CPUID_CORTEXM3: | |
97 | set_feature(env, ARM_FEATURE_V6); | |
98 | set_feature(env, ARM_FEATURE_THUMB2); | |
99 | set_feature(env, ARM_FEATURE_V7); | |
100 | set_feature(env, ARM_FEATURE_M); | |
101 | set_feature(env, ARM_FEATURE_DIV); | |
102 | break; | |
103 | case ARM_CPUID_ANY: /* For userspace emulation. */ | |
104 | set_feature(env, ARM_FEATURE_V6); | |
105 | set_feature(env, ARM_FEATURE_V6K); | |
106 | set_feature(env, ARM_FEATURE_V7); | |
107 | set_feature(env, ARM_FEATURE_THUMB2); | |
108 | set_feature(env, ARM_FEATURE_VFP); | |
109 | set_feature(env, ARM_FEATURE_VFP3); | |
110 | set_feature(env, ARM_FEATURE_NEON); | |
111 | set_feature(env, ARM_FEATURE_DIV); | |
112 | break; | |
c3d2689d AZ |
113 | case ARM_CPUID_TI915T: |
114 | case ARM_CPUID_TI925T: | |
115 | set_feature(env, ARM_FEATURE_OMAPCP); | |
116 | env->cp15.c0_cpuid = ARM_CPUID_TI925T; /* Depends on wiring. */ | |
117 | env->cp15.c0_cachetype = 0x5109149; | |
118 | env->cp15.c1_sys = 0x00000070; | |
119 | env->cp15.c15_i_max = 0x000; | |
120 | env->cp15.c15_i_min = 0xff0; | |
121 | break; | |
c1713132 AZ |
122 | case ARM_CPUID_PXA250: |
123 | case ARM_CPUID_PXA255: | |
124 | case ARM_CPUID_PXA260: | |
125 | case ARM_CPUID_PXA261: | |
126 | case ARM_CPUID_PXA262: | |
127 | set_feature(env, ARM_FEATURE_XSCALE); | |
128 | /* JTAG_ID is ((id << 28) | 0x09265013) */ | |
129 | env->cp15.c0_cachetype = 0xd172172; | |
610c3c8a | 130 | env->cp15.c1_sys = 0x00000078; |
c1713132 AZ |
131 | break; |
132 | case ARM_CPUID_PXA270_A0: | |
133 | case ARM_CPUID_PXA270_A1: | |
134 | case ARM_CPUID_PXA270_B0: | |
135 | case ARM_CPUID_PXA270_B1: | |
136 | case ARM_CPUID_PXA270_C0: | |
137 | case ARM_CPUID_PXA270_C5: | |
138 | set_feature(env, ARM_FEATURE_XSCALE); | |
139 | /* JTAG_ID is ((id << 28) | 0x09265013) */ | |
18c9b560 AZ |
140 | set_feature(env, ARM_FEATURE_IWMMXT); |
141 | env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q'; | |
c1713132 | 142 | env->cp15.c0_cachetype = 0xd172172; |
610c3c8a | 143 | env->cp15.c1_sys = 0x00000078; |
f3d6b95e PB |
144 | break; |
145 | default: | |
146 | cpu_abort(env, "Bad CPU ID: %x\n", id); | |
147 | break; | |
148 | } | |
149 | } | |
150 | ||
40f137e1 PB |
151 | void cpu_reset(CPUARMState *env) |
152 | { | |
f3d6b95e PB |
153 | uint32_t id; |
154 | id = env->cp15.c0_cpuid; | |
155 | memset(env, 0, offsetof(CPUARMState, breakpoints)); | |
156 | if (id) | |
157 | cpu_reset_model_id(env, id); | |
40f137e1 PB |
158 | #if defined (CONFIG_USER_ONLY) |
159 | env->uncached_cpsr = ARM_CPU_MODE_USR; | |
160 | env->vfp.xregs[ARM_VFP_FPEXC] = 1 << 30; | |
161 | #else | |
162 | /* SVC mode with interrupts disabled. */ | |
163 | env->uncached_cpsr = ARM_CPU_MODE_SVC | CPSR_A | CPSR_F | CPSR_I; | |
9ee6e8bb PB |
164 | /* On ARMv7-M the CPSR_I is the value of the PRIMASK register, and is |
165 | clear at reset. */ | |
166 | if (IS_M(env)) | |
167 | env->uncached_cpsr &= ~CPSR_I; | |
40f137e1 PB |
168 | env->vfp.xregs[ARM_VFP_FPEXC] = 0; |
169 | #endif | |
170 | env->regs[15] = 0; | |
f3d6b95e | 171 | tlb_flush(env, 1); |
40f137e1 PB |
172 | } |
173 | ||
aaed909a | 174 | CPUARMState *cpu_arm_init(const char *cpu_model) |
40f137e1 PB |
175 | { |
176 | CPUARMState *env; | |
aaed909a | 177 | uint32_t id; |
b26eefb6 | 178 | static int inited = 0; |
40f137e1 | 179 | |
aaed909a FB |
180 | id = cpu_arm_find_by_name(cpu_model); |
181 | if (id == 0) | |
182 | return NULL; | |
40f137e1 PB |
183 | env = qemu_mallocz(sizeof(CPUARMState)); |
184 | if (!env) | |
185 | return NULL; | |
186 | cpu_exec_init(env); | |
b26eefb6 PB |
187 | if (!inited) { |
188 | inited = 1; | |
189 | arm_translate_init(); | |
190 | } | |
191 | ||
01ba9816 | 192 | env->cpu_model_str = cpu_model; |
aaed909a | 193 | env->cp15.c0_cpuid = id; |
40f137e1 | 194 | cpu_reset(env); |
40f137e1 PB |
195 | return env; |
196 | } | |
197 | ||
3371d272 PB |
198 | struct arm_cpu_t { |
199 | uint32_t id; | |
200 | const char *name; | |
201 | }; | |
202 | ||
203 | static const struct arm_cpu_t arm_cpu_names[] = { | |
204 | { ARM_CPUID_ARM926, "arm926"}, | |
ce819861 | 205 | { ARM_CPUID_ARM946, "arm946"}, |
3371d272 | 206 | { ARM_CPUID_ARM1026, "arm1026"}, |
9ee6e8bb PB |
207 | { ARM_CPUID_ARM1136, "arm1136"}, |
208 | { ARM_CPUID_ARM11MPCORE, "arm11mpcore"}, | |
209 | { ARM_CPUID_CORTEXM3, "cortex-m3"}, | |
210 | { ARM_CPUID_CORTEXA8, "cortex-a8"}, | |
c3d2689d | 211 | { ARM_CPUID_TI925T, "ti925t" }, |
c1713132 AZ |
212 | { ARM_CPUID_PXA250, "pxa250" }, |
213 | { ARM_CPUID_PXA255, "pxa255" }, | |
214 | { ARM_CPUID_PXA260, "pxa260" }, | |
215 | { ARM_CPUID_PXA261, "pxa261" }, | |
216 | { ARM_CPUID_PXA262, "pxa262" }, | |
217 | { ARM_CPUID_PXA270, "pxa270" }, | |
218 | { ARM_CPUID_PXA270_A0, "pxa270-a0" }, | |
219 | { ARM_CPUID_PXA270_A1, "pxa270-a1" }, | |
220 | { ARM_CPUID_PXA270_B0, "pxa270-b0" }, | |
221 | { ARM_CPUID_PXA270_B1, "pxa270-b1" }, | |
222 | { ARM_CPUID_PXA270_C0, "pxa270-c0" }, | |
223 | { ARM_CPUID_PXA270_C5, "pxa270-c5" }, | |
9ee6e8bb | 224 | { ARM_CPUID_ANY, "any"}, |
3371d272 PB |
225 | { 0, NULL} |
226 | }; | |
227 | ||
c732abe2 | 228 | void arm_cpu_list(FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...)) |
5adb4839 PB |
229 | { |
230 | int i; | |
231 | ||
c732abe2 | 232 | (*cpu_fprintf)(f, "Available CPUs:\n"); |
5adb4839 | 233 | for (i = 0; arm_cpu_names[i].name; i++) { |
c732abe2 | 234 | (*cpu_fprintf)(f, " %s\n", arm_cpu_names[i].name); |
5adb4839 PB |
235 | } |
236 | } | |
237 | ||
aaed909a FB |
238 | /* return 0 if not found */ |
239 | static uint32_t cpu_arm_find_by_name(const char *name) | |
40f137e1 | 240 | { |
3371d272 PB |
241 | int i; |
242 | uint32_t id; | |
243 | ||
244 | id = 0; | |
3371d272 PB |
245 | for (i = 0; arm_cpu_names[i].name; i++) { |
246 | if (strcmp(name, arm_cpu_names[i].name) == 0) { | |
247 | id = arm_cpu_names[i].id; | |
248 | break; | |
249 | } | |
250 | } | |
aaed909a | 251 | return id; |
40f137e1 PB |
252 | } |
253 | ||
254 | void cpu_arm_close(CPUARMState *env) | |
255 | { | |
256 | free(env); | |
257 | } | |
258 | ||
2f4a40e5 AZ |
259 | uint32_t cpsr_read(CPUARMState *env) |
260 | { | |
261 | int ZF; | |
6fbe23d5 PB |
262 | ZF = (env->ZF == 0); |
263 | return env->uncached_cpsr | (env->NF & 0x80000000) | (ZF << 30) | | |
2f4a40e5 AZ |
264 | (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27) |
265 | | (env->thumb << 5) | ((env->condexec_bits & 3) << 25) | |
266 | | ((env->condexec_bits & 0xfc) << 8) | |
267 | | (env->GE << 16); | |
268 | } | |
269 | ||
270 | void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask) | |
271 | { | |
2f4a40e5 | 272 | if (mask & CPSR_NZCV) { |
6fbe23d5 PB |
273 | env->ZF = (~val) & CPSR_Z; |
274 | env->NF = val; | |
2f4a40e5 AZ |
275 | env->CF = (val >> 29) & 1; |
276 | env->VF = (val << 3) & 0x80000000; | |
277 | } | |
278 | if (mask & CPSR_Q) | |
279 | env->QF = ((val & CPSR_Q) != 0); | |
280 | if (mask & CPSR_T) | |
281 | env->thumb = ((val & CPSR_T) != 0); | |
282 | if (mask & CPSR_IT_0_1) { | |
283 | env->condexec_bits &= ~3; | |
284 | env->condexec_bits |= (val >> 25) & 3; | |
285 | } | |
286 | if (mask & CPSR_IT_2_7) { | |
287 | env->condexec_bits &= 3; | |
288 | env->condexec_bits |= (val >> 8) & 0xfc; | |
289 | } | |
290 | if (mask & CPSR_GE) { | |
291 | env->GE = (val >> 16) & 0xf; | |
292 | } | |
293 | ||
294 | if ((env->uncached_cpsr ^ val) & mask & CPSR_M) { | |
295 | switch_mode(env, val & CPSR_M); | |
296 | } | |
297 | mask &= ~CACHED_CPSR_BITS; | |
298 | env->uncached_cpsr = (env->uncached_cpsr & ~mask) | (val & mask); | |
299 | } | |
300 | ||
b26eefb6 PB |
301 | /* Sign/zero extend */ |
302 | uint32_t HELPER(sxtb16)(uint32_t x) | |
303 | { | |
304 | uint32_t res; | |
305 | res = (uint16_t)(int8_t)x; | |
306 | res |= (uint32_t)(int8_t)(x >> 16) << 16; | |
307 | return res; | |
308 | } | |
309 | ||
310 | uint32_t HELPER(uxtb16)(uint32_t x) | |
311 | { | |
312 | uint32_t res; | |
313 | res = (uint16_t)(uint8_t)x; | |
314 | res |= (uint32_t)(uint8_t)(x >> 16) << 16; | |
315 | return res; | |
316 | } | |
317 | ||
f51bbbfe PB |
318 | uint32_t HELPER(clz)(uint32_t x) |
319 | { | |
320 | int count; | |
321 | for (count = 32; x; count--) | |
322 | x >>= 1; | |
323 | return count; | |
324 | } | |
325 | ||
3670669c PB |
326 | int32_t HELPER(sdiv)(int32_t num, int32_t den) |
327 | { | |
328 | if (den == 0) | |
329 | return 0; | |
330 | return num / den; | |
331 | } | |
332 | ||
333 | uint32_t HELPER(udiv)(uint32_t num, uint32_t den) | |
334 | { | |
335 | if (den == 0) | |
336 | return 0; | |
337 | return num / den; | |
338 | } | |
339 | ||
340 | uint32_t HELPER(rbit)(uint32_t x) | |
341 | { | |
342 | x = ((x & 0xff000000) >> 24) | |
343 | | ((x & 0x00ff0000) >> 8) | |
344 | | ((x & 0x0000ff00) << 8) | |
345 | | ((x & 0x000000ff) << 24); | |
346 | x = ((x & 0xf0f0f0f0) >> 4) | |
347 | | ((x & 0x0f0f0f0f) << 4); | |
348 | x = ((x & 0x88888888) >> 3) | |
349 | | ((x & 0x44444444) >> 1) | |
350 | | ((x & 0x22222222) << 1) | |
351 | | ((x & 0x11111111) << 3); | |
352 | return x; | |
353 | } | |
354 | ||
ad69471c PB |
355 | uint32_t HELPER(abs)(uint32_t x) |
356 | { | |
357 | return ((int32_t)x < 0) ? -x : x; | |
358 | } | |
359 | ||
5fafdf24 | 360 | #if defined(CONFIG_USER_ONLY) |
b5ff1b31 FB |
361 | |
362 | void do_interrupt (CPUState *env) | |
363 | { | |
364 | env->exception_index = -1; | |
365 | } | |
366 | ||
9ee6e8bb PB |
367 | /* Structure used to record exclusive memory locations. */ |
368 | typedef struct mmon_state { | |
369 | struct mmon_state *next; | |
370 | CPUARMState *cpu_env; | |
371 | uint32_t addr; | |
372 | } mmon_state; | |
373 | ||
374 | /* Chain of current locks. */ | |
375 | static mmon_state* mmon_head = NULL; | |
376 | ||
b5ff1b31 | 377 | int cpu_arm_handle_mmu_fault (CPUState *env, target_ulong address, int rw, |
6ebbf390 | 378 | int mmu_idx, int is_softmmu) |
b5ff1b31 FB |
379 | { |
380 | if (rw == 2) { | |
381 | env->exception_index = EXCP_PREFETCH_ABORT; | |
382 | env->cp15.c6_insn = address; | |
383 | } else { | |
384 | env->exception_index = EXCP_DATA_ABORT; | |
385 | env->cp15.c6_data = address; | |
386 | } | |
387 | return 1; | |
388 | } | |
389 | ||
9ee6e8bb PB |
390 | static void allocate_mmon_state(CPUState *env) |
391 | { | |
392 | env->mmon_entry = malloc(sizeof (mmon_state)); | |
393 | if (!env->mmon_entry) | |
394 | abort(); | |
395 | memset (env->mmon_entry, 0, sizeof (mmon_state)); | |
396 | env->mmon_entry->cpu_env = env; | |
397 | mmon_head = env->mmon_entry; | |
398 | } | |
399 | ||
400 | /* Flush any monitor locks for the specified address. */ | |
401 | static void flush_mmon(uint32_t addr) | |
402 | { | |
403 | mmon_state *mon; | |
404 | ||
405 | for (mon = mmon_head; mon; mon = mon->next) | |
406 | { | |
407 | if (mon->addr != addr) | |
408 | continue; | |
409 | ||
410 | mon->addr = 0; | |
411 | break; | |
412 | } | |
413 | } | |
414 | ||
415 | /* Mark an address for exclusive access. */ | |
8f8e3aa4 | 416 | void HELPER(mark_exclusive)(CPUState *env, uint32_t addr) |
9ee6e8bb PB |
417 | { |
418 | if (!env->mmon_entry) | |
419 | allocate_mmon_state(env); | |
420 | /* Clear any previous locks. */ | |
421 | flush_mmon(addr); | |
422 | env->mmon_entry->addr = addr; | |
423 | } | |
424 | ||
425 | /* Test if an exclusive address is still exclusive. Returns zero | |
426 | if the address is still exclusive. */ | |
8f8e3aa4 | 427 | uint32_t HELPER(test_exclusive)(CPUState *env, uint32_t addr) |
9ee6e8bb PB |
428 | { |
429 | int res; | |
430 | ||
431 | if (!env->mmon_entry) | |
432 | return 1; | |
433 | if (env->mmon_entry->addr == addr) | |
434 | res = 0; | |
435 | else | |
436 | res = 1; | |
437 | flush_mmon(addr); | |
438 | return res; | |
439 | } | |
440 | ||
8f8e3aa4 | 441 | void HELPER(clrex)(CPUState *env) |
9ee6e8bb PB |
442 | { |
443 | if (!(env->mmon_entry && env->mmon_entry->addr)) | |
444 | return; | |
445 | flush_mmon(env->mmon_entry->addr); | |
446 | } | |
447 | ||
9b3c35e0 | 448 | target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr) |
b5ff1b31 FB |
449 | { |
450 | return addr; | |
451 | } | |
452 | ||
453 | /* These should probably raise undefined insn exceptions. */ | |
8984bd2e | 454 | void HELPER(set_cp)(CPUState *env, uint32_t insn, uint32_t val) |
c1713132 AZ |
455 | { |
456 | int op1 = (insn >> 8) & 0xf; | |
457 | cpu_abort(env, "cp%i insn %08x\n", op1, insn); | |
458 | return; | |
459 | } | |
460 | ||
8984bd2e | 461 | uint32_t HELPER(get_cp)(CPUState *env, uint32_t insn) |
c1713132 AZ |
462 | { |
463 | int op1 = (insn >> 8) & 0xf; | |
464 | cpu_abort(env, "cp%i insn %08x\n", op1, insn); | |
465 | return 0; | |
466 | } | |
467 | ||
8984bd2e | 468 | void HELPER(set_cp15)(CPUState *env, uint32_t insn, uint32_t val) |
b5ff1b31 FB |
469 | { |
470 | cpu_abort(env, "cp15 insn %08x\n", insn); | |
471 | } | |
472 | ||
8984bd2e | 473 | uint32_t HELPER(get_cp15)(CPUState *env, uint32_t insn) |
b5ff1b31 FB |
474 | { |
475 | cpu_abort(env, "cp15 insn %08x\n", insn); | |
476 | return 0; | |
477 | } | |
478 | ||
9ee6e8bb | 479 | /* These should probably raise undefined insn exceptions. */ |
8984bd2e | 480 | void HELPER(v7m_msr)(CPUState *env, uint32_t reg, uint32_t val) |
9ee6e8bb PB |
481 | { |
482 | cpu_abort(env, "v7m_mrs %d\n", reg); | |
483 | } | |
484 | ||
8984bd2e | 485 | uint32_t HELPER(v7m_mrs)(CPUState *env, uint32_t reg) |
9ee6e8bb PB |
486 | { |
487 | cpu_abort(env, "v7m_mrs %d\n", reg); | |
488 | return 0; | |
489 | } | |
490 | ||
b5ff1b31 FB |
491 | void switch_mode(CPUState *env, int mode) |
492 | { | |
493 | if (mode != ARM_CPU_MODE_USR) | |
494 | cpu_abort(env, "Tried to switch out of user mode\n"); | |
495 | } | |
496 | ||
b0109805 | 497 | void HELPER(set_r13_banked)(CPUState *env, uint32_t mode, uint32_t val) |
9ee6e8bb PB |
498 | { |
499 | cpu_abort(env, "banked r13 write\n"); | |
500 | } | |
501 | ||
b0109805 | 502 | uint32_t HELPER(get_r13_banked)(CPUState *env, uint32_t mode) |
9ee6e8bb PB |
503 | { |
504 | cpu_abort(env, "banked r13 read\n"); | |
505 | return 0; | |
506 | } | |
507 | ||
b5ff1b31 FB |
508 | #else |
509 | ||
8e71621f PB |
510 | extern int semihosting_enabled; |
511 | ||
b5ff1b31 FB |
512 | /* Map CPU modes onto saved register banks. */ |
513 | static inline int bank_number (int mode) | |
514 | { | |
515 | switch (mode) { | |
516 | case ARM_CPU_MODE_USR: | |
517 | case ARM_CPU_MODE_SYS: | |
518 | return 0; | |
519 | case ARM_CPU_MODE_SVC: | |
520 | return 1; | |
521 | case ARM_CPU_MODE_ABT: | |
522 | return 2; | |
523 | case ARM_CPU_MODE_UND: | |
524 | return 3; | |
525 | case ARM_CPU_MODE_IRQ: | |
526 | return 4; | |
527 | case ARM_CPU_MODE_FIQ: | |
528 | return 5; | |
529 | } | |
530 | cpu_abort(cpu_single_env, "Bad mode %x\n", mode); | |
531 | return -1; | |
532 | } | |
533 | ||
534 | void switch_mode(CPUState *env, int mode) | |
535 | { | |
536 | int old_mode; | |
537 | int i; | |
538 | ||
539 | old_mode = env->uncached_cpsr & CPSR_M; | |
540 | if (mode == old_mode) | |
541 | return; | |
542 | ||
543 | if (old_mode == ARM_CPU_MODE_FIQ) { | |
544 | memcpy (env->fiq_regs, env->regs + 8, 5 * sizeof(uint32_t)); | |
8637c67f | 545 | memcpy (env->regs + 8, env->usr_regs, 5 * sizeof(uint32_t)); |
b5ff1b31 FB |
546 | } else if (mode == ARM_CPU_MODE_FIQ) { |
547 | memcpy (env->usr_regs, env->regs + 8, 5 * sizeof(uint32_t)); | |
8637c67f | 548 | memcpy (env->regs + 8, env->fiq_regs, 5 * sizeof(uint32_t)); |
b5ff1b31 FB |
549 | } |
550 | ||
551 | i = bank_number(old_mode); | |
552 | env->banked_r13[i] = env->regs[13]; | |
553 | env->banked_r14[i] = env->regs[14]; | |
554 | env->banked_spsr[i] = env->spsr; | |
555 | ||
556 | i = bank_number(mode); | |
557 | env->regs[13] = env->banked_r13[i]; | |
558 | env->regs[14] = env->banked_r14[i]; | |
559 | env->spsr = env->banked_spsr[i]; | |
560 | } | |
561 | ||
9ee6e8bb PB |
562 | static void v7m_push(CPUARMState *env, uint32_t val) |
563 | { | |
564 | env->regs[13] -= 4; | |
565 | stl_phys(env->regs[13], val); | |
566 | } | |
567 | ||
568 | static uint32_t v7m_pop(CPUARMState *env) | |
569 | { | |
570 | uint32_t val; | |
571 | val = ldl_phys(env->regs[13]); | |
572 | env->regs[13] += 4; | |
573 | return val; | |
574 | } | |
575 | ||
576 | /* Switch to V7M main or process stack pointer. */ | |
577 | static void switch_v7m_sp(CPUARMState *env, int process) | |
578 | { | |
579 | uint32_t tmp; | |
580 | if (env->v7m.current_sp != process) { | |
581 | tmp = env->v7m.other_sp; | |
582 | env->v7m.other_sp = env->regs[13]; | |
583 | env->regs[13] = tmp; | |
584 | env->v7m.current_sp = process; | |
585 | } | |
586 | } | |
587 | ||
588 | static void do_v7m_exception_exit(CPUARMState *env) | |
589 | { | |
590 | uint32_t type; | |
591 | uint32_t xpsr; | |
592 | ||
593 | type = env->regs[15]; | |
594 | if (env->v7m.exception != 0) | |
595 | armv7m_nvic_complete_irq(env->v7m.nvic, env->v7m.exception); | |
596 | ||
597 | /* Switch to the target stack. */ | |
598 | switch_v7m_sp(env, (type & 4) != 0); | |
599 | /* Pop registers. */ | |
600 | env->regs[0] = v7m_pop(env); | |
601 | env->regs[1] = v7m_pop(env); | |
602 | env->regs[2] = v7m_pop(env); | |
603 | env->regs[3] = v7m_pop(env); | |
604 | env->regs[12] = v7m_pop(env); | |
605 | env->regs[14] = v7m_pop(env); | |
606 | env->regs[15] = v7m_pop(env); | |
607 | xpsr = v7m_pop(env); | |
608 | xpsr_write(env, xpsr, 0xfffffdff); | |
609 | /* Undo stack alignment. */ | |
610 | if (xpsr & 0x200) | |
611 | env->regs[13] |= 4; | |
612 | /* ??? The exception return type specifies Thread/Handler mode. However | |
613 | this is also implied by the xPSR value. Not sure what to do | |
614 | if there is a mismatch. */ | |
615 | /* ??? Likewise for mismatches between the CONTROL register and the stack | |
616 | pointer. */ | |
617 | } | |
618 | ||
619 | void do_interrupt_v7m(CPUARMState *env) | |
620 | { | |
621 | uint32_t xpsr = xpsr_read(env); | |
622 | uint32_t lr; | |
623 | uint32_t addr; | |
624 | ||
625 | lr = 0xfffffff1; | |
626 | if (env->v7m.current_sp) | |
627 | lr |= 4; | |
628 | if (env->v7m.exception == 0) | |
629 | lr |= 8; | |
630 | ||
631 | /* For exceptions we just mark as pending on the NVIC, and let that | |
632 | handle it. */ | |
633 | /* TODO: Need to escalate if the current priority is higher than the | |
634 | one we're raising. */ | |
635 | switch (env->exception_index) { | |
636 | case EXCP_UDEF: | |
637 | armv7m_nvic_set_pending(env->v7m.nvic, ARMV7M_EXCP_USAGE); | |
638 | return; | |
639 | case EXCP_SWI: | |
640 | env->regs[15] += 2; | |
641 | armv7m_nvic_set_pending(env->v7m.nvic, ARMV7M_EXCP_SVC); | |
642 | return; | |
643 | case EXCP_PREFETCH_ABORT: | |
644 | case EXCP_DATA_ABORT: | |
645 | armv7m_nvic_set_pending(env->v7m.nvic, ARMV7M_EXCP_MEM); | |
646 | return; | |
647 | case EXCP_BKPT: | |
2ad207d4 PB |
648 | if (semihosting_enabled) { |
649 | int nr; | |
650 | nr = lduw_code(env->regs[15]) & 0xff; | |
651 | if (nr == 0xab) { | |
652 | env->regs[15] += 2; | |
653 | env->regs[0] = do_arm_semihosting(env); | |
654 | return; | |
655 | } | |
656 | } | |
9ee6e8bb PB |
657 | armv7m_nvic_set_pending(env->v7m.nvic, ARMV7M_EXCP_DEBUG); |
658 | return; | |
659 | case EXCP_IRQ: | |
660 | env->v7m.exception = armv7m_nvic_acknowledge_irq(env->v7m.nvic); | |
661 | break; | |
662 | case EXCP_EXCEPTION_EXIT: | |
663 | do_v7m_exception_exit(env); | |
664 | return; | |
665 | default: | |
666 | cpu_abort(env, "Unhandled exception 0x%x\n", env->exception_index); | |
667 | return; /* Never happens. Keep compiler happy. */ | |
668 | } | |
669 | ||
670 | /* Align stack pointer. */ | |
671 | /* ??? Should only do this if Configuration Control Register | |
672 | STACKALIGN bit is set. */ | |
673 | if (env->regs[13] & 4) { | |
674 | env->regs[13] += 4; | |
675 | xpsr |= 0x200; | |
676 | } | |
677 | /* Switch to the hander mode. */ | |
678 | v7m_push(env, xpsr); | |
679 | v7m_push(env, env->regs[15]); | |
680 | v7m_push(env, env->regs[14]); | |
681 | v7m_push(env, env->regs[12]); | |
682 | v7m_push(env, env->regs[3]); | |
683 | v7m_push(env, env->regs[2]); | |
684 | v7m_push(env, env->regs[1]); | |
685 | v7m_push(env, env->regs[0]); | |
686 | switch_v7m_sp(env, 0); | |
687 | env->uncached_cpsr &= ~CPSR_IT; | |
688 | env->regs[14] = lr; | |
689 | addr = ldl_phys(env->v7m.vecbase + env->v7m.exception * 4); | |
690 | env->regs[15] = addr & 0xfffffffe; | |
691 | env->thumb = addr & 1; | |
692 | } | |
693 | ||
b5ff1b31 FB |
694 | /* Handle a CPU exception. */ |
695 | void do_interrupt(CPUARMState *env) | |
696 | { | |
697 | uint32_t addr; | |
698 | uint32_t mask; | |
699 | int new_mode; | |
700 | uint32_t offset; | |
701 | ||
9ee6e8bb PB |
702 | if (IS_M(env)) { |
703 | do_interrupt_v7m(env); | |
704 | return; | |
705 | } | |
b5ff1b31 FB |
706 | /* TODO: Vectored interrupt controller. */ |
707 | switch (env->exception_index) { | |
708 | case EXCP_UDEF: | |
709 | new_mode = ARM_CPU_MODE_UND; | |
710 | addr = 0x04; | |
711 | mask = CPSR_I; | |
712 | if (env->thumb) | |
713 | offset = 2; | |
714 | else | |
715 | offset = 4; | |
716 | break; | |
717 | case EXCP_SWI: | |
8e71621f PB |
718 | if (semihosting_enabled) { |
719 | /* Check for semihosting interrupt. */ | |
720 | if (env->thumb) { | |
721 | mask = lduw_code(env->regs[15] - 2) & 0xff; | |
722 | } else { | |
723 | mask = ldl_code(env->regs[15] - 4) & 0xffffff; | |
724 | } | |
725 | /* Only intercept calls from privileged modes, to provide some | |
726 | semblance of security. */ | |
727 | if (((mask == 0x123456 && !env->thumb) | |
728 | || (mask == 0xab && env->thumb)) | |
729 | && (env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR) { | |
730 | env->regs[0] = do_arm_semihosting(env); | |
731 | return; | |
732 | } | |
733 | } | |
b5ff1b31 FB |
734 | new_mode = ARM_CPU_MODE_SVC; |
735 | addr = 0x08; | |
736 | mask = CPSR_I; | |
737 | /* The PC already points to the next instructon. */ | |
738 | offset = 0; | |
739 | break; | |
06c949e6 | 740 | case EXCP_BKPT: |
9ee6e8bb | 741 | /* See if this is a semihosting syscall. */ |
2ad207d4 | 742 | if (env->thumb && semihosting_enabled) { |
9ee6e8bb PB |
743 | mask = lduw_code(env->regs[15]) & 0xff; |
744 | if (mask == 0xab | |
745 | && (env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR) { | |
746 | env->regs[15] += 2; | |
747 | env->regs[0] = do_arm_semihosting(env); | |
748 | return; | |
749 | } | |
750 | } | |
751 | /* Fall through to prefetch abort. */ | |
752 | case EXCP_PREFETCH_ABORT: | |
b5ff1b31 FB |
753 | new_mode = ARM_CPU_MODE_ABT; |
754 | addr = 0x0c; | |
755 | mask = CPSR_A | CPSR_I; | |
756 | offset = 4; | |
757 | break; | |
758 | case EXCP_DATA_ABORT: | |
759 | new_mode = ARM_CPU_MODE_ABT; | |
760 | addr = 0x10; | |
761 | mask = CPSR_A | CPSR_I; | |
762 | offset = 8; | |
763 | break; | |
764 | case EXCP_IRQ: | |
765 | new_mode = ARM_CPU_MODE_IRQ; | |
766 | addr = 0x18; | |
767 | /* Disable IRQ and imprecise data aborts. */ | |
768 | mask = CPSR_A | CPSR_I; | |
769 | offset = 4; | |
770 | break; | |
771 | case EXCP_FIQ: | |
772 | new_mode = ARM_CPU_MODE_FIQ; | |
773 | addr = 0x1c; | |
774 | /* Disable FIQ, IRQ and imprecise data aborts. */ | |
775 | mask = CPSR_A | CPSR_I | CPSR_F; | |
776 | offset = 4; | |
777 | break; | |
778 | default: | |
779 | cpu_abort(env, "Unhandled exception 0x%x\n", env->exception_index); | |
780 | return; /* Never happens. Keep compiler happy. */ | |
781 | } | |
782 | /* High vectors. */ | |
783 | if (env->cp15.c1_sys & (1 << 13)) { | |
784 | addr += 0xffff0000; | |
785 | } | |
786 | switch_mode (env, new_mode); | |
787 | env->spsr = cpsr_read(env); | |
9ee6e8bb PB |
788 | /* Clear IT bits. */ |
789 | env->condexec_bits = 0; | |
6d7e6326 | 790 | /* Switch to the new mode, and switch to Arm mode. */ |
b5ff1b31 | 791 | /* ??? Thumb interrupt handlers not implemented. */ |
6d7e6326 | 792 | env->uncached_cpsr = (env->uncached_cpsr & ~CPSR_M) | new_mode; |
b5ff1b31 | 793 | env->uncached_cpsr |= mask; |
6d7e6326 | 794 | env->thumb = 0; |
b5ff1b31 FB |
795 | env->regs[14] = env->regs[15] + offset; |
796 | env->regs[15] = addr; | |
797 | env->interrupt_request |= CPU_INTERRUPT_EXITTB; | |
798 | } | |
799 | ||
800 | /* Check section/page access permissions. | |
801 | Returns the page protection flags, or zero if the access is not | |
802 | permitted. */ | |
803 | static inline int check_ap(CPUState *env, int ap, int domain, int access_type, | |
804 | int is_user) | |
805 | { | |
9ee6e8bb PB |
806 | int prot_ro; |
807 | ||
b5ff1b31 FB |
808 | if (domain == 3) |
809 | return PAGE_READ | PAGE_WRITE; | |
810 | ||
9ee6e8bb PB |
811 | if (access_type == 1) |
812 | prot_ro = 0; | |
813 | else | |
814 | prot_ro = PAGE_READ; | |
815 | ||
b5ff1b31 FB |
816 | switch (ap) { |
817 | case 0: | |
78600320 | 818 | if (access_type == 1) |
b5ff1b31 FB |
819 | return 0; |
820 | switch ((env->cp15.c1_sys >> 8) & 3) { | |
821 | case 1: | |
822 | return is_user ? 0 : PAGE_READ; | |
823 | case 2: | |
824 | return PAGE_READ; | |
825 | default: | |
826 | return 0; | |
827 | } | |
828 | case 1: | |
829 | return is_user ? 0 : PAGE_READ | PAGE_WRITE; | |
830 | case 2: | |
831 | if (is_user) | |
9ee6e8bb | 832 | return prot_ro; |
b5ff1b31 FB |
833 | else |
834 | return PAGE_READ | PAGE_WRITE; | |
835 | case 3: | |
836 | return PAGE_READ | PAGE_WRITE; | |
9ee6e8bb PB |
837 | case 4: case 7: /* Reserved. */ |
838 | return 0; | |
839 | case 5: | |
840 | return is_user ? 0 : prot_ro; | |
841 | case 6: | |
842 | return prot_ro; | |
b5ff1b31 FB |
843 | default: |
844 | abort(); | |
845 | } | |
846 | } | |
847 | ||
9ee6e8bb PB |
848 | static int get_phys_addr_v5(CPUState *env, uint32_t address, int access_type, |
849 | int is_user, uint32_t *phys_ptr, int *prot) | |
b5ff1b31 FB |
850 | { |
851 | int code; | |
852 | uint32_t table; | |
853 | uint32_t desc; | |
854 | int type; | |
855 | int ap; | |
856 | int domain; | |
857 | uint32_t phys_addr; | |
858 | ||
9ee6e8bb PB |
859 | /* Pagetable walk. */ |
860 | /* Lookup l1 descriptor. */ | |
861 | if (address & env->cp15.c2_mask) | |
862 | table = env->cp15.c2_base1; | |
863 | else | |
864 | table = env->cp15.c2_base0; | |
865 | table = (table & 0xffffc000) | ((address >> 18) & 0x3ffc); | |
866 | desc = ldl_phys(table); | |
867 | type = (desc & 3); | |
868 | domain = (env->cp15.c3 >> ((desc >> 4) & 0x1e)) & 3; | |
869 | if (type == 0) { | |
870 | /* Secton translation fault. */ | |
871 | code = 5; | |
872 | goto do_fault; | |
873 | } | |
874 | if (domain == 0 || domain == 2) { | |
875 | if (type == 2) | |
876 | code = 9; /* Section domain fault. */ | |
877 | else | |
878 | code = 11; /* Page domain fault. */ | |
879 | goto do_fault; | |
880 | } | |
881 | if (type == 2) { | |
882 | /* 1Mb section. */ | |
883 | phys_addr = (desc & 0xfff00000) | (address & 0x000fffff); | |
884 | ap = (desc >> 10) & 3; | |
885 | code = 13; | |
886 | } else { | |
887 | /* Lookup l2 entry. */ | |
888 | if (type == 1) { | |
889 | /* Coarse pagetable. */ | |
890 | table = (desc & 0xfffffc00) | ((address >> 10) & 0x3fc); | |
891 | } else { | |
892 | /* Fine pagetable. */ | |
893 | table = (desc & 0xfffff000) | ((address >> 8) & 0xffc); | |
894 | } | |
895 | desc = ldl_phys(table); | |
896 | switch (desc & 3) { | |
897 | case 0: /* Page translation fault. */ | |
898 | code = 7; | |
899 | goto do_fault; | |
900 | case 1: /* 64k page. */ | |
901 | phys_addr = (desc & 0xffff0000) | (address & 0xffff); | |
902 | ap = (desc >> (4 + ((address >> 13) & 6))) & 3; | |
ce819861 | 903 | break; |
9ee6e8bb PB |
904 | case 2: /* 4k page. */ |
905 | phys_addr = (desc & 0xfffff000) | (address & 0xfff); | |
906 | ap = (desc >> (4 + ((address >> 13) & 6))) & 3; | |
ce819861 | 907 | break; |
9ee6e8bb PB |
908 | case 3: /* 1k page. */ |
909 | if (type == 1) { | |
910 | if (arm_feature(env, ARM_FEATURE_XSCALE)) { | |
911 | phys_addr = (desc & 0xfffff000) | (address & 0xfff); | |
912 | } else { | |
913 | /* Page translation fault. */ | |
914 | code = 7; | |
915 | goto do_fault; | |
916 | } | |
917 | } else { | |
918 | phys_addr = (desc & 0xfffffc00) | (address & 0x3ff); | |
919 | } | |
920 | ap = (desc >> 4) & 3; | |
ce819861 PB |
921 | break; |
922 | default: | |
9ee6e8bb PB |
923 | /* Never happens, but compiler isn't smart enough to tell. */ |
924 | abort(); | |
ce819861 | 925 | } |
9ee6e8bb PB |
926 | code = 15; |
927 | } | |
928 | *prot = check_ap(env, ap, domain, access_type, is_user); | |
929 | if (!*prot) { | |
930 | /* Access permission fault. */ | |
931 | goto do_fault; | |
932 | } | |
933 | *phys_ptr = phys_addr; | |
934 | return 0; | |
935 | do_fault: | |
936 | return code | (domain << 4); | |
937 | } | |
938 | ||
939 | static int get_phys_addr_v6(CPUState *env, uint32_t address, int access_type, | |
940 | int is_user, uint32_t *phys_ptr, int *prot) | |
941 | { | |
942 | int code; | |
943 | uint32_t table; | |
944 | uint32_t desc; | |
945 | uint32_t xn; | |
946 | int type; | |
947 | int ap; | |
948 | int domain; | |
949 | uint32_t phys_addr; | |
950 | ||
951 | /* Pagetable walk. */ | |
952 | /* Lookup l1 descriptor. */ | |
953 | if (address & env->cp15.c2_mask) | |
954 | table = env->cp15.c2_base1; | |
955 | else | |
956 | table = env->cp15.c2_base0; | |
957 | table = (table & 0xffffc000) | ((address >> 18) & 0x3ffc); | |
958 | desc = ldl_phys(table); | |
959 | type = (desc & 3); | |
960 | if (type == 0) { | |
961 | /* Secton translation fault. */ | |
962 | code = 5; | |
963 | domain = 0; | |
964 | goto do_fault; | |
965 | } else if (type == 2 && (desc & (1 << 18))) { | |
966 | /* Supersection. */ | |
967 | domain = 0; | |
b5ff1b31 | 968 | } else { |
9ee6e8bb PB |
969 | /* Section or page. */ |
970 | domain = (desc >> 4) & 0x1e; | |
971 | } | |
972 | domain = (env->cp15.c3 >> domain) & 3; | |
973 | if (domain == 0 || domain == 2) { | |
974 | if (type == 2) | |
975 | code = 9; /* Section domain fault. */ | |
976 | else | |
977 | code = 11; /* Page domain fault. */ | |
978 | goto do_fault; | |
979 | } | |
980 | if (type == 2) { | |
981 | if (desc & (1 << 18)) { | |
982 | /* Supersection. */ | |
983 | phys_addr = (desc & 0xff000000) | (address & 0x00ffffff); | |
b5ff1b31 | 984 | } else { |
9ee6e8bb PB |
985 | /* Section. */ |
986 | phys_addr = (desc & 0xfff00000) | (address & 0x000fffff); | |
b5ff1b31 | 987 | } |
9ee6e8bb PB |
988 | ap = ((desc >> 10) & 3) | ((desc >> 13) & 4); |
989 | xn = desc & (1 << 4); | |
990 | code = 13; | |
991 | } else { | |
992 | /* Lookup l2 entry. */ | |
993 | table = (desc & 0xfffffc00) | ((address >> 10) & 0x3fc); | |
994 | desc = ldl_phys(table); | |
995 | ap = ((desc >> 4) & 3) | ((desc >> 7) & 4); | |
996 | switch (desc & 3) { | |
997 | case 0: /* Page translation fault. */ | |
998 | code = 7; | |
b5ff1b31 | 999 | goto do_fault; |
9ee6e8bb PB |
1000 | case 1: /* 64k page. */ |
1001 | phys_addr = (desc & 0xffff0000) | (address & 0xffff); | |
1002 | xn = desc & (1 << 15); | |
1003 | break; | |
1004 | case 2: case 3: /* 4k page. */ | |
1005 | phys_addr = (desc & 0xfffff000) | (address & 0xfff); | |
1006 | xn = desc & 1; | |
1007 | break; | |
1008 | default: | |
1009 | /* Never happens, but compiler isn't smart enough to tell. */ | |
1010 | abort(); | |
b5ff1b31 | 1011 | } |
9ee6e8bb PB |
1012 | code = 15; |
1013 | } | |
1014 | if (xn && access_type == 2) | |
1015 | goto do_fault; | |
1016 | ||
1017 | *prot = check_ap(env, ap, domain, access_type, is_user); | |
1018 | if (!*prot) { | |
1019 | /* Access permission fault. */ | |
1020 | goto do_fault; | |
b5ff1b31 | 1021 | } |
9ee6e8bb | 1022 | *phys_ptr = phys_addr; |
b5ff1b31 FB |
1023 | return 0; |
1024 | do_fault: | |
1025 | return code | (domain << 4); | |
1026 | } | |
1027 | ||
9ee6e8bb PB |
1028 | static int get_phys_addr_mpu(CPUState *env, uint32_t address, int access_type, |
1029 | int is_user, uint32_t *phys_ptr, int *prot) | |
1030 | { | |
1031 | int n; | |
1032 | uint32_t mask; | |
1033 | uint32_t base; | |
1034 | ||
1035 | *phys_ptr = address; | |
1036 | for (n = 7; n >= 0; n--) { | |
1037 | base = env->cp15.c6_region[n]; | |
1038 | if ((base & 1) == 0) | |
1039 | continue; | |
1040 | mask = 1 << ((base >> 1) & 0x1f); | |
1041 | /* Keep this shift separate from the above to avoid an | |
1042 | (undefined) << 32. */ | |
1043 | mask = (mask << 1) - 1; | |
1044 | if (((base ^ address) & ~mask) == 0) | |
1045 | break; | |
1046 | } | |
1047 | if (n < 0) | |
1048 | return 2; | |
1049 | ||
1050 | if (access_type == 2) { | |
1051 | mask = env->cp15.c5_insn; | |
1052 | } else { | |
1053 | mask = env->cp15.c5_data; | |
1054 | } | |
1055 | mask = (mask >> (n * 4)) & 0xf; | |
1056 | switch (mask) { | |
1057 | case 0: | |
1058 | return 1; | |
1059 | case 1: | |
1060 | if (is_user) | |
1061 | return 1; | |
1062 | *prot = PAGE_READ | PAGE_WRITE; | |
1063 | break; | |
1064 | case 2: | |
1065 | *prot = PAGE_READ; | |
1066 | if (!is_user) | |
1067 | *prot |= PAGE_WRITE; | |
1068 | break; | |
1069 | case 3: | |
1070 | *prot = PAGE_READ | PAGE_WRITE; | |
1071 | break; | |
1072 | case 5: | |
1073 | if (is_user) | |
1074 | return 1; | |
1075 | *prot = PAGE_READ; | |
1076 | break; | |
1077 | case 6: | |
1078 | *prot = PAGE_READ; | |
1079 | break; | |
1080 | default: | |
1081 | /* Bad permission. */ | |
1082 | return 1; | |
1083 | } | |
1084 | return 0; | |
1085 | } | |
1086 | ||
1087 | static inline int get_phys_addr(CPUState *env, uint32_t address, | |
1088 | int access_type, int is_user, | |
1089 | uint32_t *phys_ptr, int *prot) | |
1090 | { | |
1091 | /* Fast Context Switch Extension. */ | |
1092 | if (address < 0x02000000) | |
1093 | address += env->cp15.c13_fcse; | |
1094 | ||
1095 | if ((env->cp15.c1_sys & 1) == 0) { | |
1096 | /* MMU/MPU disabled. */ | |
1097 | *phys_ptr = address; | |
1098 | *prot = PAGE_READ | PAGE_WRITE; | |
1099 | return 0; | |
1100 | } else if (arm_feature(env, ARM_FEATURE_MPU)) { | |
1101 | return get_phys_addr_mpu(env, address, access_type, is_user, phys_ptr, | |
1102 | prot); | |
1103 | } else if (env->cp15.c1_sys & (1 << 23)) { | |
1104 | return get_phys_addr_v6(env, address, access_type, is_user, phys_ptr, | |
1105 | prot); | |
1106 | } else { | |
1107 | return get_phys_addr_v5(env, address, access_type, is_user, phys_ptr, | |
1108 | prot); | |
1109 | } | |
1110 | } | |
1111 | ||
b5ff1b31 | 1112 | int cpu_arm_handle_mmu_fault (CPUState *env, target_ulong address, |
6ebbf390 | 1113 | int access_type, int mmu_idx, int is_softmmu) |
b5ff1b31 FB |
1114 | { |
1115 | uint32_t phys_addr; | |
1116 | int prot; | |
6ebbf390 | 1117 | int ret, is_user; |
b5ff1b31 | 1118 | |
6ebbf390 | 1119 | is_user = mmu_idx == MMU_USER_IDX; |
b5ff1b31 FB |
1120 | ret = get_phys_addr(env, address, access_type, is_user, &phys_addr, &prot); |
1121 | if (ret == 0) { | |
1122 | /* Map a single [sub]page. */ | |
1123 | phys_addr &= ~(uint32_t)0x3ff; | |
1124 | address &= ~(uint32_t)0x3ff; | |
6ebbf390 | 1125 | return tlb_set_page (env, address, phys_addr, prot, mmu_idx, |
b5ff1b31 FB |
1126 | is_softmmu); |
1127 | } | |
1128 | ||
1129 | if (access_type == 2) { | |
1130 | env->cp15.c5_insn = ret; | |
1131 | env->cp15.c6_insn = address; | |
1132 | env->exception_index = EXCP_PREFETCH_ABORT; | |
1133 | } else { | |
1134 | env->cp15.c5_data = ret; | |
9ee6e8bb PB |
1135 | if (access_type == 1 && arm_feature(env, ARM_FEATURE_V6)) |
1136 | env->cp15.c5_data |= (1 << 11); | |
b5ff1b31 FB |
1137 | env->cp15.c6_data = address; |
1138 | env->exception_index = EXCP_DATA_ABORT; | |
1139 | } | |
1140 | return 1; | |
1141 | } | |
1142 | ||
9b3c35e0 | 1143 | target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr) |
b5ff1b31 FB |
1144 | { |
1145 | uint32_t phys_addr; | |
1146 | int prot; | |
1147 | int ret; | |
1148 | ||
1149 | ret = get_phys_addr(env, addr, 0, 0, &phys_addr, &prot); | |
1150 | ||
1151 | if (ret != 0) | |
1152 | return -1; | |
1153 | ||
1154 | return phys_addr; | |
1155 | } | |
1156 | ||
9ee6e8bb PB |
1157 | /* Not really implemented. Need to figure out a sane way of doing this. |
1158 | Maybe add generic watchpoint support and use that. */ | |
1159 | ||
8f8e3aa4 | 1160 | void HELPER(mark_exclusive)(CPUState *env, uint32_t addr) |
9ee6e8bb PB |
1161 | { |
1162 | env->mmon_addr = addr; | |
1163 | } | |
1164 | ||
8f8e3aa4 | 1165 | uint32_t HELPER(test_exclusive)(CPUState *env, uint32_t addr) |
9ee6e8bb PB |
1166 | { |
1167 | return (env->mmon_addr != addr); | |
1168 | } | |
1169 | ||
8f8e3aa4 | 1170 | void HELPER(clrex)(CPUState *env) |
9ee6e8bb PB |
1171 | { |
1172 | env->mmon_addr = -1; | |
1173 | } | |
1174 | ||
8984bd2e | 1175 | void HELPER(set_cp)(CPUState *env, uint32_t insn, uint32_t val) |
c1713132 AZ |
1176 | { |
1177 | int cp_num = (insn >> 8) & 0xf; | |
1178 | int cp_info = (insn >> 5) & 7; | |
1179 | int src = (insn >> 16) & 0xf; | |
1180 | int operand = insn & 0xf; | |
1181 | ||
1182 | if (env->cp[cp_num].cp_write) | |
1183 | env->cp[cp_num].cp_write(env->cp[cp_num].opaque, | |
1184 | cp_info, src, operand, val); | |
1185 | } | |
1186 | ||
8984bd2e | 1187 | uint32_t HELPER(get_cp)(CPUState *env, uint32_t insn) |
c1713132 AZ |
1188 | { |
1189 | int cp_num = (insn >> 8) & 0xf; | |
1190 | int cp_info = (insn >> 5) & 7; | |
1191 | int dest = (insn >> 16) & 0xf; | |
1192 | int operand = insn & 0xf; | |
1193 | ||
1194 | if (env->cp[cp_num].cp_read) | |
1195 | return env->cp[cp_num].cp_read(env->cp[cp_num].opaque, | |
1196 | cp_info, dest, operand); | |
1197 | return 0; | |
1198 | } | |
1199 | ||
ce819861 PB |
1200 | /* Return basic MPU access permission bits. */ |
1201 | static uint32_t simple_mpu_ap_bits(uint32_t val) | |
1202 | { | |
1203 | uint32_t ret; | |
1204 | uint32_t mask; | |
1205 | int i; | |
1206 | ret = 0; | |
1207 | mask = 3; | |
1208 | for (i = 0; i < 16; i += 2) { | |
1209 | ret |= (val >> i) & mask; | |
1210 | mask <<= 2; | |
1211 | } | |
1212 | return ret; | |
1213 | } | |
1214 | ||
1215 | /* Pad basic MPU access permission bits to extended format. */ | |
1216 | static uint32_t extended_mpu_ap_bits(uint32_t val) | |
1217 | { | |
1218 | uint32_t ret; | |
1219 | uint32_t mask; | |
1220 | int i; | |
1221 | ret = 0; | |
1222 | mask = 3; | |
1223 | for (i = 0; i < 16; i += 2) { | |
1224 | ret |= (val & mask) << i; | |
1225 | mask <<= 2; | |
1226 | } | |
1227 | return ret; | |
1228 | } | |
1229 | ||
8984bd2e | 1230 | void HELPER(set_cp15)(CPUState *env, uint32_t insn, uint32_t val) |
b5ff1b31 | 1231 | { |
9ee6e8bb PB |
1232 | int op1; |
1233 | int op2; | |
1234 | int crm; | |
b5ff1b31 | 1235 | |
9ee6e8bb | 1236 | op1 = (insn >> 21) & 7; |
b5ff1b31 | 1237 | op2 = (insn >> 5) & 7; |
ce819861 | 1238 | crm = insn & 0xf; |
b5ff1b31 | 1239 | switch ((insn >> 16) & 0xf) { |
9ee6e8bb PB |
1240 | case 0: |
1241 | if (((insn >> 21) & 7) == 2) { | |
1242 | /* ??? Select cache level. Ignore. */ | |
1243 | return; | |
1244 | } | |
1245 | /* ID codes. */ | |
610c3c8a AZ |
1246 | if (arm_feature(env, ARM_FEATURE_XSCALE)) |
1247 | break; | |
c3d2689d AZ |
1248 | if (arm_feature(env, ARM_FEATURE_OMAPCP)) |
1249 | break; | |
b5ff1b31 FB |
1250 | goto bad_reg; |
1251 | case 1: /* System configuration. */ | |
c3d2689d AZ |
1252 | if (arm_feature(env, ARM_FEATURE_OMAPCP)) |
1253 | op2 = 0; | |
b5ff1b31 FB |
1254 | switch (op2) { |
1255 | case 0: | |
ce819861 | 1256 | if (!arm_feature(env, ARM_FEATURE_XSCALE) || crm == 0) |
c1713132 | 1257 | env->cp15.c1_sys = val; |
b5ff1b31 FB |
1258 | /* ??? Lots of these bits are not implemented. */ |
1259 | /* This may enable/disable the MMU, so do a TLB flush. */ | |
1260 | tlb_flush(env, 1); | |
1261 | break; | |
9ee6e8bb | 1262 | case 1: /* Auxiliary cotrol register. */ |
610c3c8a AZ |
1263 | if (arm_feature(env, ARM_FEATURE_XSCALE)) { |
1264 | env->cp15.c1_xscaleauxcr = val; | |
c1713132 | 1265 | break; |
610c3c8a | 1266 | } |
9ee6e8bb PB |
1267 | /* Not implemented. */ |
1268 | break; | |
b5ff1b31 | 1269 | case 2: |
610c3c8a AZ |
1270 | if (arm_feature(env, ARM_FEATURE_XSCALE)) |
1271 | goto bad_reg; | |
b5ff1b31 FB |
1272 | env->cp15.c1_coproc = val; |
1273 | /* ??? Is this safe when called from within a TB? */ | |
1274 | tb_flush(env); | |
c1713132 | 1275 | break; |
b5ff1b31 FB |
1276 | default: |
1277 | goto bad_reg; | |
1278 | } | |
1279 | break; | |
ce819861 PB |
1280 | case 2: /* MMU Page table control / MPU cache control. */ |
1281 | if (arm_feature(env, ARM_FEATURE_MPU)) { | |
1282 | switch (op2) { | |
1283 | case 0: | |
1284 | env->cp15.c2_data = val; | |
1285 | break; | |
1286 | case 1: | |
1287 | env->cp15.c2_insn = val; | |
1288 | break; | |
1289 | default: | |
1290 | goto bad_reg; | |
1291 | } | |
1292 | } else { | |
9ee6e8bb PB |
1293 | switch (op2) { |
1294 | case 0: | |
1295 | env->cp15.c2_base0 = val; | |
1296 | break; | |
1297 | case 1: | |
1298 | env->cp15.c2_base1 = val; | |
1299 | break; | |
1300 | case 2: | |
1301 | env->cp15.c2_mask = ~(((uint32_t)0xffffffffu) >> val); | |
1302 | break; | |
1303 | default: | |
1304 | goto bad_reg; | |
1305 | } | |
ce819861 | 1306 | } |
b5ff1b31 | 1307 | break; |
ce819861 | 1308 | case 3: /* MMU Domain access control / MPU write buffer control. */ |
b5ff1b31 | 1309 | env->cp15.c3 = val; |
405ee3ad | 1310 | tlb_flush(env, 1); /* Flush TLB as domain not tracked in TLB */ |
b5ff1b31 FB |
1311 | break; |
1312 | case 4: /* Reserved. */ | |
1313 | goto bad_reg; | |
ce819861 | 1314 | case 5: /* MMU Fault status / MPU access permission. */ |
c3d2689d AZ |
1315 | if (arm_feature(env, ARM_FEATURE_OMAPCP)) |
1316 | op2 = 0; | |
b5ff1b31 FB |
1317 | switch (op2) { |
1318 | case 0: | |
ce819861 PB |
1319 | if (arm_feature(env, ARM_FEATURE_MPU)) |
1320 | val = extended_mpu_ap_bits(val); | |
b5ff1b31 FB |
1321 | env->cp15.c5_data = val; |
1322 | break; | |
1323 | case 1: | |
ce819861 PB |
1324 | if (arm_feature(env, ARM_FEATURE_MPU)) |
1325 | val = extended_mpu_ap_bits(val); | |
b5ff1b31 FB |
1326 | env->cp15.c5_insn = val; |
1327 | break; | |
ce819861 PB |
1328 | case 2: |
1329 | if (!arm_feature(env, ARM_FEATURE_MPU)) | |
1330 | goto bad_reg; | |
1331 | env->cp15.c5_data = val; | |
b5ff1b31 | 1332 | break; |
ce819861 PB |
1333 | case 3: |
1334 | if (!arm_feature(env, ARM_FEATURE_MPU)) | |
1335 | goto bad_reg; | |
1336 | env->cp15.c5_insn = val; | |
b5ff1b31 FB |
1337 | break; |
1338 | default: | |
1339 | goto bad_reg; | |
1340 | } | |
1341 | break; | |
ce819861 PB |
1342 | case 6: /* MMU Fault address / MPU base/size. */ |
1343 | if (arm_feature(env, ARM_FEATURE_MPU)) { | |
1344 | if (crm >= 8) | |
1345 | goto bad_reg; | |
1346 | env->cp15.c6_region[crm] = val; | |
1347 | } else { | |
c3d2689d AZ |
1348 | if (arm_feature(env, ARM_FEATURE_OMAPCP)) |
1349 | op2 = 0; | |
ce819861 PB |
1350 | switch (op2) { |
1351 | case 0: | |
1352 | env->cp15.c6_data = val; | |
1353 | break; | |
9ee6e8bb PB |
1354 | case 1: /* ??? This is WFAR on armv6 */ |
1355 | case 2: | |
ce819861 PB |
1356 | env->cp15.c6_insn = val; |
1357 | break; | |
1358 | default: | |
1359 | goto bad_reg; | |
1360 | } | |
1361 | } | |
1362 | break; | |
b5ff1b31 | 1363 | case 7: /* Cache control. */ |
c3d2689d AZ |
1364 | env->cp15.c15_i_max = 0x000; |
1365 | env->cp15.c15_i_min = 0xff0; | |
b5ff1b31 | 1366 | /* No cache, so nothing to do. */ |
9ee6e8bb | 1367 | /* ??? MPCore has VA to PA translation functions. */ |
b5ff1b31 FB |
1368 | break; |
1369 | case 8: /* MMU TLB control. */ | |
1370 | switch (op2) { | |
1371 | case 0: /* Invalidate all. */ | |
1372 | tlb_flush(env, 0); | |
1373 | break; | |
1374 | case 1: /* Invalidate single TLB entry. */ | |
1375 | #if 0 | |
1376 | /* ??? This is wrong for large pages and sections. */ | |
1377 | /* As an ugly hack to make linux work we always flush a 4K | |
1378 | pages. */ | |
1379 | val &= 0xfffff000; | |
1380 | tlb_flush_page(env, val); | |
1381 | tlb_flush_page(env, val + 0x400); | |
1382 | tlb_flush_page(env, val + 0x800); | |
1383 | tlb_flush_page(env, val + 0xc00); | |
1384 | #else | |
1385 | tlb_flush(env, 1); | |
1386 | #endif | |
1387 | break; | |
9ee6e8bb PB |
1388 | case 2: /* Invalidate on ASID. */ |
1389 | tlb_flush(env, val == 0); | |
1390 | break; | |
1391 | case 3: /* Invalidate single entry on MVA. */ | |
1392 | /* ??? This is like case 1, but ignores ASID. */ | |
1393 | tlb_flush(env, 1); | |
1394 | break; | |
b5ff1b31 FB |
1395 | default: |
1396 | goto bad_reg; | |
1397 | } | |
1398 | break; | |
ce819861 | 1399 | case 9: |
c3d2689d AZ |
1400 | if (arm_feature(env, ARM_FEATURE_OMAPCP)) |
1401 | break; | |
ce819861 PB |
1402 | switch (crm) { |
1403 | case 0: /* Cache lockdown. */ | |
9ee6e8bb PB |
1404 | switch (op1) { |
1405 | case 0: /* L1 cache. */ | |
1406 | switch (op2) { | |
1407 | case 0: | |
1408 | env->cp15.c9_data = val; | |
1409 | break; | |
1410 | case 1: | |
1411 | env->cp15.c9_insn = val; | |
1412 | break; | |
1413 | default: | |
1414 | goto bad_reg; | |
1415 | } | |
1416 | break; | |
1417 | case 1: /* L2 cache. */ | |
1418 | /* Ignore writes to L2 lockdown/auxiliary registers. */ | |
1419 | break; | |
1420 | default: | |
1421 | goto bad_reg; | |
1422 | } | |
1423 | break; | |
ce819861 PB |
1424 | case 1: /* TCM memory region registers. */ |
1425 | /* Not implemented. */ | |
1426 | goto bad_reg; | |
b5ff1b31 FB |
1427 | default: |
1428 | goto bad_reg; | |
1429 | } | |
1430 | break; | |
1431 | case 10: /* MMU TLB lockdown. */ | |
1432 | /* ??? TLB lockdown not implemented. */ | |
1433 | break; | |
b5ff1b31 FB |
1434 | case 12: /* Reserved. */ |
1435 | goto bad_reg; | |
1436 | case 13: /* Process ID. */ | |
1437 | switch (op2) { | |
1438 | case 0: | |
d07edbfa PB |
1439 | /* Unlike real hardware the qemu TLB uses virtual addresses, |
1440 | not modified virtual addresses, so this causes a TLB flush. | |
1441 | */ | |
1442 | if (env->cp15.c13_fcse != val) | |
1443 | tlb_flush(env, 1); | |
1444 | env->cp15.c13_fcse = val; | |
b5ff1b31 FB |
1445 | break; |
1446 | case 1: | |
d07edbfa | 1447 | /* This changes the ASID, so do a TLB flush. */ |
ce819861 PB |
1448 | if (env->cp15.c13_context != val |
1449 | && !arm_feature(env, ARM_FEATURE_MPU)) | |
d07edbfa PB |
1450 | tlb_flush(env, 0); |
1451 | env->cp15.c13_context = val; | |
b5ff1b31 | 1452 | break; |
9ee6e8bb PB |
1453 | case 2: |
1454 | env->cp15.c13_tls1 = val; | |
1455 | break; | |
1456 | case 3: | |
1457 | env->cp15.c13_tls2 = val; | |
1458 | break; | |
1459 | case 4: | |
1460 | env->cp15.c13_tls3 = val; | |
1461 | break; | |
b5ff1b31 FB |
1462 | default: |
1463 | goto bad_reg; | |
1464 | } | |
1465 | break; | |
1466 | case 14: /* Reserved. */ | |
1467 | goto bad_reg; | |
1468 | case 15: /* Implementation specific. */ | |
c1713132 | 1469 | if (arm_feature(env, ARM_FEATURE_XSCALE)) { |
ce819861 | 1470 | if (op2 == 0 && crm == 1) { |
2e23213f AZ |
1471 | if (env->cp15.c15_cpar != (val & 0x3fff)) { |
1472 | /* Changes cp0 to cp13 behavior, so needs a TB flush. */ | |
1473 | tb_flush(env); | |
1474 | env->cp15.c15_cpar = val & 0x3fff; | |
1475 | } | |
c1713132 AZ |
1476 | break; |
1477 | } | |
1478 | goto bad_reg; | |
1479 | } | |
c3d2689d AZ |
1480 | if (arm_feature(env, ARM_FEATURE_OMAPCP)) { |
1481 | switch (crm) { | |
1482 | case 0: | |
1483 | break; | |
1484 | case 1: /* Set TI925T configuration. */ | |
1485 | env->cp15.c15_ticonfig = val & 0xe7; | |
1486 | env->cp15.c0_cpuid = (val & (1 << 5)) ? /* OS_TYPE bit */ | |
1487 | ARM_CPUID_TI915T : ARM_CPUID_TI925T; | |
1488 | break; | |
1489 | case 2: /* Set I_max. */ | |
1490 | env->cp15.c15_i_max = val; | |
1491 | break; | |
1492 | case 3: /* Set I_min. */ | |
1493 | env->cp15.c15_i_min = val; | |
1494 | break; | |
1495 | case 4: /* Set thread-ID. */ | |
1496 | env->cp15.c15_threadid = val & 0xffff; | |
1497 | break; | |
1498 | case 8: /* Wait-for-interrupt (deprecated). */ | |
1499 | cpu_interrupt(env, CPU_INTERRUPT_HALT); | |
1500 | break; | |
1501 | default: | |
1502 | goto bad_reg; | |
1503 | } | |
1504 | } | |
b5ff1b31 FB |
1505 | break; |
1506 | } | |
1507 | return; | |
1508 | bad_reg: | |
1509 | /* ??? For debugging only. Should raise illegal instruction exception. */ | |
9ee6e8bb PB |
1510 | cpu_abort(env, "Unimplemented cp15 register write (c%d, c%d, {%d, %d})\n", |
1511 | (insn >> 16) & 0xf, crm, op1, op2); | |
b5ff1b31 FB |
1512 | } |
1513 | ||
8984bd2e | 1514 | uint32_t HELPER(get_cp15)(CPUState *env, uint32_t insn) |
b5ff1b31 | 1515 | { |
9ee6e8bb PB |
1516 | int op1; |
1517 | int op2; | |
1518 | int crm; | |
b5ff1b31 | 1519 | |
9ee6e8bb | 1520 | op1 = (insn >> 21) & 7; |
b5ff1b31 | 1521 | op2 = (insn >> 5) & 7; |
c3d2689d | 1522 | crm = insn & 0xf; |
b5ff1b31 FB |
1523 | switch ((insn >> 16) & 0xf) { |
1524 | case 0: /* ID codes. */ | |
9ee6e8bb PB |
1525 | switch (op1) { |
1526 | case 0: | |
1527 | switch (crm) { | |
1528 | case 0: | |
1529 | switch (op2) { | |
1530 | case 0: /* Device ID. */ | |
1531 | return env->cp15.c0_cpuid; | |
1532 | case 1: /* Cache Type. */ | |
1533 | return env->cp15.c0_cachetype; | |
1534 | case 2: /* TCM status. */ | |
1535 | return 0; | |
1536 | case 3: /* TLB type register. */ | |
1537 | return 0; /* No lockable TLB entries. */ | |
1538 | case 5: /* CPU ID */ | |
1539 | return env->cpu_index; | |
1540 | default: | |
1541 | goto bad_reg; | |
1542 | } | |
1543 | case 1: | |
1544 | if (!arm_feature(env, ARM_FEATURE_V6)) | |
1545 | goto bad_reg; | |
1546 | return env->cp15.c0_c1[op2]; | |
1547 | case 2: | |
1548 | if (!arm_feature(env, ARM_FEATURE_V6)) | |
1549 | goto bad_reg; | |
1550 | return env->cp15.c0_c2[op2]; | |
1551 | case 3: case 4: case 5: case 6: case 7: | |
1552 | return 0; | |
1553 | default: | |
1554 | goto bad_reg; | |
1555 | } | |
1556 | case 1: | |
1557 | /* These registers aren't documented on arm11 cores. However | |
1558 | Linux looks at them anyway. */ | |
1559 | if (!arm_feature(env, ARM_FEATURE_V6)) | |
1560 | goto bad_reg; | |
1561 | if (crm != 0) | |
1562 | goto bad_reg; | |
610c3c8a AZ |
1563 | if (arm_feature(env, ARM_FEATURE_XSCALE)) |
1564 | goto bad_reg; | |
b5ff1b31 | 1565 | return 0; |
9ee6e8bb PB |
1566 | default: |
1567 | goto bad_reg; | |
b5ff1b31 FB |
1568 | } |
1569 | case 1: /* System configuration. */ | |
c3d2689d AZ |
1570 | if (arm_feature(env, ARM_FEATURE_OMAPCP)) |
1571 | op2 = 0; | |
b5ff1b31 FB |
1572 | switch (op2) { |
1573 | case 0: /* Control register. */ | |
1574 | return env->cp15.c1_sys; | |
1575 | case 1: /* Auxiliary control register. */ | |
c1713132 | 1576 | if (arm_feature(env, ARM_FEATURE_XSCALE)) |
610c3c8a | 1577 | return env->cp15.c1_xscaleauxcr; |
9ee6e8bb PB |
1578 | if (!arm_feature(env, ARM_FEATURE_AUXCR)) |
1579 | goto bad_reg; | |
1580 | switch (ARM_CPUID(env)) { | |
1581 | case ARM_CPUID_ARM1026: | |
1582 | return 1; | |
1583 | case ARM_CPUID_ARM1136: | |
1584 | return 7; | |
1585 | case ARM_CPUID_ARM11MPCORE: | |
1586 | return 1; | |
1587 | case ARM_CPUID_CORTEXA8: | |
1588 | return 0; | |
1589 | default: | |
1590 | goto bad_reg; | |
1591 | } | |
b5ff1b31 | 1592 | case 2: /* Coprocessor access register. */ |
610c3c8a AZ |
1593 | if (arm_feature(env, ARM_FEATURE_XSCALE)) |
1594 | goto bad_reg; | |
b5ff1b31 FB |
1595 | return env->cp15.c1_coproc; |
1596 | default: | |
1597 | goto bad_reg; | |
1598 | } | |
ce819861 PB |
1599 | case 2: /* MMU Page table control / MPU cache control. */ |
1600 | if (arm_feature(env, ARM_FEATURE_MPU)) { | |
1601 | switch (op2) { | |
1602 | case 0: | |
1603 | return env->cp15.c2_data; | |
1604 | break; | |
1605 | case 1: | |
1606 | return env->cp15.c2_insn; | |
1607 | break; | |
1608 | default: | |
1609 | goto bad_reg; | |
1610 | } | |
1611 | } else { | |
9ee6e8bb PB |
1612 | switch (op2) { |
1613 | case 0: | |
1614 | return env->cp15.c2_base0; | |
1615 | case 1: | |
1616 | return env->cp15.c2_base1; | |
1617 | case 2: | |
1618 | { | |
1619 | int n; | |
1620 | uint32_t mask; | |
1621 | n = 0; | |
1622 | mask = env->cp15.c2_mask; | |
1623 | while (mask) { | |
1624 | n++; | |
1625 | mask <<= 1; | |
1626 | } | |
1627 | return n; | |
1628 | } | |
1629 | default: | |
1630 | goto bad_reg; | |
1631 | } | |
1632 | } | |
ce819861 | 1633 | case 3: /* MMU Domain access control / MPU write buffer control. */ |
b5ff1b31 FB |
1634 | return env->cp15.c3; |
1635 | case 4: /* Reserved. */ | |
1636 | goto bad_reg; | |
ce819861 | 1637 | case 5: /* MMU Fault status / MPU access permission. */ |
c3d2689d AZ |
1638 | if (arm_feature(env, ARM_FEATURE_OMAPCP)) |
1639 | op2 = 0; | |
b5ff1b31 FB |
1640 | switch (op2) { |
1641 | case 0: | |
ce819861 PB |
1642 | if (arm_feature(env, ARM_FEATURE_MPU)) |
1643 | return simple_mpu_ap_bits(env->cp15.c5_data); | |
b5ff1b31 FB |
1644 | return env->cp15.c5_data; |
1645 | case 1: | |
ce819861 PB |
1646 | if (arm_feature(env, ARM_FEATURE_MPU)) |
1647 | return simple_mpu_ap_bits(env->cp15.c5_data); | |
1648 | return env->cp15.c5_insn; | |
1649 | case 2: | |
1650 | if (!arm_feature(env, ARM_FEATURE_MPU)) | |
1651 | goto bad_reg; | |
1652 | return env->cp15.c5_data; | |
1653 | case 3: | |
1654 | if (!arm_feature(env, ARM_FEATURE_MPU)) | |
1655 | goto bad_reg; | |
b5ff1b31 FB |
1656 | return env->cp15.c5_insn; |
1657 | default: | |
1658 | goto bad_reg; | |
1659 | } | |
9ee6e8bb | 1660 | case 6: /* MMU Fault address. */ |
ce819861 | 1661 | if (arm_feature(env, ARM_FEATURE_MPU)) { |
9ee6e8bb | 1662 | if (crm >= 8) |
ce819861 | 1663 | goto bad_reg; |
9ee6e8bb | 1664 | return env->cp15.c6_region[crm]; |
ce819861 | 1665 | } else { |
c3d2689d AZ |
1666 | if (arm_feature(env, ARM_FEATURE_OMAPCP)) |
1667 | op2 = 0; | |
9ee6e8bb PB |
1668 | switch (op2) { |
1669 | case 0: | |
1670 | return env->cp15.c6_data; | |
1671 | case 1: | |
1672 | if (arm_feature(env, ARM_FEATURE_V6)) { | |
1673 | /* Watchpoint Fault Adrress. */ | |
1674 | return 0; /* Not implemented. */ | |
1675 | } else { | |
1676 | /* Instruction Fault Adrress. */ | |
1677 | /* Arm9 doesn't have an IFAR, but implementing it anyway | |
1678 | shouldn't do any harm. */ | |
1679 | return env->cp15.c6_insn; | |
1680 | } | |
1681 | case 2: | |
1682 | if (arm_feature(env, ARM_FEATURE_V6)) { | |
1683 | /* Instruction Fault Adrress. */ | |
1684 | return env->cp15.c6_insn; | |
1685 | } else { | |
1686 | goto bad_reg; | |
1687 | } | |
1688 | default: | |
1689 | goto bad_reg; | |
1690 | } | |
b5ff1b31 FB |
1691 | } |
1692 | case 7: /* Cache control. */ | |
6fbe23d5 PB |
1693 | /* FIXME: Should only clear Z flag if destination is r15. */ |
1694 | env->ZF = 0; | |
b5ff1b31 FB |
1695 | return 0; |
1696 | case 8: /* MMU TLB control. */ | |
1697 | goto bad_reg; | |
1698 | case 9: /* Cache lockdown. */ | |
9ee6e8bb PB |
1699 | switch (op1) { |
1700 | case 0: /* L1 cache. */ | |
1701 | if (arm_feature(env, ARM_FEATURE_OMAPCP)) | |
1702 | return 0; | |
1703 | switch (op2) { | |
1704 | case 0: | |
1705 | return env->cp15.c9_data; | |
1706 | case 1: | |
1707 | return env->cp15.c9_insn; | |
1708 | default: | |
1709 | goto bad_reg; | |
1710 | } | |
1711 | case 1: /* L2 cache */ | |
1712 | if (crm != 0) | |
1713 | goto bad_reg; | |
1714 | /* L2 Lockdown and Auxiliary control. */ | |
c3d2689d | 1715 | return 0; |
b5ff1b31 FB |
1716 | default: |
1717 | goto bad_reg; | |
1718 | } | |
1719 | case 10: /* MMU TLB lockdown. */ | |
1720 | /* ??? TLB lockdown not implemented. */ | |
1721 | return 0; | |
1722 | case 11: /* TCM DMA control. */ | |
1723 | case 12: /* Reserved. */ | |
1724 | goto bad_reg; | |
1725 | case 13: /* Process ID. */ | |
1726 | switch (op2) { | |
1727 | case 0: | |
1728 | return env->cp15.c13_fcse; | |
1729 | case 1: | |
1730 | return env->cp15.c13_context; | |
9ee6e8bb PB |
1731 | case 2: |
1732 | return env->cp15.c13_tls1; | |
1733 | case 3: | |
1734 | return env->cp15.c13_tls2; | |
1735 | case 4: | |
1736 | return env->cp15.c13_tls3; | |
b5ff1b31 FB |
1737 | default: |
1738 | goto bad_reg; | |
1739 | } | |
1740 | case 14: /* Reserved. */ | |
1741 | goto bad_reg; | |
1742 | case 15: /* Implementation specific. */ | |
c1713132 | 1743 | if (arm_feature(env, ARM_FEATURE_XSCALE)) { |
c3d2689d | 1744 | if (op2 == 0 && crm == 1) |
c1713132 AZ |
1745 | return env->cp15.c15_cpar; |
1746 | ||
1747 | goto bad_reg; | |
1748 | } | |
c3d2689d AZ |
1749 | if (arm_feature(env, ARM_FEATURE_OMAPCP)) { |
1750 | switch (crm) { | |
1751 | case 0: | |
1752 | return 0; | |
1753 | case 1: /* Read TI925T configuration. */ | |
1754 | return env->cp15.c15_ticonfig; | |
1755 | case 2: /* Read I_max. */ | |
1756 | return env->cp15.c15_i_max; | |
1757 | case 3: /* Read I_min. */ | |
1758 | return env->cp15.c15_i_min; | |
1759 | case 4: /* Read thread-ID. */ | |
1760 | return env->cp15.c15_threadid; | |
1761 | case 8: /* TI925T_status */ | |
1762 | return 0; | |
1763 | } | |
1764 | goto bad_reg; | |
1765 | } | |
b5ff1b31 FB |
1766 | return 0; |
1767 | } | |
1768 | bad_reg: | |
1769 | /* ??? For debugging only. Should raise illegal instruction exception. */ | |
9ee6e8bb PB |
1770 | cpu_abort(env, "Unimplemented cp15 register read (c%d, c%d, {%d, %d})\n", |
1771 | (insn >> 16) & 0xf, crm, op1, op2); | |
b5ff1b31 FB |
1772 | return 0; |
1773 | } | |
1774 | ||
b0109805 | 1775 | void HELPER(set_r13_banked)(CPUState *env, uint32_t mode, uint32_t val) |
9ee6e8bb PB |
1776 | { |
1777 | env->banked_r13[bank_number(mode)] = val; | |
1778 | } | |
1779 | ||
b0109805 | 1780 | uint32_t HELPER(get_r13_banked)(CPUState *env, uint32_t mode) |
9ee6e8bb PB |
1781 | { |
1782 | return env->banked_r13[bank_number(mode)]; | |
1783 | } | |
1784 | ||
8984bd2e | 1785 | uint32_t HELPER(v7m_mrs)(CPUState *env, uint32_t reg) |
9ee6e8bb PB |
1786 | { |
1787 | switch (reg) { | |
1788 | case 0: /* APSR */ | |
1789 | return xpsr_read(env) & 0xf8000000; | |
1790 | case 1: /* IAPSR */ | |
1791 | return xpsr_read(env) & 0xf80001ff; | |
1792 | case 2: /* EAPSR */ | |
1793 | return xpsr_read(env) & 0xff00fc00; | |
1794 | case 3: /* xPSR */ | |
1795 | return xpsr_read(env) & 0xff00fdff; | |
1796 | case 5: /* IPSR */ | |
1797 | return xpsr_read(env) & 0x000001ff; | |
1798 | case 6: /* EPSR */ | |
1799 | return xpsr_read(env) & 0x0700fc00; | |
1800 | case 7: /* IEPSR */ | |
1801 | return xpsr_read(env) & 0x0700edff; | |
1802 | case 8: /* MSP */ | |
1803 | return env->v7m.current_sp ? env->v7m.other_sp : env->regs[13]; | |
1804 | case 9: /* PSP */ | |
1805 | return env->v7m.current_sp ? env->regs[13] : env->v7m.other_sp; | |
1806 | case 16: /* PRIMASK */ | |
1807 | return (env->uncached_cpsr & CPSR_I) != 0; | |
1808 | case 17: /* FAULTMASK */ | |
1809 | return (env->uncached_cpsr & CPSR_F) != 0; | |
1810 | case 18: /* BASEPRI */ | |
1811 | case 19: /* BASEPRI_MAX */ | |
1812 | return env->v7m.basepri; | |
1813 | case 20: /* CONTROL */ | |
1814 | return env->v7m.control; | |
1815 | default: | |
1816 | /* ??? For debugging only. */ | |
1817 | cpu_abort(env, "Unimplemented system register read (%d)\n", reg); | |
1818 | return 0; | |
1819 | } | |
1820 | } | |
1821 | ||
8984bd2e | 1822 | void HELPER(v7m_msr)(CPUState *env, uint32_t reg, uint32_t val) |
9ee6e8bb PB |
1823 | { |
1824 | switch (reg) { | |
1825 | case 0: /* APSR */ | |
1826 | xpsr_write(env, val, 0xf8000000); | |
1827 | break; | |
1828 | case 1: /* IAPSR */ | |
1829 | xpsr_write(env, val, 0xf8000000); | |
1830 | break; | |
1831 | case 2: /* EAPSR */ | |
1832 | xpsr_write(env, val, 0xfe00fc00); | |
1833 | break; | |
1834 | case 3: /* xPSR */ | |
1835 | xpsr_write(env, val, 0xfe00fc00); | |
1836 | break; | |
1837 | case 5: /* IPSR */ | |
1838 | /* IPSR bits are readonly. */ | |
1839 | break; | |
1840 | case 6: /* EPSR */ | |
1841 | xpsr_write(env, val, 0x0600fc00); | |
1842 | break; | |
1843 | case 7: /* IEPSR */ | |
1844 | xpsr_write(env, val, 0x0600fc00); | |
1845 | break; | |
1846 | case 8: /* MSP */ | |
1847 | if (env->v7m.current_sp) | |
1848 | env->v7m.other_sp = val; | |
1849 | else | |
1850 | env->regs[13] = val; | |
1851 | break; | |
1852 | case 9: /* PSP */ | |
1853 | if (env->v7m.current_sp) | |
1854 | env->regs[13] = val; | |
1855 | else | |
1856 | env->v7m.other_sp = val; | |
1857 | break; | |
1858 | case 16: /* PRIMASK */ | |
1859 | if (val & 1) | |
1860 | env->uncached_cpsr |= CPSR_I; | |
1861 | else | |
1862 | env->uncached_cpsr &= ~CPSR_I; | |
1863 | break; | |
1864 | case 17: /* FAULTMASK */ | |
1865 | if (val & 1) | |
1866 | env->uncached_cpsr |= CPSR_F; | |
1867 | else | |
1868 | env->uncached_cpsr &= ~CPSR_F; | |
1869 | break; | |
1870 | case 18: /* BASEPRI */ | |
1871 | env->v7m.basepri = val & 0xff; | |
1872 | break; | |
1873 | case 19: /* BASEPRI_MAX */ | |
1874 | val &= 0xff; | |
1875 | if (val != 0 && (val < env->v7m.basepri || env->v7m.basepri == 0)) | |
1876 | env->v7m.basepri = val; | |
1877 | break; | |
1878 | case 20: /* CONTROL */ | |
1879 | env->v7m.control = val & 3; | |
1880 | switch_v7m_sp(env, (val & 2) != 0); | |
1881 | break; | |
1882 | default: | |
1883 | /* ??? For debugging only. */ | |
1884 | cpu_abort(env, "Unimplemented system register write (%d)\n", reg); | |
1885 | return; | |
1886 | } | |
1887 | } | |
1888 | ||
c1713132 AZ |
1889 | void cpu_arm_set_cp_io(CPUARMState *env, int cpnum, |
1890 | ARMReadCPFunc *cp_read, ARMWriteCPFunc *cp_write, | |
1891 | void *opaque) | |
1892 | { | |
1893 | if (cpnum < 0 || cpnum > 14) { | |
1894 | cpu_abort(env, "Bad coprocessor number: %i\n", cpnum); | |
1895 | return; | |
1896 | } | |
1897 | ||
1898 | env->cp[cpnum].cp_read = cp_read; | |
1899 | env->cp[cpnum].cp_write = cp_write; | |
1900 | env->cp[cpnum].opaque = opaque; | |
1901 | } | |
1902 | ||
b5ff1b31 | 1903 | #endif |
6ddbc6e4 PB |
1904 | |
1905 | /* Note that signed overflow is undefined in C. The following routines are | |
1906 | careful to use unsigned types where modulo arithmetic is required. | |
1907 | Failure to do so _will_ break on newer gcc. */ | |
1908 | ||
1909 | /* Signed saturating arithmetic. */ | |
1910 | ||
1911 | /* Perform 16-bit signed satruating addition. */ | |
1912 | static inline uint16_t add16_sat(uint16_t a, uint16_t b) | |
1913 | { | |
1914 | uint16_t res; | |
1915 | ||
1916 | res = a + b; | |
1917 | if (((res ^ a) & 0x8000) && !((a ^ b) & 0x8000)) { | |
1918 | if (a & 0x8000) | |
1919 | res = 0x8000; | |
1920 | else | |
1921 | res = 0x7fff; | |
1922 | } | |
1923 | return res; | |
1924 | } | |
1925 | ||
1926 | /* Perform 8-bit signed satruating addition. */ | |
1927 | static inline uint8_t add8_sat(uint8_t a, uint8_t b) | |
1928 | { | |
1929 | uint8_t res; | |
1930 | ||
1931 | res = a + b; | |
1932 | if (((res ^ a) & 0x80) && !((a ^ b) & 0x80)) { | |
1933 | if (a & 0x80) | |
1934 | res = 0x80; | |
1935 | else | |
1936 | res = 0x7f; | |
1937 | } | |
1938 | return res; | |
1939 | } | |
1940 | ||
1941 | /* Perform 16-bit signed satruating subtraction. */ | |
1942 | static inline uint16_t sub16_sat(uint16_t a, uint16_t b) | |
1943 | { | |
1944 | uint16_t res; | |
1945 | ||
1946 | res = a - b; | |
1947 | if (((res ^ a) & 0x8000) && ((a ^ b) & 0x8000)) { | |
1948 | if (a & 0x8000) | |
1949 | res = 0x8000; | |
1950 | else | |
1951 | res = 0x7fff; | |
1952 | } | |
1953 | return res; | |
1954 | } | |
1955 | ||
1956 | /* Perform 8-bit signed satruating subtraction. */ | |
1957 | static inline uint8_t sub8_sat(uint8_t a, uint8_t b) | |
1958 | { | |
1959 | uint8_t res; | |
1960 | ||
1961 | res = a - b; | |
1962 | if (((res ^ a) & 0x80) && ((a ^ b) & 0x80)) { | |
1963 | if (a & 0x80) | |
1964 | res = 0x80; | |
1965 | else | |
1966 | res = 0x7f; | |
1967 | } | |
1968 | return res; | |
1969 | } | |
1970 | ||
1971 | #define ADD16(a, b, n) RESULT(add16_sat(a, b), n, 16); | |
1972 | #define SUB16(a, b, n) RESULT(sub16_sat(a, b), n, 16); | |
1973 | #define ADD8(a, b, n) RESULT(add8_sat(a, b), n, 8); | |
1974 | #define SUB8(a, b, n) RESULT(sub8_sat(a, b), n, 8); | |
1975 | #define PFX q | |
1976 | ||
1977 | #include "op_addsub.h" | |
1978 | ||
1979 | /* Unsigned saturating arithmetic. */ | |
1980 | static inline uint16_t add16_usat(uint16_t a, uint8_t b) | |
1981 | { | |
1982 | uint16_t res; | |
1983 | res = a + b; | |
1984 | if (res < a) | |
1985 | res = 0xffff; | |
1986 | return res; | |
1987 | } | |
1988 | ||
1989 | static inline uint16_t sub16_usat(uint16_t a, uint8_t b) | |
1990 | { | |
1991 | if (a < b) | |
1992 | return a - b; | |
1993 | else | |
1994 | return 0; | |
1995 | } | |
1996 | ||
1997 | static inline uint8_t add8_usat(uint8_t a, uint8_t b) | |
1998 | { | |
1999 | uint8_t res; | |
2000 | res = a + b; | |
2001 | if (res < a) | |
2002 | res = 0xff; | |
2003 | return res; | |
2004 | } | |
2005 | ||
2006 | static inline uint8_t sub8_usat(uint8_t a, uint8_t b) | |
2007 | { | |
2008 | if (a < b) | |
2009 | return a - b; | |
2010 | else | |
2011 | return 0; | |
2012 | } | |
2013 | ||
2014 | #define ADD16(a, b, n) RESULT(add16_usat(a, b), n, 16); | |
2015 | #define SUB16(a, b, n) RESULT(sub16_usat(a, b), n, 16); | |
2016 | #define ADD8(a, b, n) RESULT(add8_usat(a, b), n, 8); | |
2017 | #define SUB8(a, b, n) RESULT(sub8_usat(a, b), n, 8); | |
2018 | #define PFX uq | |
2019 | ||
2020 | #include "op_addsub.h" | |
2021 | ||
2022 | /* Signed modulo arithmetic. */ | |
2023 | #define SARITH16(a, b, n, op) do { \ | |
2024 | int32_t sum; \ | |
2025 | sum = (int16_t)((uint16_t)(a) op (uint16_t)(b)); \ | |
2026 | RESULT(sum, n, 16); \ | |
2027 | if (sum >= 0) \ | |
2028 | ge |= 3 << (n * 2); \ | |
2029 | } while(0) | |
2030 | ||
2031 | #define SARITH8(a, b, n, op) do { \ | |
2032 | int32_t sum; \ | |
2033 | sum = (int8_t)((uint8_t)(a) op (uint8_t)(b)); \ | |
2034 | RESULT(sum, n, 8); \ | |
2035 | if (sum >= 0) \ | |
2036 | ge |= 1 << n; \ | |
2037 | } while(0) | |
2038 | ||
2039 | ||
2040 | #define ADD16(a, b, n) SARITH16(a, b, n, +) | |
2041 | #define SUB16(a, b, n) SARITH16(a, b, n, -) | |
2042 | #define ADD8(a, b, n) SARITH8(a, b, n, +) | |
2043 | #define SUB8(a, b, n) SARITH8(a, b, n, -) | |
2044 | #define PFX s | |
2045 | #define ARITH_GE | |
2046 | ||
2047 | #include "op_addsub.h" | |
2048 | ||
2049 | /* Unsigned modulo arithmetic. */ | |
2050 | #define ADD16(a, b, n) do { \ | |
2051 | uint32_t sum; \ | |
2052 | sum = (uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b); \ | |
2053 | RESULT(sum, n, 16); \ | |
2054 | if ((sum >> 16) == 0) \ | |
2055 | ge |= 3 << (n * 2); \ | |
2056 | } while(0) | |
2057 | ||
2058 | #define ADD8(a, b, n) do { \ | |
2059 | uint32_t sum; \ | |
2060 | sum = (uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b); \ | |
2061 | RESULT(sum, n, 8); \ | |
2062 | if ((sum >> 8) == 0) \ | |
2063 | ge |= 3 << (n * 2); \ | |
2064 | } while(0) | |
2065 | ||
2066 | #define SUB16(a, b, n) do { \ | |
2067 | uint32_t sum; \ | |
2068 | sum = (uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b); \ | |
2069 | RESULT(sum, n, 16); \ | |
2070 | if ((sum >> 16) == 0) \ | |
2071 | ge |= 3 << (n * 2); \ | |
2072 | } while(0) | |
2073 | ||
2074 | #define SUB8(a, b, n) do { \ | |
2075 | uint32_t sum; \ | |
2076 | sum = (uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b); \ | |
2077 | RESULT(sum, n, 8); \ | |
2078 | if ((sum >> 8) == 0) \ | |
2079 | ge |= 3 << (n * 2); \ | |
2080 | } while(0) | |
2081 | ||
2082 | #define PFX u | |
2083 | #define ARITH_GE | |
2084 | ||
2085 | #include "op_addsub.h" | |
2086 | ||
2087 | /* Halved signed arithmetic. */ | |
2088 | #define ADD16(a, b, n) \ | |
2089 | RESULT(((int32_t)(int16_t)(a) + (int32_t)(int16_t)(b)) >> 1, n, 16) | |
2090 | #define SUB16(a, b, n) \ | |
2091 | RESULT(((int32_t)(int16_t)(a) - (int32_t)(int16_t)(b)) >> 1, n, 16) | |
2092 | #define ADD8(a, b, n) \ | |
2093 | RESULT(((int32_t)(int8_t)(a) + (int32_t)(int8_t)(b)) >> 1, n, 8) | |
2094 | #define SUB8(a, b, n) \ | |
2095 | RESULT(((int32_t)(int8_t)(a) - (int32_t)(int8_t)(b)) >> 1, n, 8) | |
2096 | #define PFX sh | |
2097 | ||
2098 | #include "op_addsub.h" | |
2099 | ||
2100 | /* Halved unsigned arithmetic. */ | |
2101 | #define ADD16(a, b, n) \ | |
2102 | RESULT(((uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b)) >> 1, n, 16) | |
2103 | #define SUB16(a, b, n) \ | |
2104 | RESULT(((uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b)) >> 1, n, 16) | |
2105 | #define ADD8(a, b, n) \ | |
2106 | RESULT(((uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b)) >> 1, n, 8) | |
2107 | #define SUB8(a, b, n) \ | |
2108 | RESULT(((uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b)) >> 1, n, 8) | |
2109 | #define PFX uh | |
2110 | ||
2111 | #include "op_addsub.h" | |
2112 | ||
2113 | static inline uint8_t do_usad(uint8_t a, uint8_t b) | |
2114 | { | |
2115 | if (a > b) | |
2116 | return a - b; | |
2117 | else | |
2118 | return b - a; | |
2119 | } | |
2120 | ||
2121 | /* Unsigned sum of absolute byte differences. */ | |
2122 | uint32_t HELPER(usad8)(uint32_t a, uint32_t b) | |
2123 | { | |
2124 | uint32_t sum; | |
2125 | sum = do_usad(a, b); | |
2126 | sum += do_usad(a >> 8, b >> 8); | |
2127 | sum += do_usad(a >> 16, b >>16); | |
2128 | sum += do_usad(a >> 24, b >> 24); | |
2129 | return sum; | |
2130 | } | |
2131 | ||
2132 | /* For ARMv6 SEL instruction. */ | |
2133 | uint32_t HELPER(sel_flags)(uint32_t flags, uint32_t a, uint32_t b) | |
2134 | { | |
2135 | uint32_t mask; | |
2136 | ||
2137 | mask = 0; | |
2138 | if (flags & 1) | |
2139 | mask |= 0xff; | |
2140 | if (flags & 2) | |
2141 | mask |= 0xff00; | |
2142 | if (flags & 4) | |
2143 | mask |= 0xff0000; | |
2144 | if (flags & 8) | |
2145 | mask |= 0xff000000; | |
2146 | return (a & mask) | (b & ~mask); | |
2147 | } | |
2148 | ||
5e3f878a PB |
2149 | uint32_t HELPER(logicq_cc)(uint64_t val) |
2150 | { | |
2151 | return (val >> 32) | (val != 0); | |
2152 | } | |
4373f3ce PB |
2153 | |
2154 | /* VFP support. We follow the convention used for VFP instrunctions: | |
2155 | Single precition routines have a "s" suffix, double precision a | |
2156 | "d" suffix. */ | |
2157 | ||
2158 | /* Convert host exception flags to vfp form. */ | |
2159 | static inline int vfp_exceptbits_from_host(int host_bits) | |
2160 | { | |
2161 | int target_bits = 0; | |
2162 | ||
2163 | if (host_bits & float_flag_invalid) | |
2164 | target_bits |= 1; | |
2165 | if (host_bits & float_flag_divbyzero) | |
2166 | target_bits |= 2; | |
2167 | if (host_bits & float_flag_overflow) | |
2168 | target_bits |= 4; | |
2169 | if (host_bits & float_flag_underflow) | |
2170 | target_bits |= 8; | |
2171 | if (host_bits & float_flag_inexact) | |
2172 | target_bits |= 0x10; | |
2173 | return target_bits; | |
2174 | } | |
2175 | ||
2176 | uint32_t HELPER(vfp_get_fpscr)(CPUState *env) | |
2177 | { | |
2178 | int i; | |
2179 | uint32_t fpscr; | |
2180 | ||
2181 | fpscr = (env->vfp.xregs[ARM_VFP_FPSCR] & 0xffc8ffff) | |
2182 | | (env->vfp.vec_len << 16) | |
2183 | | (env->vfp.vec_stride << 20); | |
2184 | i = get_float_exception_flags(&env->vfp.fp_status); | |
2185 | fpscr |= vfp_exceptbits_from_host(i); | |
2186 | return fpscr; | |
2187 | } | |
2188 | ||
2189 | /* Convert vfp exception flags to target form. */ | |
2190 | static inline int vfp_exceptbits_to_host(int target_bits) | |
2191 | { | |
2192 | int host_bits = 0; | |
2193 | ||
2194 | if (target_bits & 1) | |
2195 | host_bits |= float_flag_invalid; | |
2196 | if (target_bits & 2) | |
2197 | host_bits |= float_flag_divbyzero; | |
2198 | if (target_bits & 4) | |
2199 | host_bits |= float_flag_overflow; | |
2200 | if (target_bits & 8) | |
2201 | host_bits |= float_flag_underflow; | |
2202 | if (target_bits & 0x10) | |
2203 | host_bits |= float_flag_inexact; | |
2204 | return host_bits; | |
2205 | } | |
2206 | ||
2207 | void HELPER(vfp_set_fpscr)(CPUState *env, uint32_t val) | |
2208 | { | |
2209 | int i; | |
2210 | uint32_t changed; | |
2211 | ||
2212 | changed = env->vfp.xregs[ARM_VFP_FPSCR]; | |
2213 | env->vfp.xregs[ARM_VFP_FPSCR] = (val & 0xffc8ffff); | |
2214 | env->vfp.vec_len = (val >> 16) & 7; | |
2215 | env->vfp.vec_stride = (val >> 20) & 3; | |
2216 | ||
2217 | changed ^= val; | |
2218 | if (changed & (3 << 22)) { | |
2219 | i = (val >> 22) & 3; | |
2220 | switch (i) { | |
2221 | case 0: | |
2222 | i = float_round_nearest_even; | |
2223 | break; | |
2224 | case 1: | |
2225 | i = float_round_up; | |
2226 | break; | |
2227 | case 2: | |
2228 | i = float_round_down; | |
2229 | break; | |
2230 | case 3: | |
2231 | i = float_round_to_zero; | |
2232 | break; | |
2233 | } | |
2234 | set_float_rounding_mode(i, &env->vfp.fp_status); | |
2235 | } | |
2236 | ||
2237 | i = vfp_exceptbits_to_host((val >> 8) & 0x1f); | |
2238 | set_float_exception_flags(i, &env->vfp.fp_status); | |
2239 | /* XXX: FZ and DN are not implemented. */ | |
2240 | } | |
2241 | ||
2242 | #define VFP_HELPER(name, p) HELPER(glue(glue(vfp_,name),p)) | |
2243 | ||
2244 | #define VFP_BINOP(name) \ | |
2245 | float32 VFP_HELPER(name, s)(float32 a, float32 b, CPUState *env) \ | |
2246 | { \ | |
2247 | return float32_ ## name (a, b, &env->vfp.fp_status); \ | |
2248 | } \ | |
2249 | float64 VFP_HELPER(name, d)(float64 a, float64 b, CPUState *env) \ | |
2250 | { \ | |
2251 | return float64_ ## name (a, b, &env->vfp.fp_status); \ | |
2252 | } | |
2253 | VFP_BINOP(add) | |
2254 | VFP_BINOP(sub) | |
2255 | VFP_BINOP(mul) | |
2256 | VFP_BINOP(div) | |
2257 | #undef VFP_BINOP | |
2258 | ||
2259 | float32 VFP_HELPER(neg, s)(float32 a) | |
2260 | { | |
2261 | return float32_chs(a); | |
2262 | } | |
2263 | ||
2264 | float64 VFP_HELPER(neg, d)(float64 a) | |
2265 | { | |
2266 | return float32_chs(a); | |
2267 | } | |
2268 | ||
2269 | float32 VFP_HELPER(abs, s)(float32 a) | |
2270 | { | |
2271 | return float32_abs(a); | |
2272 | } | |
2273 | ||
2274 | float64 VFP_HELPER(abs, d)(float64 a) | |
2275 | { | |
2276 | return float32_abs(a); | |
2277 | } | |
2278 | ||
2279 | float32 VFP_HELPER(sqrt, s)(float32 a, CPUState *env) | |
2280 | { | |
2281 | return float32_sqrt(a, &env->vfp.fp_status); | |
2282 | } | |
2283 | ||
2284 | float64 VFP_HELPER(sqrt, d)(float64 a, CPUState *env) | |
2285 | { | |
2286 | return float64_sqrt(a, &env->vfp.fp_status); | |
2287 | } | |
2288 | ||
2289 | /* XXX: check quiet/signaling case */ | |
2290 | #define DO_VFP_cmp(p, type) \ | |
2291 | void VFP_HELPER(cmp, p)(type a, type b, CPUState *env) \ | |
2292 | { \ | |
2293 | uint32_t flags; \ | |
2294 | switch(type ## _compare_quiet(a, b, &env->vfp.fp_status)) { \ | |
2295 | case 0: flags = 0x6; break; \ | |
2296 | case -1: flags = 0x8; break; \ | |
2297 | case 1: flags = 0x2; break; \ | |
2298 | default: case 2: flags = 0x3; break; \ | |
2299 | } \ | |
2300 | env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \ | |
2301 | | (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \ | |
2302 | } \ | |
2303 | void VFP_HELPER(cmpe, p)(type a, type b, CPUState *env) \ | |
2304 | { \ | |
2305 | uint32_t flags; \ | |
2306 | switch(type ## _compare(a, b, &env->vfp.fp_status)) { \ | |
2307 | case 0: flags = 0x6; break; \ | |
2308 | case -1: flags = 0x8; break; \ | |
2309 | case 1: flags = 0x2; break; \ | |
2310 | default: case 2: flags = 0x3; break; \ | |
2311 | } \ | |
2312 | env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \ | |
2313 | | (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \ | |
2314 | } | |
2315 | DO_VFP_cmp(s, float32) | |
2316 | DO_VFP_cmp(d, float64) | |
2317 | #undef DO_VFP_cmp | |
2318 | ||
2319 | /* Helper routines to perform bitwise copies between float and int. */ | |
2320 | static inline float32 vfp_itos(uint32_t i) | |
2321 | { | |
2322 | union { | |
2323 | uint32_t i; | |
2324 | float32 s; | |
2325 | } v; | |
2326 | ||
2327 | v.i = i; | |
2328 | return v.s; | |
2329 | } | |
2330 | ||
2331 | static inline uint32_t vfp_stoi(float32 s) | |
2332 | { | |
2333 | union { | |
2334 | uint32_t i; | |
2335 | float32 s; | |
2336 | } v; | |
2337 | ||
2338 | v.s = s; | |
2339 | return v.i; | |
2340 | } | |
2341 | ||
2342 | static inline float64 vfp_itod(uint64_t i) | |
2343 | { | |
2344 | union { | |
2345 | uint64_t i; | |
2346 | float64 d; | |
2347 | } v; | |
2348 | ||
2349 | v.i = i; | |
2350 | return v.d; | |
2351 | } | |
2352 | ||
2353 | static inline uint64_t vfp_dtoi(float64 d) | |
2354 | { | |
2355 | union { | |
2356 | uint64_t i; | |
2357 | float64 d; | |
2358 | } v; | |
2359 | ||
2360 | v.d = d; | |
2361 | return v.i; | |
2362 | } | |
2363 | ||
2364 | /* Integer to float conversion. */ | |
2365 | float32 VFP_HELPER(uito, s)(float32 x, CPUState *env) | |
2366 | { | |
2367 | return uint32_to_float32(vfp_stoi(x), &env->vfp.fp_status); | |
2368 | } | |
2369 | ||
2370 | float64 VFP_HELPER(uito, d)(float32 x, CPUState *env) | |
2371 | { | |
2372 | return uint32_to_float64(vfp_stoi(x), &env->vfp.fp_status); | |
2373 | } | |
2374 | ||
2375 | float32 VFP_HELPER(sito, s)(float32 x, CPUState *env) | |
2376 | { | |
2377 | return int32_to_float32(vfp_stoi(x), &env->vfp.fp_status); | |
2378 | } | |
2379 | ||
2380 | float64 VFP_HELPER(sito, d)(float32 x, CPUState *env) | |
2381 | { | |
2382 | return int32_to_float64(vfp_stoi(x), &env->vfp.fp_status); | |
2383 | } | |
2384 | ||
2385 | /* Float to integer conversion. */ | |
2386 | float32 VFP_HELPER(toui, s)(float32 x, CPUState *env) | |
2387 | { | |
2388 | return vfp_itos(float32_to_uint32(x, &env->vfp.fp_status)); | |
2389 | } | |
2390 | ||
2391 | float32 VFP_HELPER(toui, d)(float64 x, CPUState *env) | |
2392 | { | |
2393 | return vfp_itos(float64_to_uint32(x, &env->vfp.fp_status)); | |
2394 | } | |
2395 | ||
2396 | float32 VFP_HELPER(tosi, s)(float32 x, CPUState *env) | |
2397 | { | |
2398 | return vfp_itos(float32_to_int32(x, &env->vfp.fp_status)); | |
2399 | } | |
2400 | ||
2401 | float32 VFP_HELPER(tosi, d)(float64 x, CPUState *env) | |
2402 | { | |
2403 | return vfp_itos(float64_to_int32(x, &env->vfp.fp_status)); | |
2404 | } | |
2405 | ||
2406 | float32 VFP_HELPER(touiz, s)(float32 x, CPUState *env) | |
2407 | { | |
2408 | return vfp_itos(float32_to_uint32_round_to_zero(x, &env->vfp.fp_status)); | |
2409 | } | |
2410 | ||
2411 | float32 VFP_HELPER(touiz, d)(float64 x, CPUState *env) | |
2412 | { | |
2413 | return vfp_itos(float64_to_uint32_round_to_zero(x, &env->vfp.fp_status)); | |
2414 | } | |
2415 | ||
2416 | float32 VFP_HELPER(tosiz, s)(float32 x, CPUState *env) | |
2417 | { | |
2418 | return vfp_itos(float32_to_int32_round_to_zero(x, &env->vfp.fp_status)); | |
2419 | } | |
2420 | ||
2421 | float32 VFP_HELPER(tosiz, d)(float64 x, CPUState *env) | |
2422 | { | |
2423 | return vfp_itos(float64_to_int32_round_to_zero(x, &env->vfp.fp_status)); | |
2424 | } | |
2425 | ||
2426 | /* floating point conversion */ | |
2427 | float64 VFP_HELPER(fcvtd, s)(float32 x, CPUState *env) | |
2428 | { | |
2429 | return float32_to_float64(x, &env->vfp.fp_status); | |
2430 | } | |
2431 | ||
2432 | float32 VFP_HELPER(fcvts, d)(float64 x, CPUState *env) | |
2433 | { | |
2434 | return float64_to_float32(x, &env->vfp.fp_status); | |
2435 | } | |
2436 | ||
2437 | /* VFP3 fixed point conversion. */ | |
2438 | #define VFP_CONV_FIX(name, p, ftype, itype, sign) \ | |
2439 | ftype VFP_HELPER(name##to, p)(ftype x, uint32_t shift, CPUState *env) \ | |
2440 | { \ | |
2441 | ftype tmp; \ | |
2442 | tmp = sign##int32_to_##ftype ((itype)vfp_##p##toi(x), \ | |
2443 | &env->vfp.fp_status); \ | |
2444 | return ftype##_scalbn(tmp, shift, &env->vfp.fp_status); \ | |
2445 | } \ | |
2446 | ftype VFP_HELPER(to##name, p)(ftype x, uint32_t shift, CPUState *env) \ | |
2447 | { \ | |
2448 | ftype tmp; \ | |
2449 | tmp = ftype##_scalbn(x, shift, &env->vfp.fp_status); \ | |
2450 | return vfp_ito##p((itype)ftype##_to_##sign##int32_round_to_zero(tmp, \ | |
2451 | &env->vfp.fp_status)); \ | |
2452 | } | |
2453 | ||
2454 | VFP_CONV_FIX(sh, d, float64, int16, ) | |
2455 | VFP_CONV_FIX(sl, d, float64, int32, ) | |
2456 | VFP_CONV_FIX(uh, d, float64, uint16, u) | |
2457 | VFP_CONV_FIX(ul, d, float64, uint32, u) | |
2458 | VFP_CONV_FIX(sh, s, float32, int16, ) | |
2459 | VFP_CONV_FIX(sl, s, float32, int32, ) | |
2460 | VFP_CONV_FIX(uh, s, float32, uint16, u) | |
2461 | VFP_CONV_FIX(ul, s, float32, uint32, u) | |
2462 | #undef VFP_CONV_FIX | |
2463 | ||
2464 | float32 HELPER(recps_f32)(float32 a, float32 b, CPUState *env) | |
2465 | { | |
2466 | float_status *s = &env->vfp.fp_status; | |
2467 | float32 two = int32_to_float32(2, s); | |
2468 | return float32_sub(two, float32_mul(a, b, s), s); | |
2469 | } | |
2470 | ||
2471 | float32 HELPER(rsqrts_f32)(float32 a, float32 b, CPUState *env) | |
2472 | { | |
2473 | float_status *s = &env->vfp.fp_status; | |
2474 | float32 three = int32_to_float32(3, s); | |
2475 | return float32_sub(three, float32_mul(a, b, s), s); | |
2476 | } | |
2477 | ||
8f8e3aa4 PB |
2478 | /* NEON helpers. */ |
2479 | ||
4373f3ce PB |
2480 | /* TODO: The architecture specifies the value that the estimate functions |
2481 | should return. We return the exact reciprocal/root instead. */ | |
2482 | float32 HELPER(recpe_f32)(float32 a, CPUState *env) | |
2483 | { | |
2484 | float_status *s = &env->vfp.fp_status; | |
2485 | float32 one = int32_to_float32(1, s); | |
2486 | return float32_div(one, a, s); | |
2487 | } | |
2488 | ||
2489 | float32 HELPER(rsqrte_f32)(float32 a, CPUState *env) | |
2490 | { | |
2491 | float_status *s = &env->vfp.fp_status; | |
2492 | float32 one = int32_to_float32(1, s); | |
2493 | return float32_div(one, float32_sqrt(a, s), s); | |
2494 | } | |
2495 | ||
2496 | uint32_t HELPER(recpe_u32)(uint32_t a, CPUState *env) | |
2497 | { | |
2498 | float_status *s = &env->vfp.fp_status; | |
2499 | float32 tmp; | |
2500 | tmp = int32_to_float32(a, s); | |
2501 | tmp = float32_scalbn(tmp, -32, s); | |
2502 | tmp = helper_recpe_f32(tmp, env); | |
2503 | tmp = float32_scalbn(tmp, 31, s); | |
2504 | return float32_to_int32(tmp, s); | |
2505 | } | |
2506 | ||
2507 | uint32_t HELPER(rsqrte_u32)(uint32_t a, CPUState *env) | |
2508 | { | |
2509 | float_status *s = &env->vfp.fp_status; | |
2510 | float32 tmp; | |
2511 | tmp = int32_to_float32(a, s); | |
2512 | tmp = float32_scalbn(tmp, -32, s); | |
2513 | tmp = helper_rsqrte_f32(tmp, env); | |
2514 | tmp = float32_scalbn(tmp, 31, s); | |
2515 | return float32_to_int32(tmp, s); | |
2516 | } |