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target-arm: Add raw_readfn and raw_writefn to ARMCPRegInfo
[mirror_qemu.git] / target-arm / helper.c
CommitLineData
b5ff1b31 1#include "cpu.h"
022c62cb 2#include "exec/gdbstub.h"
7b59220e 3#include "helper.h"
1de7afc9 4#include "qemu/host-utils.h"
9c17d615 5#include "sysemu/sysemu.h"
1de7afc9 6#include "qemu/bitops.h"
0b03bdfc 7
4a501606
PM		 8#ifndef CONFIG_USER_ONLY
9static inline int get_phys_addr(CPUARMState *env, uint32_t address,
10 int access_type, int is_user,
a8170e5e 11 hwaddr *phys_ptr, int *prot,
4a501606
PM		 12 target_ulong *page_size);
13#endif
14
0ecb72a5 15static int vfp_gdb_get_reg(CPUARMState *env, uint8_t *buf, int reg)
56aebc89
PB		 16{
17 int nregs;
18
19 /* VFP data registers are always little-endian. */
20 nregs = arm_feature(env, ARM_FEATURE_VFP3) ? 32 : 16;
21 if (reg < nregs) {
22 stfq_le_p(buf, env->vfp.regs[reg]);
23 return 8;
24 }
25 if (arm_feature(env, ARM_FEATURE_NEON)) {
26 /* Aliases for Q regs. */
27 nregs += 16;
28 if (reg < nregs) {
29 stfq_le_p(buf, env->vfp.regs[(reg - 32) * 2]);
30 stfq_le_p(buf + 8, env->vfp.regs[(reg - 32) * 2 + 1]);
31 return 16;
32 }
33 }
34 switch (reg - nregs) {
35 case 0: stl_p(buf, env->vfp.xregs[ARM_VFP_FPSID]); return 4;
36 case 1: stl_p(buf, env->vfp.xregs[ARM_VFP_FPSCR]); return 4;
37 case 2: stl_p(buf, env->vfp.xregs[ARM_VFP_FPEXC]); return 4;
38 }
39 return 0;
40}
41
0ecb72a5 42static int vfp_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg)
56aebc89
PB		 43{
44 int nregs;
45
46 nregs = arm_feature(env, ARM_FEATURE_VFP3) ? 32 : 16;
47 if (reg < nregs) {
48 env->vfp.regs[reg] = ldfq_le_p(buf);
49 return 8;
50 }
51 if (arm_feature(env, ARM_FEATURE_NEON)) {
52 nregs += 16;
53 if (reg < nregs) {
54 env->vfp.regs[(reg - 32) * 2] = ldfq_le_p(buf);
55 env->vfp.regs[(reg - 32) * 2 + 1] = ldfq_le_p(buf + 8);
56 return 16;
57 }
58 }
59 switch (reg - nregs) {
60 case 0: env->vfp.xregs[ARM_VFP_FPSID] = ldl_p(buf); return 4;
61 case 1: env->vfp.xregs[ARM_VFP_FPSCR] = ldl_p(buf); return 4;
71b3c3de 62 case 2: env->vfp.xregs[ARM_VFP_FPEXC] = ldl_p(buf) & (1 << 30); return 4;
56aebc89
PB		 63 }
64 return 0;
65}
66
c983fe6c
PM		 67static int dacr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
68{
69 env->cp15.c3 = value;
70 tlb_flush(env, 1); /* Flush TLB as domain not tracked in TLB */
71 return 0;
72}
73
08de207b
PM		 74static int fcse_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
75{
76 if (env->cp15.c13_fcse != value) {
77 /* Unlike real hardware the qemu TLB uses virtual addresses,
78 * not modified virtual addresses, so this causes a TLB flush.
79 */
80 tlb_flush(env, 1);
81 env->cp15.c13_fcse = value;
82 }
83 return 0;
84}
85static int contextidr_write(CPUARMState *env, const ARMCPRegInfo *ri,
86 uint64_t value)
87{
88 if (env->cp15.c13_context != value && !arm_feature(env, ARM_FEATURE_MPU)) {
89 /* For VMSA (when not using the LPAE long descriptor page table
90 * format) this register includes the ASID, so do a TLB flush.
91 * For PMSA it is purely a process ID and no action is needed.
92 */
93 tlb_flush(env, 1);
94 }
95 env->cp15.c13_context = value;
96 return 0;
97}
98
d929823f
PM		 99static int tlbiall_write(CPUARMState *env, const ARMCPRegInfo *ri,
100 uint64_t value)
101{
102 /* Invalidate all (TLBIALL) */
103 tlb_flush(env, 1);
104 return 0;
105}
106
107static int tlbimva_write(CPUARMState *env, const ARMCPRegInfo *ri,
108 uint64_t value)
109{
110 /* Invalidate single TLB entry by MVA and ASID (TLBIMVA) */
111 tlb_flush_page(env, value & TARGET_PAGE_MASK);
112 return 0;
113}
114
115static int tlbiasid_write(CPUARMState *env, const ARMCPRegInfo *ri,
116 uint64_t value)
117{
118 /* Invalidate by ASID (TLBIASID) */
119 tlb_flush(env, value == 0);
120 return 0;
121}
122
123static int tlbimvaa_write(CPUARMState *env, const ARMCPRegInfo *ri,
124 uint64_t value)
125{
126 /* Invalidate single entry by MVA, all ASIDs (TLBIMVAA) */
127 tlb_flush_page(env, value & TARGET_PAGE_MASK);
128 return 0;
129}
130
e9aa6c21
PM		 131static const ARMCPRegInfo cp_reginfo[] = {
132 /* DBGDIDR: just RAZ. In particular this means the "debug architecture
133 * version" bits will read as a reserved value, which should cause
134 * Linux to not try to use the debug hardware.
135 */
136 { .name = "DBGDIDR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 0,
137 .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 },
c983fe6c
PM		 138 /* MMU Domain access control / MPU write buffer control */
139 { .name = "DACR", .cp = 15,
140 .crn = 3, .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY,
141 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c3),
142 .resetvalue = 0, .writefn = dacr_write },
08de207b
PM		 143 { .name = "FCSEIDR", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 0,
144 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c13_fcse),
145 .resetvalue = 0, .writefn = fcse_write },
146 { .name = "CONTEXTIDR", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 1,
147 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c13_fcse),
148 .resetvalue = 0, .writefn = contextidr_write },
4fdd17dd
PM		 149 /* ??? This covers not just the impdef TLB lockdown registers but also
150 * some v7VMSA registers relating to TEX remap, so it is overly broad.
151 */
152 { .name = "TLB_LOCKDOWN", .cp = 15, .crn = 10, .crm = CP_ANY,
153 .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_NOP },
d929823f
PM		 154 /* MMU TLB control. Note that the wildcarding means we cover not just
155 * the unified TLB ops but also the dside/iside/inner-shareable variants.
156 */
157 { .name = "TLBIALL", .cp = 15, .crn = 8, .crm = CP_ANY,
158 .opc1 = CP_ANY, .opc2 = 0, .access = PL1_W, .writefn = tlbiall_write, },
159 { .name = "TLBIMVA", .cp = 15, .crn = 8, .crm = CP_ANY,
160 .opc1 = CP_ANY, .opc2 = 1, .access = PL1_W, .writefn = tlbimva_write, },
161 { .name = "TLBIASID", .cp = 15, .crn = 8, .crm = CP_ANY,
162 .opc1 = CP_ANY, .opc2 = 2, .access = PL1_W, .writefn = tlbiasid_write, },
163 { .name = "TLBIMVAA", .cp = 15, .crn = 8, .crm = CP_ANY,
164 .opc1 = CP_ANY, .opc2 = 3, .access = PL1_W, .writefn = tlbimvaa_write, },
c4804214
PM		 165 /* Cache maintenance ops; some of this space may be overridden later. */
166 { .name = "CACHEMAINT", .cp = 15, .crn = 7, .crm = CP_ANY,
167 .opc1 = 0, .opc2 = CP_ANY, .access = PL1_W,
168 .type = ARM_CP_NOP | ARM_CP_OVERRIDE },
e9aa6c21
PM		 169 REGINFO_SENTINEL
170};
171
7d57f408
PM		 172static const ARMCPRegInfo not_v6_cp_reginfo[] = {
173 /* Not all pre-v6 cores implemented this WFI, so this is slightly
174 * over-broad.
175 */
176 { .name = "WFI_v5", .cp = 15, .crn = 7, .crm = 8, .opc1 = 0, .opc2 = 2,
177 .access = PL1_W, .type = ARM_CP_WFI },
178 REGINFO_SENTINEL
179};
180
181static const ARMCPRegInfo not_v7_cp_reginfo[] = {
182 /* Standard v6 WFI (also used in some pre-v6 cores); not in v7 (which
183 * is UNPREDICTABLE; we choose to NOP as most implementations do).
184 */
185 { .name = "WFI_v6", .cp = 15, .crn = 7, .crm = 0, .opc1 = 0, .opc2 = 4,
186 .access = PL1_W, .type = ARM_CP_WFI },
34f90529
PM		 187 /* L1 cache lockdown. Not architectural in v6 and earlier but in practice
188 * implemented in 926, 946, 1026, 1136, 1176 and 11MPCore. StrongARM and
189 * OMAPCP will override this space.
190 */
191 { .name = "DLOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 0, .opc2 = 0,
192 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_data),
193 .resetvalue = 0 },
194 { .name = "ILOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 0, .opc2 = 1,
195 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_insn),
196 .resetvalue = 0 },
776d4e5c
PM		 197 /* v6 doesn't have the cache ID registers but Linux reads them anyway */
198 { .name = "DUMMY", .cp = 15, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = CP_ANY,
199 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
7d57f408
PM		 200 REGINFO_SENTINEL
201};
202
2771db27
PM		 203static int cpacr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
204{
205 if (env->cp15.c1_coproc != value) {
206 env->cp15.c1_coproc = value;
207 /* ??? Is this safe when called from within a TB? */
208 tb_flush(env);
209 }
210 return 0;
211}
212
7d57f408
PM		 213static const ARMCPRegInfo v6_cp_reginfo[] = {
214 /* prefetch by MVA in v6, NOP in v7 */
215 { .name = "MVA_prefetch",
216 .cp = 15, .crn = 7, .crm = 13, .opc1 = 0, .opc2 = 1,
217 .access = PL1_W, .type = ARM_CP_NOP },
218 { .name = "ISB", .cp = 15, .crn = 7, .crm = 5, .opc1 = 0, .opc2 = 4,
219 .access = PL0_W, .type = ARM_CP_NOP },
091fd17c 220 { .name = "DSB", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 4,
7d57f408 221 .access = PL0_W, .type = ARM_CP_NOP },
091fd17c 222 { .name = "DMB", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 5,
7d57f408 223 .access = PL0_W, .type = ARM_CP_NOP },
06d76f31
PM		 224 { .name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 2,
225 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c6_insn),
226 .resetvalue = 0, },
227 /* Watchpoint Fault Address Register : should actually only be present
228 * for 1136, 1176, 11MPCore.
229 */
230 { .name = "WFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1,
231 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0, },
2771db27
PM		 232 { .name = "CPACR", .cp = 15, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 2,
233 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c1_coproc),
234 .resetvalue = 0, .writefn = cpacr_write },
7d57f408
PM		 235 REGINFO_SENTINEL
236};
237
200ac0ef
PM		 238static int pmreg_read(CPUARMState *env, const ARMCPRegInfo *ri,
239 uint64_t *value)
240{
241 /* Generic performance monitor register read function for where
242 * user access may be allowed by PMUSERENR.
243 */
244 if (arm_current_pl(env) == 0 && !env->cp15.c9_pmuserenr) {
245 return EXCP_UDEF;
246 }
247 *value = CPREG_FIELD32(env, ri);
248 return 0;
249}
250
251static int pmcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
252 uint64_t value)
253{
254 if (arm_current_pl(env) == 0 && !env->cp15.c9_pmuserenr) {
255 return EXCP_UDEF;
256 }
257 /* only the DP, X, D and E bits are writable */
258 env->cp15.c9_pmcr &= ~0x39;
259 env->cp15.c9_pmcr |= (value & 0x39);
260 return 0;
261}
262
263static int pmcntenset_write(CPUARMState *env, const ARMCPRegInfo *ri,
264 uint64_t value)
265{
266 if (arm_current_pl(env) == 0 && !env->cp15.c9_pmuserenr) {
267 return EXCP_UDEF;
268 }
269 value &= (1 << 31);
270 env->cp15.c9_pmcnten |= value;
271 return 0;
272}
273
274static int pmcntenclr_write(CPUARMState *env, const ARMCPRegInfo *ri,
275 uint64_t value)
276{
277 if (arm_current_pl(env) == 0 && !env->cp15.c9_pmuserenr) {
278 return EXCP_UDEF;
279 }
280 value &= (1 << 31);
281 env->cp15.c9_pmcnten &= ~value;
282 return 0;
283}
284
285static int pmovsr_write(CPUARMState *env, const ARMCPRegInfo *ri,
286 uint64_t value)
287{
288 if (arm_current_pl(env) == 0 && !env->cp15.c9_pmuserenr) {
289 return EXCP_UDEF;
290 }
291 env->cp15.c9_pmovsr &= ~value;
292 return 0;
293}
294
295static int pmxevtyper_write(CPUARMState *env, const ARMCPRegInfo *ri,
296 uint64_t value)
297{
298 if (arm_current_pl(env) == 0 && !env->cp15.c9_pmuserenr) {
299 return EXCP_UDEF;
300 }
301 env->cp15.c9_pmxevtyper = value & 0xff;
302 return 0;
303}
304
305static int pmuserenr_write(CPUARMState *env, const ARMCPRegInfo *ri,
306 uint64_t value)
307{
308 env->cp15.c9_pmuserenr = value & 1;
309 return 0;
310}
311
312static int pmintenset_write(CPUARMState *env, const ARMCPRegInfo *ri,
313 uint64_t value)
314{
315 /* We have no event counters so only the C bit can be changed */
316 value &= (1 << 31);
317 env->cp15.c9_pminten |= value;
318 return 0;
319}
320
321static int pmintenclr_write(CPUARMState *env, const ARMCPRegInfo *ri,
322 uint64_t value)
323{
324 value &= (1 << 31);
325 env->cp15.c9_pminten &= ~value;
326 return 0;
327}
328
776d4e5c
PM		 329static int ccsidr_read(CPUARMState *env, const ARMCPRegInfo *ri,
330 uint64_t *value)
331{
332 ARMCPU *cpu = arm_env_get_cpu(env);
333 *value = cpu->ccsidr[env->cp15.c0_cssel];
334 return 0;
335}
336
337static int csselr_write(CPUARMState *env, const ARMCPRegInfo *ri,
338 uint64_t value)
339{
340 env->cp15.c0_cssel = value & 0xf;
341 return 0;
342}
343
e9aa6c21
PM		 344static const ARMCPRegInfo v7_cp_reginfo[] = {
345 /* DBGDRAR, DBGDSAR: always RAZ since we don't implement memory mapped
346 * debug components
347 */
348 { .name = "DBGDRAR", .cp = 14, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 0,
349 .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 },
091fd17c 350 { .name = "DBGDSAR", .cp = 14, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 0,
e9aa6c21 351 .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 },
7d57f408
PM		 352 /* the old v6 WFI, UNPREDICTABLE in v7 but we choose to NOP */
353 { .name = "NOP", .cp = 15, .crn = 7, .crm = 0, .opc1 = 0, .opc2 = 4,
354 .access = PL1_W, .type = ARM_CP_NOP },
200ac0ef
PM		 355 /* Performance monitors are implementation defined in v7,
356 * but with an ARM recommended set of registers, which we
357 * follow (although we don't actually implement any counters)
358 *
359 * Performance registers fall into three categories:
360 * (a) always UNDEF in PL0, RW in PL1 (PMINTENSET, PMINTENCLR)
361 * (b) RO in PL0 (ie UNDEF on write), RW in PL1 (PMUSERENR)
362 * (c) UNDEF in PL0 if PMUSERENR.EN==0, otherwise accessible (all others)
363 * For the cases controlled by PMUSERENR we must set .access to PL0_RW
364 * or PL0_RO as appropriate and then check PMUSERENR in the helper fn.
365 */
366 { .name = "PMCNTENSET", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 1,
367 .access = PL0_RW, .resetvalue = 0,
368 .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcnten),
369 .readfn = pmreg_read, .writefn = pmcntenset_write },
370 { .name = "PMCNTENCLR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 2,
371 .access = PL0_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcnten),
372 .readfn = pmreg_read, .writefn = pmcntenclr_write },
373 { .name = "PMOVSR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 3,
374 .access = PL0_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_pmovsr),
375 .readfn = pmreg_read, .writefn = pmovsr_write },
376 /* Unimplemented so WI. Strictly speaking write accesses in PL0 should
377 * respect PMUSERENR.
378 */
379 { .name = "PMSWINC", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 4,
380 .access = PL0_W, .type = ARM_CP_NOP },
381 /* Since we don't implement any events, writing to PMSELR is UNPREDICTABLE.
382 * We choose to RAZ/WI. XXX should respect PMUSERENR.
383 */
384 { .name = "PMSELR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 5,
385 .access = PL0_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
386 /* Unimplemented, RAZ/WI. XXX PMUSERENR */
387 { .name = "PMCCNTR", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 0,
388 .access = PL0_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
389 { .name = "PMXEVTYPER", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 1,
390 .access = PL0_RW,
391 .fieldoffset = offsetof(CPUARMState, cp15.c9_pmxevtyper),
392 .readfn = pmreg_read, .writefn = pmxevtyper_write },
393 /* Unimplemented, RAZ/WI. XXX PMUSERENR */
394 { .name = "PMXEVCNTR", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 2,
395 .access = PL0_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
396 { .name = "PMUSERENR", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 0,
397 .access = PL0_R | PL1_RW,
398 .fieldoffset = offsetof(CPUARMState, cp15.c9_pmuserenr),
399 .resetvalue = 0,
400 .writefn = pmuserenr_write },
401 { .name = "PMINTENSET", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 1,
402 .access = PL1_RW,
403 .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten),
404 .resetvalue = 0,
405 .writefn = pmintenset_write },
406 { .name = "PMINTENCLR", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 2,
407 .access = PL1_RW,
408 .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten),
409 .resetvalue = 0,
410 .writefn = pmintenclr_write },
2771db27
PM		 411 { .name = "SCR", .cp = 15, .crn = 1, .crm = 1, .opc1 = 0, .opc2 = 0,
412 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c1_scr),
413 .resetvalue = 0, },
776d4e5c
PM		 414 { .name = "CCSIDR", .cp = 15, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 0,
415 .access = PL1_R, .readfn = ccsidr_read },
416 { .name = "CSSELR", .cp = 15, .crn = 0, .crm = 0, .opc1 = 2, .opc2 = 0,
417 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c0_cssel),
418 .writefn = csselr_write, .resetvalue = 0 },
419 /* Auxiliary ID register: this actually has an IMPDEF value but for now
420 * just RAZ for all cores:
421 */
422 { .name = "AIDR", .cp = 15, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 7,
423 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
e9aa6c21
PM		 424 REGINFO_SENTINEL
425};
426
c326b979
PM		 427static int teecr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
428{
429 value &= 1;
430 env->teecr = value;
431 return 0;
432}
433
434static int teehbr_read(CPUARMState *env, const ARMCPRegInfo *ri,
435 uint64_t *value)
436{
437 /* This is a helper function because the user access rights
438 * depend on the value of the TEECR.
439 */
440 if (arm_current_pl(env) == 0 && (env->teecr & 1)) {
441 return EXCP_UDEF;
442 }
443 *value = env->teehbr;
444 return 0;
445}
446
447static int teehbr_write(CPUARMState *env, const ARMCPRegInfo *ri,
448 uint64_t value)
449{
450 if (arm_current_pl(env) == 0 && (env->teecr & 1)) {
451 return EXCP_UDEF;
452 }
453 env->teehbr = value;
454 return 0;
455}
456
457static const ARMCPRegInfo t2ee_cp_reginfo[] = {
458 { .name = "TEECR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 6, .opc2 = 0,
459 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, teecr),
460 .resetvalue = 0,
461 .writefn = teecr_write },
462 { .name = "TEEHBR", .cp = 14, .crn = 1, .crm = 0, .opc1 = 6, .opc2 = 0,
463 .access = PL0_RW, .fieldoffset = offsetof(CPUARMState, teehbr),
464 .resetvalue = 0,
465 .readfn = teehbr_read, .writefn = teehbr_write },
466 REGINFO_SENTINEL
467};
468
4d31c596
PM		 469static const ARMCPRegInfo v6k_cp_reginfo[] = {
470 { .name = "TPIDRURW", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 2,
471 .access = PL0_RW,
472 .fieldoffset = offsetof(CPUARMState, cp15.c13_tls1),
473 .resetvalue = 0 },
474 { .name = "TPIDRURO", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 3,
475 .access = PL0_R|PL1_W,
476 .fieldoffset = offsetof(CPUARMState, cp15.c13_tls2),
477 .resetvalue = 0 },
478 { .name = "TPIDRPRW", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 4,
479 .access = PL1_RW,
480 .fieldoffset = offsetof(CPUARMState, cp15.c13_tls3),
481 .resetvalue = 0 },
482 REGINFO_SENTINEL
483};
484
6cc7a3ae
PM		 485static const ARMCPRegInfo generic_timer_cp_reginfo[] = {
486 /* Dummy implementation: RAZ/WI the whole crn=14 space */
487 { .name = "GENERIC_TIMER", .cp = 15, .crn = 14,
488 .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY,
489 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
490 REGINFO_SENTINEL
491};
492
4a501606
PM		 493static int par_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
494{
891a2fe7
PM		 495 if (arm_feature(env, ARM_FEATURE_LPAE)) {
496 env->cp15.c7_par = value;
497 } else if (arm_feature(env, ARM_FEATURE_V7)) {
4a501606
PM		 498 env->cp15.c7_par = value & 0xfffff6ff;
499 } else {
500 env->cp15.c7_par = value & 0xfffff1ff;
501 }
502 return 0;
503}
504
505#ifndef CONFIG_USER_ONLY
506/* get_phys_addr() isn't present for user-mode-only targets */
702a9357
PM		 507
508/* Return true if extended addresses are enabled, ie this is an
509 * LPAE implementation and we are using the long-descriptor translation
510 * table format because the TTBCR EAE bit is set.
511 */
512static inline bool extended_addresses_enabled(CPUARMState *env)
513{
514 return arm_feature(env, ARM_FEATURE_LPAE)
515 && (env->cp15.c2_control & (1 << 31));
516}
517
4a501606
PM		 518static int ats_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
519{
a8170e5e 520 hwaddr phys_addr;
4a501606
PM		 521 target_ulong page_size;
522 int prot;
523 int ret, is_user = ri->opc2 & 2;
524 int access_type = ri->opc2 & 1;
525
526 if (ri->opc2 & 4) {
527 /* Other states are only available with TrustZone */
528 return EXCP_UDEF;
529 }
530 ret = get_phys_addr(env, value, access_type, is_user,
531 &phys_addr, &prot, &page_size);
702a9357
PM		 532 if (extended_addresses_enabled(env)) {
533 /* ret is a DFSR/IFSR value for the long descriptor
534 * translation table format, but with WnR always clear.
535 * Convert it to a 64-bit PAR.
536 */
537 uint64_t par64 = (1 << 11); /* LPAE bit always set */
538 if (ret == 0) {
539 par64 |= phys_addr & ~0xfffULL;
540 /* We don't set the ATTR or SH fields in the PAR. */
4a501606 541 } else {
702a9357
PM		 542 par64 |= 1; /* F */
543 par64 |= (ret & 0x3f) << 1; /* FS */
544 /* Note that S2WLK and FSTAGE are always zero, because we don't
545 * implement virtualization and therefore there can't be a stage 2
546 * fault.
547 */
4a501606 548 }
702a9357
PM		 549 env->cp15.c7_par = par64;
550 env->cp15.c7_par_hi = par64 >> 32;
4a501606 551 } else {
702a9357
PM		 552 /* ret is a DFSR/IFSR value for the short descriptor
553 * translation table format (with WnR always clear).
554 * Convert it to a 32-bit PAR.
555 */
556 if (ret == 0) {
557 /* We do not set any attribute bits in the PAR */
558 if (page_size == (1 << 24)
559 && arm_feature(env, ARM_FEATURE_V7)) {
560 env->cp15.c7_par = (phys_addr & 0xff000000) | 1 << 1;
561 } else {
562 env->cp15.c7_par = phys_addr & 0xfffff000;
563 }
564 } else {
565 env->cp15.c7_par = ((ret & (10 << 1)) >> 5) |
566 ((ret & (12 << 1)) >> 6) |
567 ((ret & 0xf) << 1) | 1;
568 }
569 env->cp15.c7_par_hi = 0;
4a501606
PM		 570 }
571 return 0;
572}
573#endif
574
575static const ARMCPRegInfo vapa_cp_reginfo[] = {
576 { .name = "PAR", .cp = 15, .crn = 7, .crm = 4, .opc1 = 0, .opc2 = 0,
577 .access = PL1_RW, .resetvalue = 0,
578 .fieldoffset = offsetof(CPUARMState, cp15.c7_par),
579 .writefn = par_write },
580#ifndef CONFIG_USER_ONLY
581 { .name = "ATS", .cp = 15, .crn = 7, .crm = 8, .opc1 = 0, .opc2 = CP_ANY,
582 .access = PL1_W, .writefn = ats_write },
583#endif
584 REGINFO_SENTINEL
585};
586
18032bec
PM		 587/* Return basic MPU access permission bits. */
588static uint32_t simple_mpu_ap_bits(uint32_t val)
589{
590 uint32_t ret;
591 uint32_t mask;
592 int i;
593 ret = 0;
594 mask = 3;
595 for (i = 0; i < 16; i += 2) {
596 ret |= (val >> i) & mask;
597 mask <<= 2;
598 }
599 return ret;
600}
601
602/* Pad basic MPU access permission bits to extended format. */
603static uint32_t extended_mpu_ap_bits(uint32_t val)
604{
605 uint32_t ret;
606 uint32_t mask;
607 int i;
608 ret = 0;
609 mask = 3;
610 for (i = 0; i < 16; i += 2) {
611 ret |= (val & mask) << i;
612 mask <<= 2;
613 }
614 return ret;
615}
616
617static int pmsav5_data_ap_write(CPUARMState *env, const ARMCPRegInfo *ri,
618 uint64_t value)
619{
620 env->cp15.c5_data = extended_mpu_ap_bits(value);
621 return 0;
622}
623
624static int pmsav5_data_ap_read(CPUARMState *env, const ARMCPRegInfo *ri,
625 uint64_t *value)
626{
627 *value = simple_mpu_ap_bits(env->cp15.c5_data);
628 return 0;
629}
630
631static int pmsav5_insn_ap_write(CPUARMState *env, const ARMCPRegInfo *ri,
632 uint64_t value)
633{
634 env->cp15.c5_insn = extended_mpu_ap_bits(value);
635 return 0;
636}
637
638static int pmsav5_insn_ap_read(CPUARMState *env, const ARMCPRegInfo *ri,
639 uint64_t *value)
640{
641 *value = simple_mpu_ap_bits(env->cp15.c5_insn);
642 return 0;
643}
644
06d76f31
PM		 645static int arm946_prbs_read(CPUARMState *env, const ARMCPRegInfo *ri,
646 uint64_t *value)
647{
599d64f6 648 if (ri->crm >= 8) {
06d76f31
PM		 649 return EXCP_UDEF;
650 }
651 *value = env->cp15.c6_region[ri->crm];
652 return 0;
653}
654
655static int arm946_prbs_write(CPUARMState *env, const ARMCPRegInfo *ri,
656 uint64_t value)
657{
599d64f6 658 if (ri->crm >= 8) {
06d76f31
PM		 659 return EXCP_UDEF;
660 }
661 env->cp15.c6_region[ri->crm] = value;
662 return 0;
663}
664
18032bec
PM		 665static const ARMCPRegInfo pmsav5_cp_reginfo[] = {
666 { .name = "DATA_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 0,
667 .access = PL1_RW,
668 .fieldoffset = offsetof(CPUARMState, cp15.c5_data), .resetvalue = 0,
669 .readfn = pmsav5_data_ap_read, .writefn = pmsav5_data_ap_write, },
670 { .name = "INSN_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 1,
671 .access = PL1_RW,
672 .fieldoffset = offsetof(CPUARMState, cp15.c5_insn), .resetvalue = 0,
673 .readfn = pmsav5_insn_ap_read, .writefn = pmsav5_insn_ap_write, },
674 { .name = "DATA_EXT_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 2,
675 .access = PL1_RW,
676 .fieldoffset = offsetof(CPUARMState, cp15.c5_data), .resetvalue = 0, },
677 { .name = "INSN_EXT_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 3,
678 .access = PL1_RW,
679 .fieldoffset = offsetof(CPUARMState, cp15.c5_insn), .resetvalue = 0, },
ecce5c3c
PM		 680 { .name = "DCACHE_CFG", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 0,
681 .access = PL1_RW,
682 .fieldoffset = offsetof(CPUARMState, cp15.c2_data), .resetvalue = 0, },
683 { .name = "ICACHE_CFG", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 1,
684 .access = PL1_RW,
685 .fieldoffset = offsetof(CPUARMState, cp15.c2_insn), .resetvalue = 0, },
06d76f31
PM		 686 /* Protection region base and size registers */
687 { .name = "946_PRBS", .cp = 15, .crn = 6, .crm = CP_ANY, .opc1 = 0,
688 .opc2 = CP_ANY, .access = PL1_RW,
689 .readfn = arm946_prbs_read, .writefn = arm946_prbs_write, },
18032bec
PM		 690 REGINFO_SENTINEL
691};
692
ecce5c3c
PM		 693static int vmsa_ttbcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
694 uint64_t value)
695{
e42c4db3
PM		 696 if (arm_feature(env, ARM_FEATURE_LPAE)) {
697 value &= ~((7 << 19) | (3 << 14) | (0xf << 3));
698 /* With LPAE the TTBCR could result in a change of ASID
699 * via the TTBCR.A1 bit, so do a TLB flush.
700 */
701 tlb_flush(env, 1);
702 } else {
703 value &= 7;
704 }
705 /* Note that we always calculate c2_mask and c2_base_mask, but
706 * they are only used for short-descriptor tables (ie if EAE is 0);
707 * for long-descriptor tables the TTBCR fields are used differently
708 * and the c2_mask and c2_base_mask values are meaningless.
709 */
ecce5c3c
PM		 710 env->cp15.c2_control = value;
711 env->cp15.c2_mask = ~(((uint32_t)0xffffffffu) >> value);
712 env->cp15.c2_base_mask = ~((uint32_t)0x3fffu >> value);
713 return 0;
714}
715
716static void vmsa_ttbcr_reset(CPUARMState *env, const ARMCPRegInfo *ri)
717{
718 env->cp15.c2_base_mask = 0xffffc000u;
719 env->cp15.c2_control = 0;
720 env->cp15.c2_mask = 0;
721}
722
18032bec
PM		 723static const ARMCPRegInfo vmsa_cp_reginfo[] = {
724 { .name = "DFSR", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 0,
725 .access = PL1_RW,
726 .fieldoffset = offsetof(CPUARMState, cp15.c5_data), .resetvalue = 0, },
727 { .name = "IFSR", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 1,
728 .access = PL1_RW,
729 .fieldoffset = offsetof(CPUARMState, cp15.c5_insn), .resetvalue = 0, },
ecce5c3c
PM		 730 { .name = "TTBR0", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 0,
731 .access = PL1_RW,
732 .fieldoffset = offsetof(CPUARMState, cp15.c2_base0), .resetvalue = 0, },
733 { .name = "TTBR1", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 1,
734 .access = PL1_RW,
81a60ada 735 .fieldoffset = offsetof(CPUARMState, cp15.c2_base1), .resetvalue = 0, },
ecce5c3c
PM		 736 { .name = "TTBCR", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 2,
737 .access = PL1_RW, .writefn = vmsa_ttbcr_write,
738 .resetfn = vmsa_ttbcr_reset,
739 .fieldoffset = offsetof(CPUARMState, cp15.c2_control) },
06d76f31
PM		 740 { .name = "DFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 0,
741 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c6_data),
742 .resetvalue = 0, },
18032bec
PM		 743 REGINFO_SENTINEL
744};
745
1047b9d7
PM		 746static int omap_ticonfig_write(CPUARMState *env, const ARMCPRegInfo *ri,
747 uint64_t value)
748{
749 env->cp15.c15_ticonfig = value & 0xe7;
750 /* The OS_TYPE bit in this register changes the reported CPUID! */
751 env->cp15.c0_cpuid = (value & (1 << 5)) ?
752 ARM_CPUID_TI915T : ARM_CPUID_TI925T;
753 return 0;
754}
755
756static int omap_threadid_write(CPUARMState *env, const ARMCPRegInfo *ri,
757 uint64_t value)
758{
759 env->cp15.c15_threadid = value & 0xffff;
760 return 0;
761}
762
763static int omap_wfi_write(CPUARMState *env, const ARMCPRegInfo *ri,
764 uint64_t value)
765{
766 /* Wait-for-interrupt (deprecated) */
c3affe56 767 cpu_interrupt(CPU(arm_env_get_cpu(env)), CPU_INTERRUPT_HALT);
1047b9d7
PM		 768 return 0;
769}
770
c4804214
PM		 771static int omap_cachemaint_write(CPUARMState *env, const ARMCPRegInfo *ri,
772 uint64_t value)
773{
774 /* On OMAP there are registers indicating the max/min index of dcache lines
775 * containing a dirty line; cache flush operations have to reset these.
776 */
777 env->cp15.c15_i_max = 0x000;
778 env->cp15.c15_i_min = 0xff0;
779 return 0;
780}
781
18032bec
PM		 782static const ARMCPRegInfo omap_cp_reginfo[] = {
783 { .name = "DFSR", .cp = 15, .crn = 5, .crm = CP_ANY,
784 .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_OVERRIDE,
785 .fieldoffset = offsetof(CPUARMState, cp15.c5_data), .resetvalue = 0, },
1047b9d7
PM		 786 { .name = "", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0,
787 .access = PL1_RW, .type = ARM_CP_NOP },
788 { .name = "TICONFIG", .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0,
789 .access = PL1_RW,
790 .fieldoffset = offsetof(CPUARMState, cp15.c15_ticonfig), .resetvalue = 0,
791 .writefn = omap_ticonfig_write },
792 { .name = "IMAX", .cp = 15, .crn = 15, .crm = 2, .opc1 = 0, .opc2 = 0,
793 .access = PL1_RW,
794 .fieldoffset = offsetof(CPUARMState, cp15.c15_i_max), .resetvalue = 0, },
795 { .name = "IMIN", .cp = 15, .crn = 15, .crm = 3, .opc1 = 0, .opc2 = 0,
796 .access = PL1_RW, .resetvalue = 0xff0,
797 .fieldoffset = offsetof(CPUARMState, cp15.c15_i_min) },
798 { .name = "THREADID", .cp = 15, .crn = 15, .crm = 4, .opc1 = 0, .opc2 = 0,
799 .access = PL1_RW,
800 .fieldoffset = offsetof(CPUARMState, cp15.c15_threadid), .resetvalue = 0,
801 .writefn = omap_threadid_write },
802 { .name = "TI925T_STATUS", .cp = 15, .crn = 15,
803 .crm = 8, .opc1 = 0, .opc2 = 0, .access = PL1_RW,
804 .readfn = arm_cp_read_zero, .writefn = omap_wfi_write, },
805 /* TODO: Peripheral port remap register:
806 * On OMAP2 mcr p15, 0, rn, c15, c2, 4 sets up the interrupt controller
807 * base address at $rn & ~0xfff and map size of 0x200 << ($rn & 0xfff),
808 * when MMU is off.
809 */
c4804214
PM		 810 { .name = "OMAP_CACHEMAINT", .cp = 15, .crn = 7, .crm = CP_ANY,
811 .opc1 = 0, .opc2 = CP_ANY, .access = PL1_W, .type = ARM_CP_OVERRIDE,
812 .writefn = omap_cachemaint_write },
34f90529
PM		 813 { .name = "C9", .cp = 15, .crn = 9,
814 .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW,
815 .type = ARM_CP_CONST | ARM_CP_OVERRIDE, .resetvalue = 0 },
1047b9d7
PM		 816 REGINFO_SENTINEL
817};
818
819static int xscale_cpar_write(CPUARMState *env, const ARMCPRegInfo *ri,
820 uint64_t value)
821{
822 value &= 0x3fff;
823 if (env->cp15.c15_cpar != value) {
824 /* Changes cp0 to cp13 behavior, so needs a TB flush. */
825 tb_flush(env);
826 env->cp15.c15_cpar = value;
827 }
828 return 0;
829}
830
831static const ARMCPRegInfo xscale_cp_reginfo[] = {
832 { .name = "XSCALE_CPAR",
833 .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0, .access = PL1_RW,
834 .fieldoffset = offsetof(CPUARMState, cp15.c15_cpar), .resetvalue = 0,
835 .writefn = xscale_cpar_write, },
2771db27
PM		 836 { .name = "XSCALE_AUXCR",
837 .cp = 15, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 1, .access = PL1_RW,
838 .fieldoffset = offsetof(CPUARMState, cp15.c1_xscaleauxcr),
839 .resetvalue = 0, },
1047b9d7
PM		 840 REGINFO_SENTINEL
841};
842
843static const ARMCPRegInfo dummy_c15_cp_reginfo[] = {
844 /* RAZ/WI the whole crn=15 space, when we don't have a more specific
845 * implementation of this implementation-defined space.
846 * Ideally this should eventually disappear in favour of actually
847 * implementing the correct behaviour for all cores.
848 */
849 { .name = "C15_IMPDEF", .cp = 15, .crn = 15,
850 .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY,
851 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
18032bec
PM		 852 REGINFO_SENTINEL
853};
854
c4804214
PM		 855static const ARMCPRegInfo cache_dirty_status_cp_reginfo[] = {
856 /* Cache status: RAZ because we have no cache so it's always clean */
857 { .name = "CDSR", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 6,
858 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
859 REGINFO_SENTINEL
860};
861
862static const ARMCPRegInfo cache_block_ops_cp_reginfo[] = {
863 /* We never have a a block transfer operation in progress */
864 { .name = "BXSR", .cp = 15, .crn = 7, .crm = 12, .opc1 = 0, .opc2 = 4,
865 .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 },
30b05bba
PM		 866 /* The cache ops themselves: these all NOP for QEMU */
867 { .name = "IICR", .cp = 15, .crm = 5, .opc1 = 0,
868 .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
869 { .name = "IDCR", .cp = 15, .crm = 6, .opc1 = 0,
870 .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
871 { .name = "CDCR", .cp = 15, .crm = 12, .opc1 = 0,
872 .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
873 { .name = "PIR", .cp = 15, .crm = 12, .opc1 = 1,
874 .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
875 { .name = "PDR", .cp = 15, .crm = 12, .opc1 = 2,
876 .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
877 { .name = "CIDCR", .cp = 15, .crm = 14, .opc1 = 0,
878 .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
c4804214
PM		 879 REGINFO_SENTINEL
880};
881
882static const ARMCPRegInfo cache_test_clean_cp_reginfo[] = {
883 /* The cache test-and-clean instructions always return (1 << 30)
884 * to indicate that there are no dirty cache lines.
885 */
886 { .name = "TC_DCACHE", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 3,
887 .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = (1 << 30) },
888 { .name = "TCI_DCACHE", .cp = 15, .crn = 7, .crm = 14, .opc1 = 0, .opc2 = 3,
889 .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = (1 << 30) },
890 REGINFO_SENTINEL
891};
892
34f90529
PM		 893static const ARMCPRegInfo strongarm_cp_reginfo[] = {
894 /* Ignore ReadBuffer accesses */
895 { .name = "C9_READBUFFER", .cp = 15, .crn = 9,
896 .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY,
897 .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_OVERRIDE,
898 .resetvalue = 0 },
899 REGINFO_SENTINEL
900};
901
81bdde9d
PM		 902static int mpidr_read(CPUARMState *env, const ARMCPRegInfo *ri,
903 uint64_t *value)
904{
55e5c285
AF		 905 CPUState *cs = CPU(arm_env_get_cpu(env));
906 uint32_t mpidr = cs->cpu_index;
81bdde9d
PM		 907 /* We don't support setting cluster ID ([8..11])
908 * so these bits always RAZ.
909 */
910 if (arm_feature(env, ARM_FEATURE_V7MP)) {
911 mpidr |= (1 << 31);
912 /* Cores which are uniprocessor (non-coherent)
913 * but still implement the MP extensions set
914 * bit 30. (For instance, A9UP.) However we do
915 * not currently model any of those cores.
916 */
917 }
918 *value = mpidr;
919 return 0;
920}
921
922static const ARMCPRegInfo mpidr_cp_reginfo[] = {
923 { .name = "MPIDR", .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 5,
924 .access = PL1_R, .readfn = mpidr_read },
925 REGINFO_SENTINEL
926};
927
891a2fe7
PM		 928static int par64_read(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t *value)
929{
930 *value = ((uint64_t)env->cp15.c7_par_hi << 32) | env->cp15.c7_par;
931 return 0;
932}
933
934static int par64_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
935{
936 env->cp15.c7_par_hi = value >> 32;
937 env->cp15.c7_par = value;
938 return 0;
939}
940
941static void par64_reset(CPUARMState *env, const ARMCPRegInfo *ri)
942{
943 env->cp15.c7_par_hi = 0;
944 env->cp15.c7_par = 0;
945}
946
947static int ttbr064_read(CPUARMState *env, const ARMCPRegInfo *ri,
948 uint64_t *value)
949{
950 *value = ((uint64_t)env->cp15.c2_base0_hi << 32) | env->cp15.c2_base0;
951 return 0;
952}
953
954static int ttbr064_write(CPUARMState *env, const ARMCPRegInfo *ri,
955 uint64_t value)
956{
957 env->cp15.c2_base0_hi = value >> 32;
958 env->cp15.c2_base0 = value;
959 /* Writes to the 64 bit format TTBRs may change the ASID */
960 tlb_flush(env, 1);
961 return 0;
962}
963
964static void ttbr064_reset(CPUARMState *env, const ARMCPRegInfo *ri)
965{
966 env->cp15.c2_base0_hi = 0;
967 env->cp15.c2_base0 = 0;
968}
969
970static int ttbr164_read(CPUARMState *env, const ARMCPRegInfo *ri,
971 uint64_t *value)
972{
973 *value = ((uint64_t)env->cp15.c2_base1_hi << 32) | env->cp15.c2_base1;
974 return 0;
975}
976
977static int ttbr164_write(CPUARMState *env, const ARMCPRegInfo *ri,
978 uint64_t value)
979{
980 env->cp15.c2_base1_hi = value >> 32;
981 env->cp15.c2_base1 = value;
982 return 0;
983}
984
985static void ttbr164_reset(CPUARMState *env, const ARMCPRegInfo *ri)
986{
987 env->cp15.c2_base1_hi = 0;
988 env->cp15.c2_base1 = 0;
989}
990
7ac681cf 991static const ARMCPRegInfo lpae_cp_reginfo[] = {
b90372ad 992 /* NOP AMAIR0/1: the override is because these clash with the rather
7ac681cf
PM		 993 * broadly specified TLB_LOCKDOWN entry in the generic cp_reginfo.
994 */
995 { .name = "AMAIR0", .cp = 15, .crn = 10, .crm = 3, .opc1 = 0, .opc2 = 0,
996 .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_OVERRIDE,
997 .resetvalue = 0 },
998 { .name = "AMAIR1", .cp = 15, .crn = 10, .crm = 3, .opc1 = 0, .opc2 = 1,
999 .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_OVERRIDE,
1000 .resetvalue = 0 },
f9fc619a
PM		 1001 /* 64 bit access versions of the (dummy) debug registers */
1002 { .name = "DBGDRAR", .cp = 14, .crm = 1, .opc1 = 0,
1003 .access = PL0_R, .type = ARM_CP_CONST|ARM_CP_64BIT, .resetvalue = 0 },
1004 { .name = "DBGDSAR", .cp = 14, .crm = 2, .opc1 = 0,
1005 .access = PL0_R, .type = ARM_CP_CONST|ARM_CP_64BIT, .resetvalue = 0 },
891a2fe7
PM		 1006 { .name = "PAR", .cp = 15, .crm = 7, .opc1 = 0,
1007 .access = PL1_RW, .type = ARM_CP_64BIT,
1008 .readfn = par64_read, .writefn = par64_write, .resetfn = par64_reset },
1009 { .name = "TTBR0", .cp = 15, .crm = 2, .opc1 = 0,
1010 .access = PL1_RW, .type = ARM_CP_64BIT, .readfn = ttbr064_read,
1011 .writefn = ttbr064_write, .resetfn = ttbr064_reset },
1012 { .name = "TTBR1", .cp = 15, .crm = 2, .opc1 = 1,
1013 .access = PL1_RW, .type = ARM_CP_64BIT, .readfn = ttbr164_read,
1014 .writefn = ttbr164_write, .resetfn = ttbr164_reset },
7ac681cf
PM		 1015 REGINFO_SENTINEL
1016};
1017
2771db27
PM		 1018static int sctlr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
1019{
1020 env->cp15.c1_sys = value;
1021 /* ??? Lots of these bits are not implemented. */
1022 /* This may enable/disable the MMU, so do a TLB flush. */
1023 tlb_flush(env, 1);
1024 return 0;
1025}
1026
2ceb98c0
PM		 1027void register_cp_regs_for_features(ARMCPU *cpu)
1028{
1029 /* Register all the coprocessor registers based on feature bits */
1030 CPUARMState *env = &cpu->env;
1031 if (arm_feature(env, ARM_FEATURE_M)) {
1032 /* M profile has no coprocessor registers */
1033 return;
1034 }
1035
e9aa6c21 1036 define_arm_cp_regs(cpu, cp_reginfo);
7d57f408 1037 if (arm_feature(env, ARM_FEATURE_V6)) {
8515a092
PM		 1038 /* The ID registers all have impdef reset values */
1039 ARMCPRegInfo v6_idregs[] = {
1040 { .name = "ID_PFR0", .cp = 15, .crn = 0, .crm = 1,
1041 .opc1 = 0, .opc2 = 0, .access = PL1_R, .type = ARM_CP_CONST,
1042 .resetvalue = cpu->id_pfr0 },
1043 { .name = "ID_PFR1", .cp = 15, .crn = 0, .crm = 1,
1044 .opc1 = 0, .opc2 = 1, .access = PL1_R, .type = ARM_CP_CONST,
1045 .resetvalue = cpu->id_pfr1 },
1046 { .name = "ID_DFR0", .cp = 15, .crn = 0, .crm = 1,
1047 .opc1 = 0, .opc2 = 2, .access = PL1_R, .type = ARM_CP_CONST,
1048 .resetvalue = cpu->id_dfr0 },
1049 { .name = "ID_AFR0", .cp = 15, .crn = 0, .crm = 1,
1050 .opc1 = 0, .opc2 = 3, .access = PL1_R, .type = ARM_CP_CONST,
1051 .resetvalue = cpu->id_afr0 },
1052 { .name = "ID_MMFR0", .cp = 15, .crn = 0, .crm = 1,
1053 .opc1 = 0, .opc2 = 4, .access = PL1_R, .type = ARM_CP_CONST,
1054 .resetvalue = cpu->id_mmfr0 },
1055 { .name = "ID_MMFR1", .cp = 15, .crn = 0, .crm = 1,
1056 .opc1 = 0, .opc2 = 5, .access = PL1_R, .type = ARM_CP_CONST,
1057 .resetvalue = cpu->id_mmfr1 },
1058 { .name = "ID_MMFR2", .cp = 15, .crn = 0, .crm = 1,
1059 .opc1 = 0, .opc2 = 6, .access = PL1_R, .type = ARM_CP_CONST,
1060 .resetvalue = cpu->id_mmfr2 },
1061 { .name = "ID_MMFR3", .cp = 15, .crn = 0, .crm = 1,
1062 .opc1 = 0, .opc2 = 7, .access = PL1_R, .type = ARM_CP_CONST,
1063 .resetvalue = cpu->id_mmfr3 },
1064 { .name = "ID_ISAR0", .cp = 15, .crn = 0, .crm = 2,
1065 .opc1 = 0, .opc2 = 0, .access = PL1_R, .type = ARM_CP_CONST,
1066 .resetvalue = cpu->id_isar0 },
1067 { .name = "ID_ISAR1", .cp = 15, .crn = 0, .crm = 2,
1068 .opc1 = 0, .opc2 = 1, .access = PL1_R, .type = ARM_CP_CONST,
1069 .resetvalue = cpu->id_isar1 },
1070 { .name = "ID_ISAR2", .cp = 15, .crn = 0, .crm = 2,
1071 .opc1 = 0, .opc2 = 2, .access = PL1_R, .type = ARM_CP_CONST,
1072 .resetvalue = cpu->id_isar2 },
1073 { .name = "ID_ISAR3", .cp = 15, .crn = 0, .crm = 2,
1074 .opc1 = 0, .opc2 = 3, .access = PL1_R, .type = ARM_CP_CONST,
1075 .resetvalue = cpu->id_isar3 },
1076 { .name = "ID_ISAR4", .cp = 15, .crn = 0, .crm = 2,
1077 .opc1 = 0, .opc2 = 4, .access = PL1_R, .type = ARM_CP_CONST,
1078 .resetvalue = cpu->id_isar4 },
1079 { .name = "ID_ISAR5", .cp = 15, .crn = 0, .crm = 2,
1080 .opc1 = 0, .opc2 = 5, .access = PL1_R, .type = ARM_CP_CONST,
1081 .resetvalue = cpu->id_isar5 },
1082 /* 6..7 are as yet unallocated and must RAZ */
1083 { .name = "ID_ISAR6", .cp = 15, .crn = 0, .crm = 2,
1084 .opc1 = 0, .opc2 = 6, .access = PL1_R, .type = ARM_CP_CONST,
1085 .resetvalue = 0 },
1086 { .name = "ID_ISAR7", .cp = 15, .crn = 0, .crm = 2,
1087 .opc1 = 0, .opc2 = 7, .access = PL1_R, .type = ARM_CP_CONST,
1088 .resetvalue = 0 },
1089 REGINFO_SENTINEL
1090 };
1091 define_arm_cp_regs(cpu, v6_idregs);
7d57f408
PM		 1092 define_arm_cp_regs(cpu, v6_cp_reginfo);
1093 } else {
1094 define_arm_cp_regs(cpu, not_v6_cp_reginfo);
1095 }
4d31c596
PM		 1096 if (arm_feature(env, ARM_FEATURE_V6K)) {
1097 define_arm_cp_regs(cpu, v6k_cp_reginfo);
1098 }
e9aa6c21 1099 if (arm_feature(env, ARM_FEATURE_V7)) {
200ac0ef
PM		 1100 /* v7 performance monitor control register: same implementor
1101 * field as main ID register, and we implement no event counters.
1102 */
1103 ARMCPRegInfo pmcr = {
1104 .name = "PMCR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 0,
1105 .access = PL0_RW, .resetvalue = cpu->midr & 0xff000000,
1106 .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcr),
1107 .readfn = pmreg_read, .writefn = pmcr_write
1108 };
776d4e5c
PM		 1109 ARMCPRegInfo clidr = {
1110 .name = "CLIDR", .cp = 15, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 1,
1111 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = cpu->clidr
1112 };
200ac0ef 1113 define_one_arm_cp_reg(cpu, &pmcr);
776d4e5c 1114 define_one_arm_cp_reg(cpu, &clidr);
e9aa6c21 1115 define_arm_cp_regs(cpu, v7_cp_reginfo);
7d57f408
PM		 1116 } else {
1117 define_arm_cp_regs(cpu, not_v7_cp_reginfo);
e9aa6c21 1118 }
18032bec
PM		 1119 if (arm_feature(env, ARM_FEATURE_MPU)) {
1120 /* These are the MPU registers prior to PMSAv6. Any new
1121 * PMSA core later than the ARM946 will require that we
1122 * implement the PMSAv6 or PMSAv7 registers, which are
1123 * completely different.
1124 */
1125 assert(!arm_feature(env, ARM_FEATURE_V6));
1126 define_arm_cp_regs(cpu, pmsav5_cp_reginfo);
1127 } else {
1128 define_arm_cp_regs(cpu, vmsa_cp_reginfo);
1129 }
c326b979
PM		 1130 if (arm_feature(env, ARM_FEATURE_THUMB2EE)) {
1131 define_arm_cp_regs(cpu, t2ee_cp_reginfo);
1132 }
6cc7a3ae
PM		 1133 if (arm_feature(env, ARM_FEATURE_GENERIC_TIMER)) {
1134 define_arm_cp_regs(cpu, generic_timer_cp_reginfo);
1135 }
4a501606
PM		 1136 if (arm_feature(env, ARM_FEATURE_VAPA)) {
1137 define_arm_cp_regs(cpu, vapa_cp_reginfo);
1138 }
c4804214
PM		 1139 if (arm_feature(env, ARM_FEATURE_CACHE_TEST_CLEAN)) {
1140 define_arm_cp_regs(cpu, cache_test_clean_cp_reginfo);
1141 }
1142 if (arm_feature(env, ARM_FEATURE_CACHE_DIRTY_REG)) {
1143 define_arm_cp_regs(cpu, cache_dirty_status_cp_reginfo);
1144 }
1145 if (arm_feature(env, ARM_FEATURE_CACHE_BLOCK_OPS)) {
1146 define_arm_cp_regs(cpu, cache_block_ops_cp_reginfo);
1147 }
18032bec
PM		 1148 if (arm_feature(env, ARM_FEATURE_OMAPCP)) {
1149 define_arm_cp_regs(cpu, omap_cp_reginfo);
1150 }
34f90529
PM		 1151 if (arm_feature(env, ARM_FEATURE_STRONGARM)) {
1152 define_arm_cp_regs(cpu, strongarm_cp_reginfo);
1153 }
1047b9d7
PM		 1154 if (arm_feature(env, ARM_FEATURE_XSCALE)) {
1155 define_arm_cp_regs(cpu, xscale_cp_reginfo);
1156 }
1157 if (arm_feature(env, ARM_FEATURE_DUMMY_C15_REGS)) {
1158 define_arm_cp_regs(cpu, dummy_c15_cp_reginfo);
1159 }
81bdde9d
PM		 1160 if (arm_feature(env, ARM_FEATURE_MPIDR)) {
1161 define_arm_cp_regs(cpu, mpidr_cp_reginfo);
1162 }
7ac681cf
PM		 1163 if (arm_feature(env, ARM_FEATURE_LPAE)) {
1164 define_arm_cp_regs(cpu, lpae_cp_reginfo);
1165 }
7884849c
PM		 1166 /* Slightly awkwardly, the OMAP and StrongARM cores need all of
1167 * cp15 crn=0 to be writes-ignored, whereas for other cores they should
1168 * be read-only (ie write causes UNDEF exception).
1169 */
1170 {
1171 ARMCPRegInfo id_cp_reginfo[] = {
1172 /* Note that the MIDR isn't a simple constant register because
1173 * of the TI925 behaviour where writes to another register can
1174 * cause the MIDR value to change.
1175 */
1176 { .name = "MIDR",
1177 .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 0,
1178 .access = PL1_R, .resetvalue = cpu->midr,
1179 .writefn = arm_cp_write_ignore,
1180 .fieldoffset = offsetof(CPUARMState, cp15.c0_cpuid) },
1181 { .name = "CTR",
1182 .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 1,
1183 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = cpu->ctr },
1184 { .name = "TCMTR",
1185 .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 2,
1186 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
1187 { .name = "TLBTR",
1188 .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 3,
1189 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
1190 /* crn = 0 op1 = 0 crm = 3..7 : currently unassigned; we RAZ. */
1191 { .name = "DUMMY",
1192 .cp = 15, .crn = 0, .crm = 3, .opc1 = 0, .opc2 = CP_ANY,
1193 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
1194 { .name = "DUMMY",
1195 .cp = 15, .crn = 0, .crm = 4, .opc1 = 0, .opc2 = CP_ANY,
1196 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
1197 { .name = "DUMMY",
1198 .cp = 15, .crn = 0, .crm = 5, .opc1 = 0, .opc2 = CP_ANY,
1199 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
1200 { .name = "DUMMY",
1201 .cp = 15, .crn = 0, .crm = 6, .opc1 = 0, .opc2 = CP_ANY,
1202 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
1203 { .name = "DUMMY",
1204 .cp = 15, .crn = 0, .crm = 7, .opc1 = 0, .opc2 = CP_ANY,
1205 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
1206 REGINFO_SENTINEL
1207 };
1208 ARMCPRegInfo crn0_wi_reginfo = {
1209 .name = "CRN0_WI", .cp = 15, .crn = 0, .crm = CP_ANY,
1210 .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_W,
1211 .type = ARM_CP_NOP | ARM_CP_OVERRIDE
1212 };
1213 if (arm_feature(env, ARM_FEATURE_OMAPCP) ||
1214 arm_feature(env, ARM_FEATURE_STRONGARM)) {
1215 ARMCPRegInfo *r;
1216 /* Register the blanket "writes ignored" value first to cover the
1217 * whole space. Then define the specific ID registers, but update
1218 * their access field to allow write access, so that they ignore
1219 * writes rather than causing them to UNDEF.
1220 */
1221 define_one_arm_cp_reg(cpu, &crn0_wi_reginfo);
1222 for (r = id_cp_reginfo; r->type != ARM_CP_SENTINEL; r++) {
1223 r->access = PL1_RW;
1224 define_one_arm_cp_reg(cpu, r);
1225 }
1226 } else {
1227 /* Just register the standard ID registers (read-only, meaning
1228 * that writes will UNDEF).
1229 */
1230 define_arm_cp_regs(cpu, id_cp_reginfo);
1231 }
1232 }
1233
2771db27
PM		 1234 if (arm_feature(env, ARM_FEATURE_AUXCR)) {
1235 ARMCPRegInfo auxcr = {
1236 .name = "AUXCR", .cp = 15, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 1,
1237 .access = PL1_RW, .type = ARM_CP_CONST,
1238 .resetvalue = cpu->reset_auxcr
1239 };
1240 define_one_arm_cp_reg(cpu, &auxcr);
1241 }
1242
1243 /* Generic registers whose values depend on the implementation */
1244 {
1245 ARMCPRegInfo sctlr = {
1246 .name = "SCTLR", .cp = 15, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 0,
1247 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c1_sys),
1248 .writefn = sctlr_write, .resetvalue = cpu->reset_sctlr
1249 };
1250 if (arm_feature(env, ARM_FEATURE_XSCALE)) {
1251 /* Normally we would always end the TB on an SCTLR write, but Linux
1252 * arch/arm/mach-pxa/sleep.S expects two instructions following
1253 * an MMU enable to execute from cache. Imitate this behaviour.
1254 */
1255 sctlr.type |= ARM_CP_SUPPRESS_TB_END;
1256 }
1257 define_one_arm_cp_reg(cpu, &sctlr);
1258 }
2ceb98c0
PM		 1259}
1260
778c3a06 1261ARMCPU *cpu_arm_init(const char *cpu_model)
40f137e1 1262{
dec9c2d4 1263 ARMCPU *cpu;
40f137e1 1264 CPUARMState *env;
5900d6b2 1265 ObjectClass *oc;
40f137e1 1266
5900d6b2
AF		 1267 oc = cpu_class_by_name(TYPE_ARM_CPU, cpu_model);
1268 if (!oc) {
aaed909a 1269 return NULL;
777dc784 1270 }
5900d6b2 1271 cpu = ARM_CPU(object_new(object_class_get_name(oc)));
dec9c2d4 1272 env = &cpu->env;
777dc784 1273 env->cpu_model_str = cpu_model;
14969266
AF		 1274
1275 /* TODO this should be set centrally, once possible */
1276 object_property_set_bool(OBJECT(cpu), true, "realized", NULL);
777dc784 1277
14969266
AF		 1278 return cpu;
1279}
1280
1281void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu)
1282{
1283 CPUARMState *env = &cpu->env;
1284
56aebc89
PB		 1285 if (arm_feature(env, ARM_FEATURE_NEON)) {
1286 gdb_register_coprocessor(env, vfp_gdb_get_reg, vfp_gdb_set_reg,
1287 51, "arm-neon.xml", 0);
1288 } else if (arm_feature(env, ARM_FEATURE_VFP3)) {
1289 gdb_register_coprocessor(env, vfp_gdb_get_reg, vfp_gdb_set_reg,
1290 35, "arm-vfp3.xml", 0);
1291 } else if (arm_feature(env, ARM_FEATURE_VFP)) {
1292 gdb_register_coprocessor(env, vfp_gdb_get_reg, vfp_gdb_set_reg,
1293 19, "arm-vfp.xml", 0);
1294 }
40f137e1
PB		 1295}
1296
777dc784
PM		 1297/* Sort alphabetically by type name, except for "any". */
1298static gint arm_cpu_list_compare(gconstpointer a, gconstpointer b)
5adb4839 1299{
777dc784
PM		 1300 ObjectClass *class_a = (ObjectClass *)a;
1301 ObjectClass *class_b = (ObjectClass *)b;
1302 const char *name_a, *name_b;
5adb4839 1303
777dc784
PM		 1304 name_a = object_class_get_name(class_a);
1305 name_b = object_class_get_name(class_b);
51492fd1 1306 if (strcmp(name_a, "any-" TYPE_ARM_CPU) == 0) {
777dc784 1307 return 1;
51492fd1 1308 } else if (strcmp(name_b, "any-" TYPE_ARM_CPU) == 0) {
777dc784
PM		 1309 return -1;
1310 } else {
1311 return strcmp(name_a, name_b);
5adb4839
PB		 1312 }
1313}
1314
777dc784 1315static void arm_cpu_list_entry(gpointer data, gpointer user_data)
40f137e1 1316{
777dc784 1317 ObjectClass *oc = data;
92a31361 1318 CPUListState *s = user_data;
51492fd1
AF		 1319 const char *typename;
1320 char *name;
3371d272 1321
51492fd1
AF		 1322 typename = object_class_get_name(oc);
1323 name = g_strndup(typename, strlen(typename) - strlen("-" TYPE_ARM_CPU));
777dc784 1324 (*s->cpu_fprintf)(s->file, " %s\n",
51492fd1
AF		 1325 name);
1326 g_free(name);
777dc784
PM		 1327}
1328
1329void arm_cpu_list(FILE *f, fprintf_function cpu_fprintf)
1330{
92a31361 1331 CPUListState s = {
777dc784
PM		 1332 .file = f,
1333 .cpu_fprintf = cpu_fprintf,
1334 };
1335 GSList *list;
1336
1337 list = object_class_get_list(TYPE_ARM_CPU, false);
1338 list = g_slist_sort(list, arm_cpu_list_compare);
1339 (*cpu_fprintf)(f, "Available CPUs:\n");
1340 g_slist_foreach(list, arm_cpu_list_entry, &s);
1341 g_slist_free(list);
40f137e1
PB		 1342}
1343
4b6a83fb
PM		 1344void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu,
1345 const ARMCPRegInfo *r, void *opaque)
1346{
1347 /* Define implementations of coprocessor registers.
1348 * We store these in a hashtable because typically
1349 * there are less than 150 registers in a space which
1350 * is 16*16*16*8*8 = 262144 in size.
1351 * Wildcarding is supported for the crm, opc1 and opc2 fields.
1352 * If a register is defined twice then the second definition is
1353 * used, so this can be used to define some generic registers and
1354 * then override them with implementation specific variations.
1355 * At least one of the original and the second definition should
1356 * include ARM_CP_OVERRIDE in its type bits -- this is just a guard
1357 * against accidental use.
1358 */
1359 int crm, opc1, opc2;
1360 int crmmin = (r->crm == CP_ANY) ? 0 : r->crm;
1361 int crmmax = (r->crm == CP_ANY) ? 15 : r->crm;
1362 int opc1min = (r->opc1 == CP_ANY) ? 0 : r->opc1;
1363 int opc1max = (r->opc1 == CP_ANY) ? 7 : r->opc1;
1364 int opc2min = (r->opc2 == CP_ANY) ? 0 : r->opc2;
1365 int opc2max = (r->opc2 == CP_ANY) ? 7 : r->opc2;
1366 /* 64 bit registers have only CRm and Opc1 fields */
1367 assert(!((r->type & ARM_CP_64BIT) && (r->opc2 || r->crn)));
1368 /* Check that the register definition has enough info to handle
1369 * reads and writes if they are permitted.
1370 */
1371 if (!(r->type & (ARM_CP_SPECIAL|ARM_CP_CONST))) {
1372 if (r->access & PL3_R) {
1373 assert(r->fieldoffset || r->readfn);
1374 }
1375 if (r->access & PL3_W) {
1376 assert(r->fieldoffset || r->writefn);
1377 }
1378 }
1379 /* Bad type field probably means missing sentinel at end of reg list */
1380 assert(cptype_valid(r->type));
1381 for (crm = crmmin; crm <= crmmax; crm++) {
1382 for (opc1 = opc1min; opc1 <= opc1max; opc1++) {
1383 for (opc2 = opc2min; opc2 <= opc2max; opc2++) {
1384 uint32_t *key = g_new(uint32_t, 1);
1385 ARMCPRegInfo *r2 = g_memdup(r, sizeof(ARMCPRegInfo));
1386 int is64 = (r->type & ARM_CP_64BIT) ? 1 : 0;
1387 *key = ENCODE_CP_REG(r->cp, is64, r->crn, crm, opc1, opc2);
1388 r2->opaque = opaque;
1389 /* Make sure reginfo passed to helpers for wildcarded regs
1390 * has the correct crm/opc1/opc2 for this reg, not CP_ANY:
1391 */
1392 r2->crm = crm;
1393 r2->opc1 = opc1;
1394 r2->opc2 = opc2;
7023ec7e
PM		 1395 /* By convention, for wildcarded registers only the first
1396 * entry is used for migration; the others are marked as
1397 * NO_MIGRATE so we don't try to transfer the register
1398 * multiple times. Special registers (ie NOP/WFI) are
1399 * never migratable.
1400 */
1401 if ((r->type & ARM_CP_SPECIAL) ||
1402 ((r->crm == CP_ANY) && crm != 0) ||
1403 ((r->opc1 == CP_ANY) && opc1 != 0) ||
1404 ((r->opc2 == CP_ANY) && opc2 != 0)) {
1405 r2->type |= ARM_CP_NO_MIGRATE;
1406 }
1407
4b6a83fb
PM		 1408 /* Overriding of an existing definition must be explicitly
1409 * requested.
1410 */
1411 if (!(r->type & ARM_CP_OVERRIDE)) {
1412 ARMCPRegInfo *oldreg;
1413 oldreg = g_hash_table_lookup(cpu->cp_regs, key);
1414 if (oldreg && !(oldreg->type & ARM_CP_OVERRIDE)) {
1415 fprintf(stderr, "Register redefined: cp=%d %d bit "
1416 "crn=%d crm=%d opc1=%d opc2=%d, "
1417 "was %s, now %s\n", r2->cp, 32 + 32 * is64,
1418 r2->crn, r2->crm, r2->opc1, r2->opc2,
1419 oldreg->name, r2->name);
1420 assert(0);
1421 }
1422 }
1423 g_hash_table_insert(cpu->cp_regs, key, r2);
1424 }
1425 }
1426 }
1427}
1428
1429void define_arm_cp_regs_with_opaque(ARMCPU *cpu,
1430 const ARMCPRegInfo *regs, void *opaque)
1431{
1432 /* Define a whole list of registers */
1433 const ARMCPRegInfo *r;
1434 for (r = regs; r->type != ARM_CP_SENTINEL; r++) {
1435 define_one_arm_cp_reg_with_opaque(cpu, r, opaque);
1436 }
1437}
1438
1439const ARMCPRegInfo *get_arm_cp_reginfo(ARMCPU *cpu, uint32_t encoded_cp)
1440{
1441 return g_hash_table_lookup(cpu->cp_regs, &encoded_cp);
1442}
1443
1444int arm_cp_write_ignore(CPUARMState *env, const ARMCPRegInfo *ri,
1445 uint64_t value)
1446{
1447 /* Helper coprocessor write function for write-ignore registers */
1448 return 0;
1449}
1450
1451int arm_cp_read_zero(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t *value)
1452{
1453 /* Helper coprocessor write function for read-as-zero registers */
1454 *value = 0;
1455 return 0;
1456}
1457
0ecb72a5 1458static int bad_mode_switch(CPUARMState *env, int mode)
37064a8b
PM		 1459{
1460 /* Return true if it is not valid for us to switch to
1461 * this CPU mode (ie all the UNPREDICTABLE cases in
1462 * the ARM ARM CPSRWriteByInstr pseudocode).
1463 */
1464 switch (mode) {
1465 case ARM_CPU_MODE_USR:
1466 case ARM_CPU_MODE_SYS:
1467 case ARM_CPU_MODE_SVC:
1468 case ARM_CPU_MODE_ABT:
1469 case ARM_CPU_MODE_UND:
1470 case ARM_CPU_MODE_IRQ:
1471 case ARM_CPU_MODE_FIQ:
1472 return 0;
1473 default:
1474 return 1;
1475 }
1476}
1477
2f4a40e5
AZ		 1478uint32_t cpsr_read(CPUARMState *env)
1479{
1480 int ZF;
6fbe23d5
PB		 1481 ZF = (env->ZF == 0);
1482 return env->uncached_cpsr | (env->NF & 0x80000000) | (ZF << 30) |
2f4a40e5
AZ		 1483 (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27)
1484 | (env->thumb << 5) | ((env->condexec_bits & 3) << 25)
1485 | ((env->condexec_bits & 0xfc) << 8)
1486 | (env->GE << 16);
1487}
1488
1489void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask)
1490{
2f4a40e5 1491 if (mask & CPSR_NZCV) {
6fbe23d5
PB		 1492 env->ZF = (~val) & CPSR_Z;
1493 env->NF = val;
2f4a40e5
AZ		 1494 env->CF = (val >> 29) & 1;
1495 env->VF = (val << 3) & 0x80000000;
1496 }
1497 if (mask & CPSR_Q)
1498 env->QF = ((val & CPSR_Q) != 0);
1499 if (mask & CPSR_T)
1500 env->thumb = ((val & CPSR_T) != 0);
1501 if (mask & CPSR_IT_0_1) {
1502 env->condexec_bits &= ~3;
1503 env->condexec_bits |= (val >> 25) & 3;
1504 }
1505 if (mask & CPSR_IT_2_7) {
1506 env->condexec_bits &= 3;
1507 env->condexec_bits |= (val >> 8) & 0xfc;
1508 }
1509 if (mask & CPSR_GE) {
1510 env->GE = (val >> 16) & 0xf;
1511 }
1512
1513 if ((env->uncached_cpsr ^ val) & mask & CPSR_M) {
37064a8b
PM		 1514 if (bad_mode_switch(env, val & CPSR_M)) {
1515 /* Attempt to switch to an invalid mode: this is UNPREDICTABLE.
1516 * We choose to ignore the attempt and leave the CPSR M field
1517 * untouched.
1518 */
1519 mask &= ~CPSR_M;
1520 } else {
1521 switch_mode(env, val & CPSR_M);
1522 }
2f4a40e5
AZ		 1523 }
1524 mask &= ~CACHED_CPSR_BITS;
1525 env->uncached_cpsr = (env->uncached_cpsr & ~mask) | (val & mask);
1526}
1527
b26eefb6
PB		 1528/* Sign/zero extend */
1529uint32_t HELPER(sxtb16)(uint32_t x)
1530{
1531 uint32_t res;
1532 res = (uint16_t)(int8_t)x;
1533 res |= (uint32_t)(int8_t)(x >> 16) << 16;
1534 return res;
1535}
1536
1537uint32_t HELPER(uxtb16)(uint32_t x)
1538{
1539 uint32_t res;
1540 res = (uint16_t)(uint8_t)x;
1541 res |= (uint32_t)(uint8_t)(x >> 16) << 16;
1542 return res;
1543}
1544
f51bbbfe
PB		 1545uint32_t HELPER(clz)(uint32_t x)
1546{
7bbcb0af 1547 return clz32(x);
f51bbbfe
PB		 1548}
1549
3670669c
PB		 1550int32_t HELPER(sdiv)(int32_t num, int32_t den)
1551{
1552 if (den == 0)
1553 return 0;
686eeb93
AJ		 1554 if (num == INT_MIN && den == -1)
1555 return INT_MIN;
3670669c
PB		 1556 return num / den;
1557}
1558
1559uint32_t HELPER(udiv)(uint32_t num, uint32_t den)
1560{
1561 if (den == 0)
1562 return 0;
1563 return num / den;
1564}
1565
1566uint32_t HELPER(rbit)(uint32_t x)
1567{
1568 x = ((x & 0xff000000) >> 24)
1569 | ((x & 0x00ff0000) >> 8)
1570 | ((x & 0x0000ff00) << 8)
1571 | ((x & 0x000000ff) << 24);
1572 x = ((x & 0xf0f0f0f0) >> 4)
1573 | ((x & 0x0f0f0f0f) << 4);
1574 x = ((x & 0x88888888) >> 3)
1575 | ((x & 0x44444444) >> 1)
1576 | ((x & 0x22222222) << 1)
1577 | ((x & 0x11111111) << 3);
1578 return x;
1579}
1580
5fafdf24 1581#if defined(CONFIG_USER_ONLY)
b5ff1b31 1582
97a8ea5a 1583void arm_cpu_do_interrupt(CPUState *cs)
b5ff1b31 1584{
97a8ea5a
AF		 1585 ARMCPU *cpu = ARM_CPU(cs);
1586 CPUARMState *env = &cpu->env;
1587
b5ff1b31
FB		 1588 env->exception_index = -1;
1589}
1590
0ecb72a5 1591int cpu_arm_handle_mmu_fault (CPUARMState *env, target_ulong address, int rw,
97b348e7 1592 int mmu_idx)
b5ff1b31
FB		 1593{
1594 if (rw == 2) {
1595 env->exception_index = EXCP_PREFETCH_ABORT;
1596 env->cp15.c6_insn = address;
1597 } else {
1598 env->exception_index = EXCP_DATA_ABORT;
1599 env->cp15.c6_data = address;
1600 }
1601 return 1;
1602}
1603
9ee6e8bb 1604/* These should probably raise undefined insn exceptions. */
0ecb72a5 1605void HELPER(v7m_msr)(CPUARMState *env, uint32_t reg, uint32_t val)
9ee6e8bb
PB		 1606{
1607 cpu_abort(env, "v7m_mrs %d\n", reg);
1608}
1609
0ecb72a5 1610uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg)
9ee6e8bb
PB		 1611{
1612 cpu_abort(env, "v7m_mrs %d\n", reg);
1613 return 0;
1614}
1615
0ecb72a5 1616void switch_mode(CPUARMState *env, int mode)
b5ff1b31
FB		 1617{
1618 if (mode != ARM_CPU_MODE_USR)
1619 cpu_abort(env, "Tried to switch out of user mode\n");
1620}
1621
0ecb72a5 1622void HELPER(set_r13_banked)(CPUARMState *env, uint32_t mode, uint32_t val)
9ee6e8bb
PB		 1623{
1624 cpu_abort(env, "banked r13 write\n");
1625}
1626
0ecb72a5 1627uint32_t HELPER(get_r13_banked)(CPUARMState *env, uint32_t mode)
9ee6e8bb
PB		 1628{
1629 cpu_abort(env, "banked r13 read\n");
1630 return 0;
1631}
1632
b5ff1b31
FB		 1633#else
1634
1635/* Map CPU modes onto saved register banks. */
494b00c7 1636int bank_number(int mode)
b5ff1b31
FB		 1637{
1638 switch (mode) {
1639 case ARM_CPU_MODE_USR:
1640 case ARM_CPU_MODE_SYS:
1641 return 0;
1642 case ARM_CPU_MODE_SVC:
1643 return 1;
1644 case ARM_CPU_MODE_ABT:
1645 return 2;
1646 case ARM_CPU_MODE_UND:
1647 return 3;
1648 case ARM_CPU_MODE_IRQ:
1649 return 4;
1650 case ARM_CPU_MODE_FIQ:
1651 return 5;
1652 }
f5206413 1653 hw_error("bank number requested for bad CPSR mode value 0x%x\n", mode);
b5ff1b31
FB		 1654}
1655
0ecb72a5 1656void switch_mode(CPUARMState *env, int mode)
b5ff1b31
FB		 1657{
1658 int old_mode;
1659 int i;
1660
1661 old_mode = env->uncached_cpsr & CPSR_M;
1662 if (mode == old_mode)
1663 return;
1664
1665 if (old_mode == ARM_CPU_MODE_FIQ) {
1666 memcpy (env->fiq_regs, env->regs + 8, 5 * sizeof(uint32_t));
8637c67f 1667 memcpy (env->regs + 8, env->usr_regs, 5 * sizeof(uint32_t));
b5ff1b31
FB		 1668 } else if (mode == ARM_CPU_MODE_FIQ) {
1669 memcpy (env->usr_regs, env->regs + 8, 5 * sizeof(uint32_t));
8637c67f 1670 memcpy (env->regs + 8, env->fiq_regs, 5 * sizeof(uint32_t));
b5ff1b31
FB		 1671 }
1672
f5206413 1673 i = bank_number(old_mode);
b5ff1b31
FB		 1674 env->banked_r13[i] = env->regs[13];
1675 env->banked_r14[i] = env->regs[14];
1676 env->banked_spsr[i] = env->spsr;
1677
f5206413 1678 i = bank_number(mode);
b5ff1b31
FB		 1679 env->regs[13] = env->banked_r13[i];
1680 env->regs[14] = env->banked_r14[i];
1681 env->spsr = env->banked_spsr[i];
1682}
1683
9ee6e8bb
PB		 1684static void v7m_push(CPUARMState *env, uint32_t val)
1685{
1686 env->regs[13] -= 4;
1687 stl_phys(env->regs[13], val);
1688}
1689
1690static uint32_t v7m_pop(CPUARMState *env)
1691{
1692 uint32_t val;
1693 val = ldl_phys(env->regs[13]);
1694 env->regs[13] += 4;
1695 return val;
1696}
1697
1698/* Switch to V7M main or process stack pointer. */
1699static void switch_v7m_sp(CPUARMState *env, int process)
1700{
1701 uint32_t tmp;
1702 if (env->v7m.current_sp != process) {
1703 tmp = env->v7m.other_sp;
1704 env->v7m.other_sp = env->regs[13];
1705 env->regs[13] = tmp;
1706 env->v7m.current_sp = process;
1707 }
1708}
1709
1710static void do_v7m_exception_exit(CPUARMState *env)
1711{
1712 uint32_t type;
1713 uint32_t xpsr;
1714
1715 type = env->regs[15];
1716 if (env->v7m.exception != 0)
983fe826 1717 armv7m_nvic_complete_irq(env->nvic, env->v7m.exception);
9ee6e8bb
PB		 1718
1719 /* Switch to the target stack. */
1720 switch_v7m_sp(env, (type & 4) != 0);
1721 /* Pop registers. */
1722 env->regs[0] = v7m_pop(env);
1723 env->regs[1] = v7m_pop(env);
1724 env->regs[2] = v7m_pop(env);
1725 env->regs[3] = v7m_pop(env);
1726 env->regs[12] = v7m_pop(env);
1727 env->regs[14] = v7m_pop(env);
1728 env->regs[15] = v7m_pop(env);
1729 xpsr = v7m_pop(env);
1730 xpsr_write(env, xpsr, 0xfffffdff);
1731 /* Undo stack alignment. */
1732 if (xpsr & 0x200)
1733 env->regs[13] |= 4;
1734 /* ??? The exception return type specifies Thread/Handler mode. However
1735 this is also implied by the xPSR value. Not sure what to do
1736 if there is a mismatch. */
1737 /* ??? Likewise for mismatches between the CONTROL register and the stack
1738 pointer. */
1739}
1740
e6f010cc 1741void arm_v7m_cpu_do_interrupt(CPUState *cs)
9ee6e8bb 1742{
e6f010cc
AF		 1743 ARMCPU *cpu = ARM_CPU(cs);
1744 CPUARMState *env = &cpu->env;
9ee6e8bb
PB		 1745 uint32_t xpsr = xpsr_read(env);
1746 uint32_t lr;
1747 uint32_t addr;
1748
1749 lr = 0xfffffff1;
1750 if (env->v7m.current_sp)
1751 lr |= 4;
1752 if (env->v7m.exception == 0)
1753 lr |= 8;
1754
1755 /* For exceptions we just mark as pending on the NVIC, and let that
1756 handle it. */
1757 /* TODO: Need to escalate if the current priority is higher than the
1758 one we're raising. */
1759 switch (env->exception_index) {
1760 case EXCP_UDEF:
983fe826 1761 armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE);
9ee6e8bb
PB		 1762 return;
1763 case EXCP_SWI:
314e2296 1764 /* The PC already points to the next instruction. */
983fe826 1765 armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_SVC);
9ee6e8bb
PB		 1766 return;
1767 case EXCP_PREFETCH_ABORT:
1768 case EXCP_DATA_ABORT:
983fe826 1769 armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_MEM);
9ee6e8bb
PB		 1770 return;
1771 case EXCP_BKPT:
2ad207d4
PB		 1772 if (semihosting_enabled) {
1773 int nr;
d31dd73e 1774 nr = arm_lduw_code(env, env->regs[15], env->bswap_code) & 0xff;
2ad207d4
PB		 1775 if (nr == 0xab) {
1776 env->regs[15] += 2;
1777 env->regs[0] = do_arm_semihosting(env);
1778 return;
1779 }
1780 }
983fe826 1781 armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_DEBUG);
9ee6e8bb
PB		 1782 return;
1783 case EXCP_IRQ:
983fe826 1784 env->v7m.exception = armv7m_nvic_acknowledge_irq(env->nvic);
9ee6e8bb
PB		 1785 break;
1786 case EXCP_EXCEPTION_EXIT:
1787 do_v7m_exception_exit(env);
1788 return;
1789 default:
1790 cpu_abort(env, "Unhandled exception 0x%x\n", env->exception_index);
1791 return; /* Never happens. Keep compiler happy. */
1792 }
1793
1794 /* Align stack pointer. */
1795 /* ??? Should only do this if Configuration Control Register
1796 STACKALIGN bit is set. */
1797 if (env->regs[13] & 4) {
ab19b0ec 1798 env->regs[13] -= 4;
9ee6e8bb
PB		 1799 xpsr |= 0x200;
1800 }
6c95676b 1801 /* Switch to the handler mode. */
9ee6e8bb
PB		 1802 v7m_push(env, xpsr);
1803 v7m_push(env, env->regs[15]);
1804 v7m_push(env, env->regs[14]);
1805 v7m_push(env, env->regs[12]);
1806 v7m_push(env, env->regs[3]);
1807 v7m_push(env, env->regs[2]);
1808 v7m_push(env, env->regs[1]);
1809 v7m_push(env, env->regs[0]);
1810 switch_v7m_sp(env, 0);
c98d174c
PM		 1811 /* Clear IT bits */
1812 env->condexec_bits = 0;
9ee6e8bb
PB		 1813 env->regs[14] = lr;
1814 addr = ldl_phys(env->v7m.vecbase + env->v7m.exception * 4);
1815 env->regs[15] = addr & 0xfffffffe;
1816 env->thumb = addr & 1;
1817}
1818
b5ff1b31 1819/* Handle a CPU exception. */
97a8ea5a 1820void arm_cpu_do_interrupt(CPUState *cs)
b5ff1b31 1821{
97a8ea5a
AF		 1822 ARMCPU *cpu = ARM_CPU(cs);
1823 CPUARMState *env = &cpu->env;
b5ff1b31
FB		 1824 uint32_t addr;
1825 uint32_t mask;
1826 int new_mode;
1827 uint32_t offset;
1828
e6f010cc
AF		 1829 assert(!IS_M(env));
1830
b5ff1b31
FB		 1831 /* TODO: Vectored interrupt controller. */
1832 switch (env->exception_index) {
1833 case EXCP_UDEF:
1834 new_mode = ARM_CPU_MODE_UND;
1835 addr = 0x04;
1836 mask = CPSR_I;
1837 if (env->thumb)
1838 offset = 2;
1839 else
1840 offset = 4;
1841 break;
1842 case EXCP_SWI:
8e71621f
PB		 1843 if (semihosting_enabled) {
1844 /* Check for semihosting interrupt. */
1845 if (env->thumb) {
d31dd73e
BS		 1846 mask = arm_lduw_code(env, env->regs[15] - 2, env->bswap_code)
1847 & 0xff;
8e71621f 1848 } else {
d31dd73e 1849 mask = arm_ldl_code(env, env->regs[15] - 4, env->bswap_code)
d8fd2954 1850 & 0xffffff;
8e71621f
PB		 1851 }
1852 /* Only intercept calls from privileged modes, to provide some
1853 semblance of security. */
1854 if (((mask == 0x123456 && !env->thumb)
1855 || (mask == 0xab && env->thumb))
1856 && (env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR) {
1857 env->regs[0] = do_arm_semihosting(env);
1858 return;
1859 }
1860 }
b5ff1b31
FB		 1861 new_mode = ARM_CPU_MODE_SVC;
1862 addr = 0x08;
1863 mask = CPSR_I;
601d70b9 1864 /* The PC already points to the next instruction. */
b5ff1b31
FB		 1865 offset = 0;
1866 break;
06c949e6 1867 case EXCP_BKPT:
9ee6e8bb 1868 /* See if this is a semihosting syscall. */
2ad207d4 1869 if (env->thumb && semihosting_enabled) {
d31dd73e 1870 mask = arm_lduw_code(env, env->regs[15], env->bswap_code) & 0xff;
9ee6e8bb
PB		 1871 if (mask == 0xab
1872 && (env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR) {
1873 env->regs[15] += 2;
1874 env->regs[0] = do_arm_semihosting(env);
1875 return;
1876 }
1877 }
81c05daf 1878 env->cp15.c5_insn = 2;
9ee6e8bb
PB		 1879 /* Fall through to prefetch abort. */
1880 case EXCP_PREFETCH_ABORT:
b5ff1b31
FB		 1881 new_mode = ARM_CPU_MODE_ABT;
1882 addr = 0x0c;
1883 mask = CPSR_A | CPSR_I;
1884 offset = 4;
1885 break;
1886 case EXCP_DATA_ABORT:
1887 new_mode = ARM_CPU_MODE_ABT;
1888 addr = 0x10;
1889 mask = CPSR_A | CPSR_I;
1890 offset = 8;
1891 break;
1892 case EXCP_IRQ:
1893 new_mode = ARM_CPU_MODE_IRQ;
1894 addr = 0x18;
1895 /* Disable IRQ and imprecise data aborts. */
1896 mask = CPSR_A | CPSR_I;
1897 offset = 4;
1898 break;
1899 case EXCP_FIQ:
1900 new_mode = ARM_CPU_MODE_FIQ;
1901 addr = 0x1c;
1902 /* Disable FIQ, IRQ and imprecise data aborts. */
1903 mask = CPSR_A | CPSR_I | CPSR_F;
1904 offset = 4;
1905 break;
1906 default:
1907 cpu_abort(env, "Unhandled exception 0x%x\n", env->exception_index);
1908 return; /* Never happens. Keep compiler happy. */
1909 }
1910 /* High vectors. */
1911 if (env->cp15.c1_sys & (1 << 13)) {
1912 addr += 0xffff0000;
1913 }
1914 switch_mode (env, new_mode);
1915 env->spsr = cpsr_read(env);
9ee6e8bb
PB		 1916 /* Clear IT bits. */
1917 env->condexec_bits = 0;
30a8cac1 1918 /* Switch to the new mode, and to the correct instruction set. */
6d7e6326 1919 env->uncached_cpsr = (env->uncached_cpsr & ~CPSR_M) | new_mode;
b5ff1b31 1920 env->uncached_cpsr |= mask;
be5e7a76
DES		 1921 /* this is a lie, as the was no c1_sys on V4T/V5, but who cares
1922 * and we should just guard the thumb mode on V4 */
1923 if (arm_feature(env, ARM_FEATURE_V4T)) {
1924 env->thumb = (env->cp15.c1_sys & (1 << 30)) != 0;
1925 }
b5ff1b31
FB		 1926 env->regs[14] = env->regs[15] + offset;
1927 env->regs[15] = addr;
259186a7 1928 cs->interrupt_request |= CPU_INTERRUPT_EXITTB;
b5ff1b31
FB		 1929}
1930
1931/* Check section/page access permissions.
1932 Returns the page protection flags, or zero if the access is not
1933 permitted. */
0ecb72a5 1934static inline int check_ap(CPUARMState *env, int ap, int domain_prot,
dd4ebc2e 1935 int access_type, int is_user)
b5ff1b31 1936{
9ee6e8bb
PB		 1937 int prot_ro;
1938
dd4ebc2e 1939 if (domain_prot == 3) {
b5ff1b31 1940 return PAGE_READ | PAGE_WRITE;
dd4ebc2e 1941 }
b5ff1b31 1942
9ee6e8bb
PB		 1943 if (access_type == 1)
1944 prot_ro = 0;
1945 else
1946 prot_ro = PAGE_READ;
1947
b5ff1b31
FB		 1948 switch (ap) {
1949 case 0:
78600320 1950 if (access_type == 1)
b5ff1b31
FB		 1951 return 0;
1952 switch ((env->cp15.c1_sys >> 8) & 3) {
1953 case 1:
1954 return is_user ? 0 : PAGE_READ;
1955 case 2:
1956 return PAGE_READ;
1957 default:
1958 return 0;
1959 }
1960 case 1:
1961 return is_user ? 0 : PAGE_READ | PAGE_WRITE;
1962 case 2:
1963 if (is_user)
9ee6e8bb 1964 return prot_ro;
b5ff1b31
FB		 1965 else
1966 return PAGE_READ | PAGE_WRITE;
1967 case 3:
1968 return PAGE_READ | PAGE_WRITE;
d4934d18 1969 case 4: /* Reserved. */
9ee6e8bb
PB		 1970 return 0;
1971 case 5:
1972 return is_user ? 0 : prot_ro;
1973 case 6:
1974 return prot_ro;
d4934d18 1975 case 7:
0ab06d83 1976 if (!arm_feature (env, ARM_FEATURE_V6K))
d4934d18
PB		 1977 return 0;
1978 return prot_ro;
b5ff1b31
FB		 1979 default:
1980 abort();
1981 }
1982}
1983
0ecb72a5 1984static uint32_t get_level1_table_address(CPUARMState *env, uint32_t address)
b2fa1797
PB		 1985{
1986 uint32_t table;
1987
1988 if (address & env->cp15.c2_mask)
1989 table = env->cp15.c2_base1 & 0xffffc000;
1990 else
1991 table = env->cp15.c2_base0 & env->cp15.c2_base_mask;
1992
1993 table |= (address >> 18) & 0x3ffc;
1994 return table;
1995}
1996
0ecb72a5 1997static int get_phys_addr_v5(CPUARMState *env, uint32_t address, int access_type,
a8170e5e 1998 int is_user, hwaddr *phys_ptr,
77a71dd1 1999 int *prot, target_ulong *page_size)
b5ff1b31
FB		 2000{
2001 int code;
2002 uint32_t table;
2003 uint32_t desc;
2004 int type;
2005 int ap;
2006 int domain;
dd4ebc2e 2007 int domain_prot;
a8170e5e 2008 hwaddr phys_addr;
b5ff1b31 2009
9ee6e8bb
PB		 2010 /* Pagetable walk. */
2011 /* Lookup l1 descriptor. */
b2fa1797 2012 table = get_level1_table_address(env, address);
9ee6e8bb
PB		 2013 desc = ldl_phys(table);
2014 type = (desc & 3);
dd4ebc2e
JCD		 2015 domain = (desc >> 5) & 0x0f;
2016 domain_prot = (env->cp15.c3 >> (domain * 2)) & 3;
9ee6e8bb 2017 if (type == 0) {
601d70b9 2018 /* Section translation fault. */
9ee6e8bb
PB		 2019 code = 5;
2020 goto do_fault;
2021 }
dd4ebc2e 2022 if (domain_prot == 0 || domain_prot == 2) {
9ee6e8bb
PB		 2023 if (type == 2)
2024 code = 9; /* Section domain fault. */
2025 else
2026 code = 11; /* Page domain fault. */
2027 goto do_fault;
2028 }
2029 if (type == 2) {
2030 /* 1Mb section. */
2031 phys_addr = (desc & 0xfff00000) | (address & 0x000fffff);
2032 ap = (desc >> 10) & 3;
2033 code = 13;
d4c430a8 2034 *page_size = 1024 * 1024;
9ee6e8bb
PB		 2035 } else {
2036 /* Lookup l2 entry. */
2037 if (type == 1) {
2038 /* Coarse pagetable. */
2039 table = (desc & 0xfffffc00) | ((address >> 10) & 0x3fc);
2040 } else {
2041 /* Fine pagetable. */
2042 table = (desc & 0xfffff000) | ((address >> 8) & 0xffc);
2043 }
2044 desc = ldl_phys(table);
2045 switch (desc & 3) {
2046 case 0: /* Page translation fault. */
2047 code = 7;
2048 goto do_fault;
2049 case 1: /* 64k page. */
2050 phys_addr = (desc & 0xffff0000) | (address & 0xffff);
2051 ap = (desc >> (4 + ((address >> 13) & 6))) & 3;
d4c430a8 2052 *page_size = 0x10000;
ce819861 2053 break;
9ee6e8bb
PB		 2054 case 2: /* 4k page. */
2055 phys_addr = (desc & 0xfffff000) | (address & 0xfff);
2056 ap = (desc >> (4 + ((address >> 13) & 6))) & 3;
d4c430a8 2057 *page_size = 0x1000;
ce819861 2058 break;
9ee6e8bb
PB		 2059 case 3: /* 1k page. */
2060 if (type == 1) {
2061 if (arm_feature(env, ARM_FEATURE_XSCALE)) {
2062 phys_addr = (desc & 0xfffff000) | (address & 0xfff);
2063 } else {
2064 /* Page translation fault. */
2065 code = 7;
2066 goto do_fault;
2067 }
2068 } else {
2069 phys_addr = (desc & 0xfffffc00) | (address & 0x3ff);
2070 }
2071 ap = (desc >> 4) & 3;
d4c430a8 2072 *page_size = 0x400;
ce819861
PB		 2073 break;
2074 default:
9ee6e8bb
PB		 2075 /* Never happens, but compiler isn't smart enough to tell. */
2076 abort();
ce819861 2077 }
9ee6e8bb
PB		 2078 code = 15;
2079 }
dd4ebc2e 2080 *prot = check_ap(env, ap, domain_prot, access_type, is_user);
9ee6e8bb
PB		 2081 if (!*prot) {
2082 /* Access permission fault. */
2083 goto do_fault;
2084 }
3ad493fc 2085 *prot |= PAGE_EXEC;
9ee6e8bb
PB		 2086 *phys_ptr = phys_addr;
2087 return 0;
2088do_fault:
2089 return code | (domain << 4);
2090}
2091
0ecb72a5 2092static int get_phys_addr_v6(CPUARMState *env, uint32_t address, int access_type,
a8170e5e 2093 int is_user, hwaddr *phys_ptr,
77a71dd1 2094 int *prot, target_ulong *page_size)
9ee6e8bb
PB		 2095{
2096 int code;
2097 uint32_t table;
2098 uint32_t desc;
2099 uint32_t xn;
de9b05b8 2100 uint32_t pxn = 0;
9ee6e8bb
PB		 2101 int type;
2102 int ap;
de9b05b8 2103 int domain = 0;
dd4ebc2e 2104 int domain_prot;
a8170e5e 2105 hwaddr phys_addr;
9ee6e8bb
PB		 2106
2107 /* Pagetable walk. */
2108 /* Lookup l1 descriptor. */
b2fa1797 2109 table = get_level1_table_address(env, address);
9ee6e8bb
PB		 2110 desc = ldl_phys(table);
2111 type = (desc & 3);
de9b05b8
PM		 2112 if (type == 0 || (type == 3 && !arm_feature(env, ARM_FEATURE_PXN))) {
2113 /* Section translation fault, or attempt to use the encoding
2114 * which is Reserved on implementations without PXN.
2115 */
9ee6e8bb 2116 code = 5;
9ee6e8bb 2117 goto do_fault;
de9b05b8
PM		 2118 }
2119 if ((type == 1) || !(desc & (1 << 18))) {
2120 /* Page or Section. */
dd4ebc2e 2121 domain = (desc >> 5) & 0x0f;
9ee6e8bb 2122 }
dd4ebc2e
JCD		 2123 domain_prot = (env->cp15.c3 >> (domain * 2)) & 3;
2124 if (domain_prot == 0 || domain_prot == 2) {
de9b05b8 2125 if (type != 1) {
9ee6e8bb 2126 code = 9; /* Section domain fault. */
de9b05b8 2127 } else {
9ee6e8bb 2128 code = 11; /* Page domain fault. */
de9b05b8 2129 }
9ee6e8bb
PB		 2130 goto do_fault;
2131 }
de9b05b8 2132 if (type != 1) {
9ee6e8bb
PB		 2133 if (desc & (1 << 18)) {
2134 /* Supersection. */
2135 phys_addr = (desc & 0xff000000) | (address & 0x00ffffff);
d4c430a8 2136 *page_size = 0x1000000;
b5ff1b31 2137 } else {
9ee6e8bb
PB		 2138 /* Section. */
2139 phys_addr = (desc & 0xfff00000) | (address & 0x000fffff);
d4c430a8 2140 *page_size = 0x100000;
b5ff1b31 2141 }
9ee6e8bb
PB		 2142 ap = ((desc >> 10) & 3) | ((desc >> 13) & 4);
2143 xn = desc & (1 << 4);
de9b05b8 2144 pxn = desc & 1;
9ee6e8bb
PB		 2145 code = 13;
2146 } else {
de9b05b8
PM		 2147 if (arm_feature(env, ARM_FEATURE_PXN)) {
2148 pxn = (desc >> 2) & 1;
2149 }
9ee6e8bb
PB		 2150 /* Lookup l2 entry. */
2151 table = (desc & 0xfffffc00) | ((address >> 10) & 0x3fc);
2152 desc = ldl_phys(table);
2153 ap = ((desc >> 4) & 3) | ((desc >> 7) & 4);
2154 switch (desc & 3) {
2155 case 0: /* Page translation fault. */
2156 code = 7;
b5ff1b31 2157 goto do_fault;
9ee6e8bb
PB		 2158 case 1: /* 64k page. */
2159 phys_addr = (desc & 0xffff0000) | (address & 0xffff);
2160 xn = desc & (1 << 15);
d4c430a8 2161 *page_size = 0x10000;
9ee6e8bb
PB		 2162 break;
2163 case 2: case 3: /* 4k page. */
2164 phys_addr = (desc & 0xfffff000) | (address & 0xfff);
2165 xn = desc & 1;
d4c430a8 2166 *page_size = 0x1000;
9ee6e8bb
PB		 2167 break;
2168 default:
2169 /* Never happens, but compiler isn't smart enough to tell. */
2170 abort();
b5ff1b31 2171 }
9ee6e8bb
PB		 2172 code = 15;
2173 }
dd4ebc2e 2174 if (domain_prot == 3) {
c0034328
JR		 2175 *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
2176 } else {
de9b05b8
PM		 2177 if (pxn && !is_user) {
2178 xn = 1;
2179 }
c0034328
JR		 2180 if (xn && access_type == 2)
2181 goto do_fault;
9ee6e8bb 2182
c0034328
JR		 2183 /* The simplified model uses AP[0] as an access control bit. */
2184 if ((env->cp15.c1_sys & (1 << 29)) && (ap & 1) == 0) {
2185 /* Access flag fault. */
2186 code = (code == 15) ? 6 : 3;
2187 goto do_fault;
2188 }
dd4ebc2e 2189 *prot = check_ap(env, ap, domain_prot, access_type, is_user);
c0034328
JR		 2190 if (!*prot) {
2191 /* Access permission fault. */
2192 goto do_fault;
2193 }
2194 if (!xn) {
2195 *prot |= PAGE_EXEC;
2196 }
3ad493fc 2197 }
9ee6e8bb 2198 *phys_ptr = phys_addr;
b5ff1b31
FB		 2199 return 0;
2200do_fault:
2201 return code | (domain << 4);
2202}
2203
3dde962f
PM		 2204/* Fault type for long-descriptor MMU fault reporting; this corresponds
2205 * to bits [5..2] in the STATUS field in long-format DFSR/IFSR.
2206 */
2207typedef enum {
2208 translation_fault = 1,
2209 access_fault = 2,
2210 permission_fault = 3,
2211} MMUFaultType;
2212
2213static int get_phys_addr_lpae(CPUARMState *env, uint32_t address,
2214 int access_type, int is_user,
a8170e5e 2215 hwaddr *phys_ptr, int *prot,
3dde962f
PM		 2216 target_ulong *page_size_ptr)
2217{
2218 /* Read an LPAE long-descriptor translation table. */
2219 MMUFaultType fault_type = translation_fault;
2220 uint32_t level = 1;
2221 uint32_t epd;
2222 uint32_t tsz;
2223 uint64_t ttbr;
2224 int ttbr_select;
2225 int n;
a8170e5e 2226 hwaddr descaddr;
3dde962f
PM		 2227 uint32_t tableattrs;
2228 target_ulong page_size;
2229 uint32_t attrs;
2230
2231 /* Determine whether this address is in the region controlled by
2232 * TTBR0 or TTBR1 (or if it is in neither region and should fault).
2233 * This is a Non-secure PL0/1 stage 1 translation, so controlled by
2234 * TTBCR/TTBR0/TTBR1 in accordance with ARM ARM DDI0406C table B-32:
2235 */
2236 uint32_t t0sz = extract32(env->cp15.c2_control, 0, 3);
2237 uint32_t t1sz = extract32(env->cp15.c2_control, 16, 3);
2238 if (t0sz && !extract32(address, 32 - t0sz, t0sz)) {
2239 /* there is a ttbr0 region and we are in it (high bits all zero) */
2240 ttbr_select = 0;
2241 } else if (t1sz && !extract32(~address, 32 - t1sz, t1sz)) {
2242 /* there is a ttbr1 region and we are in it (high bits all one) */
2243 ttbr_select = 1;
2244 } else if (!t0sz) {
2245 /* ttbr0 region is "everything not in the ttbr1 region" */
2246 ttbr_select = 0;
2247 } else if (!t1sz) {
2248 /* ttbr1 region is "everything not in the ttbr0 region" */
2249 ttbr_select = 1;
2250 } else {
2251 /* in the gap between the two regions, this is a Translation fault */
2252 fault_type = translation_fault;
2253 goto do_fault;
2254 }
2255
2256 /* Note that QEMU ignores shareability and cacheability attributes,
2257 * so we don't need to do anything with the SH, ORGN, IRGN fields
2258 * in the TTBCR. Similarly, TTBCR:A1 selects whether we get the
2259 * ASID from TTBR0 or TTBR1, but QEMU's TLB doesn't currently
2260 * implement any ASID-like capability so we can ignore it (instead
2261 * we will always flush the TLB any time the ASID is changed).
2262 */
2263 if (ttbr_select == 0) {
2264 ttbr = ((uint64_t)env->cp15.c2_base0_hi << 32) | env->cp15.c2_base0;
2265 epd = extract32(env->cp15.c2_control, 7, 1);
2266 tsz = t0sz;
2267 } else {
2268 ttbr = ((uint64_t)env->cp15.c2_base1_hi << 32) | env->cp15.c2_base1;
2269 epd = extract32(env->cp15.c2_control, 23, 1);
2270 tsz = t1sz;
2271 }
2272
2273 if (epd) {
2274 /* Translation table walk disabled => Translation fault on TLB miss */
2275 goto do_fault;
2276 }
2277
2278 /* If the region is small enough we will skip straight to a 2nd level
2279 * lookup. This affects the number of bits of the address used in
2280 * combination with the TTBR to find the first descriptor. ('n' here
2281 * matches the usage in the ARM ARM sB3.6.6, where bits [39..n] are
2282 * from the TTBR, [n-1..3] from the vaddr, and [2..0] always zero).
2283 */
2284 if (tsz > 1) {
2285 level = 2;
2286 n = 14 - tsz;
2287 } else {
2288 n = 5 - tsz;
2289 }
2290
2291 /* Clear the vaddr bits which aren't part of the within-region address,
2292 * so that we don't have to special case things when calculating the
2293 * first descriptor address.
2294 */
2295 address &= (0xffffffffU >> tsz);
2296
2297 /* Now we can extract the actual base address from the TTBR */
2298 descaddr = extract64(ttbr, 0, 40);
2299 descaddr &= ~((1ULL << n) - 1);
2300
2301 tableattrs = 0;
2302 for (;;) {
2303 uint64_t descriptor;
2304
2305 descaddr |= ((address >> (9 * (4 - level))) & 0xff8);
2306 descriptor = ldq_phys(descaddr);
2307 if (!(descriptor & 1) ||
2308 (!(descriptor & 2) && (level == 3))) {
2309 /* Invalid, or the Reserved level 3 encoding */
2310 goto do_fault;
2311 }
2312 descaddr = descriptor & 0xfffffff000ULL;
2313
2314 if ((descriptor & 2) && (level < 3)) {
2315 /* Table entry. The top five bits are attributes which may
2316 * propagate down through lower levels of the table (and
2317 * which are all arranged so that 0 means "no effect", so
2318 * we can gather them up by ORing in the bits at each level).
2319 */
2320 tableattrs |= extract64(descriptor, 59, 5);
2321 level++;
2322 continue;
2323 }
2324 /* Block entry at level 1 or 2, or page entry at level 3.
2325 * These are basically the same thing, although the number
2326 * of bits we pull in from the vaddr varies.
2327 */
2328 page_size = (1 << (39 - (9 * level)));
2329 descaddr |= (address & (page_size - 1));
2330 /* Extract attributes from the descriptor and merge with table attrs */
2331 attrs = extract64(descriptor, 2, 10)
2332 | (extract64(descriptor, 52, 12) << 10);
2333 attrs |= extract32(tableattrs, 0, 2) << 11; /* XN, PXN */
2334 attrs |= extract32(tableattrs, 3, 1) << 5; /* APTable[1] => AP[2] */
2335 /* The sense of AP[1] vs APTable[0] is reversed, as APTable[0] == 1
2336 * means "force PL1 access only", which means forcing AP[1] to 0.
2337 */
2338 if (extract32(tableattrs, 2, 1)) {
2339 attrs &= ~(1 << 4);
2340 }
2341 /* Since we're always in the Non-secure state, NSTable is ignored. */
2342 break;
2343 }
2344 /* Here descaddr is the final physical address, and attributes
2345 * are all in attrs.
2346 */
2347 fault_type = access_fault;
2348 if ((attrs & (1 << 8)) == 0) {
2349 /* Access flag */
2350 goto do_fault;
2351 }
2352 fault_type = permission_fault;
2353 if (is_user && !(attrs & (1 << 4))) {
2354 /* Unprivileged access not enabled */
2355 goto do_fault;
2356 }
2357 *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
2358 if (attrs & (1 << 12) || (!is_user && (attrs & (1 << 11)))) {
2359 /* XN or PXN */
2360 if (access_type == 2) {
2361 goto do_fault;
2362 }
2363 *prot &= ~PAGE_EXEC;
2364 }
2365 if (attrs & (1 << 5)) {
2366 /* Write access forbidden */
2367 if (access_type == 1) {
2368 goto do_fault;
2369 }
2370 *prot &= ~PAGE_WRITE;
2371 }
2372
2373 *phys_ptr = descaddr;
2374 *page_size_ptr = page_size;
2375 return 0;
2376
2377do_fault:
2378 /* Long-descriptor format IFSR/DFSR value */
2379 return (1 << 9) | (fault_type << 2) | level;
2380}
2381
77a71dd1
PM		 2382static int get_phys_addr_mpu(CPUARMState *env, uint32_t address,
2383 int access_type, int is_user,
a8170e5e 2384 hwaddr *phys_ptr, int *prot)
9ee6e8bb
PB		 2385{
2386 int n;
2387 uint32_t mask;
2388 uint32_t base;
2389
2390 *phys_ptr = address;
2391 for (n = 7; n >= 0; n--) {
2392 base = env->cp15.c6_region[n];
2393 if ((base & 1) == 0)
2394 continue;
2395 mask = 1 << ((base >> 1) & 0x1f);
2396 /* Keep this shift separate from the above to avoid an
2397 (undefined) << 32. */
2398 mask = (mask << 1) - 1;
2399 if (((base ^ address) & ~mask) == 0)
2400 break;
2401 }
2402 if (n < 0)
2403 return 2;
2404
2405 if (access_type == 2) {
2406 mask = env->cp15.c5_insn;
2407 } else {
2408 mask = env->cp15.c5_data;
2409 }
2410 mask = (mask >> (n * 4)) & 0xf;
2411 switch (mask) {
2412 case 0:
2413 return 1;
2414 case 1:
2415 if (is_user)
2416 return 1;
2417 *prot = PAGE_READ | PAGE_WRITE;
2418 break;
2419 case 2:
2420 *prot = PAGE_READ;
2421 if (!is_user)
2422 *prot |= PAGE_WRITE;
2423 break;
2424 case 3:
2425 *prot = PAGE_READ | PAGE_WRITE;
2426 break;
2427 case 5:
2428 if (is_user)
2429 return 1;
2430 *prot = PAGE_READ;
2431 break;
2432 case 6:
2433 *prot = PAGE_READ;
2434 break;
2435 default:
2436 /* Bad permission. */
2437 return 1;
2438 }
3ad493fc 2439 *prot |= PAGE_EXEC;
9ee6e8bb
PB		 2440 return 0;
2441}
2442
702a9357
PM		 2443/* get_phys_addr - get the physical address for this virtual address
2444 *
2445 * Find the physical address corresponding to the given virtual address,
2446 * by doing a translation table walk on MMU based systems or using the
2447 * MPU state on MPU based systems.
2448 *
2449 * Returns 0 if the translation was successful. Otherwise, phys_ptr,
2450 * prot and page_size are not filled in, and the return value provides
2451 * information on why the translation aborted, in the format of a
2452 * DFSR/IFSR fault register, with the following caveats:
2453 * * we honour the short vs long DFSR format differences.
2454 * * the WnR bit is never set (the caller must do this).
2455 * * for MPU based systems we don't bother to return a full FSR format
2456 * value.
2457 *
2458 * @env: CPUARMState
2459 * @address: virtual address to get physical address for
2460 * @access_type: 0 for read, 1 for write, 2 for execute
2461 * @is_user: 0 for privileged access, 1 for user
2462 * @phys_ptr: set to the physical address corresponding to the virtual address
2463 * @prot: set to the permissions for the page containing phys_ptr
2464 * @page_size: set to the size of the page containing phys_ptr
2465 */
0ecb72a5 2466static inline int get_phys_addr(CPUARMState *env, uint32_t address,
9ee6e8bb 2467 int access_type, int is_user,
a8170e5e 2468 hwaddr *phys_ptr, int *prot,
d4c430a8 2469 target_ulong *page_size)
9ee6e8bb
PB		 2470{
2471 /* Fast Context Switch Extension. */
2472 if (address < 0x02000000)
2473 address += env->cp15.c13_fcse;
2474
2475 if ((env->cp15.c1_sys & 1) == 0) {
2476 /* MMU/MPU disabled. */
2477 *phys_ptr = address;
3ad493fc 2478 *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
d4c430a8 2479 *page_size = TARGET_PAGE_SIZE;
9ee6e8bb
PB		 2480 return 0;
2481 } else if (arm_feature(env, ARM_FEATURE_MPU)) {
d4c430a8 2482 *page_size = TARGET_PAGE_SIZE;
9ee6e8bb
PB		 2483 return get_phys_addr_mpu(env, address, access_type, is_user, phys_ptr,
2484 prot);
3dde962f
PM		 2485 } else if (extended_addresses_enabled(env)) {
2486 return get_phys_addr_lpae(env, address, access_type, is_user, phys_ptr,
2487 prot, page_size);
9ee6e8bb
PB		 2488 } else if (env->cp15.c1_sys & (1 << 23)) {
2489 return get_phys_addr_v6(env, address, access_type, is_user, phys_ptr,
d4c430a8 2490 prot, page_size);
9ee6e8bb
PB		 2491 } else {
2492 return get_phys_addr_v5(env, address, access_type, is_user, phys_ptr,
d4c430a8 2493 prot, page_size);
9ee6e8bb
PB		 2494 }
2495}
2496
0ecb72a5 2497int cpu_arm_handle_mmu_fault (CPUARMState *env, target_ulong address,
97b348e7 2498 int access_type, int mmu_idx)
b5ff1b31 2499{
a8170e5e 2500 hwaddr phys_addr;
d4c430a8 2501 target_ulong page_size;
b5ff1b31 2502 int prot;
6ebbf390 2503 int ret, is_user;
b5ff1b31 2504
6ebbf390 2505 is_user = mmu_idx == MMU_USER_IDX;
d4c430a8
PB		 2506 ret = get_phys_addr(env, address, access_type, is_user, &phys_addr, &prot,
2507 &page_size);
b5ff1b31
FB		 2508 if (ret == 0) {
2509 /* Map a single [sub]page. */
a8170e5e 2510 phys_addr &= ~(hwaddr)0x3ff;
b5ff1b31 2511 address &= ~(uint32_t)0x3ff;
3ad493fc 2512 tlb_set_page (env, address, phys_addr, prot, mmu_idx, page_size);
d4c430a8 2513 return 0;
b5ff1b31
FB		 2514 }
2515
2516 if (access_type == 2) {
2517 env->cp15.c5_insn = ret;
2518 env->cp15.c6_insn = address;
2519 env->exception_index = EXCP_PREFETCH_ABORT;
2520 } else {
2521 env->cp15.c5_data = ret;
9ee6e8bb
PB		 2522 if (access_type == 1 && arm_feature(env, ARM_FEATURE_V6))
2523 env->cp15.c5_data |= (1 << 11);
b5ff1b31
FB		 2524 env->cp15.c6_data = address;
2525 env->exception_index = EXCP_DATA_ABORT;
2526 }
2527 return 1;
2528}
2529
a8170e5e 2530hwaddr cpu_get_phys_page_debug(CPUARMState *env, target_ulong addr)
b5ff1b31 2531{
a8170e5e 2532 hwaddr phys_addr;
d4c430a8 2533 target_ulong page_size;
b5ff1b31
FB		 2534 int prot;
2535 int ret;
2536
d4c430a8 2537 ret = get_phys_addr(env, addr, 0, 0, &phys_addr, &prot, &page_size);
b5ff1b31
FB		 2538
2539 if (ret != 0)
2540 return -1;
2541
2542 return phys_addr;
2543}
2544
0ecb72a5 2545void HELPER(set_r13_banked)(CPUARMState *env, uint32_t mode, uint32_t val)
9ee6e8bb 2546{
39ea3d4e
PM		 2547 if ((env->uncached_cpsr & CPSR_M) == mode) {
2548 env->regs[13] = val;
2549 } else {
f5206413 2550 env->banked_r13[bank_number(mode)] = val;
39ea3d4e 2551 }
9ee6e8bb
PB		 2552}
2553
0ecb72a5 2554uint32_t HELPER(get_r13_banked)(CPUARMState *env, uint32_t mode)
9ee6e8bb 2555{
39ea3d4e
PM		 2556 if ((env->uncached_cpsr & CPSR_M) == mode) {
2557 return env->regs[13];
2558 } else {
f5206413 2559 return env->banked_r13[bank_number(mode)];
39ea3d4e 2560 }
9ee6e8bb
PB		 2561}
2562
0ecb72a5 2563uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg)
9ee6e8bb
PB		 2564{
2565 switch (reg) {
2566 case 0: /* APSR */
2567 return xpsr_read(env) & 0xf8000000;
2568 case 1: /* IAPSR */
2569 return xpsr_read(env) & 0xf80001ff;
2570 case 2: /* EAPSR */
2571 return xpsr_read(env) & 0xff00fc00;
2572 case 3: /* xPSR */
2573 return xpsr_read(env) & 0xff00fdff;
2574 case 5: /* IPSR */
2575 return xpsr_read(env) & 0x000001ff;
2576 case 6: /* EPSR */
2577 return xpsr_read(env) & 0x0700fc00;
2578 case 7: /* IEPSR */
2579 return xpsr_read(env) & 0x0700edff;
2580 case 8: /* MSP */
2581 return env->v7m.current_sp ? env->v7m.other_sp : env->regs[13];
2582 case 9: /* PSP */
2583 return env->v7m.current_sp ? env->regs[13] : env->v7m.other_sp;
2584 case 16: /* PRIMASK */
2585 return (env->uncached_cpsr & CPSR_I) != 0;
82845826
SH		 2586 case 17: /* BASEPRI */
2587 case 18: /* BASEPRI_MAX */
9ee6e8bb 2588 return env->v7m.basepri;
82845826
SH		 2589 case 19: /* FAULTMASK */
2590 return (env->uncached_cpsr & CPSR_F) != 0;
9ee6e8bb
PB		 2591 case 20: /* CONTROL */
2592 return env->v7m.control;
2593 default:
2594 /* ??? For debugging only. */
2595 cpu_abort(env, "Unimplemented system register read (%d)\n", reg);
2596 return 0;
2597 }
2598}
2599
0ecb72a5 2600void HELPER(v7m_msr)(CPUARMState *env, uint32_t reg, uint32_t val)
9ee6e8bb
PB		 2601{
2602 switch (reg) {
2603 case 0: /* APSR */
2604 xpsr_write(env, val, 0xf8000000);
2605 break;
2606 case 1: /* IAPSR */
2607 xpsr_write(env, val, 0xf8000000);
2608 break;
2609 case 2: /* EAPSR */
2610 xpsr_write(env, val, 0xfe00fc00);
2611 break;
2612 case 3: /* xPSR */
2613 xpsr_write(env, val, 0xfe00fc00);
2614 break;
2615 case 5: /* IPSR */
2616 /* IPSR bits are readonly. */
2617 break;
2618 case 6: /* EPSR */
2619 xpsr_write(env, val, 0x0600fc00);
2620 break;
2621 case 7: /* IEPSR */
2622 xpsr_write(env, val, 0x0600fc00);
2623 break;
2624 case 8: /* MSP */
2625 if (env->v7m.current_sp)
2626 env->v7m.other_sp = val;
2627 else
2628 env->regs[13] = val;
2629 break;
2630 case 9: /* PSP */
2631 if (env->v7m.current_sp)
2632 env->regs[13] = val;
2633 else
2634 env->v7m.other_sp = val;
2635 break;
2636 case 16: /* PRIMASK */
2637 if (val & 1)
2638 env->uncached_cpsr |= CPSR_I;
2639 else
2640 env->uncached_cpsr &= ~CPSR_I;
2641 break;
82845826 2642 case 17: /* BASEPRI */
9ee6e8bb
PB		 2643 env->v7m.basepri = val & 0xff;
2644 break;
82845826 2645 case 18: /* BASEPRI_MAX */
9ee6e8bb
PB		 2646 val &= 0xff;
2647 if (val != 0 && (val < env->v7m.basepri || env->v7m.basepri == 0))
2648 env->v7m.basepri = val;
2649 break;
82845826
SH		 2650 case 19: /* FAULTMASK */
2651 if (val & 1)
2652 env->uncached_cpsr |= CPSR_F;
2653 else
2654 env->uncached_cpsr &= ~CPSR_F;
2655 break;
9ee6e8bb
PB		 2656 case 20: /* CONTROL */
2657 env->v7m.control = val & 3;
2658 switch_v7m_sp(env, (val & 2) != 0);
2659 break;
2660 default:
2661 /* ??? For debugging only. */
2662 cpu_abort(env, "Unimplemented system register write (%d)\n", reg);
2663 return;
2664 }
2665}
2666
b5ff1b31 2667#endif
6ddbc6e4
PB		 2668
2669/* Note that signed overflow is undefined in C. The following routines are
2670 careful to use unsigned types where modulo arithmetic is required.
2671 Failure to do so _will_ break on newer gcc. */
2672
2673/* Signed saturating arithmetic. */
2674
1654b2d6 2675/* Perform 16-bit signed saturating addition. */
6ddbc6e4
PB		 2676static inline uint16_t add16_sat(uint16_t a, uint16_t b)
2677{
2678 uint16_t res;
2679
2680 res = a + b;
2681 if (((res ^ a) & 0x8000) && !((a ^ b) & 0x8000)) {
2682 if (a & 0x8000)
2683 res = 0x8000;
2684 else
2685 res = 0x7fff;
2686 }
2687 return res;
2688}
2689
1654b2d6 2690/* Perform 8-bit signed saturating addition. */
6ddbc6e4
PB		 2691static inline uint8_t add8_sat(uint8_t a, uint8_t b)
2692{
2693 uint8_t res;
2694
2695 res = a + b;
2696 if (((res ^ a) & 0x80) && !((a ^ b) & 0x80)) {
2697 if (a & 0x80)
2698 res = 0x80;
2699 else
2700 res = 0x7f;
2701 }
2702 return res;
2703}
2704
1654b2d6 2705/* Perform 16-bit signed saturating subtraction. */
6ddbc6e4
PB		 2706static inline uint16_t sub16_sat(uint16_t a, uint16_t b)
2707{
2708 uint16_t res;
2709
2710 res = a - b;
2711 if (((res ^ a) & 0x8000) && ((a ^ b) & 0x8000)) {
2712 if (a & 0x8000)
2713 res = 0x8000;
2714 else
2715 res = 0x7fff;
2716 }
2717 return res;
2718}
2719
1654b2d6 2720/* Perform 8-bit signed saturating subtraction. */
6ddbc6e4
PB		 2721static inline uint8_t sub8_sat(uint8_t a, uint8_t b)
2722{
2723 uint8_t res;
2724
2725 res = a - b;
2726 if (((res ^ a) & 0x80) && ((a ^ b) & 0x80)) {
2727 if (a & 0x80)
2728 res = 0x80;
2729 else
2730 res = 0x7f;
2731 }
2732 return res;
2733}
2734
2735#define ADD16(a, b, n) RESULT(add16_sat(a, b), n, 16);
2736#define SUB16(a, b, n) RESULT(sub16_sat(a, b), n, 16);
2737#define ADD8(a, b, n) RESULT(add8_sat(a, b), n, 8);
2738#define SUB8(a, b, n) RESULT(sub8_sat(a, b), n, 8);
2739#define PFX q
2740
2741#include "op_addsub.h"
2742
2743/* Unsigned saturating arithmetic. */
460a09c1 2744static inline uint16_t add16_usat(uint16_t a, uint16_t b)
6ddbc6e4
PB		 2745{
2746 uint16_t res;
2747 res = a + b;
2748 if (res < a)
2749 res = 0xffff;
2750 return res;
2751}
2752
460a09c1 2753static inline uint16_t sub16_usat(uint16_t a, uint16_t b)
6ddbc6e4 2754{
4c4fd3f8 2755 if (a > b)
6ddbc6e4
PB		 2756 return a - b;
2757 else
2758 return 0;
2759}
2760
2761static inline uint8_t add8_usat(uint8_t a, uint8_t b)
2762{
2763 uint8_t res;
2764 res = a + b;
2765 if (res < a)
2766 res = 0xff;
2767 return res;
2768}
2769
2770static inline uint8_t sub8_usat(uint8_t a, uint8_t b)
2771{
4c4fd3f8 2772 if (a > b)
6ddbc6e4
PB		 2773 return a - b;
2774 else
2775 return 0;
2776}
2777
2778#define ADD16(a, b, n) RESULT(add16_usat(a, b), n, 16);
2779#define SUB16(a, b, n) RESULT(sub16_usat(a, b), n, 16);
2780#define ADD8(a, b, n) RESULT(add8_usat(a, b), n, 8);
2781#define SUB8(a, b, n) RESULT(sub8_usat(a, b), n, 8);
2782#define PFX uq
2783
2784#include "op_addsub.h"
2785
2786/* Signed modulo arithmetic. */
2787#define SARITH16(a, b, n, op) do { \
2788 int32_t sum; \
db6e2e65 2789 sum = (int32_t)(int16_t)(a) op (int32_t)(int16_t)(b); \
6ddbc6e4
PB		 2790 RESULT(sum, n, 16); \
2791 if (sum >= 0) \
2792 ge |= 3 << (n * 2); \
2793 } while(0)
2794
2795#define SARITH8(a, b, n, op) do { \
2796 int32_t sum; \
db6e2e65 2797 sum = (int32_t)(int8_t)(a) op (int32_t)(int8_t)(b); \
6ddbc6e4
PB		 2798 RESULT(sum, n, 8); \
2799 if (sum >= 0) \
2800 ge |= 1 << n; \
2801 } while(0)
2802
2803
2804#define ADD16(a, b, n) SARITH16(a, b, n, +)
2805#define SUB16(a, b, n) SARITH16(a, b, n, -)
2806#define ADD8(a, b, n) SARITH8(a, b, n, +)
2807#define SUB8(a, b, n) SARITH8(a, b, n, -)
2808#define PFX s
2809#define ARITH_GE
2810
2811#include "op_addsub.h"
2812
2813/* Unsigned modulo arithmetic. */
2814#define ADD16(a, b, n) do { \
2815 uint32_t sum; \
2816 sum = (uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b); \
2817 RESULT(sum, n, 16); \
a87aa10b 2818 if ((sum >> 16) == 1) \
6ddbc6e4
PB		 2819 ge |= 3 << (n * 2); \
2820 } while(0)
2821
2822#define ADD8(a, b, n) do { \
2823 uint32_t sum; \
2824 sum = (uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b); \
2825 RESULT(sum, n, 8); \
a87aa10b
AZ		 2826 if ((sum >> 8) == 1) \
2827 ge |= 1 << n; \
6ddbc6e4
PB		 2828 } while(0)
2829
2830#define SUB16(a, b, n) do { \
2831 uint32_t sum; \
2832 sum = (uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b); \
2833 RESULT(sum, n, 16); \
2834 if ((sum >> 16) == 0) \
2835 ge |= 3 << (n * 2); \
2836 } while(0)
2837
2838#define SUB8(a, b, n) do { \
2839 uint32_t sum; \
2840 sum = (uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b); \
2841 RESULT(sum, n, 8); \
2842 if ((sum >> 8) == 0) \
a87aa10b 2843 ge |= 1 << n; \
6ddbc6e4
PB		 2844 } while(0)
2845
2846#define PFX u
2847#define ARITH_GE
2848
2849#include "op_addsub.h"
2850
2851/* Halved signed arithmetic. */
2852#define ADD16(a, b, n) \
2853 RESULT(((int32_t)(int16_t)(a) + (int32_t)(int16_t)(b)) >> 1, n, 16)
2854#define SUB16(a, b, n) \
2855 RESULT(((int32_t)(int16_t)(a) - (int32_t)(int16_t)(b)) >> 1, n, 16)
2856#define ADD8(a, b, n) \
2857 RESULT(((int32_t)(int8_t)(a) + (int32_t)(int8_t)(b)) >> 1, n, 8)
2858#define SUB8(a, b, n) \
2859 RESULT(((int32_t)(int8_t)(a) - (int32_t)(int8_t)(b)) >> 1, n, 8)
2860#define PFX sh
2861
2862#include "op_addsub.h"
2863
2864/* Halved unsigned arithmetic. */
2865#define ADD16(a, b, n) \
2866 RESULT(((uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b)) >> 1, n, 16)
2867#define SUB16(a, b, n) \
2868 RESULT(((uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b)) >> 1, n, 16)
2869#define ADD8(a, b, n) \
2870 RESULT(((uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b)) >> 1, n, 8)
2871#define SUB8(a, b, n) \
2872 RESULT(((uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b)) >> 1, n, 8)
2873#define PFX uh
2874
2875#include "op_addsub.h"
2876
2877static inline uint8_t do_usad(uint8_t a, uint8_t b)
2878{
2879 if (a > b)
2880 return a - b;
2881 else
2882 return b - a;
2883}
2884
2885/* Unsigned sum of absolute byte differences. */
2886uint32_t HELPER(usad8)(uint32_t a, uint32_t b)
2887{
2888 uint32_t sum;
2889 sum = do_usad(a, b);
2890 sum += do_usad(a >> 8, b >> 8);
2891 sum += do_usad(a >> 16, b >>16);
2892 sum += do_usad(a >> 24, b >> 24);
2893 return sum;
2894}
2895
2896/* For ARMv6 SEL instruction. */
2897uint32_t HELPER(sel_flags)(uint32_t flags, uint32_t a, uint32_t b)
2898{
2899 uint32_t mask;
2900
2901 mask = 0;
2902 if (flags & 1)
2903 mask |= 0xff;
2904 if (flags & 2)
2905 mask |= 0xff00;
2906 if (flags & 4)
2907 mask |= 0xff0000;
2908 if (flags & 8)
2909 mask |= 0xff000000;
2910 return (a & mask) | (b & ~mask);
2911}
2912
b90372ad
PM		 2913/* VFP support. We follow the convention used for VFP instructions:
2914 Single precision routines have a "s" suffix, double precision a
4373f3ce
PB		 2915 "d" suffix. */
2916
2917/* Convert host exception flags to vfp form. */
2918static inline int vfp_exceptbits_from_host(int host_bits)
2919{
2920 int target_bits = 0;
2921
2922 if (host_bits & float_flag_invalid)
2923 target_bits |= 1;
2924 if (host_bits & float_flag_divbyzero)
2925 target_bits |= 2;
2926 if (host_bits & float_flag_overflow)
2927 target_bits |= 4;
36802b6b 2928 if (host_bits & (float_flag_underflow | float_flag_output_denormal))
4373f3ce
PB		 2929 target_bits |= 8;
2930 if (host_bits & float_flag_inexact)
2931 target_bits |= 0x10;
cecd8504
PM		 2932 if (host_bits & float_flag_input_denormal)
2933 target_bits |= 0x80;
4373f3ce
PB		 2934 return target_bits;
2935}
2936
0ecb72a5 2937uint32_t HELPER(vfp_get_fpscr)(CPUARMState *env)
4373f3ce
PB		 2938{
2939 int i;
2940 uint32_t fpscr;
2941
2942 fpscr = (env->vfp.xregs[ARM_VFP_FPSCR] & 0xffc8ffff)
2943 | (env->vfp.vec_len << 16)
2944 | (env->vfp.vec_stride << 20);
2945 i = get_float_exception_flags(&env->vfp.fp_status);
3a492f3a 2946 i |= get_float_exception_flags(&env->vfp.standard_fp_status);
4373f3ce
PB		 2947 fpscr |= vfp_exceptbits_from_host(i);
2948 return fpscr;
2949}
2950
0ecb72a5 2951uint32_t vfp_get_fpscr(CPUARMState *env)
01653295
PM		 2952{
2953 return HELPER(vfp_get_fpscr)(env);
2954}
2955
4373f3ce
PB		 2956/* Convert vfp exception flags to target form. */
2957static inline int vfp_exceptbits_to_host(int target_bits)
2958{
2959 int host_bits = 0;
2960
2961 if (target_bits & 1)
2962 host_bits |= float_flag_invalid;
2963 if (target_bits & 2)
2964 host_bits |= float_flag_divbyzero;
2965 if (target_bits & 4)
2966 host_bits |= float_flag_overflow;
2967 if (target_bits & 8)
2968 host_bits |= float_flag_underflow;
2969 if (target_bits & 0x10)
2970 host_bits |= float_flag_inexact;
cecd8504
PM		 2971 if (target_bits & 0x80)
2972 host_bits |= float_flag_input_denormal;
4373f3ce
PB		 2973 return host_bits;
2974}
2975
0ecb72a5 2976void HELPER(vfp_set_fpscr)(CPUARMState *env, uint32_t val)
4373f3ce
PB		 2977{
2978 int i;
2979 uint32_t changed;
2980
2981 changed = env->vfp.xregs[ARM_VFP_FPSCR];
2982 env->vfp.xregs[ARM_VFP_FPSCR] = (val & 0xffc8ffff);
2983 env->vfp.vec_len = (val >> 16) & 7;
2984 env->vfp.vec_stride = (val >> 20) & 3;
2985
2986 changed ^= val;
2987 if (changed & (3 << 22)) {
2988 i = (val >> 22) & 3;
2989 switch (i) {
2990 case 0:
2991 i = float_round_nearest_even;
2992 break;
2993 case 1:
2994 i = float_round_up;
2995 break;
2996 case 2:
2997 i = float_round_down;
2998 break;
2999 case 3:
3000 i = float_round_to_zero;
3001 break;
3002 }
3003 set_float_rounding_mode(i, &env->vfp.fp_status);
3004 }
cecd8504 3005 if (changed & (1 << 24)) {
fe76d976 3006 set_flush_to_zero((val & (1 << 24)) != 0, &env->vfp.fp_status);
cecd8504
PM		 3007 set_flush_inputs_to_zero((val & (1 << 24)) != 0, &env->vfp.fp_status);
3008 }
5c7908ed
PB		 3009 if (changed & (1 << 25))
3010 set_default_nan_mode((val & (1 << 25)) != 0, &env->vfp.fp_status);
4373f3ce 3011
b12c390b 3012 i = vfp_exceptbits_to_host(val);
4373f3ce 3013 set_float_exception_flags(i, &env->vfp.fp_status);
3a492f3a 3014 set_float_exception_flags(0, &env->vfp.standard_fp_status);
4373f3ce
PB		 3015}
3016
0ecb72a5 3017void vfp_set_fpscr(CPUARMState *env, uint32_t val)
01653295
PM		 3018{
3019 HELPER(vfp_set_fpscr)(env, val);
3020}
3021
4373f3ce
PB		 3022#define VFP_HELPER(name, p) HELPER(glue(glue(vfp_,name),p))
3023
3024#define VFP_BINOP(name) \
ae1857ec 3025float32 VFP_HELPER(name, s)(float32 a, float32 b, void *fpstp) \
4373f3ce 3026{ \
ae1857ec
PM		 3027 float_status *fpst = fpstp; \
3028 return float32_ ## name(a, b, fpst); \
4373f3ce 3029} \
ae1857ec 3030float64 VFP_HELPER(name, d)(float64 a, float64 b, void *fpstp) \
4373f3ce 3031{ \
ae1857ec
PM		 3032 float_status *fpst = fpstp; \
3033 return float64_ ## name(a, b, fpst); \
4373f3ce
PB		 3034}
3035VFP_BINOP(add)
3036VFP_BINOP(sub)
3037VFP_BINOP(mul)
3038VFP_BINOP(div)
3039#undef VFP_BINOP
3040
3041float32 VFP_HELPER(neg, s)(float32 a)
3042{
3043 return float32_chs(a);
3044}
3045
3046float64 VFP_HELPER(neg, d)(float64 a)
3047{
66230e0d 3048 return float64_chs(a);
4373f3ce
PB		 3049}
3050
3051float32 VFP_HELPER(abs, s)(float32 a)
3052{
3053 return float32_abs(a);
3054}
3055
3056float64 VFP_HELPER(abs, d)(float64 a)
3057{
66230e0d 3058 return float64_abs(a);
4373f3ce
PB		 3059}
3060
0ecb72a5 3061float32 VFP_HELPER(sqrt, s)(float32 a, CPUARMState *env)
4373f3ce
PB		 3062{
3063 return float32_sqrt(a, &env->vfp.fp_status);
3064}
3065
0ecb72a5 3066float64 VFP_HELPER(sqrt, d)(float64 a, CPUARMState *env)
4373f3ce
PB		 3067{
3068 return float64_sqrt(a, &env->vfp.fp_status);
3069}
3070
3071/* XXX: check quiet/signaling case */
3072#define DO_VFP_cmp(p, type) \
0ecb72a5 3073void VFP_HELPER(cmp, p)(type a, type b, CPUARMState *env) \
4373f3ce
PB		 3074{ \
3075 uint32_t flags; \
3076 switch(type ## _compare_quiet(a, b, &env->vfp.fp_status)) { \
3077 case 0: flags = 0x6; break; \
3078 case -1: flags = 0x8; break; \
3079 case 1: flags = 0x2; break; \
3080 default: case 2: flags = 0x3; break; \
3081 } \
3082 env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \
3083 | (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \
3084} \
0ecb72a5 3085void VFP_HELPER(cmpe, p)(type a, type b, CPUARMState *env) \
4373f3ce
PB		 3086{ \
3087 uint32_t flags; \
3088 switch(type ## _compare(a, b, &env->vfp.fp_status)) { \
3089 case 0: flags = 0x6; break; \
3090 case -1: flags = 0x8; break; \
3091 case 1: flags = 0x2; break; \
3092 default: case 2: flags = 0x3; break; \
3093 } \
3094 env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \
3095 | (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \
3096}
3097DO_VFP_cmp(s, float32)
3098DO_VFP_cmp(d, float64)
3099#undef DO_VFP_cmp
3100
5500b06c 3101/* Integer to float and float to integer conversions */
4373f3ce 3102
5500b06c
PM		 3103#define CONV_ITOF(name, fsz, sign) \
3104 float##fsz HELPER(name)(uint32_t x, void *fpstp) \
3105{ \
3106 float_status *fpst = fpstp; \
85836979 3107 return sign##int32_to_##float##fsz((sign##int32_t)x, fpst); \
4373f3ce
PB		 3108}
3109
5500b06c
PM		 3110#define CONV_FTOI(name, fsz, sign, round) \
3111uint32_t HELPER(name)(float##fsz x, void *fpstp) \
3112{ \
3113 float_status *fpst = fpstp; \
3114 if (float##fsz##_is_any_nan(x)) { \
3115 float_raise(float_flag_invalid, fpst); \
3116 return 0; \
3117 } \
3118 return float##fsz##_to_##sign##int32##round(x, fpst); \
4373f3ce
PB		 3119}
3120
5500b06c
PM		 3121#define FLOAT_CONVS(name, p, fsz, sign) \
3122CONV_ITOF(vfp_##name##to##p, fsz, sign) \
3123CONV_FTOI(vfp_to##name##p, fsz, sign, ) \
3124CONV_FTOI(vfp_to##name##z##p, fsz, sign, _round_to_zero)
4373f3ce 3125
5500b06c
PM		 3126FLOAT_CONVS(si, s, 32, )
3127FLOAT_CONVS(si, d, 64, )
3128FLOAT_CONVS(ui, s, 32, u)
3129FLOAT_CONVS(ui, d, 64, u)
4373f3ce 3130
5500b06c
PM		 3131#undef CONV_ITOF
3132#undef CONV_FTOI
3133#undef FLOAT_CONVS
4373f3ce
PB		 3134
3135/* floating point conversion */
0ecb72a5 3136float64 VFP_HELPER(fcvtd, s)(float32 x, CPUARMState *env)
4373f3ce 3137{
2d627737
PM		 3138 float64 r = float32_to_float64(x, &env->vfp.fp_status);
3139 /* ARM requires that S<->D conversion of any kind of NaN generates
3140 * a quiet NaN by forcing the most significant frac bit to 1.
3141 */
3142 return float64_maybe_silence_nan(r);
4373f3ce
PB		 3143}
3144
0ecb72a5 3145float32 VFP_HELPER(fcvts, d)(float64 x, CPUARMState *env)
4373f3ce 3146{
2d627737
PM		 3147 float32 r = float64_to_float32(x, &env->vfp.fp_status);
3148 /* ARM requires that S<->D conversion of any kind of NaN generates
3149 * a quiet NaN by forcing the most significant frac bit to 1.
3150 */
3151 return float32_maybe_silence_nan(r);
4373f3ce
PB		 3152}
3153
3154/* VFP3 fixed point conversion. */
622465e1 3155#define VFP_CONV_FIX(name, p, fsz, itype, sign) \
5500b06c
PM		 3156float##fsz HELPER(vfp_##name##to##p)(uint##fsz##_t x, uint32_t shift, \
3157 void *fpstp) \
4373f3ce 3158{ \
5500b06c 3159 float_status *fpst = fpstp; \
622465e1 3160 float##fsz tmp; \
5500b06c
PM		 3161 tmp = sign##int32_to_##float##fsz((itype##_t)x, fpst); \
3162 return float##fsz##_scalbn(tmp, -(int)shift, fpst); \
4373f3ce 3163} \
5500b06c
PM		 3164uint##fsz##_t HELPER(vfp_to##name##p)(float##fsz x, uint32_t shift, \
3165 void *fpstp) \
4373f3ce 3166{ \
5500b06c 3167 float_status *fpst = fpstp; \
622465e1
PM		 3168 float##fsz tmp; \
3169 if (float##fsz##_is_any_nan(x)) { \
5500b06c 3170 float_raise(float_flag_invalid, fpst); \
622465e1 3171 return 0; \
09d9487f 3172 } \
5500b06c
PM		 3173 tmp = float##fsz##_scalbn(x, shift, fpst); \
3174 return float##fsz##_to_##itype##_round_to_zero(tmp, fpst); \
622465e1
PM		 3175}
3176
3177VFP_CONV_FIX(sh, d, 64, int16, )
3178VFP_CONV_FIX(sl, d, 64, int32, )
3179VFP_CONV_FIX(uh, d, 64, uint16, u)
3180VFP_CONV_FIX(ul, d, 64, uint32, u)
3181VFP_CONV_FIX(sh, s, 32, int16, )
3182VFP_CONV_FIX(sl, s, 32, int32, )
3183VFP_CONV_FIX(uh, s, 32, uint16, u)
3184VFP_CONV_FIX(ul, s, 32, uint32, u)
4373f3ce
PB		 3185#undef VFP_CONV_FIX
3186
60011498 3187/* Half precision conversions. */
0ecb72a5 3188static float32 do_fcvt_f16_to_f32(uint32_t a, CPUARMState *env, float_status *s)
60011498 3189{
60011498 3190 int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0;
fb91678d
PM		 3191 float32 r = float16_to_float32(make_float16(a), ieee, s);
3192 if (ieee) {
3193 return float32_maybe_silence_nan(r);
3194 }
3195 return r;
60011498
PB		 3196}
3197
0ecb72a5 3198static uint32_t do_fcvt_f32_to_f16(float32 a, CPUARMState *env, float_status *s)
60011498 3199{
60011498 3200 int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0;
fb91678d
PM		 3201 float16 r = float32_to_float16(a, ieee, s);
3202 if (ieee) {
3203 r = float16_maybe_silence_nan(r);
3204 }
3205 return float16_val(r);
60011498
PB		 3206}
3207
0ecb72a5 3208float32 HELPER(neon_fcvt_f16_to_f32)(uint32_t a, CPUARMState *env)
2d981da7
PM		 3209{
3210 return do_fcvt_f16_to_f32(a, env, &env->vfp.standard_fp_status);
3211}
3212
0ecb72a5 3213uint32_t HELPER(neon_fcvt_f32_to_f16)(float32 a, CPUARMState *env)
2d981da7
PM		 3214{
3215 return do_fcvt_f32_to_f16(a, env, &env->vfp.standard_fp_status);
3216}
3217
0ecb72a5 3218float32 HELPER(vfp_fcvt_f16_to_f32)(uint32_t a, CPUARMState *env)
2d981da7
PM		 3219{
3220 return do_fcvt_f16_to_f32(a, env, &env->vfp.fp_status);
3221}
3222
0ecb72a5 3223uint32_t HELPER(vfp_fcvt_f32_to_f16)(float32 a, CPUARMState *env)
2d981da7
PM		 3224{
3225 return do_fcvt_f32_to_f16(a, env, &env->vfp.fp_status);
3226}
3227
dda3ec49 3228#define float32_two make_float32(0x40000000)
6aae3df1
PM		 3229#define float32_three make_float32(0x40400000)
3230#define float32_one_point_five make_float32(0x3fc00000)
dda3ec49 3231
0ecb72a5 3232float32 HELPER(recps_f32)(float32 a, float32 b, CPUARMState *env)
4373f3ce 3233{
dda3ec49
PM		 3234 float_status *s = &env->vfp.standard_fp_status;
3235 if ((float32_is_infinity(a) && float32_is_zero_or_denormal(b)) ||
3236 (float32_is_infinity(b) && float32_is_zero_or_denormal(a))) {
43fe9bdb
PM		 3237 if (!(float32_is_zero(a) || float32_is_zero(b))) {
3238 float_raise(float_flag_input_denormal, s);
3239 }
dda3ec49
PM		 3240 return float32_two;
3241 }
3242 return float32_sub(float32_two, float32_mul(a, b, s), s);
4373f3ce
PB		 3243}
3244
0ecb72a5 3245float32 HELPER(rsqrts_f32)(float32 a, float32 b, CPUARMState *env)
4373f3ce 3246{
71826966 3247 float_status *s = &env->vfp.standard_fp_status;
9ea62f57
PM		 3248 float32 product;
3249 if ((float32_is_infinity(a) && float32_is_zero_or_denormal(b)) ||
3250 (float32_is_infinity(b) && float32_is_zero_or_denormal(a))) {
43fe9bdb
PM		 3251 if (!(float32_is_zero(a) || float32_is_zero(b))) {
3252 float_raise(float_flag_input_denormal, s);
3253 }
6aae3df1 3254 return float32_one_point_five;
9ea62f57 3255 }
6aae3df1
PM		 3256 product = float32_mul(a, b, s);
3257 return float32_div(float32_sub(float32_three, product, s), float32_two, s);
4373f3ce
PB		 3258}
3259
8f8e3aa4
PB		 3260/* NEON helpers. */
3261
56bf4fe2
CL		 3262/* Constants 256 and 512 are used in some helpers; we avoid relying on
3263 * int->float conversions at run-time. */
3264#define float64_256 make_float64(0x4070000000000000LL)
3265#define float64_512 make_float64(0x4080000000000000LL)
3266
fe0e4872
CL		 3267/* The algorithm that must be used to calculate the estimate
3268 * is specified by the ARM ARM.
3269 */
0ecb72a5 3270static float64 recip_estimate(float64 a, CPUARMState *env)
fe0e4872 3271{
1146a817
PM		 3272 /* These calculations mustn't set any fp exception flags,
3273 * so we use a local copy of the fp_status.
3274 */
3275 float_status dummy_status = env->vfp.standard_fp_status;
3276 float_status *s = &dummy_status;
fe0e4872
CL		 3277 /* q = (int)(a * 512.0) */
3278 float64 q = float64_mul(float64_512, a, s);
3279 int64_t q_int = float64_to_int64_round_to_zero(q, s);
3280
3281 /* r = 1.0 / (((double)q + 0.5) / 512.0) */
3282 q = int64_to_float64(q_int, s);
3283 q = float64_add(q, float64_half, s);
3284 q = float64_div(q, float64_512, s);
3285 q = float64_div(float64_one, q, s);
3286
3287 /* s = (int)(256.0 * r + 0.5) */
3288 q = float64_mul(q, float64_256, s);
3289 q = float64_add(q, float64_half, s);
3290 q_int = float64_to_int64_round_to_zero(q, s);
3291
3292 /* return (double)s / 256.0 */
3293 return float64_div(int64_to_float64(q_int, s), float64_256, s);
3294}
3295
0ecb72a5 3296float32 HELPER(recpe_f32)(float32 a, CPUARMState *env)
4373f3ce 3297{
fe0e4872
CL		 3298 float_status *s = &env->vfp.standard_fp_status;
3299 float64 f64;
3300 uint32_t val32 = float32_val(a);
3301
3302 int result_exp;
3303 int a_exp = (val32 & 0x7f800000) >> 23;
3304 int sign = val32 & 0x80000000;
3305
3306 if (float32_is_any_nan(a)) {
3307 if (float32_is_signaling_nan(a)) {
3308 float_raise(float_flag_invalid, s);
3309 }
3310 return float32_default_nan;
3311 } else if (float32_is_infinity(a)) {
3312 return float32_set_sign(float32_zero, float32_is_neg(a));
3313 } else if (float32_is_zero_or_denormal(a)) {
43fe9bdb
PM		 3314 if (!float32_is_zero(a)) {
3315 float_raise(float_flag_input_denormal, s);
3316 }
fe0e4872
CL		 3317 float_raise(float_flag_divbyzero, s);
3318 return float32_set_sign(float32_infinity, float32_is_neg(a));
3319 } else if (a_exp >= 253) {
3320 float_raise(float_flag_underflow, s);
3321 return float32_set_sign(float32_zero, float32_is_neg(a));
3322 }
3323
3324 f64 = make_float64((0x3feULL << 52)
3325 | ((int64_t)(val32 & 0x7fffff) << 29));
3326
3327 result_exp = 253 - a_exp;
3328
3329 f64 = recip_estimate(f64, env);
3330
3331 val32 = sign
3332 | ((result_exp & 0xff) << 23)
3333 | ((float64_val(f64) >> 29) & 0x7fffff);
3334 return make_float32(val32);
4373f3ce
PB		 3335}
3336
e07be5d2
CL		 3337/* The algorithm that must be used to calculate the estimate
3338 * is specified by the ARM ARM.
3339 */
0ecb72a5 3340static float64 recip_sqrt_estimate(float64 a, CPUARMState *env)
e07be5d2 3341{
1146a817
PM		 3342 /* These calculations mustn't set any fp exception flags,
3343 * so we use a local copy of the fp_status.
3344 */
3345 float_status dummy_status = env->vfp.standard_fp_status;
3346 float_status *s = &dummy_status;
e07be5d2
CL		 3347 float64 q;
3348 int64_t q_int;
3349
3350 if (float64_lt(a, float64_half, s)) {
3351 /* range 0.25 <= a < 0.5 */
3352
3353 /* a in units of 1/512 rounded down */
3354 /* q0 = (int)(a * 512.0); */
3355 q = float64_mul(float64_512, a, s);
3356 q_int = float64_to_int64_round_to_zero(q, s);
3357
3358 /* reciprocal root r */
3359 /* r = 1.0 / sqrt(((double)q0 + 0.5) / 512.0); */
3360 q = int64_to_float64(q_int, s);
3361 q = float64_add(q, float64_half, s);
3362 q = float64_div(q, float64_512, s);
3363 q = float64_sqrt(q, s);
3364 q = float64_div(float64_one, q, s);
3365 } else {
3366 /* range 0.5 <= a < 1.0 */
3367
3368 /* a in units of 1/256 rounded down */
3369 /* q1 = (int)(a * 256.0); */
3370 q = float64_mul(float64_256, a, s);
3371 int64_t q_int = float64_to_int64_round_to_zero(q, s);
3372
3373 /* reciprocal root r */
3374 /* r = 1.0 /sqrt(((double)q1 + 0.5) / 256); */
3375 q = int64_to_float64(q_int, s);
3376 q = float64_add(q, float64_half, s);
3377 q = float64_div(q, float64_256, s);
3378 q = float64_sqrt(q, s);
3379 q = float64_div(float64_one, q, s);
3380 }
3381 /* r in units of 1/256 rounded to nearest */
3382 /* s = (int)(256.0 * r + 0.5); */
3383
3384 q = float64_mul(q, float64_256,s );
3385 q = float64_add(q, float64_half, s);
3386 q_int = float64_to_int64_round_to_zero(q, s);
3387
3388 /* return (double)s / 256.0;*/
3389 return float64_div(int64_to_float64(q_int, s), float64_256, s);
3390}
3391
0ecb72a5 3392float32 HELPER(rsqrte_f32)(float32 a, CPUARMState *env)
4373f3ce 3393{
e07be5d2
CL		 3394 float_status *s = &env->vfp.standard_fp_status;
3395 int result_exp;
3396 float64 f64;
3397 uint32_t val;
3398 uint64_t val64;
3399
3400 val = float32_val(a);
3401
3402 if (float32_is_any_nan(a)) {
3403 if (float32_is_signaling_nan(a)) {
3404 float_raise(float_flag_invalid, s);
3405 }
3406 return float32_default_nan;
3407 } else if (float32_is_zero_or_denormal(a)) {
43fe9bdb
PM		 3408 if (!float32_is_zero(a)) {
3409 float_raise(float_flag_input_denormal, s);
3410 }
e07be5d2
CL		 3411 float_raise(float_flag_divbyzero, s);
3412 return float32_set_sign(float32_infinity, float32_is_neg(a));
3413 } else if (float32_is_neg(a)) {
3414 float_raise(float_flag_invalid, s);
3415 return float32_default_nan;
3416 } else if (float32_is_infinity(a)) {
3417 return float32_zero;
3418 }
3419
3420 /* Normalize to a double-precision value between 0.25 and 1.0,
3421 * preserving the parity of the exponent. */
3422 if ((val & 0x800000) == 0) {
3423 f64 = make_float64(((uint64_t)(val & 0x80000000) << 32)
3424 | (0x3feULL << 52)
3425 | ((uint64_t)(val & 0x7fffff) << 29));
3426 } else {
3427 f64 = make_float64(((uint64_t)(val & 0x80000000) << 32)
3428 | (0x3fdULL << 52)
3429 | ((uint64_t)(val & 0x7fffff) << 29));
3430 }
3431
3432 result_exp = (380 - ((val & 0x7f800000) >> 23)) / 2;
3433
3434 f64 = recip_sqrt_estimate(f64, env);
3435
3436 val64 = float64_val(f64);
3437
26cc6abf 3438 val = ((result_exp & 0xff) << 23)
e07be5d2
CL		 3439 | ((val64 >> 29) & 0x7fffff);
3440 return make_float32(val);
4373f3ce
PB		 3441}
3442
0ecb72a5 3443uint32_t HELPER(recpe_u32)(uint32_t a, CPUARMState *env)
4373f3ce 3444{
fe0e4872
CL		 3445 float64 f64;
3446
3447 if ((a & 0x80000000) == 0) {
3448 return 0xffffffff;
3449 }
3450
3451 f64 = make_float64((0x3feULL << 52)
3452 | ((int64_t)(a & 0x7fffffff) << 21));
3453
3454 f64 = recip_estimate (f64, env);
3455
3456 return 0x80000000 | ((float64_val(f64) >> 21) & 0x7fffffff);
4373f3ce
PB		 3457}
3458
0ecb72a5 3459uint32_t HELPER(rsqrte_u32)(uint32_t a, CPUARMState *env)
4373f3ce 3460{
e07be5d2
CL		 3461 float64 f64;
3462
3463 if ((a & 0xc0000000) == 0) {
3464 return 0xffffffff;
3465 }
3466
3467 if (a & 0x80000000) {
3468 f64 = make_float64((0x3feULL << 52)
3469 | ((uint64_t)(a & 0x7fffffff) << 21));
3470 } else { /* bits 31-30 == '01' */
3471 f64 = make_float64((0x3fdULL << 52)
3472 | ((uint64_t)(a & 0x3fffffff) << 22));
3473 }
3474
3475 f64 = recip_sqrt_estimate(f64, env);
3476
3477 return 0x80000000 | ((float64_val(f64) >> 21) & 0x7fffffff);
4373f3ce 3478}
fe1479c3 3479
da97f52c
PM		 3480/* VFPv4 fused multiply-accumulate */
3481float32 VFP_HELPER(muladd, s)(float32 a, float32 b, float32 c, void *fpstp)
3482{
3483 float_status *fpst = fpstp;
3484 return float32_muladd(a, b, c, 0, fpst);
3485}
3486
3487float64 VFP_HELPER(muladd, d)(float64 a, float64 b, float64 c, void *fpstp)
3488{
3489 float_status *fpst = fpstp;
3490 return float64_muladd(a, b, c, 0, fpst);
3491}
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