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target-arm: Minimal implementation of performance counters
[mirror_qemu.git] / target-arm / helper.c
CommitLineData
b5ff1b31
FB		 1#include <stdio.h>
2#include <stdlib.h>
3#include <string.h>
4
5#include "cpu.h"
6#include "exec-all.h"
9ee6e8bb 7#include "gdbstub.h"
7b59220e 8#include "helper.h"
ca10f867 9#include "qemu-common.h"
7bbcb0af 10#include "host-utils.h"
4f78c9ad 11#if !defined(CONFIG_USER_ONLY)
983fe826 12#include "hw/loader.h"
4f78c9ad 13#endif
9ee6e8bb 14
10055562
PB		 15static uint32_t cortexa9_cp15_c0_c1[8] =
16{ 0x1031, 0x11, 0x000, 0, 0x00100103, 0x20000000, 0x01230000, 0x00002111 };
17
18static uint32_t cortexa9_cp15_c0_c2[8] =
19{ 0x00101111, 0x13112111, 0x21232041, 0x11112131, 0x00111142, 0, 0, 0 };
20
9ee6e8bb
PB		 21static uint32_t cortexa8_cp15_c0_c1[8] =
22{ 0x1031, 0x11, 0x400, 0, 0x31100003, 0x20000000, 0x01202000, 0x11 };
23
24static uint32_t cortexa8_cp15_c0_c2[8] =
25{ 0x00101111, 0x12112111, 0x21232031, 0x11112131, 0x00111142, 0, 0, 0 };
26
27static uint32_t mpcore_cp15_c0_c1[8] =
28{ 0x111, 0x1, 0, 0x2, 0x01100103, 0x10020302, 0x01222000, 0 };
29
30static uint32_t mpcore_cp15_c0_c2[8] =
31{ 0x00100011, 0x12002111, 0x11221011, 0x01102131, 0x141, 0, 0, 0 };
32
33static uint32_t arm1136_cp15_c0_c1[8] =
34{ 0x111, 0x1, 0x2, 0x3, 0x01130003, 0x10030302, 0x01222110, 0 };
35
36static uint32_t arm1136_cp15_c0_c2[8] =
37{ 0x00140011, 0x12002111, 0x11231111, 0x01102131, 0x141, 0, 0, 0 };
b5ff1b31 38
aaed909a
FB		 39static uint32_t cpu_arm_find_by_name(const char *name);
40
f3d6b95e
PB		 41static inline void set_feature(CPUARMState *env, int feature)
42{
43 env->features |= 1u << feature;
44}
45
46static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
47{
48 env->cp15.c0_cpuid = id;
49 switch (id) {
50 case ARM_CPUID_ARM926:
be5e7a76
DES		 51 set_feature(env, ARM_FEATURE_V4T);
52 set_feature(env, ARM_FEATURE_V5);
f3d6b95e
PB		 53 set_feature(env, ARM_FEATURE_VFP);
54 env->vfp.xregs[ARM_VFP_FPSID] = 0x41011090;
c1713132 55 env->cp15.c0_cachetype = 0x1dd20d2;
610c3c8a 56 env->cp15.c1_sys = 0x00090078;
f3d6b95e 57 break;
ce819861 58 case ARM_CPUID_ARM946:
be5e7a76
DES		 59 set_feature(env, ARM_FEATURE_V4T);
60 set_feature(env, ARM_FEATURE_V5);
ce819861
PB		 61 set_feature(env, ARM_FEATURE_MPU);
62 env->cp15.c0_cachetype = 0x0f004006;
610c3c8a 63 env->cp15.c1_sys = 0x00000078;
ce819861 64 break;
f3d6b95e 65 case ARM_CPUID_ARM1026:
be5e7a76
DES		 66 set_feature(env, ARM_FEATURE_V4T);
67 set_feature(env, ARM_FEATURE_V5);
f3d6b95e
PB		 68 set_feature(env, ARM_FEATURE_VFP);
69 set_feature(env, ARM_FEATURE_AUXCR);
70 env->vfp.xregs[ARM_VFP_FPSID] = 0x410110a0;
c1713132 71 env->cp15.c0_cachetype = 0x1dd20d2;
610c3c8a 72 env->cp15.c1_sys = 0x00090078;
c1713132 73 break;
827df9f3 74 case ARM_CPUID_ARM1136_R2:
9ee6e8bb 75 case ARM_CPUID_ARM1136:
be5e7a76
DES		 76 set_feature(env, ARM_FEATURE_V4T);
77 set_feature(env, ARM_FEATURE_V5);
9ee6e8bb
PB		 78 set_feature(env, ARM_FEATURE_V6);
79 set_feature(env, ARM_FEATURE_VFP);
80 set_feature(env, ARM_FEATURE_AUXCR);
81 env->vfp.xregs[ARM_VFP_FPSID] = 0x410120b4;
82 env->vfp.xregs[ARM_VFP_MVFR0] = 0x11111111;
83 env->vfp.xregs[ARM_VFP_MVFR1] = 0x00000000;
84 memcpy(env->cp15.c0_c1, arm1136_cp15_c0_c1, 8 * sizeof(uint32_t));
22478e79 85 memcpy(env->cp15.c0_c2, arm1136_cp15_c0_c2, 8 * sizeof(uint32_t));
9ee6e8bb 86 env->cp15.c0_cachetype = 0x1dd20d2;
16440c5f 87 env->cp15.c1_sys = 0x00050078;
9ee6e8bb
PB		 88 break;
89 case ARM_CPUID_ARM11MPCORE:
be5e7a76
DES		 90 set_feature(env, ARM_FEATURE_V4T);
91 set_feature(env, ARM_FEATURE_V5);
9ee6e8bb
PB		 92 set_feature(env, ARM_FEATURE_V6);
93 set_feature(env, ARM_FEATURE_V6K);
94 set_feature(env, ARM_FEATURE_VFP);
95 set_feature(env, ARM_FEATURE_AUXCR);
96 env->vfp.xregs[ARM_VFP_FPSID] = 0x410120b4;
97 env->vfp.xregs[ARM_VFP_MVFR0] = 0x11111111;
98 env->vfp.xregs[ARM_VFP_MVFR1] = 0x00000000;
99 memcpy(env->cp15.c0_c1, mpcore_cp15_c0_c1, 8 * sizeof(uint32_t));
22478e79 100 memcpy(env->cp15.c0_c2, mpcore_cp15_c0_c2, 8 * sizeof(uint32_t));
9ee6e8bb
PB		 101 env->cp15.c0_cachetype = 0x1dd20d2;
102 break;
103 case ARM_CPUID_CORTEXA8:
be5e7a76
DES		 104 set_feature(env, ARM_FEATURE_V4T);
105 set_feature(env, ARM_FEATURE_V5);
9ee6e8bb
PB		 106 set_feature(env, ARM_FEATURE_V6);
107 set_feature(env, ARM_FEATURE_V6K);
108 set_feature(env, ARM_FEATURE_V7);
109 set_feature(env, ARM_FEATURE_AUXCR);
110 set_feature(env, ARM_FEATURE_THUMB2);
111 set_feature(env, ARM_FEATURE_VFP);
112 set_feature(env, ARM_FEATURE_VFP3);
113 set_feature(env, ARM_FEATURE_NEON);
fe1479c3 114 set_feature(env, ARM_FEATURE_THUMB2EE);
9ee6e8bb
PB		 115 env->vfp.xregs[ARM_VFP_FPSID] = 0x410330c0;
116 env->vfp.xregs[ARM_VFP_MVFR0] = 0x11110222;
117 env->vfp.xregs[ARM_VFP_MVFR1] = 0x00011100;
118 memcpy(env->cp15.c0_c1, cortexa8_cp15_c0_c1, 8 * sizeof(uint32_t));
22478e79 119 memcpy(env->cp15.c0_c2, cortexa8_cp15_c0_c2, 8 * sizeof(uint32_t));
a49ea279
PB		 120 env->cp15.c0_cachetype = 0x82048004;
121 env->cp15.c0_clid = (1 << 27) | (2 << 24) | 3;
122 env->cp15.c0_ccsid[0] = 0xe007e01a; /* 16k L1 dcache. */
123 env->cp15.c0_ccsid[1] = 0x2007e01a; /* 16k L1 icache. */
124 env->cp15.c0_ccsid[2] = 0xf0000000; /* No L2 icache. */
9c486ad6 125 env->cp15.c1_sys = 0x00c50078;
9ee6e8bb 126 break;
10055562 127 case ARM_CPUID_CORTEXA9:
be5e7a76
DES		 128 set_feature(env, ARM_FEATURE_V4T);
129 set_feature(env, ARM_FEATURE_V5);
10055562
PB		 130 set_feature(env, ARM_FEATURE_V6);
131 set_feature(env, ARM_FEATURE_V6K);
132 set_feature(env, ARM_FEATURE_V7);
133 set_feature(env, ARM_FEATURE_AUXCR);
134 set_feature(env, ARM_FEATURE_THUMB2);
135 set_feature(env, ARM_FEATURE_VFP);
136 set_feature(env, ARM_FEATURE_VFP3);
137 set_feature(env, ARM_FEATURE_VFP_FP16);
138 set_feature(env, ARM_FEATURE_NEON);
139 set_feature(env, ARM_FEATURE_THUMB2EE);
e1bbf446
PM		 140 /* Note that A9 supports the MP extensions even for
141 * A9UP and single-core A9MP (which are both different
142 * and valid configurations; we don't model A9UP).
143 */
144 set_feature(env, ARM_FEATURE_V7MP);
10055562
PB		 145 env->vfp.xregs[ARM_VFP_FPSID] = 0x41034000; /* Guess */
146 env->vfp.xregs[ARM_VFP_MVFR0] = 0x11110222;
147 env->vfp.xregs[ARM_VFP_MVFR1] = 0x01111111;
148 memcpy(env->cp15.c0_c1, cortexa9_cp15_c0_c1, 8 * sizeof(uint32_t));
149 memcpy(env->cp15.c0_c2, cortexa9_cp15_c0_c2, 8 * sizeof(uint32_t));
150 env->cp15.c0_cachetype = 0x80038003;
151 env->cp15.c0_clid = (1 << 27) | (1 << 24) | 3;
152 env->cp15.c0_ccsid[0] = 0xe00fe015; /* 16k L1 dcache. */
153 env->cp15.c0_ccsid[1] = 0x200fe015; /* 16k L1 icache. */
16440c5f 154 env->cp15.c1_sys = 0x00c50078;
10055562 155 break;
9ee6e8bb 156 case ARM_CPUID_CORTEXM3:
be5e7a76
DES		 157 set_feature(env, ARM_FEATURE_V4T);
158 set_feature(env, ARM_FEATURE_V5);
9ee6e8bb
PB		 159 set_feature(env, ARM_FEATURE_V6);
160 set_feature(env, ARM_FEATURE_THUMB2);
161 set_feature(env, ARM_FEATURE_V7);
162 set_feature(env, ARM_FEATURE_M);
163 set_feature(env, ARM_FEATURE_DIV);
164 break;
165 case ARM_CPUID_ANY: /* For userspace emulation. */
be5e7a76
DES		 166 set_feature(env, ARM_FEATURE_V4T);
167 set_feature(env, ARM_FEATURE_V5);
9ee6e8bb
PB		 168 set_feature(env, ARM_FEATURE_V6);
169 set_feature(env, ARM_FEATURE_V6K);
170 set_feature(env, ARM_FEATURE_V7);
171 set_feature(env, ARM_FEATURE_THUMB2);
172 set_feature(env, ARM_FEATURE_VFP);
173 set_feature(env, ARM_FEATURE_VFP3);
60011498 174 set_feature(env, ARM_FEATURE_VFP_FP16);
9ee6e8bb 175 set_feature(env, ARM_FEATURE_NEON);
fe1479c3 176 set_feature(env, ARM_FEATURE_THUMB2EE);
9ee6e8bb 177 set_feature(env, ARM_FEATURE_DIV);
e1bbf446 178 set_feature(env, ARM_FEATURE_V7MP);
9ee6e8bb 179 break;
c3d2689d
AZ		 180 case ARM_CPUID_TI915T:
181 case ARM_CPUID_TI925T:
be5e7a76 182 set_feature(env, ARM_FEATURE_V4T);
c3d2689d
AZ		 183 set_feature(env, ARM_FEATURE_OMAPCP);
184 env->cp15.c0_cpuid = ARM_CPUID_TI925T; /* Depends on wiring. */
185 env->cp15.c0_cachetype = 0x5109149;
186 env->cp15.c1_sys = 0x00000070;
187 env->cp15.c15_i_max = 0x000;
188 env->cp15.c15_i_min = 0xff0;
189 break;
c1713132
AZ		 190 case ARM_CPUID_PXA250:
191 case ARM_CPUID_PXA255:
192 case ARM_CPUID_PXA260:
193 case ARM_CPUID_PXA261:
194 case ARM_CPUID_PXA262:
be5e7a76
DES		 195 set_feature(env, ARM_FEATURE_V4T);
196 set_feature(env, ARM_FEATURE_V5);
c1713132
AZ		 197 set_feature(env, ARM_FEATURE_XSCALE);
198 /* JTAG_ID is ((id << 28) | 0x09265013) */
199 env->cp15.c0_cachetype = 0xd172172;
610c3c8a 200 env->cp15.c1_sys = 0x00000078;
c1713132
AZ		 201 break;
202 case ARM_CPUID_PXA270_A0:
203 case ARM_CPUID_PXA270_A1:
204 case ARM_CPUID_PXA270_B0:
205 case ARM_CPUID_PXA270_B1:
206 case ARM_CPUID_PXA270_C0:
207 case ARM_CPUID_PXA270_C5:
be5e7a76
DES		 208 set_feature(env, ARM_FEATURE_V4T);
209 set_feature(env, ARM_FEATURE_V5);
c1713132
AZ		 210 set_feature(env, ARM_FEATURE_XSCALE);
211 /* JTAG_ID is ((id << 28) | 0x09265013) */
18c9b560
AZ		 212 set_feature(env, ARM_FEATURE_IWMMXT);
213 env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q';
c1713132 214 env->cp15.c0_cachetype = 0xd172172;
610c3c8a 215 env->cp15.c1_sys = 0x00000078;
f3d6b95e 216 break;
5bc95aa2
DES		 217 case ARM_CPUID_SA1100:
218 case ARM_CPUID_SA1110:
219 set_feature(env, ARM_FEATURE_STRONGARM);
220 env->cp15.c1_sys = 0x00000070;
221 break;
f3d6b95e
PB		 222 default:
223 cpu_abort(env, "Bad CPU ID: %x\n", id);
224 break;
225 }
226}
227
40f137e1
PB		 228void cpu_reset(CPUARMState *env)
229{
f3d6b95e 230 uint32_t id;
eca1bdf4
AL		 231
232 if (qemu_loglevel_mask(CPU_LOG_RESET)) {
233 qemu_log("CPU Reset (CPU %d)\n", env->cpu_index);
234 log_cpu_state(env, 0);
235 }
236
f3d6b95e
PB		 237 id = env->cp15.c0_cpuid;
238 memset(env, 0, offsetof(CPUARMState, breakpoints));
239 if (id)
240 cpu_reset_model_id(env, id);
40f137e1
PB		 241#if defined (CONFIG_USER_ONLY)
242 env->uncached_cpsr = ARM_CPU_MODE_USR;
3a807dec 243 /* For user mode we must enable access to coprocessors */
40f137e1 244 env->vfp.xregs[ARM_VFP_FPEXC] = 1 << 30;
3a807dec
PM		 245 if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
246 env->cp15.c15_cpar = 3;
247 } else if (arm_feature(env, ARM_FEATURE_XSCALE)) {
248 env->cp15.c15_cpar = 1;
249 }
40f137e1
PB		 250#else
251 /* SVC mode with interrupts disabled. */
252 env->uncached_cpsr = ARM_CPU_MODE_SVC | CPSR_A | CPSR_F | CPSR_I;
9ee6e8bb 253 /* On ARMv7-M the CPSR_I is the value of the PRIMASK register, and is
983fe826
PB		 254 clear at reset. Initial SP and PC are loaded from ROM. */
255 if (IS_M(env)) {
256 uint32_t pc;
257 uint8_t *rom;
9ee6e8bb 258 env->uncached_cpsr &= ~CPSR_I;
983fe826
PB		 259 rom = rom_ptr(0);
260 if (rom) {
261 /* We should really use ldl_phys here, in case the guest
262 modified flash and reset itself. However images
263 loaded via -kenrel have not been copied yet, so load the
264 values directly from there. */
265 env->regs[13] = ldl_p(rom);
266 pc = ldl_p(rom + 4);
267 env->thumb = pc & 1;
268 env->regs[15] = pc & ~1;
269 }
270 }
40f137e1 271 env->vfp.xregs[ARM_VFP_FPEXC] = 0;
b2fa1797 272 env->cp15.c2_base_mask = 0xffffc000u;
74594c9d
PM		 273 /* v7 performance monitor control register: same implementor
274 * field as main ID register, and we implement no event counters.
275 */
276 env->cp15.c9_pmcr = (id & 0xff000000);
40f137e1 277#endif
3a492f3a
PM		 278 set_flush_to_zero(1, &env->vfp.standard_fp_status);
279 set_flush_inputs_to_zero(1, &env->vfp.standard_fp_status);
280 set_default_nan_mode(1, &env->vfp.standard_fp_status);
9df38c47
PM		 281 set_float_detect_tininess(float_tininess_before_rounding,
282 &env->vfp.fp_status);
283 set_float_detect_tininess(float_tininess_before_rounding,
284 &env->vfp.standard_fp_status);
f3d6b95e 285 tlb_flush(env, 1);
40f137e1
PB		 286}
287
56aebc89
PB		 288static int vfp_gdb_get_reg(CPUState *env, uint8_t *buf, int reg)
289{
290 int nregs;
291
292 /* VFP data registers are always little-endian. */
293 nregs = arm_feature(env, ARM_FEATURE_VFP3) ? 32 : 16;
294 if (reg < nregs) {
295 stfq_le_p(buf, env->vfp.regs[reg]);
296 return 8;
297 }
298 if (arm_feature(env, ARM_FEATURE_NEON)) {
299 /* Aliases for Q regs. */
300 nregs += 16;
301 if (reg < nregs) {
302 stfq_le_p(buf, env->vfp.regs[(reg - 32) * 2]);
303 stfq_le_p(buf + 8, env->vfp.regs[(reg - 32) * 2 + 1]);
304 return 16;
305 }
306 }
307 switch (reg - nregs) {
308 case 0: stl_p(buf, env->vfp.xregs[ARM_VFP_FPSID]); return 4;
309 case 1: stl_p(buf, env->vfp.xregs[ARM_VFP_FPSCR]); return 4;
310 case 2: stl_p(buf, env->vfp.xregs[ARM_VFP_FPEXC]); return 4;
311 }
312 return 0;
313}
314
315static int vfp_gdb_set_reg(CPUState *env, uint8_t *buf, int reg)
316{
317 int nregs;
318
319 nregs = arm_feature(env, ARM_FEATURE_VFP3) ? 32 : 16;
320 if (reg < nregs) {
321 env->vfp.regs[reg] = ldfq_le_p(buf);
322 return 8;
323 }
324 if (arm_feature(env, ARM_FEATURE_NEON)) {
325 nregs += 16;
326 if (reg < nregs) {
327 env->vfp.regs[(reg - 32) * 2] = ldfq_le_p(buf);
328 env->vfp.regs[(reg - 32) * 2 + 1] = ldfq_le_p(buf + 8);
329 return 16;
330 }
331 }
332 switch (reg - nregs) {
333 case 0: env->vfp.xregs[ARM_VFP_FPSID] = ldl_p(buf); return 4;
334 case 1: env->vfp.xregs[ARM_VFP_FPSCR] = ldl_p(buf); return 4;
71b3c3de 335 case 2: env->vfp.xregs[ARM_VFP_FPEXC] = ldl_p(buf) & (1 << 30); return 4;
56aebc89
PB		 336 }
337 return 0;
338}
339
aaed909a 340CPUARMState *cpu_arm_init(const char *cpu_model)
40f137e1
PB		 341{
342 CPUARMState *env;
aaed909a 343 uint32_t id;
b26eefb6 344 static int inited = 0;
40f137e1 345
aaed909a
FB		 346 id = cpu_arm_find_by_name(cpu_model);
347 if (id == 0)
348 return NULL;
40f137e1 349 env = qemu_mallocz(sizeof(CPUARMState));
40f137e1 350 cpu_exec_init(env);
b26eefb6
PB		 351 if (!inited) {
352 inited = 1;
353 arm_translate_init();
354 }
355
01ba9816 356 env->cpu_model_str = cpu_model;
aaed909a 357 env->cp15.c0_cpuid = id;
40f137e1 358 cpu_reset(env);
56aebc89
PB		 359 if (arm_feature(env, ARM_FEATURE_NEON)) {
360 gdb_register_coprocessor(env, vfp_gdb_get_reg, vfp_gdb_set_reg,
361 51, "arm-neon.xml", 0);
362 } else if (arm_feature(env, ARM_FEATURE_VFP3)) {
363 gdb_register_coprocessor(env, vfp_gdb_get_reg, vfp_gdb_set_reg,
364 35, "arm-vfp3.xml", 0);
365 } else if (arm_feature(env, ARM_FEATURE_VFP)) {
366 gdb_register_coprocessor(env, vfp_gdb_get_reg, vfp_gdb_set_reg,
367 19, "arm-vfp.xml", 0);
368 }
0bf46a40 369 qemu_init_vcpu(env);
40f137e1
PB		 370 return env;
371}
372
3371d272
PB		 373struct arm_cpu_t {
374 uint32_t id;
375 const char *name;
376};
377
378static const struct arm_cpu_t arm_cpu_names[] = {
379 { ARM_CPUID_ARM926, "arm926"},
ce819861 380 { ARM_CPUID_ARM946, "arm946"},
3371d272 381 { ARM_CPUID_ARM1026, "arm1026"},
9ee6e8bb 382 { ARM_CPUID_ARM1136, "arm1136"},
827df9f3 383 { ARM_CPUID_ARM1136_R2, "arm1136-r2"},
9ee6e8bb
PB		 384 { ARM_CPUID_ARM11MPCORE, "arm11mpcore"},
385 { ARM_CPUID_CORTEXM3, "cortex-m3"},
386 { ARM_CPUID_CORTEXA8, "cortex-a8"},
10055562 387 { ARM_CPUID_CORTEXA9, "cortex-a9"},
c3d2689d 388 { ARM_CPUID_TI925T, "ti925t" },
c1713132 389 { ARM_CPUID_PXA250, "pxa250" },
5bc95aa2
DES		 390 { ARM_CPUID_SA1100, "sa1100" },
391 { ARM_CPUID_SA1110, "sa1110" },
c1713132
AZ		 392 { ARM_CPUID_PXA255, "pxa255" },
393 { ARM_CPUID_PXA260, "pxa260" },
394 { ARM_CPUID_PXA261, "pxa261" },
395 { ARM_CPUID_PXA262, "pxa262" },
396 { ARM_CPUID_PXA270, "pxa270" },
397 { ARM_CPUID_PXA270_A0, "pxa270-a0" },
398 { ARM_CPUID_PXA270_A1, "pxa270-a1" },
399 { ARM_CPUID_PXA270_B0, "pxa270-b0" },
400 { ARM_CPUID_PXA270_B1, "pxa270-b1" },
401 { ARM_CPUID_PXA270_C0, "pxa270-c0" },
402 { ARM_CPUID_PXA270_C5, "pxa270-c5" },
9ee6e8bb 403 { ARM_CPUID_ANY, "any"},
3371d272
PB		 404 { 0, NULL}
405};
406
9a78eead 407void arm_cpu_list(FILE *f, fprintf_function cpu_fprintf)
5adb4839
PB		 408{
409 int i;
410
c732abe2 411 (*cpu_fprintf)(f, "Available CPUs:\n");
5adb4839 412 for (i = 0; arm_cpu_names[i].name; i++) {
c732abe2 413 (*cpu_fprintf)(f, " %s\n", arm_cpu_names[i].name);
5adb4839
PB		 414 }
415}
416
aaed909a
FB		 417/* return 0 if not found */
418static uint32_t cpu_arm_find_by_name(const char *name)
40f137e1 419{
3371d272
PB		 420 int i;
421 uint32_t id;
422
423 id = 0;
3371d272
PB		 424 for (i = 0; arm_cpu_names[i].name; i++) {
425 if (strcmp(name, arm_cpu_names[i].name) == 0) {
426 id = arm_cpu_names[i].id;
427 break;
428 }
429 }
aaed909a 430 return id;
40f137e1
PB		 431}
432
433void cpu_arm_close(CPUARMState *env)
434{
435 free(env);
436}
437
2f4a40e5
AZ		 438uint32_t cpsr_read(CPUARMState *env)
439{
440 int ZF;
6fbe23d5
PB		 441 ZF = (env->ZF == 0);
442 return env->uncached_cpsr | (env->NF & 0x80000000) | (ZF << 30) |
2f4a40e5
AZ		 443 (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27)
444 | (env->thumb << 5) | ((env->condexec_bits & 3) << 25)
445 | ((env->condexec_bits & 0xfc) << 8)
446 | (env->GE << 16);
447}
448
449void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask)
450{
2f4a40e5 451 if (mask & CPSR_NZCV) {
6fbe23d5
PB		 452 env->ZF = (~val) & CPSR_Z;
453 env->NF = val;
2f4a40e5
AZ		 454 env->CF = (val >> 29) & 1;
455 env->VF = (val << 3) & 0x80000000;
456 }
457 if (mask & CPSR_Q)
458 env->QF = ((val & CPSR_Q) != 0);
459 if (mask & CPSR_T)
460 env->thumb = ((val & CPSR_T) != 0);
461 if (mask & CPSR_IT_0_1) {
462 env->condexec_bits &= ~3;
463 env->condexec_bits |= (val >> 25) & 3;
464 }
465 if (mask & CPSR_IT_2_7) {
466 env->condexec_bits &= 3;
467 env->condexec_bits |= (val >> 8) & 0xfc;
468 }
469 if (mask & CPSR_GE) {
470 env->GE = (val >> 16) & 0xf;
471 }
472
473 if ((env->uncached_cpsr ^ val) & mask & CPSR_M) {
474 switch_mode(env, val & CPSR_M);
475 }
476 mask &= ~CACHED_CPSR_BITS;
477 env->uncached_cpsr = (env->uncached_cpsr & ~mask) | (val & mask);
478}
479
b26eefb6
PB		 480/* Sign/zero extend */
481uint32_t HELPER(sxtb16)(uint32_t x)
482{
483 uint32_t res;
484 res = (uint16_t)(int8_t)x;
485 res |= (uint32_t)(int8_t)(x >> 16) << 16;
486 return res;
487}
488
489uint32_t HELPER(uxtb16)(uint32_t x)
490{
491 uint32_t res;
492 res = (uint16_t)(uint8_t)x;
493 res |= (uint32_t)(uint8_t)(x >> 16) << 16;
494 return res;
495}
496
f51bbbfe
PB		 497uint32_t HELPER(clz)(uint32_t x)
498{
7bbcb0af 499 return clz32(x);
f51bbbfe
PB		 500}
501
3670669c
PB		 502int32_t HELPER(sdiv)(int32_t num, int32_t den)
503{
504 if (den == 0)
505 return 0;
686eeb93
AJ		 506 if (num == INT_MIN && den == -1)
507 return INT_MIN;
3670669c
PB		 508 return num / den;
509}
510
511uint32_t HELPER(udiv)(uint32_t num, uint32_t den)
512{
513 if (den == 0)
514 return 0;
515 return num / den;
516}
517
518uint32_t HELPER(rbit)(uint32_t x)
519{
520 x = ((x & 0xff000000) >> 24)
521 | ((x & 0x00ff0000) >> 8)
522 | ((x & 0x0000ff00) << 8)
523 | ((x & 0x000000ff) << 24);
524 x = ((x & 0xf0f0f0f0) >> 4)
525 | ((x & 0x0f0f0f0f) << 4);
526 x = ((x & 0x88888888) >> 3)
527 | ((x & 0x44444444) >> 1)
528 | ((x & 0x22222222) << 1)
529 | ((x & 0x11111111) << 3);
530 return x;
531}
532
ad69471c
PB		 533uint32_t HELPER(abs)(uint32_t x)
534{
535 return ((int32_t)x < 0) ? -x : x;
536}
537
5fafdf24 538#if defined(CONFIG_USER_ONLY)
b5ff1b31
FB		 539
540void do_interrupt (CPUState *env)
541{
542 env->exception_index = -1;
543}
544
545int cpu_arm_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
6ebbf390 546 int mmu_idx, int is_softmmu)
b5ff1b31
FB		 547{
548 if (rw == 2) {
549 env->exception_index = EXCP_PREFETCH_ABORT;
550 env->cp15.c6_insn = address;
551 } else {
552 env->exception_index = EXCP_DATA_ABORT;
553 env->cp15.c6_data = address;
554 }
555 return 1;
556}
557
b5ff1b31 558/* These should probably raise undefined insn exceptions. */
8984bd2e 559void HELPER(set_cp)(CPUState *env, uint32_t insn, uint32_t val)
c1713132
AZ		 560{
561 int op1 = (insn >> 8) & 0xf;
562 cpu_abort(env, "cp%i insn %08x\n", op1, insn);
563 return;
564}
565
8984bd2e 566uint32_t HELPER(get_cp)(CPUState *env, uint32_t insn)
c1713132
AZ		 567{
568 int op1 = (insn >> 8) & 0xf;
569 cpu_abort(env, "cp%i insn %08x\n", op1, insn);
570 return 0;
571}
572
8984bd2e 573void HELPER(set_cp15)(CPUState *env, uint32_t insn, uint32_t val)
b5ff1b31
FB		 574{
575 cpu_abort(env, "cp15 insn %08x\n", insn);
576}
577
8984bd2e 578uint32_t HELPER(get_cp15)(CPUState *env, uint32_t insn)
b5ff1b31
FB		 579{
580 cpu_abort(env, "cp15 insn %08x\n", insn);
b5ff1b31
FB		 581}
582
9ee6e8bb 583/* These should probably raise undefined insn exceptions. */
8984bd2e 584void HELPER(v7m_msr)(CPUState *env, uint32_t reg, uint32_t val)
9ee6e8bb
PB		 585{
586 cpu_abort(env, "v7m_mrs %d\n", reg);
587}
588
8984bd2e 589uint32_t HELPER(v7m_mrs)(CPUState *env, uint32_t reg)
9ee6e8bb
PB		 590{
591 cpu_abort(env, "v7m_mrs %d\n", reg);
592 return 0;
593}
594
b5ff1b31
FB		 595void switch_mode(CPUState *env, int mode)
596{
597 if (mode != ARM_CPU_MODE_USR)
598 cpu_abort(env, "Tried to switch out of user mode\n");
599}
600
b0109805 601void HELPER(set_r13_banked)(CPUState *env, uint32_t mode, uint32_t val)
9ee6e8bb
PB		 602{
603 cpu_abort(env, "banked r13 write\n");
604}
605
b0109805 606uint32_t HELPER(get_r13_banked)(CPUState *env, uint32_t mode)
9ee6e8bb
PB		 607{
608 cpu_abort(env, "banked r13 read\n");
609 return 0;
610}
611
b5ff1b31
FB		 612#else
613
8e71621f
PB		 614extern int semihosting_enabled;
615
b5ff1b31
FB		 616/* Map CPU modes onto saved register banks. */
617static inline int bank_number (int mode)
618{
619 switch (mode) {
620 case ARM_CPU_MODE_USR:
621 case ARM_CPU_MODE_SYS:
622 return 0;
623 case ARM_CPU_MODE_SVC:
624 return 1;
625 case ARM_CPU_MODE_ABT:
626 return 2;
627 case ARM_CPU_MODE_UND:
628 return 3;
629 case ARM_CPU_MODE_IRQ:
630 return 4;
631 case ARM_CPU_MODE_FIQ:
632 return 5;
633 }
634 cpu_abort(cpu_single_env, "Bad mode %x\n", mode);
635 return -1;
636}
637
638void switch_mode(CPUState *env, int mode)
639{
640 int old_mode;
641 int i;
642
643 old_mode = env->uncached_cpsr & CPSR_M;
644 if (mode == old_mode)
645 return;
646
647 if (old_mode == ARM_CPU_MODE_FIQ) {
648 memcpy (env->fiq_regs, env->regs + 8, 5 * sizeof(uint32_t));
8637c67f 649 memcpy (env->regs + 8, env->usr_regs, 5 * sizeof(uint32_t));
b5ff1b31
FB		 650 } else if (mode == ARM_CPU_MODE_FIQ) {
651 memcpy (env->usr_regs, env->regs + 8, 5 * sizeof(uint32_t));
8637c67f 652 memcpy (env->regs + 8, env->fiq_regs, 5 * sizeof(uint32_t));
b5ff1b31
FB		 653 }
654
655 i = bank_number(old_mode);
656 env->banked_r13[i] = env->regs[13];
657 env->banked_r14[i] = env->regs[14];
658 env->banked_spsr[i] = env->spsr;
659
660 i = bank_number(mode);
661 env->regs[13] = env->banked_r13[i];
662 env->regs[14] = env->banked_r14[i];
663 env->spsr = env->banked_spsr[i];
664}
665
9ee6e8bb
PB		 666static void v7m_push(CPUARMState *env, uint32_t val)
667{
668 env->regs[13] -= 4;
669 stl_phys(env->regs[13], val);
670}
671
672static uint32_t v7m_pop(CPUARMState *env)
673{
674 uint32_t val;
675 val = ldl_phys(env->regs[13]);
676 env->regs[13] += 4;
677 return val;
678}
679
680/* Switch to V7M main or process stack pointer. */
681static void switch_v7m_sp(CPUARMState *env, int process)
682{
683 uint32_t tmp;
684 if (env->v7m.current_sp != process) {
685 tmp = env->v7m.other_sp;
686 env->v7m.other_sp = env->regs[13];
687 env->regs[13] = tmp;
688 env->v7m.current_sp = process;
689 }
690}
691
692static void do_v7m_exception_exit(CPUARMState *env)
693{
694 uint32_t type;
695 uint32_t xpsr;
696
697 type = env->regs[15];
698 if (env->v7m.exception != 0)
983fe826 699 armv7m_nvic_complete_irq(env->nvic, env->v7m.exception);
9ee6e8bb
PB		 700
701 /* Switch to the target stack. */
702 switch_v7m_sp(env, (type & 4) != 0);
703 /* Pop registers. */
704 env->regs[0] = v7m_pop(env);
705 env->regs[1] = v7m_pop(env);
706 env->regs[2] = v7m_pop(env);
707 env->regs[3] = v7m_pop(env);
708 env->regs[12] = v7m_pop(env);
709 env->regs[14] = v7m_pop(env);
710 env->regs[15] = v7m_pop(env);
711 xpsr = v7m_pop(env);
712 xpsr_write(env, xpsr, 0xfffffdff);
713 /* Undo stack alignment. */
714 if (xpsr & 0x200)
715 env->regs[13] |= 4;
716 /* ??? The exception return type specifies Thread/Handler mode. However
717 this is also implied by the xPSR value. Not sure what to do
718 if there is a mismatch. */
719 /* ??? Likewise for mismatches between the CONTROL register and the stack
720 pointer. */
721}
722
2b3ea315 723static void do_interrupt_v7m(CPUARMState *env)
9ee6e8bb
PB		 724{
725 uint32_t xpsr = xpsr_read(env);
726 uint32_t lr;
727 uint32_t addr;
728
729 lr = 0xfffffff1;
730 if (env->v7m.current_sp)
731 lr |= 4;
732 if (env->v7m.exception == 0)
733 lr |= 8;
734
735 /* For exceptions we just mark as pending on the NVIC, and let that
736 handle it. */
737 /* TODO: Need to escalate if the current priority is higher than the
738 one we're raising. */
739 switch (env->exception_index) {
740 case EXCP_UDEF:
983fe826 741 armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE);
9ee6e8bb
PB		 742 return;
743 case EXCP_SWI:
744 env->regs[15] += 2;
983fe826 745 armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_SVC);
9ee6e8bb
PB		 746 return;
747 case EXCP_PREFETCH_ABORT:
748 case EXCP_DATA_ABORT:
983fe826 749 armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_MEM);
9ee6e8bb
PB		 750 return;
751 case EXCP_BKPT:
2ad207d4
PB		 752 if (semihosting_enabled) {
753 int nr;
754 nr = lduw_code(env->regs[15]) & 0xff;
755 if (nr == 0xab) {
756 env->regs[15] += 2;
757 env->regs[0] = do_arm_semihosting(env);
758 return;
759 }
760 }
983fe826 761 armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_DEBUG);
9ee6e8bb
PB		 762 return;
763 case EXCP_IRQ:
983fe826 764 env->v7m.exception = armv7m_nvic_acknowledge_irq(env->nvic);
9ee6e8bb
PB		 765 break;
766 case EXCP_EXCEPTION_EXIT:
767 do_v7m_exception_exit(env);
768 return;
769 default:
770 cpu_abort(env, "Unhandled exception 0x%x\n", env->exception_index);
771 return; /* Never happens. Keep compiler happy. */
772 }
773
774 /* Align stack pointer. */
775 /* ??? Should only do this if Configuration Control Register
776 STACKALIGN bit is set. */
777 if (env->regs[13] & 4) {
ab19b0ec 778 env->regs[13] -= 4;
9ee6e8bb
PB		 779 xpsr |= 0x200;
780 }
6c95676b 781 /* Switch to the handler mode. */
9ee6e8bb
PB		 782 v7m_push(env, xpsr);
783 v7m_push(env, env->regs[15]);
784 v7m_push(env, env->regs[14]);
785 v7m_push(env, env->regs[12]);
786 v7m_push(env, env->regs[3]);
787 v7m_push(env, env->regs[2]);
788 v7m_push(env, env->regs[1]);
789 v7m_push(env, env->regs[0]);
790 switch_v7m_sp(env, 0);
791 env->uncached_cpsr &= ~CPSR_IT;
792 env->regs[14] = lr;
793 addr = ldl_phys(env->v7m.vecbase + env->v7m.exception * 4);
794 env->regs[15] = addr & 0xfffffffe;
795 env->thumb = addr & 1;
796}
797
b5ff1b31
FB		 798/* Handle a CPU exception. */
799void do_interrupt(CPUARMState *env)
800{
801 uint32_t addr;
802 uint32_t mask;
803 int new_mode;
804 uint32_t offset;
805
9ee6e8bb
PB		 806 if (IS_M(env)) {
807 do_interrupt_v7m(env);
808 return;
809 }
b5ff1b31
FB		 810 /* TODO: Vectored interrupt controller. */
811 switch (env->exception_index) {
812 case EXCP_UDEF:
813 new_mode = ARM_CPU_MODE_UND;
814 addr = 0x04;
815 mask = CPSR_I;
816 if (env->thumb)
817 offset = 2;
818 else
819 offset = 4;
820 break;
821 case EXCP_SWI:
8e71621f
PB		 822 if (semihosting_enabled) {
823 /* Check for semihosting interrupt. */
824 if (env->thumb) {
825 mask = lduw_code(env->regs[15] - 2) & 0xff;
826 } else {
827 mask = ldl_code(env->regs[15] - 4) & 0xffffff;
828 }
829 /* Only intercept calls from privileged modes, to provide some
830 semblance of security. */
831 if (((mask == 0x123456 && !env->thumb)
832 || (mask == 0xab && env->thumb))
833 && (env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR) {
834 env->regs[0] = do_arm_semihosting(env);
835 return;
836 }
837 }
b5ff1b31
FB		 838 new_mode = ARM_CPU_MODE_SVC;
839 addr = 0x08;
840 mask = CPSR_I;
601d70b9 841 /* The PC already points to the next instruction. */
b5ff1b31
FB		 842 offset = 0;
843 break;
06c949e6 844 case EXCP_BKPT:
9ee6e8bb 845 /* See if this is a semihosting syscall. */
2ad207d4 846 if (env->thumb && semihosting_enabled) {
9ee6e8bb
PB		 847 mask = lduw_code(env->regs[15]) & 0xff;
848 if (mask == 0xab
849 && (env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR) {
850 env->regs[15] += 2;
851 env->regs[0] = do_arm_semihosting(env);
852 return;
853 }
854 }
81c05daf 855 env->cp15.c5_insn = 2;
9ee6e8bb
PB		 856 /* Fall through to prefetch abort. */
857 case EXCP_PREFETCH_ABORT:
b5ff1b31
FB		 858 new_mode = ARM_CPU_MODE_ABT;
859 addr = 0x0c;
860 mask = CPSR_A | CPSR_I;
861 offset = 4;
862 break;
863 case EXCP_DATA_ABORT:
864 new_mode = ARM_CPU_MODE_ABT;
865 addr = 0x10;
866 mask = CPSR_A | CPSR_I;
867 offset = 8;
868 break;
869 case EXCP_IRQ:
870 new_mode = ARM_CPU_MODE_IRQ;
871 addr = 0x18;
872 /* Disable IRQ and imprecise data aborts. */
873 mask = CPSR_A | CPSR_I;
874 offset = 4;
875 break;
876 case EXCP_FIQ:
877 new_mode = ARM_CPU_MODE_FIQ;
878 addr = 0x1c;
879 /* Disable FIQ, IRQ and imprecise data aborts. */
880 mask = CPSR_A | CPSR_I | CPSR_F;
881 offset = 4;
882 break;
883 default:
884 cpu_abort(env, "Unhandled exception 0x%x\n", env->exception_index);
885 return; /* Never happens. Keep compiler happy. */
886 }
887 /* High vectors. */
888 if (env->cp15.c1_sys & (1 << 13)) {
889 addr += 0xffff0000;
890 }
891 switch_mode (env, new_mode);
892 env->spsr = cpsr_read(env);
9ee6e8bb
PB		 893 /* Clear IT bits. */
894 env->condexec_bits = 0;
30a8cac1 895 /* Switch to the new mode, and to the correct instruction set. */
6d7e6326 896 env->uncached_cpsr = (env->uncached_cpsr & ~CPSR_M) | new_mode;
b5ff1b31 897 env->uncached_cpsr |= mask;
be5e7a76
DES		 898 /* this is a lie, as the was no c1_sys on V4T/V5, but who cares
899 * and we should just guard the thumb mode on V4 */
900 if (arm_feature(env, ARM_FEATURE_V4T)) {
901 env->thumb = (env->cp15.c1_sys & (1 << 30)) != 0;
902 }
b5ff1b31
FB		 903 env->regs[14] = env->regs[15] + offset;
904 env->regs[15] = addr;
905 env->interrupt_request |= CPU_INTERRUPT_EXITTB;
906}
907
908/* Check section/page access permissions.
909 Returns the page protection flags, or zero if the access is not
910 permitted. */
911static inline int check_ap(CPUState *env, int ap, int domain, int access_type,
912 int is_user)
913{
9ee6e8bb
PB		 914 int prot_ro;
915
b5ff1b31
FB		 916 if (domain == 3)
917 return PAGE_READ | PAGE_WRITE;
918
9ee6e8bb
PB		 919 if (access_type == 1)
920 prot_ro = 0;
921 else
922 prot_ro = PAGE_READ;
923
b5ff1b31
FB		 924 switch (ap) {
925 case 0:
78600320 926 if (access_type == 1)
b5ff1b31
FB		 927 return 0;
928 switch ((env->cp15.c1_sys >> 8) & 3) {
929 case 1:
930 return is_user ? 0 : PAGE_READ;
931 case 2:
932 return PAGE_READ;
933 default:
934 return 0;
935 }
936 case 1:
937 return is_user ? 0 : PAGE_READ | PAGE_WRITE;
938 case 2:
939 if (is_user)
9ee6e8bb 940 return prot_ro;
b5ff1b31
FB		 941 else
942 return PAGE_READ | PAGE_WRITE;
943 case 3:
944 return PAGE_READ | PAGE_WRITE;
d4934d18 945 case 4: /* Reserved. */
9ee6e8bb
PB		 946 return 0;
947 case 5:
948 return is_user ? 0 : prot_ro;
949 case 6:
950 return prot_ro;
d4934d18
PB		 951 case 7:
952 if (!arm_feature (env, ARM_FEATURE_V7))
953 return 0;
954 return prot_ro;
b5ff1b31
FB		 955 default:
956 abort();
957 }
958}
959
b2fa1797
PB		 960static uint32_t get_level1_table_address(CPUState *env, uint32_t address)
961{
962 uint32_t table;
963
964 if (address & env->cp15.c2_mask)
965 table = env->cp15.c2_base1 & 0xffffc000;
966 else
967 table = env->cp15.c2_base0 & env->cp15.c2_base_mask;
968
969 table |= (address >> 18) & 0x3ffc;
970 return table;
971}
972
9ee6e8bb 973static int get_phys_addr_v5(CPUState *env, uint32_t address, int access_type,
d4c430a8
PB		 974 int is_user, uint32_t *phys_ptr, int *prot,
975 target_ulong *page_size)
b5ff1b31
FB		 976{
977 int code;
978 uint32_t table;
979 uint32_t desc;
980 int type;
981 int ap;
982 int domain;
983 uint32_t phys_addr;
984
9ee6e8bb
PB		 985 /* Pagetable walk. */
986 /* Lookup l1 descriptor. */
b2fa1797 987 table = get_level1_table_address(env, address);
9ee6e8bb
PB		 988 desc = ldl_phys(table);
989 type = (desc & 3);
990 domain = (env->cp15.c3 >> ((desc >> 4) & 0x1e)) & 3;
991 if (type == 0) {
601d70b9 992 /* Section translation fault. */
9ee6e8bb
PB		 993 code = 5;
994 goto do_fault;
995 }
996 if (domain == 0 || domain == 2) {
997 if (type == 2)
998 code = 9; /* Section domain fault. */
999 else
1000 code = 11; /* Page domain fault. */
1001 goto do_fault;
1002 }
1003 if (type == 2) {
1004 /* 1Mb section. */
1005 phys_addr = (desc & 0xfff00000) | (address & 0x000fffff);
1006 ap = (desc >> 10) & 3;
1007 code = 13;
d4c430a8 1008 *page_size = 1024 * 1024;
9ee6e8bb
PB		 1009 } else {
1010 /* Lookup l2 entry. */
1011 if (type == 1) {
1012 /* Coarse pagetable. */
1013 table = (desc & 0xfffffc00) | ((address >> 10) & 0x3fc);
1014 } else {
1015 /* Fine pagetable. */
1016 table = (desc & 0xfffff000) | ((address >> 8) & 0xffc);
1017 }
1018 desc = ldl_phys(table);
1019 switch (desc & 3) {
1020 case 0: /* Page translation fault. */
1021 code = 7;
1022 goto do_fault;
1023 case 1: /* 64k page. */
1024 phys_addr = (desc & 0xffff0000) | (address & 0xffff);
1025 ap = (desc >> (4 + ((address >> 13) & 6))) & 3;
d4c430a8 1026 *page_size = 0x10000;
ce819861 1027 break;
9ee6e8bb
PB		 1028 case 2: /* 4k page. */
1029 phys_addr = (desc & 0xfffff000) | (address & 0xfff);
1030 ap = (desc >> (4 + ((address >> 13) & 6))) & 3;
d4c430a8 1031 *page_size = 0x1000;
ce819861 1032 break;
9ee6e8bb
PB		 1033 case 3: /* 1k page. */
1034 if (type == 1) {
1035 if (arm_feature(env, ARM_FEATURE_XSCALE)) {
1036 phys_addr = (desc & 0xfffff000) | (address & 0xfff);
1037 } else {
1038 /* Page translation fault. */
1039 code = 7;
1040 goto do_fault;
1041 }
1042 } else {
1043 phys_addr = (desc & 0xfffffc00) | (address & 0x3ff);
1044 }
1045 ap = (desc >> 4) & 3;
d4c430a8 1046 *page_size = 0x400;
ce819861
PB		 1047 break;
1048 default:
9ee6e8bb
PB		 1049 /* Never happens, but compiler isn't smart enough to tell. */
1050 abort();
ce819861 1051 }
9ee6e8bb
PB		 1052 code = 15;
1053 }
1054 *prot = check_ap(env, ap, domain, access_type, is_user);
1055 if (!*prot) {
1056 /* Access permission fault. */
1057 goto do_fault;
1058 }
3ad493fc 1059 *prot |= PAGE_EXEC;
9ee6e8bb
PB		 1060 *phys_ptr = phys_addr;
1061 return 0;
1062do_fault:
1063 return code | (domain << 4);
1064}
1065
1066static int get_phys_addr_v6(CPUState *env, uint32_t address, int access_type,
d4c430a8
PB		 1067 int is_user, uint32_t *phys_ptr, int *prot,
1068 target_ulong *page_size)
9ee6e8bb
PB		 1069{
1070 int code;
1071 uint32_t table;
1072 uint32_t desc;
1073 uint32_t xn;
1074 int type;
1075 int ap;
1076 int domain;
1077 uint32_t phys_addr;
1078
1079 /* Pagetable walk. */
1080 /* Lookup l1 descriptor. */
b2fa1797 1081 table = get_level1_table_address(env, address);
9ee6e8bb
PB		 1082 desc = ldl_phys(table);
1083 type = (desc & 3);
1084 if (type == 0) {
601d70b9 1085 /* Section translation fault. */
9ee6e8bb
PB		 1086 code = 5;
1087 domain = 0;
1088 goto do_fault;
1089 } else if (type == 2 && (desc & (1 << 18))) {
1090 /* Supersection. */
1091 domain = 0;
b5ff1b31 1092 } else {
9ee6e8bb
PB		 1093 /* Section or page. */
1094 domain = (desc >> 4) & 0x1e;
1095 }
1096 domain = (env->cp15.c3 >> domain) & 3;
1097 if (domain == 0 || domain == 2) {
1098 if (type == 2)
1099 code = 9; /* Section domain fault. */
1100 else
1101 code = 11; /* Page domain fault. */
1102 goto do_fault;
1103 }
1104 if (type == 2) {
1105 if (desc & (1 << 18)) {
1106 /* Supersection. */
1107 phys_addr = (desc & 0xff000000) | (address & 0x00ffffff);
d4c430a8 1108 *page_size = 0x1000000;
b5ff1b31 1109 } else {
9ee6e8bb
PB		 1110 /* Section. */
1111 phys_addr = (desc & 0xfff00000) | (address & 0x000fffff);
d4c430a8 1112 *page_size = 0x100000;
b5ff1b31 1113 }
9ee6e8bb
PB		 1114 ap = ((desc >> 10) & 3) | ((desc >> 13) & 4);
1115 xn = desc & (1 << 4);
1116 code = 13;
1117 } else {
1118 /* Lookup l2 entry. */
1119 table = (desc & 0xfffffc00) | ((address >> 10) & 0x3fc);
1120 desc = ldl_phys(table);
1121 ap = ((desc >> 4) & 3) | ((desc >> 7) & 4);
1122 switch (desc & 3) {
1123 case 0: /* Page translation fault. */
1124 code = 7;
b5ff1b31 1125 goto do_fault;
9ee6e8bb
PB		 1126 case 1: /* 64k page. */
1127 phys_addr = (desc & 0xffff0000) | (address & 0xffff);
1128 xn = desc & (1 << 15);
d4c430a8 1129 *page_size = 0x10000;
9ee6e8bb
PB		 1130 break;
1131 case 2: case 3: /* 4k page. */
1132 phys_addr = (desc & 0xfffff000) | (address & 0xfff);
1133 xn = desc & 1;
d4c430a8 1134 *page_size = 0x1000;
9ee6e8bb
PB		 1135 break;
1136 default:
1137 /* Never happens, but compiler isn't smart enough to tell. */
1138 abort();
b5ff1b31 1139 }
9ee6e8bb
PB		 1140 code = 15;
1141 }
c0034328
JR		 1142 if (domain == 3) {
1143 *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
1144 } else {
1145 if (xn && access_type == 2)
1146 goto do_fault;
9ee6e8bb 1147
c0034328
JR		 1148 /* The simplified model uses AP[0] as an access control bit. */
1149 if ((env->cp15.c1_sys & (1 << 29)) && (ap & 1) == 0) {
1150 /* Access flag fault. */
1151 code = (code == 15) ? 6 : 3;
1152 goto do_fault;
1153 }
1154 *prot = check_ap(env, ap, domain, access_type, is_user);
1155 if (!*prot) {
1156 /* Access permission fault. */
1157 goto do_fault;
1158 }
1159 if (!xn) {
1160 *prot |= PAGE_EXEC;
1161 }
3ad493fc 1162 }
9ee6e8bb 1163 *phys_ptr = phys_addr;
b5ff1b31
FB		 1164 return 0;
1165do_fault:
1166 return code | (domain << 4);
1167}
1168
9ee6e8bb
PB		 1169static int get_phys_addr_mpu(CPUState *env, uint32_t address, int access_type,
1170 int is_user, uint32_t *phys_ptr, int *prot)
1171{
1172 int n;
1173 uint32_t mask;
1174 uint32_t base;
1175
1176 *phys_ptr = address;
1177 for (n = 7; n >= 0; n--) {
1178 base = env->cp15.c6_region[n];
1179 if ((base & 1) == 0)
1180 continue;
1181 mask = 1 << ((base >> 1) & 0x1f);
1182 /* Keep this shift separate from the above to avoid an
1183 (undefined) << 32. */
1184 mask = (mask << 1) - 1;
1185 if (((base ^ address) & ~mask) == 0)
1186 break;
1187 }
1188 if (n < 0)
1189 return 2;
1190
1191 if (access_type == 2) {
1192 mask = env->cp15.c5_insn;
1193 } else {
1194 mask = env->cp15.c5_data;
1195 }
1196 mask = (mask >> (n * 4)) & 0xf;
1197 switch (mask) {
1198 case 0:
1199 return 1;
1200 case 1:
1201 if (is_user)
1202 return 1;
1203 *prot = PAGE_READ | PAGE_WRITE;
1204 break;
1205 case 2:
1206 *prot = PAGE_READ;
1207 if (!is_user)
1208 *prot |= PAGE_WRITE;
1209 break;
1210 case 3:
1211 *prot = PAGE_READ | PAGE_WRITE;
1212 break;
1213 case 5:
1214 if (is_user)
1215 return 1;
1216 *prot = PAGE_READ;
1217 break;
1218 case 6:
1219 *prot = PAGE_READ;
1220 break;
1221 default:
1222 /* Bad permission. */
1223 return 1;
1224 }
3ad493fc 1225 *prot |= PAGE_EXEC;
9ee6e8bb
PB		 1226 return 0;
1227}
1228
1229static inline int get_phys_addr(CPUState *env, uint32_t address,
1230 int access_type, int is_user,
d4c430a8
PB		 1231 uint32_t *phys_ptr, int *prot,
1232 target_ulong *page_size)
9ee6e8bb
PB		 1233{
1234 /* Fast Context Switch Extension. */
1235 if (address < 0x02000000)
1236 address += env->cp15.c13_fcse;
1237
1238 if ((env->cp15.c1_sys & 1) == 0) {
1239 /* MMU/MPU disabled. */
1240 *phys_ptr = address;
3ad493fc 1241 *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
d4c430a8 1242 *page_size = TARGET_PAGE_SIZE;
9ee6e8bb
PB		 1243 return 0;
1244 } else if (arm_feature(env, ARM_FEATURE_MPU)) {
d4c430a8 1245 *page_size = TARGET_PAGE_SIZE;
9ee6e8bb
PB		 1246 return get_phys_addr_mpu(env, address, access_type, is_user, phys_ptr,
1247 prot);
1248 } else if (env->cp15.c1_sys & (1 << 23)) {
1249 return get_phys_addr_v6(env, address, access_type, is_user, phys_ptr,
d4c430a8 1250 prot, page_size);
9ee6e8bb
PB		 1251 } else {
1252 return get_phys_addr_v5(env, address, access_type, is_user, phys_ptr,
d4c430a8 1253 prot, page_size);
9ee6e8bb
PB		 1254 }
1255}
1256
b5ff1b31 1257int cpu_arm_handle_mmu_fault (CPUState *env, target_ulong address,
6ebbf390 1258 int access_type, int mmu_idx, int is_softmmu)
b5ff1b31
FB		 1259{
1260 uint32_t phys_addr;
d4c430a8 1261 target_ulong page_size;
b5ff1b31 1262 int prot;
6ebbf390 1263 int ret, is_user;
b5ff1b31 1264
6ebbf390 1265 is_user = mmu_idx == MMU_USER_IDX;
d4c430a8
PB		 1266 ret = get_phys_addr(env, address, access_type, is_user, &phys_addr, &prot,
1267 &page_size);
b5ff1b31
FB		 1268 if (ret == 0) {
1269 /* Map a single [sub]page. */
1270 phys_addr &= ~(uint32_t)0x3ff;
1271 address &= ~(uint32_t)0x3ff;
3ad493fc 1272 tlb_set_page (env, address, phys_addr, prot, mmu_idx, page_size);
d4c430a8 1273 return 0;
b5ff1b31
FB		 1274 }
1275
1276 if (access_type == 2) {
1277 env->cp15.c5_insn = ret;
1278 env->cp15.c6_insn = address;
1279 env->exception_index = EXCP_PREFETCH_ABORT;
1280 } else {
1281 env->cp15.c5_data = ret;
9ee6e8bb
PB		 1282 if (access_type == 1 && arm_feature(env, ARM_FEATURE_V6))
1283 env->cp15.c5_data |= (1 << 11);
b5ff1b31
FB		 1284 env->cp15.c6_data = address;
1285 env->exception_index = EXCP_DATA_ABORT;
1286 }
1287 return 1;
1288}
1289
c227f099 1290target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
b5ff1b31
FB		 1291{
1292 uint32_t phys_addr;
d4c430a8 1293 target_ulong page_size;
b5ff1b31
FB		 1294 int prot;
1295 int ret;
1296
d4c430a8 1297 ret = get_phys_addr(env, addr, 0, 0, &phys_addr, &prot, &page_size);
b5ff1b31
FB		 1298
1299 if (ret != 0)
1300 return -1;
1301
1302 return phys_addr;
1303}
1304
8984bd2e 1305void HELPER(set_cp)(CPUState *env, uint32_t insn, uint32_t val)
c1713132
AZ		 1306{
1307 int cp_num = (insn >> 8) & 0xf;
1308 int cp_info = (insn >> 5) & 7;
1309 int src = (insn >> 16) & 0xf;
1310 int operand = insn & 0xf;
1311
1312 if (env->cp[cp_num].cp_write)
1313 env->cp[cp_num].cp_write(env->cp[cp_num].opaque,
1314 cp_info, src, operand, val);
1315}
1316
8984bd2e 1317uint32_t HELPER(get_cp)(CPUState *env, uint32_t insn)
c1713132
AZ		 1318{
1319 int cp_num = (insn >> 8) & 0xf;
1320 int cp_info = (insn >> 5) & 7;
1321 int dest = (insn >> 16) & 0xf;
1322 int operand = insn & 0xf;
1323
1324 if (env->cp[cp_num].cp_read)
1325 return env->cp[cp_num].cp_read(env->cp[cp_num].opaque,
1326 cp_info, dest, operand);
1327 return 0;
1328}
1329
ce819861
PB		 1330/* Return basic MPU access permission bits. */
1331static uint32_t simple_mpu_ap_bits(uint32_t val)
1332{
1333 uint32_t ret;
1334 uint32_t mask;
1335 int i;
1336 ret = 0;
1337 mask = 3;
1338 for (i = 0; i < 16; i += 2) {
1339 ret |= (val >> i) & mask;
1340 mask <<= 2;
1341 }
1342 return ret;
1343}
1344
1345/* Pad basic MPU access permission bits to extended format. */
1346static uint32_t extended_mpu_ap_bits(uint32_t val)
1347{
1348 uint32_t ret;
1349 uint32_t mask;
1350 int i;
1351 ret = 0;
1352 mask = 3;
1353 for (i = 0; i < 16; i += 2) {
1354 ret |= (val & mask) << i;
1355 mask <<= 2;
1356 }
1357 return ret;
1358}
1359
8984bd2e 1360void HELPER(set_cp15)(CPUState *env, uint32_t insn, uint32_t val)
b5ff1b31 1361{
9ee6e8bb
PB		 1362 int op1;
1363 int op2;
1364 int crm;
b5ff1b31 1365
9ee6e8bb 1366 op1 = (insn >> 21) & 7;
b5ff1b31 1367 op2 = (insn >> 5) & 7;
ce819861 1368 crm = insn & 0xf;
b5ff1b31 1369 switch ((insn >> 16) & 0xf) {
9ee6e8bb 1370 case 0:
9ee6e8bb 1371 /* ID codes. */
610c3c8a
AZ		 1372 if (arm_feature(env, ARM_FEATURE_XSCALE))
1373 break;
c3d2689d
AZ		 1374 if (arm_feature(env, ARM_FEATURE_OMAPCP))
1375 break;
a49ea279
PB		 1376 if (arm_feature(env, ARM_FEATURE_V7)
1377 && op1 == 2 && crm == 0 && op2 == 0) {
1378 env->cp15.c0_cssel = val & 0xf;
1379 break;
1380 }
b5ff1b31
FB		 1381 goto bad_reg;
1382 case 1: /* System configuration. */
c3d2689d
AZ		 1383 if (arm_feature(env, ARM_FEATURE_OMAPCP))
1384 op2 = 0;
b5ff1b31
FB		 1385 switch (op2) {
1386 case 0:
ce819861 1387 if (!arm_feature(env, ARM_FEATURE_XSCALE) || crm == 0)
c1713132 1388 env->cp15.c1_sys = val;
b5ff1b31
FB		 1389 /* ??? Lots of these bits are not implemented. */
1390 /* This may enable/disable the MMU, so do a TLB flush. */
1391 tlb_flush(env, 1);
1392 break;
61cc8701 1393 case 1: /* Auxiliary control register. */
610c3c8a
AZ		 1394 if (arm_feature(env, ARM_FEATURE_XSCALE)) {
1395 env->cp15.c1_xscaleauxcr = val;
c1713132 1396 break;
610c3c8a 1397 }
9ee6e8bb
PB		 1398 /* Not implemented. */
1399 break;
b5ff1b31 1400 case 2:
610c3c8a
AZ		 1401 if (arm_feature(env, ARM_FEATURE_XSCALE))
1402 goto bad_reg;
4be27dbb
PB		 1403 if (env->cp15.c1_coproc != val) {
1404 env->cp15.c1_coproc = val;
1405 /* ??? Is this safe when called from within a TB? */
1406 tb_flush(env);
1407 }
c1713132 1408 break;
b5ff1b31
FB		 1409 default:
1410 goto bad_reg;
1411 }
1412 break;
ce819861
PB		 1413 case 2: /* MMU Page table control / MPU cache control. */
1414 if (arm_feature(env, ARM_FEATURE_MPU)) {
1415 switch (op2) {
1416 case 0:
1417 env->cp15.c2_data = val;
1418 break;
1419 case 1:
1420 env->cp15.c2_insn = val;
1421 break;
1422 default:
1423 goto bad_reg;
1424 }
1425 } else {
9ee6e8bb
PB		 1426 switch (op2) {
1427 case 0:
1428 env->cp15.c2_base0 = val;
1429 break;
1430 case 1:
1431 env->cp15.c2_base1 = val;
1432 break;
1433 case 2:
b2fa1797
PB		 1434 val &= 7;
1435 env->cp15.c2_control = val;
9ee6e8bb 1436 env->cp15.c2_mask = ~(((uint32_t)0xffffffffu) >> val);
b2fa1797 1437 env->cp15.c2_base_mask = ~((uint32_t)0x3fffu >> val);
9ee6e8bb
PB		 1438 break;
1439 default:
1440 goto bad_reg;
1441 }
ce819861 1442 }
b5ff1b31 1443 break;
ce819861 1444 case 3: /* MMU Domain access control / MPU write buffer control. */
b5ff1b31 1445 env->cp15.c3 = val;
405ee3ad 1446 tlb_flush(env, 1); /* Flush TLB as domain not tracked in TLB */
b5ff1b31
FB		 1447 break;
1448 case 4: /* Reserved. */
1449 goto bad_reg;
ce819861 1450 case 5: /* MMU Fault status / MPU access permission. */
c3d2689d
AZ		 1451 if (arm_feature(env, ARM_FEATURE_OMAPCP))
1452 op2 = 0;
b5ff1b31
FB		 1453 switch (op2) {
1454 case 0:
ce819861
PB		 1455 if (arm_feature(env, ARM_FEATURE_MPU))
1456 val = extended_mpu_ap_bits(val);
b5ff1b31
FB		 1457 env->cp15.c5_data = val;
1458 break;
1459 case 1:
ce819861
PB		 1460 if (arm_feature(env, ARM_FEATURE_MPU))
1461 val = extended_mpu_ap_bits(val);
b5ff1b31
FB		 1462 env->cp15.c5_insn = val;
1463 break;
ce819861
PB		 1464 case 2:
1465 if (!arm_feature(env, ARM_FEATURE_MPU))
1466 goto bad_reg;
1467 env->cp15.c5_data = val;
b5ff1b31 1468 break;
ce819861
PB		 1469 case 3:
1470 if (!arm_feature(env, ARM_FEATURE_MPU))
1471 goto bad_reg;
1472 env->cp15.c5_insn = val;
b5ff1b31
FB		 1473 break;
1474 default:
1475 goto bad_reg;
1476 }
1477 break;
ce819861
PB		 1478 case 6: /* MMU Fault address / MPU base/size. */
1479 if (arm_feature(env, ARM_FEATURE_MPU)) {
1480 if (crm >= 8)
1481 goto bad_reg;
1482 env->cp15.c6_region[crm] = val;
1483 } else {
c3d2689d
AZ		 1484 if (arm_feature(env, ARM_FEATURE_OMAPCP))
1485 op2 = 0;
ce819861
PB		 1486 switch (op2) {
1487 case 0:
1488 env->cp15.c6_data = val;
1489 break;
9ee6e8bb
PB		 1490 case 1: /* ??? This is WFAR on armv6 */
1491 case 2:
ce819861
PB		 1492 env->cp15.c6_insn = val;
1493 break;
1494 default:
1495 goto bad_reg;
1496 }
1497 }
1498 break;
b5ff1b31 1499 case 7: /* Cache control. */
c3d2689d
AZ		 1500 env->cp15.c15_i_max = 0x000;
1501 env->cp15.c15_i_min = 0xff0;
f8bf8606
AL		 1502 if (op1 != 0) {
1503 goto bad_reg;
1504 }
1505 /* No cache, so nothing to do except VA->PA translations. */
1506 if (arm_feature(env, ARM_FEATURE_V6K)) {
1507 switch (crm) {
1508 case 4:
1509 if (arm_feature(env, ARM_FEATURE_V7)) {
1510 env->cp15.c7_par = val & 0xfffff6ff;
1511 } else {
1512 env->cp15.c7_par = val & 0xfffff1ff;
1513 }
1514 break;
1515 case 8: {
1516 uint32_t phys_addr;
1517 target_ulong page_size;
1518 int prot;
1519 int ret, is_user = op2 & 2;
1520 int access_type = op2 & 1;
1521
1522 if (op2 & 4) {
1523 /* Other states are only available with TrustZone */
1524 goto bad_reg;
1525 }
1526 ret = get_phys_addr(env, val, access_type, is_user,
1527 &phys_addr, &prot, &page_size);
1528 if (ret == 0) {
1529 /* We do not set any attribute bits in the PAR */
1530 if (page_size == (1 << 24)
1531 && arm_feature(env, ARM_FEATURE_V7)) {
1532 env->cp15.c7_par = (phys_addr & 0xff000000) | 1 << 1;
1533 } else {
1534 env->cp15.c7_par = phys_addr & 0xfffff000;
1535 }
1536 } else {
1537 env->cp15.c7_par = ((ret & (10 << 1)) >> 5) |
1538 ((ret & (12 << 1)) >> 6) |
1539 ((ret & 0xf) << 1) | 1;
1540 }
1541 break;
1542 }
1543 }
1544 }
b5ff1b31
FB		 1545 break;
1546 case 8: /* MMU TLB control. */
1547 switch (op2) {
1548 case 0: /* Invalidate all. */
1549 tlb_flush(env, 0);
1550 break;
1551 case 1: /* Invalidate single TLB entry. */
d4c430a8 1552 tlb_flush_page(env, val & TARGET_PAGE_MASK);
b5ff1b31 1553 break;
9ee6e8bb
PB		 1554 case 2: /* Invalidate on ASID. */
1555 tlb_flush(env, val == 0);
1556 break;
1557 case 3: /* Invalidate single entry on MVA. */
1558 /* ??? This is like case 1, but ignores ASID. */
1559 tlb_flush(env, 1);
1560 break;
b5ff1b31
FB		 1561 default:
1562 goto bad_reg;
1563 }
1564 break;
ce819861 1565 case 9:
c3d2689d
AZ		 1566 if (arm_feature(env, ARM_FEATURE_OMAPCP))
1567 break;
5bc95aa2
DES		 1568 if (arm_feature(env, ARM_FEATURE_STRONGARM))
1569 break; /* Ignore ReadBuffer access */
ce819861
PB		 1570 switch (crm) {
1571 case 0: /* Cache lockdown. */
9ee6e8bb
PB		 1572 switch (op1) {
1573 case 0: /* L1 cache. */
1574 switch (op2) {
1575 case 0:
1576 env->cp15.c9_data = val;
1577 break;
1578 case 1:
1579 env->cp15.c9_insn = val;
1580 break;
1581 default:
1582 goto bad_reg;
1583 }
1584 break;
1585 case 1: /* L2 cache. */
1586 /* Ignore writes to L2 lockdown/auxiliary registers. */
1587 break;
1588 default:
1589 goto bad_reg;
1590 }
1591 break;
ce819861
PB		 1592 case 1: /* TCM memory region registers. */
1593 /* Not implemented. */
1594 goto bad_reg;
74594c9d
PM		 1595 case 12: /* Performance monitor control */
1596 /* Performance monitors are implementation defined in v7,
1597 * but with an ARM recommended set of registers, which we
1598 * follow (although we don't actually implement any counters)
1599 */
1600 if (!arm_feature(env, ARM_FEATURE_V7)) {
1601 goto bad_reg;
1602 }
1603 switch (op2) {
1604 case 0: /* performance monitor control register */
1605 /* only the DP, X, D and E bits are writable */
1606 env->cp15.c9_pmcr &= ~0x39;
1607 env->cp15.c9_pmcr |= (val & 0x39);
1608 break;
1609 case 1: /* Count enable set register */
1610 val &= (1 << 31);
1611 env->cp15.c9_pmcnten |= val;
1612 break;
1613 case 2: /* Count enable clear */
1614 val &= (1 << 31);
1615 env->cp15.c9_pmcnten &= ~val;
1616 break;
1617 case 3: /* Overflow flag status */
1618 env->cp15.c9_pmovsr &= ~val;
1619 break;
1620 case 4: /* Software increment */
1621 /* RAZ/WI since we don't implement the software-count event */
1622 break;
1623 case 5: /* Event counter selection register */
1624 /* Since we don't implement any events, writing to this register
1625 * is actually UNPREDICTABLE. So we choose to RAZ/WI.
1626 */
1627 break;
1628 default:
1629 goto bad_reg;
1630 }
1631 break;
1632 case 13: /* Performance counters */
1633 if (!arm_feature(env, ARM_FEATURE_V7)) {
1634 goto bad_reg;
1635 }
1636 switch (op2) {
1637 case 0: /* Cycle count register: not implemented, so RAZ/WI */
1638 break;
1639 case 1: /* Event type select */
1640 env->cp15.c9_pmxevtyper = val & 0xff;
1641 break;
1642 case 2: /* Event count register */
1643 /* Unimplemented (we have no events), RAZ/WI */
1644 break;
1645 default:
1646 goto bad_reg;
1647 }
1648 break;
1649 case 14: /* Performance monitor control */
1650 if (!arm_feature(env, ARM_FEATURE_V7)) {
1651 goto bad_reg;
1652 }
1653 switch (op2) {
1654 case 0: /* user enable */
1655 env->cp15.c9_pmuserenr = val & 1;
1656 /* changes access rights for cp registers, so flush tbs */
1657 tb_flush(env);
1658 break;
1659 case 1: /* interrupt enable set */
1660 /* We have no event counters so only the C bit can be changed */
1661 val &= (1 << 31);
1662 env->cp15.c9_pminten |= val;
1663 break;
1664 case 2: /* interrupt enable clear */
1665 val &= (1 << 31);
1666 env->cp15.c9_pminten &= ~val;
1667 break;
1668 }
1669 break;
b5ff1b31
FB		 1670 default:
1671 goto bad_reg;
1672 }
1673 break;
1674 case 10: /* MMU TLB lockdown. */
1675 /* ??? TLB lockdown not implemented. */
1676 break;
b5ff1b31
FB		 1677 case 12: /* Reserved. */
1678 goto bad_reg;
1679 case 13: /* Process ID. */
1680 switch (op2) {
1681 case 0:
d07edbfa
PB		 1682 /* Unlike real hardware the qemu TLB uses virtual addresses,
1683 not modified virtual addresses, so this causes a TLB flush.
1684 */
1685 if (env->cp15.c13_fcse != val)
1686 tlb_flush(env, 1);
1687 env->cp15.c13_fcse = val;
b5ff1b31
FB		 1688 break;
1689 case 1:
d07edbfa 1690 /* This changes the ASID, so do a TLB flush. */
ce819861
PB		 1691 if (env->cp15.c13_context != val
1692 && !arm_feature(env, ARM_FEATURE_MPU))
d07edbfa
PB		 1693 tlb_flush(env, 0);
1694 env->cp15.c13_context = val;
b5ff1b31
FB		 1695 break;
1696 default:
1697 goto bad_reg;
1698 }
1699 break;
1700 case 14: /* Reserved. */
1701 goto bad_reg;
1702 case 15: /* Implementation specific. */
c1713132 1703 if (arm_feature(env, ARM_FEATURE_XSCALE)) {
ce819861 1704 if (op2 == 0 && crm == 1) {
2e23213f
AZ		 1705 if (env->cp15.c15_cpar != (val & 0x3fff)) {
1706 /* Changes cp0 to cp13 behavior, so needs a TB flush. */
1707 tb_flush(env);
1708 env->cp15.c15_cpar = val & 0x3fff;
1709 }
c1713132
AZ		 1710 break;
1711 }
1712 goto bad_reg;
1713 }
c3d2689d
AZ		 1714 if (arm_feature(env, ARM_FEATURE_OMAPCP)) {
1715 switch (crm) {
1716 case 0:
1717 break;
1718 case 1: /* Set TI925T configuration. */
1719 env->cp15.c15_ticonfig = val & 0xe7;
1720 env->cp15.c0_cpuid = (val & (1 << 5)) ? /* OS_TYPE bit */
1721 ARM_CPUID_TI915T : ARM_CPUID_TI925T;
1722 break;
1723 case 2: /* Set I_max. */
1724 env->cp15.c15_i_max = val;
1725 break;
1726 case 3: /* Set I_min. */
1727 env->cp15.c15_i_min = val;
1728 break;
1729 case 4: /* Set thread-ID. */
1730 env->cp15.c15_threadid = val & 0xffff;
1731 break;
1732 case 8: /* Wait-for-interrupt (deprecated). */
1733 cpu_interrupt(env, CPU_INTERRUPT_HALT);
1734 break;
1735 default:
1736 goto bad_reg;
1737 }
1738 }
b5ff1b31
FB		 1739 break;
1740 }
1741 return;
1742bad_reg:
1743 /* ??? For debugging only. Should raise illegal instruction exception. */
9ee6e8bb
PB		 1744 cpu_abort(env, "Unimplemented cp15 register write (c%d, c%d, {%d, %d})\n",
1745 (insn >> 16) & 0xf, crm, op1, op2);
b5ff1b31
FB		 1746}
1747
8984bd2e 1748uint32_t HELPER(get_cp15)(CPUState *env, uint32_t insn)
b5ff1b31 1749{
9ee6e8bb
PB		 1750 int op1;
1751 int op2;
1752 int crm;
b5ff1b31 1753
9ee6e8bb 1754 op1 = (insn >> 21) & 7;
b5ff1b31 1755 op2 = (insn >> 5) & 7;
c3d2689d 1756 crm = insn & 0xf;
b5ff1b31
FB		 1757 switch ((insn >> 16) & 0xf) {
1758 case 0: /* ID codes. */
9ee6e8bb
PB		 1759 switch (op1) {
1760 case 0:
1761 switch (crm) {
1762 case 0:
1763 switch (op2) {
1764 case 0: /* Device ID. */
1765 return env->cp15.c0_cpuid;
1766 case 1: /* Cache Type. */
1767 return env->cp15.c0_cachetype;
1768 case 2: /* TCM status. */
1769 return 0;
1770 case 3: /* TLB type register. */
1771 return 0; /* No lockable TLB entries. */
607b4b08
PM		 1772 case 5: /* MPIDR */
1773 /* The MPIDR was standardised in v7; prior to
1774 * this it was implemented only in the 11MPCore.
1775 * For all other pre-v7 cores it does not exist.
1776 */
1777 if (arm_feature(env, ARM_FEATURE_V7) ||
1778 ARM_CPUID(env) == ARM_CPUID_ARM11MPCORE) {
1779 int mpidr = env->cpu_index;
1780 /* We don't support setting cluster ID ([8..11])
1781 * so these bits always RAZ.
1782 */
1783 if (arm_feature(env, ARM_FEATURE_V7MP)) {
1784 mpidr |= (1 << 31);
1785 /* Cores which are uniprocessor (non-coherent)
1786 * but still implement the MP extensions set
1787 * bit 30. (For instance, A9UP.) However we do
1788 * not currently model any of those cores.
1789 */
1790 }
1791 return mpidr;
10055562 1792 }
607b4b08 1793 /* otherwise fall through to the unimplemented-reg case */
9ee6e8bb
PB		 1794 default:
1795 goto bad_reg;
1796 }
1797 case 1:
1798 if (!arm_feature(env, ARM_FEATURE_V6))
1799 goto bad_reg;
1800 return env->cp15.c0_c1[op2];
1801 case 2:
1802 if (!arm_feature(env, ARM_FEATURE_V6))
1803 goto bad_reg;
1804 return env->cp15.c0_c2[op2];
1805 case 3: case 4: case 5: case 6: case 7:
1806 return 0;
1807 default:
1808 goto bad_reg;
1809 }
1810 case 1:
1811 /* These registers aren't documented on arm11 cores. However
1812 Linux looks at them anyway. */
1813 if (!arm_feature(env, ARM_FEATURE_V6))
1814 goto bad_reg;
1815 if (crm != 0)
1816 goto bad_reg;
a49ea279
PB		 1817 if (!arm_feature(env, ARM_FEATURE_V7))
1818 return 0;
1819
1820 switch (op2) {
1821 case 0:
1822 return env->cp15.c0_ccsid[env->cp15.c0_cssel];
1823 case 1:
1824 return env->cp15.c0_clid;
1825 case 7:
1826 return 0;
1827 }
1828 goto bad_reg;
1829 case 2:
1830 if (op2 != 0 || crm != 0)
610c3c8a 1831 goto bad_reg;
a49ea279 1832 return env->cp15.c0_cssel;
9ee6e8bb
PB		 1833 default:
1834 goto bad_reg;
b5ff1b31
FB		 1835 }
1836 case 1: /* System configuration. */
c3d2689d
AZ		 1837 if (arm_feature(env, ARM_FEATURE_OMAPCP))
1838 op2 = 0;
b5ff1b31
FB		 1839 switch (op2) {
1840 case 0: /* Control register. */
1841 return env->cp15.c1_sys;
1842 case 1: /* Auxiliary control register. */
c1713132 1843 if (arm_feature(env, ARM_FEATURE_XSCALE))
610c3c8a 1844 return env->cp15.c1_xscaleauxcr;
9ee6e8bb
PB		 1845 if (!arm_feature(env, ARM_FEATURE_AUXCR))
1846 goto bad_reg;
1847 switch (ARM_CPUID(env)) {
1848 case ARM_CPUID_ARM1026:
1849 return 1;
1850 case ARM_CPUID_ARM1136:
827df9f3 1851 case ARM_CPUID_ARM1136_R2:
9ee6e8bb
PB		 1852 return 7;
1853 case ARM_CPUID_ARM11MPCORE:
1854 return 1;
1855 case ARM_CPUID_CORTEXA8:
533d177a 1856 return 2;
10055562
PB		 1857 case ARM_CPUID_CORTEXA9:
1858 return 0;
9ee6e8bb
PB		 1859 default:
1860 goto bad_reg;
1861 }
b5ff1b31 1862 case 2: /* Coprocessor access register. */
610c3c8a
AZ		 1863 if (arm_feature(env, ARM_FEATURE_XSCALE))
1864 goto bad_reg;
b5ff1b31
FB		 1865 return env->cp15.c1_coproc;
1866 default:
1867 goto bad_reg;
1868 }
ce819861
PB		 1869 case 2: /* MMU Page table control / MPU cache control. */
1870 if (arm_feature(env, ARM_FEATURE_MPU)) {
1871 switch (op2) {
1872 case 0:
1873 return env->cp15.c2_data;
1874 break;
1875 case 1:
1876 return env->cp15.c2_insn;
1877 break;
1878 default:
1879 goto bad_reg;
1880 }
1881 } else {
9ee6e8bb
PB		 1882 switch (op2) {
1883 case 0:
1884 return env->cp15.c2_base0;
1885 case 1:
1886 return env->cp15.c2_base1;
1887 case 2:
b2fa1797 1888 return env->cp15.c2_control;
9ee6e8bb
PB		 1889 default:
1890 goto bad_reg;
1891 }
1892 }
ce819861 1893 case 3: /* MMU Domain access control / MPU write buffer control. */
b5ff1b31
FB		 1894 return env->cp15.c3;
1895 case 4: /* Reserved. */
1896 goto bad_reg;
ce819861 1897 case 5: /* MMU Fault status / MPU access permission. */
c3d2689d
AZ		 1898 if (arm_feature(env, ARM_FEATURE_OMAPCP))
1899 op2 = 0;
b5ff1b31
FB		 1900 switch (op2) {
1901 case 0:
ce819861
PB		 1902 if (arm_feature(env, ARM_FEATURE_MPU))
1903 return simple_mpu_ap_bits(env->cp15.c5_data);
b5ff1b31
FB		 1904 return env->cp15.c5_data;
1905 case 1:
ce819861
PB		 1906 if (arm_feature(env, ARM_FEATURE_MPU))
1907 return simple_mpu_ap_bits(env->cp15.c5_data);
1908 return env->cp15.c5_insn;
1909 case 2:
1910 if (!arm_feature(env, ARM_FEATURE_MPU))
1911 goto bad_reg;
1912 return env->cp15.c5_data;
1913 case 3:
1914 if (!arm_feature(env, ARM_FEATURE_MPU))
1915 goto bad_reg;
b5ff1b31
FB		 1916 return env->cp15.c5_insn;
1917 default:
1918 goto bad_reg;
1919 }
9ee6e8bb 1920 case 6: /* MMU Fault address. */
ce819861 1921 if (arm_feature(env, ARM_FEATURE_MPU)) {
9ee6e8bb 1922 if (crm >= 8)
ce819861 1923 goto bad_reg;
9ee6e8bb 1924 return env->cp15.c6_region[crm];
ce819861 1925 } else {
c3d2689d
AZ		 1926 if (arm_feature(env, ARM_FEATURE_OMAPCP))
1927 op2 = 0;
9ee6e8bb
PB		 1928 switch (op2) {
1929 case 0:
1930 return env->cp15.c6_data;
1931 case 1:
1932 if (arm_feature(env, ARM_FEATURE_V6)) {
1933 /* Watchpoint Fault Adrress. */
1934 return 0; /* Not implemented. */
1935 } else {
1936 /* Instruction Fault Adrress. */
1937 /* Arm9 doesn't have an IFAR, but implementing it anyway
1938 shouldn't do any harm. */
1939 return env->cp15.c6_insn;
1940 }
1941 case 2:
1942 if (arm_feature(env, ARM_FEATURE_V6)) {
1943 /* Instruction Fault Adrress. */
1944 return env->cp15.c6_insn;
1945 } else {
1946 goto bad_reg;
1947 }
1948 default:
1949 goto bad_reg;
1950 }
b5ff1b31
FB		 1951 }
1952 case 7: /* Cache control. */
f8bf8606
AL		 1953 if (crm == 4 && op1 == 0 && op2 == 0) {
1954 return env->cp15.c7_par;
1955 }
6fbe23d5
PB		 1956 /* FIXME: Should only clear Z flag if destination is r15. */
1957 env->ZF = 0;
b5ff1b31
FB		 1958 return 0;
1959 case 8: /* MMU TLB control. */
1960 goto bad_reg;
74594c9d
PM		 1961 case 9:
1962 switch (crm) {
1963 case 0: /* Cache lockdown */
1964 switch (op1) {
1965 case 0: /* L1 cache. */
1966 if (arm_feature(env, ARM_FEATURE_OMAPCP)) {
1967 return 0;
1968 }
1969 switch (op2) {
1970 case 0:
1971 return env->cp15.c9_data;
1972 case 1:
1973 return env->cp15.c9_insn;
1974 default:
1975 goto bad_reg;
1976 }
1977 case 1: /* L2 cache */
1978 if (crm != 0) {
1979 goto bad_reg;
1980 }
1981 /* L2 Lockdown and Auxiliary control. */
1982 return 0;
1983 default:
1984 goto bad_reg;
1985 }
1986 break;
1987 case 12: /* Performance monitor control */
1988 if (!arm_feature(env, ARM_FEATURE_V7)) {
1989 goto bad_reg;
1990 }
9ee6e8bb 1991 switch (op2) {
74594c9d
PM		 1992 case 0: /* performance monitor control register */
1993 return env->cp15.c9_pmcr;
1994 case 1: /* count enable set */
1995 case 2: /* count enable clear */
1996 return env->cp15.c9_pmcnten;
1997 case 3: /* overflow flag status */
1998 return env->cp15.c9_pmovsr;
1999 case 4: /* software increment */
2000 case 5: /* event counter selection register */
2001 return 0; /* Unimplemented, RAZ/WI */
9ee6e8bb
PB		 2002 default:
2003 goto bad_reg;
2004 }
74594c9d
PM		 2005 case 13: /* Performance counters */
2006 if (!arm_feature(env, ARM_FEATURE_V7)) {
2007 goto bad_reg;
2008 }
2009 switch (op2) {
2010 case 1: /* Event type select */
2011 return env->cp15.c9_pmxevtyper;
2012 case 0: /* Cycle count register */
2013 case 2: /* Event count register */
2014 /* Unimplemented, so RAZ/WI */
2015 return 0;
2016 default:
9ee6e8bb 2017 goto bad_reg;
74594c9d
PM		 2018 }
2019 case 14: /* Performance monitor control */
2020 if (!arm_feature(env, ARM_FEATURE_V7)) {
2021 goto bad_reg;
2022 }
2023 switch (op2) {
2024 case 0: /* user enable */
2025 return env->cp15.c9_pmuserenr;
2026 case 1: /* interrupt enable set */
2027 case 2: /* interrupt enable clear */
2028 return env->cp15.c9_pminten;
2029 default:
2030 goto bad_reg;
2031 }
b5ff1b31
FB		 2032 default:
2033 goto bad_reg;
2034 }
74594c9d 2035 break;
b5ff1b31
FB		 2036 case 10: /* MMU TLB lockdown. */
2037 /* ??? TLB lockdown not implemented. */
2038 return 0;
2039 case 11: /* TCM DMA control. */
2040 case 12: /* Reserved. */
2041 goto bad_reg;
2042 case 13: /* Process ID. */
2043 switch (op2) {
2044 case 0:
2045 return env->cp15.c13_fcse;
2046 case 1:
2047 return env->cp15.c13_context;
2048 default:
2049 goto bad_reg;
2050 }
2051 case 14: /* Reserved. */
2052 goto bad_reg;
2053 case 15: /* Implementation specific. */
c1713132 2054 if (arm_feature(env, ARM_FEATURE_XSCALE)) {
c3d2689d 2055 if (op2 == 0 && crm == 1)
c1713132
AZ		 2056 return env->cp15.c15_cpar;
2057
2058 goto bad_reg;
2059 }
c3d2689d
AZ		 2060 if (arm_feature(env, ARM_FEATURE_OMAPCP)) {
2061 switch (crm) {
2062 case 0:
2063 return 0;
2064 case 1: /* Read TI925T configuration. */
2065 return env->cp15.c15_ticonfig;
2066 case 2: /* Read I_max. */
2067 return env->cp15.c15_i_max;
2068 case 3: /* Read I_min. */
2069 return env->cp15.c15_i_min;
2070 case 4: /* Read thread-ID. */
2071 return env->cp15.c15_threadid;
2072 case 8: /* TI925T_status */
2073 return 0;
2074 }
827df9f3
AZ		 2075 /* TODO: Peripheral port remap register:
2076 * On OMAP2 mcr p15, 0, rn, c15, c2, 4 sets up the interrupt
2077 * controller base address at $rn & ~0xfff and map size of
2078 * 0x200 << ($rn & 0xfff), when MMU is off. */
c3d2689d
AZ		 2079 goto bad_reg;
2080 }
b5ff1b31
FB		 2081 return 0;
2082 }
2083bad_reg:
2084 /* ??? For debugging only. Should raise illegal instruction exception. */
9ee6e8bb
PB		 2085 cpu_abort(env, "Unimplemented cp15 register read (c%d, c%d, {%d, %d})\n",
2086 (insn >> 16) & 0xf, crm, op1, op2);
b5ff1b31
FB		 2087 return 0;
2088}
2089
b0109805 2090void HELPER(set_r13_banked)(CPUState *env, uint32_t mode, uint32_t val)
9ee6e8bb 2091{
39ea3d4e
PM		 2092 if ((env->uncached_cpsr & CPSR_M) == mode) {
2093 env->regs[13] = val;
2094 } else {
2095 env->banked_r13[bank_number(mode)] = val;
2096 }
9ee6e8bb
PB		 2097}
2098
b0109805 2099uint32_t HELPER(get_r13_banked)(CPUState *env, uint32_t mode)
9ee6e8bb 2100{
39ea3d4e
PM		 2101 if ((env->uncached_cpsr & CPSR_M) == mode) {
2102 return env->regs[13];
2103 } else {
2104 return env->banked_r13[bank_number(mode)];
2105 }
9ee6e8bb
PB		 2106}
2107
8984bd2e 2108uint32_t HELPER(v7m_mrs)(CPUState *env, uint32_t reg)
9ee6e8bb
PB		 2109{
2110 switch (reg) {
2111 case 0: /* APSR */
2112 return xpsr_read(env) & 0xf8000000;
2113 case 1: /* IAPSR */
2114 return xpsr_read(env) & 0xf80001ff;
2115 case 2: /* EAPSR */
2116 return xpsr_read(env) & 0xff00fc00;
2117 case 3: /* xPSR */
2118 return xpsr_read(env) & 0xff00fdff;
2119 case 5: /* IPSR */
2120 return xpsr_read(env) & 0x000001ff;
2121 case 6: /* EPSR */
2122 return xpsr_read(env) & 0x0700fc00;
2123 case 7: /* IEPSR */
2124 return xpsr_read(env) & 0x0700edff;
2125 case 8: /* MSP */
2126 return env->v7m.current_sp ? env->v7m.other_sp : env->regs[13];
2127 case 9: /* PSP */
2128 return env->v7m.current_sp ? env->regs[13] : env->v7m.other_sp;
2129 case 16: /* PRIMASK */
2130 return (env->uncached_cpsr & CPSR_I) != 0;
2131 case 17: /* FAULTMASK */
2132 return (env->uncached_cpsr & CPSR_F) != 0;
2133 case 18: /* BASEPRI */
2134 case 19: /* BASEPRI_MAX */
2135 return env->v7m.basepri;
2136 case 20: /* CONTROL */
2137 return env->v7m.control;
2138 default:
2139 /* ??? For debugging only. */
2140 cpu_abort(env, "Unimplemented system register read (%d)\n", reg);
2141 return 0;
2142 }
2143}
2144
8984bd2e 2145void HELPER(v7m_msr)(CPUState *env, uint32_t reg, uint32_t val)
9ee6e8bb
PB		 2146{
2147 switch (reg) {
2148 case 0: /* APSR */
2149 xpsr_write(env, val, 0xf8000000);
2150 break;
2151 case 1: /* IAPSR */
2152 xpsr_write(env, val, 0xf8000000);
2153 break;
2154 case 2: /* EAPSR */
2155 xpsr_write(env, val, 0xfe00fc00);
2156 break;
2157 case 3: /* xPSR */
2158 xpsr_write(env, val, 0xfe00fc00);
2159 break;
2160 case 5: /* IPSR */
2161 /* IPSR bits are readonly. */
2162 break;
2163 case 6: /* EPSR */
2164 xpsr_write(env, val, 0x0600fc00);
2165 break;
2166 case 7: /* IEPSR */
2167 xpsr_write(env, val, 0x0600fc00);
2168 break;
2169 case 8: /* MSP */
2170 if (env->v7m.current_sp)
2171 env->v7m.other_sp = val;
2172 else
2173 env->regs[13] = val;
2174 break;
2175 case 9: /* PSP */
2176 if (env->v7m.current_sp)
2177 env->regs[13] = val;
2178 else
2179 env->v7m.other_sp = val;
2180 break;
2181 case 16: /* PRIMASK */
2182 if (val & 1)
2183 env->uncached_cpsr |= CPSR_I;
2184 else
2185 env->uncached_cpsr &= ~CPSR_I;
2186 break;
2187 case 17: /* FAULTMASK */
2188 if (val & 1)
2189 env->uncached_cpsr |= CPSR_F;
2190 else
2191 env->uncached_cpsr &= ~CPSR_F;
2192 break;
2193 case 18: /* BASEPRI */
2194 env->v7m.basepri = val & 0xff;
2195 break;
2196 case 19: /* BASEPRI_MAX */
2197 val &= 0xff;
2198 if (val != 0 && (val < env->v7m.basepri || env->v7m.basepri == 0))
2199 env->v7m.basepri = val;
2200 break;
2201 case 20: /* CONTROL */
2202 env->v7m.control = val & 3;
2203 switch_v7m_sp(env, (val & 2) != 0);
2204 break;
2205 default:
2206 /* ??? For debugging only. */
2207 cpu_abort(env, "Unimplemented system register write (%d)\n", reg);
2208 return;
2209 }
2210}
2211
c1713132
AZ		 2212void cpu_arm_set_cp_io(CPUARMState *env, int cpnum,
2213 ARMReadCPFunc *cp_read, ARMWriteCPFunc *cp_write,
2214 void *opaque)
2215{
2216 if (cpnum < 0 || cpnum > 14) {
2217 cpu_abort(env, "Bad coprocessor number: %i\n", cpnum);
2218 return;
2219 }
2220
2221 env->cp[cpnum].cp_read = cp_read;
2222 env->cp[cpnum].cp_write = cp_write;
2223 env->cp[cpnum].opaque = opaque;
2224}
2225
b5ff1b31 2226#endif
6ddbc6e4
PB		 2227
2228/* Note that signed overflow is undefined in C. The following routines are
2229 careful to use unsigned types where modulo arithmetic is required.
2230 Failure to do so _will_ break on newer gcc. */
2231
2232/* Signed saturating arithmetic. */
2233
1654b2d6 2234/* Perform 16-bit signed saturating addition. */
6ddbc6e4
PB		 2235static inline uint16_t add16_sat(uint16_t a, uint16_t b)
2236{
2237 uint16_t res;
2238
2239 res = a + b;
2240 if (((res ^ a) & 0x8000) && !((a ^ b) & 0x8000)) {
2241 if (a & 0x8000)
2242 res = 0x8000;
2243 else
2244 res = 0x7fff;
2245 }
2246 return res;
2247}
2248
1654b2d6 2249/* Perform 8-bit signed saturating addition. */
6ddbc6e4
PB		 2250static inline uint8_t add8_sat(uint8_t a, uint8_t b)
2251{
2252 uint8_t res;
2253
2254 res = a + b;
2255 if (((res ^ a) & 0x80) && !((a ^ b) & 0x80)) {
2256 if (a & 0x80)
2257 res = 0x80;
2258 else
2259 res = 0x7f;
2260 }
2261 return res;
2262}
2263
1654b2d6 2264/* Perform 16-bit signed saturating subtraction. */
6ddbc6e4
PB		 2265static inline uint16_t sub16_sat(uint16_t a, uint16_t b)
2266{
2267 uint16_t res;
2268
2269 res = a - b;
2270 if (((res ^ a) & 0x8000) && ((a ^ b) & 0x8000)) {
2271 if (a & 0x8000)
2272 res = 0x8000;
2273 else
2274 res = 0x7fff;
2275 }
2276 return res;
2277}
2278
1654b2d6 2279/* Perform 8-bit signed saturating subtraction. */
6ddbc6e4
PB		 2280static inline uint8_t sub8_sat(uint8_t a, uint8_t b)
2281{
2282 uint8_t res;
2283
2284 res = a - b;
2285 if (((res ^ a) & 0x80) && ((a ^ b) & 0x80)) {
2286 if (a & 0x80)
2287 res = 0x80;
2288 else
2289 res = 0x7f;
2290 }
2291 return res;
2292}
2293
2294#define ADD16(a, b, n) RESULT(add16_sat(a, b), n, 16);
2295#define SUB16(a, b, n) RESULT(sub16_sat(a, b), n, 16);
2296#define ADD8(a, b, n) RESULT(add8_sat(a, b), n, 8);
2297#define SUB8(a, b, n) RESULT(sub8_sat(a, b), n, 8);
2298#define PFX q
2299
2300#include "op_addsub.h"
2301
2302/* Unsigned saturating arithmetic. */
460a09c1 2303static inline uint16_t add16_usat(uint16_t a, uint16_t b)
6ddbc6e4
PB		 2304{
2305 uint16_t res;
2306 res = a + b;
2307 if (res < a)
2308 res = 0xffff;
2309 return res;
2310}
2311
460a09c1 2312static inline uint16_t sub16_usat(uint16_t a, uint16_t b)
6ddbc6e4 2313{
4c4fd3f8 2314 if (a > b)
6ddbc6e4
PB		 2315 return a - b;
2316 else
2317 return 0;
2318}
2319
2320static inline uint8_t add8_usat(uint8_t a, uint8_t b)
2321{
2322 uint8_t res;
2323 res = a + b;
2324 if (res < a)
2325 res = 0xff;
2326 return res;
2327}
2328
2329static inline uint8_t sub8_usat(uint8_t a, uint8_t b)
2330{
4c4fd3f8 2331 if (a > b)
6ddbc6e4
PB		 2332 return a - b;
2333 else
2334 return 0;
2335}
2336
2337#define ADD16(a, b, n) RESULT(add16_usat(a, b), n, 16);
2338#define SUB16(a, b, n) RESULT(sub16_usat(a, b), n, 16);
2339#define ADD8(a, b, n) RESULT(add8_usat(a, b), n, 8);
2340#define SUB8(a, b, n) RESULT(sub8_usat(a, b), n, 8);
2341#define PFX uq
2342
2343#include "op_addsub.h"
2344
2345/* Signed modulo arithmetic. */
2346#define SARITH16(a, b, n, op) do { \
2347 int32_t sum; \
db6e2e65 2348 sum = (int32_t)(int16_t)(a) op (int32_t)(int16_t)(b); \
6ddbc6e4
PB		 2349 RESULT(sum, n, 16); \
2350 if (sum >= 0) \
2351 ge |= 3 << (n * 2); \
2352 } while(0)
2353
2354#define SARITH8(a, b, n, op) do { \
2355 int32_t sum; \
db6e2e65 2356 sum = (int32_t)(int8_t)(a) op (int32_t)(int8_t)(b); \
6ddbc6e4
PB		 2357 RESULT(sum, n, 8); \
2358 if (sum >= 0) \
2359 ge |= 1 << n; \
2360 } while(0)
2361
2362
2363#define ADD16(a, b, n) SARITH16(a, b, n, +)
2364#define SUB16(a, b, n) SARITH16(a, b, n, -)
2365#define ADD8(a, b, n) SARITH8(a, b, n, +)
2366#define SUB8(a, b, n) SARITH8(a, b, n, -)
2367#define PFX s
2368#define ARITH_GE
2369
2370#include "op_addsub.h"
2371
2372/* Unsigned modulo arithmetic. */
2373#define ADD16(a, b, n) do { \
2374 uint32_t sum; \
2375 sum = (uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b); \
2376 RESULT(sum, n, 16); \
a87aa10b 2377 if ((sum >> 16) == 1) \
6ddbc6e4
PB		 2378 ge |= 3 << (n * 2); \
2379 } while(0)
2380
2381#define ADD8(a, b, n) do { \
2382 uint32_t sum; \
2383 sum = (uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b); \
2384 RESULT(sum, n, 8); \
a87aa10b
AZ		 2385 if ((sum >> 8) == 1) \
2386 ge |= 1 << n; \
6ddbc6e4
PB		 2387 } while(0)
2388
2389#define SUB16(a, b, n) do { \
2390 uint32_t sum; \
2391 sum = (uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b); \
2392 RESULT(sum, n, 16); \
2393 if ((sum >> 16) == 0) \
2394 ge |= 3 << (n * 2); \
2395 } while(0)
2396
2397#define SUB8(a, b, n) do { \
2398 uint32_t sum; \
2399 sum = (uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b); \
2400 RESULT(sum, n, 8); \
2401 if ((sum >> 8) == 0) \
a87aa10b 2402 ge |= 1 << n; \
6ddbc6e4
PB		 2403 } while(0)
2404
2405#define PFX u
2406#define ARITH_GE
2407
2408#include "op_addsub.h"
2409
2410/* Halved signed arithmetic. */
2411#define ADD16(a, b, n) \
2412 RESULT(((int32_t)(int16_t)(a) + (int32_t)(int16_t)(b)) >> 1, n, 16)
2413#define SUB16(a, b, n) \
2414 RESULT(((int32_t)(int16_t)(a) - (int32_t)(int16_t)(b)) >> 1, n, 16)
2415#define ADD8(a, b, n) \
2416 RESULT(((int32_t)(int8_t)(a) + (int32_t)(int8_t)(b)) >> 1, n, 8)
2417#define SUB8(a, b, n) \
2418 RESULT(((int32_t)(int8_t)(a) - (int32_t)(int8_t)(b)) >> 1, n, 8)
2419#define PFX sh
2420
2421#include "op_addsub.h"
2422
2423/* Halved unsigned arithmetic. */
2424#define ADD16(a, b, n) \
2425 RESULT(((uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b)) >> 1, n, 16)
2426#define SUB16(a, b, n) \
2427 RESULT(((uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b)) >> 1, n, 16)
2428#define ADD8(a, b, n) \
2429 RESULT(((uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b)) >> 1, n, 8)
2430#define SUB8(a, b, n) \
2431 RESULT(((uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b)) >> 1, n, 8)
2432#define PFX uh
2433
2434#include "op_addsub.h"
2435
2436static inline uint8_t do_usad(uint8_t a, uint8_t b)
2437{
2438 if (a > b)
2439 return a - b;
2440 else
2441 return b - a;
2442}
2443
2444/* Unsigned sum of absolute byte differences. */
2445uint32_t HELPER(usad8)(uint32_t a, uint32_t b)
2446{
2447 uint32_t sum;
2448 sum = do_usad(a, b);
2449 sum += do_usad(a >> 8, b >> 8);
2450 sum += do_usad(a >> 16, b >>16);
2451 sum += do_usad(a >> 24, b >> 24);
2452 return sum;
2453}
2454
2455/* For ARMv6 SEL instruction. */
2456uint32_t HELPER(sel_flags)(uint32_t flags, uint32_t a, uint32_t b)
2457{
2458 uint32_t mask;
2459
2460 mask = 0;
2461 if (flags & 1)
2462 mask |= 0xff;
2463 if (flags & 2)
2464 mask |= 0xff00;
2465 if (flags & 4)
2466 mask |= 0xff0000;
2467 if (flags & 8)
2468 mask |= 0xff000000;
2469 return (a & mask) | (b & ~mask);
2470}
2471
5e3f878a
PB		 2472uint32_t HELPER(logicq_cc)(uint64_t val)
2473{
2474 return (val >> 32) | (val != 0);
2475}
4373f3ce
PB		 2476
2477/* VFP support. We follow the convention used for VFP instrunctions:
2478 Single precition routines have a "s" suffix, double precision a
2479 "d" suffix. */
2480
2481/* Convert host exception flags to vfp form. */
2482static inline int vfp_exceptbits_from_host(int host_bits)
2483{
2484 int target_bits = 0;
2485
2486 if (host_bits & float_flag_invalid)
2487 target_bits |= 1;
2488 if (host_bits & float_flag_divbyzero)
2489 target_bits |= 2;
2490 if (host_bits & float_flag_overflow)
2491 target_bits |= 4;
36802b6b 2492 if (host_bits & (float_flag_underflow | float_flag_output_denormal))
4373f3ce
PB		 2493 target_bits |= 8;
2494 if (host_bits & float_flag_inexact)
2495 target_bits |= 0x10;
cecd8504
PM		 2496 if (host_bits & float_flag_input_denormal)
2497 target_bits |= 0x80;
4373f3ce
PB		 2498 return target_bits;
2499}
2500
2501uint32_t HELPER(vfp_get_fpscr)(CPUState *env)
2502{
2503 int i;
2504 uint32_t fpscr;
2505
2506 fpscr = (env->vfp.xregs[ARM_VFP_FPSCR] & 0xffc8ffff)
2507 | (env->vfp.vec_len << 16)
2508 | (env->vfp.vec_stride << 20);
2509 i = get_float_exception_flags(&env->vfp.fp_status);
3a492f3a 2510 i |= get_float_exception_flags(&env->vfp.standard_fp_status);
4373f3ce
PB		 2511 fpscr |= vfp_exceptbits_from_host(i);
2512 return fpscr;
2513}
2514
01653295
PM		 2515uint32_t vfp_get_fpscr(CPUState *env)
2516{
2517 return HELPER(vfp_get_fpscr)(env);
2518}
2519
4373f3ce
PB		 2520/* Convert vfp exception flags to target form. */
2521static inline int vfp_exceptbits_to_host(int target_bits)
2522{
2523 int host_bits = 0;
2524
2525 if (target_bits & 1)
2526 host_bits |= float_flag_invalid;
2527 if (target_bits & 2)
2528 host_bits |= float_flag_divbyzero;
2529 if (target_bits & 4)
2530 host_bits |= float_flag_overflow;
2531 if (target_bits & 8)
2532 host_bits |= float_flag_underflow;
2533 if (target_bits & 0x10)
2534 host_bits |= float_flag_inexact;
cecd8504
PM		 2535 if (target_bits & 0x80)
2536 host_bits |= float_flag_input_denormal;
4373f3ce
PB		 2537 return host_bits;
2538}
2539
2540void HELPER(vfp_set_fpscr)(CPUState *env, uint32_t val)
2541{
2542 int i;
2543 uint32_t changed;
2544
2545 changed = env->vfp.xregs[ARM_VFP_FPSCR];
2546 env->vfp.xregs[ARM_VFP_FPSCR] = (val & 0xffc8ffff);
2547 env->vfp.vec_len = (val >> 16) & 7;
2548 env->vfp.vec_stride = (val >> 20) & 3;
2549
2550 changed ^= val;
2551 if (changed & (3 << 22)) {
2552 i = (val >> 22) & 3;
2553 switch (i) {
2554 case 0:
2555 i = float_round_nearest_even;
2556 break;
2557 case 1:
2558 i = float_round_up;
2559 break;
2560 case 2:
2561 i = float_round_down;
2562 break;
2563 case 3:
2564 i = float_round_to_zero;
2565 break;
2566 }
2567 set_float_rounding_mode(i, &env->vfp.fp_status);
2568 }
cecd8504 2569 if (changed & (1 << 24)) {
fe76d976 2570 set_flush_to_zero((val & (1 << 24)) != 0, &env->vfp.fp_status);
cecd8504
PM		 2571 set_flush_inputs_to_zero((val & (1 << 24)) != 0, &env->vfp.fp_status);
2572 }
5c7908ed
PB		 2573 if (changed & (1 << 25))
2574 set_default_nan_mode((val & (1 << 25)) != 0, &env->vfp.fp_status);
4373f3ce 2575
b12c390b 2576 i = vfp_exceptbits_to_host(val);
4373f3ce 2577 set_float_exception_flags(i, &env->vfp.fp_status);
3a492f3a 2578 set_float_exception_flags(0, &env->vfp.standard_fp_status);
4373f3ce
PB		 2579}
2580
01653295
PM		 2581void vfp_set_fpscr(CPUState *env, uint32_t val)
2582{
2583 HELPER(vfp_set_fpscr)(env, val);
2584}
2585
4373f3ce
PB		 2586#define VFP_HELPER(name, p) HELPER(glue(glue(vfp_,name),p))
2587
2588#define VFP_BINOP(name) \
ae1857ec 2589float32 VFP_HELPER(name, s)(float32 a, float32 b, void *fpstp) \
4373f3ce 2590{ \
ae1857ec
PM		 2591 float_status *fpst = fpstp; \
2592 return float32_ ## name(a, b, fpst); \
4373f3ce 2593} \
ae1857ec 2594float64 VFP_HELPER(name, d)(float64 a, float64 b, void *fpstp) \
4373f3ce 2595{ \
ae1857ec
PM		 2596 float_status *fpst = fpstp; \
2597 return float64_ ## name(a, b, fpst); \
4373f3ce
PB		 2598}
2599VFP_BINOP(add)
2600VFP_BINOP(sub)
2601VFP_BINOP(mul)
2602VFP_BINOP(div)
2603#undef VFP_BINOP
2604
2605float32 VFP_HELPER(neg, s)(float32 a)
2606{
2607 return float32_chs(a);
2608}
2609
2610float64 VFP_HELPER(neg, d)(float64 a)
2611{
66230e0d 2612 return float64_chs(a);
4373f3ce
PB		 2613}
2614
2615float32 VFP_HELPER(abs, s)(float32 a)
2616{
2617 return float32_abs(a);
2618}
2619
2620float64 VFP_HELPER(abs, d)(float64 a)
2621{
66230e0d 2622 return float64_abs(a);
4373f3ce
PB		 2623}
2624
2625float32 VFP_HELPER(sqrt, s)(float32 a, CPUState *env)
2626{
2627 return float32_sqrt(a, &env->vfp.fp_status);
2628}
2629
2630float64 VFP_HELPER(sqrt, d)(float64 a, CPUState *env)
2631{
2632 return float64_sqrt(a, &env->vfp.fp_status);
2633}
2634
2635/* XXX: check quiet/signaling case */
2636#define DO_VFP_cmp(p, type) \
2637void VFP_HELPER(cmp, p)(type a, type b, CPUState *env) \
2638{ \
2639 uint32_t flags; \
2640 switch(type ## _compare_quiet(a, b, &env->vfp.fp_status)) { \
2641 case 0: flags = 0x6; break; \
2642 case -1: flags = 0x8; break; \
2643 case 1: flags = 0x2; break; \
2644 default: case 2: flags = 0x3; break; \
2645 } \
2646 env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \
2647 | (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \
2648} \
2649void VFP_HELPER(cmpe, p)(type a, type b, CPUState *env) \
2650{ \
2651 uint32_t flags; \
2652 switch(type ## _compare(a, b, &env->vfp.fp_status)) { \
2653 case 0: flags = 0x6; break; \
2654 case -1: flags = 0x8; break; \
2655 case 1: flags = 0x2; break; \
2656 default: case 2: flags = 0x3; break; \
2657 } \
2658 env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \
2659 | (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \
2660}
2661DO_VFP_cmp(s, float32)
2662DO_VFP_cmp(d, float64)
2663#undef DO_VFP_cmp
2664
5500b06c 2665/* Integer to float and float to integer conversions */
4373f3ce 2666
5500b06c
PM		 2667#define CONV_ITOF(name, fsz, sign) \
2668 float##fsz HELPER(name)(uint32_t x, void *fpstp) \
2669{ \
2670 float_status *fpst = fpstp; \
2671 return sign##int32_to_##float##fsz(x, fpst); \
4373f3ce
PB		 2672}
2673
5500b06c
PM		 2674#define CONV_FTOI(name, fsz, sign, round) \
2675uint32_t HELPER(name)(float##fsz x, void *fpstp) \
2676{ \
2677 float_status *fpst = fpstp; \
2678 if (float##fsz##_is_any_nan(x)) { \
2679 float_raise(float_flag_invalid, fpst); \
2680 return 0; \
2681 } \
2682 return float##fsz##_to_##sign##int32##round(x, fpst); \
4373f3ce
PB		 2683}
2684
5500b06c
PM		 2685#define FLOAT_CONVS(name, p, fsz, sign) \
2686CONV_ITOF(vfp_##name##to##p, fsz, sign) \
2687CONV_FTOI(vfp_to##name##p, fsz, sign, ) \
2688CONV_FTOI(vfp_to##name##z##p, fsz, sign, _round_to_zero)
4373f3ce 2689
5500b06c
PM		 2690FLOAT_CONVS(si, s, 32, )
2691FLOAT_CONVS(si, d, 64, )
2692FLOAT_CONVS(ui, s, 32, u)
2693FLOAT_CONVS(ui, d, 64, u)
4373f3ce 2694
5500b06c
PM		 2695#undef CONV_ITOF
2696#undef CONV_FTOI
2697#undef FLOAT_CONVS
4373f3ce
PB		 2698
2699/* floating point conversion */
2700float64 VFP_HELPER(fcvtd, s)(float32 x, CPUState *env)
2701{
2d627737
PM		 2702 float64 r = float32_to_float64(x, &env->vfp.fp_status);
2703 /* ARM requires that S<->D conversion of any kind of NaN generates
2704 * a quiet NaN by forcing the most significant frac bit to 1.
2705 */
2706 return float64_maybe_silence_nan(r);
4373f3ce
PB		 2707}
2708
2709float32 VFP_HELPER(fcvts, d)(float64 x, CPUState *env)
2710{
2d627737
PM		 2711 float32 r = float64_to_float32(x, &env->vfp.fp_status);
2712 /* ARM requires that S<->D conversion of any kind of NaN generates
2713 * a quiet NaN by forcing the most significant frac bit to 1.
2714 */
2715 return float32_maybe_silence_nan(r);
4373f3ce
PB		 2716}
2717
2718/* VFP3 fixed point conversion. */
622465e1 2719#define VFP_CONV_FIX(name, p, fsz, itype, sign) \
5500b06c
PM		 2720float##fsz HELPER(vfp_##name##to##p)(uint##fsz##_t x, uint32_t shift, \
2721 void *fpstp) \
4373f3ce 2722{ \
5500b06c 2723 float_status *fpst = fpstp; \
622465e1 2724 float##fsz tmp; \
5500b06c
PM		 2725 tmp = sign##int32_to_##float##fsz((itype##_t)x, fpst); \
2726 return float##fsz##_scalbn(tmp, -(int)shift, fpst); \
4373f3ce 2727} \
5500b06c
PM		 2728uint##fsz##_t HELPER(vfp_to##name##p)(float##fsz x, uint32_t shift, \
2729 void *fpstp) \
4373f3ce 2730{ \
5500b06c 2731 float_status *fpst = fpstp; \
622465e1
PM		 2732 float##fsz tmp; \
2733 if (float##fsz##_is_any_nan(x)) { \
5500b06c 2734 float_raise(float_flag_invalid, fpst); \
622465e1 2735 return 0; \
09d9487f 2736 } \
5500b06c
PM		 2737 tmp = float##fsz##_scalbn(x, shift, fpst); \
2738 return float##fsz##_to_##itype##_round_to_zero(tmp, fpst); \
622465e1
PM		 2739}
2740
2741VFP_CONV_FIX(sh, d, 64, int16, )
2742VFP_CONV_FIX(sl, d, 64, int32, )
2743VFP_CONV_FIX(uh, d, 64, uint16, u)
2744VFP_CONV_FIX(ul, d, 64, uint32, u)
2745VFP_CONV_FIX(sh, s, 32, int16, )
2746VFP_CONV_FIX(sl, s, 32, int32, )
2747VFP_CONV_FIX(uh, s, 32, uint16, u)
2748VFP_CONV_FIX(ul, s, 32, uint32, u)
4373f3ce
PB		 2749#undef VFP_CONV_FIX
2750
60011498 2751/* Half precision conversions. */
2d981da7 2752static float32 do_fcvt_f16_to_f32(uint32_t a, CPUState *env, float_status *s)
60011498 2753{
60011498 2754 int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0;
fb91678d
PM		 2755 float32 r = float16_to_float32(make_float16(a), ieee, s);
2756 if (ieee) {
2757 return float32_maybe_silence_nan(r);
2758 }
2759 return r;
60011498
PB		 2760}
2761
2d981da7 2762static uint32_t do_fcvt_f32_to_f16(float32 a, CPUState *env, float_status *s)
60011498 2763{
60011498 2764 int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0;
fb91678d
PM		 2765 float16 r = float32_to_float16(a, ieee, s);
2766 if (ieee) {
2767 r = float16_maybe_silence_nan(r);
2768 }
2769 return float16_val(r);
60011498
PB		 2770}
2771
2d981da7
PM		 2772float32 HELPER(neon_fcvt_f16_to_f32)(uint32_t a, CPUState *env)
2773{
2774 return do_fcvt_f16_to_f32(a, env, &env->vfp.standard_fp_status);
2775}
2776
2777uint32_t HELPER(neon_fcvt_f32_to_f16)(float32 a, CPUState *env)
2778{
2779 return do_fcvt_f32_to_f16(a, env, &env->vfp.standard_fp_status);
2780}
2781
2782float32 HELPER(vfp_fcvt_f16_to_f32)(uint32_t a, CPUState *env)
2783{
2784 return do_fcvt_f16_to_f32(a, env, &env->vfp.fp_status);
2785}
2786
2787uint32_t HELPER(vfp_fcvt_f32_to_f16)(float32 a, CPUState *env)
2788{
2789 return do_fcvt_f32_to_f16(a, env, &env->vfp.fp_status);
2790}
2791
dda3ec49 2792#define float32_two make_float32(0x40000000)
6aae3df1
PM		 2793#define float32_three make_float32(0x40400000)
2794#define float32_one_point_five make_float32(0x3fc00000)
dda3ec49 2795
4373f3ce
PB		 2796float32 HELPER(recps_f32)(float32 a, float32 b, CPUState *env)
2797{
dda3ec49
PM		 2798 float_status *s = &env->vfp.standard_fp_status;
2799 if ((float32_is_infinity(a) && float32_is_zero_or_denormal(b)) ||
2800 (float32_is_infinity(b) && float32_is_zero_or_denormal(a))) {
43fe9bdb
PM		 2801 if (!(float32_is_zero(a) || float32_is_zero(b))) {
2802 float_raise(float_flag_input_denormal, s);
2803 }
dda3ec49
PM		 2804 return float32_two;
2805 }
2806 return float32_sub(float32_two, float32_mul(a, b, s), s);
4373f3ce
PB		 2807}
2808
2809float32 HELPER(rsqrts_f32)(float32 a, float32 b, CPUState *env)
2810{
71826966 2811 float_status *s = &env->vfp.standard_fp_status;
9ea62f57
PM		 2812 float32 product;
2813 if ((float32_is_infinity(a) && float32_is_zero_or_denormal(b)) ||
2814 (float32_is_infinity(b) && float32_is_zero_or_denormal(a))) {
43fe9bdb
PM		 2815 if (!(float32_is_zero(a) || float32_is_zero(b))) {
2816 float_raise(float_flag_input_denormal, s);
2817 }
6aae3df1 2818 return float32_one_point_five;
9ea62f57 2819 }
6aae3df1
PM		 2820 product = float32_mul(a, b, s);
2821 return float32_div(float32_sub(float32_three, product, s), float32_two, s);
4373f3ce
PB		 2822}
2823
8f8e3aa4
PB		 2824/* NEON helpers. */
2825
56bf4fe2
CL		 2826/* Constants 256 and 512 are used in some helpers; we avoid relying on
2827 * int->float conversions at run-time. */
2828#define float64_256 make_float64(0x4070000000000000LL)
2829#define float64_512 make_float64(0x4080000000000000LL)
2830
fe0e4872
CL		 2831/* The algorithm that must be used to calculate the estimate
2832 * is specified by the ARM ARM.
2833 */
2834static float64 recip_estimate(float64 a, CPUState *env)
2835{
1146a817
PM		 2836 /* These calculations mustn't set any fp exception flags,
2837 * so we use a local copy of the fp_status.
2838 */
2839 float_status dummy_status = env->vfp.standard_fp_status;
2840 float_status *s = &dummy_status;
fe0e4872
CL		 2841 /* q = (int)(a * 512.0) */
2842 float64 q = float64_mul(float64_512, a, s);
2843 int64_t q_int = float64_to_int64_round_to_zero(q, s);
2844
2845 /* r = 1.0 / (((double)q + 0.5) / 512.0) */
2846 q = int64_to_float64(q_int, s);
2847 q = float64_add(q, float64_half, s);
2848 q = float64_div(q, float64_512, s);
2849 q = float64_div(float64_one, q, s);
2850
2851 /* s = (int)(256.0 * r + 0.5) */
2852 q = float64_mul(q, float64_256, s);
2853 q = float64_add(q, float64_half, s);
2854 q_int = float64_to_int64_round_to_zero(q, s);
2855
2856 /* return (double)s / 256.0 */
2857 return float64_div(int64_to_float64(q_int, s), float64_256, s);
2858}
2859
4373f3ce
PB		 2860float32 HELPER(recpe_f32)(float32 a, CPUState *env)
2861{
fe0e4872
CL		 2862 float_status *s = &env->vfp.standard_fp_status;
2863 float64 f64;
2864 uint32_t val32 = float32_val(a);
2865
2866 int result_exp;
2867 int a_exp = (val32 & 0x7f800000) >> 23;
2868 int sign = val32 & 0x80000000;
2869
2870 if (float32_is_any_nan(a)) {
2871 if (float32_is_signaling_nan(a)) {
2872 float_raise(float_flag_invalid, s);
2873 }
2874 return float32_default_nan;
2875 } else if (float32_is_infinity(a)) {
2876 return float32_set_sign(float32_zero, float32_is_neg(a));
2877 } else if (float32_is_zero_or_denormal(a)) {
43fe9bdb
PM		 2878 if (!float32_is_zero(a)) {
2879 float_raise(float_flag_input_denormal, s);
2880 }
fe0e4872
CL		 2881 float_raise(float_flag_divbyzero, s);
2882 return float32_set_sign(float32_infinity, float32_is_neg(a));
2883 } else if (a_exp >= 253) {
2884 float_raise(float_flag_underflow, s);
2885 return float32_set_sign(float32_zero, float32_is_neg(a));
2886 }
2887
2888 f64 = make_float64((0x3feULL << 52)
2889 | ((int64_t)(val32 & 0x7fffff) << 29));
2890
2891 result_exp = 253 - a_exp;
2892
2893 f64 = recip_estimate(f64, env);
2894
2895 val32 = sign
2896 | ((result_exp & 0xff) << 23)
2897 | ((float64_val(f64) >> 29) & 0x7fffff);
2898 return make_float32(val32);
4373f3ce
PB		 2899}
2900
e07be5d2
CL		 2901/* The algorithm that must be used to calculate the estimate
2902 * is specified by the ARM ARM.
2903 */
2904static float64 recip_sqrt_estimate(float64 a, CPUState *env)
2905{
1146a817
PM		 2906 /* These calculations mustn't set any fp exception flags,
2907 * so we use a local copy of the fp_status.
2908 */
2909 float_status dummy_status = env->vfp.standard_fp_status;
2910 float_status *s = &dummy_status;
e07be5d2
CL		 2911 float64 q;
2912 int64_t q_int;
2913
2914 if (float64_lt(a, float64_half, s)) {
2915 /* range 0.25 <= a < 0.5 */
2916
2917 /* a in units of 1/512 rounded down */
2918 /* q0 = (int)(a * 512.0); */
2919 q = float64_mul(float64_512, a, s);
2920 q_int = float64_to_int64_round_to_zero(q, s);
2921
2922 /* reciprocal root r */
2923 /* r = 1.0 / sqrt(((double)q0 + 0.5) / 512.0); */
2924 q = int64_to_float64(q_int, s);
2925 q = float64_add(q, float64_half, s);
2926 q = float64_div(q, float64_512, s);
2927 q = float64_sqrt(q, s);
2928 q = float64_div(float64_one, q, s);
2929 } else {
2930 /* range 0.5 <= a < 1.0 */
2931
2932 /* a in units of 1/256 rounded down */
2933 /* q1 = (int)(a * 256.0); */
2934 q = float64_mul(float64_256, a, s);
2935 int64_t q_int = float64_to_int64_round_to_zero(q, s);
2936
2937 /* reciprocal root r */
2938 /* r = 1.0 /sqrt(((double)q1 + 0.5) / 256); */
2939 q = int64_to_float64(q_int, s);
2940 q = float64_add(q, float64_half, s);
2941 q = float64_div(q, float64_256, s);
2942 q = float64_sqrt(q, s);
2943 q = float64_div(float64_one, q, s);
2944 }
2945 /* r in units of 1/256 rounded to nearest */
2946 /* s = (int)(256.0 * r + 0.5); */
2947
2948 q = float64_mul(q, float64_256,s );
2949 q = float64_add(q, float64_half, s);
2950 q_int = float64_to_int64_round_to_zero(q, s);
2951
2952 /* return (double)s / 256.0;*/
2953 return float64_div(int64_to_float64(q_int, s), float64_256, s);
2954}
2955
4373f3ce
PB		 2956float32 HELPER(rsqrte_f32)(float32 a, CPUState *env)
2957{
e07be5d2
CL		 2958 float_status *s = &env->vfp.standard_fp_status;
2959 int result_exp;
2960 float64 f64;
2961 uint32_t val;
2962 uint64_t val64;
2963
2964 val = float32_val(a);
2965
2966 if (float32_is_any_nan(a)) {
2967 if (float32_is_signaling_nan(a)) {
2968 float_raise(float_flag_invalid, s);
2969 }
2970 return float32_default_nan;
2971 } else if (float32_is_zero_or_denormal(a)) {
43fe9bdb
PM		 2972 if (!float32_is_zero(a)) {
2973 float_raise(float_flag_input_denormal, s);
2974 }
e07be5d2
CL		 2975 float_raise(float_flag_divbyzero, s);
2976 return float32_set_sign(float32_infinity, float32_is_neg(a));
2977 } else if (float32_is_neg(a)) {
2978 float_raise(float_flag_invalid, s);
2979 return float32_default_nan;
2980 } else if (float32_is_infinity(a)) {
2981 return float32_zero;
2982 }
2983
2984 /* Normalize to a double-precision value between 0.25 and 1.0,
2985 * preserving the parity of the exponent. */
2986 if ((val & 0x800000) == 0) {
2987 f64 = make_float64(((uint64_t)(val & 0x80000000) << 32)
2988 | (0x3feULL << 52)
2989 | ((uint64_t)(val & 0x7fffff) << 29));
2990 } else {
2991 f64 = make_float64(((uint64_t)(val & 0x80000000) << 32)
2992 | (0x3fdULL << 52)
2993 | ((uint64_t)(val & 0x7fffff) << 29));
2994 }
2995
2996 result_exp = (380 - ((val & 0x7f800000) >> 23)) / 2;
2997
2998 f64 = recip_sqrt_estimate(f64, env);
2999
3000 val64 = float64_val(f64);
3001
3002 val = ((val64 >> 63) & 0x80000000)
3003 | ((result_exp & 0xff) << 23)
3004 | ((val64 >> 29) & 0x7fffff);
3005 return make_float32(val);
4373f3ce
PB		 3006}
3007
3008uint32_t HELPER(recpe_u32)(uint32_t a, CPUState *env)
3009{
fe0e4872
CL		 3010 float64 f64;
3011
3012 if ((a & 0x80000000) == 0) {
3013 return 0xffffffff;
3014 }
3015
3016 f64 = make_float64((0x3feULL << 52)
3017 | ((int64_t)(a & 0x7fffffff) << 21));
3018
3019 f64 = recip_estimate (f64, env);
3020
3021 return 0x80000000 | ((float64_val(f64) >> 21) & 0x7fffffff);
4373f3ce
PB		 3022}
3023
3024uint32_t HELPER(rsqrte_u32)(uint32_t a, CPUState *env)
3025{
e07be5d2
CL		 3026 float64 f64;
3027
3028 if ((a & 0xc0000000) == 0) {
3029 return 0xffffffff;
3030 }
3031
3032 if (a & 0x80000000) {
3033 f64 = make_float64((0x3feULL << 52)
3034 | ((uint64_t)(a & 0x7fffffff) << 21));
3035 } else { /* bits 31-30 == '01' */
3036 f64 = make_float64((0x3fdULL << 52)
3037 | ((uint64_t)(a & 0x3fffffff) << 22));
3038 }
3039
3040 f64 = recip_sqrt_estimate(f64, env);
3041
3042 return 0x80000000 | ((float64_val(f64) >> 21) & 0x7fffffff);
4373f3ce 3043}
fe1479c3
PB		 3044
3045void HELPER(set_teecr)(CPUState *env, uint32_t val)
3046{
3047 val &= 1;
3048 if (env->teecr != val) {
3049 env->teecr = val;
3050 tb_flush(env);
3051 }
3052}
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