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[mirror_qemu.git] / target-arm / helper.c
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b5ff1b31
FB		 1#include <stdio.h>
2#include <stdlib.h>
3#include <string.h>
4
5#include "cpu.h"
6#include "exec-all.h"
9ee6e8bb 7#include "gdbstub.h"
b26eefb6 8#include "helpers.h"
ca10f867 9#include "qemu-common.h"
9ee6e8bb
PB		 10
11static uint32_t cortexa8_cp15_c0_c1[8] =
12{ 0x1031, 0x11, 0x400, 0, 0x31100003, 0x20000000, 0x01202000, 0x11 };
13
14static uint32_t cortexa8_cp15_c0_c2[8] =
15{ 0x00101111, 0x12112111, 0x21232031, 0x11112131, 0x00111142, 0, 0, 0 };
16
17static uint32_t mpcore_cp15_c0_c1[8] =
18{ 0x111, 0x1, 0, 0x2, 0x01100103, 0x10020302, 0x01222000, 0 };
19
20static uint32_t mpcore_cp15_c0_c2[8] =
21{ 0x00100011, 0x12002111, 0x11221011, 0x01102131, 0x141, 0, 0, 0 };
22
23static uint32_t arm1136_cp15_c0_c1[8] =
24{ 0x111, 0x1, 0x2, 0x3, 0x01130003, 0x10030302, 0x01222110, 0 };
25
26static uint32_t arm1136_cp15_c0_c2[8] =
27{ 0x00140011, 0x12002111, 0x11231111, 0x01102131, 0x141, 0, 0, 0 };
b5ff1b31 28
aaed909a
FB		 29static uint32_t cpu_arm_find_by_name(const char *name);
30
f3d6b95e
PB		 31static inline void set_feature(CPUARMState *env, int feature)
32{
33 env->features |= 1u << feature;
34}
35
36static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
37{
38 env->cp15.c0_cpuid = id;
39 switch (id) {
40 case ARM_CPUID_ARM926:
41 set_feature(env, ARM_FEATURE_VFP);
42 env->vfp.xregs[ARM_VFP_FPSID] = 0x41011090;
c1713132 43 env->cp15.c0_cachetype = 0x1dd20d2;
610c3c8a 44 env->cp15.c1_sys = 0x00090078;
f3d6b95e 45 break;
ce819861
PB		 46 case ARM_CPUID_ARM946:
47 set_feature(env, ARM_FEATURE_MPU);
48 env->cp15.c0_cachetype = 0x0f004006;
610c3c8a 49 env->cp15.c1_sys = 0x00000078;
ce819861 50 break;
f3d6b95e
PB		 51 case ARM_CPUID_ARM1026:
52 set_feature(env, ARM_FEATURE_VFP);
53 set_feature(env, ARM_FEATURE_AUXCR);
54 env->vfp.xregs[ARM_VFP_FPSID] = 0x410110a0;
c1713132 55 env->cp15.c0_cachetype = 0x1dd20d2;
610c3c8a 56 env->cp15.c1_sys = 0x00090078;
c1713132 57 break;
827df9f3 58 case ARM_CPUID_ARM1136_R2:
9ee6e8bb
PB		 59 case ARM_CPUID_ARM1136:
60 set_feature(env, ARM_FEATURE_V6);
61 set_feature(env, ARM_FEATURE_VFP);
62 set_feature(env, ARM_FEATURE_AUXCR);
63 env->vfp.xregs[ARM_VFP_FPSID] = 0x410120b4;
64 env->vfp.xregs[ARM_VFP_MVFR0] = 0x11111111;
65 env->vfp.xregs[ARM_VFP_MVFR1] = 0x00000000;
66 memcpy(env->cp15.c0_c1, arm1136_cp15_c0_c1, 8 * sizeof(uint32_t));
22478e79 67 memcpy(env->cp15.c0_c2, arm1136_cp15_c0_c2, 8 * sizeof(uint32_t));
9ee6e8bb
PB		 68 env->cp15.c0_cachetype = 0x1dd20d2;
69 break;
70 case ARM_CPUID_ARM11MPCORE:
71 set_feature(env, ARM_FEATURE_V6);
72 set_feature(env, ARM_FEATURE_V6K);
73 set_feature(env, ARM_FEATURE_VFP);
74 set_feature(env, ARM_FEATURE_AUXCR);
75 env->vfp.xregs[ARM_VFP_FPSID] = 0x410120b4;
76 env->vfp.xregs[ARM_VFP_MVFR0] = 0x11111111;
77 env->vfp.xregs[ARM_VFP_MVFR1] = 0x00000000;
78 memcpy(env->cp15.c0_c1, mpcore_cp15_c0_c1, 8 * sizeof(uint32_t));
22478e79 79 memcpy(env->cp15.c0_c2, mpcore_cp15_c0_c2, 8 * sizeof(uint32_t));
9ee6e8bb
PB		 80 env->cp15.c0_cachetype = 0x1dd20d2;
81 break;
82 case ARM_CPUID_CORTEXA8:
83 set_feature(env, ARM_FEATURE_V6);
84 set_feature(env, ARM_FEATURE_V6K);
85 set_feature(env, ARM_FEATURE_V7);
86 set_feature(env, ARM_FEATURE_AUXCR);
87 set_feature(env, ARM_FEATURE_THUMB2);
88 set_feature(env, ARM_FEATURE_VFP);
89 set_feature(env, ARM_FEATURE_VFP3);
90 set_feature(env, ARM_FEATURE_NEON);
91 env->vfp.xregs[ARM_VFP_FPSID] = 0x410330c0;
92 env->vfp.xregs[ARM_VFP_MVFR0] = 0x11110222;
93 env->vfp.xregs[ARM_VFP_MVFR1] = 0x00011100;
94 memcpy(env->cp15.c0_c1, cortexa8_cp15_c0_c1, 8 * sizeof(uint32_t));
22478e79 95 memcpy(env->cp15.c0_c2, cortexa8_cp15_c0_c2, 8 * sizeof(uint32_t));
9ee6e8bb
PB		 96 env->cp15.c0_cachetype = 0x1dd20d2;
97 break;
98 case ARM_CPUID_CORTEXM3:
99 set_feature(env, ARM_FEATURE_V6);
100 set_feature(env, ARM_FEATURE_THUMB2);
101 set_feature(env, ARM_FEATURE_V7);
102 set_feature(env, ARM_FEATURE_M);
103 set_feature(env, ARM_FEATURE_DIV);
104 break;
105 case ARM_CPUID_ANY: /* For userspace emulation. */
106 set_feature(env, ARM_FEATURE_V6);
107 set_feature(env, ARM_FEATURE_V6K);
108 set_feature(env, ARM_FEATURE_V7);
109 set_feature(env, ARM_FEATURE_THUMB2);
110 set_feature(env, ARM_FEATURE_VFP);
111 set_feature(env, ARM_FEATURE_VFP3);
112 set_feature(env, ARM_FEATURE_NEON);
113 set_feature(env, ARM_FEATURE_DIV);
114 break;
c3d2689d
AZ		 115 case ARM_CPUID_TI915T:
116 case ARM_CPUID_TI925T:
117 set_feature(env, ARM_FEATURE_OMAPCP);
118 env->cp15.c0_cpuid = ARM_CPUID_TI925T; /* Depends on wiring. */
119 env->cp15.c0_cachetype = 0x5109149;
120 env->cp15.c1_sys = 0x00000070;
121 env->cp15.c15_i_max = 0x000;
122 env->cp15.c15_i_min = 0xff0;
123 break;
c1713132
AZ		 124 case ARM_CPUID_PXA250:
125 case ARM_CPUID_PXA255:
126 case ARM_CPUID_PXA260:
127 case ARM_CPUID_PXA261:
128 case ARM_CPUID_PXA262:
129 set_feature(env, ARM_FEATURE_XSCALE);
130 /* JTAG_ID is ((id << 28) | 0x09265013) */
131 env->cp15.c0_cachetype = 0xd172172;
610c3c8a 132 env->cp15.c1_sys = 0x00000078;
c1713132
AZ		 133 break;
134 case ARM_CPUID_PXA270_A0:
135 case ARM_CPUID_PXA270_A1:
136 case ARM_CPUID_PXA270_B0:
137 case ARM_CPUID_PXA270_B1:
138 case ARM_CPUID_PXA270_C0:
139 case ARM_CPUID_PXA270_C5:
140 set_feature(env, ARM_FEATURE_XSCALE);
141 /* JTAG_ID is ((id << 28) | 0x09265013) */
18c9b560
AZ		 142 set_feature(env, ARM_FEATURE_IWMMXT);
143 env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q';
c1713132 144 env->cp15.c0_cachetype = 0xd172172;
610c3c8a 145 env->cp15.c1_sys = 0x00000078;
f3d6b95e
PB		 146 break;
147 default:
148 cpu_abort(env, "Bad CPU ID: %x\n", id);
149 break;
150 }
151}
152
40f137e1
PB		 153void cpu_reset(CPUARMState *env)
154{
f3d6b95e
PB		 155 uint32_t id;
156 id = env->cp15.c0_cpuid;
157 memset(env, 0, offsetof(CPUARMState, breakpoints));
158 if (id)
159 cpu_reset_model_id(env, id);
40f137e1
PB		 160#if defined (CONFIG_USER_ONLY)
161 env->uncached_cpsr = ARM_CPU_MODE_USR;
162 env->vfp.xregs[ARM_VFP_FPEXC] = 1 << 30;
163#else
164 /* SVC mode with interrupts disabled. */
165 env->uncached_cpsr = ARM_CPU_MODE_SVC | CPSR_A | CPSR_F | CPSR_I;
9ee6e8bb
PB		 166 /* On ARMv7-M the CPSR_I is the value of the PRIMASK register, and is
167 clear at reset. */
168 if (IS_M(env))
169 env->uncached_cpsr &= ~CPSR_I;
40f137e1
PB		 170 env->vfp.xregs[ARM_VFP_FPEXC] = 0;
171#endif
172 env->regs[15] = 0;
f3d6b95e 173 tlb_flush(env, 1);
40f137e1
PB		 174}
175
56aebc89
PB		 176static int vfp_gdb_get_reg(CPUState *env, uint8_t *buf, int reg)
177{
178 int nregs;
179
180 /* VFP data registers are always little-endian. */
181 nregs = arm_feature(env, ARM_FEATURE_VFP3) ? 32 : 16;
182 if (reg < nregs) {
183 stfq_le_p(buf, env->vfp.regs[reg]);
184 return 8;
185 }
186 if (arm_feature(env, ARM_FEATURE_NEON)) {
187 /* Aliases for Q regs. */
188 nregs += 16;
189 if (reg < nregs) {
190 stfq_le_p(buf, env->vfp.regs[(reg - 32) * 2]);
191 stfq_le_p(buf + 8, env->vfp.regs[(reg - 32) * 2 + 1]);
192 return 16;
193 }
194 }
195 switch (reg - nregs) {
196 case 0: stl_p(buf, env->vfp.xregs[ARM_VFP_FPSID]); return 4;
197 case 1: stl_p(buf, env->vfp.xregs[ARM_VFP_FPSCR]); return 4;
198 case 2: stl_p(buf, env->vfp.xregs[ARM_VFP_FPEXC]); return 4;
199 }
200 return 0;
201}
202
203static int vfp_gdb_set_reg(CPUState *env, uint8_t *buf, int reg)
204{
205 int nregs;
206
207 nregs = arm_feature(env, ARM_FEATURE_VFP3) ? 32 : 16;
208 if (reg < nregs) {
209 env->vfp.regs[reg] = ldfq_le_p(buf);
210 return 8;
211 }
212 if (arm_feature(env, ARM_FEATURE_NEON)) {
213 nregs += 16;
214 if (reg < nregs) {
215 env->vfp.regs[(reg - 32) * 2] = ldfq_le_p(buf);
216 env->vfp.regs[(reg - 32) * 2 + 1] = ldfq_le_p(buf + 8);
217 return 16;
218 }
219 }
220 switch (reg - nregs) {
221 case 0: env->vfp.xregs[ARM_VFP_FPSID] = ldl_p(buf); return 4;
222 case 1: env->vfp.xregs[ARM_VFP_FPSCR] = ldl_p(buf); return 4;
223 case 2: env->vfp.xregs[ARM_VFP_FPEXC] = ldl_p(buf); return 4;
224 }
225 return 0;
226}
227
aaed909a 228CPUARMState *cpu_arm_init(const char *cpu_model)
40f137e1
PB		 229{
230 CPUARMState *env;
aaed909a 231 uint32_t id;
b26eefb6 232 static int inited = 0;
40f137e1 233
aaed909a
FB		 234 id = cpu_arm_find_by_name(cpu_model);
235 if (id == 0)
236 return NULL;
40f137e1
PB		 237 env = qemu_mallocz(sizeof(CPUARMState));
238 if (!env)
239 return NULL;
240 cpu_exec_init(env);
b26eefb6
PB		 241 if (!inited) {
242 inited = 1;
243 arm_translate_init();
244 }
245
01ba9816 246 env->cpu_model_str = cpu_model;
aaed909a 247 env->cp15.c0_cpuid = id;
40f137e1 248 cpu_reset(env);
56aebc89
PB		 249 if (arm_feature(env, ARM_FEATURE_NEON)) {
250 gdb_register_coprocessor(env, vfp_gdb_get_reg, vfp_gdb_set_reg,
251 51, "arm-neon.xml", 0);
252 } else if (arm_feature(env, ARM_FEATURE_VFP3)) {
253 gdb_register_coprocessor(env, vfp_gdb_get_reg, vfp_gdb_set_reg,
254 35, "arm-vfp3.xml", 0);
255 } else if (arm_feature(env, ARM_FEATURE_VFP)) {
256 gdb_register_coprocessor(env, vfp_gdb_get_reg, vfp_gdb_set_reg,
257 19, "arm-vfp.xml", 0);
258 }
40f137e1
PB		 259 return env;
260}
261
3371d272
PB		 262struct arm_cpu_t {
263 uint32_t id;
264 const char *name;
265};
266
267static const struct arm_cpu_t arm_cpu_names[] = {
268 { ARM_CPUID_ARM926, "arm926"},
ce819861 269 { ARM_CPUID_ARM946, "arm946"},
3371d272 270 { ARM_CPUID_ARM1026, "arm1026"},
9ee6e8bb 271 { ARM_CPUID_ARM1136, "arm1136"},
827df9f3 272 { ARM_CPUID_ARM1136_R2, "arm1136-r2"},
9ee6e8bb
PB		 273 { ARM_CPUID_ARM11MPCORE, "arm11mpcore"},
274 { ARM_CPUID_CORTEXM3, "cortex-m3"},
275 { ARM_CPUID_CORTEXA8, "cortex-a8"},
c3d2689d 276 { ARM_CPUID_TI925T, "ti925t" },
c1713132
AZ		 277 { ARM_CPUID_PXA250, "pxa250" },
278 { ARM_CPUID_PXA255, "pxa255" },
279 { ARM_CPUID_PXA260, "pxa260" },
280 { ARM_CPUID_PXA261, "pxa261" },
281 { ARM_CPUID_PXA262, "pxa262" },
282 { ARM_CPUID_PXA270, "pxa270" },
283 { ARM_CPUID_PXA270_A0, "pxa270-a0" },
284 { ARM_CPUID_PXA270_A1, "pxa270-a1" },
285 { ARM_CPUID_PXA270_B0, "pxa270-b0" },
286 { ARM_CPUID_PXA270_B1, "pxa270-b1" },
287 { ARM_CPUID_PXA270_C0, "pxa270-c0" },
288 { ARM_CPUID_PXA270_C5, "pxa270-c5" },
9ee6e8bb 289 { ARM_CPUID_ANY, "any"},
3371d272
PB		 290 { 0, NULL}
291};
292
c732abe2 293void arm_cpu_list(FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...))
5adb4839
PB		 294{
295 int i;
296
c732abe2 297 (*cpu_fprintf)(f, "Available CPUs:\n");
5adb4839 298 for (i = 0; arm_cpu_names[i].name; i++) {
c732abe2 299 (*cpu_fprintf)(f, " %s\n", arm_cpu_names[i].name);
5adb4839
PB		 300 }
301}
302
aaed909a
FB		 303/* return 0 if not found */
304static uint32_t cpu_arm_find_by_name(const char *name)
40f137e1 305{
3371d272
PB		 306 int i;
307 uint32_t id;
308
309 id = 0;
3371d272
PB		 310 for (i = 0; arm_cpu_names[i].name; i++) {
311 if (strcmp(name, arm_cpu_names[i].name) == 0) {
312 id = arm_cpu_names[i].id;
313 break;
314 }
315 }
aaed909a 316 return id;
40f137e1
PB		 317}
318
319void cpu_arm_close(CPUARMState *env)
320{
321 free(env);
322}
323
2f4a40e5
AZ		 324uint32_t cpsr_read(CPUARMState *env)
325{
326 int ZF;
6fbe23d5
PB		 327 ZF = (env->ZF == 0);
328 return env->uncached_cpsr | (env->NF & 0x80000000) | (ZF << 30) |
2f4a40e5
AZ		 329 (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27)
330 | (env->thumb << 5) | ((env->condexec_bits & 3) << 25)
331 | ((env->condexec_bits & 0xfc) << 8)
332 | (env->GE << 16);
333}
334
335void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask)
336{
2f4a40e5 337 if (mask & CPSR_NZCV) {
6fbe23d5
PB		 338 env->ZF = (~val) & CPSR_Z;
339 env->NF = val;
2f4a40e5
AZ		 340 env->CF = (val >> 29) & 1;
341 env->VF = (val << 3) & 0x80000000;
342 }
343 if (mask & CPSR_Q)
344 env->QF = ((val & CPSR_Q) != 0);
345 if (mask & CPSR_T)
346 env->thumb = ((val & CPSR_T) != 0);
347 if (mask & CPSR_IT_0_1) {
348 env->condexec_bits &= ~3;
349 env->condexec_bits |= (val >> 25) & 3;
350 }
351 if (mask & CPSR_IT_2_7) {
352 env->condexec_bits &= 3;
353 env->condexec_bits |= (val >> 8) & 0xfc;
354 }
355 if (mask & CPSR_GE) {
356 env->GE = (val >> 16) & 0xf;
357 }
358
359 if ((env->uncached_cpsr ^ val) & mask & CPSR_M) {
360 switch_mode(env, val & CPSR_M);
361 }
362 mask &= ~CACHED_CPSR_BITS;
363 env->uncached_cpsr = (env->uncached_cpsr & ~mask) | (val & mask);
364}
365
b26eefb6
PB		 366/* Sign/zero extend */
367uint32_t HELPER(sxtb16)(uint32_t x)
368{
369 uint32_t res;
370 res = (uint16_t)(int8_t)x;
371 res |= (uint32_t)(int8_t)(x >> 16) << 16;
372 return res;
373}
374
375uint32_t HELPER(uxtb16)(uint32_t x)
376{
377 uint32_t res;
378 res = (uint16_t)(uint8_t)x;
379 res |= (uint32_t)(uint8_t)(x >> 16) << 16;
380 return res;
381}
382
f51bbbfe
PB		 383uint32_t HELPER(clz)(uint32_t x)
384{
385 int count;
386 for (count = 32; x; count--)
387 x >>= 1;
388 return count;
389}
390
3670669c
PB		 391int32_t HELPER(sdiv)(int32_t num, int32_t den)
392{
393 if (den == 0)
394 return 0;
395 return num / den;
396}
397
398uint32_t HELPER(udiv)(uint32_t num, uint32_t den)
399{
400 if (den == 0)
401 return 0;
402 return num / den;
403}
404
405uint32_t HELPER(rbit)(uint32_t x)
406{
407 x = ((x & 0xff000000) >> 24)
408 | ((x & 0x00ff0000) >> 8)
409 | ((x & 0x0000ff00) << 8)
410 | ((x & 0x000000ff) << 24);
411 x = ((x & 0xf0f0f0f0) >> 4)
412 | ((x & 0x0f0f0f0f) << 4);
413 x = ((x & 0x88888888) >> 3)
414 | ((x & 0x44444444) >> 1)
415 | ((x & 0x22222222) << 1)
416 | ((x & 0x11111111) << 3);
417 return x;
418}
419
ad69471c
PB		 420uint32_t HELPER(abs)(uint32_t x)
421{
422 return ((int32_t)x < 0) ? -x : x;
423}
424
5fafdf24 425#if defined(CONFIG_USER_ONLY)
b5ff1b31
FB		 426
427void do_interrupt (CPUState *env)
428{
429 env->exception_index = -1;
430}
431
9ee6e8bb
PB		 432/* Structure used to record exclusive memory locations. */
433typedef struct mmon_state {
434 struct mmon_state *next;
435 CPUARMState *cpu_env;
436 uint32_t addr;
437} mmon_state;
438
439/* Chain of current locks. */
440static mmon_state* mmon_head = NULL;
441
b5ff1b31 442int cpu_arm_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
6ebbf390 443 int mmu_idx, int is_softmmu)
b5ff1b31
FB		 444{
445 if (rw == 2) {
446 env->exception_index = EXCP_PREFETCH_ABORT;
447 env->cp15.c6_insn = address;
448 } else {
449 env->exception_index = EXCP_DATA_ABORT;
450 env->cp15.c6_data = address;
451 }
452 return 1;
453}
454
9ee6e8bb
PB		 455static void allocate_mmon_state(CPUState *env)
456{
457 env->mmon_entry = malloc(sizeof (mmon_state));
458 if (!env->mmon_entry)
459 abort();
460 memset (env->mmon_entry, 0, sizeof (mmon_state));
461 env->mmon_entry->cpu_env = env;
462 mmon_head = env->mmon_entry;
463}
464
465/* Flush any monitor locks for the specified address. */
466static void flush_mmon(uint32_t addr)
467{
468 mmon_state *mon;
469
470 for (mon = mmon_head; mon; mon = mon->next)
471 {
472 if (mon->addr != addr)
473 continue;
474
475 mon->addr = 0;
476 break;
477 }
478}
479
480/* Mark an address for exclusive access. */
8f8e3aa4 481void HELPER(mark_exclusive)(CPUState *env, uint32_t addr)
9ee6e8bb
PB		 482{
483 if (!env->mmon_entry)
484 allocate_mmon_state(env);
485 /* Clear any previous locks. */
486 flush_mmon(addr);
487 env->mmon_entry->addr = addr;
488}
489
490/* Test if an exclusive address is still exclusive. Returns zero
491 if the address is still exclusive. */
8f8e3aa4 492uint32_t HELPER(test_exclusive)(CPUState *env, uint32_t addr)
9ee6e8bb
PB		 493{
494 int res;
495
496 if (!env->mmon_entry)
497 return 1;
498 if (env->mmon_entry->addr == addr)
499 res = 0;
500 else
501 res = 1;
502 flush_mmon(addr);
503 return res;
504}
505
8f8e3aa4 506void HELPER(clrex)(CPUState *env)
9ee6e8bb
PB		 507{
508 if (!(env->mmon_entry && env->mmon_entry->addr))
509 return;
510 flush_mmon(env->mmon_entry->addr);
511}
512
9b3c35e0 513target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
b5ff1b31
FB		 514{
515 return addr;
516}
517
518/* These should probably raise undefined insn exceptions. */
8984bd2e 519void HELPER(set_cp)(CPUState *env, uint32_t insn, uint32_t val)
c1713132
AZ		 520{
521 int op1 = (insn >> 8) & 0xf;
522 cpu_abort(env, "cp%i insn %08x\n", op1, insn);
523 return;
524}
525
8984bd2e 526uint32_t HELPER(get_cp)(CPUState *env, uint32_t insn)
c1713132
AZ		 527{
528 int op1 = (insn >> 8) & 0xf;
529 cpu_abort(env, "cp%i insn %08x\n", op1, insn);
530 return 0;
531}
532
8984bd2e 533void HELPER(set_cp15)(CPUState *env, uint32_t insn, uint32_t val)
b5ff1b31
FB		 534{
535 cpu_abort(env, "cp15 insn %08x\n", insn);
536}
537
8984bd2e 538uint32_t HELPER(get_cp15)(CPUState *env, uint32_t insn)
b5ff1b31
FB		 539{
540 cpu_abort(env, "cp15 insn %08x\n", insn);
541 return 0;
542}
543
9ee6e8bb 544/* These should probably raise undefined insn exceptions. */
8984bd2e 545void HELPER(v7m_msr)(CPUState *env, uint32_t reg, uint32_t val)
9ee6e8bb
PB		 546{
547 cpu_abort(env, "v7m_mrs %d\n", reg);
548}
549
8984bd2e 550uint32_t HELPER(v7m_mrs)(CPUState *env, uint32_t reg)
9ee6e8bb
PB		 551{
552 cpu_abort(env, "v7m_mrs %d\n", reg);
553 return 0;
554}
555
b5ff1b31
FB		 556void switch_mode(CPUState *env, int mode)
557{
558 if (mode != ARM_CPU_MODE_USR)
559 cpu_abort(env, "Tried to switch out of user mode\n");
560}
561
b0109805 562void HELPER(set_r13_banked)(CPUState *env, uint32_t mode, uint32_t val)
9ee6e8bb
PB		 563{
564 cpu_abort(env, "banked r13 write\n");
565}
566
b0109805 567uint32_t HELPER(get_r13_banked)(CPUState *env, uint32_t mode)
9ee6e8bb
PB		 568{
569 cpu_abort(env, "banked r13 read\n");
570 return 0;
571}
572
b5ff1b31
FB		 573#else
574
8e71621f
PB		 575extern int semihosting_enabled;
576
b5ff1b31
FB		 577/* Map CPU modes onto saved register banks. */
578static inline int bank_number (int mode)
579{
580 switch (mode) {
581 case ARM_CPU_MODE_USR:
582 case ARM_CPU_MODE_SYS:
583 return 0;
584 case ARM_CPU_MODE_SVC:
585 return 1;
586 case ARM_CPU_MODE_ABT:
587 return 2;
588 case ARM_CPU_MODE_UND:
589 return 3;
590 case ARM_CPU_MODE_IRQ:
591 return 4;
592 case ARM_CPU_MODE_FIQ:
593 return 5;
594 }
595 cpu_abort(cpu_single_env, "Bad mode %x\n", mode);
596 return -1;
597}
598
599void switch_mode(CPUState *env, int mode)
600{
601 int old_mode;
602 int i;
603
604 old_mode = env->uncached_cpsr & CPSR_M;
605 if (mode == old_mode)
606 return;
607
608 if (old_mode == ARM_CPU_MODE_FIQ) {
609 memcpy (env->fiq_regs, env->regs + 8, 5 * sizeof(uint32_t));
8637c67f 610 memcpy (env->regs + 8, env->usr_regs, 5 * sizeof(uint32_t));
b5ff1b31
FB		 611 } else if (mode == ARM_CPU_MODE_FIQ) {
612 memcpy (env->usr_regs, env->regs + 8, 5 * sizeof(uint32_t));
8637c67f 613 memcpy (env->regs + 8, env->fiq_regs, 5 * sizeof(uint32_t));
b5ff1b31
FB		 614 }
615
616 i = bank_number(old_mode);
617 env->banked_r13[i] = env->regs[13];
618 env->banked_r14[i] = env->regs[14];
619 env->banked_spsr[i] = env->spsr;
620
621 i = bank_number(mode);
622 env->regs[13] = env->banked_r13[i];
623 env->regs[14] = env->banked_r14[i];
624 env->spsr = env->banked_spsr[i];
625}
626
9ee6e8bb
PB		 627static void v7m_push(CPUARMState *env, uint32_t val)
628{
629 env->regs[13] -= 4;
630 stl_phys(env->regs[13], val);
631}
632
633static uint32_t v7m_pop(CPUARMState *env)
634{
635 uint32_t val;
636 val = ldl_phys(env->regs[13]);
637 env->regs[13] += 4;
638 return val;
639}
640
641/* Switch to V7M main or process stack pointer. */
642static void switch_v7m_sp(CPUARMState *env, int process)
643{
644 uint32_t tmp;
645 if (env->v7m.current_sp != process) {
646 tmp = env->v7m.other_sp;
647 env->v7m.other_sp = env->regs[13];
648 env->regs[13] = tmp;
649 env->v7m.current_sp = process;
650 }
651}
652
653static void do_v7m_exception_exit(CPUARMState *env)
654{
655 uint32_t type;
656 uint32_t xpsr;
657
658 type = env->regs[15];
659 if (env->v7m.exception != 0)
660 armv7m_nvic_complete_irq(env->v7m.nvic, env->v7m.exception);
661
662 /* Switch to the target stack. */
663 switch_v7m_sp(env, (type & 4) != 0);
664 /* Pop registers. */
665 env->regs[0] = v7m_pop(env);
666 env->regs[1] = v7m_pop(env);
667 env->regs[2] = v7m_pop(env);
668 env->regs[3] = v7m_pop(env);
669 env->regs[12] = v7m_pop(env);
670 env->regs[14] = v7m_pop(env);
671 env->regs[15] = v7m_pop(env);
672 xpsr = v7m_pop(env);
673 xpsr_write(env, xpsr, 0xfffffdff);
674 /* Undo stack alignment. */
675 if (xpsr & 0x200)
676 env->regs[13] |= 4;
677 /* ??? The exception return type specifies Thread/Handler mode. However
678 this is also implied by the xPSR value. Not sure what to do
679 if there is a mismatch. */
680 /* ??? Likewise for mismatches between the CONTROL register and the stack
681 pointer. */
682}
683
684void do_interrupt_v7m(CPUARMState *env)
685{
686 uint32_t xpsr = xpsr_read(env);
687 uint32_t lr;
688 uint32_t addr;
689
690 lr = 0xfffffff1;
691 if (env->v7m.current_sp)
692 lr |= 4;
693 if (env->v7m.exception == 0)
694 lr |= 8;
695
696 /* For exceptions we just mark as pending on the NVIC, and let that
697 handle it. */
698 /* TODO: Need to escalate if the current priority is higher than the
699 one we're raising. */
700 switch (env->exception_index) {
701 case EXCP_UDEF:
702 armv7m_nvic_set_pending(env->v7m.nvic, ARMV7M_EXCP_USAGE);
703 return;
704 case EXCP_SWI:
705 env->regs[15] += 2;
706 armv7m_nvic_set_pending(env->v7m.nvic, ARMV7M_EXCP_SVC);
707 return;
708 case EXCP_PREFETCH_ABORT:
709 case EXCP_DATA_ABORT:
710 armv7m_nvic_set_pending(env->v7m.nvic, ARMV7M_EXCP_MEM);
711 return;
712 case EXCP_BKPT:
2ad207d4
PB		 713 if (semihosting_enabled) {
714 int nr;
715 nr = lduw_code(env->regs[15]) & 0xff;
716 if (nr == 0xab) {
717 env->regs[15] += 2;
718 env->regs[0] = do_arm_semihosting(env);
719 return;
720 }
721 }
9ee6e8bb
PB		 722 armv7m_nvic_set_pending(env->v7m.nvic, ARMV7M_EXCP_DEBUG);
723 return;
724 case EXCP_IRQ:
725 env->v7m.exception = armv7m_nvic_acknowledge_irq(env->v7m.nvic);
726 break;
727 case EXCP_EXCEPTION_EXIT:
728 do_v7m_exception_exit(env);
729 return;
730 default:
731 cpu_abort(env, "Unhandled exception 0x%x\n", env->exception_index);
732 return; /* Never happens. Keep compiler happy. */
733 }
734
735 /* Align stack pointer. */
736 /* ??? Should only do this if Configuration Control Register
737 STACKALIGN bit is set. */
738 if (env->regs[13] & 4) {
ab19b0ec 739 env->regs[13] -= 4;
9ee6e8bb
PB		 740 xpsr |= 0x200;
741 }
6c95676b 742 /* Switch to the handler mode. */
9ee6e8bb
PB		 743 v7m_push(env, xpsr);
744 v7m_push(env, env->regs[15]);
745 v7m_push(env, env->regs[14]);
746 v7m_push(env, env->regs[12]);
747 v7m_push(env, env->regs[3]);
748 v7m_push(env, env->regs[2]);
749 v7m_push(env, env->regs[1]);
750 v7m_push(env, env->regs[0]);
751 switch_v7m_sp(env, 0);
752 env->uncached_cpsr &= ~CPSR_IT;
753 env->regs[14] = lr;
754 addr = ldl_phys(env->v7m.vecbase + env->v7m.exception * 4);
755 env->regs[15] = addr & 0xfffffffe;
756 env->thumb = addr & 1;
757}
758
b5ff1b31
FB		 759/* Handle a CPU exception. */
760void do_interrupt(CPUARMState *env)
761{
762 uint32_t addr;
763 uint32_t mask;
764 int new_mode;
765 uint32_t offset;
766
9ee6e8bb
PB		 767 if (IS_M(env)) {
768 do_interrupt_v7m(env);
769 return;
770 }
b5ff1b31
FB		 771 /* TODO: Vectored interrupt controller. */
772 switch (env->exception_index) {
773 case EXCP_UDEF:
774 new_mode = ARM_CPU_MODE_UND;
775 addr = 0x04;
776 mask = CPSR_I;
777 if (env->thumb)
778 offset = 2;
779 else
780 offset = 4;
781 break;
782 case EXCP_SWI:
8e71621f
PB		 783 if (semihosting_enabled) {
784 /* Check for semihosting interrupt. */
785 if (env->thumb) {
786 mask = lduw_code(env->regs[15] - 2) & 0xff;
787 } else {
788 mask = ldl_code(env->regs[15] - 4) & 0xffffff;
789 }
790 /* Only intercept calls from privileged modes, to provide some
791 semblance of security. */
792 if (((mask == 0x123456 && !env->thumb)
793 || (mask == 0xab && env->thumb))
794 && (env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR) {
795 env->regs[0] = do_arm_semihosting(env);
796 return;
797 }
798 }
b5ff1b31
FB		 799 new_mode = ARM_CPU_MODE_SVC;
800 addr = 0x08;
801 mask = CPSR_I;
601d70b9 802 /* The PC already points to the next instruction. */
b5ff1b31
FB		 803 offset = 0;
804 break;
06c949e6 805 case EXCP_BKPT:
9ee6e8bb 806 /* See if this is a semihosting syscall. */
2ad207d4 807 if (env->thumb && semihosting_enabled) {
9ee6e8bb
PB		 808 mask = lduw_code(env->regs[15]) & 0xff;
809 if (mask == 0xab
810 && (env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR) {
811 env->regs[15] += 2;
812 env->regs[0] = do_arm_semihosting(env);
813 return;
814 }
815 }
816 /* Fall through to prefetch abort. */
817 case EXCP_PREFETCH_ABORT:
b5ff1b31
FB		 818 new_mode = ARM_CPU_MODE_ABT;
819 addr = 0x0c;
820 mask = CPSR_A | CPSR_I;
821 offset = 4;
822 break;
823 case EXCP_DATA_ABORT:
824 new_mode = ARM_CPU_MODE_ABT;
825 addr = 0x10;
826 mask = CPSR_A | CPSR_I;
827 offset = 8;
828 break;
829 case EXCP_IRQ:
830 new_mode = ARM_CPU_MODE_IRQ;
831 addr = 0x18;
832 /* Disable IRQ and imprecise data aborts. */
833 mask = CPSR_A | CPSR_I;
834 offset = 4;
835 break;
836 case EXCP_FIQ:
837 new_mode = ARM_CPU_MODE_FIQ;
838 addr = 0x1c;
839 /* Disable FIQ, IRQ and imprecise data aborts. */
840 mask = CPSR_A | CPSR_I | CPSR_F;
841 offset = 4;
842 break;
843 default:
844 cpu_abort(env, "Unhandled exception 0x%x\n", env->exception_index);
845 return; /* Never happens. Keep compiler happy. */
846 }
847 /* High vectors. */
848 if (env->cp15.c1_sys & (1 << 13)) {
849 addr += 0xffff0000;
850 }
851 switch_mode (env, new_mode);
852 env->spsr = cpsr_read(env);
9ee6e8bb
PB		 853 /* Clear IT bits. */
854 env->condexec_bits = 0;
6d7e6326 855 /* Switch to the new mode, and switch to Arm mode. */
b5ff1b31 856 /* ??? Thumb interrupt handlers not implemented. */
6d7e6326 857 env->uncached_cpsr = (env->uncached_cpsr & ~CPSR_M) | new_mode;
b5ff1b31 858 env->uncached_cpsr |= mask;
6d7e6326 859 env->thumb = 0;
b5ff1b31
FB		 860 env->regs[14] = env->regs[15] + offset;
861 env->regs[15] = addr;
862 env->interrupt_request |= CPU_INTERRUPT_EXITTB;
863}
864
865/* Check section/page access permissions.
866 Returns the page protection flags, or zero if the access is not
867 permitted. */
868static inline int check_ap(CPUState *env, int ap, int domain, int access_type,
869 int is_user)
870{
9ee6e8bb
PB		 871 int prot_ro;
872
b5ff1b31
FB		 873 if (domain == 3)
874 return PAGE_READ | PAGE_WRITE;
875
9ee6e8bb
PB		 876 if (access_type == 1)
877 prot_ro = 0;
878 else
879 prot_ro = PAGE_READ;
880
b5ff1b31
FB		 881 switch (ap) {
882 case 0:
78600320 883 if (access_type == 1)
b5ff1b31
FB		 884 return 0;
885 switch ((env->cp15.c1_sys >> 8) & 3) {
886 case 1:
887 return is_user ? 0 : PAGE_READ;
888 case 2:
889 return PAGE_READ;
890 default:
891 return 0;
892 }
893 case 1:
894 return is_user ? 0 : PAGE_READ | PAGE_WRITE;
895 case 2:
896 if (is_user)
9ee6e8bb 897 return prot_ro;
b5ff1b31
FB		 898 else
899 return PAGE_READ | PAGE_WRITE;
900 case 3:
901 return PAGE_READ | PAGE_WRITE;
9ee6e8bb
PB		 902 case 4: case 7: /* Reserved. */
903 return 0;
904 case 5:
905 return is_user ? 0 : prot_ro;
906 case 6:
907 return prot_ro;
b5ff1b31
FB		 908 default:
909 abort();
910 }
911}
912
9ee6e8bb
PB		 913static int get_phys_addr_v5(CPUState *env, uint32_t address, int access_type,
914 int is_user, uint32_t *phys_ptr, int *prot)
b5ff1b31
FB		 915{
916 int code;
917 uint32_t table;
918 uint32_t desc;
919 int type;
920 int ap;
921 int domain;
922 uint32_t phys_addr;
923
9ee6e8bb
PB		 924 /* Pagetable walk. */
925 /* Lookup l1 descriptor. */
926 if (address & env->cp15.c2_mask)
927 table = env->cp15.c2_base1;
928 else
929 table = env->cp15.c2_base0;
930 table = (table & 0xffffc000) | ((address >> 18) & 0x3ffc);
931 desc = ldl_phys(table);
932 type = (desc & 3);
933 domain = (env->cp15.c3 >> ((desc >> 4) & 0x1e)) & 3;
934 if (type == 0) {
601d70b9 935 /* Section translation fault. */
9ee6e8bb
PB		 936 code = 5;
937 goto do_fault;
938 }
939 if (domain == 0 || domain == 2) {
940 if (type == 2)
941 code = 9; /* Section domain fault. */
942 else
943 code = 11; /* Page domain fault. */
944 goto do_fault;
945 }
946 if (type == 2) {
947 /* 1Mb section. */
948 phys_addr = (desc & 0xfff00000) | (address & 0x000fffff);
949 ap = (desc >> 10) & 3;
950 code = 13;
951 } else {
952 /* Lookup l2 entry. */
953 if (type == 1) {
954 /* Coarse pagetable. */
955 table = (desc & 0xfffffc00) | ((address >> 10) & 0x3fc);
956 } else {
957 /* Fine pagetable. */
958 table = (desc & 0xfffff000) | ((address >> 8) & 0xffc);
959 }
960 desc = ldl_phys(table);
961 switch (desc & 3) {
962 case 0: /* Page translation fault. */
963 code = 7;
964 goto do_fault;
965 case 1: /* 64k page. */
966 phys_addr = (desc & 0xffff0000) | (address & 0xffff);
967 ap = (desc >> (4 + ((address >> 13) & 6))) & 3;
ce819861 968 break;
9ee6e8bb
PB		 969 case 2: /* 4k page. */
970 phys_addr = (desc & 0xfffff000) | (address & 0xfff);
971 ap = (desc >> (4 + ((address >> 13) & 6))) & 3;
ce819861 972 break;
9ee6e8bb
PB		 973 case 3: /* 1k page. */
974 if (type == 1) {
975 if (arm_feature(env, ARM_FEATURE_XSCALE)) {
976 phys_addr = (desc & 0xfffff000) | (address & 0xfff);
977 } else {
978 /* Page translation fault. */
979 code = 7;
980 goto do_fault;
981 }
982 } else {
983 phys_addr = (desc & 0xfffffc00) | (address & 0x3ff);
984 }
985 ap = (desc >> 4) & 3;
ce819861
PB		 986 break;
987 default:
9ee6e8bb
PB		 988 /* Never happens, but compiler isn't smart enough to tell. */
989 abort();
ce819861 990 }
9ee6e8bb
PB		 991 code = 15;
992 }
993 *prot = check_ap(env, ap, domain, access_type, is_user);
994 if (!*prot) {
995 /* Access permission fault. */
996 goto do_fault;
997 }
998 *phys_ptr = phys_addr;
999 return 0;
1000do_fault:
1001 return code | (domain << 4);
1002}
1003
1004static int get_phys_addr_v6(CPUState *env, uint32_t address, int access_type,
1005 int is_user, uint32_t *phys_ptr, int *prot)
1006{
1007 int code;
1008 uint32_t table;
1009 uint32_t desc;
1010 uint32_t xn;
1011 int type;
1012 int ap;
1013 int domain;
1014 uint32_t phys_addr;
1015
1016 /* Pagetable walk. */
1017 /* Lookup l1 descriptor. */
1018 if (address & env->cp15.c2_mask)
1019 table = env->cp15.c2_base1;
1020 else
1021 table = env->cp15.c2_base0;
1022 table = (table & 0xffffc000) | ((address >> 18) & 0x3ffc);
1023 desc = ldl_phys(table);
1024 type = (desc & 3);
1025 if (type == 0) {
601d70b9 1026 /* Section translation fault. */
9ee6e8bb
PB		 1027 code = 5;
1028 domain = 0;
1029 goto do_fault;
1030 } else if (type == 2 && (desc & (1 << 18))) {
1031 /* Supersection. */
1032 domain = 0;
b5ff1b31 1033 } else {
9ee6e8bb
PB		 1034 /* Section or page. */
1035 domain = (desc >> 4) & 0x1e;
1036 }
1037 domain = (env->cp15.c3 >> domain) & 3;
1038 if (domain == 0 || domain == 2) {
1039 if (type == 2)
1040 code = 9; /* Section domain fault. */
1041 else
1042 code = 11; /* Page domain fault. */
1043 goto do_fault;
1044 }
1045 if (type == 2) {
1046 if (desc & (1 << 18)) {
1047 /* Supersection. */
1048 phys_addr = (desc & 0xff000000) | (address & 0x00ffffff);
b5ff1b31 1049 } else {
9ee6e8bb
PB		 1050 /* Section. */
1051 phys_addr = (desc & 0xfff00000) | (address & 0x000fffff);
b5ff1b31 1052 }
9ee6e8bb
PB		 1053 ap = ((desc >> 10) & 3) | ((desc >> 13) & 4);
1054 xn = desc & (1 << 4);
1055 code = 13;
1056 } else {
1057 /* Lookup l2 entry. */
1058 table = (desc & 0xfffffc00) | ((address >> 10) & 0x3fc);
1059 desc = ldl_phys(table);
1060 ap = ((desc >> 4) & 3) | ((desc >> 7) & 4);
1061 switch (desc & 3) {
1062 case 0: /* Page translation fault. */
1063 code = 7;
b5ff1b31 1064 goto do_fault;
9ee6e8bb
PB		 1065 case 1: /* 64k page. */
1066 phys_addr = (desc & 0xffff0000) | (address & 0xffff);
1067 xn = desc & (1 << 15);
1068 break;
1069 case 2: case 3: /* 4k page. */
1070 phys_addr = (desc & 0xfffff000) | (address & 0xfff);
1071 xn = desc & 1;
1072 break;
1073 default:
1074 /* Never happens, but compiler isn't smart enough to tell. */
1075 abort();
b5ff1b31 1076 }
9ee6e8bb
PB		 1077 code = 15;
1078 }
1079 if (xn && access_type == 2)
1080 goto do_fault;
1081
1082 *prot = check_ap(env, ap, domain, access_type, is_user);
1083 if (!*prot) {
1084 /* Access permission fault. */
1085 goto do_fault;
b5ff1b31 1086 }
9ee6e8bb 1087 *phys_ptr = phys_addr;
b5ff1b31
FB		 1088 return 0;
1089do_fault:
1090 return code | (domain << 4);
1091}
1092
9ee6e8bb
PB		 1093static int get_phys_addr_mpu(CPUState *env, uint32_t address, int access_type,
1094 int is_user, uint32_t *phys_ptr, int *prot)
1095{
1096 int n;
1097 uint32_t mask;
1098 uint32_t base;
1099
1100 *phys_ptr = address;
1101 for (n = 7; n >= 0; n--) {
1102 base = env->cp15.c6_region[n];
1103 if ((base & 1) == 0)
1104 continue;
1105 mask = 1 << ((base >> 1) & 0x1f);
1106 /* Keep this shift separate from the above to avoid an
1107 (undefined) << 32. */
1108 mask = (mask << 1) - 1;
1109 if (((base ^ address) & ~mask) == 0)
1110 break;
1111 }
1112 if (n < 0)
1113 return 2;
1114
1115 if (access_type == 2) {
1116 mask = env->cp15.c5_insn;
1117 } else {
1118 mask = env->cp15.c5_data;
1119 }
1120 mask = (mask >> (n * 4)) & 0xf;
1121 switch (mask) {
1122 case 0:
1123 return 1;
1124 case 1:
1125 if (is_user)
1126 return 1;
1127 *prot = PAGE_READ | PAGE_WRITE;
1128 break;
1129 case 2:
1130 *prot = PAGE_READ;
1131 if (!is_user)
1132 *prot |= PAGE_WRITE;
1133 break;
1134 case 3:
1135 *prot = PAGE_READ | PAGE_WRITE;
1136 break;
1137 case 5:
1138 if (is_user)
1139 return 1;
1140 *prot = PAGE_READ;
1141 break;
1142 case 6:
1143 *prot = PAGE_READ;
1144 break;
1145 default:
1146 /* Bad permission. */
1147 return 1;
1148 }
1149 return 0;
1150}
1151
1152static inline int get_phys_addr(CPUState *env, uint32_t address,
1153 int access_type, int is_user,
1154 uint32_t *phys_ptr, int *prot)
1155{
1156 /* Fast Context Switch Extension. */
1157 if (address < 0x02000000)
1158 address += env->cp15.c13_fcse;
1159
1160 if ((env->cp15.c1_sys & 1) == 0) {
1161 /* MMU/MPU disabled. */
1162 *phys_ptr = address;
1163 *prot = PAGE_READ | PAGE_WRITE;
1164 return 0;
1165 } else if (arm_feature(env, ARM_FEATURE_MPU)) {
1166 return get_phys_addr_mpu(env, address, access_type, is_user, phys_ptr,
1167 prot);
1168 } else if (env->cp15.c1_sys & (1 << 23)) {
1169 return get_phys_addr_v6(env, address, access_type, is_user, phys_ptr,
1170 prot);
1171 } else {
1172 return get_phys_addr_v5(env, address, access_type, is_user, phys_ptr,
1173 prot);
1174 }
1175}
1176
b5ff1b31 1177int cpu_arm_handle_mmu_fault (CPUState *env, target_ulong address,
6ebbf390 1178 int access_type, int mmu_idx, int is_softmmu)
b5ff1b31
FB		 1179{
1180 uint32_t phys_addr;
1181 int prot;
6ebbf390 1182 int ret, is_user;
b5ff1b31 1183
6ebbf390 1184 is_user = mmu_idx == MMU_USER_IDX;
b5ff1b31
FB		 1185 ret = get_phys_addr(env, address, access_type, is_user, &phys_addr, &prot);
1186 if (ret == 0) {
1187 /* Map a single [sub]page. */
1188 phys_addr &= ~(uint32_t)0x3ff;
1189 address &= ~(uint32_t)0x3ff;
6ebbf390 1190 return tlb_set_page (env, address, phys_addr, prot, mmu_idx,
b5ff1b31
FB		 1191 is_softmmu);
1192 }
1193
1194 if (access_type == 2) {
1195 env->cp15.c5_insn = ret;
1196 env->cp15.c6_insn = address;
1197 env->exception_index = EXCP_PREFETCH_ABORT;
1198 } else {
1199 env->cp15.c5_data = ret;
9ee6e8bb
PB		 1200 if (access_type == 1 && arm_feature(env, ARM_FEATURE_V6))
1201 env->cp15.c5_data |= (1 << 11);
b5ff1b31
FB		 1202 env->cp15.c6_data = address;
1203 env->exception_index = EXCP_DATA_ABORT;
1204 }
1205 return 1;
1206}
1207
9b3c35e0 1208target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
b5ff1b31
FB		 1209{
1210 uint32_t phys_addr;
1211 int prot;
1212 int ret;
1213
1214 ret = get_phys_addr(env, addr, 0, 0, &phys_addr, &prot);
1215
1216 if (ret != 0)
1217 return -1;
1218
1219 return phys_addr;
1220}
1221
9ee6e8bb
PB		 1222/* Not really implemented. Need to figure out a sane way of doing this.
1223 Maybe add generic watchpoint support and use that. */
1224
8f8e3aa4 1225void HELPER(mark_exclusive)(CPUState *env, uint32_t addr)
9ee6e8bb
PB		 1226{
1227 env->mmon_addr = addr;
1228}
1229
8f8e3aa4 1230uint32_t HELPER(test_exclusive)(CPUState *env, uint32_t addr)
9ee6e8bb
PB		 1231{
1232 return (env->mmon_addr != addr);
1233}
1234
8f8e3aa4 1235void HELPER(clrex)(CPUState *env)
9ee6e8bb
PB		 1236{
1237 env->mmon_addr = -1;
1238}
1239
8984bd2e 1240void HELPER(set_cp)(CPUState *env, uint32_t insn, uint32_t val)
c1713132
AZ		 1241{
1242 int cp_num = (insn >> 8) & 0xf;
1243 int cp_info = (insn >> 5) & 7;
1244 int src = (insn >> 16) & 0xf;
1245 int operand = insn & 0xf;
1246
1247 if (env->cp[cp_num].cp_write)
1248 env->cp[cp_num].cp_write(env->cp[cp_num].opaque,
1249 cp_info, src, operand, val);
1250}
1251
8984bd2e 1252uint32_t HELPER(get_cp)(CPUState *env, uint32_t insn)
c1713132
AZ		 1253{
1254 int cp_num = (insn >> 8) & 0xf;
1255 int cp_info = (insn >> 5) & 7;
1256 int dest = (insn >> 16) & 0xf;
1257 int operand = insn & 0xf;
1258
1259 if (env->cp[cp_num].cp_read)
1260 return env->cp[cp_num].cp_read(env->cp[cp_num].opaque,
1261 cp_info, dest, operand);
1262 return 0;
1263}
1264
ce819861
PB		 1265/* Return basic MPU access permission bits. */
1266static uint32_t simple_mpu_ap_bits(uint32_t val)
1267{
1268 uint32_t ret;
1269 uint32_t mask;
1270 int i;
1271 ret = 0;
1272 mask = 3;
1273 for (i = 0; i < 16; i += 2) {
1274 ret |= (val >> i) & mask;
1275 mask <<= 2;
1276 }
1277 return ret;
1278}
1279
1280/* Pad basic MPU access permission bits to extended format. */
1281static uint32_t extended_mpu_ap_bits(uint32_t val)
1282{
1283 uint32_t ret;
1284 uint32_t mask;
1285 int i;
1286 ret = 0;
1287 mask = 3;
1288 for (i = 0; i < 16; i += 2) {
1289 ret |= (val & mask) << i;
1290 mask <<= 2;
1291 }
1292 return ret;
1293}
1294
8984bd2e 1295void HELPER(set_cp15)(CPUState *env, uint32_t insn, uint32_t val)
b5ff1b31 1296{
9ee6e8bb
PB		 1297 int op1;
1298 int op2;
1299 int crm;
b5ff1b31 1300
9ee6e8bb 1301 op1 = (insn >> 21) & 7;
b5ff1b31 1302 op2 = (insn >> 5) & 7;
ce819861 1303 crm = insn & 0xf;
b5ff1b31 1304 switch ((insn >> 16) & 0xf) {
9ee6e8bb
PB		 1305 case 0:
1306 if (((insn >> 21) & 7) == 2) {
1307 /* ??? Select cache level. Ignore. */
1308 return;
1309 }
1310 /* ID codes. */
610c3c8a
AZ		 1311 if (arm_feature(env, ARM_FEATURE_XSCALE))
1312 break;
c3d2689d
AZ		 1313 if (arm_feature(env, ARM_FEATURE_OMAPCP))
1314 break;
b5ff1b31
FB		 1315 goto bad_reg;
1316 case 1: /* System configuration. */
c3d2689d
AZ		 1317 if (arm_feature(env, ARM_FEATURE_OMAPCP))
1318 op2 = 0;
b5ff1b31
FB		 1319 switch (op2) {
1320 case 0:
ce819861 1321 if (!arm_feature(env, ARM_FEATURE_XSCALE) || crm == 0)
c1713132 1322 env->cp15.c1_sys = val;
b5ff1b31
FB		 1323 /* ??? Lots of these bits are not implemented. */
1324 /* This may enable/disable the MMU, so do a TLB flush. */
1325 tlb_flush(env, 1);
1326 break;
9ee6e8bb 1327 case 1: /* Auxiliary cotrol register. */
610c3c8a
AZ		 1328 if (arm_feature(env, ARM_FEATURE_XSCALE)) {
1329 env->cp15.c1_xscaleauxcr = val;
c1713132 1330 break;
610c3c8a 1331 }
9ee6e8bb
PB		 1332 /* Not implemented. */
1333 break;
b5ff1b31 1334 case 2:
610c3c8a
AZ		 1335 if (arm_feature(env, ARM_FEATURE_XSCALE))
1336 goto bad_reg;
4be27dbb
PB		 1337 if (env->cp15.c1_coproc != val) {
1338 env->cp15.c1_coproc = val;
1339 /* ??? Is this safe when called from within a TB? */
1340 tb_flush(env);
1341 }
c1713132 1342 break;
b5ff1b31
FB		 1343 default:
1344 goto bad_reg;
1345 }
1346 break;
ce819861
PB		 1347 case 2: /* MMU Page table control / MPU cache control. */
1348 if (arm_feature(env, ARM_FEATURE_MPU)) {
1349 switch (op2) {
1350 case 0:
1351 env->cp15.c2_data = val;
1352 break;
1353 case 1:
1354 env->cp15.c2_insn = val;
1355 break;
1356 default:
1357 goto bad_reg;
1358 }
1359 } else {
9ee6e8bb
PB		 1360 switch (op2) {
1361 case 0:
1362 env->cp15.c2_base0 = val;
1363 break;
1364 case 1:
1365 env->cp15.c2_base1 = val;
1366 break;
1367 case 2:
1368 env->cp15.c2_mask = ~(((uint32_t)0xffffffffu) >> val);
1369 break;
1370 default:
1371 goto bad_reg;
1372 }
ce819861 1373 }
b5ff1b31 1374 break;
ce819861 1375 case 3: /* MMU Domain access control / MPU write buffer control. */
b5ff1b31 1376 env->cp15.c3 = val;
405ee3ad 1377 tlb_flush(env, 1); /* Flush TLB as domain not tracked in TLB */
b5ff1b31
FB		 1378 break;
1379 case 4: /* Reserved. */
1380 goto bad_reg;
ce819861 1381 case 5: /* MMU Fault status / MPU access permission. */
c3d2689d
AZ		 1382 if (arm_feature(env, ARM_FEATURE_OMAPCP))
1383 op2 = 0;
b5ff1b31
FB		 1384 switch (op2) {
1385 case 0:
ce819861
PB		 1386 if (arm_feature(env, ARM_FEATURE_MPU))
1387 val = extended_mpu_ap_bits(val);
b5ff1b31
FB		 1388 env->cp15.c5_data = val;
1389 break;
1390 case 1:
ce819861
PB		 1391 if (arm_feature(env, ARM_FEATURE_MPU))
1392 val = extended_mpu_ap_bits(val);
b5ff1b31
FB		 1393 env->cp15.c5_insn = val;
1394 break;
ce819861
PB		 1395 case 2:
1396 if (!arm_feature(env, ARM_FEATURE_MPU))
1397 goto bad_reg;
1398 env->cp15.c5_data = val;
b5ff1b31 1399 break;
ce819861
PB		 1400 case 3:
1401 if (!arm_feature(env, ARM_FEATURE_MPU))
1402 goto bad_reg;
1403 env->cp15.c5_insn = val;
b5ff1b31
FB		 1404 break;
1405 default:
1406 goto bad_reg;
1407 }
1408 break;
ce819861
PB		 1409 case 6: /* MMU Fault address / MPU base/size. */
1410 if (arm_feature(env, ARM_FEATURE_MPU)) {
1411 if (crm >= 8)
1412 goto bad_reg;
1413 env->cp15.c6_region[crm] = val;
1414 } else {
c3d2689d
AZ		 1415 if (arm_feature(env, ARM_FEATURE_OMAPCP))
1416 op2 = 0;
ce819861
PB		 1417 switch (op2) {
1418 case 0:
1419 env->cp15.c6_data = val;
1420 break;
9ee6e8bb
PB		 1421 case 1: /* ??? This is WFAR on armv6 */
1422 case 2:
ce819861
PB		 1423 env->cp15.c6_insn = val;
1424 break;
1425 default:
1426 goto bad_reg;
1427 }
1428 }
1429 break;
b5ff1b31 1430 case 7: /* Cache control. */
c3d2689d
AZ		 1431 env->cp15.c15_i_max = 0x000;
1432 env->cp15.c15_i_min = 0xff0;
b5ff1b31 1433 /* No cache, so nothing to do. */
9ee6e8bb 1434 /* ??? MPCore has VA to PA translation functions. */
b5ff1b31
FB		 1435 break;
1436 case 8: /* MMU TLB control. */
1437 switch (op2) {
1438 case 0: /* Invalidate all. */
1439 tlb_flush(env, 0);
1440 break;
1441 case 1: /* Invalidate single TLB entry. */
1442#if 0
1443 /* ??? This is wrong for large pages and sections. */
1444 /* As an ugly hack to make linux work we always flush a 4K
1445 pages. */
1446 val &= 0xfffff000;
1447 tlb_flush_page(env, val);
1448 tlb_flush_page(env, val + 0x400);
1449 tlb_flush_page(env, val + 0x800);
1450 tlb_flush_page(env, val + 0xc00);
1451#else
1452 tlb_flush(env, 1);
1453#endif
1454 break;
9ee6e8bb
PB		 1455 case 2: /* Invalidate on ASID. */
1456 tlb_flush(env, val == 0);
1457 break;
1458 case 3: /* Invalidate single entry on MVA. */
1459 /* ??? This is like case 1, but ignores ASID. */
1460 tlb_flush(env, 1);
1461 break;
b5ff1b31
FB		 1462 default:
1463 goto bad_reg;
1464 }
1465 break;
ce819861 1466 case 9:
c3d2689d
AZ		 1467 if (arm_feature(env, ARM_FEATURE_OMAPCP))
1468 break;
ce819861
PB		 1469 switch (crm) {
1470 case 0: /* Cache lockdown. */
9ee6e8bb
PB		 1471 switch (op1) {
1472 case 0: /* L1 cache. */
1473 switch (op2) {
1474 case 0:
1475 env->cp15.c9_data = val;
1476 break;
1477 case 1:
1478 env->cp15.c9_insn = val;
1479 break;
1480 default:
1481 goto bad_reg;
1482 }
1483 break;
1484 case 1: /* L2 cache. */
1485 /* Ignore writes to L2 lockdown/auxiliary registers. */
1486 break;
1487 default:
1488 goto bad_reg;
1489 }
1490 break;
ce819861
PB		 1491 case 1: /* TCM memory region registers. */
1492 /* Not implemented. */
1493 goto bad_reg;
b5ff1b31
FB		 1494 default:
1495 goto bad_reg;
1496 }
1497 break;
1498 case 10: /* MMU TLB lockdown. */
1499 /* ??? TLB lockdown not implemented. */
1500 break;
b5ff1b31
FB		 1501 case 12: /* Reserved. */
1502 goto bad_reg;
1503 case 13: /* Process ID. */
1504 switch (op2) {
1505 case 0:
d07edbfa
PB		 1506 /* Unlike real hardware the qemu TLB uses virtual addresses,
1507 not modified virtual addresses, so this causes a TLB flush.
1508 */
1509 if (env->cp15.c13_fcse != val)
1510 tlb_flush(env, 1);
1511 env->cp15.c13_fcse = val;
b5ff1b31
FB		 1512 break;
1513 case 1:
d07edbfa 1514 /* This changes the ASID, so do a TLB flush. */
ce819861
PB		 1515 if (env->cp15.c13_context != val
1516 && !arm_feature(env, ARM_FEATURE_MPU))
d07edbfa
PB		 1517 tlb_flush(env, 0);
1518 env->cp15.c13_context = val;
b5ff1b31 1519 break;
9ee6e8bb
PB		 1520 case 2:
1521 env->cp15.c13_tls1 = val;
1522 break;
1523 case 3:
1524 env->cp15.c13_tls2 = val;
1525 break;
1526 case 4:
1527 env->cp15.c13_tls3 = val;
1528 break;
b5ff1b31
FB		 1529 default:
1530 goto bad_reg;
1531 }
1532 break;
1533 case 14: /* Reserved. */
1534 goto bad_reg;
1535 case 15: /* Implementation specific. */
c1713132 1536 if (arm_feature(env, ARM_FEATURE_XSCALE)) {
ce819861 1537 if (op2 == 0 && crm == 1) {
2e23213f
AZ		 1538 if (env->cp15.c15_cpar != (val & 0x3fff)) {
1539 /* Changes cp0 to cp13 behavior, so needs a TB flush. */
1540 tb_flush(env);
1541 env->cp15.c15_cpar = val & 0x3fff;
1542 }
c1713132
AZ		 1543 break;
1544 }
1545 goto bad_reg;
1546 }
c3d2689d
AZ		 1547 if (arm_feature(env, ARM_FEATURE_OMAPCP)) {
1548 switch (crm) {
1549 case 0:
1550 break;
1551 case 1: /* Set TI925T configuration. */
1552 env->cp15.c15_ticonfig = val & 0xe7;
1553 env->cp15.c0_cpuid = (val & (1 << 5)) ? /* OS_TYPE bit */
1554 ARM_CPUID_TI915T : ARM_CPUID_TI925T;
1555 break;
1556 case 2: /* Set I_max. */
1557 env->cp15.c15_i_max = val;
1558 break;
1559 case 3: /* Set I_min. */
1560 env->cp15.c15_i_min = val;
1561 break;
1562 case 4: /* Set thread-ID. */
1563 env->cp15.c15_threadid = val & 0xffff;
1564 break;
1565 case 8: /* Wait-for-interrupt (deprecated). */
1566 cpu_interrupt(env, CPU_INTERRUPT_HALT);
1567 break;
1568 default:
1569 goto bad_reg;
1570 }
1571 }
b5ff1b31
FB		 1572 break;
1573 }
1574 return;
1575bad_reg:
1576 /* ??? For debugging only. Should raise illegal instruction exception. */
9ee6e8bb
PB		 1577 cpu_abort(env, "Unimplemented cp15 register write (c%d, c%d, {%d, %d})\n",
1578 (insn >> 16) & 0xf, crm, op1, op2);
b5ff1b31
FB		 1579}
1580
8984bd2e 1581uint32_t HELPER(get_cp15)(CPUState *env, uint32_t insn)
b5ff1b31 1582{
9ee6e8bb
PB		 1583 int op1;
1584 int op2;
1585 int crm;
b5ff1b31 1586
9ee6e8bb 1587 op1 = (insn >> 21) & 7;
b5ff1b31 1588 op2 = (insn >> 5) & 7;
c3d2689d 1589 crm = insn & 0xf;
b5ff1b31
FB		 1590 switch ((insn >> 16) & 0xf) {
1591 case 0: /* ID codes. */
9ee6e8bb
PB		 1592 switch (op1) {
1593 case 0:
1594 switch (crm) {
1595 case 0:
1596 switch (op2) {
1597 case 0: /* Device ID. */
1598 return env->cp15.c0_cpuid;
1599 case 1: /* Cache Type. */
1600 return env->cp15.c0_cachetype;
1601 case 2: /* TCM status. */
1602 return 0;
1603 case 3: /* TLB type register. */
1604 return 0; /* No lockable TLB entries. */
1605 case 5: /* CPU ID */
1606 return env->cpu_index;
1607 default:
1608 goto bad_reg;
1609 }
1610 case 1:
1611 if (!arm_feature(env, ARM_FEATURE_V6))
1612 goto bad_reg;
1613 return env->cp15.c0_c1[op2];
1614 case 2:
1615 if (!arm_feature(env, ARM_FEATURE_V6))
1616 goto bad_reg;
1617 return env->cp15.c0_c2[op2];
1618 case 3: case 4: case 5: case 6: case 7:
1619 return 0;
1620 default:
1621 goto bad_reg;
1622 }
1623 case 1:
1624 /* These registers aren't documented on arm11 cores. However
1625 Linux looks at them anyway. */
1626 if (!arm_feature(env, ARM_FEATURE_V6))
1627 goto bad_reg;
1628 if (crm != 0)
1629 goto bad_reg;
610c3c8a
AZ		 1630 if (arm_feature(env, ARM_FEATURE_XSCALE))
1631 goto bad_reg;
b5ff1b31 1632 return 0;
9ee6e8bb
PB		 1633 default:
1634 goto bad_reg;
b5ff1b31
FB		 1635 }
1636 case 1: /* System configuration. */
c3d2689d
AZ		 1637 if (arm_feature(env, ARM_FEATURE_OMAPCP))
1638 op2 = 0;
b5ff1b31
FB		 1639 switch (op2) {
1640 case 0: /* Control register. */
1641 return env->cp15.c1_sys;
1642 case 1: /* Auxiliary control register. */
c1713132 1643 if (arm_feature(env, ARM_FEATURE_XSCALE))
610c3c8a 1644 return env->cp15.c1_xscaleauxcr;
9ee6e8bb
PB		 1645 if (!arm_feature(env, ARM_FEATURE_AUXCR))
1646 goto bad_reg;
1647 switch (ARM_CPUID(env)) {
1648 case ARM_CPUID_ARM1026:
1649 return 1;
1650 case ARM_CPUID_ARM1136:
827df9f3 1651 case ARM_CPUID_ARM1136_R2:
9ee6e8bb
PB		 1652 return 7;
1653 case ARM_CPUID_ARM11MPCORE:
1654 return 1;
1655 case ARM_CPUID_CORTEXA8:
1656 return 0;
1657 default:
1658 goto bad_reg;
1659 }
b5ff1b31 1660 case 2: /* Coprocessor access register. */
610c3c8a
AZ		 1661 if (arm_feature(env, ARM_FEATURE_XSCALE))
1662 goto bad_reg;
b5ff1b31
FB		 1663 return env->cp15.c1_coproc;
1664 default:
1665 goto bad_reg;
1666 }
ce819861
PB		 1667 case 2: /* MMU Page table control / MPU cache control. */
1668 if (arm_feature(env, ARM_FEATURE_MPU)) {
1669 switch (op2) {
1670 case 0:
1671 return env->cp15.c2_data;
1672 break;
1673 case 1:
1674 return env->cp15.c2_insn;
1675 break;
1676 default:
1677 goto bad_reg;
1678 }
1679 } else {
9ee6e8bb
PB		 1680 switch (op2) {
1681 case 0:
1682 return env->cp15.c2_base0;
1683 case 1:
1684 return env->cp15.c2_base1;
1685 case 2:
1686 {
1687 int n;
1688 uint32_t mask;
1689 n = 0;
1690 mask = env->cp15.c2_mask;
1691 while (mask) {
1692 n++;
1693 mask <<= 1;
1694 }
1695 return n;
1696 }
1697 default:
1698 goto bad_reg;
1699 }
1700 }
ce819861 1701 case 3: /* MMU Domain access control / MPU write buffer control. */
b5ff1b31
FB		 1702 return env->cp15.c3;
1703 case 4: /* Reserved. */
1704 goto bad_reg;
ce819861 1705 case 5: /* MMU Fault status / MPU access permission. */
c3d2689d
AZ		 1706 if (arm_feature(env, ARM_FEATURE_OMAPCP))
1707 op2 = 0;
b5ff1b31
FB		 1708 switch (op2) {
1709 case 0:
ce819861
PB		 1710 if (arm_feature(env, ARM_FEATURE_MPU))
1711 return simple_mpu_ap_bits(env->cp15.c5_data);
b5ff1b31
FB		 1712 return env->cp15.c5_data;
1713 case 1:
ce819861
PB		 1714 if (arm_feature(env, ARM_FEATURE_MPU))
1715 return simple_mpu_ap_bits(env->cp15.c5_data);
1716 return env->cp15.c5_insn;
1717 case 2:
1718 if (!arm_feature(env, ARM_FEATURE_MPU))
1719 goto bad_reg;
1720 return env->cp15.c5_data;
1721 case 3:
1722 if (!arm_feature(env, ARM_FEATURE_MPU))
1723 goto bad_reg;
b5ff1b31
FB		 1724 return env->cp15.c5_insn;
1725 default:
1726 goto bad_reg;
1727 }
9ee6e8bb 1728 case 6: /* MMU Fault address. */
ce819861 1729 if (arm_feature(env, ARM_FEATURE_MPU)) {
9ee6e8bb 1730 if (crm >= 8)
ce819861 1731 goto bad_reg;
9ee6e8bb 1732 return env->cp15.c6_region[crm];
ce819861 1733 } else {
c3d2689d
AZ		 1734 if (arm_feature(env, ARM_FEATURE_OMAPCP))
1735 op2 = 0;
9ee6e8bb
PB		 1736 switch (op2) {
1737 case 0:
1738 return env->cp15.c6_data;
1739 case 1:
1740 if (arm_feature(env, ARM_FEATURE_V6)) {
1741 /* Watchpoint Fault Adrress. */
1742 return 0; /* Not implemented. */
1743 } else {
1744 /* Instruction Fault Adrress. */
1745 /* Arm9 doesn't have an IFAR, but implementing it anyway
1746 shouldn't do any harm. */
1747 return env->cp15.c6_insn;
1748 }
1749 case 2:
1750 if (arm_feature(env, ARM_FEATURE_V6)) {
1751 /* Instruction Fault Adrress. */
1752 return env->cp15.c6_insn;
1753 } else {
1754 goto bad_reg;
1755 }
1756 default:
1757 goto bad_reg;
1758 }
b5ff1b31
FB		 1759 }
1760 case 7: /* Cache control. */
6fbe23d5
PB		 1761 /* FIXME: Should only clear Z flag if destination is r15. */
1762 env->ZF = 0;
b5ff1b31
FB		 1763 return 0;
1764 case 8: /* MMU TLB control. */
1765 goto bad_reg;
1766 case 9: /* Cache lockdown. */
9ee6e8bb
PB		 1767 switch (op1) {
1768 case 0: /* L1 cache. */
1769 if (arm_feature(env, ARM_FEATURE_OMAPCP))
1770 return 0;
1771 switch (op2) {
1772 case 0:
1773 return env->cp15.c9_data;
1774 case 1:
1775 return env->cp15.c9_insn;
1776 default:
1777 goto bad_reg;
1778 }
1779 case 1: /* L2 cache */
1780 if (crm != 0)
1781 goto bad_reg;
1782 /* L2 Lockdown and Auxiliary control. */
c3d2689d 1783 return 0;
b5ff1b31
FB		 1784 default:
1785 goto bad_reg;
1786 }
1787 case 10: /* MMU TLB lockdown. */
1788 /* ??? TLB lockdown not implemented. */
1789 return 0;
1790 case 11: /* TCM DMA control. */
1791 case 12: /* Reserved. */
1792 goto bad_reg;
1793 case 13: /* Process ID. */
1794 switch (op2) {
1795 case 0:
1796 return env->cp15.c13_fcse;
1797 case 1:
1798 return env->cp15.c13_context;
9ee6e8bb
PB		 1799 case 2:
1800 return env->cp15.c13_tls1;
1801 case 3:
1802 return env->cp15.c13_tls2;
1803 case 4:
1804 return env->cp15.c13_tls3;
b5ff1b31
FB		 1805 default:
1806 goto bad_reg;
1807 }
1808 case 14: /* Reserved. */
1809 goto bad_reg;
1810 case 15: /* Implementation specific. */
c1713132 1811 if (arm_feature(env, ARM_FEATURE_XSCALE)) {
c3d2689d 1812 if (op2 == 0 && crm == 1)
c1713132
AZ		 1813 return env->cp15.c15_cpar;
1814
1815 goto bad_reg;
1816 }
c3d2689d
AZ		 1817 if (arm_feature(env, ARM_FEATURE_OMAPCP)) {
1818 switch (crm) {
1819 case 0:
1820 return 0;
1821 case 1: /* Read TI925T configuration. */
1822 return env->cp15.c15_ticonfig;
1823 case 2: /* Read I_max. */
1824 return env->cp15.c15_i_max;
1825 case 3: /* Read I_min. */
1826 return env->cp15.c15_i_min;
1827 case 4: /* Read thread-ID. */
1828 return env->cp15.c15_threadid;
1829 case 8: /* TI925T_status */
1830 return 0;
1831 }
827df9f3
AZ		 1832 /* TODO: Peripheral port remap register:
1833 * On OMAP2 mcr p15, 0, rn, c15, c2, 4 sets up the interrupt
1834 * controller base address at $rn & ~0xfff and map size of
1835 * 0x200 << ($rn & 0xfff), when MMU is off. */
c3d2689d
AZ		 1836 goto bad_reg;
1837 }
b5ff1b31
FB		 1838 return 0;
1839 }
1840bad_reg:
1841 /* ??? For debugging only. Should raise illegal instruction exception. */
9ee6e8bb
PB		 1842 cpu_abort(env, "Unimplemented cp15 register read (c%d, c%d, {%d, %d})\n",
1843 (insn >> 16) & 0xf, crm, op1, op2);
b5ff1b31
FB		 1844 return 0;
1845}
1846
b0109805 1847void HELPER(set_r13_banked)(CPUState *env, uint32_t mode, uint32_t val)
9ee6e8bb
PB		 1848{
1849 env->banked_r13[bank_number(mode)] = val;
1850}
1851
b0109805 1852uint32_t HELPER(get_r13_banked)(CPUState *env, uint32_t mode)
9ee6e8bb
PB		 1853{
1854 return env->banked_r13[bank_number(mode)];
1855}
1856
8984bd2e 1857uint32_t HELPER(v7m_mrs)(CPUState *env, uint32_t reg)
9ee6e8bb
PB		 1858{
1859 switch (reg) {
1860 case 0: /* APSR */
1861 return xpsr_read(env) & 0xf8000000;
1862 case 1: /* IAPSR */
1863 return xpsr_read(env) & 0xf80001ff;
1864 case 2: /* EAPSR */
1865 return xpsr_read(env) & 0xff00fc00;
1866 case 3: /* xPSR */
1867 return xpsr_read(env) & 0xff00fdff;
1868 case 5: /* IPSR */
1869 return xpsr_read(env) & 0x000001ff;
1870 case 6: /* EPSR */
1871 return xpsr_read(env) & 0x0700fc00;
1872 case 7: /* IEPSR */
1873 return xpsr_read(env) & 0x0700edff;
1874 case 8: /* MSP */
1875 return env->v7m.current_sp ? env->v7m.other_sp : env->regs[13];
1876 case 9: /* PSP */
1877 return env->v7m.current_sp ? env->regs[13] : env->v7m.other_sp;
1878 case 16: /* PRIMASK */
1879 return (env->uncached_cpsr & CPSR_I) != 0;
1880 case 17: /* FAULTMASK */
1881 return (env->uncached_cpsr & CPSR_F) != 0;
1882 case 18: /* BASEPRI */
1883 case 19: /* BASEPRI_MAX */
1884 return env->v7m.basepri;
1885 case 20: /* CONTROL */
1886 return env->v7m.control;
1887 default:
1888 /* ??? For debugging only. */
1889 cpu_abort(env, "Unimplemented system register read (%d)\n", reg);
1890 return 0;
1891 }
1892}
1893
8984bd2e 1894void HELPER(v7m_msr)(CPUState *env, uint32_t reg, uint32_t val)
9ee6e8bb
PB		 1895{
1896 switch (reg) {
1897 case 0: /* APSR */
1898 xpsr_write(env, val, 0xf8000000);
1899 break;
1900 case 1: /* IAPSR */
1901 xpsr_write(env, val, 0xf8000000);
1902 break;
1903 case 2: /* EAPSR */
1904 xpsr_write(env, val, 0xfe00fc00);
1905 break;
1906 case 3: /* xPSR */
1907 xpsr_write(env, val, 0xfe00fc00);
1908 break;
1909 case 5: /* IPSR */
1910 /* IPSR bits are readonly. */
1911 break;
1912 case 6: /* EPSR */
1913 xpsr_write(env, val, 0x0600fc00);
1914 break;
1915 case 7: /* IEPSR */
1916 xpsr_write(env, val, 0x0600fc00);
1917 break;
1918 case 8: /* MSP */
1919 if (env->v7m.current_sp)
1920 env->v7m.other_sp = val;
1921 else
1922 env->regs[13] = val;
1923 break;
1924 case 9: /* PSP */
1925 if (env->v7m.current_sp)
1926 env->regs[13] = val;
1927 else
1928 env->v7m.other_sp = val;
1929 break;
1930 case 16: /* PRIMASK */
1931 if (val & 1)
1932 env->uncached_cpsr |= CPSR_I;
1933 else
1934 env->uncached_cpsr &= ~CPSR_I;
1935 break;
1936 case 17: /* FAULTMASK */
1937 if (val & 1)
1938 env->uncached_cpsr |= CPSR_F;
1939 else
1940 env->uncached_cpsr &= ~CPSR_F;
1941 break;
1942 case 18: /* BASEPRI */
1943 env->v7m.basepri = val & 0xff;
1944 break;
1945 case 19: /* BASEPRI_MAX */
1946 val &= 0xff;
1947 if (val != 0 && (val < env->v7m.basepri || env->v7m.basepri == 0))
1948 env->v7m.basepri = val;
1949 break;
1950 case 20: /* CONTROL */
1951 env->v7m.control = val & 3;
1952 switch_v7m_sp(env, (val & 2) != 0);
1953 break;
1954 default:
1955 /* ??? For debugging only. */
1956 cpu_abort(env, "Unimplemented system register write (%d)\n", reg);
1957 return;
1958 }
1959}
1960
c1713132
AZ		 1961void cpu_arm_set_cp_io(CPUARMState *env, int cpnum,
1962 ARMReadCPFunc *cp_read, ARMWriteCPFunc *cp_write,
1963 void *opaque)
1964{
1965 if (cpnum < 0 || cpnum > 14) {
1966 cpu_abort(env, "Bad coprocessor number: %i\n", cpnum);
1967 return;
1968 }
1969
1970 env->cp[cpnum].cp_read = cp_read;
1971 env->cp[cpnum].cp_write = cp_write;
1972 env->cp[cpnum].opaque = opaque;
1973}
1974
b5ff1b31 1975#endif
6ddbc6e4
PB		 1976
1977/* Note that signed overflow is undefined in C. The following routines are
1978 careful to use unsigned types where modulo arithmetic is required.
1979 Failure to do so _will_ break on newer gcc. */
1980
1981/* Signed saturating arithmetic. */
1982
1654b2d6 1983/* Perform 16-bit signed saturating addition. */
6ddbc6e4
PB		 1984static inline uint16_t add16_sat(uint16_t a, uint16_t b)
1985{
1986 uint16_t res;
1987
1988 res = a + b;
1989 if (((res ^ a) & 0x8000) && !((a ^ b) & 0x8000)) {
1990 if (a & 0x8000)
1991 res = 0x8000;
1992 else
1993 res = 0x7fff;
1994 }
1995 return res;
1996}
1997
1654b2d6 1998/* Perform 8-bit signed saturating addition. */
6ddbc6e4
PB		 1999static inline uint8_t add8_sat(uint8_t a, uint8_t b)
2000{
2001 uint8_t res;
2002
2003 res = a + b;
2004 if (((res ^ a) & 0x80) && !((a ^ b) & 0x80)) {
2005 if (a & 0x80)
2006 res = 0x80;
2007 else
2008 res = 0x7f;
2009 }
2010 return res;
2011}
2012
1654b2d6 2013/* Perform 16-bit signed saturating subtraction. */
6ddbc6e4
PB		 2014static inline uint16_t sub16_sat(uint16_t a, uint16_t b)
2015{
2016 uint16_t res;
2017
2018 res = a - b;
2019 if (((res ^ a) & 0x8000) && ((a ^ b) & 0x8000)) {
2020 if (a & 0x8000)
2021 res = 0x8000;
2022 else
2023 res = 0x7fff;
2024 }
2025 return res;
2026}
2027
1654b2d6 2028/* Perform 8-bit signed saturating subtraction. */
6ddbc6e4
PB		 2029static inline uint8_t sub8_sat(uint8_t a, uint8_t b)
2030{
2031 uint8_t res;
2032
2033 res = a - b;
2034 if (((res ^ a) & 0x80) && ((a ^ b) & 0x80)) {
2035 if (a & 0x80)
2036 res = 0x80;
2037 else
2038 res = 0x7f;
2039 }
2040 return res;
2041}
2042
2043#define ADD16(a, b, n) RESULT(add16_sat(a, b), n, 16);
2044#define SUB16(a, b, n) RESULT(sub16_sat(a, b), n, 16);
2045#define ADD8(a, b, n) RESULT(add8_sat(a, b), n, 8);
2046#define SUB8(a, b, n) RESULT(sub8_sat(a, b), n, 8);
2047#define PFX q
2048
2049#include "op_addsub.h"
2050
2051/* Unsigned saturating arithmetic. */
460a09c1 2052static inline uint16_t add16_usat(uint16_t a, uint16_t b)
6ddbc6e4
PB		 2053{
2054 uint16_t res;
2055 res = a + b;
2056 if (res < a)
2057 res = 0xffff;
2058 return res;
2059}
2060
460a09c1 2061static inline uint16_t sub16_usat(uint16_t a, uint16_t b)
6ddbc6e4
PB		 2062{
2063 if (a < b)
2064 return a - b;
2065 else
2066 return 0;
2067}
2068
2069static inline uint8_t add8_usat(uint8_t a, uint8_t b)
2070{
2071 uint8_t res;
2072 res = a + b;
2073 if (res < a)
2074 res = 0xff;
2075 return res;
2076}
2077
2078static inline uint8_t sub8_usat(uint8_t a, uint8_t b)
2079{
2080 if (a < b)
2081 return a - b;
2082 else
2083 return 0;
2084}
2085
2086#define ADD16(a, b, n) RESULT(add16_usat(a, b), n, 16);
2087#define SUB16(a, b, n) RESULT(sub16_usat(a, b), n, 16);
2088#define ADD8(a, b, n) RESULT(add8_usat(a, b), n, 8);
2089#define SUB8(a, b, n) RESULT(sub8_usat(a, b), n, 8);
2090#define PFX uq
2091
2092#include "op_addsub.h"
2093
2094/* Signed modulo arithmetic. */
2095#define SARITH16(a, b, n, op) do { \
2096 int32_t sum; \
2097 sum = (int16_t)((uint16_t)(a) op (uint16_t)(b)); \
2098 RESULT(sum, n, 16); \
2099 if (sum >= 0) \
2100 ge |= 3 << (n * 2); \
2101 } while(0)
2102
2103#define SARITH8(a, b, n, op) do { \
2104 int32_t sum; \
2105 sum = (int8_t)((uint8_t)(a) op (uint8_t)(b)); \
2106 RESULT(sum, n, 8); \
2107 if (sum >= 0) \
2108 ge |= 1 << n; \
2109 } while(0)
2110
2111
2112#define ADD16(a, b, n) SARITH16(a, b, n, +)
2113#define SUB16(a, b, n) SARITH16(a, b, n, -)
2114#define ADD8(a, b, n) SARITH8(a, b, n, +)
2115#define SUB8(a, b, n) SARITH8(a, b, n, -)
2116#define PFX s
2117#define ARITH_GE
2118
2119#include "op_addsub.h"
2120
2121/* Unsigned modulo arithmetic. */
2122#define ADD16(a, b, n) do { \
2123 uint32_t sum; \
2124 sum = (uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b); \
2125 RESULT(sum, n, 16); \
a87aa10b 2126 if ((sum >> 16) == 1) \
6ddbc6e4
PB		 2127 ge |= 3 << (n * 2); \
2128 } while(0)
2129
2130#define ADD8(a, b, n) do { \
2131 uint32_t sum; \
2132 sum = (uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b); \
2133 RESULT(sum, n, 8); \
a87aa10b
AZ		 2134 if ((sum >> 8) == 1) \
2135 ge |= 1 << n; \
6ddbc6e4
PB		 2136 } while(0)
2137
2138#define SUB16(a, b, n) do { \
2139 uint32_t sum; \
2140 sum = (uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b); \
2141 RESULT(sum, n, 16); \
2142 if ((sum >> 16) == 0) \
2143 ge |= 3 << (n * 2); \
2144 } while(0)
2145
2146#define SUB8(a, b, n) do { \
2147 uint32_t sum; \
2148 sum = (uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b); \
2149 RESULT(sum, n, 8); \
2150 if ((sum >> 8) == 0) \
a87aa10b 2151 ge |= 1 << n; \
6ddbc6e4
PB		 2152 } while(0)
2153
2154#define PFX u
2155#define ARITH_GE
2156
2157#include "op_addsub.h"
2158
2159/* Halved signed arithmetic. */
2160#define ADD16(a, b, n) \
2161 RESULT(((int32_t)(int16_t)(a) + (int32_t)(int16_t)(b)) >> 1, n, 16)
2162#define SUB16(a, b, n) \
2163 RESULT(((int32_t)(int16_t)(a) - (int32_t)(int16_t)(b)) >> 1, n, 16)
2164#define ADD8(a, b, n) \
2165 RESULT(((int32_t)(int8_t)(a) + (int32_t)(int8_t)(b)) >> 1, n, 8)
2166#define SUB8(a, b, n) \
2167 RESULT(((int32_t)(int8_t)(a) - (int32_t)(int8_t)(b)) >> 1, n, 8)
2168#define PFX sh
2169
2170#include "op_addsub.h"
2171
2172/* Halved unsigned arithmetic. */
2173#define ADD16(a, b, n) \
2174 RESULT(((uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b)) >> 1, n, 16)
2175#define SUB16(a, b, n) \
2176 RESULT(((uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b)) >> 1, n, 16)
2177#define ADD8(a, b, n) \
2178 RESULT(((uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b)) >> 1, n, 8)
2179#define SUB8(a, b, n) \
2180 RESULT(((uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b)) >> 1, n, 8)
2181#define PFX uh
2182
2183#include "op_addsub.h"
2184
2185static inline uint8_t do_usad(uint8_t a, uint8_t b)
2186{
2187 if (a > b)
2188 return a - b;
2189 else
2190 return b - a;
2191}
2192
2193/* Unsigned sum of absolute byte differences. */
2194uint32_t HELPER(usad8)(uint32_t a, uint32_t b)
2195{
2196 uint32_t sum;
2197 sum = do_usad(a, b);
2198 sum += do_usad(a >> 8, b >> 8);
2199 sum += do_usad(a >> 16, b >>16);
2200 sum += do_usad(a >> 24, b >> 24);
2201 return sum;
2202}
2203
2204/* For ARMv6 SEL instruction. */
2205uint32_t HELPER(sel_flags)(uint32_t flags, uint32_t a, uint32_t b)
2206{
2207 uint32_t mask;
2208
2209 mask = 0;
2210 if (flags & 1)
2211 mask |= 0xff;
2212 if (flags & 2)
2213 mask |= 0xff00;
2214 if (flags & 4)
2215 mask |= 0xff0000;
2216 if (flags & 8)
2217 mask |= 0xff000000;
2218 return (a & mask) | (b & ~mask);
2219}
2220
5e3f878a
PB		 2221uint32_t HELPER(logicq_cc)(uint64_t val)
2222{
2223 return (val >> 32) | (val != 0);
2224}
4373f3ce
PB		 2225
2226/* VFP support. We follow the convention used for VFP instrunctions:
2227 Single precition routines have a "s" suffix, double precision a
2228 "d" suffix. */
2229
2230/* Convert host exception flags to vfp form. */
2231static inline int vfp_exceptbits_from_host(int host_bits)
2232{
2233 int target_bits = 0;
2234
2235 if (host_bits & float_flag_invalid)
2236 target_bits |= 1;
2237 if (host_bits & float_flag_divbyzero)
2238 target_bits |= 2;
2239 if (host_bits & float_flag_overflow)
2240 target_bits |= 4;
2241 if (host_bits & float_flag_underflow)
2242 target_bits |= 8;
2243 if (host_bits & float_flag_inexact)
2244 target_bits |= 0x10;
2245 return target_bits;
2246}
2247
2248uint32_t HELPER(vfp_get_fpscr)(CPUState *env)
2249{
2250 int i;
2251 uint32_t fpscr;
2252
2253 fpscr = (env->vfp.xregs[ARM_VFP_FPSCR] & 0xffc8ffff)
2254 | (env->vfp.vec_len << 16)
2255 | (env->vfp.vec_stride << 20);
2256 i = get_float_exception_flags(&env->vfp.fp_status);
2257 fpscr |= vfp_exceptbits_from_host(i);
2258 return fpscr;
2259}
2260
2261/* Convert vfp exception flags to target form. */
2262static inline int vfp_exceptbits_to_host(int target_bits)
2263{
2264 int host_bits = 0;
2265
2266 if (target_bits & 1)
2267 host_bits |= float_flag_invalid;
2268 if (target_bits & 2)
2269 host_bits |= float_flag_divbyzero;
2270 if (target_bits & 4)
2271 host_bits |= float_flag_overflow;
2272 if (target_bits & 8)
2273 host_bits |= float_flag_underflow;
2274 if (target_bits & 0x10)
2275 host_bits |= float_flag_inexact;
2276 return host_bits;
2277}
2278
2279void HELPER(vfp_set_fpscr)(CPUState *env, uint32_t val)
2280{
2281 int i;
2282 uint32_t changed;
2283
2284 changed = env->vfp.xregs[ARM_VFP_FPSCR];
2285 env->vfp.xregs[ARM_VFP_FPSCR] = (val & 0xffc8ffff);
2286 env->vfp.vec_len = (val >> 16) & 7;
2287 env->vfp.vec_stride = (val >> 20) & 3;
2288
2289 changed ^= val;
2290 if (changed & (3 << 22)) {
2291 i = (val >> 22) & 3;
2292 switch (i) {
2293 case 0:
2294 i = float_round_nearest_even;
2295 break;
2296 case 1:
2297 i = float_round_up;
2298 break;
2299 case 2:
2300 i = float_round_down;
2301 break;
2302 case 3:
2303 i = float_round_to_zero;
2304 break;
2305 }
2306 set_float_rounding_mode(i, &env->vfp.fp_status);
2307 }
2308
2309 i = vfp_exceptbits_to_host((val >> 8) & 0x1f);
2310 set_float_exception_flags(i, &env->vfp.fp_status);
2311 /* XXX: FZ and DN are not implemented. */
2312}
2313
2314#define VFP_HELPER(name, p) HELPER(glue(glue(vfp_,name),p))
2315
2316#define VFP_BINOP(name) \
2317float32 VFP_HELPER(name, s)(float32 a, float32 b, CPUState *env) \
2318{ \
2319 return float32_ ## name (a, b, &env->vfp.fp_status); \
2320} \
2321float64 VFP_HELPER(name, d)(float64 a, float64 b, CPUState *env) \
2322{ \
2323 return float64_ ## name (a, b, &env->vfp.fp_status); \
2324}
2325VFP_BINOP(add)
2326VFP_BINOP(sub)
2327VFP_BINOP(mul)
2328VFP_BINOP(div)
2329#undef VFP_BINOP
2330
2331float32 VFP_HELPER(neg, s)(float32 a)
2332{
2333 return float32_chs(a);
2334}
2335
2336float64 VFP_HELPER(neg, d)(float64 a)
2337{
66230e0d 2338 return float64_chs(a);
4373f3ce
PB		 2339}
2340
2341float32 VFP_HELPER(abs, s)(float32 a)
2342{
2343 return float32_abs(a);
2344}
2345
2346float64 VFP_HELPER(abs, d)(float64 a)
2347{
66230e0d 2348 return float64_abs(a);
4373f3ce
PB		 2349}
2350
2351float32 VFP_HELPER(sqrt, s)(float32 a, CPUState *env)
2352{
2353 return float32_sqrt(a, &env->vfp.fp_status);
2354}
2355
2356float64 VFP_HELPER(sqrt, d)(float64 a, CPUState *env)
2357{
2358 return float64_sqrt(a, &env->vfp.fp_status);
2359}
2360
2361/* XXX: check quiet/signaling case */
2362#define DO_VFP_cmp(p, type) \
2363void VFP_HELPER(cmp, p)(type a, type b, CPUState *env) \
2364{ \
2365 uint32_t flags; \
2366 switch(type ## _compare_quiet(a, b, &env->vfp.fp_status)) { \
2367 case 0: flags = 0x6; break; \
2368 case -1: flags = 0x8; break; \
2369 case 1: flags = 0x2; break; \
2370 default: case 2: flags = 0x3; break; \
2371 } \
2372 env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \
2373 | (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \
2374} \
2375void VFP_HELPER(cmpe, p)(type a, type b, CPUState *env) \
2376{ \
2377 uint32_t flags; \
2378 switch(type ## _compare(a, b, &env->vfp.fp_status)) { \
2379 case 0: flags = 0x6; break; \
2380 case -1: flags = 0x8; break; \
2381 case 1: flags = 0x2; break; \
2382 default: case 2: flags = 0x3; break; \
2383 } \
2384 env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \
2385 | (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \
2386}
2387DO_VFP_cmp(s, float32)
2388DO_VFP_cmp(d, float64)
2389#undef DO_VFP_cmp
2390
2391/* Helper routines to perform bitwise copies between float and int. */
2392static inline float32 vfp_itos(uint32_t i)
2393{
2394 union {
2395 uint32_t i;
2396 float32 s;
2397 } v;
2398
2399 v.i = i;
2400 return v.s;
2401}
2402
2403static inline uint32_t vfp_stoi(float32 s)
2404{
2405 union {
2406 uint32_t i;
2407 float32 s;
2408 } v;
2409
2410 v.s = s;
2411 return v.i;
2412}
2413
2414static inline float64 vfp_itod(uint64_t i)
2415{
2416 union {
2417 uint64_t i;
2418 float64 d;
2419 } v;
2420
2421 v.i = i;
2422 return v.d;
2423}
2424
2425static inline uint64_t vfp_dtoi(float64 d)
2426{
2427 union {
2428 uint64_t i;
2429 float64 d;
2430 } v;
2431
2432 v.d = d;
2433 return v.i;
2434}
2435
2436/* Integer to float conversion. */
2437float32 VFP_HELPER(uito, s)(float32 x, CPUState *env)
2438{
2439 return uint32_to_float32(vfp_stoi(x), &env->vfp.fp_status);
2440}
2441
2442float64 VFP_HELPER(uito, d)(float32 x, CPUState *env)
2443{
2444 return uint32_to_float64(vfp_stoi(x), &env->vfp.fp_status);
2445}
2446
2447float32 VFP_HELPER(sito, s)(float32 x, CPUState *env)
2448{
2449 return int32_to_float32(vfp_stoi(x), &env->vfp.fp_status);
2450}
2451
2452float64 VFP_HELPER(sito, d)(float32 x, CPUState *env)
2453{
2454 return int32_to_float64(vfp_stoi(x), &env->vfp.fp_status);
2455}
2456
2457/* Float to integer conversion. */
2458float32 VFP_HELPER(toui, s)(float32 x, CPUState *env)
2459{
2460 return vfp_itos(float32_to_uint32(x, &env->vfp.fp_status));
2461}
2462
2463float32 VFP_HELPER(toui, d)(float64 x, CPUState *env)
2464{
2465 return vfp_itos(float64_to_uint32(x, &env->vfp.fp_status));
2466}
2467
2468float32 VFP_HELPER(tosi, s)(float32 x, CPUState *env)
2469{
2470 return vfp_itos(float32_to_int32(x, &env->vfp.fp_status));
2471}
2472
2473float32 VFP_HELPER(tosi, d)(float64 x, CPUState *env)
2474{
2475 return vfp_itos(float64_to_int32(x, &env->vfp.fp_status));
2476}
2477
2478float32 VFP_HELPER(touiz, s)(float32 x, CPUState *env)
2479{
2480 return vfp_itos(float32_to_uint32_round_to_zero(x, &env->vfp.fp_status));
2481}
2482
2483float32 VFP_HELPER(touiz, d)(float64 x, CPUState *env)
2484{
2485 return vfp_itos(float64_to_uint32_round_to_zero(x, &env->vfp.fp_status));
2486}
2487
2488float32 VFP_HELPER(tosiz, s)(float32 x, CPUState *env)
2489{
2490 return vfp_itos(float32_to_int32_round_to_zero(x, &env->vfp.fp_status));
2491}
2492
2493float32 VFP_HELPER(tosiz, d)(float64 x, CPUState *env)
2494{
2495 return vfp_itos(float64_to_int32_round_to_zero(x, &env->vfp.fp_status));
2496}
2497
2498/* floating point conversion */
2499float64 VFP_HELPER(fcvtd, s)(float32 x, CPUState *env)
2500{
2501 return float32_to_float64(x, &env->vfp.fp_status);
2502}
2503
2504float32 VFP_HELPER(fcvts, d)(float64 x, CPUState *env)
2505{
2506 return float64_to_float32(x, &env->vfp.fp_status);
2507}
2508
2509/* VFP3 fixed point conversion. */
2510#define VFP_CONV_FIX(name, p, ftype, itype, sign) \
2511ftype VFP_HELPER(name##to, p)(ftype x, uint32_t shift, CPUState *env) \
2512{ \
2513 ftype tmp; \
2514 tmp = sign##int32_to_##ftype ((itype)vfp_##p##toi(x), \
2515 &env->vfp.fp_status); \
2516 return ftype##_scalbn(tmp, shift, &env->vfp.fp_status); \
2517} \
2518ftype VFP_HELPER(to##name, p)(ftype x, uint32_t shift, CPUState *env) \
2519{ \
2520 ftype tmp; \
2521 tmp = ftype##_scalbn(x, shift, &env->vfp.fp_status); \
2522 return vfp_ito##p((itype)ftype##_to_##sign##int32_round_to_zero(tmp, \
2523 &env->vfp.fp_status)); \
2524}
2525
2526VFP_CONV_FIX(sh, d, float64, int16, )
2527VFP_CONV_FIX(sl, d, float64, int32, )
2528VFP_CONV_FIX(uh, d, float64, uint16, u)
2529VFP_CONV_FIX(ul, d, float64, uint32, u)
2530VFP_CONV_FIX(sh, s, float32, int16, )
2531VFP_CONV_FIX(sl, s, float32, int32, )
2532VFP_CONV_FIX(uh, s, float32, uint16, u)
2533VFP_CONV_FIX(ul, s, float32, uint32, u)
2534#undef VFP_CONV_FIX
2535
2536float32 HELPER(recps_f32)(float32 a, float32 b, CPUState *env)
2537{
2538 float_status *s = &env->vfp.fp_status;
2539 float32 two = int32_to_float32(2, s);
2540 return float32_sub(two, float32_mul(a, b, s), s);
2541}
2542
2543float32 HELPER(rsqrts_f32)(float32 a, float32 b, CPUState *env)
2544{
2545 float_status *s = &env->vfp.fp_status;
2546 float32 three = int32_to_float32(3, s);
2547 return float32_sub(three, float32_mul(a, b, s), s);
2548}
2549
8f8e3aa4
PB		 2550/* NEON helpers. */
2551
4373f3ce
PB		 2552/* TODO: The architecture specifies the value that the estimate functions
2553 should return. We return the exact reciprocal/root instead. */
2554float32 HELPER(recpe_f32)(float32 a, CPUState *env)
2555{
2556 float_status *s = &env->vfp.fp_status;
2557 float32 one = int32_to_float32(1, s);
2558 return float32_div(one, a, s);
2559}
2560
2561float32 HELPER(rsqrte_f32)(float32 a, CPUState *env)
2562{
2563 float_status *s = &env->vfp.fp_status;
2564 float32 one = int32_to_float32(1, s);
2565 return float32_div(one, float32_sqrt(a, s), s);
2566}
2567
2568uint32_t HELPER(recpe_u32)(uint32_t a, CPUState *env)
2569{
2570 float_status *s = &env->vfp.fp_status;
2571 float32 tmp;
2572 tmp = int32_to_float32(a, s);
2573 tmp = float32_scalbn(tmp, -32, s);
2574 tmp = helper_recpe_f32(tmp, env);
2575 tmp = float32_scalbn(tmp, 31, s);
2576 return float32_to_int32(tmp, s);
2577}
2578
2579uint32_t HELPER(rsqrte_u32)(uint32_t a, CPUState *env)
2580{
2581 float_status *s = &env->vfp.fp_status;
2582 float32 tmp;
2583 tmp = int32_to_float32(a, s);
2584 tmp = float32_scalbn(tmp, -32, s);
2585 tmp = helper_rsqrte_f32(tmp, env);
2586 tmp = float32_scalbn(tmp, 31, s);
2587 return float32_to_int32(tmp, s);
2588}
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