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Commit | Line | Data |
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b5ff1b31 | 1 | #include "cpu.h" |
ccd38087 | 2 | #include "internals.h" |
022c62cb | 3 | #include "exec/gdbstub.h" |
2ef6175a | 4 | #include "exec/helper-proto.h" |
1de7afc9 | 5 | #include "qemu/host-utils.h" |
78027bb6 | 6 | #include "sysemu/arch_init.h" |
9c17d615 | 7 | #include "sysemu/sysemu.h" |
1de7afc9 | 8 | #include "qemu/bitops.h" |
eb0ecd5a | 9 | #include "qemu/crc32c.h" |
f08b6170 | 10 | #include "exec/cpu_ldst.h" |
1d854765 | 11 | #include "arm_ldst.h" |
eb0ecd5a | 12 | #include <zlib.h> /* For crc32 */ |
0b03bdfc | 13 | |
4a501606 | 14 | #ifndef CONFIG_USER_ONLY |
2c8dd318 | 15 | static inline int get_phys_addr(CPUARMState *env, target_ulong address, |
4a501606 | 16 | int access_type, int is_user, |
a8170e5e | 17 | hwaddr *phys_ptr, int *prot, |
4a501606 | 18 | target_ulong *page_size); |
7c2cb42b AF |
19 | |
20 | /* Definitions for the PMCCNTR and PMCR registers */ | |
21 | #define PMCRD 0x8 | |
22 | #define PMCRC 0x4 | |
23 | #define PMCRE 0x1 | |
4a501606 PM |
24 | #endif |
25 | ||
0ecb72a5 | 26 | static int vfp_gdb_get_reg(CPUARMState *env, uint8_t *buf, int reg) |
56aebc89 PB |
27 | { |
28 | int nregs; | |
29 | ||
30 | /* VFP data registers are always little-endian. */ | |
31 | nregs = arm_feature(env, ARM_FEATURE_VFP3) ? 32 : 16; | |
32 | if (reg < nregs) { | |
33 | stfq_le_p(buf, env->vfp.regs[reg]); | |
34 | return 8; | |
35 | } | |
36 | if (arm_feature(env, ARM_FEATURE_NEON)) { | |
37 | /* Aliases for Q regs. */ | |
38 | nregs += 16; | |
39 | if (reg < nregs) { | |
40 | stfq_le_p(buf, env->vfp.regs[(reg - 32) * 2]); | |
41 | stfq_le_p(buf + 8, env->vfp.regs[(reg - 32) * 2 + 1]); | |
42 | return 16; | |
43 | } | |
44 | } | |
45 | switch (reg - nregs) { | |
46 | case 0: stl_p(buf, env->vfp.xregs[ARM_VFP_FPSID]); return 4; | |
47 | case 1: stl_p(buf, env->vfp.xregs[ARM_VFP_FPSCR]); return 4; | |
48 | case 2: stl_p(buf, env->vfp.xregs[ARM_VFP_FPEXC]); return 4; | |
49 | } | |
50 | return 0; | |
51 | } | |
52 | ||
0ecb72a5 | 53 | static int vfp_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg) |
56aebc89 PB |
54 | { |
55 | int nregs; | |
56 | ||
57 | nregs = arm_feature(env, ARM_FEATURE_VFP3) ? 32 : 16; | |
58 | if (reg < nregs) { | |
59 | env->vfp.regs[reg] = ldfq_le_p(buf); | |
60 | return 8; | |
61 | } | |
62 | if (arm_feature(env, ARM_FEATURE_NEON)) { | |
63 | nregs += 16; | |
64 | if (reg < nregs) { | |
65 | env->vfp.regs[(reg - 32) * 2] = ldfq_le_p(buf); | |
66 | env->vfp.regs[(reg - 32) * 2 + 1] = ldfq_le_p(buf + 8); | |
67 | return 16; | |
68 | } | |
69 | } | |
70 | switch (reg - nregs) { | |
71 | case 0: env->vfp.xregs[ARM_VFP_FPSID] = ldl_p(buf); return 4; | |
72 | case 1: env->vfp.xregs[ARM_VFP_FPSCR] = ldl_p(buf); return 4; | |
71b3c3de | 73 | case 2: env->vfp.xregs[ARM_VFP_FPEXC] = ldl_p(buf) & (1 << 30); return 4; |
56aebc89 PB |
74 | } |
75 | return 0; | |
76 | } | |
77 | ||
6a669427 PM |
78 | static int aarch64_fpu_gdb_get_reg(CPUARMState *env, uint8_t *buf, int reg) |
79 | { | |
80 | switch (reg) { | |
81 | case 0 ... 31: | |
82 | /* 128 bit FP register */ | |
83 | stfq_le_p(buf, env->vfp.regs[reg * 2]); | |
84 | stfq_le_p(buf + 8, env->vfp.regs[reg * 2 + 1]); | |
85 | return 16; | |
86 | case 32: | |
87 | /* FPSR */ | |
88 | stl_p(buf, vfp_get_fpsr(env)); | |
89 | return 4; | |
90 | case 33: | |
91 | /* FPCR */ | |
92 | stl_p(buf, vfp_get_fpcr(env)); | |
93 | return 4; | |
94 | default: | |
95 | return 0; | |
96 | } | |
97 | } | |
98 | ||
99 | static int aarch64_fpu_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg) | |
100 | { | |
101 | switch (reg) { | |
102 | case 0 ... 31: | |
103 | /* 128 bit FP register */ | |
104 | env->vfp.regs[reg * 2] = ldfq_le_p(buf); | |
105 | env->vfp.regs[reg * 2 + 1] = ldfq_le_p(buf + 8); | |
106 | return 16; | |
107 | case 32: | |
108 | /* FPSR */ | |
109 | vfp_set_fpsr(env, ldl_p(buf)); | |
110 | return 4; | |
111 | case 33: | |
112 | /* FPCR */ | |
113 | vfp_set_fpcr(env, ldl_p(buf)); | |
114 | return 4; | |
115 | default: | |
116 | return 0; | |
117 | } | |
118 | } | |
119 | ||
c4241c7d | 120 | static uint64_t raw_read(CPUARMState *env, const ARMCPRegInfo *ri) |
d4e6df63 | 121 | { |
67ed771d | 122 | if (cpreg_field_is_64bit(ri)) { |
c4241c7d | 123 | return CPREG_FIELD64(env, ri); |
22d9e1a9 | 124 | } else { |
c4241c7d | 125 | return CPREG_FIELD32(env, ri); |
22d9e1a9 | 126 | } |
d4e6df63 PM |
127 | } |
128 | ||
c4241c7d PM |
129 | static void raw_write(CPUARMState *env, const ARMCPRegInfo *ri, |
130 | uint64_t value) | |
d4e6df63 | 131 | { |
67ed771d | 132 | if (cpreg_field_is_64bit(ri)) { |
22d9e1a9 PM |
133 | CPREG_FIELD64(env, ri) = value; |
134 | } else { | |
135 | CPREG_FIELD32(env, ri) = value; | |
136 | } | |
d4e6df63 PM |
137 | } |
138 | ||
59a1c327 | 139 | static uint64_t read_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri) |
721fae12 | 140 | { |
59a1c327 | 141 | /* Raw read of a coprocessor register (as needed for migration, etc). */ |
721fae12 | 142 | if (ri->type & ARM_CP_CONST) { |
59a1c327 | 143 | return ri->resetvalue; |
721fae12 | 144 | } else if (ri->raw_readfn) { |
59a1c327 | 145 | return ri->raw_readfn(env, ri); |
721fae12 | 146 | } else if (ri->readfn) { |
59a1c327 | 147 | return ri->readfn(env, ri); |
721fae12 | 148 | } else { |
59a1c327 | 149 | return raw_read(env, ri); |
721fae12 | 150 | } |
721fae12 PM |
151 | } |
152 | ||
59a1c327 | 153 | static void write_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri, |
7900e9f1 | 154 | uint64_t v) |
721fae12 PM |
155 | { |
156 | /* Raw write of a coprocessor register (as needed for migration, etc). | |
721fae12 PM |
157 | * Note that constant registers are treated as write-ignored; the |
158 | * caller should check for success by whether a readback gives the | |
159 | * value written. | |
160 | */ | |
161 | if (ri->type & ARM_CP_CONST) { | |
59a1c327 | 162 | return; |
721fae12 | 163 | } else if (ri->raw_writefn) { |
c4241c7d | 164 | ri->raw_writefn(env, ri, v); |
721fae12 | 165 | } else if (ri->writefn) { |
c4241c7d | 166 | ri->writefn(env, ri, v); |
721fae12 | 167 | } else { |
afb2530f | 168 | raw_write(env, ri, v); |
721fae12 | 169 | } |
721fae12 PM |
170 | } |
171 | ||
172 | bool write_cpustate_to_list(ARMCPU *cpu) | |
173 | { | |
174 | /* Write the coprocessor state from cpu->env to the (index,value) list. */ | |
175 | int i; | |
176 | bool ok = true; | |
177 | ||
178 | for (i = 0; i < cpu->cpreg_array_len; i++) { | |
179 | uint32_t regidx = kvm_to_cpreg_id(cpu->cpreg_indexes[i]); | |
180 | const ARMCPRegInfo *ri; | |
59a1c327 | 181 | |
60322b39 | 182 | ri = get_arm_cp_reginfo(cpu->cp_regs, regidx); |
721fae12 PM |
183 | if (!ri) { |
184 | ok = false; | |
185 | continue; | |
186 | } | |
187 | if (ri->type & ARM_CP_NO_MIGRATE) { | |
188 | continue; | |
189 | } | |
59a1c327 | 190 | cpu->cpreg_values[i] = read_raw_cp_reg(&cpu->env, ri); |
721fae12 PM |
191 | } |
192 | return ok; | |
193 | } | |
194 | ||
195 | bool write_list_to_cpustate(ARMCPU *cpu) | |
196 | { | |
197 | int i; | |
198 | bool ok = true; | |
199 | ||
200 | for (i = 0; i < cpu->cpreg_array_len; i++) { | |
201 | uint32_t regidx = kvm_to_cpreg_id(cpu->cpreg_indexes[i]); | |
202 | uint64_t v = cpu->cpreg_values[i]; | |
721fae12 PM |
203 | const ARMCPRegInfo *ri; |
204 | ||
60322b39 | 205 | ri = get_arm_cp_reginfo(cpu->cp_regs, regidx); |
721fae12 PM |
206 | if (!ri) { |
207 | ok = false; | |
208 | continue; | |
209 | } | |
210 | if (ri->type & ARM_CP_NO_MIGRATE) { | |
211 | continue; | |
212 | } | |
213 | /* Write value and confirm it reads back as written | |
214 | * (to catch read-only registers and partially read-only | |
215 | * registers where the incoming migration value doesn't match) | |
216 | */ | |
59a1c327 PM |
217 | write_raw_cp_reg(&cpu->env, ri, v); |
218 | if (read_raw_cp_reg(&cpu->env, ri) != v) { | |
721fae12 PM |
219 | ok = false; |
220 | } | |
221 | } | |
222 | return ok; | |
223 | } | |
224 | ||
225 | static void add_cpreg_to_list(gpointer key, gpointer opaque) | |
226 | { | |
227 | ARMCPU *cpu = opaque; | |
228 | uint64_t regidx; | |
229 | const ARMCPRegInfo *ri; | |
230 | ||
231 | regidx = *(uint32_t *)key; | |
60322b39 | 232 | ri = get_arm_cp_reginfo(cpu->cp_regs, regidx); |
721fae12 PM |
233 | |
234 | if (!(ri->type & ARM_CP_NO_MIGRATE)) { | |
235 | cpu->cpreg_indexes[cpu->cpreg_array_len] = cpreg_to_kvm_id(regidx); | |
236 | /* The value array need not be initialized at this point */ | |
237 | cpu->cpreg_array_len++; | |
238 | } | |
239 | } | |
240 | ||
241 | static void count_cpreg(gpointer key, gpointer opaque) | |
242 | { | |
243 | ARMCPU *cpu = opaque; | |
244 | uint64_t regidx; | |
245 | const ARMCPRegInfo *ri; | |
246 | ||
247 | regidx = *(uint32_t *)key; | |
60322b39 | 248 | ri = get_arm_cp_reginfo(cpu->cp_regs, regidx); |
721fae12 PM |
249 | |
250 | if (!(ri->type & ARM_CP_NO_MIGRATE)) { | |
251 | cpu->cpreg_array_len++; | |
252 | } | |
253 | } | |
254 | ||
255 | static gint cpreg_key_compare(gconstpointer a, gconstpointer b) | |
256 | { | |
cbf239b7 AR |
257 | uint64_t aidx = cpreg_to_kvm_id(*(uint32_t *)a); |
258 | uint64_t bidx = cpreg_to_kvm_id(*(uint32_t *)b); | |
721fae12 | 259 | |
cbf239b7 AR |
260 | if (aidx > bidx) { |
261 | return 1; | |
262 | } | |
263 | if (aidx < bidx) { | |
264 | return -1; | |
265 | } | |
266 | return 0; | |
721fae12 PM |
267 | } |
268 | ||
82a3a118 PM |
269 | static void cpreg_make_keylist(gpointer key, gpointer value, gpointer udata) |
270 | { | |
271 | GList **plist = udata; | |
272 | ||
273 | *plist = g_list_prepend(*plist, key); | |
274 | } | |
275 | ||
721fae12 PM |
276 | void init_cpreg_list(ARMCPU *cpu) |
277 | { | |
278 | /* Initialise the cpreg_tuples[] array based on the cp_regs hash. | |
279 | * Note that we require cpreg_tuples[] to be sorted by key ID. | |
280 | */ | |
82a3a118 | 281 | GList *keys = NULL; |
721fae12 PM |
282 | int arraylen; |
283 | ||
82a3a118 PM |
284 | g_hash_table_foreach(cpu->cp_regs, cpreg_make_keylist, &keys); |
285 | ||
721fae12 PM |
286 | keys = g_list_sort(keys, cpreg_key_compare); |
287 | ||
288 | cpu->cpreg_array_len = 0; | |
289 | ||
290 | g_list_foreach(keys, count_cpreg, cpu); | |
291 | ||
292 | arraylen = cpu->cpreg_array_len; | |
293 | cpu->cpreg_indexes = g_new(uint64_t, arraylen); | |
294 | cpu->cpreg_values = g_new(uint64_t, arraylen); | |
295 | cpu->cpreg_vmstate_indexes = g_new(uint64_t, arraylen); | |
296 | cpu->cpreg_vmstate_values = g_new(uint64_t, arraylen); | |
297 | cpu->cpreg_vmstate_array_len = cpu->cpreg_array_len; | |
298 | cpu->cpreg_array_len = 0; | |
299 | ||
300 | g_list_foreach(keys, add_cpreg_to_list, cpu); | |
301 | ||
302 | assert(cpu->cpreg_array_len == arraylen); | |
303 | ||
304 | g_list_free(keys); | |
305 | } | |
306 | ||
014406b5 PM |
307 | /* Return true if extended addresses are enabled. |
308 | * This is always the case if our translation regime is 64 bit, | |
309 | * but depends on TTBCR.EAE for 32 bit. | |
310 | */ | |
311 | static inline bool extended_addresses_enabled(CPUARMState *env) | |
312 | { | |
313 | return arm_el_is_aa64(env, 1) | |
314 | || ((arm_feature(env, ARM_FEATURE_LPAE) | |
e389be16 | 315 | && (env->cp15.c2_control & TTBCR_EAE))); |
014406b5 PM |
316 | } |
317 | ||
c4241c7d | 318 | static void dacr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) |
c983fe6c | 319 | { |
00c8cb0a AF |
320 | ARMCPU *cpu = arm_env_get_cpu(env); |
321 | ||
8d5c773e | 322 | raw_write(env, ri, value); |
00c8cb0a | 323 | tlb_flush(CPU(cpu), 1); /* Flush TLB as domain not tracked in TLB */ |
c983fe6c PM |
324 | } |
325 | ||
c4241c7d | 326 | static void fcse_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) |
08de207b | 327 | { |
00c8cb0a AF |
328 | ARMCPU *cpu = arm_env_get_cpu(env); |
329 | ||
8d5c773e | 330 | if (raw_read(env, ri) != value) { |
08de207b PM |
331 | /* Unlike real hardware the qemu TLB uses virtual addresses, |
332 | * not modified virtual addresses, so this causes a TLB flush. | |
333 | */ | |
00c8cb0a | 334 | tlb_flush(CPU(cpu), 1); |
8d5c773e | 335 | raw_write(env, ri, value); |
08de207b | 336 | } |
08de207b | 337 | } |
c4241c7d PM |
338 | |
339 | static void contextidr_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
340 | uint64_t value) | |
08de207b | 341 | { |
00c8cb0a AF |
342 | ARMCPU *cpu = arm_env_get_cpu(env); |
343 | ||
8d5c773e | 344 | if (raw_read(env, ri) != value && !arm_feature(env, ARM_FEATURE_MPU) |
014406b5 | 345 | && !extended_addresses_enabled(env)) { |
08de207b PM |
346 | /* For VMSA (when not using the LPAE long descriptor page table |
347 | * format) this register includes the ASID, so do a TLB flush. | |
348 | * For PMSA it is purely a process ID and no action is needed. | |
349 | */ | |
00c8cb0a | 350 | tlb_flush(CPU(cpu), 1); |
08de207b | 351 | } |
8d5c773e | 352 | raw_write(env, ri, value); |
08de207b PM |
353 | } |
354 | ||
c4241c7d PM |
355 | static void tlbiall_write(CPUARMState *env, const ARMCPRegInfo *ri, |
356 | uint64_t value) | |
d929823f PM |
357 | { |
358 | /* Invalidate all (TLBIALL) */ | |
00c8cb0a AF |
359 | ARMCPU *cpu = arm_env_get_cpu(env); |
360 | ||
361 | tlb_flush(CPU(cpu), 1); | |
d929823f PM |
362 | } |
363 | ||
c4241c7d PM |
364 | static void tlbimva_write(CPUARMState *env, const ARMCPRegInfo *ri, |
365 | uint64_t value) | |
d929823f PM |
366 | { |
367 | /* Invalidate single TLB entry by MVA and ASID (TLBIMVA) */ | |
31b030d4 AF |
368 | ARMCPU *cpu = arm_env_get_cpu(env); |
369 | ||
370 | tlb_flush_page(CPU(cpu), value & TARGET_PAGE_MASK); | |
d929823f PM |
371 | } |
372 | ||
c4241c7d PM |
373 | static void tlbiasid_write(CPUARMState *env, const ARMCPRegInfo *ri, |
374 | uint64_t value) | |
d929823f PM |
375 | { |
376 | /* Invalidate by ASID (TLBIASID) */ | |
00c8cb0a AF |
377 | ARMCPU *cpu = arm_env_get_cpu(env); |
378 | ||
379 | tlb_flush(CPU(cpu), value == 0); | |
d929823f PM |
380 | } |
381 | ||
c4241c7d PM |
382 | static void tlbimvaa_write(CPUARMState *env, const ARMCPRegInfo *ri, |
383 | uint64_t value) | |
d929823f PM |
384 | { |
385 | /* Invalidate single entry by MVA, all ASIDs (TLBIMVAA) */ | |
31b030d4 AF |
386 | ARMCPU *cpu = arm_env_get_cpu(env); |
387 | ||
388 | tlb_flush_page(CPU(cpu), value & TARGET_PAGE_MASK); | |
d929823f PM |
389 | } |
390 | ||
e9aa6c21 | 391 | static const ARMCPRegInfo cp_reginfo[] = { |
08de207b PM |
392 | { .name = "FCSEIDR", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 0, |
393 | .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c13_fcse), | |
d4e6df63 | 394 | .resetvalue = 0, .writefn = fcse_write, .raw_writefn = raw_write, }, |
014406b5 PM |
395 | { .name = "CONTEXTIDR", .state = ARM_CP_STATE_BOTH, |
396 | .opc0 = 3, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 1, | |
397 | .access = PL1_RW, | |
398 | .fieldoffset = offsetof(CPUARMState, cp15.contextidr_el1), | |
d4e6df63 | 399 | .resetvalue = 0, .writefn = contextidr_write, .raw_writefn = raw_write, }, |
9449fdf6 PM |
400 | REGINFO_SENTINEL |
401 | }; | |
402 | ||
403 | static const ARMCPRegInfo not_v8_cp_reginfo[] = { | |
404 | /* NB: Some of these registers exist in v8 but with more precise | |
405 | * definitions that don't use CP_ANY wildcards (mostly in v8_cp_reginfo[]). | |
406 | */ | |
407 | /* MMU Domain access control / MPU write buffer control */ | |
408 | { .name = "DACR", .cp = 15, | |
409 | .crn = 3, .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY, | |
410 | .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c3), | |
411 | .resetvalue = 0, .writefn = dacr_write, .raw_writefn = raw_write, }, | |
4fdd17dd PM |
412 | /* ??? This covers not just the impdef TLB lockdown registers but also |
413 | * some v7VMSA registers relating to TEX remap, so it is overly broad. | |
414 | */ | |
415 | { .name = "TLB_LOCKDOWN", .cp = 15, .crn = 10, .crm = CP_ANY, | |
416 | .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_NOP }, | |
d929823f PM |
417 | /* MMU TLB control. Note that the wildcarding means we cover not just |
418 | * the unified TLB ops but also the dside/iside/inner-shareable variants. | |
419 | */ | |
420 | { .name = "TLBIALL", .cp = 15, .crn = 8, .crm = CP_ANY, | |
d4e6df63 PM |
421 | .opc1 = CP_ANY, .opc2 = 0, .access = PL1_W, .writefn = tlbiall_write, |
422 | .type = ARM_CP_NO_MIGRATE }, | |
d929823f | 423 | { .name = "TLBIMVA", .cp = 15, .crn = 8, .crm = CP_ANY, |
d4e6df63 PM |
424 | .opc1 = CP_ANY, .opc2 = 1, .access = PL1_W, .writefn = tlbimva_write, |
425 | .type = ARM_CP_NO_MIGRATE }, | |
d929823f | 426 | { .name = "TLBIASID", .cp = 15, .crn = 8, .crm = CP_ANY, |
d4e6df63 PM |
427 | .opc1 = CP_ANY, .opc2 = 2, .access = PL1_W, .writefn = tlbiasid_write, |
428 | .type = ARM_CP_NO_MIGRATE }, | |
d929823f | 429 | { .name = "TLBIMVAA", .cp = 15, .crn = 8, .crm = CP_ANY, |
d4e6df63 PM |
430 | .opc1 = CP_ANY, .opc2 = 3, .access = PL1_W, .writefn = tlbimvaa_write, |
431 | .type = ARM_CP_NO_MIGRATE }, | |
c4804214 PM |
432 | /* Cache maintenance ops; some of this space may be overridden later. */ |
433 | { .name = "CACHEMAINT", .cp = 15, .crn = 7, .crm = CP_ANY, | |
434 | .opc1 = 0, .opc2 = CP_ANY, .access = PL1_W, | |
435 | .type = ARM_CP_NOP | ARM_CP_OVERRIDE }, | |
e9aa6c21 PM |
436 | REGINFO_SENTINEL |
437 | }; | |
438 | ||
7d57f408 PM |
439 | static const ARMCPRegInfo not_v6_cp_reginfo[] = { |
440 | /* Not all pre-v6 cores implemented this WFI, so this is slightly | |
441 | * over-broad. | |
442 | */ | |
443 | { .name = "WFI_v5", .cp = 15, .crn = 7, .crm = 8, .opc1 = 0, .opc2 = 2, | |
444 | .access = PL1_W, .type = ARM_CP_WFI }, | |
445 | REGINFO_SENTINEL | |
446 | }; | |
447 | ||
448 | static const ARMCPRegInfo not_v7_cp_reginfo[] = { | |
449 | /* Standard v6 WFI (also used in some pre-v6 cores); not in v7 (which | |
450 | * is UNPREDICTABLE; we choose to NOP as most implementations do). | |
451 | */ | |
452 | { .name = "WFI_v6", .cp = 15, .crn = 7, .crm = 0, .opc1 = 0, .opc2 = 4, | |
453 | .access = PL1_W, .type = ARM_CP_WFI }, | |
34f90529 PM |
454 | /* L1 cache lockdown. Not architectural in v6 and earlier but in practice |
455 | * implemented in 926, 946, 1026, 1136, 1176 and 11MPCore. StrongARM and | |
456 | * OMAPCP will override this space. | |
457 | */ | |
458 | { .name = "DLOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 0, .opc2 = 0, | |
459 | .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_data), | |
460 | .resetvalue = 0 }, | |
461 | { .name = "ILOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 0, .opc2 = 1, | |
462 | .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_insn), | |
463 | .resetvalue = 0 }, | |
776d4e5c PM |
464 | /* v6 doesn't have the cache ID registers but Linux reads them anyway */ |
465 | { .name = "DUMMY", .cp = 15, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = CP_ANY, | |
d4e6df63 PM |
466 | .access = PL1_R, .type = ARM_CP_CONST | ARM_CP_NO_MIGRATE, |
467 | .resetvalue = 0 }, | |
50300698 PM |
468 | /* We don't implement pre-v7 debug but most CPUs had at least a DBGDIDR; |
469 | * implementing it as RAZ means the "debug architecture version" bits | |
470 | * will read as a reserved value, which should cause Linux to not try | |
471 | * to use the debug hardware. | |
472 | */ | |
473 | { .name = "DBGDIDR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 0, | |
474 | .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
7d57f408 PM |
475 | REGINFO_SENTINEL |
476 | }; | |
477 | ||
c4241c7d PM |
478 | static void cpacr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
479 | uint64_t value) | |
2771db27 | 480 | { |
f0aff255 FA |
481 | uint32_t mask = 0; |
482 | ||
483 | /* In ARMv8 most bits of CPACR_EL1 are RES0. */ | |
484 | if (!arm_feature(env, ARM_FEATURE_V8)) { | |
485 | /* ARMv7 defines bits for unimplemented coprocessors as RAZ/WI. | |
486 | * ASEDIS [31] and D32DIS [30] are both UNK/SBZP without VFP. | |
487 | * TRCDIS [28] is RAZ/WI since we do not implement a trace macrocell. | |
488 | */ | |
489 | if (arm_feature(env, ARM_FEATURE_VFP)) { | |
490 | /* VFP coprocessor: cp10 & cp11 [23:20] */ | |
491 | mask |= (1 << 31) | (1 << 30) | (0xf << 20); | |
492 | ||
493 | if (!arm_feature(env, ARM_FEATURE_NEON)) { | |
494 | /* ASEDIS [31] bit is RAO/WI */ | |
495 | value |= (1 << 31); | |
496 | } | |
497 | ||
498 | /* VFPv3 and upwards with NEON implement 32 double precision | |
499 | * registers (D0-D31). | |
500 | */ | |
501 | if (!arm_feature(env, ARM_FEATURE_NEON) || | |
502 | !arm_feature(env, ARM_FEATURE_VFP3)) { | |
503 | /* D32DIS [30] is RAO/WI if D16-31 are not implemented. */ | |
504 | value |= (1 << 30); | |
505 | } | |
506 | } | |
507 | value &= mask; | |
2771db27 | 508 | } |
f0aff255 | 509 | env->cp15.c1_coproc = value; |
2771db27 PM |
510 | } |
511 | ||
7d57f408 PM |
512 | static const ARMCPRegInfo v6_cp_reginfo[] = { |
513 | /* prefetch by MVA in v6, NOP in v7 */ | |
514 | { .name = "MVA_prefetch", | |
515 | .cp = 15, .crn = 7, .crm = 13, .opc1 = 0, .opc2 = 1, | |
516 | .access = PL1_W, .type = ARM_CP_NOP }, | |
517 | { .name = "ISB", .cp = 15, .crn = 7, .crm = 5, .opc1 = 0, .opc2 = 4, | |
518 | .access = PL0_W, .type = ARM_CP_NOP }, | |
091fd17c | 519 | { .name = "DSB", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 4, |
7d57f408 | 520 | .access = PL0_W, .type = ARM_CP_NOP }, |
091fd17c | 521 | { .name = "DMB", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 5, |
7d57f408 | 522 | .access = PL0_W, .type = ARM_CP_NOP }, |
06d76f31 | 523 | { .name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 2, |
6cd8a264 | 524 | .access = PL1_RW, |
2f0180c5 | 525 | .fieldoffset = offsetofhigh32(CPUARMState, cp15.far_el[1]), |
06d76f31 PM |
526 | .resetvalue = 0, }, |
527 | /* Watchpoint Fault Address Register : should actually only be present | |
528 | * for 1136, 1176, 11MPCore. | |
529 | */ | |
530 | { .name = "WFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1, | |
531 | .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0, }, | |
34222fb8 PM |
532 | { .name = "CPACR", .state = ARM_CP_STATE_BOTH, .opc0 = 3, |
533 | .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 2, | |
2771db27 PM |
534 | .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c1_coproc), |
535 | .resetvalue = 0, .writefn = cpacr_write }, | |
7d57f408 PM |
536 | REGINFO_SENTINEL |
537 | }; | |
538 | ||
fcd25206 | 539 | static CPAccessResult pmreg_access(CPUARMState *env, const ARMCPRegInfo *ri) |
200ac0ef | 540 | { |
3b163b01 | 541 | /* Performance monitor registers user accessibility is controlled |
fcd25206 | 542 | * by PMUSERENR. |
200ac0ef PM |
543 | */ |
544 | if (arm_current_pl(env) == 0 && !env->cp15.c9_pmuserenr) { | |
fcd25206 | 545 | return CP_ACCESS_TRAP; |
200ac0ef | 546 | } |
fcd25206 | 547 | return CP_ACCESS_OK; |
200ac0ef PM |
548 | } |
549 | ||
7c2cb42b | 550 | #ifndef CONFIG_USER_ONLY |
c4241c7d PM |
551 | static void pmcr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
552 | uint64_t value) | |
200ac0ef | 553 | { |
c92c0687 | 554 | uint64_t temp_ticks; |
7c2cb42b | 555 | |
c92c0687 AF |
556 | temp_ticks = muldiv64(qemu_clock_get_us(QEMU_CLOCK_VIRTUAL), |
557 | get_ticks_per_sec(), 1000000); | |
7c2cb42b AF |
558 | |
559 | if (env->cp15.c9_pmcr & PMCRE) { | |
560 | /* If the counter is enabled */ | |
561 | if (env->cp15.c9_pmcr & PMCRD) { | |
562 | /* Increment once every 64 processor clock cycles */ | |
563 | env->cp15.c15_ccnt = (temp_ticks/64) - env->cp15.c15_ccnt; | |
564 | } else { | |
565 | env->cp15.c15_ccnt = temp_ticks - env->cp15.c15_ccnt; | |
566 | } | |
567 | } | |
568 | ||
569 | if (value & PMCRC) { | |
570 | /* The counter has been reset */ | |
571 | env->cp15.c15_ccnt = 0; | |
572 | } | |
573 | ||
200ac0ef PM |
574 | /* only the DP, X, D and E bits are writable */ |
575 | env->cp15.c9_pmcr &= ~0x39; | |
576 | env->cp15.c9_pmcr |= (value & 0x39); | |
7c2cb42b AF |
577 | |
578 | if (env->cp15.c9_pmcr & PMCRE) { | |
579 | if (env->cp15.c9_pmcr & PMCRD) { | |
580 | /* Increment once every 64 processor clock cycles */ | |
581 | temp_ticks /= 64; | |
582 | } | |
583 | env->cp15.c15_ccnt = temp_ticks - env->cp15.c15_ccnt; | |
584 | } | |
585 | } | |
586 | ||
587 | static uint64_t pmccntr_read(CPUARMState *env, const ARMCPRegInfo *ri) | |
588 | { | |
c92c0687 | 589 | uint64_t total_ticks; |
7c2cb42b AF |
590 | |
591 | if (!(env->cp15.c9_pmcr & PMCRE)) { | |
592 | /* Counter is disabled, do not change value */ | |
593 | return env->cp15.c15_ccnt; | |
594 | } | |
595 | ||
c92c0687 AF |
596 | total_ticks = muldiv64(qemu_clock_get_us(QEMU_CLOCK_VIRTUAL), |
597 | get_ticks_per_sec(), 1000000); | |
7c2cb42b AF |
598 | |
599 | if (env->cp15.c9_pmcr & PMCRD) { | |
600 | /* Increment once every 64 processor clock cycles */ | |
601 | total_ticks /= 64; | |
602 | } | |
603 | return total_ticks - env->cp15.c15_ccnt; | |
604 | } | |
605 | ||
606 | static void pmccntr_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
607 | uint64_t value) | |
608 | { | |
c92c0687 | 609 | uint64_t total_ticks; |
7c2cb42b AF |
610 | |
611 | if (!(env->cp15.c9_pmcr & PMCRE)) { | |
612 | /* Counter is disabled, set the absolute value */ | |
613 | env->cp15.c15_ccnt = value; | |
614 | return; | |
615 | } | |
616 | ||
c92c0687 AF |
617 | total_ticks = muldiv64(qemu_clock_get_us(QEMU_CLOCK_VIRTUAL), |
618 | get_ticks_per_sec(), 1000000); | |
7c2cb42b AF |
619 | |
620 | if (env->cp15.c9_pmcr & PMCRD) { | |
621 | /* Increment once every 64 processor clock cycles */ | |
622 | total_ticks /= 64; | |
623 | } | |
624 | env->cp15.c15_ccnt = total_ticks - value; | |
200ac0ef | 625 | } |
421c7ebd PC |
626 | |
627 | static void pmccntr_write32(CPUARMState *env, const ARMCPRegInfo *ri, | |
628 | uint64_t value) | |
629 | { | |
630 | uint64_t cur_val = pmccntr_read(env, NULL); | |
631 | ||
632 | pmccntr_write(env, ri, deposit64(cur_val, 0, 32, value)); | |
633 | } | |
634 | ||
7c2cb42b | 635 | #endif |
200ac0ef | 636 | |
c4241c7d | 637 | static void pmcntenset_write(CPUARMState *env, const ARMCPRegInfo *ri, |
200ac0ef PM |
638 | uint64_t value) |
639 | { | |
200ac0ef PM |
640 | value &= (1 << 31); |
641 | env->cp15.c9_pmcnten |= value; | |
200ac0ef PM |
642 | } |
643 | ||
c4241c7d PM |
644 | static void pmcntenclr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
645 | uint64_t value) | |
200ac0ef | 646 | { |
200ac0ef PM |
647 | value &= (1 << 31); |
648 | env->cp15.c9_pmcnten &= ~value; | |
200ac0ef PM |
649 | } |
650 | ||
c4241c7d PM |
651 | static void pmovsr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
652 | uint64_t value) | |
200ac0ef | 653 | { |
200ac0ef | 654 | env->cp15.c9_pmovsr &= ~value; |
200ac0ef PM |
655 | } |
656 | ||
c4241c7d PM |
657 | static void pmxevtyper_write(CPUARMState *env, const ARMCPRegInfo *ri, |
658 | uint64_t value) | |
200ac0ef | 659 | { |
200ac0ef | 660 | env->cp15.c9_pmxevtyper = value & 0xff; |
200ac0ef PM |
661 | } |
662 | ||
c4241c7d | 663 | static void pmuserenr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
200ac0ef PM |
664 | uint64_t value) |
665 | { | |
666 | env->cp15.c9_pmuserenr = value & 1; | |
200ac0ef PM |
667 | } |
668 | ||
c4241c7d PM |
669 | static void pmintenset_write(CPUARMState *env, const ARMCPRegInfo *ri, |
670 | uint64_t value) | |
200ac0ef PM |
671 | { |
672 | /* We have no event counters so only the C bit can be changed */ | |
673 | value &= (1 << 31); | |
674 | env->cp15.c9_pminten |= value; | |
200ac0ef PM |
675 | } |
676 | ||
c4241c7d PM |
677 | static void pmintenclr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
678 | uint64_t value) | |
200ac0ef PM |
679 | { |
680 | value &= (1 << 31); | |
681 | env->cp15.c9_pminten &= ~value; | |
200ac0ef PM |
682 | } |
683 | ||
c4241c7d PM |
684 | static void vbar_write(CPUARMState *env, const ARMCPRegInfo *ri, |
685 | uint64_t value) | |
8641136c | 686 | { |
a505d7fe PM |
687 | /* Note that even though the AArch64 view of this register has bits |
688 | * [10:0] all RES0 we can only mask the bottom 5, to comply with the | |
689 | * architectural requirements for bits which are RES0 only in some | |
690 | * contexts. (ARMv8 would permit us to do no masking at all, but ARMv7 | |
691 | * requires the bottom five bits to be RAZ/WI because they're UNK/SBZP.) | |
692 | */ | |
855ea66d | 693 | raw_write(env, ri, value & ~0x1FULL); |
8641136c NR |
694 | } |
695 | ||
c4241c7d | 696 | static uint64_t ccsidr_read(CPUARMState *env, const ARMCPRegInfo *ri) |
776d4e5c PM |
697 | { |
698 | ARMCPU *cpu = arm_env_get_cpu(env); | |
c4241c7d | 699 | return cpu->ccsidr[env->cp15.c0_cssel]; |
776d4e5c PM |
700 | } |
701 | ||
c4241c7d PM |
702 | static void csselr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
703 | uint64_t value) | |
776d4e5c | 704 | { |
8d5c773e | 705 | raw_write(env, ri, value & 0xf); |
776d4e5c PM |
706 | } |
707 | ||
1090b9c6 PM |
708 | static uint64_t isr_read(CPUARMState *env, const ARMCPRegInfo *ri) |
709 | { | |
710 | CPUState *cs = ENV_GET_CPU(env); | |
711 | uint64_t ret = 0; | |
712 | ||
713 | if (cs->interrupt_request & CPU_INTERRUPT_HARD) { | |
714 | ret |= CPSR_I; | |
715 | } | |
716 | if (cs->interrupt_request & CPU_INTERRUPT_FIQ) { | |
717 | ret |= CPSR_F; | |
718 | } | |
719 | /* External aborts are not possible in QEMU so A bit is always clear */ | |
720 | return ret; | |
721 | } | |
722 | ||
e9aa6c21 | 723 | static const ARMCPRegInfo v7_cp_reginfo[] = { |
7d57f408 PM |
724 | /* the old v6 WFI, UNPREDICTABLE in v7 but we choose to NOP */ |
725 | { .name = "NOP", .cp = 15, .crn = 7, .crm = 0, .opc1 = 0, .opc2 = 4, | |
726 | .access = PL1_W, .type = ARM_CP_NOP }, | |
200ac0ef PM |
727 | /* Performance monitors are implementation defined in v7, |
728 | * but with an ARM recommended set of registers, which we | |
729 | * follow (although we don't actually implement any counters) | |
730 | * | |
731 | * Performance registers fall into three categories: | |
732 | * (a) always UNDEF in PL0, RW in PL1 (PMINTENSET, PMINTENCLR) | |
733 | * (b) RO in PL0 (ie UNDEF on write), RW in PL1 (PMUSERENR) | |
734 | * (c) UNDEF in PL0 if PMUSERENR.EN==0, otherwise accessible (all others) | |
735 | * For the cases controlled by PMUSERENR we must set .access to PL0_RW | |
736 | * or PL0_RO as appropriate and then check PMUSERENR in the helper fn. | |
737 | */ | |
738 | { .name = "PMCNTENSET", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 1, | |
8521466b AF |
739 | .access = PL0_RW, .type = ARM_CP_NO_MIGRATE, |
740 | .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmcnten), | |
fcd25206 PM |
741 | .writefn = pmcntenset_write, |
742 | .accessfn = pmreg_access, | |
743 | .raw_writefn = raw_write }, | |
8521466b AF |
744 | { .name = "PMCNTENSET_EL0", .state = ARM_CP_STATE_AA64, |
745 | .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 1, | |
746 | .access = PL0_RW, .accessfn = pmreg_access, | |
747 | .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcnten), .resetvalue = 0, | |
748 | .writefn = pmcntenset_write, .raw_writefn = raw_write }, | |
200ac0ef | 749 | { .name = "PMCNTENCLR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 2, |
8521466b AF |
750 | .access = PL0_RW, |
751 | .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmcnten), | |
fcd25206 PM |
752 | .accessfn = pmreg_access, |
753 | .writefn = pmcntenclr_write, | |
d4e6df63 | 754 | .type = ARM_CP_NO_MIGRATE }, |
8521466b AF |
755 | { .name = "PMCNTENCLR_EL0", .state = ARM_CP_STATE_AA64, |
756 | .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 2, | |
757 | .access = PL0_RW, .accessfn = pmreg_access, | |
758 | .type = ARM_CP_NO_MIGRATE, | |
759 | .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcnten), | |
760 | .writefn = pmcntenclr_write }, | |
200ac0ef PM |
761 | { .name = "PMOVSR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 3, |
762 | .access = PL0_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_pmovsr), | |
fcd25206 PM |
763 | .accessfn = pmreg_access, |
764 | .writefn = pmovsr_write, | |
765 | .raw_writefn = raw_write }, | |
766 | /* Unimplemented so WI. */ | |
200ac0ef | 767 | { .name = "PMSWINC", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 4, |
fcd25206 | 768 | .access = PL0_W, .accessfn = pmreg_access, .type = ARM_CP_NOP }, |
200ac0ef | 769 | /* Since we don't implement any events, writing to PMSELR is UNPREDICTABLE. |
fcd25206 | 770 | * We choose to RAZ/WI. |
200ac0ef PM |
771 | */ |
772 | { .name = "PMSELR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 5, | |
fcd25206 PM |
773 | .access = PL0_RW, .type = ARM_CP_CONST, .resetvalue = 0, |
774 | .accessfn = pmreg_access }, | |
7c2cb42b | 775 | #ifndef CONFIG_USER_ONLY |
200ac0ef | 776 | { .name = "PMCCNTR", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 0, |
7c2cb42b | 777 | .access = PL0_RW, .resetvalue = 0, .type = ARM_CP_IO, |
421c7ebd | 778 | .readfn = pmccntr_read, .writefn = pmccntr_write32, |
fcd25206 | 779 | .accessfn = pmreg_access }, |
8521466b AF |
780 | { .name = "PMCCNTR_EL0", .state = ARM_CP_STATE_AA64, |
781 | .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 13, .opc2 = 0, | |
782 | .access = PL0_RW, .accessfn = pmreg_access, | |
783 | .type = ARM_CP_IO, | |
784 | .readfn = pmccntr_read, .writefn = pmccntr_write, }, | |
7c2cb42b | 785 | #endif |
8521466b AF |
786 | { .name = "PMCCFILTR_EL0", .state = ARM_CP_STATE_AA64, |
787 | .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 15, .opc2 = 7, | |
788 | .access = PL0_RW, .accessfn = pmreg_access, | |
789 | .type = ARM_CP_IO, | |
790 | .fieldoffset = offsetof(CPUARMState, cp15.pmccfiltr_el0), | |
791 | .resetvalue = 0, }, | |
200ac0ef PM |
792 | { .name = "PMXEVTYPER", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 1, |
793 | .access = PL0_RW, | |
794 | .fieldoffset = offsetof(CPUARMState, cp15.c9_pmxevtyper), | |
fcd25206 PM |
795 | .accessfn = pmreg_access, .writefn = pmxevtyper_write, |
796 | .raw_writefn = raw_write }, | |
797 | /* Unimplemented, RAZ/WI. */ | |
200ac0ef | 798 | { .name = "PMXEVCNTR", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 2, |
fcd25206 PM |
799 | .access = PL0_RW, .type = ARM_CP_CONST, .resetvalue = 0, |
800 | .accessfn = pmreg_access }, | |
200ac0ef PM |
801 | { .name = "PMUSERENR", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 0, |
802 | .access = PL0_R | PL1_RW, | |
803 | .fieldoffset = offsetof(CPUARMState, cp15.c9_pmuserenr), | |
804 | .resetvalue = 0, | |
d4e6df63 | 805 | .writefn = pmuserenr_write, .raw_writefn = raw_write }, |
200ac0ef PM |
806 | { .name = "PMINTENSET", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 1, |
807 | .access = PL1_RW, | |
808 | .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten), | |
809 | .resetvalue = 0, | |
d4e6df63 | 810 | .writefn = pmintenset_write, .raw_writefn = raw_write }, |
200ac0ef | 811 | { .name = "PMINTENCLR", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 2, |
d4e6df63 | 812 | .access = PL1_RW, .type = ARM_CP_NO_MIGRATE, |
200ac0ef | 813 | .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten), |
d4e6df63 | 814 | .resetvalue = 0, .writefn = pmintenclr_write, }, |
a505d7fe PM |
815 | { .name = "VBAR", .state = ARM_CP_STATE_BOTH, |
816 | .opc0 = 3, .crn = 12, .crm = 0, .opc1 = 0, .opc2 = 0, | |
8641136c | 817 | .access = PL1_RW, .writefn = vbar_write, |
68fdb6c5 | 818 | .fieldoffset = offsetof(CPUARMState, cp15.vbar_el[1]), |
8641136c | 819 | .resetvalue = 0 }, |
2771db27 PM |
820 | { .name = "SCR", .cp = 15, .crn = 1, .crm = 1, .opc1 = 0, .opc2 = 0, |
821 | .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c1_scr), | |
822 | .resetvalue = 0, }, | |
7da845b0 PM |
823 | { .name = "CCSIDR", .state = ARM_CP_STATE_BOTH, |
824 | .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 0, | |
d4e6df63 | 825 | .access = PL1_R, .readfn = ccsidr_read, .type = ARM_CP_NO_MIGRATE }, |
7da845b0 PM |
826 | { .name = "CSSELR", .state = ARM_CP_STATE_BOTH, |
827 | .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 2, .opc2 = 0, | |
776d4e5c PM |
828 | .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c0_cssel), |
829 | .writefn = csselr_write, .resetvalue = 0 }, | |
830 | /* Auxiliary ID register: this actually has an IMPDEF value but for now | |
831 | * just RAZ for all cores: | |
832 | */ | |
0ff644a7 PM |
833 | { .name = "AIDR", .state = ARM_CP_STATE_BOTH, |
834 | .opc0 = 3, .opc1 = 1, .crn = 0, .crm = 0, .opc2 = 7, | |
776d4e5c | 835 | .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 }, |
f32cdad5 PM |
836 | /* Auxiliary fault status registers: these also are IMPDEF, and we |
837 | * choose to RAZ/WI for all cores. | |
838 | */ | |
839 | { .name = "AFSR0_EL1", .state = ARM_CP_STATE_BOTH, | |
840 | .opc0 = 3, .opc1 = 0, .crn = 5, .crm = 1, .opc2 = 0, | |
841 | .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
842 | { .name = "AFSR1_EL1", .state = ARM_CP_STATE_BOTH, | |
843 | .opc0 = 3, .opc1 = 0, .crn = 5, .crm = 1, .opc2 = 1, | |
844 | .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
b0fe2427 PM |
845 | /* MAIR can just read-as-written because we don't implement caches |
846 | * and so don't need to care about memory attributes. | |
847 | */ | |
848 | { .name = "MAIR_EL1", .state = ARM_CP_STATE_AA64, | |
849 | .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 2, .opc2 = 0, | |
850 | .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.mair_el1), | |
851 | .resetvalue = 0 }, | |
852 | /* For non-long-descriptor page tables these are PRRR and NMRR; | |
853 | * regardless they still act as reads-as-written for QEMU. | |
854 | * The override is necessary because of the overly-broad TLB_LOCKDOWN | |
855 | * definition. | |
856 | */ | |
857 | { .name = "MAIR0", .state = ARM_CP_STATE_AA32, .type = ARM_CP_OVERRIDE, | |
858 | .cp = 15, .opc1 = 0, .crn = 10, .crm = 2, .opc2 = 0, .access = PL1_RW, | |
859 | .fieldoffset = offsetoflow32(CPUARMState, cp15.mair_el1), | |
860 | .resetfn = arm_cp_reset_ignore }, | |
861 | { .name = "MAIR1", .state = ARM_CP_STATE_AA32, .type = ARM_CP_OVERRIDE, | |
862 | .cp = 15, .opc1 = 0, .crn = 10, .crm = 2, .opc2 = 1, .access = PL1_RW, | |
863 | .fieldoffset = offsetofhigh32(CPUARMState, cp15.mair_el1), | |
864 | .resetfn = arm_cp_reset_ignore }, | |
1090b9c6 PM |
865 | { .name = "ISR_EL1", .state = ARM_CP_STATE_BOTH, |
866 | .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 1, .opc2 = 0, | |
867 | .type = ARM_CP_NO_MIGRATE, .access = PL1_R, .readfn = isr_read }, | |
e9aa6c21 PM |
868 | REGINFO_SENTINEL |
869 | }; | |
870 | ||
c4241c7d PM |
871 | static void teecr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
872 | uint64_t value) | |
c326b979 PM |
873 | { |
874 | value &= 1; | |
875 | env->teecr = value; | |
c326b979 PM |
876 | } |
877 | ||
c4241c7d | 878 | static CPAccessResult teehbr_access(CPUARMState *env, const ARMCPRegInfo *ri) |
c326b979 | 879 | { |
c326b979 | 880 | if (arm_current_pl(env) == 0 && (env->teecr & 1)) { |
92611c00 | 881 | return CP_ACCESS_TRAP; |
c326b979 | 882 | } |
92611c00 | 883 | return CP_ACCESS_OK; |
c326b979 PM |
884 | } |
885 | ||
886 | static const ARMCPRegInfo t2ee_cp_reginfo[] = { | |
887 | { .name = "TEECR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 6, .opc2 = 0, | |
888 | .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, teecr), | |
889 | .resetvalue = 0, | |
890 | .writefn = teecr_write }, | |
891 | { .name = "TEEHBR", .cp = 14, .crn = 1, .crm = 0, .opc1 = 6, .opc2 = 0, | |
892 | .access = PL0_RW, .fieldoffset = offsetof(CPUARMState, teehbr), | |
92611c00 | 893 | .accessfn = teehbr_access, .resetvalue = 0 }, |
c326b979 PM |
894 | REGINFO_SENTINEL |
895 | }; | |
896 | ||
4d31c596 | 897 | static const ARMCPRegInfo v6k_cp_reginfo[] = { |
e4fe830b PM |
898 | { .name = "TPIDR_EL0", .state = ARM_CP_STATE_AA64, |
899 | .opc0 = 3, .opc1 = 3, .opc2 = 2, .crn = 13, .crm = 0, | |
900 | .access = PL0_RW, | |
901 | .fieldoffset = offsetof(CPUARMState, cp15.tpidr_el0), .resetvalue = 0 }, | |
4d31c596 PM |
902 | { .name = "TPIDRURW", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 2, |
903 | .access = PL0_RW, | |
e4fe830b PM |
904 | .fieldoffset = offsetoflow32(CPUARMState, cp15.tpidr_el0), |
905 | .resetfn = arm_cp_reset_ignore }, | |
906 | { .name = "TPIDRRO_EL0", .state = ARM_CP_STATE_AA64, | |
907 | .opc0 = 3, .opc1 = 3, .opc2 = 3, .crn = 13, .crm = 0, | |
908 | .access = PL0_R|PL1_W, | |
909 | .fieldoffset = offsetof(CPUARMState, cp15.tpidrro_el0), .resetvalue = 0 }, | |
4d31c596 PM |
910 | { .name = "TPIDRURO", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 3, |
911 | .access = PL0_R|PL1_W, | |
e4fe830b PM |
912 | .fieldoffset = offsetoflow32(CPUARMState, cp15.tpidrro_el0), |
913 | .resetfn = arm_cp_reset_ignore }, | |
914 | { .name = "TPIDR_EL1", .state = ARM_CP_STATE_BOTH, | |
915 | .opc0 = 3, .opc1 = 0, .opc2 = 4, .crn = 13, .crm = 0, | |
4d31c596 | 916 | .access = PL1_RW, |
e4fe830b | 917 | .fieldoffset = offsetof(CPUARMState, cp15.tpidr_el1), .resetvalue = 0 }, |
4d31c596 PM |
918 | REGINFO_SENTINEL |
919 | }; | |
920 | ||
55d284af PM |
921 | #ifndef CONFIG_USER_ONLY |
922 | ||
00108f2d PM |
923 | static CPAccessResult gt_cntfrq_access(CPUARMState *env, const ARMCPRegInfo *ri) |
924 | { | |
925 | /* CNTFRQ: not visible from PL0 if both PL0PCTEN and PL0VCTEN are zero */ | |
926 | if (arm_current_pl(env) == 0 && !extract32(env->cp15.c14_cntkctl, 0, 2)) { | |
927 | return CP_ACCESS_TRAP; | |
928 | } | |
929 | return CP_ACCESS_OK; | |
930 | } | |
931 | ||
932 | static CPAccessResult gt_counter_access(CPUARMState *env, int timeridx) | |
933 | { | |
934 | /* CNT[PV]CT: not visible from PL0 if ELO[PV]CTEN is zero */ | |
935 | if (arm_current_pl(env) == 0 && | |
936 | !extract32(env->cp15.c14_cntkctl, timeridx, 1)) { | |
937 | return CP_ACCESS_TRAP; | |
938 | } | |
939 | return CP_ACCESS_OK; | |
940 | } | |
941 | ||
942 | static CPAccessResult gt_timer_access(CPUARMState *env, int timeridx) | |
943 | { | |
944 | /* CNT[PV]_CVAL, CNT[PV]_CTL, CNT[PV]_TVAL: not visible from PL0 if | |
945 | * EL0[PV]TEN is zero. | |
946 | */ | |
947 | if (arm_current_pl(env) == 0 && | |
948 | !extract32(env->cp15.c14_cntkctl, 9 - timeridx, 1)) { | |
949 | return CP_ACCESS_TRAP; | |
950 | } | |
951 | return CP_ACCESS_OK; | |
952 | } | |
953 | ||
954 | static CPAccessResult gt_pct_access(CPUARMState *env, | |
955 | const ARMCPRegInfo *ri) | |
956 | { | |
957 | return gt_counter_access(env, GTIMER_PHYS); | |
958 | } | |
959 | ||
960 | static CPAccessResult gt_vct_access(CPUARMState *env, | |
961 | const ARMCPRegInfo *ri) | |
962 | { | |
963 | return gt_counter_access(env, GTIMER_VIRT); | |
964 | } | |
965 | ||
966 | static CPAccessResult gt_ptimer_access(CPUARMState *env, const ARMCPRegInfo *ri) | |
967 | { | |
968 | return gt_timer_access(env, GTIMER_PHYS); | |
969 | } | |
970 | ||
971 | static CPAccessResult gt_vtimer_access(CPUARMState *env, const ARMCPRegInfo *ri) | |
972 | { | |
973 | return gt_timer_access(env, GTIMER_VIRT); | |
974 | } | |
975 | ||
55d284af PM |
976 | static uint64_t gt_get_countervalue(CPUARMState *env) |
977 | { | |
bc72ad67 | 978 | return qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) / GTIMER_SCALE; |
55d284af PM |
979 | } |
980 | ||
981 | static void gt_recalc_timer(ARMCPU *cpu, int timeridx) | |
982 | { | |
983 | ARMGenericTimer *gt = &cpu->env.cp15.c14_timer[timeridx]; | |
984 | ||
985 | if (gt->ctl & 1) { | |
986 | /* Timer enabled: calculate and set current ISTATUS, irq, and | |
987 | * reset timer to when ISTATUS next has to change | |
988 | */ | |
989 | uint64_t count = gt_get_countervalue(&cpu->env); | |
990 | /* Note that this must be unsigned 64 bit arithmetic: */ | |
991 | int istatus = count >= gt->cval; | |
992 | uint64_t nexttick; | |
993 | ||
994 | gt->ctl = deposit32(gt->ctl, 2, 1, istatus); | |
995 | qemu_set_irq(cpu->gt_timer_outputs[timeridx], | |
996 | (istatus && !(gt->ctl & 2))); | |
997 | if (istatus) { | |
998 | /* Next transition is when count rolls back over to zero */ | |
999 | nexttick = UINT64_MAX; | |
1000 | } else { | |
1001 | /* Next transition is when we hit cval */ | |
1002 | nexttick = gt->cval; | |
1003 | } | |
1004 | /* Note that the desired next expiry time might be beyond the | |
1005 | * signed-64-bit range of a QEMUTimer -- in this case we just | |
1006 | * set the timer for as far in the future as possible. When the | |
1007 | * timer expires we will reset the timer for any remaining period. | |
1008 | */ | |
1009 | if (nexttick > INT64_MAX / GTIMER_SCALE) { | |
1010 | nexttick = INT64_MAX / GTIMER_SCALE; | |
1011 | } | |
bc72ad67 | 1012 | timer_mod(cpu->gt_timer[timeridx], nexttick); |
55d284af PM |
1013 | } else { |
1014 | /* Timer disabled: ISTATUS and timer output always clear */ | |
1015 | gt->ctl &= ~4; | |
1016 | qemu_set_irq(cpu->gt_timer_outputs[timeridx], 0); | |
bc72ad67 | 1017 | timer_del(cpu->gt_timer[timeridx]); |
55d284af PM |
1018 | } |
1019 | } | |
1020 | ||
55d284af PM |
1021 | static void gt_cnt_reset(CPUARMState *env, const ARMCPRegInfo *ri) |
1022 | { | |
1023 | ARMCPU *cpu = arm_env_get_cpu(env); | |
1024 | int timeridx = ri->opc1 & 1; | |
1025 | ||
bc72ad67 | 1026 | timer_del(cpu->gt_timer[timeridx]); |
55d284af PM |
1027 | } |
1028 | ||
c4241c7d | 1029 | static uint64_t gt_cnt_read(CPUARMState *env, const ARMCPRegInfo *ri) |
55d284af | 1030 | { |
c4241c7d | 1031 | return gt_get_countervalue(env); |
55d284af PM |
1032 | } |
1033 | ||
c4241c7d PM |
1034 | static void gt_cval_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1035 | uint64_t value) | |
55d284af PM |
1036 | { |
1037 | int timeridx = ri->opc1 & 1; | |
1038 | ||
1039 | env->cp15.c14_timer[timeridx].cval = value; | |
1040 | gt_recalc_timer(arm_env_get_cpu(env), timeridx); | |
55d284af | 1041 | } |
c4241c7d PM |
1042 | |
1043 | static uint64_t gt_tval_read(CPUARMState *env, const ARMCPRegInfo *ri) | |
55d284af PM |
1044 | { |
1045 | int timeridx = ri->crm & 1; | |
1046 | ||
c4241c7d PM |
1047 | return (uint32_t)(env->cp15.c14_timer[timeridx].cval - |
1048 | gt_get_countervalue(env)); | |
55d284af PM |
1049 | } |
1050 | ||
c4241c7d PM |
1051 | static void gt_tval_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1052 | uint64_t value) | |
55d284af PM |
1053 | { |
1054 | int timeridx = ri->crm & 1; | |
1055 | ||
1056 | env->cp15.c14_timer[timeridx].cval = gt_get_countervalue(env) + | |
1057 | + sextract64(value, 0, 32); | |
1058 | gt_recalc_timer(arm_env_get_cpu(env), timeridx); | |
55d284af PM |
1059 | } |
1060 | ||
c4241c7d PM |
1061 | static void gt_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1062 | uint64_t value) | |
55d284af PM |
1063 | { |
1064 | ARMCPU *cpu = arm_env_get_cpu(env); | |
1065 | int timeridx = ri->crm & 1; | |
1066 | uint32_t oldval = env->cp15.c14_timer[timeridx].ctl; | |
1067 | ||
d3afacc7 | 1068 | env->cp15.c14_timer[timeridx].ctl = deposit64(oldval, 0, 2, value); |
55d284af PM |
1069 | if ((oldval ^ value) & 1) { |
1070 | /* Enable toggled */ | |
1071 | gt_recalc_timer(cpu, timeridx); | |
d3afacc7 | 1072 | } else if ((oldval ^ value) & 2) { |
55d284af PM |
1073 | /* IMASK toggled: don't need to recalculate, |
1074 | * just set the interrupt line based on ISTATUS | |
1075 | */ | |
1076 | qemu_set_irq(cpu->gt_timer_outputs[timeridx], | |
d3afacc7 | 1077 | (oldval & 4) && !(value & 2)); |
55d284af | 1078 | } |
55d284af PM |
1079 | } |
1080 | ||
1081 | void arm_gt_ptimer_cb(void *opaque) | |
1082 | { | |
1083 | ARMCPU *cpu = opaque; | |
1084 | ||
1085 | gt_recalc_timer(cpu, GTIMER_PHYS); | |
1086 | } | |
1087 | ||
1088 | void arm_gt_vtimer_cb(void *opaque) | |
1089 | { | |
1090 | ARMCPU *cpu = opaque; | |
1091 | ||
1092 | gt_recalc_timer(cpu, GTIMER_VIRT); | |
1093 | } | |
1094 | ||
1095 | static const ARMCPRegInfo generic_timer_cp_reginfo[] = { | |
1096 | /* Note that CNTFRQ is purely reads-as-written for the benefit | |
1097 | * of software; writing it doesn't actually change the timer frequency. | |
1098 | * Our reset value matches the fixed frequency we implement the timer at. | |
1099 | */ | |
1100 | { .name = "CNTFRQ", .cp = 15, .crn = 14, .crm = 0, .opc1 = 0, .opc2 = 0, | |
a7adc4b7 PM |
1101 | .type = ARM_CP_NO_MIGRATE, |
1102 | .access = PL1_RW | PL0_R, .accessfn = gt_cntfrq_access, | |
1103 | .fieldoffset = offsetoflow32(CPUARMState, cp15.c14_cntfrq), | |
1104 | .resetfn = arm_cp_reset_ignore, | |
1105 | }, | |
1106 | { .name = "CNTFRQ_EL0", .state = ARM_CP_STATE_AA64, | |
1107 | .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 0, | |
1108 | .access = PL1_RW | PL0_R, .accessfn = gt_cntfrq_access, | |
55d284af PM |
1109 | .fieldoffset = offsetof(CPUARMState, cp15.c14_cntfrq), |
1110 | .resetvalue = (1000 * 1000 * 1000) / GTIMER_SCALE, | |
55d284af PM |
1111 | }, |
1112 | /* overall control: mostly access permissions */ | |
a7adc4b7 PM |
1113 | { .name = "CNTKCTL", .state = ARM_CP_STATE_BOTH, |
1114 | .opc0 = 3, .opc1 = 0, .crn = 14, .crm = 1, .opc2 = 0, | |
55d284af PM |
1115 | .access = PL1_RW, |
1116 | .fieldoffset = offsetof(CPUARMState, cp15.c14_cntkctl), | |
1117 | .resetvalue = 0, | |
1118 | }, | |
1119 | /* per-timer control */ | |
1120 | { .name = "CNTP_CTL", .cp = 15, .crn = 14, .crm = 2, .opc1 = 0, .opc2 = 1, | |
a7adc4b7 PM |
1121 | .type = ARM_CP_IO | ARM_CP_NO_MIGRATE, .access = PL1_RW | PL0_R, |
1122 | .accessfn = gt_ptimer_access, | |
1123 | .fieldoffset = offsetoflow32(CPUARMState, | |
1124 | cp15.c14_timer[GTIMER_PHYS].ctl), | |
1125 | .resetfn = arm_cp_reset_ignore, | |
1126 | .writefn = gt_ctl_write, .raw_writefn = raw_write, | |
1127 | }, | |
1128 | { .name = "CNTP_CTL_EL0", .state = ARM_CP_STATE_AA64, | |
1129 | .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 2, .opc2 = 1, | |
55d284af | 1130 | .type = ARM_CP_IO, .access = PL1_RW | PL0_R, |
a7adc4b7 | 1131 | .accessfn = gt_ptimer_access, |
55d284af PM |
1132 | .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].ctl), |
1133 | .resetvalue = 0, | |
00108f2d | 1134 | .writefn = gt_ctl_write, .raw_writefn = raw_write, |
55d284af PM |
1135 | }, |
1136 | { .name = "CNTV_CTL", .cp = 15, .crn = 14, .crm = 3, .opc1 = 0, .opc2 = 1, | |
a7adc4b7 PM |
1137 | .type = ARM_CP_IO | ARM_CP_NO_MIGRATE, .access = PL1_RW | PL0_R, |
1138 | .accessfn = gt_vtimer_access, | |
1139 | .fieldoffset = offsetoflow32(CPUARMState, | |
1140 | cp15.c14_timer[GTIMER_VIRT].ctl), | |
1141 | .resetfn = arm_cp_reset_ignore, | |
1142 | .writefn = gt_ctl_write, .raw_writefn = raw_write, | |
1143 | }, | |
1144 | { .name = "CNTV_CTL_EL0", .state = ARM_CP_STATE_AA64, | |
1145 | .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 3, .opc2 = 1, | |
55d284af | 1146 | .type = ARM_CP_IO, .access = PL1_RW | PL0_R, |
a7adc4b7 | 1147 | .accessfn = gt_vtimer_access, |
55d284af PM |
1148 | .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].ctl), |
1149 | .resetvalue = 0, | |
00108f2d | 1150 | .writefn = gt_ctl_write, .raw_writefn = raw_write, |
55d284af PM |
1151 | }, |
1152 | /* TimerValue views: a 32 bit downcounting view of the underlying state */ | |
1153 | { .name = "CNTP_TVAL", .cp = 15, .crn = 14, .crm = 2, .opc1 = 0, .opc2 = 0, | |
1154 | .type = ARM_CP_NO_MIGRATE | ARM_CP_IO, .access = PL1_RW | PL0_R, | |
00108f2d | 1155 | .accessfn = gt_ptimer_access, |
55d284af PM |
1156 | .readfn = gt_tval_read, .writefn = gt_tval_write, |
1157 | }, | |
a7adc4b7 PM |
1158 | { .name = "CNTP_TVAL_EL0", .state = ARM_CP_STATE_AA64, |
1159 | .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 2, .opc2 = 0, | |
1160 | .type = ARM_CP_NO_MIGRATE | ARM_CP_IO, .access = PL1_RW | PL0_R, | |
1161 | .readfn = gt_tval_read, .writefn = gt_tval_write, | |
1162 | }, | |
55d284af PM |
1163 | { .name = "CNTV_TVAL", .cp = 15, .crn = 14, .crm = 3, .opc1 = 0, .opc2 = 0, |
1164 | .type = ARM_CP_NO_MIGRATE | ARM_CP_IO, .access = PL1_RW | PL0_R, | |
00108f2d | 1165 | .accessfn = gt_vtimer_access, |
55d284af PM |
1166 | .readfn = gt_tval_read, .writefn = gt_tval_write, |
1167 | }, | |
a7adc4b7 PM |
1168 | { .name = "CNTV_TVAL_EL0", .state = ARM_CP_STATE_AA64, |
1169 | .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 3, .opc2 = 0, | |
1170 | .type = ARM_CP_NO_MIGRATE | ARM_CP_IO, .access = PL1_RW | PL0_R, | |
1171 | .readfn = gt_tval_read, .writefn = gt_tval_write, | |
1172 | }, | |
55d284af PM |
1173 | /* The counter itself */ |
1174 | { .name = "CNTPCT", .cp = 15, .crm = 14, .opc1 = 0, | |
1175 | .access = PL0_R, .type = ARM_CP_64BIT | ARM_CP_NO_MIGRATE | ARM_CP_IO, | |
00108f2d | 1176 | .accessfn = gt_pct_access, |
a7adc4b7 PM |
1177 | .readfn = gt_cnt_read, .resetfn = arm_cp_reset_ignore, |
1178 | }, | |
1179 | { .name = "CNTPCT_EL0", .state = ARM_CP_STATE_AA64, | |
1180 | .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 1, | |
1181 | .access = PL0_R, .type = ARM_CP_NO_MIGRATE | ARM_CP_IO, | |
1182 | .accessfn = gt_pct_access, | |
55d284af PM |
1183 | .readfn = gt_cnt_read, .resetfn = gt_cnt_reset, |
1184 | }, | |
1185 | { .name = "CNTVCT", .cp = 15, .crm = 14, .opc1 = 1, | |
1186 | .access = PL0_R, .type = ARM_CP_64BIT | ARM_CP_NO_MIGRATE | ARM_CP_IO, | |
00108f2d | 1187 | .accessfn = gt_vct_access, |
a7adc4b7 PM |
1188 | .readfn = gt_cnt_read, .resetfn = arm_cp_reset_ignore, |
1189 | }, | |
1190 | { .name = "CNTVCT_EL0", .state = ARM_CP_STATE_AA64, | |
1191 | .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 2, | |
1192 | .access = PL0_R, .type = ARM_CP_NO_MIGRATE | ARM_CP_IO, | |
1193 | .accessfn = gt_vct_access, | |
55d284af PM |
1194 | .readfn = gt_cnt_read, .resetfn = gt_cnt_reset, |
1195 | }, | |
1196 | /* Comparison value, indicating when the timer goes off */ | |
1197 | { .name = "CNTP_CVAL", .cp = 15, .crm = 14, .opc1 = 2, | |
1198 | .access = PL1_RW | PL0_R, | |
a7adc4b7 | 1199 | .type = ARM_CP_64BIT | ARM_CP_IO | ARM_CP_NO_MIGRATE, |
55d284af | 1200 | .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].cval), |
a7adc4b7 PM |
1201 | .accessfn = gt_ptimer_access, .resetfn = arm_cp_reset_ignore, |
1202 | .writefn = gt_cval_write, .raw_writefn = raw_write, | |
1203 | }, | |
1204 | { .name = "CNTP_CVAL_EL0", .state = ARM_CP_STATE_AA64, | |
1205 | .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 2, .opc2 = 2, | |
1206 | .access = PL1_RW | PL0_R, | |
1207 | .type = ARM_CP_IO, | |
1208 | .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].cval), | |
1209 | .resetvalue = 0, .accessfn = gt_vtimer_access, | |
00108f2d | 1210 | .writefn = gt_cval_write, .raw_writefn = raw_write, |
55d284af PM |
1211 | }, |
1212 | { .name = "CNTV_CVAL", .cp = 15, .crm = 14, .opc1 = 3, | |
1213 | .access = PL1_RW | PL0_R, | |
a7adc4b7 | 1214 | .type = ARM_CP_64BIT | ARM_CP_IO | ARM_CP_NO_MIGRATE, |
55d284af | 1215 | .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].cval), |
a7adc4b7 PM |
1216 | .accessfn = gt_vtimer_access, .resetfn = arm_cp_reset_ignore, |
1217 | .writefn = gt_cval_write, .raw_writefn = raw_write, | |
1218 | }, | |
1219 | { .name = "CNTV_CVAL_EL0", .state = ARM_CP_STATE_AA64, | |
1220 | .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 3, .opc2 = 2, | |
1221 | .access = PL1_RW | PL0_R, | |
1222 | .type = ARM_CP_IO, | |
1223 | .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].cval), | |
1224 | .resetvalue = 0, .accessfn = gt_vtimer_access, | |
00108f2d | 1225 | .writefn = gt_cval_write, .raw_writefn = raw_write, |
55d284af PM |
1226 | }, |
1227 | REGINFO_SENTINEL | |
1228 | }; | |
1229 | ||
1230 | #else | |
1231 | /* In user-mode none of the generic timer registers are accessible, | |
bc72ad67 | 1232 | * and their implementation depends on QEMU_CLOCK_VIRTUAL and qdev gpio outputs, |
55d284af PM |
1233 | * so instead just don't register any of them. |
1234 | */ | |
6cc7a3ae | 1235 | static const ARMCPRegInfo generic_timer_cp_reginfo[] = { |
6cc7a3ae PM |
1236 | REGINFO_SENTINEL |
1237 | }; | |
1238 | ||
55d284af PM |
1239 | #endif |
1240 | ||
c4241c7d | 1241 | static void par_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) |
4a501606 | 1242 | { |
891a2fe7 | 1243 | if (arm_feature(env, ARM_FEATURE_LPAE)) { |
8d5c773e | 1244 | raw_write(env, ri, value); |
891a2fe7 | 1245 | } else if (arm_feature(env, ARM_FEATURE_V7)) { |
8d5c773e | 1246 | raw_write(env, ri, value & 0xfffff6ff); |
4a501606 | 1247 | } else { |
8d5c773e | 1248 | raw_write(env, ri, value & 0xfffff1ff); |
4a501606 | 1249 | } |
4a501606 PM |
1250 | } |
1251 | ||
1252 | #ifndef CONFIG_USER_ONLY | |
1253 | /* get_phys_addr() isn't present for user-mode-only targets */ | |
702a9357 | 1254 | |
92611c00 PM |
1255 | static CPAccessResult ats_access(CPUARMState *env, const ARMCPRegInfo *ri) |
1256 | { | |
1257 | if (ri->opc2 & 4) { | |
1258 | /* Other states are only available with TrustZone; in | |
1259 | * a non-TZ implementation these registers don't exist | |
1260 | * at all, which is an Uncategorized trap. This underdecoding | |
1261 | * is safe because the reginfo is NO_MIGRATE. | |
1262 | */ | |
1263 | return CP_ACCESS_TRAP_UNCATEGORIZED; | |
1264 | } | |
1265 | return CP_ACCESS_OK; | |
1266 | } | |
1267 | ||
c4241c7d | 1268 | static void ats_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) |
4a501606 | 1269 | { |
a8170e5e | 1270 | hwaddr phys_addr; |
4a501606 PM |
1271 | target_ulong page_size; |
1272 | int prot; | |
1273 | int ret, is_user = ri->opc2 & 2; | |
1274 | int access_type = ri->opc2 & 1; | |
1275 | ||
4a501606 PM |
1276 | ret = get_phys_addr(env, value, access_type, is_user, |
1277 | &phys_addr, &prot, &page_size); | |
702a9357 PM |
1278 | if (extended_addresses_enabled(env)) { |
1279 | /* ret is a DFSR/IFSR value for the long descriptor | |
1280 | * translation table format, but with WnR always clear. | |
1281 | * Convert it to a 64-bit PAR. | |
1282 | */ | |
1283 | uint64_t par64 = (1 << 11); /* LPAE bit always set */ | |
1284 | if (ret == 0) { | |
1285 | par64 |= phys_addr & ~0xfffULL; | |
1286 | /* We don't set the ATTR or SH fields in the PAR. */ | |
4a501606 | 1287 | } else { |
702a9357 PM |
1288 | par64 |= 1; /* F */ |
1289 | par64 |= (ret & 0x3f) << 1; /* FS */ | |
1290 | /* Note that S2WLK and FSTAGE are always zero, because we don't | |
1291 | * implement virtualization and therefore there can't be a stage 2 | |
1292 | * fault. | |
1293 | */ | |
4a501606 | 1294 | } |
19525524 | 1295 | env->cp15.par_el1 = par64; |
4a501606 | 1296 | } else { |
702a9357 PM |
1297 | /* ret is a DFSR/IFSR value for the short descriptor |
1298 | * translation table format (with WnR always clear). | |
1299 | * Convert it to a 32-bit PAR. | |
1300 | */ | |
1301 | if (ret == 0) { | |
1302 | /* We do not set any attribute bits in the PAR */ | |
1303 | if (page_size == (1 << 24) | |
1304 | && arm_feature(env, ARM_FEATURE_V7)) { | |
19525524 | 1305 | env->cp15.par_el1 = (phys_addr & 0xff000000) | 1 << 1; |
702a9357 | 1306 | } else { |
19525524 | 1307 | env->cp15.par_el1 = phys_addr & 0xfffff000; |
702a9357 PM |
1308 | } |
1309 | } else { | |
19525524 | 1310 | env->cp15.par_el1 = ((ret & (1 << 10)) >> 5) | |
775fda92 | 1311 | ((ret & (1 << 12)) >> 6) | |
702a9357 PM |
1312 | ((ret & 0xf) << 1) | 1; |
1313 | } | |
4a501606 | 1314 | } |
4a501606 PM |
1315 | } |
1316 | #endif | |
1317 | ||
1318 | static const ARMCPRegInfo vapa_cp_reginfo[] = { | |
1319 | { .name = "PAR", .cp = 15, .crn = 7, .crm = 4, .opc1 = 0, .opc2 = 0, | |
1320 | .access = PL1_RW, .resetvalue = 0, | |
19525524 | 1321 | .fieldoffset = offsetoflow32(CPUARMState, cp15.par_el1), |
4a501606 PM |
1322 | .writefn = par_write }, |
1323 | #ifndef CONFIG_USER_ONLY | |
1324 | { .name = "ATS", .cp = 15, .crn = 7, .crm = 8, .opc1 = 0, .opc2 = CP_ANY, | |
92611c00 PM |
1325 | .access = PL1_W, .accessfn = ats_access, |
1326 | .writefn = ats_write, .type = ARM_CP_NO_MIGRATE }, | |
4a501606 PM |
1327 | #endif |
1328 | REGINFO_SENTINEL | |
1329 | }; | |
1330 | ||
18032bec PM |
1331 | /* Return basic MPU access permission bits. */ |
1332 | static uint32_t simple_mpu_ap_bits(uint32_t val) | |
1333 | { | |
1334 | uint32_t ret; | |
1335 | uint32_t mask; | |
1336 | int i; | |
1337 | ret = 0; | |
1338 | mask = 3; | |
1339 | for (i = 0; i < 16; i += 2) { | |
1340 | ret |= (val >> i) & mask; | |
1341 | mask <<= 2; | |
1342 | } | |
1343 | return ret; | |
1344 | } | |
1345 | ||
1346 | /* Pad basic MPU access permission bits to extended format. */ | |
1347 | static uint32_t extended_mpu_ap_bits(uint32_t val) | |
1348 | { | |
1349 | uint32_t ret; | |
1350 | uint32_t mask; | |
1351 | int i; | |
1352 | ret = 0; | |
1353 | mask = 3; | |
1354 | for (i = 0; i < 16; i += 2) { | |
1355 | ret |= (val & mask) << i; | |
1356 | mask <<= 2; | |
1357 | } | |
1358 | return ret; | |
1359 | } | |
1360 | ||
c4241c7d PM |
1361 | static void pmsav5_data_ap_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1362 | uint64_t value) | |
18032bec | 1363 | { |
7e09797c | 1364 | env->cp15.pmsav5_data_ap = extended_mpu_ap_bits(value); |
18032bec PM |
1365 | } |
1366 | ||
c4241c7d | 1367 | static uint64_t pmsav5_data_ap_read(CPUARMState *env, const ARMCPRegInfo *ri) |
18032bec | 1368 | { |
7e09797c | 1369 | return simple_mpu_ap_bits(env->cp15.pmsav5_data_ap); |
18032bec PM |
1370 | } |
1371 | ||
c4241c7d PM |
1372 | static void pmsav5_insn_ap_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1373 | uint64_t value) | |
18032bec | 1374 | { |
7e09797c | 1375 | env->cp15.pmsav5_insn_ap = extended_mpu_ap_bits(value); |
18032bec PM |
1376 | } |
1377 | ||
c4241c7d | 1378 | static uint64_t pmsav5_insn_ap_read(CPUARMState *env, const ARMCPRegInfo *ri) |
18032bec | 1379 | { |
7e09797c | 1380 | return simple_mpu_ap_bits(env->cp15.pmsav5_insn_ap); |
18032bec PM |
1381 | } |
1382 | ||
1383 | static const ARMCPRegInfo pmsav5_cp_reginfo[] = { | |
1384 | { .name = "DATA_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 0, | |
d4e6df63 | 1385 | .access = PL1_RW, .type = ARM_CP_NO_MIGRATE, |
7e09797c PM |
1386 | .fieldoffset = offsetof(CPUARMState, cp15.pmsav5_data_ap), |
1387 | .resetvalue = 0, | |
18032bec PM |
1388 | .readfn = pmsav5_data_ap_read, .writefn = pmsav5_data_ap_write, }, |
1389 | { .name = "INSN_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 1, | |
d4e6df63 | 1390 | .access = PL1_RW, .type = ARM_CP_NO_MIGRATE, |
7e09797c PM |
1391 | .fieldoffset = offsetof(CPUARMState, cp15.pmsav5_insn_ap), |
1392 | .resetvalue = 0, | |
18032bec PM |
1393 | .readfn = pmsav5_insn_ap_read, .writefn = pmsav5_insn_ap_write, }, |
1394 | { .name = "DATA_EXT_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 2, | |
1395 | .access = PL1_RW, | |
7e09797c PM |
1396 | .fieldoffset = offsetof(CPUARMState, cp15.pmsav5_data_ap), |
1397 | .resetvalue = 0, }, | |
18032bec PM |
1398 | { .name = "INSN_EXT_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 3, |
1399 | .access = PL1_RW, | |
7e09797c PM |
1400 | .fieldoffset = offsetof(CPUARMState, cp15.pmsav5_insn_ap), |
1401 | .resetvalue = 0, }, | |
ecce5c3c PM |
1402 | { .name = "DCACHE_CFG", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 0, |
1403 | .access = PL1_RW, | |
1404 | .fieldoffset = offsetof(CPUARMState, cp15.c2_data), .resetvalue = 0, }, | |
1405 | { .name = "ICACHE_CFG", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 1, | |
1406 | .access = PL1_RW, | |
1407 | .fieldoffset = offsetof(CPUARMState, cp15.c2_insn), .resetvalue = 0, }, | |
06d76f31 | 1408 | /* Protection region base and size registers */ |
e508a92b PM |
1409 | { .name = "946_PRBS0", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, |
1410 | .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0, | |
1411 | .fieldoffset = offsetof(CPUARMState, cp15.c6_region[0]) }, | |
1412 | { .name = "946_PRBS1", .cp = 15, .crn = 6, .crm = 1, .opc1 = 0, | |
1413 | .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0, | |
1414 | .fieldoffset = offsetof(CPUARMState, cp15.c6_region[1]) }, | |
1415 | { .name = "946_PRBS2", .cp = 15, .crn = 6, .crm = 2, .opc1 = 0, | |
1416 | .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0, | |
1417 | .fieldoffset = offsetof(CPUARMState, cp15.c6_region[2]) }, | |
1418 | { .name = "946_PRBS3", .cp = 15, .crn = 6, .crm = 3, .opc1 = 0, | |
1419 | .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0, | |
1420 | .fieldoffset = offsetof(CPUARMState, cp15.c6_region[3]) }, | |
1421 | { .name = "946_PRBS4", .cp = 15, .crn = 6, .crm = 4, .opc1 = 0, | |
1422 | .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0, | |
1423 | .fieldoffset = offsetof(CPUARMState, cp15.c6_region[4]) }, | |
1424 | { .name = "946_PRBS5", .cp = 15, .crn = 6, .crm = 5, .opc1 = 0, | |
1425 | .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0, | |
1426 | .fieldoffset = offsetof(CPUARMState, cp15.c6_region[5]) }, | |
1427 | { .name = "946_PRBS6", .cp = 15, .crn = 6, .crm = 6, .opc1 = 0, | |
1428 | .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0, | |
1429 | .fieldoffset = offsetof(CPUARMState, cp15.c6_region[6]) }, | |
1430 | { .name = "946_PRBS7", .cp = 15, .crn = 6, .crm = 7, .opc1 = 0, | |
1431 | .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0, | |
1432 | .fieldoffset = offsetof(CPUARMState, cp15.c6_region[7]) }, | |
18032bec PM |
1433 | REGINFO_SENTINEL |
1434 | }; | |
1435 | ||
c4241c7d PM |
1436 | static void vmsa_ttbcr_raw_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1437 | uint64_t value) | |
ecce5c3c | 1438 | { |
2ebcebe2 PM |
1439 | int maskshift = extract32(value, 0, 3); |
1440 | ||
e389be16 FA |
1441 | if (!arm_feature(env, ARM_FEATURE_V8)) { |
1442 | if (arm_feature(env, ARM_FEATURE_LPAE) && (value & TTBCR_EAE)) { | |
1443 | /* Pre ARMv8 bits [21:19], [15:14] and [6:3] are UNK/SBZP when | |
1444 | * using Long-desciptor translation table format */ | |
1445 | value &= ~((7 << 19) | (3 << 14) | (0xf << 3)); | |
1446 | } else if (arm_feature(env, ARM_FEATURE_EL3)) { | |
1447 | /* In an implementation that includes the Security Extensions | |
1448 | * TTBCR has additional fields PD0 [4] and PD1 [5] for | |
1449 | * Short-descriptor translation table format. | |
1450 | */ | |
1451 | value &= TTBCR_PD1 | TTBCR_PD0 | TTBCR_N; | |
1452 | } else { | |
1453 | value &= TTBCR_N; | |
1454 | } | |
e42c4db3 | 1455 | } |
e389be16 | 1456 | |
e42c4db3 PM |
1457 | /* Note that we always calculate c2_mask and c2_base_mask, but |
1458 | * they are only used for short-descriptor tables (ie if EAE is 0); | |
1459 | * for long-descriptor tables the TTBCR fields are used differently | |
1460 | * and the c2_mask and c2_base_mask values are meaningless. | |
1461 | */ | |
8d5c773e | 1462 | raw_write(env, ri, value); |
2ebcebe2 PM |
1463 | env->cp15.c2_mask = ~(((uint32_t)0xffffffffu) >> maskshift); |
1464 | env->cp15.c2_base_mask = ~((uint32_t)0x3fffu >> maskshift); | |
ecce5c3c PM |
1465 | } |
1466 | ||
c4241c7d PM |
1467 | static void vmsa_ttbcr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1468 | uint64_t value) | |
d4e6df63 | 1469 | { |
00c8cb0a AF |
1470 | ARMCPU *cpu = arm_env_get_cpu(env); |
1471 | ||
d4e6df63 PM |
1472 | if (arm_feature(env, ARM_FEATURE_LPAE)) { |
1473 | /* With LPAE the TTBCR could result in a change of ASID | |
1474 | * via the TTBCR.A1 bit, so do a TLB flush. | |
1475 | */ | |
00c8cb0a | 1476 | tlb_flush(CPU(cpu), 1); |
d4e6df63 | 1477 | } |
c4241c7d | 1478 | vmsa_ttbcr_raw_write(env, ri, value); |
d4e6df63 PM |
1479 | } |
1480 | ||
ecce5c3c PM |
1481 | static void vmsa_ttbcr_reset(CPUARMState *env, const ARMCPRegInfo *ri) |
1482 | { | |
1483 | env->cp15.c2_base_mask = 0xffffc000u; | |
8d5c773e | 1484 | raw_write(env, ri, 0); |
ecce5c3c PM |
1485 | env->cp15.c2_mask = 0; |
1486 | } | |
1487 | ||
cb2e37df PM |
1488 | static void vmsa_tcr_el1_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1489 | uint64_t value) | |
1490 | { | |
00c8cb0a AF |
1491 | ARMCPU *cpu = arm_env_get_cpu(env); |
1492 | ||
cb2e37df | 1493 | /* For AArch64 the A1 bit could result in a change of ASID, so TLB flush. */ |
00c8cb0a | 1494 | tlb_flush(CPU(cpu), 1); |
8d5c773e | 1495 | raw_write(env, ri, value); |
cb2e37df PM |
1496 | } |
1497 | ||
327ed10f PM |
1498 | static void vmsa_ttbr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1499 | uint64_t value) | |
1500 | { | |
1501 | /* 64 bit accesses to the TTBRs can change the ASID and so we | |
1502 | * must flush the TLB. | |
1503 | */ | |
1504 | if (cpreg_field_is_64bit(ri)) { | |
00c8cb0a AF |
1505 | ARMCPU *cpu = arm_env_get_cpu(env); |
1506 | ||
1507 | tlb_flush(CPU(cpu), 1); | |
327ed10f PM |
1508 | } |
1509 | raw_write(env, ri, value); | |
1510 | } | |
1511 | ||
18032bec PM |
1512 | static const ARMCPRegInfo vmsa_cp_reginfo[] = { |
1513 | { .name = "DFSR", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 0, | |
6cd8a264 | 1514 | .access = PL1_RW, .type = ARM_CP_NO_MIGRATE, |
d81c519c | 1515 | .fieldoffset = offsetoflow32(CPUARMState, cp15.esr_el[1]), |
6cd8a264 | 1516 | .resetfn = arm_cp_reset_ignore, }, |
18032bec PM |
1517 | { .name = "IFSR", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 1, |
1518 | .access = PL1_RW, | |
6cd8a264 RH |
1519 | .fieldoffset = offsetof(CPUARMState, cp15.ifsr_el2), .resetvalue = 0, }, |
1520 | { .name = "ESR_EL1", .state = ARM_CP_STATE_AA64, | |
1521 | .opc0 = 3, .crn = 5, .crm = 2, .opc1 = 0, .opc2 = 0, | |
1522 | .access = PL1_RW, | |
d81c519c | 1523 | .fieldoffset = offsetof(CPUARMState, cp15.esr_el[1]), .resetvalue = 0, }, |
327ed10f PM |
1524 | { .name = "TTBR0_EL1", .state = ARM_CP_STATE_BOTH, |
1525 | .opc0 = 3, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 0, | |
1526 | .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.ttbr0_el1), | |
1527 | .writefn = vmsa_ttbr_write, .resetvalue = 0 }, | |
1528 | { .name = "TTBR1_EL1", .state = ARM_CP_STATE_BOTH, | |
1529 | .opc0 = 3, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 1, | |
1530 | .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.ttbr1_el1), | |
1531 | .writefn = vmsa_ttbr_write, .resetvalue = 0 }, | |
cb2e37df PM |
1532 | { .name = "TCR_EL1", .state = ARM_CP_STATE_AA64, |
1533 | .opc0 = 3, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 2, | |
1534 | .access = PL1_RW, .writefn = vmsa_tcr_el1_write, | |
1535 | .resetfn = vmsa_ttbcr_reset, .raw_writefn = raw_write, | |
ecce5c3c | 1536 | .fieldoffset = offsetof(CPUARMState, cp15.c2_control) }, |
cb2e37df PM |
1537 | { .name = "TTBCR", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 2, |
1538 | .access = PL1_RW, .type = ARM_CP_NO_MIGRATE, .writefn = vmsa_ttbcr_write, | |
1539 | .resetfn = arm_cp_reset_ignore, .raw_writefn = vmsa_ttbcr_raw_write, | |
1540 | .fieldoffset = offsetoflow32(CPUARMState, cp15.c2_control) }, | |
6cd8a264 RH |
1541 | /* 64-bit FAR; this entry also gives us the AArch32 DFAR */ |
1542 | { .name = "FAR_EL1", .state = ARM_CP_STATE_BOTH, | |
1543 | .opc0 = 3, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 0, | |
2f0180c5 | 1544 | .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.far_el[1]), |
06d76f31 | 1545 | .resetvalue = 0, }, |
18032bec PM |
1546 | REGINFO_SENTINEL |
1547 | }; | |
1548 | ||
c4241c7d PM |
1549 | static void omap_ticonfig_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1550 | uint64_t value) | |
1047b9d7 PM |
1551 | { |
1552 | env->cp15.c15_ticonfig = value & 0xe7; | |
1553 | /* The OS_TYPE bit in this register changes the reported CPUID! */ | |
1554 | env->cp15.c0_cpuid = (value & (1 << 5)) ? | |
1555 | ARM_CPUID_TI915T : ARM_CPUID_TI925T; | |
1047b9d7 PM |
1556 | } |
1557 | ||
c4241c7d PM |
1558 | static void omap_threadid_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1559 | uint64_t value) | |
1047b9d7 PM |
1560 | { |
1561 | env->cp15.c15_threadid = value & 0xffff; | |
1047b9d7 PM |
1562 | } |
1563 | ||
c4241c7d PM |
1564 | static void omap_wfi_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1565 | uint64_t value) | |
1047b9d7 PM |
1566 | { |
1567 | /* Wait-for-interrupt (deprecated) */ | |
c3affe56 | 1568 | cpu_interrupt(CPU(arm_env_get_cpu(env)), CPU_INTERRUPT_HALT); |
1047b9d7 PM |
1569 | } |
1570 | ||
c4241c7d PM |
1571 | static void omap_cachemaint_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1572 | uint64_t value) | |
c4804214 PM |
1573 | { |
1574 | /* On OMAP there are registers indicating the max/min index of dcache lines | |
1575 | * containing a dirty line; cache flush operations have to reset these. | |
1576 | */ | |
1577 | env->cp15.c15_i_max = 0x000; | |
1578 | env->cp15.c15_i_min = 0xff0; | |
c4804214 PM |
1579 | } |
1580 | ||
18032bec PM |
1581 | static const ARMCPRegInfo omap_cp_reginfo[] = { |
1582 | { .name = "DFSR", .cp = 15, .crn = 5, .crm = CP_ANY, | |
1583 | .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_OVERRIDE, | |
d81c519c | 1584 | .fieldoffset = offsetoflow32(CPUARMState, cp15.esr_el[1]), |
6cd8a264 | 1585 | .resetvalue = 0, }, |
1047b9d7 PM |
1586 | { .name = "", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0, |
1587 | .access = PL1_RW, .type = ARM_CP_NOP }, | |
1588 | { .name = "TICONFIG", .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0, | |
1589 | .access = PL1_RW, | |
1590 | .fieldoffset = offsetof(CPUARMState, cp15.c15_ticonfig), .resetvalue = 0, | |
1591 | .writefn = omap_ticonfig_write }, | |
1592 | { .name = "IMAX", .cp = 15, .crn = 15, .crm = 2, .opc1 = 0, .opc2 = 0, | |
1593 | .access = PL1_RW, | |
1594 | .fieldoffset = offsetof(CPUARMState, cp15.c15_i_max), .resetvalue = 0, }, | |
1595 | { .name = "IMIN", .cp = 15, .crn = 15, .crm = 3, .opc1 = 0, .opc2 = 0, | |
1596 | .access = PL1_RW, .resetvalue = 0xff0, | |
1597 | .fieldoffset = offsetof(CPUARMState, cp15.c15_i_min) }, | |
1598 | { .name = "THREADID", .cp = 15, .crn = 15, .crm = 4, .opc1 = 0, .opc2 = 0, | |
1599 | .access = PL1_RW, | |
1600 | .fieldoffset = offsetof(CPUARMState, cp15.c15_threadid), .resetvalue = 0, | |
1601 | .writefn = omap_threadid_write }, | |
1602 | { .name = "TI925T_STATUS", .cp = 15, .crn = 15, | |
1603 | .crm = 8, .opc1 = 0, .opc2 = 0, .access = PL1_RW, | |
d4e6df63 | 1604 | .type = ARM_CP_NO_MIGRATE, |
1047b9d7 PM |
1605 | .readfn = arm_cp_read_zero, .writefn = omap_wfi_write, }, |
1606 | /* TODO: Peripheral port remap register: | |
1607 | * On OMAP2 mcr p15, 0, rn, c15, c2, 4 sets up the interrupt controller | |
1608 | * base address at $rn & ~0xfff and map size of 0x200 << ($rn & 0xfff), | |
1609 | * when MMU is off. | |
1610 | */ | |
c4804214 | 1611 | { .name = "OMAP_CACHEMAINT", .cp = 15, .crn = 7, .crm = CP_ANY, |
d4e6df63 PM |
1612 | .opc1 = 0, .opc2 = CP_ANY, .access = PL1_W, |
1613 | .type = ARM_CP_OVERRIDE | ARM_CP_NO_MIGRATE, | |
c4804214 | 1614 | .writefn = omap_cachemaint_write }, |
34f90529 PM |
1615 | { .name = "C9", .cp = 15, .crn = 9, |
1616 | .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, | |
1617 | .type = ARM_CP_CONST | ARM_CP_OVERRIDE, .resetvalue = 0 }, | |
1047b9d7 PM |
1618 | REGINFO_SENTINEL |
1619 | }; | |
1620 | ||
c4241c7d PM |
1621 | static void xscale_cpar_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1622 | uint64_t value) | |
1047b9d7 PM |
1623 | { |
1624 | value &= 0x3fff; | |
1625 | if (env->cp15.c15_cpar != value) { | |
1626 | /* Changes cp0 to cp13 behavior, so needs a TB flush. */ | |
1627 | tb_flush(env); | |
1628 | env->cp15.c15_cpar = value; | |
1629 | } | |
1047b9d7 PM |
1630 | } |
1631 | ||
1632 | static const ARMCPRegInfo xscale_cp_reginfo[] = { | |
1633 | { .name = "XSCALE_CPAR", | |
1634 | .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0, .access = PL1_RW, | |
1635 | .fieldoffset = offsetof(CPUARMState, cp15.c15_cpar), .resetvalue = 0, | |
1636 | .writefn = xscale_cpar_write, }, | |
2771db27 PM |
1637 | { .name = "XSCALE_AUXCR", |
1638 | .cp = 15, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 1, .access = PL1_RW, | |
1639 | .fieldoffset = offsetof(CPUARMState, cp15.c1_xscaleauxcr), | |
1640 | .resetvalue = 0, }, | |
3b771579 PM |
1641 | /* XScale specific cache-lockdown: since we have no cache we NOP these |
1642 | * and hope the guest does not really rely on cache behaviour. | |
1643 | */ | |
1644 | { .name = "XSCALE_LOCK_ICACHE_LINE", | |
1645 | .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 0, | |
1646 | .access = PL1_W, .type = ARM_CP_NOP }, | |
1647 | { .name = "XSCALE_UNLOCK_ICACHE", | |
1648 | .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 1, | |
1649 | .access = PL1_W, .type = ARM_CP_NOP }, | |
1650 | { .name = "XSCALE_DCACHE_LOCK", | |
1651 | .cp = 15, .opc1 = 0, .crn = 9, .crm = 2, .opc2 = 0, | |
1652 | .access = PL1_RW, .type = ARM_CP_NOP }, | |
1653 | { .name = "XSCALE_UNLOCK_DCACHE", | |
1654 | .cp = 15, .opc1 = 0, .crn = 9, .crm = 2, .opc2 = 1, | |
1655 | .access = PL1_W, .type = ARM_CP_NOP }, | |
1047b9d7 PM |
1656 | REGINFO_SENTINEL |
1657 | }; | |
1658 | ||
1659 | static const ARMCPRegInfo dummy_c15_cp_reginfo[] = { | |
1660 | /* RAZ/WI the whole crn=15 space, when we don't have a more specific | |
1661 | * implementation of this implementation-defined space. | |
1662 | * Ideally this should eventually disappear in favour of actually | |
1663 | * implementing the correct behaviour for all cores. | |
1664 | */ | |
1665 | { .name = "C15_IMPDEF", .cp = 15, .crn = 15, | |
1666 | .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY, | |
3671cd87 PC |
1667 | .access = PL1_RW, |
1668 | .type = ARM_CP_CONST | ARM_CP_NO_MIGRATE | ARM_CP_OVERRIDE, | |
d4e6df63 | 1669 | .resetvalue = 0 }, |
18032bec PM |
1670 | REGINFO_SENTINEL |
1671 | }; | |
1672 | ||
c4804214 PM |
1673 | static const ARMCPRegInfo cache_dirty_status_cp_reginfo[] = { |
1674 | /* Cache status: RAZ because we have no cache so it's always clean */ | |
1675 | { .name = "CDSR", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 6, | |
d4e6df63 PM |
1676 | .access = PL1_R, .type = ARM_CP_CONST | ARM_CP_NO_MIGRATE, |
1677 | .resetvalue = 0 }, | |
c4804214 PM |
1678 | REGINFO_SENTINEL |
1679 | }; | |
1680 | ||
1681 | static const ARMCPRegInfo cache_block_ops_cp_reginfo[] = { | |
1682 | /* We never have a a block transfer operation in progress */ | |
1683 | { .name = "BXSR", .cp = 15, .crn = 7, .crm = 12, .opc1 = 0, .opc2 = 4, | |
d4e6df63 PM |
1684 | .access = PL0_R, .type = ARM_CP_CONST | ARM_CP_NO_MIGRATE, |
1685 | .resetvalue = 0 }, | |
30b05bba PM |
1686 | /* The cache ops themselves: these all NOP for QEMU */ |
1687 | { .name = "IICR", .cp = 15, .crm = 5, .opc1 = 0, | |
1688 | .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT }, | |
1689 | { .name = "IDCR", .cp = 15, .crm = 6, .opc1 = 0, | |
1690 | .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT }, | |
1691 | { .name = "CDCR", .cp = 15, .crm = 12, .opc1 = 0, | |
1692 | .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT }, | |
1693 | { .name = "PIR", .cp = 15, .crm = 12, .opc1 = 1, | |
1694 | .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT }, | |
1695 | { .name = "PDR", .cp = 15, .crm = 12, .opc1 = 2, | |
1696 | .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT }, | |
1697 | { .name = "CIDCR", .cp = 15, .crm = 14, .opc1 = 0, | |
1698 | .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT }, | |
c4804214 PM |
1699 | REGINFO_SENTINEL |
1700 | }; | |
1701 | ||
1702 | static const ARMCPRegInfo cache_test_clean_cp_reginfo[] = { | |
1703 | /* The cache test-and-clean instructions always return (1 << 30) | |
1704 | * to indicate that there are no dirty cache lines. | |
1705 | */ | |
1706 | { .name = "TC_DCACHE", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 3, | |
d4e6df63 PM |
1707 | .access = PL0_R, .type = ARM_CP_CONST | ARM_CP_NO_MIGRATE, |
1708 | .resetvalue = (1 << 30) }, | |
c4804214 | 1709 | { .name = "TCI_DCACHE", .cp = 15, .crn = 7, .crm = 14, .opc1 = 0, .opc2 = 3, |
d4e6df63 PM |
1710 | .access = PL0_R, .type = ARM_CP_CONST | ARM_CP_NO_MIGRATE, |
1711 | .resetvalue = (1 << 30) }, | |
c4804214 PM |
1712 | REGINFO_SENTINEL |
1713 | }; | |
1714 | ||
34f90529 PM |
1715 | static const ARMCPRegInfo strongarm_cp_reginfo[] = { |
1716 | /* Ignore ReadBuffer accesses */ | |
1717 | { .name = "C9_READBUFFER", .cp = 15, .crn = 9, | |
1718 | .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY, | |
d4e6df63 PM |
1719 | .access = PL1_RW, .resetvalue = 0, |
1720 | .type = ARM_CP_CONST | ARM_CP_OVERRIDE | ARM_CP_NO_MIGRATE }, | |
34f90529 PM |
1721 | REGINFO_SENTINEL |
1722 | }; | |
1723 | ||
c4241c7d | 1724 | static uint64_t mpidr_read(CPUARMState *env, const ARMCPRegInfo *ri) |
81bdde9d | 1725 | { |
55e5c285 AF |
1726 | CPUState *cs = CPU(arm_env_get_cpu(env)); |
1727 | uint32_t mpidr = cs->cpu_index; | |
4b7fff2f PM |
1728 | /* We don't support setting cluster ID ([8..11]) (known as Aff1 |
1729 | * in later ARM ARM versions), or any of the higher affinity level fields, | |
81bdde9d PM |
1730 | * so these bits always RAZ. |
1731 | */ | |
1732 | if (arm_feature(env, ARM_FEATURE_V7MP)) { | |
78dbbbe4 | 1733 | mpidr |= (1U << 31); |
81bdde9d PM |
1734 | /* Cores which are uniprocessor (non-coherent) |
1735 | * but still implement the MP extensions set | |
1736 | * bit 30. (For instance, A9UP.) However we do | |
1737 | * not currently model any of those cores. | |
1738 | */ | |
1739 | } | |
c4241c7d | 1740 | return mpidr; |
81bdde9d PM |
1741 | } |
1742 | ||
1743 | static const ARMCPRegInfo mpidr_cp_reginfo[] = { | |
4b7fff2f PM |
1744 | { .name = "MPIDR", .state = ARM_CP_STATE_BOTH, |
1745 | .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 5, | |
d4e6df63 | 1746 | .access = PL1_R, .readfn = mpidr_read, .type = ARM_CP_NO_MIGRATE }, |
81bdde9d PM |
1747 | REGINFO_SENTINEL |
1748 | }; | |
1749 | ||
7ac681cf | 1750 | static const ARMCPRegInfo lpae_cp_reginfo[] = { |
b90372ad | 1751 | /* NOP AMAIR0/1: the override is because these clash with the rather |
7ac681cf PM |
1752 | * broadly specified TLB_LOCKDOWN entry in the generic cp_reginfo. |
1753 | */ | |
b0fe2427 PM |
1754 | { .name = "AMAIR0", .state = ARM_CP_STATE_BOTH, |
1755 | .opc0 = 3, .crn = 10, .crm = 3, .opc1 = 0, .opc2 = 0, | |
7ac681cf PM |
1756 | .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_OVERRIDE, |
1757 | .resetvalue = 0 }, | |
b0fe2427 | 1758 | /* AMAIR1 is mapped to AMAIR_EL1[63:32] */ |
7ac681cf PM |
1759 | { .name = "AMAIR1", .cp = 15, .crn = 10, .crm = 3, .opc1 = 0, .opc2 = 1, |
1760 | .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_OVERRIDE, | |
1761 | .resetvalue = 0 }, | |
891a2fe7 PM |
1762 | { .name = "PAR", .cp = 15, .crm = 7, .opc1 = 0, |
1763 | .access = PL1_RW, .type = ARM_CP_64BIT, | |
19525524 | 1764 | .fieldoffset = offsetof(CPUARMState, cp15.par_el1), .resetvalue = 0 }, |
891a2fe7 | 1765 | { .name = "TTBR0", .cp = 15, .crm = 2, .opc1 = 0, |
327ed10f PM |
1766 | .access = PL1_RW, .type = ARM_CP_64BIT | ARM_CP_NO_MIGRATE, |
1767 | .fieldoffset = offsetof(CPUARMState, cp15.ttbr0_el1), | |
1768 | .writefn = vmsa_ttbr_write, .resetfn = arm_cp_reset_ignore }, | |
891a2fe7 | 1769 | { .name = "TTBR1", .cp = 15, .crm = 2, .opc1 = 1, |
327ed10f PM |
1770 | .access = PL1_RW, .type = ARM_CP_64BIT | ARM_CP_NO_MIGRATE, |
1771 | .fieldoffset = offsetof(CPUARMState, cp15.ttbr1_el1), | |
1772 | .writefn = vmsa_ttbr_write, .resetfn = arm_cp_reset_ignore }, | |
7ac681cf PM |
1773 | REGINFO_SENTINEL |
1774 | }; | |
1775 | ||
c4241c7d | 1776 | static uint64_t aa64_fpcr_read(CPUARMState *env, const ARMCPRegInfo *ri) |
b0d2b7d0 | 1777 | { |
c4241c7d | 1778 | return vfp_get_fpcr(env); |
b0d2b7d0 PM |
1779 | } |
1780 | ||
c4241c7d PM |
1781 | static void aa64_fpcr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1782 | uint64_t value) | |
b0d2b7d0 PM |
1783 | { |
1784 | vfp_set_fpcr(env, value); | |
b0d2b7d0 PM |
1785 | } |
1786 | ||
c4241c7d | 1787 | static uint64_t aa64_fpsr_read(CPUARMState *env, const ARMCPRegInfo *ri) |
b0d2b7d0 | 1788 | { |
c4241c7d | 1789 | return vfp_get_fpsr(env); |
b0d2b7d0 PM |
1790 | } |
1791 | ||
c4241c7d PM |
1792 | static void aa64_fpsr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1793 | uint64_t value) | |
b0d2b7d0 PM |
1794 | { |
1795 | vfp_set_fpsr(env, value); | |
b0d2b7d0 PM |
1796 | } |
1797 | ||
c2b820fe PM |
1798 | static CPAccessResult aa64_daif_access(CPUARMState *env, const ARMCPRegInfo *ri) |
1799 | { | |
1800 | if (arm_current_pl(env) == 0 && !(env->cp15.c1_sys & SCTLR_UMA)) { | |
1801 | return CP_ACCESS_TRAP; | |
1802 | } | |
1803 | return CP_ACCESS_OK; | |
1804 | } | |
1805 | ||
1806 | static void aa64_daif_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
1807 | uint64_t value) | |
1808 | { | |
1809 | env->daif = value & PSTATE_DAIF; | |
1810 | } | |
1811 | ||
8af35c37 PM |
1812 | static CPAccessResult aa64_cacheop_access(CPUARMState *env, |
1813 | const ARMCPRegInfo *ri) | |
1814 | { | |
1815 | /* Cache invalidate/clean: NOP, but EL0 must UNDEF unless | |
1816 | * SCTLR_EL1.UCI is set. | |
1817 | */ | |
1818 | if (arm_current_pl(env) == 0 && !(env->cp15.c1_sys & SCTLR_UCI)) { | |
1819 | return CP_ACCESS_TRAP; | |
1820 | } | |
1821 | return CP_ACCESS_OK; | |
1822 | } | |
1823 | ||
dbb1fb27 AB |
1824 | /* See: D4.7.2 TLB maintenance requirements and the TLB maintenance instructions |
1825 | * Page D4-1736 (DDI0487A.b) | |
1826 | */ | |
1827 | ||
168aa23b PM |
1828 | static void tlbi_aa64_va_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1829 | uint64_t value) | |
1830 | { | |
1831 | /* Invalidate by VA (AArch64 version) */ | |
31b030d4 | 1832 | ARMCPU *cpu = arm_env_get_cpu(env); |
dbb1fb27 AB |
1833 | uint64_t pageaddr = sextract64(value << 12, 0, 56); |
1834 | ||
31b030d4 | 1835 | tlb_flush_page(CPU(cpu), pageaddr); |
168aa23b PM |
1836 | } |
1837 | ||
1838 | static void tlbi_aa64_vaa_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
1839 | uint64_t value) | |
1840 | { | |
1841 | /* Invalidate by VA, all ASIDs (AArch64 version) */ | |
31b030d4 | 1842 | ARMCPU *cpu = arm_env_get_cpu(env); |
dbb1fb27 AB |
1843 | uint64_t pageaddr = sextract64(value << 12, 0, 56); |
1844 | ||
31b030d4 | 1845 | tlb_flush_page(CPU(cpu), pageaddr); |
168aa23b PM |
1846 | } |
1847 | ||
1848 | static void tlbi_aa64_asid_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
1849 | uint64_t value) | |
1850 | { | |
1851 | /* Invalidate by ASID (AArch64 version) */ | |
00c8cb0a | 1852 | ARMCPU *cpu = arm_env_get_cpu(env); |
168aa23b | 1853 | int asid = extract64(value, 48, 16); |
00c8cb0a | 1854 | tlb_flush(CPU(cpu), asid == 0); |
168aa23b PM |
1855 | } |
1856 | ||
aca3f40b PM |
1857 | static CPAccessResult aa64_zva_access(CPUARMState *env, const ARMCPRegInfo *ri) |
1858 | { | |
1859 | /* We don't implement EL2, so the only control on DC ZVA is the | |
1860 | * bit in the SCTLR which can prohibit access for EL0. | |
1861 | */ | |
1862 | if (arm_current_pl(env) == 0 && !(env->cp15.c1_sys & SCTLR_DZE)) { | |
1863 | return CP_ACCESS_TRAP; | |
1864 | } | |
1865 | return CP_ACCESS_OK; | |
1866 | } | |
1867 | ||
1868 | static uint64_t aa64_dczid_read(CPUARMState *env, const ARMCPRegInfo *ri) | |
1869 | { | |
1870 | ARMCPU *cpu = arm_env_get_cpu(env); | |
1871 | int dzp_bit = 1 << 4; | |
1872 | ||
1873 | /* DZP indicates whether DC ZVA access is allowed */ | |
1874 | if (aa64_zva_access(env, NULL) != CP_ACCESS_OK) { | |
1875 | dzp_bit = 0; | |
1876 | } | |
1877 | return cpu->dcz_blocksize | dzp_bit; | |
1878 | } | |
1879 | ||
f502cfc2 PM |
1880 | static CPAccessResult sp_el0_access(CPUARMState *env, const ARMCPRegInfo *ri) |
1881 | { | |
cdcf1405 | 1882 | if (!(env->pstate & PSTATE_SP)) { |
f502cfc2 PM |
1883 | /* Access to SP_EL0 is undefined if it's being used as |
1884 | * the stack pointer. | |
1885 | */ | |
1886 | return CP_ACCESS_TRAP_UNCATEGORIZED; | |
1887 | } | |
1888 | return CP_ACCESS_OK; | |
1889 | } | |
1890 | ||
1891 | static uint64_t spsel_read(CPUARMState *env, const ARMCPRegInfo *ri) | |
1892 | { | |
1893 | return env->pstate & PSTATE_SP; | |
1894 | } | |
1895 | ||
1896 | static void spsel_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t val) | |
1897 | { | |
1898 | update_spsel(env, val); | |
1899 | } | |
1900 | ||
b0d2b7d0 PM |
1901 | static const ARMCPRegInfo v8_cp_reginfo[] = { |
1902 | /* Minimal set of EL0-visible registers. This will need to be expanded | |
1903 | * significantly for system emulation of AArch64 CPUs. | |
1904 | */ | |
1905 | { .name = "NZCV", .state = ARM_CP_STATE_AA64, | |
1906 | .opc0 = 3, .opc1 = 3, .opc2 = 0, .crn = 4, .crm = 2, | |
1907 | .access = PL0_RW, .type = ARM_CP_NZCV }, | |
c2b820fe PM |
1908 | { .name = "DAIF", .state = ARM_CP_STATE_AA64, |
1909 | .opc0 = 3, .opc1 = 3, .opc2 = 1, .crn = 4, .crm = 2, | |
1910 | .type = ARM_CP_NO_MIGRATE, | |
1911 | .access = PL0_RW, .accessfn = aa64_daif_access, | |
1912 | .fieldoffset = offsetof(CPUARMState, daif), | |
1913 | .writefn = aa64_daif_write, .resetfn = arm_cp_reset_ignore }, | |
b0d2b7d0 PM |
1914 | { .name = "FPCR", .state = ARM_CP_STATE_AA64, |
1915 | .opc0 = 3, .opc1 = 3, .opc2 = 0, .crn = 4, .crm = 4, | |
1916 | .access = PL0_RW, .readfn = aa64_fpcr_read, .writefn = aa64_fpcr_write }, | |
1917 | { .name = "FPSR", .state = ARM_CP_STATE_AA64, | |
1918 | .opc0 = 3, .opc1 = 3, .opc2 = 1, .crn = 4, .crm = 4, | |
1919 | .access = PL0_RW, .readfn = aa64_fpsr_read, .writefn = aa64_fpsr_write }, | |
b0d2b7d0 PM |
1920 | { .name = "DCZID_EL0", .state = ARM_CP_STATE_AA64, |
1921 | .opc0 = 3, .opc1 = 3, .opc2 = 7, .crn = 0, .crm = 0, | |
aca3f40b PM |
1922 | .access = PL0_R, .type = ARM_CP_NO_MIGRATE, |
1923 | .readfn = aa64_dczid_read }, | |
1924 | { .name = "DC_ZVA", .state = ARM_CP_STATE_AA64, | |
1925 | .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 4, .opc2 = 1, | |
1926 | .access = PL0_W, .type = ARM_CP_DC_ZVA, | |
1927 | #ifndef CONFIG_USER_ONLY | |
1928 | /* Avoid overhead of an access check that always passes in user-mode */ | |
1929 | .accessfn = aa64_zva_access, | |
1930 | #endif | |
1931 | }, | |
0eef9d98 PM |
1932 | { .name = "CURRENTEL", .state = ARM_CP_STATE_AA64, |
1933 | .opc0 = 3, .opc1 = 0, .opc2 = 2, .crn = 4, .crm = 2, | |
1934 | .access = PL1_R, .type = ARM_CP_CURRENTEL }, | |
8af35c37 PM |
1935 | /* Cache ops: all NOPs since we don't emulate caches */ |
1936 | { .name = "IC_IALLUIS", .state = ARM_CP_STATE_AA64, | |
1937 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 1, .opc2 = 0, | |
1938 | .access = PL1_W, .type = ARM_CP_NOP }, | |
1939 | { .name = "IC_IALLU", .state = ARM_CP_STATE_AA64, | |
1940 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 0, | |
1941 | .access = PL1_W, .type = ARM_CP_NOP }, | |
1942 | { .name = "IC_IVAU", .state = ARM_CP_STATE_AA64, | |
1943 | .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 5, .opc2 = 1, | |
1944 | .access = PL0_W, .type = ARM_CP_NOP, | |
1945 | .accessfn = aa64_cacheop_access }, | |
1946 | { .name = "DC_IVAC", .state = ARM_CP_STATE_AA64, | |
1947 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 1, | |
1948 | .access = PL1_W, .type = ARM_CP_NOP }, | |
1949 | { .name = "DC_ISW", .state = ARM_CP_STATE_AA64, | |
1950 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 2, | |
1951 | .access = PL1_W, .type = ARM_CP_NOP }, | |
1952 | { .name = "DC_CVAC", .state = ARM_CP_STATE_AA64, | |
1953 | .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 10, .opc2 = 1, | |
1954 | .access = PL0_W, .type = ARM_CP_NOP, | |
1955 | .accessfn = aa64_cacheop_access }, | |
1956 | { .name = "DC_CSW", .state = ARM_CP_STATE_AA64, | |
1957 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 2, | |
1958 | .access = PL1_W, .type = ARM_CP_NOP }, | |
1959 | { .name = "DC_CVAU", .state = ARM_CP_STATE_AA64, | |
1960 | .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 11, .opc2 = 1, | |
1961 | .access = PL0_W, .type = ARM_CP_NOP, | |
1962 | .accessfn = aa64_cacheop_access }, | |
1963 | { .name = "DC_CIVAC", .state = ARM_CP_STATE_AA64, | |
1964 | .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 14, .opc2 = 1, | |
1965 | .access = PL0_W, .type = ARM_CP_NOP, | |
1966 | .accessfn = aa64_cacheop_access }, | |
1967 | { .name = "DC_CISW", .state = ARM_CP_STATE_AA64, | |
1968 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 2, | |
1969 | .access = PL1_W, .type = ARM_CP_NOP }, | |
168aa23b PM |
1970 | /* TLBI operations */ |
1971 | { .name = "TLBI_VMALLE1IS", .state = ARM_CP_STATE_AA64, | |
6ab9f499 | 1972 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 0, |
168aa23b PM |
1973 | .access = PL1_W, .type = ARM_CP_NO_MIGRATE, |
1974 | .writefn = tlbiall_write }, | |
1975 | { .name = "TLBI_VAE1IS", .state = ARM_CP_STATE_AA64, | |
6ab9f499 | 1976 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 1, |
168aa23b PM |
1977 | .access = PL1_W, .type = ARM_CP_NO_MIGRATE, |
1978 | .writefn = tlbi_aa64_va_write }, | |
1979 | { .name = "TLBI_ASIDE1IS", .state = ARM_CP_STATE_AA64, | |
6ab9f499 | 1980 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 2, |
168aa23b PM |
1981 | .access = PL1_W, .type = ARM_CP_NO_MIGRATE, |
1982 | .writefn = tlbi_aa64_asid_write }, | |
1983 | { .name = "TLBI_VAAE1IS", .state = ARM_CP_STATE_AA64, | |
6ab9f499 | 1984 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 3, |
168aa23b PM |
1985 | .access = PL1_W, .type = ARM_CP_NO_MIGRATE, |
1986 | .writefn = tlbi_aa64_vaa_write }, | |
1987 | { .name = "TLBI_VALE1IS", .state = ARM_CP_STATE_AA64, | |
6ab9f499 | 1988 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 5, |
168aa23b PM |
1989 | .access = PL1_W, .type = ARM_CP_NO_MIGRATE, |
1990 | .writefn = tlbi_aa64_va_write }, | |
1991 | { .name = "TLBI_VAALE1IS", .state = ARM_CP_STATE_AA64, | |
6ab9f499 | 1992 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 7, |
168aa23b PM |
1993 | .access = PL1_W, .type = ARM_CP_NO_MIGRATE, |
1994 | .writefn = tlbi_aa64_vaa_write }, | |
1995 | { .name = "TLBI_VMALLE1", .state = ARM_CP_STATE_AA64, | |
6ab9f499 | 1996 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 0, |
168aa23b PM |
1997 | .access = PL1_W, .type = ARM_CP_NO_MIGRATE, |
1998 | .writefn = tlbiall_write }, | |
1999 | { .name = "TLBI_VAE1", .state = ARM_CP_STATE_AA64, | |
6ab9f499 | 2000 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 1, |
168aa23b PM |
2001 | .access = PL1_W, .type = ARM_CP_NO_MIGRATE, |
2002 | .writefn = tlbi_aa64_va_write }, | |
2003 | { .name = "TLBI_ASIDE1", .state = ARM_CP_STATE_AA64, | |
6ab9f499 | 2004 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 2, |
168aa23b PM |
2005 | .access = PL1_W, .type = ARM_CP_NO_MIGRATE, |
2006 | .writefn = tlbi_aa64_asid_write }, | |
2007 | { .name = "TLBI_VAAE1", .state = ARM_CP_STATE_AA64, | |
6ab9f499 | 2008 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 3, |
168aa23b PM |
2009 | .access = PL1_W, .type = ARM_CP_NO_MIGRATE, |
2010 | .writefn = tlbi_aa64_vaa_write }, | |
2011 | { .name = "TLBI_VALE1", .state = ARM_CP_STATE_AA64, | |
6ab9f499 | 2012 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 5, |
168aa23b PM |
2013 | .access = PL1_W, .type = ARM_CP_NO_MIGRATE, |
2014 | .writefn = tlbi_aa64_va_write }, | |
2015 | { .name = "TLBI_VAALE1", .state = ARM_CP_STATE_AA64, | |
6ab9f499 | 2016 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 7, |
168aa23b PM |
2017 | .access = PL1_W, .type = ARM_CP_NO_MIGRATE, |
2018 | .writefn = tlbi_aa64_vaa_write }, | |
19525524 PM |
2019 | #ifndef CONFIG_USER_ONLY |
2020 | /* 64 bit address translation operations */ | |
2021 | { .name = "AT_S1E1R", .state = ARM_CP_STATE_AA64, | |
2022 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 0, | |
2023 | .access = PL1_W, .type = ARM_CP_NO_MIGRATE, .writefn = ats_write }, | |
2024 | { .name = "AT_S1E1W", .state = ARM_CP_STATE_AA64, | |
2025 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 1, | |
2026 | .access = PL1_W, .type = ARM_CP_NO_MIGRATE, .writefn = ats_write }, | |
2027 | { .name = "AT_S1E0R", .state = ARM_CP_STATE_AA64, | |
2028 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 2, | |
2029 | .access = PL1_W, .type = ARM_CP_NO_MIGRATE, .writefn = ats_write }, | |
2030 | { .name = "AT_S1E0W", .state = ARM_CP_STATE_AA64, | |
2031 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 3, | |
2032 | .access = PL1_W, .type = ARM_CP_NO_MIGRATE, .writefn = ats_write }, | |
2033 | #endif | |
9449fdf6 PM |
2034 | /* 32 bit TLB invalidates, Inner Shareable */ |
2035 | { .name = "TLBIALLIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 0, | |
2036 | .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn = tlbiall_write }, | |
2037 | { .name = "TLBIMVAIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 1, | |
2038 | .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn = tlbimva_write }, | |
2039 | { .name = "TLBIASIDIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 2, | |
2040 | .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn = tlbiasid_write }, | |
2041 | { .name = "TLBIMVAAIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 3, | |
2042 | .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn = tlbimvaa_write }, | |
2043 | { .name = "TLBIMVALIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 5, | |
2044 | .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn = tlbimva_write }, | |
2045 | { .name = "TLBIMVAALIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 7, | |
2046 | .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn = tlbimvaa_write }, | |
2047 | /* 32 bit ITLB invalidates */ | |
2048 | { .name = "ITLBIALL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 0, | |
2049 | .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn = tlbiall_write }, | |
2050 | { .name = "ITLBIMVA", .cp = 15, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 1, | |
2051 | .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn = tlbimva_write }, | |
2052 | { .name = "ITLBIASID", .cp = 15, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 2, | |
2053 | .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn = tlbiasid_write }, | |
2054 | /* 32 bit DTLB invalidates */ | |
2055 | { .name = "DTLBIALL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 0, | |
2056 | .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn = tlbiall_write }, | |
2057 | { .name = "DTLBIMVA", .cp = 15, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 1, | |
2058 | .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn = tlbimva_write }, | |
2059 | { .name = "DTLBIASID", .cp = 15, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 2, | |
2060 | .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn = tlbiasid_write }, | |
2061 | /* 32 bit TLB invalidates */ | |
2062 | { .name = "TLBIALL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 0, | |
2063 | .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn = tlbiall_write }, | |
2064 | { .name = "TLBIMVA", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 1, | |
2065 | .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn = tlbimva_write }, | |
2066 | { .name = "TLBIASID", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 2, | |
2067 | .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn = tlbiasid_write }, | |
2068 | { .name = "TLBIMVAA", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 3, | |
2069 | .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn = tlbimvaa_write }, | |
2070 | { .name = "TLBIMVAL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 5, | |
2071 | .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn = tlbimva_write }, | |
2072 | { .name = "TLBIMVAAL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 7, | |
2073 | .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn = tlbimvaa_write }, | |
2074 | /* 32 bit cache operations */ | |
2075 | { .name = "ICIALLUIS", .cp = 15, .opc1 = 0, .crn = 7, .crm = 1, .opc2 = 0, | |
2076 | .type = ARM_CP_NOP, .access = PL1_W }, | |
2077 | { .name = "BPIALLUIS", .cp = 15, .opc1 = 0, .crn = 7, .crm = 1, .opc2 = 6, | |
2078 | .type = ARM_CP_NOP, .access = PL1_W }, | |
2079 | { .name = "ICIALLU", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 0, | |
2080 | .type = ARM_CP_NOP, .access = PL1_W }, | |
2081 | { .name = "ICIMVAU", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 1, | |
2082 | .type = ARM_CP_NOP, .access = PL1_W }, | |
2083 | { .name = "BPIALL", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 6, | |
2084 | .type = ARM_CP_NOP, .access = PL1_W }, | |
2085 | { .name = "BPIMVA", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 7, | |
2086 | .type = ARM_CP_NOP, .access = PL1_W }, | |
2087 | { .name = "DCIMVAC", .cp = 15, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 1, | |
2088 | .type = ARM_CP_NOP, .access = PL1_W }, | |
2089 | { .name = "DCISW", .cp = 15, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 2, | |
2090 | .type = ARM_CP_NOP, .access = PL1_W }, | |
2091 | { .name = "DCCMVAC", .cp = 15, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 1, | |
2092 | .type = ARM_CP_NOP, .access = PL1_W }, | |
2093 | { .name = "DCCSW", .cp = 15, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 2, | |
2094 | .type = ARM_CP_NOP, .access = PL1_W }, | |
2095 | { .name = "DCCMVAU", .cp = 15, .opc1 = 0, .crn = 7, .crm = 11, .opc2 = 1, | |
2096 | .type = ARM_CP_NOP, .access = PL1_W }, | |
2097 | { .name = "DCCIMVAC", .cp = 15, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 1, | |
2098 | .type = ARM_CP_NOP, .access = PL1_W }, | |
2099 | { .name = "DCCISW", .cp = 15, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 2, | |
2100 | .type = ARM_CP_NOP, .access = PL1_W }, | |
2101 | /* MMU Domain access control / MPU write buffer control */ | |
2102 | { .name = "DACR", .cp = 15, | |
2103 | .opc1 = 0, .crn = 3, .crm = 0, .opc2 = 0, | |
2104 | .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c3), | |
2105 | .resetvalue = 0, .writefn = dacr_write, .raw_writefn = raw_write, }, | |
a0618a19 PM |
2106 | { .name = "ELR_EL1", .state = ARM_CP_STATE_AA64, |
2107 | .type = ARM_CP_NO_MIGRATE, | |
2108 | .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 0, .opc2 = 1, | |
6947f059 EI |
2109 | .access = PL1_RW, |
2110 | .fieldoffset = offsetof(CPUARMState, elr_el[1]) }, | |
a65f1de9 PM |
2111 | { .name = "SPSR_EL1", .state = ARM_CP_STATE_AA64, |
2112 | .type = ARM_CP_NO_MIGRATE, | |
2113 | .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 0, .opc2 = 0, | |
2114 | .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, banked_spsr[0]) }, | |
f502cfc2 PM |
2115 | /* We rely on the access checks not allowing the guest to write to the |
2116 | * state field when SPSel indicates that it's being used as the stack | |
2117 | * pointer. | |
2118 | */ | |
2119 | { .name = "SP_EL0", .state = ARM_CP_STATE_AA64, | |
2120 | .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 1, .opc2 = 0, | |
2121 | .access = PL1_RW, .accessfn = sp_el0_access, | |
2122 | .type = ARM_CP_NO_MIGRATE, | |
2123 | .fieldoffset = offsetof(CPUARMState, sp_el[0]) }, | |
2124 | { .name = "SPSel", .state = ARM_CP_STATE_AA64, | |
2125 | .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 2, .opc2 = 0, | |
2126 | .type = ARM_CP_NO_MIGRATE, | |
2127 | .access = PL1_RW, .readfn = spsel_read, .writefn = spsel_write }, | |
b0d2b7d0 PM |
2128 | REGINFO_SENTINEL |
2129 | }; | |
2130 | ||
d42e3c26 EI |
2131 | /* Used to describe the behaviour of EL2 regs when EL2 does not exist. */ |
2132 | static const ARMCPRegInfo v8_el3_no_el2_cp_reginfo[] = { | |
2133 | { .name = "VBAR_EL2", .state = ARM_CP_STATE_AA64, | |
2134 | .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 0, .opc2 = 0, | |
2135 | .access = PL2_RW, | |
2136 | .readfn = arm_cp_read_zero, .writefn = arm_cp_write_ignore }, | |
2137 | REGINFO_SENTINEL | |
2138 | }; | |
2139 | ||
3b685ba7 EI |
2140 | static const ARMCPRegInfo v8_el2_cp_reginfo[] = { |
2141 | { .name = "ELR_EL2", .state = ARM_CP_STATE_AA64, | |
2142 | .type = ARM_CP_NO_MIGRATE, | |
2143 | .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 0, .opc2 = 1, | |
2144 | .access = PL2_RW, | |
2145 | .fieldoffset = offsetof(CPUARMState, elr_el[2]) }, | |
f2c30f42 EI |
2146 | { .name = "ESR_EL2", .state = ARM_CP_STATE_AA64, |
2147 | .type = ARM_CP_NO_MIGRATE, | |
2148 | .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 2, .opc2 = 0, | |
2149 | .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.esr_el[2]) }, | |
63b60551 EI |
2150 | { .name = "FAR_EL2", .state = ARM_CP_STATE_AA64, |
2151 | .opc0 = 3, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 0, | |
2152 | .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.far_el[2]) }, | |
3b685ba7 EI |
2153 | { .name = "SPSR_EL2", .state = ARM_CP_STATE_AA64, |
2154 | .type = ARM_CP_NO_MIGRATE, | |
2155 | .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 0, .opc2 = 0, | |
2156 | .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, banked_spsr[6]) }, | |
d42e3c26 EI |
2157 | { .name = "VBAR_EL2", .state = ARM_CP_STATE_AA64, |
2158 | .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 0, .opc2 = 0, | |
2159 | .access = PL2_RW, .writefn = vbar_write, | |
2160 | .fieldoffset = offsetof(CPUARMState, cp15.vbar_el[2]), | |
2161 | .resetvalue = 0 }, | |
3b685ba7 EI |
2162 | REGINFO_SENTINEL |
2163 | }; | |
2164 | ||
81547d66 EI |
2165 | static const ARMCPRegInfo v8_el3_cp_reginfo[] = { |
2166 | { .name = "ELR_EL3", .state = ARM_CP_STATE_AA64, | |
2167 | .type = ARM_CP_NO_MIGRATE, | |
2168 | .opc0 = 3, .opc1 = 6, .crn = 4, .crm = 0, .opc2 = 1, | |
2169 | .access = PL3_RW, | |
2170 | .fieldoffset = offsetof(CPUARMState, elr_el[3]) }, | |
f2c30f42 EI |
2171 | { .name = "ESR_EL3", .state = ARM_CP_STATE_AA64, |
2172 | .type = ARM_CP_NO_MIGRATE, | |
2173 | .opc0 = 3, .opc1 = 6, .crn = 5, .crm = 2, .opc2 = 0, | |
2174 | .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.esr_el[3]) }, | |
63b60551 EI |
2175 | { .name = "FAR_EL3", .state = ARM_CP_STATE_AA64, |
2176 | .opc0 = 3, .opc1 = 6, .crn = 6, .crm = 0, .opc2 = 0, | |
2177 | .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.far_el[3]) }, | |
81547d66 EI |
2178 | { .name = "SPSR_EL3", .state = ARM_CP_STATE_AA64, |
2179 | .type = ARM_CP_NO_MIGRATE, | |
2180 | .opc0 = 3, .opc1 = 6, .crn = 4, .crm = 0, .opc2 = 0, | |
2181 | .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, banked_spsr[7]) }, | |
a1ba125c EI |
2182 | { .name = "VBAR_EL3", .state = ARM_CP_STATE_AA64, |
2183 | .opc0 = 3, .opc1 = 6, .crn = 12, .crm = 0, .opc2 = 0, | |
2184 | .access = PL3_RW, .writefn = vbar_write, | |
2185 | .fieldoffset = offsetof(CPUARMState, cp15.vbar_el[3]), | |
2186 | .resetvalue = 0 }, | |
81547d66 EI |
2187 | REGINFO_SENTINEL |
2188 | }; | |
2189 | ||
c4241c7d PM |
2190 | static void sctlr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
2191 | uint64_t value) | |
2771db27 | 2192 | { |
00c8cb0a AF |
2193 | ARMCPU *cpu = arm_env_get_cpu(env); |
2194 | ||
8d5c773e | 2195 | if (raw_read(env, ri) == value) { |
2f0d8631 PM |
2196 | /* Skip the TLB flush if nothing actually changed; Linux likes |
2197 | * to do a lot of pointless SCTLR writes. | |
2198 | */ | |
2199 | return; | |
2200 | } | |
2201 | ||
8d5c773e | 2202 | raw_write(env, ri, value); |
2771db27 PM |
2203 | /* ??? Lots of these bits are not implemented. */ |
2204 | /* This may enable/disable the MMU, so do a TLB flush. */ | |
00c8cb0a | 2205 | tlb_flush(CPU(cpu), 1); |
2771db27 PM |
2206 | } |
2207 | ||
7da845b0 PM |
2208 | static CPAccessResult ctr_el0_access(CPUARMState *env, const ARMCPRegInfo *ri) |
2209 | { | |
2210 | /* Only accessible in EL0 if SCTLR.UCT is set (and only in AArch64, | |
2211 | * but the AArch32 CTR has its own reginfo struct) | |
2212 | */ | |
2213 | if (arm_current_pl(env) == 0 && !(env->cp15.c1_sys & SCTLR_UCT)) { | |
2214 | return CP_ACCESS_TRAP; | |
2215 | } | |
2216 | return CP_ACCESS_OK; | |
2217 | } | |
2218 | ||
50300698 | 2219 | static const ARMCPRegInfo debug_cp_reginfo[] = { |
50300698 | 2220 | /* DBGDRAR, DBGDSAR: always RAZ since we don't implement memory mapped |
10aae104 PM |
2221 | * debug components. The AArch64 version of DBGDRAR is named MDRAR_EL1; |
2222 | * unlike DBGDRAR it is never accessible from EL0. | |
2223 | * DBGDSAR is deprecated and must RAZ from v8 anyway, so it has no AArch64 | |
2224 | * accessor. | |
50300698 PM |
2225 | */ |
2226 | { .name = "DBGDRAR", .cp = 14, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 0, | |
2227 | .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
10aae104 PM |
2228 | { .name = "MDRAR_EL1", .state = ARM_CP_STATE_AA64, |
2229 | .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 0, | |
2230 | .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
50300698 PM |
2231 | { .name = "DBGDSAR", .cp = 14, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 0, |
2232 | .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
2233 | /* Dummy implementation of monitor debug system control register: | |
10aae104 | 2234 | * we don't support debug. (The 32-bit alias is DBGDSCRext.) |
50300698 | 2235 | */ |
10aae104 PM |
2236 | { .name = "MDSCR_EL1", .state = ARM_CP_STATE_BOTH, |
2237 | .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 2, | |
0e5e8935 PM |
2238 | .access = PL1_RW, |
2239 | .fieldoffset = offsetof(CPUARMState, cp15.mdscr_el1), | |
2240 | .resetvalue = 0 }, | |
50300698 | 2241 | /* We define a dummy WI OSLAR_EL1, because Linux writes to it. */ |
10aae104 PM |
2242 | { .name = "OSLAR_EL1", .state = ARM_CP_STATE_BOTH, |
2243 | .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 4, | |
50300698 PM |
2244 | .access = PL1_W, .type = ARM_CP_NOP }, |
2245 | REGINFO_SENTINEL | |
2246 | }; | |
2247 | ||
2248 | static const ARMCPRegInfo debug_lpae_cp_reginfo[] = { | |
2249 | /* 64 bit access versions of the (dummy) debug registers */ | |
2250 | { .name = "DBGDRAR", .cp = 14, .crm = 1, .opc1 = 0, | |
2251 | .access = PL0_R, .type = ARM_CP_CONST|ARM_CP_64BIT, .resetvalue = 0 }, | |
2252 | { .name = "DBGDSAR", .cp = 14, .crm = 2, .opc1 = 0, | |
2253 | .access = PL0_R, .type = ARM_CP_CONST|ARM_CP_64BIT, .resetvalue = 0 }, | |
2254 | REGINFO_SENTINEL | |
2255 | }; | |
2256 | ||
2257 | static void define_debug_regs(ARMCPU *cpu) | |
0b45451e | 2258 | { |
50300698 PM |
2259 | /* Define v7 and v8 architectural debug registers. |
2260 | * These are just dummy implementations for now. | |
0b45451e PM |
2261 | */ |
2262 | int i; | |
48eb3ae6 PM |
2263 | int wrps, brps; |
2264 | ARMCPRegInfo dbgdidr = { | |
2265 | .name = "DBGDIDR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 0, | |
2266 | .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = cpu->dbgdidr, | |
2267 | }; | |
2268 | ||
2269 | brps = extract32(cpu->dbgdidr, 24, 4); | |
2270 | wrps = extract32(cpu->dbgdidr, 28, 4); | |
2271 | ||
2272 | /* The DBGDIDR and ID_AA64DFR0_EL1 define various properties | |
2273 | * of the debug registers such as number of breakpoints; | |
2274 | * check that if they both exist then they agree. | |
2275 | */ | |
2276 | if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { | |
2277 | assert(extract32(cpu->id_aa64dfr0, 12, 4) == brps); | |
2278 | assert(extract32(cpu->id_aa64dfr0, 20, 4) == wrps); | |
2279 | } | |
0b45451e | 2280 | |
48eb3ae6 | 2281 | define_one_arm_cp_reg(cpu, &dbgdidr); |
50300698 PM |
2282 | define_arm_cp_regs(cpu, debug_cp_reginfo); |
2283 | ||
2284 | if (arm_feature(&cpu->env, ARM_FEATURE_LPAE)) { | |
2285 | define_arm_cp_regs(cpu, debug_lpae_cp_reginfo); | |
2286 | } | |
2287 | ||
48eb3ae6 | 2288 | for (i = 0; i < brps + 1; i++) { |
0b45451e | 2289 | ARMCPRegInfo dbgregs[] = { |
10aae104 PM |
2290 | { .name = "DBGBVR", .state = ARM_CP_STATE_BOTH, |
2291 | .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 4, | |
0b45451e PM |
2292 | .access = PL1_RW, |
2293 | .fieldoffset = offsetof(CPUARMState, cp15.dbgbvr[i]) }, | |
10aae104 PM |
2294 | { .name = "DBGBCR", .state = ARM_CP_STATE_BOTH, |
2295 | .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 5, | |
0b45451e PM |
2296 | .access = PL1_RW, |
2297 | .fieldoffset = offsetof(CPUARMState, cp15.dbgbcr[i]) }, | |
48eb3ae6 PM |
2298 | REGINFO_SENTINEL |
2299 | }; | |
2300 | define_arm_cp_regs(cpu, dbgregs); | |
2301 | } | |
2302 | ||
2303 | for (i = 0; i < wrps + 1; i++) { | |
2304 | ARMCPRegInfo dbgregs[] = { | |
10aae104 PM |
2305 | { .name = "DBGWVR", .state = ARM_CP_STATE_BOTH, |
2306 | .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 6, | |
0b45451e PM |
2307 | .access = PL1_RW, |
2308 | .fieldoffset = offsetof(CPUARMState, cp15.dbgwvr[i]) }, | |
10aae104 PM |
2309 | { .name = "DBGWCR", .state = ARM_CP_STATE_BOTH, |
2310 | .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 7, | |
0b45451e PM |
2311 | .access = PL1_RW, |
2312 | .fieldoffset = offsetof(CPUARMState, cp15.dbgwcr[i]) }, | |
2313 | REGINFO_SENTINEL | |
2314 | }; | |
2315 | define_arm_cp_regs(cpu, dbgregs); | |
2316 | } | |
2317 | } | |
2318 | ||
2ceb98c0 PM |
2319 | void register_cp_regs_for_features(ARMCPU *cpu) |
2320 | { | |
2321 | /* Register all the coprocessor registers based on feature bits */ | |
2322 | CPUARMState *env = &cpu->env; | |
2323 | if (arm_feature(env, ARM_FEATURE_M)) { | |
2324 | /* M profile has no coprocessor registers */ | |
2325 | return; | |
2326 | } | |
2327 | ||
e9aa6c21 | 2328 | define_arm_cp_regs(cpu, cp_reginfo); |
9449fdf6 PM |
2329 | if (!arm_feature(env, ARM_FEATURE_V8)) { |
2330 | /* Must go early as it is full of wildcards that may be | |
2331 | * overridden by later definitions. | |
2332 | */ | |
2333 | define_arm_cp_regs(cpu, not_v8_cp_reginfo); | |
2334 | } | |
2335 | ||
7d57f408 | 2336 | if (arm_feature(env, ARM_FEATURE_V6)) { |
8515a092 PM |
2337 | /* The ID registers all have impdef reset values */ |
2338 | ARMCPRegInfo v6_idregs[] = { | |
0ff644a7 PM |
2339 | { .name = "ID_PFR0", .state = ARM_CP_STATE_BOTH, |
2340 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 0, | |
2341 | .access = PL1_R, .type = ARM_CP_CONST, | |
8515a092 | 2342 | .resetvalue = cpu->id_pfr0 }, |
0ff644a7 PM |
2343 | { .name = "ID_PFR1", .state = ARM_CP_STATE_BOTH, |
2344 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 1, | |
2345 | .access = PL1_R, .type = ARM_CP_CONST, | |
8515a092 | 2346 | .resetvalue = cpu->id_pfr1 }, |
0ff644a7 PM |
2347 | { .name = "ID_DFR0", .state = ARM_CP_STATE_BOTH, |
2348 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 2, | |
2349 | .access = PL1_R, .type = ARM_CP_CONST, | |
8515a092 | 2350 | .resetvalue = cpu->id_dfr0 }, |
0ff644a7 PM |
2351 | { .name = "ID_AFR0", .state = ARM_CP_STATE_BOTH, |
2352 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 3, | |
2353 | .access = PL1_R, .type = ARM_CP_CONST, | |
8515a092 | 2354 | .resetvalue = cpu->id_afr0 }, |
0ff644a7 PM |
2355 | { .name = "ID_MMFR0", .state = ARM_CP_STATE_BOTH, |
2356 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 4, | |
2357 | .access = PL1_R, .type = ARM_CP_CONST, | |
8515a092 | 2358 | .resetvalue = cpu->id_mmfr0 }, |
0ff644a7 PM |
2359 | { .name = "ID_MMFR1", .state = ARM_CP_STATE_BOTH, |
2360 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 5, | |
2361 | .access = PL1_R, .type = ARM_CP_CONST, | |
8515a092 | 2362 | .resetvalue = cpu->id_mmfr1 }, |
0ff644a7 PM |
2363 | { .name = "ID_MMFR2", .state = ARM_CP_STATE_BOTH, |
2364 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 6, | |
2365 | .access = PL1_R, .type = ARM_CP_CONST, | |
8515a092 | 2366 | .resetvalue = cpu->id_mmfr2 }, |
0ff644a7 PM |
2367 | { .name = "ID_MMFR3", .state = ARM_CP_STATE_BOTH, |
2368 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 7, | |
2369 | .access = PL1_R, .type = ARM_CP_CONST, | |
8515a092 | 2370 | .resetvalue = cpu->id_mmfr3 }, |
0ff644a7 PM |
2371 | { .name = "ID_ISAR0", .state = ARM_CP_STATE_BOTH, |
2372 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 0, | |
2373 | .access = PL1_R, .type = ARM_CP_CONST, | |
8515a092 | 2374 | .resetvalue = cpu->id_isar0 }, |
0ff644a7 PM |
2375 | { .name = "ID_ISAR1", .state = ARM_CP_STATE_BOTH, |
2376 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 1, | |
2377 | .access = PL1_R, .type = ARM_CP_CONST, | |
8515a092 | 2378 | .resetvalue = cpu->id_isar1 }, |
0ff644a7 PM |
2379 | { .name = "ID_ISAR2", .state = ARM_CP_STATE_BOTH, |
2380 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 2, | |
2381 | .access = PL1_R, .type = ARM_CP_CONST, | |
8515a092 | 2382 | .resetvalue = cpu->id_isar2 }, |
0ff644a7 PM |
2383 | { .name = "ID_ISAR3", .state = ARM_CP_STATE_BOTH, |
2384 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 3, | |
2385 | .access = PL1_R, .type = ARM_CP_CONST, | |
8515a092 | 2386 | .resetvalue = cpu->id_isar3 }, |
0ff644a7 PM |
2387 | { .name = "ID_ISAR4", .state = ARM_CP_STATE_BOTH, |
2388 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 4, | |
2389 | .access = PL1_R, .type = ARM_CP_CONST, | |
8515a092 | 2390 | .resetvalue = cpu->id_isar4 }, |
0ff644a7 PM |
2391 | { .name = "ID_ISAR5", .state = ARM_CP_STATE_BOTH, |
2392 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 5, | |
2393 | .access = PL1_R, .type = ARM_CP_CONST, | |
8515a092 PM |
2394 | .resetvalue = cpu->id_isar5 }, |
2395 | /* 6..7 are as yet unallocated and must RAZ */ | |
2396 | { .name = "ID_ISAR6", .cp = 15, .crn = 0, .crm = 2, | |
2397 | .opc1 = 0, .opc2 = 6, .access = PL1_R, .type = ARM_CP_CONST, | |
2398 | .resetvalue = 0 }, | |
2399 | { .name = "ID_ISAR7", .cp = 15, .crn = 0, .crm = 2, | |
2400 | .opc1 = 0, .opc2 = 7, .access = PL1_R, .type = ARM_CP_CONST, | |
2401 | .resetvalue = 0 }, | |
2402 | REGINFO_SENTINEL | |
2403 | }; | |
2404 | define_arm_cp_regs(cpu, v6_idregs); | |
7d57f408 PM |
2405 | define_arm_cp_regs(cpu, v6_cp_reginfo); |
2406 | } else { | |
2407 | define_arm_cp_regs(cpu, not_v6_cp_reginfo); | |
2408 | } | |
4d31c596 PM |
2409 | if (arm_feature(env, ARM_FEATURE_V6K)) { |
2410 | define_arm_cp_regs(cpu, v6k_cp_reginfo); | |
2411 | } | |
e9aa6c21 | 2412 | if (arm_feature(env, ARM_FEATURE_V7)) { |
200ac0ef | 2413 | /* v7 performance monitor control register: same implementor |
7c2cb42b AF |
2414 | * field as main ID register, and we implement only the cycle |
2415 | * count register. | |
200ac0ef | 2416 | */ |
7c2cb42b | 2417 | #ifndef CONFIG_USER_ONLY |
200ac0ef PM |
2418 | ARMCPRegInfo pmcr = { |
2419 | .name = "PMCR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 0, | |
8521466b AF |
2420 | .access = PL0_RW, |
2421 | .type = ARM_CP_IO | ARM_CP_NO_MIGRATE, | |
2422 | .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmcr), | |
fcd25206 PM |
2423 | .accessfn = pmreg_access, .writefn = pmcr_write, |
2424 | .raw_writefn = raw_write, | |
200ac0ef | 2425 | }; |
8521466b AF |
2426 | ARMCPRegInfo pmcr64 = { |
2427 | .name = "PMCR_EL0", .state = ARM_CP_STATE_AA64, | |
2428 | .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 0, | |
2429 | .access = PL0_RW, .accessfn = pmreg_access, | |
2430 | .type = ARM_CP_IO, | |
2431 | .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcr), | |
2432 | .resetvalue = cpu->midr & 0xff000000, | |
2433 | .writefn = pmcr_write, .raw_writefn = raw_write, | |
2434 | }; | |
7c2cb42b | 2435 | define_one_arm_cp_reg(cpu, &pmcr); |
8521466b | 2436 | define_one_arm_cp_reg(cpu, &pmcr64); |
7c2cb42b | 2437 | #endif |
776d4e5c | 2438 | ARMCPRegInfo clidr = { |
7da845b0 PM |
2439 | .name = "CLIDR", .state = ARM_CP_STATE_BOTH, |
2440 | .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 1, | |
776d4e5c PM |
2441 | .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = cpu->clidr |
2442 | }; | |
776d4e5c | 2443 | define_one_arm_cp_reg(cpu, &clidr); |
e9aa6c21 | 2444 | define_arm_cp_regs(cpu, v7_cp_reginfo); |
50300698 | 2445 | define_debug_regs(cpu); |
7d57f408 PM |
2446 | } else { |
2447 | define_arm_cp_regs(cpu, not_v7_cp_reginfo); | |
e9aa6c21 | 2448 | } |
b0d2b7d0 | 2449 | if (arm_feature(env, ARM_FEATURE_V8)) { |
e60cef86 PM |
2450 | /* AArch64 ID registers, which all have impdef reset values */ |
2451 | ARMCPRegInfo v8_idregs[] = { | |
2452 | { .name = "ID_AA64PFR0_EL1", .state = ARM_CP_STATE_AA64, | |
2453 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 0, | |
2454 | .access = PL1_R, .type = ARM_CP_CONST, | |
2455 | .resetvalue = cpu->id_aa64pfr0 }, | |
2456 | { .name = "ID_AA64PFR1_EL1", .state = ARM_CP_STATE_AA64, | |
2457 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 1, | |
2458 | .access = PL1_R, .type = ARM_CP_CONST, | |
2459 | .resetvalue = cpu->id_aa64pfr1}, | |
2460 | { .name = "ID_AA64DFR0_EL1", .state = ARM_CP_STATE_AA64, | |
2461 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 0, | |
2462 | .access = PL1_R, .type = ARM_CP_CONST, | |
5d831be2 | 2463 | /* We mask out the PMUVer field, because we don't currently |
9225d739 PM |
2464 | * implement the PMU. Not advertising it prevents the guest |
2465 | * from trying to use it and getting UNDEFs on registers we | |
2466 | * don't implement. | |
2467 | */ | |
2468 | .resetvalue = cpu->id_aa64dfr0 & ~0xf00 }, | |
e60cef86 PM |
2469 | { .name = "ID_AA64DFR1_EL1", .state = ARM_CP_STATE_AA64, |
2470 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 1, | |
2471 | .access = PL1_R, .type = ARM_CP_CONST, | |
2472 | .resetvalue = cpu->id_aa64dfr1 }, | |
2473 | { .name = "ID_AA64AFR0_EL1", .state = ARM_CP_STATE_AA64, | |
2474 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 4, | |
2475 | .access = PL1_R, .type = ARM_CP_CONST, | |
2476 | .resetvalue = cpu->id_aa64afr0 }, | |
2477 | { .name = "ID_AA64AFR1_EL1", .state = ARM_CP_STATE_AA64, | |
2478 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 5, | |
2479 | .access = PL1_R, .type = ARM_CP_CONST, | |
2480 | .resetvalue = cpu->id_aa64afr1 }, | |
2481 | { .name = "ID_AA64ISAR0_EL1", .state = ARM_CP_STATE_AA64, | |
2482 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 0, | |
2483 | .access = PL1_R, .type = ARM_CP_CONST, | |
2484 | .resetvalue = cpu->id_aa64isar0 }, | |
2485 | { .name = "ID_AA64ISAR1_EL1", .state = ARM_CP_STATE_AA64, | |
2486 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 1, | |
2487 | .access = PL1_R, .type = ARM_CP_CONST, | |
2488 | .resetvalue = cpu->id_aa64isar1 }, | |
2489 | { .name = "ID_AA64MMFR0_EL1", .state = ARM_CP_STATE_AA64, | |
2490 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 0, | |
2491 | .access = PL1_R, .type = ARM_CP_CONST, | |
2492 | .resetvalue = cpu->id_aa64mmfr0 }, | |
2493 | { .name = "ID_AA64MMFR1_EL1", .state = ARM_CP_STATE_AA64, | |
2494 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 1, | |
2495 | .access = PL1_R, .type = ARM_CP_CONST, | |
2496 | .resetvalue = cpu->id_aa64mmfr1 }, | |
a50c0f51 PM |
2497 | { .name = "MVFR0_EL1", .state = ARM_CP_STATE_AA64, |
2498 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 0, | |
2499 | .access = PL1_R, .type = ARM_CP_CONST, | |
2500 | .resetvalue = cpu->mvfr0 }, | |
2501 | { .name = "MVFR1_EL1", .state = ARM_CP_STATE_AA64, | |
2502 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 1, | |
2503 | .access = PL1_R, .type = ARM_CP_CONST, | |
2504 | .resetvalue = cpu->mvfr1 }, | |
2505 | { .name = "MVFR2_EL1", .state = ARM_CP_STATE_AA64, | |
2506 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 2, | |
2507 | .access = PL1_R, .type = ARM_CP_CONST, | |
2508 | .resetvalue = cpu->mvfr2 }, | |
e60cef86 PM |
2509 | REGINFO_SENTINEL |
2510 | }; | |
3933443e PM |
2511 | ARMCPRegInfo rvbar = { |
2512 | .name = "RVBAR_EL1", .state = ARM_CP_STATE_AA64, | |
2513 | .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 0, .opc2 = 2, | |
2514 | .type = ARM_CP_CONST, .access = PL1_R, .resetvalue = cpu->rvbar | |
2515 | }; | |
2516 | define_one_arm_cp_reg(cpu, &rvbar); | |
e60cef86 | 2517 | define_arm_cp_regs(cpu, v8_idregs); |
b0d2b7d0 PM |
2518 | define_arm_cp_regs(cpu, v8_cp_reginfo); |
2519 | } | |
3b685ba7 EI |
2520 | if (arm_feature(env, ARM_FEATURE_EL2)) { |
2521 | define_arm_cp_regs(cpu, v8_el2_cp_reginfo); | |
d42e3c26 EI |
2522 | } else { |
2523 | /* If EL2 is missing but higher ELs are enabled, we need to | |
2524 | * register the no_el2 reginfos. | |
2525 | */ | |
2526 | if (arm_feature(env, ARM_FEATURE_EL3)) { | |
2527 | define_arm_cp_regs(cpu, v8_el3_no_el2_cp_reginfo); | |
2528 | } | |
3b685ba7 | 2529 | } |
81547d66 EI |
2530 | if (arm_feature(env, ARM_FEATURE_EL3)) { |
2531 | define_arm_cp_regs(cpu, v8_el3_cp_reginfo); | |
2532 | } | |
18032bec PM |
2533 | if (arm_feature(env, ARM_FEATURE_MPU)) { |
2534 | /* These are the MPU registers prior to PMSAv6. Any new | |
2535 | * PMSA core later than the ARM946 will require that we | |
2536 | * implement the PMSAv6 or PMSAv7 registers, which are | |
2537 | * completely different. | |
2538 | */ | |
2539 | assert(!arm_feature(env, ARM_FEATURE_V6)); | |
2540 | define_arm_cp_regs(cpu, pmsav5_cp_reginfo); | |
2541 | } else { | |
2542 | define_arm_cp_regs(cpu, vmsa_cp_reginfo); | |
2543 | } | |
c326b979 PM |
2544 | if (arm_feature(env, ARM_FEATURE_THUMB2EE)) { |
2545 | define_arm_cp_regs(cpu, t2ee_cp_reginfo); | |
2546 | } | |
6cc7a3ae PM |
2547 | if (arm_feature(env, ARM_FEATURE_GENERIC_TIMER)) { |
2548 | define_arm_cp_regs(cpu, generic_timer_cp_reginfo); | |
2549 | } | |
4a501606 PM |
2550 | if (arm_feature(env, ARM_FEATURE_VAPA)) { |
2551 | define_arm_cp_regs(cpu, vapa_cp_reginfo); | |
2552 | } | |
c4804214 PM |
2553 | if (arm_feature(env, ARM_FEATURE_CACHE_TEST_CLEAN)) { |
2554 | define_arm_cp_regs(cpu, cache_test_clean_cp_reginfo); | |
2555 | } | |
2556 | if (arm_feature(env, ARM_FEATURE_CACHE_DIRTY_REG)) { | |
2557 | define_arm_cp_regs(cpu, cache_dirty_status_cp_reginfo); | |
2558 | } | |
2559 | if (arm_feature(env, ARM_FEATURE_CACHE_BLOCK_OPS)) { | |
2560 | define_arm_cp_regs(cpu, cache_block_ops_cp_reginfo); | |
2561 | } | |
18032bec PM |
2562 | if (arm_feature(env, ARM_FEATURE_OMAPCP)) { |
2563 | define_arm_cp_regs(cpu, omap_cp_reginfo); | |
2564 | } | |
34f90529 PM |
2565 | if (arm_feature(env, ARM_FEATURE_STRONGARM)) { |
2566 | define_arm_cp_regs(cpu, strongarm_cp_reginfo); | |
2567 | } | |
1047b9d7 PM |
2568 | if (arm_feature(env, ARM_FEATURE_XSCALE)) { |
2569 | define_arm_cp_regs(cpu, xscale_cp_reginfo); | |
2570 | } | |
2571 | if (arm_feature(env, ARM_FEATURE_DUMMY_C15_REGS)) { | |
2572 | define_arm_cp_regs(cpu, dummy_c15_cp_reginfo); | |
2573 | } | |
7ac681cf PM |
2574 | if (arm_feature(env, ARM_FEATURE_LPAE)) { |
2575 | define_arm_cp_regs(cpu, lpae_cp_reginfo); | |
2576 | } | |
7884849c PM |
2577 | /* Slightly awkwardly, the OMAP and StrongARM cores need all of |
2578 | * cp15 crn=0 to be writes-ignored, whereas for other cores they should | |
2579 | * be read-only (ie write causes UNDEF exception). | |
2580 | */ | |
2581 | { | |
00a29f3d PM |
2582 | ARMCPRegInfo id_pre_v8_midr_cp_reginfo[] = { |
2583 | /* Pre-v8 MIDR space. | |
2584 | * Note that the MIDR isn't a simple constant register because | |
7884849c PM |
2585 | * of the TI925 behaviour where writes to another register can |
2586 | * cause the MIDR value to change. | |
97ce8d61 PC |
2587 | * |
2588 | * Unimplemented registers in the c15 0 0 0 space default to | |
2589 | * MIDR. Define MIDR first as this entire space, then CTR, TCMTR | |
2590 | * and friends override accordingly. | |
7884849c PM |
2591 | */ |
2592 | { .name = "MIDR", | |
97ce8d61 | 2593 | .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = CP_ANY, |
7884849c | 2594 | .access = PL1_R, .resetvalue = cpu->midr, |
d4e6df63 | 2595 | .writefn = arm_cp_write_ignore, .raw_writefn = raw_write, |
97ce8d61 PC |
2596 | .fieldoffset = offsetof(CPUARMState, cp15.c0_cpuid), |
2597 | .type = ARM_CP_OVERRIDE }, | |
7884849c PM |
2598 | /* crn = 0 op1 = 0 crm = 3..7 : currently unassigned; we RAZ. */ |
2599 | { .name = "DUMMY", | |
2600 | .cp = 15, .crn = 0, .crm = 3, .opc1 = 0, .opc2 = CP_ANY, | |
2601 | .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
2602 | { .name = "DUMMY", | |
2603 | .cp = 15, .crn = 0, .crm = 4, .opc1 = 0, .opc2 = CP_ANY, | |
2604 | .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
2605 | { .name = "DUMMY", | |
2606 | .cp = 15, .crn = 0, .crm = 5, .opc1 = 0, .opc2 = CP_ANY, | |
2607 | .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
2608 | { .name = "DUMMY", | |
2609 | .cp = 15, .crn = 0, .crm = 6, .opc1 = 0, .opc2 = CP_ANY, | |
2610 | .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
2611 | { .name = "DUMMY", | |
2612 | .cp = 15, .crn = 0, .crm = 7, .opc1 = 0, .opc2 = CP_ANY, | |
2613 | .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
2614 | REGINFO_SENTINEL | |
2615 | }; | |
00a29f3d PM |
2616 | ARMCPRegInfo id_v8_midr_cp_reginfo[] = { |
2617 | /* v8 MIDR -- the wildcard isn't necessary, and nor is the | |
2618 | * variable-MIDR TI925 behaviour. Instead we have a single | |
2619 | * (strictly speaking IMPDEF) alias of the MIDR, REVIDR. | |
2620 | */ | |
2621 | { .name = "MIDR_EL1", .state = ARM_CP_STATE_BOTH, | |
2622 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 0, .opc2 = 0, | |
2623 | .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = cpu->midr }, | |
2624 | { .name = "REVIDR_EL1", .state = ARM_CP_STATE_BOTH, | |
2625 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 0, .opc2 = 6, | |
2626 | .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = cpu->midr }, | |
2627 | REGINFO_SENTINEL | |
2628 | }; | |
2629 | ARMCPRegInfo id_cp_reginfo[] = { | |
2630 | /* These are common to v8 and pre-v8 */ | |
2631 | { .name = "CTR", | |
2632 | .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 1, | |
2633 | .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = cpu->ctr }, | |
2634 | { .name = "CTR_EL0", .state = ARM_CP_STATE_AA64, | |
2635 | .opc0 = 3, .opc1 = 3, .opc2 = 1, .crn = 0, .crm = 0, | |
2636 | .access = PL0_R, .accessfn = ctr_el0_access, | |
2637 | .type = ARM_CP_CONST, .resetvalue = cpu->ctr }, | |
2638 | /* TCMTR and TLBTR exist in v8 but have no 64-bit versions */ | |
2639 | { .name = "TCMTR", | |
2640 | .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 2, | |
2641 | .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
2642 | { .name = "TLBTR", | |
2643 | .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 3, | |
2644 | .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
2645 | REGINFO_SENTINEL | |
2646 | }; | |
7884849c PM |
2647 | ARMCPRegInfo crn0_wi_reginfo = { |
2648 | .name = "CRN0_WI", .cp = 15, .crn = 0, .crm = CP_ANY, | |
2649 | .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_W, | |
2650 | .type = ARM_CP_NOP | ARM_CP_OVERRIDE | |
2651 | }; | |
2652 | if (arm_feature(env, ARM_FEATURE_OMAPCP) || | |
2653 | arm_feature(env, ARM_FEATURE_STRONGARM)) { | |
2654 | ARMCPRegInfo *r; | |
2655 | /* Register the blanket "writes ignored" value first to cover the | |
a703eda1 PC |
2656 | * whole space. Then update the specific ID registers to allow write |
2657 | * access, so that they ignore writes rather than causing them to | |
2658 | * UNDEF. | |
7884849c PM |
2659 | */ |
2660 | define_one_arm_cp_reg(cpu, &crn0_wi_reginfo); | |
00a29f3d PM |
2661 | for (r = id_pre_v8_midr_cp_reginfo; |
2662 | r->type != ARM_CP_SENTINEL; r++) { | |
2663 | r->access = PL1_RW; | |
2664 | } | |
7884849c PM |
2665 | for (r = id_cp_reginfo; r->type != ARM_CP_SENTINEL; r++) { |
2666 | r->access = PL1_RW; | |
7884849c | 2667 | } |
7884849c | 2668 | } |
00a29f3d PM |
2669 | if (arm_feature(env, ARM_FEATURE_V8)) { |
2670 | define_arm_cp_regs(cpu, id_v8_midr_cp_reginfo); | |
2671 | } else { | |
2672 | define_arm_cp_regs(cpu, id_pre_v8_midr_cp_reginfo); | |
2673 | } | |
a703eda1 | 2674 | define_arm_cp_regs(cpu, id_cp_reginfo); |
7884849c PM |
2675 | } |
2676 | ||
97ce8d61 PC |
2677 | if (arm_feature(env, ARM_FEATURE_MPIDR)) { |
2678 | define_arm_cp_regs(cpu, mpidr_cp_reginfo); | |
2679 | } | |
2680 | ||
2771db27 PM |
2681 | if (arm_feature(env, ARM_FEATURE_AUXCR)) { |
2682 | ARMCPRegInfo auxcr = { | |
2eef0bf8 PM |
2683 | .name = "ACTLR_EL1", .state = ARM_CP_STATE_BOTH, |
2684 | .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 1, | |
2771db27 PM |
2685 | .access = PL1_RW, .type = ARM_CP_CONST, |
2686 | .resetvalue = cpu->reset_auxcr | |
2687 | }; | |
2688 | define_one_arm_cp_reg(cpu, &auxcr); | |
2689 | } | |
2690 | ||
d8ba780b | 2691 | if (arm_feature(env, ARM_FEATURE_CBAR)) { |
f318cec6 PM |
2692 | if (arm_feature(env, ARM_FEATURE_AARCH64)) { |
2693 | /* 32 bit view is [31:18] 0...0 [43:32]. */ | |
2694 | uint32_t cbar32 = (extract64(cpu->reset_cbar, 18, 14) << 18) | |
2695 | | extract64(cpu->reset_cbar, 32, 12); | |
2696 | ARMCPRegInfo cbar_reginfo[] = { | |
2697 | { .name = "CBAR", | |
2698 | .type = ARM_CP_CONST, | |
2699 | .cp = 15, .crn = 15, .crm = 0, .opc1 = 4, .opc2 = 0, | |
2700 | .access = PL1_R, .resetvalue = cpu->reset_cbar }, | |
2701 | { .name = "CBAR_EL1", .state = ARM_CP_STATE_AA64, | |
2702 | .type = ARM_CP_CONST, | |
2703 | .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 3, .opc2 = 0, | |
2704 | .access = PL1_R, .resetvalue = cbar32 }, | |
2705 | REGINFO_SENTINEL | |
2706 | }; | |
2707 | /* We don't implement a r/w 64 bit CBAR currently */ | |
2708 | assert(arm_feature(env, ARM_FEATURE_CBAR_RO)); | |
2709 | define_arm_cp_regs(cpu, cbar_reginfo); | |
2710 | } else { | |
2711 | ARMCPRegInfo cbar = { | |
2712 | .name = "CBAR", | |
2713 | .cp = 15, .crn = 15, .crm = 0, .opc1 = 4, .opc2 = 0, | |
2714 | .access = PL1_R|PL3_W, .resetvalue = cpu->reset_cbar, | |
2715 | .fieldoffset = offsetof(CPUARMState, | |
2716 | cp15.c15_config_base_address) | |
2717 | }; | |
2718 | if (arm_feature(env, ARM_FEATURE_CBAR_RO)) { | |
2719 | cbar.access = PL1_R; | |
2720 | cbar.fieldoffset = 0; | |
2721 | cbar.type = ARM_CP_CONST; | |
2722 | } | |
2723 | define_one_arm_cp_reg(cpu, &cbar); | |
2724 | } | |
d8ba780b PC |
2725 | } |
2726 | ||
2771db27 PM |
2727 | /* Generic registers whose values depend on the implementation */ |
2728 | { | |
2729 | ARMCPRegInfo sctlr = { | |
5ebafdf3 PM |
2730 | .name = "SCTLR", .state = ARM_CP_STATE_BOTH, |
2731 | .opc0 = 3, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 0, | |
2771db27 | 2732 | .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c1_sys), |
d4e6df63 PM |
2733 | .writefn = sctlr_write, .resetvalue = cpu->reset_sctlr, |
2734 | .raw_writefn = raw_write, | |
2771db27 PM |
2735 | }; |
2736 | if (arm_feature(env, ARM_FEATURE_XSCALE)) { | |
2737 | /* Normally we would always end the TB on an SCTLR write, but Linux | |
2738 | * arch/arm/mach-pxa/sleep.S expects two instructions following | |
2739 | * an MMU enable to execute from cache. Imitate this behaviour. | |
2740 | */ | |
2741 | sctlr.type |= ARM_CP_SUPPRESS_TB_END; | |
2742 | } | |
2743 | define_one_arm_cp_reg(cpu, &sctlr); | |
2744 | } | |
2ceb98c0 PM |
2745 | } |
2746 | ||
778c3a06 | 2747 | ARMCPU *cpu_arm_init(const char *cpu_model) |
40f137e1 | 2748 | { |
9262685b | 2749 | return ARM_CPU(cpu_generic_init(TYPE_ARM_CPU, cpu_model)); |
14969266 AF |
2750 | } |
2751 | ||
2752 | void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu) | |
2753 | { | |
22169d41 | 2754 | CPUState *cs = CPU(cpu); |
14969266 AF |
2755 | CPUARMState *env = &cpu->env; |
2756 | ||
6a669427 PM |
2757 | if (arm_feature(env, ARM_FEATURE_AARCH64)) { |
2758 | gdb_register_coprocessor(cs, aarch64_fpu_gdb_get_reg, | |
2759 | aarch64_fpu_gdb_set_reg, | |
2760 | 34, "aarch64-fpu.xml", 0); | |
2761 | } else if (arm_feature(env, ARM_FEATURE_NEON)) { | |
22169d41 | 2762 | gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg, |
56aebc89 PB |
2763 | 51, "arm-neon.xml", 0); |
2764 | } else if (arm_feature(env, ARM_FEATURE_VFP3)) { | |
22169d41 | 2765 | gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg, |
56aebc89 PB |
2766 | 35, "arm-vfp3.xml", 0); |
2767 | } else if (arm_feature(env, ARM_FEATURE_VFP)) { | |
22169d41 | 2768 | gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg, |
56aebc89 PB |
2769 | 19, "arm-vfp.xml", 0); |
2770 | } | |
40f137e1 PB |
2771 | } |
2772 | ||
777dc784 PM |
2773 | /* Sort alphabetically by type name, except for "any". */ |
2774 | static gint arm_cpu_list_compare(gconstpointer a, gconstpointer b) | |
5adb4839 | 2775 | { |
777dc784 PM |
2776 | ObjectClass *class_a = (ObjectClass *)a; |
2777 | ObjectClass *class_b = (ObjectClass *)b; | |
2778 | const char *name_a, *name_b; | |
5adb4839 | 2779 | |
777dc784 PM |
2780 | name_a = object_class_get_name(class_a); |
2781 | name_b = object_class_get_name(class_b); | |
51492fd1 | 2782 | if (strcmp(name_a, "any-" TYPE_ARM_CPU) == 0) { |
777dc784 | 2783 | return 1; |
51492fd1 | 2784 | } else if (strcmp(name_b, "any-" TYPE_ARM_CPU) == 0) { |
777dc784 PM |
2785 | return -1; |
2786 | } else { | |
2787 | return strcmp(name_a, name_b); | |
5adb4839 PB |
2788 | } |
2789 | } | |
2790 | ||
777dc784 | 2791 | static void arm_cpu_list_entry(gpointer data, gpointer user_data) |
40f137e1 | 2792 | { |
777dc784 | 2793 | ObjectClass *oc = data; |
92a31361 | 2794 | CPUListState *s = user_data; |
51492fd1 AF |
2795 | const char *typename; |
2796 | char *name; | |
3371d272 | 2797 | |
51492fd1 AF |
2798 | typename = object_class_get_name(oc); |
2799 | name = g_strndup(typename, strlen(typename) - strlen("-" TYPE_ARM_CPU)); | |
777dc784 | 2800 | (*s->cpu_fprintf)(s->file, " %s\n", |
51492fd1 AF |
2801 | name); |
2802 | g_free(name); | |
777dc784 PM |
2803 | } |
2804 | ||
2805 | void arm_cpu_list(FILE *f, fprintf_function cpu_fprintf) | |
2806 | { | |
92a31361 | 2807 | CPUListState s = { |
777dc784 PM |
2808 | .file = f, |
2809 | .cpu_fprintf = cpu_fprintf, | |
2810 | }; | |
2811 | GSList *list; | |
2812 | ||
2813 | list = object_class_get_list(TYPE_ARM_CPU, false); | |
2814 | list = g_slist_sort(list, arm_cpu_list_compare); | |
2815 | (*cpu_fprintf)(f, "Available CPUs:\n"); | |
2816 | g_slist_foreach(list, arm_cpu_list_entry, &s); | |
2817 | g_slist_free(list); | |
a96c0514 PM |
2818 | #ifdef CONFIG_KVM |
2819 | /* The 'host' CPU type is dynamically registered only if KVM is | |
2820 | * enabled, so we have to special-case it here: | |
2821 | */ | |
2822 | (*cpu_fprintf)(f, " host (only available in KVM mode)\n"); | |
2823 | #endif | |
40f137e1 PB |
2824 | } |
2825 | ||
78027bb6 CR |
2826 | static void arm_cpu_add_definition(gpointer data, gpointer user_data) |
2827 | { | |
2828 | ObjectClass *oc = data; | |
2829 | CpuDefinitionInfoList **cpu_list = user_data; | |
2830 | CpuDefinitionInfoList *entry; | |
2831 | CpuDefinitionInfo *info; | |
2832 | const char *typename; | |
2833 | ||
2834 | typename = object_class_get_name(oc); | |
2835 | info = g_malloc0(sizeof(*info)); | |
2836 | info->name = g_strndup(typename, | |
2837 | strlen(typename) - strlen("-" TYPE_ARM_CPU)); | |
2838 | ||
2839 | entry = g_malloc0(sizeof(*entry)); | |
2840 | entry->value = info; | |
2841 | entry->next = *cpu_list; | |
2842 | *cpu_list = entry; | |
2843 | } | |
2844 | ||
2845 | CpuDefinitionInfoList *arch_query_cpu_definitions(Error **errp) | |
2846 | { | |
2847 | CpuDefinitionInfoList *cpu_list = NULL; | |
2848 | GSList *list; | |
2849 | ||
2850 | list = object_class_get_list(TYPE_ARM_CPU, false); | |
2851 | g_slist_foreach(list, arm_cpu_add_definition, &cpu_list); | |
2852 | g_slist_free(list); | |
2853 | ||
2854 | return cpu_list; | |
2855 | } | |
2856 | ||
6e6efd61 | 2857 | static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r, |
f5a0a5a5 PM |
2858 | void *opaque, int state, |
2859 | int crm, int opc1, int opc2) | |
6e6efd61 PM |
2860 | { |
2861 | /* Private utility function for define_one_arm_cp_reg_with_opaque(): | |
2862 | * add a single reginfo struct to the hash table. | |
2863 | */ | |
2864 | uint32_t *key = g_new(uint32_t, 1); | |
2865 | ARMCPRegInfo *r2 = g_memdup(r, sizeof(ARMCPRegInfo)); | |
2866 | int is64 = (r->type & ARM_CP_64BIT) ? 1 : 0; | |
f5a0a5a5 PM |
2867 | if (r->state == ARM_CP_STATE_BOTH && state == ARM_CP_STATE_AA32) { |
2868 | /* The AArch32 view of a shared register sees the lower 32 bits | |
2869 | * of a 64 bit backing field. It is not migratable as the AArch64 | |
2870 | * view handles that. AArch64 also handles reset. | |
58a1d8ce | 2871 | * We assume it is a cp15 register if the .cp field is left unset. |
f5a0a5a5 | 2872 | */ |
58a1d8ce PM |
2873 | if (r2->cp == 0) { |
2874 | r2->cp = 15; | |
2875 | } | |
f5a0a5a5 PM |
2876 | r2->type |= ARM_CP_NO_MIGRATE; |
2877 | r2->resetfn = arm_cp_reset_ignore; | |
2878 | #ifdef HOST_WORDS_BIGENDIAN | |
2879 | if (r2->fieldoffset) { | |
2880 | r2->fieldoffset += sizeof(uint32_t); | |
2881 | } | |
2882 | #endif | |
2883 | } | |
2884 | if (state == ARM_CP_STATE_AA64) { | |
2885 | /* To allow abbreviation of ARMCPRegInfo | |
2886 | * definitions, we treat cp == 0 as equivalent to | |
2887 | * the value for "standard guest-visible sysreg". | |
58a1d8ce PM |
2888 | * STATE_BOTH definitions are also always "standard |
2889 | * sysreg" in their AArch64 view (the .cp value may | |
2890 | * be non-zero for the benefit of the AArch32 view). | |
f5a0a5a5 | 2891 | */ |
58a1d8ce | 2892 | if (r->cp == 0 || r->state == ARM_CP_STATE_BOTH) { |
f5a0a5a5 PM |
2893 | r2->cp = CP_REG_ARM64_SYSREG_CP; |
2894 | } | |
2895 | *key = ENCODE_AA64_CP_REG(r2->cp, r2->crn, crm, | |
2896 | r2->opc0, opc1, opc2); | |
2897 | } else { | |
2898 | *key = ENCODE_CP_REG(r2->cp, is64, r2->crn, crm, opc1, opc2); | |
2899 | } | |
6e6efd61 PM |
2900 | if (opaque) { |
2901 | r2->opaque = opaque; | |
2902 | } | |
67ed771d PM |
2903 | /* reginfo passed to helpers is correct for the actual access, |
2904 | * and is never ARM_CP_STATE_BOTH: | |
2905 | */ | |
2906 | r2->state = state; | |
6e6efd61 PM |
2907 | /* Make sure reginfo passed to helpers for wildcarded regs |
2908 | * has the correct crm/opc1/opc2 for this reg, not CP_ANY: | |
2909 | */ | |
2910 | r2->crm = crm; | |
2911 | r2->opc1 = opc1; | |
2912 | r2->opc2 = opc2; | |
2913 | /* By convention, for wildcarded registers only the first | |
2914 | * entry is used for migration; the others are marked as | |
2915 | * NO_MIGRATE so we don't try to transfer the register | |
2916 | * multiple times. Special registers (ie NOP/WFI) are | |
2917 | * never migratable. | |
2918 | */ | |
2919 | if ((r->type & ARM_CP_SPECIAL) || | |
2920 | ((r->crm == CP_ANY) && crm != 0) || | |
2921 | ((r->opc1 == CP_ANY) && opc1 != 0) || | |
2922 | ((r->opc2 == CP_ANY) && opc2 != 0)) { | |
2923 | r2->type |= ARM_CP_NO_MIGRATE; | |
2924 | } | |
2925 | ||
2926 | /* Overriding of an existing definition must be explicitly | |
2927 | * requested. | |
2928 | */ | |
2929 | if (!(r->type & ARM_CP_OVERRIDE)) { | |
2930 | ARMCPRegInfo *oldreg; | |
2931 | oldreg = g_hash_table_lookup(cpu->cp_regs, key); | |
2932 | if (oldreg && !(oldreg->type & ARM_CP_OVERRIDE)) { | |
2933 | fprintf(stderr, "Register redefined: cp=%d %d bit " | |
2934 | "crn=%d crm=%d opc1=%d opc2=%d, " | |
2935 | "was %s, now %s\n", r2->cp, 32 + 32 * is64, | |
2936 | r2->crn, r2->crm, r2->opc1, r2->opc2, | |
2937 | oldreg->name, r2->name); | |
2938 | g_assert_not_reached(); | |
2939 | } | |
2940 | } | |
2941 | g_hash_table_insert(cpu->cp_regs, key, r2); | |
2942 | } | |
2943 | ||
2944 | ||
4b6a83fb PM |
2945 | void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu, |
2946 | const ARMCPRegInfo *r, void *opaque) | |
2947 | { | |
2948 | /* Define implementations of coprocessor registers. | |
2949 | * We store these in a hashtable because typically | |
2950 | * there are less than 150 registers in a space which | |
2951 | * is 16*16*16*8*8 = 262144 in size. | |
2952 | * Wildcarding is supported for the crm, opc1 and opc2 fields. | |
2953 | * If a register is defined twice then the second definition is | |
2954 | * used, so this can be used to define some generic registers and | |
2955 | * then override them with implementation specific variations. | |
2956 | * At least one of the original and the second definition should | |
2957 | * include ARM_CP_OVERRIDE in its type bits -- this is just a guard | |
2958 | * against accidental use. | |
f5a0a5a5 PM |
2959 | * |
2960 | * The state field defines whether the register is to be | |
2961 | * visible in the AArch32 or AArch64 execution state. If the | |
2962 | * state is set to ARM_CP_STATE_BOTH then we synthesise a | |
2963 | * reginfo structure for the AArch32 view, which sees the lower | |
2964 | * 32 bits of the 64 bit register. | |
2965 | * | |
2966 | * Only registers visible in AArch64 may set r->opc0; opc0 cannot | |
2967 | * be wildcarded. AArch64 registers are always considered to be 64 | |
2968 | * bits; the ARM_CP_64BIT* flag applies only to the AArch32 view of | |
2969 | * the register, if any. | |
4b6a83fb | 2970 | */ |
f5a0a5a5 | 2971 | int crm, opc1, opc2, state; |
4b6a83fb PM |
2972 | int crmmin = (r->crm == CP_ANY) ? 0 : r->crm; |
2973 | int crmmax = (r->crm == CP_ANY) ? 15 : r->crm; | |
2974 | int opc1min = (r->opc1 == CP_ANY) ? 0 : r->opc1; | |
2975 | int opc1max = (r->opc1 == CP_ANY) ? 7 : r->opc1; | |
2976 | int opc2min = (r->opc2 == CP_ANY) ? 0 : r->opc2; | |
2977 | int opc2max = (r->opc2 == CP_ANY) ? 7 : r->opc2; | |
2978 | /* 64 bit registers have only CRm and Opc1 fields */ | |
2979 | assert(!((r->type & ARM_CP_64BIT) && (r->opc2 || r->crn))); | |
f5a0a5a5 PM |
2980 | /* op0 only exists in the AArch64 encodings */ |
2981 | assert((r->state != ARM_CP_STATE_AA32) || (r->opc0 == 0)); | |
2982 | /* AArch64 regs are all 64 bit so ARM_CP_64BIT is meaningless */ | |
2983 | assert((r->state != ARM_CP_STATE_AA64) || !(r->type & ARM_CP_64BIT)); | |
2984 | /* The AArch64 pseudocode CheckSystemAccess() specifies that op1 | |
2985 | * encodes a minimum access level for the register. We roll this | |
2986 | * runtime check into our general permission check code, so check | |
2987 | * here that the reginfo's specified permissions are strict enough | |
2988 | * to encompass the generic architectural permission check. | |
2989 | */ | |
2990 | if (r->state != ARM_CP_STATE_AA32) { | |
2991 | int mask = 0; | |
2992 | switch (r->opc1) { | |
2993 | case 0: case 1: case 2: | |
2994 | /* min_EL EL1 */ | |
2995 | mask = PL1_RW; | |
2996 | break; | |
2997 | case 3: | |
2998 | /* min_EL EL0 */ | |
2999 | mask = PL0_RW; | |
3000 | break; | |
3001 | case 4: | |
3002 | /* min_EL EL2 */ | |
3003 | mask = PL2_RW; | |
3004 | break; | |
3005 | case 5: | |
3006 | /* unallocated encoding, so not possible */ | |
3007 | assert(false); | |
3008 | break; | |
3009 | case 6: | |
3010 | /* min_EL EL3 */ | |
3011 | mask = PL3_RW; | |
3012 | break; | |
3013 | case 7: | |
3014 | /* min_EL EL1, secure mode only (we don't check the latter) */ | |
3015 | mask = PL1_RW; | |
3016 | break; | |
3017 | default: | |
3018 | /* broken reginfo with out-of-range opc1 */ | |
3019 | assert(false); | |
3020 | break; | |
3021 | } | |
3022 | /* assert our permissions are not too lax (stricter is fine) */ | |
3023 | assert((r->access & ~mask) == 0); | |
3024 | } | |
3025 | ||
4b6a83fb PM |
3026 | /* Check that the register definition has enough info to handle |
3027 | * reads and writes if they are permitted. | |
3028 | */ | |
3029 | if (!(r->type & (ARM_CP_SPECIAL|ARM_CP_CONST))) { | |
3030 | if (r->access & PL3_R) { | |
3031 | assert(r->fieldoffset || r->readfn); | |
3032 | } | |
3033 | if (r->access & PL3_W) { | |
3034 | assert(r->fieldoffset || r->writefn); | |
3035 | } | |
3036 | } | |
3037 | /* Bad type field probably means missing sentinel at end of reg list */ | |
3038 | assert(cptype_valid(r->type)); | |
3039 | for (crm = crmmin; crm <= crmmax; crm++) { | |
3040 | for (opc1 = opc1min; opc1 <= opc1max; opc1++) { | |
3041 | for (opc2 = opc2min; opc2 <= opc2max; opc2++) { | |
f5a0a5a5 PM |
3042 | for (state = ARM_CP_STATE_AA32; |
3043 | state <= ARM_CP_STATE_AA64; state++) { | |
3044 | if (r->state != state && r->state != ARM_CP_STATE_BOTH) { | |
3045 | continue; | |
3046 | } | |
3047 | add_cpreg_to_hashtable(cpu, r, opaque, state, | |
3048 | crm, opc1, opc2); | |
3049 | } | |
4b6a83fb PM |
3050 | } |
3051 | } | |
3052 | } | |
3053 | } | |
3054 | ||
3055 | void define_arm_cp_regs_with_opaque(ARMCPU *cpu, | |
3056 | const ARMCPRegInfo *regs, void *opaque) | |
3057 | { | |
3058 | /* Define a whole list of registers */ | |
3059 | const ARMCPRegInfo *r; | |
3060 | for (r = regs; r->type != ARM_CP_SENTINEL; r++) { | |
3061 | define_one_arm_cp_reg_with_opaque(cpu, r, opaque); | |
3062 | } | |
3063 | } | |
3064 | ||
60322b39 | 3065 | const ARMCPRegInfo *get_arm_cp_reginfo(GHashTable *cpregs, uint32_t encoded_cp) |
4b6a83fb | 3066 | { |
60322b39 | 3067 | return g_hash_table_lookup(cpregs, &encoded_cp); |
4b6a83fb PM |
3068 | } |
3069 | ||
c4241c7d PM |
3070 | void arm_cp_write_ignore(CPUARMState *env, const ARMCPRegInfo *ri, |
3071 | uint64_t value) | |
4b6a83fb PM |
3072 | { |
3073 | /* Helper coprocessor write function for write-ignore registers */ | |
4b6a83fb PM |
3074 | } |
3075 | ||
c4241c7d | 3076 | uint64_t arm_cp_read_zero(CPUARMState *env, const ARMCPRegInfo *ri) |
4b6a83fb PM |
3077 | { |
3078 | /* Helper coprocessor write function for read-as-zero registers */ | |
4b6a83fb PM |
3079 | return 0; |
3080 | } | |
3081 | ||
f5a0a5a5 PM |
3082 | void arm_cp_reset_ignore(CPUARMState *env, const ARMCPRegInfo *opaque) |
3083 | { | |
3084 | /* Helper coprocessor reset function for do-nothing-on-reset registers */ | |
3085 | } | |
3086 | ||
0ecb72a5 | 3087 | static int bad_mode_switch(CPUARMState *env, int mode) |
37064a8b PM |
3088 | { |
3089 | /* Return true if it is not valid for us to switch to | |
3090 | * this CPU mode (ie all the UNPREDICTABLE cases in | |
3091 | * the ARM ARM CPSRWriteByInstr pseudocode). | |
3092 | */ | |
3093 | switch (mode) { | |
3094 | case ARM_CPU_MODE_USR: | |
3095 | case ARM_CPU_MODE_SYS: | |
3096 | case ARM_CPU_MODE_SVC: | |
3097 | case ARM_CPU_MODE_ABT: | |
3098 | case ARM_CPU_MODE_UND: | |
3099 | case ARM_CPU_MODE_IRQ: | |
3100 | case ARM_CPU_MODE_FIQ: | |
3101 | return 0; | |
3102 | default: | |
3103 | return 1; | |
3104 | } | |
3105 | } | |
3106 | ||
2f4a40e5 AZ |
3107 | uint32_t cpsr_read(CPUARMState *env) |
3108 | { | |
3109 | int ZF; | |
6fbe23d5 PB |
3110 | ZF = (env->ZF == 0); |
3111 | return env->uncached_cpsr | (env->NF & 0x80000000) | (ZF << 30) | | |
2f4a40e5 AZ |
3112 | (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27) |
3113 | | (env->thumb << 5) | ((env->condexec_bits & 3) << 25) | |
3114 | | ((env->condexec_bits & 0xfc) << 8) | |
af519934 | 3115 | | (env->GE << 16) | (env->daif & CPSR_AIF); |
2f4a40e5 AZ |
3116 | } |
3117 | ||
3118 | void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask) | |
3119 | { | |
2f4a40e5 | 3120 | if (mask & CPSR_NZCV) { |
6fbe23d5 PB |
3121 | env->ZF = (~val) & CPSR_Z; |
3122 | env->NF = val; | |
2f4a40e5 AZ |
3123 | env->CF = (val >> 29) & 1; |
3124 | env->VF = (val << 3) & 0x80000000; | |
3125 | } | |
3126 | if (mask & CPSR_Q) | |
3127 | env->QF = ((val & CPSR_Q) != 0); | |
3128 | if (mask & CPSR_T) | |
3129 | env->thumb = ((val & CPSR_T) != 0); | |
3130 | if (mask & CPSR_IT_0_1) { | |
3131 | env->condexec_bits &= ~3; | |
3132 | env->condexec_bits |= (val >> 25) & 3; | |
3133 | } | |
3134 | if (mask & CPSR_IT_2_7) { | |
3135 | env->condexec_bits &= 3; | |
3136 | env->condexec_bits |= (val >> 8) & 0xfc; | |
3137 | } | |
3138 | if (mask & CPSR_GE) { | |
3139 | env->GE = (val >> 16) & 0xf; | |
3140 | } | |
3141 | ||
4cc35614 PM |
3142 | env->daif &= ~(CPSR_AIF & mask); |
3143 | env->daif |= val & CPSR_AIF & mask; | |
3144 | ||
2f4a40e5 | 3145 | if ((env->uncached_cpsr ^ val) & mask & CPSR_M) { |
37064a8b PM |
3146 | if (bad_mode_switch(env, val & CPSR_M)) { |
3147 | /* Attempt to switch to an invalid mode: this is UNPREDICTABLE. | |
3148 | * We choose to ignore the attempt and leave the CPSR M field | |
3149 | * untouched. | |
3150 | */ | |
3151 | mask &= ~CPSR_M; | |
3152 | } else { | |
3153 | switch_mode(env, val & CPSR_M); | |
3154 | } | |
2f4a40e5 AZ |
3155 | } |
3156 | mask &= ~CACHED_CPSR_BITS; | |
3157 | env->uncached_cpsr = (env->uncached_cpsr & ~mask) | (val & mask); | |
3158 | } | |
3159 | ||
b26eefb6 PB |
3160 | /* Sign/zero extend */ |
3161 | uint32_t HELPER(sxtb16)(uint32_t x) | |
3162 | { | |
3163 | uint32_t res; | |
3164 | res = (uint16_t)(int8_t)x; | |
3165 | res |= (uint32_t)(int8_t)(x >> 16) << 16; | |
3166 | return res; | |
3167 | } | |
3168 | ||
3169 | uint32_t HELPER(uxtb16)(uint32_t x) | |
3170 | { | |
3171 | uint32_t res; | |
3172 | res = (uint16_t)(uint8_t)x; | |
3173 | res |= (uint32_t)(uint8_t)(x >> 16) << 16; | |
3174 | return res; | |
3175 | } | |
3176 | ||
f51bbbfe PB |
3177 | uint32_t HELPER(clz)(uint32_t x) |
3178 | { | |
7bbcb0af | 3179 | return clz32(x); |
f51bbbfe PB |
3180 | } |
3181 | ||
3670669c PB |
3182 | int32_t HELPER(sdiv)(int32_t num, int32_t den) |
3183 | { | |
3184 | if (den == 0) | |
3185 | return 0; | |
686eeb93 AJ |
3186 | if (num == INT_MIN && den == -1) |
3187 | return INT_MIN; | |
3670669c PB |
3188 | return num / den; |
3189 | } | |
3190 | ||
3191 | uint32_t HELPER(udiv)(uint32_t num, uint32_t den) | |
3192 | { | |
3193 | if (den == 0) | |
3194 | return 0; | |
3195 | return num / den; | |
3196 | } | |
3197 | ||
3198 | uint32_t HELPER(rbit)(uint32_t x) | |
3199 | { | |
3200 | x = ((x & 0xff000000) >> 24) | |
3201 | | ((x & 0x00ff0000) >> 8) | |
3202 | | ((x & 0x0000ff00) << 8) | |
3203 | | ((x & 0x000000ff) << 24); | |
3204 | x = ((x & 0xf0f0f0f0) >> 4) | |
3205 | | ((x & 0x0f0f0f0f) << 4); | |
3206 | x = ((x & 0x88888888) >> 3) | |
3207 | | ((x & 0x44444444) >> 1) | |
3208 | | ((x & 0x22222222) << 1) | |
3209 | | ((x & 0x11111111) << 3); | |
3210 | return x; | |
3211 | } | |
3212 | ||
5fafdf24 | 3213 | #if defined(CONFIG_USER_ONLY) |
b5ff1b31 | 3214 | |
97a8ea5a | 3215 | void arm_cpu_do_interrupt(CPUState *cs) |
b5ff1b31 | 3216 | { |
27103424 | 3217 | cs->exception_index = -1; |
b5ff1b31 FB |
3218 | } |
3219 | ||
7510454e AF |
3220 | int arm_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw, |
3221 | int mmu_idx) | |
b5ff1b31 | 3222 | { |
7510454e AF |
3223 | ARMCPU *cpu = ARM_CPU(cs); |
3224 | CPUARMState *env = &cpu->env; | |
3225 | ||
abf1172f | 3226 | env->exception.vaddress = address; |
b5ff1b31 | 3227 | if (rw == 2) { |
27103424 | 3228 | cs->exception_index = EXCP_PREFETCH_ABORT; |
b5ff1b31 | 3229 | } else { |
27103424 | 3230 | cs->exception_index = EXCP_DATA_ABORT; |
b5ff1b31 FB |
3231 | } |
3232 | return 1; | |
3233 | } | |
3234 | ||
9ee6e8bb | 3235 | /* These should probably raise undefined insn exceptions. */ |
0ecb72a5 | 3236 | void HELPER(v7m_msr)(CPUARMState *env, uint32_t reg, uint32_t val) |
9ee6e8bb | 3237 | { |
a47dddd7 AF |
3238 | ARMCPU *cpu = arm_env_get_cpu(env); |
3239 | ||
3240 | cpu_abort(CPU(cpu), "v7m_msr %d\n", reg); | |
9ee6e8bb PB |
3241 | } |
3242 | ||
0ecb72a5 | 3243 | uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg) |
9ee6e8bb | 3244 | { |
a47dddd7 AF |
3245 | ARMCPU *cpu = arm_env_get_cpu(env); |
3246 | ||
3247 | cpu_abort(CPU(cpu), "v7m_mrs %d\n", reg); | |
9ee6e8bb PB |
3248 | return 0; |
3249 | } | |
3250 | ||
0ecb72a5 | 3251 | void switch_mode(CPUARMState *env, int mode) |
b5ff1b31 | 3252 | { |
a47dddd7 AF |
3253 | ARMCPU *cpu = arm_env_get_cpu(env); |
3254 | ||
3255 | if (mode != ARM_CPU_MODE_USR) { | |
3256 | cpu_abort(CPU(cpu), "Tried to switch out of user mode\n"); | |
3257 | } | |
b5ff1b31 FB |
3258 | } |
3259 | ||
0ecb72a5 | 3260 | void HELPER(set_r13_banked)(CPUARMState *env, uint32_t mode, uint32_t val) |
9ee6e8bb | 3261 | { |
a47dddd7 AF |
3262 | ARMCPU *cpu = arm_env_get_cpu(env); |
3263 | ||
3264 | cpu_abort(CPU(cpu), "banked r13 write\n"); | |
9ee6e8bb PB |
3265 | } |
3266 | ||
0ecb72a5 | 3267 | uint32_t HELPER(get_r13_banked)(CPUARMState *env, uint32_t mode) |
9ee6e8bb | 3268 | { |
a47dddd7 AF |
3269 | ARMCPU *cpu = arm_env_get_cpu(env); |
3270 | ||
3271 | cpu_abort(CPU(cpu), "banked r13 read\n"); | |
9ee6e8bb PB |
3272 | return 0; |
3273 | } | |
3274 | ||
b5ff1b31 FB |
3275 | #else |
3276 | ||
3277 | /* Map CPU modes onto saved register banks. */ | |
494b00c7 | 3278 | int bank_number(int mode) |
b5ff1b31 FB |
3279 | { |
3280 | switch (mode) { | |
3281 | case ARM_CPU_MODE_USR: | |
3282 | case ARM_CPU_MODE_SYS: | |
3283 | return 0; | |
3284 | case ARM_CPU_MODE_SVC: | |
3285 | return 1; | |
3286 | case ARM_CPU_MODE_ABT: | |
3287 | return 2; | |
3288 | case ARM_CPU_MODE_UND: | |
3289 | return 3; | |
3290 | case ARM_CPU_MODE_IRQ: | |
3291 | return 4; | |
3292 | case ARM_CPU_MODE_FIQ: | |
3293 | return 5; | |
28c9457d EI |
3294 | case ARM_CPU_MODE_HYP: |
3295 | return 6; | |
3296 | case ARM_CPU_MODE_MON: | |
3297 | return 7; | |
b5ff1b31 | 3298 | } |
f5206413 | 3299 | hw_error("bank number requested for bad CPSR mode value 0x%x\n", mode); |
b5ff1b31 FB |
3300 | } |
3301 | ||
0ecb72a5 | 3302 | void switch_mode(CPUARMState *env, int mode) |
b5ff1b31 FB |
3303 | { |
3304 | int old_mode; | |
3305 | int i; | |
3306 | ||
3307 | old_mode = env->uncached_cpsr & CPSR_M; | |
3308 | if (mode == old_mode) | |
3309 | return; | |
3310 | ||
3311 | if (old_mode == ARM_CPU_MODE_FIQ) { | |
3312 | memcpy (env->fiq_regs, env->regs + 8, 5 * sizeof(uint32_t)); | |
8637c67f | 3313 | memcpy (env->regs + 8, env->usr_regs, 5 * sizeof(uint32_t)); |
b5ff1b31 FB |
3314 | } else if (mode == ARM_CPU_MODE_FIQ) { |
3315 | memcpy (env->usr_regs, env->regs + 8, 5 * sizeof(uint32_t)); | |
8637c67f | 3316 | memcpy (env->regs + 8, env->fiq_regs, 5 * sizeof(uint32_t)); |
b5ff1b31 FB |
3317 | } |
3318 | ||
f5206413 | 3319 | i = bank_number(old_mode); |
b5ff1b31 FB |
3320 | env->banked_r13[i] = env->regs[13]; |
3321 | env->banked_r14[i] = env->regs[14]; | |
3322 | env->banked_spsr[i] = env->spsr; | |
3323 | ||
f5206413 | 3324 | i = bank_number(mode); |
b5ff1b31 FB |
3325 | env->regs[13] = env->banked_r13[i]; |
3326 | env->regs[14] = env->banked_r14[i]; | |
3327 | env->spsr = env->banked_spsr[i]; | |
3328 | } | |
3329 | ||
9ee6e8bb PB |
3330 | static void v7m_push(CPUARMState *env, uint32_t val) |
3331 | { | |
70d74660 AF |
3332 | CPUState *cs = CPU(arm_env_get_cpu(env)); |
3333 | ||
9ee6e8bb | 3334 | env->regs[13] -= 4; |
ab1da857 | 3335 | stl_phys(cs->as, env->regs[13], val); |
9ee6e8bb PB |
3336 | } |
3337 | ||
3338 | static uint32_t v7m_pop(CPUARMState *env) | |
3339 | { | |
70d74660 | 3340 | CPUState *cs = CPU(arm_env_get_cpu(env)); |
9ee6e8bb | 3341 | uint32_t val; |
70d74660 | 3342 | |
fdfba1a2 | 3343 | val = ldl_phys(cs->as, env->regs[13]); |
9ee6e8bb PB |
3344 | env->regs[13] += 4; |
3345 | return val; | |
3346 | } | |
3347 | ||
3348 | /* Switch to V7M main or process stack pointer. */ | |
3349 | static void switch_v7m_sp(CPUARMState *env, int process) | |
3350 | { | |
3351 | uint32_t tmp; | |
3352 | if (env->v7m.current_sp != process) { | |
3353 | tmp = env->v7m.other_sp; | |
3354 | env->v7m.other_sp = env->regs[13]; | |
3355 | env->regs[13] = tmp; | |
3356 | env->v7m.current_sp = process; | |
3357 | } | |
3358 | } | |
3359 | ||
3360 | static void do_v7m_exception_exit(CPUARMState *env) | |
3361 | { | |
3362 | uint32_t type; | |
3363 | uint32_t xpsr; | |
3364 | ||
3365 | type = env->regs[15]; | |
3366 | if (env->v7m.exception != 0) | |
983fe826 | 3367 | armv7m_nvic_complete_irq(env->nvic, env->v7m.exception); |
9ee6e8bb PB |
3368 | |
3369 | /* Switch to the target stack. */ | |
3370 | switch_v7m_sp(env, (type & 4) != 0); | |
3371 | /* Pop registers. */ | |
3372 | env->regs[0] = v7m_pop(env); | |
3373 | env->regs[1] = v7m_pop(env); | |
3374 | env->regs[2] = v7m_pop(env); | |
3375 | env->regs[3] = v7m_pop(env); | |
3376 | env->regs[12] = v7m_pop(env); | |
3377 | env->regs[14] = v7m_pop(env); | |
3378 | env->regs[15] = v7m_pop(env); | |
3379 | xpsr = v7m_pop(env); | |
3380 | xpsr_write(env, xpsr, 0xfffffdff); | |
3381 | /* Undo stack alignment. */ | |
3382 | if (xpsr & 0x200) | |
3383 | env->regs[13] |= 4; | |
3384 | /* ??? The exception return type specifies Thread/Handler mode. However | |
3385 | this is also implied by the xPSR value. Not sure what to do | |
3386 | if there is a mismatch. */ | |
3387 | /* ??? Likewise for mismatches between the CONTROL register and the stack | |
3388 | pointer. */ | |
3389 | } | |
3390 | ||
e6f010cc | 3391 | void arm_v7m_cpu_do_interrupt(CPUState *cs) |
9ee6e8bb | 3392 | { |
e6f010cc AF |
3393 | ARMCPU *cpu = ARM_CPU(cs); |
3394 | CPUARMState *env = &cpu->env; | |
9ee6e8bb PB |
3395 | uint32_t xpsr = xpsr_read(env); |
3396 | uint32_t lr; | |
3397 | uint32_t addr; | |
3398 | ||
27103424 | 3399 | arm_log_exception(cs->exception_index); |
3f1beaca | 3400 | |
9ee6e8bb PB |
3401 | lr = 0xfffffff1; |
3402 | if (env->v7m.current_sp) | |
3403 | lr |= 4; | |
3404 | if (env->v7m.exception == 0) | |
3405 | lr |= 8; | |
3406 | ||
3407 | /* For exceptions we just mark as pending on the NVIC, and let that | |
3408 | handle it. */ | |
3409 | /* TODO: Need to escalate if the current priority is higher than the | |
3410 | one we're raising. */ | |
27103424 | 3411 | switch (cs->exception_index) { |
9ee6e8bb | 3412 | case EXCP_UDEF: |
983fe826 | 3413 | armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE); |
9ee6e8bb PB |
3414 | return; |
3415 | case EXCP_SWI: | |
314e2296 | 3416 | /* The PC already points to the next instruction. */ |
983fe826 | 3417 | armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_SVC); |
9ee6e8bb PB |
3418 | return; |
3419 | case EXCP_PREFETCH_ABORT: | |
3420 | case EXCP_DATA_ABORT: | |
abf1172f PM |
3421 | /* TODO: if we implemented the MPU registers, this is where we |
3422 | * should set the MMFAR, etc from exception.fsr and exception.vaddress. | |
3423 | */ | |
983fe826 | 3424 | armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_MEM); |
9ee6e8bb PB |
3425 | return; |
3426 | case EXCP_BKPT: | |
2ad207d4 PB |
3427 | if (semihosting_enabled) { |
3428 | int nr; | |
d31dd73e | 3429 | nr = arm_lduw_code(env, env->regs[15], env->bswap_code) & 0xff; |
2ad207d4 PB |
3430 | if (nr == 0xab) { |
3431 | env->regs[15] += 2; | |
3432 | env->regs[0] = do_arm_semihosting(env); | |
3f1beaca | 3433 | qemu_log_mask(CPU_LOG_INT, "...handled as semihosting call\n"); |
2ad207d4 PB |
3434 | return; |
3435 | } | |
3436 | } | |
983fe826 | 3437 | armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_DEBUG); |
9ee6e8bb PB |
3438 | return; |
3439 | case EXCP_IRQ: | |
983fe826 | 3440 | env->v7m.exception = armv7m_nvic_acknowledge_irq(env->nvic); |
9ee6e8bb PB |
3441 | break; |
3442 | case EXCP_EXCEPTION_EXIT: | |
3443 | do_v7m_exception_exit(env); | |
3444 | return; | |
3445 | default: | |
a47dddd7 | 3446 | cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index); |
9ee6e8bb PB |
3447 | return; /* Never happens. Keep compiler happy. */ |
3448 | } | |
3449 | ||
3450 | /* Align stack pointer. */ | |
3451 | /* ??? Should only do this if Configuration Control Register | |
3452 | STACKALIGN bit is set. */ | |
3453 | if (env->regs[13] & 4) { | |
ab19b0ec | 3454 | env->regs[13] -= 4; |
9ee6e8bb PB |
3455 | xpsr |= 0x200; |
3456 | } | |
6c95676b | 3457 | /* Switch to the handler mode. */ |
9ee6e8bb PB |
3458 | v7m_push(env, xpsr); |
3459 | v7m_push(env, env->regs[15]); | |
3460 | v7m_push(env, env->regs[14]); | |
3461 | v7m_push(env, env->regs[12]); | |
3462 | v7m_push(env, env->regs[3]); | |
3463 | v7m_push(env, env->regs[2]); | |
3464 | v7m_push(env, env->regs[1]); | |
3465 | v7m_push(env, env->regs[0]); | |
3466 | switch_v7m_sp(env, 0); | |
c98d174c PM |
3467 | /* Clear IT bits */ |
3468 | env->condexec_bits = 0; | |
9ee6e8bb | 3469 | env->regs[14] = lr; |
fdfba1a2 | 3470 | addr = ldl_phys(cs->as, env->v7m.vecbase + env->v7m.exception * 4); |
9ee6e8bb PB |
3471 | env->regs[15] = addr & 0xfffffffe; |
3472 | env->thumb = addr & 1; | |
3473 | } | |
3474 | ||
b5ff1b31 | 3475 | /* Handle a CPU exception. */ |
97a8ea5a | 3476 | void arm_cpu_do_interrupt(CPUState *cs) |
b5ff1b31 | 3477 | { |
97a8ea5a AF |
3478 | ARMCPU *cpu = ARM_CPU(cs); |
3479 | CPUARMState *env = &cpu->env; | |
b5ff1b31 FB |
3480 | uint32_t addr; |
3481 | uint32_t mask; | |
3482 | int new_mode; | |
3483 | uint32_t offset; | |
3484 | ||
e6f010cc AF |
3485 | assert(!IS_M(env)); |
3486 | ||
27103424 | 3487 | arm_log_exception(cs->exception_index); |
3f1beaca | 3488 | |
b5ff1b31 | 3489 | /* TODO: Vectored interrupt controller. */ |
27103424 | 3490 | switch (cs->exception_index) { |
b5ff1b31 FB |
3491 | case EXCP_UDEF: |
3492 | new_mode = ARM_CPU_MODE_UND; | |
3493 | addr = 0x04; | |
3494 | mask = CPSR_I; | |
3495 | if (env->thumb) | |
3496 | offset = 2; | |
3497 | else | |
3498 | offset = 4; | |
3499 | break; | |
3500 | case EXCP_SWI: | |
8e71621f PB |
3501 | if (semihosting_enabled) { |
3502 | /* Check for semihosting interrupt. */ | |
3503 | if (env->thumb) { | |
d31dd73e BS |
3504 | mask = arm_lduw_code(env, env->regs[15] - 2, env->bswap_code) |
3505 | & 0xff; | |
8e71621f | 3506 | } else { |
d31dd73e | 3507 | mask = arm_ldl_code(env, env->regs[15] - 4, env->bswap_code) |
d8fd2954 | 3508 | & 0xffffff; |
8e71621f PB |
3509 | } |
3510 | /* Only intercept calls from privileged modes, to provide some | |
3511 | semblance of security. */ | |
3512 | if (((mask == 0x123456 && !env->thumb) | |
3513 | || (mask == 0xab && env->thumb)) | |
3514 | && (env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR) { | |
3515 | env->regs[0] = do_arm_semihosting(env); | |
3f1beaca | 3516 | qemu_log_mask(CPU_LOG_INT, "...handled as semihosting call\n"); |
8e71621f PB |
3517 | return; |
3518 | } | |
3519 | } | |
b5ff1b31 FB |
3520 | new_mode = ARM_CPU_MODE_SVC; |
3521 | addr = 0x08; | |
3522 | mask = CPSR_I; | |
601d70b9 | 3523 | /* The PC already points to the next instruction. */ |
b5ff1b31 FB |
3524 | offset = 0; |
3525 | break; | |
06c949e6 | 3526 | case EXCP_BKPT: |
9ee6e8bb | 3527 | /* See if this is a semihosting syscall. */ |
2ad207d4 | 3528 | if (env->thumb && semihosting_enabled) { |
d31dd73e | 3529 | mask = arm_lduw_code(env, env->regs[15], env->bswap_code) & 0xff; |
9ee6e8bb PB |
3530 | if (mask == 0xab |
3531 | && (env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR) { | |
3532 | env->regs[15] += 2; | |
3533 | env->regs[0] = do_arm_semihosting(env); | |
3f1beaca | 3534 | qemu_log_mask(CPU_LOG_INT, "...handled as semihosting call\n"); |
9ee6e8bb PB |
3535 | return; |
3536 | } | |
3537 | } | |
abf1172f | 3538 | env->exception.fsr = 2; |
9ee6e8bb PB |
3539 | /* Fall through to prefetch abort. */ |
3540 | case EXCP_PREFETCH_ABORT: | |
6cd8a264 | 3541 | env->cp15.ifsr_el2 = env->exception.fsr; |
2f0180c5 EI |
3542 | env->cp15.far_el[1] = deposit64(env->cp15.far_el[1], 32, 32, |
3543 | env->exception.vaddress); | |
3f1beaca | 3544 | qemu_log_mask(CPU_LOG_INT, "...with IFSR 0x%x IFAR 0x%x\n", |
6cd8a264 | 3545 | env->cp15.ifsr_el2, (uint32_t)env->exception.vaddress); |
b5ff1b31 FB |
3546 | new_mode = ARM_CPU_MODE_ABT; |
3547 | addr = 0x0c; | |
3548 | mask = CPSR_A | CPSR_I; | |
3549 | offset = 4; | |
3550 | break; | |
3551 | case EXCP_DATA_ABORT: | |
d81c519c | 3552 | env->cp15.esr_el[1] = env->exception.fsr; |
2f0180c5 EI |
3553 | env->cp15.far_el[1] = deposit64(env->cp15.far_el[1], 0, 32, |
3554 | env->exception.vaddress); | |
3f1beaca | 3555 | qemu_log_mask(CPU_LOG_INT, "...with DFSR 0x%x DFAR 0x%x\n", |
d81c519c | 3556 | (uint32_t)env->cp15.esr_el[1], |
6cd8a264 | 3557 | (uint32_t)env->exception.vaddress); |
b5ff1b31 FB |
3558 | new_mode = ARM_CPU_MODE_ABT; |
3559 | addr = 0x10; | |
3560 | mask = CPSR_A | CPSR_I; | |
3561 | offset = 8; | |
3562 | break; | |
3563 | case EXCP_IRQ: | |
3564 | new_mode = ARM_CPU_MODE_IRQ; | |
3565 | addr = 0x18; | |
3566 | /* Disable IRQ and imprecise data aborts. */ | |
3567 | mask = CPSR_A | CPSR_I; | |
3568 | offset = 4; | |
3569 | break; | |
3570 | case EXCP_FIQ: | |
3571 | new_mode = ARM_CPU_MODE_FIQ; | |
3572 | addr = 0x1c; | |
3573 | /* Disable FIQ, IRQ and imprecise data aborts. */ | |
3574 | mask = CPSR_A | CPSR_I | CPSR_F; | |
3575 | offset = 4; | |
3576 | break; | |
3577 | default: | |
a47dddd7 | 3578 | cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index); |
b5ff1b31 FB |
3579 | return; /* Never happens. Keep compiler happy. */ |
3580 | } | |
3581 | /* High vectors. */ | |
76e3e1bc | 3582 | if (env->cp15.c1_sys & SCTLR_V) { |
8641136c | 3583 | /* when enabled, base address cannot be remapped. */ |
b5ff1b31 | 3584 | addr += 0xffff0000; |
8641136c NR |
3585 | } else { |
3586 | /* ARM v7 architectures provide a vector base address register to remap | |
3587 | * the interrupt vector table. | |
3588 | * This register is only followed in non-monitor mode, and has a secure | |
3589 | * and un-secure copy. Since the cpu is always in a un-secure operation | |
3590 | * and is never in monitor mode this feature is always active. | |
3591 | * Note: only bits 31:5 are valid. | |
3592 | */ | |
68fdb6c5 | 3593 | addr += env->cp15.vbar_el[1]; |
b5ff1b31 FB |
3594 | } |
3595 | switch_mode (env, new_mode); | |
662cefb7 PM |
3596 | /* For exceptions taken to AArch32 we must clear the SS bit in both |
3597 | * PSTATE and in the old-state value we save to SPSR_<mode>, so zero it now. | |
3598 | */ | |
3599 | env->uncached_cpsr &= ~PSTATE_SS; | |
b5ff1b31 | 3600 | env->spsr = cpsr_read(env); |
9ee6e8bb PB |
3601 | /* Clear IT bits. */ |
3602 | env->condexec_bits = 0; | |
30a8cac1 | 3603 | /* Switch to the new mode, and to the correct instruction set. */ |
6d7e6326 | 3604 | env->uncached_cpsr = (env->uncached_cpsr & ~CPSR_M) | new_mode; |
4cc35614 | 3605 | env->daif |= mask; |
be5e7a76 DES |
3606 | /* this is a lie, as the was no c1_sys on V4T/V5, but who cares |
3607 | * and we should just guard the thumb mode on V4 */ | |
3608 | if (arm_feature(env, ARM_FEATURE_V4T)) { | |
76e3e1bc | 3609 | env->thumb = (env->cp15.c1_sys & SCTLR_TE) != 0; |
be5e7a76 | 3610 | } |
b5ff1b31 FB |
3611 | env->regs[14] = env->regs[15] + offset; |
3612 | env->regs[15] = addr; | |
259186a7 | 3613 | cs->interrupt_request |= CPU_INTERRUPT_EXITTB; |
b5ff1b31 FB |
3614 | } |
3615 | ||
3616 | /* Check section/page access permissions. | |
3617 | Returns the page protection flags, or zero if the access is not | |
3618 | permitted. */ | |
0ecb72a5 | 3619 | static inline int check_ap(CPUARMState *env, int ap, int domain_prot, |
dd4ebc2e | 3620 | int access_type, int is_user) |
b5ff1b31 | 3621 | { |
9ee6e8bb PB |
3622 | int prot_ro; |
3623 | ||
dd4ebc2e | 3624 | if (domain_prot == 3) { |
b5ff1b31 | 3625 | return PAGE_READ | PAGE_WRITE; |
dd4ebc2e | 3626 | } |
b5ff1b31 | 3627 | |
9ee6e8bb PB |
3628 | if (access_type == 1) |
3629 | prot_ro = 0; | |
3630 | else | |
3631 | prot_ro = PAGE_READ; | |
3632 | ||
b5ff1b31 FB |
3633 | switch (ap) { |
3634 | case 0: | |
99f678a6 PM |
3635 | if (arm_feature(env, ARM_FEATURE_V7)) { |
3636 | return 0; | |
3637 | } | |
78600320 | 3638 | if (access_type == 1) |
b5ff1b31 | 3639 | return 0; |
76e3e1bc PM |
3640 | switch (env->cp15.c1_sys & (SCTLR_S | SCTLR_R)) { |
3641 | case SCTLR_S: | |
b5ff1b31 | 3642 | return is_user ? 0 : PAGE_READ; |
76e3e1bc | 3643 | case SCTLR_R: |
b5ff1b31 FB |
3644 | return PAGE_READ; |
3645 | default: | |
3646 | return 0; | |
3647 | } | |
3648 | case 1: | |
3649 | return is_user ? 0 : PAGE_READ | PAGE_WRITE; | |
3650 | case 2: | |
3651 | if (is_user) | |
9ee6e8bb | 3652 | return prot_ro; |
b5ff1b31 FB |
3653 | else |
3654 | return PAGE_READ | PAGE_WRITE; | |
3655 | case 3: | |
3656 | return PAGE_READ | PAGE_WRITE; | |
d4934d18 | 3657 | case 4: /* Reserved. */ |
9ee6e8bb PB |
3658 | return 0; |
3659 | case 5: | |
3660 | return is_user ? 0 : prot_ro; | |
3661 | case 6: | |
3662 | return prot_ro; | |
d4934d18 | 3663 | case 7: |
0ab06d83 | 3664 | if (!arm_feature (env, ARM_FEATURE_V6K)) |
d4934d18 PB |
3665 | return 0; |
3666 | return prot_ro; | |
b5ff1b31 FB |
3667 | default: |
3668 | abort(); | |
3669 | } | |
3670 | } | |
3671 | ||
e389be16 FA |
3672 | static bool get_level1_table_address(CPUARMState *env, uint32_t *table, |
3673 | uint32_t address) | |
b2fa1797 | 3674 | { |
e389be16 FA |
3675 | if (address & env->cp15.c2_mask) { |
3676 | if ((env->cp15.c2_control & TTBCR_PD1)) { | |
3677 | /* Translation table walk disabled for TTBR1 */ | |
3678 | return false; | |
3679 | } | |
3680 | *table = env->cp15.ttbr1_el1 & 0xffffc000; | |
3681 | } else { | |
3682 | if ((env->cp15.c2_control & TTBCR_PD0)) { | |
3683 | /* Translation table walk disabled for TTBR0 */ | |
3684 | return false; | |
3685 | } | |
3686 | *table = env->cp15.ttbr0_el1 & env->cp15.c2_base_mask; | |
3687 | } | |
3688 | *table |= (address >> 18) & 0x3ffc; | |
3689 | return true; | |
b2fa1797 PB |
3690 | } |
3691 | ||
0ecb72a5 | 3692 | static int get_phys_addr_v5(CPUARMState *env, uint32_t address, int access_type, |
a8170e5e | 3693 | int is_user, hwaddr *phys_ptr, |
77a71dd1 | 3694 | int *prot, target_ulong *page_size) |
b5ff1b31 | 3695 | { |
70d74660 | 3696 | CPUState *cs = CPU(arm_env_get_cpu(env)); |
b5ff1b31 FB |
3697 | int code; |
3698 | uint32_t table; | |
3699 | uint32_t desc; | |
3700 | int type; | |
3701 | int ap; | |
e389be16 | 3702 | int domain = 0; |
dd4ebc2e | 3703 | int domain_prot; |
a8170e5e | 3704 | hwaddr phys_addr; |
b5ff1b31 | 3705 | |
9ee6e8bb PB |
3706 | /* Pagetable walk. */ |
3707 | /* Lookup l1 descriptor. */ | |
e389be16 FA |
3708 | if (!get_level1_table_address(env, &table, address)) { |
3709 | /* Section translation fault if page walk is disabled by PD0 or PD1 */ | |
3710 | code = 5; | |
3711 | goto do_fault; | |
3712 | } | |
fdfba1a2 | 3713 | desc = ldl_phys(cs->as, table); |
9ee6e8bb | 3714 | type = (desc & 3); |
dd4ebc2e JCD |
3715 | domain = (desc >> 5) & 0x0f; |
3716 | domain_prot = (env->cp15.c3 >> (domain * 2)) & 3; | |
9ee6e8bb | 3717 | if (type == 0) { |
601d70b9 | 3718 | /* Section translation fault. */ |
9ee6e8bb PB |
3719 | code = 5; |
3720 | goto do_fault; | |
3721 | } | |
dd4ebc2e | 3722 | if (domain_prot == 0 || domain_prot == 2) { |
9ee6e8bb PB |
3723 | if (type == 2) |
3724 | code = 9; /* Section domain fault. */ | |
3725 | else | |
3726 | code = 11; /* Page domain fault. */ | |
3727 | goto do_fault; | |
3728 | } | |
3729 | if (type == 2) { | |
3730 | /* 1Mb section. */ | |
3731 | phys_addr = (desc & 0xfff00000) | (address & 0x000fffff); | |
3732 | ap = (desc >> 10) & 3; | |
3733 | code = 13; | |
d4c430a8 | 3734 | *page_size = 1024 * 1024; |
9ee6e8bb PB |
3735 | } else { |
3736 | /* Lookup l2 entry. */ | |
3737 | if (type == 1) { | |
3738 | /* Coarse pagetable. */ | |
3739 | table = (desc & 0xfffffc00) | ((address >> 10) & 0x3fc); | |
3740 | } else { | |
3741 | /* Fine pagetable. */ | |
3742 | table = (desc & 0xfffff000) | ((address >> 8) & 0xffc); | |
3743 | } | |
fdfba1a2 | 3744 | desc = ldl_phys(cs->as, table); |
9ee6e8bb PB |
3745 | switch (desc & 3) { |
3746 | case 0: /* Page translation fault. */ | |
3747 | code = 7; | |
3748 | goto do_fault; | |
3749 | case 1: /* 64k page. */ | |
3750 | phys_addr = (desc & 0xffff0000) | (address & 0xffff); | |
3751 | ap = (desc >> (4 + ((address >> 13) & 6))) & 3; | |
d4c430a8 | 3752 | *page_size = 0x10000; |
ce819861 | 3753 | break; |
9ee6e8bb PB |
3754 | case 2: /* 4k page. */ |
3755 | phys_addr = (desc & 0xfffff000) | (address & 0xfff); | |
c10f7fc3 | 3756 | ap = (desc >> (4 + ((address >> 9) & 6))) & 3; |
d4c430a8 | 3757 | *page_size = 0x1000; |
ce819861 | 3758 | break; |
9ee6e8bb PB |
3759 | case 3: /* 1k page. */ |
3760 | if (type == 1) { | |
3761 | if (arm_feature(env, ARM_FEATURE_XSCALE)) { | |
3762 | phys_addr = (desc & 0xfffff000) | (address & 0xfff); | |
3763 | } else { | |
3764 | /* Page translation fault. */ | |
3765 | code = 7; | |
3766 | goto do_fault; | |
3767 | } | |
3768 | } else { | |
3769 | phys_addr = (desc & 0xfffffc00) | (address & 0x3ff); | |
3770 | } | |
3771 | ap = (desc >> 4) & 3; | |
d4c430a8 | 3772 | *page_size = 0x400; |
ce819861 PB |
3773 | break; |
3774 | default: | |
9ee6e8bb PB |
3775 | /* Never happens, but compiler isn't smart enough to tell. */ |
3776 | abort(); | |
ce819861 | 3777 | } |
9ee6e8bb PB |
3778 | code = 15; |
3779 | } | |
dd4ebc2e | 3780 | *prot = check_ap(env, ap, domain_prot, access_type, is_user); |
9ee6e8bb PB |
3781 | if (!*prot) { |
3782 | /* Access permission fault. */ | |
3783 | goto do_fault; | |
3784 | } | |
3ad493fc | 3785 | *prot |= PAGE_EXEC; |
9ee6e8bb PB |
3786 | *phys_ptr = phys_addr; |
3787 | return 0; | |
3788 | do_fault: | |
3789 | return code | (domain << 4); | |
3790 | } | |
3791 | ||
0ecb72a5 | 3792 | static int get_phys_addr_v6(CPUARMState *env, uint32_t address, int access_type, |
a8170e5e | 3793 | int is_user, hwaddr *phys_ptr, |
77a71dd1 | 3794 | int *prot, target_ulong *page_size) |
9ee6e8bb | 3795 | { |
70d74660 | 3796 | CPUState *cs = CPU(arm_env_get_cpu(env)); |
9ee6e8bb PB |
3797 | int code; |
3798 | uint32_t table; | |
3799 | uint32_t desc; | |
3800 | uint32_t xn; | |
de9b05b8 | 3801 | uint32_t pxn = 0; |
9ee6e8bb PB |
3802 | int type; |
3803 | int ap; | |
de9b05b8 | 3804 | int domain = 0; |
dd4ebc2e | 3805 | int domain_prot; |
a8170e5e | 3806 | hwaddr phys_addr; |
9ee6e8bb PB |
3807 | |
3808 | /* Pagetable walk. */ | |
3809 | /* Lookup l1 descriptor. */ | |
e389be16 FA |
3810 | if (!get_level1_table_address(env, &table, address)) { |
3811 | /* Section translation fault if page walk is disabled by PD0 or PD1 */ | |
3812 | code = 5; | |
3813 | goto do_fault; | |
3814 | } | |
fdfba1a2 | 3815 | desc = ldl_phys(cs->as, table); |
9ee6e8bb | 3816 | type = (desc & 3); |
de9b05b8 PM |
3817 | if (type == 0 || (type == 3 && !arm_feature(env, ARM_FEATURE_PXN))) { |
3818 | /* Section translation fault, or attempt to use the encoding | |
3819 | * which is Reserved on implementations without PXN. | |
3820 | */ | |
9ee6e8bb | 3821 | code = 5; |
9ee6e8bb | 3822 | goto do_fault; |
de9b05b8 PM |
3823 | } |
3824 | if ((type == 1) || !(desc & (1 << 18))) { | |
3825 | /* Page or Section. */ | |
dd4ebc2e | 3826 | domain = (desc >> 5) & 0x0f; |
9ee6e8bb | 3827 | } |
dd4ebc2e JCD |
3828 | domain_prot = (env->cp15.c3 >> (domain * 2)) & 3; |
3829 | if (domain_prot == 0 || domain_prot == 2) { | |
de9b05b8 | 3830 | if (type != 1) { |
9ee6e8bb | 3831 | code = 9; /* Section domain fault. */ |
de9b05b8 | 3832 | } else { |
9ee6e8bb | 3833 | code = 11; /* Page domain fault. */ |
de9b05b8 | 3834 | } |
9ee6e8bb PB |
3835 | goto do_fault; |
3836 | } | |
de9b05b8 | 3837 | if (type != 1) { |
9ee6e8bb PB |
3838 | if (desc & (1 << 18)) { |
3839 | /* Supersection. */ | |
3840 | phys_addr = (desc & 0xff000000) | (address & 0x00ffffff); | |
d4c430a8 | 3841 | *page_size = 0x1000000; |
b5ff1b31 | 3842 | } else { |
9ee6e8bb PB |
3843 | /* Section. */ |
3844 | phys_addr = (desc & 0xfff00000) | (address & 0x000fffff); | |
d4c430a8 | 3845 | *page_size = 0x100000; |
b5ff1b31 | 3846 | } |
9ee6e8bb PB |
3847 | ap = ((desc >> 10) & 3) | ((desc >> 13) & 4); |
3848 | xn = desc & (1 << 4); | |
de9b05b8 | 3849 | pxn = desc & 1; |
9ee6e8bb PB |
3850 | code = 13; |
3851 | } else { | |
de9b05b8 PM |
3852 | if (arm_feature(env, ARM_FEATURE_PXN)) { |
3853 | pxn = (desc >> 2) & 1; | |
3854 | } | |
9ee6e8bb PB |
3855 | /* Lookup l2 entry. */ |
3856 | table = (desc & 0xfffffc00) | ((address >> 10) & 0x3fc); | |
fdfba1a2 | 3857 | desc = ldl_phys(cs->as, table); |
9ee6e8bb PB |
3858 | ap = ((desc >> 4) & 3) | ((desc >> 7) & 4); |
3859 | switch (desc & 3) { | |
3860 | case 0: /* Page translation fault. */ | |
3861 | code = 7; | |
b5ff1b31 | 3862 | goto do_fault; |
9ee6e8bb PB |
3863 | case 1: /* 64k page. */ |
3864 | phys_addr = (desc & 0xffff0000) | (address & 0xffff); | |
3865 | xn = desc & (1 << 15); | |
d4c430a8 | 3866 | *page_size = 0x10000; |
9ee6e8bb PB |
3867 | break; |
3868 | case 2: case 3: /* 4k page. */ | |
3869 | phys_addr = (desc & 0xfffff000) | (address & 0xfff); | |
3870 | xn = desc & 1; | |
d4c430a8 | 3871 | *page_size = 0x1000; |
9ee6e8bb PB |
3872 | break; |
3873 | default: | |
3874 | /* Never happens, but compiler isn't smart enough to tell. */ | |
3875 | abort(); | |
b5ff1b31 | 3876 | } |
9ee6e8bb PB |
3877 | code = 15; |
3878 | } | |
dd4ebc2e | 3879 | if (domain_prot == 3) { |
c0034328 JR |
3880 | *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; |
3881 | } else { | |
de9b05b8 PM |
3882 | if (pxn && !is_user) { |
3883 | xn = 1; | |
3884 | } | |
c0034328 JR |
3885 | if (xn && access_type == 2) |
3886 | goto do_fault; | |
9ee6e8bb | 3887 | |
c0034328 | 3888 | /* The simplified model uses AP[0] as an access control bit. */ |
76e3e1bc | 3889 | if ((env->cp15.c1_sys & SCTLR_AFE) && (ap & 1) == 0) { |
c0034328 JR |
3890 | /* Access flag fault. */ |
3891 | code = (code == 15) ? 6 : 3; | |
3892 | goto do_fault; | |
3893 | } | |
dd4ebc2e | 3894 | *prot = check_ap(env, ap, domain_prot, access_type, is_user); |
c0034328 JR |
3895 | if (!*prot) { |
3896 | /* Access permission fault. */ | |
3897 | goto do_fault; | |
3898 | } | |
3899 | if (!xn) { | |
3900 | *prot |= PAGE_EXEC; | |
3901 | } | |
3ad493fc | 3902 | } |
9ee6e8bb | 3903 | *phys_ptr = phys_addr; |
b5ff1b31 FB |
3904 | return 0; |
3905 | do_fault: | |
3906 | return code | (domain << 4); | |
3907 | } | |
3908 | ||
3dde962f PM |
3909 | /* Fault type for long-descriptor MMU fault reporting; this corresponds |
3910 | * to bits [5..2] in the STATUS field in long-format DFSR/IFSR. | |
3911 | */ | |
3912 | typedef enum { | |
3913 | translation_fault = 1, | |
3914 | access_fault = 2, | |
3915 | permission_fault = 3, | |
3916 | } MMUFaultType; | |
3917 | ||
2c8dd318 | 3918 | static int get_phys_addr_lpae(CPUARMState *env, target_ulong address, |
3dde962f | 3919 | int access_type, int is_user, |
a8170e5e | 3920 | hwaddr *phys_ptr, int *prot, |
3dde962f PM |
3921 | target_ulong *page_size_ptr) |
3922 | { | |
70d74660 | 3923 | CPUState *cs = CPU(arm_env_get_cpu(env)); |
3dde962f PM |
3924 | /* Read an LPAE long-descriptor translation table. */ |
3925 | MMUFaultType fault_type = translation_fault; | |
3926 | uint32_t level = 1; | |
3927 | uint32_t epd; | |
2c8dd318 RH |
3928 | int32_t tsz; |
3929 | uint32_t tg; | |
3dde962f PM |
3930 | uint64_t ttbr; |
3931 | int ttbr_select; | |
2c8dd318 | 3932 | hwaddr descaddr, descmask; |
3dde962f PM |
3933 | uint32_t tableattrs; |
3934 | target_ulong page_size; | |
3935 | uint32_t attrs; | |
2c8dd318 RH |
3936 | int32_t granule_sz = 9; |
3937 | int32_t va_size = 32; | |
3938 | int32_t tbi = 0; | |
3939 | ||
3940 | if (arm_el_is_aa64(env, 1)) { | |
3941 | va_size = 64; | |
3942 | if (extract64(address, 55, 1)) | |
3943 | tbi = extract64(env->cp15.c2_control, 38, 1); | |
3944 | else | |
3945 | tbi = extract64(env->cp15.c2_control, 37, 1); | |
3946 | tbi *= 8; | |
3947 | } | |
3dde962f PM |
3948 | |
3949 | /* Determine whether this address is in the region controlled by | |
3950 | * TTBR0 or TTBR1 (or if it is in neither region and should fault). | |
3951 | * This is a Non-secure PL0/1 stage 1 translation, so controlled by | |
3952 | * TTBCR/TTBR0/TTBR1 in accordance with ARM ARM DDI0406C table B-32: | |
3953 | */ | |
2c8dd318 RH |
3954 | uint32_t t0sz = extract32(env->cp15.c2_control, 0, 6); |
3955 | if (arm_el_is_aa64(env, 1)) { | |
3956 | t0sz = MIN(t0sz, 39); | |
3957 | t0sz = MAX(t0sz, 16); | |
3958 | } | |
3959 | uint32_t t1sz = extract32(env->cp15.c2_control, 16, 6); | |
3960 | if (arm_el_is_aa64(env, 1)) { | |
3961 | t1sz = MIN(t1sz, 39); | |
3962 | t1sz = MAX(t1sz, 16); | |
3963 | } | |
3964 | if (t0sz && !extract64(address, va_size - t0sz, t0sz - tbi)) { | |
3dde962f PM |
3965 | /* there is a ttbr0 region and we are in it (high bits all zero) */ |
3966 | ttbr_select = 0; | |
2c8dd318 | 3967 | } else if (t1sz && !extract64(~address, va_size - t1sz, t1sz - tbi)) { |
3dde962f PM |
3968 | /* there is a ttbr1 region and we are in it (high bits all one) */ |
3969 | ttbr_select = 1; | |
3970 | } else if (!t0sz) { | |
3971 | /* ttbr0 region is "everything not in the ttbr1 region" */ | |
3972 | ttbr_select = 0; | |
3973 | } else if (!t1sz) { | |
3974 | /* ttbr1 region is "everything not in the ttbr0 region" */ | |
3975 | ttbr_select = 1; | |
3976 | } else { | |
3977 | /* in the gap between the two regions, this is a Translation fault */ | |
3978 | fault_type = translation_fault; | |
3979 | goto do_fault; | |
3980 | } | |
3981 | ||
3982 | /* Note that QEMU ignores shareability and cacheability attributes, | |
3983 | * so we don't need to do anything with the SH, ORGN, IRGN fields | |
3984 | * in the TTBCR. Similarly, TTBCR:A1 selects whether we get the | |
3985 | * ASID from TTBR0 or TTBR1, but QEMU's TLB doesn't currently | |
3986 | * implement any ASID-like capability so we can ignore it (instead | |
3987 | * we will always flush the TLB any time the ASID is changed). | |
3988 | */ | |
3989 | if (ttbr_select == 0) { | |
327ed10f | 3990 | ttbr = env->cp15.ttbr0_el1; |
3dde962f PM |
3991 | epd = extract32(env->cp15.c2_control, 7, 1); |
3992 | tsz = t0sz; | |
2c8dd318 RH |
3993 | |
3994 | tg = extract32(env->cp15.c2_control, 14, 2); | |
3995 | if (tg == 1) { /* 64KB pages */ | |
3996 | granule_sz = 13; | |
3997 | } | |
3998 | if (tg == 2) { /* 16KB pages */ | |
3999 | granule_sz = 11; | |
4000 | } | |
3dde962f | 4001 | } else { |
327ed10f | 4002 | ttbr = env->cp15.ttbr1_el1; |
3dde962f PM |
4003 | epd = extract32(env->cp15.c2_control, 23, 1); |
4004 | tsz = t1sz; | |
2c8dd318 RH |
4005 | |
4006 | tg = extract32(env->cp15.c2_control, 30, 2); | |
4007 | if (tg == 3) { /* 64KB pages */ | |
4008 | granule_sz = 13; | |
4009 | } | |
4010 | if (tg == 1) { /* 16KB pages */ | |
4011 | granule_sz = 11; | |
4012 | } | |
3dde962f PM |
4013 | } |
4014 | ||
4015 | if (epd) { | |
4016 | /* Translation table walk disabled => Translation fault on TLB miss */ | |
4017 | goto do_fault; | |
4018 | } | |
4019 | ||
2c8dd318 RH |
4020 | /* The starting level depends on the virtual address size which can be |
4021 | * up to 48-bits and the translation granule size. | |
3dde962f | 4022 | */ |
2c8dd318 RH |
4023 | if ((va_size - tsz) > (granule_sz * 4 + 3)) { |
4024 | level = 0; | |
4025 | } else if ((va_size - tsz) > (granule_sz * 3 + 3)) { | |
4026 | level = 1; | |
3dde962f | 4027 | } else { |
2c8dd318 | 4028 | level = 2; |
3dde962f PM |
4029 | } |
4030 | ||
4031 | /* Clear the vaddr bits which aren't part of the within-region address, | |
4032 | * so that we don't have to special case things when calculating the | |
4033 | * first descriptor address. | |
4034 | */ | |
2c8dd318 RH |
4035 | if (tsz) { |
4036 | address &= (1ULL << (va_size - tsz)) - 1; | |
4037 | } | |
4038 | ||
4039 | descmask = (1ULL << (granule_sz + 3)) - 1; | |
3dde962f PM |
4040 | |
4041 | /* Now we can extract the actual base address from the TTBR */ | |
2c8dd318 RH |
4042 | descaddr = extract64(ttbr, 0, 48); |
4043 | descaddr &= ~((1ULL << (va_size - tsz - (granule_sz * (4 - level)))) - 1); | |
3dde962f PM |
4044 | |
4045 | tableattrs = 0; | |
4046 | for (;;) { | |
4047 | uint64_t descriptor; | |
4048 | ||
2c8dd318 RH |
4049 | descaddr |= (address >> (granule_sz * (4 - level))) & descmask; |
4050 | descaddr &= ~7ULL; | |
2c17449b | 4051 | descriptor = ldq_phys(cs->as, descaddr); |
3dde962f PM |
4052 | if (!(descriptor & 1) || |
4053 | (!(descriptor & 2) && (level == 3))) { | |
4054 | /* Invalid, or the Reserved level 3 encoding */ | |
4055 | goto do_fault; | |
4056 | } | |
4057 | descaddr = descriptor & 0xfffffff000ULL; | |
4058 | ||
4059 | if ((descriptor & 2) && (level < 3)) { | |
4060 | /* Table entry. The top five bits are attributes which may | |
4061 | * propagate down through lower levels of the table (and | |
4062 | * which are all arranged so that 0 means "no effect", so | |
4063 | * we can gather them up by ORing in the bits at each level). | |
4064 | */ | |
4065 | tableattrs |= extract64(descriptor, 59, 5); | |
4066 | level++; | |
4067 | continue; | |
4068 | } | |
4069 | /* Block entry at level 1 or 2, or page entry at level 3. | |
4070 | * These are basically the same thing, although the number | |
4071 | * of bits we pull in from the vaddr varies. | |
4072 | */ | |
5661ae6b | 4073 | page_size = (1ULL << ((granule_sz * (4 - level)) + 3)); |
3dde962f PM |
4074 | descaddr |= (address & (page_size - 1)); |
4075 | /* Extract attributes from the descriptor and merge with table attrs */ | |
d615efac IC |
4076 | attrs = extract64(descriptor, 2, 10) |
4077 | | (extract64(descriptor, 52, 12) << 10); | |
3dde962f PM |
4078 | attrs |= extract32(tableattrs, 0, 2) << 11; /* XN, PXN */ |
4079 | attrs |= extract32(tableattrs, 3, 1) << 5; /* APTable[1] => AP[2] */ | |
4080 | /* The sense of AP[1] vs APTable[0] is reversed, as APTable[0] == 1 | |
4081 | * means "force PL1 access only", which means forcing AP[1] to 0. | |
4082 | */ | |
4083 | if (extract32(tableattrs, 2, 1)) { | |
4084 | attrs &= ~(1 << 4); | |
4085 | } | |
4086 | /* Since we're always in the Non-secure state, NSTable is ignored. */ | |
4087 | break; | |
4088 | } | |
4089 | /* Here descaddr is the final physical address, and attributes | |
4090 | * are all in attrs. | |
4091 | */ | |
4092 | fault_type = access_fault; | |
4093 | if ((attrs & (1 << 8)) == 0) { | |
4094 | /* Access flag */ | |
4095 | goto do_fault; | |
4096 | } | |
4097 | fault_type = permission_fault; | |
4098 | if (is_user && !(attrs & (1 << 4))) { | |
4099 | /* Unprivileged access not enabled */ | |
4100 | goto do_fault; | |
4101 | } | |
4102 | *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; | |
d615efac IC |
4103 | if ((arm_feature(env, ARM_FEATURE_V8) && is_user && (attrs & (1 << 12))) || |
4104 | (!arm_feature(env, ARM_FEATURE_V8) && (attrs & (1 << 12))) || | |
4105 | (!is_user && (attrs & (1 << 11)))) { | |
4106 | /* XN/UXN or PXN. Since we only implement EL0/EL1 we unconditionally | |
4107 | * treat XN/UXN as UXN for v8. | |
4108 | */ | |
3dde962f PM |
4109 | if (access_type == 2) { |
4110 | goto do_fault; | |
4111 | } | |
4112 | *prot &= ~PAGE_EXEC; | |
4113 | } | |
4114 | if (attrs & (1 << 5)) { | |
4115 | /* Write access forbidden */ | |
4116 | if (access_type == 1) { | |
4117 | goto do_fault; | |
4118 | } | |
4119 | *prot &= ~PAGE_WRITE; | |
4120 | } | |
4121 | ||
4122 | *phys_ptr = descaddr; | |
4123 | *page_size_ptr = page_size; | |
4124 | return 0; | |
4125 | ||
4126 | do_fault: | |
4127 | /* Long-descriptor format IFSR/DFSR value */ | |
4128 | return (1 << 9) | (fault_type << 2) | level; | |
4129 | } | |
4130 | ||
77a71dd1 PM |
4131 | static int get_phys_addr_mpu(CPUARMState *env, uint32_t address, |
4132 | int access_type, int is_user, | |
a8170e5e | 4133 | hwaddr *phys_ptr, int *prot) |
9ee6e8bb PB |
4134 | { |
4135 | int n; | |
4136 | uint32_t mask; | |
4137 | uint32_t base; | |
4138 | ||
4139 | *phys_ptr = address; | |
4140 | for (n = 7; n >= 0; n--) { | |
4141 | base = env->cp15.c6_region[n]; | |
4142 | if ((base & 1) == 0) | |
4143 | continue; | |
4144 | mask = 1 << ((base >> 1) & 0x1f); | |
4145 | /* Keep this shift separate from the above to avoid an | |
4146 | (undefined) << 32. */ | |
4147 | mask = (mask << 1) - 1; | |
4148 | if (((base ^ address) & ~mask) == 0) | |
4149 | break; | |
4150 | } | |
4151 | if (n < 0) | |
4152 | return 2; | |
4153 | ||
4154 | if (access_type == 2) { | |
7e09797c | 4155 | mask = env->cp15.pmsav5_insn_ap; |
9ee6e8bb | 4156 | } else { |
7e09797c | 4157 | mask = env->cp15.pmsav5_data_ap; |
9ee6e8bb PB |
4158 | } |
4159 | mask = (mask >> (n * 4)) & 0xf; | |
4160 | switch (mask) { | |
4161 | case 0: | |
4162 | return 1; | |
4163 | case 1: | |
4164 | if (is_user) | |
4165 | return 1; | |
4166 | *prot = PAGE_READ | PAGE_WRITE; | |
4167 | break; | |
4168 | case 2: | |
4169 | *prot = PAGE_READ; | |
4170 | if (!is_user) | |
4171 | *prot |= PAGE_WRITE; | |
4172 | break; | |
4173 | case 3: | |
4174 | *prot = PAGE_READ | PAGE_WRITE; | |
4175 | break; | |
4176 | case 5: | |
4177 | if (is_user) | |
4178 | return 1; | |
4179 | *prot = PAGE_READ; | |
4180 | break; | |
4181 | case 6: | |
4182 | *prot = PAGE_READ; | |
4183 | break; | |
4184 | default: | |
4185 | /* Bad permission. */ | |
4186 | return 1; | |
4187 | } | |
3ad493fc | 4188 | *prot |= PAGE_EXEC; |
9ee6e8bb PB |
4189 | return 0; |
4190 | } | |
4191 | ||
702a9357 PM |
4192 | /* get_phys_addr - get the physical address for this virtual address |
4193 | * | |
4194 | * Find the physical address corresponding to the given virtual address, | |
4195 | * by doing a translation table walk on MMU based systems or using the | |
4196 | * MPU state on MPU based systems. | |
4197 | * | |
4198 | * Returns 0 if the translation was successful. Otherwise, phys_ptr, | |
4199 | * prot and page_size are not filled in, and the return value provides | |
4200 | * information on why the translation aborted, in the format of a | |
4201 | * DFSR/IFSR fault register, with the following caveats: | |
4202 | * * we honour the short vs long DFSR format differences. | |
4203 | * * the WnR bit is never set (the caller must do this). | |
4204 | * * for MPU based systems we don't bother to return a full FSR format | |
4205 | * value. | |
4206 | * | |
4207 | * @env: CPUARMState | |
4208 | * @address: virtual address to get physical address for | |
4209 | * @access_type: 0 for read, 1 for write, 2 for execute | |
4210 | * @is_user: 0 for privileged access, 1 for user | |
4211 | * @phys_ptr: set to the physical address corresponding to the virtual address | |
4212 | * @prot: set to the permissions for the page containing phys_ptr | |
4213 | * @page_size: set to the size of the page containing phys_ptr | |
4214 | */ | |
2c8dd318 | 4215 | static inline int get_phys_addr(CPUARMState *env, target_ulong address, |
9ee6e8bb | 4216 | int access_type, int is_user, |
a8170e5e | 4217 | hwaddr *phys_ptr, int *prot, |
d4c430a8 | 4218 | target_ulong *page_size) |
9ee6e8bb PB |
4219 | { |
4220 | /* Fast Context Switch Extension. */ | |
4221 | if (address < 0x02000000) | |
4222 | address += env->cp15.c13_fcse; | |
4223 | ||
76e3e1bc | 4224 | if ((env->cp15.c1_sys & SCTLR_M) == 0) { |
9ee6e8bb PB |
4225 | /* MMU/MPU disabled. */ |
4226 | *phys_ptr = address; | |
3ad493fc | 4227 | *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; |
d4c430a8 | 4228 | *page_size = TARGET_PAGE_SIZE; |
9ee6e8bb PB |
4229 | return 0; |
4230 | } else if (arm_feature(env, ARM_FEATURE_MPU)) { | |
d4c430a8 | 4231 | *page_size = TARGET_PAGE_SIZE; |
9ee6e8bb PB |
4232 | return get_phys_addr_mpu(env, address, access_type, is_user, phys_ptr, |
4233 | prot); | |
3dde962f PM |
4234 | } else if (extended_addresses_enabled(env)) { |
4235 | return get_phys_addr_lpae(env, address, access_type, is_user, phys_ptr, | |
4236 | prot, page_size); | |
76e3e1bc | 4237 | } else if (env->cp15.c1_sys & SCTLR_XP) { |
9ee6e8bb | 4238 | return get_phys_addr_v6(env, address, access_type, is_user, phys_ptr, |
d4c430a8 | 4239 | prot, page_size); |
9ee6e8bb PB |
4240 | } else { |
4241 | return get_phys_addr_v5(env, address, access_type, is_user, phys_ptr, | |
d4c430a8 | 4242 | prot, page_size); |
9ee6e8bb PB |
4243 | } |
4244 | } | |
4245 | ||
7510454e AF |
4246 | int arm_cpu_handle_mmu_fault(CPUState *cs, vaddr address, |
4247 | int access_type, int mmu_idx) | |
b5ff1b31 | 4248 | { |
7510454e AF |
4249 | ARMCPU *cpu = ARM_CPU(cs); |
4250 | CPUARMState *env = &cpu->env; | |
a8170e5e | 4251 | hwaddr phys_addr; |
d4c430a8 | 4252 | target_ulong page_size; |
b5ff1b31 | 4253 | int prot; |
6ebbf390 | 4254 | int ret, is_user; |
00892383 RH |
4255 | uint32_t syn; |
4256 | bool same_el = (arm_current_pl(env) != 0); | |
b5ff1b31 | 4257 | |
6ebbf390 | 4258 | is_user = mmu_idx == MMU_USER_IDX; |
d4c430a8 PB |
4259 | ret = get_phys_addr(env, address, access_type, is_user, &phys_addr, &prot, |
4260 | &page_size); | |
b5ff1b31 FB |
4261 | if (ret == 0) { |
4262 | /* Map a single [sub]page. */ | |
dcd82c11 AB |
4263 | phys_addr &= TARGET_PAGE_MASK; |
4264 | address &= TARGET_PAGE_MASK; | |
0c591eb0 | 4265 | tlb_set_page(cs, address, phys_addr, prot, mmu_idx, page_size); |
d4c430a8 | 4266 | return 0; |
b5ff1b31 FB |
4267 | } |
4268 | ||
00892383 RH |
4269 | /* AArch64 syndrome does not have an LPAE bit */ |
4270 | syn = ret & ~(1 << 9); | |
4271 | ||
4272 | /* For insn and data aborts we assume there is no instruction syndrome | |
4273 | * information; this is always true for exceptions reported to EL1. | |
4274 | */ | |
b5ff1b31 | 4275 | if (access_type == 2) { |
00892383 | 4276 | syn = syn_insn_abort(same_el, 0, 0, syn); |
27103424 | 4277 | cs->exception_index = EXCP_PREFETCH_ABORT; |
b5ff1b31 | 4278 | } else { |
00892383 | 4279 | syn = syn_data_abort(same_el, 0, 0, 0, access_type == 1, syn); |
abf1172f PM |
4280 | if (access_type == 1 && arm_feature(env, ARM_FEATURE_V6)) { |
4281 | ret |= (1 << 11); | |
4282 | } | |
27103424 | 4283 | cs->exception_index = EXCP_DATA_ABORT; |
b5ff1b31 | 4284 | } |
00892383 RH |
4285 | |
4286 | env->exception.syndrome = syn; | |
abf1172f PM |
4287 | env->exception.vaddress = address; |
4288 | env->exception.fsr = ret; | |
b5ff1b31 FB |
4289 | return 1; |
4290 | } | |
4291 | ||
00b941e5 | 4292 | hwaddr arm_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) |
b5ff1b31 | 4293 | { |
00b941e5 | 4294 | ARMCPU *cpu = ARM_CPU(cs); |
a8170e5e | 4295 | hwaddr phys_addr; |
d4c430a8 | 4296 | target_ulong page_size; |
b5ff1b31 FB |
4297 | int prot; |
4298 | int ret; | |
4299 | ||
00b941e5 | 4300 | ret = get_phys_addr(&cpu->env, addr, 0, 0, &phys_addr, &prot, &page_size); |
b5ff1b31 | 4301 | |
00b941e5 | 4302 | if (ret != 0) { |
b5ff1b31 | 4303 | return -1; |
00b941e5 | 4304 | } |
b5ff1b31 FB |
4305 | |
4306 | return phys_addr; | |
4307 | } | |
4308 | ||
0ecb72a5 | 4309 | void HELPER(set_r13_banked)(CPUARMState *env, uint32_t mode, uint32_t val) |
9ee6e8bb | 4310 | { |
39ea3d4e PM |
4311 | if ((env->uncached_cpsr & CPSR_M) == mode) { |
4312 | env->regs[13] = val; | |
4313 | } else { | |
f5206413 | 4314 | env->banked_r13[bank_number(mode)] = val; |
39ea3d4e | 4315 | } |
9ee6e8bb PB |
4316 | } |
4317 | ||
0ecb72a5 | 4318 | uint32_t HELPER(get_r13_banked)(CPUARMState *env, uint32_t mode) |
9ee6e8bb | 4319 | { |
39ea3d4e PM |
4320 | if ((env->uncached_cpsr & CPSR_M) == mode) { |
4321 | return env->regs[13]; | |
4322 | } else { | |
f5206413 | 4323 | return env->banked_r13[bank_number(mode)]; |
39ea3d4e | 4324 | } |
9ee6e8bb PB |
4325 | } |
4326 | ||
0ecb72a5 | 4327 | uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg) |
9ee6e8bb | 4328 | { |
a47dddd7 AF |
4329 | ARMCPU *cpu = arm_env_get_cpu(env); |
4330 | ||
9ee6e8bb PB |
4331 | switch (reg) { |
4332 | case 0: /* APSR */ | |
4333 | return xpsr_read(env) & 0xf8000000; | |
4334 | case 1: /* IAPSR */ | |
4335 | return xpsr_read(env) & 0xf80001ff; | |
4336 | case 2: /* EAPSR */ | |
4337 | return xpsr_read(env) & 0xff00fc00; | |
4338 | case 3: /* xPSR */ | |
4339 | return xpsr_read(env) & 0xff00fdff; | |
4340 | case 5: /* IPSR */ | |
4341 | return xpsr_read(env) & 0x000001ff; | |
4342 | case 6: /* EPSR */ | |
4343 | return xpsr_read(env) & 0x0700fc00; | |
4344 | case 7: /* IEPSR */ | |
4345 | return xpsr_read(env) & 0x0700edff; | |
4346 | case 8: /* MSP */ | |
4347 | return env->v7m.current_sp ? env->v7m.other_sp : env->regs[13]; | |
4348 | case 9: /* PSP */ | |
4349 | return env->v7m.current_sp ? env->regs[13] : env->v7m.other_sp; | |
4350 | case 16: /* PRIMASK */ | |
4cc35614 | 4351 | return (env->daif & PSTATE_I) != 0; |
82845826 SH |
4352 | case 17: /* BASEPRI */ |
4353 | case 18: /* BASEPRI_MAX */ | |
9ee6e8bb | 4354 | return env->v7m.basepri; |
82845826 | 4355 | case 19: /* FAULTMASK */ |
4cc35614 | 4356 | return (env->daif & PSTATE_F) != 0; |
9ee6e8bb PB |
4357 | case 20: /* CONTROL */ |
4358 | return env->v7m.control; | |
4359 | default: | |
4360 | /* ??? For debugging only. */ | |
a47dddd7 | 4361 | cpu_abort(CPU(cpu), "Unimplemented system register read (%d)\n", reg); |
9ee6e8bb PB |
4362 | return 0; |
4363 | } | |
4364 | } | |
4365 | ||
0ecb72a5 | 4366 | void HELPER(v7m_msr)(CPUARMState *env, uint32_t reg, uint32_t val) |
9ee6e8bb | 4367 | { |
a47dddd7 AF |
4368 | ARMCPU *cpu = arm_env_get_cpu(env); |
4369 | ||
9ee6e8bb PB |
4370 | switch (reg) { |
4371 | case 0: /* APSR */ | |
4372 | xpsr_write(env, val, 0xf8000000); | |
4373 | break; | |
4374 | case 1: /* IAPSR */ | |
4375 | xpsr_write(env, val, 0xf8000000); | |
4376 | break; | |
4377 | case 2: /* EAPSR */ | |
4378 | xpsr_write(env, val, 0xfe00fc00); | |
4379 | break; | |
4380 | case 3: /* xPSR */ | |
4381 | xpsr_write(env, val, 0xfe00fc00); | |
4382 | break; | |
4383 | case 5: /* IPSR */ | |
4384 | /* IPSR bits are readonly. */ | |
4385 | break; | |
4386 | case 6: /* EPSR */ | |
4387 | xpsr_write(env, val, 0x0600fc00); | |
4388 | break; | |
4389 | case 7: /* IEPSR */ | |
4390 | xpsr_write(env, val, 0x0600fc00); | |
4391 | break; | |
4392 | case 8: /* MSP */ | |
4393 | if (env->v7m.current_sp) | |
4394 | env->v7m.other_sp = val; | |
4395 | else | |
4396 | env->regs[13] = val; | |
4397 | break; | |
4398 | case 9: /* PSP */ | |
4399 | if (env->v7m.current_sp) | |
4400 | env->regs[13] = val; | |
4401 | else | |
4402 | env->v7m.other_sp = val; | |
4403 | break; | |
4404 | case 16: /* PRIMASK */ | |
4cc35614 PM |
4405 | if (val & 1) { |
4406 | env->daif |= PSTATE_I; | |
4407 | } else { | |
4408 | env->daif &= ~PSTATE_I; | |
4409 | } | |
9ee6e8bb | 4410 | break; |
82845826 | 4411 | case 17: /* BASEPRI */ |
9ee6e8bb PB |
4412 | env->v7m.basepri = val & 0xff; |
4413 | break; | |
82845826 | 4414 | case 18: /* BASEPRI_MAX */ |
9ee6e8bb PB |
4415 | val &= 0xff; |
4416 | if (val != 0 && (val < env->v7m.basepri || env->v7m.basepri == 0)) | |
4417 | env->v7m.basepri = val; | |
4418 | break; | |
82845826 | 4419 | case 19: /* FAULTMASK */ |
4cc35614 PM |
4420 | if (val & 1) { |
4421 | env->daif |= PSTATE_F; | |
4422 | } else { | |
4423 | env->daif &= ~PSTATE_F; | |
4424 | } | |
82845826 | 4425 | break; |
9ee6e8bb PB |
4426 | case 20: /* CONTROL */ |
4427 | env->v7m.control = val & 3; | |
4428 | switch_v7m_sp(env, (val & 2) != 0); | |
4429 | break; | |
4430 | default: | |
4431 | /* ??? For debugging only. */ | |
a47dddd7 | 4432 | cpu_abort(CPU(cpu), "Unimplemented system register write (%d)\n", reg); |
9ee6e8bb PB |
4433 | return; |
4434 | } | |
4435 | } | |
4436 | ||
b5ff1b31 | 4437 | #endif |
6ddbc6e4 | 4438 | |
aca3f40b PM |
4439 | void HELPER(dc_zva)(CPUARMState *env, uint64_t vaddr_in) |
4440 | { | |
4441 | /* Implement DC ZVA, which zeroes a fixed-length block of memory. | |
4442 | * Note that we do not implement the (architecturally mandated) | |
4443 | * alignment fault for attempts to use this on Device memory | |
4444 | * (which matches the usual QEMU behaviour of not implementing either | |
4445 | * alignment faults or any memory attribute handling). | |
4446 | */ | |
4447 | ||
4448 | ARMCPU *cpu = arm_env_get_cpu(env); | |
4449 | uint64_t blocklen = 4 << cpu->dcz_blocksize; | |
4450 | uint64_t vaddr = vaddr_in & ~(blocklen - 1); | |
4451 | ||
4452 | #ifndef CONFIG_USER_ONLY | |
4453 | { | |
4454 | /* Slightly awkwardly, QEMU's TARGET_PAGE_SIZE may be less than | |
4455 | * the block size so we might have to do more than one TLB lookup. | |
4456 | * We know that in fact for any v8 CPU the page size is at least 4K | |
4457 | * and the block size must be 2K or less, but TARGET_PAGE_SIZE is only | |
4458 | * 1K as an artefact of legacy v5 subpage support being present in the | |
4459 | * same QEMU executable. | |
4460 | */ | |
4461 | int maxidx = DIV_ROUND_UP(blocklen, TARGET_PAGE_SIZE); | |
4462 | void *hostaddr[maxidx]; | |
4463 | int try, i; | |
4464 | ||
4465 | for (try = 0; try < 2; try++) { | |
4466 | ||
4467 | for (i = 0; i < maxidx; i++) { | |
4468 | hostaddr[i] = tlb_vaddr_to_host(env, | |
4469 | vaddr + TARGET_PAGE_SIZE * i, | |
4470 | 1, cpu_mmu_index(env)); | |
4471 | if (!hostaddr[i]) { | |
4472 | break; | |
4473 | } | |
4474 | } | |
4475 | if (i == maxidx) { | |
4476 | /* If it's all in the TLB it's fair game for just writing to; | |
4477 | * we know we don't need to update dirty status, etc. | |
4478 | */ | |
4479 | for (i = 0; i < maxidx - 1; i++) { | |
4480 | memset(hostaddr[i], 0, TARGET_PAGE_SIZE); | |
4481 | } | |
4482 | memset(hostaddr[i], 0, blocklen - (i * TARGET_PAGE_SIZE)); | |
4483 | return; | |
4484 | } | |
4485 | /* OK, try a store and see if we can populate the tlb. This | |
4486 | * might cause an exception if the memory isn't writable, | |
4487 | * in which case we will longjmp out of here. We must for | |
4488 | * this purpose use the actual register value passed to us | |
4489 | * so that we get the fault address right. | |
4490 | */ | |
4491 | helper_ret_stb_mmu(env, vaddr_in, 0, cpu_mmu_index(env), GETRA()); | |
4492 | /* Now we can populate the other TLB entries, if any */ | |
4493 | for (i = 0; i < maxidx; i++) { | |
4494 | uint64_t va = vaddr + TARGET_PAGE_SIZE * i; | |
4495 | if (va != (vaddr_in & TARGET_PAGE_MASK)) { | |
4496 | helper_ret_stb_mmu(env, va, 0, cpu_mmu_index(env), GETRA()); | |
4497 | } | |
4498 | } | |
4499 | } | |
4500 | ||
4501 | /* Slow path (probably attempt to do this to an I/O device or | |
4502 | * similar, or clearing of a block of code we have translations | |
4503 | * cached for). Just do a series of byte writes as the architecture | |
4504 | * demands. It's not worth trying to use a cpu_physical_memory_map(), | |
4505 | * memset(), unmap() sequence here because: | |
4506 | * + we'd need to account for the blocksize being larger than a page | |
4507 | * + the direct-RAM access case is almost always going to be dealt | |
4508 | * with in the fastpath code above, so there's no speed benefit | |
4509 | * + we would have to deal with the map returning NULL because the | |
4510 | * bounce buffer was in use | |
4511 | */ | |
4512 | for (i = 0; i < blocklen; i++) { | |
4513 | helper_ret_stb_mmu(env, vaddr + i, 0, cpu_mmu_index(env), GETRA()); | |
4514 | } | |
4515 | } | |
4516 | #else | |
4517 | memset(g2h(vaddr), 0, blocklen); | |
4518 | #endif | |
4519 | } | |
4520 | ||
6ddbc6e4 PB |
4521 | /* Note that signed overflow is undefined in C. The following routines are |
4522 | careful to use unsigned types where modulo arithmetic is required. | |
4523 | Failure to do so _will_ break on newer gcc. */ | |
4524 | ||
4525 | /* Signed saturating arithmetic. */ | |
4526 | ||
1654b2d6 | 4527 | /* Perform 16-bit signed saturating addition. */ |
6ddbc6e4 PB |
4528 | static inline uint16_t add16_sat(uint16_t a, uint16_t b) |
4529 | { | |
4530 | uint16_t res; | |
4531 | ||
4532 | res = a + b; | |
4533 | if (((res ^ a) & 0x8000) && !((a ^ b) & 0x8000)) { | |
4534 | if (a & 0x8000) | |
4535 | res = 0x8000; | |
4536 | else | |
4537 | res = 0x7fff; | |
4538 | } | |
4539 | return res; | |
4540 | } | |
4541 | ||
1654b2d6 | 4542 | /* Perform 8-bit signed saturating addition. */ |
6ddbc6e4 PB |
4543 | static inline uint8_t add8_sat(uint8_t a, uint8_t b) |
4544 | { | |
4545 | uint8_t res; | |
4546 | ||
4547 | res = a + b; | |
4548 | if (((res ^ a) & 0x80) && !((a ^ b) & 0x80)) { | |
4549 | if (a & 0x80) | |
4550 | res = 0x80; | |
4551 | else | |
4552 | res = 0x7f; | |
4553 | } | |
4554 | return res; | |
4555 | } | |
4556 | ||
1654b2d6 | 4557 | /* Perform 16-bit signed saturating subtraction. */ |
6ddbc6e4 PB |
4558 | static inline uint16_t sub16_sat(uint16_t a, uint16_t b) |
4559 | { | |
4560 | uint16_t res; | |
4561 | ||
4562 | res = a - b; | |
4563 | if (((res ^ a) & 0x8000) && ((a ^ b) & 0x8000)) { | |
4564 | if (a & 0x8000) | |
4565 | res = 0x8000; | |
4566 | else | |
4567 | res = 0x7fff; | |
4568 | } | |
4569 | return res; | |
4570 | } | |
4571 | ||
1654b2d6 | 4572 | /* Perform 8-bit signed saturating subtraction. */ |
6ddbc6e4 PB |
4573 | static inline uint8_t sub8_sat(uint8_t a, uint8_t b) |
4574 | { | |
4575 | uint8_t res; | |
4576 | ||
4577 | res = a - b; | |
4578 | if (((res ^ a) & 0x80) && ((a ^ b) & 0x80)) { | |
4579 | if (a & 0x80) | |
4580 | res = 0x80; | |
4581 | else | |
4582 | res = 0x7f; | |
4583 | } | |
4584 | return res; | |
4585 | } | |
4586 | ||
4587 | #define ADD16(a, b, n) RESULT(add16_sat(a, b), n, 16); | |
4588 | #define SUB16(a, b, n) RESULT(sub16_sat(a, b), n, 16); | |
4589 | #define ADD8(a, b, n) RESULT(add8_sat(a, b), n, 8); | |
4590 | #define SUB8(a, b, n) RESULT(sub8_sat(a, b), n, 8); | |
4591 | #define PFX q | |
4592 | ||
4593 | #include "op_addsub.h" | |
4594 | ||
4595 | /* Unsigned saturating arithmetic. */ | |
460a09c1 | 4596 | static inline uint16_t add16_usat(uint16_t a, uint16_t b) |
6ddbc6e4 PB |
4597 | { |
4598 | uint16_t res; | |
4599 | res = a + b; | |
4600 | if (res < a) | |
4601 | res = 0xffff; | |
4602 | return res; | |
4603 | } | |
4604 | ||
460a09c1 | 4605 | static inline uint16_t sub16_usat(uint16_t a, uint16_t b) |
6ddbc6e4 | 4606 | { |
4c4fd3f8 | 4607 | if (a > b) |
6ddbc6e4 PB |
4608 | return a - b; |
4609 | else | |
4610 | return 0; | |
4611 | } | |
4612 | ||
4613 | static inline uint8_t add8_usat(uint8_t a, uint8_t b) | |
4614 | { | |
4615 | uint8_t res; | |
4616 | res = a + b; | |
4617 | if (res < a) | |
4618 | res = 0xff; | |
4619 | return res; | |
4620 | } | |
4621 | ||
4622 | static inline uint8_t sub8_usat(uint8_t a, uint8_t b) | |
4623 | { | |
4c4fd3f8 | 4624 | if (a > b) |
6ddbc6e4 PB |
4625 | return a - b; |
4626 | else | |
4627 | return 0; | |
4628 | } | |
4629 | ||
4630 | #define ADD16(a, b, n) RESULT(add16_usat(a, b), n, 16); | |
4631 | #define SUB16(a, b, n) RESULT(sub16_usat(a, b), n, 16); | |
4632 | #define ADD8(a, b, n) RESULT(add8_usat(a, b), n, 8); | |
4633 | #define SUB8(a, b, n) RESULT(sub8_usat(a, b), n, 8); | |
4634 | #define PFX uq | |
4635 | ||
4636 | #include "op_addsub.h" | |
4637 | ||
4638 | /* Signed modulo arithmetic. */ | |
4639 | #define SARITH16(a, b, n, op) do { \ | |
4640 | int32_t sum; \ | |
db6e2e65 | 4641 | sum = (int32_t)(int16_t)(a) op (int32_t)(int16_t)(b); \ |
6ddbc6e4 PB |
4642 | RESULT(sum, n, 16); \ |
4643 | if (sum >= 0) \ | |
4644 | ge |= 3 << (n * 2); \ | |
4645 | } while(0) | |
4646 | ||
4647 | #define SARITH8(a, b, n, op) do { \ | |
4648 | int32_t sum; \ | |
db6e2e65 | 4649 | sum = (int32_t)(int8_t)(a) op (int32_t)(int8_t)(b); \ |
6ddbc6e4 PB |
4650 | RESULT(sum, n, 8); \ |
4651 | if (sum >= 0) \ | |
4652 | ge |= 1 << n; \ | |
4653 | } while(0) | |
4654 | ||
4655 | ||
4656 | #define ADD16(a, b, n) SARITH16(a, b, n, +) | |
4657 | #define SUB16(a, b, n) SARITH16(a, b, n, -) | |
4658 | #define ADD8(a, b, n) SARITH8(a, b, n, +) | |
4659 | #define SUB8(a, b, n) SARITH8(a, b, n, -) | |
4660 | #define PFX s | |
4661 | #define ARITH_GE | |
4662 | ||
4663 | #include "op_addsub.h" | |
4664 | ||
4665 | /* Unsigned modulo arithmetic. */ | |
4666 | #define ADD16(a, b, n) do { \ | |
4667 | uint32_t sum; \ | |
4668 | sum = (uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b); \ | |
4669 | RESULT(sum, n, 16); \ | |
a87aa10b | 4670 | if ((sum >> 16) == 1) \ |
6ddbc6e4 PB |
4671 | ge |= 3 << (n * 2); \ |
4672 | } while(0) | |
4673 | ||
4674 | #define ADD8(a, b, n) do { \ | |
4675 | uint32_t sum; \ | |
4676 | sum = (uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b); \ | |
4677 | RESULT(sum, n, 8); \ | |
a87aa10b AZ |
4678 | if ((sum >> 8) == 1) \ |
4679 | ge |= 1 << n; \ | |
6ddbc6e4 PB |
4680 | } while(0) |
4681 | ||
4682 | #define SUB16(a, b, n) do { \ | |
4683 | uint32_t sum; \ | |
4684 | sum = (uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b); \ | |
4685 | RESULT(sum, n, 16); \ | |
4686 | if ((sum >> 16) == 0) \ | |
4687 | ge |= 3 << (n * 2); \ | |
4688 | } while(0) | |
4689 | ||
4690 | #define SUB8(a, b, n) do { \ | |
4691 | uint32_t sum; \ | |
4692 | sum = (uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b); \ | |
4693 | RESULT(sum, n, 8); \ | |
4694 | if ((sum >> 8) == 0) \ | |
a87aa10b | 4695 | ge |= 1 << n; \ |
6ddbc6e4 PB |
4696 | } while(0) |
4697 | ||
4698 | #define PFX u | |
4699 | #define ARITH_GE | |
4700 | ||
4701 | #include "op_addsub.h" | |
4702 | ||
4703 | /* Halved signed arithmetic. */ | |
4704 | #define ADD16(a, b, n) \ | |
4705 | RESULT(((int32_t)(int16_t)(a) + (int32_t)(int16_t)(b)) >> 1, n, 16) | |
4706 | #define SUB16(a, b, n) \ | |
4707 | RESULT(((int32_t)(int16_t)(a) - (int32_t)(int16_t)(b)) >> 1, n, 16) | |
4708 | #define ADD8(a, b, n) \ | |
4709 | RESULT(((int32_t)(int8_t)(a) + (int32_t)(int8_t)(b)) >> 1, n, 8) | |
4710 | #define SUB8(a, b, n) \ | |
4711 | RESULT(((int32_t)(int8_t)(a) - (int32_t)(int8_t)(b)) >> 1, n, 8) | |
4712 | #define PFX sh | |
4713 | ||
4714 | #include "op_addsub.h" | |
4715 | ||
4716 | /* Halved unsigned arithmetic. */ | |
4717 | #define ADD16(a, b, n) \ | |
4718 | RESULT(((uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b)) >> 1, n, 16) | |
4719 | #define SUB16(a, b, n) \ | |
4720 | RESULT(((uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b)) >> 1, n, 16) | |
4721 | #define ADD8(a, b, n) \ | |
4722 | RESULT(((uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b)) >> 1, n, 8) | |
4723 | #define SUB8(a, b, n) \ | |
4724 | RESULT(((uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b)) >> 1, n, 8) | |
4725 | #define PFX uh | |
4726 | ||
4727 | #include "op_addsub.h" | |
4728 | ||
4729 | static inline uint8_t do_usad(uint8_t a, uint8_t b) | |
4730 | { | |
4731 | if (a > b) | |
4732 | return a - b; | |
4733 | else | |
4734 | return b - a; | |
4735 | } | |
4736 | ||
4737 | /* Unsigned sum of absolute byte differences. */ | |
4738 | uint32_t HELPER(usad8)(uint32_t a, uint32_t b) | |
4739 | { | |
4740 | uint32_t sum; | |
4741 | sum = do_usad(a, b); | |
4742 | sum += do_usad(a >> 8, b >> 8); | |
4743 | sum += do_usad(a >> 16, b >>16); | |
4744 | sum += do_usad(a >> 24, b >> 24); | |
4745 | return sum; | |
4746 | } | |
4747 | ||
4748 | /* For ARMv6 SEL instruction. */ | |
4749 | uint32_t HELPER(sel_flags)(uint32_t flags, uint32_t a, uint32_t b) | |
4750 | { | |
4751 | uint32_t mask; | |
4752 | ||
4753 | mask = 0; | |
4754 | if (flags & 1) | |
4755 | mask |= 0xff; | |
4756 | if (flags & 2) | |
4757 | mask |= 0xff00; | |
4758 | if (flags & 4) | |
4759 | mask |= 0xff0000; | |
4760 | if (flags & 8) | |
4761 | mask |= 0xff000000; | |
4762 | return (a & mask) | (b & ~mask); | |
4763 | } | |
4764 | ||
b90372ad PM |
4765 | /* VFP support. We follow the convention used for VFP instructions: |
4766 | Single precision routines have a "s" suffix, double precision a | |
4373f3ce PB |
4767 | "d" suffix. */ |
4768 | ||
4769 | /* Convert host exception flags to vfp form. */ | |
4770 | static inline int vfp_exceptbits_from_host(int host_bits) | |
4771 | { | |
4772 | int target_bits = 0; | |
4773 | ||
4774 | if (host_bits & float_flag_invalid) | |
4775 | target_bits |= 1; | |
4776 | if (host_bits & float_flag_divbyzero) | |
4777 | target_bits |= 2; | |
4778 | if (host_bits & float_flag_overflow) | |
4779 | target_bits |= 4; | |
36802b6b | 4780 | if (host_bits & (float_flag_underflow | float_flag_output_denormal)) |
4373f3ce PB |
4781 | target_bits |= 8; |
4782 | if (host_bits & float_flag_inexact) | |
4783 | target_bits |= 0x10; | |
cecd8504 PM |
4784 | if (host_bits & float_flag_input_denormal) |
4785 | target_bits |= 0x80; | |
4373f3ce PB |
4786 | return target_bits; |
4787 | } | |
4788 | ||
0ecb72a5 | 4789 | uint32_t HELPER(vfp_get_fpscr)(CPUARMState *env) |
4373f3ce PB |
4790 | { |
4791 | int i; | |
4792 | uint32_t fpscr; | |
4793 | ||
4794 | fpscr = (env->vfp.xregs[ARM_VFP_FPSCR] & 0xffc8ffff) | |
4795 | | (env->vfp.vec_len << 16) | |
4796 | | (env->vfp.vec_stride << 20); | |
4797 | i = get_float_exception_flags(&env->vfp.fp_status); | |
3a492f3a | 4798 | i |= get_float_exception_flags(&env->vfp.standard_fp_status); |
4373f3ce PB |
4799 | fpscr |= vfp_exceptbits_from_host(i); |
4800 | return fpscr; | |
4801 | } | |
4802 | ||
0ecb72a5 | 4803 | uint32_t vfp_get_fpscr(CPUARMState *env) |
01653295 PM |
4804 | { |
4805 | return HELPER(vfp_get_fpscr)(env); | |
4806 | } | |
4807 | ||
4373f3ce PB |
4808 | /* Convert vfp exception flags to target form. */ |
4809 | static inline int vfp_exceptbits_to_host(int target_bits) | |
4810 | { | |
4811 | int host_bits = 0; | |
4812 | ||
4813 | if (target_bits & 1) | |
4814 | host_bits |= float_flag_invalid; | |
4815 | if (target_bits & 2) | |
4816 | host_bits |= float_flag_divbyzero; | |
4817 | if (target_bits & 4) | |
4818 | host_bits |= float_flag_overflow; | |
4819 | if (target_bits & 8) | |
4820 | host_bits |= float_flag_underflow; | |
4821 | if (target_bits & 0x10) | |
4822 | host_bits |= float_flag_inexact; | |
cecd8504 PM |
4823 | if (target_bits & 0x80) |
4824 | host_bits |= float_flag_input_denormal; | |
4373f3ce PB |
4825 | return host_bits; |
4826 | } | |
4827 | ||
0ecb72a5 | 4828 | void HELPER(vfp_set_fpscr)(CPUARMState *env, uint32_t val) |
4373f3ce PB |
4829 | { |
4830 | int i; | |
4831 | uint32_t changed; | |
4832 | ||
4833 | changed = env->vfp.xregs[ARM_VFP_FPSCR]; | |
4834 | env->vfp.xregs[ARM_VFP_FPSCR] = (val & 0xffc8ffff); | |
4835 | env->vfp.vec_len = (val >> 16) & 7; | |
4836 | env->vfp.vec_stride = (val >> 20) & 3; | |
4837 | ||
4838 | changed ^= val; | |
4839 | if (changed & (3 << 22)) { | |
4840 | i = (val >> 22) & 3; | |
4841 | switch (i) { | |
4d3da0f3 | 4842 | case FPROUNDING_TIEEVEN: |
4373f3ce PB |
4843 | i = float_round_nearest_even; |
4844 | break; | |
4d3da0f3 | 4845 | case FPROUNDING_POSINF: |
4373f3ce PB |
4846 | i = float_round_up; |
4847 | break; | |
4d3da0f3 | 4848 | case FPROUNDING_NEGINF: |
4373f3ce PB |
4849 | i = float_round_down; |
4850 | break; | |
4d3da0f3 | 4851 | case FPROUNDING_ZERO: |
4373f3ce PB |
4852 | i = float_round_to_zero; |
4853 | break; | |
4854 | } | |
4855 | set_float_rounding_mode(i, &env->vfp.fp_status); | |
4856 | } | |
cecd8504 | 4857 | if (changed & (1 << 24)) { |
fe76d976 | 4858 | set_flush_to_zero((val & (1 << 24)) != 0, &env->vfp.fp_status); |
cecd8504 PM |
4859 | set_flush_inputs_to_zero((val & (1 << 24)) != 0, &env->vfp.fp_status); |
4860 | } | |
5c7908ed PB |
4861 | if (changed & (1 << 25)) |
4862 | set_default_nan_mode((val & (1 << 25)) != 0, &env->vfp.fp_status); | |
4373f3ce | 4863 | |
b12c390b | 4864 | i = vfp_exceptbits_to_host(val); |
4373f3ce | 4865 | set_float_exception_flags(i, &env->vfp.fp_status); |
3a492f3a | 4866 | set_float_exception_flags(0, &env->vfp.standard_fp_status); |
4373f3ce PB |
4867 | } |
4868 | ||
0ecb72a5 | 4869 | void vfp_set_fpscr(CPUARMState *env, uint32_t val) |
01653295 PM |
4870 | { |
4871 | HELPER(vfp_set_fpscr)(env, val); | |
4872 | } | |
4873 | ||
4373f3ce PB |
4874 | #define VFP_HELPER(name, p) HELPER(glue(glue(vfp_,name),p)) |
4875 | ||
4876 | #define VFP_BINOP(name) \ | |
ae1857ec | 4877 | float32 VFP_HELPER(name, s)(float32 a, float32 b, void *fpstp) \ |
4373f3ce | 4878 | { \ |
ae1857ec PM |
4879 | float_status *fpst = fpstp; \ |
4880 | return float32_ ## name(a, b, fpst); \ | |
4373f3ce | 4881 | } \ |
ae1857ec | 4882 | float64 VFP_HELPER(name, d)(float64 a, float64 b, void *fpstp) \ |
4373f3ce | 4883 | { \ |
ae1857ec PM |
4884 | float_status *fpst = fpstp; \ |
4885 | return float64_ ## name(a, b, fpst); \ | |
4373f3ce PB |
4886 | } |
4887 | VFP_BINOP(add) | |
4888 | VFP_BINOP(sub) | |
4889 | VFP_BINOP(mul) | |
4890 | VFP_BINOP(div) | |
f71a2ae5 PM |
4891 | VFP_BINOP(min) |
4892 | VFP_BINOP(max) | |
4893 | VFP_BINOP(minnum) | |
4894 | VFP_BINOP(maxnum) | |
4373f3ce PB |
4895 | #undef VFP_BINOP |
4896 | ||
4897 | float32 VFP_HELPER(neg, s)(float32 a) | |
4898 | { | |
4899 | return float32_chs(a); | |
4900 | } | |
4901 | ||
4902 | float64 VFP_HELPER(neg, d)(float64 a) | |
4903 | { | |
66230e0d | 4904 | return float64_chs(a); |
4373f3ce PB |
4905 | } |
4906 | ||
4907 | float32 VFP_HELPER(abs, s)(float32 a) | |
4908 | { | |
4909 | return float32_abs(a); | |
4910 | } | |
4911 | ||
4912 | float64 VFP_HELPER(abs, d)(float64 a) | |
4913 | { | |
66230e0d | 4914 | return float64_abs(a); |
4373f3ce PB |
4915 | } |
4916 | ||
0ecb72a5 | 4917 | float32 VFP_HELPER(sqrt, s)(float32 a, CPUARMState *env) |
4373f3ce PB |
4918 | { |
4919 | return float32_sqrt(a, &env->vfp.fp_status); | |
4920 | } | |
4921 | ||
0ecb72a5 | 4922 | float64 VFP_HELPER(sqrt, d)(float64 a, CPUARMState *env) |
4373f3ce PB |
4923 | { |
4924 | return float64_sqrt(a, &env->vfp.fp_status); | |
4925 | } | |
4926 | ||
4927 | /* XXX: check quiet/signaling case */ | |
4928 | #define DO_VFP_cmp(p, type) \ | |
0ecb72a5 | 4929 | void VFP_HELPER(cmp, p)(type a, type b, CPUARMState *env) \ |
4373f3ce PB |
4930 | { \ |
4931 | uint32_t flags; \ | |
4932 | switch(type ## _compare_quiet(a, b, &env->vfp.fp_status)) { \ | |
4933 | case 0: flags = 0x6; break; \ | |
4934 | case -1: flags = 0x8; break; \ | |
4935 | case 1: flags = 0x2; break; \ | |
4936 | default: case 2: flags = 0x3; break; \ | |
4937 | } \ | |
4938 | env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \ | |
4939 | | (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \ | |
4940 | } \ | |
0ecb72a5 | 4941 | void VFP_HELPER(cmpe, p)(type a, type b, CPUARMState *env) \ |
4373f3ce PB |
4942 | { \ |
4943 | uint32_t flags; \ | |
4944 | switch(type ## _compare(a, b, &env->vfp.fp_status)) { \ | |
4945 | case 0: flags = 0x6; break; \ | |
4946 | case -1: flags = 0x8; break; \ | |
4947 | case 1: flags = 0x2; break; \ | |
4948 | default: case 2: flags = 0x3; break; \ | |
4949 | } \ | |
4950 | env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \ | |
4951 | | (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \ | |
4952 | } | |
4953 | DO_VFP_cmp(s, float32) | |
4954 | DO_VFP_cmp(d, float64) | |
4955 | #undef DO_VFP_cmp | |
4956 | ||
5500b06c | 4957 | /* Integer to float and float to integer conversions */ |
4373f3ce | 4958 | |
5500b06c PM |
4959 | #define CONV_ITOF(name, fsz, sign) \ |
4960 | float##fsz HELPER(name)(uint32_t x, void *fpstp) \ | |
4961 | { \ | |
4962 | float_status *fpst = fpstp; \ | |
85836979 | 4963 | return sign##int32_to_##float##fsz((sign##int32_t)x, fpst); \ |
4373f3ce PB |
4964 | } |
4965 | ||
5500b06c PM |
4966 | #define CONV_FTOI(name, fsz, sign, round) \ |
4967 | uint32_t HELPER(name)(float##fsz x, void *fpstp) \ | |
4968 | { \ | |
4969 | float_status *fpst = fpstp; \ | |
4970 | if (float##fsz##_is_any_nan(x)) { \ | |
4971 | float_raise(float_flag_invalid, fpst); \ | |
4972 | return 0; \ | |
4973 | } \ | |
4974 | return float##fsz##_to_##sign##int32##round(x, fpst); \ | |
4373f3ce PB |
4975 | } |
4976 | ||
5500b06c PM |
4977 | #define FLOAT_CONVS(name, p, fsz, sign) \ |
4978 | CONV_ITOF(vfp_##name##to##p, fsz, sign) \ | |
4979 | CONV_FTOI(vfp_to##name##p, fsz, sign, ) \ | |
4980 | CONV_FTOI(vfp_to##name##z##p, fsz, sign, _round_to_zero) | |
4373f3ce | 4981 | |
5500b06c PM |
4982 | FLOAT_CONVS(si, s, 32, ) |
4983 | FLOAT_CONVS(si, d, 64, ) | |
4984 | FLOAT_CONVS(ui, s, 32, u) | |
4985 | FLOAT_CONVS(ui, d, 64, u) | |
4373f3ce | 4986 | |
5500b06c PM |
4987 | #undef CONV_ITOF |
4988 | #undef CONV_FTOI | |
4989 | #undef FLOAT_CONVS | |
4373f3ce PB |
4990 | |
4991 | /* floating point conversion */ | |
0ecb72a5 | 4992 | float64 VFP_HELPER(fcvtd, s)(float32 x, CPUARMState *env) |
4373f3ce | 4993 | { |
2d627737 PM |
4994 | float64 r = float32_to_float64(x, &env->vfp.fp_status); |
4995 | /* ARM requires that S<->D conversion of any kind of NaN generates | |
4996 | * a quiet NaN by forcing the most significant frac bit to 1. | |
4997 | */ | |
4998 | return float64_maybe_silence_nan(r); | |
4373f3ce PB |
4999 | } |
5000 | ||
0ecb72a5 | 5001 | float32 VFP_HELPER(fcvts, d)(float64 x, CPUARMState *env) |
4373f3ce | 5002 | { |
2d627737 PM |
5003 | float32 r = float64_to_float32(x, &env->vfp.fp_status); |
5004 | /* ARM requires that S<->D conversion of any kind of NaN generates | |
5005 | * a quiet NaN by forcing the most significant frac bit to 1. | |
5006 | */ | |
5007 | return float32_maybe_silence_nan(r); | |
4373f3ce PB |
5008 | } |
5009 | ||
5010 | /* VFP3 fixed point conversion. */ | |
16d5b3ca | 5011 | #define VFP_CONV_FIX_FLOAT(name, p, fsz, isz, itype) \ |
8ed697e8 WN |
5012 | float##fsz HELPER(vfp_##name##to##p)(uint##isz##_t x, uint32_t shift, \ |
5013 | void *fpstp) \ | |
4373f3ce | 5014 | { \ |
5500b06c | 5015 | float_status *fpst = fpstp; \ |
622465e1 | 5016 | float##fsz tmp; \ |
8ed697e8 | 5017 | tmp = itype##_to_##float##fsz(x, fpst); \ |
5500b06c | 5018 | return float##fsz##_scalbn(tmp, -(int)shift, fpst); \ |
16d5b3ca WN |
5019 | } |
5020 | ||
abe66f70 PM |
5021 | /* Notice that we want only input-denormal exception flags from the |
5022 | * scalbn operation: the other possible flags (overflow+inexact if | |
5023 | * we overflow to infinity, output-denormal) aren't correct for the | |
5024 | * complete scale-and-convert operation. | |
5025 | */ | |
16d5b3ca WN |
5026 | #define VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, round) \ |
5027 | uint##isz##_t HELPER(vfp_to##name##p##round)(float##fsz x, \ | |
5028 | uint32_t shift, \ | |
5029 | void *fpstp) \ | |
4373f3ce | 5030 | { \ |
5500b06c | 5031 | float_status *fpst = fpstp; \ |
abe66f70 | 5032 | int old_exc_flags = get_float_exception_flags(fpst); \ |
622465e1 PM |
5033 | float##fsz tmp; \ |
5034 | if (float##fsz##_is_any_nan(x)) { \ | |
5500b06c | 5035 | float_raise(float_flag_invalid, fpst); \ |
622465e1 | 5036 | return 0; \ |
09d9487f | 5037 | } \ |
5500b06c | 5038 | tmp = float##fsz##_scalbn(x, shift, fpst); \ |
abe66f70 PM |
5039 | old_exc_flags |= get_float_exception_flags(fpst) \ |
5040 | & float_flag_input_denormal; \ | |
5041 | set_float_exception_flags(old_exc_flags, fpst); \ | |
16d5b3ca | 5042 | return float##fsz##_to_##itype##round(tmp, fpst); \ |
622465e1 PM |
5043 | } |
5044 | ||
16d5b3ca WN |
5045 | #define VFP_CONV_FIX(name, p, fsz, isz, itype) \ |
5046 | VFP_CONV_FIX_FLOAT(name, p, fsz, isz, itype) \ | |
3c6a074a WN |
5047 | VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, _round_to_zero) \ |
5048 | VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, ) | |
5049 | ||
5050 | #define VFP_CONV_FIX_A64(name, p, fsz, isz, itype) \ | |
5051 | VFP_CONV_FIX_FLOAT(name, p, fsz, isz, itype) \ | |
5052 | VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, ) | |
16d5b3ca | 5053 | |
8ed697e8 WN |
5054 | VFP_CONV_FIX(sh, d, 64, 64, int16) |
5055 | VFP_CONV_FIX(sl, d, 64, 64, int32) | |
3c6a074a | 5056 | VFP_CONV_FIX_A64(sq, d, 64, 64, int64) |
8ed697e8 WN |
5057 | VFP_CONV_FIX(uh, d, 64, 64, uint16) |
5058 | VFP_CONV_FIX(ul, d, 64, 64, uint32) | |
3c6a074a | 5059 | VFP_CONV_FIX_A64(uq, d, 64, 64, uint64) |
8ed697e8 WN |
5060 | VFP_CONV_FIX(sh, s, 32, 32, int16) |
5061 | VFP_CONV_FIX(sl, s, 32, 32, int32) | |
3c6a074a | 5062 | VFP_CONV_FIX_A64(sq, s, 32, 64, int64) |
8ed697e8 WN |
5063 | VFP_CONV_FIX(uh, s, 32, 32, uint16) |
5064 | VFP_CONV_FIX(ul, s, 32, 32, uint32) | |
3c6a074a | 5065 | VFP_CONV_FIX_A64(uq, s, 32, 64, uint64) |
4373f3ce | 5066 | #undef VFP_CONV_FIX |
16d5b3ca WN |
5067 | #undef VFP_CONV_FIX_FLOAT |
5068 | #undef VFP_CONV_FLOAT_FIX_ROUND | |
4373f3ce | 5069 | |
52a1f6a3 AG |
5070 | /* Set the current fp rounding mode and return the old one. |
5071 | * The argument is a softfloat float_round_ value. | |
5072 | */ | |
5073 | uint32_t HELPER(set_rmode)(uint32_t rmode, CPUARMState *env) | |
5074 | { | |
5075 | float_status *fp_status = &env->vfp.fp_status; | |
5076 | ||
5077 | uint32_t prev_rmode = get_float_rounding_mode(fp_status); | |
5078 | set_float_rounding_mode(rmode, fp_status); | |
5079 | ||
5080 | return prev_rmode; | |
5081 | } | |
5082 | ||
43630e58 WN |
5083 | /* Set the current fp rounding mode in the standard fp status and return |
5084 | * the old one. This is for NEON instructions that need to change the | |
5085 | * rounding mode but wish to use the standard FPSCR values for everything | |
5086 | * else. Always set the rounding mode back to the correct value after | |
5087 | * modifying it. | |
5088 | * The argument is a softfloat float_round_ value. | |
5089 | */ | |
5090 | uint32_t HELPER(set_neon_rmode)(uint32_t rmode, CPUARMState *env) | |
5091 | { | |
5092 | float_status *fp_status = &env->vfp.standard_fp_status; | |
5093 | ||
5094 | uint32_t prev_rmode = get_float_rounding_mode(fp_status); | |
5095 | set_float_rounding_mode(rmode, fp_status); | |
5096 | ||
5097 | return prev_rmode; | |
5098 | } | |
5099 | ||
60011498 | 5100 | /* Half precision conversions. */ |
0ecb72a5 | 5101 | static float32 do_fcvt_f16_to_f32(uint32_t a, CPUARMState *env, float_status *s) |
60011498 | 5102 | { |
60011498 | 5103 | int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0; |
fb91678d PM |
5104 | float32 r = float16_to_float32(make_float16(a), ieee, s); |
5105 | if (ieee) { | |
5106 | return float32_maybe_silence_nan(r); | |
5107 | } | |
5108 | return r; | |
60011498 PB |
5109 | } |
5110 | ||
0ecb72a5 | 5111 | static uint32_t do_fcvt_f32_to_f16(float32 a, CPUARMState *env, float_status *s) |
60011498 | 5112 | { |
60011498 | 5113 | int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0; |
fb91678d PM |
5114 | float16 r = float32_to_float16(a, ieee, s); |
5115 | if (ieee) { | |
5116 | r = float16_maybe_silence_nan(r); | |
5117 | } | |
5118 | return float16_val(r); | |
60011498 PB |
5119 | } |
5120 | ||
0ecb72a5 | 5121 | float32 HELPER(neon_fcvt_f16_to_f32)(uint32_t a, CPUARMState *env) |
2d981da7 PM |
5122 | { |
5123 | return do_fcvt_f16_to_f32(a, env, &env->vfp.standard_fp_status); | |
5124 | } | |
5125 | ||
0ecb72a5 | 5126 | uint32_t HELPER(neon_fcvt_f32_to_f16)(float32 a, CPUARMState *env) |
2d981da7 PM |
5127 | { |
5128 | return do_fcvt_f32_to_f16(a, env, &env->vfp.standard_fp_status); | |
5129 | } | |
5130 | ||
0ecb72a5 | 5131 | float32 HELPER(vfp_fcvt_f16_to_f32)(uint32_t a, CPUARMState *env) |
2d981da7 PM |
5132 | { |
5133 | return do_fcvt_f16_to_f32(a, env, &env->vfp.fp_status); | |
5134 | } | |
5135 | ||
0ecb72a5 | 5136 | uint32_t HELPER(vfp_fcvt_f32_to_f16)(float32 a, CPUARMState *env) |
2d981da7 PM |
5137 | { |
5138 | return do_fcvt_f32_to_f16(a, env, &env->vfp.fp_status); | |
5139 | } | |
5140 | ||
8900aad2 PM |
5141 | float64 HELPER(vfp_fcvt_f16_to_f64)(uint32_t a, CPUARMState *env) |
5142 | { | |
5143 | int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0; | |
5144 | float64 r = float16_to_float64(make_float16(a), ieee, &env->vfp.fp_status); | |
5145 | if (ieee) { | |
5146 | return float64_maybe_silence_nan(r); | |
5147 | } | |
5148 | return r; | |
5149 | } | |
5150 | ||
5151 | uint32_t HELPER(vfp_fcvt_f64_to_f16)(float64 a, CPUARMState *env) | |
5152 | { | |
5153 | int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0; | |
5154 | float16 r = float64_to_float16(a, ieee, &env->vfp.fp_status); | |
5155 | if (ieee) { | |
5156 | r = float16_maybe_silence_nan(r); | |
5157 | } | |
5158 | return float16_val(r); | |
5159 | } | |
5160 | ||
dda3ec49 | 5161 | #define float32_two make_float32(0x40000000) |
6aae3df1 PM |
5162 | #define float32_three make_float32(0x40400000) |
5163 | #define float32_one_point_five make_float32(0x3fc00000) | |
dda3ec49 | 5164 | |
0ecb72a5 | 5165 | float32 HELPER(recps_f32)(float32 a, float32 b, CPUARMState *env) |
4373f3ce | 5166 | { |
dda3ec49 PM |
5167 | float_status *s = &env->vfp.standard_fp_status; |
5168 | if ((float32_is_infinity(a) && float32_is_zero_or_denormal(b)) || | |
5169 | (float32_is_infinity(b) && float32_is_zero_or_denormal(a))) { | |
43fe9bdb PM |
5170 | if (!(float32_is_zero(a) || float32_is_zero(b))) { |
5171 | float_raise(float_flag_input_denormal, s); | |
5172 | } | |
dda3ec49 PM |
5173 | return float32_two; |
5174 | } | |
5175 | return float32_sub(float32_two, float32_mul(a, b, s), s); | |
4373f3ce PB |
5176 | } |
5177 | ||
0ecb72a5 | 5178 | float32 HELPER(rsqrts_f32)(float32 a, float32 b, CPUARMState *env) |
4373f3ce | 5179 | { |
71826966 | 5180 | float_status *s = &env->vfp.standard_fp_status; |
9ea62f57 PM |
5181 | float32 product; |
5182 | if ((float32_is_infinity(a) && float32_is_zero_or_denormal(b)) || | |
5183 | (float32_is_infinity(b) && float32_is_zero_or_denormal(a))) { | |
43fe9bdb PM |
5184 | if (!(float32_is_zero(a) || float32_is_zero(b))) { |
5185 | float_raise(float_flag_input_denormal, s); | |
5186 | } | |
6aae3df1 | 5187 | return float32_one_point_five; |
9ea62f57 | 5188 | } |
6aae3df1 PM |
5189 | product = float32_mul(a, b, s); |
5190 | return float32_div(float32_sub(float32_three, product, s), float32_two, s); | |
4373f3ce PB |
5191 | } |
5192 | ||
8f8e3aa4 PB |
5193 | /* NEON helpers. */ |
5194 | ||
56bf4fe2 CL |
5195 | /* Constants 256 and 512 are used in some helpers; we avoid relying on |
5196 | * int->float conversions at run-time. */ | |
5197 | #define float64_256 make_float64(0x4070000000000000LL) | |
5198 | #define float64_512 make_float64(0x4080000000000000LL) | |
b6d4443a AB |
5199 | #define float32_maxnorm make_float32(0x7f7fffff) |
5200 | #define float64_maxnorm make_float64(0x7fefffffffffffffLL) | |
56bf4fe2 | 5201 | |
b6d4443a AB |
5202 | /* Reciprocal functions |
5203 | * | |
5204 | * The algorithm that must be used to calculate the estimate | |
5205 | * is specified by the ARM ARM, see FPRecipEstimate() | |
fe0e4872 | 5206 | */ |
b6d4443a AB |
5207 | |
5208 | static float64 recip_estimate(float64 a, float_status *real_fp_status) | |
fe0e4872 | 5209 | { |
1146a817 PM |
5210 | /* These calculations mustn't set any fp exception flags, |
5211 | * so we use a local copy of the fp_status. | |
5212 | */ | |
b6d4443a | 5213 | float_status dummy_status = *real_fp_status; |
1146a817 | 5214 | float_status *s = &dummy_status; |
fe0e4872 CL |
5215 | /* q = (int)(a * 512.0) */ |
5216 | float64 q = float64_mul(float64_512, a, s); | |
5217 | int64_t q_int = float64_to_int64_round_to_zero(q, s); | |
5218 | ||
5219 | /* r = 1.0 / (((double)q + 0.5) / 512.0) */ | |
5220 | q = int64_to_float64(q_int, s); | |
5221 | q = float64_add(q, float64_half, s); | |
5222 | q = float64_div(q, float64_512, s); | |
5223 | q = float64_div(float64_one, q, s); | |
5224 | ||
5225 | /* s = (int)(256.0 * r + 0.5) */ | |
5226 | q = float64_mul(q, float64_256, s); | |
5227 | q = float64_add(q, float64_half, s); | |
5228 | q_int = float64_to_int64_round_to_zero(q, s); | |
5229 | ||
5230 | /* return (double)s / 256.0 */ | |
5231 | return float64_div(int64_to_float64(q_int, s), float64_256, s); | |
5232 | } | |
5233 | ||
b6d4443a AB |
5234 | /* Common wrapper to call recip_estimate */ |
5235 | static float64 call_recip_estimate(float64 num, int off, float_status *fpst) | |
4373f3ce | 5236 | { |
b6d4443a AB |
5237 | uint64_t val64 = float64_val(num); |
5238 | uint64_t frac = extract64(val64, 0, 52); | |
5239 | int64_t exp = extract64(val64, 52, 11); | |
5240 | uint64_t sbit; | |
5241 | float64 scaled, estimate; | |
fe0e4872 | 5242 | |
b6d4443a AB |
5243 | /* Generate the scaled number for the estimate function */ |
5244 | if (exp == 0) { | |
5245 | if (extract64(frac, 51, 1) == 0) { | |
5246 | exp = -1; | |
5247 | frac = extract64(frac, 0, 50) << 2; | |
5248 | } else { | |
5249 | frac = extract64(frac, 0, 51) << 1; | |
5250 | } | |
5251 | } | |
fe0e4872 | 5252 | |
b6d4443a AB |
5253 | /* scaled = '0' : '01111111110' : fraction<51:44> : Zeros(44); */ |
5254 | scaled = make_float64((0x3feULL << 52) | |
5255 | | extract64(frac, 44, 8) << 44); | |
5256 | ||
5257 | estimate = recip_estimate(scaled, fpst); | |
5258 | ||
5259 | /* Build new result */ | |
5260 | val64 = float64_val(estimate); | |
5261 | sbit = 0x8000000000000000ULL & val64; | |
5262 | exp = off - exp; | |
5263 | frac = extract64(val64, 0, 52); | |
5264 | ||
5265 | if (exp == 0) { | |
5266 | frac = 1ULL << 51 | extract64(frac, 1, 51); | |
5267 | } else if (exp == -1) { | |
5268 | frac = 1ULL << 50 | extract64(frac, 2, 50); | |
5269 | exp = 0; | |
5270 | } | |
5271 | ||
5272 | return make_float64(sbit | (exp << 52) | frac); | |
5273 | } | |
5274 | ||
5275 | static bool round_to_inf(float_status *fpst, bool sign_bit) | |
5276 | { | |
5277 | switch (fpst->float_rounding_mode) { | |
5278 | case float_round_nearest_even: /* Round to Nearest */ | |
5279 | return true; | |
5280 | case float_round_up: /* Round to +Inf */ | |
5281 | return !sign_bit; | |
5282 | case float_round_down: /* Round to -Inf */ | |
5283 | return sign_bit; | |
5284 | case float_round_to_zero: /* Round to Zero */ | |
5285 | return false; | |
5286 | } | |
5287 | ||
5288 | g_assert_not_reached(); | |
5289 | } | |
5290 | ||
5291 | float32 HELPER(recpe_f32)(float32 input, void *fpstp) | |
5292 | { | |
5293 | float_status *fpst = fpstp; | |
5294 | float32 f32 = float32_squash_input_denormal(input, fpst); | |
5295 | uint32_t f32_val = float32_val(f32); | |
5296 | uint32_t f32_sbit = 0x80000000ULL & f32_val; | |
5297 | int32_t f32_exp = extract32(f32_val, 23, 8); | |
5298 | uint32_t f32_frac = extract32(f32_val, 0, 23); | |
5299 | float64 f64, r64; | |
5300 | uint64_t r64_val; | |
5301 | int64_t r64_exp; | |
5302 | uint64_t r64_frac; | |
5303 | ||
5304 | if (float32_is_any_nan(f32)) { | |
5305 | float32 nan = f32; | |
5306 | if (float32_is_signaling_nan(f32)) { | |
5307 | float_raise(float_flag_invalid, fpst); | |
5308 | nan = float32_maybe_silence_nan(f32); | |
fe0e4872 | 5309 | } |
b6d4443a AB |
5310 | if (fpst->default_nan_mode) { |
5311 | nan = float32_default_nan; | |
43fe9bdb | 5312 | } |
b6d4443a AB |
5313 | return nan; |
5314 | } else if (float32_is_infinity(f32)) { | |
5315 | return float32_set_sign(float32_zero, float32_is_neg(f32)); | |
5316 | } else if (float32_is_zero(f32)) { | |
5317 | float_raise(float_flag_divbyzero, fpst); | |
5318 | return float32_set_sign(float32_infinity, float32_is_neg(f32)); | |
5319 | } else if ((f32_val & ~(1ULL << 31)) < (1ULL << 21)) { | |
5320 | /* Abs(value) < 2.0^-128 */ | |
5321 | float_raise(float_flag_overflow | float_flag_inexact, fpst); | |
5322 | if (round_to_inf(fpst, f32_sbit)) { | |
5323 | return float32_set_sign(float32_infinity, float32_is_neg(f32)); | |
5324 | } else { | |
5325 | return float32_set_sign(float32_maxnorm, float32_is_neg(f32)); | |
5326 | } | |
5327 | } else if (f32_exp >= 253 && fpst->flush_to_zero) { | |
5328 | float_raise(float_flag_underflow, fpst); | |
5329 | return float32_set_sign(float32_zero, float32_is_neg(f32)); | |
fe0e4872 CL |
5330 | } |
5331 | ||
fe0e4872 | 5332 | |
b6d4443a AB |
5333 | f64 = make_float64(((int64_t)(f32_exp) << 52) | (int64_t)(f32_frac) << 29); |
5334 | r64 = call_recip_estimate(f64, 253, fpst); | |
5335 | r64_val = float64_val(r64); | |
5336 | r64_exp = extract64(r64_val, 52, 11); | |
5337 | r64_frac = extract64(r64_val, 0, 52); | |
5338 | ||
5339 | /* result = sign : result_exp<7:0> : fraction<51:29>; */ | |
5340 | return make_float32(f32_sbit | | |
5341 | (r64_exp & 0xff) << 23 | | |
5342 | extract64(r64_frac, 29, 24)); | |
5343 | } | |
5344 | ||
5345 | float64 HELPER(recpe_f64)(float64 input, void *fpstp) | |
5346 | { | |
5347 | float_status *fpst = fpstp; | |
5348 | float64 f64 = float64_squash_input_denormal(input, fpst); | |
5349 | uint64_t f64_val = float64_val(f64); | |
5350 | uint64_t f64_sbit = 0x8000000000000000ULL & f64_val; | |
5351 | int64_t f64_exp = extract64(f64_val, 52, 11); | |
5352 | float64 r64; | |
5353 | uint64_t r64_val; | |
5354 | int64_t r64_exp; | |
5355 | uint64_t r64_frac; | |
5356 | ||
5357 | /* Deal with any special cases */ | |
5358 | if (float64_is_any_nan(f64)) { | |
5359 | float64 nan = f64; | |
5360 | if (float64_is_signaling_nan(f64)) { | |
5361 | float_raise(float_flag_invalid, fpst); | |
5362 | nan = float64_maybe_silence_nan(f64); | |
5363 | } | |
5364 | if (fpst->default_nan_mode) { | |
5365 | nan = float64_default_nan; | |
5366 | } | |
5367 | return nan; | |
5368 | } else if (float64_is_infinity(f64)) { | |
5369 | return float64_set_sign(float64_zero, float64_is_neg(f64)); | |
5370 | } else if (float64_is_zero(f64)) { | |
5371 | float_raise(float_flag_divbyzero, fpst); | |
5372 | return float64_set_sign(float64_infinity, float64_is_neg(f64)); | |
5373 | } else if ((f64_val & ~(1ULL << 63)) < (1ULL << 50)) { | |
5374 | /* Abs(value) < 2.0^-1024 */ | |
5375 | float_raise(float_flag_overflow | float_flag_inexact, fpst); | |
5376 | if (round_to_inf(fpst, f64_sbit)) { | |
5377 | return float64_set_sign(float64_infinity, float64_is_neg(f64)); | |
5378 | } else { | |
5379 | return float64_set_sign(float64_maxnorm, float64_is_neg(f64)); | |
5380 | } | |
5381 | } else if (f64_exp >= 1023 && fpst->flush_to_zero) { | |
5382 | float_raise(float_flag_underflow, fpst); | |
5383 | return float64_set_sign(float64_zero, float64_is_neg(f64)); | |
5384 | } | |
fe0e4872 | 5385 | |
b6d4443a AB |
5386 | r64 = call_recip_estimate(f64, 2045, fpst); |
5387 | r64_val = float64_val(r64); | |
5388 | r64_exp = extract64(r64_val, 52, 11); | |
5389 | r64_frac = extract64(r64_val, 0, 52); | |
fe0e4872 | 5390 | |
b6d4443a AB |
5391 | /* result = sign : result_exp<10:0> : fraction<51:0> */ |
5392 | return make_float64(f64_sbit | | |
5393 | ((r64_exp & 0x7ff) << 52) | | |
5394 | r64_frac); | |
4373f3ce PB |
5395 | } |
5396 | ||
e07be5d2 CL |
5397 | /* The algorithm that must be used to calculate the estimate |
5398 | * is specified by the ARM ARM. | |
5399 | */ | |
c2fb418e | 5400 | static float64 recip_sqrt_estimate(float64 a, float_status *real_fp_status) |
e07be5d2 | 5401 | { |
1146a817 PM |
5402 | /* These calculations mustn't set any fp exception flags, |
5403 | * so we use a local copy of the fp_status. | |
5404 | */ | |
c2fb418e | 5405 | float_status dummy_status = *real_fp_status; |
1146a817 | 5406 | float_status *s = &dummy_status; |
e07be5d2 CL |
5407 | float64 q; |
5408 | int64_t q_int; | |
5409 | ||
5410 | if (float64_lt(a, float64_half, s)) { | |
5411 | /* range 0.25 <= a < 0.5 */ | |
5412 | ||
5413 | /* a in units of 1/512 rounded down */ | |
5414 | /* q0 = (int)(a * 512.0); */ | |
5415 | q = float64_mul(float64_512, a, s); | |
5416 | q_int = float64_to_int64_round_to_zero(q, s); | |
5417 | ||
5418 | /* reciprocal root r */ | |
5419 | /* r = 1.0 / sqrt(((double)q0 + 0.5) / 512.0); */ | |
5420 | q = int64_to_float64(q_int, s); | |
5421 | q = float64_add(q, float64_half, s); | |
5422 | q = float64_div(q, float64_512, s); | |
5423 | q = float64_sqrt(q, s); | |
5424 | q = float64_div(float64_one, q, s); | |
5425 | } else { | |
5426 | /* range 0.5 <= a < 1.0 */ | |
5427 | ||
5428 | /* a in units of 1/256 rounded down */ | |
5429 | /* q1 = (int)(a * 256.0); */ | |
5430 | q = float64_mul(float64_256, a, s); | |
5431 | int64_t q_int = float64_to_int64_round_to_zero(q, s); | |
5432 | ||
5433 | /* reciprocal root r */ | |
5434 | /* r = 1.0 /sqrt(((double)q1 + 0.5) / 256); */ | |
5435 | q = int64_to_float64(q_int, s); | |
5436 | q = float64_add(q, float64_half, s); | |
5437 | q = float64_div(q, float64_256, s); | |
5438 | q = float64_sqrt(q, s); | |
5439 | q = float64_div(float64_one, q, s); | |
5440 | } | |
5441 | /* r in units of 1/256 rounded to nearest */ | |
5442 | /* s = (int)(256.0 * r + 0.5); */ | |
5443 | ||
5444 | q = float64_mul(q, float64_256,s ); | |
5445 | q = float64_add(q, float64_half, s); | |
5446 | q_int = float64_to_int64_round_to_zero(q, s); | |
5447 | ||
5448 | /* return (double)s / 256.0;*/ | |
5449 | return float64_div(int64_to_float64(q_int, s), float64_256, s); | |
5450 | } | |
5451 | ||
c2fb418e | 5452 | float32 HELPER(rsqrte_f32)(float32 input, void *fpstp) |
4373f3ce | 5453 | { |
c2fb418e AB |
5454 | float_status *s = fpstp; |
5455 | float32 f32 = float32_squash_input_denormal(input, s); | |
5456 | uint32_t val = float32_val(f32); | |
5457 | uint32_t f32_sbit = 0x80000000 & val; | |
5458 | int32_t f32_exp = extract32(val, 23, 8); | |
5459 | uint32_t f32_frac = extract32(val, 0, 23); | |
5460 | uint64_t f64_frac; | |
5461 | uint64_t val64; | |
e07be5d2 CL |
5462 | int result_exp; |
5463 | float64 f64; | |
e07be5d2 | 5464 | |
c2fb418e AB |
5465 | if (float32_is_any_nan(f32)) { |
5466 | float32 nan = f32; | |
5467 | if (float32_is_signaling_nan(f32)) { | |
e07be5d2 | 5468 | float_raise(float_flag_invalid, s); |
c2fb418e | 5469 | nan = float32_maybe_silence_nan(f32); |
e07be5d2 | 5470 | } |
c2fb418e AB |
5471 | if (s->default_nan_mode) { |
5472 | nan = float32_default_nan; | |
43fe9bdb | 5473 | } |
c2fb418e AB |
5474 | return nan; |
5475 | } else if (float32_is_zero(f32)) { | |
e07be5d2 | 5476 | float_raise(float_flag_divbyzero, s); |
c2fb418e AB |
5477 | return float32_set_sign(float32_infinity, float32_is_neg(f32)); |
5478 | } else if (float32_is_neg(f32)) { | |
e07be5d2 CL |
5479 | float_raise(float_flag_invalid, s); |
5480 | return float32_default_nan; | |
c2fb418e | 5481 | } else if (float32_is_infinity(f32)) { |
e07be5d2 CL |
5482 | return float32_zero; |
5483 | } | |
5484 | ||
c2fb418e | 5485 | /* Scale and normalize to a double-precision value between 0.25 and 1.0, |
e07be5d2 | 5486 | * preserving the parity of the exponent. */ |
c2fb418e AB |
5487 | |
5488 | f64_frac = ((uint64_t) f32_frac) << 29; | |
5489 | if (f32_exp == 0) { | |
5490 | while (extract64(f64_frac, 51, 1) == 0) { | |
5491 | f64_frac = f64_frac << 1; | |
5492 | f32_exp = f32_exp-1; | |
5493 | } | |
5494 | f64_frac = extract64(f64_frac, 0, 51) << 1; | |
5495 | } | |
5496 | ||
5497 | if (extract64(f32_exp, 0, 1) == 0) { | |
5498 | f64 = make_float64(((uint64_t) f32_sbit) << 32 | |
e07be5d2 | 5499 | | (0x3feULL << 52) |
c2fb418e | 5500 | | f64_frac); |
e07be5d2 | 5501 | } else { |
c2fb418e | 5502 | f64 = make_float64(((uint64_t) f32_sbit) << 32 |
e07be5d2 | 5503 | | (0x3fdULL << 52) |
c2fb418e | 5504 | | f64_frac); |
e07be5d2 CL |
5505 | } |
5506 | ||
c2fb418e | 5507 | result_exp = (380 - f32_exp) / 2; |
e07be5d2 | 5508 | |
c2fb418e | 5509 | f64 = recip_sqrt_estimate(f64, s); |
e07be5d2 CL |
5510 | |
5511 | val64 = float64_val(f64); | |
5512 | ||
26cc6abf | 5513 | val = ((result_exp & 0xff) << 23) |
e07be5d2 CL |
5514 | | ((val64 >> 29) & 0x7fffff); |
5515 | return make_float32(val); | |
4373f3ce PB |
5516 | } |
5517 | ||
c2fb418e AB |
5518 | float64 HELPER(rsqrte_f64)(float64 input, void *fpstp) |
5519 | { | |
5520 | float_status *s = fpstp; | |
5521 | float64 f64 = float64_squash_input_denormal(input, s); | |
5522 | uint64_t val = float64_val(f64); | |
5523 | uint64_t f64_sbit = 0x8000000000000000ULL & val; | |
5524 | int64_t f64_exp = extract64(val, 52, 11); | |
5525 | uint64_t f64_frac = extract64(val, 0, 52); | |
5526 | int64_t result_exp; | |
5527 | uint64_t result_frac; | |
5528 | ||
5529 | if (float64_is_any_nan(f64)) { | |
5530 | float64 nan = f64; | |
5531 | if (float64_is_signaling_nan(f64)) { | |
5532 | float_raise(float_flag_invalid, s); | |
5533 | nan = float64_maybe_silence_nan(f64); | |
5534 | } | |
5535 | if (s->default_nan_mode) { | |
5536 | nan = float64_default_nan; | |
5537 | } | |
5538 | return nan; | |
5539 | } else if (float64_is_zero(f64)) { | |
5540 | float_raise(float_flag_divbyzero, s); | |
5541 | return float64_set_sign(float64_infinity, float64_is_neg(f64)); | |
5542 | } else if (float64_is_neg(f64)) { | |
5543 | float_raise(float_flag_invalid, s); | |
5544 | return float64_default_nan; | |
5545 | } else if (float64_is_infinity(f64)) { | |
5546 | return float64_zero; | |
5547 | } | |
5548 | ||
5549 | /* Scale and normalize to a double-precision value between 0.25 and 1.0, | |
5550 | * preserving the parity of the exponent. */ | |
5551 | ||
5552 | if (f64_exp == 0) { | |
5553 | while (extract64(f64_frac, 51, 1) == 0) { | |
5554 | f64_frac = f64_frac << 1; | |
5555 | f64_exp = f64_exp - 1; | |
5556 | } | |
5557 | f64_frac = extract64(f64_frac, 0, 51) << 1; | |
5558 | } | |
5559 | ||
5560 | if (extract64(f64_exp, 0, 1) == 0) { | |
5561 | f64 = make_float64(f64_sbit | |
5562 | | (0x3feULL << 52) | |
5563 | | f64_frac); | |
5564 | } else { | |
5565 | f64 = make_float64(f64_sbit | |
5566 | | (0x3fdULL << 52) | |
5567 | | f64_frac); | |
5568 | } | |
5569 | ||
5570 | result_exp = (3068 - f64_exp) / 2; | |
5571 | ||
5572 | f64 = recip_sqrt_estimate(f64, s); | |
5573 | ||
5574 | result_frac = extract64(float64_val(f64), 0, 52); | |
5575 | ||
5576 | return make_float64(f64_sbit | | |
5577 | ((result_exp & 0x7ff) << 52) | | |
5578 | result_frac); | |
5579 | } | |
5580 | ||
b6d4443a | 5581 | uint32_t HELPER(recpe_u32)(uint32_t a, void *fpstp) |
4373f3ce | 5582 | { |
b6d4443a | 5583 | float_status *s = fpstp; |
fe0e4872 CL |
5584 | float64 f64; |
5585 | ||
5586 | if ((a & 0x80000000) == 0) { | |
5587 | return 0xffffffff; | |
5588 | } | |
5589 | ||
5590 | f64 = make_float64((0x3feULL << 52) | |
5591 | | ((int64_t)(a & 0x7fffffff) << 21)); | |
5592 | ||
b6d4443a | 5593 | f64 = recip_estimate(f64, s); |
fe0e4872 CL |
5594 | |
5595 | return 0x80000000 | ((float64_val(f64) >> 21) & 0x7fffffff); | |
4373f3ce PB |
5596 | } |
5597 | ||
c2fb418e | 5598 | uint32_t HELPER(rsqrte_u32)(uint32_t a, void *fpstp) |
4373f3ce | 5599 | { |
c2fb418e | 5600 | float_status *fpst = fpstp; |
e07be5d2 CL |
5601 | float64 f64; |
5602 | ||
5603 | if ((a & 0xc0000000) == 0) { | |
5604 | return 0xffffffff; | |
5605 | } | |
5606 | ||
5607 | if (a & 0x80000000) { | |
5608 | f64 = make_float64((0x3feULL << 52) | |
5609 | | ((uint64_t)(a & 0x7fffffff) << 21)); | |
5610 | } else { /* bits 31-30 == '01' */ | |
5611 | f64 = make_float64((0x3fdULL << 52) | |
5612 | | ((uint64_t)(a & 0x3fffffff) << 22)); | |
5613 | } | |
5614 | ||
c2fb418e | 5615 | f64 = recip_sqrt_estimate(f64, fpst); |
e07be5d2 CL |
5616 | |
5617 | return 0x80000000 | ((float64_val(f64) >> 21) & 0x7fffffff); | |
4373f3ce | 5618 | } |
fe1479c3 | 5619 | |
da97f52c PM |
5620 | /* VFPv4 fused multiply-accumulate */ |
5621 | float32 VFP_HELPER(muladd, s)(float32 a, float32 b, float32 c, void *fpstp) | |
5622 | { | |
5623 | float_status *fpst = fpstp; | |
5624 | return float32_muladd(a, b, c, 0, fpst); | |
5625 | } | |
5626 | ||
5627 | float64 VFP_HELPER(muladd, d)(float64 a, float64 b, float64 c, void *fpstp) | |
5628 | { | |
5629 | float_status *fpst = fpstp; | |
5630 | return float64_muladd(a, b, c, 0, fpst); | |
5631 | } | |
d9b0848d PM |
5632 | |
5633 | /* ARMv8 round to integral */ | |
5634 | float32 HELPER(rints_exact)(float32 x, void *fp_status) | |
5635 | { | |
5636 | return float32_round_to_int(x, fp_status); | |
5637 | } | |
5638 | ||
5639 | float64 HELPER(rintd_exact)(float64 x, void *fp_status) | |
5640 | { | |
5641 | return float64_round_to_int(x, fp_status); | |
5642 | } | |
5643 | ||
5644 | float32 HELPER(rints)(float32 x, void *fp_status) | |
5645 | { | |
5646 | int old_flags = get_float_exception_flags(fp_status), new_flags; | |
5647 | float32 ret; | |
5648 | ||
5649 | ret = float32_round_to_int(x, fp_status); | |
5650 | ||
5651 | /* Suppress any inexact exceptions the conversion produced */ | |
5652 | if (!(old_flags & float_flag_inexact)) { | |
5653 | new_flags = get_float_exception_flags(fp_status); | |
5654 | set_float_exception_flags(new_flags & ~float_flag_inexact, fp_status); | |
5655 | } | |
5656 | ||
5657 | return ret; | |
5658 | } | |
5659 | ||
5660 | float64 HELPER(rintd)(float64 x, void *fp_status) | |
5661 | { | |
5662 | int old_flags = get_float_exception_flags(fp_status), new_flags; | |
5663 | float64 ret; | |
5664 | ||
5665 | ret = float64_round_to_int(x, fp_status); | |
5666 | ||
5667 | new_flags = get_float_exception_flags(fp_status); | |
5668 | ||
5669 | /* Suppress any inexact exceptions the conversion produced */ | |
5670 | if (!(old_flags & float_flag_inexact)) { | |
5671 | new_flags = get_float_exception_flags(fp_status); | |
5672 | set_float_exception_flags(new_flags & ~float_flag_inexact, fp_status); | |
5673 | } | |
5674 | ||
5675 | return ret; | |
5676 | } | |
9972da66 WN |
5677 | |
5678 | /* Convert ARM rounding mode to softfloat */ | |
5679 | int arm_rmode_to_sf(int rmode) | |
5680 | { | |
5681 | switch (rmode) { | |
5682 | case FPROUNDING_TIEAWAY: | |
5683 | rmode = float_round_ties_away; | |
5684 | break; | |
5685 | case FPROUNDING_ODD: | |
5686 | /* FIXME: add support for TIEAWAY and ODD */ | |
5687 | qemu_log_mask(LOG_UNIMP, "arm: unimplemented rounding mode: %d\n", | |
5688 | rmode); | |
5689 | case FPROUNDING_TIEEVEN: | |
5690 | default: | |
5691 | rmode = float_round_nearest_even; | |
5692 | break; | |
5693 | case FPROUNDING_POSINF: | |
5694 | rmode = float_round_up; | |
5695 | break; | |
5696 | case FPROUNDING_NEGINF: | |
5697 | rmode = float_round_down; | |
5698 | break; | |
5699 | case FPROUNDING_ZERO: | |
5700 | rmode = float_round_to_zero; | |
5701 | break; | |
5702 | } | |
5703 | return rmode; | |
5704 | } | |
eb0ecd5a | 5705 | |
aa633469 PM |
5706 | /* CRC helpers. |
5707 | * The upper bytes of val (above the number specified by 'bytes') must have | |
5708 | * been zeroed out by the caller. | |
5709 | */ | |
eb0ecd5a WN |
5710 | uint32_t HELPER(crc32)(uint32_t acc, uint32_t val, uint32_t bytes) |
5711 | { | |
5712 | uint8_t buf[4]; | |
5713 | ||
aa633469 | 5714 | stl_le_p(buf, val); |
eb0ecd5a WN |
5715 | |
5716 | /* zlib crc32 converts the accumulator and output to one's complement. */ | |
5717 | return crc32(acc ^ 0xffffffff, buf, bytes) ^ 0xffffffff; | |
5718 | } | |
5719 | ||
5720 | uint32_t HELPER(crc32c)(uint32_t acc, uint32_t val, uint32_t bytes) | |
5721 | { | |
5722 | uint8_t buf[4]; | |
5723 | ||
aa633469 | 5724 | stl_le_p(buf, val); |
eb0ecd5a WN |
5725 | |
5726 | /* Linux crc32c converts the output to one's complement. */ | |
5727 | return crc32c(acc, buf, bytes) ^ 0xffffffff; | |
5728 | } |