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Commit | Line | Data |
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b5ff1b31 | 1 | #include "cpu.h" |
022c62cb | 2 | #include "exec/gdbstub.h" |
7b59220e | 3 | #include "helper.h" |
1de7afc9 | 4 | #include "qemu/host-utils.h" |
78027bb6 | 5 | #include "sysemu/arch_init.h" |
9c17d615 | 6 | #include "sysemu/sysemu.h" |
1de7afc9 | 7 | #include "qemu/bitops.h" |
0b03bdfc | 8 | |
4a501606 PM |
9 | #ifndef CONFIG_USER_ONLY |
10 | static inline int get_phys_addr(CPUARMState *env, uint32_t address, | |
11 | int access_type, int is_user, | |
a8170e5e | 12 | hwaddr *phys_ptr, int *prot, |
4a501606 PM |
13 | target_ulong *page_size); |
14 | #endif | |
15 | ||
0ecb72a5 | 16 | static int vfp_gdb_get_reg(CPUARMState *env, uint8_t *buf, int reg) |
56aebc89 PB |
17 | { |
18 | int nregs; | |
19 | ||
20 | /* VFP data registers are always little-endian. */ | |
21 | nregs = arm_feature(env, ARM_FEATURE_VFP3) ? 32 : 16; | |
22 | if (reg < nregs) { | |
23 | stfq_le_p(buf, env->vfp.regs[reg]); | |
24 | return 8; | |
25 | } | |
26 | if (arm_feature(env, ARM_FEATURE_NEON)) { | |
27 | /* Aliases for Q regs. */ | |
28 | nregs += 16; | |
29 | if (reg < nregs) { | |
30 | stfq_le_p(buf, env->vfp.regs[(reg - 32) * 2]); | |
31 | stfq_le_p(buf + 8, env->vfp.regs[(reg - 32) * 2 + 1]); | |
32 | return 16; | |
33 | } | |
34 | } | |
35 | switch (reg - nregs) { | |
36 | case 0: stl_p(buf, env->vfp.xregs[ARM_VFP_FPSID]); return 4; | |
37 | case 1: stl_p(buf, env->vfp.xregs[ARM_VFP_FPSCR]); return 4; | |
38 | case 2: stl_p(buf, env->vfp.xregs[ARM_VFP_FPEXC]); return 4; | |
39 | } | |
40 | return 0; | |
41 | } | |
42 | ||
0ecb72a5 | 43 | static int vfp_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg) |
56aebc89 PB |
44 | { |
45 | int nregs; | |
46 | ||
47 | nregs = arm_feature(env, ARM_FEATURE_VFP3) ? 32 : 16; | |
48 | if (reg < nregs) { | |
49 | env->vfp.regs[reg] = ldfq_le_p(buf); | |
50 | return 8; | |
51 | } | |
52 | if (arm_feature(env, ARM_FEATURE_NEON)) { | |
53 | nregs += 16; | |
54 | if (reg < nregs) { | |
55 | env->vfp.regs[(reg - 32) * 2] = ldfq_le_p(buf); | |
56 | env->vfp.regs[(reg - 32) * 2 + 1] = ldfq_le_p(buf + 8); | |
57 | return 16; | |
58 | } | |
59 | } | |
60 | switch (reg - nregs) { | |
61 | case 0: env->vfp.xregs[ARM_VFP_FPSID] = ldl_p(buf); return 4; | |
62 | case 1: env->vfp.xregs[ARM_VFP_FPSCR] = ldl_p(buf); return 4; | |
71b3c3de | 63 | case 2: env->vfp.xregs[ARM_VFP_FPEXC] = ldl_p(buf) & (1 << 30); return 4; |
56aebc89 PB |
64 | } |
65 | return 0; | |
66 | } | |
67 | ||
6a669427 PM |
68 | static int aarch64_fpu_gdb_get_reg(CPUARMState *env, uint8_t *buf, int reg) |
69 | { | |
70 | switch (reg) { | |
71 | case 0 ... 31: | |
72 | /* 128 bit FP register */ | |
73 | stfq_le_p(buf, env->vfp.regs[reg * 2]); | |
74 | stfq_le_p(buf + 8, env->vfp.regs[reg * 2 + 1]); | |
75 | return 16; | |
76 | case 32: | |
77 | /* FPSR */ | |
78 | stl_p(buf, vfp_get_fpsr(env)); | |
79 | return 4; | |
80 | case 33: | |
81 | /* FPCR */ | |
82 | stl_p(buf, vfp_get_fpcr(env)); | |
83 | return 4; | |
84 | default: | |
85 | return 0; | |
86 | } | |
87 | } | |
88 | ||
89 | static int aarch64_fpu_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg) | |
90 | { | |
91 | switch (reg) { | |
92 | case 0 ... 31: | |
93 | /* 128 bit FP register */ | |
94 | env->vfp.regs[reg * 2] = ldfq_le_p(buf); | |
95 | env->vfp.regs[reg * 2 + 1] = ldfq_le_p(buf + 8); | |
96 | return 16; | |
97 | case 32: | |
98 | /* FPSR */ | |
99 | vfp_set_fpsr(env, ldl_p(buf)); | |
100 | return 4; | |
101 | case 33: | |
102 | /* FPCR */ | |
103 | vfp_set_fpcr(env, ldl_p(buf)); | |
104 | return 4; | |
105 | default: | |
106 | return 0; | |
107 | } | |
108 | } | |
109 | ||
c4241c7d | 110 | static uint64_t raw_read(CPUARMState *env, const ARMCPRegInfo *ri) |
d4e6df63 | 111 | { |
22d9e1a9 | 112 | if (ri->type & ARM_CP_64BIT) { |
c4241c7d | 113 | return CPREG_FIELD64(env, ri); |
22d9e1a9 | 114 | } else { |
c4241c7d | 115 | return CPREG_FIELD32(env, ri); |
22d9e1a9 | 116 | } |
d4e6df63 PM |
117 | } |
118 | ||
c4241c7d PM |
119 | static void raw_write(CPUARMState *env, const ARMCPRegInfo *ri, |
120 | uint64_t value) | |
d4e6df63 | 121 | { |
22d9e1a9 PM |
122 | if (ri->type & ARM_CP_64BIT) { |
123 | CPREG_FIELD64(env, ri) = value; | |
124 | } else { | |
125 | CPREG_FIELD32(env, ri) = value; | |
126 | } | |
d4e6df63 PM |
127 | } |
128 | ||
59a1c327 | 129 | static uint64_t read_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri) |
721fae12 | 130 | { |
59a1c327 | 131 | /* Raw read of a coprocessor register (as needed for migration, etc). */ |
721fae12 | 132 | if (ri->type & ARM_CP_CONST) { |
59a1c327 | 133 | return ri->resetvalue; |
721fae12 | 134 | } else if (ri->raw_readfn) { |
59a1c327 | 135 | return ri->raw_readfn(env, ri); |
721fae12 | 136 | } else if (ri->readfn) { |
59a1c327 | 137 | return ri->readfn(env, ri); |
721fae12 | 138 | } else { |
59a1c327 | 139 | return raw_read(env, ri); |
721fae12 | 140 | } |
721fae12 PM |
141 | } |
142 | ||
59a1c327 | 143 | static void write_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri, |
7900e9f1 | 144 | uint64_t v) |
721fae12 PM |
145 | { |
146 | /* Raw write of a coprocessor register (as needed for migration, etc). | |
721fae12 PM |
147 | * Note that constant registers are treated as write-ignored; the |
148 | * caller should check for success by whether a readback gives the | |
149 | * value written. | |
150 | */ | |
151 | if (ri->type & ARM_CP_CONST) { | |
59a1c327 | 152 | return; |
721fae12 | 153 | } else if (ri->raw_writefn) { |
c4241c7d | 154 | ri->raw_writefn(env, ri, v); |
721fae12 | 155 | } else if (ri->writefn) { |
c4241c7d | 156 | ri->writefn(env, ri, v); |
721fae12 | 157 | } else { |
afb2530f | 158 | raw_write(env, ri, v); |
721fae12 | 159 | } |
721fae12 PM |
160 | } |
161 | ||
162 | bool write_cpustate_to_list(ARMCPU *cpu) | |
163 | { | |
164 | /* Write the coprocessor state from cpu->env to the (index,value) list. */ | |
165 | int i; | |
166 | bool ok = true; | |
167 | ||
168 | for (i = 0; i < cpu->cpreg_array_len; i++) { | |
169 | uint32_t regidx = kvm_to_cpreg_id(cpu->cpreg_indexes[i]); | |
170 | const ARMCPRegInfo *ri; | |
59a1c327 | 171 | |
60322b39 | 172 | ri = get_arm_cp_reginfo(cpu->cp_regs, regidx); |
721fae12 PM |
173 | if (!ri) { |
174 | ok = false; | |
175 | continue; | |
176 | } | |
177 | if (ri->type & ARM_CP_NO_MIGRATE) { | |
178 | continue; | |
179 | } | |
59a1c327 | 180 | cpu->cpreg_values[i] = read_raw_cp_reg(&cpu->env, ri); |
721fae12 PM |
181 | } |
182 | return ok; | |
183 | } | |
184 | ||
185 | bool write_list_to_cpustate(ARMCPU *cpu) | |
186 | { | |
187 | int i; | |
188 | bool ok = true; | |
189 | ||
190 | for (i = 0; i < cpu->cpreg_array_len; i++) { | |
191 | uint32_t regidx = kvm_to_cpreg_id(cpu->cpreg_indexes[i]); | |
192 | uint64_t v = cpu->cpreg_values[i]; | |
721fae12 PM |
193 | const ARMCPRegInfo *ri; |
194 | ||
60322b39 | 195 | ri = get_arm_cp_reginfo(cpu->cp_regs, regidx); |
721fae12 PM |
196 | if (!ri) { |
197 | ok = false; | |
198 | continue; | |
199 | } | |
200 | if (ri->type & ARM_CP_NO_MIGRATE) { | |
201 | continue; | |
202 | } | |
203 | /* Write value and confirm it reads back as written | |
204 | * (to catch read-only registers and partially read-only | |
205 | * registers where the incoming migration value doesn't match) | |
206 | */ | |
59a1c327 PM |
207 | write_raw_cp_reg(&cpu->env, ri, v); |
208 | if (read_raw_cp_reg(&cpu->env, ri) != v) { | |
721fae12 PM |
209 | ok = false; |
210 | } | |
211 | } | |
212 | return ok; | |
213 | } | |
214 | ||
215 | static void add_cpreg_to_list(gpointer key, gpointer opaque) | |
216 | { | |
217 | ARMCPU *cpu = opaque; | |
218 | uint64_t regidx; | |
219 | const ARMCPRegInfo *ri; | |
220 | ||
221 | regidx = *(uint32_t *)key; | |
60322b39 | 222 | ri = get_arm_cp_reginfo(cpu->cp_regs, regidx); |
721fae12 PM |
223 | |
224 | if (!(ri->type & ARM_CP_NO_MIGRATE)) { | |
225 | cpu->cpreg_indexes[cpu->cpreg_array_len] = cpreg_to_kvm_id(regidx); | |
226 | /* The value array need not be initialized at this point */ | |
227 | cpu->cpreg_array_len++; | |
228 | } | |
229 | } | |
230 | ||
231 | static void count_cpreg(gpointer key, gpointer opaque) | |
232 | { | |
233 | ARMCPU *cpu = opaque; | |
234 | uint64_t regidx; | |
235 | const ARMCPRegInfo *ri; | |
236 | ||
237 | regidx = *(uint32_t *)key; | |
60322b39 | 238 | ri = get_arm_cp_reginfo(cpu->cp_regs, regidx); |
721fae12 PM |
239 | |
240 | if (!(ri->type & ARM_CP_NO_MIGRATE)) { | |
241 | cpu->cpreg_array_len++; | |
242 | } | |
243 | } | |
244 | ||
245 | static gint cpreg_key_compare(gconstpointer a, gconstpointer b) | |
246 | { | |
cbf239b7 AR |
247 | uint64_t aidx = cpreg_to_kvm_id(*(uint32_t *)a); |
248 | uint64_t bidx = cpreg_to_kvm_id(*(uint32_t *)b); | |
721fae12 | 249 | |
cbf239b7 AR |
250 | if (aidx > bidx) { |
251 | return 1; | |
252 | } | |
253 | if (aidx < bidx) { | |
254 | return -1; | |
255 | } | |
256 | return 0; | |
721fae12 PM |
257 | } |
258 | ||
82a3a118 PM |
259 | static void cpreg_make_keylist(gpointer key, gpointer value, gpointer udata) |
260 | { | |
261 | GList **plist = udata; | |
262 | ||
263 | *plist = g_list_prepend(*plist, key); | |
264 | } | |
265 | ||
721fae12 PM |
266 | void init_cpreg_list(ARMCPU *cpu) |
267 | { | |
268 | /* Initialise the cpreg_tuples[] array based on the cp_regs hash. | |
269 | * Note that we require cpreg_tuples[] to be sorted by key ID. | |
270 | */ | |
82a3a118 | 271 | GList *keys = NULL; |
721fae12 PM |
272 | int arraylen; |
273 | ||
82a3a118 PM |
274 | g_hash_table_foreach(cpu->cp_regs, cpreg_make_keylist, &keys); |
275 | ||
721fae12 PM |
276 | keys = g_list_sort(keys, cpreg_key_compare); |
277 | ||
278 | cpu->cpreg_array_len = 0; | |
279 | ||
280 | g_list_foreach(keys, count_cpreg, cpu); | |
281 | ||
282 | arraylen = cpu->cpreg_array_len; | |
283 | cpu->cpreg_indexes = g_new(uint64_t, arraylen); | |
284 | cpu->cpreg_values = g_new(uint64_t, arraylen); | |
285 | cpu->cpreg_vmstate_indexes = g_new(uint64_t, arraylen); | |
286 | cpu->cpreg_vmstate_values = g_new(uint64_t, arraylen); | |
287 | cpu->cpreg_vmstate_array_len = cpu->cpreg_array_len; | |
288 | cpu->cpreg_array_len = 0; | |
289 | ||
290 | g_list_foreach(keys, add_cpreg_to_list, cpu); | |
291 | ||
292 | assert(cpu->cpreg_array_len == arraylen); | |
293 | ||
294 | g_list_free(keys); | |
295 | } | |
296 | ||
c4241c7d | 297 | static void dacr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) |
c983fe6c PM |
298 | { |
299 | env->cp15.c3 = value; | |
300 | tlb_flush(env, 1); /* Flush TLB as domain not tracked in TLB */ | |
c983fe6c PM |
301 | } |
302 | ||
c4241c7d | 303 | static void fcse_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) |
08de207b PM |
304 | { |
305 | if (env->cp15.c13_fcse != value) { | |
306 | /* Unlike real hardware the qemu TLB uses virtual addresses, | |
307 | * not modified virtual addresses, so this causes a TLB flush. | |
308 | */ | |
309 | tlb_flush(env, 1); | |
310 | env->cp15.c13_fcse = value; | |
311 | } | |
08de207b | 312 | } |
c4241c7d PM |
313 | |
314 | static void contextidr_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
315 | uint64_t value) | |
08de207b PM |
316 | { |
317 | if (env->cp15.c13_context != value && !arm_feature(env, ARM_FEATURE_MPU)) { | |
318 | /* For VMSA (when not using the LPAE long descriptor page table | |
319 | * format) this register includes the ASID, so do a TLB flush. | |
320 | * For PMSA it is purely a process ID and no action is needed. | |
321 | */ | |
322 | tlb_flush(env, 1); | |
323 | } | |
324 | env->cp15.c13_context = value; | |
08de207b PM |
325 | } |
326 | ||
c4241c7d PM |
327 | static void tlbiall_write(CPUARMState *env, const ARMCPRegInfo *ri, |
328 | uint64_t value) | |
d929823f PM |
329 | { |
330 | /* Invalidate all (TLBIALL) */ | |
331 | tlb_flush(env, 1); | |
d929823f PM |
332 | } |
333 | ||
c4241c7d PM |
334 | static void tlbimva_write(CPUARMState *env, const ARMCPRegInfo *ri, |
335 | uint64_t value) | |
d929823f PM |
336 | { |
337 | /* Invalidate single TLB entry by MVA and ASID (TLBIMVA) */ | |
338 | tlb_flush_page(env, value & TARGET_PAGE_MASK); | |
d929823f PM |
339 | } |
340 | ||
c4241c7d PM |
341 | static void tlbiasid_write(CPUARMState *env, const ARMCPRegInfo *ri, |
342 | uint64_t value) | |
d929823f PM |
343 | { |
344 | /* Invalidate by ASID (TLBIASID) */ | |
345 | tlb_flush(env, value == 0); | |
d929823f PM |
346 | } |
347 | ||
c4241c7d PM |
348 | static void tlbimvaa_write(CPUARMState *env, const ARMCPRegInfo *ri, |
349 | uint64_t value) | |
d929823f PM |
350 | { |
351 | /* Invalidate single entry by MVA, all ASIDs (TLBIMVAA) */ | |
352 | tlb_flush_page(env, value & TARGET_PAGE_MASK); | |
d929823f PM |
353 | } |
354 | ||
e9aa6c21 PM |
355 | static const ARMCPRegInfo cp_reginfo[] = { |
356 | /* DBGDIDR: just RAZ. In particular this means the "debug architecture | |
357 | * version" bits will read as a reserved value, which should cause | |
358 | * Linux to not try to use the debug hardware. | |
359 | */ | |
360 | { .name = "DBGDIDR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 0, | |
361 | .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
c983fe6c PM |
362 | /* MMU Domain access control / MPU write buffer control */ |
363 | { .name = "DACR", .cp = 15, | |
364 | .crn = 3, .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY, | |
365 | .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c3), | |
d4e6df63 | 366 | .resetvalue = 0, .writefn = dacr_write, .raw_writefn = raw_write, }, |
08de207b PM |
367 | { .name = "FCSEIDR", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 0, |
368 | .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c13_fcse), | |
d4e6df63 | 369 | .resetvalue = 0, .writefn = fcse_write, .raw_writefn = raw_write, }, |
08de207b | 370 | { .name = "CONTEXTIDR", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 1, |
a4f0cec6 | 371 | .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c13_context), |
d4e6df63 | 372 | .resetvalue = 0, .writefn = contextidr_write, .raw_writefn = raw_write, }, |
4fdd17dd PM |
373 | /* ??? This covers not just the impdef TLB lockdown registers but also |
374 | * some v7VMSA registers relating to TEX remap, so it is overly broad. | |
375 | */ | |
376 | { .name = "TLB_LOCKDOWN", .cp = 15, .crn = 10, .crm = CP_ANY, | |
377 | .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_NOP }, | |
d929823f PM |
378 | /* MMU TLB control. Note that the wildcarding means we cover not just |
379 | * the unified TLB ops but also the dside/iside/inner-shareable variants. | |
380 | */ | |
381 | { .name = "TLBIALL", .cp = 15, .crn = 8, .crm = CP_ANY, | |
d4e6df63 PM |
382 | .opc1 = CP_ANY, .opc2 = 0, .access = PL1_W, .writefn = tlbiall_write, |
383 | .type = ARM_CP_NO_MIGRATE }, | |
d929823f | 384 | { .name = "TLBIMVA", .cp = 15, .crn = 8, .crm = CP_ANY, |
d4e6df63 PM |
385 | .opc1 = CP_ANY, .opc2 = 1, .access = PL1_W, .writefn = tlbimva_write, |
386 | .type = ARM_CP_NO_MIGRATE }, | |
d929823f | 387 | { .name = "TLBIASID", .cp = 15, .crn = 8, .crm = CP_ANY, |
d4e6df63 PM |
388 | .opc1 = CP_ANY, .opc2 = 2, .access = PL1_W, .writefn = tlbiasid_write, |
389 | .type = ARM_CP_NO_MIGRATE }, | |
d929823f | 390 | { .name = "TLBIMVAA", .cp = 15, .crn = 8, .crm = CP_ANY, |
d4e6df63 PM |
391 | .opc1 = CP_ANY, .opc2 = 3, .access = PL1_W, .writefn = tlbimvaa_write, |
392 | .type = ARM_CP_NO_MIGRATE }, | |
c4804214 PM |
393 | /* Cache maintenance ops; some of this space may be overridden later. */ |
394 | { .name = "CACHEMAINT", .cp = 15, .crn = 7, .crm = CP_ANY, | |
395 | .opc1 = 0, .opc2 = CP_ANY, .access = PL1_W, | |
396 | .type = ARM_CP_NOP | ARM_CP_OVERRIDE }, | |
e9aa6c21 PM |
397 | REGINFO_SENTINEL |
398 | }; | |
399 | ||
7d57f408 PM |
400 | static const ARMCPRegInfo not_v6_cp_reginfo[] = { |
401 | /* Not all pre-v6 cores implemented this WFI, so this is slightly | |
402 | * over-broad. | |
403 | */ | |
404 | { .name = "WFI_v5", .cp = 15, .crn = 7, .crm = 8, .opc1 = 0, .opc2 = 2, | |
405 | .access = PL1_W, .type = ARM_CP_WFI }, | |
406 | REGINFO_SENTINEL | |
407 | }; | |
408 | ||
409 | static const ARMCPRegInfo not_v7_cp_reginfo[] = { | |
410 | /* Standard v6 WFI (also used in some pre-v6 cores); not in v7 (which | |
411 | * is UNPREDICTABLE; we choose to NOP as most implementations do). | |
412 | */ | |
413 | { .name = "WFI_v6", .cp = 15, .crn = 7, .crm = 0, .opc1 = 0, .opc2 = 4, | |
414 | .access = PL1_W, .type = ARM_CP_WFI }, | |
34f90529 PM |
415 | /* L1 cache lockdown. Not architectural in v6 and earlier but in practice |
416 | * implemented in 926, 946, 1026, 1136, 1176 and 11MPCore. StrongARM and | |
417 | * OMAPCP will override this space. | |
418 | */ | |
419 | { .name = "DLOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 0, .opc2 = 0, | |
420 | .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_data), | |
421 | .resetvalue = 0 }, | |
422 | { .name = "ILOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 0, .opc2 = 1, | |
423 | .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_insn), | |
424 | .resetvalue = 0 }, | |
776d4e5c PM |
425 | /* v6 doesn't have the cache ID registers but Linux reads them anyway */ |
426 | { .name = "DUMMY", .cp = 15, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = CP_ANY, | |
d4e6df63 PM |
427 | .access = PL1_R, .type = ARM_CP_CONST | ARM_CP_NO_MIGRATE, |
428 | .resetvalue = 0 }, | |
7d57f408 PM |
429 | REGINFO_SENTINEL |
430 | }; | |
431 | ||
c4241c7d PM |
432 | static void cpacr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
433 | uint64_t value) | |
2771db27 PM |
434 | { |
435 | if (env->cp15.c1_coproc != value) { | |
436 | env->cp15.c1_coproc = value; | |
437 | /* ??? Is this safe when called from within a TB? */ | |
438 | tb_flush(env); | |
439 | } | |
2771db27 PM |
440 | } |
441 | ||
7d57f408 PM |
442 | static const ARMCPRegInfo v6_cp_reginfo[] = { |
443 | /* prefetch by MVA in v6, NOP in v7 */ | |
444 | { .name = "MVA_prefetch", | |
445 | .cp = 15, .crn = 7, .crm = 13, .opc1 = 0, .opc2 = 1, | |
446 | .access = PL1_W, .type = ARM_CP_NOP }, | |
447 | { .name = "ISB", .cp = 15, .crn = 7, .crm = 5, .opc1 = 0, .opc2 = 4, | |
448 | .access = PL0_W, .type = ARM_CP_NOP }, | |
091fd17c | 449 | { .name = "DSB", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 4, |
7d57f408 | 450 | .access = PL0_W, .type = ARM_CP_NOP }, |
091fd17c | 451 | { .name = "DMB", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 5, |
7d57f408 | 452 | .access = PL0_W, .type = ARM_CP_NOP }, |
06d76f31 PM |
453 | { .name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 2, |
454 | .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c6_insn), | |
455 | .resetvalue = 0, }, | |
456 | /* Watchpoint Fault Address Register : should actually only be present | |
457 | * for 1136, 1176, 11MPCore. | |
458 | */ | |
459 | { .name = "WFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1, | |
460 | .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0, }, | |
2771db27 PM |
461 | { .name = "CPACR", .cp = 15, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 2, |
462 | .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c1_coproc), | |
463 | .resetvalue = 0, .writefn = cpacr_write }, | |
7d57f408 PM |
464 | REGINFO_SENTINEL |
465 | }; | |
466 | ||
fcd25206 | 467 | static CPAccessResult pmreg_access(CPUARMState *env, const ARMCPRegInfo *ri) |
200ac0ef | 468 | { |
fcd25206 PM |
469 | /* Perfomance monitor registers user accessibility is controlled |
470 | * by PMUSERENR. | |
200ac0ef PM |
471 | */ |
472 | if (arm_current_pl(env) == 0 && !env->cp15.c9_pmuserenr) { | |
fcd25206 | 473 | return CP_ACCESS_TRAP; |
200ac0ef | 474 | } |
fcd25206 | 475 | return CP_ACCESS_OK; |
200ac0ef PM |
476 | } |
477 | ||
c4241c7d PM |
478 | static void pmcr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
479 | uint64_t value) | |
200ac0ef | 480 | { |
200ac0ef PM |
481 | /* only the DP, X, D and E bits are writable */ |
482 | env->cp15.c9_pmcr &= ~0x39; | |
483 | env->cp15.c9_pmcr |= (value & 0x39); | |
200ac0ef PM |
484 | } |
485 | ||
c4241c7d | 486 | static void pmcntenset_write(CPUARMState *env, const ARMCPRegInfo *ri, |
200ac0ef PM |
487 | uint64_t value) |
488 | { | |
200ac0ef PM |
489 | value &= (1 << 31); |
490 | env->cp15.c9_pmcnten |= value; | |
200ac0ef PM |
491 | } |
492 | ||
c4241c7d PM |
493 | static void pmcntenclr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
494 | uint64_t value) | |
200ac0ef | 495 | { |
200ac0ef PM |
496 | value &= (1 << 31); |
497 | env->cp15.c9_pmcnten &= ~value; | |
200ac0ef PM |
498 | } |
499 | ||
c4241c7d PM |
500 | static void pmovsr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
501 | uint64_t value) | |
200ac0ef | 502 | { |
200ac0ef | 503 | env->cp15.c9_pmovsr &= ~value; |
200ac0ef PM |
504 | } |
505 | ||
c4241c7d PM |
506 | static void pmxevtyper_write(CPUARMState *env, const ARMCPRegInfo *ri, |
507 | uint64_t value) | |
200ac0ef | 508 | { |
200ac0ef | 509 | env->cp15.c9_pmxevtyper = value & 0xff; |
200ac0ef PM |
510 | } |
511 | ||
c4241c7d | 512 | static void pmuserenr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
200ac0ef PM |
513 | uint64_t value) |
514 | { | |
515 | env->cp15.c9_pmuserenr = value & 1; | |
200ac0ef PM |
516 | } |
517 | ||
c4241c7d PM |
518 | static void pmintenset_write(CPUARMState *env, const ARMCPRegInfo *ri, |
519 | uint64_t value) | |
200ac0ef PM |
520 | { |
521 | /* We have no event counters so only the C bit can be changed */ | |
522 | value &= (1 << 31); | |
523 | env->cp15.c9_pminten |= value; | |
200ac0ef PM |
524 | } |
525 | ||
c4241c7d PM |
526 | static void pmintenclr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
527 | uint64_t value) | |
200ac0ef PM |
528 | { |
529 | value &= (1 << 31); | |
530 | env->cp15.c9_pminten &= ~value; | |
200ac0ef PM |
531 | } |
532 | ||
c4241c7d PM |
533 | static void vbar_write(CPUARMState *env, const ARMCPRegInfo *ri, |
534 | uint64_t value) | |
8641136c NR |
535 | { |
536 | env->cp15.c12_vbar = value & ~0x1Ful; | |
8641136c NR |
537 | } |
538 | ||
c4241c7d | 539 | static uint64_t ccsidr_read(CPUARMState *env, const ARMCPRegInfo *ri) |
776d4e5c PM |
540 | { |
541 | ARMCPU *cpu = arm_env_get_cpu(env); | |
c4241c7d | 542 | return cpu->ccsidr[env->cp15.c0_cssel]; |
776d4e5c PM |
543 | } |
544 | ||
c4241c7d PM |
545 | static void csselr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
546 | uint64_t value) | |
776d4e5c PM |
547 | { |
548 | env->cp15.c0_cssel = value & 0xf; | |
776d4e5c PM |
549 | } |
550 | ||
e9aa6c21 PM |
551 | static const ARMCPRegInfo v7_cp_reginfo[] = { |
552 | /* DBGDRAR, DBGDSAR: always RAZ since we don't implement memory mapped | |
553 | * debug components | |
554 | */ | |
555 | { .name = "DBGDRAR", .cp = 14, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 0, | |
556 | .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
091fd17c | 557 | { .name = "DBGDSAR", .cp = 14, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 0, |
e9aa6c21 | 558 | .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 }, |
7d57f408 PM |
559 | /* the old v6 WFI, UNPREDICTABLE in v7 but we choose to NOP */ |
560 | { .name = "NOP", .cp = 15, .crn = 7, .crm = 0, .opc1 = 0, .opc2 = 4, | |
561 | .access = PL1_W, .type = ARM_CP_NOP }, | |
200ac0ef PM |
562 | /* Performance monitors are implementation defined in v7, |
563 | * but with an ARM recommended set of registers, which we | |
564 | * follow (although we don't actually implement any counters) | |
565 | * | |
566 | * Performance registers fall into three categories: | |
567 | * (a) always UNDEF in PL0, RW in PL1 (PMINTENSET, PMINTENCLR) | |
568 | * (b) RO in PL0 (ie UNDEF on write), RW in PL1 (PMUSERENR) | |
569 | * (c) UNDEF in PL0 if PMUSERENR.EN==0, otherwise accessible (all others) | |
570 | * For the cases controlled by PMUSERENR we must set .access to PL0_RW | |
571 | * or PL0_RO as appropriate and then check PMUSERENR in the helper fn. | |
572 | */ | |
573 | { .name = "PMCNTENSET", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 1, | |
574 | .access = PL0_RW, .resetvalue = 0, | |
575 | .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcnten), | |
fcd25206 PM |
576 | .writefn = pmcntenset_write, |
577 | .accessfn = pmreg_access, | |
578 | .raw_writefn = raw_write }, | |
200ac0ef PM |
579 | { .name = "PMCNTENCLR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 2, |
580 | .access = PL0_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcnten), | |
fcd25206 PM |
581 | .accessfn = pmreg_access, |
582 | .writefn = pmcntenclr_write, | |
d4e6df63 | 583 | .type = ARM_CP_NO_MIGRATE }, |
200ac0ef PM |
584 | { .name = "PMOVSR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 3, |
585 | .access = PL0_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_pmovsr), | |
fcd25206 PM |
586 | .accessfn = pmreg_access, |
587 | .writefn = pmovsr_write, | |
588 | .raw_writefn = raw_write }, | |
589 | /* Unimplemented so WI. */ | |
200ac0ef | 590 | { .name = "PMSWINC", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 4, |
fcd25206 | 591 | .access = PL0_W, .accessfn = pmreg_access, .type = ARM_CP_NOP }, |
200ac0ef | 592 | /* Since we don't implement any events, writing to PMSELR is UNPREDICTABLE. |
fcd25206 | 593 | * We choose to RAZ/WI. |
200ac0ef PM |
594 | */ |
595 | { .name = "PMSELR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 5, | |
fcd25206 PM |
596 | .access = PL0_RW, .type = ARM_CP_CONST, .resetvalue = 0, |
597 | .accessfn = pmreg_access }, | |
598 | /* Unimplemented, RAZ/WI. */ | |
200ac0ef | 599 | { .name = "PMCCNTR", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 0, |
fcd25206 PM |
600 | .access = PL0_RW, .type = ARM_CP_CONST, .resetvalue = 0, |
601 | .accessfn = pmreg_access }, | |
200ac0ef PM |
602 | { .name = "PMXEVTYPER", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 1, |
603 | .access = PL0_RW, | |
604 | .fieldoffset = offsetof(CPUARMState, cp15.c9_pmxevtyper), | |
fcd25206 PM |
605 | .accessfn = pmreg_access, .writefn = pmxevtyper_write, |
606 | .raw_writefn = raw_write }, | |
607 | /* Unimplemented, RAZ/WI. */ | |
200ac0ef | 608 | { .name = "PMXEVCNTR", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 2, |
fcd25206 PM |
609 | .access = PL0_RW, .type = ARM_CP_CONST, .resetvalue = 0, |
610 | .accessfn = pmreg_access }, | |
200ac0ef PM |
611 | { .name = "PMUSERENR", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 0, |
612 | .access = PL0_R | PL1_RW, | |
613 | .fieldoffset = offsetof(CPUARMState, cp15.c9_pmuserenr), | |
614 | .resetvalue = 0, | |
d4e6df63 | 615 | .writefn = pmuserenr_write, .raw_writefn = raw_write }, |
200ac0ef PM |
616 | { .name = "PMINTENSET", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 1, |
617 | .access = PL1_RW, | |
618 | .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten), | |
619 | .resetvalue = 0, | |
d4e6df63 | 620 | .writefn = pmintenset_write, .raw_writefn = raw_write }, |
200ac0ef | 621 | { .name = "PMINTENCLR", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 2, |
d4e6df63 | 622 | .access = PL1_RW, .type = ARM_CP_NO_MIGRATE, |
200ac0ef | 623 | .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten), |
d4e6df63 | 624 | .resetvalue = 0, .writefn = pmintenclr_write, }, |
8641136c NR |
625 | { .name = "VBAR", .cp = 15, .crn = 12, .crm = 0, .opc1 = 0, .opc2 = 0, |
626 | .access = PL1_RW, .writefn = vbar_write, | |
627 | .fieldoffset = offsetof(CPUARMState, cp15.c12_vbar), | |
628 | .resetvalue = 0 }, | |
2771db27 PM |
629 | { .name = "SCR", .cp = 15, .crn = 1, .crm = 1, .opc1 = 0, .opc2 = 0, |
630 | .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c1_scr), | |
631 | .resetvalue = 0, }, | |
776d4e5c | 632 | { .name = "CCSIDR", .cp = 15, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 0, |
d4e6df63 | 633 | .access = PL1_R, .readfn = ccsidr_read, .type = ARM_CP_NO_MIGRATE }, |
776d4e5c PM |
634 | { .name = "CSSELR", .cp = 15, .crn = 0, .crm = 0, .opc1 = 2, .opc2 = 0, |
635 | .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c0_cssel), | |
636 | .writefn = csselr_write, .resetvalue = 0 }, | |
637 | /* Auxiliary ID register: this actually has an IMPDEF value but for now | |
638 | * just RAZ for all cores: | |
639 | */ | |
640 | { .name = "AIDR", .cp = 15, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 7, | |
641 | .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
e9aa6c21 PM |
642 | REGINFO_SENTINEL |
643 | }; | |
644 | ||
c4241c7d PM |
645 | static void teecr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
646 | uint64_t value) | |
c326b979 PM |
647 | { |
648 | value &= 1; | |
649 | env->teecr = value; | |
c326b979 PM |
650 | } |
651 | ||
c4241c7d | 652 | static CPAccessResult teehbr_access(CPUARMState *env, const ARMCPRegInfo *ri) |
c326b979 | 653 | { |
c326b979 | 654 | if (arm_current_pl(env) == 0 && (env->teecr & 1)) { |
92611c00 | 655 | return CP_ACCESS_TRAP; |
c326b979 | 656 | } |
92611c00 | 657 | return CP_ACCESS_OK; |
c326b979 PM |
658 | } |
659 | ||
660 | static const ARMCPRegInfo t2ee_cp_reginfo[] = { | |
661 | { .name = "TEECR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 6, .opc2 = 0, | |
662 | .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, teecr), | |
663 | .resetvalue = 0, | |
664 | .writefn = teecr_write }, | |
665 | { .name = "TEEHBR", .cp = 14, .crn = 1, .crm = 0, .opc1 = 6, .opc2 = 0, | |
666 | .access = PL0_RW, .fieldoffset = offsetof(CPUARMState, teehbr), | |
92611c00 | 667 | .accessfn = teehbr_access, .resetvalue = 0 }, |
c326b979 PM |
668 | REGINFO_SENTINEL |
669 | }; | |
670 | ||
4d31c596 | 671 | static const ARMCPRegInfo v6k_cp_reginfo[] = { |
e4fe830b PM |
672 | { .name = "TPIDR_EL0", .state = ARM_CP_STATE_AA64, |
673 | .opc0 = 3, .opc1 = 3, .opc2 = 2, .crn = 13, .crm = 0, | |
674 | .access = PL0_RW, | |
675 | .fieldoffset = offsetof(CPUARMState, cp15.tpidr_el0), .resetvalue = 0 }, | |
4d31c596 PM |
676 | { .name = "TPIDRURW", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 2, |
677 | .access = PL0_RW, | |
e4fe830b PM |
678 | .fieldoffset = offsetoflow32(CPUARMState, cp15.tpidr_el0), |
679 | .resetfn = arm_cp_reset_ignore }, | |
680 | { .name = "TPIDRRO_EL0", .state = ARM_CP_STATE_AA64, | |
681 | .opc0 = 3, .opc1 = 3, .opc2 = 3, .crn = 13, .crm = 0, | |
682 | .access = PL0_R|PL1_W, | |
683 | .fieldoffset = offsetof(CPUARMState, cp15.tpidrro_el0), .resetvalue = 0 }, | |
4d31c596 PM |
684 | { .name = "TPIDRURO", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 3, |
685 | .access = PL0_R|PL1_W, | |
e4fe830b PM |
686 | .fieldoffset = offsetoflow32(CPUARMState, cp15.tpidrro_el0), |
687 | .resetfn = arm_cp_reset_ignore }, | |
688 | { .name = "TPIDR_EL1", .state = ARM_CP_STATE_BOTH, | |
689 | .opc0 = 3, .opc1 = 0, .opc2 = 4, .crn = 13, .crm = 0, | |
4d31c596 | 690 | .access = PL1_RW, |
e4fe830b | 691 | .fieldoffset = offsetof(CPUARMState, cp15.tpidr_el1), .resetvalue = 0 }, |
4d31c596 PM |
692 | REGINFO_SENTINEL |
693 | }; | |
694 | ||
55d284af PM |
695 | #ifndef CONFIG_USER_ONLY |
696 | ||
00108f2d PM |
697 | static CPAccessResult gt_cntfrq_access(CPUARMState *env, const ARMCPRegInfo *ri) |
698 | { | |
699 | /* CNTFRQ: not visible from PL0 if both PL0PCTEN and PL0VCTEN are zero */ | |
700 | if (arm_current_pl(env) == 0 && !extract32(env->cp15.c14_cntkctl, 0, 2)) { | |
701 | return CP_ACCESS_TRAP; | |
702 | } | |
703 | return CP_ACCESS_OK; | |
704 | } | |
705 | ||
706 | static CPAccessResult gt_counter_access(CPUARMState *env, int timeridx) | |
707 | { | |
708 | /* CNT[PV]CT: not visible from PL0 if ELO[PV]CTEN is zero */ | |
709 | if (arm_current_pl(env) == 0 && | |
710 | !extract32(env->cp15.c14_cntkctl, timeridx, 1)) { | |
711 | return CP_ACCESS_TRAP; | |
712 | } | |
713 | return CP_ACCESS_OK; | |
714 | } | |
715 | ||
716 | static CPAccessResult gt_timer_access(CPUARMState *env, int timeridx) | |
717 | { | |
718 | /* CNT[PV]_CVAL, CNT[PV]_CTL, CNT[PV]_TVAL: not visible from PL0 if | |
719 | * EL0[PV]TEN is zero. | |
720 | */ | |
721 | if (arm_current_pl(env) == 0 && | |
722 | !extract32(env->cp15.c14_cntkctl, 9 - timeridx, 1)) { | |
723 | return CP_ACCESS_TRAP; | |
724 | } | |
725 | return CP_ACCESS_OK; | |
726 | } | |
727 | ||
728 | static CPAccessResult gt_pct_access(CPUARMState *env, | |
729 | const ARMCPRegInfo *ri) | |
730 | { | |
731 | return gt_counter_access(env, GTIMER_PHYS); | |
732 | } | |
733 | ||
734 | static CPAccessResult gt_vct_access(CPUARMState *env, | |
735 | const ARMCPRegInfo *ri) | |
736 | { | |
737 | return gt_counter_access(env, GTIMER_VIRT); | |
738 | } | |
739 | ||
740 | static CPAccessResult gt_ptimer_access(CPUARMState *env, const ARMCPRegInfo *ri) | |
741 | { | |
742 | return gt_timer_access(env, GTIMER_PHYS); | |
743 | } | |
744 | ||
745 | static CPAccessResult gt_vtimer_access(CPUARMState *env, const ARMCPRegInfo *ri) | |
746 | { | |
747 | return gt_timer_access(env, GTIMER_VIRT); | |
748 | } | |
749 | ||
55d284af PM |
750 | static uint64_t gt_get_countervalue(CPUARMState *env) |
751 | { | |
bc72ad67 | 752 | return qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) / GTIMER_SCALE; |
55d284af PM |
753 | } |
754 | ||
755 | static void gt_recalc_timer(ARMCPU *cpu, int timeridx) | |
756 | { | |
757 | ARMGenericTimer *gt = &cpu->env.cp15.c14_timer[timeridx]; | |
758 | ||
759 | if (gt->ctl & 1) { | |
760 | /* Timer enabled: calculate and set current ISTATUS, irq, and | |
761 | * reset timer to when ISTATUS next has to change | |
762 | */ | |
763 | uint64_t count = gt_get_countervalue(&cpu->env); | |
764 | /* Note that this must be unsigned 64 bit arithmetic: */ | |
765 | int istatus = count >= gt->cval; | |
766 | uint64_t nexttick; | |
767 | ||
768 | gt->ctl = deposit32(gt->ctl, 2, 1, istatus); | |
769 | qemu_set_irq(cpu->gt_timer_outputs[timeridx], | |
770 | (istatus && !(gt->ctl & 2))); | |
771 | if (istatus) { | |
772 | /* Next transition is when count rolls back over to zero */ | |
773 | nexttick = UINT64_MAX; | |
774 | } else { | |
775 | /* Next transition is when we hit cval */ | |
776 | nexttick = gt->cval; | |
777 | } | |
778 | /* Note that the desired next expiry time might be beyond the | |
779 | * signed-64-bit range of a QEMUTimer -- in this case we just | |
780 | * set the timer for as far in the future as possible. When the | |
781 | * timer expires we will reset the timer for any remaining period. | |
782 | */ | |
783 | if (nexttick > INT64_MAX / GTIMER_SCALE) { | |
784 | nexttick = INT64_MAX / GTIMER_SCALE; | |
785 | } | |
bc72ad67 | 786 | timer_mod(cpu->gt_timer[timeridx], nexttick); |
55d284af PM |
787 | } else { |
788 | /* Timer disabled: ISTATUS and timer output always clear */ | |
789 | gt->ctl &= ~4; | |
790 | qemu_set_irq(cpu->gt_timer_outputs[timeridx], 0); | |
bc72ad67 | 791 | timer_del(cpu->gt_timer[timeridx]); |
55d284af PM |
792 | } |
793 | } | |
794 | ||
55d284af PM |
795 | static void gt_cnt_reset(CPUARMState *env, const ARMCPRegInfo *ri) |
796 | { | |
797 | ARMCPU *cpu = arm_env_get_cpu(env); | |
798 | int timeridx = ri->opc1 & 1; | |
799 | ||
bc72ad67 | 800 | timer_del(cpu->gt_timer[timeridx]); |
55d284af PM |
801 | } |
802 | ||
c4241c7d | 803 | static uint64_t gt_cnt_read(CPUARMState *env, const ARMCPRegInfo *ri) |
55d284af | 804 | { |
c4241c7d | 805 | return gt_get_countervalue(env); |
55d284af PM |
806 | } |
807 | ||
c4241c7d PM |
808 | static void gt_cval_write(CPUARMState *env, const ARMCPRegInfo *ri, |
809 | uint64_t value) | |
55d284af PM |
810 | { |
811 | int timeridx = ri->opc1 & 1; | |
812 | ||
813 | env->cp15.c14_timer[timeridx].cval = value; | |
814 | gt_recalc_timer(arm_env_get_cpu(env), timeridx); | |
55d284af | 815 | } |
c4241c7d PM |
816 | |
817 | static uint64_t gt_tval_read(CPUARMState *env, const ARMCPRegInfo *ri) | |
55d284af PM |
818 | { |
819 | int timeridx = ri->crm & 1; | |
820 | ||
c4241c7d PM |
821 | return (uint32_t)(env->cp15.c14_timer[timeridx].cval - |
822 | gt_get_countervalue(env)); | |
55d284af PM |
823 | } |
824 | ||
c4241c7d PM |
825 | static void gt_tval_write(CPUARMState *env, const ARMCPRegInfo *ri, |
826 | uint64_t value) | |
55d284af PM |
827 | { |
828 | int timeridx = ri->crm & 1; | |
829 | ||
830 | env->cp15.c14_timer[timeridx].cval = gt_get_countervalue(env) + | |
831 | + sextract64(value, 0, 32); | |
832 | gt_recalc_timer(arm_env_get_cpu(env), timeridx); | |
55d284af PM |
833 | } |
834 | ||
c4241c7d PM |
835 | static void gt_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri, |
836 | uint64_t value) | |
55d284af PM |
837 | { |
838 | ARMCPU *cpu = arm_env_get_cpu(env); | |
839 | int timeridx = ri->crm & 1; | |
840 | uint32_t oldval = env->cp15.c14_timer[timeridx].ctl; | |
841 | ||
842 | env->cp15.c14_timer[timeridx].ctl = value & 3; | |
843 | if ((oldval ^ value) & 1) { | |
844 | /* Enable toggled */ | |
845 | gt_recalc_timer(cpu, timeridx); | |
846 | } else if ((oldval & value) & 2) { | |
847 | /* IMASK toggled: don't need to recalculate, | |
848 | * just set the interrupt line based on ISTATUS | |
849 | */ | |
850 | qemu_set_irq(cpu->gt_timer_outputs[timeridx], | |
851 | (oldval & 4) && (value & 2)); | |
852 | } | |
55d284af PM |
853 | } |
854 | ||
855 | void arm_gt_ptimer_cb(void *opaque) | |
856 | { | |
857 | ARMCPU *cpu = opaque; | |
858 | ||
859 | gt_recalc_timer(cpu, GTIMER_PHYS); | |
860 | } | |
861 | ||
862 | void arm_gt_vtimer_cb(void *opaque) | |
863 | { | |
864 | ARMCPU *cpu = opaque; | |
865 | ||
866 | gt_recalc_timer(cpu, GTIMER_VIRT); | |
867 | } | |
868 | ||
869 | static const ARMCPRegInfo generic_timer_cp_reginfo[] = { | |
870 | /* Note that CNTFRQ is purely reads-as-written for the benefit | |
871 | * of software; writing it doesn't actually change the timer frequency. | |
872 | * Our reset value matches the fixed frequency we implement the timer at. | |
873 | */ | |
874 | { .name = "CNTFRQ", .cp = 15, .crn = 14, .crm = 0, .opc1 = 0, .opc2 = 0, | |
875 | .access = PL1_RW | PL0_R, | |
876 | .fieldoffset = offsetof(CPUARMState, cp15.c14_cntfrq), | |
877 | .resetvalue = (1000 * 1000 * 1000) / GTIMER_SCALE, | |
00108f2d | 878 | .accessfn = gt_cntfrq_access, |
55d284af PM |
879 | }, |
880 | /* overall control: mostly access permissions */ | |
881 | { .name = "CNTKCTL", .cp = 15, .crn = 14, .crm = 1, .opc1 = 0, .opc2 = 0, | |
882 | .access = PL1_RW, | |
883 | .fieldoffset = offsetof(CPUARMState, cp15.c14_cntkctl), | |
884 | .resetvalue = 0, | |
885 | }, | |
886 | /* per-timer control */ | |
887 | { .name = "CNTP_CTL", .cp = 15, .crn = 14, .crm = 2, .opc1 = 0, .opc2 = 1, | |
888 | .type = ARM_CP_IO, .access = PL1_RW | PL0_R, | |
889 | .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].ctl), | |
890 | .resetvalue = 0, | |
00108f2d PM |
891 | .accessfn = gt_ptimer_access, |
892 | .writefn = gt_ctl_write, .raw_writefn = raw_write, | |
55d284af PM |
893 | }, |
894 | { .name = "CNTV_CTL", .cp = 15, .crn = 14, .crm = 3, .opc1 = 0, .opc2 = 1, | |
895 | .type = ARM_CP_IO, .access = PL1_RW | PL0_R, | |
896 | .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].ctl), | |
897 | .resetvalue = 0, | |
00108f2d PM |
898 | .accessfn = gt_vtimer_access, |
899 | .writefn = gt_ctl_write, .raw_writefn = raw_write, | |
55d284af PM |
900 | }, |
901 | /* TimerValue views: a 32 bit downcounting view of the underlying state */ | |
902 | { .name = "CNTP_TVAL", .cp = 15, .crn = 14, .crm = 2, .opc1 = 0, .opc2 = 0, | |
903 | .type = ARM_CP_NO_MIGRATE | ARM_CP_IO, .access = PL1_RW | PL0_R, | |
00108f2d | 904 | .accessfn = gt_ptimer_access, |
55d284af PM |
905 | .readfn = gt_tval_read, .writefn = gt_tval_write, |
906 | }, | |
907 | { .name = "CNTV_TVAL", .cp = 15, .crn = 14, .crm = 3, .opc1 = 0, .opc2 = 0, | |
908 | .type = ARM_CP_NO_MIGRATE | ARM_CP_IO, .access = PL1_RW | PL0_R, | |
00108f2d | 909 | .accessfn = gt_vtimer_access, |
55d284af PM |
910 | .readfn = gt_tval_read, .writefn = gt_tval_write, |
911 | }, | |
912 | /* The counter itself */ | |
913 | { .name = "CNTPCT", .cp = 15, .crm = 14, .opc1 = 0, | |
914 | .access = PL0_R, .type = ARM_CP_64BIT | ARM_CP_NO_MIGRATE | ARM_CP_IO, | |
00108f2d | 915 | .accessfn = gt_pct_access, |
55d284af PM |
916 | .readfn = gt_cnt_read, .resetfn = gt_cnt_reset, |
917 | }, | |
918 | { .name = "CNTVCT", .cp = 15, .crm = 14, .opc1 = 1, | |
919 | .access = PL0_R, .type = ARM_CP_64BIT | ARM_CP_NO_MIGRATE | ARM_CP_IO, | |
00108f2d | 920 | .accessfn = gt_vct_access, |
55d284af PM |
921 | .readfn = gt_cnt_read, .resetfn = gt_cnt_reset, |
922 | }, | |
923 | /* Comparison value, indicating when the timer goes off */ | |
924 | { .name = "CNTP_CVAL", .cp = 15, .crm = 14, .opc1 = 2, | |
925 | .access = PL1_RW | PL0_R, | |
926 | .type = ARM_CP_64BIT | ARM_CP_IO, | |
927 | .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].cval), | |
928 | .resetvalue = 0, | |
00108f2d PM |
929 | .accessfn = gt_ptimer_access, |
930 | .writefn = gt_cval_write, .raw_writefn = raw_write, | |
55d284af PM |
931 | }, |
932 | { .name = "CNTV_CVAL", .cp = 15, .crm = 14, .opc1 = 3, | |
933 | .access = PL1_RW | PL0_R, | |
934 | .type = ARM_CP_64BIT | ARM_CP_IO, | |
935 | .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].cval), | |
936 | .resetvalue = 0, | |
00108f2d PM |
937 | .accessfn = gt_vtimer_access, |
938 | .writefn = gt_cval_write, .raw_writefn = raw_write, | |
55d284af PM |
939 | }, |
940 | REGINFO_SENTINEL | |
941 | }; | |
942 | ||
943 | #else | |
944 | /* In user-mode none of the generic timer registers are accessible, | |
bc72ad67 | 945 | * and their implementation depends on QEMU_CLOCK_VIRTUAL and qdev gpio outputs, |
55d284af PM |
946 | * so instead just don't register any of them. |
947 | */ | |
6cc7a3ae | 948 | static const ARMCPRegInfo generic_timer_cp_reginfo[] = { |
6cc7a3ae PM |
949 | REGINFO_SENTINEL |
950 | }; | |
951 | ||
55d284af PM |
952 | #endif |
953 | ||
c4241c7d | 954 | static void par_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) |
4a501606 | 955 | { |
891a2fe7 PM |
956 | if (arm_feature(env, ARM_FEATURE_LPAE)) { |
957 | env->cp15.c7_par = value; | |
958 | } else if (arm_feature(env, ARM_FEATURE_V7)) { | |
4a501606 PM |
959 | env->cp15.c7_par = value & 0xfffff6ff; |
960 | } else { | |
961 | env->cp15.c7_par = value & 0xfffff1ff; | |
962 | } | |
4a501606 PM |
963 | } |
964 | ||
965 | #ifndef CONFIG_USER_ONLY | |
966 | /* get_phys_addr() isn't present for user-mode-only targets */ | |
702a9357 PM |
967 | |
968 | /* Return true if extended addresses are enabled, ie this is an | |
969 | * LPAE implementation and we are using the long-descriptor translation | |
970 | * table format because the TTBCR EAE bit is set. | |
971 | */ | |
972 | static inline bool extended_addresses_enabled(CPUARMState *env) | |
973 | { | |
974 | return arm_feature(env, ARM_FEATURE_LPAE) | |
78dbbbe4 | 975 | && (env->cp15.c2_control & (1U << 31)); |
702a9357 PM |
976 | } |
977 | ||
92611c00 PM |
978 | static CPAccessResult ats_access(CPUARMState *env, const ARMCPRegInfo *ri) |
979 | { | |
980 | if (ri->opc2 & 4) { | |
981 | /* Other states are only available with TrustZone; in | |
982 | * a non-TZ implementation these registers don't exist | |
983 | * at all, which is an Uncategorized trap. This underdecoding | |
984 | * is safe because the reginfo is NO_MIGRATE. | |
985 | */ | |
986 | return CP_ACCESS_TRAP_UNCATEGORIZED; | |
987 | } | |
988 | return CP_ACCESS_OK; | |
989 | } | |
990 | ||
c4241c7d | 991 | static void ats_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) |
4a501606 | 992 | { |
a8170e5e | 993 | hwaddr phys_addr; |
4a501606 PM |
994 | target_ulong page_size; |
995 | int prot; | |
996 | int ret, is_user = ri->opc2 & 2; | |
997 | int access_type = ri->opc2 & 1; | |
998 | ||
4a501606 PM |
999 | ret = get_phys_addr(env, value, access_type, is_user, |
1000 | &phys_addr, &prot, &page_size); | |
702a9357 PM |
1001 | if (extended_addresses_enabled(env)) { |
1002 | /* ret is a DFSR/IFSR value for the long descriptor | |
1003 | * translation table format, but with WnR always clear. | |
1004 | * Convert it to a 64-bit PAR. | |
1005 | */ | |
1006 | uint64_t par64 = (1 << 11); /* LPAE bit always set */ | |
1007 | if (ret == 0) { | |
1008 | par64 |= phys_addr & ~0xfffULL; | |
1009 | /* We don't set the ATTR or SH fields in the PAR. */ | |
4a501606 | 1010 | } else { |
702a9357 PM |
1011 | par64 |= 1; /* F */ |
1012 | par64 |= (ret & 0x3f) << 1; /* FS */ | |
1013 | /* Note that S2WLK and FSTAGE are always zero, because we don't | |
1014 | * implement virtualization and therefore there can't be a stage 2 | |
1015 | * fault. | |
1016 | */ | |
4a501606 | 1017 | } |
702a9357 PM |
1018 | env->cp15.c7_par = par64; |
1019 | env->cp15.c7_par_hi = par64 >> 32; | |
4a501606 | 1020 | } else { |
702a9357 PM |
1021 | /* ret is a DFSR/IFSR value for the short descriptor |
1022 | * translation table format (with WnR always clear). | |
1023 | * Convert it to a 32-bit PAR. | |
1024 | */ | |
1025 | if (ret == 0) { | |
1026 | /* We do not set any attribute bits in the PAR */ | |
1027 | if (page_size == (1 << 24) | |
1028 | && arm_feature(env, ARM_FEATURE_V7)) { | |
1029 | env->cp15.c7_par = (phys_addr & 0xff000000) | 1 << 1; | |
1030 | } else { | |
1031 | env->cp15.c7_par = phys_addr & 0xfffff000; | |
1032 | } | |
1033 | } else { | |
775fda92 PM |
1034 | env->cp15.c7_par = ((ret & (1 << 10)) >> 5) | |
1035 | ((ret & (1 << 12)) >> 6) | | |
702a9357 PM |
1036 | ((ret & 0xf) << 1) | 1; |
1037 | } | |
1038 | env->cp15.c7_par_hi = 0; | |
4a501606 | 1039 | } |
4a501606 PM |
1040 | } |
1041 | #endif | |
1042 | ||
1043 | static const ARMCPRegInfo vapa_cp_reginfo[] = { | |
1044 | { .name = "PAR", .cp = 15, .crn = 7, .crm = 4, .opc1 = 0, .opc2 = 0, | |
1045 | .access = PL1_RW, .resetvalue = 0, | |
1046 | .fieldoffset = offsetof(CPUARMState, cp15.c7_par), | |
1047 | .writefn = par_write }, | |
1048 | #ifndef CONFIG_USER_ONLY | |
1049 | { .name = "ATS", .cp = 15, .crn = 7, .crm = 8, .opc1 = 0, .opc2 = CP_ANY, | |
92611c00 PM |
1050 | .access = PL1_W, .accessfn = ats_access, |
1051 | .writefn = ats_write, .type = ARM_CP_NO_MIGRATE }, | |
4a501606 PM |
1052 | #endif |
1053 | REGINFO_SENTINEL | |
1054 | }; | |
1055 | ||
18032bec PM |
1056 | /* Return basic MPU access permission bits. */ |
1057 | static uint32_t simple_mpu_ap_bits(uint32_t val) | |
1058 | { | |
1059 | uint32_t ret; | |
1060 | uint32_t mask; | |
1061 | int i; | |
1062 | ret = 0; | |
1063 | mask = 3; | |
1064 | for (i = 0; i < 16; i += 2) { | |
1065 | ret |= (val >> i) & mask; | |
1066 | mask <<= 2; | |
1067 | } | |
1068 | return ret; | |
1069 | } | |
1070 | ||
1071 | /* Pad basic MPU access permission bits to extended format. */ | |
1072 | static uint32_t extended_mpu_ap_bits(uint32_t val) | |
1073 | { | |
1074 | uint32_t ret; | |
1075 | uint32_t mask; | |
1076 | int i; | |
1077 | ret = 0; | |
1078 | mask = 3; | |
1079 | for (i = 0; i < 16; i += 2) { | |
1080 | ret |= (val & mask) << i; | |
1081 | mask <<= 2; | |
1082 | } | |
1083 | return ret; | |
1084 | } | |
1085 | ||
c4241c7d PM |
1086 | static void pmsav5_data_ap_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1087 | uint64_t value) | |
18032bec PM |
1088 | { |
1089 | env->cp15.c5_data = extended_mpu_ap_bits(value); | |
18032bec PM |
1090 | } |
1091 | ||
c4241c7d | 1092 | static uint64_t pmsav5_data_ap_read(CPUARMState *env, const ARMCPRegInfo *ri) |
18032bec | 1093 | { |
c4241c7d | 1094 | return simple_mpu_ap_bits(env->cp15.c5_data); |
18032bec PM |
1095 | } |
1096 | ||
c4241c7d PM |
1097 | static void pmsav5_insn_ap_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1098 | uint64_t value) | |
18032bec PM |
1099 | { |
1100 | env->cp15.c5_insn = extended_mpu_ap_bits(value); | |
18032bec PM |
1101 | } |
1102 | ||
c4241c7d | 1103 | static uint64_t pmsav5_insn_ap_read(CPUARMState *env, const ARMCPRegInfo *ri) |
18032bec | 1104 | { |
c4241c7d | 1105 | return simple_mpu_ap_bits(env->cp15.c5_insn); |
18032bec PM |
1106 | } |
1107 | ||
1108 | static const ARMCPRegInfo pmsav5_cp_reginfo[] = { | |
1109 | { .name = "DATA_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 0, | |
d4e6df63 | 1110 | .access = PL1_RW, .type = ARM_CP_NO_MIGRATE, |
18032bec PM |
1111 | .fieldoffset = offsetof(CPUARMState, cp15.c5_data), .resetvalue = 0, |
1112 | .readfn = pmsav5_data_ap_read, .writefn = pmsav5_data_ap_write, }, | |
1113 | { .name = "INSN_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 1, | |
d4e6df63 | 1114 | .access = PL1_RW, .type = ARM_CP_NO_MIGRATE, |
18032bec PM |
1115 | .fieldoffset = offsetof(CPUARMState, cp15.c5_insn), .resetvalue = 0, |
1116 | .readfn = pmsav5_insn_ap_read, .writefn = pmsav5_insn_ap_write, }, | |
1117 | { .name = "DATA_EXT_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 2, | |
1118 | .access = PL1_RW, | |
1119 | .fieldoffset = offsetof(CPUARMState, cp15.c5_data), .resetvalue = 0, }, | |
1120 | { .name = "INSN_EXT_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 3, | |
1121 | .access = PL1_RW, | |
1122 | .fieldoffset = offsetof(CPUARMState, cp15.c5_insn), .resetvalue = 0, }, | |
ecce5c3c PM |
1123 | { .name = "DCACHE_CFG", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 0, |
1124 | .access = PL1_RW, | |
1125 | .fieldoffset = offsetof(CPUARMState, cp15.c2_data), .resetvalue = 0, }, | |
1126 | { .name = "ICACHE_CFG", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 1, | |
1127 | .access = PL1_RW, | |
1128 | .fieldoffset = offsetof(CPUARMState, cp15.c2_insn), .resetvalue = 0, }, | |
06d76f31 | 1129 | /* Protection region base and size registers */ |
e508a92b PM |
1130 | { .name = "946_PRBS0", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, |
1131 | .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0, | |
1132 | .fieldoffset = offsetof(CPUARMState, cp15.c6_region[0]) }, | |
1133 | { .name = "946_PRBS1", .cp = 15, .crn = 6, .crm = 1, .opc1 = 0, | |
1134 | .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0, | |
1135 | .fieldoffset = offsetof(CPUARMState, cp15.c6_region[1]) }, | |
1136 | { .name = "946_PRBS2", .cp = 15, .crn = 6, .crm = 2, .opc1 = 0, | |
1137 | .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0, | |
1138 | .fieldoffset = offsetof(CPUARMState, cp15.c6_region[2]) }, | |
1139 | { .name = "946_PRBS3", .cp = 15, .crn = 6, .crm = 3, .opc1 = 0, | |
1140 | .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0, | |
1141 | .fieldoffset = offsetof(CPUARMState, cp15.c6_region[3]) }, | |
1142 | { .name = "946_PRBS4", .cp = 15, .crn = 6, .crm = 4, .opc1 = 0, | |
1143 | .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0, | |
1144 | .fieldoffset = offsetof(CPUARMState, cp15.c6_region[4]) }, | |
1145 | { .name = "946_PRBS5", .cp = 15, .crn = 6, .crm = 5, .opc1 = 0, | |
1146 | .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0, | |
1147 | .fieldoffset = offsetof(CPUARMState, cp15.c6_region[5]) }, | |
1148 | { .name = "946_PRBS6", .cp = 15, .crn = 6, .crm = 6, .opc1 = 0, | |
1149 | .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0, | |
1150 | .fieldoffset = offsetof(CPUARMState, cp15.c6_region[6]) }, | |
1151 | { .name = "946_PRBS7", .cp = 15, .crn = 6, .crm = 7, .opc1 = 0, | |
1152 | .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0, | |
1153 | .fieldoffset = offsetof(CPUARMState, cp15.c6_region[7]) }, | |
18032bec PM |
1154 | REGINFO_SENTINEL |
1155 | }; | |
1156 | ||
c4241c7d PM |
1157 | static void vmsa_ttbcr_raw_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1158 | uint64_t value) | |
ecce5c3c | 1159 | { |
2ebcebe2 PM |
1160 | int maskshift = extract32(value, 0, 3); |
1161 | ||
74f1c6dd | 1162 | if (arm_feature(env, ARM_FEATURE_LPAE) && (value & (1 << 31))) { |
e42c4db3 | 1163 | value &= ~((7 << 19) | (3 << 14) | (0xf << 3)); |
e42c4db3 PM |
1164 | } else { |
1165 | value &= 7; | |
1166 | } | |
1167 | /* Note that we always calculate c2_mask and c2_base_mask, but | |
1168 | * they are only used for short-descriptor tables (ie if EAE is 0); | |
1169 | * for long-descriptor tables the TTBCR fields are used differently | |
1170 | * and the c2_mask and c2_base_mask values are meaningless. | |
1171 | */ | |
ecce5c3c | 1172 | env->cp15.c2_control = value; |
2ebcebe2 PM |
1173 | env->cp15.c2_mask = ~(((uint32_t)0xffffffffu) >> maskshift); |
1174 | env->cp15.c2_base_mask = ~((uint32_t)0x3fffu >> maskshift); | |
ecce5c3c PM |
1175 | } |
1176 | ||
c4241c7d PM |
1177 | static void vmsa_ttbcr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1178 | uint64_t value) | |
d4e6df63 PM |
1179 | { |
1180 | if (arm_feature(env, ARM_FEATURE_LPAE)) { | |
1181 | /* With LPAE the TTBCR could result in a change of ASID | |
1182 | * via the TTBCR.A1 bit, so do a TLB flush. | |
1183 | */ | |
1184 | tlb_flush(env, 1); | |
1185 | } | |
c4241c7d | 1186 | vmsa_ttbcr_raw_write(env, ri, value); |
d4e6df63 PM |
1187 | } |
1188 | ||
ecce5c3c PM |
1189 | static void vmsa_ttbcr_reset(CPUARMState *env, const ARMCPRegInfo *ri) |
1190 | { | |
1191 | env->cp15.c2_base_mask = 0xffffc000u; | |
1192 | env->cp15.c2_control = 0; | |
1193 | env->cp15.c2_mask = 0; | |
1194 | } | |
1195 | ||
18032bec PM |
1196 | static const ARMCPRegInfo vmsa_cp_reginfo[] = { |
1197 | { .name = "DFSR", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 0, | |
1198 | .access = PL1_RW, | |
1199 | .fieldoffset = offsetof(CPUARMState, cp15.c5_data), .resetvalue = 0, }, | |
1200 | { .name = "IFSR", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 1, | |
1201 | .access = PL1_RW, | |
1202 | .fieldoffset = offsetof(CPUARMState, cp15.c5_insn), .resetvalue = 0, }, | |
ecce5c3c PM |
1203 | { .name = "TTBR0", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 0, |
1204 | .access = PL1_RW, | |
1205 | .fieldoffset = offsetof(CPUARMState, cp15.c2_base0), .resetvalue = 0, }, | |
1206 | { .name = "TTBR1", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 1, | |
1207 | .access = PL1_RW, | |
81a60ada | 1208 | .fieldoffset = offsetof(CPUARMState, cp15.c2_base1), .resetvalue = 0, }, |
ecce5c3c PM |
1209 | { .name = "TTBCR", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 2, |
1210 | .access = PL1_RW, .writefn = vmsa_ttbcr_write, | |
d4e6df63 | 1211 | .resetfn = vmsa_ttbcr_reset, .raw_writefn = vmsa_ttbcr_raw_write, |
ecce5c3c | 1212 | .fieldoffset = offsetof(CPUARMState, cp15.c2_control) }, |
06d76f31 PM |
1213 | { .name = "DFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 0, |
1214 | .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c6_data), | |
1215 | .resetvalue = 0, }, | |
18032bec PM |
1216 | REGINFO_SENTINEL |
1217 | }; | |
1218 | ||
c4241c7d PM |
1219 | static void omap_ticonfig_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1220 | uint64_t value) | |
1047b9d7 PM |
1221 | { |
1222 | env->cp15.c15_ticonfig = value & 0xe7; | |
1223 | /* The OS_TYPE bit in this register changes the reported CPUID! */ | |
1224 | env->cp15.c0_cpuid = (value & (1 << 5)) ? | |
1225 | ARM_CPUID_TI915T : ARM_CPUID_TI925T; | |
1047b9d7 PM |
1226 | } |
1227 | ||
c4241c7d PM |
1228 | static void omap_threadid_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1229 | uint64_t value) | |
1047b9d7 PM |
1230 | { |
1231 | env->cp15.c15_threadid = value & 0xffff; | |
1047b9d7 PM |
1232 | } |
1233 | ||
c4241c7d PM |
1234 | static void omap_wfi_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1235 | uint64_t value) | |
1047b9d7 PM |
1236 | { |
1237 | /* Wait-for-interrupt (deprecated) */ | |
c3affe56 | 1238 | cpu_interrupt(CPU(arm_env_get_cpu(env)), CPU_INTERRUPT_HALT); |
1047b9d7 PM |
1239 | } |
1240 | ||
c4241c7d PM |
1241 | static void omap_cachemaint_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1242 | uint64_t value) | |
c4804214 PM |
1243 | { |
1244 | /* On OMAP there are registers indicating the max/min index of dcache lines | |
1245 | * containing a dirty line; cache flush operations have to reset these. | |
1246 | */ | |
1247 | env->cp15.c15_i_max = 0x000; | |
1248 | env->cp15.c15_i_min = 0xff0; | |
c4804214 PM |
1249 | } |
1250 | ||
18032bec PM |
1251 | static const ARMCPRegInfo omap_cp_reginfo[] = { |
1252 | { .name = "DFSR", .cp = 15, .crn = 5, .crm = CP_ANY, | |
1253 | .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_OVERRIDE, | |
1254 | .fieldoffset = offsetof(CPUARMState, cp15.c5_data), .resetvalue = 0, }, | |
1047b9d7 PM |
1255 | { .name = "", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0, |
1256 | .access = PL1_RW, .type = ARM_CP_NOP }, | |
1257 | { .name = "TICONFIG", .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0, | |
1258 | .access = PL1_RW, | |
1259 | .fieldoffset = offsetof(CPUARMState, cp15.c15_ticonfig), .resetvalue = 0, | |
1260 | .writefn = omap_ticonfig_write }, | |
1261 | { .name = "IMAX", .cp = 15, .crn = 15, .crm = 2, .opc1 = 0, .opc2 = 0, | |
1262 | .access = PL1_RW, | |
1263 | .fieldoffset = offsetof(CPUARMState, cp15.c15_i_max), .resetvalue = 0, }, | |
1264 | { .name = "IMIN", .cp = 15, .crn = 15, .crm = 3, .opc1 = 0, .opc2 = 0, | |
1265 | .access = PL1_RW, .resetvalue = 0xff0, | |
1266 | .fieldoffset = offsetof(CPUARMState, cp15.c15_i_min) }, | |
1267 | { .name = "THREADID", .cp = 15, .crn = 15, .crm = 4, .opc1 = 0, .opc2 = 0, | |
1268 | .access = PL1_RW, | |
1269 | .fieldoffset = offsetof(CPUARMState, cp15.c15_threadid), .resetvalue = 0, | |
1270 | .writefn = omap_threadid_write }, | |
1271 | { .name = "TI925T_STATUS", .cp = 15, .crn = 15, | |
1272 | .crm = 8, .opc1 = 0, .opc2 = 0, .access = PL1_RW, | |
d4e6df63 | 1273 | .type = ARM_CP_NO_MIGRATE, |
1047b9d7 PM |
1274 | .readfn = arm_cp_read_zero, .writefn = omap_wfi_write, }, |
1275 | /* TODO: Peripheral port remap register: | |
1276 | * On OMAP2 mcr p15, 0, rn, c15, c2, 4 sets up the interrupt controller | |
1277 | * base address at $rn & ~0xfff and map size of 0x200 << ($rn & 0xfff), | |
1278 | * when MMU is off. | |
1279 | */ | |
c4804214 | 1280 | { .name = "OMAP_CACHEMAINT", .cp = 15, .crn = 7, .crm = CP_ANY, |
d4e6df63 PM |
1281 | .opc1 = 0, .opc2 = CP_ANY, .access = PL1_W, |
1282 | .type = ARM_CP_OVERRIDE | ARM_CP_NO_MIGRATE, | |
c4804214 | 1283 | .writefn = omap_cachemaint_write }, |
34f90529 PM |
1284 | { .name = "C9", .cp = 15, .crn = 9, |
1285 | .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, | |
1286 | .type = ARM_CP_CONST | ARM_CP_OVERRIDE, .resetvalue = 0 }, | |
1047b9d7 PM |
1287 | REGINFO_SENTINEL |
1288 | }; | |
1289 | ||
c4241c7d PM |
1290 | static void xscale_cpar_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1291 | uint64_t value) | |
1047b9d7 PM |
1292 | { |
1293 | value &= 0x3fff; | |
1294 | if (env->cp15.c15_cpar != value) { | |
1295 | /* Changes cp0 to cp13 behavior, so needs a TB flush. */ | |
1296 | tb_flush(env); | |
1297 | env->cp15.c15_cpar = value; | |
1298 | } | |
1047b9d7 PM |
1299 | } |
1300 | ||
1301 | static const ARMCPRegInfo xscale_cp_reginfo[] = { | |
1302 | { .name = "XSCALE_CPAR", | |
1303 | .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0, .access = PL1_RW, | |
1304 | .fieldoffset = offsetof(CPUARMState, cp15.c15_cpar), .resetvalue = 0, | |
1305 | .writefn = xscale_cpar_write, }, | |
2771db27 PM |
1306 | { .name = "XSCALE_AUXCR", |
1307 | .cp = 15, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 1, .access = PL1_RW, | |
1308 | .fieldoffset = offsetof(CPUARMState, cp15.c1_xscaleauxcr), | |
1309 | .resetvalue = 0, }, | |
1047b9d7 PM |
1310 | REGINFO_SENTINEL |
1311 | }; | |
1312 | ||
1313 | static const ARMCPRegInfo dummy_c15_cp_reginfo[] = { | |
1314 | /* RAZ/WI the whole crn=15 space, when we don't have a more specific | |
1315 | * implementation of this implementation-defined space. | |
1316 | * Ideally this should eventually disappear in favour of actually | |
1317 | * implementing the correct behaviour for all cores. | |
1318 | */ | |
1319 | { .name = "C15_IMPDEF", .cp = 15, .crn = 15, | |
1320 | .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY, | |
3671cd87 PC |
1321 | .access = PL1_RW, |
1322 | .type = ARM_CP_CONST | ARM_CP_NO_MIGRATE | ARM_CP_OVERRIDE, | |
d4e6df63 | 1323 | .resetvalue = 0 }, |
18032bec PM |
1324 | REGINFO_SENTINEL |
1325 | }; | |
1326 | ||
c4804214 PM |
1327 | static const ARMCPRegInfo cache_dirty_status_cp_reginfo[] = { |
1328 | /* Cache status: RAZ because we have no cache so it's always clean */ | |
1329 | { .name = "CDSR", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 6, | |
d4e6df63 PM |
1330 | .access = PL1_R, .type = ARM_CP_CONST | ARM_CP_NO_MIGRATE, |
1331 | .resetvalue = 0 }, | |
c4804214 PM |
1332 | REGINFO_SENTINEL |
1333 | }; | |
1334 | ||
1335 | static const ARMCPRegInfo cache_block_ops_cp_reginfo[] = { | |
1336 | /* We never have a a block transfer operation in progress */ | |
1337 | { .name = "BXSR", .cp = 15, .crn = 7, .crm = 12, .opc1 = 0, .opc2 = 4, | |
d4e6df63 PM |
1338 | .access = PL0_R, .type = ARM_CP_CONST | ARM_CP_NO_MIGRATE, |
1339 | .resetvalue = 0 }, | |
30b05bba PM |
1340 | /* The cache ops themselves: these all NOP for QEMU */ |
1341 | { .name = "IICR", .cp = 15, .crm = 5, .opc1 = 0, | |
1342 | .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT }, | |
1343 | { .name = "IDCR", .cp = 15, .crm = 6, .opc1 = 0, | |
1344 | .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT }, | |
1345 | { .name = "CDCR", .cp = 15, .crm = 12, .opc1 = 0, | |
1346 | .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT }, | |
1347 | { .name = "PIR", .cp = 15, .crm = 12, .opc1 = 1, | |
1348 | .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT }, | |
1349 | { .name = "PDR", .cp = 15, .crm = 12, .opc1 = 2, | |
1350 | .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT }, | |
1351 | { .name = "CIDCR", .cp = 15, .crm = 14, .opc1 = 0, | |
1352 | .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT }, | |
c4804214 PM |
1353 | REGINFO_SENTINEL |
1354 | }; | |
1355 | ||
1356 | static const ARMCPRegInfo cache_test_clean_cp_reginfo[] = { | |
1357 | /* The cache test-and-clean instructions always return (1 << 30) | |
1358 | * to indicate that there are no dirty cache lines. | |
1359 | */ | |
1360 | { .name = "TC_DCACHE", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 3, | |
d4e6df63 PM |
1361 | .access = PL0_R, .type = ARM_CP_CONST | ARM_CP_NO_MIGRATE, |
1362 | .resetvalue = (1 << 30) }, | |
c4804214 | 1363 | { .name = "TCI_DCACHE", .cp = 15, .crn = 7, .crm = 14, .opc1 = 0, .opc2 = 3, |
d4e6df63 PM |
1364 | .access = PL0_R, .type = ARM_CP_CONST | ARM_CP_NO_MIGRATE, |
1365 | .resetvalue = (1 << 30) }, | |
c4804214 PM |
1366 | REGINFO_SENTINEL |
1367 | }; | |
1368 | ||
34f90529 PM |
1369 | static const ARMCPRegInfo strongarm_cp_reginfo[] = { |
1370 | /* Ignore ReadBuffer accesses */ | |
1371 | { .name = "C9_READBUFFER", .cp = 15, .crn = 9, | |
1372 | .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY, | |
d4e6df63 PM |
1373 | .access = PL1_RW, .resetvalue = 0, |
1374 | .type = ARM_CP_CONST | ARM_CP_OVERRIDE | ARM_CP_NO_MIGRATE }, | |
34f90529 PM |
1375 | REGINFO_SENTINEL |
1376 | }; | |
1377 | ||
c4241c7d | 1378 | static uint64_t mpidr_read(CPUARMState *env, const ARMCPRegInfo *ri) |
81bdde9d | 1379 | { |
55e5c285 AF |
1380 | CPUState *cs = CPU(arm_env_get_cpu(env)); |
1381 | uint32_t mpidr = cs->cpu_index; | |
81bdde9d PM |
1382 | /* We don't support setting cluster ID ([8..11]) |
1383 | * so these bits always RAZ. | |
1384 | */ | |
1385 | if (arm_feature(env, ARM_FEATURE_V7MP)) { | |
78dbbbe4 | 1386 | mpidr |= (1U << 31); |
81bdde9d PM |
1387 | /* Cores which are uniprocessor (non-coherent) |
1388 | * but still implement the MP extensions set | |
1389 | * bit 30. (For instance, A9UP.) However we do | |
1390 | * not currently model any of those cores. | |
1391 | */ | |
1392 | } | |
c4241c7d | 1393 | return mpidr; |
81bdde9d PM |
1394 | } |
1395 | ||
1396 | static const ARMCPRegInfo mpidr_cp_reginfo[] = { | |
1397 | { .name = "MPIDR", .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 5, | |
d4e6df63 | 1398 | .access = PL1_R, .readfn = mpidr_read, .type = ARM_CP_NO_MIGRATE }, |
81bdde9d PM |
1399 | REGINFO_SENTINEL |
1400 | }; | |
1401 | ||
c4241c7d | 1402 | static uint64_t par64_read(CPUARMState *env, const ARMCPRegInfo *ri) |
891a2fe7 | 1403 | { |
c4241c7d | 1404 | return ((uint64_t)env->cp15.c7_par_hi << 32) | env->cp15.c7_par; |
891a2fe7 PM |
1405 | } |
1406 | ||
c4241c7d PM |
1407 | static void par64_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1408 | uint64_t value) | |
891a2fe7 PM |
1409 | { |
1410 | env->cp15.c7_par_hi = value >> 32; | |
1411 | env->cp15.c7_par = value; | |
891a2fe7 PM |
1412 | } |
1413 | ||
1414 | static void par64_reset(CPUARMState *env, const ARMCPRegInfo *ri) | |
1415 | { | |
1416 | env->cp15.c7_par_hi = 0; | |
1417 | env->cp15.c7_par = 0; | |
1418 | } | |
1419 | ||
c4241c7d | 1420 | static uint64_t ttbr064_read(CPUARMState *env, const ARMCPRegInfo *ri) |
891a2fe7 | 1421 | { |
c4241c7d | 1422 | return ((uint64_t)env->cp15.c2_base0_hi << 32) | env->cp15.c2_base0; |
891a2fe7 PM |
1423 | } |
1424 | ||
c4241c7d PM |
1425 | static void ttbr064_raw_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1426 | uint64_t value) | |
891a2fe7 PM |
1427 | { |
1428 | env->cp15.c2_base0_hi = value >> 32; | |
1429 | env->cp15.c2_base0 = value; | |
d4e6df63 PM |
1430 | } |
1431 | ||
c4241c7d PM |
1432 | static void ttbr064_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1433 | uint64_t value) | |
d4e6df63 | 1434 | { |
891a2fe7 PM |
1435 | /* Writes to the 64 bit format TTBRs may change the ASID */ |
1436 | tlb_flush(env, 1); | |
c4241c7d | 1437 | ttbr064_raw_write(env, ri, value); |
891a2fe7 PM |
1438 | } |
1439 | ||
1440 | static void ttbr064_reset(CPUARMState *env, const ARMCPRegInfo *ri) | |
1441 | { | |
1442 | env->cp15.c2_base0_hi = 0; | |
1443 | env->cp15.c2_base0 = 0; | |
1444 | } | |
1445 | ||
c4241c7d | 1446 | static uint64_t ttbr164_read(CPUARMState *env, const ARMCPRegInfo *ri) |
891a2fe7 | 1447 | { |
c4241c7d | 1448 | return ((uint64_t)env->cp15.c2_base1_hi << 32) | env->cp15.c2_base1; |
891a2fe7 PM |
1449 | } |
1450 | ||
c4241c7d PM |
1451 | static void ttbr164_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1452 | uint64_t value) | |
891a2fe7 PM |
1453 | { |
1454 | env->cp15.c2_base1_hi = value >> 32; | |
1455 | env->cp15.c2_base1 = value; | |
891a2fe7 PM |
1456 | } |
1457 | ||
1458 | static void ttbr164_reset(CPUARMState *env, const ARMCPRegInfo *ri) | |
1459 | { | |
1460 | env->cp15.c2_base1_hi = 0; | |
1461 | env->cp15.c2_base1 = 0; | |
1462 | } | |
1463 | ||
7ac681cf | 1464 | static const ARMCPRegInfo lpae_cp_reginfo[] = { |
b90372ad | 1465 | /* NOP AMAIR0/1: the override is because these clash with the rather |
7ac681cf PM |
1466 | * broadly specified TLB_LOCKDOWN entry in the generic cp_reginfo. |
1467 | */ | |
1468 | { .name = "AMAIR0", .cp = 15, .crn = 10, .crm = 3, .opc1 = 0, .opc2 = 0, | |
1469 | .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_OVERRIDE, | |
1470 | .resetvalue = 0 }, | |
1471 | { .name = "AMAIR1", .cp = 15, .crn = 10, .crm = 3, .opc1 = 0, .opc2 = 1, | |
1472 | .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_OVERRIDE, | |
1473 | .resetvalue = 0 }, | |
f9fc619a PM |
1474 | /* 64 bit access versions of the (dummy) debug registers */ |
1475 | { .name = "DBGDRAR", .cp = 14, .crm = 1, .opc1 = 0, | |
1476 | .access = PL0_R, .type = ARM_CP_CONST|ARM_CP_64BIT, .resetvalue = 0 }, | |
1477 | { .name = "DBGDSAR", .cp = 14, .crm = 2, .opc1 = 0, | |
1478 | .access = PL0_R, .type = ARM_CP_CONST|ARM_CP_64BIT, .resetvalue = 0 }, | |
891a2fe7 PM |
1479 | { .name = "PAR", .cp = 15, .crm = 7, .opc1 = 0, |
1480 | .access = PL1_RW, .type = ARM_CP_64BIT, | |
1481 | .readfn = par64_read, .writefn = par64_write, .resetfn = par64_reset }, | |
1482 | { .name = "TTBR0", .cp = 15, .crm = 2, .opc1 = 0, | |
1483 | .access = PL1_RW, .type = ARM_CP_64BIT, .readfn = ttbr064_read, | |
d4e6df63 PM |
1484 | .writefn = ttbr064_write, .raw_writefn = ttbr064_raw_write, |
1485 | .resetfn = ttbr064_reset }, | |
891a2fe7 PM |
1486 | { .name = "TTBR1", .cp = 15, .crm = 2, .opc1 = 1, |
1487 | .access = PL1_RW, .type = ARM_CP_64BIT, .readfn = ttbr164_read, | |
1488 | .writefn = ttbr164_write, .resetfn = ttbr164_reset }, | |
7ac681cf PM |
1489 | REGINFO_SENTINEL |
1490 | }; | |
1491 | ||
c4241c7d | 1492 | static uint64_t aa64_fpcr_read(CPUARMState *env, const ARMCPRegInfo *ri) |
b0d2b7d0 | 1493 | { |
c4241c7d | 1494 | return vfp_get_fpcr(env); |
b0d2b7d0 PM |
1495 | } |
1496 | ||
c4241c7d PM |
1497 | static void aa64_fpcr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1498 | uint64_t value) | |
b0d2b7d0 PM |
1499 | { |
1500 | vfp_set_fpcr(env, value); | |
b0d2b7d0 PM |
1501 | } |
1502 | ||
c4241c7d | 1503 | static uint64_t aa64_fpsr_read(CPUARMState *env, const ARMCPRegInfo *ri) |
b0d2b7d0 | 1504 | { |
c4241c7d | 1505 | return vfp_get_fpsr(env); |
b0d2b7d0 PM |
1506 | } |
1507 | ||
c4241c7d PM |
1508 | static void aa64_fpsr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1509 | uint64_t value) | |
b0d2b7d0 PM |
1510 | { |
1511 | vfp_set_fpsr(env, value); | |
b0d2b7d0 PM |
1512 | } |
1513 | ||
1514 | static const ARMCPRegInfo v8_cp_reginfo[] = { | |
1515 | /* Minimal set of EL0-visible registers. This will need to be expanded | |
1516 | * significantly for system emulation of AArch64 CPUs. | |
1517 | */ | |
1518 | { .name = "NZCV", .state = ARM_CP_STATE_AA64, | |
1519 | .opc0 = 3, .opc1 = 3, .opc2 = 0, .crn = 4, .crm = 2, | |
1520 | .access = PL0_RW, .type = ARM_CP_NZCV }, | |
1521 | { .name = "FPCR", .state = ARM_CP_STATE_AA64, | |
1522 | .opc0 = 3, .opc1 = 3, .opc2 = 0, .crn = 4, .crm = 4, | |
1523 | .access = PL0_RW, .readfn = aa64_fpcr_read, .writefn = aa64_fpcr_write }, | |
1524 | { .name = "FPSR", .state = ARM_CP_STATE_AA64, | |
1525 | .opc0 = 3, .opc1 = 3, .opc2 = 1, .crn = 4, .crm = 4, | |
1526 | .access = PL0_RW, .readfn = aa64_fpsr_read, .writefn = aa64_fpsr_write }, | |
1527 | /* This claims a 32 byte cacheline size for icache and dcache, VIPT icache. | |
1528 | * It will eventually need to have a CPU-specified reset value. | |
1529 | */ | |
1530 | { .name = "CTR_EL0", .state = ARM_CP_STATE_AA64, | |
1531 | .opc0 = 3, .opc1 = 3, .opc2 = 1, .crn = 0, .crm = 0, | |
1532 | .access = PL0_R, .type = ARM_CP_CONST, | |
1533 | .resetvalue = 0x80030003 }, | |
1534 | /* Prohibit use of DC ZVA. OPTME: implement DC ZVA and allow its use. | |
1535 | * For system mode the DZP bit here will need to be computed, not constant. | |
1536 | */ | |
1537 | { .name = "DCZID_EL0", .state = ARM_CP_STATE_AA64, | |
1538 | .opc0 = 3, .opc1 = 3, .opc2 = 7, .crn = 0, .crm = 0, | |
1539 | .access = PL0_R, .type = ARM_CP_CONST, | |
1540 | .resetvalue = 0x10 }, | |
1541 | REGINFO_SENTINEL | |
1542 | }; | |
1543 | ||
c4241c7d PM |
1544 | static void sctlr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1545 | uint64_t value) | |
2771db27 PM |
1546 | { |
1547 | env->cp15.c1_sys = value; | |
1548 | /* ??? Lots of these bits are not implemented. */ | |
1549 | /* This may enable/disable the MMU, so do a TLB flush. */ | |
1550 | tlb_flush(env, 1); | |
2771db27 PM |
1551 | } |
1552 | ||
2ceb98c0 PM |
1553 | void register_cp_regs_for_features(ARMCPU *cpu) |
1554 | { | |
1555 | /* Register all the coprocessor registers based on feature bits */ | |
1556 | CPUARMState *env = &cpu->env; | |
1557 | if (arm_feature(env, ARM_FEATURE_M)) { | |
1558 | /* M profile has no coprocessor registers */ | |
1559 | return; | |
1560 | } | |
1561 | ||
e9aa6c21 | 1562 | define_arm_cp_regs(cpu, cp_reginfo); |
7d57f408 | 1563 | if (arm_feature(env, ARM_FEATURE_V6)) { |
8515a092 PM |
1564 | /* The ID registers all have impdef reset values */ |
1565 | ARMCPRegInfo v6_idregs[] = { | |
1566 | { .name = "ID_PFR0", .cp = 15, .crn = 0, .crm = 1, | |
1567 | .opc1 = 0, .opc2 = 0, .access = PL1_R, .type = ARM_CP_CONST, | |
1568 | .resetvalue = cpu->id_pfr0 }, | |
1569 | { .name = "ID_PFR1", .cp = 15, .crn = 0, .crm = 1, | |
1570 | .opc1 = 0, .opc2 = 1, .access = PL1_R, .type = ARM_CP_CONST, | |
1571 | .resetvalue = cpu->id_pfr1 }, | |
1572 | { .name = "ID_DFR0", .cp = 15, .crn = 0, .crm = 1, | |
1573 | .opc1 = 0, .opc2 = 2, .access = PL1_R, .type = ARM_CP_CONST, | |
1574 | .resetvalue = cpu->id_dfr0 }, | |
1575 | { .name = "ID_AFR0", .cp = 15, .crn = 0, .crm = 1, | |
1576 | .opc1 = 0, .opc2 = 3, .access = PL1_R, .type = ARM_CP_CONST, | |
1577 | .resetvalue = cpu->id_afr0 }, | |
1578 | { .name = "ID_MMFR0", .cp = 15, .crn = 0, .crm = 1, | |
1579 | .opc1 = 0, .opc2 = 4, .access = PL1_R, .type = ARM_CP_CONST, | |
1580 | .resetvalue = cpu->id_mmfr0 }, | |
1581 | { .name = "ID_MMFR1", .cp = 15, .crn = 0, .crm = 1, | |
1582 | .opc1 = 0, .opc2 = 5, .access = PL1_R, .type = ARM_CP_CONST, | |
1583 | .resetvalue = cpu->id_mmfr1 }, | |
1584 | { .name = "ID_MMFR2", .cp = 15, .crn = 0, .crm = 1, | |
1585 | .opc1 = 0, .opc2 = 6, .access = PL1_R, .type = ARM_CP_CONST, | |
1586 | .resetvalue = cpu->id_mmfr2 }, | |
1587 | { .name = "ID_MMFR3", .cp = 15, .crn = 0, .crm = 1, | |
1588 | .opc1 = 0, .opc2 = 7, .access = PL1_R, .type = ARM_CP_CONST, | |
1589 | .resetvalue = cpu->id_mmfr3 }, | |
1590 | { .name = "ID_ISAR0", .cp = 15, .crn = 0, .crm = 2, | |
1591 | .opc1 = 0, .opc2 = 0, .access = PL1_R, .type = ARM_CP_CONST, | |
1592 | .resetvalue = cpu->id_isar0 }, | |
1593 | { .name = "ID_ISAR1", .cp = 15, .crn = 0, .crm = 2, | |
1594 | .opc1 = 0, .opc2 = 1, .access = PL1_R, .type = ARM_CP_CONST, | |
1595 | .resetvalue = cpu->id_isar1 }, | |
1596 | { .name = "ID_ISAR2", .cp = 15, .crn = 0, .crm = 2, | |
1597 | .opc1 = 0, .opc2 = 2, .access = PL1_R, .type = ARM_CP_CONST, | |
1598 | .resetvalue = cpu->id_isar2 }, | |
1599 | { .name = "ID_ISAR3", .cp = 15, .crn = 0, .crm = 2, | |
1600 | .opc1 = 0, .opc2 = 3, .access = PL1_R, .type = ARM_CP_CONST, | |
1601 | .resetvalue = cpu->id_isar3 }, | |
1602 | { .name = "ID_ISAR4", .cp = 15, .crn = 0, .crm = 2, | |
1603 | .opc1 = 0, .opc2 = 4, .access = PL1_R, .type = ARM_CP_CONST, | |
1604 | .resetvalue = cpu->id_isar4 }, | |
1605 | { .name = "ID_ISAR5", .cp = 15, .crn = 0, .crm = 2, | |
1606 | .opc1 = 0, .opc2 = 5, .access = PL1_R, .type = ARM_CP_CONST, | |
1607 | .resetvalue = cpu->id_isar5 }, | |
1608 | /* 6..7 are as yet unallocated and must RAZ */ | |
1609 | { .name = "ID_ISAR6", .cp = 15, .crn = 0, .crm = 2, | |
1610 | .opc1 = 0, .opc2 = 6, .access = PL1_R, .type = ARM_CP_CONST, | |
1611 | .resetvalue = 0 }, | |
1612 | { .name = "ID_ISAR7", .cp = 15, .crn = 0, .crm = 2, | |
1613 | .opc1 = 0, .opc2 = 7, .access = PL1_R, .type = ARM_CP_CONST, | |
1614 | .resetvalue = 0 }, | |
1615 | REGINFO_SENTINEL | |
1616 | }; | |
1617 | define_arm_cp_regs(cpu, v6_idregs); | |
7d57f408 PM |
1618 | define_arm_cp_regs(cpu, v6_cp_reginfo); |
1619 | } else { | |
1620 | define_arm_cp_regs(cpu, not_v6_cp_reginfo); | |
1621 | } | |
4d31c596 PM |
1622 | if (arm_feature(env, ARM_FEATURE_V6K)) { |
1623 | define_arm_cp_regs(cpu, v6k_cp_reginfo); | |
1624 | } | |
e9aa6c21 | 1625 | if (arm_feature(env, ARM_FEATURE_V7)) { |
200ac0ef PM |
1626 | /* v7 performance monitor control register: same implementor |
1627 | * field as main ID register, and we implement no event counters. | |
1628 | */ | |
1629 | ARMCPRegInfo pmcr = { | |
1630 | .name = "PMCR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 0, | |
1631 | .access = PL0_RW, .resetvalue = cpu->midr & 0xff000000, | |
1632 | .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcr), | |
fcd25206 PM |
1633 | .accessfn = pmreg_access, .writefn = pmcr_write, |
1634 | .raw_writefn = raw_write, | |
200ac0ef | 1635 | }; |
776d4e5c PM |
1636 | ARMCPRegInfo clidr = { |
1637 | .name = "CLIDR", .cp = 15, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 1, | |
1638 | .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = cpu->clidr | |
1639 | }; | |
200ac0ef | 1640 | define_one_arm_cp_reg(cpu, &pmcr); |
776d4e5c | 1641 | define_one_arm_cp_reg(cpu, &clidr); |
e9aa6c21 | 1642 | define_arm_cp_regs(cpu, v7_cp_reginfo); |
7d57f408 PM |
1643 | } else { |
1644 | define_arm_cp_regs(cpu, not_v7_cp_reginfo); | |
e9aa6c21 | 1645 | } |
b0d2b7d0 PM |
1646 | if (arm_feature(env, ARM_FEATURE_V8)) { |
1647 | define_arm_cp_regs(cpu, v8_cp_reginfo); | |
1648 | } | |
18032bec PM |
1649 | if (arm_feature(env, ARM_FEATURE_MPU)) { |
1650 | /* These are the MPU registers prior to PMSAv6. Any new | |
1651 | * PMSA core later than the ARM946 will require that we | |
1652 | * implement the PMSAv6 or PMSAv7 registers, which are | |
1653 | * completely different. | |
1654 | */ | |
1655 | assert(!arm_feature(env, ARM_FEATURE_V6)); | |
1656 | define_arm_cp_regs(cpu, pmsav5_cp_reginfo); | |
1657 | } else { | |
1658 | define_arm_cp_regs(cpu, vmsa_cp_reginfo); | |
1659 | } | |
c326b979 PM |
1660 | if (arm_feature(env, ARM_FEATURE_THUMB2EE)) { |
1661 | define_arm_cp_regs(cpu, t2ee_cp_reginfo); | |
1662 | } | |
6cc7a3ae PM |
1663 | if (arm_feature(env, ARM_FEATURE_GENERIC_TIMER)) { |
1664 | define_arm_cp_regs(cpu, generic_timer_cp_reginfo); | |
1665 | } | |
4a501606 PM |
1666 | if (arm_feature(env, ARM_FEATURE_VAPA)) { |
1667 | define_arm_cp_regs(cpu, vapa_cp_reginfo); | |
1668 | } | |
c4804214 PM |
1669 | if (arm_feature(env, ARM_FEATURE_CACHE_TEST_CLEAN)) { |
1670 | define_arm_cp_regs(cpu, cache_test_clean_cp_reginfo); | |
1671 | } | |
1672 | if (arm_feature(env, ARM_FEATURE_CACHE_DIRTY_REG)) { | |
1673 | define_arm_cp_regs(cpu, cache_dirty_status_cp_reginfo); | |
1674 | } | |
1675 | if (arm_feature(env, ARM_FEATURE_CACHE_BLOCK_OPS)) { | |
1676 | define_arm_cp_regs(cpu, cache_block_ops_cp_reginfo); | |
1677 | } | |
18032bec PM |
1678 | if (arm_feature(env, ARM_FEATURE_OMAPCP)) { |
1679 | define_arm_cp_regs(cpu, omap_cp_reginfo); | |
1680 | } | |
34f90529 PM |
1681 | if (arm_feature(env, ARM_FEATURE_STRONGARM)) { |
1682 | define_arm_cp_regs(cpu, strongarm_cp_reginfo); | |
1683 | } | |
1047b9d7 PM |
1684 | if (arm_feature(env, ARM_FEATURE_XSCALE)) { |
1685 | define_arm_cp_regs(cpu, xscale_cp_reginfo); | |
1686 | } | |
1687 | if (arm_feature(env, ARM_FEATURE_DUMMY_C15_REGS)) { | |
1688 | define_arm_cp_regs(cpu, dummy_c15_cp_reginfo); | |
1689 | } | |
7ac681cf PM |
1690 | if (arm_feature(env, ARM_FEATURE_LPAE)) { |
1691 | define_arm_cp_regs(cpu, lpae_cp_reginfo); | |
1692 | } | |
7884849c PM |
1693 | /* Slightly awkwardly, the OMAP and StrongARM cores need all of |
1694 | * cp15 crn=0 to be writes-ignored, whereas for other cores they should | |
1695 | * be read-only (ie write causes UNDEF exception). | |
1696 | */ | |
1697 | { | |
1698 | ARMCPRegInfo id_cp_reginfo[] = { | |
1699 | /* Note that the MIDR isn't a simple constant register because | |
1700 | * of the TI925 behaviour where writes to another register can | |
1701 | * cause the MIDR value to change. | |
97ce8d61 PC |
1702 | * |
1703 | * Unimplemented registers in the c15 0 0 0 space default to | |
1704 | * MIDR. Define MIDR first as this entire space, then CTR, TCMTR | |
1705 | * and friends override accordingly. | |
7884849c PM |
1706 | */ |
1707 | { .name = "MIDR", | |
97ce8d61 | 1708 | .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = CP_ANY, |
7884849c | 1709 | .access = PL1_R, .resetvalue = cpu->midr, |
d4e6df63 | 1710 | .writefn = arm_cp_write_ignore, .raw_writefn = raw_write, |
97ce8d61 PC |
1711 | .fieldoffset = offsetof(CPUARMState, cp15.c0_cpuid), |
1712 | .type = ARM_CP_OVERRIDE }, | |
7884849c PM |
1713 | { .name = "CTR", |
1714 | .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 1, | |
1715 | .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = cpu->ctr }, | |
1716 | { .name = "TCMTR", | |
1717 | .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 2, | |
1718 | .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
1719 | { .name = "TLBTR", | |
1720 | .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 3, | |
1721 | .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
1722 | /* crn = 0 op1 = 0 crm = 3..7 : currently unassigned; we RAZ. */ | |
1723 | { .name = "DUMMY", | |
1724 | .cp = 15, .crn = 0, .crm = 3, .opc1 = 0, .opc2 = CP_ANY, | |
1725 | .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
1726 | { .name = "DUMMY", | |
1727 | .cp = 15, .crn = 0, .crm = 4, .opc1 = 0, .opc2 = CP_ANY, | |
1728 | .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
1729 | { .name = "DUMMY", | |
1730 | .cp = 15, .crn = 0, .crm = 5, .opc1 = 0, .opc2 = CP_ANY, | |
1731 | .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
1732 | { .name = "DUMMY", | |
1733 | .cp = 15, .crn = 0, .crm = 6, .opc1 = 0, .opc2 = CP_ANY, | |
1734 | .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
1735 | { .name = "DUMMY", | |
1736 | .cp = 15, .crn = 0, .crm = 7, .opc1 = 0, .opc2 = CP_ANY, | |
1737 | .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
1738 | REGINFO_SENTINEL | |
1739 | }; | |
1740 | ARMCPRegInfo crn0_wi_reginfo = { | |
1741 | .name = "CRN0_WI", .cp = 15, .crn = 0, .crm = CP_ANY, | |
1742 | .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_W, | |
1743 | .type = ARM_CP_NOP | ARM_CP_OVERRIDE | |
1744 | }; | |
1745 | if (arm_feature(env, ARM_FEATURE_OMAPCP) || | |
1746 | arm_feature(env, ARM_FEATURE_STRONGARM)) { | |
1747 | ARMCPRegInfo *r; | |
1748 | /* Register the blanket "writes ignored" value first to cover the | |
a703eda1 PC |
1749 | * whole space. Then update the specific ID registers to allow write |
1750 | * access, so that they ignore writes rather than causing them to | |
1751 | * UNDEF. | |
7884849c PM |
1752 | */ |
1753 | define_one_arm_cp_reg(cpu, &crn0_wi_reginfo); | |
1754 | for (r = id_cp_reginfo; r->type != ARM_CP_SENTINEL; r++) { | |
1755 | r->access = PL1_RW; | |
7884849c | 1756 | } |
7884849c | 1757 | } |
a703eda1 | 1758 | define_arm_cp_regs(cpu, id_cp_reginfo); |
7884849c PM |
1759 | } |
1760 | ||
97ce8d61 PC |
1761 | if (arm_feature(env, ARM_FEATURE_MPIDR)) { |
1762 | define_arm_cp_regs(cpu, mpidr_cp_reginfo); | |
1763 | } | |
1764 | ||
2771db27 PM |
1765 | if (arm_feature(env, ARM_FEATURE_AUXCR)) { |
1766 | ARMCPRegInfo auxcr = { | |
1767 | .name = "AUXCR", .cp = 15, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 1, | |
1768 | .access = PL1_RW, .type = ARM_CP_CONST, | |
1769 | .resetvalue = cpu->reset_auxcr | |
1770 | }; | |
1771 | define_one_arm_cp_reg(cpu, &auxcr); | |
1772 | } | |
1773 | ||
d8ba780b PC |
1774 | if (arm_feature(env, ARM_FEATURE_CBAR)) { |
1775 | ARMCPRegInfo cbar = { | |
1776 | .name = "CBAR", .cp = 15, .crn = 15, .crm = 0, .opc1 = 4, .opc2 = 0, | |
1777 | .access = PL1_R|PL3_W, .resetvalue = cpu->reset_cbar, | |
1778 | .fieldoffset = offsetof(CPUARMState, cp15.c15_config_base_address) | |
1779 | }; | |
1780 | define_one_arm_cp_reg(cpu, &cbar); | |
1781 | } | |
1782 | ||
2771db27 PM |
1783 | /* Generic registers whose values depend on the implementation */ |
1784 | { | |
1785 | ARMCPRegInfo sctlr = { | |
1786 | .name = "SCTLR", .cp = 15, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 0, | |
1787 | .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c1_sys), | |
d4e6df63 PM |
1788 | .writefn = sctlr_write, .resetvalue = cpu->reset_sctlr, |
1789 | .raw_writefn = raw_write, | |
2771db27 PM |
1790 | }; |
1791 | if (arm_feature(env, ARM_FEATURE_XSCALE)) { | |
1792 | /* Normally we would always end the TB on an SCTLR write, but Linux | |
1793 | * arch/arm/mach-pxa/sleep.S expects two instructions following | |
1794 | * an MMU enable to execute from cache. Imitate this behaviour. | |
1795 | */ | |
1796 | sctlr.type |= ARM_CP_SUPPRESS_TB_END; | |
1797 | } | |
1798 | define_one_arm_cp_reg(cpu, &sctlr); | |
1799 | } | |
2ceb98c0 PM |
1800 | } |
1801 | ||
778c3a06 | 1802 | ARMCPU *cpu_arm_init(const char *cpu_model) |
40f137e1 | 1803 | { |
dec9c2d4 | 1804 | ARMCPU *cpu; |
5900d6b2 | 1805 | ObjectClass *oc; |
40f137e1 | 1806 | |
5900d6b2 AF |
1807 | oc = cpu_class_by_name(TYPE_ARM_CPU, cpu_model); |
1808 | if (!oc) { | |
aaed909a | 1809 | return NULL; |
777dc784 | 1810 | } |
5900d6b2 | 1811 | cpu = ARM_CPU(object_new(object_class_get_name(oc))); |
14969266 AF |
1812 | |
1813 | /* TODO this should be set centrally, once possible */ | |
1814 | object_property_set_bool(OBJECT(cpu), true, "realized", NULL); | |
777dc784 | 1815 | |
14969266 AF |
1816 | return cpu; |
1817 | } | |
1818 | ||
1819 | void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu) | |
1820 | { | |
22169d41 | 1821 | CPUState *cs = CPU(cpu); |
14969266 AF |
1822 | CPUARMState *env = &cpu->env; |
1823 | ||
6a669427 PM |
1824 | if (arm_feature(env, ARM_FEATURE_AARCH64)) { |
1825 | gdb_register_coprocessor(cs, aarch64_fpu_gdb_get_reg, | |
1826 | aarch64_fpu_gdb_set_reg, | |
1827 | 34, "aarch64-fpu.xml", 0); | |
1828 | } else if (arm_feature(env, ARM_FEATURE_NEON)) { | |
22169d41 | 1829 | gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg, |
56aebc89 PB |
1830 | 51, "arm-neon.xml", 0); |
1831 | } else if (arm_feature(env, ARM_FEATURE_VFP3)) { | |
22169d41 | 1832 | gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg, |
56aebc89 PB |
1833 | 35, "arm-vfp3.xml", 0); |
1834 | } else if (arm_feature(env, ARM_FEATURE_VFP)) { | |
22169d41 | 1835 | gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg, |
56aebc89 PB |
1836 | 19, "arm-vfp.xml", 0); |
1837 | } | |
40f137e1 PB |
1838 | } |
1839 | ||
777dc784 PM |
1840 | /* Sort alphabetically by type name, except for "any". */ |
1841 | static gint arm_cpu_list_compare(gconstpointer a, gconstpointer b) | |
5adb4839 | 1842 | { |
777dc784 PM |
1843 | ObjectClass *class_a = (ObjectClass *)a; |
1844 | ObjectClass *class_b = (ObjectClass *)b; | |
1845 | const char *name_a, *name_b; | |
5adb4839 | 1846 | |
777dc784 PM |
1847 | name_a = object_class_get_name(class_a); |
1848 | name_b = object_class_get_name(class_b); | |
51492fd1 | 1849 | if (strcmp(name_a, "any-" TYPE_ARM_CPU) == 0) { |
777dc784 | 1850 | return 1; |
51492fd1 | 1851 | } else if (strcmp(name_b, "any-" TYPE_ARM_CPU) == 0) { |
777dc784 PM |
1852 | return -1; |
1853 | } else { | |
1854 | return strcmp(name_a, name_b); | |
5adb4839 PB |
1855 | } |
1856 | } | |
1857 | ||
777dc784 | 1858 | static void arm_cpu_list_entry(gpointer data, gpointer user_data) |
40f137e1 | 1859 | { |
777dc784 | 1860 | ObjectClass *oc = data; |
92a31361 | 1861 | CPUListState *s = user_data; |
51492fd1 AF |
1862 | const char *typename; |
1863 | char *name; | |
3371d272 | 1864 | |
51492fd1 AF |
1865 | typename = object_class_get_name(oc); |
1866 | name = g_strndup(typename, strlen(typename) - strlen("-" TYPE_ARM_CPU)); | |
777dc784 | 1867 | (*s->cpu_fprintf)(s->file, " %s\n", |
51492fd1 AF |
1868 | name); |
1869 | g_free(name); | |
777dc784 PM |
1870 | } |
1871 | ||
1872 | void arm_cpu_list(FILE *f, fprintf_function cpu_fprintf) | |
1873 | { | |
92a31361 | 1874 | CPUListState s = { |
777dc784 PM |
1875 | .file = f, |
1876 | .cpu_fprintf = cpu_fprintf, | |
1877 | }; | |
1878 | GSList *list; | |
1879 | ||
1880 | list = object_class_get_list(TYPE_ARM_CPU, false); | |
1881 | list = g_slist_sort(list, arm_cpu_list_compare); | |
1882 | (*cpu_fprintf)(f, "Available CPUs:\n"); | |
1883 | g_slist_foreach(list, arm_cpu_list_entry, &s); | |
1884 | g_slist_free(list); | |
a96c0514 PM |
1885 | #ifdef CONFIG_KVM |
1886 | /* The 'host' CPU type is dynamically registered only if KVM is | |
1887 | * enabled, so we have to special-case it here: | |
1888 | */ | |
1889 | (*cpu_fprintf)(f, " host (only available in KVM mode)\n"); | |
1890 | #endif | |
40f137e1 PB |
1891 | } |
1892 | ||
78027bb6 CR |
1893 | static void arm_cpu_add_definition(gpointer data, gpointer user_data) |
1894 | { | |
1895 | ObjectClass *oc = data; | |
1896 | CpuDefinitionInfoList **cpu_list = user_data; | |
1897 | CpuDefinitionInfoList *entry; | |
1898 | CpuDefinitionInfo *info; | |
1899 | const char *typename; | |
1900 | ||
1901 | typename = object_class_get_name(oc); | |
1902 | info = g_malloc0(sizeof(*info)); | |
1903 | info->name = g_strndup(typename, | |
1904 | strlen(typename) - strlen("-" TYPE_ARM_CPU)); | |
1905 | ||
1906 | entry = g_malloc0(sizeof(*entry)); | |
1907 | entry->value = info; | |
1908 | entry->next = *cpu_list; | |
1909 | *cpu_list = entry; | |
1910 | } | |
1911 | ||
1912 | CpuDefinitionInfoList *arch_query_cpu_definitions(Error **errp) | |
1913 | { | |
1914 | CpuDefinitionInfoList *cpu_list = NULL; | |
1915 | GSList *list; | |
1916 | ||
1917 | list = object_class_get_list(TYPE_ARM_CPU, false); | |
1918 | g_slist_foreach(list, arm_cpu_add_definition, &cpu_list); | |
1919 | g_slist_free(list); | |
1920 | ||
1921 | return cpu_list; | |
1922 | } | |
1923 | ||
6e6efd61 | 1924 | static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r, |
f5a0a5a5 PM |
1925 | void *opaque, int state, |
1926 | int crm, int opc1, int opc2) | |
6e6efd61 PM |
1927 | { |
1928 | /* Private utility function for define_one_arm_cp_reg_with_opaque(): | |
1929 | * add a single reginfo struct to the hash table. | |
1930 | */ | |
1931 | uint32_t *key = g_new(uint32_t, 1); | |
1932 | ARMCPRegInfo *r2 = g_memdup(r, sizeof(ARMCPRegInfo)); | |
1933 | int is64 = (r->type & ARM_CP_64BIT) ? 1 : 0; | |
f5a0a5a5 PM |
1934 | if (r->state == ARM_CP_STATE_BOTH && state == ARM_CP_STATE_AA32) { |
1935 | /* The AArch32 view of a shared register sees the lower 32 bits | |
1936 | * of a 64 bit backing field. It is not migratable as the AArch64 | |
1937 | * view handles that. AArch64 also handles reset. | |
1938 | * We assume it is a cp15 register. | |
1939 | */ | |
1940 | r2->cp = 15; | |
1941 | r2->type |= ARM_CP_NO_MIGRATE; | |
1942 | r2->resetfn = arm_cp_reset_ignore; | |
1943 | #ifdef HOST_WORDS_BIGENDIAN | |
1944 | if (r2->fieldoffset) { | |
1945 | r2->fieldoffset += sizeof(uint32_t); | |
1946 | } | |
1947 | #endif | |
1948 | } | |
1949 | if (state == ARM_CP_STATE_AA64) { | |
1950 | /* To allow abbreviation of ARMCPRegInfo | |
1951 | * definitions, we treat cp == 0 as equivalent to | |
1952 | * the value for "standard guest-visible sysreg". | |
1953 | */ | |
1954 | if (r->cp == 0) { | |
1955 | r2->cp = CP_REG_ARM64_SYSREG_CP; | |
1956 | } | |
1957 | *key = ENCODE_AA64_CP_REG(r2->cp, r2->crn, crm, | |
1958 | r2->opc0, opc1, opc2); | |
1959 | } else { | |
1960 | *key = ENCODE_CP_REG(r2->cp, is64, r2->crn, crm, opc1, opc2); | |
1961 | } | |
6e6efd61 PM |
1962 | if (opaque) { |
1963 | r2->opaque = opaque; | |
1964 | } | |
1965 | /* Make sure reginfo passed to helpers for wildcarded regs | |
1966 | * has the correct crm/opc1/opc2 for this reg, not CP_ANY: | |
1967 | */ | |
1968 | r2->crm = crm; | |
1969 | r2->opc1 = opc1; | |
1970 | r2->opc2 = opc2; | |
1971 | /* By convention, for wildcarded registers only the first | |
1972 | * entry is used for migration; the others are marked as | |
1973 | * NO_MIGRATE so we don't try to transfer the register | |
1974 | * multiple times. Special registers (ie NOP/WFI) are | |
1975 | * never migratable. | |
1976 | */ | |
1977 | if ((r->type & ARM_CP_SPECIAL) || | |
1978 | ((r->crm == CP_ANY) && crm != 0) || | |
1979 | ((r->opc1 == CP_ANY) && opc1 != 0) || | |
1980 | ((r->opc2 == CP_ANY) && opc2 != 0)) { | |
1981 | r2->type |= ARM_CP_NO_MIGRATE; | |
1982 | } | |
1983 | ||
1984 | /* Overriding of an existing definition must be explicitly | |
1985 | * requested. | |
1986 | */ | |
1987 | if (!(r->type & ARM_CP_OVERRIDE)) { | |
1988 | ARMCPRegInfo *oldreg; | |
1989 | oldreg = g_hash_table_lookup(cpu->cp_regs, key); | |
1990 | if (oldreg && !(oldreg->type & ARM_CP_OVERRIDE)) { | |
1991 | fprintf(stderr, "Register redefined: cp=%d %d bit " | |
1992 | "crn=%d crm=%d opc1=%d opc2=%d, " | |
1993 | "was %s, now %s\n", r2->cp, 32 + 32 * is64, | |
1994 | r2->crn, r2->crm, r2->opc1, r2->opc2, | |
1995 | oldreg->name, r2->name); | |
1996 | g_assert_not_reached(); | |
1997 | } | |
1998 | } | |
1999 | g_hash_table_insert(cpu->cp_regs, key, r2); | |
2000 | } | |
2001 | ||
2002 | ||
4b6a83fb PM |
2003 | void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu, |
2004 | const ARMCPRegInfo *r, void *opaque) | |
2005 | { | |
2006 | /* Define implementations of coprocessor registers. | |
2007 | * We store these in a hashtable because typically | |
2008 | * there are less than 150 registers in a space which | |
2009 | * is 16*16*16*8*8 = 262144 in size. | |
2010 | * Wildcarding is supported for the crm, opc1 and opc2 fields. | |
2011 | * If a register is defined twice then the second definition is | |
2012 | * used, so this can be used to define some generic registers and | |
2013 | * then override them with implementation specific variations. | |
2014 | * At least one of the original and the second definition should | |
2015 | * include ARM_CP_OVERRIDE in its type bits -- this is just a guard | |
2016 | * against accidental use. | |
f5a0a5a5 PM |
2017 | * |
2018 | * The state field defines whether the register is to be | |
2019 | * visible in the AArch32 or AArch64 execution state. If the | |
2020 | * state is set to ARM_CP_STATE_BOTH then we synthesise a | |
2021 | * reginfo structure for the AArch32 view, which sees the lower | |
2022 | * 32 bits of the 64 bit register. | |
2023 | * | |
2024 | * Only registers visible in AArch64 may set r->opc0; opc0 cannot | |
2025 | * be wildcarded. AArch64 registers are always considered to be 64 | |
2026 | * bits; the ARM_CP_64BIT* flag applies only to the AArch32 view of | |
2027 | * the register, if any. | |
4b6a83fb | 2028 | */ |
f5a0a5a5 | 2029 | int crm, opc1, opc2, state; |
4b6a83fb PM |
2030 | int crmmin = (r->crm == CP_ANY) ? 0 : r->crm; |
2031 | int crmmax = (r->crm == CP_ANY) ? 15 : r->crm; | |
2032 | int opc1min = (r->opc1 == CP_ANY) ? 0 : r->opc1; | |
2033 | int opc1max = (r->opc1 == CP_ANY) ? 7 : r->opc1; | |
2034 | int opc2min = (r->opc2 == CP_ANY) ? 0 : r->opc2; | |
2035 | int opc2max = (r->opc2 == CP_ANY) ? 7 : r->opc2; | |
2036 | /* 64 bit registers have only CRm and Opc1 fields */ | |
2037 | assert(!((r->type & ARM_CP_64BIT) && (r->opc2 || r->crn))); | |
f5a0a5a5 PM |
2038 | /* op0 only exists in the AArch64 encodings */ |
2039 | assert((r->state != ARM_CP_STATE_AA32) || (r->opc0 == 0)); | |
2040 | /* AArch64 regs are all 64 bit so ARM_CP_64BIT is meaningless */ | |
2041 | assert((r->state != ARM_CP_STATE_AA64) || !(r->type & ARM_CP_64BIT)); | |
2042 | /* The AArch64 pseudocode CheckSystemAccess() specifies that op1 | |
2043 | * encodes a minimum access level for the register. We roll this | |
2044 | * runtime check into our general permission check code, so check | |
2045 | * here that the reginfo's specified permissions are strict enough | |
2046 | * to encompass the generic architectural permission check. | |
2047 | */ | |
2048 | if (r->state != ARM_CP_STATE_AA32) { | |
2049 | int mask = 0; | |
2050 | switch (r->opc1) { | |
2051 | case 0: case 1: case 2: | |
2052 | /* min_EL EL1 */ | |
2053 | mask = PL1_RW; | |
2054 | break; | |
2055 | case 3: | |
2056 | /* min_EL EL0 */ | |
2057 | mask = PL0_RW; | |
2058 | break; | |
2059 | case 4: | |
2060 | /* min_EL EL2 */ | |
2061 | mask = PL2_RW; | |
2062 | break; | |
2063 | case 5: | |
2064 | /* unallocated encoding, so not possible */ | |
2065 | assert(false); | |
2066 | break; | |
2067 | case 6: | |
2068 | /* min_EL EL3 */ | |
2069 | mask = PL3_RW; | |
2070 | break; | |
2071 | case 7: | |
2072 | /* min_EL EL1, secure mode only (we don't check the latter) */ | |
2073 | mask = PL1_RW; | |
2074 | break; | |
2075 | default: | |
2076 | /* broken reginfo with out-of-range opc1 */ | |
2077 | assert(false); | |
2078 | break; | |
2079 | } | |
2080 | /* assert our permissions are not too lax (stricter is fine) */ | |
2081 | assert((r->access & ~mask) == 0); | |
2082 | } | |
2083 | ||
4b6a83fb PM |
2084 | /* Check that the register definition has enough info to handle |
2085 | * reads and writes if they are permitted. | |
2086 | */ | |
2087 | if (!(r->type & (ARM_CP_SPECIAL|ARM_CP_CONST))) { | |
2088 | if (r->access & PL3_R) { | |
2089 | assert(r->fieldoffset || r->readfn); | |
2090 | } | |
2091 | if (r->access & PL3_W) { | |
2092 | assert(r->fieldoffset || r->writefn); | |
2093 | } | |
2094 | } | |
2095 | /* Bad type field probably means missing sentinel at end of reg list */ | |
2096 | assert(cptype_valid(r->type)); | |
2097 | for (crm = crmmin; crm <= crmmax; crm++) { | |
2098 | for (opc1 = opc1min; opc1 <= opc1max; opc1++) { | |
2099 | for (opc2 = opc2min; opc2 <= opc2max; opc2++) { | |
f5a0a5a5 PM |
2100 | for (state = ARM_CP_STATE_AA32; |
2101 | state <= ARM_CP_STATE_AA64; state++) { | |
2102 | if (r->state != state && r->state != ARM_CP_STATE_BOTH) { | |
2103 | continue; | |
2104 | } | |
2105 | add_cpreg_to_hashtable(cpu, r, opaque, state, | |
2106 | crm, opc1, opc2); | |
2107 | } | |
4b6a83fb PM |
2108 | } |
2109 | } | |
2110 | } | |
2111 | } | |
2112 | ||
2113 | void define_arm_cp_regs_with_opaque(ARMCPU *cpu, | |
2114 | const ARMCPRegInfo *regs, void *opaque) | |
2115 | { | |
2116 | /* Define a whole list of registers */ | |
2117 | const ARMCPRegInfo *r; | |
2118 | for (r = regs; r->type != ARM_CP_SENTINEL; r++) { | |
2119 | define_one_arm_cp_reg_with_opaque(cpu, r, opaque); | |
2120 | } | |
2121 | } | |
2122 | ||
60322b39 | 2123 | const ARMCPRegInfo *get_arm_cp_reginfo(GHashTable *cpregs, uint32_t encoded_cp) |
4b6a83fb | 2124 | { |
60322b39 | 2125 | return g_hash_table_lookup(cpregs, &encoded_cp); |
4b6a83fb PM |
2126 | } |
2127 | ||
c4241c7d PM |
2128 | void arm_cp_write_ignore(CPUARMState *env, const ARMCPRegInfo *ri, |
2129 | uint64_t value) | |
4b6a83fb PM |
2130 | { |
2131 | /* Helper coprocessor write function for write-ignore registers */ | |
4b6a83fb PM |
2132 | } |
2133 | ||
c4241c7d | 2134 | uint64_t arm_cp_read_zero(CPUARMState *env, const ARMCPRegInfo *ri) |
4b6a83fb PM |
2135 | { |
2136 | /* Helper coprocessor write function for read-as-zero registers */ | |
4b6a83fb PM |
2137 | return 0; |
2138 | } | |
2139 | ||
f5a0a5a5 PM |
2140 | void arm_cp_reset_ignore(CPUARMState *env, const ARMCPRegInfo *opaque) |
2141 | { | |
2142 | /* Helper coprocessor reset function for do-nothing-on-reset registers */ | |
2143 | } | |
2144 | ||
0ecb72a5 | 2145 | static int bad_mode_switch(CPUARMState *env, int mode) |
37064a8b PM |
2146 | { |
2147 | /* Return true if it is not valid for us to switch to | |
2148 | * this CPU mode (ie all the UNPREDICTABLE cases in | |
2149 | * the ARM ARM CPSRWriteByInstr pseudocode). | |
2150 | */ | |
2151 | switch (mode) { | |
2152 | case ARM_CPU_MODE_USR: | |
2153 | case ARM_CPU_MODE_SYS: | |
2154 | case ARM_CPU_MODE_SVC: | |
2155 | case ARM_CPU_MODE_ABT: | |
2156 | case ARM_CPU_MODE_UND: | |
2157 | case ARM_CPU_MODE_IRQ: | |
2158 | case ARM_CPU_MODE_FIQ: | |
2159 | return 0; | |
2160 | default: | |
2161 | return 1; | |
2162 | } | |
2163 | } | |
2164 | ||
2f4a40e5 AZ |
2165 | uint32_t cpsr_read(CPUARMState *env) |
2166 | { | |
2167 | int ZF; | |
6fbe23d5 PB |
2168 | ZF = (env->ZF == 0); |
2169 | return env->uncached_cpsr | (env->NF & 0x80000000) | (ZF << 30) | | |
2f4a40e5 AZ |
2170 | (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27) |
2171 | | (env->thumb << 5) | ((env->condexec_bits & 3) << 25) | |
2172 | | ((env->condexec_bits & 0xfc) << 8) | |
2173 | | (env->GE << 16); | |
2174 | } | |
2175 | ||
2176 | void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask) | |
2177 | { | |
2f4a40e5 | 2178 | if (mask & CPSR_NZCV) { |
6fbe23d5 PB |
2179 | env->ZF = (~val) & CPSR_Z; |
2180 | env->NF = val; | |
2f4a40e5 AZ |
2181 | env->CF = (val >> 29) & 1; |
2182 | env->VF = (val << 3) & 0x80000000; | |
2183 | } | |
2184 | if (mask & CPSR_Q) | |
2185 | env->QF = ((val & CPSR_Q) != 0); | |
2186 | if (mask & CPSR_T) | |
2187 | env->thumb = ((val & CPSR_T) != 0); | |
2188 | if (mask & CPSR_IT_0_1) { | |
2189 | env->condexec_bits &= ~3; | |
2190 | env->condexec_bits |= (val >> 25) & 3; | |
2191 | } | |
2192 | if (mask & CPSR_IT_2_7) { | |
2193 | env->condexec_bits &= 3; | |
2194 | env->condexec_bits |= (val >> 8) & 0xfc; | |
2195 | } | |
2196 | if (mask & CPSR_GE) { | |
2197 | env->GE = (val >> 16) & 0xf; | |
2198 | } | |
2199 | ||
2200 | if ((env->uncached_cpsr ^ val) & mask & CPSR_M) { | |
37064a8b PM |
2201 | if (bad_mode_switch(env, val & CPSR_M)) { |
2202 | /* Attempt to switch to an invalid mode: this is UNPREDICTABLE. | |
2203 | * We choose to ignore the attempt and leave the CPSR M field | |
2204 | * untouched. | |
2205 | */ | |
2206 | mask &= ~CPSR_M; | |
2207 | } else { | |
2208 | switch_mode(env, val & CPSR_M); | |
2209 | } | |
2f4a40e5 AZ |
2210 | } |
2211 | mask &= ~CACHED_CPSR_BITS; | |
2212 | env->uncached_cpsr = (env->uncached_cpsr & ~mask) | (val & mask); | |
2213 | } | |
2214 | ||
b26eefb6 PB |
2215 | /* Sign/zero extend */ |
2216 | uint32_t HELPER(sxtb16)(uint32_t x) | |
2217 | { | |
2218 | uint32_t res; | |
2219 | res = (uint16_t)(int8_t)x; | |
2220 | res |= (uint32_t)(int8_t)(x >> 16) << 16; | |
2221 | return res; | |
2222 | } | |
2223 | ||
2224 | uint32_t HELPER(uxtb16)(uint32_t x) | |
2225 | { | |
2226 | uint32_t res; | |
2227 | res = (uint16_t)(uint8_t)x; | |
2228 | res |= (uint32_t)(uint8_t)(x >> 16) << 16; | |
2229 | return res; | |
2230 | } | |
2231 | ||
f51bbbfe PB |
2232 | uint32_t HELPER(clz)(uint32_t x) |
2233 | { | |
7bbcb0af | 2234 | return clz32(x); |
f51bbbfe PB |
2235 | } |
2236 | ||
3670669c PB |
2237 | int32_t HELPER(sdiv)(int32_t num, int32_t den) |
2238 | { | |
2239 | if (den == 0) | |
2240 | return 0; | |
686eeb93 AJ |
2241 | if (num == INT_MIN && den == -1) |
2242 | return INT_MIN; | |
3670669c PB |
2243 | return num / den; |
2244 | } | |
2245 | ||
2246 | uint32_t HELPER(udiv)(uint32_t num, uint32_t den) | |
2247 | { | |
2248 | if (den == 0) | |
2249 | return 0; | |
2250 | return num / den; | |
2251 | } | |
2252 | ||
2253 | uint32_t HELPER(rbit)(uint32_t x) | |
2254 | { | |
2255 | x = ((x & 0xff000000) >> 24) | |
2256 | | ((x & 0x00ff0000) >> 8) | |
2257 | | ((x & 0x0000ff00) << 8) | |
2258 | | ((x & 0x000000ff) << 24); | |
2259 | x = ((x & 0xf0f0f0f0) >> 4) | |
2260 | | ((x & 0x0f0f0f0f) << 4); | |
2261 | x = ((x & 0x88888888) >> 3) | |
2262 | | ((x & 0x44444444) >> 1) | |
2263 | | ((x & 0x22222222) << 1) | |
2264 | | ((x & 0x11111111) << 3); | |
2265 | return x; | |
2266 | } | |
2267 | ||
5fafdf24 | 2268 | #if defined(CONFIG_USER_ONLY) |
b5ff1b31 | 2269 | |
97a8ea5a | 2270 | void arm_cpu_do_interrupt(CPUState *cs) |
b5ff1b31 | 2271 | { |
97a8ea5a AF |
2272 | ARMCPU *cpu = ARM_CPU(cs); |
2273 | CPUARMState *env = &cpu->env; | |
2274 | ||
b5ff1b31 FB |
2275 | env->exception_index = -1; |
2276 | } | |
2277 | ||
0ecb72a5 | 2278 | int cpu_arm_handle_mmu_fault (CPUARMState *env, target_ulong address, int rw, |
97b348e7 | 2279 | int mmu_idx) |
b5ff1b31 FB |
2280 | { |
2281 | if (rw == 2) { | |
2282 | env->exception_index = EXCP_PREFETCH_ABORT; | |
2283 | env->cp15.c6_insn = address; | |
2284 | } else { | |
2285 | env->exception_index = EXCP_DATA_ABORT; | |
2286 | env->cp15.c6_data = address; | |
2287 | } | |
2288 | return 1; | |
2289 | } | |
2290 | ||
9ee6e8bb | 2291 | /* These should probably raise undefined insn exceptions. */ |
0ecb72a5 | 2292 | void HELPER(v7m_msr)(CPUARMState *env, uint32_t reg, uint32_t val) |
9ee6e8bb PB |
2293 | { |
2294 | cpu_abort(env, "v7m_mrs %d\n", reg); | |
2295 | } | |
2296 | ||
0ecb72a5 | 2297 | uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg) |
9ee6e8bb PB |
2298 | { |
2299 | cpu_abort(env, "v7m_mrs %d\n", reg); | |
2300 | return 0; | |
2301 | } | |
2302 | ||
0ecb72a5 | 2303 | void switch_mode(CPUARMState *env, int mode) |
b5ff1b31 FB |
2304 | { |
2305 | if (mode != ARM_CPU_MODE_USR) | |
2306 | cpu_abort(env, "Tried to switch out of user mode\n"); | |
2307 | } | |
2308 | ||
0ecb72a5 | 2309 | void HELPER(set_r13_banked)(CPUARMState *env, uint32_t mode, uint32_t val) |
9ee6e8bb PB |
2310 | { |
2311 | cpu_abort(env, "banked r13 write\n"); | |
2312 | } | |
2313 | ||
0ecb72a5 | 2314 | uint32_t HELPER(get_r13_banked)(CPUARMState *env, uint32_t mode) |
9ee6e8bb PB |
2315 | { |
2316 | cpu_abort(env, "banked r13 read\n"); | |
2317 | return 0; | |
2318 | } | |
2319 | ||
b5ff1b31 FB |
2320 | #else |
2321 | ||
2322 | /* Map CPU modes onto saved register banks. */ | |
494b00c7 | 2323 | int bank_number(int mode) |
b5ff1b31 FB |
2324 | { |
2325 | switch (mode) { | |
2326 | case ARM_CPU_MODE_USR: | |
2327 | case ARM_CPU_MODE_SYS: | |
2328 | return 0; | |
2329 | case ARM_CPU_MODE_SVC: | |
2330 | return 1; | |
2331 | case ARM_CPU_MODE_ABT: | |
2332 | return 2; | |
2333 | case ARM_CPU_MODE_UND: | |
2334 | return 3; | |
2335 | case ARM_CPU_MODE_IRQ: | |
2336 | return 4; | |
2337 | case ARM_CPU_MODE_FIQ: | |
2338 | return 5; | |
2339 | } | |
f5206413 | 2340 | hw_error("bank number requested for bad CPSR mode value 0x%x\n", mode); |
b5ff1b31 FB |
2341 | } |
2342 | ||
0ecb72a5 | 2343 | void switch_mode(CPUARMState *env, int mode) |
b5ff1b31 FB |
2344 | { |
2345 | int old_mode; | |
2346 | int i; | |
2347 | ||
2348 | old_mode = env->uncached_cpsr & CPSR_M; | |
2349 | if (mode == old_mode) | |
2350 | return; | |
2351 | ||
2352 | if (old_mode == ARM_CPU_MODE_FIQ) { | |
2353 | memcpy (env->fiq_regs, env->regs + 8, 5 * sizeof(uint32_t)); | |
8637c67f | 2354 | memcpy (env->regs + 8, env->usr_regs, 5 * sizeof(uint32_t)); |
b5ff1b31 FB |
2355 | } else if (mode == ARM_CPU_MODE_FIQ) { |
2356 | memcpy (env->usr_regs, env->regs + 8, 5 * sizeof(uint32_t)); | |
8637c67f | 2357 | memcpy (env->regs + 8, env->fiq_regs, 5 * sizeof(uint32_t)); |
b5ff1b31 FB |
2358 | } |
2359 | ||
f5206413 | 2360 | i = bank_number(old_mode); |
b5ff1b31 FB |
2361 | env->banked_r13[i] = env->regs[13]; |
2362 | env->banked_r14[i] = env->regs[14]; | |
2363 | env->banked_spsr[i] = env->spsr; | |
2364 | ||
f5206413 | 2365 | i = bank_number(mode); |
b5ff1b31 FB |
2366 | env->regs[13] = env->banked_r13[i]; |
2367 | env->regs[14] = env->banked_r14[i]; | |
2368 | env->spsr = env->banked_spsr[i]; | |
2369 | } | |
2370 | ||
9ee6e8bb PB |
2371 | static void v7m_push(CPUARMState *env, uint32_t val) |
2372 | { | |
ab1da857 | 2373 | CPUState *cs = ENV_GET_CPU(env); |
9ee6e8bb | 2374 | env->regs[13] -= 4; |
ab1da857 | 2375 | stl_phys(cs->as, env->regs[13], val); |
9ee6e8bb PB |
2376 | } |
2377 | ||
2378 | static uint32_t v7m_pop(CPUARMState *env) | |
2379 | { | |
fdfba1a2 | 2380 | CPUState *cs = ENV_GET_CPU(env); |
9ee6e8bb | 2381 | uint32_t val; |
fdfba1a2 | 2382 | val = ldl_phys(cs->as, env->regs[13]); |
9ee6e8bb PB |
2383 | env->regs[13] += 4; |
2384 | return val; | |
2385 | } | |
2386 | ||
2387 | /* Switch to V7M main or process stack pointer. */ | |
2388 | static void switch_v7m_sp(CPUARMState *env, int process) | |
2389 | { | |
2390 | uint32_t tmp; | |
2391 | if (env->v7m.current_sp != process) { | |
2392 | tmp = env->v7m.other_sp; | |
2393 | env->v7m.other_sp = env->regs[13]; | |
2394 | env->regs[13] = tmp; | |
2395 | env->v7m.current_sp = process; | |
2396 | } | |
2397 | } | |
2398 | ||
2399 | static void do_v7m_exception_exit(CPUARMState *env) | |
2400 | { | |
2401 | uint32_t type; | |
2402 | uint32_t xpsr; | |
2403 | ||
2404 | type = env->regs[15]; | |
2405 | if (env->v7m.exception != 0) | |
983fe826 | 2406 | armv7m_nvic_complete_irq(env->nvic, env->v7m.exception); |
9ee6e8bb PB |
2407 | |
2408 | /* Switch to the target stack. */ | |
2409 | switch_v7m_sp(env, (type & 4) != 0); | |
2410 | /* Pop registers. */ | |
2411 | env->regs[0] = v7m_pop(env); | |
2412 | env->regs[1] = v7m_pop(env); | |
2413 | env->regs[2] = v7m_pop(env); | |
2414 | env->regs[3] = v7m_pop(env); | |
2415 | env->regs[12] = v7m_pop(env); | |
2416 | env->regs[14] = v7m_pop(env); | |
2417 | env->regs[15] = v7m_pop(env); | |
2418 | xpsr = v7m_pop(env); | |
2419 | xpsr_write(env, xpsr, 0xfffffdff); | |
2420 | /* Undo stack alignment. */ | |
2421 | if (xpsr & 0x200) | |
2422 | env->regs[13] |= 4; | |
2423 | /* ??? The exception return type specifies Thread/Handler mode. However | |
2424 | this is also implied by the xPSR value. Not sure what to do | |
2425 | if there is a mismatch. */ | |
2426 | /* ??? Likewise for mismatches between the CONTROL register and the stack | |
2427 | pointer. */ | |
2428 | } | |
2429 | ||
3f1beaca PM |
2430 | /* Exception names for debug logging; note that not all of these |
2431 | * precisely correspond to architectural exceptions. | |
2432 | */ | |
2433 | static const char * const excnames[] = { | |
2434 | [EXCP_UDEF] = "Undefined Instruction", | |
2435 | [EXCP_SWI] = "SVC", | |
2436 | [EXCP_PREFETCH_ABORT] = "Prefetch Abort", | |
2437 | [EXCP_DATA_ABORT] = "Data Abort", | |
2438 | [EXCP_IRQ] = "IRQ", | |
2439 | [EXCP_FIQ] = "FIQ", | |
2440 | [EXCP_BKPT] = "Breakpoint", | |
2441 | [EXCP_EXCEPTION_EXIT] = "QEMU v7M exception exit", | |
2442 | [EXCP_KERNEL_TRAP] = "QEMU intercept of kernel commpage", | |
2443 | [EXCP_STREX] = "QEMU intercept of STREX", | |
2444 | }; | |
2445 | ||
2446 | static inline void arm_log_exception(int idx) | |
2447 | { | |
2448 | if (qemu_loglevel_mask(CPU_LOG_INT)) { | |
2449 | const char *exc = NULL; | |
2450 | ||
2451 | if (idx >= 0 && idx < ARRAY_SIZE(excnames)) { | |
2452 | exc = excnames[idx]; | |
2453 | } | |
2454 | if (!exc) { | |
2455 | exc = "unknown"; | |
2456 | } | |
2457 | qemu_log_mask(CPU_LOG_INT, "Taking exception %d [%s]\n", idx, exc); | |
2458 | } | |
2459 | } | |
2460 | ||
e6f010cc | 2461 | void arm_v7m_cpu_do_interrupt(CPUState *cs) |
9ee6e8bb | 2462 | { |
e6f010cc AF |
2463 | ARMCPU *cpu = ARM_CPU(cs); |
2464 | CPUARMState *env = &cpu->env; | |
9ee6e8bb PB |
2465 | uint32_t xpsr = xpsr_read(env); |
2466 | uint32_t lr; | |
2467 | uint32_t addr; | |
2468 | ||
3f1beaca PM |
2469 | arm_log_exception(env->exception_index); |
2470 | ||
9ee6e8bb PB |
2471 | lr = 0xfffffff1; |
2472 | if (env->v7m.current_sp) | |
2473 | lr |= 4; | |
2474 | if (env->v7m.exception == 0) | |
2475 | lr |= 8; | |
2476 | ||
2477 | /* For exceptions we just mark as pending on the NVIC, and let that | |
2478 | handle it. */ | |
2479 | /* TODO: Need to escalate if the current priority is higher than the | |
2480 | one we're raising. */ | |
2481 | switch (env->exception_index) { | |
2482 | case EXCP_UDEF: | |
983fe826 | 2483 | armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE); |
9ee6e8bb PB |
2484 | return; |
2485 | case EXCP_SWI: | |
314e2296 | 2486 | /* The PC already points to the next instruction. */ |
983fe826 | 2487 | armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_SVC); |
9ee6e8bb PB |
2488 | return; |
2489 | case EXCP_PREFETCH_ABORT: | |
2490 | case EXCP_DATA_ABORT: | |
983fe826 | 2491 | armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_MEM); |
9ee6e8bb PB |
2492 | return; |
2493 | case EXCP_BKPT: | |
2ad207d4 PB |
2494 | if (semihosting_enabled) { |
2495 | int nr; | |
d31dd73e | 2496 | nr = arm_lduw_code(env, env->regs[15], env->bswap_code) & 0xff; |
2ad207d4 PB |
2497 | if (nr == 0xab) { |
2498 | env->regs[15] += 2; | |
2499 | env->regs[0] = do_arm_semihosting(env); | |
3f1beaca | 2500 | qemu_log_mask(CPU_LOG_INT, "...handled as semihosting call\n"); |
2ad207d4 PB |
2501 | return; |
2502 | } | |
2503 | } | |
983fe826 | 2504 | armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_DEBUG); |
9ee6e8bb PB |
2505 | return; |
2506 | case EXCP_IRQ: | |
983fe826 | 2507 | env->v7m.exception = armv7m_nvic_acknowledge_irq(env->nvic); |
9ee6e8bb PB |
2508 | break; |
2509 | case EXCP_EXCEPTION_EXIT: | |
2510 | do_v7m_exception_exit(env); | |
2511 | return; | |
2512 | default: | |
2513 | cpu_abort(env, "Unhandled exception 0x%x\n", env->exception_index); | |
2514 | return; /* Never happens. Keep compiler happy. */ | |
2515 | } | |
2516 | ||
2517 | /* Align stack pointer. */ | |
2518 | /* ??? Should only do this if Configuration Control Register | |
2519 | STACKALIGN bit is set. */ | |
2520 | if (env->regs[13] & 4) { | |
ab19b0ec | 2521 | env->regs[13] -= 4; |
9ee6e8bb PB |
2522 | xpsr |= 0x200; |
2523 | } | |
6c95676b | 2524 | /* Switch to the handler mode. */ |
9ee6e8bb PB |
2525 | v7m_push(env, xpsr); |
2526 | v7m_push(env, env->regs[15]); | |
2527 | v7m_push(env, env->regs[14]); | |
2528 | v7m_push(env, env->regs[12]); | |
2529 | v7m_push(env, env->regs[3]); | |
2530 | v7m_push(env, env->regs[2]); | |
2531 | v7m_push(env, env->regs[1]); | |
2532 | v7m_push(env, env->regs[0]); | |
2533 | switch_v7m_sp(env, 0); | |
c98d174c PM |
2534 | /* Clear IT bits */ |
2535 | env->condexec_bits = 0; | |
9ee6e8bb | 2536 | env->regs[14] = lr; |
fdfba1a2 | 2537 | addr = ldl_phys(cs->as, env->v7m.vecbase + env->v7m.exception * 4); |
9ee6e8bb PB |
2538 | env->regs[15] = addr & 0xfffffffe; |
2539 | env->thumb = addr & 1; | |
2540 | } | |
2541 | ||
b5ff1b31 | 2542 | /* Handle a CPU exception. */ |
97a8ea5a | 2543 | void arm_cpu_do_interrupt(CPUState *cs) |
b5ff1b31 | 2544 | { |
97a8ea5a AF |
2545 | ARMCPU *cpu = ARM_CPU(cs); |
2546 | CPUARMState *env = &cpu->env; | |
b5ff1b31 FB |
2547 | uint32_t addr; |
2548 | uint32_t mask; | |
2549 | int new_mode; | |
2550 | uint32_t offset; | |
2551 | ||
e6f010cc AF |
2552 | assert(!IS_M(env)); |
2553 | ||
3f1beaca PM |
2554 | arm_log_exception(env->exception_index); |
2555 | ||
b5ff1b31 FB |
2556 | /* TODO: Vectored interrupt controller. */ |
2557 | switch (env->exception_index) { | |
2558 | case EXCP_UDEF: | |
2559 | new_mode = ARM_CPU_MODE_UND; | |
2560 | addr = 0x04; | |
2561 | mask = CPSR_I; | |
2562 | if (env->thumb) | |
2563 | offset = 2; | |
2564 | else | |
2565 | offset = 4; | |
2566 | break; | |
2567 | case EXCP_SWI: | |
8e71621f PB |
2568 | if (semihosting_enabled) { |
2569 | /* Check for semihosting interrupt. */ | |
2570 | if (env->thumb) { | |
d31dd73e BS |
2571 | mask = arm_lduw_code(env, env->regs[15] - 2, env->bswap_code) |
2572 | & 0xff; | |
8e71621f | 2573 | } else { |
d31dd73e | 2574 | mask = arm_ldl_code(env, env->regs[15] - 4, env->bswap_code) |
d8fd2954 | 2575 | & 0xffffff; |
8e71621f PB |
2576 | } |
2577 | /* Only intercept calls from privileged modes, to provide some | |
2578 | semblance of security. */ | |
2579 | if (((mask == 0x123456 && !env->thumb) | |
2580 | || (mask == 0xab && env->thumb)) | |
2581 | && (env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR) { | |
2582 | env->regs[0] = do_arm_semihosting(env); | |
3f1beaca | 2583 | qemu_log_mask(CPU_LOG_INT, "...handled as semihosting call\n"); |
8e71621f PB |
2584 | return; |
2585 | } | |
2586 | } | |
b5ff1b31 FB |
2587 | new_mode = ARM_CPU_MODE_SVC; |
2588 | addr = 0x08; | |
2589 | mask = CPSR_I; | |
601d70b9 | 2590 | /* The PC already points to the next instruction. */ |
b5ff1b31 FB |
2591 | offset = 0; |
2592 | break; | |
06c949e6 | 2593 | case EXCP_BKPT: |
9ee6e8bb | 2594 | /* See if this is a semihosting syscall. */ |
2ad207d4 | 2595 | if (env->thumb && semihosting_enabled) { |
d31dd73e | 2596 | mask = arm_lduw_code(env, env->regs[15], env->bswap_code) & 0xff; |
9ee6e8bb PB |
2597 | if (mask == 0xab |
2598 | && (env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR) { | |
2599 | env->regs[15] += 2; | |
2600 | env->regs[0] = do_arm_semihosting(env); | |
3f1beaca | 2601 | qemu_log_mask(CPU_LOG_INT, "...handled as semihosting call\n"); |
9ee6e8bb PB |
2602 | return; |
2603 | } | |
2604 | } | |
81c05daf | 2605 | env->cp15.c5_insn = 2; |
9ee6e8bb PB |
2606 | /* Fall through to prefetch abort. */ |
2607 | case EXCP_PREFETCH_ABORT: | |
3f1beaca PM |
2608 | qemu_log_mask(CPU_LOG_INT, "...with IFSR 0x%x IFAR 0x%x\n", |
2609 | env->cp15.c5_insn, env->cp15.c6_insn); | |
b5ff1b31 FB |
2610 | new_mode = ARM_CPU_MODE_ABT; |
2611 | addr = 0x0c; | |
2612 | mask = CPSR_A | CPSR_I; | |
2613 | offset = 4; | |
2614 | break; | |
2615 | case EXCP_DATA_ABORT: | |
3f1beaca PM |
2616 | qemu_log_mask(CPU_LOG_INT, "...with DFSR 0x%x DFAR 0x%x\n", |
2617 | env->cp15.c5_data, env->cp15.c6_data); | |
b5ff1b31 FB |
2618 | new_mode = ARM_CPU_MODE_ABT; |
2619 | addr = 0x10; | |
2620 | mask = CPSR_A | CPSR_I; | |
2621 | offset = 8; | |
2622 | break; | |
2623 | case EXCP_IRQ: | |
2624 | new_mode = ARM_CPU_MODE_IRQ; | |
2625 | addr = 0x18; | |
2626 | /* Disable IRQ and imprecise data aborts. */ | |
2627 | mask = CPSR_A | CPSR_I; | |
2628 | offset = 4; | |
2629 | break; | |
2630 | case EXCP_FIQ: | |
2631 | new_mode = ARM_CPU_MODE_FIQ; | |
2632 | addr = 0x1c; | |
2633 | /* Disable FIQ, IRQ and imprecise data aborts. */ | |
2634 | mask = CPSR_A | CPSR_I | CPSR_F; | |
2635 | offset = 4; | |
2636 | break; | |
2637 | default: | |
2638 | cpu_abort(env, "Unhandled exception 0x%x\n", env->exception_index); | |
2639 | return; /* Never happens. Keep compiler happy. */ | |
2640 | } | |
2641 | /* High vectors. */ | |
76e3e1bc | 2642 | if (env->cp15.c1_sys & SCTLR_V) { |
8641136c | 2643 | /* when enabled, base address cannot be remapped. */ |
b5ff1b31 | 2644 | addr += 0xffff0000; |
8641136c NR |
2645 | } else { |
2646 | /* ARM v7 architectures provide a vector base address register to remap | |
2647 | * the interrupt vector table. | |
2648 | * This register is only followed in non-monitor mode, and has a secure | |
2649 | * and un-secure copy. Since the cpu is always in a un-secure operation | |
2650 | * and is never in monitor mode this feature is always active. | |
2651 | * Note: only bits 31:5 are valid. | |
2652 | */ | |
2653 | addr += env->cp15.c12_vbar; | |
b5ff1b31 FB |
2654 | } |
2655 | switch_mode (env, new_mode); | |
2656 | env->spsr = cpsr_read(env); | |
9ee6e8bb PB |
2657 | /* Clear IT bits. */ |
2658 | env->condexec_bits = 0; | |
30a8cac1 | 2659 | /* Switch to the new mode, and to the correct instruction set. */ |
6d7e6326 | 2660 | env->uncached_cpsr = (env->uncached_cpsr & ~CPSR_M) | new_mode; |
b5ff1b31 | 2661 | env->uncached_cpsr |= mask; |
be5e7a76 DES |
2662 | /* this is a lie, as the was no c1_sys on V4T/V5, but who cares |
2663 | * and we should just guard the thumb mode on V4 */ | |
2664 | if (arm_feature(env, ARM_FEATURE_V4T)) { | |
76e3e1bc | 2665 | env->thumb = (env->cp15.c1_sys & SCTLR_TE) != 0; |
be5e7a76 | 2666 | } |
b5ff1b31 FB |
2667 | env->regs[14] = env->regs[15] + offset; |
2668 | env->regs[15] = addr; | |
259186a7 | 2669 | cs->interrupt_request |= CPU_INTERRUPT_EXITTB; |
b5ff1b31 FB |
2670 | } |
2671 | ||
2672 | /* Check section/page access permissions. | |
2673 | Returns the page protection flags, or zero if the access is not | |
2674 | permitted. */ | |
0ecb72a5 | 2675 | static inline int check_ap(CPUARMState *env, int ap, int domain_prot, |
dd4ebc2e | 2676 | int access_type, int is_user) |
b5ff1b31 | 2677 | { |
9ee6e8bb PB |
2678 | int prot_ro; |
2679 | ||
dd4ebc2e | 2680 | if (domain_prot == 3) { |
b5ff1b31 | 2681 | return PAGE_READ | PAGE_WRITE; |
dd4ebc2e | 2682 | } |
b5ff1b31 | 2683 | |
9ee6e8bb PB |
2684 | if (access_type == 1) |
2685 | prot_ro = 0; | |
2686 | else | |
2687 | prot_ro = PAGE_READ; | |
2688 | ||
b5ff1b31 FB |
2689 | switch (ap) { |
2690 | case 0: | |
99f678a6 PM |
2691 | if (arm_feature(env, ARM_FEATURE_V7)) { |
2692 | return 0; | |
2693 | } | |
78600320 | 2694 | if (access_type == 1) |
b5ff1b31 | 2695 | return 0; |
76e3e1bc PM |
2696 | switch (env->cp15.c1_sys & (SCTLR_S | SCTLR_R)) { |
2697 | case SCTLR_S: | |
b5ff1b31 | 2698 | return is_user ? 0 : PAGE_READ; |
76e3e1bc | 2699 | case SCTLR_R: |
b5ff1b31 FB |
2700 | return PAGE_READ; |
2701 | default: | |
2702 | return 0; | |
2703 | } | |
2704 | case 1: | |
2705 | return is_user ? 0 : PAGE_READ | PAGE_WRITE; | |
2706 | case 2: | |
2707 | if (is_user) | |
9ee6e8bb | 2708 | return prot_ro; |
b5ff1b31 FB |
2709 | else |
2710 | return PAGE_READ | PAGE_WRITE; | |
2711 | case 3: | |
2712 | return PAGE_READ | PAGE_WRITE; | |
d4934d18 | 2713 | case 4: /* Reserved. */ |
9ee6e8bb PB |
2714 | return 0; |
2715 | case 5: | |
2716 | return is_user ? 0 : prot_ro; | |
2717 | case 6: | |
2718 | return prot_ro; | |
d4934d18 | 2719 | case 7: |
0ab06d83 | 2720 | if (!arm_feature (env, ARM_FEATURE_V6K)) |
d4934d18 PB |
2721 | return 0; |
2722 | return prot_ro; | |
b5ff1b31 FB |
2723 | default: |
2724 | abort(); | |
2725 | } | |
2726 | } | |
2727 | ||
0ecb72a5 | 2728 | static uint32_t get_level1_table_address(CPUARMState *env, uint32_t address) |
b2fa1797 PB |
2729 | { |
2730 | uint32_t table; | |
2731 | ||
2732 | if (address & env->cp15.c2_mask) | |
2733 | table = env->cp15.c2_base1 & 0xffffc000; | |
2734 | else | |
2735 | table = env->cp15.c2_base0 & env->cp15.c2_base_mask; | |
2736 | ||
2737 | table |= (address >> 18) & 0x3ffc; | |
2738 | return table; | |
2739 | } | |
2740 | ||
0ecb72a5 | 2741 | static int get_phys_addr_v5(CPUARMState *env, uint32_t address, int access_type, |
a8170e5e | 2742 | int is_user, hwaddr *phys_ptr, |
77a71dd1 | 2743 | int *prot, target_ulong *page_size) |
b5ff1b31 | 2744 | { |
fdfba1a2 | 2745 | CPUState *cs = ENV_GET_CPU(env); |
b5ff1b31 FB |
2746 | int code; |
2747 | uint32_t table; | |
2748 | uint32_t desc; | |
2749 | int type; | |
2750 | int ap; | |
2751 | int domain; | |
dd4ebc2e | 2752 | int domain_prot; |
a8170e5e | 2753 | hwaddr phys_addr; |
b5ff1b31 | 2754 | |
9ee6e8bb PB |
2755 | /* Pagetable walk. */ |
2756 | /* Lookup l1 descriptor. */ | |
b2fa1797 | 2757 | table = get_level1_table_address(env, address); |
fdfba1a2 | 2758 | desc = ldl_phys(cs->as, table); |
9ee6e8bb | 2759 | type = (desc & 3); |
dd4ebc2e JCD |
2760 | domain = (desc >> 5) & 0x0f; |
2761 | domain_prot = (env->cp15.c3 >> (domain * 2)) & 3; | |
9ee6e8bb | 2762 | if (type == 0) { |
601d70b9 | 2763 | /* Section translation fault. */ |
9ee6e8bb PB |
2764 | code = 5; |
2765 | goto do_fault; | |
2766 | } | |
dd4ebc2e | 2767 | if (domain_prot == 0 || domain_prot == 2) { |
9ee6e8bb PB |
2768 | if (type == 2) |
2769 | code = 9; /* Section domain fault. */ | |
2770 | else | |
2771 | code = 11; /* Page domain fault. */ | |
2772 | goto do_fault; | |
2773 | } | |
2774 | if (type == 2) { | |
2775 | /* 1Mb section. */ | |
2776 | phys_addr = (desc & 0xfff00000) | (address & 0x000fffff); | |
2777 | ap = (desc >> 10) & 3; | |
2778 | code = 13; | |
d4c430a8 | 2779 | *page_size = 1024 * 1024; |
9ee6e8bb PB |
2780 | } else { |
2781 | /* Lookup l2 entry. */ | |
2782 | if (type == 1) { | |
2783 | /* Coarse pagetable. */ | |
2784 | table = (desc & 0xfffffc00) | ((address >> 10) & 0x3fc); | |
2785 | } else { | |
2786 | /* Fine pagetable. */ | |
2787 | table = (desc & 0xfffff000) | ((address >> 8) & 0xffc); | |
2788 | } | |
fdfba1a2 | 2789 | desc = ldl_phys(cs->as, table); |
9ee6e8bb PB |
2790 | switch (desc & 3) { |
2791 | case 0: /* Page translation fault. */ | |
2792 | code = 7; | |
2793 | goto do_fault; | |
2794 | case 1: /* 64k page. */ | |
2795 | phys_addr = (desc & 0xffff0000) | (address & 0xffff); | |
2796 | ap = (desc >> (4 + ((address >> 13) & 6))) & 3; | |
d4c430a8 | 2797 | *page_size = 0x10000; |
ce819861 | 2798 | break; |
9ee6e8bb PB |
2799 | case 2: /* 4k page. */ |
2800 | phys_addr = (desc & 0xfffff000) | (address & 0xfff); | |
c10f7fc3 | 2801 | ap = (desc >> (4 + ((address >> 9) & 6))) & 3; |
d4c430a8 | 2802 | *page_size = 0x1000; |
ce819861 | 2803 | break; |
9ee6e8bb PB |
2804 | case 3: /* 1k page. */ |
2805 | if (type == 1) { | |
2806 | if (arm_feature(env, ARM_FEATURE_XSCALE)) { | |
2807 | phys_addr = (desc & 0xfffff000) | (address & 0xfff); | |
2808 | } else { | |
2809 | /* Page translation fault. */ | |
2810 | code = 7; | |
2811 | goto do_fault; | |
2812 | } | |
2813 | } else { | |
2814 | phys_addr = (desc & 0xfffffc00) | (address & 0x3ff); | |
2815 | } | |
2816 | ap = (desc >> 4) & 3; | |
d4c430a8 | 2817 | *page_size = 0x400; |
ce819861 PB |
2818 | break; |
2819 | default: | |
9ee6e8bb PB |
2820 | /* Never happens, but compiler isn't smart enough to tell. */ |
2821 | abort(); | |
ce819861 | 2822 | } |
9ee6e8bb PB |
2823 | code = 15; |
2824 | } | |
dd4ebc2e | 2825 | *prot = check_ap(env, ap, domain_prot, access_type, is_user); |
9ee6e8bb PB |
2826 | if (!*prot) { |
2827 | /* Access permission fault. */ | |
2828 | goto do_fault; | |
2829 | } | |
3ad493fc | 2830 | *prot |= PAGE_EXEC; |
9ee6e8bb PB |
2831 | *phys_ptr = phys_addr; |
2832 | return 0; | |
2833 | do_fault: | |
2834 | return code | (domain << 4); | |
2835 | } | |
2836 | ||
0ecb72a5 | 2837 | static int get_phys_addr_v6(CPUARMState *env, uint32_t address, int access_type, |
a8170e5e | 2838 | int is_user, hwaddr *phys_ptr, |
77a71dd1 | 2839 | int *prot, target_ulong *page_size) |
9ee6e8bb | 2840 | { |
fdfba1a2 | 2841 | CPUState *cs = ENV_GET_CPU(env); |
9ee6e8bb PB |
2842 | int code; |
2843 | uint32_t table; | |
2844 | uint32_t desc; | |
2845 | uint32_t xn; | |
de9b05b8 | 2846 | uint32_t pxn = 0; |
9ee6e8bb PB |
2847 | int type; |
2848 | int ap; | |
de9b05b8 | 2849 | int domain = 0; |
dd4ebc2e | 2850 | int domain_prot; |
a8170e5e | 2851 | hwaddr phys_addr; |
9ee6e8bb PB |
2852 | |
2853 | /* Pagetable walk. */ | |
2854 | /* Lookup l1 descriptor. */ | |
b2fa1797 | 2855 | table = get_level1_table_address(env, address); |
fdfba1a2 | 2856 | desc = ldl_phys(cs->as, table); |
9ee6e8bb | 2857 | type = (desc & 3); |
de9b05b8 PM |
2858 | if (type == 0 || (type == 3 && !arm_feature(env, ARM_FEATURE_PXN))) { |
2859 | /* Section translation fault, or attempt to use the encoding | |
2860 | * which is Reserved on implementations without PXN. | |
2861 | */ | |
9ee6e8bb | 2862 | code = 5; |
9ee6e8bb | 2863 | goto do_fault; |
de9b05b8 PM |
2864 | } |
2865 | if ((type == 1) || !(desc & (1 << 18))) { | |
2866 | /* Page or Section. */ | |
dd4ebc2e | 2867 | domain = (desc >> 5) & 0x0f; |
9ee6e8bb | 2868 | } |
dd4ebc2e JCD |
2869 | domain_prot = (env->cp15.c3 >> (domain * 2)) & 3; |
2870 | if (domain_prot == 0 || domain_prot == 2) { | |
de9b05b8 | 2871 | if (type != 1) { |
9ee6e8bb | 2872 | code = 9; /* Section domain fault. */ |
de9b05b8 | 2873 | } else { |
9ee6e8bb | 2874 | code = 11; /* Page domain fault. */ |
de9b05b8 | 2875 | } |
9ee6e8bb PB |
2876 | goto do_fault; |
2877 | } | |
de9b05b8 | 2878 | if (type != 1) { |
9ee6e8bb PB |
2879 | if (desc & (1 << 18)) { |
2880 | /* Supersection. */ | |
2881 | phys_addr = (desc & 0xff000000) | (address & 0x00ffffff); | |
d4c430a8 | 2882 | *page_size = 0x1000000; |
b5ff1b31 | 2883 | } else { |
9ee6e8bb PB |
2884 | /* Section. */ |
2885 | phys_addr = (desc & 0xfff00000) | (address & 0x000fffff); | |
d4c430a8 | 2886 | *page_size = 0x100000; |
b5ff1b31 | 2887 | } |
9ee6e8bb PB |
2888 | ap = ((desc >> 10) & 3) | ((desc >> 13) & 4); |
2889 | xn = desc & (1 << 4); | |
de9b05b8 | 2890 | pxn = desc & 1; |
9ee6e8bb PB |
2891 | code = 13; |
2892 | } else { | |
de9b05b8 PM |
2893 | if (arm_feature(env, ARM_FEATURE_PXN)) { |
2894 | pxn = (desc >> 2) & 1; | |
2895 | } | |
9ee6e8bb PB |
2896 | /* Lookup l2 entry. */ |
2897 | table = (desc & 0xfffffc00) | ((address >> 10) & 0x3fc); | |
fdfba1a2 | 2898 | desc = ldl_phys(cs->as, table); |
9ee6e8bb PB |
2899 | ap = ((desc >> 4) & 3) | ((desc >> 7) & 4); |
2900 | switch (desc & 3) { | |
2901 | case 0: /* Page translation fault. */ | |
2902 | code = 7; | |
b5ff1b31 | 2903 | goto do_fault; |
9ee6e8bb PB |
2904 | case 1: /* 64k page. */ |
2905 | phys_addr = (desc & 0xffff0000) | (address & 0xffff); | |
2906 | xn = desc & (1 << 15); | |
d4c430a8 | 2907 | *page_size = 0x10000; |
9ee6e8bb PB |
2908 | break; |
2909 | case 2: case 3: /* 4k page. */ | |
2910 | phys_addr = (desc & 0xfffff000) | (address & 0xfff); | |
2911 | xn = desc & 1; | |
d4c430a8 | 2912 | *page_size = 0x1000; |
9ee6e8bb PB |
2913 | break; |
2914 | default: | |
2915 | /* Never happens, but compiler isn't smart enough to tell. */ | |
2916 | abort(); | |
b5ff1b31 | 2917 | } |
9ee6e8bb PB |
2918 | code = 15; |
2919 | } | |
dd4ebc2e | 2920 | if (domain_prot == 3) { |
c0034328 JR |
2921 | *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; |
2922 | } else { | |
de9b05b8 PM |
2923 | if (pxn && !is_user) { |
2924 | xn = 1; | |
2925 | } | |
c0034328 JR |
2926 | if (xn && access_type == 2) |
2927 | goto do_fault; | |
9ee6e8bb | 2928 | |
c0034328 | 2929 | /* The simplified model uses AP[0] as an access control bit. */ |
76e3e1bc | 2930 | if ((env->cp15.c1_sys & SCTLR_AFE) && (ap & 1) == 0) { |
c0034328 JR |
2931 | /* Access flag fault. */ |
2932 | code = (code == 15) ? 6 : 3; | |
2933 | goto do_fault; | |
2934 | } | |
dd4ebc2e | 2935 | *prot = check_ap(env, ap, domain_prot, access_type, is_user); |
c0034328 JR |
2936 | if (!*prot) { |
2937 | /* Access permission fault. */ | |
2938 | goto do_fault; | |
2939 | } | |
2940 | if (!xn) { | |
2941 | *prot |= PAGE_EXEC; | |
2942 | } | |
3ad493fc | 2943 | } |
9ee6e8bb | 2944 | *phys_ptr = phys_addr; |
b5ff1b31 FB |
2945 | return 0; |
2946 | do_fault: | |
2947 | return code | (domain << 4); | |
2948 | } | |
2949 | ||
3dde962f PM |
2950 | /* Fault type for long-descriptor MMU fault reporting; this corresponds |
2951 | * to bits [5..2] in the STATUS field in long-format DFSR/IFSR. | |
2952 | */ | |
2953 | typedef enum { | |
2954 | translation_fault = 1, | |
2955 | access_fault = 2, | |
2956 | permission_fault = 3, | |
2957 | } MMUFaultType; | |
2958 | ||
2959 | static int get_phys_addr_lpae(CPUARMState *env, uint32_t address, | |
2960 | int access_type, int is_user, | |
a8170e5e | 2961 | hwaddr *phys_ptr, int *prot, |
3dde962f PM |
2962 | target_ulong *page_size_ptr) |
2963 | { | |
2c17449b | 2964 | CPUState *cs = ENV_GET_CPU(env); |
3dde962f PM |
2965 | /* Read an LPAE long-descriptor translation table. */ |
2966 | MMUFaultType fault_type = translation_fault; | |
2967 | uint32_t level = 1; | |
2968 | uint32_t epd; | |
2969 | uint32_t tsz; | |
2970 | uint64_t ttbr; | |
2971 | int ttbr_select; | |
2972 | int n; | |
a8170e5e | 2973 | hwaddr descaddr; |
3dde962f PM |
2974 | uint32_t tableattrs; |
2975 | target_ulong page_size; | |
2976 | uint32_t attrs; | |
2977 | ||
2978 | /* Determine whether this address is in the region controlled by | |
2979 | * TTBR0 or TTBR1 (or if it is in neither region and should fault). | |
2980 | * This is a Non-secure PL0/1 stage 1 translation, so controlled by | |
2981 | * TTBCR/TTBR0/TTBR1 in accordance with ARM ARM DDI0406C table B-32: | |
2982 | */ | |
2983 | uint32_t t0sz = extract32(env->cp15.c2_control, 0, 3); | |
2984 | uint32_t t1sz = extract32(env->cp15.c2_control, 16, 3); | |
2985 | if (t0sz && !extract32(address, 32 - t0sz, t0sz)) { | |
2986 | /* there is a ttbr0 region and we are in it (high bits all zero) */ | |
2987 | ttbr_select = 0; | |
2988 | } else if (t1sz && !extract32(~address, 32 - t1sz, t1sz)) { | |
2989 | /* there is a ttbr1 region and we are in it (high bits all one) */ | |
2990 | ttbr_select = 1; | |
2991 | } else if (!t0sz) { | |
2992 | /* ttbr0 region is "everything not in the ttbr1 region" */ | |
2993 | ttbr_select = 0; | |
2994 | } else if (!t1sz) { | |
2995 | /* ttbr1 region is "everything not in the ttbr0 region" */ | |
2996 | ttbr_select = 1; | |
2997 | } else { | |
2998 | /* in the gap between the two regions, this is a Translation fault */ | |
2999 | fault_type = translation_fault; | |
3000 | goto do_fault; | |
3001 | } | |
3002 | ||
3003 | /* Note that QEMU ignores shareability and cacheability attributes, | |
3004 | * so we don't need to do anything with the SH, ORGN, IRGN fields | |
3005 | * in the TTBCR. Similarly, TTBCR:A1 selects whether we get the | |
3006 | * ASID from TTBR0 or TTBR1, but QEMU's TLB doesn't currently | |
3007 | * implement any ASID-like capability so we can ignore it (instead | |
3008 | * we will always flush the TLB any time the ASID is changed). | |
3009 | */ | |
3010 | if (ttbr_select == 0) { | |
3011 | ttbr = ((uint64_t)env->cp15.c2_base0_hi << 32) | env->cp15.c2_base0; | |
3012 | epd = extract32(env->cp15.c2_control, 7, 1); | |
3013 | tsz = t0sz; | |
3014 | } else { | |
3015 | ttbr = ((uint64_t)env->cp15.c2_base1_hi << 32) | env->cp15.c2_base1; | |
3016 | epd = extract32(env->cp15.c2_control, 23, 1); | |
3017 | tsz = t1sz; | |
3018 | } | |
3019 | ||
3020 | if (epd) { | |
3021 | /* Translation table walk disabled => Translation fault on TLB miss */ | |
3022 | goto do_fault; | |
3023 | } | |
3024 | ||
3025 | /* If the region is small enough we will skip straight to a 2nd level | |
3026 | * lookup. This affects the number of bits of the address used in | |
3027 | * combination with the TTBR to find the first descriptor. ('n' here | |
3028 | * matches the usage in the ARM ARM sB3.6.6, where bits [39..n] are | |
3029 | * from the TTBR, [n-1..3] from the vaddr, and [2..0] always zero). | |
3030 | */ | |
3031 | if (tsz > 1) { | |
3032 | level = 2; | |
3033 | n = 14 - tsz; | |
3034 | } else { | |
3035 | n = 5 - tsz; | |
3036 | } | |
3037 | ||
3038 | /* Clear the vaddr bits which aren't part of the within-region address, | |
3039 | * so that we don't have to special case things when calculating the | |
3040 | * first descriptor address. | |
3041 | */ | |
3042 | address &= (0xffffffffU >> tsz); | |
3043 | ||
3044 | /* Now we can extract the actual base address from the TTBR */ | |
3045 | descaddr = extract64(ttbr, 0, 40); | |
3046 | descaddr &= ~((1ULL << n) - 1); | |
3047 | ||
3048 | tableattrs = 0; | |
3049 | for (;;) { | |
3050 | uint64_t descriptor; | |
3051 | ||
3052 | descaddr |= ((address >> (9 * (4 - level))) & 0xff8); | |
2c17449b | 3053 | descriptor = ldq_phys(cs->as, descaddr); |
3dde962f PM |
3054 | if (!(descriptor & 1) || |
3055 | (!(descriptor & 2) && (level == 3))) { | |
3056 | /* Invalid, or the Reserved level 3 encoding */ | |
3057 | goto do_fault; | |
3058 | } | |
3059 | descaddr = descriptor & 0xfffffff000ULL; | |
3060 | ||
3061 | if ((descriptor & 2) && (level < 3)) { | |
3062 | /* Table entry. The top five bits are attributes which may | |
3063 | * propagate down through lower levels of the table (and | |
3064 | * which are all arranged so that 0 means "no effect", so | |
3065 | * we can gather them up by ORing in the bits at each level). | |
3066 | */ | |
3067 | tableattrs |= extract64(descriptor, 59, 5); | |
3068 | level++; | |
3069 | continue; | |
3070 | } | |
3071 | /* Block entry at level 1 or 2, or page entry at level 3. | |
3072 | * These are basically the same thing, although the number | |
3073 | * of bits we pull in from the vaddr varies. | |
3074 | */ | |
3075 | page_size = (1 << (39 - (9 * level))); | |
3076 | descaddr |= (address & (page_size - 1)); | |
3077 | /* Extract attributes from the descriptor and merge with table attrs */ | |
3078 | attrs = extract64(descriptor, 2, 10) | |
3079 | | (extract64(descriptor, 52, 12) << 10); | |
3080 | attrs |= extract32(tableattrs, 0, 2) << 11; /* XN, PXN */ | |
3081 | attrs |= extract32(tableattrs, 3, 1) << 5; /* APTable[1] => AP[2] */ | |
3082 | /* The sense of AP[1] vs APTable[0] is reversed, as APTable[0] == 1 | |
3083 | * means "force PL1 access only", which means forcing AP[1] to 0. | |
3084 | */ | |
3085 | if (extract32(tableattrs, 2, 1)) { | |
3086 | attrs &= ~(1 << 4); | |
3087 | } | |
3088 | /* Since we're always in the Non-secure state, NSTable is ignored. */ | |
3089 | break; | |
3090 | } | |
3091 | /* Here descaddr is the final physical address, and attributes | |
3092 | * are all in attrs. | |
3093 | */ | |
3094 | fault_type = access_fault; | |
3095 | if ((attrs & (1 << 8)) == 0) { | |
3096 | /* Access flag */ | |
3097 | goto do_fault; | |
3098 | } | |
3099 | fault_type = permission_fault; | |
3100 | if (is_user && !(attrs & (1 << 4))) { | |
3101 | /* Unprivileged access not enabled */ | |
3102 | goto do_fault; | |
3103 | } | |
3104 | *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; | |
3105 | if (attrs & (1 << 12) || (!is_user && (attrs & (1 << 11)))) { | |
3106 | /* XN or PXN */ | |
3107 | if (access_type == 2) { | |
3108 | goto do_fault; | |
3109 | } | |
3110 | *prot &= ~PAGE_EXEC; | |
3111 | } | |
3112 | if (attrs & (1 << 5)) { | |
3113 | /* Write access forbidden */ | |
3114 | if (access_type == 1) { | |
3115 | goto do_fault; | |
3116 | } | |
3117 | *prot &= ~PAGE_WRITE; | |
3118 | } | |
3119 | ||
3120 | *phys_ptr = descaddr; | |
3121 | *page_size_ptr = page_size; | |
3122 | return 0; | |
3123 | ||
3124 | do_fault: | |
3125 | /* Long-descriptor format IFSR/DFSR value */ | |
3126 | return (1 << 9) | (fault_type << 2) | level; | |
3127 | } | |
3128 | ||
77a71dd1 PM |
3129 | static int get_phys_addr_mpu(CPUARMState *env, uint32_t address, |
3130 | int access_type, int is_user, | |
a8170e5e | 3131 | hwaddr *phys_ptr, int *prot) |
9ee6e8bb PB |
3132 | { |
3133 | int n; | |
3134 | uint32_t mask; | |
3135 | uint32_t base; | |
3136 | ||
3137 | *phys_ptr = address; | |
3138 | for (n = 7; n >= 0; n--) { | |
3139 | base = env->cp15.c6_region[n]; | |
3140 | if ((base & 1) == 0) | |
3141 | continue; | |
3142 | mask = 1 << ((base >> 1) & 0x1f); | |
3143 | /* Keep this shift separate from the above to avoid an | |
3144 | (undefined) << 32. */ | |
3145 | mask = (mask << 1) - 1; | |
3146 | if (((base ^ address) & ~mask) == 0) | |
3147 | break; | |
3148 | } | |
3149 | if (n < 0) | |
3150 | return 2; | |
3151 | ||
3152 | if (access_type == 2) { | |
3153 | mask = env->cp15.c5_insn; | |
3154 | } else { | |
3155 | mask = env->cp15.c5_data; | |
3156 | } | |
3157 | mask = (mask >> (n * 4)) & 0xf; | |
3158 | switch (mask) { | |
3159 | case 0: | |
3160 | return 1; | |
3161 | case 1: | |
3162 | if (is_user) | |
3163 | return 1; | |
3164 | *prot = PAGE_READ | PAGE_WRITE; | |
3165 | break; | |
3166 | case 2: | |
3167 | *prot = PAGE_READ; | |
3168 | if (!is_user) | |
3169 | *prot |= PAGE_WRITE; | |
3170 | break; | |
3171 | case 3: | |
3172 | *prot = PAGE_READ | PAGE_WRITE; | |
3173 | break; | |
3174 | case 5: | |
3175 | if (is_user) | |
3176 | return 1; | |
3177 | *prot = PAGE_READ; | |
3178 | break; | |
3179 | case 6: | |
3180 | *prot = PAGE_READ; | |
3181 | break; | |
3182 | default: | |
3183 | /* Bad permission. */ | |
3184 | return 1; | |
3185 | } | |
3ad493fc | 3186 | *prot |= PAGE_EXEC; |
9ee6e8bb PB |
3187 | return 0; |
3188 | } | |
3189 | ||
702a9357 PM |
3190 | /* get_phys_addr - get the physical address for this virtual address |
3191 | * | |
3192 | * Find the physical address corresponding to the given virtual address, | |
3193 | * by doing a translation table walk on MMU based systems or using the | |
3194 | * MPU state on MPU based systems. | |
3195 | * | |
3196 | * Returns 0 if the translation was successful. Otherwise, phys_ptr, | |
3197 | * prot and page_size are not filled in, and the return value provides | |
3198 | * information on why the translation aborted, in the format of a | |
3199 | * DFSR/IFSR fault register, with the following caveats: | |
3200 | * * we honour the short vs long DFSR format differences. | |
3201 | * * the WnR bit is never set (the caller must do this). | |
3202 | * * for MPU based systems we don't bother to return a full FSR format | |
3203 | * value. | |
3204 | * | |
3205 | * @env: CPUARMState | |
3206 | * @address: virtual address to get physical address for | |
3207 | * @access_type: 0 for read, 1 for write, 2 for execute | |
3208 | * @is_user: 0 for privileged access, 1 for user | |
3209 | * @phys_ptr: set to the physical address corresponding to the virtual address | |
3210 | * @prot: set to the permissions for the page containing phys_ptr | |
3211 | * @page_size: set to the size of the page containing phys_ptr | |
3212 | */ | |
0ecb72a5 | 3213 | static inline int get_phys_addr(CPUARMState *env, uint32_t address, |
9ee6e8bb | 3214 | int access_type, int is_user, |
a8170e5e | 3215 | hwaddr *phys_ptr, int *prot, |
d4c430a8 | 3216 | target_ulong *page_size) |
9ee6e8bb PB |
3217 | { |
3218 | /* Fast Context Switch Extension. */ | |
3219 | if (address < 0x02000000) | |
3220 | address += env->cp15.c13_fcse; | |
3221 | ||
76e3e1bc | 3222 | if ((env->cp15.c1_sys & SCTLR_M) == 0) { |
9ee6e8bb PB |
3223 | /* MMU/MPU disabled. */ |
3224 | *phys_ptr = address; | |
3ad493fc | 3225 | *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; |
d4c430a8 | 3226 | *page_size = TARGET_PAGE_SIZE; |
9ee6e8bb PB |
3227 | return 0; |
3228 | } else if (arm_feature(env, ARM_FEATURE_MPU)) { | |
d4c430a8 | 3229 | *page_size = TARGET_PAGE_SIZE; |
9ee6e8bb PB |
3230 | return get_phys_addr_mpu(env, address, access_type, is_user, phys_ptr, |
3231 | prot); | |
3dde962f PM |
3232 | } else if (extended_addresses_enabled(env)) { |
3233 | return get_phys_addr_lpae(env, address, access_type, is_user, phys_ptr, | |
3234 | prot, page_size); | |
76e3e1bc | 3235 | } else if (env->cp15.c1_sys & SCTLR_XP) { |
9ee6e8bb | 3236 | return get_phys_addr_v6(env, address, access_type, is_user, phys_ptr, |
d4c430a8 | 3237 | prot, page_size); |
9ee6e8bb PB |
3238 | } else { |
3239 | return get_phys_addr_v5(env, address, access_type, is_user, phys_ptr, | |
d4c430a8 | 3240 | prot, page_size); |
9ee6e8bb PB |
3241 | } |
3242 | } | |
3243 | ||
0ecb72a5 | 3244 | int cpu_arm_handle_mmu_fault (CPUARMState *env, target_ulong address, |
97b348e7 | 3245 | int access_type, int mmu_idx) |
b5ff1b31 | 3246 | { |
a8170e5e | 3247 | hwaddr phys_addr; |
d4c430a8 | 3248 | target_ulong page_size; |
b5ff1b31 | 3249 | int prot; |
6ebbf390 | 3250 | int ret, is_user; |
b5ff1b31 | 3251 | |
6ebbf390 | 3252 | is_user = mmu_idx == MMU_USER_IDX; |
d4c430a8 PB |
3253 | ret = get_phys_addr(env, address, access_type, is_user, &phys_addr, &prot, |
3254 | &page_size); | |
b5ff1b31 FB |
3255 | if (ret == 0) { |
3256 | /* Map a single [sub]page. */ | |
a8170e5e | 3257 | phys_addr &= ~(hwaddr)0x3ff; |
b5ff1b31 | 3258 | address &= ~(uint32_t)0x3ff; |
3ad493fc | 3259 | tlb_set_page (env, address, phys_addr, prot, mmu_idx, page_size); |
d4c430a8 | 3260 | return 0; |
b5ff1b31 FB |
3261 | } |
3262 | ||
3263 | if (access_type == 2) { | |
3264 | env->cp15.c5_insn = ret; | |
3265 | env->cp15.c6_insn = address; | |
3266 | env->exception_index = EXCP_PREFETCH_ABORT; | |
3267 | } else { | |
3268 | env->cp15.c5_data = ret; | |
9ee6e8bb PB |
3269 | if (access_type == 1 && arm_feature(env, ARM_FEATURE_V6)) |
3270 | env->cp15.c5_data |= (1 << 11); | |
b5ff1b31 FB |
3271 | env->cp15.c6_data = address; |
3272 | env->exception_index = EXCP_DATA_ABORT; | |
3273 | } | |
3274 | return 1; | |
3275 | } | |
3276 | ||
00b941e5 | 3277 | hwaddr arm_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) |
b5ff1b31 | 3278 | { |
00b941e5 | 3279 | ARMCPU *cpu = ARM_CPU(cs); |
a8170e5e | 3280 | hwaddr phys_addr; |
d4c430a8 | 3281 | target_ulong page_size; |
b5ff1b31 FB |
3282 | int prot; |
3283 | int ret; | |
3284 | ||
00b941e5 | 3285 | ret = get_phys_addr(&cpu->env, addr, 0, 0, &phys_addr, &prot, &page_size); |
b5ff1b31 | 3286 | |
00b941e5 | 3287 | if (ret != 0) { |
b5ff1b31 | 3288 | return -1; |
00b941e5 | 3289 | } |
b5ff1b31 FB |
3290 | |
3291 | return phys_addr; | |
3292 | } | |
3293 | ||
0ecb72a5 | 3294 | void HELPER(set_r13_banked)(CPUARMState *env, uint32_t mode, uint32_t val) |
9ee6e8bb | 3295 | { |
39ea3d4e PM |
3296 | if ((env->uncached_cpsr & CPSR_M) == mode) { |
3297 | env->regs[13] = val; | |
3298 | } else { | |
f5206413 | 3299 | env->banked_r13[bank_number(mode)] = val; |
39ea3d4e | 3300 | } |
9ee6e8bb PB |
3301 | } |
3302 | ||
0ecb72a5 | 3303 | uint32_t HELPER(get_r13_banked)(CPUARMState *env, uint32_t mode) |
9ee6e8bb | 3304 | { |
39ea3d4e PM |
3305 | if ((env->uncached_cpsr & CPSR_M) == mode) { |
3306 | return env->regs[13]; | |
3307 | } else { | |
f5206413 | 3308 | return env->banked_r13[bank_number(mode)]; |
39ea3d4e | 3309 | } |
9ee6e8bb PB |
3310 | } |
3311 | ||
0ecb72a5 | 3312 | uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg) |
9ee6e8bb PB |
3313 | { |
3314 | switch (reg) { | |
3315 | case 0: /* APSR */ | |
3316 | return xpsr_read(env) & 0xf8000000; | |
3317 | case 1: /* IAPSR */ | |
3318 | return xpsr_read(env) & 0xf80001ff; | |
3319 | case 2: /* EAPSR */ | |
3320 | return xpsr_read(env) & 0xff00fc00; | |
3321 | case 3: /* xPSR */ | |
3322 | return xpsr_read(env) & 0xff00fdff; | |
3323 | case 5: /* IPSR */ | |
3324 | return xpsr_read(env) & 0x000001ff; | |
3325 | case 6: /* EPSR */ | |
3326 | return xpsr_read(env) & 0x0700fc00; | |
3327 | case 7: /* IEPSR */ | |
3328 | return xpsr_read(env) & 0x0700edff; | |
3329 | case 8: /* MSP */ | |
3330 | return env->v7m.current_sp ? env->v7m.other_sp : env->regs[13]; | |
3331 | case 9: /* PSP */ | |
3332 | return env->v7m.current_sp ? env->regs[13] : env->v7m.other_sp; | |
3333 | case 16: /* PRIMASK */ | |
3334 | return (env->uncached_cpsr & CPSR_I) != 0; | |
82845826 SH |
3335 | case 17: /* BASEPRI */ |
3336 | case 18: /* BASEPRI_MAX */ | |
9ee6e8bb | 3337 | return env->v7m.basepri; |
82845826 SH |
3338 | case 19: /* FAULTMASK */ |
3339 | return (env->uncached_cpsr & CPSR_F) != 0; | |
9ee6e8bb PB |
3340 | case 20: /* CONTROL */ |
3341 | return env->v7m.control; | |
3342 | default: | |
3343 | /* ??? For debugging only. */ | |
3344 | cpu_abort(env, "Unimplemented system register read (%d)\n", reg); | |
3345 | return 0; | |
3346 | } | |
3347 | } | |
3348 | ||
0ecb72a5 | 3349 | void HELPER(v7m_msr)(CPUARMState *env, uint32_t reg, uint32_t val) |
9ee6e8bb PB |
3350 | { |
3351 | switch (reg) { | |
3352 | case 0: /* APSR */ | |
3353 | xpsr_write(env, val, 0xf8000000); | |
3354 | break; | |
3355 | case 1: /* IAPSR */ | |
3356 | xpsr_write(env, val, 0xf8000000); | |
3357 | break; | |
3358 | case 2: /* EAPSR */ | |
3359 | xpsr_write(env, val, 0xfe00fc00); | |
3360 | break; | |
3361 | case 3: /* xPSR */ | |
3362 | xpsr_write(env, val, 0xfe00fc00); | |
3363 | break; | |
3364 | case 5: /* IPSR */ | |
3365 | /* IPSR bits are readonly. */ | |
3366 | break; | |
3367 | case 6: /* EPSR */ | |
3368 | xpsr_write(env, val, 0x0600fc00); | |
3369 | break; | |
3370 | case 7: /* IEPSR */ | |
3371 | xpsr_write(env, val, 0x0600fc00); | |
3372 | break; | |
3373 | case 8: /* MSP */ | |
3374 | if (env->v7m.current_sp) | |
3375 | env->v7m.other_sp = val; | |
3376 | else | |
3377 | env->regs[13] = val; | |
3378 | break; | |
3379 | case 9: /* PSP */ | |
3380 | if (env->v7m.current_sp) | |
3381 | env->regs[13] = val; | |
3382 | else | |
3383 | env->v7m.other_sp = val; | |
3384 | break; | |
3385 | case 16: /* PRIMASK */ | |
3386 | if (val & 1) | |
3387 | env->uncached_cpsr |= CPSR_I; | |
3388 | else | |
3389 | env->uncached_cpsr &= ~CPSR_I; | |
3390 | break; | |
82845826 | 3391 | case 17: /* BASEPRI */ |
9ee6e8bb PB |
3392 | env->v7m.basepri = val & 0xff; |
3393 | break; | |
82845826 | 3394 | case 18: /* BASEPRI_MAX */ |
9ee6e8bb PB |
3395 | val &= 0xff; |
3396 | if (val != 0 && (val < env->v7m.basepri || env->v7m.basepri == 0)) | |
3397 | env->v7m.basepri = val; | |
3398 | break; | |
82845826 SH |
3399 | case 19: /* FAULTMASK */ |
3400 | if (val & 1) | |
3401 | env->uncached_cpsr |= CPSR_F; | |
3402 | else | |
3403 | env->uncached_cpsr &= ~CPSR_F; | |
3404 | break; | |
9ee6e8bb PB |
3405 | case 20: /* CONTROL */ |
3406 | env->v7m.control = val & 3; | |
3407 | switch_v7m_sp(env, (val & 2) != 0); | |
3408 | break; | |
3409 | default: | |
3410 | /* ??? For debugging only. */ | |
3411 | cpu_abort(env, "Unimplemented system register write (%d)\n", reg); | |
3412 | return; | |
3413 | } | |
3414 | } | |
3415 | ||
b5ff1b31 | 3416 | #endif |
6ddbc6e4 PB |
3417 | |
3418 | /* Note that signed overflow is undefined in C. The following routines are | |
3419 | careful to use unsigned types where modulo arithmetic is required. | |
3420 | Failure to do so _will_ break on newer gcc. */ | |
3421 | ||
3422 | /* Signed saturating arithmetic. */ | |
3423 | ||
1654b2d6 | 3424 | /* Perform 16-bit signed saturating addition. */ |
6ddbc6e4 PB |
3425 | static inline uint16_t add16_sat(uint16_t a, uint16_t b) |
3426 | { | |
3427 | uint16_t res; | |
3428 | ||
3429 | res = a + b; | |
3430 | if (((res ^ a) & 0x8000) && !((a ^ b) & 0x8000)) { | |
3431 | if (a & 0x8000) | |
3432 | res = 0x8000; | |
3433 | else | |
3434 | res = 0x7fff; | |
3435 | } | |
3436 | return res; | |
3437 | } | |
3438 | ||
1654b2d6 | 3439 | /* Perform 8-bit signed saturating addition. */ |
6ddbc6e4 PB |
3440 | static inline uint8_t add8_sat(uint8_t a, uint8_t b) |
3441 | { | |
3442 | uint8_t res; | |
3443 | ||
3444 | res = a + b; | |
3445 | if (((res ^ a) & 0x80) && !((a ^ b) & 0x80)) { | |
3446 | if (a & 0x80) | |
3447 | res = 0x80; | |
3448 | else | |
3449 | res = 0x7f; | |
3450 | } | |
3451 | return res; | |
3452 | } | |
3453 | ||
1654b2d6 | 3454 | /* Perform 16-bit signed saturating subtraction. */ |
6ddbc6e4 PB |
3455 | static inline uint16_t sub16_sat(uint16_t a, uint16_t b) |
3456 | { | |
3457 | uint16_t res; | |
3458 | ||
3459 | res = a - b; | |
3460 | if (((res ^ a) & 0x8000) && ((a ^ b) & 0x8000)) { | |
3461 | if (a & 0x8000) | |
3462 | res = 0x8000; | |
3463 | else | |
3464 | res = 0x7fff; | |
3465 | } | |
3466 | return res; | |
3467 | } | |
3468 | ||
1654b2d6 | 3469 | /* Perform 8-bit signed saturating subtraction. */ |
6ddbc6e4 PB |
3470 | static inline uint8_t sub8_sat(uint8_t a, uint8_t b) |
3471 | { | |
3472 | uint8_t res; | |
3473 | ||
3474 | res = a - b; | |
3475 | if (((res ^ a) & 0x80) && ((a ^ b) & 0x80)) { | |
3476 | if (a & 0x80) | |
3477 | res = 0x80; | |
3478 | else | |
3479 | res = 0x7f; | |
3480 | } | |
3481 | return res; | |
3482 | } | |
3483 | ||
3484 | #define ADD16(a, b, n) RESULT(add16_sat(a, b), n, 16); | |
3485 | #define SUB16(a, b, n) RESULT(sub16_sat(a, b), n, 16); | |
3486 | #define ADD8(a, b, n) RESULT(add8_sat(a, b), n, 8); | |
3487 | #define SUB8(a, b, n) RESULT(sub8_sat(a, b), n, 8); | |
3488 | #define PFX q | |
3489 | ||
3490 | #include "op_addsub.h" | |
3491 | ||
3492 | /* Unsigned saturating arithmetic. */ | |
460a09c1 | 3493 | static inline uint16_t add16_usat(uint16_t a, uint16_t b) |
6ddbc6e4 PB |
3494 | { |
3495 | uint16_t res; | |
3496 | res = a + b; | |
3497 | if (res < a) | |
3498 | res = 0xffff; | |
3499 | return res; | |
3500 | } | |
3501 | ||
460a09c1 | 3502 | static inline uint16_t sub16_usat(uint16_t a, uint16_t b) |
6ddbc6e4 | 3503 | { |
4c4fd3f8 | 3504 | if (a > b) |
6ddbc6e4 PB |
3505 | return a - b; |
3506 | else | |
3507 | return 0; | |
3508 | } | |
3509 | ||
3510 | static inline uint8_t add8_usat(uint8_t a, uint8_t b) | |
3511 | { | |
3512 | uint8_t res; | |
3513 | res = a + b; | |
3514 | if (res < a) | |
3515 | res = 0xff; | |
3516 | return res; | |
3517 | } | |
3518 | ||
3519 | static inline uint8_t sub8_usat(uint8_t a, uint8_t b) | |
3520 | { | |
4c4fd3f8 | 3521 | if (a > b) |
6ddbc6e4 PB |
3522 | return a - b; |
3523 | else | |
3524 | return 0; | |
3525 | } | |
3526 | ||
3527 | #define ADD16(a, b, n) RESULT(add16_usat(a, b), n, 16); | |
3528 | #define SUB16(a, b, n) RESULT(sub16_usat(a, b), n, 16); | |
3529 | #define ADD8(a, b, n) RESULT(add8_usat(a, b), n, 8); | |
3530 | #define SUB8(a, b, n) RESULT(sub8_usat(a, b), n, 8); | |
3531 | #define PFX uq | |
3532 | ||
3533 | #include "op_addsub.h" | |
3534 | ||
3535 | /* Signed modulo arithmetic. */ | |
3536 | #define SARITH16(a, b, n, op) do { \ | |
3537 | int32_t sum; \ | |
db6e2e65 | 3538 | sum = (int32_t)(int16_t)(a) op (int32_t)(int16_t)(b); \ |
6ddbc6e4 PB |
3539 | RESULT(sum, n, 16); \ |
3540 | if (sum >= 0) \ | |
3541 | ge |= 3 << (n * 2); \ | |
3542 | } while(0) | |
3543 | ||
3544 | #define SARITH8(a, b, n, op) do { \ | |
3545 | int32_t sum; \ | |
db6e2e65 | 3546 | sum = (int32_t)(int8_t)(a) op (int32_t)(int8_t)(b); \ |
6ddbc6e4 PB |
3547 | RESULT(sum, n, 8); \ |
3548 | if (sum >= 0) \ | |
3549 | ge |= 1 << n; \ | |
3550 | } while(0) | |
3551 | ||
3552 | ||
3553 | #define ADD16(a, b, n) SARITH16(a, b, n, +) | |
3554 | #define SUB16(a, b, n) SARITH16(a, b, n, -) | |
3555 | #define ADD8(a, b, n) SARITH8(a, b, n, +) | |
3556 | #define SUB8(a, b, n) SARITH8(a, b, n, -) | |
3557 | #define PFX s | |
3558 | #define ARITH_GE | |
3559 | ||
3560 | #include "op_addsub.h" | |
3561 | ||
3562 | /* Unsigned modulo arithmetic. */ | |
3563 | #define ADD16(a, b, n) do { \ | |
3564 | uint32_t sum; \ | |
3565 | sum = (uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b); \ | |
3566 | RESULT(sum, n, 16); \ | |
a87aa10b | 3567 | if ((sum >> 16) == 1) \ |
6ddbc6e4 PB |
3568 | ge |= 3 << (n * 2); \ |
3569 | } while(0) | |
3570 | ||
3571 | #define ADD8(a, b, n) do { \ | |
3572 | uint32_t sum; \ | |
3573 | sum = (uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b); \ | |
3574 | RESULT(sum, n, 8); \ | |
a87aa10b AZ |
3575 | if ((sum >> 8) == 1) \ |
3576 | ge |= 1 << n; \ | |
6ddbc6e4 PB |
3577 | } while(0) |
3578 | ||
3579 | #define SUB16(a, b, n) do { \ | |
3580 | uint32_t sum; \ | |
3581 | sum = (uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b); \ | |
3582 | RESULT(sum, n, 16); \ | |
3583 | if ((sum >> 16) == 0) \ | |
3584 | ge |= 3 << (n * 2); \ | |
3585 | } while(0) | |
3586 | ||
3587 | #define SUB8(a, b, n) do { \ | |
3588 | uint32_t sum; \ | |
3589 | sum = (uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b); \ | |
3590 | RESULT(sum, n, 8); \ | |
3591 | if ((sum >> 8) == 0) \ | |
a87aa10b | 3592 | ge |= 1 << n; \ |
6ddbc6e4 PB |
3593 | } while(0) |
3594 | ||
3595 | #define PFX u | |
3596 | #define ARITH_GE | |
3597 | ||
3598 | #include "op_addsub.h" | |
3599 | ||
3600 | /* Halved signed arithmetic. */ | |
3601 | #define ADD16(a, b, n) \ | |
3602 | RESULT(((int32_t)(int16_t)(a) + (int32_t)(int16_t)(b)) >> 1, n, 16) | |
3603 | #define SUB16(a, b, n) \ | |
3604 | RESULT(((int32_t)(int16_t)(a) - (int32_t)(int16_t)(b)) >> 1, n, 16) | |
3605 | #define ADD8(a, b, n) \ | |
3606 | RESULT(((int32_t)(int8_t)(a) + (int32_t)(int8_t)(b)) >> 1, n, 8) | |
3607 | #define SUB8(a, b, n) \ | |
3608 | RESULT(((int32_t)(int8_t)(a) - (int32_t)(int8_t)(b)) >> 1, n, 8) | |
3609 | #define PFX sh | |
3610 | ||
3611 | #include "op_addsub.h" | |
3612 | ||
3613 | /* Halved unsigned arithmetic. */ | |
3614 | #define ADD16(a, b, n) \ | |
3615 | RESULT(((uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b)) >> 1, n, 16) | |
3616 | #define SUB16(a, b, n) \ | |
3617 | RESULT(((uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b)) >> 1, n, 16) | |
3618 | #define ADD8(a, b, n) \ | |
3619 | RESULT(((uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b)) >> 1, n, 8) | |
3620 | #define SUB8(a, b, n) \ | |
3621 | RESULT(((uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b)) >> 1, n, 8) | |
3622 | #define PFX uh | |
3623 | ||
3624 | #include "op_addsub.h" | |
3625 | ||
3626 | static inline uint8_t do_usad(uint8_t a, uint8_t b) | |
3627 | { | |
3628 | if (a > b) | |
3629 | return a - b; | |
3630 | else | |
3631 | return b - a; | |
3632 | } | |
3633 | ||
3634 | /* Unsigned sum of absolute byte differences. */ | |
3635 | uint32_t HELPER(usad8)(uint32_t a, uint32_t b) | |
3636 | { | |
3637 | uint32_t sum; | |
3638 | sum = do_usad(a, b); | |
3639 | sum += do_usad(a >> 8, b >> 8); | |
3640 | sum += do_usad(a >> 16, b >>16); | |
3641 | sum += do_usad(a >> 24, b >> 24); | |
3642 | return sum; | |
3643 | } | |
3644 | ||
3645 | /* For ARMv6 SEL instruction. */ | |
3646 | uint32_t HELPER(sel_flags)(uint32_t flags, uint32_t a, uint32_t b) | |
3647 | { | |
3648 | uint32_t mask; | |
3649 | ||
3650 | mask = 0; | |
3651 | if (flags & 1) | |
3652 | mask |= 0xff; | |
3653 | if (flags & 2) | |
3654 | mask |= 0xff00; | |
3655 | if (flags & 4) | |
3656 | mask |= 0xff0000; | |
3657 | if (flags & 8) | |
3658 | mask |= 0xff000000; | |
3659 | return (a & mask) | (b & ~mask); | |
3660 | } | |
3661 | ||
b90372ad PM |
3662 | /* VFP support. We follow the convention used for VFP instructions: |
3663 | Single precision routines have a "s" suffix, double precision a | |
4373f3ce PB |
3664 | "d" suffix. */ |
3665 | ||
3666 | /* Convert host exception flags to vfp form. */ | |
3667 | static inline int vfp_exceptbits_from_host(int host_bits) | |
3668 | { | |
3669 | int target_bits = 0; | |
3670 | ||
3671 | if (host_bits & float_flag_invalid) | |
3672 | target_bits |= 1; | |
3673 | if (host_bits & float_flag_divbyzero) | |
3674 | target_bits |= 2; | |
3675 | if (host_bits & float_flag_overflow) | |
3676 | target_bits |= 4; | |
36802b6b | 3677 | if (host_bits & (float_flag_underflow | float_flag_output_denormal)) |
4373f3ce PB |
3678 | target_bits |= 8; |
3679 | if (host_bits & float_flag_inexact) | |
3680 | target_bits |= 0x10; | |
cecd8504 PM |
3681 | if (host_bits & float_flag_input_denormal) |
3682 | target_bits |= 0x80; | |
4373f3ce PB |
3683 | return target_bits; |
3684 | } | |
3685 | ||
0ecb72a5 | 3686 | uint32_t HELPER(vfp_get_fpscr)(CPUARMState *env) |
4373f3ce PB |
3687 | { |
3688 | int i; | |
3689 | uint32_t fpscr; | |
3690 | ||
3691 | fpscr = (env->vfp.xregs[ARM_VFP_FPSCR] & 0xffc8ffff) | |
3692 | | (env->vfp.vec_len << 16) | |
3693 | | (env->vfp.vec_stride << 20); | |
3694 | i = get_float_exception_flags(&env->vfp.fp_status); | |
3a492f3a | 3695 | i |= get_float_exception_flags(&env->vfp.standard_fp_status); |
4373f3ce PB |
3696 | fpscr |= vfp_exceptbits_from_host(i); |
3697 | return fpscr; | |
3698 | } | |
3699 | ||
0ecb72a5 | 3700 | uint32_t vfp_get_fpscr(CPUARMState *env) |
01653295 PM |
3701 | { |
3702 | return HELPER(vfp_get_fpscr)(env); | |
3703 | } | |
3704 | ||
4373f3ce PB |
3705 | /* Convert vfp exception flags to target form. */ |
3706 | static inline int vfp_exceptbits_to_host(int target_bits) | |
3707 | { | |
3708 | int host_bits = 0; | |
3709 | ||
3710 | if (target_bits & 1) | |
3711 | host_bits |= float_flag_invalid; | |
3712 | if (target_bits & 2) | |
3713 | host_bits |= float_flag_divbyzero; | |
3714 | if (target_bits & 4) | |
3715 | host_bits |= float_flag_overflow; | |
3716 | if (target_bits & 8) | |
3717 | host_bits |= float_flag_underflow; | |
3718 | if (target_bits & 0x10) | |
3719 | host_bits |= float_flag_inexact; | |
cecd8504 PM |
3720 | if (target_bits & 0x80) |
3721 | host_bits |= float_flag_input_denormal; | |
4373f3ce PB |
3722 | return host_bits; |
3723 | } | |
3724 | ||
0ecb72a5 | 3725 | void HELPER(vfp_set_fpscr)(CPUARMState *env, uint32_t val) |
4373f3ce PB |
3726 | { |
3727 | int i; | |
3728 | uint32_t changed; | |
3729 | ||
3730 | changed = env->vfp.xregs[ARM_VFP_FPSCR]; | |
3731 | env->vfp.xregs[ARM_VFP_FPSCR] = (val & 0xffc8ffff); | |
3732 | env->vfp.vec_len = (val >> 16) & 7; | |
3733 | env->vfp.vec_stride = (val >> 20) & 3; | |
3734 | ||
3735 | changed ^= val; | |
3736 | if (changed & (3 << 22)) { | |
3737 | i = (val >> 22) & 3; | |
3738 | switch (i) { | |
4d3da0f3 | 3739 | case FPROUNDING_TIEEVEN: |
4373f3ce PB |
3740 | i = float_round_nearest_even; |
3741 | break; | |
4d3da0f3 | 3742 | case FPROUNDING_POSINF: |
4373f3ce PB |
3743 | i = float_round_up; |
3744 | break; | |
4d3da0f3 | 3745 | case FPROUNDING_NEGINF: |
4373f3ce PB |
3746 | i = float_round_down; |
3747 | break; | |
4d3da0f3 | 3748 | case FPROUNDING_ZERO: |
4373f3ce PB |
3749 | i = float_round_to_zero; |
3750 | break; | |
3751 | } | |
3752 | set_float_rounding_mode(i, &env->vfp.fp_status); | |
3753 | } | |
cecd8504 | 3754 | if (changed & (1 << 24)) { |
fe76d976 | 3755 | set_flush_to_zero((val & (1 << 24)) != 0, &env->vfp.fp_status); |
cecd8504 PM |
3756 | set_flush_inputs_to_zero((val & (1 << 24)) != 0, &env->vfp.fp_status); |
3757 | } | |
5c7908ed PB |
3758 | if (changed & (1 << 25)) |
3759 | set_default_nan_mode((val & (1 << 25)) != 0, &env->vfp.fp_status); | |
4373f3ce | 3760 | |
b12c390b | 3761 | i = vfp_exceptbits_to_host(val); |
4373f3ce | 3762 | set_float_exception_flags(i, &env->vfp.fp_status); |
3a492f3a | 3763 | set_float_exception_flags(0, &env->vfp.standard_fp_status); |
4373f3ce PB |
3764 | } |
3765 | ||
0ecb72a5 | 3766 | void vfp_set_fpscr(CPUARMState *env, uint32_t val) |
01653295 PM |
3767 | { |
3768 | HELPER(vfp_set_fpscr)(env, val); | |
3769 | } | |
3770 | ||
4373f3ce PB |
3771 | #define VFP_HELPER(name, p) HELPER(glue(glue(vfp_,name),p)) |
3772 | ||
3773 | #define VFP_BINOP(name) \ | |
ae1857ec | 3774 | float32 VFP_HELPER(name, s)(float32 a, float32 b, void *fpstp) \ |
4373f3ce | 3775 | { \ |
ae1857ec PM |
3776 | float_status *fpst = fpstp; \ |
3777 | return float32_ ## name(a, b, fpst); \ | |
4373f3ce | 3778 | } \ |
ae1857ec | 3779 | float64 VFP_HELPER(name, d)(float64 a, float64 b, void *fpstp) \ |
4373f3ce | 3780 | { \ |
ae1857ec PM |
3781 | float_status *fpst = fpstp; \ |
3782 | return float64_ ## name(a, b, fpst); \ | |
4373f3ce PB |
3783 | } |
3784 | VFP_BINOP(add) | |
3785 | VFP_BINOP(sub) | |
3786 | VFP_BINOP(mul) | |
3787 | VFP_BINOP(div) | |
f71a2ae5 PM |
3788 | VFP_BINOP(min) |
3789 | VFP_BINOP(max) | |
3790 | VFP_BINOP(minnum) | |
3791 | VFP_BINOP(maxnum) | |
4373f3ce PB |
3792 | #undef VFP_BINOP |
3793 | ||
3794 | float32 VFP_HELPER(neg, s)(float32 a) | |
3795 | { | |
3796 | return float32_chs(a); | |
3797 | } | |
3798 | ||
3799 | float64 VFP_HELPER(neg, d)(float64 a) | |
3800 | { | |
66230e0d | 3801 | return float64_chs(a); |
4373f3ce PB |
3802 | } |
3803 | ||
3804 | float32 VFP_HELPER(abs, s)(float32 a) | |
3805 | { | |
3806 | return float32_abs(a); | |
3807 | } | |
3808 | ||
3809 | float64 VFP_HELPER(abs, d)(float64 a) | |
3810 | { | |
66230e0d | 3811 | return float64_abs(a); |
4373f3ce PB |
3812 | } |
3813 | ||
0ecb72a5 | 3814 | float32 VFP_HELPER(sqrt, s)(float32 a, CPUARMState *env) |
4373f3ce PB |
3815 | { |
3816 | return float32_sqrt(a, &env->vfp.fp_status); | |
3817 | } | |
3818 | ||
0ecb72a5 | 3819 | float64 VFP_HELPER(sqrt, d)(float64 a, CPUARMState *env) |
4373f3ce PB |
3820 | { |
3821 | return float64_sqrt(a, &env->vfp.fp_status); | |
3822 | } | |
3823 | ||
3824 | /* XXX: check quiet/signaling case */ | |
3825 | #define DO_VFP_cmp(p, type) \ | |
0ecb72a5 | 3826 | void VFP_HELPER(cmp, p)(type a, type b, CPUARMState *env) \ |
4373f3ce PB |
3827 | { \ |
3828 | uint32_t flags; \ | |
3829 | switch(type ## _compare_quiet(a, b, &env->vfp.fp_status)) { \ | |
3830 | case 0: flags = 0x6; break; \ | |
3831 | case -1: flags = 0x8; break; \ | |
3832 | case 1: flags = 0x2; break; \ | |
3833 | default: case 2: flags = 0x3; break; \ | |
3834 | } \ | |
3835 | env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \ | |
3836 | | (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \ | |
3837 | } \ | |
0ecb72a5 | 3838 | void VFP_HELPER(cmpe, p)(type a, type b, CPUARMState *env) \ |
4373f3ce PB |
3839 | { \ |
3840 | uint32_t flags; \ | |
3841 | switch(type ## _compare(a, b, &env->vfp.fp_status)) { \ | |
3842 | case 0: flags = 0x6; break; \ | |
3843 | case -1: flags = 0x8; break; \ | |
3844 | case 1: flags = 0x2; break; \ | |
3845 | default: case 2: flags = 0x3; break; \ | |
3846 | } \ | |
3847 | env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \ | |
3848 | | (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \ | |
3849 | } | |
3850 | DO_VFP_cmp(s, float32) | |
3851 | DO_VFP_cmp(d, float64) | |
3852 | #undef DO_VFP_cmp | |
3853 | ||
5500b06c | 3854 | /* Integer to float and float to integer conversions */ |
4373f3ce | 3855 | |
5500b06c PM |
3856 | #define CONV_ITOF(name, fsz, sign) \ |
3857 | float##fsz HELPER(name)(uint32_t x, void *fpstp) \ | |
3858 | { \ | |
3859 | float_status *fpst = fpstp; \ | |
85836979 | 3860 | return sign##int32_to_##float##fsz((sign##int32_t)x, fpst); \ |
4373f3ce PB |
3861 | } |
3862 | ||
5500b06c PM |
3863 | #define CONV_FTOI(name, fsz, sign, round) \ |
3864 | uint32_t HELPER(name)(float##fsz x, void *fpstp) \ | |
3865 | { \ | |
3866 | float_status *fpst = fpstp; \ | |
3867 | if (float##fsz##_is_any_nan(x)) { \ | |
3868 | float_raise(float_flag_invalid, fpst); \ | |
3869 | return 0; \ | |
3870 | } \ | |
3871 | return float##fsz##_to_##sign##int32##round(x, fpst); \ | |
4373f3ce PB |
3872 | } |
3873 | ||
5500b06c PM |
3874 | #define FLOAT_CONVS(name, p, fsz, sign) \ |
3875 | CONV_ITOF(vfp_##name##to##p, fsz, sign) \ | |
3876 | CONV_FTOI(vfp_to##name##p, fsz, sign, ) \ | |
3877 | CONV_FTOI(vfp_to##name##z##p, fsz, sign, _round_to_zero) | |
4373f3ce | 3878 | |
5500b06c PM |
3879 | FLOAT_CONVS(si, s, 32, ) |
3880 | FLOAT_CONVS(si, d, 64, ) | |
3881 | FLOAT_CONVS(ui, s, 32, u) | |
3882 | FLOAT_CONVS(ui, d, 64, u) | |
4373f3ce | 3883 | |
5500b06c PM |
3884 | #undef CONV_ITOF |
3885 | #undef CONV_FTOI | |
3886 | #undef FLOAT_CONVS | |
4373f3ce PB |
3887 | |
3888 | /* floating point conversion */ | |
0ecb72a5 | 3889 | float64 VFP_HELPER(fcvtd, s)(float32 x, CPUARMState *env) |
4373f3ce | 3890 | { |
2d627737 PM |
3891 | float64 r = float32_to_float64(x, &env->vfp.fp_status); |
3892 | /* ARM requires that S<->D conversion of any kind of NaN generates | |
3893 | * a quiet NaN by forcing the most significant frac bit to 1. | |
3894 | */ | |
3895 | return float64_maybe_silence_nan(r); | |
4373f3ce PB |
3896 | } |
3897 | ||
0ecb72a5 | 3898 | float32 VFP_HELPER(fcvts, d)(float64 x, CPUARMState *env) |
4373f3ce | 3899 | { |
2d627737 PM |
3900 | float32 r = float64_to_float32(x, &env->vfp.fp_status); |
3901 | /* ARM requires that S<->D conversion of any kind of NaN generates | |
3902 | * a quiet NaN by forcing the most significant frac bit to 1. | |
3903 | */ | |
3904 | return float32_maybe_silence_nan(r); | |
4373f3ce PB |
3905 | } |
3906 | ||
3907 | /* VFP3 fixed point conversion. */ | |
16d5b3ca | 3908 | #define VFP_CONV_FIX_FLOAT(name, p, fsz, isz, itype) \ |
8ed697e8 WN |
3909 | float##fsz HELPER(vfp_##name##to##p)(uint##isz##_t x, uint32_t shift, \ |
3910 | void *fpstp) \ | |
4373f3ce | 3911 | { \ |
5500b06c | 3912 | float_status *fpst = fpstp; \ |
622465e1 | 3913 | float##fsz tmp; \ |
8ed697e8 | 3914 | tmp = itype##_to_##float##fsz(x, fpst); \ |
5500b06c | 3915 | return float##fsz##_scalbn(tmp, -(int)shift, fpst); \ |
16d5b3ca WN |
3916 | } |
3917 | ||
abe66f70 PM |
3918 | /* Notice that we want only input-denormal exception flags from the |
3919 | * scalbn operation: the other possible flags (overflow+inexact if | |
3920 | * we overflow to infinity, output-denormal) aren't correct for the | |
3921 | * complete scale-and-convert operation. | |
3922 | */ | |
16d5b3ca WN |
3923 | #define VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, round) \ |
3924 | uint##isz##_t HELPER(vfp_to##name##p##round)(float##fsz x, \ | |
3925 | uint32_t shift, \ | |
3926 | void *fpstp) \ | |
4373f3ce | 3927 | { \ |
5500b06c | 3928 | float_status *fpst = fpstp; \ |
abe66f70 | 3929 | int old_exc_flags = get_float_exception_flags(fpst); \ |
622465e1 PM |
3930 | float##fsz tmp; \ |
3931 | if (float##fsz##_is_any_nan(x)) { \ | |
5500b06c | 3932 | float_raise(float_flag_invalid, fpst); \ |
622465e1 | 3933 | return 0; \ |
09d9487f | 3934 | } \ |
5500b06c | 3935 | tmp = float##fsz##_scalbn(x, shift, fpst); \ |
abe66f70 PM |
3936 | old_exc_flags |= get_float_exception_flags(fpst) \ |
3937 | & float_flag_input_denormal; \ | |
3938 | set_float_exception_flags(old_exc_flags, fpst); \ | |
16d5b3ca | 3939 | return float##fsz##_to_##itype##round(tmp, fpst); \ |
622465e1 PM |
3940 | } |
3941 | ||
16d5b3ca WN |
3942 | #define VFP_CONV_FIX(name, p, fsz, isz, itype) \ |
3943 | VFP_CONV_FIX_FLOAT(name, p, fsz, isz, itype) \ | |
3c6a074a WN |
3944 | VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, _round_to_zero) \ |
3945 | VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, ) | |
3946 | ||
3947 | #define VFP_CONV_FIX_A64(name, p, fsz, isz, itype) \ | |
3948 | VFP_CONV_FIX_FLOAT(name, p, fsz, isz, itype) \ | |
3949 | VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, ) | |
16d5b3ca | 3950 | |
8ed697e8 WN |
3951 | VFP_CONV_FIX(sh, d, 64, 64, int16) |
3952 | VFP_CONV_FIX(sl, d, 64, 64, int32) | |
3c6a074a | 3953 | VFP_CONV_FIX_A64(sq, d, 64, 64, int64) |
8ed697e8 WN |
3954 | VFP_CONV_FIX(uh, d, 64, 64, uint16) |
3955 | VFP_CONV_FIX(ul, d, 64, 64, uint32) | |
3c6a074a | 3956 | VFP_CONV_FIX_A64(uq, d, 64, 64, uint64) |
8ed697e8 WN |
3957 | VFP_CONV_FIX(sh, s, 32, 32, int16) |
3958 | VFP_CONV_FIX(sl, s, 32, 32, int32) | |
3c6a074a | 3959 | VFP_CONV_FIX_A64(sq, s, 32, 64, int64) |
8ed697e8 WN |
3960 | VFP_CONV_FIX(uh, s, 32, 32, uint16) |
3961 | VFP_CONV_FIX(ul, s, 32, 32, uint32) | |
3c6a074a | 3962 | VFP_CONV_FIX_A64(uq, s, 32, 64, uint64) |
4373f3ce | 3963 | #undef VFP_CONV_FIX |
16d5b3ca WN |
3964 | #undef VFP_CONV_FIX_FLOAT |
3965 | #undef VFP_CONV_FLOAT_FIX_ROUND | |
4373f3ce | 3966 | |
52a1f6a3 AG |
3967 | /* Set the current fp rounding mode and return the old one. |
3968 | * The argument is a softfloat float_round_ value. | |
3969 | */ | |
3970 | uint32_t HELPER(set_rmode)(uint32_t rmode, CPUARMState *env) | |
3971 | { | |
3972 | float_status *fp_status = &env->vfp.fp_status; | |
3973 | ||
3974 | uint32_t prev_rmode = get_float_rounding_mode(fp_status); | |
3975 | set_float_rounding_mode(rmode, fp_status); | |
3976 | ||
3977 | return prev_rmode; | |
3978 | } | |
3979 | ||
43630e58 WN |
3980 | /* Set the current fp rounding mode in the standard fp status and return |
3981 | * the old one. This is for NEON instructions that need to change the | |
3982 | * rounding mode but wish to use the standard FPSCR values for everything | |
3983 | * else. Always set the rounding mode back to the correct value after | |
3984 | * modifying it. | |
3985 | * The argument is a softfloat float_round_ value. | |
3986 | */ | |
3987 | uint32_t HELPER(set_neon_rmode)(uint32_t rmode, CPUARMState *env) | |
3988 | { | |
3989 | float_status *fp_status = &env->vfp.standard_fp_status; | |
3990 | ||
3991 | uint32_t prev_rmode = get_float_rounding_mode(fp_status); | |
3992 | set_float_rounding_mode(rmode, fp_status); | |
3993 | ||
3994 | return prev_rmode; | |
3995 | } | |
3996 | ||
60011498 | 3997 | /* Half precision conversions. */ |
0ecb72a5 | 3998 | static float32 do_fcvt_f16_to_f32(uint32_t a, CPUARMState *env, float_status *s) |
60011498 | 3999 | { |
60011498 | 4000 | int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0; |
fb91678d PM |
4001 | float32 r = float16_to_float32(make_float16(a), ieee, s); |
4002 | if (ieee) { | |
4003 | return float32_maybe_silence_nan(r); | |
4004 | } | |
4005 | return r; | |
60011498 PB |
4006 | } |
4007 | ||
0ecb72a5 | 4008 | static uint32_t do_fcvt_f32_to_f16(float32 a, CPUARMState *env, float_status *s) |
60011498 | 4009 | { |
60011498 | 4010 | int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0; |
fb91678d PM |
4011 | float16 r = float32_to_float16(a, ieee, s); |
4012 | if (ieee) { | |
4013 | r = float16_maybe_silence_nan(r); | |
4014 | } | |
4015 | return float16_val(r); | |
60011498 PB |
4016 | } |
4017 | ||
0ecb72a5 | 4018 | float32 HELPER(neon_fcvt_f16_to_f32)(uint32_t a, CPUARMState *env) |
2d981da7 PM |
4019 | { |
4020 | return do_fcvt_f16_to_f32(a, env, &env->vfp.standard_fp_status); | |
4021 | } | |
4022 | ||
0ecb72a5 | 4023 | uint32_t HELPER(neon_fcvt_f32_to_f16)(float32 a, CPUARMState *env) |
2d981da7 PM |
4024 | { |
4025 | return do_fcvt_f32_to_f16(a, env, &env->vfp.standard_fp_status); | |
4026 | } | |
4027 | ||
0ecb72a5 | 4028 | float32 HELPER(vfp_fcvt_f16_to_f32)(uint32_t a, CPUARMState *env) |
2d981da7 PM |
4029 | { |
4030 | return do_fcvt_f16_to_f32(a, env, &env->vfp.fp_status); | |
4031 | } | |
4032 | ||
0ecb72a5 | 4033 | uint32_t HELPER(vfp_fcvt_f32_to_f16)(float32 a, CPUARMState *env) |
2d981da7 PM |
4034 | { |
4035 | return do_fcvt_f32_to_f16(a, env, &env->vfp.fp_status); | |
4036 | } | |
4037 | ||
8900aad2 PM |
4038 | float64 HELPER(vfp_fcvt_f16_to_f64)(uint32_t a, CPUARMState *env) |
4039 | { | |
4040 | int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0; | |
4041 | float64 r = float16_to_float64(make_float16(a), ieee, &env->vfp.fp_status); | |
4042 | if (ieee) { | |
4043 | return float64_maybe_silence_nan(r); | |
4044 | } | |
4045 | return r; | |
4046 | } | |
4047 | ||
4048 | uint32_t HELPER(vfp_fcvt_f64_to_f16)(float64 a, CPUARMState *env) | |
4049 | { | |
4050 | int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0; | |
4051 | float16 r = float64_to_float16(a, ieee, &env->vfp.fp_status); | |
4052 | if (ieee) { | |
4053 | r = float16_maybe_silence_nan(r); | |
4054 | } | |
4055 | return float16_val(r); | |
4056 | } | |
4057 | ||
dda3ec49 | 4058 | #define float32_two make_float32(0x40000000) |
6aae3df1 PM |
4059 | #define float32_three make_float32(0x40400000) |
4060 | #define float32_one_point_five make_float32(0x3fc00000) | |
dda3ec49 | 4061 | |
0ecb72a5 | 4062 | float32 HELPER(recps_f32)(float32 a, float32 b, CPUARMState *env) |
4373f3ce | 4063 | { |
dda3ec49 PM |
4064 | float_status *s = &env->vfp.standard_fp_status; |
4065 | if ((float32_is_infinity(a) && float32_is_zero_or_denormal(b)) || | |
4066 | (float32_is_infinity(b) && float32_is_zero_or_denormal(a))) { | |
43fe9bdb PM |
4067 | if (!(float32_is_zero(a) || float32_is_zero(b))) { |
4068 | float_raise(float_flag_input_denormal, s); | |
4069 | } | |
dda3ec49 PM |
4070 | return float32_two; |
4071 | } | |
4072 | return float32_sub(float32_two, float32_mul(a, b, s), s); | |
4373f3ce PB |
4073 | } |
4074 | ||
0ecb72a5 | 4075 | float32 HELPER(rsqrts_f32)(float32 a, float32 b, CPUARMState *env) |
4373f3ce | 4076 | { |
71826966 | 4077 | float_status *s = &env->vfp.standard_fp_status; |
9ea62f57 PM |
4078 | float32 product; |
4079 | if ((float32_is_infinity(a) && float32_is_zero_or_denormal(b)) || | |
4080 | (float32_is_infinity(b) && float32_is_zero_or_denormal(a))) { | |
43fe9bdb PM |
4081 | if (!(float32_is_zero(a) || float32_is_zero(b))) { |
4082 | float_raise(float_flag_input_denormal, s); | |
4083 | } | |
6aae3df1 | 4084 | return float32_one_point_five; |
9ea62f57 | 4085 | } |
6aae3df1 PM |
4086 | product = float32_mul(a, b, s); |
4087 | return float32_div(float32_sub(float32_three, product, s), float32_two, s); | |
4373f3ce PB |
4088 | } |
4089 | ||
8f8e3aa4 PB |
4090 | /* NEON helpers. */ |
4091 | ||
56bf4fe2 CL |
4092 | /* Constants 256 and 512 are used in some helpers; we avoid relying on |
4093 | * int->float conversions at run-time. */ | |
4094 | #define float64_256 make_float64(0x4070000000000000LL) | |
4095 | #define float64_512 make_float64(0x4080000000000000LL) | |
4096 | ||
fe0e4872 CL |
4097 | /* The algorithm that must be used to calculate the estimate |
4098 | * is specified by the ARM ARM. | |
4099 | */ | |
0ecb72a5 | 4100 | static float64 recip_estimate(float64 a, CPUARMState *env) |
fe0e4872 | 4101 | { |
1146a817 PM |
4102 | /* These calculations mustn't set any fp exception flags, |
4103 | * so we use a local copy of the fp_status. | |
4104 | */ | |
4105 | float_status dummy_status = env->vfp.standard_fp_status; | |
4106 | float_status *s = &dummy_status; | |
fe0e4872 CL |
4107 | /* q = (int)(a * 512.0) */ |
4108 | float64 q = float64_mul(float64_512, a, s); | |
4109 | int64_t q_int = float64_to_int64_round_to_zero(q, s); | |
4110 | ||
4111 | /* r = 1.0 / (((double)q + 0.5) / 512.0) */ | |
4112 | q = int64_to_float64(q_int, s); | |
4113 | q = float64_add(q, float64_half, s); | |
4114 | q = float64_div(q, float64_512, s); | |
4115 | q = float64_div(float64_one, q, s); | |
4116 | ||
4117 | /* s = (int)(256.0 * r + 0.5) */ | |
4118 | q = float64_mul(q, float64_256, s); | |
4119 | q = float64_add(q, float64_half, s); | |
4120 | q_int = float64_to_int64_round_to_zero(q, s); | |
4121 | ||
4122 | /* return (double)s / 256.0 */ | |
4123 | return float64_div(int64_to_float64(q_int, s), float64_256, s); | |
4124 | } | |
4125 | ||
0ecb72a5 | 4126 | float32 HELPER(recpe_f32)(float32 a, CPUARMState *env) |
4373f3ce | 4127 | { |
fe0e4872 CL |
4128 | float_status *s = &env->vfp.standard_fp_status; |
4129 | float64 f64; | |
4130 | uint32_t val32 = float32_val(a); | |
4131 | ||
4132 | int result_exp; | |
4133 | int a_exp = (val32 & 0x7f800000) >> 23; | |
4134 | int sign = val32 & 0x80000000; | |
4135 | ||
4136 | if (float32_is_any_nan(a)) { | |
4137 | if (float32_is_signaling_nan(a)) { | |
4138 | float_raise(float_flag_invalid, s); | |
4139 | } | |
4140 | return float32_default_nan; | |
4141 | } else if (float32_is_infinity(a)) { | |
4142 | return float32_set_sign(float32_zero, float32_is_neg(a)); | |
4143 | } else if (float32_is_zero_or_denormal(a)) { | |
43fe9bdb PM |
4144 | if (!float32_is_zero(a)) { |
4145 | float_raise(float_flag_input_denormal, s); | |
4146 | } | |
fe0e4872 CL |
4147 | float_raise(float_flag_divbyzero, s); |
4148 | return float32_set_sign(float32_infinity, float32_is_neg(a)); | |
4149 | } else if (a_exp >= 253) { | |
4150 | float_raise(float_flag_underflow, s); | |
4151 | return float32_set_sign(float32_zero, float32_is_neg(a)); | |
4152 | } | |
4153 | ||
4154 | f64 = make_float64((0x3feULL << 52) | |
4155 | | ((int64_t)(val32 & 0x7fffff) << 29)); | |
4156 | ||
4157 | result_exp = 253 - a_exp; | |
4158 | ||
4159 | f64 = recip_estimate(f64, env); | |
4160 | ||
4161 | val32 = sign | |
4162 | | ((result_exp & 0xff) << 23) | |
4163 | | ((float64_val(f64) >> 29) & 0x7fffff); | |
4164 | return make_float32(val32); | |
4373f3ce PB |
4165 | } |
4166 | ||
e07be5d2 CL |
4167 | /* The algorithm that must be used to calculate the estimate |
4168 | * is specified by the ARM ARM. | |
4169 | */ | |
0ecb72a5 | 4170 | static float64 recip_sqrt_estimate(float64 a, CPUARMState *env) |
e07be5d2 | 4171 | { |
1146a817 PM |
4172 | /* These calculations mustn't set any fp exception flags, |
4173 | * so we use a local copy of the fp_status. | |
4174 | */ | |
4175 | float_status dummy_status = env->vfp.standard_fp_status; | |
4176 | float_status *s = &dummy_status; | |
e07be5d2 CL |
4177 | float64 q; |
4178 | int64_t q_int; | |
4179 | ||
4180 | if (float64_lt(a, float64_half, s)) { | |
4181 | /* range 0.25 <= a < 0.5 */ | |
4182 | ||
4183 | /* a in units of 1/512 rounded down */ | |
4184 | /* q0 = (int)(a * 512.0); */ | |
4185 | q = float64_mul(float64_512, a, s); | |
4186 | q_int = float64_to_int64_round_to_zero(q, s); | |
4187 | ||
4188 | /* reciprocal root r */ | |
4189 | /* r = 1.0 / sqrt(((double)q0 + 0.5) / 512.0); */ | |
4190 | q = int64_to_float64(q_int, s); | |
4191 | q = float64_add(q, float64_half, s); | |
4192 | q = float64_div(q, float64_512, s); | |
4193 | q = float64_sqrt(q, s); | |
4194 | q = float64_div(float64_one, q, s); | |
4195 | } else { | |
4196 | /* range 0.5 <= a < 1.0 */ | |
4197 | ||
4198 | /* a in units of 1/256 rounded down */ | |
4199 | /* q1 = (int)(a * 256.0); */ | |
4200 | q = float64_mul(float64_256, a, s); | |
4201 | int64_t q_int = float64_to_int64_round_to_zero(q, s); | |
4202 | ||
4203 | /* reciprocal root r */ | |
4204 | /* r = 1.0 /sqrt(((double)q1 + 0.5) / 256); */ | |
4205 | q = int64_to_float64(q_int, s); | |
4206 | q = float64_add(q, float64_half, s); | |
4207 | q = float64_div(q, float64_256, s); | |
4208 | q = float64_sqrt(q, s); | |
4209 | q = float64_div(float64_one, q, s); | |
4210 | } | |
4211 | /* r in units of 1/256 rounded to nearest */ | |
4212 | /* s = (int)(256.0 * r + 0.5); */ | |
4213 | ||
4214 | q = float64_mul(q, float64_256,s ); | |
4215 | q = float64_add(q, float64_half, s); | |
4216 | q_int = float64_to_int64_round_to_zero(q, s); | |
4217 | ||
4218 | /* return (double)s / 256.0;*/ | |
4219 | return float64_div(int64_to_float64(q_int, s), float64_256, s); | |
4220 | } | |
4221 | ||
0ecb72a5 | 4222 | float32 HELPER(rsqrte_f32)(float32 a, CPUARMState *env) |
4373f3ce | 4223 | { |
e07be5d2 CL |
4224 | float_status *s = &env->vfp.standard_fp_status; |
4225 | int result_exp; | |
4226 | float64 f64; | |
4227 | uint32_t val; | |
4228 | uint64_t val64; | |
4229 | ||
4230 | val = float32_val(a); | |
4231 | ||
4232 | if (float32_is_any_nan(a)) { | |
4233 | if (float32_is_signaling_nan(a)) { | |
4234 | float_raise(float_flag_invalid, s); | |
4235 | } | |
4236 | return float32_default_nan; | |
4237 | } else if (float32_is_zero_or_denormal(a)) { | |
43fe9bdb PM |
4238 | if (!float32_is_zero(a)) { |
4239 | float_raise(float_flag_input_denormal, s); | |
4240 | } | |
e07be5d2 CL |
4241 | float_raise(float_flag_divbyzero, s); |
4242 | return float32_set_sign(float32_infinity, float32_is_neg(a)); | |
4243 | } else if (float32_is_neg(a)) { | |
4244 | float_raise(float_flag_invalid, s); | |
4245 | return float32_default_nan; | |
4246 | } else if (float32_is_infinity(a)) { | |
4247 | return float32_zero; | |
4248 | } | |
4249 | ||
4250 | /* Normalize to a double-precision value between 0.25 and 1.0, | |
4251 | * preserving the parity of the exponent. */ | |
4252 | if ((val & 0x800000) == 0) { | |
4253 | f64 = make_float64(((uint64_t)(val & 0x80000000) << 32) | |
4254 | | (0x3feULL << 52) | |
4255 | | ((uint64_t)(val & 0x7fffff) << 29)); | |
4256 | } else { | |
4257 | f64 = make_float64(((uint64_t)(val & 0x80000000) << 32) | |
4258 | | (0x3fdULL << 52) | |
4259 | | ((uint64_t)(val & 0x7fffff) << 29)); | |
4260 | } | |
4261 | ||
4262 | result_exp = (380 - ((val & 0x7f800000) >> 23)) / 2; | |
4263 | ||
4264 | f64 = recip_sqrt_estimate(f64, env); | |
4265 | ||
4266 | val64 = float64_val(f64); | |
4267 | ||
26cc6abf | 4268 | val = ((result_exp & 0xff) << 23) |
e07be5d2 CL |
4269 | | ((val64 >> 29) & 0x7fffff); |
4270 | return make_float32(val); | |
4373f3ce PB |
4271 | } |
4272 | ||
0ecb72a5 | 4273 | uint32_t HELPER(recpe_u32)(uint32_t a, CPUARMState *env) |
4373f3ce | 4274 | { |
fe0e4872 CL |
4275 | float64 f64; |
4276 | ||
4277 | if ((a & 0x80000000) == 0) { | |
4278 | return 0xffffffff; | |
4279 | } | |
4280 | ||
4281 | f64 = make_float64((0x3feULL << 52) | |
4282 | | ((int64_t)(a & 0x7fffffff) << 21)); | |
4283 | ||
4284 | f64 = recip_estimate (f64, env); | |
4285 | ||
4286 | return 0x80000000 | ((float64_val(f64) >> 21) & 0x7fffffff); | |
4373f3ce PB |
4287 | } |
4288 | ||
0ecb72a5 | 4289 | uint32_t HELPER(rsqrte_u32)(uint32_t a, CPUARMState *env) |
4373f3ce | 4290 | { |
e07be5d2 CL |
4291 | float64 f64; |
4292 | ||
4293 | if ((a & 0xc0000000) == 0) { | |
4294 | return 0xffffffff; | |
4295 | } | |
4296 | ||
4297 | if (a & 0x80000000) { | |
4298 | f64 = make_float64((0x3feULL << 52) | |
4299 | | ((uint64_t)(a & 0x7fffffff) << 21)); | |
4300 | } else { /* bits 31-30 == '01' */ | |
4301 | f64 = make_float64((0x3fdULL << 52) | |
4302 | | ((uint64_t)(a & 0x3fffffff) << 22)); | |
4303 | } | |
4304 | ||
4305 | f64 = recip_sqrt_estimate(f64, env); | |
4306 | ||
4307 | return 0x80000000 | ((float64_val(f64) >> 21) & 0x7fffffff); | |
4373f3ce | 4308 | } |
fe1479c3 | 4309 | |
da97f52c PM |
4310 | /* VFPv4 fused multiply-accumulate */ |
4311 | float32 VFP_HELPER(muladd, s)(float32 a, float32 b, float32 c, void *fpstp) | |
4312 | { | |
4313 | float_status *fpst = fpstp; | |
4314 | return float32_muladd(a, b, c, 0, fpst); | |
4315 | } | |
4316 | ||
4317 | float64 VFP_HELPER(muladd, d)(float64 a, float64 b, float64 c, void *fpstp) | |
4318 | { | |
4319 | float_status *fpst = fpstp; | |
4320 | return float64_muladd(a, b, c, 0, fpst); | |
4321 | } | |
d9b0848d PM |
4322 | |
4323 | /* ARMv8 round to integral */ | |
4324 | float32 HELPER(rints_exact)(float32 x, void *fp_status) | |
4325 | { | |
4326 | return float32_round_to_int(x, fp_status); | |
4327 | } | |
4328 | ||
4329 | float64 HELPER(rintd_exact)(float64 x, void *fp_status) | |
4330 | { | |
4331 | return float64_round_to_int(x, fp_status); | |
4332 | } | |
4333 | ||
4334 | float32 HELPER(rints)(float32 x, void *fp_status) | |
4335 | { | |
4336 | int old_flags = get_float_exception_flags(fp_status), new_flags; | |
4337 | float32 ret; | |
4338 | ||
4339 | ret = float32_round_to_int(x, fp_status); | |
4340 | ||
4341 | /* Suppress any inexact exceptions the conversion produced */ | |
4342 | if (!(old_flags & float_flag_inexact)) { | |
4343 | new_flags = get_float_exception_flags(fp_status); | |
4344 | set_float_exception_flags(new_flags & ~float_flag_inexact, fp_status); | |
4345 | } | |
4346 | ||
4347 | return ret; | |
4348 | } | |
4349 | ||
4350 | float64 HELPER(rintd)(float64 x, void *fp_status) | |
4351 | { | |
4352 | int old_flags = get_float_exception_flags(fp_status), new_flags; | |
4353 | float64 ret; | |
4354 | ||
4355 | ret = float64_round_to_int(x, fp_status); | |
4356 | ||
4357 | new_flags = get_float_exception_flags(fp_status); | |
4358 | ||
4359 | /* Suppress any inexact exceptions the conversion produced */ | |
4360 | if (!(old_flags & float_flag_inexact)) { | |
4361 | new_flags = get_float_exception_flags(fp_status); | |
4362 | set_float_exception_flags(new_flags & ~float_flag_inexact, fp_status); | |
4363 | } | |
4364 | ||
4365 | return ret; | |
4366 | } | |
9972da66 WN |
4367 | |
4368 | /* Convert ARM rounding mode to softfloat */ | |
4369 | int arm_rmode_to_sf(int rmode) | |
4370 | { | |
4371 | switch (rmode) { | |
4372 | case FPROUNDING_TIEAWAY: | |
4373 | rmode = float_round_ties_away; | |
4374 | break; | |
4375 | case FPROUNDING_ODD: | |
4376 | /* FIXME: add support for TIEAWAY and ODD */ | |
4377 | qemu_log_mask(LOG_UNIMP, "arm: unimplemented rounding mode: %d\n", | |
4378 | rmode); | |
4379 | case FPROUNDING_TIEEVEN: | |
4380 | default: | |
4381 | rmode = float_round_nearest_even; | |
4382 | break; | |
4383 | case FPROUNDING_POSINF: | |
4384 | rmode = float_round_up; | |
4385 | break; | |
4386 | case FPROUNDING_NEGINF: | |
4387 | rmode = float_round_down; | |
4388 | break; | |
4389 | case FPROUNDING_ZERO: | |
4390 | rmode = float_round_to_zero; | |
4391 | break; | |
4392 | } | |
4393 | return rmode; | |
4394 | } |