]>
Commit | Line | Data |
---|---|---|
b5ff1b31 | 1 | #include "cpu.h" |
ccd38087 | 2 | #include "internals.h" |
022c62cb | 3 | #include "exec/gdbstub.h" |
2ef6175a | 4 | #include "exec/helper-proto.h" |
1de7afc9 | 5 | #include "qemu/host-utils.h" |
78027bb6 | 6 | #include "sysemu/arch_init.h" |
9c17d615 | 7 | #include "sysemu/sysemu.h" |
1de7afc9 | 8 | #include "qemu/bitops.h" |
eb0ecd5a | 9 | #include "qemu/crc32c.h" |
f08b6170 | 10 | #include "exec/cpu_ldst.h" |
1d854765 | 11 | #include "arm_ldst.h" |
eb0ecd5a | 12 | #include <zlib.h> /* For crc32 */ |
0b03bdfc | 13 | |
4a501606 | 14 | #ifndef CONFIG_USER_ONLY |
2c8dd318 | 15 | static inline int get_phys_addr(CPUARMState *env, target_ulong address, |
4a501606 | 16 | int access_type, int is_user, |
a8170e5e | 17 | hwaddr *phys_ptr, int *prot, |
4a501606 | 18 | target_ulong *page_size); |
7c2cb42b AF |
19 | |
20 | /* Definitions for the PMCCNTR and PMCR registers */ | |
21 | #define PMCRD 0x8 | |
22 | #define PMCRC 0x4 | |
23 | #define PMCRE 0x1 | |
4a501606 PM |
24 | #endif |
25 | ||
0ecb72a5 | 26 | static int vfp_gdb_get_reg(CPUARMState *env, uint8_t *buf, int reg) |
56aebc89 PB |
27 | { |
28 | int nregs; | |
29 | ||
30 | /* VFP data registers are always little-endian. */ | |
31 | nregs = arm_feature(env, ARM_FEATURE_VFP3) ? 32 : 16; | |
32 | if (reg < nregs) { | |
33 | stfq_le_p(buf, env->vfp.regs[reg]); | |
34 | return 8; | |
35 | } | |
36 | if (arm_feature(env, ARM_FEATURE_NEON)) { | |
37 | /* Aliases for Q regs. */ | |
38 | nregs += 16; | |
39 | if (reg < nregs) { | |
40 | stfq_le_p(buf, env->vfp.regs[(reg - 32) * 2]); | |
41 | stfq_le_p(buf + 8, env->vfp.regs[(reg - 32) * 2 + 1]); | |
42 | return 16; | |
43 | } | |
44 | } | |
45 | switch (reg - nregs) { | |
46 | case 0: stl_p(buf, env->vfp.xregs[ARM_VFP_FPSID]); return 4; | |
47 | case 1: stl_p(buf, env->vfp.xregs[ARM_VFP_FPSCR]); return 4; | |
48 | case 2: stl_p(buf, env->vfp.xregs[ARM_VFP_FPEXC]); return 4; | |
49 | } | |
50 | return 0; | |
51 | } | |
52 | ||
0ecb72a5 | 53 | static int vfp_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg) |
56aebc89 PB |
54 | { |
55 | int nregs; | |
56 | ||
57 | nregs = arm_feature(env, ARM_FEATURE_VFP3) ? 32 : 16; | |
58 | if (reg < nregs) { | |
59 | env->vfp.regs[reg] = ldfq_le_p(buf); | |
60 | return 8; | |
61 | } | |
62 | if (arm_feature(env, ARM_FEATURE_NEON)) { | |
63 | nregs += 16; | |
64 | if (reg < nregs) { | |
65 | env->vfp.regs[(reg - 32) * 2] = ldfq_le_p(buf); | |
66 | env->vfp.regs[(reg - 32) * 2 + 1] = ldfq_le_p(buf + 8); | |
67 | return 16; | |
68 | } | |
69 | } | |
70 | switch (reg - nregs) { | |
71 | case 0: env->vfp.xregs[ARM_VFP_FPSID] = ldl_p(buf); return 4; | |
72 | case 1: env->vfp.xregs[ARM_VFP_FPSCR] = ldl_p(buf); return 4; | |
71b3c3de | 73 | case 2: env->vfp.xregs[ARM_VFP_FPEXC] = ldl_p(buf) & (1 << 30); return 4; |
56aebc89 PB |
74 | } |
75 | return 0; | |
76 | } | |
77 | ||
6a669427 PM |
78 | static int aarch64_fpu_gdb_get_reg(CPUARMState *env, uint8_t *buf, int reg) |
79 | { | |
80 | switch (reg) { | |
81 | case 0 ... 31: | |
82 | /* 128 bit FP register */ | |
83 | stfq_le_p(buf, env->vfp.regs[reg * 2]); | |
84 | stfq_le_p(buf + 8, env->vfp.regs[reg * 2 + 1]); | |
85 | return 16; | |
86 | case 32: | |
87 | /* FPSR */ | |
88 | stl_p(buf, vfp_get_fpsr(env)); | |
89 | return 4; | |
90 | case 33: | |
91 | /* FPCR */ | |
92 | stl_p(buf, vfp_get_fpcr(env)); | |
93 | return 4; | |
94 | default: | |
95 | return 0; | |
96 | } | |
97 | } | |
98 | ||
99 | static int aarch64_fpu_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg) | |
100 | { | |
101 | switch (reg) { | |
102 | case 0 ... 31: | |
103 | /* 128 bit FP register */ | |
104 | env->vfp.regs[reg * 2] = ldfq_le_p(buf); | |
105 | env->vfp.regs[reg * 2 + 1] = ldfq_le_p(buf + 8); | |
106 | return 16; | |
107 | case 32: | |
108 | /* FPSR */ | |
109 | vfp_set_fpsr(env, ldl_p(buf)); | |
110 | return 4; | |
111 | case 33: | |
112 | /* FPCR */ | |
113 | vfp_set_fpcr(env, ldl_p(buf)); | |
114 | return 4; | |
115 | default: | |
116 | return 0; | |
117 | } | |
118 | } | |
119 | ||
c4241c7d | 120 | static uint64_t raw_read(CPUARMState *env, const ARMCPRegInfo *ri) |
d4e6df63 | 121 | { |
67ed771d | 122 | if (cpreg_field_is_64bit(ri)) { |
c4241c7d | 123 | return CPREG_FIELD64(env, ri); |
22d9e1a9 | 124 | } else { |
c4241c7d | 125 | return CPREG_FIELD32(env, ri); |
22d9e1a9 | 126 | } |
d4e6df63 PM |
127 | } |
128 | ||
c4241c7d PM |
129 | static void raw_write(CPUARMState *env, const ARMCPRegInfo *ri, |
130 | uint64_t value) | |
d4e6df63 | 131 | { |
67ed771d | 132 | if (cpreg_field_is_64bit(ri)) { |
22d9e1a9 PM |
133 | CPREG_FIELD64(env, ri) = value; |
134 | } else { | |
135 | CPREG_FIELD32(env, ri) = value; | |
136 | } | |
d4e6df63 PM |
137 | } |
138 | ||
59a1c327 | 139 | static uint64_t read_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri) |
721fae12 | 140 | { |
59a1c327 | 141 | /* Raw read of a coprocessor register (as needed for migration, etc). */ |
721fae12 | 142 | if (ri->type & ARM_CP_CONST) { |
59a1c327 | 143 | return ri->resetvalue; |
721fae12 | 144 | } else if (ri->raw_readfn) { |
59a1c327 | 145 | return ri->raw_readfn(env, ri); |
721fae12 | 146 | } else if (ri->readfn) { |
59a1c327 | 147 | return ri->readfn(env, ri); |
721fae12 | 148 | } else { |
59a1c327 | 149 | return raw_read(env, ri); |
721fae12 | 150 | } |
721fae12 PM |
151 | } |
152 | ||
59a1c327 | 153 | static void write_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri, |
7900e9f1 | 154 | uint64_t v) |
721fae12 PM |
155 | { |
156 | /* Raw write of a coprocessor register (as needed for migration, etc). | |
721fae12 PM |
157 | * Note that constant registers are treated as write-ignored; the |
158 | * caller should check for success by whether a readback gives the | |
159 | * value written. | |
160 | */ | |
161 | if (ri->type & ARM_CP_CONST) { | |
59a1c327 | 162 | return; |
721fae12 | 163 | } else if (ri->raw_writefn) { |
c4241c7d | 164 | ri->raw_writefn(env, ri, v); |
721fae12 | 165 | } else if (ri->writefn) { |
c4241c7d | 166 | ri->writefn(env, ri, v); |
721fae12 | 167 | } else { |
afb2530f | 168 | raw_write(env, ri, v); |
721fae12 | 169 | } |
721fae12 PM |
170 | } |
171 | ||
172 | bool write_cpustate_to_list(ARMCPU *cpu) | |
173 | { | |
174 | /* Write the coprocessor state from cpu->env to the (index,value) list. */ | |
175 | int i; | |
176 | bool ok = true; | |
177 | ||
178 | for (i = 0; i < cpu->cpreg_array_len; i++) { | |
179 | uint32_t regidx = kvm_to_cpreg_id(cpu->cpreg_indexes[i]); | |
180 | const ARMCPRegInfo *ri; | |
59a1c327 | 181 | |
60322b39 | 182 | ri = get_arm_cp_reginfo(cpu->cp_regs, regidx); |
721fae12 PM |
183 | if (!ri) { |
184 | ok = false; | |
185 | continue; | |
186 | } | |
187 | if (ri->type & ARM_CP_NO_MIGRATE) { | |
188 | continue; | |
189 | } | |
59a1c327 | 190 | cpu->cpreg_values[i] = read_raw_cp_reg(&cpu->env, ri); |
721fae12 PM |
191 | } |
192 | return ok; | |
193 | } | |
194 | ||
195 | bool write_list_to_cpustate(ARMCPU *cpu) | |
196 | { | |
197 | int i; | |
198 | bool ok = true; | |
199 | ||
200 | for (i = 0; i < cpu->cpreg_array_len; i++) { | |
201 | uint32_t regidx = kvm_to_cpreg_id(cpu->cpreg_indexes[i]); | |
202 | uint64_t v = cpu->cpreg_values[i]; | |
721fae12 PM |
203 | const ARMCPRegInfo *ri; |
204 | ||
60322b39 | 205 | ri = get_arm_cp_reginfo(cpu->cp_regs, regidx); |
721fae12 PM |
206 | if (!ri) { |
207 | ok = false; | |
208 | continue; | |
209 | } | |
210 | if (ri->type & ARM_CP_NO_MIGRATE) { | |
211 | continue; | |
212 | } | |
213 | /* Write value and confirm it reads back as written | |
214 | * (to catch read-only registers and partially read-only | |
215 | * registers where the incoming migration value doesn't match) | |
216 | */ | |
59a1c327 PM |
217 | write_raw_cp_reg(&cpu->env, ri, v); |
218 | if (read_raw_cp_reg(&cpu->env, ri) != v) { | |
721fae12 PM |
219 | ok = false; |
220 | } | |
221 | } | |
222 | return ok; | |
223 | } | |
224 | ||
225 | static void add_cpreg_to_list(gpointer key, gpointer opaque) | |
226 | { | |
227 | ARMCPU *cpu = opaque; | |
228 | uint64_t regidx; | |
229 | const ARMCPRegInfo *ri; | |
230 | ||
231 | regidx = *(uint32_t *)key; | |
60322b39 | 232 | ri = get_arm_cp_reginfo(cpu->cp_regs, regidx); |
721fae12 PM |
233 | |
234 | if (!(ri->type & ARM_CP_NO_MIGRATE)) { | |
235 | cpu->cpreg_indexes[cpu->cpreg_array_len] = cpreg_to_kvm_id(regidx); | |
236 | /* The value array need not be initialized at this point */ | |
237 | cpu->cpreg_array_len++; | |
238 | } | |
239 | } | |
240 | ||
241 | static void count_cpreg(gpointer key, gpointer opaque) | |
242 | { | |
243 | ARMCPU *cpu = opaque; | |
244 | uint64_t regidx; | |
245 | const ARMCPRegInfo *ri; | |
246 | ||
247 | regidx = *(uint32_t *)key; | |
60322b39 | 248 | ri = get_arm_cp_reginfo(cpu->cp_regs, regidx); |
721fae12 PM |
249 | |
250 | if (!(ri->type & ARM_CP_NO_MIGRATE)) { | |
251 | cpu->cpreg_array_len++; | |
252 | } | |
253 | } | |
254 | ||
255 | static gint cpreg_key_compare(gconstpointer a, gconstpointer b) | |
256 | { | |
cbf239b7 AR |
257 | uint64_t aidx = cpreg_to_kvm_id(*(uint32_t *)a); |
258 | uint64_t bidx = cpreg_to_kvm_id(*(uint32_t *)b); | |
721fae12 | 259 | |
cbf239b7 AR |
260 | if (aidx > bidx) { |
261 | return 1; | |
262 | } | |
263 | if (aidx < bidx) { | |
264 | return -1; | |
265 | } | |
266 | return 0; | |
721fae12 PM |
267 | } |
268 | ||
82a3a118 PM |
269 | static void cpreg_make_keylist(gpointer key, gpointer value, gpointer udata) |
270 | { | |
271 | GList **plist = udata; | |
272 | ||
273 | *plist = g_list_prepend(*plist, key); | |
274 | } | |
275 | ||
721fae12 PM |
276 | void init_cpreg_list(ARMCPU *cpu) |
277 | { | |
278 | /* Initialise the cpreg_tuples[] array based on the cp_regs hash. | |
279 | * Note that we require cpreg_tuples[] to be sorted by key ID. | |
280 | */ | |
82a3a118 | 281 | GList *keys = NULL; |
721fae12 PM |
282 | int arraylen; |
283 | ||
82a3a118 PM |
284 | g_hash_table_foreach(cpu->cp_regs, cpreg_make_keylist, &keys); |
285 | ||
721fae12 PM |
286 | keys = g_list_sort(keys, cpreg_key_compare); |
287 | ||
288 | cpu->cpreg_array_len = 0; | |
289 | ||
290 | g_list_foreach(keys, count_cpreg, cpu); | |
291 | ||
292 | arraylen = cpu->cpreg_array_len; | |
293 | cpu->cpreg_indexes = g_new(uint64_t, arraylen); | |
294 | cpu->cpreg_values = g_new(uint64_t, arraylen); | |
295 | cpu->cpreg_vmstate_indexes = g_new(uint64_t, arraylen); | |
296 | cpu->cpreg_vmstate_values = g_new(uint64_t, arraylen); | |
297 | cpu->cpreg_vmstate_array_len = cpu->cpreg_array_len; | |
298 | cpu->cpreg_array_len = 0; | |
299 | ||
300 | g_list_foreach(keys, add_cpreg_to_list, cpu); | |
301 | ||
302 | assert(cpu->cpreg_array_len == arraylen); | |
303 | ||
304 | g_list_free(keys); | |
305 | } | |
306 | ||
c4241c7d | 307 | static void dacr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) |
c983fe6c | 308 | { |
00c8cb0a AF |
309 | ARMCPU *cpu = arm_env_get_cpu(env); |
310 | ||
8d5c773e | 311 | raw_write(env, ri, value); |
00c8cb0a | 312 | tlb_flush(CPU(cpu), 1); /* Flush TLB as domain not tracked in TLB */ |
c983fe6c PM |
313 | } |
314 | ||
c4241c7d | 315 | static void fcse_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) |
08de207b | 316 | { |
00c8cb0a AF |
317 | ARMCPU *cpu = arm_env_get_cpu(env); |
318 | ||
8d5c773e | 319 | if (raw_read(env, ri) != value) { |
08de207b PM |
320 | /* Unlike real hardware the qemu TLB uses virtual addresses, |
321 | * not modified virtual addresses, so this causes a TLB flush. | |
322 | */ | |
00c8cb0a | 323 | tlb_flush(CPU(cpu), 1); |
8d5c773e | 324 | raw_write(env, ri, value); |
08de207b | 325 | } |
08de207b | 326 | } |
c4241c7d PM |
327 | |
328 | static void contextidr_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
329 | uint64_t value) | |
08de207b | 330 | { |
00c8cb0a AF |
331 | ARMCPU *cpu = arm_env_get_cpu(env); |
332 | ||
8d5c773e | 333 | if (raw_read(env, ri) != value && !arm_feature(env, ARM_FEATURE_MPU) |
014406b5 | 334 | && !extended_addresses_enabled(env)) { |
08de207b PM |
335 | /* For VMSA (when not using the LPAE long descriptor page table |
336 | * format) this register includes the ASID, so do a TLB flush. | |
337 | * For PMSA it is purely a process ID and no action is needed. | |
338 | */ | |
00c8cb0a | 339 | tlb_flush(CPU(cpu), 1); |
08de207b | 340 | } |
8d5c773e | 341 | raw_write(env, ri, value); |
08de207b PM |
342 | } |
343 | ||
c4241c7d PM |
344 | static void tlbiall_write(CPUARMState *env, const ARMCPRegInfo *ri, |
345 | uint64_t value) | |
d929823f PM |
346 | { |
347 | /* Invalidate all (TLBIALL) */ | |
00c8cb0a AF |
348 | ARMCPU *cpu = arm_env_get_cpu(env); |
349 | ||
350 | tlb_flush(CPU(cpu), 1); | |
d929823f PM |
351 | } |
352 | ||
c4241c7d PM |
353 | static void tlbimva_write(CPUARMState *env, const ARMCPRegInfo *ri, |
354 | uint64_t value) | |
d929823f PM |
355 | { |
356 | /* Invalidate single TLB entry by MVA and ASID (TLBIMVA) */ | |
31b030d4 AF |
357 | ARMCPU *cpu = arm_env_get_cpu(env); |
358 | ||
359 | tlb_flush_page(CPU(cpu), value & TARGET_PAGE_MASK); | |
d929823f PM |
360 | } |
361 | ||
c4241c7d PM |
362 | static void tlbiasid_write(CPUARMState *env, const ARMCPRegInfo *ri, |
363 | uint64_t value) | |
d929823f PM |
364 | { |
365 | /* Invalidate by ASID (TLBIASID) */ | |
00c8cb0a AF |
366 | ARMCPU *cpu = arm_env_get_cpu(env); |
367 | ||
368 | tlb_flush(CPU(cpu), value == 0); | |
d929823f PM |
369 | } |
370 | ||
c4241c7d PM |
371 | static void tlbimvaa_write(CPUARMState *env, const ARMCPRegInfo *ri, |
372 | uint64_t value) | |
d929823f PM |
373 | { |
374 | /* Invalidate single entry by MVA, all ASIDs (TLBIMVAA) */ | |
31b030d4 AF |
375 | ARMCPU *cpu = arm_env_get_cpu(env); |
376 | ||
377 | tlb_flush_page(CPU(cpu), value & TARGET_PAGE_MASK); | |
d929823f PM |
378 | } |
379 | ||
fa439fc5 PM |
380 | /* IS variants of TLB operations must affect all cores */ |
381 | static void tlbiall_is_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
382 | uint64_t value) | |
383 | { | |
384 | CPUState *other_cs; | |
385 | ||
386 | CPU_FOREACH(other_cs) { | |
387 | tlb_flush(other_cs, 1); | |
388 | } | |
389 | } | |
390 | ||
391 | static void tlbiasid_is_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
392 | uint64_t value) | |
393 | { | |
394 | CPUState *other_cs; | |
395 | ||
396 | CPU_FOREACH(other_cs) { | |
397 | tlb_flush(other_cs, value == 0); | |
398 | } | |
399 | } | |
400 | ||
401 | static void tlbimva_is_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
402 | uint64_t value) | |
403 | { | |
404 | CPUState *other_cs; | |
405 | ||
406 | CPU_FOREACH(other_cs) { | |
407 | tlb_flush_page(other_cs, value & TARGET_PAGE_MASK); | |
408 | } | |
409 | } | |
410 | ||
411 | static void tlbimvaa_is_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
412 | uint64_t value) | |
413 | { | |
414 | CPUState *other_cs; | |
415 | ||
416 | CPU_FOREACH(other_cs) { | |
417 | tlb_flush_page(other_cs, value & TARGET_PAGE_MASK); | |
418 | } | |
419 | } | |
420 | ||
e9aa6c21 | 421 | static const ARMCPRegInfo cp_reginfo[] = { |
08de207b PM |
422 | { .name = "FCSEIDR", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 0, |
423 | .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c13_fcse), | |
d4e6df63 | 424 | .resetvalue = 0, .writefn = fcse_write, .raw_writefn = raw_write, }, |
014406b5 PM |
425 | { .name = "CONTEXTIDR", .state = ARM_CP_STATE_BOTH, |
426 | .opc0 = 3, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 1, | |
427 | .access = PL1_RW, | |
428 | .fieldoffset = offsetof(CPUARMState, cp15.contextidr_el1), | |
d4e6df63 | 429 | .resetvalue = 0, .writefn = contextidr_write, .raw_writefn = raw_write, }, |
9449fdf6 PM |
430 | REGINFO_SENTINEL |
431 | }; | |
432 | ||
433 | static const ARMCPRegInfo not_v8_cp_reginfo[] = { | |
434 | /* NB: Some of these registers exist in v8 but with more precise | |
435 | * definitions that don't use CP_ANY wildcards (mostly in v8_cp_reginfo[]). | |
436 | */ | |
437 | /* MMU Domain access control / MPU write buffer control */ | |
438 | { .name = "DACR", .cp = 15, | |
439 | .crn = 3, .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY, | |
440 | .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c3), | |
441 | .resetvalue = 0, .writefn = dacr_write, .raw_writefn = raw_write, }, | |
4fdd17dd PM |
442 | /* ??? This covers not just the impdef TLB lockdown registers but also |
443 | * some v7VMSA registers relating to TEX remap, so it is overly broad. | |
444 | */ | |
445 | { .name = "TLB_LOCKDOWN", .cp = 15, .crn = 10, .crm = CP_ANY, | |
446 | .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_NOP }, | |
c4804214 PM |
447 | /* Cache maintenance ops; some of this space may be overridden later. */ |
448 | { .name = "CACHEMAINT", .cp = 15, .crn = 7, .crm = CP_ANY, | |
449 | .opc1 = 0, .opc2 = CP_ANY, .access = PL1_W, | |
450 | .type = ARM_CP_NOP | ARM_CP_OVERRIDE }, | |
e9aa6c21 PM |
451 | REGINFO_SENTINEL |
452 | }; | |
453 | ||
7d57f408 PM |
454 | static const ARMCPRegInfo not_v6_cp_reginfo[] = { |
455 | /* Not all pre-v6 cores implemented this WFI, so this is slightly | |
456 | * over-broad. | |
457 | */ | |
458 | { .name = "WFI_v5", .cp = 15, .crn = 7, .crm = 8, .opc1 = 0, .opc2 = 2, | |
459 | .access = PL1_W, .type = ARM_CP_WFI }, | |
460 | REGINFO_SENTINEL | |
461 | }; | |
462 | ||
463 | static const ARMCPRegInfo not_v7_cp_reginfo[] = { | |
464 | /* Standard v6 WFI (also used in some pre-v6 cores); not in v7 (which | |
465 | * is UNPREDICTABLE; we choose to NOP as most implementations do). | |
466 | */ | |
467 | { .name = "WFI_v6", .cp = 15, .crn = 7, .crm = 0, .opc1 = 0, .opc2 = 4, | |
468 | .access = PL1_W, .type = ARM_CP_WFI }, | |
34f90529 PM |
469 | /* L1 cache lockdown. Not architectural in v6 and earlier but in practice |
470 | * implemented in 926, 946, 1026, 1136, 1176 and 11MPCore. StrongARM and | |
471 | * OMAPCP will override this space. | |
472 | */ | |
473 | { .name = "DLOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 0, .opc2 = 0, | |
474 | .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_data), | |
475 | .resetvalue = 0 }, | |
476 | { .name = "ILOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 0, .opc2 = 1, | |
477 | .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_insn), | |
478 | .resetvalue = 0 }, | |
776d4e5c PM |
479 | /* v6 doesn't have the cache ID registers but Linux reads them anyway */ |
480 | { .name = "DUMMY", .cp = 15, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = CP_ANY, | |
d4e6df63 PM |
481 | .access = PL1_R, .type = ARM_CP_CONST | ARM_CP_NO_MIGRATE, |
482 | .resetvalue = 0 }, | |
50300698 PM |
483 | /* We don't implement pre-v7 debug but most CPUs had at least a DBGDIDR; |
484 | * implementing it as RAZ means the "debug architecture version" bits | |
485 | * will read as a reserved value, which should cause Linux to not try | |
486 | * to use the debug hardware. | |
487 | */ | |
488 | { .name = "DBGDIDR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 0, | |
489 | .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
995939a6 PM |
490 | /* MMU TLB control. Note that the wildcarding means we cover not just |
491 | * the unified TLB ops but also the dside/iside/inner-shareable variants. | |
492 | */ | |
493 | { .name = "TLBIALL", .cp = 15, .crn = 8, .crm = CP_ANY, | |
494 | .opc1 = CP_ANY, .opc2 = 0, .access = PL1_W, .writefn = tlbiall_write, | |
495 | .type = ARM_CP_NO_MIGRATE }, | |
496 | { .name = "TLBIMVA", .cp = 15, .crn = 8, .crm = CP_ANY, | |
497 | .opc1 = CP_ANY, .opc2 = 1, .access = PL1_W, .writefn = tlbimva_write, | |
498 | .type = ARM_CP_NO_MIGRATE }, | |
499 | { .name = "TLBIASID", .cp = 15, .crn = 8, .crm = CP_ANY, | |
500 | .opc1 = CP_ANY, .opc2 = 2, .access = PL1_W, .writefn = tlbiasid_write, | |
501 | .type = ARM_CP_NO_MIGRATE }, | |
502 | { .name = "TLBIMVAA", .cp = 15, .crn = 8, .crm = CP_ANY, | |
503 | .opc1 = CP_ANY, .opc2 = 3, .access = PL1_W, .writefn = tlbimvaa_write, | |
504 | .type = ARM_CP_NO_MIGRATE }, | |
7d57f408 PM |
505 | REGINFO_SENTINEL |
506 | }; | |
507 | ||
c4241c7d PM |
508 | static void cpacr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
509 | uint64_t value) | |
2771db27 | 510 | { |
f0aff255 FA |
511 | uint32_t mask = 0; |
512 | ||
513 | /* In ARMv8 most bits of CPACR_EL1 are RES0. */ | |
514 | if (!arm_feature(env, ARM_FEATURE_V8)) { | |
515 | /* ARMv7 defines bits for unimplemented coprocessors as RAZ/WI. | |
516 | * ASEDIS [31] and D32DIS [30] are both UNK/SBZP without VFP. | |
517 | * TRCDIS [28] is RAZ/WI since we do not implement a trace macrocell. | |
518 | */ | |
519 | if (arm_feature(env, ARM_FEATURE_VFP)) { | |
520 | /* VFP coprocessor: cp10 & cp11 [23:20] */ | |
521 | mask |= (1 << 31) | (1 << 30) | (0xf << 20); | |
522 | ||
523 | if (!arm_feature(env, ARM_FEATURE_NEON)) { | |
524 | /* ASEDIS [31] bit is RAO/WI */ | |
525 | value |= (1 << 31); | |
526 | } | |
527 | ||
528 | /* VFPv3 and upwards with NEON implement 32 double precision | |
529 | * registers (D0-D31). | |
530 | */ | |
531 | if (!arm_feature(env, ARM_FEATURE_NEON) || | |
532 | !arm_feature(env, ARM_FEATURE_VFP3)) { | |
533 | /* D32DIS [30] is RAO/WI if D16-31 are not implemented. */ | |
534 | value |= (1 << 30); | |
535 | } | |
536 | } | |
537 | value &= mask; | |
2771db27 | 538 | } |
f0aff255 | 539 | env->cp15.c1_coproc = value; |
2771db27 PM |
540 | } |
541 | ||
7d57f408 PM |
542 | static const ARMCPRegInfo v6_cp_reginfo[] = { |
543 | /* prefetch by MVA in v6, NOP in v7 */ | |
544 | { .name = "MVA_prefetch", | |
545 | .cp = 15, .crn = 7, .crm = 13, .opc1 = 0, .opc2 = 1, | |
546 | .access = PL1_W, .type = ARM_CP_NOP }, | |
547 | { .name = "ISB", .cp = 15, .crn = 7, .crm = 5, .opc1 = 0, .opc2 = 4, | |
548 | .access = PL0_W, .type = ARM_CP_NOP }, | |
091fd17c | 549 | { .name = "DSB", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 4, |
7d57f408 | 550 | .access = PL0_W, .type = ARM_CP_NOP }, |
091fd17c | 551 | { .name = "DMB", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 5, |
7d57f408 | 552 | .access = PL0_W, .type = ARM_CP_NOP }, |
06d76f31 | 553 | { .name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 2, |
6cd8a264 | 554 | .access = PL1_RW, |
2f0180c5 | 555 | .fieldoffset = offsetofhigh32(CPUARMState, cp15.far_el[1]), |
06d76f31 PM |
556 | .resetvalue = 0, }, |
557 | /* Watchpoint Fault Address Register : should actually only be present | |
558 | * for 1136, 1176, 11MPCore. | |
559 | */ | |
560 | { .name = "WFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1, | |
561 | .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0, }, | |
34222fb8 PM |
562 | { .name = "CPACR", .state = ARM_CP_STATE_BOTH, .opc0 = 3, |
563 | .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 2, | |
2771db27 PM |
564 | .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c1_coproc), |
565 | .resetvalue = 0, .writefn = cpacr_write }, | |
7d57f408 PM |
566 | REGINFO_SENTINEL |
567 | }; | |
568 | ||
fcd25206 | 569 | static CPAccessResult pmreg_access(CPUARMState *env, const ARMCPRegInfo *ri) |
200ac0ef | 570 | { |
3b163b01 | 571 | /* Performance monitor registers user accessibility is controlled |
fcd25206 | 572 | * by PMUSERENR. |
200ac0ef | 573 | */ |
dcbff19b | 574 | if (arm_current_el(env) == 0 && !env->cp15.c9_pmuserenr) { |
fcd25206 | 575 | return CP_ACCESS_TRAP; |
200ac0ef | 576 | } |
fcd25206 | 577 | return CP_ACCESS_OK; |
200ac0ef PM |
578 | } |
579 | ||
7c2cb42b | 580 | #ifndef CONFIG_USER_ONLY |
87124fde AF |
581 | |
582 | static inline bool arm_ccnt_enabled(CPUARMState *env) | |
583 | { | |
584 | /* This does not support checking PMCCFILTR_EL0 register */ | |
585 | ||
586 | if (!(env->cp15.c9_pmcr & PMCRE)) { | |
587 | return false; | |
588 | } | |
589 | ||
590 | return true; | |
591 | } | |
592 | ||
ec7b4ce4 AF |
593 | void pmccntr_sync(CPUARMState *env) |
594 | { | |
595 | uint64_t temp_ticks; | |
596 | ||
597 | temp_ticks = muldiv64(qemu_clock_get_us(QEMU_CLOCK_VIRTUAL), | |
598 | get_ticks_per_sec(), 1000000); | |
599 | ||
600 | if (env->cp15.c9_pmcr & PMCRD) { | |
601 | /* Increment once every 64 processor clock cycles */ | |
602 | temp_ticks /= 64; | |
603 | } | |
604 | ||
605 | if (arm_ccnt_enabled(env)) { | |
606 | env->cp15.c15_ccnt = temp_ticks - env->cp15.c15_ccnt; | |
607 | } | |
608 | } | |
609 | ||
c4241c7d PM |
610 | static void pmcr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
611 | uint64_t value) | |
200ac0ef | 612 | { |
942a155b | 613 | pmccntr_sync(env); |
7c2cb42b AF |
614 | |
615 | if (value & PMCRC) { | |
616 | /* The counter has been reset */ | |
617 | env->cp15.c15_ccnt = 0; | |
618 | } | |
619 | ||
200ac0ef PM |
620 | /* only the DP, X, D and E bits are writable */ |
621 | env->cp15.c9_pmcr &= ~0x39; | |
622 | env->cp15.c9_pmcr |= (value & 0x39); | |
7c2cb42b | 623 | |
942a155b | 624 | pmccntr_sync(env); |
7c2cb42b AF |
625 | } |
626 | ||
627 | static uint64_t pmccntr_read(CPUARMState *env, const ARMCPRegInfo *ri) | |
628 | { | |
c92c0687 | 629 | uint64_t total_ticks; |
7c2cb42b | 630 | |
942a155b | 631 | if (!arm_ccnt_enabled(env)) { |
7c2cb42b AF |
632 | /* Counter is disabled, do not change value */ |
633 | return env->cp15.c15_ccnt; | |
634 | } | |
635 | ||
c92c0687 AF |
636 | total_ticks = muldiv64(qemu_clock_get_us(QEMU_CLOCK_VIRTUAL), |
637 | get_ticks_per_sec(), 1000000); | |
7c2cb42b AF |
638 | |
639 | if (env->cp15.c9_pmcr & PMCRD) { | |
640 | /* Increment once every 64 processor clock cycles */ | |
641 | total_ticks /= 64; | |
642 | } | |
643 | return total_ticks - env->cp15.c15_ccnt; | |
644 | } | |
645 | ||
646 | static void pmccntr_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
647 | uint64_t value) | |
648 | { | |
c92c0687 | 649 | uint64_t total_ticks; |
7c2cb42b | 650 | |
942a155b | 651 | if (!arm_ccnt_enabled(env)) { |
7c2cb42b AF |
652 | /* Counter is disabled, set the absolute value */ |
653 | env->cp15.c15_ccnt = value; | |
654 | return; | |
655 | } | |
656 | ||
c92c0687 AF |
657 | total_ticks = muldiv64(qemu_clock_get_us(QEMU_CLOCK_VIRTUAL), |
658 | get_ticks_per_sec(), 1000000); | |
7c2cb42b AF |
659 | |
660 | if (env->cp15.c9_pmcr & PMCRD) { | |
661 | /* Increment once every 64 processor clock cycles */ | |
662 | total_ticks /= 64; | |
663 | } | |
664 | env->cp15.c15_ccnt = total_ticks - value; | |
200ac0ef | 665 | } |
421c7ebd PC |
666 | |
667 | static void pmccntr_write32(CPUARMState *env, const ARMCPRegInfo *ri, | |
668 | uint64_t value) | |
669 | { | |
670 | uint64_t cur_val = pmccntr_read(env, NULL); | |
671 | ||
672 | pmccntr_write(env, ri, deposit64(cur_val, 0, 32, value)); | |
673 | } | |
674 | ||
ec7b4ce4 AF |
675 | #else /* CONFIG_USER_ONLY */ |
676 | ||
677 | void pmccntr_sync(CPUARMState *env) | |
678 | { | |
679 | } | |
680 | ||
7c2cb42b | 681 | #endif |
200ac0ef | 682 | |
0614601c AF |
683 | static void pmccfiltr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
684 | uint64_t value) | |
685 | { | |
686 | pmccntr_sync(env); | |
687 | env->cp15.pmccfiltr_el0 = value & 0x7E000000; | |
688 | pmccntr_sync(env); | |
689 | } | |
690 | ||
c4241c7d | 691 | static void pmcntenset_write(CPUARMState *env, const ARMCPRegInfo *ri, |
200ac0ef PM |
692 | uint64_t value) |
693 | { | |
200ac0ef PM |
694 | value &= (1 << 31); |
695 | env->cp15.c9_pmcnten |= value; | |
200ac0ef PM |
696 | } |
697 | ||
c4241c7d PM |
698 | static void pmcntenclr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
699 | uint64_t value) | |
200ac0ef | 700 | { |
200ac0ef PM |
701 | value &= (1 << 31); |
702 | env->cp15.c9_pmcnten &= ~value; | |
200ac0ef PM |
703 | } |
704 | ||
c4241c7d PM |
705 | static void pmovsr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
706 | uint64_t value) | |
200ac0ef | 707 | { |
200ac0ef | 708 | env->cp15.c9_pmovsr &= ~value; |
200ac0ef PM |
709 | } |
710 | ||
c4241c7d PM |
711 | static void pmxevtyper_write(CPUARMState *env, const ARMCPRegInfo *ri, |
712 | uint64_t value) | |
200ac0ef | 713 | { |
200ac0ef | 714 | env->cp15.c9_pmxevtyper = value & 0xff; |
200ac0ef PM |
715 | } |
716 | ||
c4241c7d | 717 | static void pmuserenr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
200ac0ef PM |
718 | uint64_t value) |
719 | { | |
720 | env->cp15.c9_pmuserenr = value & 1; | |
200ac0ef PM |
721 | } |
722 | ||
c4241c7d PM |
723 | static void pmintenset_write(CPUARMState *env, const ARMCPRegInfo *ri, |
724 | uint64_t value) | |
200ac0ef PM |
725 | { |
726 | /* We have no event counters so only the C bit can be changed */ | |
727 | value &= (1 << 31); | |
728 | env->cp15.c9_pminten |= value; | |
200ac0ef PM |
729 | } |
730 | ||
c4241c7d PM |
731 | static void pmintenclr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
732 | uint64_t value) | |
200ac0ef PM |
733 | { |
734 | value &= (1 << 31); | |
735 | env->cp15.c9_pminten &= ~value; | |
200ac0ef PM |
736 | } |
737 | ||
c4241c7d PM |
738 | static void vbar_write(CPUARMState *env, const ARMCPRegInfo *ri, |
739 | uint64_t value) | |
8641136c | 740 | { |
a505d7fe PM |
741 | /* Note that even though the AArch64 view of this register has bits |
742 | * [10:0] all RES0 we can only mask the bottom 5, to comply with the | |
743 | * architectural requirements for bits which are RES0 only in some | |
744 | * contexts. (ARMv8 would permit us to do no masking at all, but ARMv7 | |
745 | * requires the bottom five bits to be RAZ/WI because they're UNK/SBZP.) | |
746 | */ | |
855ea66d | 747 | raw_write(env, ri, value & ~0x1FULL); |
8641136c NR |
748 | } |
749 | ||
64e0e2de EI |
750 | static void scr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) |
751 | { | |
752 | /* We only mask off bits that are RES0 both for AArch64 and AArch32. | |
753 | * For bits that vary between AArch32/64, code needs to check the | |
754 | * current execution mode before directly using the feature bit. | |
755 | */ | |
756 | uint32_t valid_mask = SCR_AARCH64_MASK | SCR_AARCH32_MASK; | |
757 | ||
758 | if (!arm_feature(env, ARM_FEATURE_EL2)) { | |
759 | valid_mask &= ~SCR_HCE; | |
760 | ||
761 | /* On ARMv7, SMD (or SCD as it is called in v7) is only | |
762 | * supported if EL2 exists. The bit is UNK/SBZP when | |
763 | * EL2 is unavailable. In QEMU ARMv7, we force it to always zero | |
764 | * when EL2 is unavailable. | |
765 | */ | |
766 | if (arm_feature(env, ARM_FEATURE_V7)) { | |
767 | valid_mask &= ~SCR_SMD; | |
768 | } | |
769 | } | |
770 | ||
771 | /* Clear all-context RES0 bits. */ | |
772 | value &= valid_mask; | |
773 | raw_write(env, ri, value); | |
774 | } | |
775 | ||
c4241c7d | 776 | static uint64_t ccsidr_read(CPUARMState *env, const ARMCPRegInfo *ri) |
776d4e5c PM |
777 | { |
778 | ARMCPU *cpu = arm_env_get_cpu(env); | |
b85a1fd6 FA |
779 | |
780 | /* Acquire the CSSELR index from the bank corresponding to the CCSIDR | |
781 | * bank | |
782 | */ | |
783 | uint32_t index = A32_BANKED_REG_GET(env, csselr, | |
784 | ri->secure & ARM_CP_SECSTATE_S); | |
785 | ||
786 | return cpu->ccsidr[index]; | |
776d4e5c PM |
787 | } |
788 | ||
c4241c7d PM |
789 | static void csselr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
790 | uint64_t value) | |
776d4e5c | 791 | { |
8d5c773e | 792 | raw_write(env, ri, value & 0xf); |
776d4e5c PM |
793 | } |
794 | ||
1090b9c6 PM |
795 | static uint64_t isr_read(CPUARMState *env, const ARMCPRegInfo *ri) |
796 | { | |
797 | CPUState *cs = ENV_GET_CPU(env); | |
798 | uint64_t ret = 0; | |
799 | ||
800 | if (cs->interrupt_request & CPU_INTERRUPT_HARD) { | |
801 | ret |= CPSR_I; | |
802 | } | |
803 | if (cs->interrupt_request & CPU_INTERRUPT_FIQ) { | |
804 | ret |= CPSR_F; | |
805 | } | |
806 | /* External aborts are not possible in QEMU so A bit is always clear */ | |
807 | return ret; | |
808 | } | |
809 | ||
e9aa6c21 | 810 | static const ARMCPRegInfo v7_cp_reginfo[] = { |
7d57f408 PM |
811 | /* the old v6 WFI, UNPREDICTABLE in v7 but we choose to NOP */ |
812 | { .name = "NOP", .cp = 15, .crn = 7, .crm = 0, .opc1 = 0, .opc2 = 4, | |
813 | .access = PL1_W, .type = ARM_CP_NOP }, | |
200ac0ef PM |
814 | /* Performance monitors are implementation defined in v7, |
815 | * but with an ARM recommended set of registers, which we | |
816 | * follow (although we don't actually implement any counters) | |
817 | * | |
818 | * Performance registers fall into three categories: | |
819 | * (a) always UNDEF in PL0, RW in PL1 (PMINTENSET, PMINTENCLR) | |
820 | * (b) RO in PL0 (ie UNDEF on write), RW in PL1 (PMUSERENR) | |
821 | * (c) UNDEF in PL0 if PMUSERENR.EN==0, otherwise accessible (all others) | |
822 | * For the cases controlled by PMUSERENR we must set .access to PL0_RW | |
823 | * or PL0_RO as appropriate and then check PMUSERENR in the helper fn. | |
824 | */ | |
825 | { .name = "PMCNTENSET", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 1, | |
8521466b AF |
826 | .access = PL0_RW, .type = ARM_CP_NO_MIGRATE, |
827 | .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmcnten), | |
fcd25206 PM |
828 | .writefn = pmcntenset_write, |
829 | .accessfn = pmreg_access, | |
830 | .raw_writefn = raw_write }, | |
8521466b AF |
831 | { .name = "PMCNTENSET_EL0", .state = ARM_CP_STATE_AA64, |
832 | .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 1, | |
833 | .access = PL0_RW, .accessfn = pmreg_access, | |
834 | .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcnten), .resetvalue = 0, | |
835 | .writefn = pmcntenset_write, .raw_writefn = raw_write }, | |
200ac0ef | 836 | { .name = "PMCNTENCLR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 2, |
8521466b AF |
837 | .access = PL0_RW, |
838 | .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmcnten), | |
fcd25206 PM |
839 | .accessfn = pmreg_access, |
840 | .writefn = pmcntenclr_write, | |
d4e6df63 | 841 | .type = ARM_CP_NO_MIGRATE }, |
8521466b AF |
842 | { .name = "PMCNTENCLR_EL0", .state = ARM_CP_STATE_AA64, |
843 | .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 2, | |
844 | .access = PL0_RW, .accessfn = pmreg_access, | |
845 | .type = ARM_CP_NO_MIGRATE, | |
846 | .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcnten), | |
847 | .writefn = pmcntenclr_write }, | |
200ac0ef PM |
848 | { .name = "PMOVSR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 3, |
849 | .access = PL0_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_pmovsr), | |
fcd25206 PM |
850 | .accessfn = pmreg_access, |
851 | .writefn = pmovsr_write, | |
852 | .raw_writefn = raw_write }, | |
853 | /* Unimplemented so WI. */ | |
200ac0ef | 854 | { .name = "PMSWINC", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 4, |
fcd25206 | 855 | .access = PL0_W, .accessfn = pmreg_access, .type = ARM_CP_NOP }, |
200ac0ef | 856 | /* Since we don't implement any events, writing to PMSELR is UNPREDICTABLE. |
fcd25206 | 857 | * We choose to RAZ/WI. |
200ac0ef PM |
858 | */ |
859 | { .name = "PMSELR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 5, | |
fcd25206 PM |
860 | .access = PL0_RW, .type = ARM_CP_CONST, .resetvalue = 0, |
861 | .accessfn = pmreg_access }, | |
7c2cb42b | 862 | #ifndef CONFIG_USER_ONLY |
200ac0ef | 863 | { .name = "PMCCNTR", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 0, |
7c2cb42b | 864 | .access = PL0_RW, .resetvalue = 0, .type = ARM_CP_IO, |
421c7ebd | 865 | .readfn = pmccntr_read, .writefn = pmccntr_write32, |
fcd25206 | 866 | .accessfn = pmreg_access }, |
8521466b AF |
867 | { .name = "PMCCNTR_EL0", .state = ARM_CP_STATE_AA64, |
868 | .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 13, .opc2 = 0, | |
869 | .access = PL0_RW, .accessfn = pmreg_access, | |
870 | .type = ARM_CP_IO, | |
871 | .readfn = pmccntr_read, .writefn = pmccntr_write, }, | |
7c2cb42b | 872 | #endif |
8521466b AF |
873 | { .name = "PMCCFILTR_EL0", .state = ARM_CP_STATE_AA64, |
874 | .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 15, .opc2 = 7, | |
0614601c | 875 | .writefn = pmccfiltr_write, |
8521466b AF |
876 | .access = PL0_RW, .accessfn = pmreg_access, |
877 | .type = ARM_CP_IO, | |
878 | .fieldoffset = offsetof(CPUARMState, cp15.pmccfiltr_el0), | |
879 | .resetvalue = 0, }, | |
200ac0ef PM |
880 | { .name = "PMXEVTYPER", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 1, |
881 | .access = PL0_RW, | |
882 | .fieldoffset = offsetof(CPUARMState, cp15.c9_pmxevtyper), | |
fcd25206 PM |
883 | .accessfn = pmreg_access, .writefn = pmxevtyper_write, |
884 | .raw_writefn = raw_write }, | |
885 | /* Unimplemented, RAZ/WI. */ | |
200ac0ef | 886 | { .name = "PMXEVCNTR", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 2, |
fcd25206 PM |
887 | .access = PL0_RW, .type = ARM_CP_CONST, .resetvalue = 0, |
888 | .accessfn = pmreg_access }, | |
200ac0ef PM |
889 | { .name = "PMUSERENR", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 0, |
890 | .access = PL0_R | PL1_RW, | |
891 | .fieldoffset = offsetof(CPUARMState, cp15.c9_pmuserenr), | |
892 | .resetvalue = 0, | |
d4e6df63 | 893 | .writefn = pmuserenr_write, .raw_writefn = raw_write }, |
200ac0ef PM |
894 | { .name = "PMINTENSET", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 1, |
895 | .access = PL1_RW, | |
896 | .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten), | |
897 | .resetvalue = 0, | |
d4e6df63 | 898 | .writefn = pmintenset_write, .raw_writefn = raw_write }, |
200ac0ef | 899 | { .name = "PMINTENCLR", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 2, |
d4e6df63 | 900 | .access = PL1_RW, .type = ARM_CP_NO_MIGRATE, |
200ac0ef | 901 | .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten), |
d4e6df63 | 902 | .resetvalue = 0, .writefn = pmintenclr_write, }, |
a505d7fe PM |
903 | { .name = "VBAR", .state = ARM_CP_STATE_BOTH, |
904 | .opc0 = 3, .crn = 12, .crm = 0, .opc1 = 0, .opc2 = 0, | |
8641136c | 905 | .access = PL1_RW, .writefn = vbar_write, |
68fdb6c5 | 906 | .fieldoffset = offsetof(CPUARMState, cp15.vbar_el[1]), |
8641136c | 907 | .resetvalue = 0 }, |
7da845b0 PM |
908 | { .name = "CCSIDR", .state = ARM_CP_STATE_BOTH, |
909 | .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 0, | |
d4e6df63 | 910 | .access = PL1_R, .readfn = ccsidr_read, .type = ARM_CP_NO_MIGRATE }, |
7da845b0 PM |
911 | { .name = "CSSELR", .state = ARM_CP_STATE_BOTH, |
912 | .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 2, .opc2 = 0, | |
b85a1fd6 FA |
913 | .access = PL1_RW, .writefn = csselr_write, .resetvalue = 0, |
914 | .bank_fieldoffsets = { offsetof(CPUARMState, cp15.csselr_s), | |
915 | offsetof(CPUARMState, cp15.csselr_ns) } }, | |
776d4e5c PM |
916 | /* Auxiliary ID register: this actually has an IMPDEF value but for now |
917 | * just RAZ for all cores: | |
918 | */ | |
0ff644a7 PM |
919 | { .name = "AIDR", .state = ARM_CP_STATE_BOTH, |
920 | .opc0 = 3, .opc1 = 1, .crn = 0, .crm = 0, .opc2 = 7, | |
776d4e5c | 921 | .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 }, |
f32cdad5 PM |
922 | /* Auxiliary fault status registers: these also are IMPDEF, and we |
923 | * choose to RAZ/WI for all cores. | |
924 | */ | |
925 | { .name = "AFSR0_EL1", .state = ARM_CP_STATE_BOTH, | |
926 | .opc0 = 3, .opc1 = 0, .crn = 5, .crm = 1, .opc2 = 0, | |
927 | .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
928 | { .name = "AFSR1_EL1", .state = ARM_CP_STATE_BOTH, | |
929 | .opc0 = 3, .opc1 = 0, .crn = 5, .crm = 1, .opc2 = 1, | |
930 | .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
b0fe2427 PM |
931 | /* MAIR can just read-as-written because we don't implement caches |
932 | * and so don't need to care about memory attributes. | |
933 | */ | |
934 | { .name = "MAIR_EL1", .state = ARM_CP_STATE_AA64, | |
935 | .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 2, .opc2 = 0, | |
936 | .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.mair_el1), | |
937 | .resetvalue = 0 }, | |
938 | /* For non-long-descriptor page tables these are PRRR and NMRR; | |
939 | * regardless they still act as reads-as-written for QEMU. | |
940 | * The override is necessary because of the overly-broad TLB_LOCKDOWN | |
941 | * definition. | |
942 | */ | |
943 | { .name = "MAIR0", .state = ARM_CP_STATE_AA32, .type = ARM_CP_OVERRIDE, | |
944 | .cp = 15, .opc1 = 0, .crn = 10, .crm = 2, .opc2 = 0, .access = PL1_RW, | |
945 | .fieldoffset = offsetoflow32(CPUARMState, cp15.mair_el1), | |
946 | .resetfn = arm_cp_reset_ignore }, | |
947 | { .name = "MAIR1", .state = ARM_CP_STATE_AA32, .type = ARM_CP_OVERRIDE, | |
948 | .cp = 15, .opc1 = 0, .crn = 10, .crm = 2, .opc2 = 1, .access = PL1_RW, | |
949 | .fieldoffset = offsetofhigh32(CPUARMState, cp15.mair_el1), | |
950 | .resetfn = arm_cp_reset_ignore }, | |
1090b9c6 PM |
951 | { .name = "ISR_EL1", .state = ARM_CP_STATE_BOTH, |
952 | .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 1, .opc2 = 0, | |
953 | .type = ARM_CP_NO_MIGRATE, .access = PL1_R, .readfn = isr_read }, | |
995939a6 PM |
954 | /* 32 bit ITLB invalidates */ |
955 | { .name = "ITLBIALL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 0, | |
956 | .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn = tlbiall_write }, | |
957 | { .name = "ITLBIMVA", .cp = 15, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 1, | |
958 | .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn = tlbimva_write }, | |
959 | { .name = "ITLBIASID", .cp = 15, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 2, | |
960 | .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn = tlbiasid_write }, | |
961 | /* 32 bit DTLB invalidates */ | |
962 | { .name = "DTLBIALL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 0, | |
963 | .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn = tlbiall_write }, | |
964 | { .name = "DTLBIMVA", .cp = 15, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 1, | |
965 | .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn = tlbimva_write }, | |
966 | { .name = "DTLBIASID", .cp = 15, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 2, | |
967 | .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn = tlbiasid_write }, | |
968 | /* 32 bit TLB invalidates */ | |
969 | { .name = "TLBIALL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 0, | |
970 | .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn = tlbiall_write }, | |
971 | { .name = "TLBIMVA", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 1, | |
972 | .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn = tlbimva_write }, | |
973 | { .name = "TLBIASID", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 2, | |
974 | .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn = tlbiasid_write }, | |
975 | { .name = "TLBIMVAA", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 3, | |
976 | .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn = tlbimvaa_write }, | |
977 | REGINFO_SENTINEL | |
978 | }; | |
979 | ||
980 | static const ARMCPRegInfo v7mp_cp_reginfo[] = { | |
981 | /* 32 bit TLB invalidates, Inner Shareable */ | |
982 | { .name = "TLBIALLIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 0, | |
fa439fc5 | 983 | .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn = tlbiall_is_write }, |
995939a6 | 984 | { .name = "TLBIMVAIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 1, |
fa439fc5 | 985 | .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn = tlbimva_is_write }, |
995939a6 | 986 | { .name = "TLBIASIDIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 2, |
fa439fc5 PM |
987 | .type = ARM_CP_NO_MIGRATE, .access = PL1_W, |
988 | .writefn = tlbiasid_is_write }, | |
995939a6 | 989 | { .name = "TLBIMVAAIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 3, |
fa439fc5 PM |
990 | .type = ARM_CP_NO_MIGRATE, .access = PL1_W, |
991 | .writefn = tlbimvaa_is_write }, | |
e9aa6c21 PM |
992 | REGINFO_SENTINEL |
993 | }; | |
994 | ||
c4241c7d PM |
995 | static void teecr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
996 | uint64_t value) | |
c326b979 PM |
997 | { |
998 | value &= 1; | |
999 | env->teecr = value; | |
c326b979 PM |
1000 | } |
1001 | ||
c4241c7d | 1002 | static CPAccessResult teehbr_access(CPUARMState *env, const ARMCPRegInfo *ri) |
c326b979 | 1003 | { |
dcbff19b | 1004 | if (arm_current_el(env) == 0 && (env->teecr & 1)) { |
92611c00 | 1005 | return CP_ACCESS_TRAP; |
c326b979 | 1006 | } |
92611c00 | 1007 | return CP_ACCESS_OK; |
c326b979 PM |
1008 | } |
1009 | ||
1010 | static const ARMCPRegInfo t2ee_cp_reginfo[] = { | |
1011 | { .name = "TEECR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 6, .opc2 = 0, | |
1012 | .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, teecr), | |
1013 | .resetvalue = 0, | |
1014 | .writefn = teecr_write }, | |
1015 | { .name = "TEEHBR", .cp = 14, .crn = 1, .crm = 0, .opc1 = 6, .opc2 = 0, | |
1016 | .access = PL0_RW, .fieldoffset = offsetof(CPUARMState, teehbr), | |
92611c00 | 1017 | .accessfn = teehbr_access, .resetvalue = 0 }, |
c326b979 PM |
1018 | REGINFO_SENTINEL |
1019 | }; | |
1020 | ||
4d31c596 | 1021 | static const ARMCPRegInfo v6k_cp_reginfo[] = { |
e4fe830b PM |
1022 | { .name = "TPIDR_EL0", .state = ARM_CP_STATE_AA64, |
1023 | .opc0 = 3, .opc1 = 3, .opc2 = 2, .crn = 13, .crm = 0, | |
1024 | .access = PL0_RW, | |
1025 | .fieldoffset = offsetof(CPUARMState, cp15.tpidr_el0), .resetvalue = 0 }, | |
4d31c596 PM |
1026 | { .name = "TPIDRURW", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 2, |
1027 | .access = PL0_RW, | |
e4fe830b PM |
1028 | .fieldoffset = offsetoflow32(CPUARMState, cp15.tpidr_el0), |
1029 | .resetfn = arm_cp_reset_ignore }, | |
1030 | { .name = "TPIDRRO_EL0", .state = ARM_CP_STATE_AA64, | |
1031 | .opc0 = 3, .opc1 = 3, .opc2 = 3, .crn = 13, .crm = 0, | |
1032 | .access = PL0_R|PL1_W, | |
1033 | .fieldoffset = offsetof(CPUARMState, cp15.tpidrro_el0), .resetvalue = 0 }, | |
4d31c596 PM |
1034 | { .name = "TPIDRURO", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 3, |
1035 | .access = PL0_R|PL1_W, | |
e4fe830b PM |
1036 | .fieldoffset = offsetoflow32(CPUARMState, cp15.tpidrro_el0), |
1037 | .resetfn = arm_cp_reset_ignore }, | |
1038 | { .name = "TPIDR_EL1", .state = ARM_CP_STATE_BOTH, | |
1039 | .opc0 = 3, .opc1 = 0, .opc2 = 4, .crn = 13, .crm = 0, | |
4d31c596 | 1040 | .access = PL1_RW, |
e4fe830b | 1041 | .fieldoffset = offsetof(CPUARMState, cp15.tpidr_el1), .resetvalue = 0 }, |
4d31c596 PM |
1042 | REGINFO_SENTINEL |
1043 | }; | |
1044 | ||
55d284af PM |
1045 | #ifndef CONFIG_USER_ONLY |
1046 | ||
00108f2d PM |
1047 | static CPAccessResult gt_cntfrq_access(CPUARMState *env, const ARMCPRegInfo *ri) |
1048 | { | |
1049 | /* CNTFRQ: not visible from PL0 if both PL0PCTEN and PL0VCTEN are zero */ | |
dcbff19b | 1050 | if (arm_current_el(env) == 0 && !extract32(env->cp15.c14_cntkctl, 0, 2)) { |
00108f2d PM |
1051 | return CP_ACCESS_TRAP; |
1052 | } | |
1053 | return CP_ACCESS_OK; | |
1054 | } | |
1055 | ||
1056 | static CPAccessResult gt_counter_access(CPUARMState *env, int timeridx) | |
1057 | { | |
1058 | /* CNT[PV]CT: not visible from PL0 if ELO[PV]CTEN is zero */ | |
dcbff19b | 1059 | if (arm_current_el(env) == 0 && |
00108f2d PM |
1060 | !extract32(env->cp15.c14_cntkctl, timeridx, 1)) { |
1061 | return CP_ACCESS_TRAP; | |
1062 | } | |
1063 | return CP_ACCESS_OK; | |
1064 | } | |
1065 | ||
1066 | static CPAccessResult gt_timer_access(CPUARMState *env, int timeridx) | |
1067 | { | |
1068 | /* CNT[PV]_CVAL, CNT[PV]_CTL, CNT[PV]_TVAL: not visible from PL0 if | |
1069 | * EL0[PV]TEN is zero. | |
1070 | */ | |
dcbff19b | 1071 | if (arm_current_el(env) == 0 && |
00108f2d PM |
1072 | !extract32(env->cp15.c14_cntkctl, 9 - timeridx, 1)) { |
1073 | return CP_ACCESS_TRAP; | |
1074 | } | |
1075 | return CP_ACCESS_OK; | |
1076 | } | |
1077 | ||
1078 | static CPAccessResult gt_pct_access(CPUARMState *env, | |
1079 | const ARMCPRegInfo *ri) | |
1080 | { | |
1081 | return gt_counter_access(env, GTIMER_PHYS); | |
1082 | } | |
1083 | ||
1084 | static CPAccessResult gt_vct_access(CPUARMState *env, | |
1085 | const ARMCPRegInfo *ri) | |
1086 | { | |
1087 | return gt_counter_access(env, GTIMER_VIRT); | |
1088 | } | |
1089 | ||
1090 | static CPAccessResult gt_ptimer_access(CPUARMState *env, const ARMCPRegInfo *ri) | |
1091 | { | |
1092 | return gt_timer_access(env, GTIMER_PHYS); | |
1093 | } | |
1094 | ||
1095 | static CPAccessResult gt_vtimer_access(CPUARMState *env, const ARMCPRegInfo *ri) | |
1096 | { | |
1097 | return gt_timer_access(env, GTIMER_VIRT); | |
1098 | } | |
1099 | ||
55d284af PM |
1100 | static uint64_t gt_get_countervalue(CPUARMState *env) |
1101 | { | |
bc72ad67 | 1102 | return qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) / GTIMER_SCALE; |
55d284af PM |
1103 | } |
1104 | ||
1105 | static void gt_recalc_timer(ARMCPU *cpu, int timeridx) | |
1106 | { | |
1107 | ARMGenericTimer *gt = &cpu->env.cp15.c14_timer[timeridx]; | |
1108 | ||
1109 | if (gt->ctl & 1) { | |
1110 | /* Timer enabled: calculate and set current ISTATUS, irq, and | |
1111 | * reset timer to when ISTATUS next has to change | |
1112 | */ | |
1113 | uint64_t count = gt_get_countervalue(&cpu->env); | |
1114 | /* Note that this must be unsigned 64 bit arithmetic: */ | |
1115 | int istatus = count >= gt->cval; | |
1116 | uint64_t nexttick; | |
1117 | ||
1118 | gt->ctl = deposit32(gt->ctl, 2, 1, istatus); | |
1119 | qemu_set_irq(cpu->gt_timer_outputs[timeridx], | |
1120 | (istatus && !(gt->ctl & 2))); | |
1121 | if (istatus) { | |
1122 | /* Next transition is when count rolls back over to zero */ | |
1123 | nexttick = UINT64_MAX; | |
1124 | } else { | |
1125 | /* Next transition is when we hit cval */ | |
1126 | nexttick = gt->cval; | |
1127 | } | |
1128 | /* Note that the desired next expiry time might be beyond the | |
1129 | * signed-64-bit range of a QEMUTimer -- in this case we just | |
1130 | * set the timer for as far in the future as possible. When the | |
1131 | * timer expires we will reset the timer for any remaining period. | |
1132 | */ | |
1133 | if (nexttick > INT64_MAX / GTIMER_SCALE) { | |
1134 | nexttick = INT64_MAX / GTIMER_SCALE; | |
1135 | } | |
bc72ad67 | 1136 | timer_mod(cpu->gt_timer[timeridx], nexttick); |
55d284af PM |
1137 | } else { |
1138 | /* Timer disabled: ISTATUS and timer output always clear */ | |
1139 | gt->ctl &= ~4; | |
1140 | qemu_set_irq(cpu->gt_timer_outputs[timeridx], 0); | |
bc72ad67 | 1141 | timer_del(cpu->gt_timer[timeridx]); |
55d284af PM |
1142 | } |
1143 | } | |
1144 | ||
55d284af PM |
1145 | static void gt_cnt_reset(CPUARMState *env, const ARMCPRegInfo *ri) |
1146 | { | |
1147 | ARMCPU *cpu = arm_env_get_cpu(env); | |
1148 | int timeridx = ri->opc1 & 1; | |
1149 | ||
bc72ad67 | 1150 | timer_del(cpu->gt_timer[timeridx]); |
55d284af PM |
1151 | } |
1152 | ||
c4241c7d | 1153 | static uint64_t gt_cnt_read(CPUARMState *env, const ARMCPRegInfo *ri) |
55d284af | 1154 | { |
c4241c7d | 1155 | return gt_get_countervalue(env); |
55d284af PM |
1156 | } |
1157 | ||
c4241c7d PM |
1158 | static void gt_cval_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1159 | uint64_t value) | |
55d284af PM |
1160 | { |
1161 | int timeridx = ri->opc1 & 1; | |
1162 | ||
1163 | env->cp15.c14_timer[timeridx].cval = value; | |
1164 | gt_recalc_timer(arm_env_get_cpu(env), timeridx); | |
55d284af | 1165 | } |
c4241c7d PM |
1166 | |
1167 | static uint64_t gt_tval_read(CPUARMState *env, const ARMCPRegInfo *ri) | |
55d284af PM |
1168 | { |
1169 | int timeridx = ri->crm & 1; | |
1170 | ||
c4241c7d PM |
1171 | return (uint32_t)(env->cp15.c14_timer[timeridx].cval - |
1172 | gt_get_countervalue(env)); | |
55d284af PM |
1173 | } |
1174 | ||
c4241c7d PM |
1175 | static void gt_tval_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1176 | uint64_t value) | |
55d284af PM |
1177 | { |
1178 | int timeridx = ri->crm & 1; | |
1179 | ||
1180 | env->cp15.c14_timer[timeridx].cval = gt_get_countervalue(env) + | |
1181 | + sextract64(value, 0, 32); | |
1182 | gt_recalc_timer(arm_env_get_cpu(env), timeridx); | |
55d284af PM |
1183 | } |
1184 | ||
c4241c7d PM |
1185 | static void gt_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1186 | uint64_t value) | |
55d284af PM |
1187 | { |
1188 | ARMCPU *cpu = arm_env_get_cpu(env); | |
1189 | int timeridx = ri->crm & 1; | |
1190 | uint32_t oldval = env->cp15.c14_timer[timeridx].ctl; | |
1191 | ||
d3afacc7 | 1192 | env->cp15.c14_timer[timeridx].ctl = deposit64(oldval, 0, 2, value); |
55d284af PM |
1193 | if ((oldval ^ value) & 1) { |
1194 | /* Enable toggled */ | |
1195 | gt_recalc_timer(cpu, timeridx); | |
d3afacc7 | 1196 | } else if ((oldval ^ value) & 2) { |
55d284af PM |
1197 | /* IMASK toggled: don't need to recalculate, |
1198 | * just set the interrupt line based on ISTATUS | |
1199 | */ | |
1200 | qemu_set_irq(cpu->gt_timer_outputs[timeridx], | |
d3afacc7 | 1201 | (oldval & 4) && !(value & 2)); |
55d284af | 1202 | } |
55d284af PM |
1203 | } |
1204 | ||
1205 | void arm_gt_ptimer_cb(void *opaque) | |
1206 | { | |
1207 | ARMCPU *cpu = opaque; | |
1208 | ||
1209 | gt_recalc_timer(cpu, GTIMER_PHYS); | |
1210 | } | |
1211 | ||
1212 | void arm_gt_vtimer_cb(void *opaque) | |
1213 | { | |
1214 | ARMCPU *cpu = opaque; | |
1215 | ||
1216 | gt_recalc_timer(cpu, GTIMER_VIRT); | |
1217 | } | |
1218 | ||
1219 | static const ARMCPRegInfo generic_timer_cp_reginfo[] = { | |
1220 | /* Note that CNTFRQ is purely reads-as-written for the benefit | |
1221 | * of software; writing it doesn't actually change the timer frequency. | |
1222 | * Our reset value matches the fixed frequency we implement the timer at. | |
1223 | */ | |
1224 | { .name = "CNTFRQ", .cp = 15, .crn = 14, .crm = 0, .opc1 = 0, .opc2 = 0, | |
a7adc4b7 PM |
1225 | .type = ARM_CP_NO_MIGRATE, |
1226 | .access = PL1_RW | PL0_R, .accessfn = gt_cntfrq_access, | |
1227 | .fieldoffset = offsetoflow32(CPUARMState, cp15.c14_cntfrq), | |
1228 | .resetfn = arm_cp_reset_ignore, | |
1229 | }, | |
1230 | { .name = "CNTFRQ_EL0", .state = ARM_CP_STATE_AA64, | |
1231 | .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 0, | |
1232 | .access = PL1_RW | PL0_R, .accessfn = gt_cntfrq_access, | |
55d284af PM |
1233 | .fieldoffset = offsetof(CPUARMState, cp15.c14_cntfrq), |
1234 | .resetvalue = (1000 * 1000 * 1000) / GTIMER_SCALE, | |
55d284af PM |
1235 | }, |
1236 | /* overall control: mostly access permissions */ | |
a7adc4b7 PM |
1237 | { .name = "CNTKCTL", .state = ARM_CP_STATE_BOTH, |
1238 | .opc0 = 3, .opc1 = 0, .crn = 14, .crm = 1, .opc2 = 0, | |
55d284af PM |
1239 | .access = PL1_RW, |
1240 | .fieldoffset = offsetof(CPUARMState, cp15.c14_cntkctl), | |
1241 | .resetvalue = 0, | |
1242 | }, | |
1243 | /* per-timer control */ | |
1244 | { .name = "CNTP_CTL", .cp = 15, .crn = 14, .crm = 2, .opc1 = 0, .opc2 = 1, | |
a7adc4b7 PM |
1245 | .type = ARM_CP_IO | ARM_CP_NO_MIGRATE, .access = PL1_RW | PL0_R, |
1246 | .accessfn = gt_ptimer_access, | |
1247 | .fieldoffset = offsetoflow32(CPUARMState, | |
1248 | cp15.c14_timer[GTIMER_PHYS].ctl), | |
1249 | .resetfn = arm_cp_reset_ignore, | |
1250 | .writefn = gt_ctl_write, .raw_writefn = raw_write, | |
1251 | }, | |
1252 | { .name = "CNTP_CTL_EL0", .state = ARM_CP_STATE_AA64, | |
1253 | .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 2, .opc2 = 1, | |
55d284af | 1254 | .type = ARM_CP_IO, .access = PL1_RW | PL0_R, |
a7adc4b7 | 1255 | .accessfn = gt_ptimer_access, |
55d284af PM |
1256 | .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].ctl), |
1257 | .resetvalue = 0, | |
00108f2d | 1258 | .writefn = gt_ctl_write, .raw_writefn = raw_write, |
55d284af PM |
1259 | }, |
1260 | { .name = "CNTV_CTL", .cp = 15, .crn = 14, .crm = 3, .opc1 = 0, .opc2 = 1, | |
a7adc4b7 PM |
1261 | .type = ARM_CP_IO | ARM_CP_NO_MIGRATE, .access = PL1_RW | PL0_R, |
1262 | .accessfn = gt_vtimer_access, | |
1263 | .fieldoffset = offsetoflow32(CPUARMState, | |
1264 | cp15.c14_timer[GTIMER_VIRT].ctl), | |
1265 | .resetfn = arm_cp_reset_ignore, | |
1266 | .writefn = gt_ctl_write, .raw_writefn = raw_write, | |
1267 | }, | |
1268 | { .name = "CNTV_CTL_EL0", .state = ARM_CP_STATE_AA64, | |
1269 | .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 3, .opc2 = 1, | |
55d284af | 1270 | .type = ARM_CP_IO, .access = PL1_RW | PL0_R, |
a7adc4b7 | 1271 | .accessfn = gt_vtimer_access, |
55d284af PM |
1272 | .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].ctl), |
1273 | .resetvalue = 0, | |
00108f2d | 1274 | .writefn = gt_ctl_write, .raw_writefn = raw_write, |
55d284af PM |
1275 | }, |
1276 | /* TimerValue views: a 32 bit downcounting view of the underlying state */ | |
1277 | { .name = "CNTP_TVAL", .cp = 15, .crn = 14, .crm = 2, .opc1 = 0, .opc2 = 0, | |
1278 | .type = ARM_CP_NO_MIGRATE | ARM_CP_IO, .access = PL1_RW | PL0_R, | |
00108f2d | 1279 | .accessfn = gt_ptimer_access, |
55d284af PM |
1280 | .readfn = gt_tval_read, .writefn = gt_tval_write, |
1281 | }, | |
a7adc4b7 PM |
1282 | { .name = "CNTP_TVAL_EL0", .state = ARM_CP_STATE_AA64, |
1283 | .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 2, .opc2 = 0, | |
1284 | .type = ARM_CP_NO_MIGRATE | ARM_CP_IO, .access = PL1_RW | PL0_R, | |
1285 | .readfn = gt_tval_read, .writefn = gt_tval_write, | |
1286 | }, | |
55d284af PM |
1287 | { .name = "CNTV_TVAL", .cp = 15, .crn = 14, .crm = 3, .opc1 = 0, .opc2 = 0, |
1288 | .type = ARM_CP_NO_MIGRATE | ARM_CP_IO, .access = PL1_RW | PL0_R, | |
00108f2d | 1289 | .accessfn = gt_vtimer_access, |
55d284af PM |
1290 | .readfn = gt_tval_read, .writefn = gt_tval_write, |
1291 | }, | |
a7adc4b7 PM |
1292 | { .name = "CNTV_TVAL_EL0", .state = ARM_CP_STATE_AA64, |
1293 | .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 3, .opc2 = 0, | |
1294 | .type = ARM_CP_NO_MIGRATE | ARM_CP_IO, .access = PL1_RW | PL0_R, | |
1295 | .readfn = gt_tval_read, .writefn = gt_tval_write, | |
1296 | }, | |
55d284af PM |
1297 | /* The counter itself */ |
1298 | { .name = "CNTPCT", .cp = 15, .crm = 14, .opc1 = 0, | |
1299 | .access = PL0_R, .type = ARM_CP_64BIT | ARM_CP_NO_MIGRATE | ARM_CP_IO, | |
00108f2d | 1300 | .accessfn = gt_pct_access, |
a7adc4b7 PM |
1301 | .readfn = gt_cnt_read, .resetfn = arm_cp_reset_ignore, |
1302 | }, | |
1303 | { .name = "CNTPCT_EL0", .state = ARM_CP_STATE_AA64, | |
1304 | .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 1, | |
1305 | .access = PL0_R, .type = ARM_CP_NO_MIGRATE | ARM_CP_IO, | |
1306 | .accessfn = gt_pct_access, | |
55d284af PM |
1307 | .readfn = gt_cnt_read, .resetfn = gt_cnt_reset, |
1308 | }, | |
1309 | { .name = "CNTVCT", .cp = 15, .crm = 14, .opc1 = 1, | |
1310 | .access = PL0_R, .type = ARM_CP_64BIT | ARM_CP_NO_MIGRATE | ARM_CP_IO, | |
00108f2d | 1311 | .accessfn = gt_vct_access, |
a7adc4b7 PM |
1312 | .readfn = gt_cnt_read, .resetfn = arm_cp_reset_ignore, |
1313 | }, | |
1314 | { .name = "CNTVCT_EL0", .state = ARM_CP_STATE_AA64, | |
1315 | .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 2, | |
1316 | .access = PL0_R, .type = ARM_CP_NO_MIGRATE | ARM_CP_IO, | |
1317 | .accessfn = gt_vct_access, | |
55d284af PM |
1318 | .readfn = gt_cnt_read, .resetfn = gt_cnt_reset, |
1319 | }, | |
1320 | /* Comparison value, indicating when the timer goes off */ | |
1321 | { .name = "CNTP_CVAL", .cp = 15, .crm = 14, .opc1 = 2, | |
1322 | .access = PL1_RW | PL0_R, | |
a7adc4b7 | 1323 | .type = ARM_CP_64BIT | ARM_CP_IO | ARM_CP_NO_MIGRATE, |
55d284af | 1324 | .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].cval), |
a7adc4b7 PM |
1325 | .accessfn = gt_ptimer_access, .resetfn = arm_cp_reset_ignore, |
1326 | .writefn = gt_cval_write, .raw_writefn = raw_write, | |
1327 | }, | |
1328 | { .name = "CNTP_CVAL_EL0", .state = ARM_CP_STATE_AA64, | |
1329 | .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 2, .opc2 = 2, | |
1330 | .access = PL1_RW | PL0_R, | |
1331 | .type = ARM_CP_IO, | |
1332 | .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].cval), | |
1333 | .resetvalue = 0, .accessfn = gt_vtimer_access, | |
00108f2d | 1334 | .writefn = gt_cval_write, .raw_writefn = raw_write, |
55d284af PM |
1335 | }, |
1336 | { .name = "CNTV_CVAL", .cp = 15, .crm = 14, .opc1 = 3, | |
1337 | .access = PL1_RW | PL0_R, | |
a7adc4b7 | 1338 | .type = ARM_CP_64BIT | ARM_CP_IO | ARM_CP_NO_MIGRATE, |
55d284af | 1339 | .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].cval), |
a7adc4b7 PM |
1340 | .accessfn = gt_vtimer_access, .resetfn = arm_cp_reset_ignore, |
1341 | .writefn = gt_cval_write, .raw_writefn = raw_write, | |
1342 | }, | |
1343 | { .name = "CNTV_CVAL_EL0", .state = ARM_CP_STATE_AA64, | |
1344 | .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 3, .opc2 = 2, | |
1345 | .access = PL1_RW | PL0_R, | |
1346 | .type = ARM_CP_IO, | |
1347 | .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].cval), | |
1348 | .resetvalue = 0, .accessfn = gt_vtimer_access, | |
00108f2d | 1349 | .writefn = gt_cval_write, .raw_writefn = raw_write, |
55d284af PM |
1350 | }, |
1351 | REGINFO_SENTINEL | |
1352 | }; | |
1353 | ||
1354 | #else | |
1355 | /* In user-mode none of the generic timer registers are accessible, | |
bc72ad67 | 1356 | * and their implementation depends on QEMU_CLOCK_VIRTUAL and qdev gpio outputs, |
55d284af PM |
1357 | * so instead just don't register any of them. |
1358 | */ | |
6cc7a3ae | 1359 | static const ARMCPRegInfo generic_timer_cp_reginfo[] = { |
6cc7a3ae PM |
1360 | REGINFO_SENTINEL |
1361 | }; | |
1362 | ||
55d284af PM |
1363 | #endif |
1364 | ||
c4241c7d | 1365 | static void par_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) |
4a501606 | 1366 | { |
891a2fe7 | 1367 | if (arm_feature(env, ARM_FEATURE_LPAE)) { |
8d5c773e | 1368 | raw_write(env, ri, value); |
891a2fe7 | 1369 | } else if (arm_feature(env, ARM_FEATURE_V7)) { |
8d5c773e | 1370 | raw_write(env, ri, value & 0xfffff6ff); |
4a501606 | 1371 | } else { |
8d5c773e | 1372 | raw_write(env, ri, value & 0xfffff1ff); |
4a501606 | 1373 | } |
4a501606 PM |
1374 | } |
1375 | ||
1376 | #ifndef CONFIG_USER_ONLY | |
1377 | /* get_phys_addr() isn't present for user-mode-only targets */ | |
702a9357 | 1378 | |
92611c00 PM |
1379 | static CPAccessResult ats_access(CPUARMState *env, const ARMCPRegInfo *ri) |
1380 | { | |
1381 | if (ri->opc2 & 4) { | |
1382 | /* Other states are only available with TrustZone; in | |
1383 | * a non-TZ implementation these registers don't exist | |
1384 | * at all, which is an Uncategorized trap. This underdecoding | |
1385 | * is safe because the reginfo is NO_MIGRATE. | |
1386 | */ | |
1387 | return CP_ACCESS_TRAP_UNCATEGORIZED; | |
1388 | } | |
1389 | return CP_ACCESS_OK; | |
1390 | } | |
1391 | ||
c4241c7d | 1392 | static void ats_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) |
4a501606 | 1393 | { |
a8170e5e | 1394 | hwaddr phys_addr; |
4a501606 PM |
1395 | target_ulong page_size; |
1396 | int prot; | |
1397 | int ret, is_user = ri->opc2 & 2; | |
1398 | int access_type = ri->opc2 & 1; | |
1399 | ||
4a501606 PM |
1400 | ret = get_phys_addr(env, value, access_type, is_user, |
1401 | &phys_addr, &prot, &page_size); | |
702a9357 PM |
1402 | if (extended_addresses_enabled(env)) { |
1403 | /* ret is a DFSR/IFSR value for the long descriptor | |
1404 | * translation table format, but with WnR always clear. | |
1405 | * Convert it to a 64-bit PAR. | |
1406 | */ | |
1407 | uint64_t par64 = (1 << 11); /* LPAE bit always set */ | |
1408 | if (ret == 0) { | |
1409 | par64 |= phys_addr & ~0xfffULL; | |
1410 | /* We don't set the ATTR or SH fields in the PAR. */ | |
4a501606 | 1411 | } else { |
702a9357 PM |
1412 | par64 |= 1; /* F */ |
1413 | par64 |= (ret & 0x3f) << 1; /* FS */ | |
1414 | /* Note that S2WLK and FSTAGE are always zero, because we don't | |
1415 | * implement virtualization and therefore there can't be a stage 2 | |
1416 | * fault. | |
1417 | */ | |
4a501606 | 1418 | } |
19525524 | 1419 | env->cp15.par_el1 = par64; |
4a501606 | 1420 | } else { |
702a9357 PM |
1421 | /* ret is a DFSR/IFSR value for the short descriptor |
1422 | * translation table format (with WnR always clear). | |
1423 | * Convert it to a 32-bit PAR. | |
1424 | */ | |
1425 | if (ret == 0) { | |
1426 | /* We do not set any attribute bits in the PAR */ | |
1427 | if (page_size == (1 << 24) | |
1428 | && arm_feature(env, ARM_FEATURE_V7)) { | |
19525524 | 1429 | env->cp15.par_el1 = (phys_addr & 0xff000000) | 1 << 1; |
702a9357 | 1430 | } else { |
19525524 | 1431 | env->cp15.par_el1 = phys_addr & 0xfffff000; |
702a9357 PM |
1432 | } |
1433 | } else { | |
19525524 | 1434 | env->cp15.par_el1 = ((ret & (1 << 10)) >> 5) | |
775fda92 | 1435 | ((ret & (1 << 12)) >> 6) | |
702a9357 PM |
1436 | ((ret & 0xf) << 1) | 1; |
1437 | } | |
4a501606 | 1438 | } |
4a501606 PM |
1439 | } |
1440 | #endif | |
1441 | ||
1442 | static const ARMCPRegInfo vapa_cp_reginfo[] = { | |
1443 | { .name = "PAR", .cp = 15, .crn = 7, .crm = 4, .opc1 = 0, .opc2 = 0, | |
1444 | .access = PL1_RW, .resetvalue = 0, | |
19525524 | 1445 | .fieldoffset = offsetoflow32(CPUARMState, cp15.par_el1), |
4a501606 PM |
1446 | .writefn = par_write }, |
1447 | #ifndef CONFIG_USER_ONLY | |
1448 | { .name = "ATS", .cp = 15, .crn = 7, .crm = 8, .opc1 = 0, .opc2 = CP_ANY, | |
92611c00 PM |
1449 | .access = PL1_W, .accessfn = ats_access, |
1450 | .writefn = ats_write, .type = ARM_CP_NO_MIGRATE }, | |
4a501606 PM |
1451 | #endif |
1452 | REGINFO_SENTINEL | |
1453 | }; | |
1454 | ||
18032bec PM |
1455 | /* Return basic MPU access permission bits. */ |
1456 | static uint32_t simple_mpu_ap_bits(uint32_t val) | |
1457 | { | |
1458 | uint32_t ret; | |
1459 | uint32_t mask; | |
1460 | int i; | |
1461 | ret = 0; | |
1462 | mask = 3; | |
1463 | for (i = 0; i < 16; i += 2) { | |
1464 | ret |= (val >> i) & mask; | |
1465 | mask <<= 2; | |
1466 | } | |
1467 | return ret; | |
1468 | } | |
1469 | ||
1470 | /* Pad basic MPU access permission bits to extended format. */ | |
1471 | static uint32_t extended_mpu_ap_bits(uint32_t val) | |
1472 | { | |
1473 | uint32_t ret; | |
1474 | uint32_t mask; | |
1475 | int i; | |
1476 | ret = 0; | |
1477 | mask = 3; | |
1478 | for (i = 0; i < 16; i += 2) { | |
1479 | ret |= (val & mask) << i; | |
1480 | mask <<= 2; | |
1481 | } | |
1482 | return ret; | |
1483 | } | |
1484 | ||
c4241c7d PM |
1485 | static void pmsav5_data_ap_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1486 | uint64_t value) | |
18032bec | 1487 | { |
7e09797c | 1488 | env->cp15.pmsav5_data_ap = extended_mpu_ap_bits(value); |
18032bec PM |
1489 | } |
1490 | ||
c4241c7d | 1491 | static uint64_t pmsav5_data_ap_read(CPUARMState *env, const ARMCPRegInfo *ri) |
18032bec | 1492 | { |
7e09797c | 1493 | return simple_mpu_ap_bits(env->cp15.pmsav5_data_ap); |
18032bec PM |
1494 | } |
1495 | ||
c4241c7d PM |
1496 | static void pmsav5_insn_ap_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1497 | uint64_t value) | |
18032bec | 1498 | { |
7e09797c | 1499 | env->cp15.pmsav5_insn_ap = extended_mpu_ap_bits(value); |
18032bec PM |
1500 | } |
1501 | ||
c4241c7d | 1502 | static uint64_t pmsav5_insn_ap_read(CPUARMState *env, const ARMCPRegInfo *ri) |
18032bec | 1503 | { |
7e09797c | 1504 | return simple_mpu_ap_bits(env->cp15.pmsav5_insn_ap); |
18032bec PM |
1505 | } |
1506 | ||
1507 | static const ARMCPRegInfo pmsav5_cp_reginfo[] = { | |
1508 | { .name = "DATA_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 0, | |
d4e6df63 | 1509 | .access = PL1_RW, .type = ARM_CP_NO_MIGRATE, |
7e09797c PM |
1510 | .fieldoffset = offsetof(CPUARMState, cp15.pmsav5_data_ap), |
1511 | .resetvalue = 0, | |
18032bec PM |
1512 | .readfn = pmsav5_data_ap_read, .writefn = pmsav5_data_ap_write, }, |
1513 | { .name = "INSN_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 1, | |
d4e6df63 | 1514 | .access = PL1_RW, .type = ARM_CP_NO_MIGRATE, |
7e09797c PM |
1515 | .fieldoffset = offsetof(CPUARMState, cp15.pmsav5_insn_ap), |
1516 | .resetvalue = 0, | |
18032bec PM |
1517 | .readfn = pmsav5_insn_ap_read, .writefn = pmsav5_insn_ap_write, }, |
1518 | { .name = "DATA_EXT_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 2, | |
1519 | .access = PL1_RW, | |
7e09797c PM |
1520 | .fieldoffset = offsetof(CPUARMState, cp15.pmsav5_data_ap), |
1521 | .resetvalue = 0, }, | |
18032bec PM |
1522 | { .name = "INSN_EXT_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 3, |
1523 | .access = PL1_RW, | |
7e09797c PM |
1524 | .fieldoffset = offsetof(CPUARMState, cp15.pmsav5_insn_ap), |
1525 | .resetvalue = 0, }, | |
ecce5c3c PM |
1526 | { .name = "DCACHE_CFG", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 0, |
1527 | .access = PL1_RW, | |
1528 | .fieldoffset = offsetof(CPUARMState, cp15.c2_data), .resetvalue = 0, }, | |
1529 | { .name = "ICACHE_CFG", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 1, | |
1530 | .access = PL1_RW, | |
1531 | .fieldoffset = offsetof(CPUARMState, cp15.c2_insn), .resetvalue = 0, }, | |
06d76f31 | 1532 | /* Protection region base and size registers */ |
e508a92b PM |
1533 | { .name = "946_PRBS0", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, |
1534 | .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0, | |
1535 | .fieldoffset = offsetof(CPUARMState, cp15.c6_region[0]) }, | |
1536 | { .name = "946_PRBS1", .cp = 15, .crn = 6, .crm = 1, .opc1 = 0, | |
1537 | .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0, | |
1538 | .fieldoffset = offsetof(CPUARMState, cp15.c6_region[1]) }, | |
1539 | { .name = "946_PRBS2", .cp = 15, .crn = 6, .crm = 2, .opc1 = 0, | |
1540 | .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0, | |
1541 | .fieldoffset = offsetof(CPUARMState, cp15.c6_region[2]) }, | |
1542 | { .name = "946_PRBS3", .cp = 15, .crn = 6, .crm = 3, .opc1 = 0, | |
1543 | .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0, | |
1544 | .fieldoffset = offsetof(CPUARMState, cp15.c6_region[3]) }, | |
1545 | { .name = "946_PRBS4", .cp = 15, .crn = 6, .crm = 4, .opc1 = 0, | |
1546 | .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0, | |
1547 | .fieldoffset = offsetof(CPUARMState, cp15.c6_region[4]) }, | |
1548 | { .name = "946_PRBS5", .cp = 15, .crn = 6, .crm = 5, .opc1 = 0, | |
1549 | .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0, | |
1550 | .fieldoffset = offsetof(CPUARMState, cp15.c6_region[5]) }, | |
1551 | { .name = "946_PRBS6", .cp = 15, .crn = 6, .crm = 6, .opc1 = 0, | |
1552 | .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0, | |
1553 | .fieldoffset = offsetof(CPUARMState, cp15.c6_region[6]) }, | |
1554 | { .name = "946_PRBS7", .cp = 15, .crn = 6, .crm = 7, .opc1 = 0, | |
1555 | .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0, | |
1556 | .fieldoffset = offsetof(CPUARMState, cp15.c6_region[7]) }, | |
18032bec PM |
1557 | REGINFO_SENTINEL |
1558 | }; | |
1559 | ||
c4241c7d PM |
1560 | static void vmsa_ttbcr_raw_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1561 | uint64_t value) | |
ecce5c3c | 1562 | { |
2ebcebe2 PM |
1563 | int maskshift = extract32(value, 0, 3); |
1564 | ||
e389be16 FA |
1565 | if (!arm_feature(env, ARM_FEATURE_V8)) { |
1566 | if (arm_feature(env, ARM_FEATURE_LPAE) && (value & TTBCR_EAE)) { | |
1567 | /* Pre ARMv8 bits [21:19], [15:14] and [6:3] are UNK/SBZP when | |
1568 | * using Long-desciptor translation table format */ | |
1569 | value &= ~((7 << 19) | (3 << 14) | (0xf << 3)); | |
1570 | } else if (arm_feature(env, ARM_FEATURE_EL3)) { | |
1571 | /* In an implementation that includes the Security Extensions | |
1572 | * TTBCR has additional fields PD0 [4] and PD1 [5] for | |
1573 | * Short-descriptor translation table format. | |
1574 | */ | |
1575 | value &= TTBCR_PD1 | TTBCR_PD0 | TTBCR_N; | |
1576 | } else { | |
1577 | value &= TTBCR_N; | |
1578 | } | |
e42c4db3 | 1579 | } |
e389be16 | 1580 | |
e42c4db3 PM |
1581 | /* Note that we always calculate c2_mask and c2_base_mask, but |
1582 | * they are only used for short-descriptor tables (ie if EAE is 0); | |
1583 | * for long-descriptor tables the TTBCR fields are used differently | |
1584 | * and the c2_mask and c2_base_mask values are meaningless. | |
1585 | */ | |
8d5c773e | 1586 | raw_write(env, ri, value); |
2ebcebe2 PM |
1587 | env->cp15.c2_mask = ~(((uint32_t)0xffffffffu) >> maskshift); |
1588 | env->cp15.c2_base_mask = ~((uint32_t)0x3fffu >> maskshift); | |
ecce5c3c PM |
1589 | } |
1590 | ||
c4241c7d PM |
1591 | static void vmsa_ttbcr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1592 | uint64_t value) | |
d4e6df63 | 1593 | { |
00c8cb0a AF |
1594 | ARMCPU *cpu = arm_env_get_cpu(env); |
1595 | ||
d4e6df63 PM |
1596 | if (arm_feature(env, ARM_FEATURE_LPAE)) { |
1597 | /* With LPAE the TTBCR could result in a change of ASID | |
1598 | * via the TTBCR.A1 bit, so do a TLB flush. | |
1599 | */ | |
00c8cb0a | 1600 | tlb_flush(CPU(cpu), 1); |
d4e6df63 | 1601 | } |
c4241c7d | 1602 | vmsa_ttbcr_raw_write(env, ri, value); |
d4e6df63 PM |
1603 | } |
1604 | ||
ecce5c3c PM |
1605 | static void vmsa_ttbcr_reset(CPUARMState *env, const ARMCPRegInfo *ri) |
1606 | { | |
1607 | env->cp15.c2_base_mask = 0xffffc000u; | |
8d5c773e | 1608 | raw_write(env, ri, 0); |
ecce5c3c PM |
1609 | env->cp15.c2_mask = 0; |
1610 | } | |
1611 | ||
cb2e37df PM |
1612 | static void vmsa_tcr_el1_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1613 | uint64_t value) | |
1614 | { | |
00c8cb0a AF |
1615 | ARMCPU *cpu = arm_env_get_cpu(env); |
1616 | ||
cb2e37df | 1617 | /* For AArch64 the A1 bit could result in a change of ASID, so TLB flush. */ |
00c8cb0a | 1618 | tlb_flush(CPU(cpu), 1); |
8d5c773e | 1619 | raw_write(env, ri, value); |
cb2e37df PM |
1620 | } |
1621 | ||
327ed10f PM |
1622 | static void vmsa_ttbr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1623 | uint64_t value) | |
1624 | { | |
1625 | /* 64 bit accesses to the TTBRs can change the ASID and so we | |
1626 | * must flush the TLB. | |
1627 | */ | |
1628 | if (cpreg_field_is_64bit(ri)) { | |
00c8cb0a AF |
1629 | ARMCPU *cpu = arm_env_get_cpu(env); |
1630 | ||
1631 | tlb_flush(CPU(cpu), 1); | |
327ed10f PM |
1632 | } |
1633 | raw_write(env, ri, value); | |
1634 | } | |
1635 | ||
18032bec PM |
1636 | static const ARMCPRegInfo vmsa_cp_reginfo[] = { |
1637 | { .name = "DFSR", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 0, | |
6cd8a264 | 1638 | .access = PL1_RW, .type = ARM_CP_NO_MIGRATE, |
d81c519c | 1639 | .fieldoffset = offsetoflow32(CPUARMState, cp15.esr_el[1]), |
6cd8a264 | 1640 | .resetfn = arm_cp_reset_ignore, }, |
18032bec PM |
1641 | { .name = "IFSR", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 1, |
1642 | .access = PL1_RW, | |
6cd8a264 RH |
1643 | .fieldoffset = offsetof(CPUARMState, cp15.ifsr_el2), .resetvalue = 0, }, |
1644 | { .name = "ESR_EL1", .state = ARM_CP_STATE_AA64, | |
1645 | .opc0 = 3, .crn = 5, .crm = 2, .opc1 = 0, .opc2 = 0, | |
1646 | .access = PL1_RW, | |
d81c519c | 1647 | .fieldoffset = offsetof(CPUARMState, cp15.esr_el[1]), .resetvalue = 0, }, |
327ed10f PM |
1648 | { .name = "TTBR0_EL1", .state = ARM_CP_STATE_BOTH, |
1649 | .opc0 = 3, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 0, | |
1650 | .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.ttbr0_el1), | |
1651 | .writefn = vmsa_ttbr_write, .resetvalue = 0 }, | |
1652 | { .name = "TTBR1_EL1", .state = ARM_CP_STATE_BOTH, | |
1653 | .opc0 = 3, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 1, | |
1654 | .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.ttbr1_el1), | |
1655 | .writefn = vmsa_ttbr_write, .resetvalue = 0 }, | |
cb2e37df PM |
1656 | { .name = "TCR_EL1", .state = ARM_CP_STATE_AA64, |
1657 | .opc0 = 3, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 2, | |
1658 | .access = PL1_RW, .writefn = vmsa_tcr_el1_write, | |
1659 | .resetfn = vmsa_ttbcr_reset, .raw_writefn = raw_write, | |
ecce5c3c | 1660 | .fieldoffset = offsetof(CPUARMState, cp15.c2_control) }, |
cb2e37df PM |
1661 | { .name = "TTBCR", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 2, |
1662 | .access = PL1_RW, .type = ARM_CP_NO_MIGRATE, .writefn = vmsa_ttbcr_write, | |
1663 | .resetfn = arm_cp_reset_ignore, .raw_writefn = vmsa_ttbcr_raw_write, | |
1664 | .fieldoffset = offsetoflow32(CPUARMState, cp15.c2_control) }, | |
6cd8a264 RH |
1665 | /* 64-bit FAR; this entry also gives us the AArch32 DFAR */ |
1666 | { .name = "FAR_EL1", .state = ARM_CP_STATE_BOTH, | |
1667 | .opc0 = 3, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 0, | |
2f0180c5 | 1668 | .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.far_el[1]), |
06d76f31 | 1669 | .resetvalue = 0, }, |
18032bec PM |
1670 | REGINFO_SENTINEL |
1671 | }; | |
1672 | ||
c4241c7d PM |
1673 | static void omap_ticonfig_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1674 | uint64_t value) | |
1047b9d7 PM |
1675 | { |
1676 | env->cp15.c15_ticonfig = value & 0xe7; | |
1677 | /* The OS_TYPE bit in this register changes the reported CPUID! */ | |
1678 | env->cp15.c0_cpuid = (value & (1 << 5)) ? | |
1679 | ARM_CPUID_TI915T : ARM_CPUID_TI925T; | |
1047b9d7 PM |
1680 | } |
1681 | ||
c4241c7d PM |
1682 | static void omap_threadid_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1683 | uint64_t value) | |
1047b9d7 PM |
1684 | { |
1685 | env->cp15.c15_threadid = value & 0xffff; | |
1047b9d7 PM |
1686 | } |
1687 | ||
c4241c7d PM |
1688 | static void omap_wfi_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1689 | uint64_t value) | |
1047b9d7 PM |
1690 | { |
1691 | /* Wait-for-interrupt (deprecated) */ | |
c3affe56 | 1692 | cpu_interrupt(CPU(arm_env_get_cpu(env)), CPU_INTERRUPT_HALT); |
1047b9d7 PM |
1693 | } |
1694 | ||
c4241c7d PM |
1695 | static void omap_cachemaint_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1696 | uint64_t value) | |
c4804214 PM |
1697 | { |
1698 | /* On OMAP there are registers indicating the max/min index of dcache lines | |
1699 | * containing a dirty line; cache flush operations have to reset these. | |
1700 | */ | |
1701 | env->cp15.c15_i_max = 0x000; | |
1702 | env->cp15.c15_i_min = 0xff0; | |
c4804214 PM |
1703 | } |
1704 | ||
18032bec PM |
1705 | static const ARMCPRegInfo omap_cp_reginfo[] = { |
1706 | { .name = "DFSR", .cp = 15, .crn = 5, .crm = CP_ANY, | |
1707 | .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_OVERRIDE, | |
d81c519c | 1708 | .fieldoffset = offsetoflow32(CPUARMState, cp15.esr_el[1]), |
6cd8a264 | 1709 | .resetvalue = 0, }, |
1047b9d7 PM |
1710 | { .name = "", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0, |
1711 | .access = PL1_RW, .type = ARM_CP_NOP }, | |
1712 | { .name = "TICONFIG", .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0, | |
1713 | .access = PL1_RW, | |
1714 | .fieldoffset = offsetof(CPUARMState, cp15.c15_ticonfig), .resetvalue = 0, | |
1715 | .writefn = omap_ticonfig_write }, | |
1716 | { .name = "IMAX", .cp = 15, .crn = 15, .crm = 2, .opc1 = 0, .opc2 = 0, | |
1717 | .access = PL1_RW, | |
1718 | .fieldoffset = offsetof(CPUARMState, cp15.c15_i_max), .resetvalue = 0, }, | |
1719 | { .name = "IMIN", .cp = 15, .crn = 15, .crm = 3, .opc1 = 0, .opc2 = 0, | |
1720 | .access = PL1_RW, .resetvalue = 0xff0, | |
1721 | .fieldoffset = offsetof(CPUARMState, cp15.c15_i_min) }, | |
1722 | { .name = "THREADID", .cp = 15, .crn = 15, .crm = 4, .opc1 = 0, .opc2 = 0, | |
1723 | .access = PL1_RW, | |
1724 | .fieldoffset = offsetof(CPUARMState, cp15.c15_threadid), .resetvalue = 0, | |
1725 | .writefn = omap_threadid_write }, | |
1726 | { .name = "TI925T_STATUS", .cp = 15, .crn = 15, | |
1727 | .crm = 8, .opc1 = 0, .opc2 = 0, .access = PL1_RW, | |
d4e6df63 | 1728 | .type = ARM_CP_NO_MIGRATE, |
1047b9d7 PM |
1729 | .readfn = arm_cp_read_zero, .writefn = omap_wfi_write, }, |
1730 | /* TODO: Peripheral port remap register: | |
1731 | * On OMAP2 mcr p15, 0, rn, c15, c2, 4 sets up the interrupt controller | |
1732 | * base address at $rn & ~0xfff and map size of 0x200 << ($rn & 0xfff), | |
1733 | * when MMU is off. | |
1734 | */ | |
c4804214 | 1735 | { .name = "OMAP_CACHEMAINT", .cp = 15, .crn = 7, .crm = CP_ANY, |
d4e6df63 PM |
1736 | .opc1 = 0, .opc2 = CP_ANY, .access = PL1_W, |
1737 | .type = ARM_CP_OVERRIDE | ARM_CP_NO_MIGRATE, | |
c4804214 | 1738 | .writefn = omap_cachemaint_write }, |
34f90529 PM |
1739 | { .name = "C9", .cp = 15, .crn = 9, |
1740 | .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, | |
1741 | .type = ARM_CP_CONST | ARM_CP_OVERRIDE, .resetvalue = 0 }, | |
1047b9d7 PM |
1742 | REGINFO_SENTINEL |
1743 | }; | |
1744 | ||
c4241c7d PM |
1745 | static void xscale_cpar_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1746 | uint64_t value) | |
1047b9d7 | 1747 | { |
c0f4af17 | 1748 | env->cp15.c15_cpar = value & 0x3fff; |
1047b9d7 PM |
1749 | } |
1750 | ||
1751 | static const ARMCPRegInfo xscale_cp_reginfo[] = { | |
1752 | { .name = "XSCALE_CPAR", | |
1753 | .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0, .access = PL1_RW, | |
1754 | .fieldoffset = offsetof(CPUARMState, cp15.c15_cpar), .resetvalue = 0, | |
1755 | .writefn = xscale_cpar_write, }, | |
2771db27 PM |
1756 | { .name = "XSCALE_AUXCR", |
1757 | .cp = 15, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 1, .access = PL1_RW, | |
1758 | .fieldoffset = offsetof(CPUARMState, cp15.c1_xscaleauxcr), | |
1759 | .resetvalue = 0, }, | |
3b771579 PM |
1760 | /* XScale specific cache-lockdown: since we have no cache we NOP these |
1761 | * and hope the guest does not really rely on cache behaviour. | |
1762 | */ | |
1763 | { .name = "XSCALE_LOCK_ICACHE_LINE", | |
1764 | .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 0, | |
1765 | .access = PL1_W, .type = ARM_CP_NOP }, | |
1766 | { .name = "XSCALE_UNLOCK_ICACHE", | |
1767 | .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 1, | |
1768 | .access = PL1_W, .type = ARM_CP_NOP }, | |
1769 | { .name = "XSCALE_DCACHE_LOCK", | |
1770 | .cp = 15, .opc1 = 0, .crn = 9, .crm = 2, .opc2 = 0, | |
1771 | .access = PL1_RW, .type = ARM_CP_NOP }, | |
1772 | { .name = "XSCALE_UNLOCK_DCACHE", | |
1773 | .cp = 15, .opc1 = 0, .crn = 9, .crm = 2, .opc2 = 1, | |
1774 | .access = PL1_W, .type = ARM_CP_NOP }, | |
1047b9d7 PM |
1775 | REGINFO_SENTINEL |
1776 | }; | |
1777 | ||
1778 | static const ARMCPRegInfo dummy_c15_cp_reginfo[] = { | |
1779 | /* RAZ/WI the whole crn=15 space, when we don't have a more specific | |
1780 | * implementation of this implementation-defined space. | |
1781 | * Ideally this should eventually disappear in favour of actually | |
1782 | * implementing the correct behaviour for all cores. | |
1783 | */ | |
1784 | { .name = "C15_IMPDEF", .cp = 15, .crn = 15, | |
1785 | .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY, | |
3671cd87 PC |
1786 | .access = PL1_RW, |
1787 | .type = ARM_CP_CONST | ARM_CP_NO_MIGRATE | ARM_CP_OVERRIDE, | |
d4e6df63 | 1788 | .resetvalue = 0 }, |
18032bec PM |
1789 | REGINFO_SENTINEL |
1790 | }; | |
1791 | ||
c4804214 PM |
1792 | static const ARMCPRegInfo cache_dirty_status_cp_reginfo[] = { |
1793 | /* Cache status: RAZ because we have no cache so it's always clean */ | |
1794 | { .name = "CDSR", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 6, | |
d4e6df63 PM |
1795 | .access = PL1_R, .type = ARM_CP_CONST | ARM_CP_NO_MIGRATE, |
1796 | .resetvalue = 0 }, | |
c4804214 PM |
1797 | REGINFO_SENTINEL |
1798 | }; | |
1799 | ||
1800 | static const ARMCPRegInfo cache_block_ops_cp_reginfo[] = { | |
1801 | /* We never have a a block transfer operation in progress */ | |
1802 | { .name = "BXSR", .cp = 15, .crn = 7, .crm = 12, .opc1 = 0, .opc2 = 4, | |
d4e6df63 PM |
1803 | .access = PL0_R, .type = ARM_CP_CONST | ARM_CP_NO_MIGRATE, |
1804 | .resetvalue = 0 }, | |
30b05bba PM |
1805 | /* The cache ops themselves: these all NOP for QEMU */ |
1806 | { .name = "IICR", .cp = 15, .crm = 5, .opc1 = 0, | |
1807 | .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT }, | |
1808 | { .name = "IDCR", .cp = 15, .crm = 6, .opc1 = 0, | |
1809 | .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT }, | |
1810 | { .name = "CDCR", .cp = 15, .crm = 12, .opc1 = 0, | |
1811 | .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT }, | |
1812 | { .name = "PIR", .cp = 15, .crm = 12, .opc1 = 1, | |
1813 | .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT }, | |
1814 | { .name = "PDR", .cp = 15, .crm = 12, .opc1 = 2, | |
1815 | .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT }, | |
1816 | { .name = "CIDCR", .cp = 15, .crm = 14, .opc1 = 0, | |
1817 | .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT }, | |
c4804214 PM |
1818 | REGINFO_SENTINEL |
1819 | }; | |
1820 | ||
1821 | static const ARMCPRegInfo cache_test_clean_cp_reginfo[] = { | |
1822 | /* The cache test-and-clean instructions always return (1 << 30) | |
1823 | * to indicate that there are no dirty cache lines. | |
1824 | */ | |
1825 | { .name = "TC_DCACHE", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 3, | |
d4e6df63 PM |
1826 | .access = PL0_R, .type = ARM_CP_CONST | ARM_CP_NO_MIGRATE, |
1827 | .resetvalue = (1 << 30) }, | |
c4804214 | 1828 | { .name = "TCI_DCACHE", .cp = 15, .crn = 7, .crm = 14, .opc1 = 0, .opc2 = 3, |
d4e6df63 PM |
1829 | .access = PL0_R, .type = ARM_CP_CONST | ARM_CP_NO_MIGRATE, |
1830 | .resetvalue = (1 << 30) }, | |
c4804214 PM |
1831 | REGINFO_SENTINEL |
1832 | }; | |
1833 | ||
34f90529 PM |
1834 | static const ARMCPRegInfo strongarm_cp_reginfo[] = { |
1835 | /* Ignore ReadBuffer accesses */ | |
1836 | { .name = "C9_READBUFFER", .cp = 15, .crn = 9, | |
1837 | .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY, | |
d4e6df63 PM |
1838 | .access = PL1_RW, .resetvalue = 0, |
1839 | .type = ARM_CP_CONST | ARM_CP_OVERRIDE | ARM_CP_NO_MIGRATE }, | |
34f90529 PM |
1840 | REGINFO_SENTINEL |
1841 | }; | |
1842 | ||
c4241c7d | 1843 | static uint64_t mpidr_read(CPUARMState *env, const ARMCPRegInfo *ri) |
81bdde9d | 1844 | { |
55e5c285 AF |
1845 | CPUState *cs = CPU(arm_env_get_cpu(env)); |
1846 | uint32_t mpidr = cs->cpu_index; | |
4b7fff2f PM |
1847 | /* We don't support setting cluster ID ([8..11]) (known as Aff1 |
1848 | * in later ARM ARM versions), or any of the higher affinity level fields, | |
81bdde9d PM |
1849 | * so these bits always RAZ. |
1850 | */ | |
1851 | if (arm_feature(env, ARM_FEATURE_V7MP)) { | |
78dbbbe4 | 1852 | mpidr |= (1U << 31); |
81bdde9d PM |
1853 | /* Cores which are uniprocessor (non-coherent) |
1854 | * but still implement the MP extensions set | |
1855 | * bit 30. (For instance, A9UP.) However we do | |
1856 | * not currently model any of those cores. | |
1857 | */ | |
1858 | } | |
c4241c7d | 1859 | return mpidr; |
81bdde9d PM |
1860 | } |
1861 | ||
1862 | static const ARMCPRegInfo mpidr_cp_reginfo[] = { | |
4b7fff2f PM |
1863 | { .name = "MPIDR", .state = ARM_CP_STATE_BOTH, |
1864 | .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 5, | |
d4e6df63 | 1865 | .access = PL1_R, .readfn = mpidr_read, .type = ARM_CP_NO_MIGRATE }, |
81bdde9d PM |
1866 | REGINFO_SENTINEL |
1867 | }; | |
1868 | ||
7ac681cf | 1869 | static const ARMCPRegInfo lpae_cp_reginfo[] = { |
b90372ad | 1870 | /* NOP AMAIR0/1: the override is because these clash with the rather |
7ac681cf PM |
1871 | * broadly specified TLB_LOCKDOWN entry in the generic cp_reginfo. |
1872 | */ | |
b0fe2427 PM |
1873 | { .name = "AMAIR0", .state = ARM_CP_STATE_BOTH, |
1874 | .opc0 = 3, .crn = 10, .crm = 3, .opc1 = 0, .opc2 = 0, | |
7ac681cf PM |
1875 | .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_OVERRIDE, |
1876 | .resetvalue = 0 }, | |
b0fe2427 | 1877 | /* AMAIR1 is mapped to AMAIR_EL1[63:32] */ |
7ac681cf PM |
1878 | { .name = "AMAIR1", .cp = 15, .crn = 10, .crm = 3, .opc1 = 0, .opc2 = 1, |
1879 | .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_OVERRIDE, | |
1880 | .resetvalue = 0 }, | |
891a2fe7 PM |
1881 | { .name = "PAR", .cp = 15, .crm = 7, .opc1 = 0, |
1882 | .access = PL1_RW, .type = ARM_CP_64BIT, | |
19525524 | 1883 | .fieldoffset = offsetof(CPUARMState, cp15.par_el1), .resetvalue = 0 }, |
891a2fe7 | 1884 | { .name = "TTBR0", .cp = 15, .crm = 2, .opc1 = 0, |
327ed10f PM |
1885 | .access = PL1_RW, .type = ARM_CP_64BIT | ARM_CP_NO_MIGRATE, |
1886 | .fieldoffset = offsetof(CPUARMState, cp15.ttbr0_el1), | |
1887 | .writefn = vmsa_ttbr_write, .resetfn = arm_cp_reset_ignore }, | |
891a2fe7 | 1888 | { .name = "TTBR1", .cp = 15, .crm = 2, .opc1 = 1, |
327ed10f PM |
1889 | .access = PL1_RW, .type = ARM_CP_64BIT | ARM_CP_NO_MIGRATE, |
1890 | .fieldoffset = offsetof(CPUARMState, cp15.ttbr1_el1), | |
1891 | .writefn = vmsa_ttbr_write, .resetfn = arm_cp_reset_ignore }, | |
7ac681cf PM |
1892 | REGINFO_SENTINEL |
1893 | }; | |
1894 | ||
c4241c7d | 1895 | static uint64_t aa64_fpcr_read(CPUARMState *env, const ARMCPRegInfo *ri) |
b0d2b7d0 | 1896 | { |
c4241c7d | 1897 | return vfp_get_fpcr(env); |
b0d2b7d0 PM |
1898 | } |
1899 | ||
c4241c7d PM |
1900 | static void aa64_fpcr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1901 | uint64_t value) | |
b0d2b7d0 PM |
1902 | { |
1903 | vfp_set_fpcr(env, value); | |
b0d2b7d0 PM |
1904 | } |
1905 | ||
c4241c7d | 1906 | static uint64_t aa64_fpsr_read(CPUARMState *env, const ARMCPRegInfo *ri) |
b0d2b7d0 | 1907 | { |
c4241c7d | 1908 | return vfp_get_fpsr(env); |
b0d2b7d0 PM |
1909 | } |
1910 | ||
c4241c7d PM |
1911 | static void aa64_fpsr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1912 | uint64_t value) | |
b0d2b7d0 PM |
1913 | { |
1914 | vfp_set_fpsr(env, value); | |
b0d2b7d0 PM |
1915 | } |
1916 | ||
c2b820fe PM |
1917 | static CPAccessResult aa64_daif_access(CPUARMState *env, const ARMCPRegInfo *ri) |
1918 | { | |
137feaa9 | 1919 | if (arm_current_el(env) == 0 && !(env->cp15.sctlr_el[1] & SCTLR_UMA)) { |
c2b820fe PM |
1920 | return CP_ACCESS_TRAP; |
1921 | } | |
1922 | return CP_ACCESS_OK; | |
1923 | } | |
1924 | ||
1925 | static void aa64_daif_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
1926 | uint64_t value) | |
1927 | { | |
1928 | env->daif = value & PSTATE_DAIF; | |
1929 | } | |
1930 | ||
8af35c37 PM |
1931 | static CPAccessResult aa64_cacheop_access(CPUARMState *env, |
1932 | const ARMCPRegInfo *ri) | |
1933 | { | |
1934 | /* Cache invalidate/clean: NOP, but EL0 must UNDEF unless | |
1935 | * SCTLR_EL1.UCI is set. | |
1936 | */ | |
137feaa9 | 1937 | if (arm_current_el(env) == 0 && !(env->cp15.sctlr_el[1] & SCTLR_UCI)) { |
8af35c37 PM |
1938 | return CP_ACCESS_TRAP; |
1939 | } | |
1940 | return CP_ACCESS_OK; | |
1941 | } | |
1942 | ||
dbb1fb27 AB |
1943 | /* See: D4.7.2 TLB maintenance requirements and the TLB maintenance instructions |
1944 | * Page D4-1736 (DDI0487A.b) | |
1945 | */ | |
1946 | ||
168aa23b PM |
1947 | static void tlbi_aa64_va_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1948 | uint64_t value) | |
1949 | { | |
1950 | /* Invalidate by VA (AArch64 version) */ | |
31b030d4 | 1951 | ARMCPU *cpu = arm_env_get_cpu(env); |
dbb1fb27 AB |
1952 | uint64_t pageaddr = sextract64(value << 12, 0, 56); |
1953 | ||
31b030d4 | 1954 | tlb_flush_page(CPU(cpu), pageaddr); |
168aa23b PM |
1955 | } |
1956 | ||
1957 | static void tlbi_aa64_vaa_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
1958 | uint64_t value) | |
1959 | { | |
1960 | /* Invalidate by VA, all ASIDs (AArch64 version) */ | |
31b030d4 | 1961 | ARMCPU *cpu = arm_env_get_cpu(env); |
dbb1fb27 AB |
1962 | uint64_t pageaddr = sextract64(value << 12, 0, 56); |
1963 | ||
31b030d4 | 1964 | tlb_flush_page(CPU(cpu), pageaddr); |
168aa23b PM |
1965 | } |
1966 | ||
1967 | static void tlbi_aa64_asid_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
1968 | uint64_t value) | |
1969 | { | |
1970 | /* Invalidate by ASID (AArch64 version) */ | |
00c8cb0a | 1971 | ARMCPU *cpu = arm_env_get_cpu(env); |
168aa23b | 1972 | int asid = extract64(value, 48, 16); |
00c8cb0a | 1973 | tlb_flush(CPU(cpu), asid == 0); |
168aa23b PM |
1974 | } |
1975 | ||
fa439fc5 PM |
1976 | static void tlbi_aa64_va_is_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1977 | uint64_t value) | |
1978 | { | |
1979 | CPUState *other_cs; | |
1980 | uint64_t pageaddr = sextract64(value << 12, 0, 56); | |
1981 | ||
1982 | CPU_FOREACH(other_cs) { | |
1983 | tlb_flush_page(other_cs, pageaddr); | |
1984 | } | |
1985 | } | |
1986 | ||
1987 | static void tlbi_aa64_vaa_is_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
1988 | uint64_t value) | |
1989 | { | |
1990 | CPUState *other_cs; | |
1991 | uint64_t pageaddr = sextract64(value << 12, 0, 56); | |
1992 | ||
1993 | CPU_FOREACH(other_cs) { | |
1994 | tlb_flush_page(other_cs, pageaddr); | |
1995 | } | |
1996 | } | |
1997 | ||
1998 | static void tlbi_aa64_asid_is_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
1999 | uint64_t value) | |
2000 | { | |
2001 | CPUState *other_cs; | |
2002 | int asid = extract64(value, 48, 16); | |
2003 | ||
2004 | CPU_FOREACH(other_cs) { | |
2005 | tlb_flush(other_cs, asid == 0); | |
2006 | } | |
2007 | } | |
2008 | ||
aca3f40b PM |
2009 | static CPAccessResult aa64_zva_access(CPUARMState *env, const ARMCPRegInfo *ri) |
2010 | { | |
2011 | /* We don't implement EL2, so the only control on DC ZVA is the | |
2012 | * bit in the SCTLR which can prohibit access for EL0. | |
2013 | */ | |
137feaa9 | 2014 | if (arm_current_el(env) == 0 && !(env->cp15.sctlr_el[1] & SCTLR_DZE)) { |
aca3f40b PM |
2015 | return CP_ACCESS_TRAP; |
2016 | } | |
2017 | return CP_ACCESS_OK; | |
2018 | } | |
2019 | ||
2020 | static uint64_t aa64_dczid_read(CPUARMState *env, const ARMCPRegInfo *ri) | |
2021 | { | |
2022 | ARMCPU *cpu = arm_env_get_cpu(env); | |
2023 | int dzp_bit = 1 << 4; | |
2024 | ||
2025 | /* DZP indicates whether DC ZVA access is allowed */ | |
14e5f106 | 2026 | if (aa64_zva_access(env, NULL) == CP_ACCESS_OK) { |
aca3f40b PM |
2027 | dzp_bit = 0; |
2028 | } | |
2029 | return cpu->dcz_blocksize | dzp_bit; | |
2030 | } | |
2031 | ||
f502cfc2 PM |
2032 | static CPAccessResult sp_el0_access(CPUARMState *env, const ARMCPRegInfo *ri) |
2033 | { | |
cdcf1405 | 2034 | if (!(env->pstate & PSTATE_SP)) { |
f502cfc2 PM |
2035 | /* Access to SP_EL0 is undefined if it's being used as |
2036 | * the stack pointer. | |
2037 | */ | |
2038 | return CP_ACCESS_TRAP_UNCATEGORIZED; | |
2039 | } | |
2040 | return CP_ACCESS_OK; | |
2041 | } | |
2042 | ||
2043 | static uint64_t spsel_read(CPUARMState *env, const ARMCPRegInfo *ri) | |
2044 | { | |
2045 | return env->pstate & PSTATE_SP; | |
2046 | } | |
2047 | ||
2048 | static void spsel_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t val) | |
2049 | { | |
2050 | update_spsel(env, val); | |
2051 | } | |
2052 | ||
137feaa9 FA |
2053 | static void sctlr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
2054 | uint64_t value) | |
2055 | { | |
2056 | ARMCPU *cpu = arm_env_get_cpu(env); | |
2057 | ||
2058 | if (raw_read(env, ri) == value) { | |
2059 | /* Skip the TLB flush if nothing actually changed; Linux likes | |
2060 | * to do a lot of pointless SCTLR writes. | |
2061 | */ | |
2062 | return; | |
2063 | } | |
2064 | ||
2065 | raw_write(env, ri, value); | |
2066 | /* ??? Lots of these bits are not implemented. */ | |
2067 | /* This may enable/disable the MMU, so do a TLB flush. */ | |
2068 | tlb_flush(CPU(cpu), 1); | |
2069 | } | |
2070 | ||
b0d2b7d0 PM |
2071 | static const ARMCPRegInfo v8_cp_reginfo[] = { |
2072 | /* Minimal set of EL0-visible registers. This will need to be expanded | |
2073 | * significantly for system emulation of AArch64 CPUs. | |
2074 | */ | |
2075 | { .name = "NZCV", .state = ARM_CP_STATE_AA64, | |
2076 | .opc0 = 3, .opc1 = 3, .opc2 = 0, .crn = 4, .crm = 2, | |
2077 | .access = PL0_RW, .type = ARM_CP_NZCV }, | |
c2b820fe PM |
2078 | { .name = "DAIF", .state = ARM_CP_STATE_AA64, |
2079 | .opc0 = 3, .opc1 = 3, .opc2 = 1, .crn = 4, .crm = 2, | |
2080 | .type = ARM_CP_NO_MIGRATE, | |
2081 | .access = PL0_RW, .accessfn = aa64_daif_access, | |
2082 | .fieldoffset = offsetof(CPUARMState, daif), | |
2083 | .writefn = aa64_daif_write, .resetfn = arm_cp_reset_ignore }, | |
b0d2b7d0 PM |
2084 | { .name = "FPCR", .state = ARM_CP_STATE_AA64, |
2085 | .opc0 = 3, .opc1 = 3, .opc2 = 0, .crn = 4, .crm = 4, | |
2086 | .access = PL0_RW, .readfn = aa64_fpcr_read, .writefn = aa64_fpcr_write }, | |
2087 | { .name = "FPSR", .state = ARM_CP_STATE_AA64, | |
2088 | .opc0 = 3, .opc1 = 3, .opc2 = 1, .crn = 4, .crm = 4, | |
2089 | .access = PL0_RW, .readfn = aa64_fpsr_read, .writefn = aa64_fpsr_write }, | |
b0d2b7d0 PM |
2090 | { .name = "DCZID_EL0", .state = ARM_CP_STATE_AA64, |
2091 | .opc0 = 3, .opc1 = 3, .opc2 = 7, .crn = 0, .crm = 0, | |
aca3f40b PM |
2092 | .access = PL0_R, .type = ARM_CP_NO_MIGRATE, |
2093 | .readfn = aa64_dczid_read }, | |
2094 | { .name = "DC_ZVA", .state = ARM_CP_STATE_AA64, | |
2095 | .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 4, .opc2 = 1, | |
2096 | .access = PL0_W, .type = ARM_CP_DC_ZVA, | |
2097 | #ifndef CONFIG_USER_ONLY | |
2098 | /* Avoid overhead of an access check that always passes in user-mode */ | |
2099 | .accessfn = aa64_zva_access, | |
2100 | #endif | |
2101 | }, | |
0eef9d98 PM |
2102 | { .name = "CURRENTEL", .state = ARM_CP_STATE_AA64, |
2103 | .opc0 = 3, .opc1 = 0, .opc2 = 2, .crn = 4, .crm = 2, | |
2104 | .access = PL1_R, .type = ARM_CP_CURRENTEL }, | |
8af35c37 PM |
2105 | /* Cache ops: all NOPs since we don't emulate caches */ |
2106 | { .name = "IC_IALLUIS", .state = ARM_CP_STATE_AA64, | |
2107 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 1, .opc2 = 0, | |
2108 | .access = PL1_W, .type = ARM_CP_NOP }, | |
2109 | { .name = "IC_IALLU", .state = ARM_CP_STATE_AA64, | |
2110 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 0, | |
2111 | .access = PL1_W, .type = ARM_CP_NOP }, | |
2112 | { .name = "IC_IVAU", .state = ARM_CP_STATE_AA64, | |
2113 | .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 5, .opc2 = 1, | |
2114 | .access = PL0_W, .type = ARM_CP_NOP, | |
2115 | .accessfn = aa64_cacheop_access }, | |
2116 | { .name = "DC_IVAC", .state = ARM_CP_STATE_AA64, | |
2117 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 1, | |
2118 | .access = PL1_W, .type = ARM_CP_NOP }, | |
2119 | { .name = "DC_ISW", .state = ARM_CP_STATE_AA64, | |
2120 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 2, | |
2121 | .access = PL1_W, .type = ARM_CP_NOP }, | |
2122 | { .name = "DC_CVAC", .state = ARM_CP_STATE_AA64, | |
2123 | .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 10, .opc2 = 1, | |
2124 | .access = PL0_W, .type = ARM_CP_NOP, | |
2125 | .accessfn = aa64_cacheop_access }, | |
2126 | { .name = "DC_CSW", .state = ARM_CP_STATE_AA64, | |
2127 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 2, | |
2128 | .access = PL1_W, .type = ARM_CP_NOP }, | |
2129 | { .name = "DC_CVAU", .state = ARM_CP_STATE_AA64, | |
2130 | .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 11, .opc2 = 1, | |
2131 | .access = PL0_W, .type = ARM_CP_NOP, | |
2132 | .accessfn = aa64_cacheop_access }, | |
2133 | { .name = "DC_CIVAC", .state = ARM_CP_STATE_AA64, | |
2134 | .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 14, .opc2 = 1, | |
2135 | .access = PL0_W, .type = ARM_CP_NOP, | |
2136 | .accessfn = aa64_cacheop_access }, | |
2137 | { .name = "DC_CISW", .state = ARM_CP_STATE_AA64, | |
2138 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 2, | |
2139 | .access = PL1_W, .type = ARM_CP_NOP }, | |
168aa23b PM |
2140 | /* TLBI operations */ |
2141 | { .name = "TLBI_VMALLE1IS", .state = ARM_CP_STATE_AA64, | |
6ab9f499 | 2142 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 0, |
168aa23b | 2143 | .access = PL1_W, .type = ARM_CP_NO_MIGRATE, |
fa439fc5 | 2144 | .writefn = tlbiall_is_write }, |
168aa23b | 2145 | { .name = "TLBI_VAE1IS", .state = ARM_CP_STATE_AA64, |
6ab9f499 | 2146 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 1, |
168aa23b | 2147 | .access = PL1_W, .type = ARM_CP_NO_MIGRATE, |
fa439fc5 | 2148 | .writefn = tlbi_aa64_va_is_write }, |
168aa23b | 2149 | { .name = "TLBI_ASIDE1IS", .state = ARM_CP_STATE_AA64, |
6ab9f499 | 2150 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 2, |
168aa23b | 2151 | .access = PL1_W, .type = ARM_CP_NO_MIGRATE, |
fa439fc5 | 2152 | .writefn = tlbi_aa64_asid_is_write }, |
168aa23b | 2153 | { .name = "TLBI_VAAE1IS", .state = ARM_CP_STATE_AA64, |
6ab9f499 | 2154 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 3, |
168aa23b | 2155 | .access = PL1_W, .type = ARM_CP_NO_MIGRATE, |
fa439fc5 | 2156 | .writefn = tlbi_aa64_vaa_is_write }, |
168aa23b | 2157 | { .name = "TLBI_VALE1IS", .state = ARM_CP_STATE_AA64, |
6ab9f499 | 2158 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 5, |
168aa23b | 2159 | .access = PL1_W, .type = ARM_CP_NO_MIGRATE, |
fa439fc5 | 2160 | .writefn = tlbi_aa64_va_is_write }, |
168aa23b | 2161 | { .name = "TLBI_VAALE1IS", .state = ARM_CP_STATE_AA64, |
6ab9f499 | 2162 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 7, |
168aa23b | 2163 | .access = PL1_W, .type = ARM_CP_NO_MIGRATE, |
fa439fc5 | 2164 | .writefn = tlbi_aa64_vaa_is_write }, |
168aa23b | 2165 | { .name = "TLBI_VMALLE1", .state = ARM_CP_STATE_AA64, |
6ab9f499 | 2166 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 0, |
168aa23b PM |
2167 | .access = PL1_W, .type = ARM_CP_NO_MIGRATE, |
2168 | .writefn = tlbiall_write }, | |
2169 | { .name = "TLBI_VAE1", .state = ARM_CP_STATE_AA64, | |
6ab9f499 | 2170 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 1, |
168aa23b PM |
2171 | .access = PL1_W, .type = ARM_CP_NO_MIGRATE, |
2172 | .writefn = tlbi_aa64_va_write }, | |
2173 | { .name = "TLBI_ASIDE1", .state = ARM_CP_STATE_AA64, | |
6ab9f499 | 2174 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 2, |
168aa23b PM |
2175 | .access = PL1_W, .type = ARM_CP_NO_MIGRATE, |
2176 | .writefn = tlbi_aa64_asid_write }, | |
2177 | { .name = "TLBI_VAAE1", .state = ARM_CP_STATE_AA64, | |
6ab9f499 | 2178 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 3, |
168aa23b PM |
2179 | .access = PL1_W, .type = ARM_CP_NO_MIGRATE, |
2180 | .writefn = tlbi_aa64_vaa_write }, | |
2181 | { .name = "TLBI_VALE1", .state = ARM_CP_STATE_AA64, | |
6ab9f499 | 2182 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 5, |
168aa23b PM |
2183 | .access = PL1_W, .type = ARM_CP_NO_MIGRATE, |
2184 | .writefn = tlbi_aa64_va_write }, | |
2185 | { .name = "TLBI_VAALE1", .state = ARM_CP_STATE_AA64, | |
6ab9f499 | 2186 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 7, |
168aa23b PM |
2187 | .access = PL1_W, .type = ARM_CP_NO_MIGRATE, |
2188 | .writefn = tlbi_aa64_vaa_write }, | |
19525524 PM |
2189 | #ifndef CONFIG_USER_ONLY |
2190 | /* 64 bit address translation operations */ | |
2191 | { .name = "AT_S1E1R", .state = ARM_CP_STATE_AA64, | |
2192 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 0, | |
2193 | .access = PL1_W, .type = ARM_CP_NO_MIGRATE, .writefn = ats_write }, | |
2194 | { .name = "AT_S1E1W", .state = ARM_CP_STATE_AA64, | |
2195 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 1, | |
2196 | .access = PL1_W, .type = ARM_CP_NO_MIGRATE, .writefn = ats_write }, | |
2197 | { .name = "AT_S1E0R", .state = ARM_CP_STATE_AA64, | |
2198 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 2, | |
2199 | .access = PL1_W, .type = ARM_CP_NO_MIGRATE, .writefn = ats_write }, | |
2200 | { .name = "AT_S1E0W", .state = ARM_CP_STATE_AA64, | |
2201 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 3, | |
2202 | .access = PL1_W, .type = ARM_CP_NO_MIGRATE, .writefn = ats_write }, | |
2203 | #endif | |
995939a6 | 2204 | /* TLB invalidate last level of translation table walk */ |
9449fdf6 | 2205 | { .name = "TLBIMVALIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 5, |
fa439fc5 | 2206 | .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn = tlbimva_is_write }, |
9449fdf6 | 2207 | { .name = "TLBIMVAALIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 7, |
fa439fc5 PM |
2208 | .type = ARM_CP_NO_MIGRATE, .access = PL1_W, |
2209 | .writefn = tlbimvaa_is_write }, | |
9449fdf6 PM |
2210 | { .name = "TLBIMVAL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 5, |
2211 | .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn = tlbimva_write }, | |
2212 | { .name = "TLBIMVAAL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 7, | |
2213 | .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn = tlbimvaa_write }, | |
2214 | /* 32 bit cache operations */ | |
2215 | { .name = "ICIALLUIS", .cp = 15, .opc1 = 0, .crn = 7, .crm = 1, .opc2 = 0, | |
2216 | .type = ARM_CP_NOP, .access = PL1_W }, | |
2217 | { .name = "BPIALLUIS", .cp = 15, .opc1 = 0, .crn = 7, .crm = 1, .opc2 = 6, | |
2218 | .type = ARM_CP_NOP, .access = PL1_W }, | |
2219 | { .name = "ICIALLU", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 0, | |
2220 | .type = ARM_CP_NOP, .access = PL1_W }, | |
2221 | { .name = "ICIMVAU", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 1, | |
2222 | .type = ARM_CP_NOP, .access = PL1_W }, | |
2223 | { .name = "BPIALL", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 6, | |
2224 | .type = ARM_CP_NOP, .access = PL1_W }, | |
2225 | { .name = "BPIMVA", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 7, | |
2226 | .type = ARM_CP_NOP, .access = PL1_W }, | |
2227 | { .name = "DCIMVAC", .cp = 15, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 1, | |
2228 | .type = ARM_CP_NOP, .access = PL1_W }, | |
2229 | { .name = "DCISW", .cp = 15, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 2, | |
2230 | .type = ARM_CP_NOP, .access = PL1_W }, | |
2231 | { .name = "DCCMVAC", .cp = 15, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 1, | |
2232 | .type = ARM_CP_NOP, .access = PL1_W }, | |
2233 | { .name = "DCCSW", .cp = 15, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 2, | |
2234 | .type = ARM_CP_NOP, .access = PL1_W }, | |
2235 | { .name = "DCCMVAU", .cp = 15, .opc1 = 0, .crn = 7, .crm = 11, .opc2 = 1, | |
2236 | .type = ARM_CP_NOP, .access = PL1_W }, | |
2237 | { .name = "DCCIMVAC", .cp = 15, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 1, | |
2238 | .type = ARM_CP_NOP, .access = PL1_W }, | |
2239 | { .name = "DCCISW", .cp = 15, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 2, | |
2240 | .type = ARM_CP_NOP, .access = PL1_W }, | |
2241 | /* MMU Domain access control / MPU write buffer control */ | |
2242 | { .name = "DACR", .cp = 15, | |
2243 | .opc1 = 0, .crn = 3, .crm = 0, .opc2 = 0, | |
2244 | .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c3), | |
2245 | .resetvalue = 0, .writefn = dacr_write, .raw_writefn = raw_write, }, | |
a0618a19 PM |
2246 | { .name = "ELR_EL1", .state = ARM_CP_STATE_AA64, |
2247 | .type = ARM_CP_NO_MIGRATE, | |
2248 | .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 0, .opc2 = 1, | |
6947f059 EI |
2249 | .access = PL1_RW, |
2250 | .fieldoffset = offsetof(CPUARMState, elr_el[1]) }, | |
a65f1de9 PM |
2251 | { .name = "SPSR_EL1", .state = ARM_CP_STATE_AA64, |
2252 | .type = ARM_CP_NO_MIGRATE, | |
2253 | .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 0, .opc2 = 0, | |
2254 | .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, banked_spsr[0]) }, | |
f502cfc2 PM |
2255 | /* We rely on the access checks not allowing the guest to write to the |
2256 | * state field when SPSel indicates that it's being used as the stack | |
2257 | * pointer. | |
2258 | */ | |
2259 | { .name = "SP_EL0", .state = ARM_CP_STATE_AA64, | |
2260 | .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 1, .opc2 = 0, | |
2261 | .access = PL1_RW, .accessfn = sp_el0_access, | |
2262 | .type = ARM_CP_NO_MIGRATE, | |
2263 | .fieldoffset = offsetof(CPUARMState, sp_el[0]) }, | |
2264 | { .name = "SPSel", .state = ARM_CP_STATE_AA64, | |
2265 | .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 2, .opc2 = 0, | |
2266 | .type = ARM_CP_NO_MIGRATE, | |
2267 | .access = PL1_RW, .readfn = spsel_read, .writefn = spsel_write }, | |
b0d2b7d0 PM |
2268 | REGINFO_SENTINEL |
2269 | }; | |
2270 | ||
d42e3c26 EI |
2271 | /* Used to describe the behaviour of EL2 regs when EL2 does not exist. */ |
2272 | static const ARMCPRegInfo v8_el3_no_el2_cp_reginfo[] = { | |
2273 | { .name = "VBAR_EL2", .state = ARM_CP_STATE_AA64, | |
2274 | .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 0, .opc2 = 0, | |
2275 | .access = PL2_RW, | |
2276 | .readfn = arm_cp_read_zero, .writefn = arm_cp_write_ignore }, | |
f149e3e8 EI |
2277 | { .name = "HCR_EL2", .state = ARM_CP_STATE_AA64, |
2278 | .type = ARM_CP_NO_MIGRATE, | |
2279 | .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 0, | |
2280 | .access = PL2_RW, | |
2281 | .readfn = arm_cp_read_zero, .writefn = arm_cp_write_ignore }, | |
d42e3c26 EI |
2282 | REGINFO_SENTINEL |
2283 | }; | |
2284 | ||
f149e3e8 EI |
2285 | static void hcr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) |
2286 | { | |
2287 | ARMCPU *cpu = arm_env_get_cpu(env); | |
2288 | uint64_t valid_mask = HCR_MASK; | |
2289 | ||
2290 | if (arm_feature(env, ARM_FEATURE_EL3)) { | |
2291 | valid_mask &= ~HCR_HCD; | |
2292 | } else { | |
2293 | valid_mask &= ~HCR_TSC; | |
2294 | } | |
2295 | ||
2296 | /* Clear RES0 bits. */ | |
2297 | value &= valid_mask; | |
2298 | ||
2299 | /* These bits change the MMU setup: | |
2300 | * HCR_VM enables stage 2 translation | |
2301 | * HCR_PTW forbids certain page-table setups | |
2302 | * HCR_DC Disables stage1 and enables stage2 translation | |
2303 | */ | |
2304 | if ((raw_read(env, ri) ^ value) & (HCR_VM | HCR_PTW | HCR_DC)) { | |
2305 | tlb_flush(CPU(cpu), 1); | |
2306 | } | |
2307 | raw_write(env, ri, value); | |
2308 | } | |
2309 | ||
3b685ba7 | 2310 | static const ARMCPRegInfo v8_el2_cp_reginfo[] = { |
f149e3e8 EI |
2311 | { .name = "HCR_EL2", .state = ARM_CP_STATE_AA64, |
2312 | .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 0, | |
2313 | .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.hcr_el2), | |
2314 | .writefn = hcr_write }, | |
3b685ba7 EI |
2315 | { .name = "ELR_EL2", .state = ARM_CP_STATE_AA64, |
2316 | .type = ARM_CP_NO_MIGRATE, | |
2317 | .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 0, .opc2 = 1, | |
2318 | .access = PL2_RW, | |
2319 | .fieldoffset = offsetof(CPUARMState, elr_el[2]) }, | |
f2c30f42 EI |
2320 | { .name = "ESR_EL2", .state = ARM_CP_STATE_AA64, |
2321 | .type = ARM_CP_NO_MIGRATE, | |
2322 | .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 2, .opc2 = 0, | |
2323 | .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.esr_el[2]) }, | |
63b60551 EI |
2324 | { .name = "FAR_EL2", .state = ARM_CP_STATE_AA64, |
2325 | .opc0 = 3, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 0, | |
2326 | .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.far_el[2]) }, | |
3b685ba7 EI |
2327 | { .name = "SPSR_EL2", .state = ARM_CP_STATE_AA64, |
2328 | .type = ARM_CP_NO_MIGRATE, | |
2329 | .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 0, .opc2 = 0, | |
2330 | .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, banked_spsr[6]) }, | |
d42e3c26 EI |
2331 | { .name = "VBAR_EL2", .state = ARM_CP_STATE_AA64, |
2332 | .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 0, .opc2 = 0, | |
2333 | .access = PL2_RW, .writefn = vbar_write, | |
2334 | .fieldoffset = offsetof(CPUARMState, cp15.vbar_el[2]), | |
2335 | .resetvalue = 0 }, | |
3b685ba7 EI |
2336 | REGINFO_SENTINEL |
2337 | }; | |
2338 | ||
81547d66 | 2339 | static const ARMCPRegInfo v8_el3_cp_reginfo[] = { |
137feaa9 FA |
2340 | { .name = "SCTLR_EL3", .state = ARM_CP_STATE_AA64, |
2341 | .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 0, .opc2 = 0, | |
2342 | .access = PL3_RW, .raw_writefn = raw_write, .writefn = sctlr_write, | |
2343 | .fieldoffset = offsetof(CPUARMState, cp15.sctlr_el[3]) }, | |
81547d66 EI |
2344 | { .name = "ELR_EL3", .state = ARM_CP_STATE_AA64, |
2345 | .type = ARM_CP_NO_MIGRATE, | |
2346 | .opc0 = 3, .opc1 = 6, .crn = 4, .crm = 0, .opc2 = 1, | |
2347 | .access = PL3_RW, | |
2348 | .fieldoffset = offsetof(CPUARMState, elr_el[3]) }, | |
f2c30f42 EI |
2349 | { .name = "ESR_EL3", .state = ARM_CP_STATE_AA64, |
2350 | .type = ARM_CP_NO_MIGRATE, | |
2351 | .opc0 = 3, .opc1 = 6, .crn = 5, .crm = 2, .opc2 = 0, | |
2352 | .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.esr_el[3]) }, | |
63b60551 EI |
2353 | { .name = "FAR_EL3", .state = ARM_CP_STATE_AA64, |
2354 | .opc0 = 3, .opc1 = 6, .crn = 6, .crm = 0, .opc2 = 0, | |
2355 | .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.far_el[3]) }, | |
81547d66 EI |
2356 | { .name = "SPSR_EL3", .state = ARM_CP_STATE_AA64, |
2357 | .type = ARM_CP_NO_MIGRATE, | |
2358 | .opc0 = 3, .opc1 = 6, .crn = 4, .crm = 0, .opc2 = 0, | |
2359 | .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, banked_spsr[7]) }, | |
a1ba125c EI |
2360 | { .name = "VBAR_EL3", .state = ARM_CP_STATE_AA64, |
2361 | .opc0 = 3, .opc1 = 6, .crn = 12, .crm = 0, .opc2 = 0, | |
2362 | .access = PL3_RW, .writefn = vbar_write, | |
2363 | .fieldoffset = offsetof(CPUARMState, cp15.vbar_el[3]), | |
2364 | .resetvalue = 0 }, | |
0f1a3b24 FA |
2365 | REGINFO_SENTINEL |
2366 | }; | |
2367 | ||
2368 | static const ARMCPRegInfo el3_cp_reginfo[] = { | |
64e0e2de | 2369 | { .name = "SCR_EL3", .state = ARM_CP_STATE_AA64, |
64e0e2de EI |
2370 | .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 1, .opc2 = 0, |
2371 | .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.scr_el3), | |
0f1a3b24 FA |
2372 | .resetvalue = 0, .writefn = scr_write }, |
2373 | { .name = "SCR", .type = ARM_CP_NO_MIGRATE, | |
2374 | .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 0, | |
2375 | .access = PL3_RW, .fieldoffset = offsetoflow32(CPUARMState, cp15.scr_el3), | |
2376 | .resetfn = arm_cp_reset_ignore, .writefn = scr_write }, | |
144634ae GB |
2377 | { .name = "SDER32_EL3", .state = ARM_CP_STATE_AA64, |
2378 | .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 1, .opc2 = 1, | |
2379 | .access = PL3_RW, .resetvalue = 0, | |
2380 | .fieldoffset = offsetof(CPUARMState, cp15.sder) }, | |
2381 | { .name = "SDER", | |
2382 | .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 1, | |
2383 | .access = PL3_RW, .resetvalue = 0, | |
2384 | .fieldoffset = offsetoflow32(CPUARMState, cp15.sder) }, | |
77022576 FA |
2385 | /* TODO: Implement NSACR trapping of secure EL1 accesses to EL3 */ |
2386 | { .name = "NSACR", .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 2, | |
2387 | .access = PL3_W | PL1_R, .resetvalue = 0, | |
2388 | .fieldoffset = offsetof(CPUARMState, cp15.nsacr) }, | |
e89e51a1 FA |
2389 | { .name = "MVBAR", .cp = 15, .opc1 = 0, .crn = 12, .crm = 0, .opc2 = 1, |
2390 | .access = PL3_RW, .writefn = vbar_write, .resetvalue = 0, | |
2391 | .fieldoffset = offsetof(CPUARMState, cp15.mvbar) }, | |
81547d66 EI |
2392 | REGINFO_SENTINEL |
2393 | }; | |
2394 | ||
7da845b0 PM |
2395 | static CPAccessResult ctr_el0_access(CPUARMState *env, const ARMCPRegInfo *ri) |
2396 | { | |
2397 | /* Only accessible in EL0 if SCTLR.UCT is set (and only in AArch64, | |
2398 | * but the AArch32 CTR has its own reginfo struct) | |
2399 | */ | |
137feaa9 | 2400 | if (arm_current_el(env) == 0 && !(env->cp15.sctlr_el[1] & SCTLR_UCT)) { |
7da845b0 PM |
2401 | return CP_ACCESS_TRAP; |
2402 | } | |
2403 | return CP_ACCESS_OK; | |
2404 | } | |
2405 | ||
50300698 | 2406 | static const ARMCPRegInfo debug_cp_reginfo[] = { |
50300698 | 2407 | /* DBGDRAR, DBGDSAR: always RAZ since we don't implement memory mapped |
10aae104 PM |
2408 | * debug components. The AArch64 version of DBGDRAR is named MDRAR_EL1; |
2409 | * unlike DBGDRAR it is never accessible from EL0. | |
2410 | * DBGDSAR is deprecated and must RAZ from v8 anyway, so it has no AArch64 | |
2411 | * accessor. | |
50300698 PM |
2412 | */ |
2413 | { .name = "DBGDRAR", .cp = 14, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 0, | |
2414 | .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
10aae104 PM |
2415 | { .name = "MDRAR_EL1", .state = ARM_CP_STATE_AA64, |
2416 | .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 0, | |
2417 | .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
50300698 PM |
2418 | { .name = "DBGDSAR", .cp = 14, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 0, |
2419 | .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
17a9eb53 | 2420 | /* Monitor debug system control register; the 32-bit alias is DBGDSCRext. */ |
10aae104 PM |
2421 | { .name = "MDSCR_EL1", .state = ARM_CP_STATE_BOTH, |
2422 | .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 2, | |
0e5e8935 PM |
2423 | .access = PL1_RW, |
2424 | .fieldoffset = offsetof(CPUARMState, cp15.mdscr_el1), | |
2425 | .resetvalue = 0 }, | |
5e8b12ff PM |
2426 | /* MDCCSR_EL0, aka DBGDSCRint. This is a read-only mirror of MDSCR_EL1. |
2427 | * We don't implement the configurable EL0 access. | |
2428 | */ | |
2429 | { .name = "MDCCSR_EL0", .state = ARM_CP_STATE_BOTH, | |
2430 | .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 0, | |
2431 | .type = ARM_CP_NO_MIGRATE, | |
2432 | .access = PL1_R, | |
2433 | .fieldoffset = offsetof(CPUARMState, cp15.mdscr_el1), | |
2434 | .resetfn = arm_cp_reset_ignore }, | |
50300698 | 2435 | /* We define a dummy WI OSLAR_EL1, because Linux writes to it. */ |
10aae104 PM |
2436 | { .name = "OSLAR_EL1", .state = ARM_CP_STATE_BOTH, |
2437 | .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 4, | |
50300698 | 2438 | .access = PL1_W, .type = ARM_CP_NOP }, |
5e8b12ff PM |
2439 | /* Dummy OSDLR_EL1: 32-bit Linux will read this */ |
2440 | { .name = "OSDLR_EL1", .state = ARM_CP_STATE_BOTH, | |
2441 | .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 3, .opc2 = 4, | |
2442 | .access = PL1_RW, .type = ARM_CP_NOP }, | |
2443 | /* Dummy DBGVCR: Linux wants to clear this on startup, but we don't | |
2444 | * implement vector catch debug events yet. | |
2445 | */ | |
2446 | { .name = "DBGVCR", | |
2447 | .cp = 14, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 0, | |
2448 | .access = PL1_RW, .type = ARM_CP_NOP }, | |
50300698 PM |
2449 | REGINFO_SENTINEL |
2450 | }; | |
2451 | ||
2452 | static const ARMCPRegInfo debug_lpae_cp_reginfo[] = { | |
2453 | /* 64 bit access versions of the (dummy) debug registers */ | |
2454 | { .name = "DBGDRAR", .cp = 14, .crm = 1, .opc1 = 0, | |
2455 | .access = PL0_R, .type = ARM_CP_CONST|ARM_CP_64BIT, .resetvalue = 0 }, | |
2456 | { .name = "DBGDSAR", .cp = 14, .crm = 2, .opc1 = 0, | |
2457 | .access = PL0_R, .type = ARM_CP_CONST|ARM_CP_64BIT, .resetvalue = 0 }, | |
2458 | REGINFO_SENTINEL | |
2459 | }; | |
2460 | ||
9ee98ce8 PM |
2461 | void hw_watchpoint_update(ARMCPU *cpu, int n) |
2462 | { | |
2463 | CPUARMState *env = &cpu->env; | |
2464 | vaddr len = 0; | |
2465 | vaddr wvr = env->cp15.dbgwvr[n]; | |
2466 | uint64_t wcr = env->cp15.dbgwcr[n]; | |
2467 | int mask; | |
2468 | int flags = BP_CPU | BP_STOP_BEFORE_ACCESS; | |
2469 | ||
2470 | if (env->cpu_watchpoint[n]) { | |
2471 | cpu_watchpoint_remove_by_ref(CPU(cpu), env->cpu_watchpoint[n]); | |
2472 | env->cpu_watchpoint[n] = NULL; | |
2473 | } | |
2474 | ||
2475 | if (!extract64(wcr, 0, 1)) { | |
2476 | /* E bit clear : watchpoint disabled */ | |
2477 | return; | |
2478 | } | |
2479 | ||
2480 | switch (extract64(wcr, 3, 2)) { | |
2481 | case 0: | |
2482 | /* LSC 00 is reserved and must behave as if the wp is disabled */ | |
2483 | return; | |
2484 | case 1: | |
2485 | flags |= BP_MEM_READ; | |
2486 | break; | |
2487 | case 2: | |
2488 | flags |= BP_MEM_WRITE; | |
2489 | break; | |
2490 | case 3: | |
2491 | flags |= BP_MEM_ACCESS; | |
2492 | break; | |
2493 | } | |
2494 | ||
2495 | /* Attempts to use both MASK and BAS fields simultaneously are | |
2496 | * CONSTRAINED UNPREDICTABLE; we opt to ignore BAS in this case, | |
2497 | * thus generating a watchpoint for every byte in the masked region. | |
2498 | */ | |
2499 | mask = extract64(wcr, 24, 4); | |
2500 | if (mask == 1 || mask == 2) { | |
2501 | /* Reserved values of MASK; we must act as if the mask value was | |
2502 | * some non-reserved value, or as if the watchpoint were disabled. | |
2503 | * We choose the latter. | |
2504 | */ | |
2505 | return; | |
2506 | } else if (mask) { | |
2507 | /* Watchpoint covers an aligned area up to 2GB in size */ | |
2508 | len = 1ULL << mask; | |
2509 | /* If masked bits in WVR are not zero it's CONSTRAINED UNPREDICTABLE | |
2510 | * whether the watchpoint fires when the unmasked bits match; we opt | |
2511 | * to generate the exceptions. | |
2512 | */ | |
2513 | wvr &= ~(len - 1); | |
2514 | } else { | |
2515 | /* Watchpoint covers bytes defined by the byte address select bits */ | |
2516 | int bas = extract64(wcr, 5, 8); | |
2517 | int basstart; | |
2518 | ||
2519 | if (bas == 0) { | |
2520 | /* This must act as if the watchpoint is disabled */ | |
2521 | return; | |
2522 | } | |
2523 | ||
2524 | if (extract64(wvr, 2, 1)) { | |
2525 | /* Deprecated case of an only 4-aligned address. BAS[7:4] are | |
2526 | * ignored, and BAS[3:0] define which bytes to watch. | |
2527 | */ | |
2528 | bas &= 0xf; | |
2529 | } | |
2530 | /* The BAS bits are supposed to be programmed to indicate a contiguous | |
2531 | * range of bytes. Otherwise it is CONSTRAINED UNPREDICTABLE whether | |
2532 | * we fire for each byte in the word/doubleword addressed by the WVR. | |
2533 | * We choose to ignore any non-zero bits after the first range of 1s. | |
2534 | */ | |
2535 | basstart = ctz32(bas); | |
2536 | len = cto32(bas >> basstart); | |
2537 | wvr += basstart; | |
2538 | } | |
2539 | ||
2540 | cpu_watchpoint_insert(CPU(cpu), wvr, len, flags, | |
2541 | &env->cpu_watchpoint[n]); | |
2542 | } | |
2543 | ||
2544 | void hw_watchpoint_update_all(ARMCPU *cpu) | |
2545 | { | |
2546 | int i; | |
2547 | CPUARMState *env = &cpu->env; | |
2548 | ||
2549 | /* Completely clear out existing QEMU watchpoints and our array, to | |
2550 | * avoid possible stale entries following migration load. | |
2551 | */ | |
2552 | cpu_watchpoint_remove_all(CPU(cpu), BP_CPU); | |
2553 | memset(env->cpu_watchpoint, 0, sizeof(env->cpu_watchpoint)); | |
2554 | ||
2555 | for (i = 0; i < ARRAY_SIZE(cpu->env.cpu_watchpoint); i++) { | |
2556 | hw_watchpoint_update(cpu, i); | |
2557 | } | |
2558 | } | |
2559 | ||
2560 | static void dbgwvr_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
2561 | uint64_t value) | |
2562 | { | |
2563 | ARMCPU *cpu = arm_env_get_cpu(env); | |
2564 | int i = ri->crm; | |
2565 | ||
2566 | /* Bits [63:49] are hardwired to the value of bit [48]; that is, the | |
2567 | * register reads and behaves as if values written are sign extended. | |
2568 | * Bits [1:0] are RES0. | |
2569 | */ | |
2570 | value = sextract64(value, 0, 49) & ~3ULL; | |
2571 | ||
2572 | raw_write(env, ri, value); | |
2573 | hw_watchpoint_update(cpu, i); | |
2574 | } | |
2575 | ||
2576 | static void dbgwcr_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
2577 | uint64_t value) | |
2578 | { | |
2579 | ARMCPU *cpu = arm_env_get_cpu(env); | |
2580 | int i = ri->crm; | |
2581 | ||
2582 | raw_write(env, ri, value); | |
2583 | hw_watchpoint_update(cpu, i); | |
2584 | } | |
2585 | ||
46747d15 PM |
2586 | void hw_breakpoint_update(ARMCPU *cpu, int n) |
2587 | { | |
2588 | CPUARMState *env = &cpu->env; | |
2589 | uint64_t bvr = env->cp15.dbgbvr[n]; | |
2590 | uint64_t bcr = env->cp15.dbgbcr[n]; | |
2591 | vaddr addr; | |
2592 | int bt; | |
2593 | int flags = BP_CPU; | |
2594 | ||
2595 | if (env->cpu_breakpoint[n]) { | |
2596 | cpu_breakpoint_remove_by_ref(CPU(cpu), env->cpu_breakpoint[n]); | |
2597 | env->cpu_breakpoint[n] = NULL; | |
2598 | } | |
2599 | ||
2600 | if (!extract64(bcr, 0, 1)) { | |
2601 | /* E bit clear : watchpoint disabled */ | |
2602 | return; | |
2603 | } | |
2604 | ||
2605 | bt = extract64(bcr, 20, 4); | |
2606 | ||
2607 | switch (bt) { | |
2608 | case 4: /* unlinked address mismatch (reserved if AArch64) */ | |
2609 | case 5: /* linked address mismatch (reserved if AArch64) */ | |
2610 | qemu_log_mask(LOG_UNIMP, | |
2611 | "arm: address mismatch breakpoint types not implemented"); | |
2612 | return; | |
2613 | case 0: /* unlinked address match */ | |
2614 | case 1: /* linked address match */ | |
2615 | { | |
2616 | /* Bits [63:49] are hardwired to the value of bit [48]; that is, | |
2617 | * we behave as if the register was sign extended. Bits [1:0] are | |
2618 | * RES0. The BAS field is used to allow setting breakpoints on 16 | |
2619 | * bit wide instructions; it is CONSTRAINED UNPREDICTABLE whether | |
2620 | * a bp will fire if the addresses covered by the bp and the addresses | |
2621 | * covered by the insn overlap but the insn doesn't start at the | |
2622 | * start of the bp address range. We choose to require the insn and | |
2623 | * the bp to have the same address. The constraints on writing to | |
2624 | * BAS enforced in dbgbcr_write mean we have only four cases: | |
2625 | * 0b0000 => no breakpoint | |
2626 | * 0b0011 => breakpoint on addr | |
2627 | * 0b1100 => breakpoint on addr + 2 | |
2628 | * 0b1111 => breakpoint on addr | |
2629 | * See also figure D2-3 in the v8 ARM ARM (DDI0487A.c). | |
2630 | */ | |
2631 | int bas = extract64(bcr, 5, 4); | |
2632 | addr = sextract64(bvr, 0, 49) & ~3ULL; | |
2633 | if (bas == 0) { | |
2634 | return; | |
2635 | } | |
2636 | if (bas == 0xc) { | |
2637 | addr += 2; | |
2638 | } | |
2639 | break; | |
2640 | } | |
2641 | case 2: /* unlinked context ID match */ | |
2642 | case 8: /* unlinked VMID match (reserved if no EL2) */ | |
2643 | case 10: /* unlinked context ID and VMID match (reserved if no EL2) */ | |
2644 | qemu_log_mask(LOG_UNIMP, | |
2645 | "arm: unlinked context breakpoint types not implemented"); | |
2646 | return; | |
2647 | case 9: /* linked VMID match (reserved if no EL2) */ | |
2648 | case 11: /* linked context ID and VMID match (reserved if no EL2) */ | |
2649 | case 3: /* linked context ID match */ | |
2650 | default: | |
2651 | /* We must generate no events for Linked context matches (unless | |
2652 | * they are linked to by some other bp/wp, which is handled in | |
2653 | * updates for the linking bp/wp). We choose to also generate no events | |
2654 | * for reserved values. | |
2655 | */ | |
2656 | return; | |
2657 | } | |
2658 | ||
2659 | cpu_breakpoint_insert(CPU(cpu), addr, flags, &env->cpu_breakpoint[n]); | |
2660 | } | |
2661 | ||
2662 | void hw_breakpoint_update_all(ARMCPU *cpu) | |
2663 | { | |
2664 | int i; | |
2665 | CPUARMState *env = &cpu->env; | |
2666 | ||
2667 | /* Completely clear out existing QEMU breakpoints and our array, to | |
2668 | * avoid possible stale entries following migration load. | |
2669 | */ | |
2670 | cpu_breakpoint_remove_all(CPU(cpu), BP_CPU); | |
2671 | memset(env->cpu_breakpoint, 0, sizeof(env->cpu_breakpoint)); | |
2672 | ||
2673 | for (i = 0; i < ARRAY_SIZE(cpu->env.cpu_breakpoint); i++) { | |
2674 | hw_breakpoint_update(cpu, i); | |
2675 | } | |
2676 | } | |
2677 | ||
2678 | static void dbgbvr_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
2679 | uint64_t value) | |
2680 | { | |
2681 | ARMCPU *cpu = arm_env_get_cpu(env); | |
2682 | int i = ri->crm; | |
2683 | ||
2684 | raw_write(env, ri, value); | |
2685 | hw_breakpoint_update(cpu, i); | |
2686 | } | |
2687 | ||
2688 | static void dbgbcr_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
2689 | uint64_t value) | |
2690 | { | |
2691 | ARMCPU *cpu = arm_env_get_cpu(env); | |
2692 | int i = ri->crm; | |
2693 | ||
2694 | /* BAS[3] is a read-only copy of BAS[2], and BAS[1] a read-only | |
2695 | * copy of BAS[0]. | |
2696 | */ | |
2697 | value = deposit64(value, 6, 1, extract64(value, 5, 1)); | |
2698 | value = deposit64(value, 8, 1, extract64(value, 7, 1)); | |
2699 | ||
2700 | raw_write(env, ri, value); | |
2701 | hw_breakpoint_update(cpu, i); | |
2702 | } | |
2703 | ||
50300698 | 2704 | static void define_debug_regs(ARMCPU *cpu) |
0b45451e | 2705 | { |
50300698 PM |
2706 | /* Define v7 and v8 architectural debug registers. |
2707 | * These are just dummy implementations for now. | |
0b45451e PM |
2708 | */ |
2709 | int i; | |
3ff6fc91 | 2710 | int wrps, brps, ctx_cmps; |
48eb3ae6 PM |
2711 | ARMCPRegInfo dbgdidr = { |
2712 | .name = "DBGDIDR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 0, | |
2713 | .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = cpu->dbgdidr, | |
2714 | }; | |
2715 | ||
3ff6fc91 | 2716 | /* Note that all these register fields hold "number of Xs minus 1". */ |
48eb3ae6 PM |
2717 | brps = extract32(cpu->dbgdidr, 24, 4); |
2718 | wrps = extract32(cpu->dbgdidr, 28, 4); | |
3ff6fc91 PM |
2719 | ctx_cmps = extract32(cpu->dbgdidr, 20, 4); |
2720 | ||
2721 | assert(ctx_cmps <= brps); | |
48eb3ae6 PM |
2722 | |
2723 | /* The DBGDIDR and ID_AA64DFR0_EL1 define various properties | |
2724 | * of the debug registers such as number of breakpoints; | |
2725 | * check that if they both exist then they agree. | |
2726 | */ | |
2727 | if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { | |
2728 | assert(extract32(cpu->id_aa64dfr0, 12, 4) == brps); | |
2729 | assert(extract32(cpu->id_aa64dfr0, 20, 4) == wrps); | |
3ff6fc91 | 2730 | assert(extract32(cpu->id_aa64dfr0, 28, 4) == ctx_cmps); |
48eb3ae6 | 2731 | } |
0b45451e | 2732 | |
48eb3ae6 | 2733 | define_one_arm_cp_reg(cpu, &dbgdidr); |
50300698 PM |
2734 | define_arm_cp_regs(cpu, debug_cp_reginfo); |
2735 | ||
2736 | if (arm_feature(&cpu->env, ARM_FEATURE_LPAE)) { | |
2737 | define_arm_cp_regs(cpu, debug_lpae_cp_reginfo); | |
2738 | } | |
2739 | ||
48eb3ae6 | 2740 | for (i = 0; i < brps + 1; i++) { |
0b45451e | 2741 | ARMCPRegInfo dbgregs[] = { |
10aae104 PM |
2742 | { .name = "DBGBVR", .state = ARM_CP_STATE_BOTH, |
2743 | .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 4, | |
0b45451e | 2744 | .access = PL1_RW, |
46747d15 PM |
2745 | .fieldoffset = offsetof(CPUARMState, cp15.dbgbvr[i]), |
2746 | .writefn = dbgbvr_write, .raw_writefn = raw_write | |
2747 | }, | |
10aae104 PM |
2748 | { .name = "DBGBCR", .state = ARM_CP_STATE_BOTH, |
2749 | .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 5, | |
0b45451e | 2750 | .access = PL1_RW, |
46747d15 PM |
2751 | .fieldoffset = offsetof(CPUARMState, cp15.dbgbcr[i]), |
2752 | .writefn = dbgbcr_write, .raw_writefn = raw_write | |
2753 | }, | |
48eb3ae6 PM |
2754 | REGINFO_SENTINEL |
2755 | }; | |
2756 | define_arm_cp_regs(cpu, dbgregs); | |
2757 | } | |
2758 | ||
2759 | for (i = 0; i < wrps + 1; i++) { | |
2760 | ARMCPRegInfo dbgregs[] = { | |
10aae104 PM |
2761 | { .name = "DBGWVR", .state = ARM_CP_STATE_BOTH, |
2762 | .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 6, | |
0b45451e | 2763 | .access = PL1_RW, |
9ee98ce8 PM |
2764 | .fieldoffset = offsetof(CPUARMState, cp15.dbgwvr[i]), |
2765 | .writefn = dbgwvr_write, .raw_writefn = raw_write | |
2766 | }, | |
10aae104 PM |
2767 | { .name = "DBGWCR", .state = ARM_CP_STATE_BOTH, |
2768 | .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 7, | |
0b45451e | 2769 | .access = PL1_RW, |
9ee98ce8 PM |
2770 | .fieldoffset = offsetof(CPUARMState, cp15.dbgwcr[i]), |
2771 | .writefn = dbgwcr_write, .raw_writefn = raw_write | |
2772 | }, | |
2773 | REGINFO_SENTINEL | |
0b45451e PM |
2774 | }; |
2775 | define_arm_cp_regs(cpu, dbgregs); | |
2776 | } | |
2777 | } | |
2778 | ||
2ceb98c0 PM |
2779 | void register_cp_regs_for_features(ARMCPU *cpu) |
2780 | { | |
2781 | /* Register all the coprocessor registers based on feature bits */ | |
2782 | CPUARMState *env = &cpu->env; | |
2783 | if (arm_feature(env, ARM_FEATURE_M)) { | |
2784 | /* M profile has no coprocessor registers */ | |
2785 | return; | |
2786 | } | |
2787 | ||
e9aa6c21 | 2788 | define_arm_cp_regs(cpu, cp_reginfo); |
9449fdf6 PM |
2789 | if (!arm_feature(env, ARM_FEATURE_V8)) { |
2790 | /* Must go early as it is full of wildcards that may be | |
2791 | * overridden by later definitions. | |
2792 | */ | |
2793 | define_arm_cp_regs(cpu, not_v8_cp_reginfo); | |
2794 | } | |
2795 | ||
7d57f408 | 2796 | if (arm_feature(env, ARM_FEATURE_V6)) { |
8515a092 PM |
2797 | /* The ID registers all have impdef reset values */ |
2798 | ARMCPRegInfo v6_idregs[] = { | |
0ff644a7 PM |
2799 | { .name = "ID_PFR0", .state = ARM_CP_STATE_BOTH, |
2800 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 0, | |
2801 | .access = PL1_R, .type = ARM_CP_CONST, | |
8515a092 | 2802 | .resetvalue = cpu->id_pfr0 }, |
0ff644a7 PM |
2803 | { .name = "ID_PFR1", .state = ARM_CP_STATE_BOTH, |
2804 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 1, | |
2805 | .access = PL1_R, .type = ARM_CP_CONST, | |
8515a092 | 2806 | .resetvalue = cpu->id_pfr1 }, |
0ff644a7 PM |
2807 | { .name = "ID_DFR0", .state = ARM_CP_STATE_BOTH, |
2808 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 2, | |
2809 | .access = PL1_R, .type = ARM_CP_CONST, | |
8515a092 | 2810 | .resetvalue = cpu->id_dfr0 }, |
0ff644a7 PM |
2811 | { .name = "ID_AFR0", .state = ARM_CP_STATE_BOTH, |
2812 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 3, | |
2813 | .access = PL1_R, .type = ARM_CP_CONST, | |
8515a092 | 2814 | .resetvalue = cpu->id_afr0 }, |
0ff644a7 PM |
2815 | { .name = "ID_MMFR0", .state = ARM_CP_STATE_BOTH, |
2816 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 4, | |
2817 | .access = PL1_R, .type = ARM_CP_CONST, | |
8515a092 | 2818 | .resetvalue = cpu->id_mmfr0 }, |
0ff644a7 PM |
2819 | { .name = "ID_MMFR1", .state = ARM_CP_STATE_BOTH, |
2820 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 5, | |
2821 | .access = PL1_R, .type = ARM_CP_CONST, | |
8515a092 | 2822 | .resetvalue = cpu->id_mmfr1 }, |
0ff644a7 PM |
2823 | { .name = "ID_MMFR2", .state = ARM_CP_STATE_BOTH, |
2824 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 6, | |
2825 | .access = PL1_R, .type = ARM_CP_CONST, | |
8515a092 | 2826 | .resetvalue = cpu->id_mmfr2 }, |
0ff644a7 PM |
2827 | { .name = "ID_MMFR3", .state = ARM_CP_STATE_BOTH, |
2828 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 7, | |
2829 | .access = PL1_R, .type = ARM_CP_CONST, | |
8515a092 | 2830 | .resetvalue = cpu->id_mmfr3 }, |
0ff644a7 PM |
2831 | { .name = "ID_ISAR0", .state = ARM_CP_STATE_BOTH, |
2832 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 0, | |
2833 | .access = PL1_R, .type = ARM_CP_CONST, | |
8515a092 | 2834 | .resetvalue = cpu->id_isar0 }, |
0ff644a7 PM |
2835 | { .name = "ID_ISAR1", .state = ARM_CP_STATE_BOTH, |
2836 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 1, | |
2837 | .access = PL1_R, .type = ARM_CP_CONST, | |
8515a092 | 2838 | .resetvalue = cpu->id_isar1 }, |
0ff644a7 PM |
2839 | { .name = "ID_ISAR2", .state = ARM_CP_STATE_BOTH, |
2840 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 2, | |
2841 | .access = PL1_R, .type = ARM_CP_CONST, | |
8515a092 | 2842 | .resetvalue = cpu->id_isar2 }, |
0ff644a7 PM |
2843 | { .name = "ID_ISAR3", .state = ARM_CP_STATE_BOTH, |
2844 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 3, | |
2845 | .access = PL1_R, .type = ARM_CP_CONST, | |
8515a092 | 2846 | .resetvalue = cpu->id_isar3 }, |
0ff644a7 PM |
2847 | { .name = "ID_ISAR4", .state = ARM_CP_STATE_BOTH, |
2848 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 4, | |
2849 | .access = PL1_R, .type = ARM_CP_CONST, | |
8515a092 | 2850 | .resetvalue = cpu->id_isar4 }, |
0ff644a7 PM |
2851 | { .name = "ID_ISAR5", .state = ARM_CP_STATE_BOTH, |
2852 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 5, | |
2853 | .access = PL1_R, .type = ARM_CP_CONST, | |
8515a092 PM |
2854 | .resetvalue = cpu->id_isar5 }, |
2855 | /* 6..7 are as yet unallocated and must RAZ */ | |
2856 | { .name = "ID_ISAR6", .cp = 15, .crn = 0, .crm = 2, | |
2857 | .opc1 = 0, .opc2 = 6, .access = PL1_R, .type = ARM_CP_CONST, | |
2858 | .resetvalue = 0 }, | |
2859 | { .name = "ID_ISAR7", .cp = 15, .crn = 0, .crm = 2, | |
2860 | .opc1 = 0, .opc2 = 7, .access = PL1_R, .type = ARM_CP_CONST, | |
2861 | .resetvalue = 0 }, | |
2862 | REGINFO_SENTINEL | |
2863 | }; | |
2864 | define_arm_cp_regs(cpu, v6_idregs); | |
7d57f408 PM |
2865 | define_arm_cp_regs(cpu, v6_cp_reginfo); |
2866 | } else { | |
2867 | define_arm_cp_regs(cpu, not_v6_cp_reginfo); | |
2868 | } | |
4d31c596 PM |
2869 | if (arm_feature(env, ARM_FEATURE_V6K)) { |
2870 | define_arm_cp_regs(cpu, v6k_cp_reginfo); | |
2871 | } | |
995939a6 PM |
2872 | if (arm_feature(env, ARM_FEATURE_V7MP)) { |
2873 | define_arm_cp_regs(cpu, v7mp_cp_reginfo); | |
2874 | } | |
e9aa6c21 | 2875 | if (arm_feature(env, ARM_FEATURE_V7)) { |
200ac0ef | 2876 | /* v7 performance monitor control register: same implementor |
7c2cb42b AF |
2877 | * field as main ID register, and we implement only the cycle |
2878 | * count register. | |
200ac0ef | 2879 | */ |
7c2cb42b | 2880 | #ifndef CONFIG_USER_ONLY |
200ac0ef PM |
2881 | ARMCPRegInfo pmcr = { |
2882 | .name = "PMCR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 0, | |
8521466b AF |
2883 | .access = PL0_RW, |
2884 | .type = ARM_CP_IO | ARM_CP_NO_MIGRATE, | |
2885 | .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmcr), | |
fcd25206 PM |
2886 | .accessfn = pmreg_access, .writefn = pmcr_write, |
2887 | .raw_writefn = raw_write, | |
200ac0ef | 2888 | }; |
8521466b AF |
2889 | ARMCPRegInfo pmcr64 = { |
2890 | .name = "PMCR_EL0", .state = ARM_CP_STATE_AA64, | |
2891 | .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 0, | |
2892 | .access = PL0_RW, .accessfn = pmreg_access, | |
2893 | .type = ARM_CP_IO, | |
2894 | .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcr), | |
2895 | .resetvalue = cpu->midr & 0xff000000, | |
2896 | .writefn = pmcr_write, .raw_writefn = raw_write, | |
2897 | }; | |
7c2cb42b | 2898 | define_one_arm_cp_reg(cpu, &pmcr); |
8521466b | 2899 | define_one_arm_cp_reg(cpu, &pmcr64); |
7c2cb42b | 2900 | #endif |
776d4e5c | 2901 | ARMCPRegInfo clidr = { |
7da845b0 PM |
2902 | .name = "CLIDR", .state = ARM_CP_STATE_BOTH, |
2903 | .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 1, | |
776d4e5c PM |
2904 | .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = cpu->clidr |
2905 | }; | |
776d4e5c | 2906 | define_one_arm_cp_reg(cpu, &clidr); |
e9aa6c21 | 2907 | define_arm_cp_regs(cpu, v7_cp_reginfo); |
50300698 | 2908 | define_debug_regs(cpu); |
7d57f408 PM |
2909 | } else { |
2910 | define_arm_cp_regs(cpu, not_v7_cp_reginfo); | |
e9aa6c21 | 2911 | } |
b0d2b7d0 | 2912 | if (arm_feature(env, ARM_FEATURE_V8)) { |
e60cef86 PM |
2913 | /* AArch64 ID registers, which all have impdef reset values */ |
2914 | ARMCPRegInfo v8_idregs[] = { | |
2915 | { .name = "ID_AA64PFR0_EL1", .state = ARM_CP_STATE_AA64, | |
2916 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 0, | |
2917 | .access = PL1_R, .type = ARM_CP_CONST, | |
2918 | .resetvalue = cpu->id_aa64pfr0 }, | |
2919 | { .name = "ID_AA64PFR1_EL1", .state = ARM_CP_STATE_AA64, | |
2920 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 1, | |
2921 | .access = PL1_R, .type = ARM_CP_CONST, | |
2922 | .resetvalue = cpu->id_aa64pfr1}, | |
2923 | { .name = "ID_AA64DFR0_EL1", .state = ARM_CP_STATE_AA64, | |
2924 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 0, | |
2925 | .access = PL1_R, .type = ARM_CP_CONST, | |
5d831be2 | 2926 | /* We mask out the PMUVer field, because we don't currently |
9225d739 PM |
2927 | * implement the PMU. Not advertising it prevents the guest |
2928 | * from trying to use it and getting UNDEFs on registers we | |
2929 | * don't implement. | |
2930 | */ | |
2931 | .resetvalue = cpu->id_aa64dfr0 & ~0xf00 }, | |
e60cef86 PM |
2932 | { .name = "ID_AA64DFR1_EL1", .state = ARM_CP_STATE_AA64, |
2933 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 1, | |
2934 | .access = PL1_R, .type = ARM_CP_CONST, | |
2935 | .resetvalue = cpu->id_aa64dfr1 }, | |
2936 | { .name = "ID_AA64AFR0_EL1", .state = ARM_CP_STATE_AA64, | |
2937 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 4, | |
2938 | .access = PL1_R, .type = ARM_CP_CONST, | |
2939 | .resetvalue = cpu->id_aa64afr0 }, | |
2940 | { .name = "ID_AA64AFR1_EL1", .state = ARM_CP_STATE_AA64, | |
2941 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 5, | |
2942 | .access = PL1_R, .type = ARM_CP_CONST, | |
2943 | .resetvalue = cpu->id_aa64afr1 }, | |
2944 | { .name = "ID_AA64ISAR0_EL1", .state = ARM_CP_STATE_AA64, | |
2945 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 0, | |
2946 | .access = PL1_R, .type = ARM_CP_CONST, | |
2947 | .resetvalue = cpu->id_aa64isar0 }, | |
2948 | { .name = "ID_AA64ISAR1_EL1", .state = ARM_CP_STATE_AA64, | |
2949 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 1, | |
2950 | .access = PL1_R, .type = ARM_CP_CONST, | |
2951 | .resetvalue = cpu->id_aa64isar1 }, | |
2952 | { .name = "ID_AA64MMFR0_EL1", .state = ARM_CP_STATE_AA64, | |
2953 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 0, | |
2954 | .access = PL1_R, .type = ARM_CP_CONST, | |
2955 | .resetvalue = cpu->id_aa64mmfr0 }, | |
2956 | { .name = "ID_AA64MMFR1_EL1", .state = ARM_CP_STATE_AA64, | |
2957 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 1, | |
2958 | .access = PL1_R, .type = ARM_CP_CONST, | |
2959 | .resetvalue = cpu->id_aa64mmfr1 }, | |
a50c0f51 PM |
2960 | { .name = "MVFR0_EL1", .state = ARM_CP_STATE_AA64, |
2961 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 0, | |
2962 | .access = PL1_R, .type = ARM_CP_CONST, | |
2963 | .resetvalue = cpu->mvfr0 }, | |
2964 | { .name = "MVFR1_EL1", .state = ARM_CP_STATE_AA64, | |
2965 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 1, | |
2966 | .access = PL1_R, .type = ARM_CP_CONST, | |
2967 | .resetvalue = cpu->mvfr1 }, | |
2968 | { .name = "MVFR2_EL1", .state = ARM_CP_STATE_AA64, | |
2969 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 2, | |
2970 | .access = PL1_R, .type = ARM_CP_CONST, | |
2971 | .resetvalue = cpu->mvfr2 }, | |
e60cef86 PM |
2972 | REGINFO_SENTINEL |
2973 | }; | |
3933443e PM |
2974 | ARMCPRegInfo rvbar = { |
2975 | .name = "RVBAR_EL1", .state = ARM_CP_STATE_AA64, | |
2976 | .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 0, .opc2 = 2, | |
2977 | .type = ARM_CP_CONST, .access = PL1_R, .resetvalue = cpu->rvbar | |
2978 | }; | |
2979 | define_one_arm_cp_reg(cpu, &rvbar); | |
e60cef86 | 2980 | define_arm_cp_regs(cpu, v8_idregs); |
b0d2b7d0 PM |
2981 | define_arm_cp_regs(cpu, v8_cp_reginfo); |
2982 | } | |
3b685ba7 EI |
2983 | if (arm_feature(env, ARM_FEATURE_EL2)) { |
2984 | define_arm_cp_regs(cpu, v8_el2_cp_reginfo); | |
d42e3c26 EI |
2985 | } else { |
2986 | /* If EL2 is missing but higher ELs are enabled, we need to | |
2987 | * register the no_el2 reginfos. | |
2988 | */ | |
2989 | if (arm_feature(env, ARM_FEATURE_EL3)) { | |
2990 | define_arm_cp_regs(cpu, v8_el3_no_el2_cp_reginfo); | |
2991 | } | |
3b685ba7 | 2992 | } |
81547d66 | 2993 | if (arm_feature(env, ARM_FEATURE_EL3)) { |
0f1a3b24 FA |
2994 | if (arm_feature(env, ARM_FEATURE_V8)) { |
2995 | define_arm_cp_regs(cpu, v8_el3_cp_reginfo); | |
2996 | } | |
2997 | define_arm_cp_regs(cpu, el3_cp_reginfo); | |
81547d66 | 2998 | } |
18032bec PM |
2999 | if (arm_feature(env, ARM_FEATURE_MPU)) { |
3000 | /* These are the MPU registers prior to PMSAv6. Any new | |
3001 | * PMSA core later than the ARM946 will require that we | |
3002 | * implement the PMSAv6 or PMSAv7 registers, which are | |
3003 | * completely different. | |
3004 | */ | |
3005 | assert(!arm_feature(env, ARM_FEATURE_V6)); | |
3006 | define_arm_cp_regs(cpu, pmsav5_cp_reginfo); | |
3007 | } else { | |
3008 | define_arm_cp_regs(cpu, vmsa_cp_reginfo); | |
3009 | } | |
c326b979 PM |
3010 | if (arm_feature(env, ARM_FEATURE_THUMB2EE)) { |
3011 | define_arm_cp_regs(cpu, t2ee_cp_reginfo); | |
3012 | } | |
6cc7a3ae PM |
3013 | if (arm_feature(env, ARM_FEATURE_GENERIC_TIMER)) { |
3014 | define_arm_cp_regs(cpu, generic_timer_cp_reginfo); | |
3015 | } | |
4a501606 PM |
3016 | if (arm_feature(env, ARM_FEATURE_VAPA)) { |
3017 | define_arm_cp_regs(cpu, vapa_cp_reginfo); | |
3018 | } | |
c4804214 PM |
3019 | if (arm_feature(env, ARM_FEATURE_CACHE_TEST_CLEAN)) { |
3020 | define_arm_cp_regs(cpu, cache_test_clean_cp_reginfo); | |
3021 | } | |
3022 | if (arm_feature(env, ARM_FEATURE_CACHE_DIRTY_REG)) { | |
3023 | define_arm_cp_regs(cpu, cache_dirty_status_cp_reginfo); | |
3024 | } | |
3025 | if (arm_feature(env, ARM_FEATURE_CACHE_BLOCK_OPS)) { | |
3026 | define_arm_cp_regs(cpu, cache_block_ops_cp_reginfo); | |
3027 | } | |
18032bec PM |
3028 | if (arm_feature(env, ARM_FEATURE_OMAPCP)) { |
3029 | define_arm_cp_regs(cpu, omap_cp_reginfo); | |
3030 | } | |
34f90529 PM |
3031 | if (arm_feature(env, ARM_FEATURE_STRONGARM)) { |
3032 | define_arm_cp_regs(cpu, strongarm_cp_reginfo); | |
3033 | } | |
1047b9d7 PM |
3034 | if (arm_feature(env, ARM_FEATURE_XSCALE)) { |
3035 | define_arm_cp_regs(cpu, xscale_cp_reginfo); | |
3036 | } | |
3037 | if (arm_feature(env, ARM_FEATURE_DUMMY_C15_REGS)) { | |
3038 | define_arm_cp_regs(cpu, dummy_c15_cp_reginfo); | |
3039 | } | |
7ac681cf PM |
3040 | if (arm_feature(env, ARM_FEATURE_LPAE)) { |
3041 | define_arm_cp_regs(cpu, lpae_cp_reginfo); | |
3042 | } | |
7884849c PM |
3043 | /* Slightly awkwardly, the OMAP and StrongARM cores need all of |
3044 | * cp15 crn=0 to be writes-ignored, whereas for other cores they should | |
3045 | * be read-only (ie write causes UNDEF exception). | |
3046 | */ | |
3047 | { | |
00a29f3d PM |
3048 | ARMCPRegInfo id_pre_v8_midr_cp_reginfo[] = { |
3049 | /* Pre-v8 MIDR space. | |
3050 | * Note that the MIDR isn't a simple constant register because | |
7884849c PM |
3051 | * of the TI925 behaviour where writes to another register can |
3052 | * cause the MIDR value to change. | |
97ce8d61 PC |
3053 | * |
3054 | * Unimplemented registers in the c15 0 0 0 space default to | |
3055 | * MIDR. Define MIDR first as this entire space, then CTR, TCMTR | |
3056 | * and friends override accordingly. | |
7884849c PM |
3057 | */ |
3058 | { .name = "MIDR", | |
97ce8d61 | 3059 | .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = CP_ANY, |
7884849c | 3060 | .access = PL1_R, .resetvalue = cpu->midr, |
d4e6df63 | 3061 | .writefn = arm_cp_write_ignore, .raw_writefn = raw_write, |
97ce8d61 PC |
3062 | .fieldoffset = offsetof(CPUARMState, cp15.c0_cpuid), |
3063 | .type = ARM_CP_OVERRIDE }, | |
7884849c PM |
3064 | /* crn = 0 op1 = 0 crm = 3..7 : currently unassigned; we RAZ. */ |
3065 | { .name = "DUMMY", | |
3066 | .cp = 15, .crn = 0, .crm = 3, .opc1 = 0, .opc2 = CP_ANY, | |
3067 | .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
3068 | { .name = "DUMMY", | |
3069 | .cp = 15, .crn = 0, .crm = 4, .opc1 = 0, .opc2 = CP_ANY, | |
3070 | .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
3071 | { .name = "DUMMY", | |
3072 | .cp = 15, .crn = 0, .crm = 5, .opc1 = 0, .opc2 = CP_ANY, | |
3073 | .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
3074 | { .name = "DUMMY", | |
3075 | .cp = 15, .crn = 0, .crm = 6, .opc1 = 0, .opc2 = CP_ANY, | |
3076 | .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
3077 | { .name = "DUMMY", | |
3078 | .cp = 15, .crn = 0, .crm = 7, .opc1 = 0, .opc2 = CP_ANY, | |
3079 | .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
3080 | REGINFO_SENTINEL | |
3081 | }; | |
00a29f3d PM |
3082 | ARMCPRegInfo id_v8_midr_cp_reginfo[] = { |
3083 | /* v8 MIDR -- the wildcard isn't necessary, and nor is the | |
3084 | * variable-MIDR TI925 behaviour. Instead we have a single | |
3085 | * (strictly speaking IMPDEF) alias of the MIDR, REVIDR. | |
3086 | */ | |
3087 | { .name = "MIDR_EL1", .state = ARM_CP_STATE_BOTH, | |
3088 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 0, .opc2 = 0, | |
3089 | .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = cpu->midr }, | |
3090 | { .name = "REVIDR_EL1", .state = ARM_CP_STATE_BOTH, | |
3091 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 0, .opc2 = 6, | |
3092 | .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = cpu->midr }, | |
3093 | REGINFO_SENTINEL | |
3094 | }; | |
3095 | ARMCPRegInfo id_cp_reginfo[] = { | |
3096 | /* These are common to v8 and pre-v8 */ | |
3097 | { .name = "CTR", | |
3098 | .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 1, | |
3099 | .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = cpu->ctr }, | |
3100 | { .name = "CTR_EL0", .state = ARM_CP_STATE_AA64, | |
3101 | .opc0 = 3, .opc1 = 3, .opc2 = 1, .crn = 0, .crm = 0, | |
3102 | .access = PL0_R, .accessfn = ctr_el0_access, | |
3103 | .type = ARM_CP_CONST, .resetvalue = cpu->ctr }, | |
3104 | /* TCMTR and TLBTR exist in v8 but have no 64-bit versions */ | |
3105 | { .name = "TCMTR", | |
3106 | .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 2, | |
3107 | .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
3108 | { .name = "TLBTR", | |
3109 | .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 3, | |
3110 | .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
3111 | REGINFO_SENTINEL | |
3112 | }; | |
7884849c PM |
3113 | ARMCPRegInfo crn0_wi_reginfo = { |
3114 | .name = "CRN0_WI", .cp = 15, .crn = 0, .crm = CP_ANY, | |
3115 | .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_W, | |
3116 | .type = ARM_CP_NOP | ARM_CP_OVERRIDE | |
3117 | }; | |
3118 | if (arm_feature(env, ARM_FEATURE_OMAPCP) || | |
3119 | arm_feature(env, ARM_FEATURE_STRONGARM)) { | |
3120 | ARMCPRegInfo *r; | |
3121 | /* Register the blanket "writes ignored" value first to cover the | |
a703eda1 PC |
3122 | * whole space. Then update the specific ID registers to allow write |
3123 | * access, so that they ignore writes rather than causing them to | |
3124 | * UNDEF. | |
7884849c PM |
3125 | */ |
3126 | define_one_arm_cp_reg(cpu, &crn0_wi_reginfo); | |
00a29f3d PM |
3127 | for (r = id_pre_v8_midr_cp_reginfo; |
3128 | r->type != ARM_CP_SENTINEL; r++) { | |
3129 | r->access = PL1_RW; | |
3130 | } | |
7884849c PM |
3131 | for (r = id_cp_reginfo; r->type != ARM_CP_SENTINEL; r++) { |
3132 | r->access = PL1_RW; | |
7884849c | 3133 | } |
7884849c | 3134 | } |
00a29f3d PM |
3135 | if (arm_feature(env, ARM_FEATURE_V8)) { |
3136 | define_arm_cp_regs(cpu, id_v8_midr_cp_reginfo); | |
3137 | } else { | |
3138 | define_arm_cp_regs(cpu, id_pre_v8_midr_cp_reginfo); | |
3139 | } | |
a703eda1 | 3140 | define_arm_cp_regs(cpu, id_cp_reginfo); |
7884849c PM |
3141 | } |
3142 | ||
97ce8d61 PC |
3143 | if (arm_feature(env, ARM_FEATURE_MPIDR)) { |
3144 | define_arm_cp_regs(cpu, mpidr_cp_reginfo); | |
3145 | } | |
3146 | ||
2771db27 PM |
3147 | if (arm_feature(env, ARM_FEATURE_AUXCR)) { |
3148 | ARMCPRegInfo auxcr = { | |
2eef0bf8 PM |
3149 | .name = "ACTLR_EL1", .state = ARM_CP_STATE_BOTH, |
3150 | .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 1, | |
2771db27 PM |
3151 | .access = PL1_RW, .type = ARM_CP_CONST, |
3152 | .resetvalue = cpu->reset_auxcr | |
3153 | }; | |
3154 | define_one_arm_cp_reg(cpu, &auxcr); | |
3155 | } | |
3156 | ||
d8ba780b | 3157 | if (arm_feature(env, ARM_FEATURE_CBAR)) { |
f318cec6 PM |
3158 | if (arm_feature(env, ARM_FEATURE_AARCH64)) { |
3159 | /* 32 bit view is [31:18] 0...0 [43:32]. */ | |
3160 | uint32_t cbar32 = (extract64(cpu->reset_cbar, 18, 14) << 18) | |
3161 | | extract64(cpu->reset_cbar, 32, 12); | |
3162 | ARMCPRegInfo cbar_reginfo[] = { | |
3163 | { .name = "CBAR", | |
3164 | .type = ARM_CP_CONST, | |
3165 | .cp = 15, .crn = 15, .crm = 0, .opc1 = 4, .opc2 = 0, | |
3166 | .access = PL1_R, .resetvalue = cpu->reset_cbar }, | |
3167 | { .name = "CBAR_EL1", .state = ARM_CP_STATE_AA64, | |
3168 | .type = ARM_CP_CONST, | |
3169 | .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 3, .opc2 = 0, | |
3170 | .access = PL1_R, .resetvalue = cbar32 }, | |
3171 | REGINFO_SENTINEL | |
3172 | }; | |
3173 | /* We don't implement a r/w 64 bit CBAR currently */ | |
3174 | assert(arm_feature(env, ARM_FEATURE_CBAR_RO)); | |
3175 | define_arm_cp_regs(cpu, cbar_reginfo); | |
3176 | } else { | |
3177 | ARMCPRegInfo cbar = { | |
3178 | .name = "CBAR", | |
3179 | .cp = 15, .crn = 15, .crm = 0, .opc1 = 4, .opc2 = 0, | |
3180 | .access = PL1_R|PL3_W, .resetvalue = cpu->reset_cbar, | |
3181 | .fieldoffset = offsetof(CPUARMState, | |
3182 | cp15.c15_config_base_address) | |
3183 | }; | |
3184 | if (arm_feature(env, ARM_FEATURE_CBAR_RO)) { | |
3185 | cbar.access = PL1_R; | |
3186 | cbar.fieldoffset = 0; | |
3187 | cbar.type = ARM_CP_CONST; | |
3188 | } | |
3189 | define_one_arm_cp_reg(cpu, &cbar); | |
3190 | } | |
d8ba780b PC |
3191 | } |
3192 | ||
2771db27 PM |
3193 | /* Generic registers whose values depend on the implementation */ |
3194 | { | |
3195 | ARMCPRegInfo sctlr = { | |
5ebafdf3 | 3196 | .name = "SCTLR", .state = ARM_CP_STATE_BOTH, |
137feaa9 FA |
3197 | .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 0, |
3198 | .access = PL1_RW, | |
3199 | .bank_fieldoffsets = { offsetof(CPUARMState, cp15.sctlr_s), | |
3200 | offsetof(CPUARMState, cp15.sctlr_ns) }, | |
d4e6df63 PM |
3201 | .writefn = sctlr_write, .resetvalue = cpu->reset_sctlr, |
3202 | .raw_writefn = raw_write, | |
2771db27 PM |
3203 | }; |
3204 | if (arm_feature(env, ARM_FEATURE_XSCALE)) { | |
3205 | /* Normally we would always end the TB on an SCTLR write, but Linux | |
3206 | * arch/arm/mach-pxa/sleep.S expects two instructions following | |
3207 | * an MMU enable to execute from cache. Imitate this behaviour. | |
3208 | */ | |
3209 | sctlr.type |= ARM_CP_SUPPRESS_TB_END; | |
3210 | } | |
3211 | define_one_arm_cp_reg(cpu, &sctlr); | |
3212 | } | |
2ceb98c0 PM |
3213 | } |
3214 | ||
778c3a06 | 3215 | ARMCPU *cpu_arm_init(const char *cpu_model) |
40f137e1 | 3216 | { |
9262685b | 3217 | return ARM_CPU(cpu_generic_init(TYPE_ARM_CPU, cpu_model)); |
14969266 AF |
3218 | } |
3219 | ||
3220 | void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu) | |
3221 | { | |
22169d41 | 3222 | CPUState *cs = CPU(cpu); |
14969266 AF |
3223 | CPUARMState *env = &cpu->env; |
3224 | ||
6a669427 PM |
3225 | if (arm_feature(env, ARM_FEATURE_AARCH64)) { |
3226 | gdb_register_coprocessor(cs, aarch64_fpu_gdb_get_reg, | |
3227 | aarch64_fpu_gdb_set_reg, | |
3228 | 34, "aarch64-fpu.xml", 0); | |
3229 | } else if (arm_feature(env, ARM_FEATURE_NEON)) { | |
22169d41 | 3230 | gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg, |
56aebc89 PB |
3231 | 51, "arm-neon.xml", 0); |
3232 | } else if (arm_feature(env, ARM_FEATURE_VFP3)) { | |
22169d41 | 3233 | gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg, |
56aebc89 PB |
3234 | 35, "arm-vfp3.xml", 0); |
3235 | } else if (arm_feature(env, ARM_FEATURE_VFP)) { | |
22169d41 | 3236 | gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg, |
56aebc89 PB |
3237 | 19, "arm-vfp.xml", 0); |
3238 | } | |
40f137e1 PB |
3239 | } |
3240 | ||
777dc784 PM |
3241 | /* Sort alphabetically by type name, except for "any". */ |
3242 | static gint arm_cpu_list_compare(gconstpointer a, gconstpointer b) | |
5adb4839 | 3243 | { |
777dc784 PM |
3244 | ObjectClass *class_a = (ObjectClass *)a; |
3245 | ObjectClass *class_b = (ObjectClass *)b; | |
3246 | const char *name_a, *name_b; | |
5adb4839 | 3247 | |
777dc784 PM |
3248 | name_a = object_class_get_name(class_a); |
3249 | name_b = object_class_get_name(class_b); | |
51492fd1 | 3250 | if (strcmp(name_a, "any-" TYPE_ARM_CPU) == 0) { |
777dc784 | 3251 | return 1; |
51492fd1 | 3252 | } else if (strcmp(name_b, "any-" TYPE_ARM_CPU) == 0) { |
777dc784 PM |
3253 | return -1; |
3254 | } else { | |
3255 | return strcmp(name_a, name_b); | |
5adb4839 PB |
3256 | } |
3257 | } | |
3258 | ||
777dc784 | 3259 | static void arm_cpu_list_entry(gpointer data, gpointer user_data) |
40f137e1 | 3260 | { |
777dc784 | 3261 | ObjectClass *oc = data; |
92a31361 | 3262 | CPUListState *s = user_data; |
51492fd1 AF |
3263 | const char *typename; |
3264 | char *name; | |
3371d272 | 3265 | |
51492fd1 AF |
3266 | typename = object_class_get_name(oc); |
3267 | name = g_strndup(typename, strlen(typename) - strlen("-" TYPE_ARM_CPU)); | |
777dc784 | 3268 | (*s->cpu_fprintf)(s->file, " %s\n", |
51492fd1 AF |
3269 | name); |
3270 | g_free(name); | |
777dc784 PM |
3271 | } |
3272 | ||
3273 | void arm_cpu_list(FILE *f, fprintf_function cpu_fprintf) | |
3274 | { | |
92a31361 | 3275 | CPUListState s = { |
777dc784 PM |
3276 | .file = f, |
3277 | .cpu_fprintf = cpu_fprintf, | |
3278 | }; | |
3279 | GSList *list; | |
3280 | ||
3281 | list = object_class_get_list(TYPE_ARM_CPU, false); | |
3282 | list = g_slist_sort(list, arm_cpu_list_compare); | |
3283 | (*cpu_fprintf)(f, "Available CPUs:\n"); | |
3284 | g_slist_foreach(list, arm_cpu_list_entry, &s); | |
3285 | g_slist_free(list); | |
a96c0514 PM |
3286 | #ifdef CONFIG_KVM |
3287 | /* The 'host' CPU type is dynamically registered only if KVM is | |
3288 | * enabled, so we have to special-case it here: | |
3289 | */ | |
3290 | (*cpu_fprintf)(f, " host (only available in KVM mode)\n"); | |
3291 | #endif | |
40f137e1 PB |
3292 | } |
3293 | ||
78027bb6 CR |
3294 | static void arm_cpu_add_definition(gpointer data, gpointer user_data) |
3295 | { | |
3296 | ObjectClass *oc = data; | |
3297 | CpuDefinitionInfoList **cpu_list = user_data; | |
3298 | CpuDefinitionInfoList *entry; | |
3299 | CpuDefinitionInfo *info; | |
3300 | const char *typename; | |
3301 | ||
3302 | typename = object_class_get_name(oc); | |
3303 | info = g_malloc0(sizeof(*info)); | |
3304 | info->name = g_strndup(typename, | |
3305 | strlen(typename) - strlen("-" TYPE_ARM_CPU)); | |
3306 | ||
3307 | entry = g_malloc0(sizeof(*entry)); | |
3308 | entry->value = info; | |
3309 | entry->next = *cpu_list; | |
3310 | *cpu_list = entry; | |
3311 | } | |
3312 | ||
3313 | CpuDefinitionInfoList *arch_query_cpu_definitions(Error **errp) | |
3314 | { | |
3315 | CpuDefinitionInfoList *cpu_list = NULL; | |
3316 | GSList *list; | |
3317 | ||
3318 | list = object_class_get_list(TYPE_ARM_CPU, false); | |
3319 | g_slist_foreach(list, arm_cpu_add_definition, &cpu_list); | |
3320 | g_slist_free(list); | |
3321 | ||
3322 | return cpu_list; | |
3323 | } | |
3324 | ||
6e6efd61 | 3325 | static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r, |
51a79b03 | 3326 | void *opaque, int state, int secstate, |
f5a0a5a5 | 3327 | int crm, int opc1, int opc2) |
6e6efd61 PM |
3328 | { |
3329 | /* Private utility function for define_one_arm_cp_reg_with_opaque(): | |
3330 | * add a single reginfo struct to the hash table. | |
3331 | */ | |
3332 | uint32_t *key = g_new(uint32_t, 1); | |
3333 | ARMCPRegInfo *r2 = g_memdup(r, sizeof(ARMCPRegInfo)); | |
3334 | int is64 = (r->type & ARM_CP_64BIT) ? 1 : 0; | |
3f3c82a5 FA |
3335 | int ns = (secstate & ARM_CP_SECSTATE_NS) ? 1 : 0; |
3336 | ||
3337 | /* Reset the secure state to the specific incoming state. This is | |
3338 | * necessary as the register may have been defined with both states. | |
3339 | */ | |
3340 | r2->secure = secstate; | |
3341 | ||
3342 | if (r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1]) { | |
3343 | /* Register is banked (using both entries in array). | |
3344 | * Overwriting fieldoffset as the array is only used to define | |
3345 | * banked registers but later only fieldoffset is used. | |
f5a0a5a5 | 3346 | */ |
3f3c82a5 FA |
3347 | r2->fieldoffset = r->bank_fieldoffsets[ns]; |
3348 | } | |
3349 | ||
3350 | if (state == ARM_CP_STATE_AA32) { | |
3351 | if (r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1]) { | |
3352 | /* If the register is banked then we don't need to migrate or | |
3353 | * reset the 32-bit instance in certain cases: | |
3354 | * | |
3355 | * 1) If the register has both 32-bit and 64-bit instances then we | |
3356 | * can count on the 64-bit instance taking care of the | |
3357 | * non-secure bank. | |
3358 | * 2) If ARMv8 is enabled then we can count on a 64-bit version | |
3359 | * taking care of the secure bank. This requires that separate | |
3360 | * 32 and 64-bit definitions are provided. | |
3361 | */ | |
3362 | if ((r->state == ARM_CP_STATE_BOTH && ns) || | |
3363 | (arm_feature(&cpu->env, ARM_FEATURE_V8) && !ns)) { | |
3364 | r2->type |= ARM_CP_NO_MIGRATE; | |
3365 | r2->resetfn = arm_cp_reset_ignore; | |
3366 | } | |
3367 | } else if ((secstate != r->secure) && !ns) { | |
3368 | /* The register is not banked so we only want to allow migration of | |
3369 | * the non-secure instance. | |
3370 | */ | |
3371 | r2->type |= ARM_CP_NO_MIGRATE; | |
3372 | r2->resetfn = arm_cp_reset_ignore; | |
58a1d8ce | 3373 | } |
3f3c82a5 FA |
3374 | |
3375 | if (r->state == ARM_CP_STATE_BOTH) { | |
3376 | /* We assume it is a cp15 register if the .cp field is left unset. | |
3377 | */ | |
3378 | if (r2->cp == 0) { | |
3379 | r2->cp = 15; | |
3380 | } | |
3381 | ||
f5a0a5a5 | 3382 | #ifdef HOST_WORDS_BIGENDIAN |
3f3c82a5 FA |
3383 | if (r2->fieldoffset) { |
3384 | r2->fieldoffset += sizeof(uint32_t); | |
3385 | } | |
f5a0a5a5 | 3386 | #endif |
3f3c82a5 | 3387 | } |
f5a0a5a5 PM |
3388 | } |
3389 | if (state == ARM_CP_STATE_AA64) { | |
3390 | /* To allow abbreviation of ARMCPRegInfo | |
3391 | * definitions, we treat cp == 0 as equivalent to | |
3392 | * the value for "standard guest-visible sysreg". | |
58a1d8ce PM |
3393 | * STATE_BOTH definitions are also always "standard |
3394 | * sysreg" in their AArch64 view (the .cp value may | |
3395 | * be non-zero for the benefit of the AArch32 view). | |
f5a0a5a5 | 3396 | */ |
58a1d8ce | 3397 | if (r->cp == 0 || r->state == ARM_CP_STATE_BOTH) { |
f5a0a5a5 PM |
3398 | r2->cp = CP_REG_ARM64_SYSREG_CP; |
3399 | } | |
3400 | *key = ENCODE_AA64_CP_REG(r2->cp, r2->crn, crm, | |
3401 | r2->opc0, opc1, opc2); | |
3402 | } else { | |
51a79b03 | 3403 | *key = ENCODE_CP_REG(r2->cp, is64, ns, r2->crn, crm, opc1, opc2); |
f5a0a5a5 | 3404 | } |
6e6efd61 PM |
3405 | if (opaque) { |
3406 | r2->opaque = opaque; | |
3407 | } | |
67ed771d PM |
3408 | /* reginfo passed to helpers is correct for the actual access, |
3409 | * and is never ARM_CP_STATE_BOTH: | |
3410 | */ | |
3411 | r2->state = state; | |
6e6efd61 PM |
3412 | /* Make sure reginfo passed to helpers for wildcarded regs |
3413 | * has the correct crm/opc1/opc2 for this reg, not CP_ANY: | |
3414 | */ | |
3415 | r2->crm = crm; | |
3416 | r2->opc1 = opc1; | |
3417 | r2->opc2 = opc2; | |
3418 | /* By convention, for wildcarded registers only the first | |
3419 | * entry is used for migration; the others are marked as | |
3420 | * NO_MIGRATE so we don't try to transfer the register | |
3421 | * multiple times. Special registers (ie NOP/WFI) are | |
3422 | * never migratable. | |
3423 | */ | |
3424 | if ((r->type & ARM_CP_SPECIAL) || | |
3425 | ((r->crm == CP_ANY) && crm != 0) || | |
3426 | ((r->opc1 == CP_ANY) && opc1 != 0) || | |
3427 | ((r->opc2 == CP_ANY) && opc2 != 0)) { | |
3428 | r2->type |= ARM_CP_NO_MIGRATE; | |
3429 | } | |
3430 | ||
3431 | /* Overriding of an existing definition must be explicitly | |
3432 | * requested. | |
3433 | */ | |
3434 | if (!(r->type & ARM_CP_OVERRIDE)) { | |
3435 | ARMCPRegInfo *oldreg; | |
3436 | oldreg = g_hash_table_lookup(cpu->cp_regs, key); | |
3437 | if (oldreg && !(oldreg->type & ARM_CP_OVERRIDE)) { | |
3438 | fprintf(stderr, "Register redefined: cp=%d %d bit " | |
3439 | "crn=%d crm=%d opc1=%d opc2=%d, " | |
3440 | "was %s, now %s\n", r2->cp, 32 + 32 * is64, | |
3441 | r2->crn, r2->crm, r2->opc1, r2->opc2, | |
3442 | oldreg->name, r2->name); | |
3443 | g_assert_not_reached(); | |
3444 | } | |
3445 | } | |
3446 | g_hash_table_insert(cpu->cp_regs, key, r2); | |
3447 | } | |
3448 | ||
3449 | ||
4b6a83fb PM |
3450 | void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu, |
3451 | const ARMCPRegInfo *r, void *opaque) | |
3452 | { | |
3453 | /* Define implementations of coprocessor registers. | |
3454 | * We store these in a hashtable because typically | |
3455 | * there are less than 150 registers in a space which | |
3456 | * is 16*16*16*8*8 = 262144 in size. | |
3457 | * Wildcarding is supported for the crm, opc1 and opc2 fields. | |
3458 | * If a register is defined twice then the second definition is | |
3459 | * used, so this can be used to define some generic registers and | |
3460 | * then override them with implementation specific variations. | |
3461 | * At least one of the original and the second definition should | |
3462 | * include ARM_CP_OVERRIDE in its type bits -- this is just a guard | |
3463 | * against accidental use. | |
f5a0a5a5 PM |
3464 | * |
3465 | * The state field defines whether the register is to be | |
3466 | * visible in the AArch32 or AArch64 execution state. If the | |
3467 | * state is set to ARM_CP_STATE_BOTH then we synthesise a | |
3468 | * reginfo structure for the AArch32 view, which sees the lower | |
3469 | * 32 bits of the 64 bit register. | |
3470 | * | |
3471 | * Only registers visible in AArch64 may set r->opc0; opc0 cannot | |
3472 | * be wildcarded. AArch64 registers are always considered to be 64 | |
3473 | * bits; the ARM_CP_64BIT* flag applies only to the AArch32 view of | |
3474 | * the register, if any. | |
4b6a83fb | 3475 | */ |
f5a0a5a5 | 3476 | int crm, opc1, opc2, state; |
4b6a83fb PM |
3477 | int crmmin = (r->crm == CP_ANY) ? 0 : r->crm; |
3478 | int crmmax = (r->crm == CP_ANY) ? 15 : r->crm; | |
3479 | int opc1min = (r->opc1 == CP_ANY) ? 0 : r->opc1; | |
3480 | int opc1max = (r->opc1 == CP_ANY) ? 7 : r->opc1; | |
3481 | int opc2min = (r->opc2 == CP_ANY) ? 0 : r->opc2; | |
3482 | int opc2max = (r->opc2 == CP_ANY) ? 7 : r->opc2; | |
3483 | /* 64 bit registers have only CRm and Opc1 fields */ | |
3484 | assert(!((r->type & ARM_CP_64BIT) && (r->opc2 || r->crn))); | |
f5a0a5a5 PM |
3485 | /* op0 only exists in the AArch64 encodings */ |
3486 | assert((r->state != ARM_CP_STATE_AA32) || (r->opc0 == 0)); | |
3487 | /* AArch64 regs are all 64 bit so ARM_CP_64BIT is meaningless */ | |
3488 | assert((r->state != ARM_CP_STATE_AA64) || !(r->type & ARM_CP_64BIT)); | |
3489 | /* The AArch64 pseudocode CheckSystemAccess() specifies that op1 | |
3490 | * encodes a minimum access level for the register. We roll this | |
3491 | * runtime check into our general permission check code, so check | |
3492 | * here that the reginfo's specified permissions are strict enough | |
3493 | * to encompass the generic architectural permission check. | |
3494 | */ | |
3495 | if (r->state != ARM_CP_STATE_AA32) { | |
3496 | int mask = 0; | |
3497 | switch (r->opc1) { | |
3498 | case 0: case 1: case 2: | |
3499 | /* min_EL EL1 */ | |
3500 | mask = PL1_RW; | |
3501 | break; | |
3502 | case 3: | |
3503 | /* min_EL EL0 */ | |
3504 | mask = PL0_RW; | |
3505 | break; | |
3506 | case 4: | |
3507 | /* min_EL EL2 */ | |
3508 | mask = PL2_RW; | |
3509 | break; | |
3510 | case 5: | |
3511 | /* unallocated encoding, so not possible */ | |
3512 | assert(false); | |
3513 | break; | |
3514 | case 6: | |
3515 | /* min_EL EL3 */ | |
3516 | mask = PL3_RW; | |
3517 | break; | |
3518 | case 7: | |
3519 | /* min_EL EL1, secure mode only (we don't check the latter) */ | |
3520 | mask = PL1_RW; | |
3521 | break; | |
3522 | default: | |
3523 | /* broken reginfo with out-of-range opc1 */ | |
3524 | assert(false); | |
3525 | break; | |
3526 | } | |
3527 | /* assert our permissions are not too lax (stricter is fine) */ | |
3528 | assert((r->access & ~mask) == 0); | |
3529 | } | |
3530 | ||
4b6a83fb PM |
3531 | /* Check that the register definition has enough info to handle |
3532 | * reads and writes if they are permitted. | |
3533 | */ | |
3534 | if (!(r->type & (ARM_CP_SPECIAL|ARM_CP_CONST))) { | |
3535 | if (r->access & PL3_R) { | |
3f3c82a5 FA |
3536 | assert((r->fieldoffset || |
3537 | (r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1])) || | |
3538 | r->readfn); | |
4b6a83fb PM |
3539 | } |
3540 | if (r->access & PL3_W) { | |
3f3c82a5 FA |
3541 | assert((r->fieldoffset || |
3542 | (r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1])) || | |
3543 | r->writefn); | |
4b6a83fb PM |
3544 | } |
3545 | } | |
3546 | /* Bad type field probably means missing sentinel at end of reg list */ | |
3547 | assert(cptype_valid(r->type)); | |
3548 | for (crm = crmmin; crm <= crmmax; crm++) { | |
3549 | for (opc1 = opc1min; opc1 <= opc1max; opc1++) { | |
3550 | for (opc2 = opc2min; opc2 <= opc2max; opc2++) { | |
f5a0a5a5 PM |
3551 | for (state = ARM_CP_STATE_AA32; |
3552 | state <= ARM_CP_STATE_AA64; state++) { | |
3553 | if (r->state != state && r->state != ARM_CP_STATE_BOTH) { | |
3554 | continue; | |
3555 | } | |
3f3c82a5 FA |
3556 | if (state == ARM_CP_STATE_AA32) { |
3557 | /* Under AArch32 CP registers can be common | |
3558 | * (same for secure and non-secure world) or banked. | |
3559 | */ | |
3560 | switch (r->secure) { | |
3561 | case ARM_CP_SECSTATE_S: | |
3562 | case ARM_CP_SECSTATE_NS: | |
3563 | add_cpreg_to_hashtable(cpu, r, opaque, state, | |
3564 | r->secure, crm, opc1, opc2); | |
3565 | break; | |
3566 | default: | |
3567 | add_cpreg_to_hashtable(cpu, r, opaque, state, | |
3568 | ARM_CP_SECSTATE_S, | |
3569 | crm, opc1, opc2); | |
3570 | add_cpreg_to_hashtable(cpu, r, opaque, state, | |
3571 | ARM_CP_SECSTATE_NS, | |
3572 | crm, opc1, opc2); | |
3573 | break; | |
3574 | } | |
3575 | } else { | |
3576 | /* AArch64 registers get mapped to non-secure instance | |
3577 | * of AArch32 */ | |
3578 | add_cpreg_to_hashtable(cpu, r, opaque, state, | |
3579 | ARM_CP_SECSTATE_NS, | |
3580 | crm, opc1, opc2); | |
3581 | } | |
f5a0a5a5 | 3582 | } |
4b6a83fb PM |
3583 | } |
3584 | } | |
3585 | } | |
3586 | } | |
3587 | ||
3588 | void define_arm_cp_regs_with_opaque(ARMCPU *cpu, | |
3589 | const ARMCPRegInfo *regs, void *opaque) | |
3590 | { | |
3591 | /* Define a whole list of registers */ | |
3592 | const ARMCPRegInfo *r; | |
3593 | for (r = regs; r->type != ARM_CP_SENTINEL; r++) { | |
3594 | define_one_arm_cp_reg_with_opaque(cpu, r, opaque); | |
3595 | } | |
3596 | } | |
3597 | ||
60322b39 | 3598 | const ARMCPRegInfo *get_arm_cp_reginfo(GHashTable *cpregs, uint32_t encoded_cp) |
4b6a83fb | 3599 | { |
60322b39 | 3600 | return g_hash_table_lookup(cpregs, &encoded_cp); |
4b6a83fb PM |
3601 | } |
3602 | ||
c4241c7d PM |
3603 | void arm_cp_write_ignore(CPUARMState *env, const ARMCPRegInfo *ri, |
3604 | uint64_t value) | |
4b6a83fb PM |
3605 | { |
3606 | /* Helper coprocessor write function for write-ignore registers */ | |
4b6a83fb PM |
3607 | } |
3608 | ||
c4241c7d | 3609 | uint64_t arm_cp_read_zero(CPUARMState *env, const ARMCPRegInfo *ri) |
4b6a83fb PM |
3610 | { |
3611 | /* Helper coprocessor write function for read-as-zero registers */ | |
4b6a83fb PM |
3612 | return 0; |
3613 | } | |
3614 | ||
f5a0a5a5 PM |
3615 | void arm_cp_reset_ignore(CPUARMState *env, const ARMCPRegInfo *opaque) |
3616 | { | |
3617 | /* Helper coprocessor reset function for do-nothing-on-reset registers */ | |
3618 | } | |
3619 | ||
0ecb72a5 | 3620 | static int bad_mode_switch(CPUARMState *env, int mode) |
37064a8b PM |
3621 | { |
3622 | /* Return true if it is not valid for us to switch to | |
3623 | * this CPU mode (ie all the UNPREDICTABLE cases in | |
3624 | * the ARM ARM CPSRWriteByInstr pseudocode). | |
3625 | */ | |
3626 | switch (mode) { | |
3627 | case ARM_CPU_MODE_USR: | |
3628 | case ARM_CPU_MODE_SYS: | |
3629 | case ARM_CPU_MODE_SVC: | |
3630 | case ARM_CPU_MODE_ABT: | |
3631 | case ARM_CPU_MODE_UND: | |
3632 | case ARM_CPU_MODE_IRQ: | |
3633 | case ARM_CPU_MODE_FIQ: | |
3634 | return 0; | |
027fc527 SF |
3635 | case ARM_CPU_MODE_MON: |
3636 | return !arm_is_secure(env); | |
37064a8b PM |
3637 | default: |
3638 | return 1; | |
3639 | } | |
3640 | } | |
3641 | ||
2f4a40e5 AZ |
3642 | uint32_t cpsr_read(CPUARMState *env) |
3643 | { | |
3644 | int ZF; | |
6fbe23d5 PB |
3645 | ZF = (env->ZF == 0); |
3646 | return env->uncached_cpsr | (env->NF & 0x80000000) | (ZF << 30) | | |
2f4a40e5 AZ |
3647 | (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27) |
3648 | | (env->thumb << 5) | ((env->condexec_bits & 3) << 25) | |
3649 | | ((env->condexec_bits & 0xfc) << 8) | |
af519934 | 3650 | | (env->GE << 16) | (env->daif & CPSR_AIF); |
2f4a40e5 AZ |
3651 | } |
3652 | ||
3653 | void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask) | |
3654 | { | |
6e8801f9 FA |
3655 | uint32_t changed_daif; |
3656 | ||
2f4a40e5 | 3657 | if (mask & CPSR_NZCV) { |
6fbe23d5 PB |
3658 | env->ZF = (~val) & CPSR_Z; |
3659 | env->NF = val; | |
2f4a40e5 AZ |
3660 | env->CF = (val >> 29) & 1; |
3661 | env->VF = (val << 3) & 0x80000000; | |
3662 | } | |
3663 | if (mask & CPSR_Q) | |
3664 | env->QF = ((val & CPSR_Q) != 0); | |
3665 | if (mask & CPSR_T) | |
3666 | env->thumb = ((val & CPSR_T) != 0); | |
3667 | if (mask & CPSR_IT_0_1) { | |
3668 | env->condexec_bits &= ~3; | |
3669 | env->condexec_bits |= (val >> 25) & 3; | |
3670 | } | |
3671 | if (mask & CPSR_IT_2_7) { | |
3672 | env->condexec_bits &= 3; | |
3673 | env->condexec_bits |= (val >> 8) & 0xfc; | |
3674 | } | |
3675 | if (mask & CPSR_GE) { | |
3676 | env->GE = (val >> 16) & 0xf; | |
3677 | } | |
3678 | ||
6e8801f9 FA |
3679 | /* In a V7 implementation that includes the security extensions but does |
3680 | * not include Virtualization Extensions the SCR.FW and SCR.AW bits control | |
3681 | * whether non-secure software is allowed to change the CPSR_F and CPSR_A | |
3682 | * bits respectively. | |
3683 | * | |
3684 | * In a V8 implementation, it is permitted for privileged software to | |
3685 | * change the CPSR A/F bits regardless of the SCR.AW/FW bits. | |
3686 | */ | |
3687 | if (!arm_feature(env, ARM_FEATURE_V8) && | |
3688 | arm_feature(env, ARM_FEATURE_EL3) && | |
3689 | !arm_feature(env, ARM_FEATURE_EL2) && | |
3690 | !arm_is_secure(env)) { | |
3691 | ||
3692 | changed_daif = (env->daif ^ val) & mask; | |
3693 | ||
3694 | if (changed_daif & CPSR_A) { | |
3695 | /* Check to see if we are allowed to change the masking of async | |
3696 | * abort exceptions from a non-secure state. | |
3697 | */ | |
3698 | if (!(env->cp15.scr_el3 & SCR_AW)) { | |
3699 | qemu_log_mask(LOG_GUEST_ERROR, | |
3700 | "Ignoring attempt to switch CPSR_A flag from " | |
3701 | "non-secure world with SCR.AW bit clear\n"); | |
3702 | mask &= ~CPSR_A; | |
3703 | } | |
3704 | } | |
3705 | ||
3706 | if (changed_daif & CPSR_F) { | |
3707 | /* Check to see if we are allowed to change the masking of FIQ | |
3708 | * exceptions from a non-secure state. | |
3709 | */ | |
3710 | if (!(env->cp15.scr_el3 & SCR_FW)) { | |
3711 | qemu_log_mask(LOG_GUEST_ERROR, | |
3712 | "Ignoring attempt to switch CPSR_F flag from " | |
3713 | "non-secure world with SCR.FW bit clear\n"); | |
3714 | mask &= ~CPSR_F; | |
3715 | } | |
3716 | ||
3717 | /* Check whether non-maskable FIQ (NMFI) support is enabled. | |
3718 | * If this bit is set software is not allowed to mask | |
3719 | * FIQs, but is allowed to set CPSR_F to 0. | |
3720 | */ | |
3721 | if ((A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_NMFI) && | |
3722 | (val & CPSR_F)) { | |
3723 | qemu_log_mask(LOG_GUEST_ERROR, | |
3724 | "Ignoring attempt to enable CPSR_F flag " | |
3725 | "(non-maskable FIQ [NMFI] support enabled)\n"); | |
3726 | mask &= ~CPSR_F; | |
3727 | } | |
3728 | } | |
3729 | } | |
3730 | ||
4cc35614 PM |
3731 | env->daif &= ~(CPSR_AIF & mask); |
3732 | env->daif |= val & CPSR_AIF & mask; | |
3733 | ||
2f4a40e5 | 3734 | if ((env->uncached_cpsr ^ val) & mask & CPSR_M) { |
37064a8b PM |
3735 | if (bad_mode_switch(env, val & CPSR_M)) { |
3736 | /* Attempt to switch to an invalid mode: this is UNPREDICTABLE. | |
3737 | * We choose to ignore the attempt and leave the CPSR M field | |
3738 | * untouched. | |
3739 | */ | |
3740 | mask &= ~CPSR_M; | |
3741 | } else { | |
3742 | switch_mode(env, val & CPSR_M); | |
3743 | } | |
2f4a40e5 AZ |
3744 | } |
3745 | mask &= ~CACHED_CPSR_BITS; | |
3746 | env->uncached_cpsr = (env->uncached_cpsr & ~mask) | (val & mask); | |
3747 | } | |
3748 | ||
b26eefb6 PB |
3749 | /* Sign/zero extend */ |
3750 | uint32_t HELPER(sxtb16)(uint32_t x) | |
3751 | { | |
3752 | uint32_t res; | |
3753 | res = (uint16_t)(int8_t)x; | |
3754 | res |= (uint32_t)(int8_t)(x >> 16) << 16; | |
3755 | return res; | |
3756 | } | |
3757 | ||
3758 | uint32_t HELPER(uxtb16)(uint32_t x) | |
3759 | { | |
3760 | uint32_t res; | |
3761 | res = (uint16_t)(uint8_t)x; | |
3762 | res |= (uint32_t)(uint8_t)(x >> 16) << 16; | |
3763 | return res; | |
3764 | } | |
3765 | ||
f51bbbfe PB |
3766 | uint32_t HELPER(clz)(uint32_t x) |
3767 | { | |
7bbcb0af | 3768 | return clz32(x); |
f51bbbfe PB |
3769 | } |
3770 | ||
3670669c PB |
3771 | int32_t HELPER(sdiv)(int32_t num, int32_t den) |
3772 | { | |
3773 | if (den == 0) | |
3774 | return 0; | |
686eeb93 AJ |
3775 | if (num == INT_MIN && den == -1) |
3776 | return INT_MIN; | |
3670669c PB |
3777 | return num / den; |
3778 | } | |
3779 | ||
3780 | uint32_t HELPER(udiv)(uint32_t num, uint32_t den) | |
3781 | { | |
3782 | if (den == 0) | |
3783 | return 0; | |
3784 | return num / den; | |
3785 | } | |
3786 | ||
3787 | uint32_t HELPER(rbit)(uint32_t x) | |
3788 | { | |
3789 | x = ((x & 0xff000000) >> 24) | |
3790 | | ((x & 0x00ff0000) >> 8) | |
3791 | | ((x & 0x0000ff00) << 8) | |
3792 | | ((x & 0x000000ff) << 24); | |
3793 | x = ((x & 0xf0f0f0f0) >> 4) | |
3794 | | ((x & 0x0f0f0f0f) << 4); | |
3795 | x = ((x & 0x88888888) >> 3) | |
3796 | | ((x & 0x44444444) >> 1) | |
3797 | | ((x & 0x22222222) << 1) | |
3798 | | ((x & 0x11111111) << 3); | |
3799 | return x; | |
3800 | } | |
3801 | ||
5fafdf24 | 3802 | #if defined(CONFIG_USER_ONLY) |
b5ff1b31 | 3803 | |
7510454e AF |
3804 | int arm_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw, |
3805 | int mmu_idx) | |
b5ff1b31 | 3806 | { |
7510454e AF |
3807 | ARMCPU *cpu = ARM_CPU(cs); |
3808 | CPUARMState *env = &cpu->env; | |
3809 | ||
abf1172f | 3810 | env->exception.vaddress = address; |
b5ff1b31 | 3811 | if (rw == 2) { |
27103424 | 3812 | cs->exception_index = EXCP_PREFETCH_ABORT; |
b5ff1b31 | 3813 | } else { |
27103424 | 3814 | cs->exception_index = EXCP_DATA_ABORT; |
b5ff1b31 FB |
3815 | } |
3816 | return 1; | |
3817 | } | |
3818 | ||
9ee6e8bb | 3819 | /* These should probably raise undefined insn exceptions. */ |
0ecb72a5 | 3820 | void HELPER(v7m_msr)(CPUARMState *env, uint32_t reg, uint32_t val) |
9ee6e8bb | 3821 | { |
a47dddd7 AF |
3822 | ARMCPU *cpu = arm_env_get_cpu(env); |
3823 | ||
3824 | cpu_abort(CPU(cpu), "v7m_msr %d\n", reg); | |
9ee6e8bb PB |
3825 | } |
3826 | ||
0ecb72a5 | 3827 | uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg) |
9ee6e8bb | 3828 | { |
a47dddd7 AF |
3829 | ARMCPU *cpu = arm_env_get_cpu(env); |
3830 | ||
3831 | cpu_abort(CPU(cpu), "v7m_mrs %d\n", reg); | |
9ee6e8bb PB |
3832 | return 0; |
3833 | } | |
3834 | ||
0ecb72a5 | 3835 | void switch_mode(CPUARMState *env, int mode) |
b5ff1b31 | 3836 | { |
a47dddd7 AF |
3837 | ARMCPU *cpu = arm_env_get_cpu(env); |
3838 | ||
3839 | if (mode != ARM_CPU_MODE_USR) { | |
3840 | cpu_abort(CPU(cpu), "Tried to switch out of user mode\n"); | |
3841 | } | |
b5ff1b31 FB |
3842 | } |
3843 | ||
0ecb72a5 | 3844 | void HELPER(set_r13_banked)(CPUARMState *env, uint32_t mode, uint32_t val) |
9ee6e8bb | 3845 | { |
a47dddd7 AF |
3846 | ARMCPU *cpu = arm_env_get_cpu(env); |
3847 | ||
3848 | cpu_abort(CPU(cpu), "banked r13 write\n"); | |
9ee6e8bb PB |
3849 | } |
3850 | ||
0ecb72a5 | 3851 | uint32_t HELPER(get_r13_banked)(CPUARMState *env, uint32_t mode) |
9ee6e8bb | 3852 | { |
a47dddd7 AF |
3853 | ARMCPU *cpu = arm_env_get_cpu(env); |
3854 | ||
3855 | cpu_abort(CPU(cpu), "banked r13 read\n"); | |
9ee6e8bb PB |
3856 | return 0; |
3857 | } | |
3858 | ||
9e729b57 EI |
3859 | unsigned int arm_excp_target_el(CPUState *cs, unsigned int excp_idx) |
3860 | { | |
3861 | return 1; | |
3862 | } | |
3863 | ||
b5ff1b31 FB |
3864 | #else |
3865 | ||
3866 | /* Map CPU modes onto saved register banks. */ | |
494b00c7 | 3867 | int bank_number(int mode) |
b5ff1b31 FB |
3868 | { |
3869 | switch (mode) { | |
3870 | case ARM_CPU_MODE_USR: | |
3871 | case ARM_CPU_MODE_SYS: | |
3872 | return 0; | |
3873 | case ARM_CPU_MODE_SVC: | |
3874 | return 1; | |
3875 | case ARM_CPU_MODE_ABT: | |
3876 | return 2; | |
3877 | case ARM_CPU_MODE_UND: | |
3878 | return 3; | |
3879 | case ARM_CPU_MODE_IRQ: | |
3880 | return 4; | |
3881 | case ARM_CPU_MODE_FIQ: | |
3882 | return 5; | |
28c9457d EI |
3883 | case ARM_CPU_MODE_HYP: |
3884 | return 6; | |
3885 | case ARM_CPU_MODE_MON: | |
3886 | return 7; | |
b5ff1b31 | 3887 | } |
f5206413 | 3888 | hw_error("bank number requested for bad CPSR mode value 0x%x\n", mode); |
b5ff1b31 FB |
3889 | } |
3890 | ||
0ecb72a5 | 3891 | void switch_mode(CPUARMState *env, int mode) |
b5ff1b31 FB |
3892 | { |
3893 | int old_mode; | |
3894 | int i; | |
3895 | ||
3896 | old_mode = env->uncached_cpsr & CPSR_M; | |
3897 | if (mode == old_mode) | |
3898 | return; | |
3899 | ||
3900 | if (old_mode == ARM_CPU_MODE_FIQ) { | |
3901 | memcpy (env->fiq_regs, env->regs + 8, 5 * sizeof(uint32_t)); | |
8637c67f | 3902 | memcpy (env->regs + 8, env->usr_regs, 5 * sizeof(uint32_t)); |
b5ff1b31 FB |
3903 | } else if (mode == ARM_CPU_MODE_FIQ) { |
3904 | memcpy (env->usr_regs, env->regs + 8, 5 * sizeof(uint32_t)); | |
8637c67f | 3905 | memcpy (env->regs + 8, env->fiq_regs, 5 * sizeof(uint32_t)); |
b5ff1b31 FB |
3906 | } |
3907 | ||
f5206413 | 3908 | i = bank_number(old_mode); |
b5ff1b31 FB |
3909 | env->banked_r13[i] = env->regs[13]; |
3910 | env->banked_r14[i] = env->regs[14]; | |
3911 | env->banked_spsr[i] = env->spsr; | |
3912 | ||
f5206413 | 3913 | i = bank_number(mode); |
b5ff1b31 FB |
3914 | env->regs[13] = env->banked_r13[i]; |
3915 | env->regs[14] = env->banked_r14[i]; | |
3916 | env->spsr = env->banked_spsr[i]; | |
3917 | } | |
3918 | ||
0eeb17d6 GB |
3919 | /* Physical Interrupt Target EL Lookup Table |
3920 | * | |
3921 | * [ From ARM ARM section G1.13.4 (Table G1-15) ] | |
3922 | * | |
3923 | * The below multi-dimensional table is used for looking up the target | |
3924 | * exception level given numerous condition criteria. Specifically, the | |
3925 | * target EL is based on SCR and HCR routing controls as well as the | |
3926 | * currently executing EL and secure state. | |
3927 | * | |
3928 | * Dimensions: | |
3929 | * target_el_table[2][2][2][2][2][4] | |
3930 | * | | | | | +--- Current EL | |
3931 | * | | | | +------ Non-secure(0)/Secure(1) | |
3932 | * | | | +--------- HCR mask override | |
3933 | * | | +------------ SCR exec state control | |
3934 | * | +--------------- SCR mask override | |
3935 | * +------------------ 32-bit(0)/64-bit(1) EL3 | |
3936 | * | |
3937 | * The table values are as such: | |
3938 | * 0-3 = EL0-EL3 | |
3939 | * -1 = Cannot occur | |
3940 | * | |
3941 | * The ARM ARM target EL table includes entries indicating that an "exception | |
3942 | * is not taken". The two cases where this is applicable are: | |
3943 | * 1) An exception is taken from EL3 but the SCR does not have the exception | |
3944 | * routed to EL3. | |
3945 | * 2) An exception is taken from EL2 but the HCR does not have the exception | |
3946 | * routed to EL2. | |
3947 | * In these two cases, the below table contain a target of EL1. This value is | |
3948 | * returned as it is expected that the consumer of the table data will check | |
3949 | * for "target EL >= current EL" to ensure the exception is not taken. | |
3950 | * | |
3951 | * SCR HCR | |
3952 | * 64 EA AMO From | |
3953 | * BIT IRQ IMO Non-secure Secure | |
3954 | * EL3 FIQ RW FMO EL0 EL1 EL2 EL3 EL0 EL1 EL2 EL3 | |
3955 | */ | |
3956 | const int8_t target_el_table[2][2][2][2][2][4] = { | |
3957 | {{{{/* 0 0 0 0 */{ 1, 1, 2, -1 },{ 3, -1, -1, 3 },}, | |
3958 | {/* 0 0 0 1 */{ 2, 2, 2, -1 },{ 3, -1, -1, 3 },},}, | |
3959 | {{/* 0 0 1 0 */{ 1, 1, 2, -1 },{ 3, -1, -1, 3 },}, | |
3960 | {/* 0 0 1 1 */{ 2, 2, 2, -1 },{ 3, -1, -1, 3 },},},}, | |
3961 | {{{/* 0 1 0 0 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },}, | |
3962 | {/* 0 1 0 1 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },},}, | |
3963 | {{/* 0 1 1 0 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },}, | |
3964 | {/* 0 1 1 1 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },},},},}, | |
3965 | {{{{/* 1 0 0 0 */{ 1, 1, 2, -1 },{ 1, 1, -1, 1 },}, | |
3966 | {/* 1 0 0 1 */{ 2, 2, 2, -1 },{ 1, 1, -1, 1 },},}, | |
3967 | {{/* 1 0 1 0 */{ 1, 1, 1, -1 },{ 1, 1, -1, 1 },}, | |
3968 | {/* 1 0 1 1 */{ 2, 2, 2, -1 },{ 1, 1, -1, 1 },},},}, | |
3969 | {{{/* 1 1 0 0 */{ 3, 3, 3, -1 },{ 3, 3, -1, 3 },}, | |
3970 | {/* 1 1 0 1 */{ 3, 3, 3, -1 },{ 3, 3, -1, 3 },},}, | |
3971 | {{/* 1 1 1 0 */{ 3, 3, 3, -1 },{ 3, 3, -1, 3 },}, | |
3972 | {/* 1 1 1 1 */{ 3, 3, 3, -1 },{ 3, 3, -1, 3 },},},},}, | |
3973 | }; | |
3974 | ||
3975 | /* | |
3976 | * Determine the target EL for physical exceptions | |
3977 | */ | |
3978 | static inline uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx, | |
3979 | uint32_t cur_el, bool secure) | |
3980 | { | |
3981 | CPUARMState *env = cs->env_ptr; | |
3982 | int rw = ((env->cp15.scr_el3 & SCR_RW) == SCR_RW); | |
3983 | int scr; | |
3984 | int hcr; | |
3985 | int target_el; | |
3986 | int is64 = arm_el_is_aa64(env, 3); | |
3987 | ||
3988 | switch (excp_idx) { | |
3989 | case EXCP_IRQ: | |
3990 | scr = ((env->cp15.scr_el3 & SCR_IRQ) == SCR_IRQ); | |
3991 | hcr = ((env->cp15.hcr_el2 & HCR_IMO) == HCR_IMO); | |
3992 | break; | |
3993 | case EXCP_FIQ: | |
3994 | scr = ((env->cp15.scr_el3 & SCR_FIQ) == SCR_FIQ); | |
3995 | hcr = ((env->cp15.hcr_el2 & HCR_FMO) == HCR_FMO); | |
3996 | break; | |
3997 | default: | |
3998 | scr = ((env->cp15.scr_el3 & SCR_EA) == SCR_EA); | |
3999 | hcr = ((env->cp15.hcr_el2 & HCR_AMO) == HCR_AMO); | |
4000 | break; | |
4001 | }; | |
4002 | ||
4003 | /* If HCR.TGE is set then HCR is treated as being 1 */ | |
4004 | hcr |= ((env->cp15.hcr_el2 & HCR_TGE) == HCR_TGE); | |
4005 | ||
4006 | /* Perform a table-lookup for the target EL given the current state */ | |
4007 | target_el = target_el_table[is64][scr][rw][hcr][secure][cur_el]; | |
4008 | ||
4009 | assert(target_el > 0); | |
4010 | ||
4011 | return target_el; | |
4012 | } | |
4013 | ||
9e729b57 EI |
4014 | /* |
4015 | * Determine the target EL for a given exception type. | |
4016 | */ | |
4017 | unsigned int arm_excp_target_el(CPUState *cs, unsigned int excp_idx) | |
4018 | { | |
35979d71 EI |
4019 | ARMCPU *cpu = ARM_CPU(cs); |
4020 | CPUARMState *env = &cpu->env; | |
dcbff19b | 4021 | unsigned int cur_el = arm_current_el(env); |
35979d71 | 4022 | unsigned int target_el; |
0eeb17d6 | 4023 | bool secure = arm_is_secure(env); |
35979d71 EI |
4024 | |
4025 | switch (excp_idx) { | |
4026 | case EXCP_HVC: | |
607d98b8 | 4027 | case EXCP_HYP_TRAP: |
35979d71 EI |
4028 | target_el = 2; |
4029 | break; | |
e0d6e6a5 EI |
4030 | case EXCP_SMC: |
4031 | target_el = 3; | |
4032 | break; | |
041c9666 EI |
4033 | case EXCP_FIQ: |
4034 | case EXCP_IRQ: | |
0eeb17d6 | 4035 | target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure); |
041c9666 | 4036 | break; |
136e67e9 EI |
4037 | case EXCP_VIRQ: |
4038 | case EXCP_VFIQ: | |
4039 | target_el = 1; | |
4040 | break; | |
35979d71 EI |
4041 | default: |
4042 | target_el = MAX(cur_el, 1); | |
4043 | break; | |
4044 | } | |
4045 | return target_el; | |
9e729b57 EI |
4046 | } |
4047 | ||
9ee6e8bb PB |
4048 | static void v7m_push(CPUARMState *env, uint32_t val) |
4049 | { | |
70d74660 AF |
4050 | CPUState *cs = CPU(arm_env_get_cpu(env)); |
4051 | ||
9ee6e8bb | 4052 | env->regs[13] -= 4; |
ab1da857 | 4053 | stl_phys(cs->as, env->regs[13], val); |
9ee6e8bb PB |
4054 | } |
4055 | ||
4056 | static uint32_t v7m_pop(CPUARMState *env) | |
4057 | { | |
70d74660 | 4058 | CPUState *cs = CPU(arm_env_get_cpu(env)); |
9ee6e8bb | 4059 | uint32_t val; |
70d74660 | 4060 | |
fdfba1a2 | 4061 | val = ldl_phys(cs->as, env->regs[13]); |
9ee6e8bb PB |
4062 | env->regs[13] += 4; |
4063 | return val; | |
4064 | } | |
4065 | ||
4066 | /* Switch to V7M main or process stack pointer. */ | |
4067 | static void switch_v7m_sp(CPUARMState *env, int process) | |
4068 | { | |
4069 | uint32_t tmp; | |
4070 | if (env->v7m.current_sp != process) { | |
4071 | tmp = env->v7m.other_sp; | |
4072 | env->v7m.other_sp = env->regs[13]; | |
4073 | env->regs[13] = tmp; | |
4074 | env->v7m.current_sp = process; | |
4075 | } | |
4076 | } | |
4077 | ||
4078 | static void do_v7m_exception_exit(CPUARMState *env) | |
4079 | { | |
4080 | uint32_t type; | |
4081 | uint32_t xpsr; | |
4082 | ||
4083 | type = env->regs[15]; | |
4084 | if (env->v7m.exception != 0) | |
983fe826 | 4085 | armv7m_nvic_complete_irq(env->nvic, env->v7m.exception); |
9ee6e8bb PB |
4086 | |
4087 | /* Switch to the target stack. */ | |
4088 | switch_v7m_sp(env, (type & 4) != 0); | |
4089 | /* Pop registers. */ | |
4090 | env->regs[0] = v7m_pop(env); | |
4091 | env->regs[1] = v7m_pop(env); | |
4092 | env->regs[2] = v7m_pop(env); | |
4093 | env->regs[3] = v7m_pop(env); | |
4094 | env->regs[12] = v7m_pop(env); | |
4095 | env->regs[14] = v7m_pop(env); | |
4096 | env->regs[15] = v7m_pop(env); | |
4097 | xpsr = v7m_pop(env); | |
4098 | xpsr_write(env, xpsr, 0xfffffdff); | |
4099 | /* Undo stack alignment. */ | |
4100 | if (xpsr & 0x200) | |
4101 | env->regs[13] |= 4; | |
4102 | /* ??? The exception return type specifies Thread/Handler mode. However | |
4103 | this is also implied by the xPSR value. Not sure what to do | |
4104 | if there is a mismatch. */ | |
4105 | /* ??? Likewise for mismatches between the CONTROL register and the stack | |
4106 | pointer. */ | |
4107 | } | |
4108 | ||
e6f010cc | 4109 | void arm_v7m_cpu_do_interrupt(CPUState *cs) |
9ee6e8bb | 4110 | { |
e6f010cc AF |
4111 | ARMCPU *cpu = ARM_CPU(cs); |
4112 | CPUARMState *env = &cpu->env; | |
9ee6e8bb PB |
4113 | uint32_t xpsr = xpsr_read(env); |
4114 | uint32_t lr; | |
4115 | uint32_t addr; | |
4116 | ||
27103424 | 4117 | arm_log_exception(cs->exception_index); |
3f1beaca | 4118 | |
9ee6e8bb PB |
4119 | lr = 0xfffffff1; |
4120 | if (env->v7m.current_sp) | |
4121 | lr |= 4; | |
4122 | if (env->v7m.exception == 0) | |
4123 | lr |= 8; | |
4124 | ||
4125 | /* For exceptions we just mark as pending on the NVIC, and let that | |
4126 | handle it. */ | |
4127 | /* TODO: Need to escalate if the current priority is higher than the | |
4128 | one we're raising. */ | |
27103424 | 4129 | switch (cs->exception_index) { |
9ee6e8bb | 4130 | case EXCP_UDEF: |
983fe826 | 4131 | armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE); |
9ee6e8bb PB |
4132 | return; |
4133 | case EXCP_SWI: | |
314e2296 | 4134 | /* The PC already points to the next instruction. */ |
983fe826 | 4135 | armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_SVC); |
9ee6e8bb PB |
4136 | return; |
4137 | case EXCP_PREFETCH_ABORT: | |
4138 | case EXCP_DATA_ABORT: | |
abf1172f PM |
4139 | /* TODO: if we implemented the MPU registers, this is where we |
4140 | * should set the MMFAR, etc from exception.fsr and exception.vaddress. | |
4141 | */ | |
983fe826 | 4142 | armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_MEM); |
9ee6e8bb PB |
4143 | return; |
4144 | case EXCP_BKPT: | |
2ad207d4 PB |
4145 | if (semihosting_enabled) { |
4146 | int nr; | |
d31dd73e | 4147 | nr = arm_lduw_code(env, env->regs[15], env->bswap_code) & 0xff; |
2ad207d4 PB |
4148 | if (nr == 0xab) { |
4149 | env->regs[15] += 2; | |
4150 | env->regs[0] = do_arm_semihosting(env); | |
3f1beaca | 4151 | qemu_log_mask(CPU_LOG_INT, "...handled as semihosting call\n"); |
2ad207d4 PB |
4152 | return; |
4153 | } | |
4154 | } | |
983fe826 | 4155 | armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_DEBUG); |
9ee6e8bb PB |
4156 | return; |
4157 | case EXCP_IRQ: | |
983fe826 | 4158 | env->v7m.exception = armv7m_nvic_acknowledge_irq(env->nvic); |
9ee6e8bb PB |
4159 | break; |
4160 | case EXCP_EXCEPTION_EXIT: | |
4161 | do_v7m_exception_exit(env); | |
4162 | return; | |
4163 | default: | |
a47dddd7 | 4164 | cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index); |
9ee6e8bb PB |
4165 | return; /* Never happens. Keep compiler happy. */ |
4166 | } | |
4167 | ||
4168 | /* Align stack pointer. */ | |
4169 | /* ??? Should only do this if Configuration Control Register | |
4170 | STACKALIGN bit is set. */ | |
4171 | if (env->regs[13] & 4) { | |
ab19b0ec | 4172 | env->regs[13] -= 4; |
9ee6e8bb PB |
4173 | xpsr |= 0x200; |
4174 | } | |
6c95676b | 4175 | /* Switch to the handler mode. */ |
9ee6e8bb PB |
4176 | v7m_push(env, xpsr); |
4177 | v7m_push(env, env->regs[15]); | |
4178 | v7m_push(env, env->regs[14]); | |
4179 | v7m_push(env, env->regs[12]); | |
4180 | v7m_push(env, env->regs[3]); | |
4181 | v7m_push(env, env->regs[2]); | |
4182 | v7m_push(env, env->regs[1]); | |
4183 | v7m_push(env, env->regs[0]); | |
4184 | switch_v7m_sp(env, 0); | |
c98d174c PM |
4185 | /* Clear IT bits */ |
4186 | env->condexec_bits = 0; | |
9ee6e8bb | 4187 | env->regs[14] = lr; |
fdfba1a2 | 4188 | addr = ldl_phys(cs->as, env->v7m.vecbase + env->v7m.exception * 4); |
9ee6e8bb PB |
4189 | env->regs[15] = addr & 0xfffffffe; |
4190 | env->thumb = addr & 1; | |
4191 | } | |
4192 | ||
b5ff1b31 | 4193 | /* Handle a CPU exception. */ |
97a8ea5a | 4194 | void arm_cpu_do_interrupt(CPUState *cs) |
b5ff1b31 | 4195 | { |
97a8ea5a AF |
4196 | ARMCPU *cpu = ARM_CPU(cs); |
4197 | CPUARMState *env = &cpu->env; | |
b5ff1b31 FB |
4198 | uint32_t addr; |
4199 | uint32_t mask; | |
4200 | int new_mode; | |
4201 | uint32_t offset; | |
16a906fd | 4202 | uint32_t moe; |
b5ff1b31 | 4203 | |
e6f010cc AF |
4204 | assert(!IS_M(env)); |
4205 | ||
27103424 | 4206 | arm_log_exception(cs->exception_index); |
3f1beaca | 4207 | |
98128601 RH |
4208 | if (arm_is_psci_call(cpu, cs->exception_index)) { |
4209 | arm_handle_psci_call(cpu); | |
4210 | qemu_log_mask(CPU_LOG_INT, "...handled as PSCI call\n"); | |
4211 | return; | |
4212 | } | |
4213 | ||
16a906fd PM |
4214 | /* If this is a debug exception we must update the DBGDSCR.MOE bits */ |
4215 | switch (env->exception.syndrome >> ARM_EL_EC_SHIFT) { | |
4216 | case EC_BREAKPOINT: | |
4217 | case EC_BREAKPOINT_SAME_EL: | |
4218 | moe = 1; | |
4219 | break; | |
4220 | case EC_WATCHPOINT: | |
4221 | case EC_WATCHPOINT_SAME_EL: | |
4222 | moe = 10; | |
4223 | break; | |
4224 | case EC_AA32_BKPT: | |
4225 | moe = 3; | |
4226 | break; | |
4227 | case EC_VECTORCATCH: | |
4228 | moe = 5; | |
4229 | break; | |
4230 | default: | |
4231 | moe = 0; | |
4232 | break; | |
4233 | } | |
4234 | ||
4235 | if (moe) { | |
4236 | env->cp15.mdscr_el1 = deposit64(env->cp15.mdscr_el1, 2, 4, moe); | |
4237 | } | |
4238 | ||
b5ff1b31 | 4239 | /* TODO: Vectored interrupt controller. */ |
27103424 | 4240 | switch (cs->exception_index) { |
b5ff1b31 FB |
4241 | case EXCP_UDEF: |
4242 | new_mode = ARM_CPU_MODE_UND; | |
4243 | addr = 0x04; | |
4244 | mask = CPSR_I; | |
4245 | if (env->thumb) | |
4246 | offset = 2; | |
4247 | else | |
4248 | offset = 4; | |
4249 | break; | |
4250 | case EXCP_SWI: | |
8e71621f PB |
4251 | if (semihosting_enabled) { |
4252 | /* Check for semihosting interrupt. */ | |
4253 | if (env->thumb) { | |
d31dd73e BS |
4254 | mask = arm_lduw_code(env, env->regs[15] - 2, env->bswap_code) |
4255 | & 0xff; | |
8e71621f | 4256 | } else { |
d31dd73e | 4257 | mask = arm_ldl_code(env, env->regs[15] - 4, env->bswap_code) |
d8fd2954 | 4258 | & 0xffffff; |
8e71621f PB |
4259 | } |
4260 | /* Only intercept calls from privileged modes, to provide some | |
4261 | semblance of security. */ | |
4262 | if (((mask == 0x123456 && !env->thumb) | |
4263 | || (mask == 0xab && env->thumb)) | |
4264 | && (env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR) { | |
4265 | env->regs[0] = do_arm_semihosting(env); | |
3f1beaca | 4266 | qemu_log_mask(CPU_LOG_INT, "...handled as semihosting call\n"); |
8e71621f PB |
4267 | return; |
4268 | } | |
4269 | } | |
b5ff1b31 FB |
4270 | new_mode = ARM_CPU_MODE_SVC; |
4271 | addr = 0x08; | |
4272 | mask = CPSR_I; | |
601d70b9 | 4273 | /* The PC already points to the next instruction. */ |
b5ff1b31 FB |
4274 | offset = 0; |
4275 | break; | |
06c949e6 | 4276 | case EXCP_BKPT: |
9ee6e8bb | 4277 | /* See if this is a semihosting syscall. */ |
2ad207d4 | 4278 | if (env->thumb && semihosting_enabled) { |
d31dd73e | 4279 | mask = arm_lduw_code(env, env->regs[15], env->bswap_code) & 0xff; |
9ee6e8bb PB |
4280 | if (mask == 0xab |
4281 | && (env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR) { | |
4282 | env->regs[15] += 2; | |
4283 | env->regs[0] = do_arm_semihosting(env); | |
3f1beaca | 4284 | qemu_log_mask(CPU_LOG_INT, "...handled as semihosting call\n"); |
9ee6e8bb PB |
4285 | return; |
4286 | } | |
4287 | } | |
abf1172f | 4288 | env->exception.fsr = 2; |
9ee6e8bb PB |
4289 | /* Fall through to prefetch abort. */ |
4290 | case EXCP_PREFETCH_ABORT: | |
6cd8a264 | 4291 | env->cp15.ifsr_el2 = env->exception.fsr; |
2f0180c5 EI |
4292 | env->cp15.far_el[1] = deposit64(env->cp15.far_el[1], 32, 32, |
4293 | env->exception.vaddress); | |
3f1beaca | 4294 | qemu_log_mask(CPU_LOG_INT, "...with IFSR 0x%x IFAR 0x%x\n", |
6cd8a264 | 4295 | env->cp15.ifsr_el2, (uint32_t)env->exception.vaddress); |
b5ff1b31 FB |
4296 | new_mode = ARM_CPU_MODE_ABT; |
4297 | addr = 0x0c; | |
4298 | mask = CPSR_A | CPSR_I; | |
4299 | offset = 4; | |
4300 | break; | |
4301 | case EXCP_DATA_ABORT: | |
d81c519c | 4302 | env->cp15.esr_el[1] = env->exception.fsr; |
2f0180c5 EI |
4303 | env->cp15.far_el[1] = deposit64(env->cp15.far_el[1], 0, 32, |
4304 | env->exception.vaddress); | |
3f1beaca | 4305 | qemu_log_mask(CPU_LOG_INT, "...with DFSR 0x%x DFAR 0x%x\n", |
d81c519c | 4306 | (uint32_t)env->cp15.esr_el[1], |
6cd8a264 | 4307 | (uint32_t)env->exception.vaddress); |
b5ff1b31 FB |
4308 | new_mode = ARM_CPU_MODE_ABT; |
4309 | addr = 0x10; | |
4310 | mask = CPSR_A | CPSR_I; | |
4311 | offset = 8; | |
4312 | break; | |
4313 | case EXCP_IRQ: | |
4314 | new_mode = ARM_CPU_MODE_IRQ; | |
4315 | addr = 0x18; | |
4316 | /* Disable IRQ and imprecise data aborts. */ | |
4317 | mask = CPSR_A | CPSR_I; | |
4318 | offset = 4; | |
de38d23b FA |
4319 | if (env->cp15.scr_el3 & SCR_IRQ) { |
4320 | /* IRQ routed to monitor mode */ | |
4321 | new_mode = ARM_CPU_MODE_MON; | |
4322 | mask |= CPSR_F; | |
4323 | } | |
b5ff1b31 FB |
4324 | break; |
4325 | case EXCP_FIQ: | |
4326 | new_mode = ARM_CPU_MODE_FIQ; | |
4327 | addr = 0x1c; | |
4328 | /* Disable FIQ, IRQ and imprecise data aborts. */ | |
4329 | mask = CPSR_A | CPSR_I | CPSR_F; | |
de38d23b FA |
4330 | if (env->cp15.scr_el3 & SCR_FIQ) { |
4331 | /* FIQ routed to monitor mode */ | |
4332 | new_mode = ARM_CPU_MODE_MON; | |
4333 | } | |
b5ff1b31 FB |
4334 | offset = 4; |
4335 | break; | |
dbe9d163 FA |
4336 | case EXCP_SMC: |
4337 | new_mode = ARM_CPU_MODE_MON; | |
4338 | addr = 0x08; | |
4339 | mask = CPSR_A | CPSR_I | CPSR_F; | |
4340 | offset = 0; | |
4341 | break; | |
b5ff1b31 | 4342 | default: |
a47dddd7 | 4343 | cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index); |
b5ff1b31 FB |
4344 | return; /* Never happens. Keep compiler happy. */ |
4345 | } | |
e89e51a1 FA |
4346 | |
4347 | if (new_mode == ARM_CPU_MODE_MON) { | |
4348 | addr += env->cp15.mvbar; | |
137feaa9 | 4349 | } else if (A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_V) { |
e89e51a1 | 4350 | /* High vectors. When enabled, base address cannot be remapped. */ |
b5ff1b31 | 4351 | addr += 0xffff0000; |
8641136c NR |
4352 | } else { |
4353 | /* ARM v7 architectures provide a vector base address register to remap | |
4354 | * the interrupt vector table. | |
e89e51a1 | 4355 | * This register is only followed in non-monitor mode, and is banked. |
8641136c NR |
4356 | * Note: only bits 31:5 are valid. |
4357 | */ | |
68fdb6c5 | 4358 | addr += env->cp15.vbar_el[1]; |
b5ff1b31 | 4359 | } |
dbe9d163 FA |
4360 | |
4361 | if ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_MON) { | |
4362 | env->cp15.scr_el3 &= ~SCR_NS; | |
4363 | } | |
4364 | ||
b5ff1b31 | 4365 | switch_mode (env, new_mode); |
662cefb7 PM |
4366 | /* For exceptions taken to AArch32 we must clear the SS bit in both |
4367 | * PSTATE and in the old-state value we save to SPSR_<mode>, so zero it now. | |
4368 | */ | |
4369 | env->uncached_cpsr &= ~PSTATE_SS; | |
b5ff1b31 | 4370 | env->spsr = cpsr_read(env); |
9ee6e8bb PB |
4371 | /* Clear IT bits. */ |
4372 | env->condexec_bits = 0; | |
30a8cac1 | 4373 | /* Switch to the new mode, and to the correct instruction set. */ |
6d7e6326 | 4374 | env->uncached_cpsr = (env->uncached_cpsr & ~CPSR_M) | new_mode; |
4cc35614 | 4375 | env->daif |= mask; |
be5e7a76 DES |
4376 | /* this is a lie, as the was no c1_sys on V4T/V5, but who cares |
4377 | * and we should just guard the thumb mode on V4 */ | |
4378 | if (arm_feature(env, ARM_FEATURE_V4T)) { | |
137feaa9 | 4379 | env->thumb = (A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_TE) != 0; |
be5e7a76 | 4380 | } |
b5ff1b31 FB |
4381 | env->regs[14] = env->regs[15] + offset; |
4382 | env->regs[15] = addr; | |
259186a7 | 4383 | cs->interrupt_request |= CPU_INTERRUPT_EXITTB; |
b5ff1b31 FB |
4384 | } |
4385 | ||
4386 | /* Check section/page access permissions. | |
4387 | Returns the page protection flags, or zero if the access is not | |
4388 | permitted. */ | |
0ecb72a5 | 4389 | static inline int check_ap(CPUARMState *env, int ap, int domain_prot, |
dd4ebc2e | 4390 | int access_type, int is_user) |
b5ff1b31 | 4391 | { |
9ee6e8bb PB |
4392 | int prot_ro; |
4393 | ||
dd4ebc2e | 4394 | if (domain_prot == 3) { |
b5ff1b31 | 4395 | return PAGE_READ | PAGE_WRITE; |
dd4ebc2e | 4396 | } |
b5ff1b31 | 4397 | |
9ee6e8bb PB |
4398 | if (access_type == 1) |
4399 | prot_ro = 0; | |
4400 | else | |
4401 | prot_ro = PAGE_READ; | |
4402 | ||
b5ff1b31 FB |
4403 | switch (ap) { |
4404 | case 0: | |
99f678a6 PM |
4405 | if (arm_feature(env, ARM_FEATURE_V7)) { |
4406 | return 0; | |
4407 | } | |
78600320 | 4408 | if (access_type == 1) |
b5ff1b31 | 4409 | return 0; |
137feaa9 | 4410 | switch (A32_BANKED_CURRENT_REG_GET(env, sctlr) & (SCTLR_S | SCTLR_R)) { |
76e3e1bc | 4411 | case SCTLR_S: |
b5ff1b31 | 4412 | return is_user ? 0 : PAGE_READ; |
76e3e1bc | 4413 | case SCTLR_R: |
b5ff1b31 FB |
4414 | return PAGE_READ; |
4415 | default: | |
4416 | return 0; | |
4417 | } | |
4418 | case 1: | |
4419 | return is_user ? 0 : PAGE_READ | PAGE_WRITE; | |
4420 | case 2: | |
4421 | if (is_user) | |
9ee6e8bb | 4422 | return prot_ro; |
b5ff1b31 FB |
4423 | else |
4424 | return PAGE_READ | PAGE_WRITE; | |
4425 | case 3: | |
4426 | return PAGE_READ | PAGE_WRITE; | |
d4934d18 | 4427 | case 4: /* Reserved. */ |
9ee6e8bb PB |
4428 | return 0; |
4429 | case 5: | |
4430 | return is_user ? 0 : prot_ro; | |
4431 | case 6: | |
4432 | return prot_ro; | |
d4934d18 | 4433 | case 7: |
0ab06d83 | 4434 | if (!arm_feature (env, ARM_FEATURE_V6K)) |
d4934d18 PB |
4435 | return 0; |
4436 | return prot_ro; | |
b5ff1b31 FB |
4437 | default: |
4438 | abort(); | |
4439 | } | |
4440 | } | |
4441 | ||
e389be16 FA |
4442 | static bool get_level1_table_address(CPUARMState *env, uint32_t *table, |
4443 | uint32_t address) | |
b2fa1797 | 4444 | { |
e389be16 FA |
4445 | if (address & env->cp15.c2_mask) { |
4446 | if ((env->cp15.c2_control & TTBCR_PD1)) { | |
4447 | /* Translation table walk disabled for TTBR1 */ | |
4448 | return false; | |
4449 | } | |
4450 | *table = env->cp15.ttbr1_el1 & 0xffffc000; | |
4451 | } else { | |
4452 | if ((env->cp15.c2_control & TTBCR_PD0)) { | |
4453 | /* Translation table walk disabled for TTBR0 */ | |
4454 | return false; | |
4455 | } | |
4456 | *table = env->cp15.ttbr0_el1 & env->cp15.c2_base_mask; | |
4457 | } | |
4458 | *table |= (address >> 18) & 0x3ffc; | |
4459 | return true; | |
b2fa1797 PB |
4460 | } |
4461 | ||
0ecb72a5 | 4462 | static int get_phys_addr_v5(CPUARMState *env, uint32_t address, int access_type, |
a8170e5e | 4463 | int is_user, hwaddr *phys_ptr, |
77a71dd1 | 4464 | int *prot, target_ulong *page_size) |
b5ff1b31 | 4465 | { |
70d74660 | 4466 | CPUState *cs = CPU(arm_env_get_cpu(env)); |
b5ff1b31 FB |
4467 | int code; |
4468 | uint32_t table; | |
4469 | uint32_t desc; | |
4470 | int type; | |
4471 | int ap; | |
e389be16 | 4472 | int domain = 0; |
dd4ebc2e | 4473 | int domain_prot; |
a8170e5e | 4474 | hwaddr phys_addr; |
b5ff1b31 | 4475 | |
9ee6e8bb PB |
4476 | /* Pagetable walk. */ |
4477 | /* Lookup l1 descriptor. */ | |
e389be16 FA |
4478 | if (!get_level1_table_address(env, &table, address)) { |
4479 | /* Section translation fault if page walk is disabled by PD0 or PD1 */ | |
4480 | code = 5; | |
4481 | goto do_fault; | |
4482 | } | |
fdfba1a2 | 4483 | desc = ldl_phys(cs->as, table); |
9ee6e8bb | 4484 | type = (desc & 3); |
dd4ebc2e JCD |
4485 | domain = (desc >> 5) & 0x0f; |
4486 | domain_prot = (env->cp15.c3 >> (domain * 2)) & 3; | |
9ee6e8bb | 4487 | if (type == 0) { |
601d70b9 | 4488 | /* Section translation fault. */ |
9ee6e8bb PB |
4489 | code = 5; |
4490 | goto do_fault; | |
4491 | } | |
dd4ebc2e | 4492 | if (domain_prot == 0 || domain_prot == 2) { |
9ee6e8bb PB |
4493 | if (type == 2) |
4494 | code = 9; /* Section domain fault. */ | |
4495 | else | |
4496 | code = 11; /* Page domain fault. */ | |
4497 | goto do_fault; | |
4498 | } | |
4499 | if (type == 2) { | |
4500 | /* 1Mb section. */ | |
4501 | phys_addr = (desc & 0xfff00000) | (address & 0x000fffff); | |
4502 | ap = (desc >> 10) & 3; | |
4503 | code = 13; | |
d4c430a8 | 4504 | *page_size = 1024 * 1024; |
9ee6e8bb PB |
4505 | } else { |
4506 | /* Lookup l2 entry. */ | |
4507 | if (type == 1) { | |
4508 | /* Coarse pagetable. */ | |
4509 | table = (desc & 0xfffffc00) | ((address >> 10) & 0x3fc); | |
4510 | } else { | |
4511 | /* Fine pagetable. */ | |
4512 | table = (desc & 0xfffff000) | ((address >> 8) & 0xffc); | |
4513 | } | |
fdfba1a2 | 4514 | desc = ldl_phys(cs->as, table); |
9ee6e8bb PB |
4515 | switch (desc & 3) { |
4516 | case 0: /* Page translation fault. */ | |
4517 | code = 7; | |
4518 | goto do_fault; | |
4519 | case 1: /* 64k page. */ | |
4520 | phys_addr = (desc & 0xffff0000) | (address & 0xffff); | |
4521 | ap = (desc >> (4 + ((address >> 13) & 6))) & 3; | |
d4c430a8 | 4522 | *page_size = 0x10000; |
ce819861 | 4523 | break; |
9ee6e8bb PB |
4524 | case 2: /* 4k page. */ |
4525 | phys_addr = (desc & 0xfffff000) | (address & 0xfff); | |
c10f7fc3 | 4526 | ap = (desc >> (4 + ((address >> 9) & 6))) & 3; |
d4c430a8 | 4527 | *page_size = 0x1000; |
ce819861 | 4528 | break; |
9ee6e8bb PB |
4529 | case 3: /* 1k page. */ |
4530 | if (type == 1) { | |
4531 | if (arm_feature(env, ARM_FEATURE_XSCALE)) { | |
4532 | phys_addr = (desc & 0xfffff000) | (address & 0xfff); | |
4533 | } else { | |
4534 | /* Page translation fault. */ | |
4535 | code = 7; | |
4536 | goto do_fault; | |
4537 | } | |
4538 | } else { | |
4539 | phys_addr = (desc & 0xfffffc00) | (address & 0x3ff); | |
4540 | } | |
4541 | ap = (desc >> 4) & 3; | |
d4c430a8 | 4542 | *page_size = 0x400; |
ce819861 PB |
4543 | break; |
4544 | default: | |
9ee6e8bb PB |
4545 | /* Never happens, but compiler isn't smart enough to tell. */ |
4546 | abort(); | |
ce819861 | 4547 | } |
9ee6e8bb PB |
4548 | code = 15; |
4549 | } | |
dd4ebc2e | 4550 | *prot = check_ap(env, ap, domain_prot, access_type, is_user); |
9ee6e8bb PB |
4551 | if (!*prot) { |
4552 | /* Access permission fault. */ | |
4553 | goto do_fault; | |
4554 | } | |
3ad493fc | 4555 | *prot |= PAGE_EXEC; |
9ee6e8bb PB |
4556 | *phys_ptr = phys_addr; |
4557 | return 0; | |
4558 | do_fault: | |
4559 | return code | (domain << 4); | |
4560 | } | |
4561 | ||
0ecb72a5 | 4562 | static int get_phys_addr_v6(CPUARMState *env, uint32_t address, int access_type, |
a8170e5e | 4563 | int is_user, hwaddr *phys_ptr, |
77a71dd1 | 4564 | int *prot, target_ulong *page_size) |
9ee6e8bb | 4565 | { |
70d74660 | 4566 | CPUState *cs = CPU(arm_env_get_cpu(env)); |
9ee6e8bb PB |
4567 | int code; |
4568 | uint32_t table; | |
4569 | uint32_t desc; | |
4570 | uint32_t xn; | |
de9b05b8 | 4571 | uint32_t pxn = 0; |
9ee6e8bb PB |
4572 | int type; |
4573 | int ap; | |
de9b05b8 | 4574 | int domain = 0; |
dd4ebc2e | 4575 | int domain_prot; |
a8170e5e | 4576 | hwaddr phys_addr; |
9ee6e8bb PB |
4577 | |
4578 | /* Pagetable walk. */ | |
4579 | /* Lookup l1 descriptor. */ | |
e389be16 FA |
4580 | if (!get_level1_table_address(env, &table, address)) { |
4581 | /* Section translation fault if page walk is disabled by PD0 or PD1 */ | |
4582 | code = 5; | |
4583 | goto do_fault; | |
4584 | } | |
fdfba1a2 | 4585 | desc = ldl_phys(cs->as, table); |
9ee6e8bb | 4586 | type = (desc & 3); |
de9b05b8 PM |
4587 | if (type == 0 || (type == 3 && !arm_feature(env, ARM_FEATURE_PXN))) { |
4588 | /* Section translation fault, or attempt to use the encoding | |
4589 | * which is Reserved on implementations without PXN. | |
4590 | */ | |
9ee6e8bb | 4591 | code = 5; |
9ee6e8bb | 4592 | goto do_fault; |
de9b05b8 PM |
4593 | } |
4594 | if ((type == 1) || !(desc & (1 << 18))) { | |
4595 | /* Page or Section. */ | |
dd4ebc2e | 4596 | domain = (desc >> 5) & 0x0f; |
9ee6e8bb | 4597 | } |
dd4ebc2e JCD |
4598 | domain_prot = (env->cp15.c3 >> (domain * 2)) & 3; |
4599 | if (domain_prot == 0 || domain_prot == 2) { | |
de9b05b8 | 4600 | if (type != 1) { |
9ee6e8bb | 4601 | code = 9; /* Section domain fault. */ |
de9b05b8 | 4602 | } else { |
9ee6e8bb | 4603 | code = 11; /* Page domain fault. */ |
de9b05b8 | 4604 | } |
9ee6e8bb PB |
4605 | goto do_fault; |
4606 | } | |
de9b05b8 | 4607 | if (type != 1) { |
9ee6e8bb PB |
4608 | if (desc & (1 << 18)) { |
4609 | /* Supersection. */ | |
4610 | phys_addr = (desc & 0xff000000) | (address & 0x00ffffff); | |
d4c430a8 | 4611 | *page_size = 0x1000000; |
b5ff1b31 | 4612 | } else { |
9ee6e8bb PB |
4613 | /* Section. */ |
4614 | phys_addr = (desc & 0xfff00000) | (address & 0x000fffff); | |
d4c430a8 | 4615 | *page_size = 0x100000; |
b5ff1b31 | 4616 | } |
9ee6e8bb PB |
4617 | ap = ((desc >> 10) & 3) | ((desc >> 13) & 4); |
4618 | xn = desc & (1 << 4); | |
de9b05b8 | 4619 | pxn = desc & 1; |
9ee6e8bb PB |
4620 | code = 13; |
4621 | } else { | |
de9b05b8 PM |
4622 | if (arm_feature(env, ARM_FEATURE_PXN)) { |
4623 | pxn = (desc >> 2) & 1; | |
4624 | } | |
9ee6e8bb PB |
4625 | /* Lookup l2 entry. */ |
4626 | table = (desc & 0xfffffc00) | ((address >> 10) & 0x3fc); | |
fdfba1a2 | 4627 | desc = ldl_phys(cs->as, table); |
9ee6e8bb PB |
4628 | ap = ((desc >> 4) & 3) | ((desc >> 7) & 4); |
4629 | switch (desc & 3) { | |
4630 | case 0: /* Page translation fault. */ | |
4631 | code = 7; | |
b5ff1b31 | 4632 | goto do_fault; |
9ee6e8bb PB |
4633 | case 1: /* 64k page. */ |
4634 | phys_addr = (desc & 0xffff0000) | (address & 0xffff); | |
4635 | xn = desc & (1 << 15); | |
d4c430a8 | 4636 | *page_size = 0x10000; |
9ee6e8bb PB |
4637 | break; |
4638 | case 2: case 3: /* 4k page. */ | |
4639 | phys_addr = (desc & 0xfffff000) | (address & 0xfff); | |
4640 | xn = desc & 1; | |
d4c430a8 | 4641 | *page_size = 0x1000; |
9ee6e8bb PB |
4642 | break; |
4643 | default: | |
4644 | /* Never happens, but compiler isn't smart enough to tell. */ | |
4645 | abort(); | |
b5ff1b31 | 4646 | } |
9ee6e8bb PB |
4647 | code = 15; |
4648 | } | |
dd4ebc2e | 4649 | if (domain_prot == 3) { |
c0034328 JR |
4650 | *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; |
4651 | } else { | |
de9b05b8 PM |
4652 | if (pxn && !is_user) { |
4653 | xn = 1; | |
4654 | } | |
c0034328 JR |
4655 | if (xn && access_type == 2) |
4656 | goto do_fault; | |
9ee6e8bb | 4657 | |
c0034328 | 4658 | /* The simplified model uses AP[0] as an access control bit. */ |
137feaa9 FA |
4659 | if ((A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_AFE) |
4660 | && (ap & 1) == 0) { | |
c0034328 JR |
4661 | /* Access flag fault. */ |
4662 | code = (code == 15) ? 6 : 3; | |
4663 | goto do_fault; | |
4664 | } | |
dd4ebc2e | 4665 | *prot = check_ap(env, ap, domain_prot, access_type, is_user); |
c0034328 JR |
4666 | if (!*prot) { |
4667 | /* Access permission fault. */ | |
4668 | goto do_fault; | |
4669 | } | |
4670 | if (!xn) { | |
4671 | *prot |= PAGE_EXEC; | |
4672 | } | |
3ad493fc | 4673 | } |
9ee6e8bb | 4674 | *phys_ptr = phys_addr; |
b5ff1b31 FB |
4675 | return 0; |
4676 | do_fault: | |
4677 | return code | (domain << 4); | |
4678 | } | |
4679 | ||
3dde962f PM |
4680 | /* Fault type for long-descriptor MMU fault reporting; this corresponds |
4681 | * to bits [5..2] in the STATUS field in long-format DFSR/IFSR. | |
4682 | */ | |
4683 | typedef enum { | |
4684 | translation_fault = 1, | |
4685 | access_fault = 2, | |
4686 | permission_fault = 3, | |
4687 | } MMUFaultType; | |
4688 | ||
2c8dd318 | 4689 | static int get_phys_addr_lpae(CPUARMState *env, target_ulong address, |
3dde962f | 4690 | int access_type, int is_user, |
a8170e5e | 4691 | hwaddr *phys_ptr, int *prot, |
3dde962f PM |
4692 | target_ulong *page_size_ptr) |
4693 | { | |
70d74660 | 4694 | CPUState *cs = CPU(arm_env_get_cpu(env)); |
3dde962f PM |
4695 | /* Read an LPAE long-descriptor translation table. */ |
4696 | MMUFaultType fault_type = translation_fault; | |
4697 | uint32_t level = 1; | |
4698 | uint32_t epd; | |
2c8dd318 RH |
4699 | int32_t tsz; |
4700 | uint32_t tg; | |
3dde962f PM |
4701 | uint64_t ttbr; |
4702 | int ttbr_select; | |
2c8dd318 | 4703 | hwaddr descaddr, descmask; |
3dde962f PM |
4704 | uint32_t tableattrs; |
4705 | target_ulong page_size; | |
4706 | uint32_t attrs; | |
2c8dd318 RH |
4707 | int32_t granule_sz = 9; |
4708 | int32_t va_size = 32; | |
4709 | int32_t tbi = 0; | |
4710 | ||
4711 | if (arm_el_is_aa64(env, 1)) { | |
4712 | va_size = 64; | |
4713 | if (extract64(address, 55, 1)) | |
4714 | tbi = extract64(env->cp15.c2_control, 38, 1); | |
4715 | else | |
4716 | tbi = extract64(env->cp15.c2_control, 37, 1); | |
4717 | tbi *= 8; | |
4718 | } | |
3dde962f PM |
4719 | |
4720 | /* Determine whether this address is in the region controlled by | |
4721 | * TTBR0 or TTBR1 (or if it is in neither region and should fault). | |
4722 | * This is a Non-secure PL0/1 stage 1 translation, so controlled by | |
4723 | * TTBCR/TTBR0/TTBR1 in accordance with ARM ARM DDI0406C table B-32: | |
4724 | */ | |
2c8dd318 RH |
4725 | uint32_t t0sz = extract32(env->cp15.c2_control, 0, 6); |
4726 | if (arm_el_is_aa64(env, 1)) { | |
4727 | t0sz = MIN(t0sz, 39); | |
4728 | t0sz = MAX(t0sz, 16); | |
4729 | } | |
4730 | uint32_t t1sz = extract32(env->cp15.c2_control, 16, 6); | |
4731 | if (arm_el_is_aa64(env, 1)) { | |
4732 | t1sz = MIN(t1sz, 39); | |
4733 | t1sz = MAX(t1sz, 16); | |
4734 | } | |
4735 | if (t0sz && !extract64(address, va_size - t0sz, t0sz - tbi)) { | |
3dde962f PM |
4736 | /* there is a ttbr0 region and we are in it (high bits all zero) */ |
4737 | ttbr_select = 0; | |
2c8dd318 | 4738 | } else if (t1sz && !extract64(~address, va_size - t1sz, t1sz - tbi)) { |
3dde962f PM |
4739 | /* there is a ttbr1 region and we are in it (high bits all one) */ |
4740 | ttbr_select = 1; | |
4741 | } else if (!t0sz) { | |
4742 | /* ttbr0 region is "everything not in the ttbr1 region" */ | |
4743 | ttbr_select = 0; | |
4744 | } else if (!t1sz) { | |
4745 | /* ttbr1 region is "everything not in the ttbr0 region" */ | |
4746 | ttbr_select = 1; | |
4747 | } else { | |
4748 | /* in the gap between the two regions, this is a Translation fault */ | |
4749 | fault_type = translation_fault; | |
4750 | goto do_fault; | |
4751 | } | |
4752 | ||
4753 | /* Note that QEMU ignores shareability and cacheability attributes, | |
4754 | * so we don't need to do anything with the SH, ORGN, IRGN fields | |
4755 | * in the TTBCR. Similarly, TTBCR:A1 selects whether we get the | |
4756 | * ASID from TTBR0 or TTBR1, but QEMU's TLB doesn't currently | |
4757 | * implement any ASID-like capability so we can ignore it (instead | |
4758 | * we will always flush the TLB any time the ASID is changed). | |
4759 | */ | |
4760 | if (ttbr_select == 0) { | |
327ed10f | 4761 | ttbr = env->cp15.ttbr0_el1; |
3dde962f PM |
4762 | epd = extract32(env->cp15.c2_control, 7, 1); |
4763 | tsz = t0sz; | |
2c8dd318 RH |
4764 | |
4765 | tg = extract32(env->cp15.c2_control, 14, 2); | |
4766 | if (tg == 1) { /* 64KB pages */ | |
4767 | granule_sz = 13; | |
4768 | } | |
4769 | if (tg == 2) { /* 16KB pages */ | |
4770 | granule_sz = 11; | |
4771 | } | |
3dde962f | 4772 | } else { |
327ed10f | 4773 | ttbr = env->cp15.ttbr1_el1; |
3dde962f PM |
4774 | epd = extract32(env->cp15.c2_control, 23, 1); |
4775 | tsz = t1sz; | |
2c8dd318 RH |
4776 | |
4777 | tg = extract32(env->cp15.c2_control, 30, 2); | |
4778 | if (tg == 3) { /* 64KB pages */ | |
4779 | granule_sz = 13; | |
4780 | } | |
4781 | if (tg == 1) { /* 16KB pages */ | |
4782 | granule_sz = 11; | |
4783 | } | |
3dde962f PM |
4784 | } |
4785 | ||
4786 | if (epd) { | |
4787 | /* Translation table walk disabled => Translation fault on TLB miss */ | |
4788 | goto do_fault; | |
4789 | } | |
4790 | ||
d6be29e3 PM |
4791 | /* The starting level depends on the virtual address size (which can be |
4792 | * up to 48 bits) and the translation granule size. It indicates the number | |
4793 | * of strides (granule_sz bits at a time) needed to consume the bits | |
4794 | * of the input address. In the pseudocode this is: | |
4795 | * level = 4 - RoundUp((inputsize - grainsize) / stride) | |
4796 | * where their 'inputsize' is our 'va_size - tsz', 'grainsize' is | |
4797 | * our 'granule_sz + 3' and 'stride' is our 'granule_sz'. | |
4798 | * Applying the usual "rounded up m/n is (m+n-1)/n" and simplifying: | |
4799 | * = 4 - (va_size - tsz - granule_sz - 3 + granule_sz - 1) / granule_sz | |
4800 | * = 4 - (va_size - tsz - 4) / granule_sz; | |
3dde962f | 4801 | */ |
d6be29e3 | 4802 | level = 4 - (va_size - tsz - 4) / granule_sz; |
3dde962f PM |
4803 | |
4804 | /* Clear the vaddr bits which aren't part of the within-region address, | |
4805 | * so that we don't have to special case things when calculating the | |
4806 | * first descriptor address. | |
4807 | */ | |
2c8dd318 RH |
4808 | if (tsz) { |
4809 | address &= (1ULL << (va_size - tsz)) - 1; | |
4810 | } | |
4811 | ||
4812 | descmask = (1ULL << (granule_sz + 3)) - 1; | |
3dde962f PM |
4813 | |
4814 | /* Now we can extract the actual base address from the TTBR */ | |
2c8dd318 RH |
4815 | descaddr = extract64(ttbr, 0, 48); |
4816 | descaddr &= ~((1ULL << (va_size - tsz - (granule_sz * (4 - level)))) - 1); | |
3dde962f PM |
4817 | |
4818 | tableattrs = 0; | |
4819 | for (;;) { | |
4820 | uint64_t descriptor; | |
4821 | ||
2c8dd318 RH |
4822 | descaddr |= (address >> (granule_sz * (4 - level))) & descmask; |
4823 | descaddr &= ~7ULL; | |
2c17449b | 4824 | descriptor = ldq_phys(cs->as, descaddr); |
3dde962f PM |
4825 | if (!(descriptor & 1) || |
4826 | (!(descriptor & 2) && (level == 3))) { | |
4827 | /* Invalid, or the Reserved level 3 encoding */ | |
4828 | goto do_fault; | |
4829 | } | |
4830 | descaddr = descriptor & 0xfffffff000ULL; | |
4831 | ||
4832 | if ((descriptor & 2) && (level < 3)) { | |
4833 | /* Table entry. The top five bits are attributes which may | |
4834 | * propagate down through lower levels of the table (and | |
4835 | * which are all arranged so that 0 means "no effect", so | |
4836 | * we can gather them up by ORing in the bits at each level). | |
4837 | */ | |
4838 | tableattrs |= extract64(descriptor, 59, 5); | |
4839 | level++; | |
4840 | continue; | |
4841 | } | |
4842 | /* Block entry at level 1 or 2, or page entry at level 3. | |
4843 | * These are basically the same thing, although the number | |
4844 | * of bits we pull in from the vaddr varies. | |
4845 | */ | |
5661ae6b | 4846 | page_size = (1ULL << ((granule_sz * (4 - level)) + 3)); |
3dde962f PM |
4847 | descaddr |= (address & (page_size - 1)); |
4848 | /* Extract attributes from the descriptor and merge with table attrs */ | |
d615efac IC |
4849 | attrs = extract64(descriptor, 2, 10) |
4850 | | (extract64(descriptor, 52, 12) << 10); | |
3dde962f PM |
4851 | attrs |= extract32(tableattrs, 0, 2) << 11; /* XN, PXN */ |
4852 | attrs |= extract32(tableattrs, 3, 1) << 5; /* APTable[1] => AP[2] */ | |
4853 | /* The sense of AP[1] vs APTable[0] is reversed, as APTable[0] == 1 | |
4854 | * means "force PL1 access only", which means forcing AP[1] to 0. | |
4855 | */ | |
4856 | if (extract32(tableattrs, 2, 1)) { | |
4857 | attrs &= ~(1 << 4); | |
4858 | } | |
4859 | /* Since we're always in the Non-secure state, NSTable is ignored. */ | |
4860 | break; | |
4861 | } | |
4862 | /* Here descaddr is the final physical address, and attributes | |
4863 | * are all in attrs. | |
4864 | */ | |
4865 | fault_type = access_fault; | |
4866 | if ((attrs & (1 << 8)) == 0) { | |
4867 | /* Access flag */ | |
4868 | goto do_fault; | |
4869 | } | |
4870 | fault_type = permission_fault; | |
4871 | if (is_user && !(attrs & (1 << 4))) { | |
4872 | /* Unprivileged access not enabled */ | |
4873 | goto do_fault; | |
4874 | } | |
4875 | *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; | |
d615efac IC |
4876 | if ((arm_feature(env, ARM_FEATURE_V8) && is_user && (attrs & (1 << 12))) || |
4877 | (!arm_feature(env, ARM_FEATURE_V8) && (attrs & (1 << 12))) || | |
4878 | (!is_user && (attrs & (1 << 11)))) { | |
4879 | /* XN/UXN or PXN. Since we only implement EL0/EL1 we unconditionally | |
4880 | * treat XN/UXN as UXN for v8. | |
4881 | */ | |
3dde962f PM |
4882 | if (access_type == 2) { |
4883 | goto do_fault; | |
4884 | } | |
4885 | *prot &= ~PAGE_EXEC; | |
4886 | } | |
4887 | if (attrs & (1 << 5)) { | |
4888 | /* Write access forbidden */ | |
4889 | if (access_type == 1) { | |
4890 | goto do_fault; | |
4891 | } | |
4892 | *prot &= ~PAGE_WRITE; | |
4893 | } | |
4894 | ||
4895 | *phys_ptr = descaddr; | |
4896 | *page_size_ptr = page_size; | |
4897 | return 0; | |
4898 | ||
4899 | do_fault: | |
4900 | /* Long-descriptor format IFSR/DFSR value */ | |
4901 | return (1 << 9) | (fault_type << 2) | level; | |
4902 | } | |
4903 | ||
77a71dd1 PM |
4904 | static int get_phys_addr_mpu(CPUARMState *env, uint32_t address, |
4905 | int access_type, int is_user, | |
a8170e5e | 4906 | hwaddr *phys_ptr, int *prot) |
9ee6e8bb PB |
4907 | { |
4908 | int n; | |
4909 | uint32_t mask; | |
4910 | uint32_t base; | |
4911 | ||
4912 | *phys_ptr = address; | |
4913 | for (n = 7; n >= 0; n--) { | |
4914 | base = env->cp15.c6_region[n]; | |
4915 | if ((base & 1) == 0) | |
4916 | continue; | |
4917 | mask = 1 << ((base >> 1) & 0x1f); | |
4918 | /* Keep this shift separate from the above to avoid an | |
4919 | (undefined) << 32. */ | |
4920 | mask = (mask << 1) - 1; | |
4921 | if (((base ^ address) & ~mask) == 0) | |
4922 | break; | |
4923 | } | |
4924 | if (n < 0) | |
4925 | return 2; | |
4926 | ||
4927 | if (access_type == 2) { | |
7e09797c | 4928 | mask = env->cp15.pmsav5_insn_ap; |
9ee6e8bb | 4929 | } else { |
7e09797c | 4930 | mask = env->cp15.pmsav5_data_ap; |
9ee6e8bb PB |
4931 | } |
4932 | mask = (mask >> (n * 4)) & 0xf; | |
4933 | switch (mask) { | |
4934 | case 0: | |
4935 | return 1; | |
4936 | case 1: | |
4937 | if (is_user) | |
4938 | return 1; | |
4939 | *prot = PAGE_READ | PAGE_WRITE; | |
4940 | break; | |
4941 | case 2: | |
4942 | *prot = PAGE_READ; | |
4943 | if (!is_user) | |
4944 | *prot |= PAGE_WRITE; | |
4945 | break; | |
4946 | case 3: | |
4947 | *prot = PAGE_READ | PAGE_WRITE; | |
4948 | break; | |
4949 | case 5: | |
4950 | if (is_user) | |
4951 | return 1; | |
4952 | *prot = PAGE_READ; | |
4953 | break; | |
4954 | case 6: | |
4955 | *prot = PAGE_READ; | |
4956 | break; | |
4957 | default: | |
4958 | /* Bad permission. */ | |
4959 | return 1; | |
4960 | } | |
3ad493fc | 4961 | *prot |= PAGE_EXEC; |
9ee6e8bb PB |
4962 | return 0; |
4963 | } | |
4964 | ||
702a9357 PM |
4965 | /* get_phys_addr - get the physical address for this virtual address |
4966 | * | |
4967 | * Find the physical address corresponding to the given virtual address, | |
4968 | * by doing a translation table walk on MMU based systems or using the | |
4969 | * MPU state on MPU based systems. | |
4970 | * | |
4971 | * Returns 0 if the translation was successful. Otherwise, phys_ptr, | |
4972 | * prot and page_size are not filled in, and the return value provides | |
4973 | * information on why the translation aborted, in the format of a | |
4974 | * DFSR/IFSR fault register, with the following caveats: | |
4975 | * * we honour the short vs long DFSR format differences. | |
4976 | * * the WnR bit is never set (the caller must do this). | |
4977 | * * for MPU based systems we don't bother to return a full FSR format | |
4978 | * value. | |
4979 | * | |
4980 | * @env: CPUARMState | |
4981 | * @address: virtual address to get physical address for | |
4982 | * @access_type: 0 for read, 1 for write, 2 for execute | |
4983 | * @is_user: 0 for privileged access, 1 for user | |
4984 | * @phys_ptr: set to the physical address corresponding to the virtual address | |
4985 | * @prot: set to the permissions for the page containing phys_ptr | |
4986 | * @page_size: set to the size of the page containing phys_ptr | |
4987 | */ | |
2c8dd318 | 4988 | static inline int get_phys_addr(CPUARMState *env, target_ulong address, |
9ee6e8bb | 4989 | int access_type, int is_user, |
a8170e5e | 4990 | hwaddr *phys_ptr, int *prot, |
d4c430a8 | 4991 | target_ulong *page_size) |
9ee6e8bb | 4992 | { |
137feaa9 FA |
4993 | /* This is not entirely correct as get_phys_addr() can also be called |
4994 | * from ats_write() for an address translation of a specific regime. | |
4995 | */ | |
4996 | uint32_t sctlr = A32_BANKED_CURRENT_REG_GET(env, sctlr); | |
4997 | ||
9ee6e8bb PB |
4998 | /* Fast Context Switch Extension. */ |
4999 | if (address < 0x02000000) | |
5000 | address += env->cp15.c13_fcse; | |
5001 | ||
137feaa9 | 5002 | if ((sctlr & SCTLR_M) == 0) { |
9ee6e8bb PB |
5003 | /* MMU/MPU disabled. */ |
5004 | *phys_ptr = address; | |
3ad493fc | 5005 | *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; |
d4c430a8 | 5006 | *page_size = TARGET_PAGE_SIZE; |
9ee6e8bb PB |
5007 | return 0; |
5008 | } else if (arm_feature(env, ARM_FEATURE_MPU)) { | |
d4c430a8 | 5009 | *page_size = TARGET_PAGE_SIZE; |
9ee6e8bb PB |
5010 | return get_phys_addr_mpu(env, address, access_type, is_user, phys_ptr, |
5011 | prot); | |
3dde962f PM |
5012 | } else if (extended_addresses_enabled(env)) { |
5013 | return get_phys_addr_lpae(env, address, access_type, is_user, phys_ptr, | |
5014 | prot, page_size); | |
137feaa9 | 5015 | } else if (sctlr & SCTLR_XP) { |
9ee6e8bb | 5016 | return get_phys_addr_v6(env, address, access_type, is_user, phys_ptr, |
d4c430a8 | 5017 | prot, page_size); |
9ee6e8bb PB |
5018 | } else { |
5019 | return get_phys_addr_v5(env, address, access_type, is_user, phys_ptr, | |
d4c430a8 | 5020 | prot, page_size); |
9ee6e8bb PB |
5021 | } |
5022 | } | |
5023 | ||
7510454e AF |
5024 | int arm_cpu_handle_mmu_fault(CPUState *cs, vaddr address, |
5025 | int access_type, int mmu_idx) | |
b5ff1b31 | 5026 | { |
7510454e AF |
5027 | ARMCPU *cpu = ARM_CPU(cs); |
5028 | CPUARMState *env = &cpu->env; | |
a8170e5e | 5029 | hwaddr phys_addr; |
d4c430a8 | 5030 | target_ulong page_size; |
b5ff1b31 | 5031 | int prot; |
6ebbf390 | 5032 | int ret, is_user; |
00892383 | 5033 | uint32_t syn; |
dcbff19b | 5034 | bool same_el = (arm_current_el(env) != 0); |
b5ff1b31 | 5035 | |
6ebbf390 | 5036 | is_user = mmu_idx == MMU_USER_IDX; |
d4c430a8 PB |
5037 | ret = get_phys_addr(env, address, access_type, is_user, &phys_addr, &prot, |
5038 | &page_size); | |
b5ff1b31 FB |
5039 | if (ret == 0) { |
5040 | /* Map a single [sub]page. */ | |
dcd82c11 AB |
5041 | phys_addr &= TARGET_PAGE_MASK; |
5042 | address &= TARGET_PAGE_MASK; | |
0c591eb0 | 5043 | tlb_set_page(cs, address, phys_addr, prot, mmu_idx, page_size); |
d4c430a8 | 5044 | return 0; |
b5ff1b31 FB |
5045 | } |
5046 | ||
00892383 RH |
5047 | /* AArch64 syndrome does not have an LPAE bit */ |
5048 | syn = ret & ~(1 << 9); | |
5049 | ||
5050 | /* For insn and data aborts we assume there is no instruction syndrome | |
5051 | * information; this is always true for exceptions reported to EL1. | |
5052 | */ | |
b5ff1b31 | 5053 | if (access_type == 2) { |
00892383 | 5054 | syn = syn_insn_abort(same_el, 0, 0, syn); |
27103424 | 5055 | cs->exception_index = EXCP_PREFETCH_ABORT; |
b5ff1b31 | 5056 | } else { |
00892383 | 5057 | syn = syn_data_abort(same_el, 0, 0, 0, access_type == 1, syn); |
abf1172f PM |
5058 | if (access_type == 1 && arm_feature(env, ARM_FEATURE_V6)) { |
5059 | ret |= (1 << 11); | |
5060 | } | |
27103424 | 5061 | cs->exception_index = EXCP_DATA_ABORT; |
b5ff1b31 | 5062 | } |
00892383 RH |
5063 | |
5064 | env->exception.syndrome = syn; | |
abf1172f PM |
5065 | env->exception.vaddress = address; |
5066 | env->exception.fsr = ret; | |
b5ff1b31 FB |
5067 | return 1; |
5068 | } | |
5069 | ||
00b941e5 | 5070 | hwaddr arm_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) |
b5ff1b31 | 5071 | { |
00b941e5 | 5072 | ARMCPU *cpu = ARM_CPU(cs); |
a8170e5e | 5073 | hwaddr phys_addr; |
d4c430a8 | 5074 | target_ulong page_size; |
b5ff1b31 FB |
5075 | int prot; |
5076 | int ret; | |
5077 | ||
00b941e5 | 5078 | ret = get_phys_addr(&cpu->env, addr, 0, 0, &phys_addr, &prot, &page_size); |
b5ff1b31 | 5079 | |
00b941e5 | 5080 | if (ret != 0) { |
b5ff1b31 | 5081 | return -1; |
00b941e5 | 5082 | } |
b5ff1b31 FB |
5083 | |
5084 | return phys_addr; | |
5085 | } | |
5086 | ||
0ecb72a5 | 5087 | void HELPER(set_r13_banked)(CPUARMState *env, uint32_t mode, uint32_t val) |
9ee6e8bb | 5088 | { |
39ea3d4e PM |
5089 | if ((env->uncached_cpsr & CPSR_M) == mode) { |
5090 | env->regs[13] = val; | |
5091 | } else { | |
f5206413 | 5092 | env->banked_r13[bank_number(mode)] = val; |
39ea3d4e | 5093 | } |
9ee6e8bb PB |
5094 | } |
5095 | ||
0ecb72a5 | 5096 | uint32_t HELPER(get_r13_banked)(CPUARMState *env, uint32_t mode) |
9ee6e8bb | 5097 | { |
39ea3d4e PM |
5098 | if ((env->uncached_cpsr & CPSR_M) == mode) { |
5099 | return env->regs[13]; | |
5100 | } else { | |
f5206413 | 5101 | return env->banked_r13[bank_number(mode)]; |
39ea3d4e | 5102 | } |
9ee6e8bb PB |
5103 | } |
5104 | ||
0ecb72a5 | 5105 | uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg) |
9ee6e8bb | 5106 | { |
a47dddd7 AF |
5107 | ARMCPU *cpu = arm_env_get_cpu(env); |
5108 | ||
9ee6e8bb PB |
5109 | switch (reg) { |
5110 | case 0: /* APSR */ | |
5111 | return xpsr_read(env) & 0xf8000000; | |
5112 | case 1: /* IAPSR */ | |
5113 | return xpsr_read(env) & 0xf80001ff; | |
5114 | case 2: /* EAPSR */ | |
5115 | return xpsr_read(env) & 0xff00fc00; | |
5116 | case 3: /* xPSR */ | |
5117 | return xpsr_read(env) & 0xff00fdff; | |
5118 | case 5: /* IPSR */ | |
5119 | return xpsr_read(env) & 0x000001ff; | |
5120 | case 6: /* EPSR */ | |
5121 | return xpsr_read(env) & 0x0700fc00; | |
5122 | case 7: /* IEPSR */ | |
5123 | return xpsr_read(env) & 0x0700edff; | |
5124 | case 8: /* MSP */ | |
5125 | return env->v7m.current_sp ? env->v7m.other_sp : env->regs[13]; | |
5126 | case 9: /* PSP */ | |
5127 | return env->v7m.current_sp ? env->regs[13] : env->v7m.other_sp; | |
5128 | case 16: /* PRIMASK */ | |
4cc35614 | 5129 | return (env->daif & PSTATE_I) != 0; |
82845826 SH |
5130 | case 17: /* BASEPRI */ |
5131 | case 18: /* BASEPRI_MAX */ | |
9ee6e8bb | 5132 | return env->v7m.basepri; |
82845826 | 5133 | case 19: /* FAULTMASK */ |
4cc35614 | 5134 | return (env->daif & PSTATE_F) != 0; |
9ee6e8bb PB |
5135 | case 20: /* CONTROL */ |
5136 | return env->v7m.control; | |
5137 | default: | |
5138 | /* ??? For debugging only. */ | |
a47dddd7 | 5139 | cpu_abort(CPU(cpu), "Unimplemented system register read (%d)\n", reg); |
9ee6e8bb PB |
5140 | return 0; |
5141 | } | |
5142 | } | |
5143 | ||
0ecb72a5 | 5144 | void HELPER(v7m_msr)(CPUARMState *env, uint32_t reg, uint32_t val) |
9ee6e8bb | 5145 | { |
a47dddd7 AF |
5146 | ARMCPU *cpu = arm_env_get_cpu(env); |
5147 | ||
9ee6e8bb PB |
5148 | switch (reg) { |
5149 | case 0: /* APSR */ | |
5150 | xpsr_write(env, val, 0xf8000000); | |
5151 | break; | |
5152 | case 1: /* IAPSR */ | |
5153 | xpsr_write(env, val, 0xf8000000); | |
5154 | break; | |
5155 | case 2: /* EAPSR */ | |
5156 | xpsr_write(env, val, 0xfe00fc00); | |
5157 | break; | |
5158 | case 3: /* xPSR */ | |
5159 | xpsr_write(env, val, 0xfe00fc00); | |
5160 | break; | |
5161 | case 5: /* IPSR */ | |
5162 | /* IPSR bits are readonly. */ | |
5163 | break; | |
5164 | case 6: /* EPSR */ | |
5165 | xpsr_write(env, val, 0x0600fc00); | |
5166 | break; | |
5167 | case 7: /* IEPSR */ | |
5168 | xpsr_write(env, val, 0x0600fc00); | |
5169 | break; | |
5170 | case 8: /* MSP */ | |
5171 | if (env->v7m.current_sp) | |
5172 | env->v7m.other_sp = val; | |
5173 | else | |
5174 | env->regs[13] = val; | |
5175 | break; | |
5176 | case 9: /* PSP */ | |
5177 | if (env->v7m.current_sp) | |
5178 | env->regs[13] = val; | |
5179 | else | |
5180 | env->v7m.other_sp = val; | |
5181 | break; | |
5182 | case 16: /* PRIMASK */ | |
4cc35614 PM |
5183 | if (val & 1) { |
5184 | env->daif |= PSTATE_I; | |
5185 | } else { | |
5186 | env->daif &= ~PSTATE_I; | |
5187 | } | |
9ee6e8bb | 5188 | break; |
82845826 | 5189 | case 17: /* BASEPRI */ |
9ee6e8bb PB |
5190 | env->v7m.basepri = val & 0xff; |
5191 | break; | |
82845826 | 5192 | case 18: /* BASEPRI_MAX */ |
9ee6e8bb PB |
5193 | val &= 0xff; |
5194 | if (val != 0 && (val < env->v7m.basepri || env->v7m.basepri == 0)) | |
5195 | env->v7m.basepri = val; | |
5196 | break; | |
82845826 | 5197 | case 19: /* FAULTMASK */ |
4cc35614 PM |
5198 | if (val & 1) { |
5199 | env->daif |= PSTATE_F; | |
5200 | } else { | |
5201 | env->daif &= ~PSTATE_F; | |
5202 | } | |
82845826 | 5203 | break; |
9ee6e8bb PB |
5204 | case 20: /* CONTROL */ |
5205 | env->v7m.control = val & 3; | |
5206 | switch_v7m_sp(env, (val & 2) != 0); | |
5207 | break; | |
5208 | default: | |
5209 | /* ??? For debugging only. */ | |
a47dddd7 | 5210 | cpu_abort(CPU(cpu), "Unimplemented system register write (%d)\n", reg); |
9ee6e8bb PB |
5211 | return; |
5212 | } | |
5213 | } | |
5214 | ||
b5ff1b31 | 5215 | #endif |
6ddbc6e4 | 5216 | |
aca3f40b PM |
5217 | void HELPER(dc_zva)(CPUARMState *env, uint64_t vaddr_in) |
5218 | { | |
5219 | /* Implement DC ZVA, which zeroes a fixed-length block of memory. | |
5220 | * Note that we do not implement the (architecturally mandated) | |
5221 | * alignment fault for attempts to use this on Device memory | |
5222 | * (which matches the usual QEMU behaviour of not implementing either | |
5223 | * alignment faults or any memory attribute handling). | |
5224 | */ | |
5225 | ||
5226 | ARMCPU *cpu = arm_env_get_cpu(env); | |
5227 | uint64_t blocklen = 4 << cpu->dcz_blocksize; | |
5228 | uint64_t vaddr = vaddr_in & ~(blocklen - 1); | |
5229 | ||
5230 | #ifndef CONFIG_USER_ONLY | |
5231 | { | |
5232 | /* Slightly awkwardly, QEMU's TARGET_PAGE_SIZE may be less than | |
5233 | * the block size so we might have to do more than one TLB lookup. | |
5234 | * We know that in fact for any v8 CPU the page size is at least 4K | |
5235 | * and the block size must be 2K or less, but TARGET_PAGE_SIZE is only | |
5236 | * 1K as an artefact of legacy v5 subpage support being present in the | |
5237 | * same QEMU executable. | |
5238 | */ | |
5239 | int maxidx = DIV_ROUND_UP(blocklen, TARGET_PAGE_SIZE); | |
5240 | void *hostaddr[maxidx]; | |
5241 | int try, i; | |
5242 | ||
5243 | for (try = 0; try < 2; try++) { | |
5244 | ||
5245 | for (i = 0; i < maxidx; i++) { | |
5246 | hostaddr[i] = tlb_vaddr_to_host(env, | |
5247 | vaddr + TARGET_PAGE_SIZE * i, | |
5248 | 1, cpu_mmu_index(env)); | |
5249 | if (!hostaddr[i]) { | |
5250 | break; | |
5251 | } | |
5252 | } | |
5253 | if (i == maxidx) { | |
5254 | /* If it's all in the TLB it's fair game for just writing to; | |
5255 | * we know we don't need to update dirty status, etc. | |
5256 | */ | |
5257 | for (i = 0; i < maxidx - 1; i++) { | |
5258 | memset(hostaddr[i], 0, TARGET_PAGE_SIZE); | |
5259 | } | |
5260 | memset(hostaddr[i], 0, blocklen - (i * TARGET_PAGE_SIZE)); | |
5261 | return; | |
5262 | } | |
5263 | /* OK, try a store and see if we can populate the tlb. This | |
5264 | * might cause an exception if the memory isn't writable, | |
5265 | * in which case we will longjmp out of here. We must for | |
5266 | * this purpose use the actual register value passed to us | |
5267 | * so that we get the fault address right. | |
5268 | */ | |
5269 | helper_ret_stb_mmu(env, vaddr_in, 0, cpu_mmu_index(env), GETRA()); | |
5270 | /* Now we can populate the other TLB entries, if any */ | |
5271 | for (i = 0; i < maxidx; i++) { | |
5272 | uint64_t va = vaddr + TARGET_PAGE_SIZE * i; | |
5273 | if (va != (vaddr_in & TARGET_PAGE_MASK)) { | |
5274 | helper_ret_stb_mmu(env, va, 0, cpu_mmu_index(env), GETRA()); | |
5275 | } | |
5276 | } | |
5277 | } | |
5278 | ||
5279 | /* Slow path (probably attempt to do this to an I/O device or | |
5280 | * similar, or clearing of a block of code we have translations | |
5281 | * cached for). Just do a series of byte writes as the architecture | |
5282 | * demands. It's not worth trying to use a cpu_physical_memory_map(), | |
5283 | * memset(), unmap() sequence here because: | |
5284 | * + we'd need to account for the blocksize being larger than a page | |
5285 | * + the direct-RAM access case is almost always going to be dealt | |
5286 | * with in the fastpath code above, so there's no speed benefit | |
5287 | * + we would have to deal with the map returning NULL because the | |
5288 | * bounce buffer was in use | |
5289 | */ | |
5290 | for (i = 0; i < blocklen; i++) { | |
5291 | helper_ret_stb_mmu(env, vaddr + i, 0, cpu_mmu_index(env), GETRA()); | |
5292 | } | |
5293 | } | |
5294 | #else | |
5295 | memset(g2h(vaddr), 0, blocklen); | |
5296 | #endif | |
5297 | } | |
5298 | ||
6ddbc6e4 PB |
5299 | /* Note that signed overflow is undefined in C. The following routines are |
5300 | careful to use unsigned types where modulo arithmetic is required. | |
5301 | Failure to do so _will_ break on newer gcc. */ | |
5302 | ||
5303 | /* Signed saturating arithmetic. */ | |
5304 | ||
1654b2d6 | 5305 | /* Perform 16-bit signed saturating addition. */ |
6ddbc6e4 PB |
5306 | static inline uint16_t add16_sat(uint16_t a, uint16_t b) |
5307 | { | |
5308 | uint16_t res; | |
5309 | ||
5310 | res = a + b; | |
5311 | if (((res ^ a) & 0x8000) && !((a ^ b) & 0x8000)) { | |
5312 | if (a & 0x8000) | |
5313 | res = 0x8000; | |
5314 | else | |
5315 | res = 0x7fff; | |
5316 | } | |
5317 | return res; | |
5318 | } | |
5319 | ||
1654b2d6 | 5320 | /* Perform 8-bit signed saturating addition. */ |
6ddbc6e4 PB |
5321 | static inline uint8_t add8_sat(uint8_t a, uint8_t b) |
5322 | { | |
5323 | uint8_t res; | |
5324 | ||
5325 | res = a + b; | |
5326 | if (((res ^ a) & 0x80) && !((a ^ b) & 0x80)) { | |
5327 | if (a & 0x80) | |
5328 | res = 0x80; | |
5329 | else | |
5330 | res = 0x7f; | |
5331 | } | |
5332 | return res; | |
5333 | } | |
5334 | ||
1654b2d6 | 5335 | /* Perform 16-bit signed saturating subtraction. */ |
6ddbc6e4 PB |
5336 | static inline uint16_t sub16_sat(uint16_t a, uint16_t b) |
5337 | { | |
5338 | uint16_t res; | |
5339 | ||
5340 | res = a - b; | |
5341 | if (((res ^ a) & 0x8000) && ((a ^ b) & 0x8000)) { | |
5342 | if (a & 0x8000) | |
5343 | res = 0x8000; | |
5344 | else | |
5345 | res = 0x7fff; | |
5346 | } | |
5347 | return res; | |
5348 | } | |
5349 | ||
1654b2d6 | 5350 | /* Perform 8-bit signed saturating subtraction. */ |
6ddbc6e4 PB |
5351 | static inline uint8_t sub8_sat(uint8_t a, uint8_t b) |
5352 | { | |
5353 | uint8_t res; | |
5354 | ||
5355 | res = a - b; | |
5356 | if (((res ^ a) & 0x80) && ((a ^ b) & 0x80)) { | |
5357 | if (a & 0x80) | |
5358 | res = 0x80; | |
5359 | else | |
5360 | res = 0x7f; | |
5361 | } | |
5362 | return res; | |
5363 | } | |
5364 | ||
5365 | #define ADD16(a, b, n) RESULT(add16_sat(a, b), n, 16); | |
5366 | #define SUB16(a, b, n) RESULT(sub16_sat(a, b), n, 16); | |
5367 | #define ADD8(a, b, n) RESULT(add8_sat(a, b), n, 8); | |
5368 | #define SUB8(a, b, n) RESULT(sub8_sat(a, b), n, 8); | |
5369 | #define PFX q | |
5370 | ||
5371 | #include "op_addsub.h" | |
5372 | ||
5373 | /* Unsigned saturating arithmetic. */ | |
460a09c1 | 5374 | static inline uint16_t add16_usat(uint16_t a, uint16_t b) |
6ddbc6e4 PB |
5375 | { |
5376 | uint16_t res; | |
5377 | res = a + b; | |
5378 | if (res < a) | |
5379 | res = 0xffff; | |
5380 | return res; | |
5381 | } | |
5382 | ||
460a09c1 | 5383 | static inline uint16_t sub16_usat(uint16_t a, uint16_t b) |
6ddbc6e4 | 5384 | { |
4c4fd3f8 | 5385 | if (a > b) |
6ddbc6e4 PB |
5386 | return a - b; |
5387 | else | |
5388 | return 0; | |
5389 | } | |
5390 | ||
5391 | static inline uint8_t add8_usat(uint8_t a, uint8_t b) | |
5392 | { | |
5393 | uint8_t res; | |
5394 | res = a + b; | |
5395 | if (res < a) | |
5396 | res = 0xff; | |
5397 | return res; | |
5398 | } | |
5399 | ||
5400 | static inline uint8_t sub8_usat(uint8_t a, uint8_t b) | |
5401 | { | |
4c4fd3f8 | 5402 | if (a > b) |
6ddbc6e4 PB |
5403 | return a - b; |
5404 | else | |
5405 | return 0; | |
5406 | } | |
5407 | ||
5408 | #define ADD16(a, b, n) RESULT(add16_usat(a, b), n, 16); | |
5409 | #define SUB16(a, b, n) RESULT(sub16_usat(a, b), n, 16); | |
5410 | #define ADD8(a, b, n) RESULT(add8_usat(a, b), n, 8); | |
5411 | #define SUB8(a, b, n) RESULT(sub8_usat(a, b), n, 8); | |
5412 | #define PFX uq | |
5413 | ||
5414 | #include "op_addsub.h" | |
5415 | ||
5416 | /* Signed modulo arithmetic. */ | |
5417 | #define SARITH16(a, b, n, op) do { \ | |
5418 | int32_t sum; \ | |
db6e2e65 | 5419 | sum = (int32_t)(int16_t)(a) op (int32_t)(int16_t)(b); \ |
6ddbc6e4 PB |
5420 | RESULT(sum, n, 16); \ |
5421 | if (sum >= 0) \ | |
5422 | ge |= 3 << (n * 2); \ | |
5423 | } while(0) | |
5424 | ||
5425 | #define SARITH8(a, b, n, op) do { \ | |
5426 | int32_t sum; \ | |
db6e2e65 | 5427 | sum = (int32_t)(int8_t)(a) op (int32_t)(int8_t)(b); \ |
6ddbc6e4 PB |
5428 | RESULT(sum, n, 8); \ |
5429 | if (sum >= 0) \ | |
5430 | ge |= 1 << n; \ | |
5431 | } while(0) | |
5432 | ||
5433 | ||
5434 | #define ADD16(a, b, n) SARITH16(a, b, n, +) | |
5435 | #define SUB16(a, b, n) SARITH16(a, b, n, -) | |
5436 | #define ADD8(a, b, n) SARITH8(a, b, n, +) | |
5437 | #define SUB8(a, b, n) SARITH8(a, b, n, -) | |
5438 | #define PFX s | |
5439 | #define ARITH_GE | |
5440 | ||
5441 | #include "op_addsub.h" | |
5442 | ||
5443 | /* Unsigned modulo arithmetic. */ | |
5444 | #define ADD16(a, b, n) do { \ | |
5445 | uint32_t sum; \ | |
5446 | sum = (uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b); \ | |
5447 | RESULT(sum, n, 16); \ | |
a87aa10b | 5448 | if ((sum >> 16) == 1) \ |
6ddbc6e4 PB |
5449 | ge |= 3 << (n * 2); \ |
5450 | } while(0) | |
5451 | ||
5452 | #define ADD8(a, b, n) do { \ | |
5453 | uint32_t sum; \ | |
5454 | sum = (uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b); \ | |
5455 | RESULT(sum, n, 8); \ | |
a87aa10b AZ |
5456 | if ((sum >> 8) == 1) \ |
5457 | ge |= 1 << n; \ | |
6ddbc6e4 PB |
5458 | } while(0) |
5459 | ||
5460 | #define SUB16(a, b, n) do { \ | |
5461 | uint32_t sum; \ | |
5462 | sum = (uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b); \ | |
5463 | RESULT(sum, n, 16); \ | |
5464 | if ((sum >> 16) == 0) \ | |
5465 | ge |= 3 << (n * 2); \ | |
5466 | } while(0) | |
5467 | ||
5468 | #define SUB8(a, b, n) do { \ | |
5469 | uint32_t sum; \ | |
5470 | sum = (uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b); \ | |
5471 | RESULT(sum, n, 8); \ | |
5472 | if ((sum >> 8) == 0) \ | |
a87aa10b | 5473 | ge |= 1 << n; \ |
6ddbc6e4 PB |
5474 | } while(0) |
5475 | ||
5476 | #define PFX u | |
5477 | #define ARITH_GE | |
5478 | ||
5479 | #include "op_addsub.h" | |
5480 | ||
5481 | /* Halved signed arithmetic. */ | |
5482 | #define ADD16(a, b, n) \ | |
5483 | RESULT(((int32_t)(int16_t)(a) + (int32_t)(int16_t)(b)) >> 1, n, 16) | |
5484 | #define SUB16(a, b, n) \ | |
5485 | RESULT(((int32_t)(int16_t)(a) - (int32_t)(int16_t)(b)) >> 1, n, 16) | |
5486 | #define ADD8(a, b, n) \ | |
5487 | RESULT(((int32_t)(int8_t)(a) + (int32_t)(int8_t)(b)) >> 1, n, 8) | |
5488 | #define SUB8(a, b, n) \ | |
5489 | RESULT(((int32_t)(int8_t)(a) - (int32_t)(int8_t)(b)) >> 1, n, 8) | |
5490 | #define PFX sh | |
5491 | ||
5492 | #include "op_addsub.h" | |
5493 | ||
5494 | /* Halved unsigned arithmetic. */ | |
5495 | #define ADD16(a, b, n) \ | |
5496 | RESULT(((uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b)) >> 1, n, 16) | |
5497 | #define SUB16(a, b, n) \ | |
5498 | RESULT(((uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b)) >> 1, n, 16) | |
5499 | #define ADD8(a, b, n) \ | |
5500 | RESULT(((uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b)) >> 1, n, 8) | |
5501 | #define SUB8(a, b, n) \ | |
5502 | RESULT(((uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b)) >> 1, n, 8) | |
5503 | #define PFX uh | |
5504 | ||
5505 | #include "op_addsub.h" | |
5506 | ||
5507 | static inline uint8_t do_usad(uint8_t a, uint8_t b) | |
5508 | { | |
5509 | if (a > b) | |
5510 | return a - b; | |
5511 | else | |
5512 | return b - a; | |
5513 | } | |
5514 | ||
5515 | /* Unsigned sum of absolute byte differences. */ | |
5516 | uint32_t HELPER(usad8)(uint32_t a, uint32_t b) | |
5517 | { | |
5518 | uint32_t sum; | |
5519 | sum = do_usad(a, b); | |
5520 | sum += do_usad(a >> 8, b >> 8); | |
5521 | sum += do_usad(a >> 16, b >>16); | |
5522 | sum += do_usad(a >> 24, b >> 24); | |
5523 | return sum; | |
5524 | } | |
5525 | ||
5526 | /* For ARMv6 SEL instruction. */ | |
5527 | uint32_t HELPER(sel_flags)(uint32_t flags, uint32_t a, uint32_t b) | |
5528 | { | |
5529 | uint32_t mask; | |
5530 | ||
5531 | mask = 0; | |
5532 | if (flags & 1) | |
5533 | mask |= 0xff; | |
5534 | if (flags & 2) | |
5535 | mask |= 0xff00; | |
5536 | if (flags & 4) | |
5537 | mask |= 0xff0000; | |
5538 | if (flags & 8) | |
5539 | mask |= 0xff000000; | |
5540 | return (a & mask) | (b & ~mask); | |
5541 | } | |
5542 | ||
b90372ad PM |
5543 | /* VFP support. We follow the convention used for VFP instructions: |
5544 | Single precision routines have a "s" suffix, double precision a | |
4373f3ce PB |
5545 | "d" suffix. */ |
5546 | ||
5547 | /* Convert host exception flags to vfp form. */ | |
5548 | static inline int vfp_exceptbits_from_host(int host_bits) | |
5549 | { | |
5550 | int target_bits = 0; | |
5551 | ||
5552 | if (host_bits & float_flag_invalid) | |
5553 | target_bits |= 1; | |
5554 | if (host_bits & float_flag_divbyzero) | |
5555 | target_bits |= 2; | |
5556 | if (host_bits & float_flag_overflow) | |
5557 | target_bits |= 4; | |
36802b6b | 5558 | if (host_bits & (float_flag_underflow | float_flag_output_denormal)) |
4373f3ce PB |
5559 | target_bits |= 8; |
5560 | if (host_bits & float_flag_inexact) | |
5561 | target_bits |= 0x10; | |
cecd8504 PM |
5562 | if (host_bits & float_flag_input_denormal) |
5563 | target_bits |= 0x80; | |
4373f3ce PB |
5564 | return target_bits; |
5565 | } | |
5566 | ||
0ecb72a5 | 5567 | uint32_t HELPER(vfp_get_fpscr)(CPUARMState *env) |
4373f3ce PB |
5568 | { |
5569 | int i; | |
5570 | uint32_t fpscr; | |
5571 | ||
5572 | fpscr = (env->vfp.xregs[ARM_VFP_FPSCR] & 0xffc8ffff) | |
5573 | | (env->vfp.vec_len << 16) | |
5574 | | (env->vfp.vec_stride << 20); | |
5575 | i = get_float_exception_flags(&env->vfp.fp_status); | |
3a492f3a | 5576 | i |= get_float_exception_flags(&env->vfp.standard_fp_status); |
4373f3ce PB |
5577 | fpscr |= vfp_exceptbits_from_host(i); |
5578 | return fpscr; | |
5579 | } | |
5580 | ||
0ecb72a5 | 5581 | uint32_t vfp_get_fpscr(CPUARMState *env) |
01653295 PM |
5582 | { |
5583 | return HELPER(vfp_get_fpscr)(env); | |
5584 | } | |
5585 | ||
4373f3ce PB |
5586 | /* Convert vfp exception flags to target form. */ |
5587 | static inline int vfp_exceptbits_to_host(int target_bits) | |
5588 | { | |
5589 | int host_bits = 0; | |
5590 | ||
5591 | if (target_bits & 1) | |
5592 | host_bits |= float_flag_invalid; | |
5593 | if (target_bits & 2) | |
5594 | host_bits |= float_flag_divbyzero; | |
5595 | if (target_bits & 4) | |
5596 | host_bits |= float_flag_overflow; | |
5597 | if (target_bits & 8) | |
5598 | host_bits |= float_flag_underflow; | |
5599 | if (target_bits & 0x10) | |
5600 | host_bits |= float_flag_inexact; | |
cecd8504 PM |
5601 | if (target_bits & 0x80) |
5602 | host_bits |= float_flag_input_denormal; | |
4373f3ce PB |
5603 | return host_bits; |
5604 | } | |
5605 | ||
0ecb72a5 | 5606 | void HELPER(vfp_set_fpscr)(CPUARMState *env, uint32_t val) |
4373f3ce PB |
5607 | { |
5608 | int i; | |
5609 | uint32_t changed; | |
5610 | ||
5611 | changed = env->vfp.xregs[ARM_VFP_FPSCR]; | |
5612 | env->vfp.xregs[ARM_VFP_FPSCR] = (val & 0xffc8ffff); | |
5613 | env->vfp.vec_len = (val >> 16) & 7; | |
5614 | env->vfp.vec_stride = (val >> 20) & 3; | |
5615 | ||
5616 | changed ^= val; | |
5617 | if (changed & (3 << 22)) { | |
5618 | i = (val >> 22) & 3; | |
5619 | switch (i) { | |
4d3da0f3 | 5620 | case FPROUNDING_TIEEVEN: |
4373f3ce PB |
5621 | i = float_round_nearest_even; |
5622 | break; | |
4d3da0f3 | 5623 | case FPROUNDING_POSINF: |
4373f3ce PB |
5624 | i = float_round_up; |
5625 | break; | |
4d3da0f3 | 5626 | case FPROUNDING_NEGINF: |
4373f3ce PB |
5627 | i = float_round_down; |
5628 | break; | |
4d3da0f3 | 5629 | case FPROUNDING_ZERO: |
4373f3ce PB |
5630 | i = float_round_to_zero; |
5631 | break; | |
5632 | } | |
5633 | set_float_rounding_mode(i, &env->vfp.fp_status); | |
5634 | } | |
cecd8504 | 5635 | if (changed & (1 << 24)) { |
fe76d976 | 5636 | set_flush_to_zero((val & (1 << 24)) != 0, &env->vfp.fp_status); |
cecd8504 PM |
5637 | set_flush_inputs_to_zero((val & (1 << 24)) != 0, &env->vfp.fp_status); |
5638 | } | |
5c7908ed PB |
5639 | if (changed & (1 << 25)) |
5640 | set_default_nan_mode((val & (1 << 25)) != 0, &env->vfp.fp_status); | |
4373f3ce | 5641 | |
b12c390b | 5642 | i = vfp_exceptbits_to_host(val); |
4373f3ce | 5643 | set_float_exception_flags(i, &env->vfp.fp_status); |
3a492f3a | 5644 | set_float_exception_flags(0, &env->vfp.standard_fp_status); |
4373f3ce PB |
5645 | } |
5646 | ||
0ecb72a5 | 5647 | void vfp_set_fpscr(CPUARMState *env, uint32_t val) |
01653295 PM |
5648 | { |
5649 | HELPER(vfp_set_fpscr)(env, val); | |
5650 | } | |
5651 | ||
4373f3ce PB |
5652 | #define VFP_HELPER(name, p) HELPER(glue(glue(vfp_,name),p)) |
5653 | ||
5654 | #define VFP_BINOP(name) \ | |
ae1857ec | 5655 | float32 VFP_HELPER(name, s)(float32 a, float32 b, void *fpstp) \ |
4373f3ce | 5656 | { \ |
ae1857ec PM |
5657 | float_status *fpst = fpstp; \ |
5658 | return float32_ ## name(a, b, fpst); \ | |
4373f3ce | 5659 | } \ |
ae1857ec | 5660 | float64 VFP_HELPER(name, d)(float64 a, float64 b, void *fpstp) \ |
4373f3ce | 5661 | { \ |
ae1857ec PM |
5662 | float_status *fpst = fpstp; \ |
5663 | return float64_ ## name(a, b, fpst); \ | |
4373f3ce PB |
5664 | } |
5665 | VFP_BINOP(add) | |
5666 | VFP_BINOP(sub) | |
5667 | VFP_BINOP(mul) | |
5668 | VFP_BINOP(div) | |
f71a2ae5 PM |
5669 | VFP_BINOP(min) |
5670 | VFP_BINOP(max) | |
5671 | VFP_BINOP(minnum) | |
5672 | VFP_BINOP(maxnum) | |
4373f3ce PB |
5673 | #undef VFP_BINOP |
5674 | ||
5675 | float32 VFP_HELPER(neg, s)(float32 a) | |
5676 | { | |
5677 | return float32_chs(a); | |
5678 | } | |
5679 | ||
5680 | float64 VFP_HELPER(neg, d)(float64 a) | |
5681 | { | |
66230e0d | 5682 | return float64_chs(a); |
4373f3ce PB |
5683 | } |
5684 | ||
5685 | float32 VFP_HELPER(abs, s)(float32 a) | |
5686 | { | |
5687 | return float32_abs(a); | |
5688 | } | |
5689 | ||
5690 | float64 VFP_HELPER(abs, d)(float64 a) | |
5691 | { | |
66230e0d | 5692 | return float64_abs(a); |
4373f3ce PB |
5693 | } |
5694 | ||
0ecb72a5 | 5695 | float32 VFP_HELPER(sqrt, s)(float32 a, CPUARMState *env) |
4373f3ce PB |
5696 | { |
5697 | return float32_sqrt(a, &env->vfp.fp_status); | |
5698 | } | |
5699 | ||
0ecb72a5 | 5700 | float64 VFP_HELPER(sqrt, d)(float64 a, CPUARMState *env) |
4373f3ce PB |
5701 | { |
5702 | return float64_sqrt(a, &env->vfp.fp_status); | |
5703 | } | |
5704 | ||
5705 | /* XXX: check quiet/signaling case */ | |
5706 | #define DO_VFP_cmp(p, type) \ | |
0ecb72a5 | 5707 | void VFP_HELPER(cmp, p)(type a, type b, CPUARMState *env) \ |
4373f3ce PB |
5708 | { \ |
5709 | uint32_t flags; \ | |
5710 | switch(type ## _compare_quiet(a, b, &env->vfp.fp_status)) { \ | |
5711 | case 0: flags = 0x6; break; \ | |
5712 | case -1: flags = 0x8; break; \ | |
5713 | case 1: flags = 0x2; break; \ | |
5714 | default: case 2: flags = 0x3; break; \ | |
5715 | } \ | |
5716 | env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \ | |
5717 | | (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \ | |
5718 | } \ | |
0ecb72a5 | 5719 | void VFP_HELPER(cmpe, p)(type a, type b, CPUARMState *env) \ |
4373f3ce PB |
5720 | { \ |
5721 | uint32_t flags; \ | |
5722 | switch(type ## _compare(a, b, &env->vfp.fp_status)) { \ | |
5723 | case 0: flags = 0x6; break; \ | |
5724 | case -1: flags = 0x8; break; \ | |
5725 | case 1: flags = 0x2; break; \ | |
5726 | default: case 2: flags = 0x3; break; \ | |
5727 | } \ | |
5728 | env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \ | |
5729 | | (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \ | |
5730 | } | |
5731 | DO_VFP_cmp(s, float32) | |
5732 | DO_VFP_cmp(d, float64) | |
5733 | #undef DO_VFP_cmp | |
5734 | ||
5500b06c | 5735 | /* Integer to float and float to integer conversions */ |
4373f3ce | 5736 | |
5500b06c PM |
5737 | #define CONV_ITOF(name, fsz, sign) \ |
5738 | float##fsz HELPER(name)(uint32_t x, void *fpstp) \ | |
5739 | { \ | |
5740 | float_status *fpst = fpstp; \ | |
85836979 | 5741 | return sign##int32_to_##float##fsz((sign##int32_t)x, fpst); \ |
4373f3ce PB |
5742 | } |
5743 | ||
5500b06c PM |
5744 | #define CONV_FTOI(name, fsz, sign, round) \ |
5745 | uint32_t HELPER(name)(float##fsz x, void *fpstp) \ | |
5746 | { \ | |
5747 | float_status *fpst = fpstp; \ | |
5748 | if (float##fsz##_is_any_nan(x)) { \ | |
5749 | float_raise(float_flag_invalid, fpst); \ | |
5750 | return 0; \ | |
5751 | } \ | |
5752 | return float##fsz##_to_##sign##int32##round(x, fpst); \ | |
4373f3ce PB |
5753 | } |
5754 | ||
5500b06c PM |
5755 | #define FLOAT_CONVS(name, p, fsz, sign) \ |
5756 | CONV_ITOF(vfp_##name##to##p, fsz, sign) \ | |
5757 | CONV_FTOI(vfp_to##name##p, fsz, sign, ) \ | |
5758 | CONV_FTOI(vfp_to##name##z##p, fsz, sign, _round_to_zero) | |
4373f3ce | 5759 | |
5500b06c PM |
5760 | FLOAT_CONVS(si, s, 32, ) |
5761 | FLOAT_CONVS(si, d, 64, ) | |
5762 | FLOAT_CONVS(ui, s, 32, u) | |
5763 | FLOAT_CONVS(ui, d, 64, u) | |
4373f3ce | 5764 | |
5500b06c PM |
5765 | #undef CONV_ITOF |
5766 | #undef CONV_FTOI | |
5767 | #undef FLOAT_CONVS | |
4373f3ce PB |
5768 | |
5769 | /* floating point conversion */ | |
0ecb72a5 | 5770 | float64 VFP_HELPER(fcvtd, s)(float32 x, CPUARMState *env) |
4373f3ce | 5771 | { |
2d627737 PM |
5772 | float64 r = float32_to_float64(x, &env->vfp.fp_status); |
5773 | /* ARM requires that S<->D conversion of any kind of NaN generates | |
5774 | * a quiet NaN by forcing the most significant frac bit to 1. | |
5775 | */ | |
5776 | return float64_maybe_silence_nan(r); | |
4373f3ce PB |
5777 | } |
5778 | ||
0ecb72a5 | 5779 | float32 VFP_HELPER(fcvts, d)(float64 x, CPUARMState *env) |
4373f3ce | 5780 | { |
2d627737 PM |
5781 | float32 r = float64_to_float32(x, &env->vfp.fp_status); |
5782 | /* ARM requires that S<->D conversion of any kind of NaN generates | |
5783 | * a quiet NaN by forcing the most significant frac bit to 1. | |
5784 | */ | |
5785 | return float32_maybe_silence_nan(r); | |
4373f3ce PB |
5786 | } |
5787 | ||
5788 | /* VFP3 fixed point conversion. */ | |
16d5b3ca | 5789 | #define VFP_CONV_FIX_FLOAT(name, p, fsz, isz, itype) \ |
8ed697e8 WN |
5790 | float##fsz HELPER(vfp_##name##to##p)(uint##isz##_t x, uint32_t shift, \ |
5791 | void *fpstp) \ | |
4373f3ce | 5792 | { \ |
5500b06c | 5793 | float_status *fpst = fpstp; \ |
622465e1 | 5794 | float##fsz tmp; \ |
8ed697e8 | 5795 | tmp = itype##_to_##float##fsz(x, fpst); \ |
5500b06c | 5796 | return float##fsz##_scalbn(tmp, -(int)shift, fpst); \ |
16d5b3ca WN |
5797 | } |
5798 | ||
abe66f70 PM |
5799 | /* Notice that we want only input-denormal exception flags from the |
5800 | * scalbn operation: the other possible flags (overflow+inexact if | |
5801 | * we overflow to infinity, output-denormal) aren't correct for the | |
5802 | * complete scale-and-convert operation. | |
5803 | */ | |
16d5b3ca WN |
5804 | #define VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, round) \ |
5805 | uint##isz##_t HELPER(vfp_to##name##p##round)(float##fsz x, \ | |
5806 | uint32_t shift, \ | |
5807 | void *fpstp) \ | |
4373f3ce | 5808 | { \ |
5500b06c | 5809 | float_status *fpst = fpstp; \ |
abe66f70 | 5810 | int old_exc_flags = get_float_exception_flags(fpst); \ |
622465e1 PM |
5811 | float##fsz tmp; \ |
5812 | if (float##fsz##_is_any_nan(x)) { \ | |
5500b06c | 5813 | float_raise(float_flag_invalid, fpst); \ |
622465e1 | 5814 | return 0; \ |
09d9487f | 5815 | } \ |
5500b06c | 5816 | tmp = float##fsz##_scalbn(x, shift, fpst); \ |
abe66f70 PM |
5817 | old_exc_flags |= get_float_exception_flags(fpst) \ |
5818 | & float_flag_input_denormal; \ | |
5819 | set_float_exception_flags(old_exc_flags, fpst); \ | |
16d5b3ca | 5820 | return float##fsz##_to_##itype##round(tmp, fpst); \ |
622465e1 PM |
5821 | } |
5822 | ||
16d5b3ca WN |
5823 | #define VFP_CONV_FIX(name, p, fsz, isz, itype) \ |
5824 | VFP_CONV_FIX_FLOAT(name, p, fsz, isz, itype) \ | |
3c6a074a WN |
5825 | VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, _round_to_zero) \ |
5826 | VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, ) | |
5827 | ||
5828 | #define VFP_CONV_FIX_A64(name, p, fsz, isz, itype) \ | |
5829 | VFP_CONV_FIX_FLOAT(name, p, fsz, isz, itype) \ | |
5830 | VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, ) | |
16d5b3ca | 5831 | |
8ed697e8 WN |
5832 | VFP_CONV_FIX(sh, d, 64, 64, int16) |
5833 | VFP_CONV_FIX(sl, d, 64, 64, int32) | |
3c6a074a | 5834 | VFP_CONV_FIX_A64(sq, d, 64, 64, int64) |
8ed697e8 WN |
5835 | VFP_CONV_FIX(uh, d, 64, 64, uint16) |
5836 | VFP_CONV_FIX(ul, d, 64, 64, uint32) | |
3c6a074a | 5837 | VFP_CONV_FIX_A64(uq, d, 64, 64, uint64) |
8ed697e8 WN |
5838 | VFP_CONV_FIX(sh, s, 32, 32, int16) |
5839 | VFP_CONV_FIX(sl, s, 32, 32, int32) | |
3c6a074a | 5840 | VFP_CONV_FIX_A64(sq, s, 32, 64, int64) |
8ed697e8 WN |
5841 | VFP_CONV_FIX(uh, s, 32, 32, uint16) |
5842 | VFP_CONV_FIX(ul, s, 32, 32, uint32) | |
3c6a074a | 5843 | VFP_CONV_FIX_A64(uq, s, 32, 64, uint64) |
4373f3ce | 5844 | #undef VFP_CONV_FIX |
16d5b3ca WN |
5845 | #undef VFP_CONV_FIX_FLOAT |
5846 | #undef VFP_CONV_FLOAT_FIX_ROUND | |
4373f3ce | 5847 | |
52a1f6a3 AG |
5848 | /* Set the current fp rounding mode and return the old one. |
5849 | * The argument is a softfloat float_round_ value. | |
5850 | */ | |
5851 | uint32_t HELPER(set_rmode)(uint32_t rmode, CPUARMState *env) | |
5852 | { | |
5853 | float_status *fp_status = &env->vfp.fp_status; | |
5854 | ||
5855 | uint32_t prev_rmode = get_float_rounding_mode(fp_status); | |
5856 | set_float_rounding_mode(rmode, fp_status); | |
5857 | ||
5858 | return prev_rmode; | |
5859 | } | |
5860 | ||
43630e58 WN |
5861 | /* Set the current fp rounding mode in the standard fp status and return |
5862 | * the old one. This is for NEON instructions that need to change the | |
5863 | * rounding mode but wish to use the standard FPSCR values for everything | |
5864 | * else. Always set the rounding mode back to the correct value after | |
5865 | * modifying it. | |
5866 | * The argument is a softfloat float_round_ value. | |
5867 | */ | |
5868 | uint32_t HELPER(set_neon_rmode)(uint32_t rmode, CPUARMState *env) | |
5869 | { | |
5870 | float_status *fp_status = &env->vfp.standard_fp_status; | |
5871 | ||
5872 | uint32_t prev_rmode = get_float_rounding_mode(fp_status); | |
5873 | set_float_rounding_mode(rmode, fp_status); | |
5874 | ||
5875 | return prev_rmode; | |
5876 | } | |
5877 | ||
60011498 | 5878 | /* Half precision conversions. */ |
0ecb72a5 | 5879 | static float32 do_fcvt_f16_to_f32(uint32_t a, CPUARMState *env, float_status *s) |
60011498 | 5880 | { |
60011498 | 5881 | int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0; |
fb91678d PM |
5882 | float32 r = float16_to_float32(make_float16(a), ieee, s); |
5883 | if (ieee) { | |
5884 | return float32_maybe_silence_nan(r); | |
5885 | } | |
5886 | return r; | |
60011498 PB |
5887 | } |
5888 | ||
0ecb72a5 | 5889 | static uint32_t do_fcvt_f32_to_f16(float32 a, CPUARMState *env, float_status *s) |
60011498 | 5890 | { |
60011498 | 5891 | int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0; |
fb91678d PM |
5892 | float16 r = float32_to_float16(a, ieee, s); |
5893 | if (ieee) { | |
5894 | r = float16_maybe_silence_nan(r); | |
5895 | } | |
5896 | return float16_val(r); | |
60011498 PB |
5897 | } |
5898 | ||
0ecb72a5 | 5899 | float32 HELPER(neon_fcvt_f16_to_f32)(uint32_t a, CPUARMState *env) |
2d981da7 PM |
5900 | { |
5901 | return do_fcvt_f16_to_f32(a, env, &env->vfp.standard_fp_status); | |
5902 | } | |
5903 | ||
0ecb72a5 | 5904 | uint32_t HELPER(neon_fcvt_f32_to_f16)(float32 a, CPUARMState *env) |
2d981da7 PM |
5905 | { |
5906 | return do_fcvt_f32_to_f16(a, env, &env->vfp.standard_fp_status); | |
5907 | } | |
5908 | ||
0ecb72a5 | 5909 | float32 HELPER(vfp_fcvt_f16_to_f32)(uint32_t a, CPUARMState *env) |
2d981da7 PM |
5910 | { |
5911 | return do_fcvt_f16_to_f32(a, env, &env->vfp.fp_status); | |
5912 | } | |
5913 | ||
0ecb72a5 | 5914 | uint32_t HELPER(vfp_fcvt_f32_to_f16)(float32 a, CPUARMState *env) |
2d981da7 PM |
5915 | { |
5916 | return do_fcvt_f32_to_f16(a, env, &env->vfp.fp_status); | |
5917 | } | |
5918 | ||
8900aad2 PM |
5919 | float64 HELPER(vfp_fcvt_f16_to_f64)(uint32_t a, CPUARMState *env) |
5920 | { | |
5921 | int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0; | |
5922 | float64 r = float16_to_float64(make_float16(a), ieee, &env->vfp.fp_status); | |
5923 | if (ieee) { | |
5924 | return float64_maybe_silence_nan(r); | |
5925 | } | |
5926 | return r; | |
5927 | } | |
5928 | ||
5929 | uint32_t HELPER(vfp_fcvt_f64_to_f16)(float64 a, CPUARMState *env) | |
5930 | { | |
5931 | int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0; | |
5932 | float16 r = float64_to_float16(a, ieee, &env->vfp.fp_status); | |
5933 | if (ieee) { | |
5934 | r = float16_maybe_silence_nan(r); | |
5935 | } | |
5936 | return float16_val(r); | |
5937 | } | |
5938 | ||
dda3ec49 | 5939 | #define float32_two make_float32(0x40000000) |
6aae3df1 PM |
5940 | #define float32_three make_float32(0x40400000) |
5941 | #define float32_one_point_five make_float32(0x3fc00000) | |
dda3ec49 | 5942 | |
0ecb72a5 | 5943 | float32 HELPER(recps_f32)(float32 a, float32 b, CPUARMState *env) |
4373f3ce | 5944 | { |
dda3ec49 PM |
5945 | float_status *s = &env->vfp.standard_fp_status; |
5946 | if ((float32_is_infinity(a) && float32_is_zero_or_denormal(b)) || | |
5947 | (float32_is_infinity(b) && float32_is_zero_or_denormal(a))) { | |
43fe9bdb PM |
5948 | if (!(float32_is_zero(a) || float32_is_zero(b))) { |
5949 | float_raise(float_flag_input_denormal, s); | |
5950 | } | |
dda3ec49 PM |
5951 | return float32_two; |
5952 | } | |
5953 | return float32_sub(float32_two, float32_mul(a, b, s), s); | |
4373f3ce PB |
5954 | } |
5955 | ||
0ecb72a5 | 5956 | float32 HELPER(rsqrts_f32)(float32 a, float32 b, CPUARMState *env) |
4373f3ce | 5957 | { |
71826966 | 5958 | float_status *s = &env->vfp.standard_fp_status; |
9ea62f57 PM |
5959 | float32 product; |
5960 | if ((float32_is_infinity(a) && float32_is_zero_or_denormal(b)) || | |
5961 | (float32_is_infinity(b) && float32_is_zero_or_denormal(a))) { | |
43fe9bdb PM |
5962 | if (!(float32_is_zero(a) || float32_is_zero(b))) { |
5963 | float_raise(float_flag_input_denormal, s); | |
5964 | } | |
6aae3df1 | 5965 | return float32_one_point_five; |
9ea62f57 | 5966 | } |
6aae3df1 PM |
5967 | product = float32_mul(a, b, s); |
5968 | return float32_div(float32_sub(float32_three, product, s), float32_two, s); | |
4373f3ce PB |
5969 | } |
5970 | ||
8f8e3aa4 PB |
5971 | /* NEON helpers. */ |
5972 | ||
56bf4fe2 CL |
5973 | /* Constants 256 and 512 are used in some helpers; we avoid relying on |
5974 | * int->float conversions at run-time. */ | |
5975 | #define float64_256 make_float64(0x4070000000000000LL) | |
5976 | #define float64_512 make_float64(0x4080000000000000LL) | |
b6d4443a AB |
5977 | #define float32_maxnorm make_float32(0x7f7fffff) |
5978 | #define float64_maxnorm make_float64(0x7fefffffffffffffLL) | |
56bf4fe2 | 5979 | |
b6d4443a AB |
5980 | /* Reciprocal functions |
5981 | * | |
5982 | * The algorithm that must be used to calculate the estimate | |
5983 | * is specified by the ARM ARM, see FPRecipEstimate() | |
fe0e4872 | 5984 | */ |
b6d4443a AB |
5985 | |
5986 | static float64 recip_estimate(float64 a, float_status *real_fp_status) | |
fe0e4872 | 5987 | { |
1146a817 PM |
5988 | /* These calculations mustn't set any fp exception flags, |
5989 | * so we use a local copy of the fp_status. | |
5990 | */ | |
b6d4443a | 5991 | float_status dummy_status = *real_fp_status; |
1146a817 | 5992 | float_status *s = &dummy_status; |
fe0e4872 CL |
5993 | /* q = (int)(a * 512.0) */ |
5994 | float64 q = float64_mul(float64_512, a, s); | |
5995 | int64_t q_int = float64_to_int64_round_to_zero(q, s); | |
5996 | ||
5997 | /* r = 1.0 / (((double)q + 0.5) / 512.0) */ | |
5998 | q = int64_to_float64(q_int, s); | |
5999 | q = float64_add(q, float64_half, s); | |
6000 | q = float64_div(q, float64_512, s); | |
6001 | q = float64_div(float64_one, q, s); | |
6002 | ||
6003 | /* s = (int)(256.0 * r + 0.5) */ | |
6004 | q = float64_mul(q, float64_256, s); | |
6005 | q = float64_add(q, float64_half, s); | |
6006 | q_int = float64_to_int64_round_to_zero(q, s); | |
6007 | ||
6008 | /* return (double)s / 256.0 */ | |
6009 | return float64_div(int64_to_float64(q_int, s), float64_256, s); | |
6010 | } | |
6011 | ||
b6d4443a AB |
6012 | /* Common wrapper to call recip_estimate */ |
6013 | static float64 call_recip_estimate(float64 num, int off, float_status *fpst) | |
4373f3ce | 6014 | { |
b6d4443a AB |
6015 | uint64_t val64 = float64_val(num); |
6016 | uint64_t frac = extract64(val64, 0, 52); | |
6017 | int64_t exp = extract64(val64, 52, 11); | |
6018 | uint64_t sbit; | |
6019 | float64 scaled, estimate; | |
fe0e4872 | 6020 | |
b6d4443a AB |
6021 | /* Generate the scaled number for the estimate function */ |
6022 | if (exp == 0) { | |
6023 | if (extract64(frac, 51, 1) == 0) { | |
6024 | exp = -1; | |
6025 | frac = extract64(frac, 0, 50) << 2; | |
6026 | } else { | |
6027 | frac = extract64(frac, 0, 51) << 1; | |
6028 | } | |
6029 | } | |
fe0e4872 | 6030 | |
b6d4443a AB |
6031 | /* scaled = '0' : '01111111110' : fraction<51:44> : Zeros(44); */ |
6032 | scaled = make_float64((0x3feULL << 52) | |
6033 | | extract64(frac, 44, 8) << 44); | |
6034 | ||
6035 | estimate = recip_estimate(scaled, fpst); | |
6036 | ||
6037 | /* Build new result */ | |
6038 | val64 = float64_val(estimate); | |
6039 | sbit = 0x8000000000000000ULL & val64; | |
6040 | exp = off - exp; | |
6041 | frac = extract64(val64, 0, 52); | |
6042 | ||
6043 | if (exp == 0) { | |
6044 | frac = 1ULL << 51 | extract64(frac, 1, 51); | |
6045 | } else if (exp == -1) { | |
6046 | frac = 1ULL << 50 | extract64(frac, 2, 50); | |
6047 | exp = 0; | |
6048 | } | |
6049 | ||
6050 | return make_float64(sbit | (exp << 52) | frac); | |
6051 | } | |
6052 | ||
6053 | static bool round_to_inf(float_status *fpst, bool sign_bit) | |
6054 | { | |
6055 | switch (fpst->float_rounding_mode) { | |
6056 | case float_round_nearest_even: /* Round to Nearest */ | |
6057 | return true; | |
6058 | case float_round_up: /* Round to +Inf */ | |
6059 | return !sign_bit; | |
6060 | case float_round_down: /* Round to -Inf */ | |
6061 | return sign_bit; | |
6062 | case float_round_to_zero: /* Round to Zero */ | |
6063 | return false; | |
6064 | } | |
6065 | ||
6066 | g_assert_not_reached(); | |
6067 | } | |
6068 | ||
6069 | float32 HELPER(recpe_f32)(float32 input, void *fpstp) | |
6070 | { | |
6071 | float_status *fpst = fpstp; | |
6072 | float32 f32 = float32_squash_input_denormal(input, fpst); | |
6073 | uint32_t f32_val = float32_val(f32); | |
6074 | uint32_t f32_sbit = 0x80000000ULL & f32_val; | |
6075 | int32_t f32_exp = extract32(f32_val, 23, 8); | |
6076 | uint32_t f32_frac = extract32(f32_val, 0, 23); | |
6077 | float64 f64, r64; | |
6078 | uint64_t r64_val; | |
6079 | int64_t r64_exp; | |
6080 | uint64_t r64_frac; | |
6081 | ||
6082 | if (float32_is_any_nan(f32)) { | |
6083 | float32 nan = f32; | |
6084 | if (float32_is_signaling_nan(f32)) { | |
6085 | float_raise(float_flag_invalid, fpst); | |
6086 | nan = float32_maybe_silence_nan(f32); | |
fe0e4872 | 6087 | } |
b6d4443a AB |
6088 | if (fpst->default_nan_mode) { |
6089 | nan = float32_default_nan; | |
43fe9bdb | 6090 | } |
b6d4443a AB |
6091 | return nan; |
6092 | } else if (float32_is_infinity(f32)) { | |
6093 | return float32_set_sign(float32_zero, float32_is_neg(f32)); | |
6094 | } else if (float32_is_zero(f32)) { | |
6095 | float_raise(float_flag_divbyzero, fpst); | |
6096 | return float32_set_sign(float32_infinity, float32_is_neg(f32)); | |
6097 | } else if ((f32_val & ~(1ULL << 31)) < (1ULL << 21)) { | |
6098 | /* Abs(value) < 2.0^-128 */ | |
6099 | float_raise(float_flag_overflow | float_flag_inexact, fpst); | |
6100 | if (round_to_inf(fpst, f32_sbit)) { | |
6101 | return float32_set_sign(float32_infinity, float32_is_neg(f32)); | |
6102 | } else { | |
6103 | return float32_set_sign(float32_maxnorm, float32_is_neg(f32)); | |
6104 | } | |
6105 | } else if (f32_exp >= 253 && fpst->flush_to_zero) { | |
6106 | float_raise(float_flag_underflow, fpst); | |
6107 | return float32_set_sign(float32_zero, float32_is_neg(f32)); | |
fe0e4872 CL |
6108 | } |
6109 | ||
fe0e4872 | 6110 | |
b6d4443a AB |
6111 | f64 = make_float64(((int64_t)(f32_exp) << 52) | (int64_t)(f32_frac) << 29); |
6112 | r64 = call_recip_estimate(f64, 253, fpst); | |
6113 | r64_val = float64_val(r64); | |
6114 | r64_exp = extract64(r64_val, 52, 11); | |
6115 | r64_frac = extract64(r64_val, 0, 52); | |
6116 | ||
6117 | /* result = sign : result_exp<7:0> : fraction<51:29>; */ | |
6118 | return make_float32(f32_sbit | | |
6119 | (r64_exp & 0xff) << 23 | | |
6120 | extract64(r64_frac, 29, 24)); | |
6121 | } | |
6122 | ||
6123 | float64 HELPER(recpe_f64)(float64 input, void *fpstp) | |
6124 | { | |
6125 | float_status *fpst = fpstp; | |
6126 | float64 f64 = float64_squash_input_denormal(input, fpst); | |
6127 | uint64_t f64_val = float64_val(f64); | |
6128 | uint64_t f64_sbit = 0x8000000000000000ULL & f64_val; | |
6129 | int64_t f64_exp = extract64(f64_val, 52, 11); | |
6130 | float64 r64; | |
6131 | uint64_t r64_val; | |
6132 | int64_t r64_exp; | |
6133 | uint64_t r64_frac; | |
6134 | ||
6135 | /* Deal with any special cases */ | |
6136 | if (float64_is_any_nan(f64)) { | |
6137 | float64 nan = f64; | |
6138 | if (float64_is_signaling_nan(f64)) { | |
6139 | float_raise(float_flag_invalid, fpst); | |
6140 | nan = float64_maybe_silence_nan(f64); | |
6141 | } | |
6142 | if (fpst->default_nan_mode) { | |
6143 | nan = float64_default_nan; | |
6144 | } | |
6145 | return nan; | |
6146 | } else if (float64_is_infinity(f64)) { | |
6147 | return float64_set_sign(float64_zero, float64_is_neg(f64)); | |
6148 | } else if (float64_is_zero(f64)) { | |
6149 | float_raise(float_flag_divbyzero, fpst); | |
6150 | return float64_set_sign(float64_infinity, float64_is_neg(f64)); | |
6151 | } else if ((f64_val & ~(1ULL << 63)) < (1ULL << 50)) { | |
6152 | /* Abs(value) < 2.0^-1024 */ | |
6153 | float_raise(float_flag_overflow | float_flag_inexact, fpst); | |
6154 | if (round_to_inf(fpst, f64_sbit)) { | |
6155 | return float64_set_sign(float64_infinity, float64_is_neg(f64)); | |
6156 | } else { | |
6157 | return float64_set_sign(float64_maxnorm, float64_is_neg(f64)); | |
6158 | } | |
6159 | } else if (f64_exp >= 1023 && fpst->flush_to_zero) { | |
6160 | float_raise(float_flag_underflow, fpst); | |
6161 | return float64_set_sign(float64_zero, float64_is_neg(f64)); | |
6162 | } | |
fe0e4872 | 6163 | |
b6d4443a AB |
6164 | r64 = call_recip_estimate(f64, 2045, fpst); |
6165 | r64_val = float64_val(r64); | |
6166 | r64_exp = extract64(r64_val, 52, 11); | |
6167 | r64_frac = extract64(r64_val, 0, 52); | |
fe0e4872 | 6168 | |
b6d4443a AB |
6169 | /* result = sign : result_exp<10:0> : fraction<51:0> */ |
6170 | return make_float64(f64_sbit | | |
6171 | ((r64_exp & 0x7ff) << 52) | | |
6172 | r64_frac); | |
4373f3ce PB |
6173 | } |
6174 | ||
e07be5d2 CL |
6175 | /* The algorithm that must be used to calculate the estimate |
6176 | * is specified by the ARM ARM. | |
6177 | */ | |
c2fb418e | 6178 | static float64 recip_sqrt_estimate(float64 a, float_status *real_fp_status) |
e07be5d2 | 6179 | { |
1146a817 PM |
6180 | /* These calculations mustn't set any fp exception flags, |
6181 | * so we use a local copy of the fp_status. | |
6182 | */ | |
c2fb418e | 6183 | float_status dummy_status = *real_fp_status; |
1146a817 | 6184 | float_status *s = &dummy_status; |
e07be5d2 CL |
6185 | float64 q; |
6186 | int64_t q_int; | |
6187 | ||
6188 | if (float64_lt(a, float64_half, s)) { | |
6189 | /* range 0.25 <= a < 0.5 */ | |
6190 | ||
6191 | /* a in units of 1/512 rounded down */ | |
6192 | /* q0 = (int)(a * 512.0); */ | |
6193 | q = float64_mul(float64_512, a, s); | |
6194 | q_int = float64_to_int64_round_to_zero(q, s); | |
6195 | ||
6196 | /* reciprocal root r */ | |
6197 | /* r = 1.0 / sqrt(((double)q0 + 0.5) / 512.0); */ | |
6198 | q = int64_to_float64(q_int, s); | |
6199 | q = float64_add(q, float64_half, s); | |
6200 | q = float64_div(q, float64_512, s); | |
6201 | q = float64_sqrt(q, s); | |
6202 | q = float64_div(float64_one, q, s); | |
6203 | } else { | |
6204 | /* range 0.5 <= a < 1.0 */ | |
6205 | ||
6206 | /* a in units of 1/256 rounded down */ | |
6207 | /* q1 = (int)(a * 256.0); */ | |
6208 | q = float64_mul(float64_256, a, s); | |
6209 | int64_t q_int = float64_to_int64_round_to_zero(q, s); | |
6210 | ||
6211 | /* reciprocal root r */ | |
6212 | /* r = 1.0 /sqrt(((double)q1 + 0.5) / 256); */ | |
6213 | q = int64_to_float64(q_int, s); | |
6214 | q = float64_add(q, float64_half, s); | |
6215 | q = float64_div(q, float64_256, s); | |
6216 | q = float64_sqrt(q, s); | |
6217 | q = float64_div(float64_one, q, s); | |
6218 | } | |
6219 | /* r in units of 1/256 rounded to nearest */ | |
6220 | /* s = (int)(256.0 * r + 0.5); */ | |
6221 | ||
6222 | q = float64_mul(q, float64_256,s ); | |
6223 | q = float64_add(q, float64_half, s); | |
6224 | q_int = float64_to_int64_round_to_zero(q, s); | |
6225 | ||
6226 | /* return (double)s / 256.0;*/ | |
6227 | return float64_div(int64_to_float64(q_int, s), float64_256, s); | |
6228 | } | |
6229 | ||
c2fb418e | 6230 | float32 HELPER(rsqrte_f32)(float32 input, void *fpstp) |
4373f3ce | 6231 | { |
c2fb418e AB |
6232 | float_status *s = fpstp; |
6233 | float32 f32 = float32_squash_input_denormal(input, s); | |
6234 | uint32_t val = float32_val(f32); | |
6235 | uint32_t f32_sbit = 0x80000000 & val; | |
6236 | int32_t f32_exp = extract32(val, 23, 8); | |
6237 | uint32_t f32_frac = extract32(val, 0, 23); | |
6238 | uint64_t f64_frac; | |
6239 | uint64_t val64; | |
e07be5d2 CL |
6240 | int result_exp; |
6241 | float64 f64; | |
e07be5d2 | 6242 | |
c2fb418e AB |
6243 | if (float32_is_any_nan(f32)) { |
6244 | float32 nan = f32; | |
6245 | if (float32_is_signaling_nan(f32)) { | |
e07be5d2 | 6246 | float_raise(float_flag_invalid, s); |
c2fb418e | 6247 | nan = float32_maybe_silence_nan(f32); |
e07be5d2 | 6248 | } |
c2fb418e AB |
6249 | if (s->default_nan_mode) { |
6250 | nan = float32_default_nan; | |
43fe9bdb | 6251 | } |
c2fb418e AB |
6252 | return nan; |
6253 | } else if (float32_is_zero(f32)) { | |
e07be5d2 | 6254 | float_raise(float_flag_divbyzero, s); |
c2fb418e AB |
6255 | return float32_set_sign(float32_infinity, float32_is_neg(f32)); |
6256 | } else if (float32_is_neg(f32)) { | |
e07be5d2 CL |
6257 | float_raise(float_flag_invalid, s); |
6258 | return float32_default_nan; | |
c2fb418e | 6259 | } else if (float32_is_infinity(f32)) { |
e07be5d2 CL |
6260 | return float32_zero; |
6261 | } | |
6262 | ||
c2fb418e | 6263 | /* Scale and normalize to a double-precision value between 0.25 and 1.0, |
e07be5d2 | 6264 | * preserving the parity of the exponent. */ |
c2fb418e AB |
6265 | |
6266 | f64_frac = ((uint64_t) f32_frac) << 29; | |
6267 | if (f32_exp == 0) { | |
6268 | while (extract64(f64_frac, 51, 1) == 0) { | |
6269 | f64_frac = f64_frac << 1; | |
6270 | f32_exp = f32_exp-1; | |
6271 | } | |
6272 | f64_frac = extract64(f64_frac, 0, 51) << 1; | |
6273 | } | |
6274 | ||
6275 | if (extract64(f32_exp, 0, 1) == 0) { | |
6276 | f64 = make_float64(((uint64_t) f32_sbit) << 32 | |
e07be5d2 | 6277 | | (0x3feULL << 52) |
c2fb418e | 6278 | | f64_frac); |
e07be5d2 | 6279 | } else { |
c2fb418e | 6280 | f64 = make_float64(((uint64_t) f32_sbit) << 32 |
e07be5d2 | 6281 | | (0x3fdULL << 52) |
c2fb418e | 6282 | | f64_frac); |
e07be5d2 CL |
6283 | } |
6284 | ||
c2fb418e | 6285 | result_exp = (380 - f32_exp) / 2; |
e07be5d2 | 6286 | |
c2fb418e | 6287 | f64 = recip_sqrt_estimate(f64, s); |
e07be5d2 CL |
6288 | |
6289 | val64 = float64_val(f64); | |
6290 | ||
26cc6abf | 6291 | val = ((result_exp & 0xff) << 23) |
e07be5d2 CL |
6292 | | ((val64 >> 29) & 0x7fffff); |
6293 | return make_float32(val); | |
4373f3ce PB |
6294 | } |
6295 | ||
c2fb418e AB |
6296 | float64 HELPER(rsqrte_f64)(float64 input, void *fpstp) |
6297 | { | |
6298 | float_status *s = fpstp; | |
6299 | float64 f64 = float64_squash_input_denormal(input, s); | |
6300 | uint64_t val = float64_val(f64); | |
6301 | uint64_t f64_sbit = 0x8000000000000000ULL & val; | |
6302 | int64_t f64_exp = extract64(val, 52, 11); | |
6303 | uint64_t f64_frac = extract64(val, 0, 52); | |
6304 | int64_t result_exp; | |
6305 | uint64_t result_frac; | |
6306 | ||
6307 | if (float64_is_any_nan(f64)) { | |
6308 | float64 nan = f64; | |
6309 | if (float64_is_signaling_nan(f64)) { | |
6310 | float_raise(float_flag_invalid, s); | |
6311 | nan = float64_maybe_silence_nan(f64); | |
6312 | } | |
6313 | if (s->default_nan_mode) { | |
6314 | nan = float64_default_nan; | |
6315 | } | |
6316 | return nan; | |
6317 | } else if (float64_is_zero(f64)) { | |
6318 | float_raise(float_flag_divbyzero, s); | |
6319 | return float64_set_sign(float64_infinity, float64_is_neg(f64)); | |
6320 | } else if (float64_is_neg(f64)) { | |
6321 | float_raise(float_flag_invalid, s); | |
6322 | return float64_default_nan; | |
6323 | } else if (float64_is_infinity(f64)) { | |
6324 | return float64_zero; | |
6325 | } | |
6326 | ||
6327 | /* Scale and normalize to a double-precision value between 0.25 and 1.0, | |
6328 | * preserving the parity of the exponent. */ | |
6329 | ||
6330 | if (f64_exp == 0) { | |
6331 | while (extract64(f64_frac, 51, 1) == 0) { | |
6332 | f64_frac = f64_frac << 1; | |
6333 | f64_exp = f64_exp - 1; | |
6334 | } | |
6335 | f64_frac = extract64(f64_frac, 0, 51) << 1; | |
6336 | } | |
6337 | ||
6338 | if (extract64(f64_exp, 0, 1) == 0) { | |
6339 | f64 = make_float64(f64_sbit | |
6340 | | (0x3feULL << 52) | |
6341 | | f64_frac); | |
6342 | } else { | |
6343 | f64 = make_float64(f64_sbit | |
6344 | | (0x3fdULL << 52) | |
6345 | | f64_frac); | |
6346 | } | |
6347 | ||
6348 | result_exp = (3068 - f64_exp) / 2; | |
6349 | ||
6350 | f64 = recip_sqrt_estimate(f64, s); | |
6351 | ||
6352 | result_frac = extract64(float64_val(f64), 0, 52); | |
6353 | ||
6354 | return make_float64(f64_sbit | | |
6355 | ((result_exp & 0x7ff) << 52) | | |
6356 | result_frac); | |
6357 | } | |
6358 | ||
b6d4443a | 6359 | uint32_t HELPER(recpe_u32)(uint32_t a, void *fpstp) |
4373f3ce | 6360 | { |
b6d4443a | 6361 | float_status *s = fpstp; |
fe0e4872 CL |
6362 | float64 f64; |
6363 | ||
6364 | if ((a & 0x80000000) == 0) { | |
6365 | return 0xffffffff; | |
6366 | } | |
6367 | ||
6368 | f64 = make_float64((0x3feULL << 52) | |
6369 | | ((int64_t)(a & 0x7fffffff) << 21)); | |
6370 | ||
b6d4443a | 6371 | f64 = recip_estimate(f64, s); |
fe0e4872 CL |
6372 | |
6373 | return 0x80000000 | ((float64_val(f64) >> 21) & 0x7fffffff); | |
4373f3ce PB |
6374 | } |
6375 | ||
c2fb418e | 6376 | uint32_t HELPER(rsqrte_u32)(uint32_t a, void *fpstp) |
4373f3ce | 6377 | { |
c2fb418e | 6378 | float_status *fpst = fpstp; |
e07be5d2 CL |
6379 | float64 f64; |
6380 | ||
6381 | if ((a & 0xc0000000) == 0) { | |
6382 | return 0xffffffff; | |
6383 | } | |
6384 | ||
6385 | if (a & 0x80000000) { | |
6386 | f64 = make_float64((0x3feULL << 52) | |
6387 | | ((uint64_t)(a & 0x7fffffff) << 21)); | |
6388 | } else { /* bits 31-30 == '01' */ | |
6389 | f64 = make_float64((0x3fdULL << 52) | |
6390 | | ((uint64_t)(a & 0x3fffffff) << 22)); | |
6391 | } | |
6392 | ||
c2fb418e | 6393 | f64 = recip_sqrt_estimate(f64, fpst); |
e07be5d2 CL |
6394 | |
6395 | return 0x80000000 | ((float64_val(f64) >> 21) & 0x7fffffff); | |
4373f3ce | 6396 | } |
fe1479c3 | 6397 | |
da97f52c PM |
6398 | /* VFPv4 fused multiply-accumulate */ |
6399 | float32 VFP_HELPER(muladd, s)(float32 a, float32 b, float32 c, void *fpstp) | |
6400 | { | |
6401 | float_status *fpst = fpstp; | |
6402 | return float32_muladd(a, b, c, 0, fpst); | |
6403 | } | |
6404 | ||
6405 | float64 VFP_HELPER(muladd, d)(float64 a, float64 b, float64 c, void *fpstp) | |
6406 | { | |
6407 | float_status *fpst = fpstp; | |
6408 | return float64_muladd(a, b, c, 0, fpst); | |
6409 | } | |
d9b0848d PM |
6410 | |
6411 | /* ARMv8 round to integral */ | |
6412 | float32 HELPER(rints_exact)(float32 x, void *fp_status) | |
6413 | { | |
6414 | return float32_round_to_int(x, fp_status); | |
6415 | } | |
6416 | ||
6417 | float64 HELPER(rintd_exact)(float64 x, void *fp_status) | |
6418 | { | |
6419 | return float64_round_to_int(x, fp_status); | |
6420 | } | |
6421 | ||
6422 | float32 HELPER(rints)(float32 x, void *fp_status) | |
6423 | { | |
6424 | int old_flags = get_float_exception_flags(fp_status), new_flags; | |
6425 | float32 ret; | |
6426 | ||
6427 | ret = float32_round_to_int(x, fp_status); | |
6428 | ||
6429 | /* Suppress any inexact exceptions the conversion produced */ | |
6430 | if (!(old_flags & float_flag_inexact)) { | |
6431 | new_flags = get_float_exception_flags(fp_status); | |
6432 | set_float_exception_flags(new_flags & ~float_flag_inexact, fp_status); | |
6433 | } | |
6434 | ||
6435 | return ret; | |
6436 | } | |
6437 | ||
6438 | float64 HELPER(rintd)(float64 x, void *fp_status) | |
6439 | { | |
6440 | int old_flags = get_float_exception_flags(fp_status), new_flags; | |
6441 | float64 ret; | |
6442 | ||
6443 | ret = float64_round_to_int(x, fp_status); | |
6444 | ||
6445 | new_flags = get_float_exception_flags(fp_status); | |
6446 | ||
6447 | /* Suppress any inexact exceptions the conversion produced */ | |
6448 | if (!(old_flags & float_flag_inexact)) { | |
6449 | new_flags = get_float_exception_flags(fp_status); | |
6450 | set_float_exception_flags(new_flags & ~float_flag_inexact, fp_status); | |
6451 | } | |
6452 | ||
6453 | return ret; | |
6454 | } | |
9972da66 WN |
6455 | |
6456 | /* Convert ARM rounding mode to softfloat */ | |
6457 | int arm_rmode_to_sf(int rmode) | |
6458 | { | |
6459 | switch (rmode) { | |
6460 | case FPROUNDING_TIEAWAY: | |
6461 | rmode = float_round_ties_away; | |
6462 | break; | |
6463 | case FPROUNDING_ODD: | |
6464 | /* FIXME: add support for TIEAWAY and ODD */ | |
6465 | qemu_log_mask(LOG_UNIMP, "arm: unimplemented rounding mode: %d\n", | |
6466 | rmode); | |
6467 | case FPROUNDING_TIEEVEN: | |
6468 | default: | |
6469 | rmode = float_round_nearest_even; | |
6470 | break; | |
6471 | case FPROUNDING_POSINF: | |
6472 | rmode = float_round_up; | |
6473 | break; | |
6474 | case FPROUNDING_NEGINF: | |
6475 | rmode = float_round_down; | |
6476 | break; | |
6477 | case FPROUNDING_ZERO: | |
6478 | rmode = float_round_to_zero; | |
6479 | break; | |
6480 | } | |
6481 | return rmode; | |
6482 | } | |
eb0ecd5a | 6483 | |
aa633469 PM |
6484 | /* CRC helpers. |
6485 | * The upper bytes of val (above the number specified by 'bytes') must have | |
6486 | * been zeroed out by the caller. | |
6487 | */ | |
eb0ecd5a WN |
6488 | uint32_t HELPER(crc32)(uint32_t acc, uint32_t val, uint32_t bytes) |
6489 | { | |
6490 | uint8_t buf[4]; | |
6491 | ||
aa633469 | 6492 | stl_le_p(buf, val); |
eb0ecd5a WN |
6493 | |
6494 | /* zlib crc32 converts the accumulator and output to one's complement. */ | |
6495 | return crc32(acc ^ 0xffffffff, buf, bytes) ^ 0xffffffff; | |
6496 | } | |
6497 | ||
6498 | uint32_t HELPER(crc32c)(uint32_t acc, uint32_t val, uint32_t bytes) | |
6499 | { | |
6500 | uint8_t buf[4]; | |
6501 | ||
aa633469 | 6502 | stl_le_p(buf, val); |
eb0ecd5a WN |
6503 | |
6504 | /* Linux crc32c converts the output to one's complement. */ | |
6505 | return crc32c(acc, buf, bytes) ^ 0xffffffff; | |
6506 | } |