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target-arm: implement Thumb-2 exception return
[mirror_qemu.git] / target-arm / helper.c
CommitLineData
b5ff1b31
FB		 1#include <stdio.h>
2#include <stdlib.h>
3#include <string.h>
4
5#include "cpu.h"
6#include "exec-all.h"
9ee6e8bb 7#include "gdbstub.h"
b26eefb6 8#include "helpers.h"
ca10f867 9#include "qemu-common.h"
7bbcb0af 10#include "host-utils.h"
9ee6e8bb 11
10055562
PB		 12static uint32_t cortexa9_cp15_c0_c1[8] =
13{ 0x1031, 0x11, 0x000, 0, 0x00100103, 0x20000000, 0x01230000, 0x00002111 };
14
15static uint32_t cortexa9_cp15_c0_c2[8] =
16{ 0x00101111, 0x13112111, 0x21232041, 0x11112131, 0x00111142, 0, 0, 0 };
17
9ee6e8bb
PB		 18static uint32_t cortexa8_cp15_c0_c1[8] =
19{ 0x1031, 0x11, 0x400, 0, 0x31100003, 0x20000000, 0x01202000, 0x11 };
20
21static uint32_t cortexa8_cp15_c0_c2[8] =
22{ 0x00101111, 0x12112111, 0x21232031, 0x11112131, 0x00111142, 0, 0, 0 };
23
24static uint32_t mpcore_cp15_c0_c1[8] =
25{ 0x111, 0x1, 0, 0x2, 0x01100103, 0x10020302, 0x01222000, 0 };
26
27static uint32_t mpcore_cp15_c0_c2[8] =
28{ 0x00100011, 0x12002111, 0x11221011, 0x01102131, 0x141, 0, 0, 0 };
29
30static uint32_t arm1136_cp15_c0_c1[8] =
31{ 0x111, 0x1, 0x2, 0x3, 0x01130003, 0x10030302, 0x01222110, 0 };
32
33static uint32_t arm1136_cp15_c0_c2[8] =
34{ 0x00140011, 0x12002111, 0x11231111, 0x01102131, 0x141, 0, 0, 0 };
b5ff1b31 35
aaed909a
FB		 36static uint32_t cpu_arm_find_by_name(const char *name);
37
f3d6b95e
PB		 38static inline void set_feature(CPUARMState *env, int feature)
39{
40 env->features |= 1u << feature;
41}
42
43static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
44{
45 env->cp15.c0_cpuid = id;
46 switch (id) {
47 case ARM_CPUID_ARM926:
48 set_feature(env, ARM_FEATURE_VFP);
49 env->vfp.xregs[ARM_VFP_FPSID] = 0x41011090;
c1713132 50 env->cp15.c0_cachetype = 0x1dd20d2;
610c3c8a 51 env->cp15.c1_sys = 0x00090078;
f3d6b95e 52 break;
ce819861
PB		 53 case ARM_CPUID_ARM946:
54 set_feature(env, ARM_FEATURE_MPU);
55 env->cp15.c0_cachetype = 0x0f004006;
610c3c8a 56 env->cp15.c1_sys = 0x00000078;
ce819861 57 break;
f3d6b95e
PB		 58 case ARM_CPUID_ARM1026:
59 set_feature(env, ARM_FEATURE_VFP);
60 set_feature(env, ARM_FEATURE_AUXCR);
61 env->vfp.xregs[ARM_VFP_FPSID] = 0x410110a0;
c1713132 62 env->cp15.c0_cachetype = 0x1dd20d2;
610c3c8a 63 env->cp15.c1_sys = 0x00090078;
c1713132 64 break;
827df9f3 65 case ARM_CPUID_ARM1136_R2:
9ee6e8bb
PB		 66 case ARM_CPUID_ARM1136:
67 set_feature(env, ARM_FEATURE_V6);
68 set_feature(env, ARM_FEATURE_VFP);
69 set_feature(env, ARM_FEATURE_AUXCR);
70 env->vfp.xregs[ARM_VFP_FPSID] = 0x410120b4;
71 env->vfp.xregs[ARM_VFP_MVFR0] = 0x11111111;
72 env->vfp.xregs[ARM_VFP_MVFR1] = 0x00000000;
73 memcpy(env->cp15.c0_c1, arm1136_cp15_c0_c1, 8 * sizeof(uint32_t));
22478e79 74 memcpy(env->cp15.c0_c2, arm1136_cp15_c0_c2, 8 * sizeof(uint32_t));
9ee6e8bb
PB		 75 env->cp15.c0_cachetype = 0x1dd20d2;
76 break;
77 case ARM_CPUID_ARM11MPCORE:
78 set_feature(env, ARM_FEATURE_V6);
79 set_feature(env, ARM_FEATURE_V6K);
80 set_feature(env, ARM_FEATURE_VFP);
81 set_feature(env, ARM_FEATURE_AUXCR);
82 env->vfp.xregs[ARM_VFP_FPSID] = 0x410120b4;
83 env->vfp.xregs[ARM_VFP_MVFR0] = 0x11111111;
84 env->vfp.xregs[ARM_VFP_MVFR1] = 0x00000000;
85 memcpy(env->cp15.c0_c1, mpcore_cp15_c0_c1, 8 * sizeof(uint32_t));
22478e79 86 memcpy(env->cp15.c0_c2, mpcore_cp15_c0_c2, 8 * sizeof(uint32_t));
9ee6e8bb
PB		 87 env->cp15.c0_cachetype = 0x1dd20d2;
88 break;
89 case ARM_CPUID_CORTEXA8:
90 set_feature(env, ARM_FEATURE_V6);
91 set_feature(env, ARM_FEATURE_V6K);
92 set_feature(env, ARM_FEATURE_V7);
93 set_feature(env, ARM_FEATURE_AUXCR);
94 set_feature(env, ARM_FEATURE_THUMB2);
95 set_feature(env, ARM_FEATURE_VFP);
96 set_feature(env, ARM_FEATURE_VFP3);
97 set_feature(env, ARM_FEATURE_NEON);
fe1479c3 98 set_feature(env, ARM_FEATURE_THUMB2EE);
9ee6e8bb
PB		 99 env->vfp.xregs[ARM_VFP_FPSID] = 0x410330c0;
100 env->vfp.xregs[ARM_VFP_MVFR0] = 0x11110222;
101 env->vfp.xregs[ARM_VFP_MVFR1] = 0x00011100;
102 memcpy(env->cp15.c0_c1, cortexa8_cp15_c0_c1, 8 * sizeof(uint32_t));
22478e79 103 memcpy(env->cp15.c0_c2, cortexa8_cp15_c0_c2, 8 * sizeof(uint32_t));
a49ea279
PB		 104 env->cp15.c0_cachetype = 0x82048004;
105 env->cp15.c0_clid = (1 << 27) | (2 << 24) | 3;
106 env->cp15.c0_ccsid[0] = 0xe007e01a; /* 16k L1 dcache. */
107 env->cp15.c0_ccsid[1] = 0x2007e01a; /* 16k L1 icache. */
108 env->cp15.c0_ccsid[2] = 0xf0000000; /* No L2 icache. */
9ee6e8bb 109 break;
10055562
PB		 110 case ARM_CPUID_CORTEXA9:
111 set_feature(env, ARM_FEATURE_V6);
112 set_feature(env, ARM_FEATURE_V6K);
113 set_feature(env, ARM_FEATURE_V7);
114 set_feature(env, ARM_FEATURE_AUXCR);
115 set_feature(env, ARM_FEATURE_THUMB2);
116 set_feature(env, ARM_FEATURE_VFP);
117 set_feature(env, ARM_FEATURE_VFP3);
118 set_feature(env, ARM_FEATURE_VFP_FP16);
119 set_feature(env, ARM_FEATURE_NEON);
120 set_feature(env, ARM_FEATURE_THUMB2EE);
121 env->vfp.xregs[ARM_VFP_FPSID] = 0x41034000; /* Guess */
122 env->vfp.xregs[ARM_VFP_MVFR0] = 0x11110222;
123 env->vfp.xregs[ARM_VFP_MVFR1] = 0x01111111;
124 memcpy(env->cp15.c0_c1, cortexa9_cp15_c0_c1, 8 * sizeof(uint32_t));
125 memcpy(env->cp15.c0_c2, cortexa9_cp15_c0_c2, 8 * sizeof(uint32_t));
126 env->cp15.c0_cachetype = 0x80038003;
127 env->cp15.c0_clid = (1 << 27) | (1 << 24) | 3;
128 env->cp15.c0_ccsid[0] = 0xe00fe015; /* 16k L1 dcache. */
129 env->cp15.c0_ccsid[1] = 0x200fe015; /* 16k L1 icache. */
130 break;
9ee6e8bb
PB		 131 case ARM_CPUID_CORTEXM3:
132 set_feature(env, ARM_FEATURE_V6);
133 set_feature(env, ARM_FEATURE_THUMB2);
134 set_feature(env, ARM_FEATURE_V7);
135 set_feature(env, ARM_FEATURE_M);
136 set_feature(env, ARM_FEATURE_DIV);
137 break;
138 case ARM_CPUID_ANY: /* For userspace emulation. */
139 set_feature(env, ARM_FEATURE_V6);
140 set_feature(env, ARM_FEATURE_V6K);
141 set_feature(env, ARM_FEATURE_V7);
142 set_feature(env, ARM_FEATURE_THUMB2);
143 set_feature(env, ARM_FEATURE_VFP);
144 set_feature(env, ARM_FEATURE_VFP3);
60011498 145 set_feature(env, ARM_FEATURE_VFP_FP16);
9ee6e8bb 146 set_feature(env, ARM_FEATURE_NEON);
fe1479c3 147 set_feature(env, ARM_FEATURE_THUMB2EE);
9ee6e8bb
PB		 148 set_feature(env, ARM_FEATURE_DIV);
149 break;
c3d2689d
AZ		 150 case ARM_CPUID_TI915T:
151 case ARM_CPUID_TI925T:
152 set_feature(env, ARM_FEATURE_OMAPCP);
153 env->cp15.c0_cpuid = ARM_CPUID_TI925T; /* Depends on wiring. */
154 env->cp15.c0_cachetype = 0x5109149;
155 env->cp15.c1_sys = 0x00000070;
156 env->cp15.c15_i_max = 0x000;
157 env->cp15.c15_i_min = 0xff0;
158 break;
c1713132
AZ		 159 case ARM_CPUID_PXA250:
160 case ARM_CPUID_PXA255:
161 case ARM_CPUID_PXA260:
162 case ARM_CPUID_PXA261:
163 case ARM_CPUID_PXA262:
164 set_feature(env, ARM_FEATURE_XSCALE);
165 /* JTAG_ID is ((id << 28) | 0x09265013) */
166 env->cp15.c0_cachetype = 0xd172172;
610c3c8a 167 env->cp15.c1_sys = 0x00000078;
c1713132
AZ		 168 break;
169 case ARM_CPUID_PXA270_A0:
170 case ARM_CPUID_PXA270_A1:
171 case ARM_CPUID_PXA270_B0:
172 case ARM_CPUID_PXA270_B1:
173 case ARM_CPUID_PXA270_C0:
174 case ARM_CPUID_PXA270_C5:
175 set_feature(env, ARM_FEATURE_XSCALE);
176 /* JTAG_ID is ((id << 28) | 0x09265013) */
18c9b560
AZ		 177 set_feature(env, ARM_FEATURE_IWMMXT);
178 env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q';
c1713132 179 env->cp15.c0_cachetype = 0xd172172;
610c3c8a 180 env->cp15.c1_sys = 0x00000078;
f3d6b95e
PB		 181 break;
182 default:
183 cpu_abort(env, "Bad CPU ID: %x\n", id);
184 break;
185 }
186}
187
40f137e1
PB		 188void cpu_reset(CPUARMState *env)
189{
f3d6b95e 190 uint32_t id;
eca1bdf4
AL		 191
192 if (qemu_loglevel_mask(CPU_LOG_RESET)) {
193 qemu_log("CPU Reset (CPU %d)\n", env->cpu_index);
194 log_cpu_state(env, 0);
195 }
196
f3d6b95e
PB		 197 id = env->cp15.c0_cpuid;
198 memset(env, 0, offsetof(CPUARMState, breakpoints));
199 if (id)
200 cpu_reset_model_id(env, id);
40f137e1
PB		 201#if defined (CONFIG_USER_ONLY)
202 env->uncached_cpsr = ARM_CPU_MODE_USR;
203 env->vfp.xregs[ARM_VFP_FPEXC] = 1 << 30;
204#else
205 /* SVC mode with interrupts disabled. */
206 env->uncached_cpsr = ARM_CPU_MODE_SVC | CPSR_A | CPSR_F | CPSR_I;
9ee6e8bb
PB		 207 /* On ARMv7-M the CPSR_I is the value of the PRIMASK register, and is
208 clear at reset. */
209 if (IS_M(env))
210 env->uncached_cpsr &= ~CPSR_I;
40f137e1 211 env->vfp.xregs[ARM_VFP_FPEXC] = 0;
b2fa1797 212 env->cp15.c2_base_mask = 0xffffc000u;
40f137e1
PB		 213#endif
214 env->regs[15] = 0;
f3d6b95e 215 tlb_flush(env, 1);
40f137e1
PB		 216}
217
56aebc89
PB		 218static int vfp_gdb_get_reg(CPUState *env, uint8_t *buf, int reg)
219{
220 int nregs;
221
222 /* VFP data registers are always little-endian. */
223 nregs = arm_feature(env, ARM_FEATURE_VFP3) ? 32 : 16;
224 if (reg < nregs) {
225 stfq_le_p(buf, env->vfp.regs[reg]);
226 return 8;
227 }
228 if (arm_feature(env, ARM_FEATURE_NEON)) {
229 /* Aliases for Q regs. */
230 nregs += 16;
231 if (reg < nregs) {
232 stfq_le_p(buf, env->vfp.regs[(reg - 32) * 2]);
233 stfq_le_p(buf + 8, env->vfp.regs[(reg - 32) * 2 + 1]);
234 return 16;
235 }
236 }
237 switch (reg - nregs) {
238 case 0: stl_p(buf, env->vfp.xregs[ARM_VFP_FPSID]); return 4;
239 case 1: stl_p(buf, env->vfp.xregs[ARM_VFP_FPSCR]); return 4;
240 case 2: stl_p(buf, env->vfp.xregs[ARM_VFP_FPEXC]); return 4;
241 }
242 return 0;
243}
244
245static int vfp_gdb_set_reg(CPUState *env, uint8_t *buf, int reg)
246{
247 int nregs;
248
249 nregs = arm_feature(env, ARM_FEATURE_VFP3) ? 32 : 16;
250 if (reg < nregs) {
251 env->vfp.regs[reg] = ldfq_le_p(buf);
252 return 8;
253 }
254 if (arm_feature(env, ARM_FEATURE_NEON)) {
255 nregs += 16;
256 if (reg < nregs) {
257 env->vfp.regs[(reg - 32) * 2] = ldfq_le_p(buf);
258 env->vfp.regs[(reg - 32) * 2 + 1] = ldfq_le_p(buf + 8);
259 return 16;
260 }
261 }
262 switch (reg - nregs) {
263 case 0: env->vfp.xregs[ARM_VFP_FPSID] = ldl_p(buf); return 4;
264 case 1: env->vfp.xregs[ARM_VFP_FPSCR] = ldl_p(buf); return 4;
71b3c3de 265 case 2: env->vfp.xregs[ARM_VFP_FPEXC] = ldl_p(buf) & (1 << 30); return 4;
56aebc89
PB		 266 }
267 return 0;
268}
269
aaed909a 270CPUARMState *cpu_arm_init(const char *cpu_model)
40f137e1
PB		 271{
272 CPUARMState *env;
aaed909a 273 uint32_t id;
b26eefb6 274 static int inited = 0;
40f137e1 275
aaed909a
FB		 276 id = cpu_arm_find_by_name(cpu_model);
277 if (id == 0)
278 return NULL;
40f137e1 279 env = qemu_mallocz(sizeof(CPUARMState));
40f137e1 280 cpu_exec_init(env);
b26eefb6
PB		 281 if (!inited) {
282 inited = 1;
283 arm_translate_init();
284 }
285
01ba9816 286 env->cpu_model_str = cpu_model;
aaed909a 287 env->cp15.c0_cpuid = id;
40f137e1 288 cpu_reset(env);
56aebc89
PB		 289 if (arm_feature(env, ARM_FEATURE_NEON)) {
290 gdb_register_coprocessor(env, vfp_gdb_get_reg, vfp_gdb_set_reg,
291 51, "arm-neon.xml", 0);
292 } else if (arm_feature(env, ARM_FEATURE_VFP3)) {
293 gdb_register_coprocessor(env, vfp_gdb_get_reg, vfp_gdb_set_reg,
294 35, "arm-vfp3.xml", 0);
295 } else if (arm_feature(env, ARM_FEATURE_VFP)) {
296 gdb_register_coprocessor(env, vfp_gdb_get_reg, vfp_gdb_set_reg,
297 19, "arm-vfp.xml", 0);
298 }
0bf46a40 299 qemu_init_vcpu(env);
40f137e1
PB		 300 return env;
301}
302
3371d272
PB		 303struct arm_cpu_t {
304 uint32_t id;
305 const char *name;
306};
307
308static const struct arm_cpu_t arm_cpu_names[] = {
309 { ARM_CPUID_ARM926, "arm926"},
ce819861 310 { ARM_CPUID_ARM946, "arm946"},
3371d272 311 { ARM_CPUID_ARM1026, "arm1026"},
9ee6e8bb 312 { ARM_CPUID_ARM1136, "arm1136"},
827df9f3 313 { ARM_CPUID_ARM1136_R2, "arm1136-r2"},
9ee6e8bb
PB		 314 { ARM_CPUID_ARM11MPCORE, "arm11mpcore"},
315 { ARM_CPUID_CORTEXM3, "cortex-m3"},
316 { ARM_CPUID_CORTEXA8, "cortex-a8"},
10055562 317 { ARM_CPUID_CORTEXA9, "cortex-a9"},
c3d2689d 318 { ARM_CPUID_TI925T, "ti925t" },
c1713132
AZ		 319 { ARM_CPUID_PXA250, "pxa250" },
320 { ARM_CPUID_PXA255, "pxa255" },
321 { ARM_CPUID_PXA260, "pxa260" },
322 { ARM_CPUID_PXA261, "pxa261" },
323 { ARM_CPUID_PXA262, "pxa262" },
324 { ARM_CPUID_PXA270, "pxa270" },
325 { ARM_CPUID_PXA270_A0, "pxa270-a0" },
326 { ARM_CPUID_PXA270_A1, "pxa270-a1" },
327 { ARM_CPUID_PXA270_B0, "pxa270-b0" },
328 { ARM_CPUID_PXA270_B1, "pxa270-b1" },
329 { ARM_CPUID_PXA270_C0, "pxa270-c0" },
330 { ARM_CPUID_PXA270_C5, "pxa270-c5" },
9ee6e8bb 331 { ARM_CPUID_ANY, "any"},
3371d272
PB		 332 { 0, NULL}
333};
334
c732abe2 335void arm_cpu_list(FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...))
5adb4839
PB		 336{
337 int i;
338
c732abe2 339 (*cpu_fprintf)(f, "Available CPUs:\n");
5adb4839 340 for (i = 0; arm_cpu_names[i].name; i++) {
c732abe2 341 (*cpu_fprintf)(f, " %s\n", arm_cpu_names[i].name);
5adb4839
PB		 342 }
343}
344
aaed909a
FB		 345/* return 0 if not found */
346static uint32_t cpu_arm_find_by_name(const char *name)
40f137e1 347{
3371d272
PB		 348 int i;
349 uint32_t id;
350
351 id = 0;
3371d272
PB		 352 for (i = 0; arm_cpu_names[i].name; i++) {
353 if (strcmp(name, arm_cpu_names[i].name) == 0) {
354 id = arm_cpu_names[i].id;
355 break;
356 }
357 }
aaed909a 358 return id;
40f137e1
PB		 359}
360
361void cpu_arm_close(CPUARMState *env)
362{
363 free(env);
364}
365
2f4a40e5
AZ		 366uint32_t cpsr_read(CPUARMState *env)
367{
368 int ZF;
6fbe23d5
PB		 369 ZF = (env->ZF == 0);
370 return env->uncached_cpsr | (env->NF & 0x80000000) | (ZF << 30) |
2f4a40e5
AZ		 371 (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27)
372 | (env->thumb << 5) | ((env->condexec_bits & 3) << 25)
373 | ((env->condexec_bits & 0xfc) << 8)
374 | (env->GE << 16);
375}
376
377void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask)
378{
2f4a40e5 379 if (mask & CPSR_NZCV) {
6fbe23d5
PB		 380 env->ZF = (~val) & CPSR_Z;
381 env->NF = val;
2f4a40e5
AZ		 382 env->CF = (val >> 29) & 1;
383 env->VF = (val << 3) & 0x80000000;
384 }
385 if (mask & CPSR_Q)
386 env->QF = ((val & CPSR_Q) != 0);
387 if (mask & CPSR_T)
388 env->thumb = ((val & CPSR_T) != 0);
389 if (mask & CPSR_IT_0_1) {
390 env->condexec_bits &= ~3;
391 env->condexec_bits |= (val >> 25) & 3;
392 }
393 if (mask & CPSR_IT_2_7) {
394 env->condexec_bits &= 3;
395 env->condexec_bits |= (val >> 8) & 0xfc;
396 }
397 if (mask & CPSR_GE) {
398 env->GE = (val >> 16) & 0xf;
399 }
400
401 if ((env->uncached_cpsr ^ val) & mask & CPSR_M) {
402 switch_mode(env, val & CPSR_M);
403 }
404 mask &= ~CACHED_CPSR_BITS;
405 env->uncached_cpsr = (env->uncached_cpsr & ~mask) | (val & mask);
406}
407
b26eefb6
PB		 408/* Sign/zero extend */
409uint32_t HELPER(sxtb16)(uint32_t x)
410{
411 uint32_t res;
412 res = (uint16_t)(int8_t)x;
413 res |= (uint32_t)(int8_t)(x >> 16) << 16;
414 return res;
415}
416
417uint32_t HELPER(uxtb16)(uint32_t x)
418{
419 uint32_t res;
420 res = (uint16_t)(uint8_t)x;
421 res |= (uint32_t)(uint8_t)(x >> 16) << 16;
422 return res;
423}
424
f51bbbfe
PB		 425uint32_t HELPER(clz)(uint32_t x)
426{
7bbcb0af 427 return clz32(x);
f51bbbfe
PB		 428}
429
3670669c
PB		 430int32_t HELPER(sdiv)(int32_t num, int32_t den)
431{
432 if (den == 0)
433 return 0;
686eeb93
AJ		 434 if (num == INT_MIN && den == -1)
435 return INT_MIN;
3670669c
PB		 436 return num / den;
437}
438
439uint32_t HELPER(udiv)(uint32_t num, uint32_t den)
440{
441 if (den == 0)
442 return 0;
443 return num / den;
444}
445
446uint32_t HELPER(rbit)(uint32_t x)
447{
448 x = ((x & 0xff000000) >> 24)
449 | ((x & 0x00ff0000) >> 8)
450 | ((x & 0x0000ff00) << 8)
451 | ((x & 0x000000ff) << 24);
452 x = ((x & 0xf0f0f0f0) >> 4)
453 | ((x & 0x0f0f0f0f) << 4);
454 x = ((x & 0x88888888) >> 3)
455 | ((x & 0x44444444) >> 1)
456 | ((x & 0x22222222) << 1)
457 | ((x & 0x11111111) << 3);
458 return x;
459}
460
ad69471c
PB		 461uint32_t HELPER(abs)(uint32_t x)
462{
463 return ((int32_t)x < 0) ? -x : x;
464}
465
5fafdf24 466#if defined(CONFIG_USER_ONLY)
b5ff1b31
FB		 467
468void do_interrupt (CPUState *env)
469{
470 env->exception_index = -1;
471}
472
473int cpu_arm_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
6ebbf390 474 int mmu_idx, int is_softmmu)
b5ff1b31
FB		 475{
476 if (rw == 2) {
477 env->exception_index = EXCP_PREFETCH_ABORT;
478 env->cp15.c6_insn = address;
479 } else {
480 env->exception_index = EXCP_DATA_ABORT;
481 env->cp15.c6_data = address;
482 }
483 return 1;
484}
485
c227f099 486target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
b5ff1b31
FB		 487{
488 return addr;
489}
490
491/* These should probably raise undefined insn exceptions. */
8984bd2e 492void HELPER(set_cp)(CPUState *env, uint32_t insn, uint32_t val)
c1713132
AZ		 493{
494 int op1 = (insn >> 8) & 0xf;
495 cpu_abort(env, "cp%i insn %08x\n", op1, insn);
496 return;
497}
498
8984bd2e 499uint32_t HELPER(get_cp)(CPUState *env, uint32_t insn)
c1713132
AZ		 500{
501 int op1 = (insn >> 8) & 0xf;
502 cpu_abort(env, "cp%i insn %08x\n", op1, insn);
503 return 0;
504}
505
8984bd2e 506void HELPER(set_cp15)(CPUState *env, uint32_t insn, uint32_t val)
b5ff1b31
FB		 507{
508 cpu_abort(env, "cp15 insn %08x\n", insn);
509}
510
8984bd2e 511uint32_t HELPER(get_cp15)(CPUState *env, uint32_t insn)
b5ff1b31
FB		 512{
513 cpu_abort(env, "cp15 insn %08x\n", insn);
b5ff1b31
FB		 514}
515
9ee6e8bb 516/* These should probably raise undefined insn exceptions. */
8984bd2e 517void HELPER(v7m_msr)(CPUState *env, uint32_t reg, uint32_t val)
9ee6e8bb
PB		 518{
519 cpu_abort(env, "v7m_mrs %d\n", reg);
520}
521
8984bd2e 522uint32_t HELPER(v7m_mrs)(CPUState *env, uint32_t reg)
9ee6e8bb
PB		 523{
524 cpu_abort(env, "v7m_mrs %d\n", reg);
525 return 0;
526}
527
b5ff1b31
FB		 528void switch_mode(CPUState *env, int mode)
529{
530 if (mode != ARM_CPU_MODE_USR)
531 cpu_abort(env, "Tried to switch out of user mode\n");
532}
533
b0109805 534void HELPER(set_r13_banked)(CPUState *env, uint32_t mode, uint32_t val)
9ee6e8bb
PB		 535{
536 cpu_abort(env, "banked r13 write\n");
537}
538
b0109805 539uint32_t HELPER(get_r13_banked)(CPUState *env, uint32_t mode)
9ee6e8bb
PB		 540{
541 cpu_abort(env, "banked r13 read\n");
542 return 0;
543}
544
b5ff1b31
FB		 545#else
546
8e71621f
PB		 547extern int semihosting_enabled;
548
b5ff1b31
FB		 549/* Map CPU modes onto saved register banks. */
550static inline int bank_number (int mode)
551{
552 switch (mode) {
553 case ARM_CPU_MODE_USR:
554 case ARM_CPU_MODE_SYS:
555 return 0;
556 case ARM_CPU_MODE_SVC:
557 return 1;
558 case ARM_CPU_MODE_ABT:
559 return 2;
560 case ARM_CPU_MODE_UND:
561 return 3;
562 case ARM_CPU_MODE_IRQ:
563 return 4;
564 case ARM_CPU_MODE_FIQ:
565 return 5;
566 }
567 cpu_abort(cpu_single_env, "Bad mode %x\n", mode);
568 return -1;
569}
570
571void switch_mode(CPUState *env, int mode)
572{
573 int old_mode;
574 int i;
575
576 old_mode = env->uncached_cpsr & CPSR_M;
577 if (mode == old_mode)
578 return;
579
580 if (old_mode == ARM_CPU_MODE_FIQ) {
581 memcpy (env->fiq_regs, env->regs + 8, 5 * sizeof(uint32_t));
8637c67f 582 memcpy (env->regs + 8, env->usr_regs, 5 * sizeof(uint32_t));
b5ff1b31
FB		 583 } else if (mode == ARM_CPU_MODE_FIQ) {
584 memcpy (env->usr_regs, env->regs + 8, 5 * sizeof(uint32_t));
8637c67f 585 memcpy (env->regs + 8, env->fiq_regs, 5 * sizeof(uint32_t));
b5ff1b31
FB		 586 }
587
588 i = bank_number(old_mode);
589 env->banked_r13[i] = env->regs[13];
590 env->banked_r14[i] = env->regs[14];
591 env->banked_spsr[i] = env->spsr;
592
593 i = bank_number(mode);
594 env->regs[13] = env->banked_r13[i];
595 env->regs[14] = env->banked_r14[i];
596 env->spsr = env->banked_spsr[i];
597}
598
9ee6e8bb
PB		 599static void v7m_push(CPUARMState *env, uint32_t val)
600{
601 env->regs[13] -= 4;
602 stl_phys(env->regs[13], val);
603}
604
605static uint32_t v7m_pop(CPUARMState *env)
606{
607 uint32_t val;
608 val = ldl_phys(env->regs[13]);
609 env->regs[13] += 4;
610 return val;
611}
612
613/* Switch to V7M main or process stack pointer. */
614static void switch_v7m_sp(CPUARMState *env, int process)
615{
616 uint32_t tmp;
617 if (env->v7m.current_sp != process) {
618 tmp = env->v7m.other_sp;
619 env->v7m.other_sp = env->regs[13];
620 env->regs[13] = tmp;
621 env->v7m.current_sp = process;
622 }
623}
624
625static void do_v7m_exception_exit(CPUARMState *env)
626{
627 uint32_t type;
628 uint32_t xpsr;
629
630 type = env->regs[15];
631 if (env->v7m.exception != 0)
632 armv7m_nvic_complete_irq(env->v7m.nvic, env->v7m.exception);
633
634 /* Switch to the target stack. */
635 switch_v7m_sp(env, (type & 4) != 0);
636 /* Pop registers. */
637 env->regs[0] = v7m_pop(env);
638 env->regs[1] = v7m_pop(env);
639 env->regs[2] = v7m_pop(env);
640 env->regs[3] = v7m_pop(env);
641 env->regs[12] = v7m_pop(env);
642 env->regs[14] = v7m_pop(env);
643 env->regs[15] = v7m_pop(env);
644 xpsr = v7m_pop(env);
645 xpsr_write(env, xpsr, 0xfffffdff);
646 /* Undo stack alignment. */
647 if (xpsr & 0x200)
648 env->regs[13] |= 4;
649 /* ??? The exception return type specifies Thread/Handler mode. However
650 this is also implied by the xPSR value. Not sure what to do
651 if there is a mismatch. */
652 /* ??? Likewise for mismatches between the CONTROL register and the stack
653 pointer. */
654}
655
2b3ea315 656static void do_interrupt_v7m(CPUARMState *env)
9ee6e8bb
PB		 657{
658 uint32_t xpsr = xpsr_read(env);
659 uint32_t lr;
660 uint32_t addr;
661
662 lr = 0xfffffff1;
663 if (env->v7m.current_sp)
664 lr |= 4;
665 if (env->v7m.exception == 0)
666 lr |= 8;
667
668 /* For exceptions we just mark as pending on the NVIC, and let that
669 handle it. */
670 /* TODO: Need to escalate if the current priority is higher than the
671 one we're raising. */
672 switch (env->exception_index) {
673 case EXCP_UDEF:
674 armv7m_nvic_set_pending(env->v7m.nvic, ARMV7M_EXCP_USAGE);
675 return;
676 case EXCP_SWI:
677 env->regs[15] += 2;
678 armv7m_nvic_set_pending(env->v7m.nvic, ARMV7M_EXCP_SVC);
679 return;
680 case EXCP_PREFETCH_ABORT:
681 case EXCP_DATA_ABORT:
682 armv7m_nvic_set_pending(env->v7m.nvic, ARMV7M_EXCP_MEM);
683 return;
684 case EXCP_BKPT:
2ad207d4
PB		 685 if (semihosting_enabled) {
686 int nr;
687 nr = lduw_code(env->regs[15]) & 0xff;
688 if (nr == 0xab) {
689 env->regs[15] += 2;
690 env->regs[0] = do_arm_semihosting(env);
691 return;
692 }
693 }
9ee6e8bb
PB		 694 armv7m_nvic_set_pending(env->v7m.nvic, ARMV7M_EXCP_DEBUG);
695 return;
696 case EXCP_IRQ:
697 env->v7m.exception = armv7m_nvic_acknowledge_irq(env->v7m.nvic);
698 break;
699 case EXCP_EXCEPTION_EXIT:
700 do_v7m_exception_exit(env);
701 return;
702 default:
703 cpu_abort(env, "Unhandled exception 0x%x\n", env->exception_index);
704 return; /* Never happens. Keep compiler happy. */
705 }
706
707 /* Align stack pointer. */
708 /* ??? Should only do this if Configuration Control Register
709 STACKALIGN bit is set. */
710 if (env->regs[13] & 4) {
ab19b0ec 711 env->regs[13] -= 4;
9ee6e8bb
PB		 712 xpsr |= 0x200;
713 }
6c95676b 714 /* Switch to the handler mode. */
9ee6e8bb
PB		 715 v7m_push(env, xpsr);
716 v7m_push(env, env->regs[15]);
717 v7m_push(env, env->regs[14]);
718 v7m_push(env, env->regs[12]);
719 v7m_push(env, env->regs[3]);
720 v7m_push(env, env->regs[2]);
721 v7m_push(env, env->regs[1]);
722 v7m_push(env, env->regs[0]);
723 switch_v7m_sp(env, 0);
724 env->uncached_cpsr &= ~CPSR_IT;
725 env->regs[14] = lr;
726 addr = ldl_phys(env->v7m.vecbase + env->v7m.exception * 4);
727 env->regs[15] = addr & 0xfffffffe;
728 env->thumb = addr & 1;
729}
730
b5ff1b31
FB		 731/* Handle a CPU exception. */
732void do_interrupt(CPUARMState *env)
733{
734 uint32_t addr;
735 uint32_t mask;
736 int new_mode;
737 uint32_t offset;
738
9ee6e8bb
PB		 739 if (IS_M(env)) {
740 do_interrupt_v7m(env);
741 return;
742 }
b5ff1b31
FB		 743 /* TODO: Vectored interrupt controller. */
744 switch (env->exception_index) {
745 case EXCP_UDEF:
746 new_mode = ARM_CPU_MODE_UND;
747 addr = 0x04;
748 mask = CPSR_I;
749 if (env->thumb)
750 offset = 2;
751 else
752 offset = 4;
753 break;
754 case EXCP_SWI:
8e71621f
PB		 755 if (semihosting_enabled) {
756 /* Check for semihosting interrupt. */
757 if (env->thumb) {
758 mask = lduw_code(env->regs[15] - 2) & 0xff;
759 } else {
760 mask = ldl_code(env->regs[15] - 4) & 0xffffff;
761 }
762 /* Only intercept calls from privileged modes, to provide some
763 semblance of security. */
764 if (((mask == 0x123456 && !env->thumb)
765 || (mask == 0xab && env->thumb))
766 && (env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR) {
767 env->regs[0] = do_arm_semihosting(env);
768 return;
769 }
770 }
b5ff1b31
FB		 771 new_mode = ARM_CPU_MODE_SVC;
772 addr = 0x08;
773 mask = CPSR_I;
601d70b9 774 /* The PC already points to the next instruction. */
b5ff1b31
FB		 775 offset = 0;
776 break;
06c949e6 777 case EXCP_BKPT:
9ee6e8bb 778 /* See if this is a semihosting syscall. */
2ad207d4 779 if (env->thumb && semihosting_enabled) {
9ee6e8bb
PB		 780 mask = lduw_code(env->regs[15]) & 0xff;
781 if (mask == 0xab
782 && (env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR) {
783 env->regs[15] += 2;
784 env->regs[0] = do_arm_semihosting(env);
785 return;
786 }
787 }
788 /* Fall through to prefetch abort. */
789 case EXCP_PREFETCH_ABORT:
b5ff1b31
FB		 790 new_mode = ARM_CPU_MODE_ABT;
791 addr = 0x0c;
792 mask = CPSR_A | CPSR_I;
793 offset = 4;
794 break;
795 case EXCP_DATA_ABORT:
796 new_mode = ARM_CPU_MODE_ABT;
797 addr = 0x10;
798 mask = CPSR_A | CPSR_I;
799 offset = 8;
800 break;
801 case EXCP_IRQ:
802 new_mode = ARM_CPU_MODE_IRQ;
803 addr = 0x18;
804 /* Disable IRQ and imprecise data aborts. */
805 mask = CPSR_A | CPSR_I;
806 offset = 4;
807 break;
808 case EXCP_FIQ:
809 new_mode = ARM_CPU_MODE_FIQ;
810 addr = 0x1c;
811 /* Disable FIQ, IRQ and imprecise data aborts. */
812 mask = CPSR_A | CPSR_I | CPSR_F;
813 offset = 4;
814 break;
815 default:
816 cpu_abort(env, "Unhandled exception 0x%x\n", env->exception_index);
817 return; /* Never happens. Keep compiler happy. */
818 }
819 /* High vectors. */
820 if (env->cp15.c1_sys & (1 << 13)) {
821 addr += 0xffff0000;
822 }
823 switch_mode (env, new_mode);
824 env->spsr = cpsr_read(env);
9ee6e8bb
PB		 825 /* Clear IT bits. */
826 env->condexec_bits = 0;
6d7e6326 827 /* Switch to the new mode, and switch to Arm mode. */
b5ff1b31 828 /* ??? Thumb interrupt handlers not implemented. */
6d7e6326 829 env->uncached_cpsr = (env->uncached_cpsr & ~CPSR_M) | new_mode;
b5ff1b31 830 env->uncached_cpsr |= mask;
6d7e6326 831 env->thumb = 0;
b5ff1b31
FB		 832 env->regs[14] = env->regs[15] + offset;
833 env->regs[15] = addr;
834 env->interrupt_request |= CPU_INTERRUPT_EXITTB;
835}
836
837/* Check section/page access permissions.
838 Returns the page protection flags, or zero if the access is not
839 permitted. */
840static inline int check_ap(CPUState *env, int ap, int domain, int access_type,
841 int is_user)
842{
9ee6e8bb
PB		 843 int prot_ro;
844
b5ff1b31
FB		 845 if (domain == 3)
846 return PAGE_READ | PAGE_WRITE;
847
9ee6e8bb
PB		 848 if (access_type == 1)
849 prot_ro = 0;
850 else
851 prot_ro = PAGE_READ;
852
b5ff1b31
FB		 853 switch (ap) {
854 case 0:
78600320 855 if (access_type == 1)
b5ff1b31
FB		 856 return 0;
857 switch ((env->cp15.c1_sys >> 8) & 3) {
858 case 1:
859 return is_user ? 0 : PAGE_READ;
860 case 2:
861 return PAGE_READ;
862 default:
863 return 0;
864 }
865 case 1:
866 return is_user ? 0 : PAGE_READ | PAGE_WRITE;
867 case 2:
868 if (is_user)
9ee6e8bb 869 return prot_ro;
b5ff1b31
FB		 870 else
871 return PAGE_READ | PAGE_WRITE;
872 case 3:
873 return PAGE_READ | PAGE_WRITE;
d4934d18 874 case 4: /* Reserved. */
9ee6e8bb
PB		 875 return 0;
876 case 5:
877 return is_user ? 0 : prot_ro;
878 case 6:
879 return prot_ro;
d4934d18
PB		 880 case 7:
881 if (!arm_feature (env, ARM_FEATURE_V7))
882 return 0;
883 return prot_ro;
b5ff1b31
FB		 884 default:
885 abort();
886 }
887}
888
b2fa1797
PB		 889static uint32_t get_level1_table_address(CPUState *env, uint32_t address)
890{
891 uint32_t table;
892
893 if (address & env->cp15.c2_mask)
894 table = env->cp15.c2_base1 & 0xffffc000;
895 else
896 table = env->cp15.c2_base0 & env->cp15.c2_base_mask;
897
898 table |= (address >> 18) & 0x3ffc;
899 return table;
900}
901
9ee6e8bb
PB		 902static int get_phys_addr_v5(CPUState *env, uint32_t address, int access_type,
903 int is_user, uint32_t *phys_ptr, int *prot)
b5ff1b31
FB		 904{
905 int code;
906 uint32_t table;
907 uint32_t desc;
908 int type;
909 int ap;
910 int domain;
911 uint32_t phys_addr;
912
9ee6e8bb
PB		 913 /* Pagetable walk. */
914 /* Lookup l1 descriptor. */
b2fa1797 915 table = get_level1_table_address(env, address);
9ee6e8bb
PB		 916 desc = ldl_phys(table);
917 type = (desc & 3);
918 domain = (env->cp15.c3 >> ((desc >> 4) & 0x1e)) & 3;
919 if (type == 0) {
601d70b9 920 /* Section translation fault. */
9ee6e8bb
PB		 921 code = 5;
922 goto do_fault;
923 }
924 if (domain == 0 || domain == 2) {
925 if (type == 2)
926 code = 9; /* Section domain fault. */
927 else
928 code = 11; /* Page domain fault. */
929 goto do_fault;
930 }
931 if (type == 2) {
932 /* 1Mb section. */
933 phys_addr = (desc & 0xfff00000) | (address & 0x000fffff);
934 ap = (desc >> 10) & 3;
935 code = 13;
936 } else {
937 /* Lookup l2 entry. */
938 if (type == 1) {
939 /* Coarse pagetable. */
940 table = (desc & 0xfffffc00) | ((address >> 10) & 0x3fc);
941 } else {
942 /* Fine pagetable. */
943 table = (desc & 0xfffff000) | ((address >> 8) & 0xffc);
944 }
945 desc = ldl_phys(table);
946 switch (desc & 3) {
947 case 0: /* Page translation fault. */
948 code = 7;
949 goto do_fault;
950 case 1: /* 64k page. */
951 phys_addr = (desc & 0xffff0000) | (address & 0xffff);
952 ap = (desc >> (4 + ((address >> 13) & 6))) & 3;
ce819861 953 break;
9ee6e8bb
PB		 954 case 2: /* 4k page. */
955 phys_addr = (desc & 0xfffff000) | (address & 0xfff);
956 ap = (desc >> (4 + ((address >> 13) & 6))) & 3;
ce819861 957 break;
9ee6e8bb
PB		 958 case 3: /* 1k page. */
959 if (type == 1) {
960 if (arm_feature(env, ARM_FEATURE_XSCALE)) {
961 phys_addr = (desc & 0xfffff000) | (address & 0xfff);
962 } else {
963 /* Page translation fault. */
964 code = 7;
965 goto do_fault;
966 }
967 } else {
968 phys_addr = (desc & 0xfffffc00) | (address & 0x3ff);
969 }
970 ap = (desc >> 4) & 3;
ce819861
PB		 971 break;
972 default:
9ee6e8bb
PB		 973 /* Never happens, but compiler isn't smart enough to tell. */
974 abort();
ce819861 975 }
9ee6e8bb
PB		 976 code = 15;
977 }
978 *prot = check_ap(env, ap, domain, access_type, is_user);
979 if (!*prot) {
980 /* Access permission fault. */
981 goto do_fault;
982 }
983 *phys_ptr = phys_addr;
984 return 0;
985do_fault:
986 return code | (domain << 4);
987}
988
989static int get_phys_addr_v6(CPUState *env, uint32_t address, int access_type,
990 int is_user, uint32_t *phys_ptr, int *prot)
991{
992 int code;
993 uint32_t table;
994 uint32_t desc;
995 uint32_t xn;
996 int type;
997 int ap;
998 int domain;
999 uint32_t phys_addr;
1000
1001 /* Pagetable walk. */
1002 /* Lookup l1 descriptor. */
b2fa1797 1003 table = get_level1_table_address(env, address);
9ee6e8bb
PB		 1004 desc = ldl_phys(table);
1005 type = (desc & 3);
1006 if (type == 0) {
601d70b9 1007 /* Section translation fault. */
9ee6e8bb
PB		 1008 code = 5;
1009 domain = 0;
1010 goto do_fault;
1011 } else if (type == 2 && (desc & (1 << 18))) {
1012 /* Supersection. */
1013 domain = 0;
b5ff1b31 1014 } else {
9ee6e8bb
PB		 1015 /* Section or page. */
1016 domain = (desc >> 4) & 0x1e;
1017 }
1018 domain = (env->cp15.c3 >> domain) & 3;
1019 if (domain == 0 || domain == 2) {
1020 if (type == 2)
1021 code = 9; /* Section domain fault. */
1022 else
1023 code = 11; /* Page domain fault. */
1024 goto do_fault;
1025 }
1026 if (type == 2) {
1027 if (desc & (1 << 18)) {
1028 /* Supersection. */
1029 phys_addr = (desc & 0xff000000) | (address & 0x00ffffff);
b5ff1b31 1030 } else {
9ee6e8bb
PB		 1031 /* Section. */
1032 phys_addr = (desc & 0xfff00000) | (address & 0x000fffff);
b5ff1b31 1033 }
9ee6e8bb
PB		 1034 ap = ((desc >> 10) & 3) | ((desc >> 13) & 4);
1035 xn = desc & (1 << 4);
1036 code = 13;
1037 } else {
1038 /* Lookup l2 entry. */
1039 table = (desc & 0xfffffc00) | ((address >> 10) & 0x3fc);
1040 desc = ldl_phys(table);
1041 ap = ((desc >> 4) & 3) | ((desc >> 7) & 4);
1042 switch (desc & 3) {
1043 case 0: /* Page translation fault. */
1044 code = 7;
b5ff1b31 1045 goto do_fault;
9ee6e8bb
PB		 1046 case 1: /* 64k page. */
1047 phys_addr = (desc & 0xffff0000) | (address & 0xffff);
1048 xn = desc & (1 << 15);
1049 break;
1050 case 2: case 3: /* 4k page. */
1051 phys_addr = (desc & 0xfffff000) | (address & 0xfff);
1052 xn = desc & 1;
1053 break;
1054 default:
1055 /* Never happens, but compiler isn't smart enough to tell. */
1056 abort();
b5ff1b31 1057 }
9ee6e8bb
PB		 1058 code = 15;
1059 }
1060 if (xn && access_type == 2)
1061 goto do_fault;
1062
d4934d18
PB		 1063 /* The simplified model uses AP[0] as an access control bit. */
1064 if ((env->cp15.c1_sys & (1 << 29)) && (ap & 1) == 0) {
1065 /* Access flag fault. */
1066 code = (code == 15) ? 6 : 3;
1067 goto do_fault;
1068 }
9ee6e8bb
PB		 1069 *prot = check_ap(env, ap, domain, access_type, is_user);
1070 if (!*prot) {
1071 /* Access permission fault. */
1072 goto do_fault;
b5ff1b31 1073 }
9ee6e8bb 1074 *phys_ptr = phys_addr;
b5ff1b31
FB		 1075 return 0;
1076do_fault:
1077 return code | (domain << 4);
1078}
1079
9ee6e8bb
PB		 1080static int get_phys_addr_mpu(CPUState *env, uint32_t address, int access_type,
1081 int is_user, uint32_t *phys_ptr, int *prot)
1082{
1083 int n;
1084 uint32_t mask;
1085 uint32_t base;
1086
1087 *phys_ptr = address;
1088 for (n = 7; n >= 0; n--) {
1089 base = env->cp15.c6_region[n];
1090 if ((base & 1) == 0)
1091 continue;
1092 mask = 1 << ((base >> 1) & 0x1f);
1093 /* Keep this shift separate from the above to avoid an
1094 (undefined) << 32. */
1095 mask = (mask << 1) - 1;
1096 if (((base ^ address) & ~mask) == 0)
1097 break;
1098 }
1099 if (n < 0)
1100 return 2;
1101
1102 if (access_type == 2) {
1103 mask = env->cp15.c5_insn;
1104 } else {
1105 mask = env->cp15.c5_data;
1106 }
1107 mask = (mask >> (n * 4)) & 0xf;
1108 switch (mask) {
1109 case 0:
1110 return 1;
1111 case 1:
1112 if (is_user)
1113 return 1;
1114 *prot = PAGE_READ | PAGE_WRITE;
1115 break;
1116 case 2:
1117 *prot = PAGE_READ;
1118 if (!is_user)
1119 *prot |= PAGE_WRITE;
1120 break;
1121 case 3:
1122 *prot = PAGE_READ | PAGE_WRITE;
1123 break;
1124 case 5:
1125 if (is_user)
1126 return 1;
1127 *prot = PAGE_READ;
1128 break;
1129 case 6:
1130 *prot = PAGE_READ;
1131 break;
1132 default:
1133 /* Bad permission. */
1134 return 1;
1135 }
1136 return 0;
1137}
1138
1139static inline int get_phys_addr(CPUState *env, uint32_t address,
1140 int access_type, int is_user,
1141 uint32_t *phys_ptr, int *prot)
1142{
1143 /* Fast Context Switch Extension. */
1144 if (address < 0x02000000)
1145 address += env->cp15.c13_fcse;
1146
1147 if ((env->cp15.c1_sys & 1) == 0) {
1148 /* MMU/MPU disabled. */
1149 *phys_ptr = address;
1150 *prot = PAGE_READ | PAGE_WRITE;
1151 return 0;
1152 } else if (arm_feature(env, ARM_FEATURE_MPU)) {
1153 return get_phys_addr_mpu(env, address, access_type, is_user, phys_ptr,
1154 prot);
1155 } else if (env->cp15.c1_sys & (1 << 23)) {
1156 return get_phys_addr_v6(env, address, access_type, is_user, phys_ptr,
1157 prot);
1158 } else {
1159 return get_phys_addr_v5(env, address, access_type, is_user, phys_ptr,
1160 prot);
1161 }
1162}
1163
b5ff1b31 1164int cpu_arm_handle_mmu_fault (CPUState *env, target_ulong address,
6ebbf390 1165 int access_type, int mmu_idx, int is_softmmu)
b5ff1b31
FB		 1166{
1167 uint32_t phys_addr;
1168 int prot;
6ebbf390 1169 int ret, is_user;
b5ff1b31 1170
6ebbf390 1171 is_user = mmu_idx == MMU_USER_IDX;
b5ff1b31
FB		 1172 ret = get_phys_addr(env, address, access_type, is_user, &phys_addr, &prot);
1173 if (ret == 0) {
1174 /* Map a single [sub]page. */
1175 phys_addr &= ~(uint32_t)0x3ff;
1176 address &= ~(uint32_t)0x3ff;
6ebbf390 1177 return tlb_set_page (env, address, phys_addr, prot, mmu_idx,
b5ff1b31
FB		 1178 is_softmmu);
1179 }
1180
1181 if (access_type == 2) {
1182 env->cp15.c5_insn = ret;
1183 env->cp15.c6_insn = address;
1184 env->exception_index = EXCP_PREFETCH_ABORT;
1185 } else {
1186 env->cp15.c5_data = ret;
9ee6e8bb
PB		 1187 if (access_type == 1 && arm_feature(env, ARM_FEATURE_V6))
1188 env->cp15.c5_data |= (1 << 11);
b5ff1b31
FB		 1189 env->cp15.c6_data = address;
1190 env->exception_index = EXCP_DATA_ABORT;
1191 }
1192 return 1;
1193}
1194
c227f099 1195target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
b5ff1b31
FB		 1196{
1197 uint32_t phys_addr;
1198 int prot;
1199 int ret;
1200
1201 ret = get_phys_addr(env, addr, 0, 0, &phys_addr, &prot);
1202
1203 if (ret != 0)
1204 return -1;
1205
1206 return phys_addr;
1207}
1208
8984bd2e 1209void HELPER(set_cp)(CPUState *env, uint32_t insn, uint32_t val)
c1713132
AZ		 1210{
1211 int cp_num = (insn >> 8) & 0xf;
1212 int cp_info = (insn >> 5) & 7;
1213 int src = (insn >> 16) & 0xf;
1214 int operand = insn & 0xf;
1215
1216 if (env->cp[cp_num].cp_write)
1217 env->cp[cp_num].cp_write(env->cp[cp_num].opaque,
1218 cp_info, src, operand, val);
1219}
1220
8984bd2e 1221uint32_t HELPER(get_cp)(CPUState *env, uint32_t insn)
c1713132
AZ		 1222{
1223 int cp_num = (insn >> 8) & 0xf;
1224 int cp_info = (insn >> 5) & 7;
1225 int dest = (insn >> 16) & 0xf;
1226 int operand = insn & 0xf;
1227
1228 if (env->cp[cp_num].cp_read)
1229 return env->cp[cp_num].cp_read(env->cp[cp_num].opaque,
1230 cp_info, dest, operand);
1231 return 0;
1232}
1233
ce819861
PB		 1234/* Return basic MPU access permission bits. */
1235static uint32_t simple_mpu_ap_bits(uint32_t val)
1236{
1237 uint32_t ret;
1238 uint32_t mask;
1239 int i;
1240 ret = 0;
1241 mask = 3;
1242 for (i = 0; i < 16; i += 2) {
1243 ret |= (val >> i) & mask;
1244 mask <<= 2;
1245 }
1246 return ret;
1247}
1248
1249/* Pad basic MPU access permission bits to extended format. */
1250static uint32_t extended_mpu_ap_bits(uint32_t val)
1251{
1252 uint32_t ret;
1253 uint32_t mask;
1254 int i;
1255 ret = 0;
1256 mask = 3;
1257 for (i = 0; i < 16; i += 2) {
1258 ret |= (val & mask) << i;
1259 mask <<= 2;
1260 }
1261 return ret;
1262}
1263
8984bd2e 1264void HELPER(set_cp15)(CPUState *env, uint32_t insn, uint32_t val)
b5ff1b31 1265{
9ee6e8bb
PB		 1266 int op1;
1267 int op2;
1268 int crm;
b5ff1b31 1269
9ee6e8bb 1270 op1 = (insn >> 21) & 7;
b5ff1b31 1271 op2 = (insn >> 5) & 7;
ce819861 1272 crm = insn & 0xf;
b5ff1b31 1273 switch ((insn >> 16) & 0xf) {
9ee6e8bb 1274 case 0:
9ee6e8bb 1275 /* ID codes. */
610c3c8a
AZ		 1276 if (arm_feature(env, ARM_FEATURE_XSCALE))
1277 break;
c3d2689d
AZ		 1278 if (arm_feature(env, ARM_FEATURE_OMAPCP))
1279 break;
a49ea279
PB		 1280 if (arm_feature(env, ARM_FEATURE_V7)
1281 && op1 == 2 && crm == 0 && op2 == 0) {
1282 env->cp15.c0_cssel = val & 0xf;
1283 break;
1284 }
b5ff1b31
FB		 1285 goto bad_reg;
1286 case 1: /* System configuration. */
c3d2689d
AZ		 1287 if (arm_feature(env, ARM_FEATURE_OMAPCP))
1288 op2 = 0;
b5ff1b31
FB		 1289 switch (op2) {
1290 case 0:
ce819861 1291 if (!arm_feature(env, ARM_FEATURE_XSCALE) || crm == 0)
c1713132 1292 env->cp15.c1_sys = val;
b5ff1b31
FB		 1293 /* ??? Lots of these bits are not implemented. */
1294 /* This may enable/disable the MMU, so do a TLB flush. */
1295 tlb_flush(env, 1);
1296 break;
9ee6e8bb 1297 case 1: /* Auxiliary cotrol register. */
610c3c8a
AZ		 1298 if (arm_feature(env, ARM_FEATURE_XSCALE)) {
1299 env->cp15.c1_xscaleauxcr = val;
c1713132 1300 break;
610c3c8a 1301 }
9ee6e8bb
PB		 1302 /* Not implemented. */
1303 break;
b5ff1b31 1304 case 2:
610c3c8a
AZ		 1305 if (arm_feature(env, ARM_FEATURE_XSCALE))
1306 goto bad_reg;
4be27dbb
PB		 1307 if (env->cp15.c1_coproc != val) {
1308 env->cp15.c1_coproc = val;
1309 /* ??? Is this safe when called from within a TB? */
1310 tb_flush(env);
1311 }
c1713132 1312 break;
b5ff1b31
FB		 1313 default:
1314 goto bad_reg;
1315 }
1316 break;
ce819861
PB		 1317 case 2: /* MMU Page table control / MPU cache control. */
1318 if (arm_feature(env, ARM_FEATURE_MPU)) {
1319 switch (op2) {
1320 case 0:
1321 env->cp15.c2_data = val;
1322 break;
1323 case 1:
1324 env->cp15.c2_insn = val;
1325 break;
1326 default:
1327 goto bad_reg;
1328 }
1329 } else {
9ee6e8bb
PB		 1330 switch (op2) {
1331 case 0:
1332 env->cp15.c2_base0 = val;
1333 break;
1334 case 1:
1335 env->cp15.c2_base1 = val;
1336 break;
1337 case 2:
b2fa1797
PB		 1338 val &= 7;
1339 env->cp15.c2_control = val;
9ee6e8bb 1340 env->cp15.c2_mask = ~(((uint32_t)0xffffffffu) >> val);
b2fa1797 1341 env->cp15.c2_base_mask = ~((uint32_t)0x3fffu >> val);
9ee6e8bb
PB		 1342 break;
1343 default:
1344 goto bad_reg;
1345 }
ce819861 1346 }
b5ff1b31 1347 break;
ce819861 1348 case 3: /* MMU Domain access control / MPU write buffer control. */
b5ff1b31 1349 env->cp15.c3 = val;
405ee3ad 1350 tlb_flush(env, 1); /* Flush TLB as domain not tracked in TLB */
b5ff1b31
FB		 1351 break;
1352 case 4: /* Reserved. */
1353 goto bad_reg;
ce819861 1354 case 5: /* MMU Fault status / MPU access permission. */
c3d2689d
AZ		 1355 if (arm_feature(env, ARM_FEATURE_OMAPCP))
1356 op2 = 0;
b5ff1b31
FB		 1357 switch (op2) {
1358 case 0:
ce819861
PB		 1359 if (arm_feature(env, ARM_FEATURE_MPU))
1360 val = extended_mpu_ap_bits(val);
b5ff1b31
FB		 1361 env->cp15.c5_data = val;
1362 break;
1363 case 1:
ce819861
PB		 1364 if (arm_feature(env, ARM_FEATURE_MPU))
1365 val = extended_mpu_ap_bits(val);
b5ff1b31
FB		 1366 env->cp15.c5_insn = val;
1367 break;
ce819861
PB		 1368 case 2:
1369 if (!arm_feature(env, ARM_FEATURE_MPU))
1370 goto bad_reg;
1371 env->cp15.c5_data = val;
b5ff1b31 1372 break;
ce819861
PB		 1373 case 3:
1374 if (!arm_feature(env, ARM_FEATURE_MPU))
1375 goto bad_reg;
1376 env->cp15.c5_insn = val;
b5ff1b31
FB		 1377 break;
1378 default:
1379 goto bad_reg;
1380 }
1381 break;
ce819861
PB		 1382 case 6: /* MMU Fault address / MPU base/size. */
1383 if (arm_feature(env, ARM_FEATURE_MPU)) {
1384 if (crm >= 8)
1385 goto bad_reg;
1386 env->cp15.c6_region[crm] = val;
1387 } else {
c3d2689d
AZ		 1388 if (arm_feature(env, ARM_FEATURE_OMAPCP))
1389 op2 = 0;
ce819861
PB		 1390 switch (op2) {
1391 case 0:
1392 env->cp15.c6_data = val;
1393 break;
9ee6e8bb
PB		 1394 case 1: /* ??? This is WFAR on armv6 */
1395 case 2:
ce819861
PB		 1396 env->cp15.c6_insn = val;
1397 break;
1398 default:
1399 goto bad_reg;
1400 }
1401 }
1402 break;
b5ff1b31 1403 case 7: /* Cache control. */
c3d2689d
AZ		 1404 env->cp15.c15_i_max = 0x000;
1405 env->cp15.c15_i_min = 0xff0;
b5ff1b31 1406 /* No cache, so nothing to do. */
9ee6e8bb 1407 /* ??? MPCore has VA to PA translation functions. */
b5ff1b31
FB		 1408 break;
1409 case 8: /* MMU TLB control. */
1410 switch (op2) {
1411 case 0: /* Invalidate all. */
1412 tlb_flush(env, 0);
1413 break;
1414 case 1: /* Invalidate single TLB entry. */
1415#if 0
1416 /* ??? This is wrong for large pages and sections. */
1417 /* As an ugly hack to make linux work we always flush a 4K
1418 pages. */
1419 val &= 0xfffff000;
1420 tlb_flush_page(env, val);
1421 tlb_flush_page(env, val + 0x400);
1422 tlb_flush_page(env, val + 0x800);
1423 tlb_flush_page(env, val + 0xc00);
1424#else
1425 tlb_flush(env, 1);
1426#endif
1427 break;
9ee6e8bb
PB		 1428 case 2: /* Invalidate on ASID. */
1429 tlb_flush(env, val == 0);
1430 break;
1431 case 3: /* Invalidate single entry on MVA. */
1432 /* ??? This is like case 1, but ignores ASID. */
1433 tlb_flush(env, 1);
1434 break;
b5ff1b31
FB		 1435 default:
1436 goto bad_reg;
1437 }
1438 break;
ce819861 1439 case 9:
c3d2689d
AZ		 1440 if (arm_feature(env, ARM_FEATURE_OMAPCP))
1441 break;
ce819861
PB		 1442 switch (crm) {
1443 case 0: /* Cache lockdown. */
9ee6e8bb
PB		 1444 switch (op1) {
1445 case 0: /* L1 cache. */
1446 switch (op2) {
1447 case 0:
1448 env->cp15.c9_data = val;
1449 break;
1450 case 1:
1451 env->cp15.c9_insn = val;
1452 break;
1453 default:
1454 goto bad_reg;
1455 }
1456 break;
1457 case 1: /* L2 cache. */
1458 /* Ignore writes to L2 lockdown/auxiliary registers. */
1459 break;
1460 default:
1461 goto bad_reg;
1462 }
1463 break;
ce819861
PB		 1464 case 1: /* TCM memory region registers. */
1465 /* Not implemented. */
1466 goto bad_reg;
b5ff1b31
FB		 1467 default:
1468 goto bad_reg;
1469 }
1470 break;
1471 case 10: /* MMU TLB lockdown. */
1472 /* ??? TLB lockdown not implemented. */
1473 break;
b5ff1b31
FB		 1474 case 12: /* Reserved. */
1475 goto bad_reg;
1476 case 13: /* Process ID. */
1477 switch (op2) {
1478 case 0:
d07edbfa
PB		 1479 /* Unlike real hardware the qemu TLB uses virtual addresses,
1480 not modified virtual addresses, so this causes a TLB flush.
1481 */
1482 if (env->cp15.c13_fcse != val)
1483 tlb_flush(env, 1);
1484 env->cp15.c13_fcse = val;
b5ff1b31
FB		 1485 break;
1486 case 1:
d07edbfa 1487 /* This changes the ASID, so do a TLB flush. */
ce819861
PB		 1488 if (env->cp15.c13_context != val
1489 && !arm_feature(env, ARM_FEATURE_MPU))
d07edbfa
PB		 1490 tlb_flush(env, 0);
1491 env->cp15.c13_context = val;
b5ff1b31
FB		 1492 break;
1493 default:
1494 goto bad_reg;
1495 }
1496 break;
1497 case 14: /* Reserved. */
1498 goto bad_reg;
1499 case 15: /* Implementation specific. */
c1713132 1500 if (arm_feature(env, ARM_FEATURE_XSCALE)) {
ce819861 1501 if (op2 == 0 && crm == 1) {
2e23213f
AZ		 1502 if (env->cp15.c15_cpar != (val & 0x3fff)) {
1503 /* Changes cp0 to cp13 behavior, so needs a TB flush. */
1504 tb_flush(env);
1505 env->cp15.c15_cpar = val & 0x3fff;
1506 }
c1713132
AZ		 1507 break;
1508 }
1509 goto bad_reg;
1510 }
c3d2689d
AZ		 1511 if (arm_feature(env, ARM_FEATURE_OMAPCP)) {
1512 switch (crm) {
1513 case 0:
1514 break;
1515 case 1: /* Set TI925T configuration. */
1516 env->cp15.c15_ticonfig = val & 0xe7;
1517 env->cp15.c0_cpuid = (val & (1 << 5)) ? /* OS_TYPE bit */
1518 ARM_CPUID_TI915T : ARM_CPUID_TI925T;
1519 break;
1520 case 2: /* Set I_max. */
1521 env->cp15.c15_i_max = val;
1522 break;
1523 case 3: /* Set I_min. */
1524 env->cp15.c15_i_min = val;
1525 break;
1526 case 4: /* Set thread-ID. */
1527 env->cp15.c15_threadid = val & 0xffff;
1528 break;
1529 case 8: /* Wait-for-interrupt (deprecated). */
1530 cpu_interrupt(env, CPU_INTERRUPT_HALT);
1531 break;
1532 default:
1533 goto bad_reg;
1534 }
1535 }
b5ff1b31
FB		 1536 break;
1537 }
1538 return;
1539bad_reg:
1540 /* ??? For debugging only. Should raise illegal instruction exception. */
9ee6e8bb
PB		 1541 cpu_abort(env, "Unimplemented cp15 register write (c%d, c%d, {%d, %d})\n",
1542 (insn >> 16) & 0xf, crm, op1, op2);
b5ff1b31
FB		 1543}
1544
8984bd2e 1545uint32_t HELPER(get_cp15)(CPUState *env, uint32_t insn)
b5ff1b31 1546{
9ee6e8bb
PB		 1547 int op1;
1548 int op2;
1549 int crm;
b5ff1b31 1550
9ee6e8bb 1551 op1 = (insn >> 21) & 7;
b5ff1b31 1552 op2 = (insn >> 5) & 7;
c3d2689d 1553 crm = insn & 0xf;
b5ff1b31
FB		 1554 switch ((insn >> 16) & 0xf) {
1555 case 0: /* ID codes. */
9ee6e8bb
PB		 1556 switch (op1) {
1557 case 0:
1558 switch (crm) {
1559 case 0:
1560 switch (op2) {
1561 case 0: /* Device ID. */
1562 return env->cp15.c0_cpuid;
1563 case 1: /* Cache Type. */
1564 return env->cp15.c0_cachetype;
1565 case 2: /* TCM status. */
1566 return 0;
1567 case 3: /* TLB type register. */
1568 return 0; /* No lockable TLB entries. */
1569 case 5: /* CPU ID */
10055562
PB		 1570 if (ARM_CPUID(env) == ARM_CPUID_CORTEXA9) {
1571 return env->cpu_index | 0x80000900;
1572 } else {
1573 return env->cpu_index;
1574 }
9ee6e8bb
PB		 1575 default:
1576 goto bad_reg;
1577 }
1578 case 1:
1579 if (!arm_feature(env, ARM_FEATURE_V6))
1580 goto bad_reg;
1581 return env->cp15.c0_c1[op2];
1582 case 2:
1583 if (!arm_feature(env, ARM_FEATURE_V6))
1584 goto bad_reg;
1585 return env->cp15.c0_c2[op2];
1586 case 3: case 4: case 5: case 6: case 7:
1587 return 0;
1588 default:
1589 goto bad_reg;
1590 }
1591 case 1:
1592 /* These registers aren't documented on arm11 cores. However
1593 Linux looks at them anyway. */
1594 if (!arm_feature(env, ARM_FEATURE_V6))
1595 goto bad_reg;
1596 if (crm != 0)
1597 goto bad_reg;
a49ea279
PB		 1598 if (!arm_feature(env, ARM_FEATURE_V7))
1599 return 0;
1600
1601 switch (op2) {
1602 case 0:
1603 return env->cp15.c0_ccsid[env->cp15.c0_cssel];
1604 case 1:
1605 return env->cp15.c0_clid;
1606 case 7:
1607 return 0;
1608 }
1609 goto bad_reg;
1610 case 2:
1611 if (op2 != 0 || crm != 0)
610c3c8a 1612 goto bad_reg;
a49ea279 1613 return env->cp15.c0_cssel;
9ee6e8bb
PB		 1614 default:
1615 goto bad_reg;
b5ff1b31
FB		 1616 }
1617 case 1: /* System configuration. */
c3d2689d
AZ		 1618 if (arm_feature(env, ARM_FEATURE_OMAPCP))
1619 op2 = 0;
b5ff1b31
FB		 1620 switch (op2) {
1621 case 0: /* Control register. */
1622 return env->cp15.c1_sys;
1623 case 1: /* Auxiliary control register. */
c1713132 1624 if (arm_feature(env, ARM_FEATURE_XSCALE))
610c3c8a 1625 return env->cp15.c1_xscaleauxcr;
9ee6e8bb
PB		 1626 if (!arm_feature(env, ARM_FEATURE_AUXCR))
1627 goto bad_reg;
1628 switch (ARM_CPUID(env)) {
1629 case ARM_CPUID_ARM1026:
1630 return 1;
1631 case ARM_CPUID_ARM1136:
827df9f3 1632 case ARM_CPUID_ARM1136_R2:
9ee6e8bb
PB		 1633 return 7;
1634 case ARM_CPUID_ARM11MPCORE:
1635 return 1;
1636 case ARM_CPUID_CORTEXA8:
533d177a 1637 return 2;
10055562
PB		 1638 case ARM_CPUID_CORTEXA9:
1639 return 0;
9ee6e8bb
PB		 1640 default:
1641 goto bad_reg;
1642 }
b5ff1b31 1643 case 2: /* Coprocessor access register. */
610c3c8a
AZ		 1644 if (arm_feature(env, ARM_FEATURE_XSCALE))
1645 goto bad_reg;
b5ff1b31
FB		 1646 return env->cp15.c1_coproc;
1647 default:
1648 goto bad_reg;
1649 }
ce819861
PB		 1650 case 2: /* MMU Page table control / MPU cache control. */
1651 if (arm_feature(env, ARM_FEATURE_MPU)) {
1652 switch (op2) {
1653 case 0:
1654 return env->cp15.c2_data;
1655 break;
1656 case 1:
1657 return env->cp15.c2_insn;
1658 break;
1659 default:
1660 goto bad_reg;
1661 }
1662 } else {
9ee6e8bb
PB		 1663 switch (op2) {
1664 case 0:
1665 return env->cp15.c2_base0;
1666 case 1:
1667 return env->cp15.c2_base1;
1668 case 2:
b2fa1797 1669 return env->cp15.c2_control;
9ee6e8bb
PB		 1670 default:
1671 goto bad_reg;
1672 }
1673 }
ce819861 1674 case 3: /* MMU Domain access control / MPU write buffer control. */
b5ff1b31
FB		 1675 return env->cp15.c3;
1676 case 4: /* Reserved. */
1677 goto bad_reg;
ce819861 1678 case 5: /* MMU Fault status / MPU access permission. */
c3d2689d
AZ		 1679 if (arm_feature(env, ARM_FEATURE_OMAPCP))
1680 op2 = 0;
b5ff1b31
FB		 1681 switch (op2) {
1682 case 0:
ce819861
PB		 1683 if (arm_feature(env, ARM_FEATURE_MPU))
1684 return simple_mpu_ap_bits(env->cp15.c5_data);
b5ff1b31
FB		 1685 return env->cp15.c5_data;
1686 case 1:
ce819861
PB		 1687 if (arm_feature(env, ARM_FEATURE_MPU))
1688 return simple_mpu_ap_bits(env->cp15.c5_data);
1689 return env->cp15.c5_insn;
1690 case 2:
1691 if (!arm_feature(env, ARM_FEATURE_MPU))
1692 goto bad_reg;
1693 return env->cp15.c5_data;
1694 case 3:
1695 if (!arm_feature(env, ARM_FEATURE_MPU))
1696 goto bad_reg;
b5ff1b31
FB		 1697 return env->cp15.c5_insn;
1698 default:
1699 goto bad_reg;
1700 }
9ee6e8bb 1701 case 6: /* MMU Fault address. */
ce819861 1702 if (arm_feature(env, ARM_FEATURE_MPU)) {
9ee6e8bb 1703 if (crm >= 8)
ce819861 1704 goto bad_reg;
9ee6e8bb 1705 return env->cp15.c6_region[crm];
ce819861 1706 } else {
c3d2689d
AZ		 1707 if (arm_feature(env, ARM_FEATURE_OMAPCP))
1708 op2 = 0;
9ee6e8bb
PB		 1709 switch (op2) {
1710 case 0:
1711 return env->cp15.c6_data;
1712 case 1:
1713 if (arm_feature(env, ARM_FEATURE_V6)) {
1714 /* Watchpoint Fault Adrress. */
1715 return 0; /* Not implemented. */
1716 } else {
1717 /* Instruction Fault Adrress. */
1718 /* Arm9 doesn't have an IFAR, but implementing it anyway
1719 shouldn't do any harm. */
1720 return env->cp15.c6_insn;
1721 }
1722 case 2:
1723 if (arm_feature(env, ARM_FEATURE_V6)) {
1724 /* Instruction Fault Adrress. */
1725 return env->cp15.c6_insn;
1726 } else {
1727 goto bad_reg;
1728 }
1729 default:
1730 goto bad_reg;
1731 }
b5ff1b31
FB		 1732 }
1733 case 7: /* Cache control. */
6fbe23d5
PB		 1734 /* FIXME: Should only clear Z flag if destination is r15. */
1735 env->ZF = 0;
b5ff1b31
FB		 1736 return 0;
1737 case 8: /* MMU TLB control. */
1738 goto bad_reg;
1739 case 9: /* Cache lockdown. */
9ee6e8bb
PB		 1740 switch (op1) {
1741 case 0: /* L1 cache. */
1742 if (arm_feature(env, ARM_FEATURE_OMAPCP))
1743 return 0;
1744 switch (op2) {
1745 case 0:
1746 return env->cp15.c9_data;
1747 case 1:
1748 return env->cp15.c9_insn;
1749 default:
1750 goto bad_reg;
1751 }
1752 case 1: /* L2 cache */
1753 if (crm != 0)
1754 goto bad_reg;
1755 /* L2 Lockdown and Auxiliary control. */
c3d2689d 1756 return 0;
b5ff1b31
FB		 1757 default:
1758 goto bad_reg;
1759 }
1760 case 10: /* MMU TLB lockdown. */
1761 /* ??? TLB lockdown not implemented. */
1762 return 0;
1763 case 11: /* TCM DMA control. */
1764 case 12: /* Reserved. */
1765 goto bad_reg;
1766 case 13: /* Process ID. */
1767 switch (op2) {
1768 case 0:
1769 return env->cp15.c13_fcse;
1770 case 1:
1771 return env->cp15.c13_context;
1772 default:
1773 goto bad_reg;
1774 }
1775 case 14: /* Reserved. */
1776 goto bad_reg;
1777 case 15: /* Implementation specific. */
c1713132 1778 if (arm_feature(env, ARM_FEATURE_XSCALE)) {
c3d2689d 1779 if (op2 == 0 && crm == 1)
c1713132
AZ		 1780 return env->cp15.c15_cpar;
1781
1782 goto bad_reg;
1783 }
c3d2689d
AZ		 1784 if (arm_feature(env, ARM_FEATURE_OMAPCP)) {
1785 switch (crm) {
1786 case 0:
1787 return 0;
1788 case 1: /* Read TI925T configuration. */
1789 return env->cp15.c15_ticonfig;
1790 case 2: /* Read I_max. */
1791 return env->cp15.c15_i_max;
1792 case 3: /* Read I_min. */
1793 return env->cp15.c15_i_min;
1794 case 4: /* Read thread-ID. */
1795 return env->cp15.c15_threadid;
1796 case 8: /* TI925T_status */
1797 return 0;
1798 }
827df9f3
AZ		 1799 /* TODO: Peripheral port remap register:
1800 * On OMAP2 mcr p15, 0, rn, c15, c2, 4 sets up the interrupt
1801 * controller base address at $rn & ~0xfff and map size of
1802 * 0x200 << ($rn & 0xfff), when MMU is off. */
c3d2689d
AZ		 1803 goto bad_reg;
1804 }
b5ff1b31
FB		 1805 return 0;
1806 }
1807bad_reg:
1808 /* ??? For debugging only. Should raise illegal instruction exception. */
9ee6e8bb
PB		 1809 cpu_abort(env, "Unimplemented cp15 register read (c%d, c%d, {%d, %d})\n",
1810 (insn >> 16) & 0xf, crm, op1, op2);
b5ff1b31
FB		 1811 return 0;
1812}
1813
b0109805 1814void HELPER(set_r13_banked)(CPUState *env, uint32_t mode, uint32_t val)
9ee6e8bb
PB		 1815{
1816 env->banked_r13[bank_number(mode)] = val;
1817}
1818
b0109805 1819uint32_t HELPER(get_r13_banked)(CPUState *env, uint32_t mode)
9ee6e8bb
PB		 1820{
1821 return env->banked_r13[bank_number(mode)];
1822}
1823
8984bd2e 1824uint32_t HELPER(v7m_mrs)(CPUState *env, uint32_t reg)
9ee6e8bb
PB		 1825{
1826 switch (reg) {
1827 case 0: /* APSR */
1828 return xpsr_read(env) & 0xf8000000;
1829 case 1: /* IAPSR */
1830 return xpsr_read(env) & 0xf80001ff;
1831 case 2: /* EAPSR */
1832 return xpsr_read(env) & 0xff00fc00;
1833 case 3: /* xPSR */
1834 return xpsr_read(env) & 0xff00fdff;
1835 case 5: /* IPSR */
1836 return xpsr_read(env) & 0x000001ff;
1837 case 6: /* EPSR */
1838 return xpsr_read(env) & 0x0700fc00;
1839 case 7: /* IEPSR */
1840 return xpsr_read(env) & 0x0700edff;
1841 case 8: /* MSP */
1842 return env->v7m.current_sp ? env->v7m.other_sp : env->regs[13];
1843 case 9: /* PSP */
1844 return env->v7m.current_sp ? env->regs[13] : env->v7m.other_sp;
1845 case 16: /* PRIMASK */
1846 return (env->uncached_cpsr & CPSR_I) != 0;
1847 case 17: /* FAULTMASK */
1848 return (env->uncached_cpsr & CPSR_F) != 0;
1849 case 18: /* BASEPRI */
1850 case 19: /* BASEPRI_MAX */
1851 return env->v7m.basepri;
1852 case 20: /* CONTROL */
1853 return env->v7m.control;
1854 default:
1855 /* ??? For debugging only. */
1856 cpu_abort(env, "Unimplemented system register read (%d)\n", reg);
1857 return 0;
1858 }
1859}
1860
8984bd2e 1861void HELPER(v7m_msr)(CPUState *env, uint32_t reg, uint32_t val)
9ee6e8bb
PB		 1862{
1863 switch (reg) {
1864 case 0: /* APSR */
1865 xpsr_write(env, val, 0xf8000000);
1866 break;
1867 case 1: /* IAPSR */
1868 xpsr_write(env, val, 0xf8000000);
1869 break;
1870 case 2: /* EAPSR */
1871 xpsr_write(env, val, 0xfe00fc00);
1872 break;
1873 case 3: /* xPSR */
1874 xpsr_write(env, val, 0xfe00fc00);
1875 break;
1876 case 5: /* IPSR */
1877 /* IPSR bits are readonly. */
1878 break;
1879 case 6: /* EPSR */
1880 xpsr_write(env, val, 0x0600fc00);
1881 break;
1882 case 7: /* IEPSR */
1883 xpsr_write(env, val, 0x0600fc00);
1884 break;
1885 case 8: /* MSP */
1886 if (env->v7m.current_sp)
1887 env->v7m.other_sp = val;
1888 else
1889 env->regs[13] = val;
1890 break;
1891 case 9: /* PSP */
1892 if (env->v7m.current_sp)
1893 env->regs[13] = val;
1894 else
1895 env->v7m.other_sp = val;
1896 break;
1897 case 16: /* PRIMASK */
1898 if (val & 1)
1899 env->uncached_cpsr |= CPSR_I;
1900 else
1901 env->uncached_cpsr &= ~CPSR_I;
1902 break;
1903 case 17: /* FAULTMASK */
1904 if (val & 1)
1905 env->uncached_cpsr |= CPSR_F;
1906 else
1907 env->uncached_cpsr &= ~CPSR_F;
1908 break;
1909 case 18: /* BASEPRI */
1910 env->v7m.basepri = val & 0xff;
1911 break;
1912 case 19: /* BASEPRI_MAX */
1913 val &= 0xff;
1914 if (val != 0 && (val < env->v7m.basepri || env->v7m.basepri == 0))
1915 env->v7m.basepri = val;
1916 break;
1917 case 20: /* CONTROL */
1918 env->v7m.control = val & 3;
1919 switch_v7m_sp(env, (val & 2) != 0);
1920 break;
1921 default:
1922 /* ??? For debugging only. */
1923 cpu_abort(env, "Unimplemented system register write (%d)\n", reg);
1924 return;
1925 }
1926}
1927
c1713132
AZ		 1928void cpu_arm_set_cp_io(CPUARMState *env, int cpnum,
1929 ARMReadCPFunc *cp_read, ARMWriteCPFunc *cp_write,
1930 void *opaque)
1931{
1932 if (cpnum < 0 || cpnum > 14) {
1933 cpu_abort(env, "Bad coprocessor number: %i\n", cpnum);
1934 return;
1935 }
1936
1937 env->cp[cpnum].cp_read = cp_read;
1938 env->cp[cpnum].cp_write = cp_write;
1939 env->cp[cpnum].opaque = opaque;
1940}
1941
b5ff1b31 1942#endif
6ddbc6e4
PB		 1943
1944/* Note that signed overflow is undefined in C. The following routines are
1945 careful to use unsigned types where modulo arithmetic is required.
1946 Failure to do so _will_ break on newer gcc. */
1947
1948/* Signed saturating arithmetic. */
1949
1654b2d6 1950/* Perform 16-bit signed saturating addition. */
6ddbc6e4
PB		 1951static inline uint16_t add16_sat(uint16_t a, uint16_t b)
1952{
1953 uint16_t res;
1954
1955 res = a + b;
1956 if (((res ^ a) & 0x8000) && !((a ^ b) & 0x8000)) {
1957 if (a & 0x8000)
1958 res = 0x8000;
1959 else
1960 res = 0x7fff;
1961 }
1962 return res;
1963}
1964
1654b2d6 1965/* Perform 8-bit signed saturating addition. */
6ddbc6e4
PB		 1966static inline uint8_t add8_sat(uint8_t a, uint8_t b)
1967{
1968 uint8_t res;
1969
1970 res = a + b;
1971 if (((res ^ a) & 0x80) && !((a ^ b) & 0x80)) {
1972 if (a & 0x80)
1973 res = 0x80;
1974 else
1975 res = 0x7f;
1976 }
1977 return res;
1978}
1979
1654b2d6 1980/* Perform 16-bit signed saturating subtraction. */
6ddbc6e4
PB		 1981static inline uint16_t sub16_sat(uint16_t a, uint16_t b)
1982{
1983 uint16_t res;
1984
1985 res = a - b;
1986 if (((res ^ a) & 0x8000) && ((a ^ b) & 0x8000)) {
1987 if (a & 0x8000)
1988 res = 0x8000;
1989 else
1990 res = 0x7fff;
1991 }
1992 return res;
1993}
1994
1654b2d6 1995/* Perform 8-bit signed saturating subtraction. */
6ddbc6e4
PB		 1996static inline uint8_t sub8_sat(uint8_t a, uint8_t b)
1997{
1998 uint8_t res;
1999
2000 res = a - b;
2001 if (((res ^ a) & 0x80) && ((a ^ b) & 0x80)) {
2002 if (a & 0x80)
2003 res = 0x80;
2004 else
2005 res = 0x7f;
2006 }
2007 return res;
2008}
2009
2010#define ADD16(a, b, n) RESULT(add16_sat(a, b), n, 16);
2011#define SUB16(a, b, n) RESULT(sub16_sat(a, b), n, 16);
2012#define ADD8(a, b, n) RESULT(add8_sat(a, b), n, 8);
2013#define SUB8(a, b, n) RESULT(sub8_sat(a, b), n, 8);
2014#define PFX q
2015
2016#include "op_addsub.h"
2017
2018/* Unsigned saturating arithmetic. */
460a09c1 2019static inline uint16_t add16_usat(uint16_t a, uint16_t b)
6ddbc6e4
PB		 2020{
2021 uint16_t res;
2022 res = a + b;
2023 if (res < a)
2024 res = 0xffff;
2025 return res;
2026}
2027
460a09c1 2028static inline uint16_t sub16_usat(uint16_t a, uint16_t b)
6ddbc6e4
PB		 2029{
2030 if (a < b)
2031 return a - b;
2032 else
2033 return 0;
2034}
2035
2036static inline uint8_t add8_usat(uint8_t a, uint8_t b)
2037{
2038 uint8_t res;
2039 res = a + b;
2040 if (res < a)
2041 res = 0xff;
2042 return res;
2043}
2044
2045static inline uint8_t sub8_usat(uint8_t a, uint8_t b)
2046{
2047 if (a < b)
2048 return a - b;
2049 else
2050 return 0;
2051}
2052
2053#define ADD16(a, b, n) RESULT(add16_usat(a, b), n, 16);
2054#define SUB16(a, b, n) RESULT(sub16_usat(a, b), n, 16);
2055#define ADD8(a, b, n) RESULT(add8_usat(a, b), n, 8);
2056#define SUB8(a, b, n) RESULT(sub8_usat(a, b), n, 8);
2057#define PFX uq
2058
2059#include "op_addsub.h"
2060
2061/* Signed modulo arithmetic. */
2062#define SARITH16(a, b, n, op) do { \
2063 int32_t sum; \
2064 sum = (int16_t)((uint16_t)(a) op (uint16_t)(b)); \
2065 RESULT(sum, n, 16); \
2066 if (sum >= 0) \
2067 ge |= 3 << (n * 2); \
2068 } while(0)
2069
2070#define SARITH8(a, b, n, op) do { \
2071 int32_t sum; \
2072 sum = (int8_t)((uint8_t)(a) op (uint8_t)(b)); \
2073 RESULT(sum, n, 8); \
2074 if (sum >= 0) \
2075 ge |= 1 << n; \
2076 } while(0)
2077
2078
2079#define ADD16(a, b, n) SARITH16(a, b, n, +)
2080#define SUB16(a, b, n) SARITH16(a, b, n, -)
2081#define ADD8(a, b, n) SARITH8(a, b, n, +)
2082#define SUB8(a, b, n) SARITH8(a, b, n, -)
2083#define PFX s
2084#define ARITH_GE
2085
2086#include "op_addsub.h"
2087
2088/* Unsigned modulo arithmetic. */
2089#define ADD16(a, b, n) do { \
2090 uint32_t sum; \
2091 sum = (uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b); \
2092 RESULT(sum, n, 16); \
a87aa10b 2093 if ((sum >> 16) == 1) \
6ddbc6e4
PB		 2094 ge |= 3 << (n * 2); \
2095 } while(0)
2096
2097#define ADD8(a, b, n) do { \
2098 uint32_t sum; \
2099 sum = (uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b); \
2100 RESULT(sum, n, 8); \
a87aa10b
AZ		 2101 if ((sum >> 8) == 1) \
2102 ge |= 1 << n; \
6ddbc6e4
PB		 2103 } while(0)
2104
2105#define SUB16(a, b, n) do { \
2106 uint32_t sum; \
2107 sum = (uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b); \
2108 RESULT(sum, n, 16); \
2109 if ((sum >> 16) == 0) \
2110 ge |= 3 << (n * 2); \
2111 } while(0)
2112
2113#define SUB8(a, b, n) do { \
2114 uint32_t sum; \
2115 sum = (uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b); \
2116 RESULT(sum, n, 8); \
2117 if ((sum >> 8) == 0) \
a87aa10b 2118 ge |= 1 << n; \
6ddbc6e4
PB		 2119 } while(0)
2120
2121#define PFX u
2122#define ARITH_GE
2123
2124#include "op_addsub.h"
2125
2126/* Halved signed arithmetic. */
2127#define ADD16(a, b, n) \
2128 RESULT(((int32_t)(int16_t)(a) + (int32_t)(int16_t)(b)) >> 1, n, 16)
2129#define SUB16(a, b, n) \
2130 RESULT(((int32_t)(int16_t)(a) - (int32_t)(int16_t)(b)) >> 1, n, 16)
2131#define ADD8(a, b, n) \
2132 RESULT(((int32_t)(int8_t)(a) + (int32_t)(int8_t)(b)) >> 1, n, 8)
2133#define SUB8(a, b, n) \
2134 RESULT(((int32_t)(int8_t)(a) - (int32_t)(int8_t)(b)) >> 1, n, 8)
2135#define PFX sh
2136
2137#include "op_addsub.h"
2138
2139/* Halved unsigned arithmetic. */
2140#define ADD16(a, b, n) \
2141 RESULT(((uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b)) >> 1, n, 16)
2142#define SUB16(a, b, n) \
2143 RESULT(((uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b)) >> 1, n, 16)
2144#define ADD8(a, b, n) \
2145 RESULT(((uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b)) >> 1, n, 8)
2146#define SUB8(a, b, n) \
2147 RESULT(((uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b)) >> 1, n, 8)
2148#define PFX uh
2149
2150#include "op_addsub.h"
2151
2152static inline uint8_t do_usad(uint8_t a, uint8_t b)
2153{
2154 if (a > b)
2155 return a - b;
2156 else
2157 return b - a;
2158}
2159
2160/* Unsigned sum of absolute byte differences. */
2161uint32_t HELPER(usad8)(uint32_t a, uint32_t b)
2162{
2163 uint32_t sum;
2164 sum = do_usad(a, b);
2165 sum += do_usad(a >> 8, b >> 8);
2166 sum += do_usad(a >> 16, b >>16);
2167 sum += do_usad(a >> 24, b >> 24);
2168 return sum;
2169}
2170
2171/* For ARMv6 SEL instruction. */
2172uint32_t HELPER(sel_flags)(uint32_t flags, uint32_t a, uint32_t b)
2173{
2174 uint32_t mask;
2175
2176 mask = 0;
2177 if (flags & 1)
2178 mask |= 0xff;
2179 if (flags & 2)
2180 mask |= 0xff00;
2181 if (flags & 4)
2182 mask |= 0xff0000;
2183 if (flags & 8)
2184 mask |= 0xff000000;
2185 return (a & mask) | (b & ~mask);
2186}
2187
5e3f878a
PB		 2188uint32_t HELPER(logicq_cc)(uint64_t val)
2189{
2190 return (val >> 32) | (val != 0);
2191}
4373f3ce
PB		 2192
2193/* VFP support. We follow the convention used for VFP instrunctions:
2194 Single precition routines have a "s" suffix, double precision a
2195 "d" suffix. */
2196
2197/* Convert host exception flags to vfp form. */
2198static inline int vfp_exceptbits_from_host(int host_bits)
2199{
2200 int target_bits = 0;
2201
2202 if (host_bits & float_flag_invalid)
2203 target_bits |= 1;
2204 if (host_bits & float_flag_divbyzero)
2205 target_bits |= 2;
2206 if (host_bits & float_flag_overflow)
2207 target_bits |= 4;
2208 if (host_bits & float_flag_underflow)
2209 target_bits |= 8;
2210 if (host_bits & float_flag_inexact)
2211 target_bits |= 0x10;
2212 return target_bits;
2213}
2214
2215uint32_t HELPER(vfp_get_fpscr)(CPUState *env)
2216{
2217 int i;
2218 uint32_t fpscr;
2219
2220 fpscr = (env->vfp.xregs[ARM_VFP_FPSCR] & 0xffc8ffff)
2221 | (env->vfp.vec_len << 16)
2222 | (env->vfp.vec_stride << 20);
2223 i = get_float_exception_flags(&env->vfp.fp_status);
2224 fpscr |= vfp_exceptbits_from_host(i);
2225 return fpscr;
2226}
2227
2228/* Convert vfp exception flags to target form. */
2229static inline int vfp_exceptbits_to_host(int target_bits)
2230{
2231 int host_bits = 0;
2232
2233 if (target_bits & 1)
2234 host_bits |= float_flag_invalid;
2235 if (target_bits & 2)
2236 host_bits |= float_flag_divbyzero;
2237 if (target_bits & 4)
2238 host_bits |= float_flag_overflow;
2239 if (target_bits & 8)
2240 host_bits |= float_flag_underflow;
2241 if (target_bits & 0x10)
2242 host_bits |= float_flag_inexact;
2243 return host_bits;
2244}
2245
2246void HELPER(vfp_set_fpscr)(CPUState *env, uint32_t val)
2247{
2248 int i;
2249 uint32_t changed;
2250
2251 changed = env->vfp.xregs[ARM_VFP_FPSCR];
2252 env->vfp.xregs[ARM_VFP_FPSCR] = (val & 0xffc8ffff);
2253 env->vfp.vec_len = (val >> 16) & 7;
2254 env->vfp.vec_stride = (val >> 20) & 3;
2255
2256 changed ^= val;
2257 if (changed & (3 << 22)) {
2258 i = (val >> 22) & 3;
2259 switch (i) {
2260 case 0:
2261 i = float_round_nearest_even;
2262 break;
2263 case 1:
2264 i = float_round_up;
2265 break;
2266 case 2:
2267 i = float_round_down;
2268 break;
2269 case 3:
2270 i = float_round_to_zero;
2271 break;
2272 }
2273 set_float_rounding_mode(i, &env->vfp.fp_status);
2274 }
fe76d976
PB		 2275 if (changed & (1 << 24))
2276 set_flush_to_zero((val & (1 << 24)) != 0, &env->vfp.fp_status);
5c7908ed
PB		 2277 if (changed & (1 << 25))
2278 set_default_nan_mode((val & (1 << 25)) != 0, &env->vfp.fp_status);
4373f3ce
PB		 2279
2280 i = vfp_exceptbits_to_host((val >> 8) & 0x1f);
2281 set_float_exception_flags(i, &env->vfp.fp_status);
4373f3ce
PB		 2282}
2283
2284#define VFP_HELPER(name, p) HELPER(glue(glue(vfp_,name),p))
2285
2286#define VFP_BINOP(name) \
2287float32 VFP_HELPER(name, s)(float32 a, float32 b, CPUState *env) \
2288{ \
2289 return float32_ ## name (a, b, &env->vfp.fp_status); \
2290} \
2291float64 VFP_HELPER(name, d)(float64 a, float64 b, CPUState *env) \
2292{ \
2293 return float64_ ## name (a, b, &env->vfp.fp_status); \
2294}
2295VFP_BINOP(add)
2296VFP_BINOP(sub)
2297VFP_BINOP(mul)
2298VFP_BINOP(div)
2299#undef VFP_BINOP
2300
2301float32 VFP_HELPER(neg, s)(float32 a)
2302{
2303 return float32_chs(a);
2304}
2305
2306float64 VFP_HELPER(neg, d)(float64 a)
2307{
66230e0d 2308 return float64_chs(a);
4373f3ce
PB		 2309}
2310
2311float32 VFP_HELPER(abs, s)(float32 a)
2312{
2313 return float32_abs(a);
2314}
2315
2316float64 VFP_HELPER(abs, d)(float64 a)
2317{
66230e0d 2318 return float64_abs(a);
4373f3ce
PB		 2319}
2320
2321float32 VFP_HELPER(sqrt, s)(float32 a, CPUState *env)
2322{
2323 return float32_sqrt(a, &env->vfp.fp_status);
2324}
2325
2326float64 VFP_HELPER(sqrt, d)(float64 a, CPUState *env)
2327{
2328 return float64_sqrt(a, &env->vfp.fp_status);
2329}
2330
2331/* XXX: check quiet/signaling case */
2332#define DO_VFP_cmp(p, type) \
2333void VFP_HELPER(cmp, p)(type a, type b, CPUState *env) \
2334{ \
2335 uint32_t flags; \
2336 switch(type ## _compare_quiet(a, b, &env->vfp.fp_status)) { \
2337 case 0: flags = 0x6; break; \
2338 case -1: flags = 0x8; break; \
2339 case 1: flags = 0x2; break; \
2340 default: case 2: flags = 0x3; break; \
2341 } \
2342 env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \
2343 | (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \
2344} \
2345void VFP_HELPER(cmpe, p)(type a, type b, CPUState *env) \
2346{ \
2347 uint32_t flags; \
2348 switch(type ## _compare(a, b, &env->vfp.fp_status)) { \
2349 case 0: flags = 0x6; break; \
2350 case -1: flags = 0x8; break; \
2351 case 1: flags = 0x2; break; \
2352 default: case 2: flags = 0x3; break; \
2353 } \
2354 env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \
2355 | (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \
2356}
2357DO_VFP_cmp(s, float32)
2358DO_VFP_cmp(d, float64)
2359#undef DO_VFP_cmp
2360
2361/* Helper routines to perform bitwise copies between float and int. */
2362static inline float32 vfp_itos(uint32_t i)
2363{
2364 union {
2365 uint32_t i;
2366 float32 s;
2367 } v;
2368
2369 v.i = i;
2370 return v.s;
2371}
2372
2373static inline uint32_t vfp_stoi(float32 s)
2374{
2375 union {
2376 uint32_t i;
2377 float32 s;
2378 } v;
2379
2380 v.s = s;
2381 return v.i;
2382}
2383
2384static inline float64 vfp_itod(uint64_t i)
2385{
2386 union {
2387 uint64_t i;
2388 float64 d;
2389 } v;
2390
2391 v.i = i;
2392 return v.d;
2393}
2394
2395static inline uint64_t vfp_dtoi(float64 d)
2396{
2397 union {
2398 uint64_t i;
2399 float64 d;
2400 } v;
2401
2402 v.d = d;
2403 return v.i;
2404}
2405
2406/* Integer to float conversion. */
2407float32 VFP_HELPER(uito, s)(float32 x, CPUState *env)
2408{
2409 return uint32_to_float32(vfp_stoi(x), &env->vfp.fp_status);
2410}
2411
2412float64 VFP_HELPER(uito, d)(float32 x, CPUState *env)
2413{
2414 return uint32_to_float64(vfp_stoi(x), &env->vfp.fp_status);
2415}
2416
2417float32 VFP_HELPER(sito, s)(float32 x, CPUState *env)
2418{
2419 return int32_to_float32(vfp_stoi(x), &env->vfp.fp_status);
2420}
2421
2422float64 VFP_HELPER(sito, d)(float32 x, CPUState *env)
2423{
2424 return int32_to_float64(vfp_stoi(x), &env->vfp.fp_status);
2425}
2426
2427/* Float to integer conversion. */
2428float32 VFP_HELPER(toui, s)(float32 x, CPUState *env)
2429{
2430 return vfp_itos(float32_to_uint32(x, &env->vfp.fp_status));
2431}
2432
2433float32 VFP_HELPER(toui, d)(float64 x, CPUState *env)
2434{
2435 return vfp_itos(float64_to_uint32(x, &env->vfp.fp_status));
2436}
2437
2438float32 VFP_HELPER(tosi, s)(float32 x, CPUState *env)
2439{
2440 return vfp_itos(float32_to_int32(x, &env->vfp.fp_status));
2441}
2442
2443float32 VFP_HELPER(tosi, d)(float64 x, CPUState *env)
2444{
2445 return vfp_itos(float64_to_int32(x, &env->vfp.fp_status));
2446}
2447
2448float32 VFP_HELPER(touiz, s)(float32 x, CPUState *env)
2449{
2450 return vfp_itos(float32_to_uint32_round_to_zero(x, &env->vfp.fp_status));
2451}
2452
2453float32 VFP_HELPER(touiz, d)(float64 x, CPUState *env)
2454{
2455 return vfp_itos(float64_to_uint32_round_to_zero(x, &env->vfp.fp_status));
2456}
2457
2458float32 VFP_HELPER(tosiz, s)(float32 x, CPUState *env)
2459{
2460 return vfp_itos(float32_to_int32_round_to_zero(x, &env->vfp.fp_status));
2461}
2462
2463float32 VFP_HELPER(tosiz, d)(float64 x, CPUState *env)
2464{
2465 return vfp_itos(float64_to_int32_round_to_zero(x, &env->vfp.fp_status));
2466}
2467
2468/* floating point conversion */
2469float64 VFP_HELPER(fcvtd, s)(float32 x, CPUState *env)
2470{
2471 return float32_to_float64(x, &env->vfp.fp_status);
2472}
2473
2474float32 VFP_HELPER(fcvts, d)(float64 x, CPUState *env)
2475{
2476 return float64_to_float32(x, &env->vfp.fp_status);
2477}
2478
2479/* VFP3 fixed point conversion. */
2480#define VFP_CONV_FIX(name, p, ftype, itype, sign) \
2481ftype VFP_HELPER(name##to, p)(ftype x, uint32_t shift, CPUState *env) \
2482{ \
2483 ftype tmp; \
2484 tmp = sign##int32_to_##ftype ((itype)vfp_##p##toi(x), \
2485 &env->vfp.fp_status); \
644ad806 2486 return ftype##_scalbn(tmp, -(int)shift, &env->vfp.fp_status); \
4373f3ce
PB		 2487} \
2488ftype VFP_HELPER(to##name, p)(ftype x, uint32_t shift, CPUState *env) \
2489{ \
2490 ftype tmp; \
2491 tmp = ftype##_scalbn(x, shift, &env->vfp.fp_status); \
2492 return vfp_ito##p((itype)ftype##_to_##sign##int32_round_to_zero(tmp, \
2493 &env->vfp.fp_status)); \
2494}
2495
2496VFP_CONV_FIX(sh, d, float64, int16, )
2497VFP_CONV_FIX(sl, d, float64, int32, )
2498VFP_CONV_FIX(uh, d, float64, uint16, u)
2499VFP_CONV_FIX(ul, d, float64, uint32, u)
2500VFP_CONV_FIX(sh, s, float32, int16, )
2501VFP_CONV_FIX(sl, s, float32, int32, )
2502VFP_CONV_FIX(uh, s, float32, uint16, u)
2503VFP_CONV_FIX(ul, s, float32, uint32, u)
2504#undef VFP_CONV_FIX
2505
60011498
PB		 2506/* Half precision conversions. */
2507float32 HELPER(vfp_fcvt_f16_to_f32)(uint32_t a, CPUState *env)
2508{
2509 float_status *s = &env->vfp.fp_status;
2510 int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0;
2511 return float16_to_float32(a, ieee, s);
2512}
2513
2514uint32_t HELPER(vfp_fcvt_f32_to_f16)(float32 a, CPUState *env)
2515{
2516 float_status *s = &env->vfp.fp_status;
2517 int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0;
2518 return float32_to_float16(a, ieee, s);
2519}
2520
4373f3ce
PB		 2521float32 HELPER(recps_f32)(float32 a, float32 b, CPUState *env)
2522{
2523 float_status *s = &env->vfp.fp_status;
2524 float32 two = int32_to_float32(2, s);
2525 return float32_sub(two, float32_mul(a, b, s), s);
2526}
2527
2528float32 HELPER(rsqrts_f32)(float32 a, float32 b, CPUState *env)
2529{
2530 float_status *s = &env->vfp.fp_status;
2531 float32 three = int32_to_float32(3, s);
2532 return float32_sub(three, float32_mul(a, b, s), s);
2533}
2534
8f8e3aa4
PB		 2535/* NEON helpers. */
2536
4373f3ce
PB		 2537/* TODO: The architecture specifies the value that the estimate functions
2538 should return. We return the exact reciprocal/root instead. */
2539float32 HELPER(recpe_f32)(float32 a, CPUState *env)
2540{
2541 float_status *s = &env->vfp.fp_status;
2542 float32 one = int32_to_float32(1, s);
2543 return float32_div(one, a, s);
2544}
2545
2546float32 HELPER(rsqrte_f32)(float32 a, CPUState *env)
2547{
2548 float_status *s = &env->vfp.fp_status;
2549 float32 one = int32_to_float32(1, s);
2550 return float32_div(one, float32_sqrt(a, s), s);
2551}
2552
2553uint32_t HELPER(recpe_u32)(uint32_t a, CPUState *env)
2554{
2555 float_status *s = &env->vfp.fp_status;
2556 float32 tmp;
2557 tmp = int32_to_float32(a, s);
2558 tmp = float32_scalbn(tmp, -32, s);
2559 tmp = helper_recpe_f32(tmp, env);
2560 tmp = float32_scalbn(tmp, 31, s);
2561 return float32_to_int32(tmp, s);
2562}
2563
2564uint32_t HELPER(rsqrte_u32)(uint32_t a, CPUState *env)
2565{
2566 float_status *s = &env->vfp.fp_status;
2567 float32 tmp;
2568 tmp = int32_to_float32(a, s);
2569 tmp = float32_scalbn(tmp, -32, s);
2570 tmp = helper_rsqrte_f32(tmp, env);
2571 tmp = float32_scalbn(tmp, 31, s);
2572 return float32_to_int32(tmp, s);
2573}
fe1479c3
PB		 2574
2575void HELPER(set_teecr)(CPUState *env, uint32_t val)
2576{
2577 val &= 1;
2578 if (env->teecr != val) {
2579 env->teecr = val;
2580 tb_flush(env);
2581 }
2582}
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