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[mirror_qemu.git] / target-arm / helper.c
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b5ff1b31 1#include "cpu.h"
022c62cb 2#include "exec/gdbstub.h"
7b59220e 3#include "helper.h"
1de7afc9 4#include "qemu/host-utils.h"
9c17d615 5#include "sysemu/sysemu.h"
1de7afc9 6#include "qemu/bitops.h"
0b03bdfc 7
4a501606
PM		 8#ifndef CONFIG_USER_ONLY
9static inline int get_phys_addr(CPUARMState *env, uint32_t address,
10 int access_type, int is_user,
a8170e5e 11 hwaddr *phys_ptr, int *prot,
4a501606
PM		 12 target_ulong *page_size);
13#endif
14
0ecb72a5 15static int vfp_gdb_get_reg(CPUARMState *env, uint8_t *buf, int reg)
56aebc89
PB		 16{
17 int nregs;
18
19 /* VFP data registers are always little-endian. */
20 nregs = arm_feature(env, ARM_FEATURE_VFP3) ? 32 : 16;
21 if (reg < nregs) {
22 stfq_le_p(buf, env->vfp.regs[reg]);
23 return 8;
24 }
25 if (arm_feature(env, ARM_FEATURE_NEON)) {
26 /* Aliases for Q regs. */
27 nregs += 16;
28 if (reg < nregs) {
29 stfq_le_p(buf, env->vfp.regs[(reg - 32) * 2]);
30 stfq_le_p(buf + 8, env->vfp.regs[(reg - 32) * 2 + 1]);
31 return 16;
32 }
33 }
34 switch (reg - nregs) {
35 case 0: stl_p(buf, env->vfp.xregs[ARM_VFP_FPSID]); return 4;
36 case 1: stl_p(buf, env->vfp.xregs[ARM_VFP_FPSCR]); return 4;
37 case 2: stl_p(buf, env->vfp.xregs[ARM_VFP_FPEXC]); return 4;
38 }
39 return 0;
40}
41
0ecb72a5 42static int vfp_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg)
56aebc89
PB		 43{
44 int nregs;
45
46 nregs = arm_feature(env, ARM_FEATURE_VFP3) ? 32 : 16;
47 if (reg < nregs) {
48 env->vfp.regs[reg] = ldfq_le_p(buf);
49 return 8;
50 }
51 if (arm_feature(env, ARM_FEATURE_NEON)) {
52 nregs += 16;
53 if (reg < nregs) {
54 env->vfp.regs[(reg - 32) * 2] = ldfq_le_p(buf);
55 env->vfp.regs[(reg - 32) * 2 + 1] = ldfq_le_p(buf + 8);
56 return 16;
57 }
58 }
59 switch (reg - nregs) {
60 case 0: env->vfp.xregs[ARM_VFP_FPSID] = ldl_p(buf); return 4;
61 case 1: env->vfp.xregs[ARM_VFP_FPSCR] = ldl_p(buf); return 4;
71b3c3de 62 case 2: env->vfp.xregs[ARM_VFP_FPEXC] = ldl_p(buf) & (1 << 30); return 4;
56aebc89
PB		 63 }
64 return 0;
65}
66
d4e6df63
PM		 67static int raw_read(CPUARMState *env, const ARMCPRegInfo *ri,
68 uint64_t *value)
69{
22d9e1a9
PM		 70 if (ri->type & ARM_CP_64BIT) {
71 *value = CPREG_FIELD64(env, ri);
72 } else {
73 *value = CPREG_FIELD32(env, ri);
74 }
d4e6df63
PM		 75 return 0;
76}
77
78static int raw_write(CPUARMState *env, const ARMCPRegInfo *ri,
79 uint64_t value)
80{
22d9e1a9
PM		 81 if (ri->type & ARM_CP_64BIT) {
82 CPREG_FIELD64(env, ri) = value;
83 } else {
84 CPREG_FIELD32(env, ri) = value;
85 }
d4e6df63
PM		 86 return 0;
87}
88
721fae12
PM		 89static bool read_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri,
90 uint64_t *v)
91{
92 /* Raw read of a coprocessor register (as needed for migration, etc)
93 * return true on success, false if the read is impossible for some reason.
94 */
95 if (ri->type & ARM_CP_CONST) {
96 *v = ri->resetvalue;
97 } else if (ri->raw_readfn) {
98 return (ri->raw_readfn(env, ri, v) == 0);
99 } else if (ri->readfn) {
100 return (ri->readfn(env, ri, v) == 0);
101 } else {
102 if (ri->type & ARM_CP_64BIT) {
103 *v = CPREG_FIELD64(env, ri);
104 } else {
105 *v = CPREG_FIELD32(env, ri);
106 }
107 }
108 return true;
109}
110
111static bool write_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri,
112 int64_t v)
113{
114 /* Raw write of a coprocessor register (as needed for migration, etc).
115 * Return true on success, false if the write is impossible for some reason.
116 * Note that constant registers are treated as write-ignored; the
117 * caller should check for success by whether a readback gives the
118 * value written.
119 */
120 if (ri->type & ARM_CP_CONST) {
121 return true;
122 } else if (ri->raw_writefn) {
123 return (ri->raw_writefn(env, ri, v) == 0);
124 } else if (ri->writefn) {
125 return (ri->writefn(env, ri, v) == 0);
126 } else {
127 if (ri->type & ARM_CP_64BIT) {
128 CPREG_FIELD64(env, ri) = v;
129 } else {
130 CPREG_FIELD32(env, ri) = v;
131 }
132 }
133 return true;
134}
135
136bool write_cpustate_to_list(ARMCPU *cpu)
137{
138 /* Write the coprocessor state from cpu->env to the (index,value) list. */
139 int i;
140 bool ok = true;
141
142 for (i = 0; i < cpu->cpreg_array_len; i++) {
143 uint32_t regidx = kvm_to_cpreg_id(cpu->cpreg_indexes[i]);
144 const ARMCPRegInfo *ri;
145 uint64_t v;
146 ri = get_arm_cp_reginfo(cpu, regidx);
147 if (!ri) {
148 ok = false;
149 continue;
150 }
151 if (ri->type & ARM_CP_NO_MIGRATE) {
152 continue;
153 }
154 if (!read_raw_cp_reg(&cpu->env, ri, &v)) {
155 ok = false;
156 continue;
157 }
158 cpu->cpreg_values[i] = v;
159 }
160 return ok;
161}
162
163bool write_list_to_cpustate(ARMCPU *cpu)
164{
165 int i;
166 bool ok = true;
167
168 for (i = 0; i < cpu->cpreg_array_len; i++) {
169 uint32_t regidx = kvm_to_cpreg_id(cpu->cpreg_indexes[i]);
170 uint64_t v = cpu->cpreg_values[i];
171 uint64_t readback;
172 const ARMCPRegInfo *ri;
173
174 ri = get_arm_cp_reginfo(cpu, regidx);
175 if (!ri) {
176 ok = false;
177 continue;
178 }
179 if (ri->type & ARM_CP_NO_MIGRATE) {
180 continue;
181 }
182 /* Write value and confirm it reads back as written
183 * (to catch read-only registers and partially read-only
184 * registers where the incoming migration value doesn't match)
185 */
186 if (!write_raw_cp_reg(&cpu->env, ri, v) ||
187 !read_raw_cp_reg(&cpu->env, ri, &readback) ||
188 readback != v) {
189 ok = false;
190 }
191 }
192 return ok;
193}
194
195static void add_cpreg_to_list(gpointer key, gpointer opaque)
196{
197 ARMCPU *cpu = opaque;
198 uint64_t regidx;
199 const ARMCPRegInfo *ri;
200
201 regidx = *(uint32_t *)key;
202 ri = get_arm_cp_reginfo(cpu, regidx);
203
204 if (!(ri->type & ARM_CP_NO_MIGRATE)) {
205 cpu->cpreg_indexes[cpu->cpreg_array_len] = cpreg_to_kvm_id(regidx);
206 /* The value array need not be initialized at this point */
207 cpu->cpreg_array_len++;
208 }
209}
210
211static void count_cpreg(gpointer key, gpointer opaque)
212{
213 ARMCPU *cpu = opaque;
214 uint64_t regidx;
215 const ARMCPRegInfo *ri;
216
217 regidx = *(uint32_t *)key;
218 ri = get_arm_cp_reginfo(cpu, regidx);
219
220 if (!(ri->type & ARM_CP_NO_MIGRATE)) {
221 cpu->cpreg_array_len++;
222 }
223}
224
225static gint cpreg_key_compare(gconstpointer a, gconstpointer b)
226{
227 uint32_t aidx = *(uint32_t *)a;
228 uint32_t bidx = *(uint32_t *)b;
229
230 return aidx - bidx;
231}
232
82a3a118
PM		 233static void cpreg_make_keylist(gpointer key, gpointer value, gpointer udata)
234{
235 GList **plist = udata;
236
237 *plist = g_list_prepend(*plist, key);
238}
239
721fae12
PM		 240void init_cpreg_list(ARMCPU *cpu)
241{
242 /* Initialise the cpreg_tuples[] array based on the cp_regs hash.
243 * Note that we require cpreg_tuples[] to be sorted by key ID.
244 */
82a3a118 245 GList *keys = NULL;
721fae12
PM		 246 int arraylen;
247
82a3a118
PM		 248 g_hash_table_foreach(cpu->cp_regs, cpreg_make_keylist, &keys);
249
721fae12
PM		 250 keys = g_list_sort(keys, cpreg_key_compare);
251
252 cpu->cpreg_array_len = 0;
253
254 g_list_foreach(keys, count_cpreg, cpu);
255
256 arraylen = cpu->cpreg_array_len;
257 cpu->cpreg_indexes = g_new(uint64_t, arraylen);
258 cpu->cpreg_values = g_new(uint64_t, arraylen);
259 cpu->cpreg_vmstate_indexes = g_new(uint64_t, arraylen);
260 cpu->cpreg_vmstate_values = g_new(uint64_t, arraylen);
261 cpu->cpreg_vmstate_array_len = cpu->cpreg_array_len;
262 cpu->cpreg_array_len = 0;
263
264 g_list_foreach(keys, add_cpreg_to_list, cpu);
265
266 assert(cpu->cpreg_array_len == arraylen);
267
268 g_list_free(keys);
269}
270
c983fe6c
PM		 271static int dacr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
272{
273 env->cp15.c3 = value;
274 tlb_flush(env, 1); /* Flush TLB as domain not tracked in TLB */
275 return 0;
276}
277
08de207b
PM		 278static int fcse_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
279{
280 if (env->cp15.c13_fcse != value) {
281 /* Unlike real hardware the qemu TLB uses virtual addresses,
282 * not modified virtual addresses, so this causes a TLB flush.
283 */
284 tlb_flush(env, 1);
285 env->cp15.c13_fcse = value;
286 }
287 return 0;
288}
289static int contextidr_write(CPUARMState *env, const ARMCPRegInfo *ri,
290 uint64_t value)
291{
292 if (env->cp15.c13_context != value && !arm_feature(env, ARM_FEATURE_MPU)) {
293 /* For VMSA (when not using the LPAE long descriptor page table
294 * format) this register includes the ASID, so do a TLB flush.
295 * For PMSA it is purely a process ID and no action is needed.
296 */
297 tlb_flush(env, 1);
298 }
299 env->cp15.c13_context = value;
300 return 0;
301}
302
d929823f
PM		 303static int tlbiall_write(CPUARMState *env, const ARMCPRegInfo *ri,
304 uint64_t value)
305{
306 /* Invalidate all (TLBIALL) */
307 tlb_flush(env, 1);
308 return 0;
309}
310
311static int tlbimva_write(CPUARMState *env, const ARMCPRegInfo *ri,
312 uint64_t value)
313{
314 /* Invalidate single TLB entry by MVA and ASID (TLBIMVA) */
315 tlb_flush_page(env, value & TARGET_PAGE_MASK);
316 return 0;
317}
318
319static int tlbiasid_write(CPUARMState *env, const ARMCPRegInfo *ri,
320 uint64_t value)
321{
322 /* Invalidate by ASID (TLBIASID) */
323 tlb_flush(env, value == 0);
324 return 0;
325}
326
327static int tlbimvaa_write(CPUARMState *env, const ARMCPRegInfo *ri,
328 uint64_t value)
329{
330 /* Invalidate single entry by MVA, all ASIDs (TLBIMVAA) */
331 tlb_flush_page(env, value & TARGET_PAGE_MASK);
332 return 0;
333}
334
e9aa6c21
PM		 335static const ARMCPRegInfo cp_reginfo[] = {
336 /* DBGDIDR: just RAZ. In particular this means the "debug architecture
337 * version" bits will read as a reserved value, which should cause
338 * Linux to not try to use the debug hardware.
339 */
340 { .name = "DBGDIDR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 0,
341 .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 },
c983fe6c
PM		 342 /* MMU Domain access control / MPU write buffer control */
343 { .name = "DACR", .cp = 15,
344 .crn = 3, .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY,
345 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c3),
d4e6df63 346 .resetvalue = 0, .writefn = dacr_write, .raw_writefn = raw_write, },
08de207b
PM		 347 { .name = "FCSEIDR", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 0,
348 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c13_fcse),
d4e6df63 349 .resetvalue = 0, .writefn = fcse_write, .raw_writefn = raw_write, },
08de207b
PM		 350 { .name = "CONTEXTIDR", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 1,
351 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c13_fcse),
d4e6df63 352 .resetvalue = 0, .writefn = contextidr_write, .raw_writefn = raw_write, },
4fdd17dd
PM		 353 /* ??? This covers not just the impdef TLB lockdown registers but also
354 * some v7VMSA registers relating to TEX remap, so it is overly broad.
355 */
356 { .name = "TLB_LOCKDOWN", .cp = 15, .crn = 10, .crm = CP_ANY,
357 .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_NOP },
d929823f
PM		 358 /* MMU TLB control. Note that the wildcarding means we cover not just
359 * the unified TLB ops but also the dside/iside/inner-shareable variants.
360 */
361 { .name = "TLBIALL", .cp = 15, .crn = 8, .crm = CP_ANY,
d4e6df63
PM		 362 .opc1 = CP_ANY, .opc2 = 0, .access = PL1_W, .writefn = tlbiall_write,
363 .type = ARM_CP_NO_MIGRATE },
d929823f 364 { .name = "TLBIMVA", .cp = 15, .crn = 8, .crm = CP_ANY,
d4e6df63
PM		 365 .opc1 = CP_ANY, .opc2 = 1, .access = PL1_W, .writefn = tlbimva_write,
366 .type = ARM_CP_NO_MIGRATE },
d929823f 367 { .name = "TLBIASID", .cp = 15, .crn = 8, .crm = CP_ANY,
d4e6df63
PM		 368 .opc1 = CP_ANY, .opc2 = 2, .access = PL1_W, .writefn = tlbiasid_write,
369 .type = ARM_CP_NO_MIGRATE },
d929823f 370 { .name = "TLBIMVAA", .cp = 15, .crn = 8, .crm = CP_ANY,
d4e6df63
PM		 371 .opc1 = CP_ANY, .opc2 = 3, .access = PL1_W, .writefn = tlbimvaa_write,
372 .type = ARM_CP_NO_MIGRATE },
c4804214
PM		 373 /* Cache maintenance ops; some of this space may be overridden later. */
374 { .name = "CACHEMAINT", .cp = 15, .crn = 7, .crm = CP_ANY,
375 .opc1 = 0, .opc2 = CP_ANY, .access = PL1_W,
376 .type = ARM_CP_NOP | ARM_CP_OVERRIDE },
e9aa6c21
PM		 377 REGINFO_SENTINEL
378};
379
7d57f408
PM		 380static const ARMCPRegInfo not_v6_cp_reginfo[] = {
381 /* Not all pre-v6 cores implemented this WFI, so this is slightly
382 * over-broad.
383 */
384 { .name = "WFI_v5", .cp = 15, .crn = 7, .crm = 8, .opc1 = 0, .opc2 = 2,
385 .access = PL1_W, .type = ARM_CP_WFI },
386 REGINFO_SENTINEL
387};
388
389static const ARMCPRegInfo not_v7_cp_reginfo[] = {
390 /* Standard v6 WFI (also used in some pre-v6 cores); not in v7 (which
391 * is UNPREDICTABLE; we choose to NOP as most implementations do).
392 */
393 { .name = "WFI_v6", .cp = 15, .crn = 7, .crm = 0, .opc1 = 0, .opc2 = 4,
394 .access = PL1_W, .type = ARM_CP_WFI },
34f90529
PM		 395 /* L1 cache lockdown. Not architectural in v6 and earlier but in practice
396 * implemented in 926, 946, 1026, 1136, 1176 and 11MPCore. StrongARM and
397 * OMAPCP will override this space.
398 */
399 { .name = "DLOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 0, .opc2 = 0,
400 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_data),
401 .resetvalue = 0 },
402 { .name = "ILOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 0, .opc2 = 1,
403 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_insn),
404 .resetvalue = 0 },
776d4e5c
PM		 405 /* v6 doesn't have the cache ID registers but Linux reads them anyway */
406 { .name = "DUMMY", .cp = 15, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = CP_ANY,
d4e6df63
PM		 407 .access = PL1_R, .type = ARM_CP_CONST | ARM_CP_NO_MIGRATE,
408 .resetvalue = 0 },
7d57f408
PM		 409 REGINFO_SENTINEL
410};
411
2771db27
PM		 412static int cpacr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
413{
414 if (env->cp15.c1_coproc != value) {
415 env->cp15.c1_coproc = value;
416 /* ??? Is this safe when called from within a TB? */
417 tb_flush(env);
418 }
419 return 0;
420}
421
7d57f408
PM		 422static const ARMCPRegInfo v6_cp_reginfo[] = {
423 /* prefetch by MVA in v6, NOP in v7 */
424 { .name = "MVA_prefetch",
425 .cp = 15, .crn = 7, .crm = 13, .opc1 = 0, .opc2 = 1,
426 .access = PL1_W, .type = ARM_CP_NOP },
427 { .name = "ISB", .cp = 15, .crn = 7, .crm = 5, .opc1 = 0, .opc2 = 4,
428 .access = PL0_W, .type = ARM_CP_NOP },
091fd17c 429 { .name = "DSB", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 4,
7d57f408 430 .access = PL0_W, .type = ARM_CP_NOP },
091fd17c 431 { .name = "DMB", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 5,
7d57f408 432 .access = PL0_W, .type = ARM_CP_NOP },
06d76f31
PM		 433 { .name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 2,
434 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c6_insn),
435 .resetvalue = 0, },
436 /* Watchpoint Fault Address Register : should actually only be present
437 * for 1136, 1176, 11MPCore.
438 */
439 { .name = "WFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1,
440 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0, },
2771db27
PM		 441 { .name = "CPACR", .cp = 15, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 2,
442 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c1_coproc),
443 .resetvalue = 0, .writefn = cpacr_write },
7d57f408
PM		 444 REGINFO_SENTINEL
445};
446
d4e6df63 447
200ac0ef
PM		 448static int pmreg_read(CPUARMState *env, const ARMCPRegInfo *ri,
449 uint64_t *value)
450{
451 /* Generic performance monitor register read function for where
452 * user access may be allowed by PMUSERENR.
453 */
454 if (arm_current_pl(env) == 0 && !env->cp15.c9_pmuserenr) {
455 return EXCP_UDEF;
456 }
457 *value = CPREG_FIELD32(env, ri);
458 return 0;
459}
460
461static int pmcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
462 uint64_t value)
463{
464 if (arm_current_pl(env) == 0 && !env->cp15.c9_pmuserenr) {
465 return EXCP_UDEF;
466 }
467 /* only the DP, X, D and E bits are writable */
468 env->cp15.c9_pmcr &= ~0x39;
469 env->cp15.c9_pmcr |= (value & 0x39);
470 return 0;
471}
472
473static int pmcntenset_write(CPUARMState *env, const ARMCPRegInfo *ri,
474 uint64_t value)
475{
476 if (arm_current_pl(env) == 0 && !env->cp15.c9_pmuserenr) {
477 return EXCP_UDEF;
478 }
479 value &= (1 << 31);
480 env->cp15.c9_pmcnten |= value;
481 return 0;
482}
483
484static int pmcntenclr_write(CPUARMState *env, const ARMCPRegInfo *ri,
485 uint64_t value)
486{
487 if (arm_current_pl(env) == 0 && !env->cp15.c9_pmuserenr) {
488 return EXCP_UDEF;
489 }
490 value &= (1 << 31);
491 env->cp15.c9_pmcnten &= ~value;
492 return 0;
493}
494
495static int pmovsr_write(CPUARMState *env, const ARMCPRegInfo *ri,
496 uint64_t value)
497{
498 if (arm_current_pl(env) == 0 && !env->cp15.c9_pmuserenr) {
499 return EXCP_UDEF;
500 }
501 env->cp15.c9_pmovsr &= ~value;
502 return 0;
503}
504
505static int pmxevtyper_write(CPUARMState *env, const ARMCPRegInfo *ri,
506 uint64_t value)
507{
508 if (arm_current_pl(env) == 0 && !env->cp15.c9_pmuserenr) {
509 return EXCP_UDEF;
510 }
511 env->cp15.c9_pmxevtyper = value & 0xff;
512 return 0;
513}
514
515static int pmuserenr_write(CPUARMState *env, const ARMCPRegInfo *ri,
516 uint64_t value)
517{
518 env->cp15.c9_pmuserenr = value & 1;
519 return 0;
520}
521
522static int pmintenset_write(CPUARMState *env, const ARMCPRegInfo *ri,
523 uint64_t value)
524{
525 /* We have no event counters so only the C bit can be changed */
526 value &= (1 << 31);
527 env->cp15.c9_pminten |= value;
528 return 0;
529}
530
531static int pmintenclr_write(CPUARMState *env, const ARMCPRegInfo *ri,
532 uint64_t value)
533{
534 value &= (1 << 31);
535 env->cp15.c9_pminten &= ~value;
536 return 0;
537}
538
776d4e5c
PM		 539static int ccsidr_read(CPUARMState *env, const ARMCPRegInfo *ri,
540 uint64_t *value)
541{
542 ARMCPU *cpu = arm_env_get_cpu(env);
543 *value = cpu->ccsidr[env->cp15.c0_cssel];
544 return 0;
545}
546
547static int csselr_write(CPUARMState *env, const ARMCPRegInfo *ri,
548 uint64_t value)
549{
550 env->cp15.c0_cssel = value & 0xf;
551 return 0;
552}
553
e9aa6c21
PM		 554static const ARMCPRegInfo v7_cp_reginfo[] = {
555 /* DBGDRAR, DBGDSAR: always RAZ since we don't implement memory mapped
556 * debug components
557 */
558 { .name = "DBGDRAR", .cp = 14, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 0,
559 .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 },
091fd17c 560 { .name = "DBGDSAR", .cp = 14, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 0,
e9aa6c21 561 .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 },
7d57f408
PM		 562 /* the old v6 WFI, UNPREDICTABLE in v7 but we choose to NOP */
563 { .name = "NOP", .cp = 15, .crn = 7, .crm = 0, .opc1 = 0, .opc2 = 4,
564 .access = PL1_W, .type = ARM_CP_NOP },
200ac0ef
PM		 565 /* Performance monitors are implementation defined in v7,
566 * but with an ARM recommended set of registers, which we
567 * follow (although we don't actually implement any counters)
568 *
569 * Performance registers fall into three categories:
570 * (a) always UNDEF in PL0, RW in PL1 (PMINTENSET, PMINTENCLR)
571 * (b) RO in PL0 (ie UNDEF on write), RW in PL1 (PMUSERENR)
572 * (c) UNDEF in PL0 if PMUSERENR.EN==0, otherwise accessible (all others)
573 * For the cases controlled by PMUSERENR we must set .access to PL0_RW
574 * or PL0_RO as appropriate and then check PMUSERENR in the helper fn.
575 */
576 { .name = "PMCNTENSET", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 1,
577 .access = PL0_RW, .resetvalue = 0,
578 .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcnten),
d4e6df63
PM		 579 .readfn = pmreg_read, .writefn = pmcntenset_write,
580 .raw_readfn = raw_read, .raw_writefn = raw_write },
200ac0ef
PM		 581 { .name = "PMCNTENCLR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 2,
582 .access = PL0_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcnten),
d4e6df63
PM		 583 .readfn = pmreg_read, .writefn = pmcntenclr_write,
584 .type = ARM_CP_NO_MIGRATE },
200ac0ef
PM		 585 { .name = "PMOVSR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 3,
586 .access = PL0_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_pmovsr),
d4e6df63
PM		 587 .readfn = pmreg_read, .writefn = pmovsr_write,
588 .raw_readfn = raw_read, .raw_writefn = raw_write },
200ac0ef
PM		 589 /* Unimplemented so WI. Strictly speaking write accesses in PL0 should
590 * respect PMUSERENR.
591 */
592 { .name = "PMSWINC", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 4,
593 .access = PL0_W, .type = ARM_CP_NOP },
594 /* Since we don't implement any events, writing to PMSELR is UNPREDICTABLE.
595 * We choose to RAZ/WI. XXX should respect PMUSERENR.
596 */
597 { .name = "PMSELR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 5,
598 .access = PL0_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
599 /* Unimplemented, RAZ/WI. XXX PMUSERENR */
600 { .name = "PMCCNTR", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 0,
601 .access = PL0_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
602 { .name = "PMXEVTYPER", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 1,
603 .access = PL0_RW,
604 .fieldoffset = offsetof(CPUARMState, cp15.c9_pmxevtyper),
d4e6df63
PM		 605 .readfn = pmreg_read, .writefn = pmxevtyper_write,
606 .raw_readfn = raw_read, .raw_writefn = raw_write },
200ac0ef
PM		 607 /* Unimplemented, RAZ/WI. XXX PMUSERENR */
608 { .name = "PMXEVCNTR", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 2,
609 .access = PL0_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
610 { .name = "PMUSERENR", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 0,
611 .access = PL0_R | PL1_RW,
612 .fieldoffset = offsetof(CPUARMState, cp15.c9_pmuserenr),
613 .resetvalue = 0,
d4e6df63 614 .writefn = pmuserenr_write, .raw_writefn = raw_write },
200ac0ef
PM		 615 { .name = "PMINTENSET", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 1,
616 .access = PL1_RW,
617 .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten),
618 .resetvalue = 0,
d4e6df63 619 .writefn = pmintenset_write, .raw_writefn = raw_write },
200ac0ef 620 { .name = "PMINTENCLR", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 2,
d4e6df63 621 .access = PL1_RW, .type = ARM_CP_NO_MIGRATE,
200ac0ef 622 .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten),
d4e6df63 623 .resetvalue = 0, .writefn = pmintenclr_write, },
2771db27
PM		 624 { .name = "SCR", .cp = 15, .crn = 1, .crm = 1, .opc1 = 0, .opc2 = 0,
625 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c1_scr),
626 .resetvalue = 0, },
776d4e5c 627 { .name = "CCSIDR", .cp = 15, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 0,
d4e6df63 628 .access = PL1_R, .readfn = ccsidr_read, .type = ARM_CP_NO_MIGRATE },
776d4e5c
PM		 629 { .name = "CSSELR", .cp = 15, .crn = 0, .crm = 0, .opc1 = 2, .opc2 = 0,
630 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c0_cssel),
631 .writefn = csselr_write, .resetvalue = 0 },
632 /* Auxiliary ID register: this actually has an IMPDEF value but for now
633 * just RAZ for all cores:
634 */
635 { .name = "AIDR", .cp = 15, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 7,
636 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
e9aa6c21
PM		 637 REGINFO_SENTINEL
638};
639
c326b979
PM		 640static int teecr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
641{
642 value &= 1;
643 env->teecr = value;
644 return 0;
645}
646
647static int teehbr_read(CPUARMState *env, const ARMCPRegInfo *ri,
648 uint64_t *value)
649{
650 /* This is a helper function because the user access rights
651 * depend on the value of the TEECR.
652 */
653 if (arm_current_pl(env) == 0 && (env->teecr & 1)) {
654 return EXCP_UDEF;
655 }
656 *value = env->teehbr;
657 return 0;
658}
659
660static int teehbr_write(CPUARMState *env, const ARMCPRegInfo *ri,
661 uint64_t value)
662{
663 if (arm_current_pl(env) == 0 && (env->teecr & 1)) {
664 return EXCP_UDEF;
665 }
666 env->teehbr = value;
667 return 0;
668}
669
670static const ARMCPRegInfo t2ee_cp_reginfo[] = {
671 { .name = "TEECR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 6, .opc2 = 0,
672 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, teecr),
673 .resetvalue = 0,
674 .writefn = teecr_write },
675 { .name = "TEEHBR", .cp = 14, .crn = 1, .crm = 0, .opc1 = 6, .opc2 = 0,
676 .access = PL0_RW, .fieldoffset = offsetof(CPUARMState, teehbr),
d4e6df63 677 .resetvalue = 0, .raw_readfn = raw_read, .raw_writefn = raw_write,
c326b979
PM		 678 .readfn = teehbr_read, .writefn = teehbr_write },
679 REGINFO_SENTINEL
680};
681
4d31c596
PM		 682static const ARMCPRegInfo v6k_cp_reginfo[] = {
683 { .name = "TPIDRURW", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 2,
684 .access = PL0_RW,
685 .fieldoffset = offsetof(CPUARMState, cp15.c13_tls1),
686 .resetvalue = 0 },
687 { .name = "TPIDRURO", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 3,
688 .access = PL0_R|PL1_W,
689 .fieldoffset = offsetof(CPUARMState, cp15.c13_tls2),
690 .resetvalue = 0 },
691 { .name = "TPIDRPRW", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 4,
692 .access = PL1_RW,
693 .fieldoffset = offsetof(CPUARMState, cp15.c13_tls3),
694 .resetvalue = 0 },
695 REGINFO_SENTINEL
696};
697
55d284af
PM		 698#ifndef CONFIG_USER_ONLY
699
700static uint64_t gt_get_countervalue(CPUARMState *env)
701{
bc72ad67 702 return qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) / GTIMER_SCALE;
55d284af
PM		 703}
704
705static void gt_recalc_timer(ARMCPU *cpu, int timeridx)
706{
707 ARMGenericTimer *gt = &cpu->env.cp15.c14_timer[timeridx];
708
709 if (gt->ctl & 1) {
710 /* Timer enabled: calculate and set current ISTATUS, irq, and
711 * reset timer to when ISTATUS next has to change
712 */
713 uint64_t count = gt_get_countervalue(&cpu->env);
714 /* Note that this must be unsigned 64 bit arithmetic: */
715 int istatus = count >= gt->cval;
716 uint64_t nexttick;
717
718 gt->ctl = deposit32(gt->ctl, 2, 1, istatus);
719 qemu_set_irq(cpu->gt_timer_outputs[timeridx],
720 (istatus && !(gt->ctl & 2)));
721 if (istatus) {
722 /* Next transition is when count rolls back over to zero */
723 nexttick = UINT64_MAX;
724 } else {
725 /* Next transition is when we hit cval */
726 nexttick = gt->cval;
727 }
728 /* Note that the desired next expiry time might be beyond the
729 * signed-64-bit range of a QEMUTimer -- in this case we just
730 * set the timer for as far in the future as possible. When the
731 * timer expires we will reset the timer for any remaining period.
732 */
733 if (nexttick > INT64_MAX / GTIMER_SCALE) {
734 nexttick = INT64_MAX / GTIMER_SCALE;
735 }
bc72ad67 736 timer_mod(cpu->gt_timer[timeridx], nexttick);
55d284af
PM		 737 } else {
738 /* Timer disabled: ISTATUS and timer output always clear */
739 gt->ctl &= ~4;
740 qemu_set_irq(cpu->gt_timer_outputs[timeridx], 0);
bc72ad67 741 timer_del(cpu->gt_timer[timeridx]);
55d284af
PM		 742 }
743}
744
745static int gt_cntfrq_read(CPUARMState *env, const ARMCPRegInfo *ri,
746 uint64_t *value)
747{
748 /* Not visible from PL0 if both PL0PCTEN and PL0VCTEN are zero */
749 if (arm_current_pl(env) == 0 && !extract32(env->cp15.c14_cntkctl, 0, 2)) {
750 return EXCP_UDEF;
751 }
752 *value = env->cp15.c14_cntfrq;
753 return 0;
754}
755
756static void gt_cnt_reset(CPUARMState *env, const ARMCPRegInfo *ri)
757{
758 ARMCPU *cpu = arm_env_get_cpu(env);
759 int timeridx = ri->opc1 & 1;
760
bc72ad67 761 timer_del(cpu->gt_timer[timeridx]);
55d284af
PM		 762}
763
764static int gt_cnt_read(CPUARMState *env, const ARMCPRegInfo *ri,
765 uint64_t *value)
766{
767 int timeridx = ri->opc1 & 1;
768
769 if (arm_current_pl(env) == 0 &&
770 !extract32(env->cp15.c14_cntkctl, timeridx, 1)) {
771 return EXCP_UDEF;
772 }
773 *value = gt_get_countervalue(env);
774 return 0;
775}
776
777static int gt_cval_read(CPUARMState *env, const ARMCPRegInfo *ri,
778 uint64_t *value)
779{
780 int timeridx = ri->opc1 & 1;
781
782 if (arm_current_pl(env) == 0 &&
783 !extract32(env->cp15.c14_cntkctl, 9 - timeridx, 1)) {
784 return EXCP_UDEF;
785 }
786 *value = env->cp15.c14_timer[timeridx].cval;
787 return 0;
788}
789
790static int gt_cval_write(CPUARMState *env, const ARMCPRegInfo *ri,
791 uint64_t value)
792{
793 int timeridx = ri->opc1 & 1;
794
795 env->cp15.c14_timer[timeridx].cval = value;
796 gt_recalc_timer(arm_env_get_cpu(env), timeridx);
797 return 0;
798}
799static int gt_tval_read(CPUARMState *env, const ARMCPRegInfo *ri,
800 uint64_t *value)
801{
802 int timeridx = ri->crm & 1;
803
804 if (arm_current_pl(env) == 0 &&
805 !extract32(env->cp15.c14_cntkctl, 9 - timeridx, 1)) {
806 return EXCP_UDEF;
807 }
808 *value = (uint32_t)(env->cp15.c14_timer[timeridx].cval -
809 gt_get_countervalue(env));
810 return 0;
811}
812
813static int gt_tval_write(CPUARMState *env, const ARMCPRegInfo *ri,
814 uint64_t value)
815{
816 int timeridx = ri->crm & 1;
817
818 env->cp15.c14_timer[timeridx].cval = gt_get_countervalue(env) +
819 + sextract64(value, 0, 32);
820 gt_recalc_timer(arm_env_get_cpu(env), timeridx);
821 return 0;
822}
823
824static int gt_ctl_read(CPUARMState *env, const ARMCPRegInfo *ri,
825 uint64_t *value)
826{
827 int timeridx = ri->crm & 1;
828
829 if (arm_current_pl(env) == 0 &&
830 !extract32(env->cp15.c14_cntkctl, 9 - timeridx, 1)) {
831 return EXCP_UDEF;
832 }
833 *value = env->cp15.c14_timer[timeridx].ctl;
834 return 0;
835}
836
837static int gt_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri,
838 uint64_t value)
839{
840 ARMCPU *cpu = arm_env_get_cpu(env);
841 int timeridx = ri->crm & 1;
842 uint32_t oldval = env->cp15.c14_timer[timeridx].ctl;
843
844 env->cp15.c14_timer[timeridx].ctl = value & 3;
845 if ((oldval ^ value) & 1) {
846 /* Enable toggled */
847 gt_recalc_timer(cpu, timeridx);
848 } else if ((oldval & value) & 2) {
849 /* IMASK toggled: don't need to recalculate,
850 * just set the interrupt line based on ISTATUS
851 */
852 qemu_set_irq(cpu->gt_timer_outputs[timeridx],
853 (oldval & 4) && (value & 2));
854 }
855 return 0;
856}
857
858void arm_gt_ptimer_cb(void *opaque)
859{
860 ARMCPU *cpu = opaque;
861
862 gt_recalc_timer(cpu, GTIMER_PHYS);
863}
864
865void arm_gt_vtimer_cb(void *opaque)
866{
867 ARMCPU *cpu = opaque;
868
869 gt_recalc_timer(cpu, GTIMER_VIRT);
870}
871
872static const ARMCPRegInfo generic_timer_cp_reginfo[] = {
873 /* Note that CNTFRQ is purely reads-as-written for the benefit
874 * of software; writing it doesn't actually change the timer frequency.
875 * Our reset value matches the fixed frequency we implement the timer at.
876 */
877 { .name = "CNTFRQ", .cp = 15, .crn = 14, .crm = 0, .opc1 = 0, .opc2 = 0,
878 .access = PL1_RW | PL0_R,
879 .fieldoffset = offsetof(CPUARMState, cp15.c14_cntfrq),
880 .resetvalue = (1000 * 1000 * 1000) / GTIMER_SCALE,
881 .readfn = gt_cntfrq_read, .raw_readfn = raw_read,
882 },
883 /* overall control: mostly access permissions */
884 { .name = "CNTKCTL", .cp = 15, .crn = 14, .crm = 1, .opc1 = 0, .opc2 = 0,
885 .access = PL1_RW,
886 .fieldoffset = offsetof(CPUARMState, cp15.c14_cntkctl),
887 .resetvalue = 0,
888 },
889 /* per-timer control */
890 { .name = "CNTP_CTL", .cp = 15, .crn = 14, .crm = 2, .opc1 = 0, .opc2 = 1,
891 .type = ARM_CP_IO, .access = PL1_RW | PL0_R,
892 .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].ctl),
893 .resetvalue = 0,
894 .readfn = gt_ctl_read, .writefn = gt_ctl_write,
895 .raw_readfn = raw_read, .raw_writefn = raw_write,
896 },
897 { .name = "CNTV_CTL", .cp = 15, .crn = 14, .crm = 3, .opc1 = 0, .opc2 = 1,
898 .type = ARM_CP_IO, .access = PL1_RW | PL0_R,
899 .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].ctl),
900 .resetvalue = 0,
901 .readfn = gt_ctl_read, .writefn = gt_ctl_write,
902 .raw_readfn = raw_read, .raw_writefn = raw_write,
903 },
904 /* TimerValue views: a 32 bit downcounting view of the underlying state */
905 { .name = "CNTP_TVAL", .cp = 15, .crn = 14, .crm = 2, .opc1 = 0, .opc2 = 0,
906 .type = ARM_CP_NO_MIGRATE | ARM_CP_IO, .access = PL1_RW | PL0_R,
907 .readfn = gt_tval_read, .writefn = gt_tval_write,
908 },
909 { .name = "CNTV_TVAL", .cp = 15, .crn = 14, .crm = 3, .opc1 = 0, .opc2 = 0,
910 .type = ARM_CP_NO_MIGRATE | ARM_CP_IO, .access = PL1_RW | PL0_R,
911 .readfn = gt_tval_read, .writefn = gt_tval_write,
912 },
913 /* The counter itself */
914 { .name = "CNTPCT", .cp = 15, .crm = 14, .opc1 = 0,
915 .access = PL0_R, .type = ARM_CP_64BIT | ARM_CP_NO_MIGRATE | ARM_CP_IO,
916 .readfn = gt_cnt_read, .resetfn = gt_cnt_reset,
917 },
918 { .name = "CNTVCT", .cp = 15, .crm = 14, .opc1 = 1,
919 .access = PL0_R, .type = ARM_CP_64BIT | ARM_CP_NO_MIGRATE | ARM_CP_IO,
920 .readfn = gt_cnt_read, .resetfn = gt_cnt_reset,
921 },
922 /* Comparison value, indicating when the timer goes off */
923 { .name = "CNTP_CVAL", .cp = 15, .crm = 14, .opc1 = 2,
924 .access = PL1_RW | PL0_R,
925 .type = ARM_CP_64BIT | ARM_CP_IO,
926 .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].cval),
927 .resetvalue = 0,
928 .readfn = gt_cval_read, .writefn = gt_cval_write,
929 .raw_readfn = raw_read, .raw_writefn = raw_write,
930 },
931 { .name = "CNTV_CVAL", .cp = 15, .crm = 14, .opc1 = 3,
932 .access = PL1_RW | PL0_R,
933 .type = ARM_CP_64BIT | ARM_CP_IO,
934 .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].cval),
935 .resetvalue = 0,
936 .readfn = gt_cval_read, .writefn = gt_cval_write,
937 .raw_readfn = raw_read, .raw_writefn = raw_write,
938 },
939 REGINFO_SENTINEL
940};
941
942#else
943/* In user-mode none of the generic timer registers are accessible,
bc72ad67 944 * and their implementation depends on QEMU_CLOCK_VIRTUAL and qdev gpio outputs,
55d284af
PM		 945 * so instead just don't register any of them.
946 */
6cc7a3ae 947static const ARMCPRegInfo generic_timer_cp_reginfo[] = {
6cc7a3ae
PM		 948 REGINFO_SENTINEL
949};
950
55d284af
PM		 951#endif
952
4a501606
PM		 953static int par_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
954{
891a2fe7
PM		 955 if (arm_feature(env, ARM_FEATURE_LPAE)) {
956 env->cp15.c7_par = value;
957 } else if (arm_feature(env, ARM_FEATURE_V7)) {
4a501606
PM		 958 env->cp15.c7_par = value & 0xfffff6ff;
959 } else {
960 env->cp15.c7_par = value & 0xfffff1ff;
961 }
962 return 0;
963}
964
965#ifndef CONFIG_USER_ONLY
966/* get_phys_addr() isn't present for user-mode-only targets */
702a9357
PM		 967
968/* Return true if extended addresses are enabled, ie this is an
969 * LPAE implementation and we are using the long-descriptor translation
970 * table format because the TTBCR EAE bit is set.
971 */
972static inline bool extended_addresses_enabled(CPUARMState *env)
973{
974 return arm_feature(env, ARM_FEATURE_LPAE)
975 && (env->cp15.c2_control & (1 << 31));
976}
977
4a501606
PM		 978static int ats_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
979{
a8170e5e 980 hwaddr phys_addr;
4a501606
PM		 981 target_ulong page_size;
982 int prot;
983 int ret, is_user = ri->opc2 & 2;
984 int access_type = ri->opc2 & 1;
985
986 if (ri->opc2 & 4) {
987 /* Other states are only available with TrustZone */
988 return EXCP_UDEF;
989 }
990 ret = get_phys_addr(env, value, access_type, is_user,
991 &phys_addr, &prot, &page_size);
702a9357
PM		 992 if (extended_addresses_enabled(env)) {
993 /* ret is a DFSR/IFSR value for the long descriptor
994 * translation table format, but with WnR always clear.
995 * Convert it to a 64-bit PAR.
996 */
997 uint64_t par64 = (1 << 11); /* LPAE bit always set */
998 if (ret == 0) {
999 par64 |= phys_addr & ~0xfffULL;
1000 /* We don't set the ATTR or SH fields in the PAR. */
4a501606 1001 } else {
702a9357
PM		 1002 par64 |= 1; /* F */
1003 par64 |= (ret & 0x3f) << 1; /* FS */
1004 /* Note that S2WLK and FSTAGE are always zero, because we don't
1005 * implement virtualization and therefore there can't be a stage 2
1006 * fault.
1007 */
4a501606 1008 }
702a9357
PM		 1009 env->cp15.c7_par = par64;
1010 env->cp15.c7_par_hi = par64 >> 32;
4a501606 1011 } else {
702a9357
PM		 1012 /* ret is a DFSR/IFSR value for the short descriptor
1013 * translation table format (with WnR always clear).
1014 * Convert it to a 32-bit PAR.
1015 */
1016 if (ret == 0) {
1017 /* We do not set any attribute bits in the PAR */
1018 if (page_size == (1 << 24)
1019 && arm_feature(env, ARM_FEATURE_V7)) {
1020 env->cp15.c7_par = (phys_addr & 0xff000000) | 1 << 1;
1021 } else {
1022 env->cp15.c7_par = phys_addr & 0xfffff000;
1023 }
1024 } else {
1025 env->cp15.c7_par = ((ret & (10 << 1)) >> 5) |
1026 ((ret & (12 << 1)) >> 6) |
1027 ((ret & 0xf) << 1) | 1;
1028 }
1029 env->cp15.c7_par_hi = 0;
4a501606
PM		 1030 }
1031 return 0;
1032}
1033#endif
1034
1035static const ARMCPRegInfo vapa_cp_reginfo[] = {
1036 { .name = "PAR", .cp = 15, .crn = 7, .crm = 4, .opc1 = 0, .opc2 = 0,
1037 .access = PL1_RW, .resetvalue = 0,
1038 .fieldoffset = offsetof(CPUARMState, cp15.c7_par),
1039 .writefn = par_write },
1040#ifndef CONFIG_USER_ONLY
1041 { .name = "ATS", .cp = 15, .crn = 7, .crm = 8, .opc1 = 0, .opc2 = CP_ANY,
d4e6df63 1042 .access = PL1_W, .writefn = ats_write, .type = ARM_CP_NO_MIGRATE },
4a501606
PM		 1043#endif
1044 REGINFO_SENTINEL
1045};
1046
18032bec
PM		 1047/* Return basic MPU access permission bits. */
1048static uint32_t simple_mpu_ap_bits(uint32_t val)
1049{
1050 uint32_t ret;
1051 uint32_t mask;
1052 int i;
1053 ret = 0;
1054 mask = 3;
1055 for (i = 0; i < 16; i += 2) {
1056 ret |= (val >> i) & mask;
1057 mask <<= 2;
1058 }
1059 return ret;
1060}
1061
1062/* Pad basic MPU access permission bits to extended format. */
1063static uint32_t extended_mpu_ap_bits(uint32_t val)
1064{
1065 uint32_t ret;
1066 uint32_t mask;
1067 int i;
1068 ret = 0;
1069 mask = 3;
1070 for (i = 0; i < 16; i += 2) {
1071 ret |= (val & mask) << i;
1072 mask <<= 2;
1073 }
1074 return ret;
1075}
1076
1077static int pmsav5_data_ap_write(CPUARMState *env, const ARMCPRegInfo *ri,
1078 uint64_t value)
1079{
1080 env->cp15.c5_data = extended_mpu_ap_bits(value);
1081 return 0;
1082}
1083
1084static int pmsav5_data_ap_read(CPUARMState *env, const ARMCPRegInfo *ri,
1085 uint64_t *value)
1086{
1087 *value = simple_mpu_ap_bits(env->cp15.c5_data);
1088 return 0;
1089}
1090
1091static int pmsav5_insn_ap_write(CPUARMState *env, const ARMCPRegInfo *ri,
1092 uint64_t value)
1093{
1094 env->cp15.c5_insn = extended_mpu_ap_bits(value);
1095 return 0;
1096}
1097
1098static int pmsav5_insn_ap_read(CPUARMState *env, const ARMCPRegInfo *ri,
1099 uint64_t *value)
1100{
1101 *value = simple_mpu_ap_bits(env->cp15.c5_insn);
1102 return 0;
1103}
1104
06d76f31
PM		 1105static int arm946_prbs_read(CPUARMState *env, const ARMCPRegInfo *ri,
1106 uint64_t *value)
1107{
599d64f6 1108 if (ri->crm >= 8) {
06d76f31
PM		 1109 return EXCP_UDEF;
1110 }
1111 *value = env->cp15.c6_region[ri->crm];
1112 return 0;
1113}
1114
1115static int arm946_prbs_write(CPUARMState *env, const ARMCPRegInfo *ri,
1116 uint64_t value)
1117{
599d64f6 1118 if (ri->crm >= 8) {
06d76f31
PM		 1119 return EXCP_UDEF;
1120 }
1121 env->cp15.c6_region[ri->crm] = value;
1122 return 0;
1123}
1124
18032bec
PM		 1125static const ARMCPRegInfo pmsav5_cp_reginfo[] = {
1126 { .name = "DATA_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 0,
d4e6df63 1127 .access = PL1_RW, .type = ARM_CP_NO_MIGRATE,
18032bec
PM		 1128 .fieldoffset = offsetof(CPUARMState, cp15.c5_data), .resetvalue = 0,
1129 .readfn = pmsav5_data_ap_read, .writefn = pmsav5_data_ap_write, },
1130 { .name = "INSN_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 1,
d4e6df63 1131 .access = PL1_RW, .type = ARM_CP_NO_MIGRATE,
18032bec
PM		 1132 .fieldoffset = offsetof(CPUARMState, cp15.c5_insn), .resetvalue = 0,
1133 .readfn = pmsav5_insn_ap_read, .writefn = pmsav5_insn_ap_write, },
1134 { .name = "DATA_EXT_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 2,
1135 .access = PL1_RW,
1136 .fieldoffset = offsetof(CPUARMState, cp15.c5_data), .resetvalue = 0, },
1137 { .name = "INSN_EXT_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 3,
1138 .access = PL1_RW,
1139 .fieldoffset = offsetof(CPUARMState, cp15.c5_insn), .resetvalue = 0, },
ecce5c3c
PM		 1140 { .name = "DCACHE_CFG", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 0,
1141 .access = PL1_RW,
1142 .fieldoffset = offsetof(CPUARMState, cp15.c2_data), .resetvalue = 0, },
1143 { .name = "ICACHE_CFG", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 1,
1144 .access = PL1_RW,
1145 .fieldoffset = offsetof(CPUARMState, cp15.c2_insn), .resetvalue = 0, },
06d76f31
PM		 1146 /* Protection region base and size registers */
1147 { .name = "946_PRBS", .cp = 15, .crn = 6, .crm = CP_ANY, .opc1 = 0,
1148 .opc2 = CP_ANY, .access = PL1_RW,
1149 .readfn = arm946_prbs_read, .writefn = arm946_prbs_write, },
18032bec
PM		 1150 REGINFO_SENTINEL
1151};
1152
d4e6df63
PM		 1153static int vmsa_ttbcr_raw_write(CPUARMState *env, const ARMCPRegInfo *ri,
1154 uint64_t value)
ecce5c3c 1155{
2ebcebe2
PM		 1156 int maskshift = extract32(value, 0, 3);
1157
e42c4db3
PM		 1158 if (arm_feature(env, ARM_FEATURE_LPAE)) {
1159 value &= ~((7 << 19) | (3 << 14) | (0xf << 3));
e42c4db3
PM		 1160 } else {
1161 value &= 7;
1162 }
1163 /* Note that we always calculate c2_mask and c2_base_mask, but
1164 * they are only used for short-descriptor tables (ie if EAE is 0);
1165 * for long-descriptor tables the TTBCR fields are used differently
1166 * and the c2_mask and c2_base_mask values are meaningless.
1167 */
ecce5c3c 1168 env->cp15.c2_control = value;
2ebcebe2
PM		 1169 env->cp15.c2_mask = ~(((uint32_t)0xffffffffu) >> maskshift);
1170 env->cp15.c2_base_mask = ~((uint32_t)0x3fffu >> maskshift);
ecce5c3c
PM		 1171 return 0;
1172}
1173
d4e6df63
PM		 1174static int vmsa_ttbcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
1175 uint64_t value)
1176{
1177 if (arm_feature(env, ARM_FEATURE_LPAE)) {
1178 /* With LPAE the TTBCR could result in a change of ASID
1179 * via the TTBCR.A1 bit, so do a TLB flush.
1180 */
1181 tlb_flush(env, 1);
1182 }
1183 return vmsa_ttbcr_raw_write(env, ri, value);
1184}
1185
ecce5c3c
PM		 1186static void vmsa_ttbcr_reset(CPUARMState *env, const ARMCPRegInfo *ri)
1187{
1188 env->cp15.c2_base_mask = 0xffffc000u;
1189 env->cp15.c2_control = 0;
1190 env->cp15.c2_mask = 0;
1191}
1192
18032bec
PM		 1193static const ARMCPRegInfo vmsa_cp_reginfo[] = {
1194 { .name = "DFSR", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 0,
1195 .access = PL1_RW,
1196 .fieldoffset = offsetof(CPUARMState, cp15.c5_data), .resetvalue = 0, },
1197 { .name = "IFSR", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 1,
1198 .access = PL1_RW,
1199 .fieldoffset = offsetof(CPUARMState, cp15.c5_insn), .resetvalue = 0, },
ecce5c3c
PM		 1200 { .name = "TTBR0", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 0,
1201 .access = PL1_RW,
1202 .fieldoffset = offsetof(CPUARMState, cp15.c2_base0), .resetvalue = 0, },
1203 { .name = "TTBR1", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 1,
1204 .access = PL1_RW,
81a60ada 1205 .fieldoffset = offsetof(CPUARMState, cp15.c2_base1), .resetvalue = 0, },
ecce5c3c
PM		 1206 { .name = "TTBCR", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 2,
1207 .access = PL1_RW, .writefn = vmsa_ttbcr_write,
d4e6df63 1208 .resetfn = vmsa_ttbcr_reset, .raw_writefn = vmsa_ttbcr_raw_write,
ecce5c3c 1209 .fieldoffset = offsetof(CPUARMState, cp15.c2_control) },
06d76f31
PM		 1210 { .name = "DFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 0,
1211 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c6_data),
1212 .resetvalue = 0, },
18032bec
PM		 1213 REGINFO_SENTINEL
1214};
1215
1047b9d7
PM		 1216static int omap_ticonfig_write(CPUARMState *env, const ARMCPRegInfo *ri,
1217 uint64_t value)
1218{
1219 env->cp15.c15_ticonfig = value & 0xe7;
1220 /* The OS_TYPE bit in this register changes the reported CPUID! */
1221 env->cp15.c0_cpuid = (value & (1 << 5)) ?
1222 ARM_CPUID_TI915T : ARM_CPUID_TI925T;
1223 return 0;
1224}
1225
1226static int omap_threadid_write(CPUARMState *env, const ARMCPRegInfo *ri,
1227 uint64_t value)
1228{
1229 env->cp15.c15_threadid = value & 0xffff;
1230 return 0;
1231}
1232
1233static int omap_wfi_write(CPUARMState *env, const ARMCPRegInfo *ri,
1234 uint64_t value)
1235{
1236 /* Wait-for-interrupt (deprecated) */
c3affe56 1237 cpu_interrupt(CPU(arm_env_get_cpu(env)), CPU_INTERRUPT_HALT);
1047b9d7
PM		 1238 return 0;
1239}
1240
c4804214
PM		 1241static int omap_cachemaint_write(CPUARMState *env, const ARMCPRegInfo *ri,
1242 uint64_t value)
1243{
1244 /* On OMAP there are registers indicating the max/min index of dcache lines
1245 * containing a dirty line; cache flush operations have to reset these.
1246 */
1247 env->cp15.c15_i_max = 0x000;
1248 env->cp15.c15_i_min = 0xff0;
1249 return 0;
1250}
1251
18032bec
PM		 1252static const ARMCPRegInfo omap_cp_reginfo[] = {
1253 { .name = "DFSR", .cp = 15, .crn = 5, .crm = CP_ANY,
1254 .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_OVERRIDE,
1255 .fieldoffset = offsetof(CPUARMState, cp15.c5_data), .resetvalue = 0, },
1047b9d7
PM		 1256 { .name = "", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0,
1257 .access = PL1_RW, .type = ARM_CP_NOP },
1258 { .name = "TICONFIG", .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0,
1259 .access = PL1_RW,
1260 .fieldoffset = offsetof(CPUARMState, cp15.c15_ticonfig), .resetvalue = 0,
1261 .writefn = omap_ticonfig_write },
1262 { .name = "IMAX", .cp = 15, .crn = 15, .crm = 2, .opc1 = 0, .opc2 = 0,
1263 .access = PL1_RW,
1264 .fieldoffset = offsetof(CPUARMState, cp15.c15_i_max), .resetvalue = 0, },
1265 { .name = "IMIN", .cp = 15, .crn = 15, .crm = 3, .opc1 = 0, .opc2 = 0,
1266 .access = PL1_RW, .resetvalue = 0xff0,
1267 .fieldoffset = offsetof(CPUARMState, cp15.c15_i_min) },
1268 { .name = "THREADID", .cp = 15, .crn = 15, .crm = 4, .opc1 = 0, .opc2 = 0,
1269 .access = PL1_RW,
1270 .fieldoffset = offsetof(CPUARMState, cp15.c15_threadid), .resetvalue = 0,
1271 .writefn = omap_threadid_write },
1272 { .name = "TI925T_STATUS", .cp = 15, .crn = 15,
1273 .crm = 8, .opc1 = 0, .opc2 = 0, .access = PL1_RW,
d4e6df63 1274 .type = ARM_CP_NO_MIGRATE,
1047b9d7
PM		 1275 .readfn = arm_cp_read_zero, .writefn = omap_wfi_write, },
1276 /* TODO: Peripheral port remap register:
1277 * On OMAP2 mcr p15, 0, rn, c15, c2, 4 sets up the interrupt controller
1278 * base address at $rn & ~0xfff and map size of 0x200 << ($rn & 0xfff),
1279 * when MMU is off.
1280 */
c4804214 1281 { .name = "OMAP_CACHEMAINT", .cp = 15, .crn = 7, .crm = CP_ANY,
d4e6df63
PM		 1282 .opc1 = 0, .opc2 = CP_ANY, .access = PL1_W,
1283 .type = ARM_CP_OVERRIDE | ARM_CP_NO_MIGRATE,
c4804214 1284 .writefn = omap_cachemaint_write },
34f90529
PM		 1285 { .name = "C9", .cp = 15, .crn = 9,
1286 .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW,
1287 .type = ARM_CP_CONST | ARM_CP_OVERRIDE, .resetvalue = 0 },
1047b9d7
PM		 1288 REGINFO_SENTINEL
1289};
1290
1291static int xscale_cpar_write(CPUARMState *env, const ARMCPRegInfo *ri,
1292 uint64_t value)
1293{
1294 value &= 0x3fff;
1295 if (env->cp15.c15_cpar != value) {
1296 /* Changes cp0 to cp13 behavior, so needs a TB flush. */
1297 tb_flush(env);
1298 env->cp15.c15_cpar = value;
1299 }
1300 return 0;
1301}
1302
1303static const ARMCPRegInfo xscale_cp_reginfo[] = {
1304 { .name = "XSCALE_CPAR",
1305 .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0, .access = PL1_RW,
1306 .fieldoffset = offsetof(CPUARMState, cp15.c15_cpar), .resetvalue = 0,
1307 .writefn = xscale_cpar_write, },
2771db27
PM		 1308 { .name = "XSCALE_AUXCR",
1309 .cp = 15, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 1, .access = PL1_RW,
1310 .fieldoffset = offsetof(CPUARMState, cp15.c1_xscaleauxcr),
1311 .resetvalue = 0, },
1047b9d7
PM		 1312 REGINFO_SENTINEL
1313};
1314
1315static const ARMCPRegInfo dummy_c15_cp_reginfo[] = {
1316 /* RAZ/WI the whole crn=15 space, when we don't have a more specific
1317 * implementation of this implementation-defined space.
1318 * Ideally this should eventually disappear in favour of actually
1319 * implementing the correct behaviour for all cores.
1320 */
1321 { .name = "C15_IMPDEF", .cp = 15, .crn = 15,
1322 .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY,
d4e6df63
PM		 1323 .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_NO_MIGRATE,
1324 .resetvalue = 0 },
18032bec
PM		 1325 REGINFO_SENTINEL
1326};
1327
c4804214
PM		 1328static const ARMCPRegInfo cache_dirty_status_cp_reginfo[] = {
1329 /* Cache status: RAZ because we have no cache so it's always clean */
1330 { .name = "CDSR", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 6,
d4e6df63
PM		 1331 .access = PL1_R, .type = ARM_CP_CONST | ARM_CP_NO_MIGRATE,
1332 .resetvalue = 0 },
c4804214
PM		 1333 REGINFO_SENTINEL
1334};
1335
1336static const ARMCPRegInfo cache_block_ops_cp_reginfo[] = {
1337 /* We never have a a block transfer operation in progress */
1338 { .name = "BXSR", .cp = 15, .crn = 7, .crm = 12, .opc1 = 0, .opc2 = 4,
d4e6df63
PM		 1339 .access = PL0_R, .type = ARM_CP_CONST | ARM_CP_NO_MIGRATE,
1340 .resetvalue = 0 },
30b05bba
PM		 1341 /* The cache ops themselves: these all NOP for QEMU */
1342 { .name = "IICR", .cp = 15, .crm = 5, .opc1 = 0,
1343 .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
1344 { .name = "IDCR", .cp = 15, .crm = 6, .opc1 = 0,
1345 .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
1346 { .name = "CDCR", .cp = 15, .crm = 12, .opc1 = 0,
1347 .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
1348 { .name = "PIR", .cp = 15, .crm = 12, .opc1 = 1,
1349 .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
1350 { .name = "PDR", .cp = 15, .crm = 12, .opc1 = 2,
1351 .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
1352 { .name = "CIDCR", .cp = 15, .crm = 14, .opc1 = 0,
1353 .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
c4804214
PM		 1354 REGINFO_SENTINEL
1355};
1356
1357static const ARMCPRegInfo cache_test_clean_cp_reginfo[] = {
1358 /* The cache test-and-clean instructions always return (1 << 30)
1359 * to indicate that there are no dirty cache lines.
1360 */
1361 { .name = "TC_DCACHE", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 3,
d4e6df63
PM		 1362 .access = PL0_R, .type = ARM_CP_CONST | ARM_CP_NO_MIGRATE,
1363 .resetvalue = (1 << 30) },
c4804214 1364 { .name = "TCI_DCACHE", .cp = 15, .crn = 7, .crm = 14, .opc1 = 0, .opc2 = 3,
d4e6df63
PM		 1365 .access = PL0_R, .type = ARM_CP_CONST | ARM_CP_NO_MIGRATE,
1366 .resetvalue = (1 << 30) },
c4804214
PM		 1367 REGINFO_SENTINEL
1368};
1369
34f90529
PM		 1370static const ARMCPRegInfo strongarm_cp_reginfo[] = {
1371 /* Ignore ReadBuffer accesses */
1372 { .name = "C9_READBUFFER", .cp = 15, .crn = 9,
1373 .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY,
d4e6df63
PM		 1374 .access = PL1_RW, .resetvalue = 0,
1375 .type = ARM_CP_CONST | ARM_CP_OVERRIDE | ARM_CP_NO_MIGRATE },
34f90529
PM		 1376 REGINFO_SENTINEL
1377};
1378
81bdde9d
PM		 1379static int mpidr_read(CPUARMState *env, const ARMCPRegInfo *ri,
1380 uint64_t *value)
1381{
55e5c285
AF		 1382 CPUState *cs = CPU(arm_env_get_cpu(env));
1383 uint32_t mpidr = cs->cpu_index;
81bdde9d
PM		 1384 /* We don't support setting cluster ID ([8..11])
1385 * so these bits always RAZ.
1386 */
1387 if (arm_feature(env, ARM_FEATURE_V7MP)) {
1388 mpidr |= (1 << 31);
1389 /* Cores which are uniprocessor (non-coherent)
1390 * but still implement the MP extensions set
1391 * bit 30. (For instance, A9UP.) However we do
1392 * not currently model any of those cores.
1393 */
1394 }
1395 *value = mpidr;
1396 return 0;
1397}
1398
1399static const ARMCPRegInfo mpidr_cp_reginfo[] = {
1400 { .name = "MPIDR", .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 5,
d4e6df63 1401 .access = PL1_R, .readfn = mpidr_read, .type = ARM_CP_NO_MIGRATE },
81bdde9d
PM		 1402 REGINFO_SENTINEL
1403};
1404
891a2fe7
PM		 1405static int par64_read(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t *value)
1406{
1407 *value = ((uint64_t)env->cp15.c7_par_hi << 32) | env->cp15.c7_par;
1408 return 0;
1409}
1410
1411static int par64_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
1412{
1413 env->cp15.c7_par_hi = value >> 32;
1414 env->cp15.c7_par = value;
1415 return 0;
1416}
1417
1418static void par64_reset(CPUARMState *env, const ARMCPRegInfo *ri)
1419{
1420 env->cp15.c7_par_hi = 0;
1421 env->cp15.c7_par = 0;
1422}
1423
1424static int ttbr064_read(CPUARMState *env, const ARMCPRegInfo *ri,
1425 uint64_t *value)
1426{
1427 *value = ((uint64_t)env->cp15.c2_base0_hi << 32) | env->cp15.c2_base0;
1428 return 0;
1429}
1430
d4e6df63
PM		 1431static int ttbr064_raw_write(CPUARMState *env, const ARMCPRegInfo *ri,
1432 uint64_t value)
891a2fe7
PM		 1433{
1434 env->cp15.c2_base0_hi = value >> 32;
1435 env->cp15.c2_base0 = value;
d4e6df63
PM		 1436 return 0;
1437}
1438
1439static int ttbr064_write(CPUARMState *env, const ARMCPRegInfo *ri,
1440 uint64_t value)
1441{
891a2fe7
PM		 1442 /* Writes to the 64 bit format TTBRs may change the ASID */
1443 tlb_flush(env, 1);
d4e6df63 1444 return ttbr064_raw_write(env, ri, value);
891a2fe7
PM		 1445}
1446
1447static void ttbr064_reset(CPUARMState *env, const ARMCPRegInfo *ri)
1448{
1449 env->cp15.c2_base0_hi = 0;
1450 env->cp15.c2_base0 = 0;
1451}
1452
1453static int ttbr164_read(CPUARMState *env, const ARMCPRegInfo *ri,
1454 uint64_t *value)
1455{
1456 *value = ((uint64_t)env->cp15.c2_base1_hi << 32) | env->cp15.c2_base1;
1457 return 0;
1458}
1459
1460static int ttbr164_write(CPUARMState *env, const ARMCPRegInfo *ri,
1461 uint64_t value)
1462{
1463 env->cp15.c2_base1_hi = value >> 32;
1464 env->cp15.c2_base1 = value;
1465 return 0;
1466}
1467
1468static void ttbr164_reset(CPUARMState *env, const ARMCPRegInfo *ri)
1469{
1470 env->cp15.c2_base1_hi = 0;
1471 env->cp15.c2_base1 = 0;
1472}
1473
7ac681cf 1474static const ARMCPRegInfo lpae_cp_reginfo[] = {
b90372ad 1475 /* NOP AMAIR0/1: the override is because these clash with the rather
7ac681cf
PM		 1476 * broadly specified TLB_LOCKDOWN entry in the generic cp_reginfo.
1477 */
1478 { .name = "AMAIR0", .cp = 15, .crn = 10, .crm = 3, .opc1 = 0, .opc2 = 0,
1479 .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_OVERRIDE,
1480 .resetvalue = 0 },
1481 { .name = "AMAIR1", .cp = 15, .crn = 10, .crm = 3, .opc1 = 0, .opc2 = 1,
1482 .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_OVERRIDE,
1483 .resetvalue = 0 },
f9fc619a
PM		 1484 /* 64 bit access versions of the (dummy) debug registers */
1485 { .name = "DBGDRAR", .cp = 14, .crm = 1, .opc1 = 0,
1486 .access = PL0_R, .type = ARM_CP_CONST|ARM_CP_64BIT, .resetvalue = 0 },
1487 { .name = "DBGDSAR", .cp = 14, .crm = 2, .opc1 = 0,
1488 .access = PL0_R, .type = ARM_CP_CONST|ARM_CP_64BIT, .resetvalue = 0 },
891a2fe7
PM		 1489 { .name = "PAR", .cp = 15, .crm = 7, .opc1 = 0,
1490 .access = PL1_RW, .type = ARM_CP_64BIT,
1491 .readfn = par64_read, .writefn = par64_write, .resetfn = par64_reset },
1492 { .name = "TTBR0", .cp = 15, .crm = 2, .opc1 = 0,
1493 .access = PL1_RW, .type = ARM_CP_64BIT, .readfn = ttbr064_read,
d4e6df63
PM		 1494 .writefn = ttbr064_write, .raw_writefn = ttbr064_raw_write,
1495 .resetfn = ttbr064_reset },
891a2fe7
PM		 1496 { .name = "TTBR1", .cp = 15, .crm = 2, .opc1 = 1,
1497 .access = PL1_RW, .type = ARM_CP_64BIT, .readfn = ttbr164_read,
1498 .writefn = ttbr164_write, .resetfn = ttbr164_reset },
7ac681cf
PM		 1499 REGINFO_SENTINEL
1500};
1501
2771db27
PM		 1502static int sctlr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
1503{
1504 env->cp15.c1_sys = value;
1505 /* ??? Lots of these bits are not implemented. */
1506 /* This may enable/disable the MMU, so do a TLB flush. */
1507 tlb_flush(env, 1);
1508 return 0;
1509}
1510
2ceb98c0
PM		 1511void register_cp_regs_for_features(ARMCPU *cpu)
1512{
1513 /* Register all the coprocessor registers based on feature bits */
1514 CPUARMState *env = &cpu->env;
1515 if (arm_feature(env, ARM_FEATURE_M)) {
1516 /* M profile has no coprocessor registers */
1517 return;
1518 }
1519
e9aa6c21 1520 define_arm_cp_regs(cpu, cp_reginfo);
7d57f408 1521 if (arm_feature(env, ARM_FEATURE_V6)) {
8515a092
PM		 1522 /* The ID registers all have impdef reset values */
1523 ARMCPRegInfo v6_idregs[] = {
1524 { .name = "ID_PFR0", .cp = 15, .crn = 0, .crm = 1,
1525 .opc1 = 0, .opc2 = 0, .access = PL1_R, .type = ARM_CP_CONST,
1526 .resetvalue = cpu->id_pfr0 },
1527 { .name = "ID_PFR1", .cp = 15, .crn = 0, .crm = 1,
1528 .opc1 = 0, .opc2 = 1, .access = PL1_R, .type = ARM_CP_CONST,
1529 .resetvalue = cpu->id_pfr1 },
1530 { .name = "ID_DFR0", .cp = 15, .crn = 0, .crm = 1,
1531 .opc1 = 0, .opc2 = 2, .access = PL1_R, .type = ARM_CP_CONST,
1532 .resetvalue = cpu->id_dfr0 },
1533 { .name = "ID_AFR0", .cp = 15, .crn = 0, .crm = 1,
1534 .opc1 = 0, .opc2 = 3, .access = PL1_R, .type = ARM_CP_CONST,
1535 .resetvalue = cpu->id_afr0 },
1536 { .name = "ID_MMFR0", .cp = 15, .crn = 0, .crm = 1,
1537 .opc1 = 0, .opc2 = 4, .access = PL1_R, .type = ARM_CP_CONST,
1538 .resetvalue = cpu->id_mmfr0 },
1539 { .name = "ID_MMFR1", .cp = 15, .crn = 0, .crm = 1,
1540 .opc1 = 0, .opc2 = 5, .access = PL1_R, .type = ARM_CP_CONST,
1541 .resetvalue = cpu->id_mmfr1 },
1542 { .name = "ID_MMFR2", .cp = 15, .crn = 0, .crm = 1,
1543 .opc1 = 0, .opc2 = 6, .access = PL1_R, .type = ARM_CP_CONST,
1544 .resetvalue = cpu->id_mmfr2 },
1545 { .name = "ID_MMFR3", .cp = 15, .crn = 0, .crm = 1,
1546 .opc1 = 0, .opc2 = 7, .access = PL1_R, .type = ARM_CP_CONST,
1547 .resetvalue = cpu->id_mmfr3 },
1548 { .name = "ID_ISAR0", .cp = 15, .crn = 0, .crm = 2,
1549 .opc1 = 0, .opc2 = 0, .access = PL1_R, .type = ARM_CP_CONST,
1550 .resetvalue = cpu->id_isar0 },
1551 { .name = "ID_ISAR1", .cp = 15, .crn = 0, .crm = 2,
1552 .opc1 = 0, .opc2 = 1, .access = PL1_R, .type = ARM_CP_CONST,
1553 .resetvalue = cpu->id_isar1 },
1554 { .name = "ID_ISAR2", .cp = 15, .crn = 0, .crm = 2,
1555 .opc1 = 0, .opc2 = 2, .access = PL1_R, .type = ARM_CP_CONST,
1556 .resetvalue = cpu->id_isar2 },
1557 { .name = "ID_ISAR3", .cp = 15, .crn = 0, .crm = 2,
1558 .opc1 = 0, .opc2 = 3, .access = PL1_R, .type = ARM_CP_CONST,
1559 .resetvalue = cpu->id_isar3 },
1560 { .name = "ID_ISAR4", .cp = 15, .crn = 0, .crm = 2,
1561 .opc1 = 0, .opc2 = 4, .access = PL1_R, .type = ARM_CP_CONST,
1562 .resetvalue = cpu->id_isar4 },
1563 { .name = "ID_ISAR5", .cp = 15, .crn = 0, .crm = 2,
1564 .opc1 = 0, .opc2 = 5, .access = PL1_R, .type = ARM_CP_CONST,
1565 .resetvalue = cpu->id_isar5 },
1566 /* 6..7 are as yet unallocated and must RAZ */
1567 { .name = "ID_ISAR6", .cp = 15, .crn = 0, .crm = 2,
1568 .opc1 = 0, .opc2 = 6, .access = PL1_R, .type = ARM_CP_CONST,
1569 .resetvalue = 0 },
1570 { .name = "ID_ISAR7", .cp = 15, .crn = 0, .crm = 2,
1571 .opc1 = 0, .opc2 = 7, .access = PL1_R, .type = ARM_CP_CONST,
1572 .resetvalue = 0 },
1573 REGINFO_SENTINEL
1574 };
1575 define_arm_cp_regs(cpu, v6_idregs);
7d57f408
PM		 1576 define_arm_cp_regs(cpu, v6_cp_reginfo);
1577 } else {
1578 define_arm_cp_regs(cpu, not_v6_cp_reginfo);
1579 }
4d31c596
PM		 1580 if (arm_feature(env, ARM_FEATURE_V6K)) {
1581 define_arm_cp_regs(cpu, v6k_cp_reginfo);
1582 }
e9aa6c21 1583 if (arm_feature(env, ARM_FEATURE_V7)) {
200ac0ef
PM		 1584 /* v7 performance monitor control register: same implementor
1585 * field as main ID register, and we implement no event counters.
1586 */
1587 ARMCPRegInfo pmcr = {
1588 .name = "PMCR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 0,
1589 .access = PL0_RW, .resetvalue = cpu->midr & 0xff000000,
1590 .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcr),
d4e6df63
PM		 1591 .readfn = pmreg_read, .writefn = pmcr_write,
1592 .raw_readfn = raw_read, .raw_writefn = raw_write,
200ac0ef 1593 };
776d4e5c
PM		 1594 ARMCPRegInfo clidr = {
1595 .name = "CLIDR", .cp = 15, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 1,
1596 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = cpu->clidr
1597 };
200ac0ef 1598 define_one_arm_cp_reg(cpu, &pmcr);
776d4e5c 1599 define_one_arm_cp_reg(cpu, &clidr);
e9aa6c21 1600 define_arm_cp_regs(cpu, v7_cp_reginfo);
7d57f408
PM		 1601 } else {
1602 define_arm_cp_regs(cpu, not_v7_cp_reginfo);
e9aa6c21 1603 }
18032bec
PM		 1604 if (arm_feature(env, ARM_FEATURE_MPU)) {
1605 /* These are the MPU registers prior to PMSAv6. Any new
1606 * PMSA core later than the ARM946 will require that we
1607 * implement the PMSAv6 or PMSAv7 registers, which are
1608 * completely different.
1609 */
1610 assert(!arm_feature(env, ARM_FEATURE_V6));
1611 define_arm_cp_regs(cpu, pmsav5_cp_reginfo);
1612 } else {
1613 define_arm_cp_regs(cpu, vmsa_cp_reginfo);
1614 }
c326b979
PM		 1615 if (arm_feature(env, ARM_FEATURE_THUMB2EE)) {
1616 define_arm_cp_regs(cpu, t2ee_cp_reginfo);
1617 }
6cc7a3ae
PM		 1618 if (arm_feature(env, ARM_FEATURE_GENERIC_TIMER)) {
1619 define_arm_cp_regs(cpu, generic_timer_cp_reginfo);
1620 }
4a501606
PM		 1621 if (arm_feature(env, ARM_FEATURE_VAPA)) {
1622 define_arm_cp_regs(cpu, vapa_cp_reginfo);
1623 }
c4804214
PM		 1624 if (arm_feature(env, ARM_FEATURE_CACHE_TEST_CLEAN)) {
1625 define_arm_cp_regs(cpu, cache_test_clean_cp_reginfo);
1626 }
1627 if (arm_feature(env, ARM_FEATURE_CACHE_DIRTY_REG)) {
1628 define_arm_cp_regs(cpu, cache_dirty_status_cp_reginfo);
1629 }
1630 if (arm_feature(env, ARM_FEATURE_CACHE_BLOCK_OPS)) {
1631 define_arm_cp_regs(cpu, cache_block_ops_cp_reginfo);
1632 }
18032bec
PM		 1633 if (arm_feature(env, ARM_FEATURE_OMAPCP)) {
1634 define_arm_cp_regs(cpu, omap_cp_reginfo);
1635 }
34f90529
PM		 1636 if (arm_feature(env, ARM_FEATURE_STRONGARM)) {
1637 define_arm_cp_regs(cpu, strongarm_cp_reginfo);
1638 }
1047b9d7
PM		 1639 if (arm_feature(env, ARM_FEATURE_XSCALE)) {
1640 define_arm_cp_regs(cpu, xscale_cp_reginfo);
1641 }
1642 if (arm_feature(env, ARM_FEATURE_DUMMY_C15_REGS)) {
1643 define_arm_cp_regs(cpu, dummy_c15_cp_reginfo);
1644 }
7ac681cf
PM		 1645 if (arm_feature(env, ARM_FEATURE_LPAE)) {
1646 define_arm_cp_regs(cpu, lpae_cp_reginfo);
1647 }
7884849c
PM		 1648 /* Slightly awkwardly, the OMAP and StrongARM cores need all of
1649 * cp15 crn=0 to be writes-ignored, whereas for other cores they should
1650 * be read-only (ie write causes UNDEF exception).
1651 */
1652 {
1653 ARMCPRegInfo id_cp_reginfo[] = {
1654 /* Note that the MIDR isn't a simple constant register because
1655 * of the TI925 behaviour where writes to another register can
1656 * cause the MIDR value to change.
97ce8d61
PC		 1657 *
1658 * Unimplemented registers in the c15 0 0 0 space default to
1659 * MIDR. Define MIDR first as this entire space, then CTR, TCMTR
1660 * and friends override accordingly.
7884849c
PM		 1661 */
1662 { .name = "MIDR",
97ce8d61 1663 .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = CP_ANY,
7884849c 1664 .access = PL1_R, .resetvalue = cpu->midr,
d4e6df63 1665 .writefn = arm_cp_write_ignore, .raw_writefn = raw_write,
97ce8d61
PC		 1666 .fieldoffset = offsetof(CPUARMState, cp15.c0_cpuid),
1667 .type = ARM_CP_OVERRIDE },
7884849c
PM		 1668 { .name = "CTR",
1669 .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 1,
1670 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = cpu->ctr },
1671 { .name = "TCMTR",
1672 .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 2,
1673 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
1674 { .name = "TLBTR",
1675 .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 3,
1676 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
1677 /* crn = 0 op1 = 0 crm = 3..7 : currently unassigned; we RAZ. */
1678 { .name = "DUMMY",
1679 .cp = 15, .crn = 0, .crm = 3, .opc1 = 0, .opc2 = CP_ANY,
1680 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
1681 { .name = "DUMMY",
1682 .cp = 15, .crn = 0, .crm = 4, .opc1 = 0, .opc2 = CP_ANY,
1683 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
1684 { .name = "DUMMY",
1685 .cp = 15, .crn = 0, .crm = 5, .opc1 = 0, .opc2 = CP_ANY,
1686 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
1687 { .name = "DUMMY",
1688 .cp = 15, .crn = 0, .crm = 6, .opc1 = 0, .opc2 = CP_ANY,
1689 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
1690 { .name = "DUMMY",
1691 .cp = 15, .crn = 0, .crm = 7, .opc1 = 0, .opc2 = CP_ANY,
1692 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
1693 REGINFO_SENTINEL
1694 };
1695 ARMCPRegInfo crn0_wi_reginfo = {
1696 .name = "CRN0_WI", .cp = 15, .crn = 0, .crm = CP_ANY,
1697 .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_W,
1698 .type = ARM_CP_NOP | ARM_CP_OVERRIDE
1699 };
1700 if (arm_feature(env, ARM_FEATURE_OMAPCP) ||
1701 arm_feature(env, ARM_FEATURE_STRONGARM)) {
1702 ARMCPRegInfo *r;
1703 /* Register the blanket "writes ignored" value first to cover the
a703eda1
PC		 1704 * whole space. Then update the specific ID registers to allow write
1705 * access, so that they ignore writes rather than causing them to
1706 * UNDEF.
7884849c
PM		 1707 */
1708 define_one_arm_cp_reg(cpu, &crn0_wi_reginfo);
1709 for (r = id_cp_reginfo; r->type != ARM_CP_SENTINEL; r++) {
1710 r->access = PL1_RW;
7884849c 1711 }
7884849c 1712 }
a703eda1 1713 define_arm_cp_regs(cpu, id_cp_reginfo);
7884849c
PM		 1714 }
1715
97ce8d61
PC		 1716 if (arm_feature(env, ARM_FEATURE_MPIDR)) {
1717 define_arm_cp_regs(cpu, mpidr_cp_reginfo);
1718 }
1719
2771db27
PM		 1720 if (arm_feature(env, ARM_FEATURE_AUXCR)) {
1721 ARMCPRegInfo auxcr = {
1722 .name = "AUXCR", .cp = 15, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 1,
1723 .access = PL1_RW, .type = ARM_CP_CONST,
1724 .resetvalue = cpu->reset_auxcr
1725 };
1726 define_one_arm_cp_reg(cpu, &auxcr);
1727 }
1728
1729 /* Generic registers whose values depend on the implementation */
1730 {
1731 ARMCPRegInfo sctlr = {
1732 .name = "SCTLR", .cp = 15, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 0,
1733 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c1_sys),
d4e6df63
PM		 1734 .writefn = sctlr_write, .resetvalue = cpu->reset_sctlr,
1735 .raw_writefn = raw_write,
2771db27
PM		 1736 };
1737 if (arm_feature(env, ARM_FEATURE_XSCALE)) {
1738 /* Normally we would always end the TB on an SCTLR write, but Linux
1739 * arch/arm/mach-pxa/sleep.S expects two instructions following
1740 * an MMU enable to execute from cache. Imitate this behaviour.
1741 */
1742 sctlr.type |= ARM_CP_SUPPRESS_TB_END;
1743 }
1744 define_one_arm_cp_reg(cpu, &sctlr);
1745 }
2ceb98c0
PM		 1746}
1747
778c3a06 1748ARMCPU *cpu_arm_init(const char *cpu_model)
40f137e1 1749{
dec9c2d4 1750 ARMCPU *cpu;
40f137e1 1751 CPUARMState *env;
5900d6b2 1752 ObjectClass *oc;
40f137e1 1753
5900d6b2
AF		 1754 oc = cpu_class_by_name(TYPE_ARM_CPU, cpu_model);
1755 if (!oc) {
aaed909a 1756 return NULL;
777dc784 1757 }
5900d6b2 1758 cpu = ARM_CPU(object_new(object_class_get_name(oc)));
dec9c2d4 1759 env = &cpu->env;
777dc784 1760 env->cpu_model_str = cpu_model;
14969266
AF		 1761
1762 /* TODO this should be set centrally, once possible */
1763 object_property_set_bool(OBJECT(cpu), true, "realized", NULL);
777dc784 1764
14969266
AF		 1765 return cpu;
1766}
1767
1768void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu)
1769{
22169d41 1770 CPUState *cs = CPU(cpu);
14969266
AF		 1771 CPUARMState *env = &cpu->env;
1772
56aebc89 1773 if (arm_feature(env, ARM_FEATURE_NEON)) {
22169d41 1774 gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg,
56aebc89
PB		 1775 51, "arm-neon.xml", 0);
1776 } else if (arm_feature(env, ARM_FEATURE_VFP3)) {
22169d41 1777 gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg,
56aebc89
PB		 1778 35, "arm-vfp3.xml", 0);
1779 } else if (arm_feature(env, ARM_FEATURE_VFP)) {
22169d41 1780 gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg,
56aebc89
PB		 1781 19, "arm-vfp.xml", 0);
1782 }
40f137e1
PB		 1783}
1784
777dc784
PM		 1785/* Sort alphabetically by type name, except for "any". */
1786static gint arm_cpu_list_compare(gconstpointer a, gconstpointer b)
5adb4839 1787{
777dc784
PM		 1788 ObjectClass *class_a = (ObjectClass *)a;
1789 ObjectClass *class_b = (ObjectClass *)b;
1790 const char *name_a, *name_b;
5adb4839 1791
777dc784
PM		 1792 name_a = object_class_get_name(class_a);
1793 name_b = object_class_get_name(class_b);
51492fd1 1794 if (strcmp(name_a, "any-" TYPE_ARM_CPU) == 0) {
777dc784 1795 return 1;
51492fd1 1796 } else if (strcmp(name_b, "any-" TYPE_ARM_CPU) == 0) {
777dc784
PM		 1797 return -1;
1798 } else {
1799 return strcmp(name_a, name_b);
5adb4839
PB		 1800 }
1801}
1802
777dc784 1803static void arm_cpu_list_entry(gpointer data, gpointer user_data)
40f137e1 1804{
777dc784 1805 ObjectClass *oc = data;
92a31361 1806 CPUListState *s = user_data;
51492fd1
AF		 1807 const char *typename;
1808 char *name;
3371d272 1809
51492fd1
AF		 1810 typename = object_class_get_name(oc);
1811 name = g_strndup(typename, strlen(typename) - strlen("-" TYPE_ARM_CPU));
777dc784 1812 (*s->cpu_fprintf)(s->file, " %s\n",
51492fd1
AF		 1813 name);
1814 g_free(name);
777dc784
PM		 1815}
1816
1817void arm_cpu_list(FILE *f, fprintf_function cpu_fprintf)
1818{
92a31361 1819 CPUListState s = {
777dc784
PM		 1820 .file = f,
1821 .cpu_fprintf = cpu_fprintf,
1822 };
1823 GSList *list;
1824
1825 list = object_class_get_list(TYPE_ARM_CPU, false);
1826 list = g_slist_sort(list, arm_cpu_list_compare);
1827 (*cpu_fprintf)(f, "Available CPUs:\n");
1828 g_slist_foreach(list, arm_cpu_list_entry, &s);
1829 g_slist_free(list);
40f137e1
PB		 1830}
1831
4b6a83fb
PM		 1832void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu,
1833 const ARMCPRegInfo *r, void *opaque)
1834{
1835 /* Define implementations of coprocessor registers.
1836 * We store these in a hashtable because typically
1837 * there are less than 150 registers in a space which
1838 * is 16*16*16*8*8 = 262144 in size.
1839 * Wildcarding is supported for the crm, opc1 and opc2 fields.
1840 * If a register is defined twice then the second definition is
1841 * used, so this can be used to define some generic registers and
1842 * then override them with implementation specific variations.
1843 * At least one of the original and the second definition should
1844 * include ARM_CP_OVERRIDE in its type bits -- this is just a guard
1845 * against accidental use.
1846 */
1847 int crm, opc1, opc2;
1848 int crmmin = (r->crm == CP_ANY) ? 0 : r->crm;
1849 int crmmax = (r->crm == CP_ANY) ? 15 : r->crm;
1850 int opc1min = (r->opc1 == CP_ANY) ? 0 : r->opc1;
1851 int opc1max = (r->opc1 == CP_ANY) ? 7 : r->opc1;
1852 int opc2min = (r->opc2 == CP_ANY) ? 0 : r->opc2;
1853 int opc2max = (r->opc2 == CP_ANY) ? 7 : r->opc2;
1854 /* 64 bit registers have only CRm and Opc1 fields */
1855 assert(!((r->type & ARM_CP_64BIT) && (r->opc2 || r->crn)));
1856 /* Check that the register definition has enough info to handle
1857 * reads and writes if they are permitted.
1858 */
1859 if (!(r->type & (ARM_CP_SPECIAL|ARM_CP_CONST))) {
1860 if (r->access & PL3_R) {
1861 assert(r->fieldoffset || r->readfn);
1862 }
1863 if (r->access & PL3_W) {
1864 assert(r->fieldoffset || r->writefn);
1865 }
1866 }
1867 /* Bad type field probably means missing sentinel at end of reg list */
1868 assert(cptype_valid(r->type));
1869 for (crm = crmmin; crm <= crmmax; crm++) {
1870 for (opc1 = opc1min; opc1 <= opc1max; opc1++) {
1871 for (opc2 = opc2min; opc2 <= opc2max; opc2++) {
1872 uint32_t *key = g_new(uint32_t, 1);
1873 ARMCPRegInfo *r2 = g_memdup(r, sizeof(ARMCPRegInfo));
1874 int is64 = (r->type & ARM_CP_64BIT) ? 1 : 0;
1875 *key = ENCODE_CP_REG(r->cp, is64, r->crn, crm, opc1, opc2);
204a9c43
PC		 1876 if (opaque) {
1877 r2->opaque = opaque;
1878 }
4b6a83fb
PM		 1879 /* Make sure reginfo passed to helpers for wildcarded regs
1880 * has the correct crm/opc1/opc2 for this reg, not CP_ANY:
1881 */
1882 r2->crm = crm;
1883 r2->opc1 = opc1;
1884 r2->opc2 = opc2;
7023ec7e
PM		 1885 /* By convention, for wildcarded registers only the first
1886 * entry is used for migration; the others are marked as
1887 * NO_MIGRATE so we don't try to transfer the register
1888 * multiple times. Special registers (ie NOP/WFI) are
1889 * never migratable.
1890 */
1891 if ((r->type & ARM_CP_SPECIAL) ||
1892 ((r->crm == CP_ANY) && crm != 0) ||
1893 ((r->opc1 == CP_ANY) && opc1 != 0) ||
1894 ((r->opc2 == CP_ANY) && opc2 != 0)) {
1895 r2->type |= ARM_CP_NO_MIGRATE;
1896 }
1897
4b6a83fb
PM		 1898 /* Overriding of an existing definition must be explicitly
1899 * requested.
1900 */
1901 if (!(r->type & ARM_CP_OVERRIDE)) {
1902 ARMCPRegInfo *oldreg;
1903 oldreg = g_hash_table_lookup(cpu->cp_regs, key);
1904 if (oldreg && !(oldreg->type & ARM_CP_OVERRIDE)) {
1905 fprintf(stderr, "Register redefined: cp=%d %d bit "
1906 "crn=%d crm=%d opc1=%d opc2=%d, "
1907 "was %s, now %s\n", r2->cp, 32 + 32 * is64,
1908 r2->crn, r2->crm, r2->opc1, r2->opc2,
1909 oldreg->name, r2->name);
dfc6f865 1910 g_assert_not_reached();
4b6a83fb
PM		 1911 }
1912 }
1913 g_hash_table_insert(cpu->cp_regs, key, r2);
1914 }
1915 }
1916 }
1917}
1918
1919void define_arm_cp_regs_with_opaque(ARMCPU *cpu,
1920 const ARMCPRegInfo *regs, void *opaque)
1921{
1922 /* Define a whole list of registers */
1923 const ARMCPRegInfo *r;
1924 for (r = regs; r->type != ARM_CP_SENTINEL; r++) {
1925 define_one_arm_cp_reg_with_opaque(cpu, r, opaque);
1926 }
1927}
1928
1929const ARMCPRegInfo *get_arm_cp_reginfo(ARMCPU *cpu, uint32_t encoded_cp)
1930{
1931 return g_hash_table_lookup(cpu->cp_regs, &encoded_cp);
1932}
1933
1934int arm_cp_write_ignore(CPUARMState *env, const ARMCPRegInfo *ri,
1935 uint64_t value)
1936{
1937 /* Helper coprocessor write function for write-ignore registers */
1938 return 0;
1939}
1940
1941int arm_cp_read_zero(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t *value)
1942{
1943 /* Helper coprocessor write function for read-as-zero registers */
1944 *value = 0;
1945 return 0;
1946}
1947
0ecb72a5 1948static int bad_mode_switch(CPUARMState *env, int mode)
37064a8b
PM		 1949{
1950 /* Return true if it is not valid for us to switch to
1951 * this CPU mode (ie all the UNPREDICTABLE cases in
1952 * the ARM ARM CPSRWriteByInstr pseudocode).
1953 */
1954 switch (mode) {
1955 case ARM_CPU_MODE_USR:
1956 case ARM_CPU_MODE_SYS:
1957 case ARM_CPU_MODE_SVC:
1958 case ARM_CPU_MODE_ABT:
1959 case ARM_CPU_MODE_UND:
1960 case ARM_CPU_MODE_IRQ:
1961 case ARM_CPU_MODE_FIQ:
1962 return 0;
1963 default:
1964 return 1;
1965 }
1966}
1967
2f4a40e5
AZ		 1968uint32_t cpsr_read(CPUARMState *env)
1969{
1970 int ZF;
6fbe23d5
PB		 1971 ZF = (env->ZF == 0);
1972 return env->uncached_cpsr | (env->NF & 0x80000000) | (ZF << 30) |
2f4a40e5
AZ		 1973 (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27)
1974 | (env->thumb << 5) | ((env->condexec_bits & 3) << 25)
1975 | ((env->condexec_bits & 0xfc) << 8)
1976 | (env->GE << 16);
1977}
1978
1979void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask)
1980{
2f4a40e5 1981 if (mask & CPSR_NZCV) {
6fbe23d5
PB		 1982 env->ZF = (~val) & CPSR_Z;
1983 env->NF = val;
2f4a40e5
AZ		 1984 env->CF = (val >> 29) & 1;
1985 env->VF = (val << 3) & 0x80000000;
1986 }
1987 if (mask & CPSR_Q)
1988 env->QF = ((val & CPSR_Q) != 0);
1989 if (mask & CPSR_T)
1990 env->thumb = ((val & CPSR_T) != 0);
1991 if (mask & CPSR_IT_0_1) {
1992 env->condexec_bits &= ~3;
1993 env->condexec_bits |= (val >> 25) & 3;
1994 }
1995 if (mask & CPSR_IT_2_7) {
1996 env->condexec_bits &= 3;
1997 env->condexec_bits |= (val >> 8) & 0xfc;
1998 }
1999 if (mask & CPSR_GE) {
2000 env->GE = (val >> 16) & 0xf;
2001 }
2002
2003 if ((env->uncached_cpsr ^ val) & mask & CPSR_M) {
37064a8b
PM		 2004 if (bad_mode_switch(env, val & CPSR_M)) {
2005 /* Attempt to switch to an invalid mode: this is UNPREDICTABLE.
2006 * We choose to ignore the attempt and leave the CPSR M field
2007 * untouched.
2008 */
2009 mask &= ~CPSR_M;
2010 } else {
2011 switch_mode(env, val & CPSR_M);
2012 }
2f4a40e5
AZ		 2013 }
2014 mask &= ~CACHED_CPSR_BITS;
2015 env->uncached_cpsr = (env->uncached_cpsr & ~mask) | (val & mask);
2016}
2017
b26eefb6
PB		 2018/* Sign/zero extend */
2019uint32_t HELPER(sxtb16)(uint32_t x)
2020{
2021 uint32_t res;
2022 res = (uint16_t)(int8_t)x;
2023 res |= (uint32_t)(int8_t)(x >> 16) << 16;
2024 return res;
2025}
2026
2027uint32_t HELPER(uxtb16)(uint32_t x)
2028{
2029 uint32_t res;
2030 res = (uint16_t)(uint8_t)x;
2031 res |= (uint32_t)(uint8_t)(x >> 16) << 16;
2032 return res;
2033}
2034
f51bbbfe
PB		 2035uint32_t HELPER(clz)(uint32_t x)
2036{
7bbcb0af 2037 return clz32(x);
f51bbbfe
PB		 2038}
2039
3670669c
PB		 2040int32_t HELPER(sdiv)(int32_t num, int32_t den)
2041{
2042 if (den == 0)
2043 return 0;
686eeb93
AJ		 2044 if (num == INT_MIN && den == -1)
2045 return INT_MIN;
3670669c
PB		 2046 return num / den;
2047}
2048
2049uint32_t HELPER(udiv)(uint32_t num, uint32_t den)
2050{
2051 if (den == 0)
2052 return 0;
2053 return num / den;
2054}
2055
2056uint32_t HELPER(rbit)(uint32_t x)
2057{
2058 x = ((x & 0xff000000) >> 24)
2059 | ((x & 0x00ff0000) >> 8)
2060 | ((x & 0x0000ff00) << 8)
2061 | ((x & 0x000000ff) << 24);
2062 x = ((x & 0xf0f0f0f0) >> 4)
2063 | ((x & 0x0f0f0f0f) << 4);
2064 x = ((x & 0x88888888) >> 3)
2065 | ((x & 0x44444444) >> 1)
2066 | ((x & 0x22222222) << 1)
2067 | ((x & 0x11111111) << 3);
2068 return x;
2069}
2070
5fafdf24 2071#if defined(CONFIG_USER_ONLY)
b5ff1b31 2072
97a8ea5a 2073void arm_cpu_do_interrupt(CPUState *cs)
b5ff1b31 2074{
97a8ea5a
AF		 2075 ARMCPU *cpu = ARM_CPU(cs);
2076 CPUARMState *env = &cpu->env;
2077
b5ff1b31
FB		 2078 env->exception_index = -1;
2079}
2080
0ecb72a5 2081int cpu_arm_handle_mmu_fault (CPUARMState *env, target_ulong address, int rw,
97b348e7 2082 int mmu_idx)
b5ff1b31
FB		 2083{
2084 if (rw == 2) {
2085 env->exception_index = EXCP_PREFETCH_ABORT;
2086 env->cp15.c6_insn = address;
2087 } else {
2088 env->exception_index = EXCP_DATA_ABORT;
2089 env->cp15.c6_data = address;
2090 }
2091 return 1;
2092}
2093
9ee6e8bb 2094/* These should probably raise undefined insn exceptions. */
0ecb72a5 2095void HELPER(v7m_msr)(CPUARMState *env, uint32_t reg, uint32_t val)
9ee6e8bb
PB		 2096{
2097 cpu_abort(env, "v7m_mrs %d\n", reg);
2098}
2099
0ecb72a5 2100uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg)
9ee6e8bb
PB		 2101{
2102 cpu_abort(env, "v7m_mrs %d\n", reg);
2103 return 0;
2104}
2105
0ecb72a5 2106void switch_mode(CPUARMState *env, int mode)
b5ff1b31
FB		 2107{
2108 if (mode != ARM_CPU_MODE_USR)
2109 cpu_abort(env, "Tried to switch out of user mode\n");
2110}
2111
0ecb72a5 2112void HELPER(set_r13_banked)(CPUARMState *env, uint32_t mode, uint32_t val)
9ee6e8bb
PB		 2113{
2114 cpu_abort(env, "banked r13 write\n");
2115}
2116
0ecb72a5 2117uint32_t HELPER(get_r13_banked)(CPUARMState *env, uint32_t mode)
9ee6e8bb
PB		 2118{
2119 cpu_abort(env, "banked r13 read\n");
2120 return 0;
2121}
2122
b5ff1b31
FB		 2123#else
2124
2125/* Map CPU modes onto saved register banks. */
494b00c7 2126int bank_number(int mode)
b5ff1b31
FB		 2127{
2128 switch (mode) {
2129 case ARM_CPU_MODE_USR:
2130 case ARM_CPU_MODE_SYS:
2131 return 0;
2132 case ARM_CPU_MODE_SVC:
2133 return 1;
2134 case ARM_CPU_MODE_ABT:
2135 return 2;
2136 case ARM_CPU_MODE_UND:
2137 return 3;
2138 case ARM_CPU_MODE_IRQ:
2139 return 4;
2140 case ARM_CPU_MODE_FIQ:
2141 return 5;
2142 }
f5206413 2143 hw_error("bank number requested for bad CPSR mode value 0x%x\n", mode);
b5ff1b31
FB		 2144}
2145
0ecb72a5 2146void switch_mode(CPUARMState *env, int mode)
b5ff1b31
FB		 2147{
2148 int old_mode;
2149 int i;
2150
2151 old_mode = env->uncached_cpsr & CPSR_M;
2152 if (mode == old_mode)
2153 return;
2154
2155 if (old_mode == ARM_CPU_MODE_FIQ) {
2156 memcpy (env->fiq_regs, env->regs + 8, 5 * sizeof(uint32_t));
8637c67f 2157 memcpy (env->regs + 8, env->usr_regs, 5 * sizeof(uint32_t));
b5ff1b31
FB		 2158 } else if (mode == ARM_CPU_MODE_FIQ) {
2159 memcpy (env->usr_regs, env->regs + 8, 5 * sizeof(uint32_t));
8637c67f 2160 memcpy (env->regs + 8, env->fiq_regs, 5 * sizeof(uint32_t));
b5ff1b31
FB		 2161 }
2162
f5206413 2163 i = bank_number(old_mode);
b5ff1b31
FB		 2164 env->banked_r13[i] = env->regs[13];
2165 env->banked_r14[i] = env->regs[14];
2166 env->banked_spsr[i] = env->spsr;
2167
f5206413 2168 i = bank_number(mode);
b5ff1b31
FB		 2169 env->regs[13] = env->banked_r13[i];
2170 env->regs[14] = env->banked_r14[i];
2171 env->spsr = env->banked_spsr[i];
2172}
2173
9ee6e8bb
PB		 2174static void v7m_push(CPUARMState *env, uint32_t val)
2175{
2176 env->regs[13] -= 4;
2177 stl_phys(env->regs[13], val);
2178}
2179
2180static uint32_t v7m_pop(CPUARMState *env)
2181{
2182 uint32_t val;
2183 val = ldl_phys(env->regs[13]);
2184 env->regs[13] += 4;
2185 return val;
2186}
2187
2188/* Switch to V7M main or process stack pointer. */
2189static void switch_v7m_sp(CPUARMState *env, int process)
2190{
2191 uint32_t tmp;
2192 if (env->v7m.current_sp != process) {
2193 tmp = env->v7m.other_sp;
2194 env->v7m.other_sp = env->regs[13];
2195 env->regs[13] = tmp;
2196 env->v7m.current_sp = process;
2197 }
2198}
2199
2200static void do_v7m_exception_exit(CPUARMState *env)
2201{
2202 uint32_t type;
2203 uint32_t xpsr;
2204
2205 type = env->regs[15];
2206 if (env->v7m.exception != 0)
983fe826 2207 armv7m_nvic_complete_irq(env->nvic, env->v7m.exception);
9ee6e8bb
PB		 2208
2209 /* Switch to the target stack. */
2210 switch_v7m_sp(env, (type & 4) != 0);
2211 /* Pop registers. */
2212 env->regs[0] = v7m_pop(env);
2213 env->regs[1] = v7m_pop(env);
2214 env->regs[2] = v7m_pop(env);
2215 env->regs[3] = v7m_pop(env);
2216 env->regs[12] = v7m_pop(env);
2217 env->regs[14] = v7m_pop(env);
2218 env->regs[15] = v7m_pop(env);
2219 xpsr = v7m_pop(env);
2220 xpsr_write(env, xpsr, 0xfffffdff);
2221 /* Undo stack alignment. */
2222 if (xpsr & 0x200)
2223 env->regs[13] |= 4;
2224 /* ??? The exception return type specifies Thread/Handler mode. However
2225 this is also implied by the xPSR value. Not sure what to do
2226 if there is a mismatch. */
2227 /* ??? Likewise for mismatches between the CONTROL register and the stack
2228 pointer. */
2229}
2230
3f1beaca
PM		 2231/* Exception names for debug logging; note that not all of these
2232 * precisely correspond to architectural exceptions.
2233 */
2234static const char * const excnames[] = {
2235 [EXCP_UDEF] = "Undefined Instruction",
2236 [EXCP_SWI] = "SVC",
2237 [EXCP_PREFETCH_ABORT] = "Prefetch Abort",
2238 [EXCP_DATA_ABORT] = "Data Abort",
2239 [EXCP_IRQ] = "IRQ",
2240 [EXCP_FIQ] = "FIQ",
2241 [EXCP_BKPT] = "Breakpoint",
2242 [EXCP_EXCEPTION_EXIT] = "QEMU v7M exception exit",
2243 [EXCP_KERNEL_TRAP] = "QEMU intercept of kernel commpage",
2244 [EXCP_STREX] = "QEMU intercept of STREX",
2245};
2246
2247static inline void arm_log_exception(int idx)
2248{
2249 if (qemu_loglevel_mask(CPU_LOG_INT)) {
2250 const char *exc = NULL;
2251
2252 if (idx >= 0 && idx < ARRAY_SIZE(excnames)) {
2253 exc = excnames[idx];
2254 }
2255 if (!exc) {
2256 exc = "unknown";
2257 }
2258 qemu_log_mask(CPU_LOG_INT, "Taking exception %d [%s]\n", idx, exc);
2259 }
2260}
2261
e6f010cc 2262void arm_v7m_cpu_do_interrupt(CPUState *cs)
9ee6e8bb 2263{
e6f010cc
AF		 2264 ARMCPU *cpu = ARM_CPU(cs);
2265 CPUARMState *env = &cpu->env;
9ee6e8bb
PB		 2266 uint32_t xpsr = xpsr_read(env);
2267 uint32_t lr;
2268 uint32_t addr;
2269
3f1beaca
PM		 2270 arm_log_exception(env->exception_index);
2271
9ee6e8bb
PB		 2272 lr = 0xfffffff1;
2273 if (env->v7m.current_sp)
2274 lr |= 4;
2275 if (env->v7m.exception == 0)
2276 lr |= 8;
2277
2278 /* For exceptions we just mark as pending on the NVIC, and let that
2279 handle it. */
2280 /* TODO: Need to escalate if the current priority is higher than the
2281 one we're raising. */
2282 switch (env->exception_index) {
2283 case EXCP_UDEF:
983fe826 2284 armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE);
9ee6e8bb
PB		 2285 return;
2286 case EXCP_SWI:
314e2296 2287 /* The PC already points to the next instruction. */
983fe826 2288 armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_SVC);
9ee6e8bb
PB		 2289 return;
2290 case EXCP_PREFETCH_ABORT:
2291 case EXCP_DATA_ABORT:
983fe826 2292 armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_MEM);
9ee6e8bb
PB		 2293 return;
2294 case EXCP_BKPT:
2ad207d4
PB		 2295 if (semihosting_enabled) {
2296 int nr;
d31dd73e 2297 nr = arm_lduw_code(env, env->regs[15], env->bswap_code) & 0xff;
2ad207d4
PB		 2298 if (nr == 0xab) {
2299 env->regs[15] += 2;
2300 env->regs[0] = do_arm_semihosting(env);
3f1beaca 2301 qemu_log_mask(CPU_LOG_INT, "...handled as semihosting call\n");
2ad207d4
PB		 2302 return;
2303 }
2304 }
983fe826 2305 armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_DEBUG);
9ee6e8bb
PB		 2306 return;
2307 case EXCP_IRQ:
983fe826 2308 env->v7m.exception = armv7m_nvic_acknowledge_irq(env->nvic);
9ee6e8bb
PB		 2309 break;
2310 case EXCP_EXCEPTION_EXIT:
2311 do_v7m_exception_exit(env);
2312 return;
2313 default:
2314 cpu_abort(env, "Unhandled exception 0x%x\n", env->exception_index);
2315 return; /* Never happens. Keep compiler happy. */
2316 }
2317
2318 /* Align stack pointer. */
2319 /* ??? Should only do this if Configuration Control Register
2320 STACKALIGN bit is set. */
2321 if (env->regs[13] & 4) {
ab19b0ec 2322 env->regs[13] -= 4;
9ee6e8bb
PB		 2323 xpsr |= 0x200;
2324 }
6c95676b 2325 /* Switch to the handler mode. */
9ee6e8bb
PB		 2326 v7m_push(env, xpsr);
2327 v7m_push(env, env->regs[15]);
2328 v7m_push(env, env->regs[14]);
2329 v7m_push(env, env->regs[12]);
2330 v7m_push(env, env->regs[3]);
2331 v7m_push(env, env->regs[2]);
2332 v7m_push(env, env->regs[1]);
2333 v7m_push(env, env->regs[0]);
2334 switch_v7m_sp(env, 0);
c98d174c
PM		 2335 /* Clear IT bits */
2336 env->condexec_bits = 0;
9ee6e8bb
PB		 2337 env->regs[14] = lr;
2338 addr = ldl_phys(env->v7m.vecbase + env->v7m.exception * 4);
2339 env->regs[15] = addr & 0xfffffffe;
2340 env->thumb = addr & 1;
2341}
2342
b5ff1b31 2343/* Handle a CPU exception. */
97a8ea5a 2344void arm_cpu_do_interrupt(CPUState *cs)
b5ff1b31 2345{
97a8ea5a
AF		 2346 ARMCPU *cpu = ARM_CPU(cs);
2347 CPUARMState *env = &cpu->env;
b5ff1b31
FB		 2348 uint32_t addr;
2349 uint32_t mask;
2350 int new_mode;
2351 uint32_t offset;
2352
e6f010cc
AF		 2353 assert(!IS_M(env));
2354
3f1beaca
PM		 2355 arm_log_exception(env->exception_index);
2356
b5ff1b31
FB		 2357 /* TODO: Vectored interrupt controller. */
2358 switch (env->exception_index) {
2359 case EXCP_UDEF:
2360 new_mode = ARM_CPU_MODE_UND;
2361 addr = 0x04;
2362 mask = CPSR_I;
2363 if (env->thumb)
2364 offset = 2;
2365 else
2366 offset = 4;
2367 break;
2368 case EXCP_SWI:
8e71621f
PB		 2369 if (semihosting_enabled) {
2370 /* Check for semihosting interrupt. */
2371 if (env->thumb) {
d31dd73e
BS		 2372 mask = arm_lduw_code(env, env->regs[15] - 2, env->bswap_code)
2373 & 0xff;
8e71621f 2374 } else {
d31dd73e 2375 mask = arm_ldl_code(env, env->regs[15] - 4, env->bswap_code)
d8fd2954 2376 & 0xffffff;
8e71621f
PB		 2377 }
2378 /* Only intercept calls from privileged modes, to provide some
2379 semblance of security. */
2380 if (((mask == 0x123456 && !env->thumb)
2381 || (mask == 0xab && env->thumb))
2382 && (env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR) {
2383 env->regs[0] = do_arm_semihosting(env);
3f1beaca 2384 qemu_log_mask(CPU_LOG_INT, "...handled as semihosting call\n");
8e71621f
PB		 2385 return;
2386 }
2387 }
b5ff1b31
FB		 2388 new_mode = ARM_CPU_MODE_SVC;
2389 addr = 0x08;
2390 mask = CPSR_I;
601d70b9 2391 /* The PC already points to the next instruction. */
b5ff1b31
FB		 2392 offset = 0;
2393 break;
06c949e6 2394 case EXCP_BKPT:
9ee6e8bb 2395 /* See if this is a semihosting syscall. */
2ad207d4 2396 if (env->thumb && semihosting_enabled) {
d31dd73e 2397 mask = arm_lduw_code(env, env->regs[15], env->bswap_code) & 0xff;
9ee6e8bb
PB		 2398 if (mask == 0xab
2399 && (env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR) {
2400 env->regs[15] += 2;
2401 env->regs[0] = do_arm_semihosting(env);
3f1beaca 2402 qemu_log_mask(CPU_LOG_INT, "...handled as semihosting call\n");
9ee6e8bb
PB		 2403 return;
2404 }
2405 }
81c05daf 2406 env->cp15.c5_insn = 2;
9ee6e8bb
PB		 2407 /* Fall through to prefetch abort. */
2408 case EXCP_PREFETCH_ABORT:
3f1beaca
PM		 2409 qemu_log_mask(CPU_LOG_INT, "...with IFSR 0x%x IFAR 0x%x\n",
2410 env->cp15.c5_insn, env->cp15.c6_insn);
b5ff1b31
FB		 2411 new_mode = ARM_CPU_MODE_ABT;
2412 addr = 0x0c;
2413 mask = CPSR_A | CPSR_I;
2414 offset = 4;
2415 break;
2416 case EXCP_DATA_ABORT:
3f1beaca
PM		 2417 qemu_log_mask(CPU_LOG_INT, "...with DFSR 0x%x DFAR 0x%x\n",
2418 env->cp15.c5_data, env->cp15.c6_data);
b5ff1b31
FB		 2419 new_mode = ARM_CPU_MODE_ABT;
2420 addr = 0x10;
2421 mask = CPSR_A | CPSR_I;
2422 offset = 8;
2423 break;
2424 case EXCP_IRQ:
2425 new_mode = ARM_CPU_MODE_IRQ;
2426 addr = 0x18;
2427 /* Disable IRQ and imprecise data aborts. */
2428 mask = CPSR_A | CPSR_I;
2429 offset = 4;
2430 break;
2431 case EXCP_FIQ:
2432 new_mode = ARM_CPU_MODE_FIQ;
2433 addr = 0x1c;
2434 /* Disable FIQ, IRQ and imprecise data aborts. */
2435 mask = CPSR_A | CPSR_I | CPSR_F;
2436 offset = 4;
2437 break;
2438 default:
2439 cpu_abort(env, "Unhandled exception 0x%x\n", env->exception_index);
2440 return; /* Never happens. Keep compiler happy. */
2441 }
2442 /* High vectors. */
2443 if (env->cp15.c1_sys & (1 << 13)) {
2444 addr += 0xffff0000;
2445 }
2446 switch_mode (env, new_mode);
2447 env->spsr = cpsr_read(env);
9ee6e8bb
PB		 2448 /* Clear IT bits. */
2449 env->condexec_bits = 0;
30a8cac1 2450 /* Switch to the new mode, and to the correct instruction set. */
6d7e6326 2451 env->uncached_cpsr = (env->uncached_cpsr & ~CPSR_M) | new_mode;
b5ff1b31 2452 env->uncached_cpsr |= mask;
be5e7a76
DES		 2453 /* this is a lie, as the was no c1_sys on V4T/V5, but who cares
2454 * and we should just guard the thumb mode on V4 */
2455 if (arm_feature(env, ARM_FEATURE_V4T)) {
2456 env->thumb = (env->cp15.c1_sys & (1 << 30)) != 0;
2457 }
b5ff1b31
FB		 2458 env->regs[14] = env->regs[15] + offset;
2459 env->regs[15] = addr;
259186a7 2460 cs->interrupt_request |= CPU_INTERRUPT_EXITTB;
b5ff1b31
FB		 2461}
2462
2463/* Check section/page access permissions.
2464 Returns the page protection flags, or zero if the access is not
2465 permitted. */
0ecb72a5 2466static inline int check_ap(CPUARMState *env, int ap, int domain_prot,
dd4ebc2e 2467 int access_type, int is_user)
b5ff1b31 2468{
9ee6e8bb
PB		 2469 int prot_ro;
2470
dd4ebc2e 2471 if (domain_prot == 3) {
b5ff1b31 2472 return PAGE_READ | PAGE_WRITE;
dd4ebc2e 2473 }
b5ff1b31 2474
9ee6e8bb
PB		 2475 if (access_type == 1)
2476 prot_ro = 0;
2477 else
2478 prot_ro = PAGE_READ;
2479
b5ff1b31
FB		 2480 switch (ap) {
2481 case 0:
78600320 2482 if (access_type == 1)
b5ff1b31
FB		 2483 return 0;
2484 switch ((env->cp15.c1_sys >> 8) & 3) {
2485 case 1:
2486 return is_user ? 0 : PAGE_READ;
2487 case 2:
2488 return PAGE_READ;
2489 default:
2490 return 0;
2491 }
2492 case 1:
2493 return is_user ? 0 : PAGE_READ | PAGE_WRITE;
2494 case 2:
2495 if (is_user)
9ee6e8bb 2496 return prot_ro;
b5ff1b31
FB		 2497 else
2498 return PAGE_READ | PAGE_WRITE;
2499 case 3:
2500 return PAGE_READ | PAGE_WRITE;
d4934d18 2501 case 4: /* Reserved. */
9ee6e8bb
PB		 2502 return 0;
2503 case 5:
2504 return is_user ? 0 : prot_ro;
2505 case 6:
2506 return prot_ro;
d4934d18 2507 case 7:
0ab06d83 2508 if (!arm_feature (env, ARM_FEATURE_V6K))
d4934d18
PB		 2509 return 0;
2510 return prot_ro;
b5ff1b31
FB		 2511 default:
2512 abort();
2513 }
2514}
2515
0ecb72a5 2516static uint32_t get_level1_table_address(CPUARMState *env, uint32_t address)
b2fa1797
PB		 2517{
2518 uint32_t table;
2519
2520 if (address & env->cp15.c2_mask)
2521 table = env->cp15.c2_base1 & 0xffffc000;
2522 else
2523 table = env->cp15.c2_base0 & env->cp15.c2_base_mask;
2524
2525 table |= (address >> 18) & 0x3ffc;
2526 return table;
2527}
2528
0ecb72a5 2529static int get_phys_addr_v5(CPUARMState *env, uint32_t address, int access_type,
a8170e5e 2530 int is_user, hwaddr *phys_ptr,
77a71dd1 2531 int *prot, target_ulong *page_size)
b5ff1b31
FB		 2532{
2533 int code;
2534 uint32_t table;
2535 uint32_t desc;
2536 int type;
2537 int ap;
2538 int domain;
dd4ebc2e 2539 int domain_prot;
a8170e5e 2540 hwaddr phys_addr;
b5ff1b31 2541
9ee6e8bb
PB		 2542 /* Pagetable walk. */
2543 /* Lookup l1 descriptor. */
b2fa1797 2544 table = get_level1_table_address(env, address);
9ee6e8bb
PB		 2545 desc = ldl_phys(table);
2546 type = (desc & 3);
dd4ebc2e
JCD		 2547 domain = (desc >> 5) & 0x0f;
2548 domain_prot = (env->cp15.c3 >> (domain * 2)) & 3;
9ee6e8bb 2549 if (type == 0) {
601d70b9 2550 /* Section translation fault. */
9ee6e8bb
PB		 2551 code = 5;
2552 goto do_fault;
2553 }
dd4ebc2e 2554 if (domain_prot == 0 || domain_prot == 2) {
9ee6e8bb
PB		 2555 if (type == 2)
2556 code = 9; /* Section domain fault. */
2557 else
2558 code = 11; /* Page domain fault. */
2559 goto do_fault;
2560 }
2561 if (type == 2) {
2562 /* 1Mb section. */
2563 phys_addr = (desc & 0xfff00000) | (address & 0x000fffff);
2564 ap = (desc >> 10) & 3;
2565 code = 13;
d4c430a8 2566 *page_size = 1024 * 1024;
9ee6e8bb
PB		 2567 } else {
2568 /* Lookup l2 entry. */
2569 if (type == 1) {
2570 /* Coarse pagetable. */
2571 table = (desc & 0xfffffc00) | ((address >> 10) & 0x3fc);
2572 } else {
2573 /* Fine pagetable. */
2574 table = (desc & 0xfffff000) | ((address >> 8) & 0xffc);
2575 }
2576 desc = ldl_phys(table);
2577 switch (desc & 3) {
2578 case 0: /* Page translation fault. */
2579 code = 7;
2580 goto do_fault;
2581 case 1: /* 64k page. */
2582 phys_addr = (desc & 0xffff0000) | (address & 0xffff);
2583 ap = (desc >> (4 + ((address >> 13) & 6))) & 3;
d4c430a8 2584 *page_size = 0x10000;
ce819861 2585 break;
9ee6e8bb
PB		 2586 case 2: /* 4k page. */
2587 phys_addr = (desc & 0xfffff000) | (address & 0xfff);
2588 ap = (desc >> (4 + ((address >> 13) & 6))) & 3;
d4c430a8 2589 *page_size = 0x1000;
ce819861 2590 break;
9ee6e8bb
PB		 2591 case 3: /* 1k page. */
2592 if (type == 1) {
2593 if (arm_feature(env, ARM_FEATURE_XSCALE)) {
2594 phys_addr = (desc & 0xfffff000) | (address & 0xfff);
2595 } else {
2596 /* Page translation fault. */
2597 code = 7;
2598 goto do_fault;
2599 }
2600 } else {
2601 phys_addr = (desc & 0xfffffc00) | (address & 0x3ff);
2602 }
2603 ap = (desc >> 4) & 3;
d4c430a8 2604 *page_size = 0x400;
ce819861
PB		 2605 break;
2606 default:
9ee6e8bb
PB		 2607 /* Never happens, but compiler isn't smart enough to tell. */
2608 abort();
ce819861 2609 }
9ee6e8bb
PB		 2610 code = 15;
2611 }
dd4ebc2e 2612 *prot = check_ap(env, ap, domain_prot, access_type, is_user);
9ee6e8bb
PB		 2613 if (!*prot) {
2614 /* Access permission fault. */
2615 goto do_fault;
2616 }
3ad493fc 2617 *prot |= PAGE_EXEC;
9ee6e8bb
PB		 2618 *phys_ptr = phys_addr;
2619 return 0;
2620do_fault:
2621 return code | (domain << 4);
2622}
2623
0ecb72a5 2624static int get_phys_addr_v6(CPUARMState *env, uint32_t address, int access_type,
a8170e5e 2625 int is_user, hwaddr *phys_ptr,
77a71dd1 2626 int *prot, target_ulong *page_size)
9ee6e8bb
PB		 2627{
2628 int code;
2629 uint32_t table;
2630 uint32_t desc;
2631 uint32_t xn;
de9b05b8 2632 uint32_t pxn = 0;
9ee6e8bb
PB		 2633 int type;
2634 int ap;
de9b05b8 2635 int domain = 0;
dd4ebc2e 2636 int domain_prot;
a8170e5e 2637 hwaddr phys_addr;
9ee6e8bb
PB		 2638
2639 /* Pagetable walk. */
2640 /* Lookup l1 descriptor. */
b2fa1797 2641 table = get_level1_table_address(env, address);
9ee6e8bb
PB		 2642 desc = ldl_phys(table);
2643 type = (desc & 3);
de9b05b8
PM		 2644 if (type == 0 || (type == 3 && !arm_feature(env, ARM_FEATURE_PXN))) {
2645 /* Section translation fault, or attempt to use the encoding
2646 * which is Reserved on implementations without PXN.
2647 */
9ee6e8bb 2648 code = 5;
9ee6e8bb 2649 goto do_fault;
de9b05b8
PM		 2650 }
2651 if ((type == 1) || !(desc & (1 << 18))) {
2652 /* Page or Section. */
dd4ebc2e 2653 domain = (desc >> 5) & 0x0f;
9ee6e8bb 2654 }
dd4ebc2e
JCD		 2655 domain_prot = (env->cp15.c3 >> (domain * 2)) & 3;
2656 if (domain_prot == 0 || domain_prot == 2) {
de9b05b8 2657 if (type != 1) {
9ee6e8bb 2658 code = 9; /* Section domain fault. */
de9b05b8 2659 } else {
9ee6e8bb 2660 code = 11; /* Page domain fault. */
de9b05b8 2661 }
9ee6e8bb
PB		 2662 goto do_fault;
2663 }
de9b05b8 2664 if (type != 1) {
9ee6e8bb
PB		 2665 if (desc & (1 << 18)) {
2666 /* Supersection. */
2667 phys_addr = (desc & 0xff000000) | (address & 0x00ffffff);
d4c430a8 2668 *page_size = 0x1000000;
b5ff1b31 2669 } else {
9ee6e8bb
PB		 2670 /* Section. */
2671 phys_addr = (desc & 0xfff00000) | (address & 0x000fffff);
d4c430a8 2672 *page_size = 0x100000;
b5ff1b31 2673 }
9ee6e8bb
PB		 2674 ap = ((desc >> 10) & 3) | ((desc >> 13) & 4);
2675 xn = desc & (1 << 4);
de9b05b8 2676 pxn = desc & 1;
9ee6e8bb
PB		 2677 code = 13;
2678 } else {
de9b05b8
PM		 2679 if (arm_feature(env, ARM_FEATURE_PXN)) {
2680 pxn = (desc >> 2) & 1;
2681 }
9ee6e8bb
PB		 2682 /* Lookup l2 entry. */
2683 table = (desc & 0xfffffc00) | ((address >> 10) & 0x3fc);
2684 desc = ldl_phys(table);
2685 ap = ((desc >> 4) & 3) | ((desc >> 7) & 4);
2686 switch (desc & 3) {
2687 case 0: /* Page translation fault. */
2688 code = 7;
b5ff1b31 2689 goto do_fault;
9ee6e8bb
PB		 2690 case 1: /* 64k page. */
2691 phys_addr = (desc & 0xffff0000) | (address & 0xffff);
2692 xn = desc & (1 << 15);
d4c430a8 2693 *page_size = 0x10000;
9ee6e8bb
PB		 2694 break;
2695 case 2: case 3: /* 4k page. */
2696 phys_addr = (desc & 0xfffff000) | (address & 0xfff);
2697 xn = desc & 1;
d4c430a8 2698 *page_size = 0x1000;
9ee6e8bb
PB		 2699 break;
2700 default:
2701 /* Never happens, but compiler isn't smart enough to tell. */
2702 abort();
b5ff1b31 2703 }
9ee6e8bb
PB		 2704 code = 15;
2705 }
dd4ebc2e 2706 if (domain_prot == 3) {
c0034328
JR		 2707 *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
2708 } else {
de9b05b8
PM		 2709 if (pxn && !is_user) {
2710 xn = 1;
2711 }
c0034328
JR		 2712 if (xn && access_type == 2)
2713 goto do_fault;
9ee6e8bb 2714
c0034328
JR		 2715 /* The simplified model uses AP[0] as an access control bit. */
2716 if ((env->cp15.c1_sys & (1 << 29)) && (ap & 1) == 0) {
2717 /* Access flag fault. */
2718 code = (code == 15) ? 6 : 3;
2719 goto do_fault;
2720 }
dd4ebc2e 2721 *prot = check_ap(env, ap, domain_prot, access_type, is_user);
c0034328
JR		 2722 if (!*prot) {
2723 /* Access permission fault. */
2724 goto do_fault;
2725 }
2726 if (!xn) {
2727 *prot |= PAGE_EXEC;
2728 }
3ad493fc 2729 }
9ee6e8bb 2730 *phys_ptr = phys_addr;
b5ff1b31
FB		 2731 return 0;
2732do_fault:
2733 return code | (domain << 4);
2734}
2735
3dde962f
PM		 2736/* Fault type for long-descriptor MMU fault reporting; this corresponds
2737 * to bits [5..2] in the STATUS field in long-format DFSR/IFSR.
2738 */
2739typedef enum {
2740 translation_fault = 1,
2741 access_fault = 2,
2742 permission_fault = 3,
2743} MMUFaultType;
2744
2745static int get_phys_addr_lpae(CPUARMState *env, uint32_t address,
2746 int access_type, int is_user,
a8170e5e 2747 hwaddr *phys_ptr, int *prot,
3dde962f
PM		 2748 target_ulong *page_size_ptr)
2749{
2750 /* Read an LPAE long-descriptor translation table. */
2751 MMUFaultType fault_type = translation_fault;
2752 uint32_t level = 1;
2753 uint32_t epd;
2754 uint32_t tsz;
2755 uint64_t ttbr;
2756 int ttbr_select;
2757 int n;
a8170e5e 2758 hwaddr descaddr;
3dde962f
PM		 2759 uint32_t tableattrs;
2760 target_ulong page_size;
2761 uint32_t attrs;
2762
2763 /* Determine whether this address is in the region controlled by
2764 * TTBR0 or TTBR1 (or if it is in neither region and should fault).
2765 * This is a Non-secure PL0/1 stage 1 translation, so controlled by
2766 * TTBCR/TTBR0/TTBR1 in accordance with ARM ARM DDI0406C table B-32:
2767 */
2768 uint32_t t0sz = extract32(env->cp15.c2_control, 0, 3);
2769 uint32_t t1sz = extract32(env->cp15.c2_control, 16, 3);
2770 if (t0sz && !extract32(address, 32 - t0sz, t0sz)) {
2771 /* there is a ttbr0 region and we are in it (high bits all zero) */
2772 ttbr_select = 0;
2773 } else if (t1sz && !extract32(~address, 32 - t1sz, t1sz)) {
2774 /* there is a ttbr1 region and we are in it (high bits all one) */
2775 ttbr_select = 1;
2776 } else if (!t0sz) {
2777 /* ttbr0 region is "everything not in the ttbr1 region" */
2778 ttbr_select = 0;
2779 } else if (!t1sz) {
2780 /* ttbr1 region is "everything not in the ttbr0 region" */
2781 ttbr_select = 1;
2782 } else {
2783 /* in the gap between the two regions, this is a Translation fault */
2784 fault_type = translation_fault;
2785 goto do_fault;
2786 }
2787
2788 /* Note that QEMU ignores shareability and cacheability attributes,
2789 * so we don't need to do anything with the SH, ORGN, IRGN fields
2790 * in the TTBCR. Similarly, TTBCR:A1 selects whether we get the
2791 * ASID from TTBR0 or TTBR1, but QEMU's TLB doesn't currently
2792 * implement any ASID-like capability so we can ignore it (instead
2793 * we will always flush the TLB any time the ASID is changed).
2794 */
2795 if (ttbr_select == 0) {
2796 ttbr = ((uint64_t)env->cp15.c2_base0_hi << 32) | env->cp15.c2_base0;
2797 epd = extract32(env->cp15.c2_control, 7, 1);
2798 tsz = t0sz;
2799 } else {
2800 ttbr = ((uint64_t)env->cp15.c2_base1_hi << 32) | env->cp15.c2_base1;
2801 epd = extract32(env->cp15.c2_control, 23, 1);
2802 tsz = t1sz;
2803 }
2804
2805 if (epd) {
2806 /* Translation table walk disabled => Translation fault on TLB miss */
2807 goto do_fault;
2808 }
2809
2810 /* If the region is small enough we will skip straight to a 2nd level
2811 * lookup. This affects the number of bits of the address used in
2812 * combination with the TTBR to find the first descriptor. ('n' here
2813 * matches the usage in the ARM ARM sB3.6.6, where bits [39..n] are
2814 * from the TTBR, [n-1..3] from the vaddr, and [2..0] always zero).
2815 */
2816 if (tsz > 1) {
2817 level = 2;
2818 n = 14 - tsz;
2819 } else {
2820 n = 5 - tsz;
2821 }
2822
2823 /* Clear the vaddr bits which aren't part of the within-region address,
2824 * so that we don't have to special case things when calculating the
2825 * first descriptor address.
2826 */
2827 address &= (0xffffffffU >> tsz);
2828
2829 /* Now we can extract the actual base address from the TTBR */
2830 descaddr = extract64(ttbr, 0, 40);
2831 descaddr &= ~((1ULL << n) - 1);
2832
2833 tableattrs = 0;
2834 for (;;) {
2835 uint64_t descriptor;
2836
2837 descaddr |= ((address >> (9 * (4 - level))) & 0xff8);
2838 descriptor = ldq_phys(descaddr);
2839 if (!(descriptor & 1) ||
2840 (!(descriptor & 2) && (level == 3))) {
2841 /* Invalid, or the Reserved level 3 encoding */
2842 goto do_fault;
2843 }
2844 descaddr = descriptor & 0xfffffff000ULL;
2845
2846 if ((descriptor & 2) && (level < 3)) {
2847 /* Table entry. The top five bits are attributes which may
2848 * propagate down through lower levels of the table (and
2849 * which are all arranged so that 0 means "no effect", so
2850 * we can gather them up by ORing in the bits at each level).
2851 */
2852 tableattrs |= extract64(descriptor, 59, 5);
2853 level++;
2854 continue;
2855 }
2856 /* Block entry at level 1 or 2, or page entry at level 3.
2857 * These are basically the same thing, although the number
2858 * of bits we pull in from the vaddr varies.
2859 */
2860 page_size = (1 << (39 - (9 * level)));
2861 descaddr |= (address & (page_size - 1));
2862 /* Extract attributes from the descriptor and merge with table attrs */
2863 attrs = extract64(descriptor, 2, 10)
2864 | (extract64(descriptor, 52, 12) << 10);
2865 attrs |= extract32(tableattrs, 0, 2) << 11; /* XN, PXN */
2866 attrs |= extract32(tableattrs, 3, 1) << 5; /* APTable[1] => AP[2] */
2867 /* The sense of AP[1] vs APTable[0] is reversed, as APTable[0] == 1
2868 * means "force PL1 access only", which means forcing AP[1] to 0.
2869 */
2870 if (extract32(tableattrs, 2, 1)) {
2871 attrs &= ~(1 << 4);
2872 }
2873 /* Since we're always in the Non-secure state, NSTable is ignored. */
2874 break;
2875 }
2876 /* Here descaddr is the final physical address, and attributes
2877 * are all in attrs.
2878 */
2879 fault_type = access_fault;
2880 if ((attrs & (1 << 8)) == 0) {
2881 /* Access flag */
2882 goto do_fault;
2883 }
2884 fault_type = permission_fault;
2885 if (is_user && !(attrs & (1 << 4))) {
2886 /* Unprivileged access not enabled */
2887 goto do_fault;
2888 }
2889 *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
2890 if (attrs & (1 << 12) || (!is_user && (attrs & (1 << 11)))) {
2891 /* XN or PXN */
2892 if (access_type == 2) {
2893 goto do_fault;
2894 }
2895 *prot &= ~PAGE_EXEC;
2896 }
2897 if (attrs & (1 << 5)) {
2898 /* Write access forbidden */
2899 if (access_type == 1) {
2900 goto do_fault;
2901 }
2902 *prot &= ~PAGE_WRITE;
2903 }
2904
2905 *phys_ptr = descaddr;
2906 *page_size_ptr = page_size;
2907 return 0;
2908
2909do_fault:
2910 /* Long-descriptor format IFSR/DFSR value */
2911 return (1 << 9) | (fault_type << 2) | level;
2912}
2913
77a71dd1
PM		 2914static int get_phys_addr_mpu(CPUARMState *env, uint32_t address,
2915 int access_type, int is_user,
a8170e5e 2916 hwaddr *phys_ptr, int *prot)
9ee6e8bb
PB		 2917{
2918 int n;
2919 uint32_t mask;
2920 uint32_t base;
2921
2922 *phys_ptr = address;
2923 for (n = 7; n >= 0; n--) {
2924 base = env->cp15.c6_region[n];
2925 if ((base & 1) == 0)
2926 continue;
2927 mask = 1 << ((base >> 1) & 0x1f);
2928 /* Keep this shift separate from the above to avoid an
2929 (undefined) << 32. */
2930 mask = (mask << 1) - 1;
2931 if (((base ^ address) & ~mask) == 0)
2932 break;
2933 }
2934 if (n < 0)
2935 return 2;
2936
2937 if (access_type == 2) {
2938 mask = env->cp15.c5_insn;
2939 } else {
2940 mask = env->cp15.c5_data;
2941 }
2942 mask = (mask >> (n * 4)) & 0xf;
2943 switch (mask) {
2944 case 0:
2945 return 1;
2946 case 1:
2947 if (is_user)
2948 return 1;
2949 *prot = PAGE_READ | PAGE_WRITE;
2950 break;
2951 case 2:
2952 *prot = PAGE_READ;
2953 if (!is_user)
2954 *prot |= PAGE_WRITE;
2955 break;
2956 case 3:
2957 *prot = PAGE_READ | PAGE_WRITE;
2958 break;
2959 case 5:
2960 if (is_user)
2961 return 1;
2962 *prot = PAGE_READ;
2963 break;
2964 case 6:
2965 *prot = PAGE_READ;
2966 break;
2967 default:
2968 /* Bad permission. */
2969 return 1;
2970 }
3ad493fc 2971 *prot |= PAGE_EXEC;
9ee6e8bb
PB		 2972 return 0;
2973}
2974
702a9357
PM		 2975/* get_phys_addr - get the physical address for this virtual address
2976 *
2977 * Find the physical address corresponding to the given virtual address,
2978 * by doing a translation table walk on MMU based systems or using the
2979 * MPU state on MPU based systems.
2980 *
2981 * Returns 0 if the translation was successful. Otherwise, phys_ptr,
2982 * prot and page_size are not filled in, and the return value provides
2983 * information on why the translation aborted, in the format of a
2984 * DFSR/IFSR fault register, with the following caveats:
2985 * * we honour the short vs long DFSR format differences.
2986 * * the WnR bit is never set (the caller must do this).
2987 * * for MPU based systems we don't bother to return a full FSR format
2988 * value.
2989 *
2990 * @env: CPUARMState
2991 * @address: virtual address to get physical address for
2992 * @access_type: 0 for read, 1 for write, 2 for execute
2993 * @is_user: 0 for privileged access, 1 for user
2994 * @phys_ptr: set to the physical address corresponding to the virtual address
2995 * @prot: set to the permissions for the page containing phys_ptr
2996 * @page_size: set to the size of the page containing phys_ptr
2997 */
0ecb72a5 2998static inline int get_phys_addr(CPUARMState *env, uint32_t address,
9ee6e8bb 2999 int access_type, int is_user,
a8170e5e 3000 hwaddr *phys_ptr, int *prot,
d4c430a8 3001 target_ulong *page_size)
9ee6e8bb
PB		 3002{
3003 /* Fast Context Switch Extension. */
3004 if (address < 0x02000000)
3005 address += env->cp15.c13_fcse;
3006
3007 if ((env->cp15.c1_sys & 1) == 0) {
3008 /* MMU/MPU disabled. */
3009 *phys_ptr = address;
3ad493fc 3010 *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
d4c430a8 3011 *page_size = TARGET_PAGE_SIZE;
9ee6e8bb
PB		 3012 return 0;
3013 } else if (arm_feature(env, ARM_FEATURE_MPU)) {
d4c430a8 3014 *page_size = TARGET_PAGE_SIZE;
9ee6e8bb
PB		 3015 return get_phys_addr_mpu(env, address, access_type, is_user, phys_ptr,
3016 prot);
3dde962f
PM		 3017 } else if (extended_addresses_enabled(env)) {
3018 return get_phys_addr_lpae(env, address, access_type, is_user, phys_ptr,
3019 prot, page_size);
9ee6e8bb
PB		 3020 } else if (env->cp15.c1_sys & (1 << 23)) {
3021 return get_phys_addr_v6(env, address, access_type, is_user, phys_ptr,
d4c430a8 3022 prot, page_size);
9ee6e8bb
PB		 3023 } else {
3024 return get_phys_addr_v5(env, address, access_type, is_user, phys_ptr,
d4c430a8 3025 prot, page_size);
9ee6e8bb
PB		 3026 }
3027}
3028
0ecb72a5 3029int cpu_arm_handle_mmu_fault (CPUARMState *env, target_ulong address,
97b348e7 3030 int access_type, int mmu_idx)
b5ff1b31 3031{
a8170e5e 3032 hwaddr phys_addr;
d4c430a8 3033 target_ulong page_size;
b5ff1b31 3034 int prot;
6ebbf390 3035 int ret, is_user;
b5ff1b31 3036
6ebbf390 3037 is_user = mmu_idx == MMU_USER_IDX;
d4c430a8
PB		 3038 ret = get_phys_addr(env, address, access_type, is_user, &phys_addr, &prot,
3039 &page_size);
b5ff1b31
FB		 3040 if (ret == 0) {
3041 /* Map a single [sub]page. */
a8170e5e 3042 phys_addr &= ~(hwaddr)0x3ff;
b5ff1b31 3043 address &= ~(uint32_t)0x3ff;
3ad493fc 3044 tlb_set_page (env, address, phys_addr, prot, mmu_idx, page_size);
d4c430a8 3045 return 0;
b5ff1b31
FB		 3046 }
3047
3048 if (access_type == 2) {
3049 env->cp15.c5_insn = ret;
3050 env->cp15.c6_insn = address;
3051 env->exception_index = EXCP_PREFETCH_ABORT;
3052 } else {
3053 env->cp15.c5_data = ret;
9ee6e8bb
PB		 3054 if (access_type == 1 && arm_feature(env, ARM_FEATURE_V6))
3055 env->cp15.c5_data |= (1 << 11);
b5ff1b31
FB		 3056 env->cp15.c6_data = address;
3057 env->exception_index = EXCP_DATA_ABORT;
3058 }
3059 return 1;
3060}
3061
00b941e5 3062hwaddr arm_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
b5ff1b31 3063{
00b941e5 3064 ARMCPU *cpu = ARM_CPU(cs);
a8170e5e 3065 hwaddr phys_addr;
d4c430a8 3066 target_ulong page_size;
b5ff1b31
FB		 3067 int prot;
3068 int ret;
3069
00b941e5 3070 ret = get_phys_addr(&cpu->env, addr, 0, 0, &phys_addr, &prot, &page_size);
b5ff1b31 3071
00b941e5 3072 if (ret != 0) {
b5ff1b31 3073 return -1;
00b941e5 3074 }
b5ff1b31
FB		 3075
3076 return phys_addr;
3077}
3078
0ecb72a5 3079void HELPER(set_r13_banked)(CPUARMState *env, uint32_t mode, uint32_t val)
9ee6e8bb 3080{
39ea3d4e
PM		 3081 if ((env->uncached_cpsr & CPSR_M) == mode) {
3082 env->regs[13] = val;
3083 } else {
f5206413 3084 env->banked_r13[bank_number(mode)] = val;
39ea3d4e 3085 }
9ee6e8bb
PB		 3086}
3087
0ecb72a5 3088uint32_t HELPER(get_r13_banked)(CPUARMState *env, uint32_t mode)
9ee6e8bb 3089{
39ea3d4e
PM		 3090 if ((env->uncached_cpsr & CPSR_M) == mode) {
3091 return env->regs[13];
3092 } else {
f5206413 3093 return env->banked_r13[bank_number(mode)];
39ea3d4e 3094 }
9ee6e8bb
PB		 3095}
3096
0ecb72a5 3097uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg)
9ee6e8bb
PB		 3098{
3099 switch (reg) {
3100 case 0: /* APSR */
3101 return xpsr_read(env) & 0xf8000000;
3102 case 1: /* IAPSR */
3103 return xpsr_read(env) & 0xf80001ff;
3104 case 2: /* EAPSR */
3105 return xpsr_read(env) & 0xff00fc00;
3106 case 3: /* xPSR */
3107 return xpsr_read(env) & 0xff00fdff;
3108 case 5: /* IPSR */
3109 return xpsr_read(env) & 0x000001ff;
3110 case 6: /* EPSR */
3111 return xpsr_read(env) & 0x0700fc00;
3112 case 7: /* IEPSR */
3113 return xpsr_read(env) & 0x0700edff;
3114 case 8: /* MSP */
3115 return env->v7m.current_sp ? env->v7m.other_sp : env->regs[13];
3116 case 9: /* PSP */
3117 return env->v7m.current_sp ? env->regs[13] : env->v7m.other_sp;
3118 case 16: /* PRIMASK */
3119 return (env->uncached_cpsr & CPSR_I) != 0;
82845826
SH		 3120 case 17: /* BASEPRI */
3121 case 18: /* BASEPRI_MAX */
9ee6e8bb 3122 return env->v7m.basepri;
82845826
SH		 3123 case 19: /* FAULTMASK */
3124 return (env->uncached_cpsr & CPSR_F) != 0;
9ee6e8bb
PB		 3125 case 20: /* CONTROL */
3126 return env->v7m.control;
3127 default:
3128 /* ??? For debugging only. */
3129 cpu_abort(env, "Unimplemented system register read (%d)\n", reg);
3130 return 0;
3131 }
3132}
3133
0ecb72a5 3134void HELPER(v7m_msr)(CPUARMState *env, uint32_t reg, uint32_t val)
9ee6e8bb
PB		 3135{
3136 switch (reg) {
3137 case 0: /* APSR */
3138 xpsr_write(env, val, 0xf8000000);
3139 break;
3140 case 1: /* IAPSR */
3141 xpsr_write(env, val, 0xf8000000);
3142 break;
3143 case 2: /* EAPSR */
3144 xpsr_write(env, val, 0xfe00fc00);
3145 break;
3146 case 3: /* xPSR */
3147 xpsr_write(env, val, 0xfe00fc00);
3148 break;
3149 case 5: /* IPSR */
3150 /* IPSR bits are readonly. */
3151 break;
3152 case 6: /* EPSR */
3153 xpsr_write(env, val, 0x0600fc00);
3154 break;
3155 case 7: /* IEPSR */
3156 xpsr_write(env, val, 0x0600fc00);
3157 break;
3158 case 8: /* MSP */
3159 if (env->v7m.current_sp)
3160 env->v7m.other_sp = val;
3161 else
3162 env->regs[13] = val;
3163 break;
3164 case 9: /* PSP */
3165 if (env->v7m.current_sp)
3166 env->regs[13] = val;
3167 else
3168 env->v7m.other_sp = val;
3169 break;
3170 case 16: /* PRIMASK */
3171 if (val & 1)
3172 env->uncached_cpsr |= CPSR_I;
3173 else
3174 env->uncached_cpsr &= ~CPSR_I;
3175 break;
82845826 3176 case 17: /* BASEPRI */
9ee6e8bb
PB		 3177 env->v7m.basepri = val & 0xff;
3178 break;
82845826 3179 case 18: /* BASEPRI_MAX */
9ee6e8bb
PB		 3180 val &= 0xff;
3181 if (val != 0 && (val < env->v7m.basepri || env->v7m.basepri == 0))
3182 env->v7m.basepri = val;
3183 break;
82845826
SH		 3184 case 19: /* FAULTMASK */
3185 if (val & 1)
3186 env->uncached_cpsr |= CPSR_F;
3187 else
3188 env->uncached_cpsr &= ~CPSR_F;
3189 break;
9ee6e8bb
PB		 3190 case 20: /* CONTROL */
3191 env->v7m.control = val & 3;
3192 switch_v7m_sp(env, (val & 2) != 0);
3193 break;
3194 default:
3195 /* ??? For debugging only. */
3196 cpu_abort(env, "Unimplemented system register write (%d)\n", reg);
3197 return;
3198 }
3199}
3200
b5ff1b31 3201#endif
6ddbc6e4
PB		 3202
3203/* Note that signed overflow is undefined in C. The following routines are
3204 careful to use unsigned types where modulo arithmetic is required.
3205 Failure to do so _will_ break on newer gcc. */
3206
3207/* Signed saturating arithmetic. */
3208
1654b2d6 3209/* Perform 16-bit signed saturating addition. */
6ddbc6e4
PB		 3210static inline uint16_t add16_sat(uint16_t a, uint16_t b)
3211{
3212 uint16_t res;
3213
3214 res = a + b;
3215 if (((res ^ a) & 0x8000) && !((a ^ b) & 0x8000)) {
3216 if (a & 0x8000)
3217 res = 0x8000;
3218 else
3219 res = 0x7fff;
3220 }
3221 return res;
3222}
3223
1654b2d6 3224/* Perform 8-bit signed saturating addition. */
6ddbc6e4
PB		 3225static inline uint8_t add8_sat(uint8_t a, uint8_t b)
3226{
3227 uint8_t res;
3228
3229 res = a + b;
3230 if (((res ^ a) & 0x80) && !((a ^ b) & 0x80)) {
3231 if (a & 0x80)
3232 res = 0x80;
3233 else
3234 res = 0x7f;
3235 }
3236 return res;
3237}
3238
1654b2d6 3239/* Perform 16-bit signed saturating subtraction. */
6ddbc6e4
PB		 3240static inline uint16_t sub16_sat(uint16_t a, uint16_t b)
3241{
3242 uint16_t res;
3243
3244 res = a - b;
3245 if (((res ^ a) & 0x8000) && ((a ^ b) & 0x8000)) {
3246 if (a & 0x8000)
3247 res = 0x8000;
3248 else
3249 res = 0x7fff;
3250 }
3251 return res;
3252}
3253
1654b2d6 3254/* Perform 8-bit signed saturating subtraction. */
6ddbc6e4
PB		 3255static inline uint8_t sub8_sat(uint8_t a, uint8_t b)
3256{
3257 uint8_t res;
3258
3259 res = a - b;
3260 if (((res ^ a) & 0x80) && ((a ^ b) & 0x80)) {
3261 if (a & 0x80)
3262 res = 0x80;
3263 else
3264 res = 0x7f;
3265 }
3266 return res;
3267}
3268
3269#define ADD16(a, b, n) RESULT(add16_sat(a, b), n, 16);
3270#define SUB16(a, b, n) RESULT(sub16_sat(a, b), n, 16);
3271#define ADD8(a, b, n) RESULT(add8_sat(a, b), n, 8);
3272#define SUB8(a, b, n) RESULT(sub8_sat(a, b), n, 8);
3273#define PFX q
3274
3275#include "op_addsub.h"
3276
3277/* Unsigned saturating arithmetic. */
460a09c1 3278static inline uint16_t add16_usat(uint16_t a, uint16_t b)
6ddbc6e4
PB		 3279{
3280 uint16_t res;
3281 res = a + b;
3282 if (res < a)
3283 res = 0xffff;
3284 return res;
3285}
3286
460a09c1 3287static inline uint16_t sub16_usat(uint16_t a, uint16_t b)
6ddbc6e4 3288{
4c4fd3f8 3289 if (a > b)
6ddbc6e4
PB		 3290 return a - b;
3291 else
3292 return 0;
3293}
3294
3295static inline uint8_t add8_usat(uint8_t a, uint8_t b)
3296{
3297 uint8_t res;
3298 res = a + b;
3299 if (res < a)
3300 res = 0xff;
3301 return res;
3302}
3303
3304static inline uint8_t sub8_usat(uint8_t a, uint8_t b)
3305{
4c4fd3f8 3306 if (a > b)
6ddbc6e4
PB		 3307 return a - b;
3308 else
3309 return 0;
3310}
3311
3312#define ADD16(a, b, n) RESULT(add16_usat(a, b), n, 16);
3313#define SUB16(a, b, n) RESULT(sub16_usat(a, b), n, 16);
3314#define ADD8(a, b, n) RESULT(add8_usat(a, b), n, 8);
3315#define SUB8(a, b, n) RESULT(sub8_usat(a, b), n, 8);
3316#define PFX uq
3317
3318#include "op_addsub.h"
3319
3320/* Signed modulo arithmetic. */
3321#define SARITH16(a, b, n, op) do { \
3322 int32_t sum; \
db6e2e65 3323 sum = (int32_t)(int16_t)(a) op (int32_t)(int16_t)(b); \
6ddbc6e4
PB		 3324 RESULT(sum, n, 16); \
3325 if (sum >= 0) \
3326 ge |= 3 << (n * 2); \
3327 } while(0)
3328
3329#define SARITH8(a, b, n, op) do { \
3330 int32_t sum; \
db6e2e65 3331 sum = (int32_t)(int8_t)(a) op (int32_t)(int8_t)(b); \
6ddbc6e4
PB		 3332 RESULT(sum, n, 8); \
3333 if (sum >= 0) \
3334 ge |= 1 << n; \
3335 } while(0)
3336
3337
3338#define ADD16(a, b, n) SARITH16(a, b, n, +)
3339#define SUB16(a, b, n) SARITH16(a, b, n, -)
3340#define ADD8(a, b, n) SARITH8(a, b, n, +)
3341#define SUB8(a, b, n) SARITH8(a, b, n, -)
3342#define PFX s
3343#define ARITH_GE
3344
3345#include "op_addsub.h"
3346
3347/* Unsigned modulo arithmetic. */
3348#define ADD16(a, b, n) do { \
3349 uint32_t sum; \
3350 sum = (uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b); \
3351 RESULT(sum, n, 16); \
a87aa10b 3352 if ((sum >> 16) == 1) \
6ddbc6e4
PB		 3353 ge |= 3 << (n * 2); \
3354 } while(0)
3355
3356#define ADD8(a, b, n) do { \
3357 uint32_t sum; \
3358 sum = (uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b); \
3359 RESULT(sum, n, 8); \
a87aa10b
AZ		 3360 if ((sum >> 8) == 1) \
3361 ge |= 1 << n; \
6ddbc6e4
PB		 3362 } while(0)
3363
3364#define SUB16(a, b, n) do { \
3365 uint32_t sum; \
3366 sum = (uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b); \
3367 RESULT(sum, n, 16); \
3368 if ((sum >> 16) == 0) \
3369 ge |= 3 << (n * 2); \
3370 } while(0)
3371
3372#define SUB8(a, b, n) do { \
3373 uint32_t sum; \
3374 sum = (uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b); \
3375 RESULT(sum, n, 8); \
3376 if ((sum >> 8) == 0) \
a87aa10b 3377 ge |= 1 << n; \
6ddbc6e4
PB		 3378 } while(0)
3379
3380#define PFX u
3381#define ARITH_GE
3382
3383#include "op_addsub.h"
3384
3385/* Halved signed arithmetic. */
3386#define ADD16(a, b, n) \
3387 RESULT(((int32_t)(int16_t)(a) + (int32_t)(int16_t)(b)) >> 1, n, 16)
3388#define SUB16(a, b, n) \
3389 RESULT(((int32_t)(int16_t)(a) - (int32_t)(int16_t)(b)) >> 1, n, 16)
3390#define ADD8(a, b, n) \
3391 RESULT(((int32_t)(int8_t)(a) + (int32_t)(int8_t)(b)) >> 1, n, 8)
3392#define SUB8(a, b, n) \
3393 RESULT(((int32_t)(int8_t)(a) - (int32_t)(int8_t)(b)) >> 1, n, 8)
3394#define PFX sh
3395
3396#include "op_addsub.h"
3397
3398/* Halved unsigned arithmetic. */
3399#define ADD16(a, b, n) \
3400 RESULT(((uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b)) >> 1, n, 16)
3401#define SUB16(a, b, n) \
3402 RESULT(((uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b)) >> 1, n, 16)
3403#define ADD8(a, b, n) \
3404 RESULT(((uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b)) >> 1, n, 8)
3405#define SUB8(a, b, n) \
3406 RESULT(((uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b)) >> 1, n, 8)
3407#define PFX uh
3408
3409#include "op_addsub.h"
3410
3411static inline uint8_t do_usad(uint8_t a, uint8_t b)
3412{
3413 if (a > b)
3414 return a - b;
3415 else
3416 return b - a;
3417}
3418
3419/* Unsigned sum of absolute byte differences. */
3420uint32_t HELPER(usad8)(uint32_t a, uint32_t b)
3421{
3422 uint32_t sum;
3423 sum = do_usad(a, b);
3424 sum += do_usad(a >> 8, b >> 8);
3425 sum += do_usad(a >> 16, b >>16);
3426 sum += do_usad(a >> 24, b >> 24);
3427 return sum;
3428}
3429
3430/* For ARMv6 SEL instruction. */
3431uint32_t HELPER(sel_flags)(uint32_t flags, uint32_t a, uint32_t b)
3432{
3433 uint32_t mask;
3434
3435 mask = 0;
3436 if (flags & 1)
3437 mask |= 0xff;
3438 if (flags & 2)
3439 mask |= 0xff00;
3440 if (flags & 4)
3441 mask |= 0xff0000;
3442 if (flags & 8)
3443 mask |= 0xff000000;
3444 return (a & mask) | (b & ~mask);
3445}
3446
b90372ad
PM		 3447/* VFP support. We follow the convention used for VFP instructions:
3448 Single precision routines have a "s" suffix, double precision a
4373f3ce
PB		 3449 "d" suffix. */
3450
3451/* Convert host exception flags to vfp form. */
3452static inline int vfp_exceptbits_from_host(int host_bits)
3453{
3454 int target_bits = 0;
3455
3456 if (host_bits & float_flag_invalid)
3457 target_bits |= 1;
3458 if (host_bits & float_flag_divbyzero)
3459 target_bits |= 2;
3460 if (host_bits & float_flag_overflow)
3461 target_bits |= 4;
36802b6b 3462 if (host_bits & (float_flag_underflow | float_flag_output_denormal))
4373f3ce
PB		 3463 target_bits |= 8;
3464 if (host_bits & float_flag_inexact)
3465 target_bits |= 0x10;
cecd8504
PM		 3466 if (host_bits & float_flag_input_denormal)
3467 target_bits |= 0x80;
4373f3ce
PB		 3468 return target_bits;
3469}
3470
0ecb72a5 3471uint32_t HELPER(vfp_get_fpscr)(CPUARMState *env)
4373f3ce
PB		 3472{
3473 int i;
3474 uint32_t fpscr;
3475
3476 fpscr = (env->vfp.xregs[ARM_VFP_FPSCR] & 0xffc8ffff)
3477 | (env->vfp.vec_len << 16)
3478 | (env->vfp.vec_stride << 20);
3479 i = get_float_exception_flags(&env->vfp.fp_status);
3a492f3a 3480 i |= get_float_exception_flags(&env->vfp.standard_fp_status);
4373f3ce
PB		 3481 fpscr |= vfp_exceptbits_from_host(i);
3482 return fpscr;
3483}
3484
0ecb72a5 3485uint32_t vfp_get_fpscr(CPUARMState *env)
01653295
PM		 3486{
3487 return HELPER(vfp_get_fpscr)(env);
3488}
3489
4373f3ce
PB		 3490/* Convert vfp exception flags to target form. */
3491static inline int vfp_exceptbits_to_host(int target_bits)
3492{
3493 int host_bits = 0;
3494
3495 if (target_bits & 1)
3496 host_bits |= float_flag_invalid;
3497 if (target_bits & 2)
3498 host_bits |= float_flag_divbyzero;
3499 if (target_bits & 4)
3500 host_bits |= float_flag_overflow;
3501 if (target_bits & 8)
3502 host_bits |= float_flag_underflow;
3503 if (target_bits & 0x10)
3504 host_bits |= float_flag_inexact;
cecd8504
PM		 3505 if (target_bits & 0x80)
3506 host_bits |= float_flag_input_denormal;
4373f3ce
PB		 3507 return host_bits;
3508}
3509
0ecb72a5 3510void HELPER(vfp_set_fpscr)(CPUARMState *env, uint32_t val)
4373f3ce
PB		 3511{
3512 int i;
3513 uint32_t changed;
3514
3515 changed = env->vfp.xregs[ARM_VFP_FPSCR];
3516 env->vfp.xregs[ARM_VFP_FPSCR] = (val & 0xffc8ffff);
3517 env->vfp.vec_len = (val >> 16) & 7;
3518 env->vfp.vec_stride = (val >> 20) & 3;
3519
3520 changed ^= val;
3521 if (changed & (3 << 22)) {
3522 i = (val >> 22) & 3;
3523 switch (i) {
3524 case 0:
3525 i = float_round_nearest_even;
3526 break;
3527 case 1:
3528 i = float_round_up;
3529 break;
3530 case 2:
3531 i = float_round_down;
3532 break;
3533 case 3:
3534 i = float_round_to_zero;
3535 break;
3536 }
3537 set_float_rounding_mode(i, &env->vfp.fp_status);
3538 }
cecd8504 3539 if (changed & (1 << 24)) {
fe76d976 3540 set_flush_to_zero((val & (1 << 24)) != 0, &env->vfp.fp_status);
cecd8504
PM		 3541 set_flush_inputs_to_zero((val & (1 << 24)) != 0, &env->vfp.fp_status);
3542 }
5c7908ed
PB		 3543 if (changed & (1 << 25))
3544 set_default_nan_mode((val & (1 << 25)) != 0, &env->vfp.fp_status);
4373f3ce 3545
b12c390b 3546 i = vfp_exceptbits_to_host(val);
4373f3ce 3547 set_float_exception_flags(i, &env->vfp.fp_status);
3a492f3a 3548 set_float_exception_flags(0, &env->vfp.standard_fp_status);
4373f3ce
PB		 3549}
3550
0ecb72a5 3551void vfp_set_fpscr(CPUARMState *env, uint32_t val)
01653295
PM		 3552{
3553 HELPER(vfp_set_fpscr)(env, val);
3554}
3555
4373f3ce
PB		 3556#define VFP_HELPER(name, p) HELPER(glue(glue(vfp_,name),p))
3557
3558#define VFP_BINOP(name) \
ae1857ec 3559float32 VFP_HELPER(name, s)(float32 a, float32 b, void *fpstp) \
4373f3ce 3560{ \
ae1857ec
PM		 3561 float_status *fpst = fpstp; \
3562 return float32_ ## name(a, b, fpst); \
4373f3ce 3563} \
ae1857ec 3564float64 VFP_HELPER(name, d)(float64 a, float64 b, void *fpstp) \
4373f3ce 3565{ \
ae1857ec
PM		 3566 float_status *fpst = fpstp; \
3567 return float64_ ## name(a, b, fpst); \
4373f3ce
PB		 3568}
3569VFP_BINOP(add)
3570VFP_BINOP(sub)
3571VFP_BINOP(mul)
3572VFP_BINOP(div)
3573#undef VFP_BINOP
3574
3575float32 VFP_HELPER(neg, s)(float32 a)
3576{
3577 return float32_chs(a);
3578}
3579
3580float64 VFP_HELPER(neg, d)(float64 a)
3581{
66230e0d 3582 return float64_chs(a);
4373f3ce
PB		 3583}
3584
3585float32 VFP_HELPER(abs, s)(float32 a)
3586{
3587 return float32_abs(a);
3588}
3589
3590float64 VFP_HELPER(abs, d)(float64 a)
3591{
66230e0d 3592 return float64_abs(a);
4373f3ce
PB		 3593}
3594
0ecb72a5 3595float32 VFP_HELPER(sqrt, s)(float32 a, CPUARMState *env)
4373f3ce
PB		 3596{
3597 return float32_sqrt(a, &env->vfp.fp_status);
3598}
3599
0ecb72a5 3600float64 VFP_HELPER(sqrt, d)(float64 a, CPUARMState *env)
4373f3ce
PB		 3601{
3602 return float64_sqrt(a, &env->vfp.fp_status);
3603}
3604
3605/* XXX: check quiet/signaling case */
3606#define DO_VFP_cmp(p, type) \
0ecb72a5 3607void VFP_HELPER(cmp, p)(type a, type b, CPUARMState *env) \
4373f3ce
PB		 3608{ \
3609 uint32_t flags; \
3610 switch(type ## _compare_quiet(a, b, &env->vfp.fp_status)) { \
3611 case 0: flags = 0x6; break; \
3612 case -1: flags = 0x8; break; \
3613 case 1: flags = 0x2; break; \
3614 default: case 2: flags = 0x3; break; \
3615 } \
3616 env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \
3617 | (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \
3618} \
0ecb72a5 3619void VFP_HELPER(cmpe, p)(type a, type b, CPUARMState *env) \
4373f3ce
PB		 3620{ \
3621 uint32_t flags; \
3622 switch(type ## _compare(a, b, &env->vfp.fp_status)) { \
3623 case 0: flags = 0x6; break; \
3624 case -1: flags = 0x8; break; \
3625 case 1: flags = 0x2; break; \
3626 default: case 2: flags = 0x3; break; \
3627 } \
3628 env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \
3629 | (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \
3630}
3631DO_VFP_cmp(s, float32)
3632DO_VFP_cmp(d, float64)
3633#undef DO_VFP_cmp
3634
5500b06c 3635/* Integer to float and float to integer conversions */
4373f3ce 3636
5500b06c
PM		 3637#define CONV_ITOF(name, fsz, sign) \
3638 float##fsz HELPER(name)(uint32_t x, void *fpstp) \
3639{ \
3640 float_status *fpst = fpstp; \
85836979 3641 return sign##int32_to_##float##fsz((sign##int32_t)x, fpst); \
4373f3ce
PB		 3642}
3643
5500b06c
PM		 3644#define CONV_FTOI(name, fsz, sign, round) \
3645uint32_t HELPER(name)(float##fsz x, void *fpstp) \
3646{ \
3647 float_status *fpst = fpstp; \
3648 if (float##fsz##_is_any_nan(x)) { \
3649 float_raise(float_flag_invalid, fpst); \
3650 return 0; \
3651 } \
3652 return float##fsz##_to_##sign##int32##round(x, fpst); \
4373f3ce
PB		 3653}
3654
5500b06c
PM		 3655#define FLOAT_CONVS(name, p, fsz, sign) \
3656CONV_ITOF(vfp_##name##to##p, fsz, sign) \
3657CONV_FTOI(vfp_to##name##p, fsz, sign, ) \
3658CONV_FTOI(vfp_to##name##z##p, fsz, sign, _round_to_zero)
4373f3ce 3659
5500b06c
PM		 3660FLOAT_CONVS(si, s, 32, )
3661FLOAT_CONVS(si, d, 64, )
3662FLOAT_CONVS(ui, s, 32, u)
3663FLOAT_CONVS(ui, d, 64, u)
4373f3ce 3664
5500b06c
PM		 3665#undef CONV_ITOF
3666#undef CONV_FTOI
3667#undef FLOAT_CONVS
4373f3ce
PB		 3668
3669/* floating point conversion */
0ecb72a5 3670float64 VFP_HELPER(fcvtd, s)(float32 x, CPUARMState *env)
4373f3ce 3671{
2d627737
PM		 3672 float64 r = float32_to_float64(x, &env->vfp.fp_status);
3673 /* ARM requires that S<->D conversion of any kind of NaN generates
3674 * a quiet NaN by forcing the most significant frac bit to 1.
3675 */
3676 return float64_maybe_silence_nan(r);
4373f3ce
PB		 3677}
3678
0ecb72a5 3679float32 VFP_HELPER(fcvts, d)(float64 x, CPUARMState *env)
4373f3ce 3680{
2d627737
PM		 3681 float32 r = float64_to_float32(x, &env->vfp.fp_status);
3682 /* ARM requires that S<->D conversion of any kind of NaN generates
3683 * a quiet NaN by forcing the most significant frac bit to 1.
3684 */
3685 return float32_maybe_silence_nan(r);
4373f3ce
PB		 3686}
3687
3688/* VFP3 fixed point conversion. */
622465e1 3689#define VFP_CONV_FIX(name, p, fsz, itype, sign) \
5500b06c
PM		 3690float##fsz HELPER(vfp_##name##to##p)(uint##fsz##_t x, uint32_t shift, \
3691 void *fpstp) \
4373f3ce 3692{ \
5500b06c 3693 float_status *fpst = fpstp; \
622465e1 3694 float##fsz tmp; \
5500b06c
PM		 3695 tmp = sign##int32_to_##float##fsz((itype##_t)x, fpst); \
3696 return float##fsz##_scalbn(tmp, -(int)shift, fpst); \
4373f3ce 3697} \
5500b06c
PM		 3698uint##fsz##_t HELPER(vfp_to##name##p)(float##fsz x, uint32_t shift, \
3699 void *fpstp) \
4373f3ce 3700{ \
5500b06c 3701 float_status *fpst = fpstp; \
622465e1
PM		 3702 float##fsz tmp; \
3703 if (float##fsz##_is_any_nan(x)) { \
5500b06c 3704 float_raise(float_flag_invalid, fpst); \
622465e1 3705 return 0; \
09d9487f 3706 } \
5500b06c
PM		 3707 tmp = float##fsz##_scalbn(x, shift, fpst); \
3708 return float##fsz##_to_##itype##_round_to_zero(tmp, fpst); \
622465e1
PM		 3709}
3710
3711VFP_CONV_FIX(sh, d, 64, int16, )
3712VFP_CONV_FIX(sl, d, 64, int32, )
3713VFP_CONV_FIX(uh, d, 64, uint16, u)
3714VFP_CONV_FIX(ul, d, 64, uint32, u)
3715VFP_CONV_FIX(sh, s, 32, int16, )
3716VFP_CONV_FIX(sl, s, 32, int32, )
3717VFP_CONV_FIX(uh, s, 32, uint16, u)
3718VFP_CONV_FIX(ul, s, 32, uint32, u)
4373f3ce
PB		 3719#undef VFP_CONV_FIX
3720
60011498 3721/* Half precision conversions. */
0ecb72a5 3722static float32 do_fcvt_f16_to_f32(uint32_t a, CPUARMState *env, float_status *s)
60011498 3723{
60011498 3724 int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0;
fb91678d
PM		 3725 float32 r = float16_to_float32(make_float16(a), ieee, s);
3726 if (ieee) {
3727 return float32_maybe_silence_nan(r);
3728 }
3729 return r;
60011498
PB		 3730}
3731
0ecb72a5 3732static uint32_t do_fcvt_f32_to_f16(float32 a, CPUARMState *env, float_status *s)
60011498 3733{
60011498 3734 int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0;
fb91678d
PM		 3735 float16 r = float32_to_float16(a, ieee, s);
3736 if (ieee) {
3737 r = float16_maybe_silence_nan(r);
3738 }
3739 return float16_val(r);
60011498
PB		 3740}
3741
0ecb72a5 3742float32 HELPER(neon_fcvt_f16_to_f32)(uint32_t a, CPUARMState *env)
2d981da7
PM		 3743{
3744 return do_fcvt_f16_to_f32(a, env, &env->vfp.standard_fp_status);
3745}
3746
0ecb72a5 3747uint32_t HELPER(neon_fcvt_f32_to_f16)(float32 a, CPUARMState *env)
2d981da7
PM		 3748{
3749 return do_fcvt_f32_to_f16(a, env, &env->vfp.standard_fp_status);
3750}
3751
0ecb72a5 3752float32 HELPER(vfp_fcvt_f16_to_f32)(uint32_t a, CPUARMState *env)
2d981da7
PM		 3753{
3754 return do_fcvt_f16_to_f32(a, env, &env->vfp.fp_status);
3755}
3756
0ecb72a5 3757uint32_t HELPER(vfp_fcvt_f32_to_f16)(float32 a, CPUARMState *env)
2d981da7
PM		 3758{
3759 return do_fcvt_f32_to_f16(a, env, &env->vfp.fp_status);
3760}
3761
dda3ec49 3762#define float32_two make_float32(0x40000000)
6aae3df1
PM		 3763#define float32_three make_float32(0x40400000)
3764#define float32_one_point_five make_float32(0x3fc00000)
dda3ec49 3765
0ecb72a5 3766float32 HELPER(recps_f32)(float32 a, float32 b, CPUARMState *env)
4373f3ce 3767{
dda3ec49
PM		 3768 float_status *s = &env->vfp.standard_fp_status;
3769 if ((float32_is_infinity(a) && float32_is_zero_or_denormal(b)) ||
3770 (float32_is_infinity(b) && float32_is_zero_or_denormal(a))) {
43fe9bdb
PM		 3771 if (!(float32_is_zero(a) || float32_is_zero(b))) {
3772 float_raise(float_flag_input_denormal, s);
3773 }
dda3ec49
PM		 3774 return float32_two;
3775 }
3776 return float32_sub(float32_two, float32_mul(a, b, s), s);
4373f3ce
PB		 3777}
3778
0ecb72a5 3779float32 HELPER(rsqrts_f32)(float32 a, float32 b, CPUARMState *env)
4373f3ce 3780{
71826966 3781 float_status *s = &env->vfp.standard_fp_status;
9ea62f57
PM		 3782 float32 product;
3783 if ((float32_is_infinity(a) && float32_is_zero_or_denormal(b)) ||
3784 (float32_is_infinity(b) && float32_is_zero_or_denormal(a))) {
43fe9bdb
PM		 3785 if (!(float32_is_zero(a) || float32_is_zero(b))) {
3786 float_raise(float_flag_input_denormal, s);
3787 }
6aae3df1 3788 return float32_one_point_five;
9ea62f57 3789 }
6aae3df1
PM		 3790 product = float32_mul(a, b, s);
3791 return float32_div(float32_sub(float32_three, product, s), float32_two, s);
4373f3ce
PB		 3792}
3793
8f8e3aa4
PB		 3794/* NEON helpers. */
3795
56bf4fe2
CL		 3796/* Constants 256 and 512 are used in some helpers; we avoid relying on
3797 * int->float conversions at run-time. */
3798#define float64_256 make_float64(0x4070000000000000LL)
3799#define float64_512 make_float64(0x4080000000000000LL)
3800
fe0e4872
CL		 3801/* The algorithm that must be used to calculate the estimate
3802 * is specified by the ARM ARM.
3803 */
0ecb72a5 3804static float64 recip_estimate(float64 a, CPUARMState *env)
fe0e4872 3805{
1146a817
PM		 3806 /* These calculations mustn't set any fp exception flags,
3807 * so we use a local copy of the fp_status.
3808 */
3809 float_status dummy_status = env->vfp.standard_fp_status;
3810 float_status *s = &dummy_status;
fe0e4872
CL		 3811 /* q = (int)(a * 512.0) */
3812 float64 q = float64_mul(float64_512, a, s);
3813 int64_t q_int = float64_to_int64_round_to_zero(q, s);
3814
3815 /* r = 1.0 / (((double)q + 0.5) / 512.0) */
3816 q = int64_to_float64(q_int, s);
3817 q = float64_add(q, float64_half, s);
3818 q = float64_div(q, float64_512, s);
3819 q = float64_div(float64_one, q, s);
3820
3821 /* s = (int)(256.0 * r + 0.5) */
3822 q = float64_mul(q, float64_256, s);
3823 q = float64_add(q, float64_half, s);
3824 q_int = float64_to_int64_round_to_zero(q, s);
3825
3826 /* return (double)s / 256.0 */
3827 return float64_div(int64_to_float64(q_int, s), float64_256, s);
3828}
3829
0ecb72a5 3830float32 HELPER(recpe_f32)(float32 a, CPUARMState *env)
4373f3ce 3831{
fe0e4872
CL		 3832 float_status *s = &env->vfp.standard_fp_status;
3833 float64 f64;
3834 uint32_t val32 = float32_val(a);
3835
3836 int result_exp;
3837 int a_exp = (val32 & 0x7f800000) >> 23;
3838 int sign = val32 & 0x80000000;
3839
3840 if (float32_is_any_nan(a)) {
3841 if (float32_is_signaling_nan(a)) {
3842 float_raise(float_flag_invalid, s);
3843 }
3844 return float32_default_nan;
3845 } else if (float32_is_infinity(a)) {
3846 return float32_set_sign(float32_zero, float32_is_neg(a));
3847 } else if (float32_is_zero_or_denormal(a)) {
43fe9bdb
PM		 3848 if (!float32_is_zero(a)) {
3849 float_raise(float_flag_input_denormal, s);
3850 }
fe0e4872
CL		 3851 float_raise(float_flag_divbyzero, s);
3852 return float32_set_sign(float32_infinity, float32_is_neg(a));
3853 } else if (a_exp >= 253) {
3854 float_raise(float_flag_underflow, s);
3855 return float32_set_sign(float32_zero, float32_is_neg(a));
3856 }
3857
3858 f64 = make_float64((0x3feULL << 52)
3859 | ((int64_t)(val32 & 0x7fffff) << 29));
3860
3861 result_exp = 253 - a_exp;
3862
3863 f64 = recip_estimate(f64, env);
3864
3865 val32 = sign
3866 | ((result_exp & 0xff) << 23)
3867 | ((float64_val(f64) >> 29) & 0x7fffff);
3868 return make_float32(val32);
4373f3ce
PB		 3869}
3870
e07be5d2
CL		 3871/* The algorithm that must be used to calculate the estimate
3872 * is specified by the ARM ARM.
3873 */
0ecb72a5 3874static float64 recip_sqrt_estimate(float64 a, CPUARMState *env)
e07be5d2 3875{
1146a817
PM		 3876 /* These calculations mustn't set any fp exception flags,
3877 * so we use a local copy of the fp_status.
3878 */
3879 float_status dummy_status = env->vfp.standard_fp_status;
3880 float_status *s = &dummy_status;
e07be5d2
CL		 3881 float64 q;
3882 int64_t q_int;
3883
3884 if (float64_lt(a, float64_half, s)) {
3885 /* range 0.25 <= a < 0.5 */
3886
3887 /* a in units of 1/512 rounded down */
3888 /* q0 = (int)(a * 512.0); */
3889 q = float64_mul(float64_512, a, s);
3890 q_int = float64_to_int64_round_to_zero(q, s);
3891
3892 /* reciprocal root r */
3893 /* r = 1.0 / sqrt(((double)q0 + 0.5) / 512.0); */
3894 q = int64_to_float64(q_int, s);
3895 q = float64_add(q, float64_half, s);
3896 q = float64_div(q, float64_512, s);
3897 q = float64_sqrt(q, s);
3898 q = float64_div(float64_one, q, s);
3899 } else {
3900 /* range 0.5 <= a < 1.0 */
3901
3902 /* a in units of 1/256 rounded down */
3903 /* q1 = (int)(a * 256.0); */
3904 q = float64_mul(float64_256, a, s);
3905 int64_t q_int = float64_to_int64_round_to_zero(q, s);
3906
3907 /* reciprocal root r */
3908 /* r = 1.0 /sqrt(((double)q1 + 0.5) / 256); */
3909 q = int64_to_float64(q_int, s);
3910 q = float64_add(q, float64_half, s);
3911 q = float64_div(q, float64_256, s);
3912 q = float64_sqrt(q, s);
3913 q = float64_div(float64_one, q, s);
3914 }
3915 /* r in units of 1/256 rounded to nearest */
3916 /* s = (int)(256.0 * r + 0.5); */
3917
3918 q = float64_mul(q, float64_256,s );
3919 q = float64_add(q, float64_half, s);
3920 q_int = float64_to_int64_round_to_zero(q, s);
3921
3922 /* return (double)s / 256.0;*/
3923 return float64_div(int64_to_float64(q_int, s), float64_256, s);
3924}
3925
0ecb72a5 3926float32 HELPER(rsqrte_f32)(float32 a, CPUARMState *env)
4373f3ce 3927{
e07be5d2
CL		 3928 float_status *s = &env->vfp.standard_fp_status;
3929 int result_exp;
3930 float64 f64;
3931 uint32_t val;
3932 uint64_t val64;
3933
3934 val = float32_val(a);
3935
3936 if (float32_is_any_nan(a)) {
3937 if (float32_is_signaling_nan(a)) {
3938 float_raise(float_flag_invalid, s);
3939 }
3940 return float32_default_nan;
3941 } else if (float32_is_zero_or_denormal(a)) {
43fe9bdb
PM		 3942 if (!float32_is_zero(a)) {
3943 float_raise(float_flag_input_denormal, s);
3944 }
e07be5d2
CL		 3945 float_raise(float_flag_divbyzero, s);
3946 return float32_set_sign(float32_infinity, float32_is_neg(a));
3947 } else if (float32_is_neg(a)) {
3948 float_raise(float_flag_invalid, s);
3949 return float32_default_nan;
3950 } else if (float32_is_infinity(a)) {
3951 return float32_zero;
3952 }
3953
3954 /* Normalize to a double-precision value between 0.25 and 1.0,
3955 * preserving the parity of the exponent. */
3956 if ((val & 0x800000) == 0) {
3957 f64 = make_float64(((uint64_t)(val & 0x80000000) << 32)
3958 | (0x3feULL << 52)
3959 | ((uint64_t)(val & 0x7fffff) << 29));
3960 } else {
3961 f64 = make_float64(((uint64_t)(val & 0x80000000) << 32)
3962 | (0x3fdULL << 52)
3963 | ((uint64_t)(val & 0x7fffff) << 29));
3964 }
3965
3966 result_exp = (380 - ((val & 0x7f800000) >> 23)) / 2;
3967
3968 f64 = recip_sqrt_estimate(f64, env);
3969
3970 val64 = float64_val(f64);
3971
26cc6abf 3972 val = ((result_exp & 0xff) << 23)
e07be5d2
CL		 3973 | ((val64 >> 29) & 0x7fffff);
3974 return make_float32(val);
4373f3ce
PB		 3975}
3976
0ecb72a5 3977uint32_t HELPER(recpe_u32)(uint32_t a, CPUARMState *env)
4373f3ce 3978{
fe0e4872
CL		 3979 float64 f64;
3980
3981 if ((a & 0x80000000) == 0) {
3982 return 0xffffffff;
3983 }
3984
3985 f64 = make_float64((0x3feULL << 52)
3986 | ((int64_t)(a & 0x7fffffff) << 21));
3987
3988 f64 = recip_estimate (f64, env);
3989
3990 return 0x80000000 | ((float64_val(f64) >> 21) & 0x7fffffff);
4373f3ce
PB		 3991}
3992
0ecb72a5 3993uint32_t HELPER(rsqrte_u32)(uint32_t a, CPUARMState *env)
4373f3ce 3994{
e07be5d2
CL		 3995 float64 f64;
3996
3997 if ((a & 0xc0000000) == 0) {
3998 return 0xffffffff;
3999 }
4000
4001 if (a & 0x80000000) {
4002 f64 = make_float64((0x3feULL << 52)
4003 | ((uint64_t)(a & 0x7fffffff) << 21));
4004 } else { /* bits 31-30 == '01' */
4005 f64 = make_float64((0x3fdULL << 52)
4006 | ((uint64_t)(a & 0x3fffffff) << 22));
4007 }
4008
4009 f64 = recip_sqrt_estimate(f64, env);
4010
4011 return 0x80000000 | ((float64_val(f64) >> 21) & 0x7fffffff);
4373f3ce 4012}
fe1479c3 4013
da97f52c
PM		 4014/* VFPv4 fused multiply-accumulate */
4015float32 VFP_HELPER(muladd, s)(float32 a, float32 b, float32 c, void *fpstp)
4016{
4017 float_status *fpst = fpstp;
4018 return float32_muladd(a, b, c, 0, fpst);
4019}
4020
4021float64 VFP_HELPER(muladd, d)(float64 a, float64 b, float64 c, void *fpstp)
4022{
4023 float_status *fpst = fpstp;
4024 return float64_muladd(a, b, c, 0, fpst);
4025}
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