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Commit | Line | Data |
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b5ff1b31 FB |
1 | #include <stdio.h> |
2 | #include <stdlib.h> | |
3 | #include <string.h> | |
4 | ||
5 | #include "cpu.h" | |
6 | #include "exec-all.h" | |
9ee6e8bb | 7 | #include "gdbstub.h" |
b26eefb6 | 8 | #include "helpers.h" |
ca10f867 | 9 | #include "qemu-common.h" |
7bbcb0af | 10 | #include "host-utils.h" |
9ee6e8bb | 11 | |
10055562 PB |
12 | static uint32_t cortexa9_cp15_c0_c1[8] = |
13 | { 0x1031, 0x11, 0x000, 0, 0x00100103, 0x20000000, 0x01230000, 0x00002111 }; | |
14 | ||
15 | static uint32_t cortexa9_cp15_c0_c2[8] = | |
16 | { 0x00101111, 0x13112111, 0x21232041, 0x11112131, 0x00111142, 0, 0, 0 }; | |
17 | ||
9ee6e8bb PB |
18 | static uint32_t cortexa8_cp15_c0_c1[8] = |
19 | { 0x1031, 0x11, 0x400, 0, 0x31100003, 0x20000000, 0x01202000, 0x11 }; | |
20 | ||
21 | static uint32_t cortexa8_cp15_c0_c2[8] = | |
22 | { 0x00101111, 0x12112111, 0x21232031, 0x11112131, 0x00111142, 0, 0, 0 }; | |
23 | ||
24 | static uint32_t mpcore_cp15_c0_c1[8] = | |
25 | { 0x111, 0x1, 0, 0x2, 0x01100103, 0x10020302, 0x01222000, 0 }; | |
26 | ||
27 | static uint32_t mpcore_cp15_c0_c2[8] = | |
28 | { 0x00100011, 0x12002111, 0x11221011, 0x01102131, 0x141, 0, 0, 0 }; | |
29 | ||
30 | static uint32_t arm1136_cp15_c0_c1[8] = | |
31 | { 0x111, 0x1, 0x2, 0x3, 0x01130003, 0x10030302, 0x01222110, 0 }; | |
32 | ||
33 | static uint32_t arm1136_cp15_c0_c2[8] = | |
34 | { 0x00140011, 0x12002111, 0x11231111, 0x01102131, 0x141, 0, 0, 0 }; | |
b5ff1b31 | 35 | |
aaed909a FB |
36 | static uint32_t cpu_arm_find_by_name(const char *name); |
37 | ||
f3d6b95e PB |
38 | static inline void set_feature(CPUARMState *env, int feature) |
39 | { | |
40 | env->features |= 1u << feature; | |
41 | } | |
42 | ||
43 | static void cpu_reset_model_id(CPUARMState *env, uint32_t id) | |
44 | { | |
45 | env->cp15.c0_cpuid = id; | |
46 | switch (id) { | |
47 | case ARM_CPUID_ARM926: | |
48 | set_feature(env, ARM_FEATURE_VFP); | |
49 | env->vfp.xregs[ARM_VFP_FPSID] = 0x41011090; | |
c1713132 | 50 | env->cp15.c0_cachetype = 0x1dd20d2; |
610c3c8a | 51 | env->cp15.c1_sys = 0x00090078; |
f3d6b95e | 52 | break; |
ce819861 PB |
53 | case ARM_CPUID_ARM946: |
54 | set_feature(env, ARM_FEATURE_MPU); | |
55 | env->cp15.c0_cachetype = 0x0f004006; | |
610c3c8a | 56 | env->cp15.c1_sys = 0x00000078; |
ce819861 | 57 | break; |
f3d6b95e PB |
58 | case ARM_CPUID_ARM1026: |
59 | set_feature(env, ARM_FEATURE_VFP); | |
60 | set_feature(env, ARM_FEATURE_AUXCR); | |
61 | env->vfp.xregs[ARM_VFP_FPSID] = 0x410110a0; | |
c1713132 | 62 | env->cp15.c0_cachetype = 0x1dd20d2; |
610c3c8a | 63 | env->cp15.c1_sys = 0x00090078; |
c1713132 | 64 | break; |
827df9f3 | 65 | case ARM_CPUID_ARM1136_R2: |
9ee6e8bb PB |
66 | case ARM_CPUID_ARM1136: |
67 | set_feature(env, ARM_FEATURE_V6); | |
68 | set_feature(env, ARM_FEATURE_VFP); | |
69 | set_feature(env, ARM_FEATURE_AUXCR); | |
70 | env->vfp.xregs[ARM_VFP_FPSID] = 0x410120b4; | |
71 | env->vfp.xregs[ARM_VFP_MVFR0] = 0x11111111; | |
72 | env->vfp.xregs[ARM_VFP_MVFR1] = 0x00000000; | |
73 | memcpy(env->cp15.c0_c1, arm1136_cp15_c0_c1, 8 * sizeof(uint32_t)); | |
22478e79 | 74 | memcpy(env->cp15.c0_c2, arm1136_cp15_c0_c2, 8 * sizeof(uint32_t)); |
9ee6e8bb PB |
75 | env->cp15.c0_cachetype = 0x1dd20d2; |
76 | break; | |
77 | case ARM_CPUID_ARM11MPCORE: | |
78 | set_feature(env, ARM_FEATURE_V6); | |
79 | set_feature(env, ARM_FEATURE_V6K); | |
80 | set_feature(env, ARM_FEATURE_VFP); | |
81 | set_feature(env, ARM_FEATURE_AUXCR); | |
82 | env->vfp.xregs[ARM_VFP_FPSID] = 0x410120b4; | |
83 | env->vfp.xregs[ARM_VFP_MVFR0] = 0x11111111; | |
84 | env->vfp.xregs[ARM_VFP_MVFR1] = 0x00000000; | |
85 | memcpy(env->cp15.c0_c1, mpcore_cp15_c0_c1, 8 * sizeof(uint32_t)); | |
22478e79 | 86 | memcpy(env->cp15.c0_c2, mpcore_cp15_c0_c2, 8 * sizeof(uint32_t)); |
9ee6e8bb PB |
87 | env->cp15.c0_cachetype = 0x1dd20d2; |
88 | break; | |
89 | case ARM_CPUID_CORTEXA8: | |
90 | set_feature(env, ARM_FEATURE_V6); | |
91 | set_feature(env, ARM_FEATURE_V6K); | |
92 | set_feature(env, ARM_FEATURE_V7); | |
93 | set_feature(env, ARM_FEATURE_AUXCR); | |
94 | set_feature(env, ARM_FEATURE_THUMB2); | |
95 | set_feature(env, ARM_FEATURE_VFP); | |
96 | set_feature(env, ARM_FEATURE_VFP3); | |
97 | set_feature(env, ARM_FEATURE_NEON); | |
fe1479c3 | 98 | set_feature(env, ARM_FEATURE_THUMB2EE); |
9ee6e8bb PB |
99 | env->vfp.xregs[ARM_VFP_FPSID] = 0x410330c0; |
100 | env->vfp.xregs[ARM_VFP_MVFR0] = 0x11110222; | |
101 | env->vfp.xregs[ARM_VFP_MVFR1] = 0x00011100; | |
102 | memcpy(env->cp15.c0_c1, cortexa8_cp15_c0_c1, 8 * sizeof(uint32_t)); | |
22478e79 | 103 | memcpy(env->cp15.c0_c2, cortexa8_cp15_c0_c2, 8 * sizeof(uint32_t)); |
a49ea279 PB |
104 | env->cp15.c0_cachetype = 0x82048004; |
105 | env->cp15.c0_clid = (1 << 27) | (2 << 24) | 3; | |
106 | env->cp15.c0_ccsid[0] = 0xe007e01a; /* 16k L1 dcache. */ | |
107 | env->cp15.c0_ccsid[1] = 0x2007e01a; /* 16k L1 icache. */ | |
108 | env->cp15.c0_ccsid[2] = 0xf0000000; /* No L2 icache. */ | |
9ee6e8bb | 109 | break; |
10055562 PB |
110 | case ARM_CPUID_CORTEXA9: |
111 | set_feature(env, ARM_FEATURE_V6); | |
112 | set_feature(env, ARM_FEATURE_V6K); | |
113 | set_feature(env, ARM_FEATURE_V7); | |
114 | set_feature(env, ARM_FEATURE_AUXCR); | |
115 | set_feature(env, ARM_FEATURE_THUMB2); | |
116 | set_feature(env, ARM_FEATURE_VFP); | |
117 | set_feature(env, ARM_FEATURE_VFP3); | |
118 | set_feature(env, ARM_FEATURE_VFP_FP16); | |
119 | set_feature(env, ARM_FEATURE_NEON); | |
120 | set_feature(env, ARM_FEATURE_THUMB2EE); | |
121 | env->vfp.xregs[ARM_VFP_FPSID] = 0x41034000; /* Guess */ | |
122 | env->vfp.xregs[ARM_VFP_MVFR0] = 0x11110222; | |
123 | env->vfp.xregs[ARM_VFP_MVFR1] = 0x01111111; | |
124 | memcpy(env->cp15.c0_c1, cortexa9_cp15_c0_c1, 8 * sizeof(uint32_t)); | |
125 | memcpy(env->cp15.c0_c2, cortexa9_cp15_c0_c2, 8 * sizeof(uint32_t)); | |
126 | env->cp15.c0_cachetype = 0x80038003; | |
127 | env->cp15.c0_clid = (1 << 27) | (1 << 24) | 3; | |
128 | env->cp15.c0_ccsid[0] = 0xe00fe015; /* 16k L1 dcache. */ | |
129 | env->cp15.c0_ccsid[1] = 0x200fe015; /* 16k L1 icache. */ | |
130 | break; | |
9ee6e8bb PB |
131 | case ARM_CPUID_CORTEXM3: |
132 | set_feature(env, ARM_FEATURE_V6); | |
133 | set_feature(env, ARM_FEATURE_THUMB2); | |
134 | set_feature(env, ARM_FEATURE_V7); | |
135 | set_feature(env, ARM_FEATURE_M); | |
136 | set_feature(env, ARM_FEATURE_DIV); | |
137 | break; | |
138 | case ARM_CPUID_ANY: /* For userspace emulation. */ | |
139 | set_feature(env, ARM_FEATURE_V6); | |
140 | set_feature(env, ARM_FEATURE_V6K); | |
141 | set_feature(env, ARM_FEATURE_V7); | |
142 | set_feature(env, ARM_FEATURE_THUMB2); | |
143 | set_feature(env, ARM_FEATURE_VFP); | |
144 | set_feature(env, ARM_FEATURE_VFP3); | |
60011498 | 145 | set_feature(env, ARM_FEATURE_VFP_FP16); |
9ee6e8bb | 146 | set_feature(env, ARM_FEATURE_NEON); |
fe1479c3 | 147 | set_feature(env, ARM_FEATURE_THUMB2EE); |
9ee6e8bb PB |
148 | set_feature(env, ARM_FEATURE_DIV); |
149 | break; | |
c3d2689d AZ |
150 | case ARM_CPUID_TI915T: |
151 | case ARM_CPUID_TI925T: | |
152 | set_feature(env, ARM_FEATURE_OMAPCP); | |
153 | env->cp15.c0_cpuid = ARM_CPUID_TI925T; /* Depends on wiring. */ | |
154 | env->cp15.c0_cachetype = 0x5109149; | |
155 | env->cp15.c1_sys = 0x00000070; | |
156 | env->cp15.c15_i_max = 0x000; | |
157 | env->cp15.c15_i_min = 0xff0; | |
158 | break; | |
c1713132 AZ |
159 | case ARM_CPUID_PXA250: |
160 | case ARM_CPUID_PXA255: | |
161 | case ARM_CPUID_PXA260: | |
162 | case ARM_CPUID_PXA261: | |
163 | case ARM_CPUID_PXA262: | |
164 | set_feature(env, ARM_FEATURE_XSCALE); | |
165 | /* JTAG_ID is ((id << 28) | 0x09265013) */ | |
166 | env->cp15.c0_cachetype = 0xd172172; | |
610c3c8a | 167 | env->cp15.c1_sys = 0x00000078; |
c1713132 AZ |
168 | break; |
169 | case ARM_CPUID_PXA270_A0: | |
170 | case ARM_CPUID_PXA270_A1: | |
171 | case ARM_CPUID_PXA270_B0: | |
172 | case ARM_CPUID_PXA270_B1: | |
173 | case ARM_CPUID_PXA270_C0: | |
174 | case ARM_CPUID_PXA270_C5: | |
175 | set_feature(env, ARM_FEATURE_XSCALE); | |
176 | /* JTAG_ID is ((id << 28) | 0x09265013) */ | |
18c9b560 AZ |
177 | set_feature(env, ARM_FEATURE_IWMMXT); |
178 | env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q'; | |
c1713132 | 179 | env->cp15.c0_cachetype = 0xd172172; |
610c3c8a | 180 | env->cp15.c1_sys = 0x00000078; |
f3d6b95e PB |
181 | break; |
182 | default: | |
183 | cpu_abort(env, "Bad CPU ID: %x\n", id); | |
184 | break; | |
185 | } | |
186 | } | |
187 | ||
40f137e1 PB |
188 | void cpu_reset(CPUARMState *env) |
189 | { | |
f3d6b95e | 190 | uint32_t id; |
eca1bdf4 AL |
191 | |
192 | if (qemu_loglevel_mask(CPU_LOG_RESET)) { | |
193 | qemu_log("CPU Reset (CPU %d)\n", env->cpu_index); | |
194 | log_cpu_state(env, 0); | |
195 | } | |
196 | ||
f3d6b95e PB |
197 | id = env->cp15.c0_cpuid; |
198 | memset(env, 0, offsetof(CPUARMState, breakpoints)); | |
199 | if (id) | |
200 | cpu_reset_model_id(env, id); | |
40f137e1 PB |
201 | #if defined (CONFIG_USER_ONLY) |
202 | env->uncached_cpsr = ARM_CPU_MODE_USR; | |
203 | env->vfp.xregs[ARM_VFP_FPEXC] = 1 << 30; | |
204 | #else | |
205 | /* SVC mode with interrupts disabled. */ | |
206 | env->uncached_cpsr = ARM_CPU_MODE_SVC | CPSR_A | CPSR_F | CPSR_I; | |
9ee6e8bb PB |
207 | /* On ARMv7-M the CPSR_I is the value of the PRIMASK register, and is |
208 | clear at reset. */ | |
209 | if (IS_M(env)) | |
210 | env->uncached_cpsr &= ~CPSR_I; | |
40f137e1 | 211 | env->vfp.xregs[ARM_VFP_FPEXC] = 0; |
b2fa1797 | 212 | env->cp15.c2_base_mask = 0xffffc000u; |
40f137e1 PB |
213 | #endif |
214 | env->regs[15] = 0; | |
f3d6b95e | 215 | tlb_flush(env, 1); |
40f137e1 PB |
216 | } |
217 | ||
56aebc89 PB |
218 | static int vfp_gdb_get_reg(CPUState *env, uint8_t *buf, int reg) |
219 | { | |
220 | int nregs; | |
221 | ||
222 | /* VFP data registers are always little-endian. */ | |
223 | nregs = arm_feature(env, ARM_FEATURE_VFP3) ? 32 : 16; | |
224 | if (reg < nregs) { | |
225 | stfq_le_p(buf, env->vfp.regs[reg]); | |
226 | return 8; | |
227 | } | |
228 | if (arm_feature(env, ARM_FEATURE_NEON)) { | |
229 | /* Aliases for Q regs. */ | |
230 | nregs += 16; | |
231 | if (reg < nregs) { | |
232 | stfq_le_p(buf, env->vfp.regs[(reg - 32) * 2]); | |
233 | stfq_le_p(buf + 8, env->vfp.regs[(reg - 32) * 2 + 1]); | |
234 | return 16; | |
235 | } | |
236 | } | |
237 | switch (reg - nregs) { | |
238 | case 0: stl_p(buf, env->vfp.xregs[ARM_VFP_FPSID]); return 4; | |
239 | case 1: stl_p(buf, env->vfp.xregs[ARM_VFP_FPSCR]); return 4; | |
240 | case 2: stl_p(buf, env->vfp.xregs[ARM_VFP_FPEXC]); return 4; | |
241 | } | |
242 | return 0; | |
243 | } | |
244 | ||
245 | static int vfp_gdb_set_reg(CPUState *env, uint8_t *buf, int reg) | |
246 | { | |
247 | int nregs; | |
248 | ||
249 | nregs = arm_feature(env, ARM_FEATURE_VFP3) ? 32 : 16; | |
250 | if (reg < nregs) { | |
251 | env->vfp.regs[reg] = ldfq_le_p(buf); | |
252 | return 8; | |
253 | } | |
254 | if (arm_feature(env, ARM_FEATURE_NEON)) { | |
255 | nregs += 16; | |
256 | if (reg < nregs) { | |
257 | env->vfp.regs[(reg - 32) * 2] = ldfq_le_p(buf); | |
258 | env->vfp.regs[(reg - 32) * 2 + 1] = ldfq_le_p(buf + 8); | |
259 | return 16; | |
260 | } | |
261 | } | |
262 | switch (reg - nregs) { | |
263 | case 0: env->vfp.xregs[ARM_VFP_FPSID] = ldl_p(buf); return 4; | |
264 | case 1: env->vfp.xregs[ARM_VFP_FPSCR] = ldl_p(buf); return 4; | |
71b3c3de | 265 | case 2: env->vfp.xregs[ARM_VFP_FPEXC] = ldl_p(buf) & (1 << 30); return 4; |
56aebc89 PB |
266 | } |
267 | return 0; | |
268 | } | |
269 | ||
aaed909a | 270 | CPUARMState *cpu_arm_init(const char *cpu_model) |
40f137e1 PB |
271 | { |
272 | CPUARMState *env; | |
aaed909a | 273 | uint32_t id; |
b26eefb6 | 274 | static int inited = 0; |
40f137e1 | 275 | |
aaed909a FB |
276 | id = cpu_arm_find_by_name(cpu_model); |
277 | if (id == 0) | |
278 | return NULL; | |
40f137e1 | 279 | env = qemu_mallocz(sizeof(CPUARMState)); |
40f137e1 | 280 | cpu_exec_init(env); |
b26eefb6 PB |
281 | if (!inited) { |
282 | inited = 1; | |
283 | arm_translate_init(); | |
284 | } | |
285 | ||
01ba9816 | 286 | env->cpu_model_str = cpu_model; |
aaed909a | 287 | env->cp15.c0_cpuid = id; |
40f137e1 | 288 | cpu_reset(env); |
56aebc89 PB |
289 | if (arm_feature(env, ARM_FEATURE_NEON)) { |
290 | gdb_register_coprocessor(env, vfp_gdb_get_reg, vfp_gdb_set_reg, | |
291 | 51, "arm-neon.xml", 0); | |
292 | } else if (arm_feature(env, ARM_FEATURE_VFP3)) { | |
293 | gdb_register_coprocessor(env, vfp_gdb_get_reg, vfp_gdb_set_reg, | |
294 | 35, "arm-vfp3.xml", 0); | |
295 | } else if (arm_feature(env, ARM_FEATURE_VFP)) { | |
296 | gdb_register_coprocessor(env, vfp_gdb_get_reg, vfp_gdb_set_reg, | |
297 | 19, "arm-vfp.xml", 0); | |
298 | } | |
0bf46a40 | 299 | qemu_init_vcpu(env); |
40f137e1 PB |
300 | return env; |
301 | } | |
302 | ||
3371d272 PB |
303 | struct arm_cpu_t { |
304 | uint32_t id; | |
305 | const char *name; | |
306 | }; | |
307 | ||
308 | static const struct arm_cpu_t arm_cpu_names[] = { | |
309 | { ARM_CPUID_ARM926, "arm926"}, | |
ce819861 | 310 | { ARM_CPUID_ARM946, "arm946"}, |
3371d272 | 311 | { ARM_CPUID_ARM1026, "arm1026"}, |
9ee6e8bb | 312 | { ARM_CPUID_ARM1136, "arm1136"}, |
827df9f3 | 313 | { ARM_CPUID_ARM1136_R2, "arm1136-r2"}, |
9ee6e8bb PB |
314 | { ARM_CPUID_ARM11MPCORE, "arm11mpcore"}, |
315 | { ARM_CPUID_CORTEXM3, "cortex-m3"}, | |
316 | { ARM_CPUID_CORTEXA8, "cortex-a8"}, | |
10055562 | 317 | { ARM_CPUID_CORTEXA9, "cortex-a9"}, |
c3d2689d | 318 | { ARM_CPUID_TI925T, "ti925t" }, |
c1713132 AZ |
319 | { ARM_CPUID_PXA250, "pxa250" }, |
320 | { ARM_CPUID_PXA255, "pxa255" }, | |
321 | { ARM_CPUID_PXA260, "pxa260" }, | |
322 | { ARM_CPUID_PXA261, "pxa261" }, | |
323 | { ARM_CPUID_PXA262, "pxa262" }, | |
324 | { ARM_CPUID_PXA270, "pxa270" }, | |
325 | { ARM_CPUID_PXA270_A0, "pxa270-a0" }, | |
326 | { ARM_CPUID_PXA270_A1, "pxa270-a1" }, | |
327 | { ARM_CPUID_PXA270_B0, "pxa270-b0" }, | |
328 | { ARM_CPUID_PXA270_B1, "pxa270-b1" }, | |
329 | { ARM_CPUID_PXA270_C0, "pxa270-c0" }, | |
330 | { ARM_CPUID_PXA270_C5, "pxa270-c5" }, | |
9ee6e8bb | 331 | { ARM_CPUID_ANY, "any"}, |
3371d272 PB |
332 | { 0, NULL} |
333 | }; | |
334 | ||
c732abe2 | 335 | void arm_cpu_list(FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...)) |
5adb4839 PB |
336 | { |
337 | int i; | |
338 | ||
c732abe2 | 339 | (*cpu_fprintf)(f, "Available CPUs:\n"); |
5adb4839 | 340 | for (i = 0; arm_cpu_names[i].name; i++) { |
c732abe2 | 341 | (*cpu_fprintf)(f, " %s\n", arm_cpu_names[i].name); |
5adb4839 PB |
342 | } |
343 | } | |
344 | ||
aaed909a FB |
345 | /* return 0 if not found */ |
346 | static uint32_t cpu_arm_find_by_name(const char *name) | |
40f137e1 | 347 | { |
3371d272 PB |
348 | int i; |
349 | uint32_t id; | |
350 | ||
351 | id = 0; | |
3371d272 PB |
352 | for (i = 0; arm_cpu_names[i].name; i++) { |
353 | if (strcmp(name, arm_cpu_names[i].name) == 0) { | |
354 | id = arm_cpu_names[i].id; | |
355 | break; | |
356 | } | |
357 | } | |
aaed909a | 358 | return id; |
40f137e1 PB |
359 | } |
360 | ||
361 | void cpu_arm_close(CPUARMState *env) | |
362 | { | |
363 | free(env); | |
364 | } | |
365 | ||
2f4a40e5 AZ |
366 | uint32_t cpsr_read(CPUARMState *env) |
367 | { | |
368 | int ZF; | |
6fbe23d5 PB |
369 | ZF = (env->ZF == 0); |
370 | return env->uncached_cpsr | (env->NF & 0x80000000) | (ZF << 30) | | |
2f4a40e5 AZ |
371 | (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27) |
372 | | (env->thumb << 5) | ((env->condexec_bits & 3) << 25) | |
373 | | ((env->condexec_bits & 0xfc) << 8) | |
374 | | (env->GE << 16); | |
375 | } | |
376 | ||
377 | void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask) | |
378 | { | |
2f4a40e5 | 379 | if (mask & CPSR_NZCV) { |
6fbe23d5 PB |
380 | env->ZF = (~val) & CPSR_Z; |
381 | env->NF = val; | |
2f4a40e5 AZ |
382 | env->CF = (val >> 29) & 1; |
383 | env->VF = (val << 3) & 0x80000000; | |
384 | } | |
385 | if (mask & CPSR_Q) | |
386 | env->QF = ((val & CPSR_Q) != 0); | |
387 | if (mask & CPSR_T) | |
388 | env->thumb = ((val & CPSR_T) != 0); | |
389 | if (mask & CPSR_IT_0_1) { | |
390 | env->condexec_bits &= ~3; | |
391 | env->condexec_bits |= (val >> 25) & 3; | |
392 | } | |
393 | if (mask & CPSR_IT_2_7) { | |
394 | env->condexec_bits &= 3; | |
395 | env->condexec_bits |= (val >> 8) & 0xfc; | |
396 | } | |
397 | if (mask & CPSR_GE) { | |
398 | env->GE = (val >> 16) & 0xf; | |
399 | } | |
400 | ||
401 | if ((env->uncached_cpsr ^ val) & mask & CPSR_M) { | |
402 | switch_mode(env, val & CPSR_M); | |
403 | } | |
404 | mask &= ~CACHED_CPSR_BITS; | |
405 | env->uncached_cpsr = (env->uncached_cpsr & ~mask) | (val & mask); | |
406 | } | |
407 | ||
b26eefb6 PB |
408 | /* Sign/zero extend */ |
409 | uint32_t HELPER(sxtb16)(uint32_t x) | |
410 | { | |
411 | uint32_t res; | |
412 | res = (uint16_t)(int8_t)x; | |
413 | res |= (uint32_t)(int8_t)(x >> 16) << 16; | |
414 | return res; | |
415 | } | |
416 | ||
417 | uint32_t HELPER(uxtb16)(uint32_t x) | |
418 | { | |
419 | uint32_t res; | |
420 | res = (uint16_t)(uint8_t)x; | |
421 | res |= (uint32_t)(uint8_t)(x >> 16) << 16; | |
422 | return res; | |
423 | } | |
424 | ||
f51bbbfe PB |
425 | uint32_t HELPER(clz)(uint32_t x) |
426 | { | |
7bbcb0af | 427 | return clz32(x); |
f51bbbfe PB |
428 | } |
429 | ||
3670669c PB |
430 | int32_t HELPER(sdiv)(int32_t num, int32_t den) |
431 | { | |
432 | if (den == 0) | |
433 | return 0; | |
686eeb93 AJ |
434 | if (num == INT_MIN && den == -1) |
435 | return INT_MIN; | |
3670669c PB |
436 | return num / den; |
437 | } | |
438 | ||
439 | uint32_t HELPER(udiv)(uint32_t num, uint32_t den) | |
440 | { | |
441 | if (den == 0) | |
442 | return 0; | |
443 | return num / den; | |
444 | } | |
445 | ||
446 | uint32_t HELPER(rbit)(uint32_t x) | |
447 | { | |
448 | x = ((x & 0xff000000) >> 24) | |
449 | | ((x & 0x00ff0000) >> 8) | |
450 | | ((x & 0x0000ff00) << 8) | |
451 | | ((x & 0x000000ff) << 24); | |
452 | x = ((x & 0xf0f0f0f0) >> 4) | |
453 | | ((x & 0x0f0f0f0f) << 4); | |
454 | x = ((x & 0x88888888) >> 3) | |
455 | | ((x & 0x44444444) >> 1) | |
456 | | ((x & 0x22222222) << 1) | |
457 | | ((x & 0x11111111) << 3); | |
458 | return x; | |
459 | } | |
460 | ||
ad69471c PB |
461 | uint32_t HELPER(abs)(uint32_t x) |
462 | { | |
463 | return ((int32_t)x < 0) ? -x : x; | |
464 | } | |
465 | ||
5fafdf24 | 466 | #if defined(CONFIG_USER_ONLY) |
b5ff1b31 FB |
467 | |
468 | void do_interrupt (CPUState *env) | |
469 | { | |
470 | env->exception_index = -1; | |
471 | } | |
472 | ||
473 | int cpu_arm_handle_mmu_fault (CPUState *env, target_ulong address, int rw, | |
6ebbf390 | 474 | int mmu_idx, int is_softmmu) |
b5ff1b31 FB |
475 | { |
476 | if (rw == 2) { | |
477 | env->exception_index = EXCP_PREFETCH_ABORT; | |
478 | env->cp15.c6_insn = address; | |
479 | } else { | |
480 | env->exception_index = EXCP_DATA_ABORT; | |
481 | env->cp15.c6_data = address; | |
482 | } | |
483 | return 1; | |
484 | } | |
485 | ||
b5ff1b31 | 486 | /* These should probably raise undefined insn exceptions. */ |
8984bd2e | 487 | void HELPER(set_cp)(CPUState *env, uint32_t insn, uint32_t val) |
c1713132 AZ |
488 | { |
489 | int op1 = (insn >> 8) & 0xf; | |
490 | cpu_abort(env, "cp%i insn %08x\n", op1, insn); | |
491 | return; | |
492 | } | |
493 | ||
8984bd2e | 494 | uint32_t HELPER(get_cp)(CPUState *env, uint32_t insn) |
c1713132 AZ |
495 | { |
496 | int op1 = (insn >> 8) & 0xf; | |
497 | cpu_abort(env, "cp%i insn %08x\n", op1, insn); | |
498 | return 0; | |
499 | } | |
500 | ||
8984bd2e | 501 | void HELPER(set_cp15)(CPUState *env, uint32_t insn, uint32_t val) |
b5ff1b31 FB |
502 | { |
503 | cpu_abort(env, "cp15 insn %08x\n", insn); | |
504 | } | |
505 | ||
8984bd2e | 506 | uint32_t HELPER(get_cp15)(CPUState *env, uint32_t insn) |
b5ff1b31 FB |
507 | { |
508 | cpu_abort(env, "cp15 insn %08x\n", insn); | |
b5ff1b31 FB |
509 | } |
510 | ||
9ee6e8bb | 511 | /* These should probably raise undefined insn exceptions. */ |
8984bd2e | 512 | void HELPER(v7m_msr)(CPUState *env, uint32_t reg, uint32_t val) |
9ee6e8bb PB |
513 | { |
514 | cpu_abort(env, "v7m_mrs %d\n", reg); | |
515 | } | |
516 | ||
8984bd2e | 517 | uint32_t HELPER(v7m_mrs)(CPUState *env, uint32_t reg) |
9ee6e8bb PB |
518 | { |
519 | cpu_abort(env, "v7m_mrs %d\n", reg); | |
520 | return 0; | |
521 | } | |
522 | ||
b5ff1b31 FB |
523 | void switch_mode(CPUState *env, int mode) |
524 | { | |
525 | if (mode != ARM_CPU_MODE_USR) | |
526 | cpu_abort(env, "Tried to switch out of user mode\n"); | |
527 | } | |
528 | ||
b0109805 | 529 | void HELPER(set_r13_banked)(CPUState *env, uint32_t mode, uint32_t val) |
9ee6e8bb PB |
530 | { |
531 | cpu_abort(env, "banked r13 write\n"); | |
532 | } | |
533 | ||
b0109805 | 534 | uint32_t HELPER(get_r13_banked)(CPUState *env, uint32_t mode) |
9ee6e8bb PB |
535 | { |
536 | cpu_abort(env, "banked r13 read\n"); | |
537 | return 0; | |
538 | } | |
539 | ||
b5ff1b31 FB |
540 | #else |
541 | ||
8e71621f PB |
542 | extern int semihosting_enabled; |
543 | ||
b5ff1b31 FB |
544 | /* Map CPU modes onto saved register banks. */ |
545 | static inline int bank_number (int mode) | |
546 | { | |
547 | switch (mode) { | |
548 | case ARM_CPU_MODE_USR: | |
549 | case ARM_CPU_MODE_SYS: | |
550 | return 0; | |
551 | case ARM_CPU_MODE_SVC: | |
552 | return 1; | |
553 | case ARM_CPU_MODE_ABT: | |
554 | return 2; | |
555 | case ARM_CPU_MODE_UND: | |
556 | return 3; | |
557 | case ARM_CPU_MODE_IRQ: | |
558 | return 4; | |
559 | case ARM_CPU_MODE_FIQ: | |
560 | return 5; | |
561 | } | |
562 | cpu_abort(cpu_single_env, "Bad mode %x\n", mode); | |
563 | return -1; | |
564 | } | |
565 | ||
566 | void switch_mode(CPUState *env, int mode) | |
567 | { | |
568 | int old_mode; | |
569 | int i; | |
570 | ||
571 | old_mode = env->uncached_cpsr & CPSR_M; | |
572 | if (mode == old_mode) | |
573 | return; | |
574 | ||
575 | if (old_mode == ARM_CPU_MODE_FIQ) { | |
576 | memcpy (env->fiq_regs, env->regs + 8, 5 * sizeof(uint32_t)); | |
8637c67f | 577 | memcpy (env->regs + 8, env->usr_regs, 5 * sizeof(uint32_t)); |
b5ff1b31 FB |
578 | } else if (mode == ARM_CPU_MODE_FIQ) { |
579 | memcpy (env->usr_regs, env->regs + 8, 5 * sizeof(uint32_t)); | |
8637c67f | 580 | memcpy (env->regs + 8, env->fiq_regs, 5 * sizeof(uint32_t)); |
b5ff1b31 FB |
581 | } |
582 | ||
583 | i = bank_number(old_mode); | |
584 | env->banked_r13[i] = env->regs[13]; | |
585 | env->banked_r14[i] = env->regs[14]; | |
586 | env->banked_spsr[i] = env->spsr; | |
587 | ||
588 | i = bank_number(mode); | |
589 | env->regs[13] = env->banked_r13[i]; | |
590 | env->regs[14] = env->banked_r14[i]; | |
591 | env->spsr = env->banked_spsr[i]; | |
592 | } | |
593 | ||
9ee6e8bb PB |
594 | static void v7m_push(CPUARMState *env, uint32_t val) |
595 | { | |
596 | env->regs[13] -= 4; | |
597 | stl_phys(env->regs[13], val); | |
598 | } | |
599 | ||
600 | static uint32_t v7m_pop(CPUARMState *env) | |
601 | { | |
602 | uint32_t val; | |
603 | val = ldl_phys(env->regs[13]); | |
604 | env->regs[13] += 4; | |
605 | return val; | |
606 | } | |
607 | ||
608 | /* Switch to V7M main or process stack pointer. */ | |
609 | static void switch_v7m_sp(CPUARMState *env, int process) | |
610 | { | |
611 | uint32_t tmp; | |
612 | if (env->v7m.current_sp != process) { | |
613 | tmp = env->v7m.other_sp; | |
614 | env->v7m.other_sp = env->regs[13]; | |
615 | env->regs[13] = tmp; | |
616 | env->v7m.current_sp = process; | |
617 | } | |
618 | } | |
619 | ||
620 | static void do_v7m_exception_exit(CPUARMState *env) | |
621 | { | |
622 | uint32_t type; | |
623 | uint32_t xpsr; | |
624 | ||
625 | type = env->regs[15]; | |
626 | if (env->v7m.exception != 0) | |
627 | armv7m_nvic_complete_irq(env->v7m.nvic, env->v7m.exception); | |
628 | ||
629 | /* Switch to the target stack. */ | |
630 | switch_v7m_sp(env, (type & 4) != 0); | |
631 | /* Pop registers. */ | |
632 | env->regs[0] = v7m_pop(env); | |
633 | env->regs[1] = v7m_pop(env); | |
634 | env->regs[2] = v7m_pop(env); | |
635 | env->regs[3] = v7m_pop(env); | |
636 | env->regs[12] = v7m_pop(env); | |
637 | env->regs[14] = v7m_pop(env); | |
638 | env->regs[15] = v7m_pop(env); | |
639 | xpsr = v7m_pop(env); | |
640 | xpsr_write(env, xpsr, 0xfffffdff); | |
641 | /* Undo stack alignment. */ | |
642 | if (xpsr & 0x200) | |
643 | env->regs[13] |= 4; | |
644 | /* ??? The exception return type specifies Thread/Handler mode. However | |
645 | this is also implied by the xPSR value. Not sure what to do | |
646 | if there is a mismatch. */ | |
647 | /* ??? Likewise for mismatches between the CONTROL register and the stack | |
648 | pointer. */ | |
649 | } | |
650 | ||
2b3ea315 | 651 | static void do_interrupt_v7m(CPUARMState *env) |
9ee6e8bb PB |
652 | { |
653 | uint32_t xpsr = xpsr_read(env); | |
654 | uint32_t lr; | |
655 | uint32_t addr; | |
656 | ||
657 | lr = 0xfffffff1; | |
658 | if (env->v7m.current_sp) | |
659 | lr |= 4; | |
660 | if (env->v7m.exception == 0) | |
661 | lr |= 8; | |
662 | ||
663 | /* For exceptions we just mark as pending on the NVIC, and let that | |
664 | handle it. */ | |
665 | /* TODO: Need to escalate if the current priority is higher than the | |
666 | one we're raising. */ | |
667 | switch (env->exception_index) { | |
668 | case EXCP_UDEF: | |
669 | armv7m_nvic_set_pending(env->v7m.nvic, ARMV7M_EXCP_USAGE); | |
670 | return; | |
671 | case EXCP_SWI: | |
672 | env->regs[15] += 2; | |
673 | armv7m_nvic_set_pending(env->v7m.nvic, ARMV7M_EXCP_SVC); | |
674 | return; | |
675 | case EXCP_PREFETCH_ABORT: | |
676 | case EXCP_DATA_ABORT: | |
677 | armv7m_nvic_set_pending(env->v7m.nvic, ARMV7M_EXCP_MEM); | |
678 | return; | |
679 | case EXCP_BKPT: | |
2ad207d4 PB |
680 | if (semihosting_enabled) { |
681 | int nr; | |
682 | nr = lduw_code(env->regs[15]) & 0xff; | |
683 | if (nr == 0xab) { | |
684 | env->regs[15] += 2; | |
685 | env->regs[0] = do_arm_semihosting(env); | |
686 | return; | |
687 | } | |
688 | } | |
9ee6e8bb PB |
689 | armv7m_nvic_set_pending(env->v7m.nvic, ARMV7M_EXCP_DEBUG); |
690 | return; | |
691 | case EXCP_IRQ: | |
692 | env->v7m.exception = armv7m_nvic_acknowledge_irq(env->v7m.nvic); | |
693 | break; | |
694 | case EXCP_EXCEPTION_EXIT: | |
695 | do_v7m_exception_exit(env); | |
696 | return; | |
697 | default: | |
698 | cpu_abort(env, "Unhandled exception 0x%x\n", env->exception_index); | |
699 | return; /* Never happens. Keep compiler happy. */ | |
700 | } | |
701 | ||
702 | /* Align stack pointer. */ | |
703 | /* ??? Should only do this if Configuration Control Register | |
704 | STACKALIGN bit is set. */ | |
705 | if (env->regs[13] & 4) { | |
ab19b0ec | 706 | env->regs[13] -= 4; |
9ee6e8bb PB |
707 | xpsr |= 0x200; |
708 | } | |
6c95676b | 709 | /* Switch to the handler mode. */ |
9ee6e8bb PB |
710 | v7m_push(env, xpsr); |
711 | v7m_push(env, env->regs[15]); | |
712 | v7m_push(env, env->regs[14]); | |
713 | v7m_push(env, env->regs[12]); | |
714 | v7m_push(env, env->regs[3]); | |
715 | v7m_push(env, env->regs[2]); | |
716 | v7m_push(env, env->regs[1]); | |
717 | v7m_push(env, env->regs[0]); | |
718 | switch_v7m_sp(env, 0); | |
719 | env->uncached_cpsr &= ~CPSR_IT; | |
720 | env->regs[14] = lr; | |
721 | addr = ldl_phys(env->v7m.vecbase + env->v7m.exception * 4); | |
722 | env->regs[15] = addr & 0xfffffffe; | |
723 | env->thumb = addr & 1; | |
724 | } | |
725 | ||
b5ff1b31 FB |
726 | /* Handle a CPU exception. */ |
727 | void do_interrupt(CPUARMState *env) | |
728 | { | |
729 | uint32_t addr; | |
730 | uint32_t mask; | |
731 | int new_mode; | |
732 | uint32_t offset; | |
733 | ||
9ee6e8bb PB |
734 | if (IS_M(env)) { |
735 | do_interrupt_v7m(env); | |
736 | return; | |
737 | } | |
b5ff1b31 FB |
738 | /* TODO: Vectored interrupt controller. */ |
739 | switch (env->exception_index) { | |
740 | case EXCP_UDEF: | |
741 | new_mode = ARM_CPU_MODE_UND; | |
742 | addr = 0x04; | |
743 | mask = CPSR_I; | |
744 | if (env->thumb) | |
745 | offset = 2; | |
746 | else | |
747 | offset = 4; | |
748 | break; | |
749 | case EXCP_SWI: | |
8e71621f PB |
750 | if (semihosting_enabled) { |
751 | /* Check for semihosting interrupt. */ | |
752 | if (env->thumb) { | |
753 | mask = lduw_code(env->regs[15] - 2) & 0xff; | |
754 | } else { | |
755 | mask = ldl_code(env->regs[15] - 4) & 0xffffff; | |
756 | } | |
757 | /* Only intercept calls from privileged modes, to provide some | |
758 | semblance of security. */ | |
759 | if (((mask == 0x123456 && !env->thumb) | |
760 | || (mask == 0xab && env->thumb)) | |
761 | && (env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR) { | |
762 | env->regs[0] = do_arm_semihosting(env); | |
763 | return; | |
764 | } | |
765 | } | |
b5ff1b31 FB |
766 | new_mode = ARM_CPU_MODE_SVC; |
767 | addr = 0x08; | |
768 | mask = CPSR_I; | |
601d70b9 | 769 | /* The PC already points to the next instruction. */ |
b5ff1b31 FB |
770 | offset = 0; |
771 | break; | |
06c949e6 | 772 | case EXCP_BKPT: |
9ee6e8bb | 773 | /* See if this is a semihosting syscall. */ |
2ad207d4 | 774 | if (env->thumb && semihosting_enabled) { |
9ee6e8bb PB |
775 | mask = lduw_code(env->regs[15]) & 0xff; |
776 | if (mask == 0xab | |
777 | && (env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR) { | |
778 | env->regs[15] += 2; | |
779 | env->regs[0] = do_arm_semihosting(env); | |
780 | return; | |
781 | } | |
782 | } | |
783 | /* Fall through to prefetch abort. */ | |
784 | case EXCP_PREFETCH_ABORT: | |
b5ff1b31 FB |
785 | new_mode = ARM_CPU_MODE_ABT; |
786 | addr = 0x0c; | |
787 | mask = CPSR_A | CPSR_I; | |
788 | offset = 4; | |
789 | break; | |
790 | case EXCP_DATA_ABORT: | |
791 | new_mode = ARM_CPU_MODE_ABT; | |
792 | addr = 0x10; | |
793 | mask = CPSR_A | CPSR_I; | |
794 | offset = 8; | |
795 | break; | |
796 | case EXCP_IRQ: | |
797 | new_mode = ARM_CPU_MODE_IRQ; | |
798 | addr = 0x18; | |
799 | /* Disable IRQ and imprecise data aborts. */ | |
800 | mask = CPSR_A | CPSR_I; | |
801 | offset = 4; | |
802 | break; | |
803 | case EXCP_FIQ: | |
804 | new_mode = ARM_CPU_MODE_FIQ; | |
805 | addr = 0x1c; | |
806 | /* Disable FIQ, IRQ and imprecise data aborts. */ | |
807 | mask = CPSR_A | CPSR_I | CPSR_F; | |
808 | offset = 4; | |
809 | break; | |
810 | default: | |
811 | cpu_abort(env, "Unhandled exception 0x%x\n", env->exception_index); | |
812 | return; /* Never happens. Keep compiler happy. */ | |
813 | } | |
814 | /* High vectors. */ | |
815 | if (env->cp15.c1_sys & (1 << 13)) { | |
816 | addr += 0xffff0000; | |
817 | } | |
818 | switch_mode (env, new_mode); | |
819 | env->spsr = cpsr_read(env); | |
9ee6e8bb PB |
820 | /* Clear IT bits. */ |
821 | env->condexec_bits = 0; | |
30a8cac1 | 822 | /* Switch to the new mode, and to the correct instruction set. */ |
6d7e6326 | 823 | env->uncached_cpsr = (env->uncached_cpsr & ~CPSR_M) | new_mode; |
b5ff1b31 | 824 | env->uncached_cpsr |= mask; |
30a8cac1 | 825 | env->thumb = (env->cp15.c1_sys & (1 << 30)) != 0; |
b5ff1b31 FB |
826 | env->regs[14] = env->regs[15] + offset; |
827 | env->regs[15] = addr; | |
828 | env->interrupt_request |= CPU_INTERRUPT_EXITTB; | |
829 | } | |
830 | ||
831 | /* Check section/page access permissions. | |
832 | Returns the page protection flags, or zero if the access is not | |
833 | permitted. */ | |
834 | static inline int check_ap(CPUState *env, int ap, int domain, int access_type, | |
835 | int is_user) | |
836 | { | |
9ee6e8bb PB |
837 | int prot_ro; |
838 | ||
b5ff1b31 FB |
839 | if (domain == 3) |
840 | return PAGE_READ | PAGE_WRITE; | |
841 | ||
9ee6e8bb PB |
842 | if (access_type == 1) |
843 | prot_ro = 0; | |
844 | else | |
845 | prot_ro = PAGE_READ; | |
846 | ||
b5ff1b31 FB |
847 | switch (ap) { |
848 | case 0: | |
78600320 | 849 | if (access_type == 1) |
b5ff1b31 FB |
850 | return 0; |
851 | switch ((env->cp15.c1_sys >> 8) & 3) { | |
852 | case 1: | |
853 | return is_user ? 0 : PAGE_READ; | |
854 | case 2: | |
855 | return PAGE_READ; | |
856 | default: | |
857 | return 0; | |
858 | } | |
859 | case 1: | |
860 | return is_user ? 0 : PAGE_READ | PAGE_WRITE; | |
861 | case 2: | |
862 | if (is_user) | |
9ee6e8bb | 863 | return prot_ro; |
b5ff1b31 FB |
864 | else |
865 | return PAGE_READ | PAGE_WRITE; | |
866 | case 3: | |
867 | return PAGE_READ | PAGE_WRITE; | |
d4934d18 | 868 | case 4: /* Reserved. */ |
9ee6e8bb PB |
869 | return 0; |
870 | case 5: | |
871 | return is_user ? 0 : prot_ro; | |
872 | case 6: | |
873 | return prot_ro; | |
d4934d18 PB |
874 | case 7: |
875 | if (!arm_feature (env, ARM_FEATURE_V7)) | |
876 | return 0; | |
877 | return prot_ro; | |
b5ff1b31 FB |
878 | default: |
879 | abort(); | |
880 | } | |
881 | } | |
882 | ||
b2fa1797 PB |
883 | static uint32_t get_level1_table_address(CPUState *env, uint32_t address) |
884 | { | |
885 | uint32_t table; | |
886 | ||
887 | if (address & env->cp15.c2_mask) | |
888 | table = env->cp15.c2_base1 & 0xffffc000; | |
889 | else | |
890 | table = env->cp15.c2_base0 & env->cp15.c2_base_mask; | |
891 | ||
892 | table |= (address >> 18) & 0x3ffc; | |
893 | return table; | |
894 | } | |
895 | ||
9ee6e8bb | 896 | static int get_phys_addr_v5(CPUState *env, uint32_t address, int access_type, |
d4c430a8 PB |
897 | int is_user, uint32_t *phys_ptr, int *prot, |
898 | target_ulong *page_size) | |
b5ff1b31 FB |
899 | { |
900 | int code; | |
901 | uint32_t table; | |
902 | uint32_t desc; | |
903 | int type; | |
904 | int ap; | |
905 | int domain; | |
906 | uint32_t phys_addr; | |
907 | ||
9ee6e8bb PB |
908 | /* Pagetable walk. */ |
909 | /* Lookup l1 descriptor. */ | |
b2fa1797 | 910 | table = get_level1_table_address(env, address); |
9ee6e8bb PB |
911 | desc = ldl_phys(table); |
912 | type = (desc & 3); | |
913 | domain = (env->cp15.c3 >> ((desc >> 4) & 0x1e)) & 3; | |
914 | if (type == 0) { | |
601d70b9 | 915 | /* Section translation fault. */ |
9ee6e8bb PB |
916 | code = 5; |
917 | goto do_fault; | |
918 | } | |
919 | if (domain == 0 || domain == 2) { | |
920 | if (type == 2) | |
921 | code = 9; /* Section domain fault. */ | |
922 | else | |
923 | code = 11; /* Page domain fault. */ | |
924 | goto do_fault; | |
925 | } | |
926 | if (type == 2) { | |
927 | /* 1Mb section. */ | |
928 | phys_addr = (desc & 0xfff00000) | (address & 0x000fffff); | |
929 | ap = (desc >> 10) & 3; | |
930 | code = 13; | |
d4c430a8 | 931 | *page_size = 1024 * 1024; |
9ee6e8bb PB |
932 | } else { |
933 | /* Lookup l2 entry. */ | |
934 | if (type == 1) { | |
935 | /* Coarse pagetable. */ | |
936 | table = (desc & 0xfffffc00) | ((address >> 10) & 0x3fc); | |
937 | } else { | |
938 | /* Fine pagetable. */ | |
939 | table = (desc & 0xfffff000) | ((address >> 8) & 0xffc); | |
940 | } | |
941 | desc = ldl_phys(table); | |
942 | switch (desc & 3) { | |
943 | case 0: /* Page translation fault. */ | |
944 | code = 7; | |
945 | goto do_fault; | |
946 | case 1: /* 64k page. */ | |
947 | phys_addr = (desc & 0xffff0000) | (address & 0xffff); | |
948 | ap = (desc >> (4 + ((address >> 13) & 6))) & 3; | |
d4c430a8 | 949 | *page_size = 0x10000; |
ce819861 | 950 | break; |
9ee6e8bb PB |
951 | case 2: /* 4k page. */ |
952 | phys_addr = (desc & 0xfffff000) | (address & 0xfff); | |
953 | ap = (desc >> (4 + ((address >> 13) & 6))) & 3; | |
d4c430a8 | 954 | *page_size = 0x1000; |
ce819861 | 955 | break; |
9ee6e8bb PB |
956 | case 3: /* 1k page. */ |
957 | if (type == 1) { | |
958 | if (arm_feature(env, ARM_FEATURE_XSCALE)) { | |
959 | phys_addr = (desc & 0xfffff000) | (address & 0xfff); | |
960 | } else { | |
961 | /* Page translation fault. */ | |
962 | code = 7; | |
963 | goto do_fault; | |
964 | } | |
965 | } else { | |
966 | phys_addr = (desc & 0xfffffc00) | (address & 0x3ff); | |
967 | } | |
968 | ap = (desc >> 4) & 3; | |
d4c430a8 | 969 | *page_size = 0x400; |
ce819861 PB |
970 | break; |
971 | default: | |
9ee6e8bb PB |
972 | /* Never happens, but compiler isn't smart enough to tell. */ |
973 | abort(); | |
ce819861 | 974 | } |
9ee6e8bb PB |
975 | code = 15; |
976 | } | |
977 | *prot = check_ap(env, ap, domain, access_type, is_user); | |
978 | if (!*prot) { | |
979 | /* Access permission fault. */ | |
980 | goto do_fault; | |
981 | } | |
982 | *phys_ptr = phys_addr; | |
983 | return 0; | |
984 | do_fault: | |
985 | return code | (domain << 4); | |
986 | } | |
987 | ||
988 | static int get_phys_addr_v6(CPUState *env, uint32_t address, int access_type, | |
d4c430a8 PB |
989 | int is_user, uint32_t *phys_ptr, int *prot, |
990 | target_ulong *page_size) | |
9ee6e8bb PB |
991 | { |
992 | int code; | |
993 | uint32_t table; | |
994 | uint32_t desc; | |
995 | uint32_t xn; | |
996 | int type; | |
997 | int ap; | |
998 | int domain; | |
999 | uint32_t phys_addr; | |
1000 | ||
1001 | /* Pagetable walk. */ | |
1002 | /* Lookup l1 descriptor. */ | |
b2fa1797 | 1003 | table = get_level1_table_address(env, address); |
9ee6e8bb PB |
1004 | desc = ldl_phys(table); |
1005 | type = (desc & 3); | |
1006 | if (type == 0) { | |
601d70b9 | 1007 | /* Section translation fault. */ |
9ee6e8bb PB |
1008 | code = 5; |
1009 | domain = 0; | |
1010 | goto do_fault; | |
1011 | } else if (type == 2 && (desc & (1 << 18))) { | |
1012 | /* Supersection. */ | |
1013 | domain = 0; | |
b5ff1b31 | 1014 | } else { |
9ee6e8bb PB |
1015 | /* Section or page. */ |
1016 | domain = (desc >> 4) & 0x1e; | |
1017 | } | |
1018 | domain = (env->cp15.c3 >> domain) & 3; | |
1019 | if (domain == 0 || domain == 2) { | |
1020 | if (type == 2) | |
1021 | code = 9; /* Section domain fault. */ | |
1022 | else | |
1023 | code = 11; /* Page domain fault. */ | |
1024 | goto do_fault; | |
1025 | } | |
1026 | if (type == 2) { | |
1027 | if (desc & (1 << 18)) { | |
1028 | /* Supersection. */ | |
1029 | phys_addr = (desc & 0xff000000) | (address & 0x00ffffff); | |
d4c430a8 | 1030 | *page_size = 0x1000000; |
b5ff1b31 | 1031 | } else { |
9ee6e8bb PB |
1032 | /* Section. */ |
1033 | phys_addr = (desc & 0xfff00000) | (address & 0x000fffff); | |
d4c430a8 | 1034 | *page_size = 0x100000; |
b5ff1b31 | 1035 | } |
9ee6e8bb PB |
1036 | ap = ((desc >> 10) & 3) | ((desc >> 13) & 4); |
1037 | xn = desc & (1 << 4); | |
1038 | code = 13; | |
1039 | } else { | |
1040 | /* Lookup l2 entry. */ | |
1041 | table = (desc & 0xfffffc00) | ((address >> 10) & 0x3fc); | |
1042 | desc = ldl_phys(table); | |
1043 | ap = ((desc >> 4) & 3) | ((desc >> 7) & 4); | |
1044 | switch (desc & 3) { | |
1045 | case 0: /* Page translation fault. */ | |
1046 | code = 7; | |
b5ff1b31 | 1047 | goto do_fault; |
9ee6e8bb PB |
1048 | case 1: /* 64k page. */ |
1049 | phys_addr = (desc & 0xffff0000) | (address & 0xffff); | |
1050 | xn = desc & (1 << 15); | |
d4c430a8 | 1051 | *page_size = 0x10000; |
9ee6e8bb PB |
1052 | break; |
1053 | case 2: case 3: /* 4k page. */ | |
1054 | phys_addr = (desc & 0xfffff000) | (address & 0xfff); | |
1055 | xn = desc & 1; | |
d4c430a8 | 1056 | *page_size = 0x1000; |
9ee6e8bb PB |
1057 | break; |
1058 | default: | |
1059 | /* Never happens, but compiler isn't smart enough to tell. */ | |
1060 | abort(); | |
b5ff1b31 | 1061 | } |
9ee6e8bb PB |
1062 | code = 15; |
1063 | } | |
1064 | if (xn && access_type == 2) | |
1065 | goto do_fault; | |
1066 | ||
d4934d18 PB |
1067 | /* The simplified model uses AP[0] as an access control bit. */ |
1068 | if ((env->cp15.c1_sys & (1 << 29)) && (ap & 1) == 0) { | |
1069 | /* Access flag fault. */ | |
1070 | code = (code == 15) ? 6 : 3; | |
1071 | goto do_fault; | |
1072 | } | |
9ee6e8bb PB |
1073 | *prot = check_ap(env, ap, domain, access_type, is_user); |
1074 | if (!*prot) { | |
1075 | /* Access permission fault. */ | |
1076 | goto do_fault; | |
b5ff1b31 | 1077 | } |
9ee6e8bb | 1078 | *phys_ptr = phys_addr; |
b5ff1b31 FB |
1079 | return 0; |
1080 | do_fault: | |
1081 | return code | (domain << 4); | |
1082 | } | |
1083 | ||
9ee6e8bb PB |
1084 | static int get_phys_addr_mpu(CPUState *env, uint32_t address, int access_type, |
1085 | int is_user, uint32_t *phys_ptr, int *prot) | |
1086 | { | |
1087 | int n; | |
1088 | uint32_t mask; | |
1089 | uint32_t base; | |
1090 | ||
1091 | *phys_ptr = address; | |
1092 | for (n = 7; n >= 0; n--) { | |
1093 | base = env->cp15.c6_region[n]; | |
1094 | if ((base & 1) == 0) | |
1095 | continue; | |
1096 | mask = 1 << ((base >> 1) & 0x1f); | |
1097 | /* Keep this shift separate from the above to avoid an | |
1098 | (undefined) << 32. */ | |
1099 | mask = (mask << 1) - 1; | |
1100 | if (((base ^ address) & ~mask) == 0) | |
1101 | break; | |
1102 | } | |
1103 | if (n < 0) | |
1104 | return 2; | |
1105 | ||
1106 | if (access_type == 2) { | |
1107 | mask = env->cp15.c5_insn; | |
1108 | } else { | |
1109 | mask = env->cp15.c5_data; | |
1110 | } | |
1111 | mask = (mask >> (n * 4)) & 0xf; | |
1112 | switch (mask) { | |
1113 | case 0: | |
1114 | return 1; | |
1115 | case 1: | |
1116 | if (is_user) | |
1117 | return 1; | |
1118 | *prot = PAGE_READ | PAGE_WRITE; | |
1119 | break; | |
1120 | case 2: | |
1121 | *prot = PAGE_READ; | |
1122 | if (!is_user) | |
1123 | *prot |= PAGE_WRITE; | |
1124 | break; | |
1125 | case 3: | |
1126 | *prot = PAGE_READ | PAGE_WRITE; | |
1127 | break; | |
1128 | case 5: | |
1129 | if (is_user) | |
1130 | return 1; | |
1131 | *prot = PAGE_READ; | |
1132 | break; | |
1133 | case 6: | |
1134 | *prot = PAGE_READ; | |
1135 | break; | |
1136 | default: | |
1137 | /* Bad permission. */ | |
1138 | return 1; | |
1139 | } | |
1140 | return 0; | |
1141 | } | |
1142 | ||
1143 | static inline int get_phys_addr(CPUState *env, uint32_t address, | |
1144 | int access_type, int is_user, | |
d4c430a8 PB |
1145 | uint32_t *phys_ptr, int *prot, |
1146 | target_ulong *page_size) | |
9ee6e8bb PB |
1147 | { |
1148 | /* Fast Context Switch Extension. */ | |
1149 | if (address < 0x02000000) | |
1150 | address += env->cp15.c13_fcse; | |
1151 | ||
1152 | if ((env->cp15.c1_sys & 1) == 0) { | |
1153 | /* MMU/MPU disabled. */ | |
1154 | *phys_ptr = address; | |
1155 | *prot = PAGE_READ | PAGE_WRITE; | |
d4c430a8 | 1156 | *page_size = TARGET_PAGE_SIZE; |
9ee6e8bb PB |
1157 | return 0; |
1158 | } else if (arm_feature(env, ARM_FEATURE_MPU)) { | |
d4c430a8 | 1159 | *page_size = TARGET_PAGE_SIZE; |
9ee6e8bb PB |
1160 | return get_phys_addr_mpu(env, address, access_type, is_user, phys_ptr, |
1161 | prot); | |
1162 | } else if (env->cp15.c1_sys & (1 << 23)) { | |
1163 | return get_phys_addr_v6(env, address, access_type, is_user, phys_ptr, | |
d4c430a8 | 1164 | prot, page_size); |
9ee6e8bb PB |
1165 | } else { |
1166 | return get_phys_addr_v5(env, address, access_type, is_user, phys_ptr, | |
d4c430a8 | 1167 | prot, page_size); |
9ee6e8bb PB |
1168 | } |
1169 | } | |
1170 | ||
b5ff1b31 | 1171 | int cpu_arm_handle_mmu_fault (CPUState *env, target_ulong address, |
6ebbf390 | 1172 | int access_type, int mmu_idx, int is_softmmu) |
b5ff1b31 FB |
1173 | { |
1174 | uint32_t phys_addr; | |
d4c430a8 | 1175 | target_ulong page_size; |
b5ff1b31 | 1176 | int prot; |
6ebbf390 | 1177 | int ret, is_user; |
b5ff1b31 | 1178 | |
6ebbf390 | 1179 | is_user = mmu_idx == MMU_USER_IDX; |
d4c430a8 PB |
1180 | ret = get_phys_addr(env, address, access_type, is_user, &phys_addr, &prot, |
1181 | &page_size); | |
b5ff1b31 FB |
1182 | if (ret == 0) { |
1183 | /* Map a single [sub]page. */ | |
1184 | phys_addr &= ~(uint32_t)0x3ff; | |
1185 | address &= ~(uint32_t)0x3ff; | |
d4c430a8 PB |
1186 | tlb_set_page (env, address, phys_addr, prot | PAGE_EXEC, mmu_idx, |
1187 | page_size); | |
1188 | return 0; | |
b5ff1b31 FB |
1189 | } |
1190 | ||
1191 | if (access_type == 2) { | |
1192 | env->cp15.c5_insn = ret; | |
1193 | env->cp15.c6_insn = address; | |
1194 | env->exception_index = EXCP_PREFETCH_ABORT; | |
1195 | } else { | |
1196 | env->cp15.c5_data = ret; | |
9ee6e8bb PB |
1197 | if (access_type == 1 && arm_feature(env, ARM_FEATURE_V6)) |
1198 | env->cp15.c5_data |= (1 << 11); | |
b5ff1b31 FB |
1199 | env->cp15.c6_data = address; |
1200 | env->exception_index = EXCP_DATA_ABORT; | |
1201 | } | |
1202 | return 1; | |
1203 | } | |
1204 | ||
c227f099 | 1205 | target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr) |
b5ff1b31 FB |
1206 | { |
1207 | uint32_t phys_addr; | |
d4c430a8 | 1208 | target_ulong page_size; |
b5ff1b31 FB |
1209 | int prot; |
1210 | int ret; | |
1211 | ||
d4c430a8 | 1212 | ret = get_phys_addr(env, addr, 0, 0, &phys_addr, &prot, &page_size); |
b5ff1b31 FB |
1213 | |
1214 | if (ret != 0) | |
1215 | return -1; | |
1216 | ||
1217 | return phys_addr; | |
1218 | } | |
1219 | ||
8984bd2e | 1220 | void HELPER(set_cp)(CPUState *env, uint32_t insn, uint32_t val) |
c1713132 AZ |
1221 | { |
1222 | int cp_num = (insn >> 8) & 0xf; | |
1223 | int cp_info = (insn >> 5) & 7; | |
1224 | int src = (insn >> 16) & 0xf; | |
1225 | int operand = insn & 0xf; | |
1226 | ||
1227 | if (env->cp[cp_num].cp_write) | |
1228 | env->cp[cp_num].cp_write(env->cp[cp_num].opaque, | |
1229 | cp_info, src, operand, val); | |
1230 | } | |
1231 | ||
8984bd2e | 1232 | uint32_t HELPER(get_cp)(CPUState *env, uint32_t insn) |
c1713132 AZ |
1233 | { |
1234 | int cp_num = (insn >> 8) & 0xf; | |
1235 | int cp_info = (insn >> 5) & 7; | |
1236 | int dest = (insn >> 16) & 0xf; | |
1237 | int operand = insn & 0xf; | |
1238 | ||
1239 | if (env->cp[cp_num].cp_read) | |
1240 | return env->cp[cp_num].cp_read(env->cp[cp_num].opaque, | |
1241 | cp_info, dest, operand); | |
1242 | return 0; | |
1243 | } | |
1244 | ||
ce819861 PB |
1245 | /* Return basic MPU access permission bits. */ |
1246 | static uint32_t simple_mpu_ap_bits(uint32_t val) | |
1247 | { | |
1248 | uint32_t ret; | |
1249 | uint32_t mask; | |
1250 | int i; | |
1251 | ret = 0; | |
1252 | mask = 3; | |
1253 | for (i = 0; i < 16; i += 2) { | |
1254 | ret |= (val >> i) & mask; | |
1255 | mask <<= 2; | |
1256 | } | |
1257 | return ret; | |
1258 | } | |
1259 | ||
1260 | /* Pad basic MPU access permission bits to extended format. */ | |
1261 | static uint32_t extended_mpu_ap_bits(uint32_t val) | |
1262 | { | |
1263 | uint32_t ret; | |
1264 | uint32_t mask; | |
1265 | int i; | |
1266 | ret = 0; | |
1267 | mask = 3; | |
1268 | for (i = 0; i < 16; i += 2) { | |
1269 | ret |= (val & mask) << i; | |
1270 | mask <<= 2; | |
1271 | } | |
1272 | return ret; | |
1273 | } | |
1274 | ||
8984bd2e | 1275 | void HELPER(set_cp15)(CPUState *env, uint32_t insn, uint32_t val) |
b5ff1b31 | 1276 | { |
9ee6e8bb PB |
1277 | int op1; |
1278 | int op2; | |
1279 | int crm; | |
b5ff1b31 | 1280 | |
9ee6e8bb | 1281 | op1 = (insn >> 21) & 7; |
b5ff1b31 | 1282 | op2 = (insn >> 5) & 7; |
ce819861 | 1283 | crm = insn & 0xf; |
b5ff1b31 | 1284 | switch ((insn >> 16) & 0xf) { |
9ee6e8bb | 1285 | case 0: |
9ee6e8bb | 1286 | /* ID codes. */ |
610c3c8a AZ |
1287 | if (arm_feature(env, ARM_FEATURE_XSCALE)) |
1288 | break; | |
c3d2689d AZ |
1289 | if (arm_feature(env, ARM_FEATURE_OMAPCP)) |
1290 | break; | |
a49ea279 PB |
1291 | if (arm_feature(env, ARM_FEATURE_V7) |
1292 | && op1 == 2 && crm == 0 && op2 == 0) { | |
1293 | env->cp15.c0_cssel = val & 0xf; | |
1294 | break; | |
1295 | } | |
b5ff1b31 FB |
1296 | goto bad_reg; |
1297 | case 1: /* System configuration. */ | |
c3d2689d AZ |
1298 | if (arm_feature(env, ARM_FEATURE_OMAPCP)) |
1299 | op2 = 0; | |
b5ff1b31 FB |
1300 | switch (op2) { |
1301 | case 0: | |
ce819861 | 1302 | if (!arm_feature(env, ARM_FEATURE_XSCALE) || crm == 0) |
c1713132 | 1303 | env->cp15.c1_sys = val; |
b5ff1b31 FB |
1304 | /* ??? Lots of these bits are not implemented. */ |
1305 | /* This may enable/disable the MMU, so do a TLB flush. */ | |
1306 | tlb_flush(env, 1); | |
1307 | break; | |
9ee6e8bb | 1308 | case 1: /* Auxiliary cotrol register. */ |
610c3c8a AZ |
1309 | if (arm_feature(env, ARM_FEATURE_XSCALE)) { |
1310 | env->cp15.c1_xscaleauxcr = val; | |
c1713132 | 1311 | break; |
610c3c8a | 1312 | } |
9ee6e8bb PB |
1313 | /* Not implemented. */ |
1314 | break; | |
b5ff1b31 | 1315 | case 2: |
610c3c8a AZ |
1316 | if (arm_feature(env, ARM_FEATURE_XSCALE)) |
1317 | goto bad_reg; | |
4be27dbb PB |
1318 | if (env->cp15.c1_coproc != val) { |
1319 | env->cp15.c1_coproc = val; | |
1320 | /* ??? Is this safe when called from within a TB? */ | |
1321 | tb_flush(env); | |
1322 | } | |
c1713132 | 1323 | break; |
b5ff1b31 FB |
1324 | default: |
1325 | goto bad_reg; | |
1326 | } | |
1327 | break; | |
ce819861 PB |
1328 | case 2: /* MMU Page table control / MPU cache control. */ |
1329 | if (arm_feature(env, ARM_FEATURE_MPU)) { | |
1330 | switch (op2) { | |
1331 | case 0: | |
1332 | env->cp15.c2_data = val; | |
1333 | break; | |
1334 | case 1: | |
1335 | env->cp15.c2_insn = val; | |
1336 | break; | |
1337 | default: | |
1338 | goto bad_reg; | |
1339 | } | |
1340 | } else { | |
9ee6e8bb PB |
1341 | switch (op2) { |
1342 | case 0: | |
1343 | env->cp15.c2_base0 = val; | |
1344 | break; | |
1345 | case 1: | |
1346 | env->cp15.c2_base1 = val; | |
1347 | break; | |
1348 | case 2: | |
b2fa1797 PB |
1349 | val &= 7; |
1350 | env->cp15.c2_control = val; | |
9ee6e8bb | 1351 | env->cp15.c2_mask = ~(((uint32_t)0xffffffffu) >> val); |
b2fa1797 | 1352 | env->cp15.c2_base_mask = ~((uint32_t)0x3fffu >> val); |
9ee6e8bb PB |
1353 | break; |
1354 | default: | |
1355 | goto bad_reg; | |
1356 | } | |
ce819861 | 1357 | } |
b5ff1b31 | 1358 | break; |
ce819861 | 1359 | case 3: /* MMU Domain access control / MPU write buffer control. */ |
b5ff1b31 | 1360 | env->cp15.c3 = val; |
405ee3ad | 1361 | tlb_flush(env, 1); /* Flush TLB as domain not tracked in TLB */ |
b5ff1b31 FB |
1362 | break; |
1363 | case 4: /* Reserved. */ | |
1364 | goto bad_reg; | |
ce819861 | 1365 | case 5: /* MMU Fault status / MPU access permission. */ |
c3d2689d AZ |
1366 | if (arm_feature(env, ARM_FEATURE_OMAPCP)) |
1367 | op2 = 0; | |
b5ff1b31 FB |
1368 | switch (op2) { |
1369 | case 0: | |
ce819861 PB |
1370 | if (arm_feature(env, ARM_FEATURE_MPU)) |
1371 | val = extended_mpu_ap_bits(val); | |
b5ff1b31 FB |
1372 | env->cp15.c5_data = val; |
1373 | break; | |
1374 | case 1: | |
ce819861 PB |
1375 | if (arm_feature(env, ARM_FEATURE_MPU)) |
1376 | val = extended_mpu_ap_bits(val); | |
b5ff1b31 FB |
1377 | env->cp15.c5_insn = val; |
1378 | break; | |
ce819861 PB |
1379 | case 2: |
1380 | if (!arm_feature(env, ARM_FEATURE_MPU)) | |
1381 | goto bad_reg; | |
1382 | env->cp15.c5_data = val; | |
b5ff1b31 | 1383 | break; |
ce819861 PB |
1384 | case 3: |
1385 | if (!arm_feature(env, ARM_FEATURE_MPU)) | |
1386 | goto bad_reg; | |
1387 | env->cp15.c5_insn = val; | |
b5ff1b31 FB |
1388 | break; |
1389 | default: | |
1390 | goto bad_reg; | |
1391 | } | |
1392 | break; | |
ce819861 PB |
1393 | case 6: /* MMU Fault address / MPU base/size. */ |
1394 | if (arm_feature(env, ARM_FEATURE_MPU)) { | |
1395 | if (crm >= 8) | |
1396 | goto bad_reg; | |
1397 | env->cp15.c6_region[crm] = val; | |
1398 | } else { | |
c3d2689d AZ |
1399 | if (arm_feature(env, ARM_FEATURE_OMAPCP)) |
1400 | op2 = 0; | |
ce819861 PB |
1401 | switch (op2) { |
1402 | case 0: | |
1403 | env->cp15.c6_data = val; | |
1404 | break; | |
9ee6e8bb PB |
1405 | case 1: /* ??? This is WFAR on armv6 */ |
1406 | case 2: | |
ce819861 PB |
1407 | env->cp15.c6_insn = val; |
1408 | break; | |
1409 | default: | |
1410 | goto bad_reg; | |
1411 | } | |
1412 | } | |
1413 | break; | |
b5ff1b31 | 1414 | case 7: /* Cache control. */ |
c3d2689d AZ |
1415 | env->cp15.c15_i_max = 0x000; |
1416 | env->cp15.c15_i_min = 0xff0; | |
b5ff1b31 | 1417 | /* No cache, so nothing to do. */ |
9ee6e8bb | 1418 | /* ??? MPCore has VA to PA translation functions. */ |
b5ff1b31 FB |
1419 | break; |
1420 | case 8: /* MMU TLB control. */ | |
1421 | switch (op2) { | |
1422 | case 0: /* Invalidate all. */ | |
1423 | tlb_flush(env, 0); | |
1424 | break; | |
1425 | case 1: /* Invalidate single TLB entry. */ | |
d4c430a8 | 1426 | tlb_flush_page(env, val & TARGET_PAGE_MASK); |
b5ff1b31 | 1427 | break; |
9ee6e8bb PB |
1428 | case 2: /* Invalidate on ASID. */ |
1429 | tlb_flush(env, val == 0); | |
1430 | break; | |
1431 | case 3: /* Invalidate single entry on MVA. */ | |
1432 | /* ??? This is like case 1, but ignores ASID. */ | |
1433 | tlb_flush(env, 1); | |
1434 | break; | |
b5ff1b31 FB |
1435 | default: |
1436 | goto bad_reg; | |
1437 | } | |
1438 | break; | |
ce819861 | 1439 | case 9: |
c3d2689d AZ |
1440 | if (arm_feature(env, ARM_FEATURE_OMAPCP)) |
1441 | break; | |
ce819861 PB |
1442 | switch (crm) { |
1443 | case 0: /* Cache lockdown. */ | |
9ee6e8bb PB |
1444 | switch (op1) { |
1445 | case 0: /* L1 cache. */ | |
1446 | switch (op2) { | |
1447 | case 0: | |
1448 | env->cp15.c9_data = val; | |
1449 | break; | |
1450 | case 1: | |
1451 | env->cp15.c9_insn = val; | |
1452 | break; | |
1453 | default: | |
1454 | goto bad_reg; | |
1455 | } | |
1456 | break; | |
1457 | case 1: /* L2 cache. */ | |
1458 | /* Ignore writes to L2 lockdown/auxiliary registers. */ | |
1459 | break; | |
1460 | default: | |
1461 | goto bad_reg; | |
1462 | } | |
1463 | break; | |
ce819861 PB |
1464 | case 1: /* TCM memory region registers. */ |
1465 | /* Not implemented. */ | |
1466 | goto bad_reg; | |
b5ff1b31 FB |
1467 | default: |
1468 | goto bad_reg; | |
1469 | } | |
1470 | break; | |
1471 | case 10: /* MMU TLB lockdown. */ | |
1472 | /* ??? TLB lockdown not implemented. */ | |
1473 | break; | |
b5ff1b31 FB |
1474 | case 12: /* Reserved. */ |
1475 | goto bad_reg; | |
1476 | case 13: /* Process ID. */ | |
1477 | switch (op2) { | |
1478 | case 0: | |
d07edbfa PB |
1479 | /* Unlike real hardware the qemu TLB uses virtual addresses, |
1480 | not modified virtual addresses, so this causes a TLB flush. | |
1481 | */ | |
1482 | if (env->cp15.c13_fcse != val) | |
1483 | tlb_flush(env, 1); | |
1484 | env->cp15.c13_fcse = val; | |
b5ff1b31 FB |
1485 | break; |
1486 | case 1: | |
d07edbfa | 1487 | /* This changes the ASID, so do a TLB flush. */ |
ce819861 PB |
1488 | if (env->cp15.c13_context != val |
1489 | && !arm_feature(env, ARM_FEATURE_MPU)) | |
d07edbfa PB |
1490 | tlb_flush(env, 0); |
1491 | env->cp15.c13_context = val; | |
b5ff1b31 FB |
1492 | break; |
1493 | default: | |
1494 | goto bad_reg; | |
1495 | } | |
1496 | break; | |
1497 | case 14: /* Reserved. */ | |
1498 | goto bad_reg; | |
1499 | case 15: /* Implementation specific. */ | |
c1713132 | 1500 | if (arm_feature(env, ARM_FEATURE_XSCALE)) { |
ce819861 | 1501 | if (op2 == 0 && crm == 1) { |
2e23213f AZ |
1502 | if (env->cp15.c15_cpar != (val & 0x3fff)) { |
1503 | /* Changes cp0 to cp13 behavior, so needs a TB flush. */ | |
1504 | tb_flush(env); | |
1505 | env->cp15.c15_cpar = val & 0x3fff; | |
1506 | } | |
c1713132 AZ |
1507 | break; |
1508 | } | |
1509 | goto bad_reg; | |
1510 | } | |
c3d2689d AZ |
1511 | if (arm_feature(env, ARM_FEATURE_OMAPCP)) { |
1512 | switch (crm) { | |
1513 | case 0: | |
1514 | break; | |
1515 | case 1: /* Set TI925T configuration. */ | |
1516 | env->cp15.c15_ticonfig = val & 0xe7; | |
1517 | env->cp15.c0_cpuid = (val & (1 << 5)) ? /* OS_TYPE bit */ | |
1518 | ARM_CPUID_TI915T : ARM_CPUID_TI925T; | |
1519 | break; | |
1520 | case 2: /* Set I_max. */ | |
1521 | env->cp15.c15_i_max = val; | |
1522 | break; | |
1523 | case 3: /* Set I_min. */ | |
1524 | env->cp15.c15_i_min = val; | |
1525 | break; | |
1526 | case 4: /* Set thread-ID. */ | |
1527 | env->cp15.c15_threadid = val & 0xffff; | |
1528 | break; | |
1529 | case 8: /* Wait-for-interrupt (deprecated). */ | |
1530 | cpu_interrupt(env, CPU_INTERRUPT_HALT); | |
1531 | break; | |
1532 | default: | |
1533 | goto bad_reg; | |
1534 | } | |
1535 | } | |
b5ff1b31 FB |
1536 | break; |
1537 | } | |
1538 | return; | |
1539 | bad_reg: | |
1540 | /* ??? For debugging only. Should raise illegal instruction exception. */ | |
9ee6e8bb PB |
1541 | cpu_abort(env, "Unimplemented cp15 register write (c%d, c%d, {%d, %d})\n", |
1542 | (insn >> 16) & 0xf, crm, op1, op2); | |
b5ff1b31 FB |
1543 | } |
1544 | ||
8984bd2e | 1545 | uint32_t HELPER(get_cp15)(CPUState *env, uint32_t insn) |
b5ff1b31 | 1546 | { |
9ee6e8bb PB |
1547 | int op1; |
1548 | int op2; | |
1549 | int crm; | |
b5ff1b31 | 1550 | |
9ee6e8bb | 1551 | op1 = (insn >> 21) & 7; |
b5ff1b31 | 1552 | op2 = (insn >> 5) & 7; |
c3d2689d | 1553 | crm = insn & 0xf; |
b5ff1b31 FB |
1554 | switch ((insn >> 16) & 0xf) { |
1555 | case 0: /* ID codes. */ | |
9ee6e8bb PB |
1556 | switch (op1) { |
1557 | case 0: | |
1558 | switch (crm) { | |
1559 | case 0: | |
1560 | switch (op2) { | |
1561 | case 0: /* Device ID. */ | |
1562 | return env->cp15.c0_cpuid; | |
1563 | case 1: /* Cache Type. */ | |
1564 | return env->cp15.c0_cachetype; | |
1565 | case 2: /* TCM status. */ | |
1566 | return 0; | |
1567 | case 3: /* TLB type register. */ | |
1568 | return 0; /* No lockable TLB entries. */ | |
1569 | case 5: /* CPU ID */ | |
10055562 PB |
1570 | if (ARM_CPUID(env) == ARM_CPUID_CORTEXA9) { |
1571 | return env->cpu_index | 0x80000900; | |
1572 | } else { | |
1573 | return env->cpu_index; | |
1574 | } | |
9ee6e8bb PB |
1575 | default: |
1576 | goto bad_reg; | |
1577 | } | |
1578 | case 1: | |
1579 | if (!arm_feature(env, ARM_FEATURE_V6)) | |
1580 | goto bad_reg; | |
1581 | return env->cp15.c0_c1[op2]; | |
1582 | case 2: | |
1583 | if (!arm_feature(env, ARM_FEATURE_V6)) | |
1584 | goto bad_reg; | |
1585 | return env->cp15.c0_c2[op2]; | |
1586 | case 3: case 4: case 5: case 6: case 7: | |
1587 | return 0; | |
1588 | default: | |
1589 | goto bad_reg; | |
1590 | } | |
1591 | case 1: | |
1592 | /* These registers aren't documented on arm11 cores. However | |
1593 | Linux looks at them anyway. */ | |
1594 | if (!arm_feature(env, ARM_FEATURE_V6)) | |
1595 | goto bad_reg; | |
1596 | if (crm != 0) | |
1597 | goto bad_reg; | |
a49ea279 PB |
1598 | if (!arm_feature(env, ARM_FEATURE_V7)) |
1599 | return 0; | |
1600 | ||
1601 | switch (op2) { | |
1602 | case 0: | |
1603 | return env->cp15.c0_ccsid[env->cp15.c0_cssel]; | |
1604 | case 1: | |
1605 | return env->cp15.c0_clid; | |
1606 | case 7: | |
1607 | return 0; | |
1608 | } | |
1609 | goto bad_reg; | |
1610 | case 2: | |
1611 | if (op2 != 0 || crm != 0) | |
610c3c8a | 1612 | goto bad_reg; |
a49ea279 | 1613 | return env->cp15.c0_cssel; |
9ee6e8bb PB |
1614 | default: |
1615 | goto bad_reg; | |
b5ff1b31 FB |
1616 | } |
1617 | case 1: /* System configuration. */ | |
c3d2689d AZ |
1618 | if (arm_feature(env, ARM_FEATURE_OMAPCP)) |
1619 | op2 = 0; | |
b5ff1b31 FB |
1620 | switch (op2) { |
1621 | case 0: /* Control register. */ | |
1622 | return env->cp15.c1_sys; | |
1623 | case 1: /* Auxiliary control register. */ | |
c1713132 | 1624 | if (arm_feature(env, ARM_FEATURE_XSCALE)) |
610c3c8a | 1625 | return env->cp15.c1_xscaleauxcr; |
9ee6e8bb PB |
1626 | if (!arm_feature(env, ARM_FEATURE_AUXCR)) |
1627 | goto bad_reg; | |
1628 | switch (ARM_CPUID(env)) { | |
1629 | case ARM_CPUID_ARM1026: | |
1630 | return 1; | |
1631 | case ARM_CPUID_ARM1136: | |
827df9f3 | 1632 | case ARM_CPUID_ARM1136_R2: |
9ee6e8bb PB |
1633 | return 7; |
1634 | case ARM_CPUID_ARM11MPCORE: | |
1635 | return 1; | |
1636 | case ARM_CPUID_CORTEXA8: | |
533d177a | 1637 | return 2; |
10055562 PB |
1638 | case ARM_CPUID_CORTEXA9: |
1639 | return 0; | |
9ee6e8bb PB |
1640 | default: |
1641 | goto bad_reg; | |
1642 | } | |
b5ff1b31 | 1643 | case 2: /* Coprocessor access register. */ |
610c3c8a AZ |
1644 | if (arm_feature(env, ARM_FEATURE_XSCALE)) |
1645 | goto bad_reg; | |
b5ff1b31 FB |
1646 | return env->cp15.c1_coproc; |
1647 | default: | |
1648 | goto bad_reg; | |
1649 | } | |
ce819861 PB |
1650 | case 2: /* MMU Page table control / MPU cache control. */ |
1651 | if (arm_feature(env, ARM_FEATURE_MPU)) { | |
1652 | switch (op2) { | |
1653 | case 0: | |
1654 | return env->cp15.c2_data; | |
1655 | break; | |
1656 | case 1: | |
1657 | return env->cp15.c2_insn; | |
1658 | break; | |
1659 | default: | |
1660 | goto bad_reg; | |
1661 | } | |
1662 | } else { | |
9ee6e8bb PB |
1663 | switch (op2) { |
1664 | case 0: | |
1665 | return env->cp15.c2_base0; | |
1666 | case 1: | |
1667 | return env->cp15.c2_base1; | |
1668 | case 2: | |
b2fa1797 | 1669 | return env->cp15.c2_control; |
9ee6e8bb PB |
1670 | default: |
1671 | goto bad_reg; | |
1672 | } | |
1673 | } | |
ce819861 | 1674 | case 3: /* MMU Domain access control / MPU write buffer control. */ |
b5ff1b31 FB |
1675 | return env->cp15.c3; |
1676 | case 4: /* Reserved. */ | |
1677 | goto bad_reg; | |
ce819861 | 1678 | case 5: /* MMU Fault status / MPU access permission. */ |
c3d2689d AZ |
1679 | if (arm_feature(env, ARM_FEATURE_OMAPCP)) |
1680 | op2 = 0; | |
b5ff1b31 FB |
1681 | switch (op2) { |
1682 | case 0: | |
ce819861 PB |
1683 | if (arm_feature(env, ARM_FEATURE_MPU)) |
1684 | return simple_mpu_ap_bits(env->cp15.c5_data); | |
b5ff1b31 FB |
1685 | return env->cp15.c5_data; |
1686 | case 1: | |
ce819861 PB |
1687 | if (arm_feature(env, ARM_FEATURE_MPU)) |
1688 | return simple_mpu_ap_bits(env->cp15.c5_data); | |
1689 | return env->cp15.c5_insn; | |
1690 | case 2: | |
1691 | if (!arm_feature(env, ARM_FEATURE_MPU)) | |
1692 | goto bad_reg; | |
1693 | return env->cp15.c5_data; | |
1694 | case 3: | |
1695 | if (!arm_feature(env, ARM_FEATURE_MPU)) | |
1696 | goto bad_reg; | |
b5ff1b31 FB |
1697 | return env->cp15.c5_insn; |
1698 | default: | |
1699 | goto bad_reg; | |
1700 | } | |
9ee6e8bb | 1701 | case 6: /* MMU Fault address. */ |
ce819861 | 1702 | if (arm_feature(env, ARM_FEATURE_MPU)) { |
9ee6e8bb | 1703 | if (crm >= 8) |
ce819861 | 1704 | goto bad_reg; |
9ee6e8bb | 1705 | return env->cp15.c6_region[crm]; |
ce819861 | 1706 | } else { |
c3d2689d AZ |
1707 | if (arm_feature(env, ARM_FEATURE_OMAPCP)) |
1708 | op2 = 0; | |
9ee6e8bb PB |
1709 | switch (op2) { |
1710 | case 0: | |
1711 | return env->cp15.c6_data; | |
1712 | case 1: | |
1713 | if (arm_feature(env, ARM_FEATURE_V6)) { | |
1714 | /* Watchpoint Fault Adrress. */ | |
1715 | return 0; /* Not implemented. */ | |
1716 | } else { | |
1717 | /* Instruction Fault Adrress. */ | |
1718 | /* Arm9 doesn't have an IFAR, but implementing it anyway | |
1719 | shouldn't do any harm. */ | |
1720 | return env->cp15.c6_insn; | |
1721 | } | |
1722 | case 2: | |
1723 | if (arm_feature(env, ARM_FEATURE_V6)) { | |
1724 | /* Instruction Fault Adrress. */ | |
1725 | return env->cp15.c6_insn; | |
1726 | } else { | |
1727 | goto bad_reg; | |
1728 | } | |
1729 | default: | |
1730 | goto bad_reg; | |
1731 | } | |
b5ff1b31 FB |
1732 | } |
1733 | case 7: /* Cache control. */ | |
6fbe23d5 PB |
1734 | /* FIXME: Should only clear Z flag if destination is r15. */ |
1735 | env->ZF = 0; | |
b5ff1b31 FB |
1736 | return 0; |
1737 | case 8: /* MMU TLB control. */ | |
1738 | goto bad_reg; | |
1739 | case 9: /* Cache lockdown. */ | |
9ee6e8bb PB |
1740 | switch (op1) { |
1741 | case 0: /* L1 cache. */ | |
1742 | if (arm_feature(env, ARM_FEATURE_OMAPCP)) | |
1743 | return 0; | |
1744 | switch (op2) { | |
1745 | case 0: | |
1746 | return env->cp15.c9_data; | |
1747 | case 1: | |
1748 | return env->cp15.c9_insn; | |
1749 | default: | |
1750 | goto bad_reg; | |
1751 | } | |
1752 | case 1: /* L2 cache */ | |
1753 | if (crm != 0) | |
1754 | goto bad_reg; | |
1755 | /* L2 Lockdown and Auxiliary control. */ | |
c3d2689d | 1756 | return 0; |
b5ff1b31 FB |
1757 | default: |
1758 | goto bad_reg; | |
1759 | } | |
1760 | case 10: /* MMU TLB lockdown. */ | |
1761 | /* ??? TLB lockdown not implemented. */ | |
1762 | return 0; | |
1763 | case 11: /* TCM DMA control. */ | |
1764 | case 12: /* Reserved. */ | |
1765 | goto bad_reg; | |
1766 | case 13: /* Process ID. */ | |
1767 | switch (op2) { | |
1768 | case 0: | |
1769 | return env->cp15.c13_fcse; | |
1770 | case 1: | |
1771 | return env->cp15.c13_context; | |
1772 | default: | |
1773 | goto bad_reg; | |
1774 | } | |
1775 | case 14: /* Reserved. */ | |
1776 | goto bad_reg; | |
1777 | case 15: /* Implementation specific. */ | |
c1713132 | 1778 | if (arm_feature(env, ARM_FEATURE_XSCALE)) { |
c3d2689d | 1779 | if (op2 == 0 && crm == 1) |
c1713132 AZ |
1780 | return env->cp15.c15_cpar; |
1781 | ||
1782 | goto bad_reg; | |
1783 | } | |
c3d2689d AZ |
1784 | if (arm_feature(env, ARM_FEATURE_OMAPCP)) { |
1785 | switch (crm) { | |
1786 | case 0: | |
1787 | return 0; | |
1788 | case 1: /* Read TI925T configuration. */ | |
1789 | return env->cp15.c15_ticonfig; | |
1790 | case 2: /* Read I_max. */ | |
1791 | return env->cp15.c15_i_max; | |
1792 | case 3: /* Read I_min. */ | |
1793 | return env->cp15.c15_i_min; | |
1794 | case 4: /* Read thread-ID. */ | |
1795 | return env->cp15.c15_threadid; | |
1796 | case 8: /* TI925T_status */ | |
1797 | return 0; | |
1798 | } | |
827df9f3 AZ |
1799 | /* TODO: Peripheral port remap register: |
1800 | * On OMAP2 mcr p15, 0, rn, c15, c2, 4 sets up the interrupt | |
1801 | * controller base address at $rn & ~0xfff and map size of | |
1802 | * 0x200 << ($rn & 0xfff), when MMU is off. */ | |
c3d2689d AZ |
1803 | goto bad_reg; |
1804 | } | |
b5ff1b31 FB |
1805 | return 0; |
1806 | } | |
1807 | bad_reg: | |
1808 | /* ??? For debugging only. Should raise illegal instruction exception. */ | |
9ee6e8bb PB |
1809 | cpu_abort(env, "Unimplemented cp15 register read (c%d, c%d, {%d, %d})\n", |
1810 | (insn >> 16) & 0xf, crm, op1, op2); | |
b5ff1b31 FB |
1811 | return 0; |
1812 | } | |
1813 | ||
b0109805 | 1814 | void HELPER(set_r13_banked)(CPUState *env, uint32_t mode, uint32_t val) |
9ee6e8bb PB |
1815 | { |
1816 | env->banked_r13[bank_number(mode)] = val; | |
1817 | } | |
1818 | ||
b0109805 | 1819 | uint32_t HELPER(get_r13_banked)(CPUState *env, uint32_t mode) |
9ee6e8bb PB |
1820 | { |
1821 | return env->banked_r13[bank_number(mode)]; | |
1822 | } | |
1823 | ||
8984bd2e | 1824 | uint32_t HELPER(v7m_mrs)(CPUState *env, uint32_t reg) |
9ee6e8bb PB |
1825 | { |
1826 | switch (reg) { | |
1827 | case 0: /* APSR */ | |
1828 | return xpsr_read(env) & 0xf8000000; | |
1829 | case 1: /* IAPSR */ | |
1830 | return xpsr_read(env) & 0xf80001ff; | |
1831 | case 2: /* EAPSR */ | |
1832 | return xpsr_read(env) & 0xff00fc00; | |
1833 | case 3: /* xPSR */ | |
1834 | return xpsr_read(env) & 0xff00fdff; | |
1835 | case 5: /* IPSR */ | |
1836 | return xpsr_read(env) & 0x000001ff; | |
1837 | case 6: /* EPSR */ | |
1838 | return xpsr_read(env) & 0x0700fc00; | |
1839 | case 7: /* IEPSR */ | |
1840 | return xpsr_read(env) & 0x0700edff; | |
1841 | case 8: /* MSP */ | |
1842 | return env->v7m.current_sp ? env->v7m.other_sp : env->regs[13]; | |
1843 | case 9: /* PSP */ | |
1844 | return env->v7m.current_sp ? env->regs[13] : env->v7m.other_sp; | |
1845 | case 16: /* PRIMASK */ | |
1846 | return (env->uncached_cpsr & CPSR_I) != 0; | |
1847 | case 17: /* FAULTMASK */ | |
1848 | return (env->uncached_cpsr & CPSR_F) != 0; | |
1849 | case 18: /* BASEPRI */ | |
1850 | case 19: /* BASEPRI_MAX */ | |
1851 | return env->v7m.basepri; | |
1852 | case 20: /* CONTROL */ | |
1853 | return env->v7m.control; | |
1854 | default: | |
1855 | /* ??? For debugging only. */ | |
1856 | cpu_abort(env, "Unimplemented system register read (%d)\n", reg); | |
1857 | return 0; | |
1858 | } | |
1859 | } | |
1860 | ||
8984bd2e | 1861 | void HELPER(v7m_msr)(CPUState *env, uint32_t reg, uint32_t val) |
9ee6e8bb PB |
1862 | { |
1863 | switch (reg) { | |
1864 | case 0: /* APSR */ | |
1865 | xpsr_write(env, val, 0xf8000000); | |
1866 | break; | |
1867 | case 1: /* IAPSR */ | |
1868 | xpsr_write(env, val, 0xf8000000); | |
1869 | break; | |
1870 | case 2: /* EAPSR */ | |
1871 | xpsr_write(env, val, 0xfe00fc00); | |
1872 | break; | |
1873 | case 3: /* xPSR */ | |
1874 | xpsr_write(env, val, 0xfe00fc00); | |
1875 | break; | |
1876 | case 5: /* IPSR */ | |
1877 | /* IPSR bits are readonly. */ | |
1878 | break; | |
1879 | case 6: /* EPSR */ | |
1880 | xpsr_write(env, val, 0x0600fc00); | |
1881 | break; | |
1882 | case 7: /* IEPSR */ | |
1883 | xpsr_write(env, val, 0x0600fc00); | |
1884 | break; | |
1885 | case 8: /* MSP */ | |
1886 | if (env->v7m.current_sp) | |
1887 | env->v7m.other_sp = val; | |
1888 | else | |
1889 | env->regs[13] = val; | |
1890 | break; | |
1891 | case 9: /* PSP */ | |
1892 | if (env->v7m.current_sp) | |
1893 | env->regs[13] = val; | |
1894 | else | |
1895 | env->v7m.other_sp = val; | |
1896 | break; | |
1897 | case 16: /* PRIMASK */ | |
1898 | if (val & 1) | |
1899 | env->uncached_cpsr |= CPSR_I; | |
1900 | else | |
1901 | env->uncached_cpsr &= ~CPSR_I; | |
1902 | break; | |
1903 | case 17: /* FAULTMASK */ | |
1904 | if (val & 1) | |
1905 | env->uncached_cpsr |= CPSR_F; | |
1906 | else | |
1907 | env->uncached_cpsr &= ~CPSR_F; | |
1908 | break; | |
1909 | case 18: /* BASEPRI */ | |
1910 | env->v7m.basepri = val & 0xff; | |
1911 | break; | |
1912 | case 19: /* BASEPRI_MAX */ | |
1913 | val &= 0xff; | |
1914 | if (val != 0 && (val < env->v7m.basepri || env->v7m.basepri == 0)) | |
1915 | env->v7m.basepri = val; | |
1916 | break; | |
1917 | case 20: /* CONTROL */ | |
1918 | env->v7m.control = val & 3; | |
1919 | switch_v7m_sp(env, (val & 2) != 0); | |
1920 | break; | |
1921 | default: | |
1922 | /* ??? For debugging only. */ | |
1923 | cpu_abort(env, "Unimplemented system register write (%d)\n", reg); | |
1924 | return; | |
1925 | } | |
1926 | } | |
1927 | ||
c1713132 AZ |
1928 | void cpu_arm_set_cp_io(CPUARMState *env, int cpnum, |
1929 | ARMReadCPFunc *cp_read, ARMWriteCPFunc *cp_write, | |
1930 | void *opaque) | |
1931 | { | |
1932 | if (cpnum < 0 || cpnum > 14) { | |
1933 | cpu_abort(env, "Bad coprocessor number: %i\n", cpnum); | |
1934 | return; | |
1935 | } | |
1936 | ||
1937 | env->cp[cpnum].cp_read = cp_read; | |
1938 | env->cp[cpnum].cp_write = cp_write; | |
1939 | env->cp[cpnum].opaque = opaque; | |
1940 | } | |
1941 | ||
b5ff1b31 | 1942 | #endif |
6ddbc6e4 PB |
1943 | |
1944 | /* Note that signed overflow is undefined in C. The following routines are | |
1945 | careful to use unsigned types where modulo arithmetic is required. | |
1946 | Failure to do so _will_ break on newer gcc. */ | |
1947 | ||
1948 | /* Signed saturating arithmetic. */ | |
1949 | ||
1654b2d6 | 1950 | /* Perform 16-bit signed saturating addition. */ |
6ddbc6e4 PB |
1951 | static inline uint16_t add16_sat(uint16_t a, uint16_t b) |
1952 | { | |
1953 | uint16_t res; | |
1954 | ||
1955 | res = a + b; | |
1956 | if (((res ^ a) & 0x8000) && !((a ^ b) & 0x8000)) { | |
1957 | if (a & 0x8000) | |
1958 | res = 0x8000; | |
1959 | else | |
1960 | res = 0x7fff; | |
1961 | } | |
1962 | return res; | |
1963 | } | |
1964 | ||
1654b2d6 | 1965 | /* Perform 8-bit signed saturating addition. */ |
6ddbc6e4 PB |
1966 | static inline uint8_t add8_sat(uint8_t a, uint8_t b) |
1967 | { | |
1968 | uint8_t res; | |
1969 | ||
1970 | res = a + b; | |
1971 | if (((res ^ a) & 0x80) && !((a ^ b) & 0x80)) { | |
1972 | if (a & 0x80) | |
1973 | res = 0x80; | |
1974 | else | |
1975 | res = 0x7f; | |
1976 | } | |
1977 | return res; | |
1978 | } | |
1979 | ||
1654b2d6 | 1980 | /* Perform 16-bit signed saturating subtraction. */ |
6ddbc6e4 PB |
1981 | static inline uint16_t sub16_sat(uint16_t a, uint16_t b) |
1982 | { | |
1983 | uint16_t res; | |
1984 | ||
1985 | res = a - b; | |
1986 | if (((res ^ a) & 0x8000) && ((a ^ b) & 0x8000)) { | |
1987 | if (a & 0x8000) | |
1988 | res = 0x8000; | |
1989 | else | |
1990 | res = 0x7fff; | |
1991 | } | |
1992 | return res; | |
1993 | } | |
1994 | ||
1654b2d6 | 1995 | /* Perform 8-bit signed saturating subtraction. */ |
6ddbc6e4 PB |
1996 | static inline uint8_t sub8_sat(uint8_t a, uint8_t b) |
1997 | { | |
1998 | uint8_t res; | |
1999 | ||
2000 | res = a - b; | |
2001 | if (((res ^ a) & 0x80) && ((a ^ b) & 0x80)) { | |
2002 | if (a & 0x80) | |
2003 | res = 0x80; | |
2004 | else | |
2005 | res = 0x7f; | |
2006 | } | |
2007 | return res; | |
2008 | } | |
2009 | ||
2010 | #define ADD16(a, b, n) RESULT(add16_sat(a, b), n, 16); | |
2011 | #define SUB16(a, b, n) RESULT(sub16_sat(a, b), n, 16); | |
2012 | #define ADD8(a, b, n) RESULT(add8_sat(a, b), n, 8); | |
2013 | #define SUB8(a, b, n) RESULT(sub8_sat(a, b), n, 8); | |
2014 | #define PFX q | |
2015 | ||
2016 | #include "op_addsub.h" | |
2017 | ||
2018 | /* Unsigned saturating arithmetic. */ | |
460a09c1 | 2019 | static inline uint16_t add16_usat(uint16_t a, uint16_t b) |
6ddbc6e4 PB |
2020 | { |
2021 | uint16_t res; | |
2022 | res = a + b; | |
2023 | if (res < a) | |
2024 | res = 0xffff; | |
2025 | return res; | |
2026 | } | |
2027 | ||
460a09c1 | 2028 | static inline uint16_t sub16_usat(uint16_t a, uint16_t b) |
6ddbc6e4 PB |
2029 | { |
2030 | if (a < b) | |
2031 | return a - b; | |
2032 | else | |
2033 | return 0; | |
2034 | } | |
2035 | ||
2036 | static inline uint8_t add8_usat(uint8_t a, uint8_t b) | |
2037 | { | |
2038 | uint8_t res; | |
2039 | res = a + b; | |
2040 | if (res < a) | |
2041 | res = 0xff; | |
2042 | return res; | |
2043 | } | |
2044 | ||
2045 | static inline uint8_t sub8_usat(uint8_t a, uint8_t b) | |
2046 | { | |
2047 | if (a < b) | |
2048 | return a - b; | |
2049 | else | |
2050 | return 0; | |
2051 | } | |
2052 | ||
2053 | #define ADD16(a, b, n) RESULT(add16_usat(a, b), n, 16); | |
2054 | #define SUB16(a, b, n) RESULT(sub16_usat(a, b), n, 16); | |
2055 | #define ADD8(a, b, n) RESULT(add8_usat(a, b), n, 8); | |
2056 | #define SUB8(a, b, n) RESULT(sub8_usat(a, b), n, 8); | |
2057 | #define PFX uq | |
2058 | ||
2059 | #include "op_addsub.h" | |
2060 | ||
2061 | /* Signed modulo arithmetic. */ | |
2062 | #define SARITH16(a, b, n, op) do { \ | |
2063 | int32_t sum; \ | |
2064 | sum = (int16_t)((uint16_t)(a) op (uint16_t)(b)); \ | |
2065 | RESULT(sum, n, 16); \ | |
2066 | if (sum >= 0) \ | |
2067 | ge |= 3 << (n * 2); \ | |
2068 | } while(0) | |
2069 | ||
2070 | #define SARITH8(a, b, n, op) do { \ | |
2071 | int32_t sum; \ | |
2072 | sum = (int8_t)((uint8_t)(a) op (uint8_t)(b)); \ | |
2073 | RESULT(sum, n, 8); \ | |
2074 | if (sum >= 0) \ | |
2075 | ge |= 1 << n; \ | |
2076 | } while(0) | |
2077 | ||
2078 | ||
2079 | #define ADD16(a, b, n) SARITH16(a, b, n, +) | |
2080 | #define SUB16(a, b, n) SARITH16(a, b, n, -) | |
2081 | #define ADD8(a, b, n) SARITH8(a, b, n, +) | |
2082 | #define SUB8(a, b, n) SARITH8(a, b, n, -) | |
2083 | #define PFX s | |
2084 | #define ARITH_GE | |
2085 | ||
2086 | #include "op_addsub.h" | |
2087 | ||
2088 | /* Unsigned modulo arithmetic. */ | |
2089 | #define ADD16(a, b, n) do { \ | |
2090 | uint32_t sum; \ | |
2091 | sum = (uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b); \ | |
2092 | RESULT(sum, n, 16); \ | |
a87aa10b | 2093 | if ((sum >> 16) == 1) \ |
6ddbc6e4 PB |
2094 | ge |= 3 << (n * 2); \ |
2095 | } while(0) | |
2096 | ||
2097 | #define ADD8(a, b, n) do { \ | |
2098 | uint32_t sum; \ | |
2099 | sum = (uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b); \ | |
2100 | RESULT(sum, n, 8); \ | |
a87aa10b AZ |
2101 | if ((sum >> 8) == 1) \ |
2102 | ge |= 1 << n; \ | |
6ddbc6e4 PB |
2103 | } while(0) |
2104 | ||
2105 | #define SUB16(a, b, n) do { \ | |
2106 | uint32_t sum; \ | |
2107 | sum = (uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b); \ | |
2108 | RESULT(sum, n, 16); \ | |
2109 | if ((sum >> 16) == 0) \ | |
2110 | ge |= 3 << (n * 2); \ | |
2111 | } while(0) | |
2112 | ||
2113 | #define SUB8(a, b, n) do { \ | |
2114 | uint32_t sum; \ | |
2115 | sum = (uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b); \ | |
2116 | RESULT(sum, n, 8); \ | |
2117 | if ((sum >> 8) == 0) \ | |
a87aa10b | 2118 | ge |= 1 << n; \ |
6ddbc6e4 PB |
2119 | } while(0) |
2120 | ||
2121 | #define PFX u | |
2122 | #define ARITH_GE | |
2123 | ||
2124 | #include "op_addsub.h" | |
2125 | ||
2126 | /* Halved signed arithmetic. */ | |
2127 | #define ADD16(a, b, n) \ | |
2128 | RESULT(((int32_t)(int16_t)(a) + (int32_t)(int16_t)(b)) >> 1, n, 16) | |
2129 | #define SUB16(a, b, n) \ | |
2130 | RESULT(((int32_t)(int16_t)(a) - (int32_t)(int16_t)(b)) >> 1, n, 16) | |
2131 | #define ADD8(a, b, n) \ | |
2132 | RESULT(((int32_t)(int8_t)(a) + (int32_t)(int8_t)(b)) >> 1, n, 8) | |
2133 | #define SUB8(a, b, n) \ | |
2134 | RESULT(((int32_t)(int8_t)(a) - (int32_t)(int8_t)(b)) >> 1, n, 8) | |
2135 | #define PFX sh | |
2136 | ||
2137 | #include "op_addsub.h" | |
2138 | ||
2139 | /* Halved unsigned arithmetic. */ | |
2140 | #define ADD16(a, b, n) \ | |
2141 | RESULT(((uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b)) >> 1, n, 16) | |
2142 | #define SUB16(a, b, n) \ | |
2143 | RESULT(((uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b)) >> 1, n, 16) | |
2144 | #define ADD8(a, b, n) \ | |
2145 | RESULT(((uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b)) >> 1, n, 8) | |
2146 | #define SUB8(a, b, n) \ | |
2147 | RESULT(((uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b)) >> 1, n, 8) | |
2148 | #define PFX uh | |
2149 | ||
2150 | #include "op_addsub.h" | |
2151 | ||
2152 | static inline uint8_t do_usad(uint8_t a, uint8_t b) | |
2153 | { | |
2154 | if (a > b) | |
2155 | return a - b; | |
2156 | else | |
2157 | return b - a; | |
2158 | } | |
2159 | ||
2160 | /* Unsigned sum of absolute byte differences. */ | |
2161 | uint32_t HELPER(usad8)(uint32_t a, uint32_t b) | |
2162 | { | |
2163 | uint32_t sum; | |
2164 | sum = do_usad(a, b); | |
2165 | sum += do_usad(a >> 8, b >> 8); | |
2166 | sum += do_usad(a >> 16, b >>16); | |
2167 | sum += do_usad(a >> 24, b >> 24); | |
2168 | return sum; | |
2169 | } | |
2170 | ||
2171 | /* For ARMv6 SEL instruction. */ | |
2172 | uint32_t HELPER(sel_flags)(uint32_t flags, uint32_t a, uint32_t b) | |
2173 | { | |
2174 | uint32_t mask; | |
2175 | ||
2176 | mask = 0; | |
2177 | if (flags & 1) | |
2178 | mask |= 0xff; | |
2179 | if (flags & 2) | |
2180 | mask |= 0xff00; | |
2181 | if (flags & 4) | |
2182 | mask |= 0xff0000; | |
2183 | if (flags & 8) | |
2184 | mask |= 0xff000000; | |
2185 | return (a & mask) | (b & ~mask); | |
2186 | } | |
2187 | ||
5e3f878a PB |
2188 | uint32_t HELPER(logicq_cc)(uint64_t val) |
2189 | { | |
2190 | return (val >> 32) | (val != 0); | |
2191 | } | |
4373f3ce PB |
2192 | |
2193 | /* VFP support. We follow the convention used for VFP instrunctions: | |
2194 | Single precition routines have a "s" suffix, double precision a | |
2195 | "d" suffix. */ | |
2196 | ||
2197 | /* Convert host exception flags to vfp form. */ | |
2198 | static inline int vfp_exceptbits_from_host(int host_bits) | |
2199 | { | |
2200 | int target_bits = 0; | |
2201 | ||
2202 | if (host_bits & float_flag_invalid) | |
2203 | target_bits |= 1; | |
2204 | if (host_bits & float_flag_divbyzero) | |
2205 | target_bits |= 2; | |
2206 | if (host_bits & float_flag_overflow) | |
2207 | target_bits |= 4; | |
2208 | if (host_bits & float_flag_underflow) | |
2209 | target_bits |= 8; | |
2210 | if (host_bits & float_flag_inexact) | |
2211 | target_bits |= 0x10; | |
2212 | return target_bits; | |
2213 | } | |
2214 | ||
2215 | uint32_t HELPER(vfp_get_fpscr)(CPUState *env) | |
2216 | { | |
2217 | int i; | |
2218 | uint32_t fpscr; | |
2219 | ||
2220 | fpscr = (env->vfp.xregs[ARM_VFP_FPSCR] & 0xffc8ffff) | |
2221 | | (env->vfp.vec_len << 16) | |
2222 | | (env->vfp.vec_stride << 20); | |
2223 | i = get_float_exception_flags(&env->vfp.fp_status); | |
2224 | fpscr |= vfp_exceptbits_from_host(i); | |
2225 | return fpscr; | |
2226 | } | |
2227 | ||
2228 | /* Convert vfp exception flags to target form. */ | |
2229 | static inline int vfp_exceptbits_to_host(int target_bits) | |
2230 | { | |
2231 | int host_bits = 0; | |
2232 | ||
2233 | if (target_bits & 1) | |
2234 | host_bits |= float_flag_invalid; | |
2235 | if (target_bits & 2) | |
2236 | host_bits |= float_flag_divbyzero; | |
2237 | if (target_bits & 4) | |
2238 | host_bits |= float_flag_overflow; | |
2239 | if (target_bits & 8) | |
2240 | host_bits |= float_flag_underflow; | |
2241 | if (target_bits & 0x10) | |
2242 | host_bits |= float_flag_inexact; | |
2243 | return host_bits; | |
2244 | } | |
2245 | ||
2246 | void HELPER(vfp_set_fpscr)(CPUState *env, uint32_t val) | |
2247 | { | |
2248 | int i; | |
2249 | uint32_t changed; | |
2250 | ||
2251 | changed = env->vfp.xregs[ARM_VFP_FPSCR]; | |
2252 | env->vfp.xregs[ARM_VFP_FPSCR] = (val & 0xffc8ffff); | |
2253 | env->vfp.vec_len = (val >> 16) & 7; | |
2254 | env->vfp.vec_stride = (val >> 20) & 3; | |
2255 | ||
2256 | changed ^= val; | |
2257 | if (changed & (3 << 22)) { | |
2258 | i = (val >> 22) & 3; | |
2259 | switch (i) { | |
2260 | case 0: | |
2261 | i = float_round_nearest_even; | |
2262 | break; | |
2263 | case 1: | |
2264 | i = float_round_up; | |
2265 | break; | |
2266 | case 2: | |
2267 | i = float_round_down; | |
2268 | break; | |
2269 | case 3: | |
2270 | i = float_round_to_zero; | |
2271 | break; | |
2272 | } | |
2273 | set_float_rounding_mode(i, &env->vfp.fp_status); | |
2274 | } | |
fe76d976 PB |
2275 | if (changed & (1 << 24)) |
2276 | set_flush_to_zero((val & (1 << 24)) != 0, &env->vfp.fp_status); | |
5c7908ed PB |
2277 | if (changed & (1 << 25)) |
2278 | set_default_nan_mode((val & (1 << 25)) != 0, &env->vfp.fp_status); | |
4373f3ce PB |
2279 | |
2280 | i = vfp_exceptbits_to_host((val >> 8) & 0x1f); | |
2281 | set_float_exception_flags(i, &env->vfp.fp_status); | |
4373f3ce PB |
2282 | } |
2283 | ||
2284 | #define VFP_HELPER(name, p) HELPER(glue(glue(vfp_,name),p)) | |
2285 | ||
2286 | #define VFP_BINOP(name) \ | |
2287 | float32 VFP_HELPER(name, s)(float32 a, float32 b, CPUState *env) \ | |
2288 | { \ | |
2289 | return float32_ ## name (a, b, &env->vfp.fp_status); \ | |
2290 | } \ | |
2291 | float64 VFP_HELPER(name, d)(float64 a, float64 b, CPUState *env) \ | |
2292 | { \ | |
2293 | return float64_ ## name (a, b, &env->vfp.fp_status); \ | |
2294 | } | |
2295 | VFP_BINOP(add) | |
2296 | VFP_BINOP(sub) | |
2297 | VFP_BINOP(mul) | |
2298 | VFP_BINOP(div) | |
2299 | #undef VFP_BINOP | |
2300 | ||
2301 | float32 VFP_HELPER(neg, s)(float32 a) | |
2302 | { | |
2303 | return float32_chs(a); | |
2304 | } | |
2305 | ||
2306 | float64 VFP_HELPER(neg, d)(float64 a) | |
2307 | { | |
66230e0d | 2308 | return float64_chs(a); |
4373f3ce PB |
2309 | } |
2310 | ||
2311 | float32 VFP_HELPER(abs, s)(float32 a) | |
2312 | { | |
2313 | return float32_abs(a); | |
2314 | } | |
2315 | ||
2316 | float64 VFP_HELPER(abs, d)(float64 a) | |
2317 | { | |
66230e0d | 2318 | return float64_abs(a); |
4373f3ce PB |
2319 | } |
2320 | ||
2321 | float32 VFP_HELPER(sqrt, s)(float32 a, CPUState *env) | |
2322 | { | |
2323 | return float32_sqrt(a, &env->vfp.fp_status); | |
2324 | } | |
2325 | ||
2326 | float64 VFP_HELPER(sqrt, d)(float64 a, CPUState *env) | |
2327 | { | |
2328 | return float64_sqrt(a, &env->vfp.fp_status); | |
2329 | } | |
2330 | ||
2331 | /* XXX: check quiet/signaling case */ | |
2332 | #define DO_VFP_cmp(p, type) \ | |
2333 | void VFP_HELPER(cmp, p)(type a, type b, CPUState *env) \ | |
2334 | { \ | |
2335 | uint32_t flags; \ | |
2336 | switch(type ## _compare_quiet(a, b, &env->vfp.fp_status)) { \ | |
2337 | case 0: flags = 0x6; break; \ | |
2338 | case -1: flags = 0x8; break; \ | |
2339 | case 1: flags = 0x2; break; \ | |
2340 | default: case 2: flags = 0x3; break; \ | |
2341 | } \ | |
2342 | env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \ | |
2343 | | (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \ | |
2344 | } \ | |
2345 | void VFP_HELPER(cmpe, p)(type a, type b, CPUState *env) \ | |
2346 | { \ | |
2347 | uint32_t flags; \ | |
2348 | switch(type ## _compare(a, b, &env->vfp.fp_status)) { \ | |
2349 | case 0: flags = 0x6; break; \ | |
2350 | case -1: flags = 0x8; break; \ | |
2351 | case 1: flags = 0x2; break; \ | |
2352 | default: case 2: flags = 0x3; break; \ | |
2353 | } \ | |
2354 | env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \ | |
2355 | | (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \ | |
2356 | } | |
2357 | DO_VFP_cmp(s, float32) | |
2358 | DO_VFP_cmp(d, float64) | |
2359 | #undef DO_VFP_cmp | |
2360 | ||
2361 | /* Helper routines to perform bitwise copies between float and int. */ | |
2362 | static inline float32 vfp_itos(uint32_t i) | |
2363 | { | |
2364 | union { | |
2365 | uint32_t i; | |
2366 | float32 s; | |
2367 | } v; | |
2368 | ||
2369 | v.i = i; | |
2370 | return v.s; | |
2371 | } | |
2372 | ||
2373 | static inline uint32_t vfp_stoi(float32 s) | |
2374 | { | |
2375 | union { | |
2376 | uint32_t i; | |
2377 | float32 s; | |
2378 | } v; | |
2379 | ||
2380 | v.s = s; | |
2381 | return v.i; | |
2382 | } | |
2383 | ||
2384 | static inline float64 vfp_itod(uint64_t i) | |
2385 | { | |
2386 | union { | |
2387 | uint64_t i; | |
2388 | float64 d; | |
2389 | } v; | |
2390 | ||
2391 | v.i = i; | |
2392 | return v.d; | |
2393 | } | |
2394 | ||
2395 | static inline uint64_t vfp_dtoi(float64 d) | |
2396 | { | |
2397 | union { | |
2398 | uint64_t i; | |
2399 | float64 d; | |
2400 | } v; | |
2401 | ||
2402 | v.d = d; | |
2403 | return v.i; | |
2404 | } | |
2405 | ||
2406 | /* Integer to float conversion. */ | |
2407 | float32 VFP_HELPER(uito, s)(float32 x, CPUState *env) | |
2408 | { | |
2409 | return uint32_to_float32(vfp_stoi(x), &env->vfp.fp_status); | |
2410 | } | |
2411 | ||
2412 | float64 VFP_HELPER(uito, d)(float32 x, CPUState *env) | |
2413 | { | |
2414 | return uint32_to_float64(vfp_stoi(x), &env->vfp.fp_status); | |
2415 | } | |
2416 | ||
2417 | float32 VFP_HELPER(sito, s)(float32 x, CPUState *env) | |
2418 | { | |
2419 | return int32_to_float32(vfp_stoi(x), &env->vfp.fp_status); | |
2420 | } | |
2421 | ||
2422 | float64 VFP_HELPER(sito, d)(float32 x, CPUState *env) | |
2423 | { | |
2424 | return int32_to_float64(vfp_stoi(x), &env->vfp.fp_status); | |
2425 | } | |
2426 | ||
2427 | /* Float to integer conversion. */ | |
2428 | float32 VFP_HELPER(toui, s)(float32 x, CPUState *env) | |
2429 | { | |
2430 | return vfp_itos(float32_to_uint32(x, &env->vfp.fp_status)); | |
2431 | } | |
2432 | ||
2433 | float32 VFP_HELPER(toui, d)(float64 x, CPUState *env) | |
2434 | { | |
2435 | return vfp_itos(float64_to_uint32(x, &env->vfp.fp_status)); | |
2436 | } | |
2437 | ||
2438 | float32 VFP_HELPER(tosi, s)(float32 x, CPUState *env) | |
2439 | { | |
2440 | return vfp_itos(float32_to_int32(x, &env->vfp.fp_status)); | |
2441 | } | |
2442 | ||
2443 | float32 VFP_HELPER(tosi, d)(float64 x, CPUState *env) | |
2444 | { | |
2445 | return vfp_itos(float64_to_int32(x, &env->vfp.fp_status)); | |
2446 | } | |
2447 | ||
2448 | float32 VFP_HELPER(touiz, s)(float32 x, CPUState *env) | |
2449 | { | |
2450 | return vfp_itos(float32_to_uint32_round_to_zero(x, &env->vfp.fp_status)); | |
2451 | } | |
2452 | ||
2453 | float32 VFP_HELPER(touiz, d)(float64 x, CPUState *env) | |
2454 | { | |
2455 | return vfp_itos(float64_to_uint32_round_to_zero(x, &env->vfp.fp_status)); | |
2456 | } | |
2457 | ||
2458 | float32 VFP_HELPER(tosiz, s)(float32 x, CPUState *env) | |
2459 | { | |
2460 | return vfp_itos(float32_to_int32_round_to_zero(x, &env->vfp.fp_status)); | |
2461 | } | |
2462 | ||
2463 | float32 VFP_HELPER(tosiz, d)(float64 x, CPUState *env) | |
2464 | { | |
2465 | return vfp_itos(float64_to_int32_round_to_zero(x, &env->vfp.fp_status)); | |
2466 | } | |
2467 | ||
2468 | /* floating point conversion */ | |
2469 | float64 VFP_HELPER(fcvtd, s)(float32 x, CPUState *env) | |
2470 | { | |
2471 | return float32_to_float64(x, &env->vfp.fp_status); | |
2472 | } | |
2473 | ||
2474 | float32 VFP_HELPER(fcvts, d)(float64 x, CPUState *env) | |
2475 | { | |
2476 | return float64_to_float32(x, &env->vfp.fp_status); | |
2477 | } | |
2478 | ||
2479 | /* VFP3 fixed point conversion. */ | |
2480 | #define VFP_CONV_FIX(name, p, ftype, itype, sign) \ | |
2481 | ftype VFP_HELPER(name##to, p)(ftype x, uint32_t shift, CPUState *env) \ | |
2482 | { \ | |
2483 | ftype tmp; \ | |
2484 | tmp = sign##int32_to_##ftype ((itype)vfp_##p##toi(x), \ | |
2485 | &env->vfp.fp_status); \ | |
644ad806 | 2486 | return ftype##_scalbn(tmp, -(int)shift, &env->vfp.fp_status); \ |
4373f3ce PB |
2487 | } \ |
2488 | ftype VFP_HELPER(to##name, p)(ftype x, uint32_t shift, CPUState *env) \ | |
2489 | { \ | |
2490 | ftype tmp; \ | |
2491 | tmp = ftype##_scalbn(x, shift, &env->vfp.fp_status); \ | |
2492 | return vfp_ito##p((itype)ftype##_to_##sign##int32_round_to_zero(tmp, \ | |
2493 | &env->vfp.fp_status)); \ | |
2494 | } | |
2495 | ||
2496 | VFP_CONV_FIX(sh, d, float64, int16, ) | |
2497 | VFP_CONV_FIX(sl, d, float64, int32, ) | |
2498 | VFP_CONV_FIX(uh, d, float64, uint16, u) | |
2499 | VFP_CONV_FIX(ul, d, float64, uint32, u) | |
2500 | VFP_CONV_FIX(sh, s, float32, int16, ) | |
2501 | VFP_CONV_FIX(sl, s, float32, int32, ) | |
2502 | VFP_CONV_FIX(uh, s, float32, uint16, u) | |
2503 | VFP_CONV_FIX(ul, s, float32, uint32, u) | |
2504 | #undef VFP_CONV_FIX | |
2505 | ||
60011498 PB |
2506 | /* Half precision conversions. */ |
2507 | float32 HELPER(vfp_fcvt_f16_to_f32)(uint32_t a, CPUState *env) | |
2508 | { | |
2509 | float_status *s = &env->vfp.fp_status; | |
2510 | int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0; | |
2511 | return float16_to_float32(a, ieee, s); | |
2512 | } | |
2513 | ||
2514 | uint32_t HELPER(vfp_fcvt_f32_to_f16)(float32 a, CPUState *env) | |
2515 | { | |
2516 | float_status *s = &env->vfp.fp_status; | |
2517 | int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0; | |
2518 | return float32_to_float16(a, ieee, s); | |
2519 | } | |
2520 | ||
4373f3ce PB |
2521 | float32 HELPER(recps_f32)(float32 a, float32 b, CPUState *env) |
2522 | { | |
2523 | float_status *s = &env->vfp.fp_status; | |
2524 | float32 two = int32_to_float32(2, s); | |
2525 | return float32_sub(two, float32_mul(a, b, s), s); | |
2526 | } | |
2527 | ||
2528 | float32 HELPER(rsqrts_f32)(float32 a, float32 b, CPUState *env) | |
2529 | { | |
2530 | float_status *s = &env->vfp.fp_status; | |
2531 | float32 three = int32_to_float32(3, s); | |
2532 | return float32_sub(three, float32_mul(a, b, s), s); | |
2533 | } | |
2534 | ||
8f8e3aa4 PB |
2535 | /* NEON helpers. */ |
2536 | ||
4373f3ce PB |
2537 | /* TODO: The architecture specifies the value that the estimate functions |
2538 | should return. We return the exact reciprocal/root instead. */ | |
2539 | float32 HELPER(recpe_f32)(float32 a, CPUState *env) | |
2540 | { | |
2541 | float_status *s = &env->vfp.fp_status; | |
2542 | float32 one = int32_to_float32(1, s); | |
2543 | return float32_div(one, a, s); | |
2544 | } | |
2545 | ||
2546 | float32 HELPER(rsqrte_f32)(float32 a, CPUState *env) | |
2547 | { | |
2548 | float_status *s = &env->vfp.fp_status; | |
2549 | float32 one = int32_to_float32(1, s); | |
2550 | return float32_div(one, float32_sqrt(a, s), s); | |
2551 | } | |
2552 | ||
2553 | uint32_t HELPER(recpe_u32)(uint32_t a, CPUState *env) | |
2554 | { | |
2555 | float_status *s = &env->vfp.fp_status; | |
2556 | float32 tmp; | |
2557 | tmp = int32_to_float32(a, s); | |
2558 | tmp = float32_scalbn(tmp, -32, s); | |
2559 | tmp = helper_recpe_f32(tmp, env); | |
2560 | tmp = float32_scalbn(tmp, 31, s); | |
2561 | return float32_to_int32(tmp, s); | |
2562 | } | |
2563 | ||
2564 | uint32_t HELPER(rsqrte_u32)(uint32_t a, CPUState *env) | |
2565 | { | |
2566 | float_status *s = &env->vfp.fp_status; | |
2567 | float32 tmp; | |
2568 | tmp = int32_to_float32(a, s); | |
2569 | tmp = float32_scalbn(tmp, -32, s); | |
2570 | tmp = helper_rsqrte_f32(tmp, env); | |
2571 | tmp = float32_scalbn(tmp, 31, s); | |
2572 | return float32_to_int32(tmp, s); | |
2573 | } | |
fe1479c3 PB |
2574 | |
2575 | void HELPER(set_teecr)(CPUState *env, uint32_t val) | |
2576 | { | |
2577 | val &= 1; | |
2578 | if (env->teecr != val) { | |
2579 | env->teecr = val; | |
2580 | tb_flush(env); | |
2581 | } | |
2582 | } |