]>
Commit | Line | Data |
---|---|---|
74c21bd0 | 1 | #include "qemu/osdep.h" |
b5ff1b31 | 2 | #include "cpu.h" |
ccd38087 | 3 | #include "internals.h" |
022c62cb | 4 | #include "exec/gdbstub.h" |
2ef6175a | 5 | #include "exec/helper-proto.h" |
1de7afc9 | 6 | #include "qemu/host-utils.h" |
78027bb6 | 7 | #include "sysemu/arch_init.h" |
9c17d615 | 8 | #include "sysemu/sysemu.h" |
1de7afc9 | 9 | #include "qemu/bitops.h" |
eb0ecd5a | 10 | #include "qemu/crc32c.h" |
f08b6170 | 11 | #include "exec/cpu_ldst.h" |
1d854765 | 12 | #include "arm_ldst.h" |
eb0ecd5a | 13 | #include <zlib.h> /* For crc32 */ |
cfe67cef | 14 | #include "exec/semihost.h" |
f3a9b694 | 15 | #include "sysemu/kvm.h" |
0b03bdfc | 16 | |
352c98e5 LV |
17 | #define ARM_CPU_FREQ 1000000000 /* FIXME: 1 GHz, should be configurable */ |
18 | ||
4a501606 | 19 | #ifndef CONFIG_USER_ONLY |
af51f566 EI |
20 | static bool get_phys_addr(CPUARMState *env, target_ulong address, |
21 | int access_type, ARMMMUIdx mmu_idx, | |
22 | hwaddr *phys_ptr, MemTxAttrs *attrs, int *prot, | |
e14b5a23 EI |
23 | target_ulong *page_size, uint32_t *fsr, |
24 | ARMMMUFaultInfo *fi); | |
7c2cb42b | 25 | |
37785977 EI |
26 | static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address, |
27 | int access_type, ARMMMUIdx mmu_idx, | |
28 | hwaddr *phys_ptr, MemTxAttrs *txattrs, int *prot, | |
29 | target_ulong *page_size_ptr, uint32_t *fsr, | |
30 | ARMMMUFaultInfo *fi); | |
31 | ||
7c2cb42b AF |
32 | /* Definitions for the PMCCNTR and PMCR registers */ |
33 | #define PMCRD 0x8 | |
34 | #define PMCRC 0x4 | |
35 | #define PMCRE 0x1 | |
4a501606 PM |
36 | #endif |
37 | ||
0ecb72a5 | 38 | static int vfp_gdb_get_reg(CPUARMState *env, uint8_t *buf, int reg) |
56aebc89 PB |
39 | { |
40 | int nregs; | |
41 | ||
42 | /* VFP data registers are always little-endian. */ | |
43 | nregs = arm_feature(env, ARM_FEATURE_VFP3) ? 32 : 16; | |
44 | if (reg < nregs) { | |
45 | stfq_le_p(buf, env->vfp.regs[reg]); | |
46 | return 8; | |
47 | } | |
48 | if (arm_feature(env, ARM_FEATURE_NEON)) { | |
49 | /* Aliases for Q regs. */ | |
50 | nregs += 16; | |
51 | if (reg < nregs) { | |
52 | stfq_le_p(buf, env->vfp.regs[(reg - 32) * 2]); | |
53 | stfq_le_p(buf + 8, env->vfp.regs[(reg - 32) * 2 + 1]); | |
54 | return 16; | |
55 | } | |
56 | } | |
57 | switch (reg - nregs) { | |
58 | case 0: stl_p(buf, env->vfp.xregs[ARM_VFP_FPSID]); return 4; | |
59 | case 1: stl_p(buf, env->vfp.xregs[ARM_VFP_FPSCR]); return 4; | |
60 | case 2: stl_p(buf, env->vfp.xregs[ARM_VFP_FPEXC]); return 4; | |
61 | } | |
62 | return 0; | |
63 | } | |
64 | ||
0ecb72a5 | 65 | static int vfp_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg) |
56aebc89 PB |
66 | { |
67 | int nregs; | |
68 | ||
69 | nregs = arm_feature(env, ARM_FEATURE_VFP3) ? 32 : 16; | |
70 | if (reg < nregs) { | |
71 | env->vfp.regs[reg] = ldfq_le_p(buf); | |
72 | return 8; | |
73 | } | |
74 | if (arm_feature(env, ARM_FEATURE_NEON)) { | |
75 | nregs += 16; | |
76 | if (reg < nregs) { | |
77 | env->vfp.regs[(reg - 32) * 2] = ldfq_le_p(buf); | |
78 | env->vfp.regs[(reg - 32) * 2 + 1] = ldfq_le_p(buf + 8); | |
79 | return 16; | |
80 | } | |
81 | } | |
82 | switch (reg - nregs) { | |
83 | case 0: env->vfp.xregs[ARM_VFP_FPSID] = ldl_p(buf); return 4; | |
84 | case 1: env->vfp.xregs[ARM_VFP_FPSCR] = ldl_p(buf); return 4; | |
71b3c3de | 85 | case 2: env->vfp.xregs[ARM_VFP_FPEXC] = ldl_p(buf) & (1 << 30); return 4; |
56aebc89 PB |
86 | } |
87 | return 0; | |
88 | } | |
89 | ||
6a669427 PM |
90 | static int aarch64_fpu_gdb_get_reg(CPUARMState *env, uint8_t *buf, int reg) |
91 | { | |
92 | switch (reg) { | |
93 | case 0 ... 31: | |
94 | /* 128 bit FP register */ | |
95 | stfq_le_p(buf, env->vfp.regs[reg * 2]); | |
96 | stfq_le_p(buf + 8, env->vfp.regs[reg * 2 + 1]); | |
97 | return 16; | |
98 | case 32: | |
99 | /* FPSR */ | |
100 | stl_p(buf, vfp_get_fpsr(env)); | |
101 | return 4; | |
102 | case 33: | |
103 | /* FPCR */ | |
104 | stl_p(buf, vfp_get_fpcr(env)); | |
105 | return 4; | |
106 | default: | |
107 | return 0; | |
108 | } | |
109 | } | |
110 | ||
111 | static int aarch64_fpu_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg) | |
112 | { | |
113 | switch (reg) { | |
114 | case 0 ... 31: | |
115 | /* 128 bit FP register */ | |
116 | env->vfp.regs[reg * 2] = ldfq_le_p(buf); | |
117 | env->vfp.regs[reg * 2 + 1] = ldfq_le_p(buf + 8); | |
118 | return 16; | |
119 | case 32: | |
120 | /* FPSR */ | |
121 | vfp_set_fpsr(env, ldl_p(buf)); | |
122 | return 4; | |
123 | case 33: | |
124 | /* FPCR */ | |
125 | vfp_set_fpcr(env, ldl_p(buf)); | |
126 | return 4; | |
127 | default: | |
128 | return 0; | |
129 | } | |
130 | } | |
131 | ||
c4241c7d | 132 | static uint64_t raw_read(CPUARMState *env, const ARMCPRegInfo *ri) |
d4e6df63 | 133 | { |
375421cc | 134 | assert(ri->fieldoffset); |
67ed771d | 135 | if (cpreg_field_is_64bit(ri)) { |
c4241c7d | 136 | return CPREG_FIELD64(env, ri); |
22d9e1a9 | 137 | } else { |
c4241c7d | 138 | return CPREG_FIELD32(env, ri); |
22d9e1a9 | 139 | } |
d4e6df63 PM |
140 | } |
141 | ||
c4241c7d PM |
142 | static void raw_write(CPUARMState *env, const ARMCPRegInfo *ri, |
143 | uint64_t value) | |
d4e6df63 | 144 | { |
375421cc | 145 | assert(ri->fieldoffset); |
67ed771d | 146 | if (cpreg_field_is_64bit(ri)) { |
22d9e1a9 PM |
147 | CPREG_FIELD64(env, ri) = value; |
148 | } else { | |
149 | CPREG_FIELD32(env, ri) = value; | |
150 | } | |
d4e6df63 PM |
151 | } |
152 | ||
11f136ee FA |
153 | static void *raw_ptr(CPUARMState *env, const ARMCPRegInfo *ri) |
154 | { | |
155 | return (char *)env + ri->fieldoffset; | |
156 | } | |
157 | ||
49a66191 | 158 | uint64_t read_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri) |
721fae12 | 159 | { |
59a1c327 | 160 | /* Raw read of a coprocessor register (as needed for migration, etc). */ |
721fae12 | 161 | if (ri->type & ARM_CP_CONST) { |
59a1c327 | 162 | return ri->resetvalue; |
721fae12 | 163 | } else if (ri->raw_readfn) { |
59a1c327 | 164 | return ri->raw_readfn(env, ri); |
721fae12 | 165 | } else if (ri->readfn) { |
59a1c327 | 166 | return ri->readfn(env, ri); |
721fae12 | 167 | } else { |
59a1c327 | 168 | return raw_read(env, ri); |
721fae12 | 169 | } |
721fae12 PM |
170 | } |
171 | ||
59a1c327 | 172 | static void write_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri, |
7900e9f1 | 173 | uint64_t v) |
721fae12 PM |
174 | { |
175 | /* Raw write of a coprocessor register (as needed for migration, etc). | |
721fae12 PM |
176 | * Note that constant registers are treated as write-ignored; the |
177 | * caller should check for success by whether a readback gives the | |
178 | * value written. | |
179 | */ | |
180 | if (ri->type & ARM_CP_CONST) { | |
59a1c327 | 181 | return; |
721fae12 | 182 | } else if (ri->raw_writefn) { |
c4241c7d | 183 | ri->raw_writefn(env, ri, v); |
721fae12 | 184 | } else if (ri->writefn) { |
c4241c7d | 185 | ri->writefn(env, ri, v); |
721fae12 | 186 | } else { |
afb2530f | 187 | raw_write(env, ri, v); |
721fae12 | 188 | } |
721fae12 PM |
189 | } |
190 | ||
375421cc PM |
191 | static bool raw_accessors_invalid(const ARMCPRegInfo *ri) |
192 | { | |
193 | /* Return true if the regdef would cause an assertion if you called | |
194 | * read_raw_cp_reg() or write_raw_cp_reg() on it (ie if it is a | |
195 | * program bug for it not to have the NO_RAW flag). | |
196 | * NB that returning false here doesn't necessarily mean that calling | |
197 | * read/write_raw_cp_reg() is safe, because we can't distinguish "has | |
198 | * read/write access functions which are safe for raw use" from "has | |
199 | * read/write access functions which have side effects but has forgotten | |
200 | * to provide raw access functions". | |
201 | * The tests here line up with the conditions in read/write_raw_cp_reg() | |
202 | * and assertions in raw_read()/raw_write(). | |
203 | */ | |
204 | if ((ri->type & ARM_CP_CONST) || | |
205 | ri->fieldoffset || | |
206 | ((ri->raw_writefn || ri->writefn) && (ri->raw_readfn || ri->readfn))) { | |
207 | return false; | |
208 | } | |
209 | return true; | |
210 | } | |
211 | ||
721fae12 PM |
212 | bool write_cpustate_to_list(ARMCPU *cpu) |
213 | { | |
214 | /* Write the coprocessor state from cpu->env to the (index,value) list. */ | |
215 | int i; | |
216 | bool ok = true; | |
217 | ||
218 | for (i = 0; i < cpu->cpreg_array_len; i++) { | |
219 | uint32_t regidx = kvm_to_cpreg_id(cpu->cpreg_indexes[i]); | |
220 | const ARMCPRegInfo *ri; | |
59a1c327 | 221 | |
60322b39 | 222 | ri = get_arm_cp_reginfo(cpu->cp_regs, regidx); |
721fae12 PM |
223 | if (!ri) { |
224 | ok = false; | |
225 | continue; | |
226 | } | |
7a0e58fa | 227 | if (ri->type & ARM_CP_NO_RAW) { |
721fae12 PM |
228 | continue; |
229 | } | |
59a1c327 | 230 | cpu->cpreg_values[i] = read_raw_cp_reg(&cpu->env, ri); |
721fae12 PM |
231 | } |
232 | return ok; | |
233 | } | |
234 | ||
235 | bool write_list_to_cpustate(ARMCPU *cpu) | |
236 | { | |
237 | int i; | |
238 | bool ok = true; | |
239 | ||
240 | for (i = 0; i < cpu->cpreg_array_len; i++) { | |
241 | uint32_t regidx = kvm_to_cpreg_id(cpu->cpreg_indexes[i]); | |
242 | uint64_t v = cpu->cpreg_values[i]; | |
721fae12 PM |
243 | const ARMCPRegInfo *ri; |
244 | ||
60322b39 | 245 | ri = get_arm_cp_reginfo(cpu->cp_regs, regidx); |
721fae12 PM |
246 | if (!ri) { |
247 | ok = false; | |
248 | continue; | |
249 | } | |
7a0e58fa | 250 | if (ri->type & ARM_CP_NO_RAW) { |
721fae12 PM |
251 | continue; |
252 | } | |
253 | /* Write value and confirm it reads back as written | |
254 | * (to catch read-only registers and partially read-only | |
255 | * registers where the incoming migration value doesn't match) | |
256 | */ | |
59a1c327 PM |
257 | write_raw_cp_reg(&cpu->env, ri, v); |
258 | if (read_raw_cp_reg(&cpu->env, ri) != v) { | |
721fae12 PM |
259 | ok = false; |
260 | } | |
261 | } | |
262 | return ok; | |
263 | } | |
264 | ||
265 | static void add_cpreg_to_list(gpointer key, gpointer opaque) | |
266 | { | |
267 | ARMCPU *cpu = opaque; | |
268 | uint64_t regidx; | |
269 | const ARMCPRegInfo *ri; | |
270 | ||
271 | regidx = *(uint32_t *)key; | |
60322b39 | 272 | ri = get_arm_cp_reginfo(cpu->cp_regs, regidx); |
721fae12 | 273 | |
7a0e58fa | 274 | if (!(ri->type & (ARM_CP_NO_RAW|ARM_CP_ALIAS))) { |
721fae12 PM |
275 | cpu->cpreg_indexes[cpu->cpreg_array_len] = cpreg_to_kvm_id(regidx); |
276 | /* The value array need not be initialized at this point */ | |
277 | cpu->cpreg_array_len++; | |
278 | } | |
279 | } | |
280 | ||
281 | static void count_cpreg(gpointer key, gpointer opaque) | |
282 | { | |
283 | ARMCPU *cpu = opaque; | |
284 | uint64_t regidx; | |
285 | const ARMCPRegInfo *ri; | |
286 | ||
287 | regidx = *(uint32_t *)key; | |
60322b39 | 288 | ri = get_arm_cp_reginfo(cpu->cp_regs, regidx); |
721fae12 | 289 | |
7a0e58fa | 290 | if (!(ri->type & (ARM_CP_NO_RAW|ARM_CP_ALIAS))) { |
721fae12 PM |
291 | cpu->cpreg_array_len++; |
292 | } | |
293 | } | |
294 | ||
295 | static gint cpreg_key_compare(gconstpointer a, gconstpointer b) | |
296 | { | |
cbf239b7 AR |
297 | uint64_t aidx = cpreg_to_kvm_id(*(uint32_t *)a); |
298 | uint64_t bidx = cpreg_to_kvm_id(*(uint32_t *)b); | |
721fae12 | 299 | |
cbf239b7 AR |
300 | if (aidx > bidx) { |
301 | return 1; | |
302 | } | |
303 | if (aidx < bidx) { | |
304 | return -1; | |
305 | } | |
306 | return 0; | |
721fae12 PM |
307 | } |
308 | ||
309 | void init_cpreg_list(ARMCPU *cpu) | |
310 | { | |
311 | /* Initialise the cpreg_tuples[] array based on the cp_regs hash. | |
312 | * Note that we require cpreg_tuples[] to be sorted by key ID. | |
313 | */ | |
57b6d95e | 314 | GList *keys; |
721fae12 PM |
315 | int arraylen; |
316 | ||
57b6d95e | 317 | keys = g_hash_table_get_keys(cpu->cp_regs); |
721fae12 PM |
318 | keys = g_list_sort(keys, cpreg_key_compare); |
319 | ||
320 | cpu->cpreg_array_len = 0; | |
321 | ||
322 | g_list_foreach(keys, count_cpreg, cpu); | |
323 | ||
324 | arraylen = cpu->cpreg_array_len; | |
325 | cpu->cpreg_indexes = g_new(uint64_t, arraylen); | |
326 | cpu->cpreg_values = g_new(uint64_t, arraylen); | |
327 | cpu->cpreg_vmstate_indexes = g_new(uint64_t, arraylen); | |
328 | cpu->cpreg_vmstate_values = g_new(uint64_t, arraylen); | |
329 | cpu->cpreg_vmstate_array_len = cpu->cpreg_array_len; | |
330 | cpu->cpreg_array_len = 0; | |
331 | ||
332 | g_list_foreach(keys, add_cpreg_to_list, cpu); | |
333 | ||
334 | assert(cpu->cpreg_array_len == arraylen); | |
335 | ||
336 | g_list_free(keys); | |
337 | } | |
338 | ||
68e9c2fe EI |
339 | /* |
340 | * Some registers are not accessible if EL3.NS=0 and EL3 is using AArch32 but | |
341 | * they are accessible when EL3 is using AArch64 regardless of EL3.NS. | |
342 | * | |
343 | * access_el3_aa32ns: Used to check AArch32 register views. | |
344 | * access_el3_aa32ns_aa64any: Used to check both AArch32/64 register views. | |
345 | */ | |
346 | static CPAccessResult access_el3_aa32ns(CPUARMState *env, | |
3f208fd7 PM |
347 | const ARMCPRegInfo *ri, |
348 | bool isread) | |
68e9c2fe EI |
349 | { |
350 | bool secure = arm_is_secure_below_el3(env); | |
351 | ||
352 | assert(!arm_el_is_aa64(env, 3)); | |
353 | if (secure) { | |
354 | return CP_ACCESS_TRAP_UNCATEGORIZED; | |
355 | } | |
356 | return CP_ACCESS_OK; | |
357 | } | |
358 | ||
359 | static CPAccessResult access_el3_aa32ns_aa64any(CPUARMState *env, | |
3f208fd7 PM |
360 | const ARMCPRegInfo *ri, |
361 | bool isread) | |
68e9c2fe EI |
362 | { |
363 | if (!arm_el_is_aa64(env, 3)) { | |
3f208fd7 | 364 | return access_el3_aa32ns(env, ri, isread); |
68e9c2fe EI |
365 | } |
366 | return CP_ACCESS_OK; | |
367 | } | |
368 | ||
5513c3ab PM |
369 | /* Some secure-only AArch32 registers trap to EL3 if used from |
370 | * Secure EL1 (but are just ordinary UNDEF in other non-EL3 contexts). | |
371 | * Note that an access from Secure EL1 can only happen if EL3 is AArch64. | |
372 | * We assume that the .access field is set to PL1_RW. | |
373 | */ | |
374 | static CPAccessResult access_trap_aa32s_el1(CPUARMState *env, | |
3f208fd7 PM |
375 | const ARMCPRegInfo *ri, |
376 | bool isread) | |
5513c3ab PM |
377 | { |
378 | if (arm_current_el(env) == 3) { | |
379 | return CP_ACCESS_OK; | |
380 | } | |
381 | if (arm_is_secure_below_el3(env)) { | |
382 | return CP_ACCESS_TRAP_EL3; | |
383 | } | |
384 | /* This will be EL1 NS and EL2 NS, which just UNDEF */ | |
385 | return CP_ACCESS_TRAP_UNCATEGORIZED; | |
386 | } | |
387 | ||
187f678d PM |
388 | /* Check for traps to "powerdown debug" registers, which are controlled |
389 | * by MDCR.TDOSA | |
390 | */ | |
391 | static CPAccessResult access_tdosa(CPUARMState *env, const ARMCPRegInfo *ri, | |
392 | bool isread) | |
393 | { | |
394 | int el = arm_current_el(env); | |
395 | ||
396 | if (el < 2 && (env->cp15.mdcr_el2 & MDCR_TDOSA) | |
397 | && !arm_is_secure_below_el3(env)) { | |
398 | return CP_ACCESS_TRAP_EL2; | |
399 | } | |
400 | if (el < 3 && (env->cp15.mdcr_el3 & MDCR_TDOSA)) { | |
401 | return CP_ACCESS_TRAP_EL3; | |
402 | } | |
403 | return CP_ACCESS_OK; | |
404 | } | |
405 | ||
91b0a238 PM |
406 | /* Check for traps to "debug ROM" registers, which are controlled |
407 | * by MDCR_EL2.TDRA for EL2 but by the more general MDCR_EL3.TDA for EL3. | |
408 | */ | |
409 | static CPAccessResult access_tdra(CPUARMState *env, const ARMCPRegInfo *ri, | |
410 | bool isread) | |
411 | { | |
412 | int el = arm_current_el(env); | |
413 | ||
414 | if (el < 2 && (env->cp15.mdcr_el2 & MDCR_TDRA) | |
415 | && !arm_is_secure_below_el3(env)) { | |
416 | return CP_ACCESS_TRAP_EL2; | |
417 | } | |
418 | if (el < 3 && (env->cp15.mdcr_el3 & MDCR_TDA)) { | |
419 | return CP_ACCESS_TRAP_EL3; | |
420 | } | |
421 | return CP_ACCESS_OK; | |
422 | } | |
423 | ||
d6c8cf81 PM |
424 | /* Check for traps to general debug registers, which are controlled |
425 | * by MDCR_EL2.TDA for EL2 and MDCR_EL3.TDA for EL3. | |
426 | */ | |
427 | static CPAccessResult access_tda(CPUARMState *env, const ARMCPRegInfo *ri, | |
428 | bool isread) | |
429 | { | |
430 | int el = arm_current_el(env); | |
431 | ||
432 | if (el < 2 && (env->cp15.mdcr_el2 & MDCR_TDA) | |
433 | && !arm_is_secure_below_el3(env)) { | |
434 | return CP_ACCESS_TRAP_EL2; | |
435 | } | |
436 | if (el < 3 && (env->cp15.mdcr_el3 & MDCR_TDA)) { | |
437 | return CP_ACCESS_TRAP_EL3; | |
438 | } | |
439 | return CP_ACCESS_OK; | |
440 | } | |
441 | ||
c4241c7d | 442 | static void dacr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) |
c983fe6c | 443 | { |
00c8cb0a AF |
444 | ARMCPU *cpu = arm_env_get_cpu(env); |
445 | ||
8d5c773e | 446 | raw_write(env, ri, value); |
00c8cb0a | 447 | tlb_flush(CPU(cpu), 1); /* Flush TLB as domain not tracked in TLB */ |
c983fe6c PM |
448 | } |
449 | ||
c4241c7d | 450 | static void fcse_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) |
08de207b | 451 | { |
00c8cb0a AF |
452 | ARMCPU *cpu = arm_env_get_cpu(env); |
453 | ||
8d5c773e | 454 | if (raw_read(env, ri) != value) { |
08de207b PM |
455 | /* Unlike real hardware the qemu TLB uses virtual addresses, |
456 | * not modified virtual addresses, so this causes a TLB flush. | |
457 | */ | |
00c8cb0a | 458 | tlb_flush(CPU(cpu), 1); |
8d5c773e | 459 | raw_write(env, ri, value); |
08de207b | 460 | } |
08de207b | 461 | } |
c4241c7d PM |
462 | |
463 | static void contextidr_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
464 | uint64_t value) | |
08de207b | 465 | { |
00c8cb0a AF |
466 | ARMCPU *cpu = arm_env_get_cpu(env); |
467 | ||
8d5c773e | 468 | if (raw_read(env, ri) != value && !arm_feature(env, ARM_FEATURE_MPU) |
014406b5 | 469 | && !extended_addresses_enabled(env)) { |
08de207b PM |
470 | /* For VMSA (when not using the LPAE long descriptor page table |
471 | * format) this register includes the ASID, so do a TLB flush. | |
472 | * For PMSA it is purely a process ID and no action is needed. | |
473 | */ | |
00c8cb0a | 474 | tlb_flush(CPU(cpu), 1); |
08de207b | 475 | } |
8d5c773e | 476 | raw_write(env, ri, value); |
08de207b PM |
477 | } |
478 | ||
c4241c7d PM |
479 | static void tlbiall_write(CPUARMState *env, const ARMCPRegInfo *ri, |
480 | uint64_t value) | |
d929823f PM |
481 | { |
482 | /* Invalidate all (TLBIALL) */ | |
00c8cb0a AF |
483 | ARMCPU *cpu = arm_env_get_cpu(env); |
484 | ||
485 | tlb_flush(CPU(cpu), 1); | |
d929823f PM |
486 | } |
487 | ||
c4241c7d PM |
488 | static void tlbimva_write(CPUARMState *env, const ARMCPRegInfo *ri, |
489 | uint64_t value) | |
d929823f PM |
490 | { |
491 | /* Invalidate single TLB entry by MVA and ASID (TLBIMVA) */ | |
31b030d4 AF |
492 | ARMCPU *cpu = arm_env_get_cpu(env); |
493 | ||
494 | tlb_flush_page(CPU(cpu), value & TARGET_PAGE_MASK); | |
d929823f PM |
495 | } |
496 | ||
c4241c7d PM |
497 | static void tlbiasid_write(CPUARMState *env, const ARMCPRegInfo *ri, |
498 | uint64_t value) | |
d929823f PM |
499 | { |
500 | /* Invalidate by ASID (TLBIASID) */ | |
00c8cb0a AF |
501 | ARMCPU *cpu = arm_env_get_cpu(env); |
502 | ||
503 | tlb_flush(CPU(cpu), value == 0); | |
d929823f PM |
504 | } |
505 | ||
c4241c7d PM |
506 | static void tlbimvaa_write(CPUARMState *env, const ARMCPRegInfo *ri, |
507 | uint64_t value) | |
d929823f PM |
508 | { |
509 | /* Invalidate single entry by MVA, all ASIDs (TLBIMVAA) */ | |
31b030d4 AF |
510 | ARMCPU *cpu = arm_env_get_cpu(env); |
511 | ||
512 | tlb_flush_page(CPU(cpu), value & TARGET_PAGE_MASK); | |
d929823f PM |
513 | } |
514 | ||
fa439fc5 PM |
515 | /* IS variants of TLB operations must affect all cores */ |
516 | static void tlbiall_is_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
517 | uint64_t value) | |
518 | { | |
519 | CPUState *other_cs; | |
520 | ||
521 | CPU_FOREACH(other_cs) { | |
522 | tlb_flush(other_cs, 1); | |
523 | } | |
524 | } | |
525 | ||
526 | static void tlbiasid_is_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
527 | uint64_t value) | |
528 | { | |
529 | CPUState *other_cs; | |
530 | ||
531 | CPU_FOREACH(other_cs) { | |
532 | tlb_flush(other_cs, value == 0); | |
533 | } | |
534 | } | |
535 | ||
536 | static void tlbimva_is_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
537 | uint64_t value) | |
538 | { | |
539 | CPUState *other_cs; | |
540 | ||
541 | CPU_FOREACH(other_cs) { | |
542 | tlb_flush_page(other_cs, value & TARGET_PAGE_MASK); | |
543 | } | |
544 | } | |
545 | ||
546 | static void tlbimvaa_is_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
547 | uint64_t value) | |
548 | { | |
549 | CPUState *other_cs; | |
550 | ||
551 | CPU_FOREACH(other_cs) { | |
552 | tlb_flush_page(other_cs, value & TARGET_PAGE_MASK); | |
553 | } | |
554 | } | |
555 | ||
e9aa6c21 | 556 | static const ARMCPRegInfo cp_reginfo[] = { |
54bf36ed FA |
557 | /* Define the secure and non-secure FCSE identifier CP registers |
558 | * separately because there is no secure bank in V8 (no _EL3). This allows | |
559 | * the secure register to be properly reset and migrated. There is also no | |
560 | * v8 EL1 version of the register so the non-secure instance stands alone. | |
561 | */ | |
562 | { .name = "FCSEIDR(NS)", | |
563 | .cp = 15, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 0, | |
564 | .access = PL1_RW, .secure = ARM_CP_SECSTATE_NS, | |
565 | .fieldoffset = offsetof(CPUARMState, cp15.fcseidr_ns), | |
566 | .resetvalue = 0, .writefn = fcse_write, .raw_writefn = raw_write, }, | |
567 | { .name = "FCSEIDR(S)", | |
568 | .cp = 15, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 0, | |
569 | .access = PL1_RW, .secure = ARM_CP_SECSTATE_S, | |
570 | .fieldoffset = offsetof(CPUARMState, cp15.fcseidr_s), | |
d4e6df63 | 571 | .resetvalue = 0, .writefn = fcse_write, .raw_writefn = raw_write, }, |
54bf36ed FA |
572 | /* Define the secure and non-secure context identifier CP registers |
573 | * separately because there is no secure bank in V8 (no _EL3). This allows | |
574 | * the secure register to be properly reset and migrated. In the | |
575 | * non-secure case, the 32-bit register will have reset and migration | |
576 | * disabled during registration as it is handled by the 64-bit instance. | |
577 | */ | |
578 | { .name = "CONTEXTIDR_EL1", .state = ARM_CP_STATE_BOTH, | |
014406b5 | 579 | .opc0 = 3, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 1, |
54bf36ed FA |
580 | .access = PL1_RW, .secure = ARM_CP_SECSTATE_NS, |
581 | .fieldoffset = offsetof(CPUARMState, cp15.contextidr_el[1]), | |
582 | .resetvalue = 0, .writefn = contextidr_write, .raw_writefn = raw_write, }, | |
583 | { .name = "CONTEXTIDR(S)", .state = ARM_CP_STATE_AA32, | |
584 | .cp = 15, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 1, | |
585 | .access = PL1_RW, .secure = ARM_CP_SECSTATE_S, | |
586 | .fieldoffset = offsetof(CPUARMState, cp15.contextidr_s), | |
d4e6df63 | 587 | .resetvalue = 0, .writefn = contextidr_write, .raw_writefn = raw_write, }, |
9449fdf6 PM |
588 | REGINFO_SENTINEL |
589 | }; | |
590 | ||
591 | static const ARMCPRegInfo not_v8_cp_reginfo[] = { | |
592 | /* NB: Some of these registers exist in v8 but with more precise | |
593 | * definitions that don't use CP_ANY wildcards (mostly in v8_cp_reginfo[]). | |
594 | */ | |
595 | /* MMU Domain access control / MPU write buffer control */ | |
0c17d68c FA |
596 | { .name = "DACR", |
597 | .cp = 15, .opc1 = CP_ANY, .crn = 3, .crm = CP_ANY, .opc2 = CP_ANY, | |
598 | .access = PL1_RW, .resetvalue = 0, | |
599 | .writefn = dacr_write, .raw_writefn = raw_write, | |
600 | .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.dacr_s), | |
601 | offsetoflow32(CPUARMState, cp15.dacr_ns) } }, | |
a903c449 EI |
602 | /* ARMv7 allocates a range of implementation defined TLB LOCKDOWN regs. |
603 | * For v6 and v5, these mappings are overly broad. | |
4fdd17dd | 604 | */ |
a903c449 EI |
605 | { .name = "TLB_LOCKDOWN", .cp = 15, .crn = 10, .crm = 0, |
606 | .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_NOP }, | |
607 | { .name = "TLB_LOCKDOWN", .cp = 15, .crn = 10, .crm = 1, | |
608 | .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_NOP }, | |
609 | { .name = "TLB_LOCKDOWN", .cp = 15, .crn = 10, .crm = 4, | |
610 | .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_NOP }, | |
611 | { .name = "TLB_LOCKDOWN", .cp = 15, .crn = 10, .crm = 8, | |
4fdd17dd | 612 | .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_NOP }, |
c4804214 PM |
613 | /* Cache maintenance ops; some of this space may be overridden later. */ |
614 | { .name = "CACHEMAINT", .cp = 15, .crn = 7, .crm = CP_ANY, | |
615 | .opc1 = 0, .opc2 = CP_ANY, .access = PL1_W, | |
616 | .type = ARM_CP_NOP | ARM_CP_OVERRIDE }, | |
e9aa6c21 PM |
617 | REGINFO_SENTINEL |
618 | }; | |
619 | ||
7d57f408 PM |
620 | static const ARMCPRegInfo not_v6_cp_reginfo[] = { |
621 | /* Not all pre-v6 cores implemented this WFI, so this is slightly | |
622 | * over-broad. | |
623 | */ | |
624 | { .name = "WFI_v5", .cp = 15, .crn = 7, .crm = 8, .opc1 = 0, .opc2 = 2, | |
625 | .access = PL1_W, .type = ARM_CP_WFI }, | |
626 | REGINFO_SENTINEL | |
627 | }; | |
628 | ||
629 | static const ARMCPRegInfo not_v7_cp_reginfo[] = { | |
630 | /* Standard v6 WFI (also used in some pre-v6 cores); not in v7 (which | |
631 | * is UNPREDICTABLE; we choose to NOP as most implementations do). | |
632 | */ | |
633 | { .name = "WFI_v6", .cp = 15, .crn = 7, .crm = 0, .opc1 = 0, .opc2 = 4, | |
634 | .access = PL1_W, .type = ARM_CP_WFI }, | |
34f90529 PM |
635 | /* L1 cache lockdown. Not architectural in v6 and earlier but in practice |
636 | * implemented in 926, 946, 1026, 1136, 1176 and 11MPCore. StrongARM and | |
637 | * OMAPCP will override this space. | |
638 | */ | |
639 | { .name = "DLOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 0, .opc2 = 0, | |
640 | .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_data), | |
641 | .resetvalue = 0 }, | |
642 | { .name = "ILOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 0, .opc2 = 1, | |
643 | .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_insn), | |
644 | .resetvalue = 0 }, | |
776d4e5c PM |
645 | /* v6 doesn't have the cache ID registers but Linux reads them anyway */ |
646 | { .name = "DUMMY", .cp = 15, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = CP_ANY, | |
7a0e58fa | 647 | .access = PL1_R, .type = ARM_CP_CONST | ARM_CP_NO_RAW, |
d4e6df63 | 648 | .resetvalue = 0 }, |
50300698 PM |
649 | /* We don't implement pre-v7 debug but most CPUs had at least a DBGDIDR; |
650 | * implementing it as RAZ means the "debug architecture version" bits | |
651 | * will read as a reserved value, which should cause Linux to not try | |
652 | * to use the debug hardware. | |
653 | */ | |
654 | { .name = "DBGDIDR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 0, | |
655 | .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
995939a6 PM |
656 | /* MMU TLB control. Note that the wildcarding means we cover not just |
657 | * the unified TLB ops but also the dside/iside/inner-shareable variants. | |
658 | */ | |
659 | { .name = "TLBIALL", .cp = 15, .crn = 8, .crm = CP_ANY, | |
660 | .opc1 = CP_ANY, .opc2 = 0, .access = PL1_W, .writefn = tlbiall_write, | |
7a0e58fa | 661 | .type = ARM_CP_NO_RAW }, |
995939a6 PM |
662 | { .name = "TLBIMVA", .cp = 15, .crn = 8, .crm = CP_ANY, |
663 | .opc1 = CP_ANY, .opc2 = 1, .access = PL1_W, .writefn = tlbimva_write, | |
7a0e58fa | 664 | .type = ARM_CP_NO_RAW }, |
995939a6 PM |
665 | { .name = "TLBIASID", .cp = 15, .crn = 8, .crm = CP_ANY, |
666 | .opc1 = CP_ANY, .opc2 = 2, .access = PL1_W, .writefn = tlbiasid_write, | |
7a0e58fa | 667 | .type = ARM_CP_NO_RAW }, |
995939a6 PM |
668 | { .name = "TLBIMVAA", .cp = 15, .crn = 8, .crm = CP_ANY, |
669 | .opc1 = CP_ANY, .opc2 = 3, .access = PL1_W, .writefn = tlbimvaa_write, | |
7a0e58fa | 670 | .type = ARM_CP_NO_RAW }, |
a903c449 EI |
671 | { .name = "PRRR", .cp = 15, .crn = 10, .crm = 2, |
672 | .opc1 = 0, .opc2 = 0, .access = PL1_RW, .type = ARM_CP_NOP }, | |
673 | { .name = "NMRR", .cp = 15, .crn = 10, .crm = 2, | |
674 | .opc1 = 0, .opc2 = 1, .access = PL1_RW, .type = ARM_CP_NOP }, | |
7d57f408 PM |
675 | REGINFO_SENTINEL |
676 | }; | |
677 | ||
c4241c7d PM |
678 | static void cpacr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
679 | uint64_t value) | |
2771db27 | 680 | { |
f0aff255 FA |
681 | uint32_t mask = 0; |
682 | ||
683 | /* In ARMv8 most bits of CPACR_EL1 are RES0. */ | |
684 | if (!arm_feature(env, ARM_FEATURE_V8)) { | |
685 | /* ARMv7 defines bits for unimplemented coprocessors as RAZ/WI. | |
686 | * ASEDIS [31] and D32DIS [30] are both UNK/SBZP without VFP. | |
687 | * TRCDIS [28] is RAZ/WI since we do not implement a trace macrocell. | |
688 | */ | |
689 | if (arm_feature(env, ARM_FEATURE_VFP)) { | |
690 | /* VFP coprocessor: cp10 & cp11 [23:20] */ | |
691 | mask |= (1 << 31) | (1 << 30) | (0xf << 20); | |
692 | ||
693 | if (!arm_feature(env, ARM_FEATURE_NEON)) { | |
694 | /* ASEDIS [31] bit is RAO/WI */ | |
695 | value |= (1 << 31); | |
696 | } | |
697 | ||
698 | /* VFPv3 and upwards with NEON implement 32 double precision | |
699 | * registers (D0-D31). | |
700 | */ | |
701 | if (!arm_feature(env, ARM_FEATURE_NEON) || | |
702 | !arm_feature(env, ARM_FEATURE_VFP3)) { | |
703 | /* D32DIS [30] is RAO/WI if D16-31 are not implemented. */ | |
704 | value |= (1 << 30); | |
705 | } | |
706 | } | |
707 | value &= mask; | |
2771db27 | 708 | } |
7ebd5f2e | 709 | env->cp15.cpacr_el1 = value; |
2771db27 PM |
710 | } |
711 | ||
3f208fd7 PM |
712 | static CPAccessResult cpacr_access(CPUARMState *env, const ARMCPRegInfo *ri, |
713 | bool isread) | |
c6f19164 GB |
714 | { |
715 | if (arm_feature(env, ARM_FEATURE_V8)) { | |
716 | /* Check if CPACR accesses are to be trapped to EL2 */ | |
717 | if (arm_current_el(env) == 1 && | |
718 | (env->cp15.cptr_el[2] & CPTR_TCPAC) && !arm_is_secure(env)) { | |
719 | return CP_ACCESS_TRAP_EL2; | |
720 | /* Check if CPACR accesses are to be trapped to EL3 */ | |
721 | } else if (arm_current_el(env) < 3 && | |
722 | (env->cp15.cptr_el[3] & CPTR_TCPAC)) { | |
723 | return CP_ACCESS_TRAP_EL3; | |
724 | } | |
725 | } | |
726 | ||
727 | return CP_ACCESS_OK; | |
728 | } | |
729 | ||
3f208fd7 PM |
730 | static CPAccessResult cptr_access(CPUARMState *env, const ARMCPRegInfo *ri, |
731 | bool isread) | |
c6f19164 GB |
732 | { |
733 | /* Check if CPTR accesses are set to trap to EL3 */ | |
734 | if (arm_current_el(env) == 2 && (env->cp15.cptr_el[3] & CPTR_TCPAC)) { | |
735 | return CP_ACCESS_TRAP_EL3; | |
736 | } | |
737 | ||
738 | return CP_ACCESS_OK; | |
739 | } | |
740 | ||
7d57f408 PM |
741 | static const ARMCPRegInfo v6_cp_reginfo[] = { |
742 | /* prefetch by MVA in v6, NOP in v7 */ | |
743 | { .name = "MVA_prefetch", | |
744 | .cp = 15, .crn = 7, .crm = 13, .opc1 = 0, .opc2 = 1, | |
745 | .access = PL1_W, .type = ARM_CP_NOP }, | |
6df99dec SS |
746 | /* We need to break the TB after ISB to execute self-modifying code |
747 | * correctly and also to take any pending interrupts immediately. | |
748 | * So use arm_cp_write_ignore() function instead of ARM_CP_NOP flag. | |
749 | */ | |
7d57f408 | 750 | { .name = "ISB", .cp = 15, .crn = 7, .crm = 5, .opc1 = 0, .opc2 = 4, |
6df99dec | 751 | .access = PL0_W, .type = ARM_CP_NO_RAW, .writefn = arm_cp_write_ignore }, |
091fd17c | 752 | { .name = "DSB", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 4, |
7d57f408 | 753 | .access = PL0_W, .type = ARM_CP_NOP }, |
091fd17c | 754 | { .name = "DMB", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 5, |
7d57f408 | 755 | .access = PL0_W, .type = ARM_CP_NOP }, |
06d76f31 | 756 | { .name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 2, |
6cd8a264 | 757 | .access = PL1_RW, |
b848ce2b FA |
758 | .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ifar_s), |
759 | offsetof(CPUARMState, cp15.ifar_ns) }, | |
06d76f31 PM |
760 | .resetvalue = 0, }, |
761 | /* Watchpoint Fault Address Register : should actually only be present | |
762 | * for 1136, 1176, 11MPCore. | |
763 | */ | |
764 | { .name = "WFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1, | |
765 | .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0, }, | |
34222fb8 | 766 | { .name = "CPACR", .state = ARM_CP_STATE_BOTH, .opc0 = 3, |
c6f19164 | 767 | .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 2, .accessfn = cpacr_access, |
7ebd5f2e | 768 | .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.cpacr_el1), |
2771db27 | 769 | .resetvalue = 0, .writefn = cpacr_write }, |
7d57f408 PM |
770 | REGINFO_SENTINEL |
771 | }; | |
772 | ||
3f208fd7 PM |
773 | static CPAccessResult pmreg_access(CPUARMState *env, const ARMCPRegInfo *ri, |
774 | bool isread) | |
200ac0ef | 775 | { |
3b163b01 | 776 | /* Performance monitor registers user accessibility is controlled |
fcd25206 | 777 | * by PMUSERENR. |
200ac0ef | 778 | */ |
dcbff19b | 779 | if (arm_current_el(env) == 0 && !env->cp15.c9_pmuserenr) { |
fcd25206 | 780 | return CP_ACCESS_TRAP; |
200ac0ef | 781 | } |
fcd25206 | 782 | return CP_ACCESS_OK; |
200ac0ef PM |
783 | } |
784 | ||
7c2cb42b | 785 | #ifndef CONFIG_USER_ONLY |
87124fde AF |
786 | |
787 | static inline bool arm_ccnt_enabled(CPUARMState *env) | |
788 | { | |
789 | /* This does not support checking PMCCFILTR_EL0 register */ | |
790 | ||
791 | if (!(env->cp15.c9_pmcr & PMCRE)) { | |
792 | return false; | |
793 | } | |
794 | ||
795 | return true; | |
796 | } | |
797 | ||
ec7b4ce4 AF |
798 | void pmccntr_sync(CPUARMState *env) |
799 | { | |
800 | uint64_t temp_ticks; | |
801 | ||
352c98e5 LV |
802 | temp_ticks = muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), |
803 | ARM_CPU_FREQ, NANOSECONDS_PER_SECOND); | |
ec7b4ce4 AF |
804 | |
805 | if (env->cp15.c9_pmcr & PMCRD) { | |
806 | /* Increment once every 64 processor clock cycles */ | |
807 | temp_ticks /= 64; | |
808 | } | |
809 | ||
810 | if (arm_ccnt_enabled(env)) { | |
811 | env->cp15.c15_ccnt = temp_ticks - env->cp15.c15_ccnt; | |
812 | } | |
813 | } | |
814 | ||
c4241c7d PM |
815 | static void pmcr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
816 | uint64_t value) | |
200ac0ef | 817 | { |
942a155b | 818 | pmccntr_sync(env); |
7c2cb42b AF |
819 | |
820 | if (value & PMCRC) { | |
821 | /* The counter has been reset */ | |
822 | env->cp15.c15_ccnt = 0; | |
823 | } | |
824 | ||
200ac0ef PM |
825 | /* only the DP, X, D and E bits are writable */ |
826 | env->cp15.c9_pmcr &= ~0x39; | |
827 | env->cp15.c9_pmcr |= (value & 0x39); | |
7c2cb42b | 828 | |
942a155b | 829 | pmccntr_sync(env); |
7c2cb42b AF |
830 | } |
831 | ||
832 | static uint64_t pmccntr_read(CPUARMState *env, const ARMCPRegInfo *ri) | |
833 | { | |
c92c0687 | 834 | uint64_t total_ticks; |
7c2cb42b | 835 | |
942a155b | 836 | if (!arm_ccnt_enabled(env)) { |
7c2cb42b AF |
837 | /* Counter is disabled, do not change value */ |
838 | return env->cp15.c15_ccnt; | |
839 | } | |
840 | ||
352c98e5 LV |
841 | total_ticks = muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), |
842 | ARM_CPU_FREQ, NANOSECONDS_PER_SECOND); | |
7c2cb42b AF |
843 | |
844 | if (env->cp15.c9_pmcr & PMCRD) { | |
845 | /* Increment once every 64 processor clock cycles */ | |
846 | total_ticks /= 64; | |
847 | } | |
848 | return total_ticks - env->cp15.c15_ccnt; | |
849 | } | |
850 | ||
851 | static void pmccntr_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
852 | uint64_t value) | |
853 | { | |
c92c0687 | 854 | uint64_t total_ticks; |
7c2cb42b | 855 | |
942a155b | 856 | if (!arm_ccnt_enabled(env)) { |
7c2cb42b AF |
857 | /* Counter is disabled, set the absolute value */ |
858 | env->cp15.c15_ccnt = value; | |
859 | return; | |
860 | } | |
861 | ||
352c98e5 LV |
862 | total_ticks = muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), |
863 | ARM_CPU_FREQ, NANOSECONDS_PER_SECOND); | |
7c2cb42b AF |
864 | |
865 | if (env->cp15.c9_pmcr & PMCRD) { | |
866 | /* Increment once every 64 processor clock cycles */ | |
867 | total_ticks /= 64; | |
868 | } | |
869 | env->cp15.c15_ccnt = total_ticks - value; | |
200ac0ef | 870 | } |
421c7ebd PC |
871 | |
872 | static void pmccntr_write32(CPUARMState *env, const ARMCPRegInfo *ri, | |
873 | uint64_t value) | |
874 | { | |
875 | uint64_t cur_val = pmccntr_read(env, NULL); | |
876 | ||
877 | pmccntr_write(env, ri, deposit64(cur_val, 0, 32, value)); | |
878 | } | |
879 | ||
ec7b4ce4 AF |
880 | #else /* CONFIG_USER_ONLY */ |
881 | ||
882 | void pmccntr_sync(CPUARMState *env) | |
883 | { | |
884 | } | |
885 | ||
7c2cb42b | 886 | #endif |
200ac0ef | 887 | |
0614601c AF |
888 | static void pmccfiltr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
889 | uint64_t value) | |
890 | { | |
891 | pmccntr_sync(env); | |
892 | env->cp15.pmccfiltr_el0 = value & 0x7E000000; | |
893 | pmccntr_sync(env); | |
894 | } | |
895 | ||
c4241c7d | 896 | static void pmcntenset_write(CPUARMState *env, const ARMCPRegInfo *ri, |
200ac0ef PM |
897 | uint64_t value) |
898 | { | |
200ac0ef PM |
899 | value &= (1 << 31); |
900 | env->cp15.c9_pmcnten |= value; | |
200ac0ef PM |
901 | } |
902 | ||
c4241c7d PM |
903 | static void pmcntenclr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
904 | uint64_t value) | |
200ac0ef | 905 | { |
200ac0ef PM |
906 | value &= (1 << 31); |
907 | env->cp15.c9_pmcnten &= ~value; | |
200ac0ef PM |
908 | } |
909 | ||
c4241c7d PM |
910 | static void pmovsr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
911 | uint64_t value) | |
200ac0ef | 912 | { |
200ac0ef | 913 | env->cp15.c9_pmovsr &= ~value; |
200ac0ef PM |
914 | } |
915 | ||
c4241c7d PM |
916 | static void pmxevtyper_write(CPUARMState *env, const ARMCPRegInfo *ri, |
917 | uint64_t value) | |
200ac0ef | 918 | { |
200ac0ef | 919 | env->cp15.c9_pmxevtyper = value & 0xff; |
200ac0ef PM |
920 | } |
921 | ||
c4241c7d | 922 | static void pmuserenr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
200ac0ef PM |
923 | uint64_t value) |
924 | { | |
925 | env->cp15.c9_pmuserenr = value & 1; | |
200ac0ef PM |
926 | } |
927 | ||
c4241c7d PM |
928 | static void pmintenset_write(CPUARMState *env, const ARMCPRegInfo *ri, |
929 | uint64_t value) | |
200ac0ef PM |
930 | { |
931 | /* We have no event counters so only the C bit can be changed */ | |
932 | value &= (1 << 31); | |
933 | env->cp15.c9_pminten |= value; | |
200ac0ef PM |
934 | } |
935 | ||
c4241c7d PM |
936 | static void pmintenclr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
937 | uint64_t value) | |
200ac0ef PM |
938 | { |
939 | value &= (1 << 31); | |
940 | env->cp15.c9_pminten &= ~value; | |
200ac0ef PM |
941 | } |
942 | ||
c4241c7d PM |
943 | static void vbar_write(CPUARMState *env, const ARMCPRegInfo *ri, |
944 | uint64_t value) | |
8641136c | 945 | { |
a505d7fe PM |
946 | /* Note that even though the AArch64 view of this register has bits |
947 | * [10:0] all RES0 we can only mask the bottom 5, to comply with the | |
948 | * architectural requirements for bits which are RES0 only in some | |
949 | * contexts. (ARMv8 would permit us to do no masking at all, but ARMv7 | |
950 | * requires the bottom five bits to be RAZ/WI because they're UNK/SBZP.) | |
951 | */ | |
855ea66d | 952 | raw_write(env, ri, value & ~0x1FULL); |
8641136c NR |
953 | } |
954 | ||
64e0e2de EI |
955 | static void scr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) |
956 | { | |
957 | /* We only mask off bits that are RES0 both for AArch64 and AArch32. | |
958 | * For bits that vary between AArch32/64, code needs to check the | |
959 | * current execution mode before directly using the feature bit. | |
960 | */ | |
961 | uint32_t valid_mask = SCR_AARCH64_MASK | SCR_AARCH32_MASK; | |
962 | ||
963 | if (!arm_feature(env, ARM_FEATURE_EL2)) { | |
964 | valid_mask &= ~SCR_HCE; | |
965 | ||
966 | /* On ARMv7, SMD (or SCD as it is called in v7) is only | |
967 | * supported if EL2 exists. The bit is UNK/SBZP when | |
968 | * EL2 is unavailable. In QEMU ARMv7, we force it to always zero | |
969 | * when EL2 is unavailable. | |
4eb27640 | 970 | * On ARMv8, this bit is always available. |
64e0e2de | 971 | */ |
4eb27640 GB |
972 | if (arm_feature(env, ARM_FEATURE_V7) && |
973 | !arm_feature(env, ARM_FEATURE_V8)) { | |
64e0e2de EI |
974 | valid_mask &= ~SCR_SMD; |
975 | } | |
976 | } | |
977 | ||
978 | /* Clear all-context RES0 bits. */ | |
979 | value &= valid_mask; | |
980 | raw_write(env, ri, value); | |
981 | } | |
982 | ||
c4241c7d | 983 | static uint64_t ccsidr_read(CPUARMState *env, const ARMCPRegInfo *ri) |
776d4e5c PM |
984 | { |
985 | ARMCPU *cpu = arm_env_get_cpu(env); | |
b85a1fd6 FA |
986 | |
987 | /* Acquire the CSSELR index from the bank corresponding to the CCSIDR | |
988 | * bank | |
989 | */ | |
990 | uint32_t index = A32_BANKED_REG_GET(env, csselr, | |
991 | ri->secure & ARM_CP_SECSTATE_S); | |
992 | ||
993 | return cpu->ccsidr[index]; | |
776d4e5c PM |
994 | } |
995 | ||
c4241c7d PM |
996 | static void csselr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
997 | uint64_t value) | |
776d4e5c | 998 | { |
8d5c773e | 999 | raw_write(env, ri, value & 0xf); |
776d4e5c PM |
1000 | } |
1001 | ||
1090b9c6 PM |
1002 | static uint64_t isr_read(CPUARMState *env, const ARMCPRegInfo *ri) |
1003 | { | |
1004 | CPUState *cs = ENV_GET_CPU(env); | |
1005 | uint64_t ret = 0; | |
1006 | ||
1007 | if (cs->interrupt_request & CPU_INTERRUPT_HARD) { | |
1008 | ret |= CPSR_I; | |
1009 | } | |
1010 | if (cs->interrupt_request & CPU_INTERRUPT_FIQ) { | |
1011 | ret |= CPSR_F; | |
1012 | } | |
1013 | /* External aborts are not possible in QEMU so A bit is always clear */ | |
1014 | return ret; | |
1015 | } | |
1016 | ||
e9aa6c21 | 1017 | static const ARMCPRegInfo v7_cp_reginfo[] = { |
7d57f408 PM |
1018 | /* the old v6 WFI, UNPREDICTABLE in v7 but we choose to NOP */ |
1019 | { .name = "NOP", .cp = 15, .crn = 7, .crm = 0, .opc1 = 0, .opc2 = 4, | |
1020 | .access = PL1_W, .type = ARM_CP_NOP }, | |
200ac0ef PM |
1021 | /* Performance monitors are implementation defined in v7, |
1022 | * but with an ARM recommended set of registers, which we | |
1023 | * follow (although we don't actually implement any counters) | |
1024 | * | |
1025 | * Performance registers fall into three categories: | |
1026 | * (a) always UNDEF in PL0, RW in PL1 (PMINTENSET, PMINTENCLR) | |
1027 | * (b) RO in PL0 (ie UNDEF on write), RW in PL1 (PMUSERENR) | |
1028 | * (c) UNDEF in PL0 if PMUSERENR.EN==0, otherwise accessible (all others) | |
1029 | * For the cases controlled by PMUSERENR we must set .access to PL0_RW | |
1030 | * or PL0_RO as appropriate and then check PMUSERENR in the helper fn. | |
1031 | */ | |
1032 | { .name = "PMCNTENSET", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 1, | |
7a0e58fa | 1033 | .access = PL0_RW, .type = ARM_CP_ALIAS, |
8521466b | 1034 | .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmcnten), |
fcd25206 PM |
1035 | .writefn = pmcntenset_write, |
1036 | .accessfn = pmreg_access, | |
1037 | .raw_writefn = raw_write }, | |
8521466b AF |
1038 | { .name = "PMCNTENSET_EL0", .state = ARM_CP_STATE_AA64, |
1039 | .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 1, | |
1040 | .access = PL0_RW, .accessfn = pmreg_access, | |
1041 | .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcnten), .resetvalue = 0, | |
1042 | .writefn = pmcntenset_write, .raw_writefn = raw_write }, | |
200ac0ef | 1043 | { .name = "PMCNTENCLR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 2, |
8521466b AF |
1044 | .access = PL0_RW, |
1045 | .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmcnten), | |
fcd25206 PM |
1046 | .accessfn = pmreg_access, |
1047 | .writefn = pmcntenclr_write, | |
7a0e58fa | 1048 | .type = ARM_CP_ALIAS }, |
8521466b AF |
1049 | { .name = "PMCNTENCLR_EL0", .state = ARM_CP_STATE_AA64, |
1050 | .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 2, | |
1051 | .access = PL0_RW, .accessfn = pmreg_access, | |
7a0e58fa | 1052 | .type = ARM_CP_ALIAS, |
8521466b AF |
1053 | .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcnten), |
1054 | .writefn = pmcntenclr_write }, | |
200ac0ef PM |
1055 | { .name = "PMOVSR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 3, |
1056 | .access = PL0_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_pmovsr), | |
fcd25206 PM |
1057 | .accessfn = pmreg_access, |
1058 | .writefn = pmovsr_write, | |
1059 | .raw_writefn = raw_write }, | |
978364f1 AF |
1060 | { .name = "PMOVSCLR_EL0", .state = ARM_CP_STATE_AA64, |
1061 | .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 3, | |
1062 | .access = PL0_RW, .accessfn = pmreg_access, | |
1063 | .type = ARM_CP_ALIAS, | |
1064 | .fieldoffset = offsetof(CPUARMState, cp15.c9_pmovsr), | |
1065 | .writefn = pmovsr_write, | |
1066 | .raw_writefn = raw_write }, | |
fcd25206 | 1067 | /* Unimplemented so WI. */ |
200ac0ef | 1068 | { .name = "PMSWINC", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 4, |
fcd25206 | 1069 | .access = PL0_W, .accessfn = pmreg_access, .type = ARM_CP_NOP }, |
200ac0ef | 1070 | /* Since we don't implement any events, writing to PMSELR is UNPREDICTABLE. |
fcd25206 | 1071 | * We choose to RAZ/WI. |
200ac0ef PM |
1072 | */ |
1073 | { .name = "PMSELR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 5, | |
fcd25206 PM |
1074 | .access = PL0_RW, .type = ARM_CP_CONST, .resetvalue = 0, |
1075 | .accessfn = pmreg_access }, | |
7c2cb42b | 1076 | #ifndef CONFIG_USER_ONLY |
200ac0ef | 1077 | { .name = "PMCCNTR", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 0, |
7c2cb42b | 1078 | .access = PL0_RW, .resetvalue = 0, .type = ARM_CP_IO, |
421c7ebd | 1079 | .readfn = pmccntr_read, .writefn = pmccntr_write32, |
fcd25206 | 1080 | .accessfn = pmreg_access }, |
8521466b AF |
1081 | { .name = "PMCCNTR_EL0", .state = ARM_CP_STATE_AA64, |
1082 | .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 13, .opc2 = 0, | |
1083 | .access = PL0_RW, .accessfn = pmreg_access, | |
1084 | .type = ARM_CP_IO, | |
1085 | .readfn = pmccntr_read, .writefn = pmccntr_write, }, | |
7c2cb42b | 1086 | #endif |
8521466b AF |
1087 | { .name = "PMCCFILTR_EL0", .state = ARM_CP_STATE_AA64, |
1088 | .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 15, .opc2 = 7, | |
0614601c | 1089 | .writefn = pmccfiltr_write, |
8521466b AF |
1090 | .access = PL0_RW, .accessfn = pmreg_access, |
1091 | .type = ARM_CP_IO, | |
1092 | .fieldoffset = offsetof(CPUARMState, cp15.pmccfiltr_el0), | |
1093 | .resetvalue = 0, }, | |
200ac0ef PM |
1094 | { .name = "PMXEVTYPER", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 1, |
1095 | .access = PL0_RW, | |
1096 | .fieldoffset = offsetof(CPUARMState, cp15.c9_pmxevtyper), | |
fcd25206 PM |
1097 | .accessfn = pmreg_access, .writefn = pmxevtyper_write, |
1098 | .raw_writefn = raw_write }, | |
1099 | /* Unimplemented, RAZ/WI. */ | |
200ac0ef | 1100 | { .name = "PMXEVCNTR", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 2, |
fcd25206 PM |
1101 | .access = PL0_RW, .type = ARM_CP_CONST, .resetvalue = 0, |
1102 | .accessfn = pmreg_access }, | |
200ac0ef PM |
1103 | { .name = "PMUSERENR", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 0, |
1104 | .access = PL0_R | PL1_RW, | |
1105 | .fieldoffset = offsetof(CPUARMState, cp15.c9_pmuserenr), | |
1106 | .resetvalue = 0, | |
d4e6df63 | 1107 | .writefn = pmuserenr_write, .raw_writefn = raw_write }, |
8a83ffc2 AF |
1108 | { .name = "PMUSERENR_EL0", .state = ARM_CP_STATE_AA64, |
1109 | .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 14, .opc2 = 0, | |
1110 | .access = PL0_R | PL1_RW, .type = ARM_CP_ALIAS, | |
1111 | .fieldoffset = offsetof(CPUARMState, cp15.c9_pmuserenr), | |
1112 | .resetvalue = 0, | |
1113 | .writefn = pmuserenr_write, .raw_writefn = raw_write }, | |
200ac0ef PM |
1114 | { .name = "PMINTENSET", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 1, |
1115 | .access = PL1_RW, | |
1116 | .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten), | |
1117 | .resetvalue = 0, | |
d4e6df63 | 1118 | .writefn = pmintenset_write, .raw_writefn = raw_write }, |
200ac0ef | 1119 | { .name = "PMINTENCLR", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 2, |
7a0e58fa | 1120 | .access = PL1_RW, .type = ARM_CP_ALIAS, |
200ac0ef | 1121 | .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten), |
b061a82b | 1122 | .writefn = pmintenclr_write, }, |
978364f1 AF |
1123 | { .name = "PMINTENCLR_EL1", .state = ARM_CP_STATE_AA64, |
1124 | .opc0 = 3, .opc1 = 0, .crn = 9, .crm = 14, .opc2 = 2, | |
1125 | .access = PL1_RW, .type = ARM_CP_ALIAS, | |
1126 | .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten), | |
1127 | .writefn = pmintenclr_write }, | |
a505d7fe PM |
1128 | { .name = "VBAR", .state = ARM_CP_STATE_BOTH, |
1129 | .opc0 = 3, .crn = 12, .crm = 0, .opc1 = 0, .opc2 = 0, | |
8641136c | 1130 | .access = PL1_RW, .writefn = vbar_write, |
fb6c91ba GB |
1131 | .bank_fieldoffsets = { offsetof(CPUARMState, cp15.vbar_s), |
1132 | offsetof(CPUARMState, cp15.vbar_ns) }, | |
8641136c | 1133 | .resetvalue = 0 }, |
7da845b0 PM |
1134 | { .name = "CCSIDR", .state = ARM_CP_STATE_BOTH, |
1135 | .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 0, | |
7a0e58fa | 1136 | .access = PL1_R, .readfn = ccsidr_read, .type = ARM_CP_NO_RAW }, |
7da845b0 PM |
1137 | { .name = "CSSELR", .state = ARM_CP_STATE_BOTH, |
1138 | .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 2, .opc2 = 0, | |
b85a1fd6 FA |
1139 | .access = PL1_RW, .writefn = csselr_write, .resetvalue = 0, |
1140 | .bank_fieldoffsets = { offsetof(CPUARMState, cp15.csselr_s), | |
1141 | offsetof(CPUARMState, cp15.csselr_ns) } }, | |
776d4e5c PM |
1142 | /* Auxiliary ID register: this actually has an IMPDEF value but for now |
1143 | * just RAZ for all cores: | |
1144 | */ | |
0ff644a7 PM |
1145 | { .name = "AIDR", .state = ARM_CP_STATE_BOTH, |
1146 | .opc0 = 3, .opc1 = 1, .crn = 0, .crm = 0, .opc2 = 7, | |
776d4e5c | 1147 | .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 }, |
f32cdad5 PM |
1148 | /* Auxiliary fault status registers: these also are IMPDEF, and we |
1149 | * choose to RAZ/WI for all cores. | |
1150 | */ | |
1151 | { .name = "AFSR0_EL1", .state = ARM_CP_STATE_BOTH, | |
1152 | .opc0 = 3, .opc1 = 0, .crn = 5, .crm = 1, .opc2 = 0, | |
1153 | .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
1154 | { .name = "AFSR1_EL1", .state = ARM_CP_STATE_BOTH, | |
1155 | .opc0 = 3, .opc1 = 0, .crn = 5, .crm = 1, .opc2 = 1, | |
1156 | .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
b0fe2427 PM |
1157 | /* MAIR can just read-as-written because we don't implement caches |
1158 | * and so don't need to care about memory attributes. | |
1159 | */ | |
1160 | { .name = "MAIR_EL1", .state = ARM_CP_STATE_AA64, | |
1161 | .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 2, .opc2 = 0, | |
be693c87 | 1162 | .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.mair_el[1]), |
b0fe2427 | 1163 | .resetvalue = 0 }, |
4cfb8ad8 PM |
1164 | { .name = "MAIR_EL3", .state = ARM_CP_STATE_AA64, |
1165 | .opc0 = 3, .opc1 = 6, .crn = 10, .crm = 2, .opc2 = 0, | |
1166 | .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.mair_el[3]), | |
1167 | .resetvalue = 0 }, | |
b0fe2427 PM |
1168 | /* For non-long-descriptor page tables these are PRRR and NMRR; |
1169 | * regardless they still act as reads-as-written for QEMU. | |
b0fe2427 | 1170 | */ |
1281f8e3 | 1171 | /* MAIR0/1 are defined separately from their 64-bit counterpart which |
be693c87 GB |
1172 | * allows them to assign the correct fieldoffset based on the endianness |
1173 | * handled in the field definitions. | |
1174 | */ | |
a903c449 | 1175 | { .name = "MAIR0", .state = ARM_CP_STATE_AA32, |
b0fe2427 | 1176 | .cp = 15, .opc1 = 0, .crn = 10, .crm = 2, .opc2 = 0, .access = PL1_RW, |
be693c87 GB |
1177 | .bank_fieldoffsets = { offsetof(CPUARMState, cp15.mair0_s), |
1178 | offsetof(CPUARMState, cp15.mair0_ns) }, | |
b0fe2427 | 1179 | .resetfn = arm_cp_reset_ignore }, |
a903c449 | 1180 | { .name = "MAIR1", .state = ARM_CP_STATE_AA32, |
b0fe2427 | 1181 | .cp = 15, .opc1 = 0, .crn = 10, .crm = 2, .opc2 = 1, .access = PL1_RW, |
be693c87 GB |
1182 | .bank_fieldoffsets = { offsetof(CPUARMState, cp15.mair1_s), |
1183 | offsetof(CPUARMState, cp15.mair1_ns) }, | |
b0fe2427 | 1184 | .resetfn = arm_cp_reset_ignore }, |
1090b9c6 PM |
1185 | { .name = "ISR_EL1", .state = ARM_CP_STATE_BOTH, |
1186 | .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 1, .opc2 = 0, | |
7a0e58fa | 1187 | .type = ARM_CP_NO_RAW, .access = PL1_R, .readfn = isr_read }, |
995939a6 PM |
1188 | /* 32 bit ITLB invalidates */ |
1189 | { .name = "ITLBIALL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 0, | |
7a0e58fa | 1190 | .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbiall_write }, |
995939a6 | 1191 | { .name = "ITLBIMVA", .cp = 15, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 1, |
7a0e58fa | 1192 | .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimva_write }, |
995939a6 | 1193 | { .name = "ITLBIASID", .cp = 15, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 2, |
7a0e58fa | 1194 | .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbiasid_write }, |
995939a6 PM |
1195 | /* 32 bit DTLB invalidates */ |
1196 | { .name = "DTLBIALL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 0, | |
7a0e58fa | 1197 | .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbiall_write }, |
995939a6 | 1198 | { .name = "DTLBIMVA", .cp = 15, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 1, |
7a0e58fa | 1199 | .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimva_write }, |
995939a6 | 1200 | { .name = "DTLBIASID", .cp = 15, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 2, |
7a0e58fa | 1201 | .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbiasid_write }, |
995939a6 PM |
1202 | /* 32 bit TLB invalidates */ |
1203 | { .name = "TLBIALL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 0, | |
7a0e58fa | 1204 | .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbiall_write }, |
995939a6 | 1205 | { .name = "TLBIMVA", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 1, |
7a0e58fa | 1206 | .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimva_write }, |
995939a6 | 1207 | { .name = "TLBIASID", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 2, |
7a0e58fa | 1208 | .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbiasid_write }, |
995939a6 | 1209 | { .name = "TLBIMVAA", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 3, |
7a0e58fa | 1210 | .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimvaa_write }, |
995939a6 PM |
1211 | REGINFO_SENTINEL |
1212 | }; | |
1213 | ||
1214 | static const ARMCPRegInfo v7mp_cp_reginfo[] = { | |
1215 | /* 32 bit TLB invalidates, Inner Shareable */ | |
1216 | { .name = "TLBIALLIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 0, | |
7a0e58fa | 1217 | .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbiall_is_write }, |
995939a6 | 1218 | { .name = "TLBIMVAIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 1, |
7a0e58fa | 1219 | .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimva_is_write }, |
995939a6 | 1220 | { .name = "TLBIASIDIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 2, |
7a0e58fa | 1221 | .type = ARM_CP_NO_RAW, .access = PL1_W, |
fa439fc5 | 1222 | .writefn = tlbiasid_is_write }, |
995939a6 | 1223 | { .name = "TLBIMVAAIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 3, |
7a0e58fa | 1224 | .type = ARM_CP_NO_RAW, .access = PL1_W, |
fa439fc5 | 1225 | .writefn = tlbimvaa_is_write }, |
e9aa6c21 PM |
1226 | REGINFO_SENTINEL |
1227 | }; | |
1228 | ||
c4241c7d PM |
1229 | static void teecr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1230 | uint64_t value) | |
c326b979 PM |
1231 | { |
1232 | value &= 1; | |
1233 | env->teecr = value; | |
c326b979 PM |
1234 | } |
1235 | ||
3f208fd7 PM |
1236 | static CPAccessResult teehbr_access(CPUARMState *env, const ARMCPRegInfo *ri, |
1237 | bool isread) | |
c326b979 | 1238 | { |
dcbff19b | 1239 | if (arm_current_el(env) == 0 && (env->teecr & 1)) { |
92611c00 | 1240 | return CP_ACCESS_TRAP; |
c326b979 | 1241 | } |
92611c00 | 1242 | return CP_ACCESS_OK; |
c326b979 PM |
1243 | } |
1244 | ||
1245 | static const ARMCPRegInfo t2ee_cp_reginfo[] = { | |
1246 | { .name = "TEECR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 6, .opc2 = 0, | |
1247 | .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, teecr), | |
1248 | .resetvalue = 0, | |
1249 | .writefn = teecr_write }, | |
1250 | { .name = "TEEHBR", .cp = 14, .crn = 1, .crm = 0, .opc1 = 6, .opc2 = 0, | |
1251 | .access = PL0_RW, .fieldoffset = offsetof(CPUARMState, teehbr), | |
92611c00 | 1252 | .accessfn = teehbr_access, .resetvalue = 0 }, |
c326b979 PM |
1253 | REGINFO_SENTINEL |
1254 | }; | |
1255 | ||
4d31c596 | 1256 | static const ARMCPRegInfo v6k_cp_reginfo[] = { |
e4fe830b PM |
1257 | { .name = "TPIDR_EL0", .state = ARM_CP_STATE_AA64, |
1258 | .opc0 = 3, .opc1 = 3, .opc2 = 2, .crn = 13, .crm = 0, | |
1259 | .access = PL0_RW, | |
54bf36ed | 1260 | .fieldoffset = offsetof(CPUARMState, cp15.tpidr_el[0]), .resetvalue = 0 }, |
4d31c596 PM |
1261 | { .name = "TPIDRURW", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 2, |
1262 | .access = PL0_RW, | |
54bf36ed FA |
1263 | .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.tpidrurw_s), |
1264 | offsetoflow32(CPUARMState, cp15.tpidrurw_ns) }, | |
e4fe830b PM |
1265 | .resetfn = arm_cp_reset_ignore }, |
1266 | { .name = "TPIDRRO_EL0", .state = ARM_CP_STATE_AA64, | |
1267 | .opc0 = 3, .opc1 = 3, .opc2 = 3, .crn = 13, .crm = 0, | |
1268 | .access = PL0_R|PL1_W, | |
54bf36ed FA |
1269 | .fieldoffset = offsetof(CPUARMState, cp15.tpidrro_el[0]), |
1270 | .resetvalue = 0}, | |
4d31c596 PM |
1271 | { .name = "TPIDRURO", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 3, |
1272 | .access = PL0_R|PL1_W, | |
54bf36ed FA |
1273 | .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.tpidruro_s), |
1274 | offsetoflow32(CPUARMState, cp15.tpidruro_ns) }, | |
e4fe830b | 1275 | .resetfn = arm_cp_reset_ignore }, |
54bf36ed | 1276 | { .name = "TPIDR_EL1", .state = ARM_CP_STATE_AA64, |
e4fe830b | 1277 | .opc0 = 3, .opc1 = 0, .opc2 = 4, .crn = 13, .crm = 0, |
4d31c596 | 1278 | .access = PL1_RW, |
54bf36ed FA |
1279 | .fieldoffset = offsetof(CPUARMState, cp15.tpidr_el[1]), .resetvalue = 0 }, |
1280 | { .name = "TPIDRPRW", .opc1 = 0, .cp = 15, .crn = 13, .crm = 0, .opc2 = 4, | |
1281 | .access = PL1_RW, | |
1282 | .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.tpidrprw_s), | |
1283 | offsetoflow32(CPUARMState, cp15.tpidrprw_ns) }, | |
1284 | .resetvalue = 0 }, | |
4d31c596 PM |
1285 | REGINFO_SENTINEL |
1286 | }; | |
1287 | ||
55d284af PM |
1288 | #ifndef CONFIG_USER_ONLY |
1289 | ||
3f208fd7 PM |
1290 | static CPAccessResult gt_cntfrq_access(CPUARMState *env, const ARMCPRegInfo *ri, |
1291 | bool isread) | |
00108f2d | 1292 | { |
75502672 PM |
1293 | /* CNTFRQ: not visible from PL0 if both PL0PCTEN and PL0VCTEN are zero. |
1294 | * Writable only at the highest implemented exception level. | |
1295 | */ | |
1296 | int el = arm_current_el(env); | |
1297 | ||
1298 | switch (el) { | |
1299 | case 0: | |
1300 | if (!extract32(env->cp15.c14_cntkctl, 0, 2)) { | |
1301 | return CP_ACCESS_TRAP; | |
1302 | } | |
1303 | break; | |
1304 | case 1: | |
1305 | if (!isread && ri->state == ARM_CP_STATE_AA32 && | |
1306 | arm_is_secure_below_el3(env)) { | |
1307 | /* Accesses from 32-bit Secure EL1 UNDEF (*not* trap to EL3!) */ | |
1308 | return CP_ACCESS_TRAP_UNCATEGORIZED; | |
1309 | } | |
1310 | break; | |
1311 | case 2: | |
1312 | case 3: | |
1313 | break; | |
00108f2d | 1314 | } |
75502672 PM |
1315 | |
1316 | if (!isread && el < arm_highest_el(env)) { | |
1317 | return CP_ACCESS_TRAP_UNCATEGORIZED; | |
1318 | } | |
1319 | ||
00108f2d PM |
1320 | return CP_ACCESS_OK; |
1321 | } | |
1322 | ||
3f208fd7 PM |
1323 | static CPAccessResult gt_counter_access(CPUARMState *env, int timeridx, |
1324 | bool isread) | |
00108f2d | 1325 | { |
0b6440af EI |
1326 | unsigned int cur_el = arm_current_el(env); |
1327 | bool secure = arm_is_secure(env); | |
1328 | ||
00108f2d | 1329 | /* CNT[PV]CT: not visible from PL0 if ELO[PV]CTEN is zero */ |
0b6440af | 1330 | if (cur_el == 0 && |
00108f2d PM |
1331 | !extract32(env->cp15.c14_cntkctl, timeridx, 1)) { |
1332 | return CP_ACCESS_TRAP; | |
1333 | } | |
0b6440af EI |
1334 | |
1335 | if (arm_feature(env, ARM_FEATURE_EL2) && | |
1336 | timeridx == GTIMER_PHYS && !secure && cur_el < 2 && | |
1337 | !extract32(env->cp15.cnthctl_el2, 0, 1)) { | |
1338 | return CP_ACCESS_TRAP_EL2; | |
1339 | } | |
00108f2d PM |
1340 | return CP_ACCESS_OK; |
1341 | } | |
1342 | ||
3f208fd7 PM |
1343 | static CPAccessResult gt_timer_access(CPUARMState *env, int timeridx, |
1344 | bool isread) | |
00108f2d | 1345 | { |
0b6440af EI |
1346 | unsigned int cur_el = arm_current_el(env); |
1347 | bool secure = arm_is_secure(env); | |
1348 | ||
00108f2d PM |
1349 | /* CNT[PV]_CVAL, CNT[PV]_CTL, CNT[PV]_TVAL: not visible from PL0 if |
1350 | * EL0[PV]TEN is zero. | |
1351 | */ | |
0b6440af | 1352 | if (cur_el == 0 && |
00108f2d PM |
1353 | !extract32(env->cp15.c14_cntkctl, 9 - timeridx, 1)) { |
1354 | return CP_ACCESS_TRAP; | |
1355 | } | |
0b6440af EI |
1356 | |
1357 | if (arm_feature(env, ARM_FEATURE_EL2) && | |
1358 | timeridx == GTIMER_PHYS && !secure && cur_el < 2 && | |
1359 | !extract32(env->cp15.cnthctl_el2, 1, 1)) { | |
1360 | return CP_ACCESS_TRAP_EL2; | |
1361 | } | |
00108f2d PM |
1362 | return CP_ACCESS_OK; |
1363 | } | |
1364 | ||
1365 | static CPAccessResult gt_pct_access(CPUARMState *env, | |
3f208fd7 PM |
1366 | const ARMCPRegInfo *ri, |
1367 | bool isread) | |
00108f2d | 1368 | { |
3f208fd7 | 1369 | return gt_counter_access(env, GTIMER_PHYS, isread); |
00108f2d PM |
1370 | } |
1371 | ||
1372 | static CPAccessResult gt_vct_access(CPUARMState *env, | |
3f208fd7 PM |
1373 | const ARMCPRegInfo *ri, |
1374 | bool isread) | |
00108f2d | 1375 | { |
3f208fd7 | 1376 | return gt_counter_access(env, GTIMER_VIRT, isread); |
00108f2d PM |
1377 | } |
1378 | ||
3f208fd7 PM |
1379 | static CPAccessResult gt_ptimer_access(CPUARMState *env, const ARMCPRegInfo *ri, |
1380 | bool isread) | |
00108f2d | 1381 | { |
3f208fd7 | 1382 | return gt_timer_access(env, GTIMER_PHYS, isread); |
00108f2d PM |
1383 | } |
1384 | ||
3f208fd7 PM |
1385 | static CPAccessResult gt_vtimer_access(CPUARMState *env, const ARMCPRegInfo *ri, |
1386 | bool isread) | |
00108f2d | 1387 | { |
3f208fd7 | 1388 | return gt_timer_access(env, GTIMER_VIRT, isread); |
00108f2d PM |
1389 | } |
1390 | ||
b4d3978c | 1391 | static CPAccessResult gt_stimer_access(CPUARMState *env, |
3f208fd7 PM |
1392 | const ARMCPRegInfo *ri, |
1393 | bool isread) | |
b4d3978c PM |
1394 | { |
1395 | /* The AArch64 register view of the secure physical timer is | |
1396 | * always accessible from EL3, and configurably accessible from | |
1397 | * Secure EL1. | |
1398 | */ | |
1399 | switch (arm_current_el(env)) { | |
1400 | case 1: | |
1401 | if (!arm_is_secure(env)) { | |
1402 | return CP_ACCESS_TRAP; | |
1403 | } | |
1404 | if (!(env->cp15.scr_el3 & SCR_ST)) { | |
1405 | return CP_ACCESS_TRAP_EL3; | |
1406 | } | |
1407 | return CP_ACCESS_OK; | |
1408 | case 0: | |
1409 | case 2: | |
1410 | return CP_ACCESS_TRAP; | |
1411 | case 3: | |
1412 | return CP_ACCESS_OK; | |
1413 | default: | |
1414 | g_assert_not_reached(); | |
1415 | } | |
1416 | } | |
1417 | ||
55d284af PM |
1418 | static uint64_t gt_get_countervalue(CPUARMState *env) |
1419 | { | |
bc72ad67 | 1420 | return qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) / GTIMER_SCALE; |
55d284af PM |
1421 | } |
1422 | ||
1423 | static void gt_recalc_timer(ARMCPU *cpu, int timeridx) | |
1424 | { | |
1425 | ARMGenericTimer *gt = &cpu->env.cp15.c14_timer[timeridx]; | |
1426 | ||
1427 | if (gt->ctl & 1) { | |
1428 | /* Timer enabled: calculate and set current ISTATUS, irq, and | |
1429 | * reset timer to when ISTATUS next has to change | |
1430 | */ | |
edac4d8a EI |
1431 | uint64_t offset = timeridx == GTIMER_VIRT ? |
1432 | cpu->env.cp15.cntvoff_el2 : 0; | |
55d284af PM |
1433 | uint64_t count = gt_get_countervalue(&cpu->env); |
1434 | /* Note that this must be unsigned 64 bit arithmetic: */ | |
edac4d8a | 1435 | int istatus = count - offset >= gt->cval; |
55d284af PM |
1436 | uint64_t nexttick; |
1437 | ||
1438 | gt->ctl = deposit32(gt->ctl, 2, 1, istatus); | |
1439 | qemu_set_irq(cpu->gt_timer_outputs[timeridx], | |
1440 | (istatus && !(gt->ctl & 2))); | |
1441 | if (istatus) { | |
1442 | /* Next transition is when count rolls back over to zero */ | |
1443 | nexttick = UINT64_MAX; | |
1444 | } else { | |
1445 | /* Next transition is when we hit cval */ | |
edac4d8a | 1446 | nexttick = gt->cval + offset; |
55d284af PM |
1447 | } |
1448 | /* Note that the desired next expiry time might be beyond the | |
1449 | * signed-64-bit range of a QEMUTimer -- in this case we just | |
1450 | * set the timer for as far in the future as possible. When the | |
1451 | * timer expires we will reset the timer for any remaining period. | |
1452 | */ | |
1453 | if (nexttick > INT64_MAX / GTIMER_SCALE) { | |
1454 | nexttick = INT64_MAX / GTIMER_SCALE; | |
1455 | } | |
bc72ad67 | 1456 | timer_mod(cpu->gt_timer[timeridx], nexttick); |
55d284af PM |
1457 | } else { |
1458 | /* Timer disabled: ISTATUS and timer output always clear */ | |
1459 | gt->ctl &= ~4; | |
1460 | qemu_set_irq(cpu->gt_timer_outputs[timeridx], 0); | |
bc72ad67 | 1461 | timer_del(cpu->gt_timer[timeridx]); |
55d284af PM |
1462 | } |
1463 | } | |
1464 | ||
0e3eca4c EI |
1465 | static void gt_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri, |
1466 | int timeridx) | |
55d284af PM |
1467 | { |
1468 | ARMCPU *cpu = arm_env_get_cpu(env); | |
55d284af | 1469 | |
bc72ad67 | 1470 | timer_del(cpu->gt_timer[timeridx]); |
55d284af PM |
1471 | } |
1472 | ||
c4241c7d | 1473 | static uint64_t gt_cnt_read(CPUARMState *env, const ARMCPRegInfo *ri) |
55d284af | 1474 | { |
c4241c7d | 1475 | return gt_get_countervalue(env); |
55d284af PM |
1476 | } |
1477 | ||
edac4d8a EI |
1478 | static uint64_t gt_virt_cnt_read(CPUARMState *env, const ARMCPRegInfo *ri) |
1479 | { | |
1480 | return gt_get_countervalue(env) - env->cp15.cntvoff_el2; | |
1481 | } | |
1482 | ||
c4241c7d | 1483 | static void gt_cval_write(CPUARMState *env, const ARMCPRegInfo *ri, |
0e3eca4c | 1484 | int timeridx, |
c4241c7d | 1485 | uint64_t value) |
55d284af | 1486 | { |
55d284af PM |
1487 | env->cp15.c14_timer[timeridx].cval = value; |
1488 | gt_recalc_timer(arm_env_get_cpu(env), timeridx); | |
55d284af | 1489 | } |
c4241c7d | 1490 | |
0e3eca4c EI |
1491 | static uint64_t gt_tval_read(CPUARMState *env, const ARMCPRegInfo *ri, |
1492 | int timeridx) | |
55d284af | 1493 | { |
edac4d8a | 1494 | uint64_t offset = timeridx == GTIMER_VIRT ? env->cp15.cntvoff_el2 : 0; |
55d284af | 1495 | |
c4241c7d | 1496 | return (uint32_t)(env->cp15.c14_timer[timeridx].cval - |
edac4d8a | 1497 | (gt_get_countervalue(env) - offset)); |
55d284af PM |
1498 | } |
1499 | ||
c4241c7d | 1500 | static void gt_tval_write(CPUARMState *env, const ARMCPRegInfo *ri, |
0e3eca4c | 1501 | int timeridx, |
c4241c7d | 1502 | uint64_t value) |
55d284af | 1503 | { |
edac4d8a | 1504 | uint64_t offset = timeridx == GTIMER_VIRT ? env->cp15.cntvoff_el2 : 0; |
55d284af | 1505 | |
edac4d8a | 1506 | env->cp15.c14_timer[timeridx].cval = gt_get_countervalue(env) - offset + |
18084b2f | 1507 | sextract64(value, 0, 32); |
55d284af | 1508 | gt_recalc_timer(arm_env_get_cpu(env), timeridx); |
55d284af PM |
1509 | } |
1510 | ||
c4241c7d | 1511 | static void gt_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri, |
0e3eca4c | 1512 | int timeridx, |
c4241c7d | 1513 | uint64_t value) |
55d284af PM |
1514 | { |
1515 | ARMCPU *cpu = arm_env_get_cpu(env); | |
55d284af PM |
1516 | uint32_t oldval = env->cp15.c14_timer[timeridx].ctl; |
1517 | ||
d3afacc7 | 1518 | env->cp15.c14_timer[timeridx].ctl = deposit64(oldval, 0, 2, value); |
55d284af PM |
1519 | if ((oldval ^ value) & 1) { |
1520 | /* Enable toggled */ | |
1521 | gt_recalc_timer(cpu, timeridx); | |
d3afacc7 | 1522 | } else if ((oldval ^ value) & 2) { |
55d284af PM |
1523 | /* IMASK toggled: don't need to recalculate, |
1524 | * just set the interrupt line based on ISTATUS | |
1525 | */ | |
1526 | qemu_set_irq(cpu->gt_timer_outputs[timeridx], | |
d3afacc7 | 1527 | (oldval & 4) && !(value & 2)); |
55d284af | 1528 | } |
55d284af PM |
1529 | } |
1530 | ||
0e3eca4c EI |
1531 | static void gt_phys_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri) |
1532 | { | |
1533 | gt_timer_reset(env, ri, GTIMER_PHYS); | |
1534 | } | |
1535 | ||
1536 | static void gt_phys_cval_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
1537 | uint64_t value) | |
1538 | { | |
1539 | gt_cval_write(env, ri, GTIMER_PHYS, value); | |
1540 | } | |
1541 | ||
1542 | static uint64_t gt_phys_tval_read(CPUARMState *env, const ARMCPRegInfo *ri) | |
1543 | { | |
1544 | return gt_tval_read(env, ri, GTIMER_PHYS); | |
1545 | } | |
1546 | ||
1547 | static void gt_phys_tval_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
1548 | uint64_t value) | |
1549 | { | |
1550 | gt_tval_write(env, ri, GTIMER_PHYS, value); | |
1551 | } | |
1552 | ||
1553 | static void gt_phys_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
1554 | uint64_t value) | |
1555 | { | |
1556 | gt_ctl_write(env, ri, GTIMER_PHYS, value); | |
1557 | } | |
1558 | ||
1559 | static void gt_virt_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri) | |
1560 | { | |
1561 | gt_timer_reset(env, ri, GTIMER_VIRT); | |
1562 | } | |
1563 | ||
1564 | static void gt_virt_cval_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
1565 | uint64_t value) | |
1566 | { | |
1567 | gt_cval_write(env, ri, GTIMER_VIRT, value); | |
1568 | } | |
1569 | ||
1570 | static uint64_t gt_virt_tval_read(CPUARMState *env, const ARMCPRegInfo *ri) | |
1571 | { | |
1572 | return gt_tval_read(env, ri, GTIMER_VIRT); | |
1573 | } | |
1574 | ||
1575 | static void gt_virt_tval_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
1576 | uint64_t value) | |
1577 | { | |
1578 | gt_tval_write(env, ri, GTIMER_VIRT, value); | |
1579 | } | |
1580 | ||
1581 | static void gt_virt_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
1582 | uint64_t value) | |
1583 | { | |
1584 | gt_ctl_write(env, ri, GTIMER_VIRT, value); | |
1585 | } | |
1586 | ||
edac4d8a EI |
1587 | static void gt_cntvoff_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1588 | uint64_t value) | |
1589 | { | |
1590 | ARMCPU *cpu = arm_env_get_cpu(env); | |
1591 | ||
1592 | raw_write(env, ri, value); | |
1593 | gt_recalc_timer(cpu, GTIMER_VIRT); | |
1594 | } | |
1595 | ||
b0e66d95 EI |
1596 | static void gt_hyp_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri) |
1597 | { | |
1598 | gt_timer_reset(env, ri, GTIMER_HYP); | |
1599 | } | |
1600 | ||
1601 | static void gt_hyp_cval_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
1602 | uint64_t value) | |
1603 | { | |
1604 | gt_cval_write(env, ri, GTIMER_HYP, value); | |
1605 | } | |
1606 | ||
1607 | static uint64_t gt_hyp_tval_read(CPUARMState *env, const ARMCPRegInfo *ri) | |
1608 | { | |
1609 | return gt_tval_read(env, ri, GTIMER_HYP); | |
1610 | } | |
1611 | ||
1612 | static void gt_hyp_tval_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
1613 | uint64_t value) | |
1614 | { | |
1615 | gt_tval_write(env, ri, GTIMER_HYP, value); | |
1616 | } | |
1617 | ||
1618 | static void gt_hyp_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
1619 | uint64_t value) | |
1620 | { | |
1621 | gt_ctl_write(env, ri, GTIMER_HYP, value); | |
1622 | } | |
1623 | ||
b4d3978c PM |
1624 | static void gt_sec_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri) |
1625 | { | |
1626 | gt_timer_reset(env, ri, GTIMER_SEC); | |
1627 | } | |
1628 | ||
1629 | static void gt_sec_cval_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
1630 | uint64_t value) | |
1631 | { | |
1632 | gt_cval_write(env, ri, GTIMER_SEC, value); | |
1633 | } | |
1634 | ||
1635 | static uint64_t gt_sec_tval_read(CPUARMState *env, const ARMCPRegInfo *ri) | |
1636 | { | |
1637 | return gt_tval_read(env, ri, GTIMER_SEC); | |
1638 | } | |
1639 | ||
1640 | static void gt_sec_tval_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
1641 | uint64_t value) | |
1642 | { | |
1643 | gt_tval_write(env, ri, GTIMER_SEC, value); | |
1644 | } | |
1645 | ||
1646 | static void gt_sec_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
1647 | uint64_t value) | |
1648 | { | |
1649 | gt_ctl_write(env, ri, GTIMER_SEC, value); | |
1650 | } | |
1651 | ||
55d284af PM |
1652 | void arm_gt_ptimer_cb(void *opaque) |
1653 | { | |
1654 | ARMCPU *cpu = opaque; | |
1655 | ||
1656 | gt_recalc_timer(cpu, GTIMER_PHYS); | |
1657 | } | |
1658 | ||
1659 | void arm_gt_vtimer_cb(void *opaque) | |
1660 | { | |
1661 | ARMCPU *cpu = opaque; | |
1662 | ||
1663 | gt_recalc_timer(cpu, GTIMER_VIRT); | |
1664 | } | |
1665 | ||
b0e66d95 EI |
1666 | void arm_gt_htimer_cb(void *opaque) |
1667 | { | |
1668 | ARMCPU *cpu = opaque; | |
1669 | ||
1670 | gt_recalc_timer(cpu, GTIMER_HYP); | |
1671 | } | |
1672 | ||
b4d3978c PM |
1673 | void arm_gt_stimer_cb(void *opaque) |
1674 | { | |
1675 | ARMCPU *cpu = opaque; | |
1676 | ||
1677 | gt_recalc_timer(cpu, GTIMER_SEC); | |
1678 | } | |
1679 | ||
55d284af PM |
1680 | static const ARMCPRegInfo generic_timer_cp_reginfo[] = { |
1681 | /* Note that CNTFRQ is purely reads-as-written for the benefit | |
1682 | * of software; writing it doesn't actually change the timer frequency. | |
1683 | * Our reset value matches the fixed frequency we implement the timer at. | |
1684 | */ | |
1685 | { .name = "CNTFRQ", .cp = 15, .crn = 14, .crm = 0, .opc1 = 0, .opc2 = 0, | |
7a0e58fa | 1686 | .type = ARM_CP_ALIAS, |
a7adc4b7 PM |
1687 | .access = PL1_RW | PL0_R, .accessfn = gt_cntfrq_access, |
1688 | .fieldoffset = offsetoflow32(CPUARMState, cp15.c14_cntfrq), | |
a7adc4b7 PM |
1689 | }, |
1690 | { .name = "CNTFRQ_EL0", .state = ARM_CP_STATE_AA64, | |
1691 | .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 0, | |
1692 | .access = PL1_RW | PL0_R, .accessfn = gt_cntfrq_access, | |
55d284af PM |
1693 | .fieldoffset = offsetof(CPUARMState, cp15.c14_cntfrq), |
1694 | .resetvalue = (1000 * 1000 * 1000) / GTIMER_SCALE, | |
55d284af PM |
1695 | }, |
1696 | /* overall control: mostly access permissions */ | |
a7adc4b7 PM |
1697 | { .name = "CNTKCTL", .state = ARM_CP_STATE_BOTH, |
1698 | .opc0 = 3, .opc1 = 0, .crn = 14, .crm = 1, .opc2 = 0, | |
55d284af PM |
1699 | .access = PL1_RW, |
1700 | .fieldoffset = offsetof(CPUARMState, cp15.c14_cntkctl), | |
1701 | .resetvalue = 0, | |
1702 | }, | |
1703 | /* per-timer control */ | |
1704 | { .name = "CNTP_CTL", .cp = 15, .crn = 14, .crm = 2, .opc1 = 0, .opc2 = 1, | |
9ff9dd3c | 1705 | .secure = ARM_CP_SECSTATE_NS, |
7a0e58fa | 1706 | .type = ARM_CP_IO | ARM_CP_ALIAS, .access = PL1_RW | PL0_R, |
a7adc4b7 PM |
1707 | .accessfn = gt_ptimer_access, |
1708 | .fieldoffset = offsetoflow32(CPUARMState, | |
1709 | cp15.c14_timer[GTIMER_PHYS].ctl), | |
0e3eca4c | 1710 | .writefn = gt_phys_ctl_write, .raw_writefn = raw_write, |
a7adc4b7 | 1711 | }, |
9ff9dd3c PM |
1712 | { .name = "CNTP_CTL(S)", |
1713 | .cp = 15, .crn = 14, .crm = 2, .opc1 = 0, .opc2 = 1, | |
1714 | .secure = ARM_CP_SECSTATE_S, | |
1715 | .type = ARM_CP_IO | ARM_CP_ALIAS, .access = PL1_RW | PL0_R, | |
1716 | .accessfn = gt_ptimer_access, | |
1717 | .fieldoffset = offsetoflow32(CPUARMState, | |
1718 | cp15.c14_timer[GTIMER_SEC].ctl), | |
1719 | .writefn = gt_sec_ctl_write, .raw_writefn = raw_write, | |
1720 | }, | |
a7adc4b7 PM |
1721 | { .name = "CNTP_CTL_EL0", .state = ARM_CP_STATE_AA64, |
1722 | .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 2, .opc2 = 1, | |
55d284af | 1723 | .type = ARM_CP_IO, .access = PL1_RW | PL0_R, |
a7adc4b7 | 1724 | .accessfn = gt_ptimer_access, |
55d284af PM |
1725 | .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].ctl), |
1726 | .resetvalue = 0, | |
0e3eca4c | 1727 | .writefn = gt_phys_ctl_write, .raw_writefn = raw_write, |
55d284af PM |
1728 | }, |
1729 | { .name = "CNTV_CTL", .cp = 15, .crn = 14, .crm = 3, .opc1 = 0, .opc2 = 1, | |
7a0e58fa | 1730 | .type = ARM_CP_IO | ARM_CP_ALIAS, .access = PL1_RW | PL0_R, |
a7adc4b7 PM |
1731 | .accessfn = gt_vtimer_access, |
1732 | .fieldoffset = offsetoflow32(CPUARMState, | |
1733 | cp15.c14_timer[GTIMER_VIRT].ctl), | |
0e3eca4c | 1734 | .writefn = gt_virt_ctl_write, .raw_writefn = raw_write, |
a7adc4b7 PM |
1735 | }, |
1736 | { .name = "CNTV_CTL_EL0", .state = ARM_CP_STATE_AA64, | |
1737 | .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 3, .opc2 = 1, | |
55d284af | 1738 | .type = ARM_CP_IO, .access = PL1_RW | PL0_R, |
a7adc4b7 | 1739 | .accessfn = gt_vtimer_access, |
55d284af PM |
1740 | .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].ctl), |
1741 | .resetvalue = 0, | |
0e3eca4c | 1742 | .writefn = gt_virt_ctl_write, .raw_writefn = raw_write, |
55d284af PM |
1743 | }, |
1744 | /* TimerValue views: a 32 bit downcounting view of the underlying state */ | |
1745 | { .name = "CNTP_TVAL", .cp = 15, .crn = 14, .crm = 2, .opc1 = 0, .opc2 = 0, | |
9ff9dd3c | 1746 | .secure = ARM_CP_SECSTATE_NS, |
7a0e58fa | 1747 | .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL1_RW | PL0_R, |
00108f2d | 1748 | .accessfn = gt_ptimer_access, |
0e3eca4c | 1749 | .readfn = gt_phys_tval_read, .writefn = gt_phys_tval_write, |
55d284af | 1750 | }, |
9ff9dd3c PM |
1751 | { .name = "CNTP_TVAL(S)", |
1752 | .cp = 15, .crn = 14, .crm = 2, .opc1 = 0, .opc2 = 0, | |
1753 | .secure = ARM_CP_SECSTATE_S, | |
1754 | .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL1_RW | PL0_R, | |
1755 | .accessfn = gt_ptimer_access, | |
1756 | .readfn = gt_sec_tval_read, .writefn = gt_sec_tval_write, | |
1757 | }, | |
a7adc4b7 PM |
1758 | { .name = "CNTP_TVAL_EL0", .state = ARM_CP_STATE_AA64, |
1759 | .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 2, .opc2 = 0, | |
7a0e58fa | 1760 | .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL1_RW | PL0_R, |
0e3eca4c EI |
1761 | .accessfn = gt_ptimer_access, .resetfn = gt_phys_timer_reset, |
1762 | .readfn = gt_phys_tval_read, .writefn = gt_phys_tval_write, | |
a7adc4b7 | 1763 | }, |
55d284af | 1764 | { .name = "CNTV_TVAL", .cp = 15, .crn = 14, .crm = 3, .opc1 = 0, .opc2 = 0, |
7a0e58fa | 1765 | .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL1_RW | PL0_R, |
00108f2d | 1766 | .accessfn = gt_vtimer_access, |
0e3eca4c | 1767 | .readfn = gt_virt_tval_read, .writefn = gt_virt_tval_write, |
55d284af | 1768 | }, |
a7adc4b7 PM |
1769 | { .name = "CNTV_TVAL_EL0", .state = ARM_CP_STATE_AA64, |
1770 | .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 3, .opc2 = 0, | |
7a0e58fa | 1771 | .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL1_RW | PL0_R, |
0e3eca4c EI |
1772 | .accessfn = gt_vtimer_access, .resetfn = gt_virt_timer_reset, |
1773 | .readfn = gt_virt_tval_read, .writefn = gt_virt_tval_write, | |
a7adc4b7 | 1774 | }, |
55d284af PM |
1775 | /* The counter itself */ |
1776 | { .name = "CNTPCT", .cp = 15, .crm = 14, .opc1 = 0, | |
7a0e58fa | 1777 | .access = PL0_R, .type = ARM_CP_64BIT | ARM_CP_NO_RAW | ARM_CP_IO, |
00108f2d | 1778 | .accessfn = gt_pct_access, |
a7adc4b7 PM |
1779 | .readfn = gt_cnt_read, .resetfn = arm_cp_reset_ignore, |
1780 | }, | |
1781 | { .name = "CNTPCT_EL0", .state = ARM_CP_STATE_AA64, | |
1782 | .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 1, | |
7a0e58fa | 1783 | .access = PL0_R, .type = ARM_CP_NO_RAW | ARM_CP_IO, |
d57b9ee8 | 1784 | .accessfn = gt_pct_access, .readfn = gt_cnt_read, |
55d284af PM |
1785 | }, |
1786 | { .name = "CNTVCT", .cp = 15, .crm = 14, .opc1 = 1, | |
7a0e58fa | 1787 | .access = PL0_R, .type = ARM_CP_64BIT | ARM_CP_NO_RAW | ARM_CP_IO, |
00108f2d | 1788 | .accessfn = gt_vct_access, |
edac4d8a | 1789 | .readfn = gt_virt_cnt_read, .resetfn = arm_cp_reset_ignore, |
a7adc4b7 PM |
1790 | }, |
1791 | { .name = "CNTVCT_EL0", .state = ARM_CP_STATE_AA64, | |
1792 | .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 2, | |
7a0e58fa | 1793 | .access = PL0_R, .type = ARM_CP_NO_RAW | ARM_CP_IO, |
d57b9ee8 | 1794 | .accessfn = gt_vct_access, .readfn = gt_virt_cnt_read, |
55d284af PM |
1795 | }, |
1796 | /* Comparison value, indicating when the timer goes off */ | |
1797 | { .name = "CNTP_CVAL", .cp = 15, .crm = 14, .opc1 = 2, | |
9ff9dd3c | 1798 | .secure = ARM_CP_SECSTATE_NS, |
55d284af | 1799 | .access = PL1_RW | PL0_R, |
7a0e58fa | 1800 | .type = ARM_CP_64BIT | ARM_CP_IO | ARM_CP_ALIAS, |
55d284af | 1801 | .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].cval), |
b061a82b | 1802 | .accessfn = gt_ptimer_access, |
0e3eca4c | 1803 | .writefn = gt_phys_cval_write, .raw_writefn = raw_write, |
a7adc4b7 | 1804 | }, |
9ff9dd3c PM |
1805 | { .name = "CNTP_CVAL(S)", .cp = 15, .crm = 14, .opc1 = 2, |
1806 | .secure = ARM_CP_SECSTATE_S, | |
1807 | .access = PL1_RW | PL0_R, | |
1808 | .type = ARM_CP_64BIT | ARM_CP_IO | ARM_CP_ALIAS, | |
1809 | .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_SEC].cval), | |
1810 | .accessfn = gt_ptimer_access, | |
1811 | .writefn = gt_sec_cval_write, .raw_writefn = raw_write, | |
1812 | }, | |
a7adc4b7 PM |
1813 | { .name = "CNTP_CVAL_EL0", .state = ARM_CP_STATE_AA64, |
1814 | .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 2, .opc2 = 2, | |
1815 | .access = PL1_RW | PL0_R, | |
1816 | .type = ARM_CP_IO, | |
1817 | .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].cval), | |
12cde08a | 1818 | .resetvalue = 0, .accessfn = gt_ptimer_access, |
0e3eca4c | 1819 | .writefn = gt_phys_cval_write, .raw_writefn = raw_write, |
55d284af PM |
1820 | }, |
1821 | { .name = "CNTV_CVAL", .cp = 15, .crm = 14, .opc1 = 3, | |
1822 | .access = PL1_RW | PL0_R, | |
7a0e58fa | 1823 | .type = ARM_CP_64BIT | ARM_CP_IO | ARM_CP_ALIAS, |
55d284af | 1824 | .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].cval), |
b061a82b | 1825 | .accessfn = gt_vtimer_access, |
0e3eca4c | 1826 | .writefn = gt_virt_cval_write, .raw_writefn = raw_write, |
a7adc4b7 PM |
1827 | }, |
1828 | { .name = "CNTV_CVAL_EL0", .state = ARM_CP_STATE_AA64, | |
1829 | .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 3, .opc2 = 2, | |
1830 | .access = PL1_RW | PL0_R, | |
1831 | .type = ARM_CP_IO, | |
1832 | .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].cval), | |
1833 | .resetvalue = 0, .accessfn = gt_vtimer_access, | |
0e3eca4c | 1834 | .writefn = gt_virt_cval_write, .raw_writefn = raw_write, |
55d284af | 1835 | }, |
b4d3978c PM |
1836 | /* Secure timer -- this is actually restricted to only EL3 |
1837 | * and configurably Secure-EL1 via the accessfn. | |
1838 | */ | |
1839 | { .name = "CNTPS_TVAL_EL1", .state = ARM_CP_STATE_AA64, | |
1840 | .opc0 = 3, .opc1 = 7, .crn = 14, .crm = 2, .opc2 = 0, | |
1841 | .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL1_RW, | |
1842 | .accessfn = gt_stimer_access, | |
1843 | .readfn = gt_sec_tval_read, | |
1844 | .writefn = gt_sec_tval_write, | |
1845 | .resetfn = gt_sec_timer_reset, | |
1846 | }, | |
1847 | { .name = "CNTPS_CTL_EL1", .state = ARM_CP_STATE_AA64, | |
1848 | .opc0 = 3, .opc1 = 7, .crn = 14, .crm = 2, .opc2 = 1, | |
1849 | .type = ARM_CP_IO, .access = PL1_RW, | |
1850 | .accessfn = gt_stimer_access, | |
1851 | .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_SEC].ctl), | |
1852 | .resetvalue = 0, | |
1853 | .writefn = gt_sec_ctl_write, .raw_writefn = raw_write, | |
1854 | }, | |
1855 | { .name = "CNTPS_CVAL_EL1", .state = ARM_CP_STATE_AA64, | |
1856 | .opc0 = 3, .opc1 = 7, .crn = 14, .crm = 2, .opc2 = 2, | |
1857 | .type = ARM_CP_IO, .access = PL1_RW, | |
1858 | .accessfn = gt_stimer_access, | |
1859 | .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_SEC].cval), | |
1860 | .writefn = gt_sec_cval_write, .raw_writefn = raw_write, | |
1861 | }, | |
55d284af PM |
1862 | REGINFO_SENTINEL |
1863 | }; | |
1864 | ||
1865 | #else | |
1866 | /* In user-mode none of the generic timer registers are accessible, | |
bc72ad67 | 1867 | * and their implementation depends on QEMU_CLOCK_VIRTUAL and qdev gpio outputs, |
55d284af PM |
1868 | * so instead just don't register any of them. |
1869 | */ | |
6cc7a3ae | 1870 | static const ARMCPRegInfo generic_timer_cp_reginfo[] = { |
6cc7a3ae PM |
1871 | REGINFO_SENTINEL |
1872 | }; | |
1873 | ||
55d284af PM |
1874 | #endif |
1875 | ||
c4241c7d | 1876 | static void par_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) |
4a501606 | 1877 | { |
891a2fe7 | 1878 | if (arm_feature(env, ARM_FEATURE_LPAE)) { |
8d5c773e | 1879 | raw_write(env, ri, value); |
891a2fe7 | 1880 | } else if (arm_feature(env, ARM_FEATURE_V7)) { |
8d5c773e | 1881 | raw_write(env, ri, value & 0xfffff6ff); |
4a501606 | 1882 | } else { |
8d5c773e | 1883 | raw_write(env, ri, value & 0xfffff1ff); |
4a501606 | 1884 | } |
4a501606 PM |
1885 | } |
1886 | ||
1887 | #ifndef CONFIG_USER_ONLY | |
1888 | /* get_phys_addr() isn't present for user-mode-only targets */ | |
702a9357 | 1889 | |
3f208fd7 PM |
1890 | static CPAccessResult ats_access(CPUARMState *env, const ARMCPRegInfo *ri, |
1891 | bool isread) | |
92611c00 PM |
1892 | { |
1893 | if (ri->opc2 & 4) { | |
87562e4f PM |
1894 | /* The ATS12NSO* operations must trap to EL3 if executed in |
1895 | * Secure EL1 (which can only happen if EL3 is AArch64). | |
1896 | * They are simply UNDEF if executed from NS EL1. | |
1897 | * They function normally from EL2 or EL3. | |
92611c00 | 1898 | */ |
87562e4f PM |
1899 | if (arm_current_el(env) == 1) { |
1900 | if (arm_is_secure_below_el3(env)) { | |
1901 | return CP_ACCESS_TRAP_UNCATEGORIZED_EL3; | |
1902 | } | |
1903 | return CP_ACCESS_TRAP_UNCATEGORIZED; | |
1904 | } | |
92611c00 PM |
1905 | } |
1906 | return CP_ACCESS_OK; | |
1907 | } | |
1908 | ||
060e8a48 | 1909 | static uint64_t do_ats_write(CPUARMState *env, uint64_t value, |
d3649702 | 1910 | int access_type, ARMMMUIdx mmu_idx) |
4a501606 | 1911 | { |
a8170e5e | 1912 | hwaddr phys_addr; |
4a501606 PM |
1913 | target_ulong page_size; |
1914 | int prot; | |
b7cc4e82 PC |
1915 | uint32_t fsr; |
1916 | bool ret; | |
01c097f7 | 1917 | uint64_t par64; |
8bf5b6a9 | 1918 | MemTxAttrs attrs = {}; |
e14b5a23 | 1919 | ARMMMUFaultInfo fi = {}; |
4a501606 | 1920 | |
d3649702 | 1921 | ret = get_phys_addr(env, value, access_type, mmu_idx, |
e14b5a23 | 1922 | &phys_addr, &attrs, &prot, &page_size, &fsr, &fi); |
702a9357 | 1923 | if (extended_addresses_enabled(env)) { |
b7cc4e82 | 1924 | /* fsr is a DFSR/IFSR value for the long descriptor |
702a9357 PM |
1925 | * translation table format, but with WnR always clear. |
1926 | * Convert it to a 64-bit PAR. | |
1927 | */ | |
01c097f7 | 1928 | par64 = (1 << 11); /* LPAE bit always set */ |
b7cc4e82 | 1929 | if (!ret) { |
702a9357 | 1930 | par64 |= phys_addr & ~0xfffULL; |
8bf5b6a9 PM |
1931 | if (!attrs.secure) { |
1932 | par64 |= (1 << 9); /* NS */ | |
1933 | } | |
702a9357 | 1934 | /* We don't set the ATTR or SH fields in the PAR. */ |
4a501606 | 1935 | } else { |
702a9357 | 1936 | par64 |= 1; /* F */ |
b7cc4e82 | 1937 | par64 |= (fsr & 0x3f) << 1; /* FS */ |
702a9357 PM |
1938 | /* Note that S2WLK and FSTAGE are always zero, because we don't |
1939 | * implement virtualization and therefore there can't be a stage 2 | |
1940 | * fault. | |
1941 | */ | |
4a501606 PM |
1942 | } |
1943 | } else { | |
b7cc4e82 | 1944 | /* fsr is a DFSR/IFSR value for the short descriptor |
702a9357 PM |
1945 | * translation table format (with WnR always clear). |
1946 | * Convert it to a 32-bit PAR. | |
1947 | */ | |
b7cc4e82 | 1948 | if (!ret) { |
702a9357 PM |
1949 | /* We do not set any attribute bits in the PAR */ |
1950 | if (page_size == (1 << 24) | |
1951 | && arm_feature(env, ARM_FEATURE_V7)) { | |
01c097f7 | 1952 | par64 = (phys_addr & 0xff000000) | (1 << 1); |
702a9357 | 1953 | } else { |
01c097f7 | 1954 | par64 = phys_addr & 0xfffff000; |
702a9357 | 1955 | } |
8bf5b6a9 PM |
1956 | if (!attrs.secure) { |
1957 | par64 |= (1 << 9); /* NS */ | |
1958 | } | |
702a9357 | 1959 | } else { |
b7cc4e82 PC |
1960 | par64 = ((fsr & (1 << 10)) >> 5) | ((fsr & (1 << 12)) >> 6) | |
1961 | ((fsr & 0xf) << 1) | 1; | |
702a9357 | 1962 | } |
4a501606 | 1963 | } |
060e8a48 PM |
1964 | return par64; |
1965 | } | |
1966 | ||
1967 | static void ats_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) | |
1968 | { | |
060e8a48 PM |
1969 | int access_type = ri->opc2 & 1; |
1970 | uint64_t par64; | |
d3649702 PM |
1971 | ARMMMUIdx mmu_idx; |
1972 | int el = arm_current_el(env); | |
1973 | bool secure = arm_is_secure_below_el3(env); | |
060e8a48 | 1974 | |
d3649702 PM |
1975 | switch (ri->opc2 & 6) { |
1976 | case 0: | |
1977 | /* stage 1 current state PL1: ATS1CPR, ATS1CPW */ | |
1978 | switch (el) { | |
1979 | case 3: | |
1980 | mmu_idx = ARMMMUIdx_S1E3; | |
1981 | break; | |
1982 | case 2: | |
1983 | mmu_idx = ARMMMUIdx_S1NSE1; | |
1984 | break; | |
1985 | case 1: | |
1986 | mmu_idx = secure ? ARMMMUIdx_S1SE1 : ARMMMUIdx_S1NSE1; | |
1987 | break; | |
1988 | default: | |
1989 | g_assert_not_reached(); | |
1990 | } | |
1991 | break; | |
1992 | case 2: | |
1993 | /* stage 1 current state PL0: ATS1CUR, ATS1CUW */ | |
1994 | switch (el) { | |
1995 | case 3: | |
1996 | mmu_idx = ARMMMUIdx_S1SE0; | |
1997 | break; | |
1998 | case 2: | |
1999 | mmu_idx = ARMMMUIdx_S1NSE0; | |
2000 | break; | |
2001 | case 1: | |
2002 | mmu_idx = secure ? ARMMMUIdx_S1SE0 : ARMMMUIdx_S1NSE0; | |
2003 | break; | |
2004 | default: | |
2005 | g_assert_not_reached(); | |
2006 | } | |
2007 | break; | |
2008 | case 4: | |
2009 | /* stage 1+2 NonSecure PL1: ATS12NSOPR, ATS12NSOPW */ | |
2010 | mmu_idx = ARMMMUIdx_S12NSE1; | |
2011 | break; | |
2012 | case 6: | |
2013 | /* stage 1+2 NonSecure PL0: ATS12NSOUR, ATS12NSOUW */ | |
2014 | mmu_idx = ARMMMUIdx_S12NSE0; | |
2015 | break; | |
2016 | default: | |
2017 | g_assert_not_reached(); | |
2018 | } | |
2019 | ||
2020 | par64 = do_ats_write(env, value, access_type, mmu_idx); | |
01c097f7 FA |
2021 | |
2022 | A32_BANKED_CURRENT_REG_SET(env, par, par64); | |
4a501606 | 2023 | } |
060e8a48 | 2024 | |
14db7fe0 PM |
2025 | static void ats1h_write(CPUARMState *env, const ARMCPRegInfo *ri, |
2026 | uint64_t value) | |
2027 | { | |
2028 | int access_type = ri->opc2 & 1; | |
2029 | uint64_t par64; | |
2030 | ||
2031 | par64 = do_ats_write(env, value, access_type, ARMMMUIdx_S2NS); | |
2032 | ||
2033 | A32_BANKED_CURRENT_REG_SET(env, par, par64); | |
2034 | } | |
2035 | ||
3f208fd7 PM |
2036 | static CPAccessResult at_s1e2_access(CPUARMState *env, const ARMCPRegInfo *ri, |
2037 | bool isread) | |
2a47df95 PM |
2038 | { |
2039 | if (arm_current_el(env) == 3 && !(env->cp15.scr_el3 & SCR_NS)) { | |
2040 | return CP_ACCESS_TRAP; | |
2041 | } | |
2042 | return CP_ACCESS_OK; | |
2043 | } | |
2044 | ||
060e8a48 PM |
2045 | static void ats_write64(CPUARMState *env, const ARMCPRegInfo *ri, |
2046 | uint64_t value) | |
2047 | { | |
060e8a48 | 2048 | int access_type = ri->opc2 & 1; |
d3649702 PM |
2049 | ARMMMUIdx mmu_idx; |
2050 | int secure = arm_is_secure_below_el3(env); | |
2051 | ||
2052 | switch (ri->opc2 & 6) { | |
2053 | case 0: | |
2054 | switch (ri->opc1) { | |
2055 | case 0: /* AT S1E1R, AT S1E1W */ | |
2056 | mmu_idx = secure ? ARMMMUIdx_S1SE1 : ARMMMUIdx_S1NSE1; | |
2057 | break; | |
2058 | case 4: /* AT S1E2R, AT S1E2W */ | |
2059 | mmu_idx = ARMMMUIdx_S1E2; | |
2060 | break; | |
2061 | case 6: /* AT S1E3R, AT S1E3W */ | |
2062 | mmu_idx = ARMMMUIdx_S1E3; | |
2063 | break; | |
2064 | default: | |
2065 | g_assert_not_reached(); | |
2066 | } | |
2067 | break; | |
2068 | case 2: /* AT S1E0R, AT S1E0W */ | |
2069 | mmu_idx = secure ? ARMMMUIdx_S1SE0 : ARMMMUIdx_S1NSE0; | |
2070 | break; | |
2071 | case 4: /* AT S12E1R, AT S12E1W */ | |
2a47df95 | 2072 | mmu_idx = secure ? ARMMMUIdx_S1SE1 : ARMMMUIdx_S12NSE1; |
d3649702 PM |
2073 | break; |
2074 | case 6: /* AT S12E0R, AT S12E0W */ | |
2a47df95 | 2075 | mmu_idx = secure ? ARMMMUIdx_S1SE0 : ARMMMUIdx_S12NSE0; |
d3649702 PM |
2076 | break; |
2077 | default: | |
2078 | g_assert_not_reached(); | |
2079 | } | |
060e8a48 | 2080 | |
d3649702 | 2081 | env->cp15.par_el[1] = do_ats_write(env, value, access_type, mmu_idx); |
060e8a48 | 2082 | } |
4a501606 PM |
2083 | #endif |
2084 | ||
2085 | static const ARMCPRegInfo vapa_cp_reginfo[] = { | |
2086 | { .name = "PAR", .cp = 15, .crn = 7, .crm = 4, .opc1 = 0, .opc2 = 0, | |
2087 | .access = PL1_RW, .resetvalue = 0, | |
01c097f7 FA |
2088 | .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.par_s), |
2089 | offsetoflow32(CPUARMState, cp15.par_ns) }, | |
4a501606 PM |
2090 | .writefn = par_write }, |
2091 | #ifndef CONFIG_USER_ONLY | |
87562e4f | 2092 | /* This underdecoding is safe because the reginfo is NO_RAW. */ |
4a501606 | 2093 | { .name = "ATS", .cp = 15, .crn = 7, .crm = 8, .opc1 = 0, .opc2 = CP_ANY, |
92611c00 | 2094 | .access = PL1_W, .accessfn = ats_access, |
7a0e58fa | 2095 | .writefn = ats_write, .type = ARM_CP_NO_RAW }, |
4a501606 PM |
2096 | #endif |
2097 | REGINFO_SENTINEL | |
2098 | }; | |
2099 | ||
18032bec PM |
2100 | /* Return basic MPU access permission bits. */ |
2101 | static uint32_t simple_mpu_ap_bits(uint32_t val) | |
2102 | { | |
2103 | uint32_t ret; | |
2104 | uint32_t mask; | |
2105 | int i; | |
2106 | ret = 0; | |
2107 | mask = 3; | |
2108 | for (i = 0; i < 16; i += 2) { | |
2109 | ret |= (val >> i) & mask; | |
2110 | mask <<= 2; | |
2111 | } | |
2112 | return ret; | |
2113 | } | |
2114 | ||
2115 | /* Pad basic MPU access permission bits to extended format. */ | |
2116 | static uint32_t extended_mpu_ap_bits(uint32_t val) | |
2117 | { | |
2118 | uint32_t ret; | |
2119 | uint32_t mask; | |
2120 | int i; | |
2121 | ret = 0; | |
2122 | mask = 3; | |
2123 | for (i = 0; i < 16; i += 2) { | |
2124 | ret |= (val & mask) << i; | |
2125 | mask <<= 2; | |
2126 | } | |
2127 | return ret; | |
2128 | } | |
2129 | ||
c4241c7d PM |
2130 | static void pmsav5_data_ap_write(CPUARMState *env, const ARMCPRegInfo *ri, |
2131 | uint64_t value) | |
18032bec | 2132 | { |
7e09797c | 2133 | env->cp15.pmsav5_data_ap = extended_mpu_ap_bits(value); |
18032bec PM |
2134 | } |
2135 | ||
c4241c7d | 2136 | static uint64_t pmsav5_data_ap_read(CPUARMState *env, const ARMCPRegInfo *ri) |
18032bec | 2137 | { |
7e09797c | 2138 | return simple_mpu_ap_bits(env->cp15.pmsav5_data_ap); |
18032bec PM |
2139 | } |
2140 | ||
c4241c7d PM |
2141 | static void pmsav5_insn_ap_write(CPUARMState *env, const ARMCPRegInfo *ri, |
2142 | uint64_t value) | |
18032bec | 2143 | { |
7e09797c | 2144 | env->cp15.pmsav5_insn_ap = extended_mpu_ap_bits(value); |
18032bec PM |
2145 | } |
2146 | ||
c4241c7d | 2147 | static uint64_t pmsav5_insn_ap_read(CPUARMState *env, const ARMCPRegInfo *ri) |
18032bec | 2148 | { |
7e09797c | 2149 | return simple_mpu_ap_bits(env->cp15.pmsav5_insn_ap); |
18032bec PM |
2150 | } |
2151 | ||
6cb0b013 PC |
2152 | static uint64_t pmsav7_read(CPUARMState *env, const ARMCPRegInfo *ri) |
2153 | { | |
2154 | uint32_t *u32p = *(uint32_t **)raw_ptr(env, ri); | |
2155 | ||
2156 | if (!u32p) { | |
2157 | return 0; | |
2158 | } | |
2159 | ||
2160 | u32p += env->cp15.c6_rgnr; | |
2161 | return *u32p; | |
2162 | } | |
2163 | ||
2164 | static void pmsav7_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
2165 | uint64_t value) | |
2166 | { | |
2167 | ARMCPU *cpu = arm_env_get_cpu(env); | |
2168 | uint32_t *u32p = *(uint32_t **)raw_ptr(env, ri); | |
2169 | ||
2170 | if (!u32p) { | |
2171 | return; | |
2172 | } | |
2173 | ||
2174 | u32p += env->cp15.c6_rgnr; | |
2175 | tlb_flush(CPU(cpu), 1); /* Mappings may have changed - purge! */ | |
2176 | *u32p = value; | |
2177 | } | |
2178 | ||
2179 | static void pmsav7_reset(CPUARMState *env, const ARMCPRegInfo *ri) | |
2180 | { | |
2181 | ARMCPU *cpu = arm_env_get_cpu(env); | |
2182 | uint32_t *u32p = *(uint32_t **)raw_ptr(env, ri); | |
2183 | ||
2184 | if (!u32p) { | |
2185 | return; | |
2186 | } | |
2187 | ||
2188 | memset(u32p, 0, sizeof(*u32p) * cpu->pmsav7_dregion); | |
2189 | } | |
2190 | ||
2191 | static void pmsav7_rgnr_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
2192 | uint64_t value) | |
2193 | { | |
2194 | ARMCPU *cpu = arm_env_get_cpu(env); | |
2195 | uint32_t nrgs = cpu->pmsav7_dregion; | |
2196 | ||
2197 | if (value >= nrgs) { | |
2198 | qemu_log_mask(LOG_GUEST_ERROR, | |
2199 | "PMSAv7 RGNR write >= # supported regions, %" PRIu32 | |
2200 | " > %" PRIu32 "\n", (uint32_t)value, nrgs); | |
2201 | return; | |
2202 | } | |
2203 | ||
2204 | raw_write(env, ri, value); | |
2205 | } | |
2206 | ||
2207 | static const ARMCPRegInfo pmsav7_cp_reginfo[] = { | |
2208 | { .name = "DRBAR", .cp = 15, .crn = 6, .opc1 = 0, .crm = 1, .opc2 = 0, | |
2209 | .access = PL1_RW, .type = ARM_CP_NO_RAW, | |
2210 | .fieldoffset = offsetof(CPUARMState, pmsav7.drbar), | |
2211 | .readfn = pmsav7_read, .writefn = pmsav7_write, .resetfn = pmsav7_reset }, | |
2212 | { .name = "DRSR", .cp = 15, .crn = 6, .opc1 = 0, .crm = 1, .opc2 = 2, | |
2213 | .access = PL1_RW, .type = ARM_CP_NO_RAW, | |
2214 | .fieldoffset = offsetof(CPUARMState, pmsav7.drsr), | |
2215 | .readfn = pmsav7_read, .writefn = pmsav7_write, .resetfn = pmsav7_reset }, | |
2216 | { .name = "DRACR", .cp = 15, .crn = 6, .opc1 = 0, .crm = 1, .opc2 = 4, | |
2217 | .access = PL1_RW, .type = ARM_CP_NO_RAW, | |
2218 | .fieldoffset = offsetof(CPUARMState, pmsav7.dracr), | |
2219 | .readfn = pmsav7_read, .writefn = pmsav7_write, .resetfn = pmsav7_reset }, | |
2220 | { .name = "RGNR", .cp = 15, .crn = 6, .opc1 = 0, .crm = 2, .opc2 = 0, | |
2221 | .access = PL1_RW, | |
2222 | .fieldoffset = offsetof(CPUARMState, cp15.c6_rgnr), | |
2223 | .writefn = pmsav7_rgnr_write }, | |
2224 | REGINFO_SENTINEL | |
2225 | }; | |
2226 | ||
18032bec PM |
2227 | static const ARMCPRegInfo pmsav5_cp_reginfo[] = { |
2228 | { .name = "DATA_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 0, | |
7a0e58fa | 2229 | .access = PL1_RW, .type = ARM_CP_ALIAS, |
7e09797c | 2230 | .fieldoffset = offsetof(CPUARMState, cp15.pmsav5_data_ap), |
18032bec PM |
2231 | .readfn = pmsav5_data_ap_read, .writefn = pmsav5_data_ap_write, }, |
2232 | { .name = "INSN_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 1, | |
7a0e58fa | 2233 | .access = PL1_RW, .type = ARM_CP_ALIAS, |
7e09797c | 2234 | .fieldoffset = offsetof(CPUARMState, cp15.pmsav5_insn_ap), |
18032bec PM |
2235 | .readfn = pmsav5_insn_ap_read, .writefn = pmsav5_insn_ap_write, }, |
2236 | { .name = "DATA_EXT_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 2, | |
2237 | .access = PL1_RW, | |
7e09797c PM |
2238 | .fieldoffset = offsetof(CPUARMState, cp15.pmsav5_data_ap), |
2239 | .resetvalue = 0, }, | |
18032bec PM |
2240 | { .name = "INSN_EXT_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 3, |
2241 | .access = PL1_RW, | |
7e09797c PM |
2242 | .fieldoffset = offsetof(CPUARMState, cp15.pmsav5_insn_ap), |
2243 | .resetvalue = 0, }, | |
ecce5c3c PM |
2244 | { .name = "DCACHE_CFG", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 0, |
2245 | .access = PL1_RW, | |
2246 | .fieldoffset = offsetof(CPUARMState, cp15.c2_data), .resetvalue = 0, }, | |
2247 | { .name = "ICACHE_CFG", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 1, | |
2248 | .access = PL1_RW, | |
2249 | .fieldoffset = offsetof(CPUARMState, cp15.c2_insn), .resetvalue = 0, }, | |
06d76f31 | 2250 | /* Protection region base and size registers */ |
e508a92b PM |
2251 | { .name = "946_PRBS0", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, |
2252 | .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0, | |
2253 | .fieldoffset = offsetof(CPUARMState, cp15.c6_region[0]) }, | |
2254 | { .name = "946_PRBS1", .cp = 15, .crn = 6, .crm = 1, .opc1 = 0, | |
2255 | .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0, | |
2256 | .fieldoffset = offsetof(CPUARMState, cp15.c6_region[1]) }, | |
2257 | { .name = "946_PRBS2", .cp = 15, .crn = 6, .crm = 2, .opc1 = 0, | |
2258 | .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0, | |
2259 | .fieldoffset = offsetof(CPUARMState, cp15.c6_region[2]) }, | |
2260 | { .name = "946_PRBS3", .cp = 15, .crn = 6, .crm = 3, .opc1 = 0, | |
2261 | .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0, | |
2262 | .fieldoffset = offsetof(CPUARMState, cp15.c6_region[3]) }, | |
2263 | { .name = "946_PRBS4", .cp = 15, .crn = 6, .crm = 4, .opc1 = 0, | |
2264 | .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0, | |
2265 | .fieldoffset = offsetof(CPUARMState, cp15.c6_region[4]) }, | |
2266 | { .name = "946_PRBS5", .cp = 15, .crn = 6, .crm = 5, .opc1 = 0, | |
2267 | .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0, | |
2268 | .fieldoffset = offsetof(CPUARMState, cp15.c6_region[5]) }, | |
2269 | { .name = "946_PRBS6", .cp = 15, .crn = 6, .crm = 6, .opc1 = 0, | |
2270 | .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0, | |
2271 | .fieldoffset = offsetof(CPUARMState, cp15.c6_region[6]) }, | |
2272 | { .name = "946_PRBS7", .cp = 15, .crn = 6, .crm = 7, .opc1 = 0, | |
2273 | .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0, | |
2274 | .fieldoffset = offsetof(CPUARMState, cp15.c6_region[7]) }, | |
18032bec PM |
2275 | REGINFO_SENTINEL |
2276 | }; | |
2277 | ||
c4241c7d PM |
2278 | static void vmsa_ttbcr_raw_write(CPUARMState *env, const ARMCPRegInfo *ri, |
2279 | uint64_t value) | |
ecce5c3c | 2280 | { |
11f136ee | 2281 | TCR *tcr = raw_ptr(env, ri); |
2ebcebe2 PM |
2282 | int maskshift = extract32(value, 0, 3); |
2283 | ||
e389be16 FA |
2284 | if (!arm_feature(env, ARM_FEATURE_V8)) { |
2285 | if (arm_feature(env, ARM_FEATURE_LPAE) && (value & TTBCR_EAE)) { | |
2286 | /* Pre ARMv8 bits [21:19], [15:14] and [6:3] are UNK/SBZP when | |
2287 | * using Long-desciptor translation table format */ | |
2288 | value &= ~((7 << 19) | (3 << 14) | (0xf << 3)); | |
2289 | } else if (arm_feature(env, ARM_FEATURE_EL3)) { | |
2290 | /* In an implementation that includes the Security Extensions | |
2291 | * TTBCR has additional fields PD0 [4] and PD1 [5] for | |
2292 | * Short-descriptor translation table format. | |
2293 | */ | |
2294 | value &= TTBCR_PD1 | TTBCR_PD0 | TTBCR_N; | |
2295 | } else { | |
2296 | value &= TTBCR_N; | |
2297 | } | |
e42c4db3 | 2298 | } |
e389be16 | 2299 | |
b6af0975 | 2300 | /* Update the masks corresponding to the TCR bank being written |
11f136ee | 2301 | * Note that we always calculate mask and base_mask, but |
e42c4db3 | 2302 | * they are only used for short-descriptor tables (ie if EAE is 0); |
11f136ee FA |
2303 | * for long-descriptor tables the TCR fields are used differently |
2304 | * and the mask and base_mask values are meaningless. | |
e42c4db3 | 2305 | */ |
11f136ee FA |
2306 | tcr->raw_tcr = value; |
2307 | tcr->mask = ~(((uint32_t)0xffffffffu) >> maskshift); | |
2308 | tcr->base_mask = ~((uint32_t)0x3fffu >> maskshift); | |
ecce5c3c PM |
2309 | } |
2310 | ||
c4241c7d PM |
2311 | static void vmsa_ttbcr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
2312 | uint64_t value) | |
d4e6df63 | 2313 | { |
00c8cb0a AF |
2314 | ARMCPU *cpu = arm_env_get_cpu(env); |
2315 | ||
d4e6df63 PM |
2316 | if (arm_feature(env, ARM_FEATURE_LPAE)) { |
2317 | /* With LPAE the TTBCR could result in a change of ASID | |
2318 | * via the TTBCR.A1 bit, so do a TLB flush. | |
2319 | */ | |
00c8cb0a | 2320 | tlb_flush(CPU(cpu), 1); |
d4e6df63 | 2321 | } |
c4241c7d | 2322 | vmsa_ttbcr_raw_write(env, ri, value); |
d4e6df63 PM |
2323 | } |
2324 | ||
ecce5c3c PM |
2325 | static void vmsa_ttbcr_reset(CPUARMState *env, const ARMCPRegInfo *ri) |
2326 | { | |
11f136ee FA |
2327 | TCR *tcr = raw_ptr(env, ri); |
2328 | ||
2329 | /* Reset both the TCR as well as the masks corresponding to the bank of | |
2330 | * the TCR being reset. | |
2331 | */ | |
2332 | tcr->raw_tcr = 0; | |
2333 | tcr->mask = 0; | |
2334 | tcr->base_mask = 0xffffc000u; | |
ecce5c3c PM |
2335 | } |
2336 | ||
cb2e37df PM |
2337 | static void vmsa_tcr_el1_write(CPUARMState *env, const ARMCPRegInfo *ri, |
2338 | uint64_t value) | |
2339 | { | |
00c8cb0a | 2340 | ARMCPU *cpu = arm_env_get_cpu(env); |
11f136ee | 2341 | TCR *tcr = raw_ptr(env, ri); |
00c8cb0a | 2342 | |
cb2e37df | 2343 | /* For AArch64 the A1 bit could result in a change of ASID, so TLB flush. */ |
00c8cb0a | 2344 | tlb_flush(CPU(cpu), 1); |
11f136ee | 2345 | tcr->raw_tcr = value; |
cb2e37df PM |
2346 | } |
2347 | ||
327ed10f PM |
2348 | static void vmsa_ttbr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
2349 | uint64_t value) | |
2350 | { | |
2351 | /* 64 bit accesses to the TTBRs can change the ASID and so we | |
2352 | * must flush the TLB. | |
2353 | */ | |
2354 | if (cpreg_field_is_64bit(ri)) { | |
00c8cb0a AF |
2355 | ARMCPU *cpu = arm_env_get_cpu(env); |
2356 | ||
2357 | tlb_flush(CPU(cpu), 1); | |
327ed10f PM |
2358 | } |
2359 | raw_write(env, ri, value); | |
2360 | } | |
2361 | ||
b698e9cf EI |
2362 | static void vttbr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
2363 | uint64_t value) | |
2364 | { | |
2365 | ARMCPU *cpu = arm_env_get_cpu(env); | |
2366 | CPUState *cs = CPU(cpu); | |
2367 | ||
2368 | /* Accesses to VTTBR may change the VMID so we must flush the TLB. */ | |
2369 | if (raw_read(env, ri) != value) { | |
2370 | tlb_flush_by_mmuidx(cs, ARMMMUIdx_S12NSE1, ARMMMUIdx_S12NSE0, | |
2371 | ARMMMUIdx_S2NS, -1); | |
2372 | raw_write(env, ri, value); | |
2373 | } | |
2374 | } | |
2375 | ||
8e5d75c9 | 2376 | static const ARMCPRegInfo vmsa_pmsa_cp_reginfo[] = { |
18032bec | 2377 | { .name = "DFSR", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 0, |
7a0e58fa | 2378 | .access = PL1_RW, .type = ARM_CP_ALIAS, |
4a7e2d73 | 2379 | .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.dfsr_s), |
b061a82b | 2380 | offsetoflow32(CPUARMState, cp15.dfsr_ns) }, }, |
18032bec | 2381 | { .name = "IFSR", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 1, |
88ca1c2d FA |
2382 | .access = PL1_RW, .resetvalue = 0, |
2383 | .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.ifsr_s), | |
2384 | offsetoflow32(CPUARMState, cp15.ifsr_ns) } }, | |
8e5d75c9 PC |
2385 | { .name = "DFAR", .cp = 15, .opc1 = 0, .crn = 6, .crm = 0, .opc2 = 0, |
2386 | .access = PL1_RW, .resetvalue = 0, | |
2387 | .bank_fieldoffsets = { offsetof(CPUARMState, cp15.dfar_s), | |
2388 | offsetof(CPUARMState, cp15.dfar_ns) } }, | |
2389 | { .name = "FAR_EL1", .state = ARM_CP_STATE_AA64, | |
2390 | .opc0 = 3, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 0, | |
2391 | .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.far_el[1]), | |
2392 | .resetvalue = 0, }, | |
2393 | REGINFO_SENTINEL | |
2394 | }; | |
2395 | ||
2396 | static const ARMCPRegInfo vmsa_cp_reginfo[] = { | |
6cd8a264 RH |
2397 | { .name = "ESR_EL1", .state = ARM_CP_STATE_AA64, |
2398 | .opc0 = 3, .crn = 5, .crm = 2, .opc1 = 0, .opc2 = 0, | |
2399 | .access = PL1_RW, | |
d81c519c | 2400 | .fieldoffset = offsetof(CPUARMState, cp15.esr_el[1]), .resetvalue = 0, }, |
327ed10f | 2401 | { .name = "TTBR0_EL1", .state = ARM_CP_STATE_BOTH, |
7dd8c9af FA |
2402 | .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 0, .opc2 = 0, |
2403 | .access = PL1_RW, .writefn = vmsa_ttbr_write, .resetvalue = 0, | |
2404 | .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ttbr0_s), | |
2405 | offsetof(CPUARMState, cp15.ttbr0_ns) } }, | |
327ed10f | 2406 | { .name = "TTBR1_EL1", .state = ARM_CP_STATE_BOTH, |
7dd8c9af FA |
2407 | .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 0, .opc2 = 1, |
2408 | .access = PL1_RW, .writefn = vmsa_ttbr_write, .resetvalue = 0, | |
2409 | .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ttbr1_s), | |
2410 | offsetof(CPUARMState, cp15.ttbr1_ns) } }, | |
cb2e37df PM |
2411 | { .name = "TCR_EL1", .state = ARM_CP_STATE_AA64, |
2412 | .opc0 = 3, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 2, | |
2413 | .access = PL1_RW, .writefn = vmsa_tcr_el1_write, | |
2414 | .resetfn = vmsa_ttbcr_reset, .raw_writefn = raw_write, | |
11f136ee | 2415 | .fieldoffset = offsetof(CPUARMState, cp15.tcr_el[1]) }, |
cb2e37df | 2416 | { .name = "TTBCR", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 2, |
7a0e58fa | 2417 | .access = PL1_RW, .type = ARM_CP_ALIAS, .writefn = vmsa_ttbcr_write, |
b061a82b | 2418 | .raw_writefn = vmsa_ttbcr_raw_write, |
11f136ee FA |
2419 | .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.tcr_el[3]), |
2420 | offsetoflow32(CPUARMState, cp15.tcr_el[1])} }, | |
18032bec PM |
2421 | REGINFO_SENTINEL |
2422 | }; | |
2423 | ||
c4241c7d PM |
2424 | static void omap_ticonfig_write(CPUARMState *env, const ARMCPRegInfo *ri, |
2425 | uint64_t value) | |
1047b9d7 PM |
2426 | { |
2427 | env->cp15.c15_ticonfig = value & 0xe7; | |
2428 | /* The OS_TYPE bit in this register changes the reported CPUID! */ | |
2429 | env->cp15.c0_cpuid = (value & (1 << 5)) ? | |
2430 | ARM_CPUID_TI915T : ARM_CPUID_TI925T; | |
1047b9d7 PM |
2431 | } |
2432 | ||
c4241c7d PM |
2433 | static void omap_threadid_write(CPUARMState *env, const ARMCPRegInfo *ri, |
2434 | uint64_t value) | |
1047b9d7 PM |
2435 | { |
2436 | env->cp15.c15_threadid = value & 0xffff; | |
1047b9d7 PM |
2437 | } |
2438 | ||
c4241c7d PM |
2439 | static void omap_wfi_write(CPUARMState *env, const ARMCPRegInfo *ri, |
2440 | uint64_t value) | |
1047b9d7 PM |
2441 | { |
2442 | /* Wait-for-interrupt (deprecated) */ | |
c3affe56 | 2443 | cpu_interrupt(CPU(arm_env_get_cpu(env)), CPU_INTERRUPT_HALT); |
1047b9d7 PM |
2444 | } |
2445 | ||
c4241c7d PM |
2446 | static void omap_cachemaint_write(CPUARMState *env, const ARMCPRegInfo *ri, |
2447 | uint64_t value) | |
c4804214 PM |
2448 | { |
2449 | /* On OMAP there are registers indicating the max/min index of dcache lines | |
2450 | * containing a dirty line; cache flush operations have to reset these. | |
2451 | */ | |
2452 | env->cp15.c15_i_max = 0x000; | |
2453 | env->cp15.c15_i_min = 0xff0; | |
c4804214 PM |
2454 | } |
2455 | ||
18032bec PM |
2456 | static const ARMCPRegInfo omap_cp_reginfo[] = { |
2457 | { .name = "DFSR", .cp = 15, .crn = 5, .crm = CP_ANY, | |
2458 | .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_OVERRIDE, | |
d81c519c | 2459 | .fieldoffset = offsetoflow32(CPUARMState, cp15.esr_el[1]), |
6cd8a264 | 2460 | .resetvalue = 0, }, |
1047b9d7 PM |
2461 | { .name = "", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0, |
2462 | .access = PL1_RW, .type = ARM_CP_NOP }, | |
2463 | { .name = "TICONFIG", .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0, | |
2464 | .access = PL1_RW, | |
2465 | .fieldoffset = offsetof(CPUARMState, cp15.c15_ticonfig), .resetvalue = 0, | |
2466 | .writefn = omap_ticonfig_write }, | |
2467 | { .name = "IMAX", .cp = 15, .crn = 15, .crm = 2, .opc1 = 0, .opc2 = 0, | |
2468 | .access = PL1_RW, | |
2469 | .fieldoffset = offsetof(CPUARMState, cp15.c15_i_max), .resetvalue = 0, }, | |
2470 | { .name = "IMIN", .cp = 15, .crn = 15, .crm = 3, .opc1 = 0, .opc2 = 0, | |
2471 | .access = PL1_RW, .resetvalue = 0xff0, | |
2472 | .fieldoffset = offsetof(CPUARMState, cp15.c15_i_min) }, | |
2473 | { .name = "THREADID", .cp = 15, .crn = 15, .crm = 4, .opc1 = 0, .opc2 = 0, | |
2474 | .access = PL1_RW, | |
2475 | .fieldoffset = offsetof(CPUARMState, cp15.c15_threadid), .resetvalue = 0, | |
2476 | .writefn = omap_threadid_write }, | |
2477 | { .name = "TI925T_STATUS", .cp = 15, .crn = 15, | |
2478 | .crm = 8, .opc1 = 0, .opc2 = 0, .access = PL1_RW, | |
7a0e58fa | 2479 | .type = ARM_CP_NO_RAW, |
1047b9d7 PM |
2480 | .readfn = arm_cp_read_zero, .writefn = omap_wfi_write, }, |
2481 | /* TODO: Peripheral port remap register: | |
2482 | * On OMAP2 mcr p15, 0, rn, c15, c2, 4 sets up the interrupt controller | |
2483 | * base address at $rn & ~0xfff and map size of 0x200 << ($rn & 0xfff), | |
2484 | * when MMU is off. | |
2485 | */ | |
c4804214 | 2486 | { .name = "OMAP_CACHEMAINT", .cp = 15, .crn = 7, .crm = CP_ANY, |
d4e6df63 | 2487 | .opc1 = 0, .opc2 = CP_ANY, .access = PL1_W, |
7a0e58fa | 2488 | .type = ARM_CP_OVERRIDE | ARM_CP_NO_RAW, |
c4804214 | 2489 | .writefn = omap_cachemaint_write }, |
34f90529 PM |
2490 | { .name = "C9", .cp = 15, .crn = 9, |
2491 | .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, | |
2492 | .type = ARM_CP_CONST | ARM_CP_OVERRIDE, .resetvalue = 0 }, | |
1047b9d7 PM |
2493 | REGINFO_SENTINEL |
2494 | }; | |
2495 | ||
c4241c7d PM |
2496 | static void xscale_cpar_write(CPUARMState *env, const ARMCPRegInfo *ri, |
2497 | uint64_t value) | |
1047b9d7 | 2498 | { |
c0f4af17 | 2499 | env->cp15.c15_cpar = value & 0x3fff; |
1047b9d7 PM |
2500 | } |
2501 | ||
2502 | static const ARMCPRegInfo xscale_cp_reginfo[] = { | |
2503 | { .name = "XSCALE_CPAR", | |
2504 | .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0, .access = PL1_RW, | |
2505 | .fieldoffset = offsetof(CPUARMState, cp15.c15_cpar), .resetvalue = 0, | |
2506 | .writefn = xscale_cpar_write, }, | |
2771db27 PM |
2507 | { .name = "XSCALE_AUXCR", |
2508 | .cp = 15, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 1, .access = PL1_RW, | |
2509 | .fieldoffset = offsetof(CPUARMState, cp15.c1_xscaleauxcr), | |
2510 | .resetvalue = 0, }, | |
3b771579 PM |
2511 | /* XScale specific cache-lockdown: since we have no cache we NOP these |
2512 | * and hope the guest does not really rely on cache behaviour. | |
2513 | */ | |
2514 | { .name = "XSCALE_LOCK_ICACHE_LINE", | |
2515 | .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 0, | |
2516 | .access = PL1_W, .type = ARM_CP_NOP }, | |
2517 | { .name = "XSCALE_UNLOCK_ICACHE", | |
2518 | .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 1, | |
2519 | .access = PL1_W, .type = ARM_CP_NOP }, | |
2520 | { .name = "XSCALE_DCACHE_LOCK", | |
2521 | .cp = 15, .opc1 = 0, .crn = 9, .crm = 2, .opc2 = 0, | |
2522 | .access = PL1_RW, .type = ARM_CP_NOP }, | |
2523 | { .name = "XSCALE_UNLOCK_DCACHE", | |
2524 | .cp = 15, .opc1 = 0, .crn = 9, .crm = 2, .opc2 = 1, | |
2525 | .access = PL1_W, .type = ARM_CP_NOP }, | |
1047b9d7 PM |
2526 | REGINFO_SENTINEL |
2527 | }; | |
2528 | ||
2529 | static const ARMCPRegInfo dummy_c15_cp_reginfo[] = { | |
2530 | /* RAZ/WI the whole crn=15 space, when we don't have a more specific | |
2531 | * implementation of this implementation-defined space. | |
2532 | * Ideally this should eventually disappear in favour of actually | |
2533 | * implementing the correct behaviour for all cores. | |
2534 | */ | |
2535 | { .name = "C15_IMPDEF", .cp = 15, .crn = 15, | |
2536 | .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY, | |
3671cd87 | 2537 | .access = PL1_RW, |
7a0e58fa | 2538 | .type = ARM_CP_CONST | ARM_CP_NO_RAW | ARM_CP_OVERRIDE, |
d4e6df63 | 2539 | .resetvalue = 0 }, |
18032bec PM |
2540 | REGINFO_SENTINEL |
2541 | }; | |
2542 | ||
c4804214 PM |
2543 | static const ARMCPRegInfo cache_dirty_status_cp_reginfo[] = { |
2544 | /* Cache status: RAZ because we have no cache so it's always clean */ | |
2545 | { .name = "CDSR", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 6, | |
7a0e58fa | 2546 | .access = PL1_R, .type = ARM_CP_CONST | ARM_CP_NO_RAW, |
d4e6df63 | 2547 | .resetvalue = 0 }, |
c4804214 PM |
2548 | REGINFO_SENTINEL |
2549 | }; | |
2550 | ||
2551 | static const ARMCPRegInfo cache_block_ops_cp_reginfo[] = { | |
2552 | /* We never have a a block transfer operation in progress */ | |
2553 | { .name = "BXSR", .cp = 15, .crn = 7, .crm = 12, .opc1 = 0, .opc2 = 4, | |
7a0e58fa | 2554 | .access = PL0_R, .type = ARM_CP_CONST | ARM_CP_NO_RAW, |
d4e6df63 | 2555 | .resetvalue = 0 }, |
30b05bba PM |
2556 | /* The cache ops themselves: these all NOP for QEMU */ |
2557 | { .name = "IICR", .cp = 15, .crm = 5, .opc1 = 0, | |
2558 | .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT }, | |
2559 | { .name = "IDCR", .cp = 15, .crm = 6, .opc1 = 0, | |
2560 | .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT }, | |
2561 | { .name = "CDCR", .cp = 15, .crm = 12, .opc1 = 0, | |
2562 | .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT }, | |
2563 | { .name = "PIR", .cp = 15, .crm = 12, .opc1 = 1, | |
2564 | .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT }, | |
2565 | { .name = "PDR", .cp = 15, .crm = 12, .opc1 = 2, | |
2566 | .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT }, | |
2567 | { .name = "CIDCR", .cp = 15, .crm = 14, .opc1 = 0, | |
2568 | .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT }, | |
c4804214 PM |
2569 | REGINFO_SENTINEL |
2570 | }; | |
2571 | ||
2572 | static const ARMCPRegInfo cache_test_clean_cp_reginfo[] = { | |
2573 | /* The cache test-and-clean instructions always return (1 << 30) | |
2574 | * to indicate that there are no dirty cache lines. | |
2575 | */ | |
2576 | { .name = "TC_DCACHE", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 3, | |
7a0e58fa | 2577 | .access = PL0_R, .type = ARM_CP_CONST | ARM_CP_NO_RAW, |
d4e6df63 | 2578 | .resetvalue = (1 << 30) }, |
c4804214 | 2579 | { .name = "TCI_DCACHE", .cp = 15, .crn = 7, .crm = 14, .opc1 = 0, .opc2 = 3, |
7a0e58fa | 2580 | .access = PL0_R, .type = ARM_CP_CONST | ARM_CP_NO_RAW, |
d4e6df63 | 2581 | .resetvalue = (1 << 30) }, |
c4804214 PM |
2582 | REGINFO_SENTINEL |
2583 | }; | |
2584 | ||
34f90529 PM |
2585 | static const ARMCPRegInfo strongarm_cp_reginfo[] = { |
2586 | /* Ignore ReadBuffer accesses */ | |
2587 | { .name = "C9_READBUFFER", .cp = 15, .crn = 9, | |
2588 | .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY, | |
d4e6df63 | 2589 | .access = PL1_RW, .resetvalue = 0, |
7a0e58fa | 2590 | .type = ARM_CP_CONST | ARM_CP_OVERRIDE | ARM_CP_NO_RAW }, |
34f90529 PM |
2591 | REGINFO_SENTINEL |
2592 | }; | |
2593 | ||
731de9e6 EI |
2594 | static uint64_t midr_read(CPUARMState *env, const ARMCPRegInfo *ri) |
2595 | { | |
2596 | ARMCPU *cpu = arm_env_get_cpu(env); | |
2597 | unsigned int cur_el = arm_current_el(env); | |
2598 | bool secure = arm_is_secure(env); | |
2599 | ||
2600 | if (arm_feature(&cpu->env, ARM_FEATURE_EL2) && !secure && cur_el == 1) { | |
2601 | return env->cp15.vpidr_el2; | |
2602 | } | |
2603 | return raw_read(env, ri); | |
2604 | } | |
2605 | ||
06a7e647 | 2606 | static uint64_t mpidr_read_val(CPUARMState *env) |
81bdde9d | 2607 | { |
eb5e1d3c PF |
2608 | ARMCPU *cpu = ARM_CPU(arm_env_get_cpu(env)); |
2609 | uint64_t mpidr = cpu->mp_affinity; | |
2610 | ||
81bdde9d | 2611 | if (arm_feature(env, ARM_FEATURE_V7MP)) { |
78dbbbe4 | 2612 | mpidr |= (1U << 31); |
81bdde9d PM |
2613 | /* Cores which are uniprocessor (non-coherent) |
2614 | * but still implement the MP extensions set | |
a8e81b31 | 2615 | * bit 30. (For instance, Cortex-R5). |
81bdde9d | 2616 | */ |
a8e81b31 PC |
2617 | if (cpu->mp_is_up) { |
2618 | mpidr |= (1u << 30); | |
2619 | } | |
81bdde9d | 2620 | } |
c4241c7d | 2621 | return mpidr; |
81bdde9d PM |
2622 | } |
2623 | ||
06a7e647 EI |
2624 | static uint64_t mpidr_read(CPUARMState *env, const ARMCPRegInfo *ri) |
2625 | { | |
f0d574d6 EI |
2626 | unsigned int cur_el = arm_current_el(env); |
2627 | bool secure = arm_is_secure(env); | |
2628 | ||
2629 | if (arm_feature(env, ARM_FEATURE_EL2) && !secure && cur_el == 1) { | |
2630 | return env->cp15.vmpidr_el2; | |
2631 | } | |
06a7e647 EI |
2632 | return mpidr_read_val(env); |
2633 | } | |
2634 | ||
81bdde9d | 2635 | static const ARMCPRegInfo mpidr_cp_reginfo[] = { |
4b7fff2f PM |
2636 | { .name = "MPIDR", .state = ARM_CP_STATE_BOTH, |
2637 | .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 5, | |
7a0e58fa | 2638 | .access = PL1_R, .readfn = mpidr_read, .type = ARM_CP_NO_RAW }, |
81bdde9d PM |
2639 | REGINFO_SENTINEL |
2640 | }; | |
2641 | ||
7ac681cf | 2642 | static const ARMCPRegInfo lpae_cp_reginfo[] = { |
a903c449 | 2643 | /* NOP AMAIR0/1 */ |
b0fe2427 PM |
2644 | { .name = "AMAIR0", .state = ARM_CP_STATE_BOTH, |
2645 | .opc0 = 3, .crn = 10, .crm = 3, .opc1 = 0, .opc2 = 0, | |
a903c449 | 2646 | .access = PL1_RW, .type = ARM_CP_CONST, |
7ac681cf | 2647 | .resetvalue = 0 }, |
b0fe2427 | 2648 | /* AMAIR1 is mapped to AMAIR_EL1[63:32] */ |
7ac681cf | 2649 | { .name = "AMAIR1", .cp = 15, .crn = 10, .crm = 3, .opc1 = 0, .opc2 = 1, |
a903c449 | 2650 | .access = PL1_RW, .type = ARM_CP_CONST, |
7ac681cf | 2651 | .resetvalue = 0 }, |
891a2fe7 | 2652 | { .name = "PAR", .cp = 15, .crm = 7, .opc1 = 0, |
01c097f7 FA |
2653 | .access = PL1_RW, .type = ARM_CP_64BIT, .resetvalue = 0, |
2654 | .bank_fieldoffsets = { offsetof(CPUARMState, cp15.par_s), | |
2655 | offsetof(CPUARMState, cp15.par_ns)} }, | |
891a2fe7 | 2656 | { .name = "TTBR0", .cp = 15, .crm = 2, .opc1 = 0, |
7a0e58fa | 2657 | .access = PL1_RW, .type = ARM_CP_64BIT | ARM_CP_ALIAS, |
7dd8c9af FA |
2658 | .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ttbr0_s), |
2659 | offsetof(CPUARMState, cp15.ttbr0_ns) }, | |
b061a82b | 2660 | .writefn = vmsa_ttbr_write, }, |
891a2fe7 | 2661 | { .name = "TTBR1", .cp = 15, .crm = 2, .opc1 = 1, |
7a0e58fa | 2662 | .access = PL1_RW, .type = ARM_CP_64BIT | ARM_CP_ALIAS, |
7dd8c9af FA |
2663 | .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ttbr1_s), |
2664 | offsetof(CPUARMState, cp15.ttbr1_ns) }, | |
b061a82b | 2665 | .writefn = vmsa_ttbr_write, }, |
7ac681cf PM |
2666 | REGINFO_SENTINEL |
2667 | }; | |
2668 | ||
c4241c7d | 2669 | static uint64_t aa64_fpcr_read(CPUARMState *env, const ARMCPRegInfo *ri) |
b0d2b7d0 | 2670 | { |
c4241c7d | 2671 | return vfp_get_fpcr(env); |
b0d2b7d0 PM |
2672 | } |
2673 | ||
c4241c7d PM |
2674 | static void aa64_fpcr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
2675 | uint64_t value) | |
b0d2b7d0 PM |
2676 | { |
2677 | vfp_set_fpcr(env, value); | |
b0d2b7d0 PM |
2678 | } |
2679 | ||
c4241c7d | 2680 | static uint64_t aa64_fpsr_read(CPUARMState *env, const ARMCPRegInfo *ri) |
b0d2b7d0 | 2681 | { |
c4241c7d | 2682 | return vfp_get_fpsr(env); |
b0d2b7d0 PM |
2683 | } |
2684 | ||
c4241c7d PM |
2685 | static void aa64_fpsr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
2686 | uint64_t value) | |
b0d2b7d0 PM |
2687 | { |
2688 | vfp_set_fpsr(env, value); | |
b0d2b7d0 PM |
2689 | } |
2690 | ||
3f208fd7 PM |
2691 | static CPAccessResult aa64_daif_access(CPUARMState *env, const ARMCPRegInfo *ri, |
2692 | bool isread) | |
c2b820fe | 2693 | { |
137feaa9 | 2694 | if (arm_current_el(env) == 0 && !(env->cp15.sctlr_el[1] & SCTLR_UMA)) { |
c2b820fe PM |
2695 | return CP_ACCESS_TRAP; |
2696 | } | |
2697 | return CP_ACCESS_OK; | |
2698 | } | |
2699 | ||
2700 | static void aa64_daif_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
2701 | uint64_t value) | |
2702 | { | |
2703 | env->daif = value & PSTATE_DAIF; | |
2704 | } | |
2705 | ||
8af35c37 | 2706 | static CPAccessResult aa64_cacheop_access(CPUARMState *env, |
3f208fd7 PM |
2707 | const ARMCPRegInfo *ri, |
2708 | bool isread) | |
8af35c37 PM |
2709 | { |
2710 | /* Cache invalidate/clean: NOP, but EL0 must UNDEF unless | |
2711 | * SCTLR_EL1.UCI is set. | |
2712 | */ | |
137feaa9 | 2713 | if (arm_current_el(env) == 0 && !(env->cp15.sctlr_el[1] & SCTLR_UCI)) { |
8af35c37 PM |
2714 | return CP_ACCESS_TRAP; |
2715 | } | |
2716 | return CP_ACCESS_OK; | |
2717 | } | |
2718 | ||
dbb1fb27 AB |
2719 | /* See: D4.7.2 TLB maintenance requirements and the TLB maintenance instructions |
2720 | * Page D4-1736 (DDI0487A.b) | |
2721 | */ | |
2722 | ||
fd3ed969 PM |
2723 | static void tlbi_aa64_vmalle1_write(CPUARMState *env, const ARMCPRegInfo *ri, |
2724 | uint64_t value) | |
168aa23b | 2725 | { |
31b030d4 | 2726 | ARMCPU *cpu = arm_env_get_cpu(env); |
fd3ed969 | 2727 | CPUState *cs = CPU(cpu); |
dbb1fb27 | 2728 | |
fd3ed969 PM |
2729 | if (arm_is_secure_below_el3(env)) { |
2730 | tlb_flush_by_mmuidx(cs, ARMMMUIdx_S1SE1, ARMMMUIdx_S1SE0, -1); | |
2731 | } else { | |
2732 | tlb_flush_by_mmuidx(cs, ARMMMUIdx_S12NSE1, ARMMMUIdx_S12NSE0, -1); | |
2733 | } | |
168aa23b PM |
2734 | } |
2735 | ||
fd3ed969 PM |
2736 | static void tlbi_aa64_vmalle1is_write(CPUARMState *env, const ARMCPRegInfo *ri, |
2737 | uint64_t value) | |
168aa23b | 2738 | { |
fd3ed969 PM |
2739 | bool sec = arm_is_secure_below_el3(env); |
2740 | CPUState *other_cs; | |
dbb1fb27 | 2741 | |
fd3ed969 PM |
2742 | CPU_FOREACH(other_cs) { |
2743 | if (sec) { | |
2744 | tlb_flush_by_mmuidx(other_cs, ARMMMUIdx_S1SE1, ARMMMUIdx_S1SE0, -1); | |
2745 | } else { | |
2746 | tlb_flush_by_mmuidx(other_cs, ARMMMUIdx_S12NSE1, | |
2747 | ARMMMUIdx_S12NSE0, -1); | |
2748 | } | |
2749 | } | |
168aa23b PM |
2750 | } |
2751 | ||
fd3ed969 PM |
2752 | static void tlbi_aa64_alle1_write(CPUARMState *env, const ARMCPRegInfo *ri, |
2753 | uint64_t value) | |
168aa23b | 2754 | { |
fd3ed969 PM |
2755 | /* Note that the 'ALL' scope must invalidate both stage 1 and |
2756 | * stage 2 translations, whereas most other scopes only invalidate | |
2757 | * stage 1 translations. | |
2758 | */ | |
00c8cb0a | 2759 | ARMCPU *cpu = arm_env_get_cpu(env); |
fd3ed969 PM |
2760 | CPUState *cs = CPU(cpu); |
2761 | ||
2762 | if (arm_is_secure_below_el3(env)) { | |
2763 | tlb_flush_by_mmuidx(cs, ARMMMUIdx_S1SE1, ARMMMUIdx_S1SE0, -1); | |
2764 | } else { | |
2765 | if (arm_feature(env, ARM_FEATURE_EL2)) { | |
2766 | tlb_flush_by_mmuidx(cs, ARMMMUIdx_S12NSE1, ARMMMUIdx_S12NSE0, | |
2767 | ARMMMUIdx_S2NS, -1); | |
2768 | } else { | |
2769 | tlb_flush_by_mmuidx(cs, ARMMMUIdx_S12NSE1, ARMMMUIdx_S12NSE0, -1); | |
2770 | } | |
2771 | } | |
168aa23b PM |
2772 | } |
2773 | ||
fd3ed969 | 2774 | static void tlbi_aa64_alle2_write(CPUARMState *env, const ARMCPRegInfo *ri, |
fa439fc5 PM |
2775 | uint64_t value) |
2776 | { | |
fd3ed969 PM |
2777 | ARMCPU *cpu = arm_env_get_cpu(env); |
2778 | CPUState *cs = CPU(cpu); | |
2779 | ||
2780 | tlb_flush_by_mmuidx(cs, ARMMMUIdx_S1E2, -1); | |
2781 | } | |
2782 | ||
43efaa33 PM |
2783 | static void tlbi_aa64_alle3_write(CPUARMState *env, const ARMCPRegInfo *ri, |
2784 | uint64_t value) | |
2785 | { | |
2786 | ARMCPU *cpu = arm_env_get_cpu(env); | |
2787 | CPUState *cs = CPU(cpu); | |
2788 | ||
2789 | tlb_flush_by_mmuidx(cs, ARMMMUIdx_S1E3, -1); | |
2790 | } | |
2791 | ||
fd3ed969 PM |
2792 | static void tlbi_aa64_alle1is_write(CPUARMState *env, const ARMCPRegInfo *ri, |
2793 | uint64_t value) | |
2794 | { | |
2795 | /* Note that the 'ALL' scope must invalidate both stage 1 and | |
2796 | * stage 2 translations, whereas most other scopes only invalidate | |
2797 | * stage 1 translations. | |
2798 | */ | |
2799 | bool sec = arm_is_secure_below_el3(env); | |
2800 | bool has_el2 = arm_feature(env, ARM_FEATURE_EL2); | |
fa439fc5 | 2801 | CPUState *other_cs; |
fa439fc5 PM |
2802 | |
2803 | CPU_FOREACH(other_cs) { | |
fd3ed969 PM |
2804 | if (sec) { |
2805 | tlb_flush_by_mmuidx(other_cs, ARMMMUIdx_S1SE1, ARMMMUIdx_S1SE0, -1); | |
2806 | } else if (has_el2) { | |
2807 | tlb_flush_by_mmuidx(other_cs, ARMMMUIdx_S12NSE1, | |
2808 | ARMMMUIdx_S12NSE0, ARMMMUIdx_S2NS, -1); | |
2809 | } else { | |
2810 | tlb_flush_by_mmuidx(other_cs, ARMMMUIdx_S12NSE1, | |
2811 | ARMMMUIdx_S12NSE0, -1); | |
2812 | } | |
fa439fc5 PM |
2813 | } |
2814 | } | |
2815 | ||
2bfb9d75 PM |
2816 | static void tlbi_aa64_alle2is_write(CPUARMState *env, const ARMCPRegInfo *ri, |
2817 | uint64_t value) | |
2818 | { | |
2819 | CPUState *other_cs; | |
2820 | ||
2821 | CPU_FOREACH(other_cs) { | |
2822 | tlb_flush_by_mmuidx(other_cs, ARMMMUIdx_S1E2, -1); | |
2823 | } | |
2824 | } | |
2825 | ||
43efaa33 PM |
2826 | static void tlbi_aa64_alle3is_write(CPUARMState *env, const ARMCPRegInfo *ri, |
2827 | uint64_t value) | |
2828 | { | |
2829 | CPUState *other_cs; | |
2830 | ||
2831 | CPU_FOREACH(other_cs) { | |
2832 | tlb_flush_by_mmuidx(other_cs, ARMMMUIdx_S1E3, -1); | |
2833 | } | |
2834 | } | |
2835 | ||
fd3ed969 PM |
2836 | static void tlbi_aa64_vae1_write(CPUARMState *env, const ARMCPRegInfo *ri, |
2837 | uint64_t value) | |
2838 | { | |
2839 | /* Invalidate by VA, EL1&0 (AArch64 version). | |
2840 | * Currently handles all of VAE1, VAAE1, VAALE1 and VALE1, | |
2841 | * since we don't support flush-for-specific-ASID-only or | |
2842 | * flush-last-level-only. | |
2843 | */ | |
2844 | ARMCPU *cpu = arm_env_get_cpu(env); | |
2845 | CPUState *cs = CPU(cpu); | |
2846 | uint64_t pageaddr = sextract64(value << 12, 0, 56); | |
2847 | ||
2848 | if (arm_is_secure_below_el3(env)) { | |
2849 | tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdx_S1SE1, | |
2850 | ARMMMUIdx_S1SE0, -1); | |
2851 | } else { | |
2852 | tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdx_S12NSE1, | |
2853 | ARMMMUIdx_S12NSE0, -1); | |
2854 | } | |
2855 | } | |
2856 | ||
2857 | static void tlbi_aa64_vae2_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
2858 | uint64_t value) | |
fa439fc5 | 2859 | { |
fd3ed969 PM |
2860 | /* Invalidate by VA, EL2 |
2861 | * Currently handles both VAE2 and VALE2, since we don't support | |
2862 | * flush-last-level-only. | |
2863 | */ | |
2864 | ARMCPU *cpu = arm_env_get_cpu(env); | |
2865 | CPUState *cs = CPU(cpu); | |
2866 | uint64_t pageaddr = sextract64(value << 12, 0, 56); | |
2867 | ||
2868 | tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdx_S1E2, -1); | |
2869 | } | |
2870 | ||
43efaa33 PM |
2871 | static void tlbi_aa64_vae3_write(CPUARMState *env, const ARMCPRegInfo *ri, |
2872 | uint64_t value) | |
2873 | { | |
2874 | /* Invalidate by VA, EL3 | |
2875 | * Currently handles both VAE3 and VALE3, since we don't support | |
2876 | * flush-last-level-only. | |
2877 | */ | |
2878 | ARMCPU *cpu = arm_env_get_cpu(env); | |
2879 | CPUState *cs = CPU(cpu); | |
2880 | uint64_t pageaddr = sextract64(value << 12, 0, 56); | |
2881 | ||
2882 | tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdx_S1E3, -1); | |
2883 | } | |
2884 | ||
fd3ed969 PM |
2885 | static void tlbi_aa64_vae1is_write(CPUARMState *env, const ARMCPRegInfo *ri, |
2886 | uint64_t value) | |
2887 | { | |
2888 | bool sec = arm_is_secure_below_el3(env); | |
fa439fc5 PM |
2889 | CPUState *other_cs; |
2890 | uint64_t pageaddr = sextract64(value << 12, 0, 56); | |
2891 | ||
2892 | CPU_FOREACH(other_cs) { | |
fd3ed969 PM |
2893 | if (sec) { |
2894 | tlb_flush_page_by_mmuidx(other_cs, pageaddr, ARMMMUIdx_S1SE1, | |
2895 | ARMMMUIdx_S1SE0, -1); | |
2896 | } else { | |
2897 | tlb_flush_page_by_mmuidx(other_cs, pageaddr, ARMMMUIdx_S12NSE1, | |
2898 | ARMMMUIdx_S12NSE0, -1); | |
2899 | } | |
fa439fc5 PM |
2900 | } |
2901 | } | |
2902 | ||
fd3ed969 PM |
2903 | static void tlbi_aa64_vae2is_write(CPUARMState *env, const ARMCPRegInfo *ri, |
2904 | uint64_t value) | |
fa439fc5 PM |
2905 | { |
2906 | CPUState *other_cs; | |
fd3ed969 | 2907 | uint64_t pageaddr = sextract64(value << 12, 0, 56); |
fa439fc5 PM |
2908 | |
2909 | CPU_FOREACH(other_cs) { | |
fd3ed969 | 2910 | tlb_flush_page_by_mmuidx(other_cs, pageaddr, ARMMMUIdx_S1E2, -1); |
fa439fc5 PM |
2911 | } |
2912 | } | |
2913 | ||
43efaa33 PM |
2914 | static void tlbi_aa64_vae3is_write(CPUARMState *env, const ARMCPRegInfo *ri, |
2915 | uint64_t value) | |
2916 | { | |
2917 | CPUState *other_cs; | |
2918 | uint64_t pageaddr = sextract64(value << 12, 0, 56); | |
2919 | ||
2920 | CPU_FOREACH(other_cs) { | |
2921 | tlb_flush_page_by_mmuidx(other_cs, pageaddr, ARMMMUIdx_S1E3, -1); | |
2922 | } | |
2923 | } | |
2924 | ||
cea66e91 PM |
2925 | static void tlbi_aa64_ipas2e1_write(CPUARMState *env, const ARMCPRegInfo *ri, |
2926 | uint64_t value) | |
2927 | { | |
2928 | /* Invalidate by IPA. This has to invalidate any structures that | |
2929 | * contain only stage 2 translation information, but does not need | |
2930 | * to apply to structures that contain combined stage 1 and stage 2 | |
2931 | * translation information. | |
2932 | * This must NOP if EL2 isn't implemented or SCR_EL3.NS is zero. | |
2933 | */ | |
2934 | ARMCPU *cpu = arm_env_get_cpu(env); | |
2935 | CPUState *cs = CPU(cpu); | |
2936 | uint64_t pageaddr; | |
2937 | ||
2938 | if (!arm_feature(env, ARM_FEATURE_EL2) || !(env->cp15.scr_el3 & SCR_NS)) { | |
2939 | return; | |
2940 | } | |
2941 | ||
2942 | pageaddr = sextract64(value << 12, 0, 48); | |
2943 | ||
2944 | tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdx_S2NS, -1); | |
2945 | } | |
2946 | ||
2947 | static void tlbi_aa64_ipas2e1is_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
2948 | uint64_t value) | |
2949 | { | |
2950 | CPUState *other_cs; | |
2951 | uint64_t pageaddr; | |
2952 | ||
2953 | if (!arm_feature(env, ARM_FEATURE_EL2) || !(env->cp15.scr_el3 & SCR_NS)) { | |
2954 | return; | |
2955 | } | |
2956 | ||
2957 | pageaddr = sextract64(value << 12, 0, 48); | |
2958 | ||
2959 | CPU_FOREACH(other_cs) { | |
2960 | tlb_flush_page_by_mmuidx(other_cs, pageaddr, ARMMMUIdx_S2NS, -1); | |
2961 | } | |
2962 | } | |
2963 | ||
3f208fd7 PM |
2964 | static CPAccessResult aa64_zva_access(CPUARMState *env, const ARMCPRegInfo *ri, |
2965 | bool isread) | |
aca3f40b PM |
2966 | { |
2967 | /* We don't implement EL2, so the only control on DC ZVA is the | |
2968 | * bit in the SCTLR which can prohibit access for EL0. | |
2969 | */ | |
137feaa9 | 2970 | if (arm_current_el(env) == 0 && !(env->cp15.sctlr_el[1] & SCTLR_DZE)) { |
aca3f40b PM |
2971 | return CP_ACCESS_TRAP; |
2972 | } | |
2973 | return CP_ACCESS_OK; | |
2974 | } | |
2975 | ||
2976 | static uint64_t aa64_dczid_read(CPUARMState *env, const ARMCPRegInfo *ri) | |
2977 | { | |
2978 | ARMCPU *cpu = arm_env_get_cpu(env); | |
2979 | int dzp_bit = 1 << 4; | |
2980 | ||
2981 | /* DZP indicates whether DC ZVA access is allowed */ | |
3f208fd7 | 2982 | if (aa64_zva_access(env, NULL, false) == CP_ACCESS_OK) { |
aca3f40b PM |
2983 | dzp_bit = 0; |
2984 | } | |
2985 | return cpu->dcz_blocksize | dzp_bit; | |
2986 | } | |
2987 | ||
3f208fd7 PM |
2988 | static CPAccessResult sp_el0_access(CPUARMState *env, const ARMCPRegInfo *ri, |
2989 | bool isread) | |
f502cfc2 | 2990 | { |
cdcf1405 | 2991 | if (!(env->pstate & PSTATE_SP)) { |
f502cfc2 PM |
2992 | /* Access to SP_EL0 is undefined if it's being used as |
2993 | * the stack pointer. | |
2994 | */ | |
2995 | return CP_ACCESS_TRAP_UNCATEGORIZED; | |
2996 | } | |
2997 | return CP_ACCESS_OK; | |
2998 | } | |
2999 | ||
3000 | static uint64_t spsel_read(CPUARMState *env, const ARMCPRegInfo *ri) | |
3001 | { | |
3002 | return env->pstate & PSTATE_SP; | |
3003 | } | |
3004 | ||
3005 | static void spsel_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t val) | |
3006 | { | |
3007 | update_spsel(env, val); | |
3008 | } | |
3009 | ||
137feaa9 FA |
3010 | static void sctlr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
3011 | uint64_t value) | |
3012 | { | |
3013 | ARMCPU *cpu = arm_env_get_cpu(env); | |
3014 | ||
3015 | if (raw_read(env, ri) == value) { | |
3016 | /* Skip the TLB flush if nothing actually changed; Linux likes | |
3017 | * to do a lot of pointless SCTLR writes. | |
3018 | */ | |
3019 | return; | |
3020 | } | |
3021 | ||
3022 | raw_write(env, ri, value); | |
3023 | /* ??? Lots of these bits are not implemented. */ | |
3024 | /* This may enable/disable the MMU, so do a TLB flush. */ | |
3025 | tlb_flush(CPU(cpu), 1); | |
3026 | } | |
3027 | ||
3f208fd7 PM |
3028 | static CPAccessResult fpexc32_access(CPUARMState *env, const ARMCPRegInfo *ri, |
3029 | bool isread) | |
03fbf20f PM |
3030 | { |
3031 | if ((env->cp15.cptr_el[2] & CPTR_TFP) && arm_current_el(env) == 2) { | |
f2cae609 | 3032 | return CP_ACCESS_TRAP_FP_EL2; |
03fbf20f PM |
3033 | } |
3034 | if (env->cp15.cptr_el[3] & CPTR_TFP) { | |
f2cae609 | 3035 | return CP_ACCESS_TRAP_FP_EL3; |
03fbf20f PM |
3036 | } |
3037 | return CP_ACCESS_OK; | |
3038 | } | |
3039 | ||
b0d2b7d0 PM |
3040 | static const ARMCPRegInfo v8_cp_reginfo[] = { |
3041 | /* Minimal set of EL0-visible registers. This will need to be expanded | |
3042 | * significantly for system emulation of AArch64 CPUs. | |
3043 | */ | |
3044 | { .name = "NZCV", .state = ARM_CP_STATE_AA64, | |
3045 | .opc0 = 3, .opc1 = 3, .opc2 = 0, .crn = 4, .crm = 2, | |
3046 | .access = PL0_RW, .type = ARM_CP_NZCV }, | |
c2b820fe PM |
3047 | { .name = "DAIF", .state = ARM_CP_STATE_AA64, |
3048 | .opc0 = 3, .opc1 = 3, .opc2 = 1, .crn = 4, .crm = 2, | |
7a0e58fa | 3049 | .type = ARM_CP_NO_RAW, |
c2b820fe PM |
3050 | .access = PL0_RW, .accessfn = aa64_daif_access, |
3051 | .fieldoffset = offsetof(CPUARMState, daif), | |
3052 | .writefn = aa64_daif_write, .resetfn = arm_cp_reset_ignore }, | |
b0d2b7d0 PM |
3053 | { .name = "FPCR", .state = ARM_CP_STATE_AA64, |
3054 | .opc0 = 3, .opc1 = 3, .opc2 = 0, .crn = 4, .crm = 4, | |
3055 | .access = PL0_RW, .readfn = aa64_fpcr_read, .writefn = aa64_fpcr_write }, | |
3056 | { .name = "FPSR", .state = ARM_CP_STATE_AA64, | |
3057 | .opc0 = 3, .opc1 = 3, .opc2 = 1, .crn = 4, .crm = 4, | |
3058 | .access = PL0_RW, .readfn = aa64_fpsr_read, .writefn = aa64_fpsr_write }, | |
b0d2b7d0 PM |
3059 | { .name = "DCZID_EL0", .state = ARM_CP_STATE_AA64, |
3060 | .opc0 = 3, .opc1 = 3, .opc2 = 7, .crn = 0, .crm = 0, | |
7a0e58fa | 3061 | .access = PL0_R, .type = ARM_CP_NO_RAW, |
aca3f40b PM |
3062 | .readfn = aa64_dczid_read }, |
3063 | { .name = "DC_ZVA", .state = ARM_CP_STATE_AA64, | |
3064 | .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 4, .opc2 = 1, | |
3065 | .access = PL0_W, .type = ARM_CP_DC_ZVA, | |
3066 | #ifndef CONFIG_USER_ONLY | |
3067 | /* Avoid overhead of an access check that always passes in user-mode */ | |
3068 | .accessfn = aa64_zva_access, | |
3069 | #endif | |
3070 | }, | |
0eef9d98 PM |
3071 | { .name = "CURRENTEL", .state = ARM_CP_STATE_AA64, |
3072 | .opc0 = 3, .opc1 = 0, .opc2 = 2, .crn = 4, .crm = 2, | |
3073 | .access = PL1_R, .type = ARM_CP_CURRENTEL }, | |
8af35c37 PM |
3074 | /* Cache ops: all NOPs since we don't emulate caches */ |
3075 | { .name = "IC_IALLUIS", .state = ARM_CP_STATE_AA64, | |
3076 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 1, .opc2 = 0, | |
3077 | .access = PL1_W, .type = ARM_CP_NOP }, | |
3078 | { .name = "IC_IALLU", .state = ARM_CP_STATE_AA64, | |
3079 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 0, | |
3080 | .access = PL1_W, .type = ARM_CP_NOP }, | |
3081 | { .name = "IC_IVAU", .state = ARM_CP_STATE_AA64, | |
3082 | .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 5, .opc2 = 1, | |
3083 | .access = PL0_W, .type = ARM_CP_NOP, | |
3084 | .accessfn = aa64_cacheop_access }, | |
3085 | { .name = "DC_IVAC", .state = ARM_CP_STATE_AA64, | |
3086 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 1, | |
3087 | .access = PL1_W, .type = ARM_CP_NOP }, | |
3088 | { .name = "DC_ISW", .state = ARM_CP_STATE_AA64, | |
3089 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 2, | |
3090 | .access = PL1_W, .type = ARM_CP_NOP }, | |
3091 | { .name = "DC_CVAC", .state = ARM_CP_STATE_AA64, | |
3092 | .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 10, .opc2 = 1, | |
3093 | .access = PL0_W, .type = ARM_CP_NOP, | |
3094 | .accessfn = aa64_cacheop_access }, | |
3095 | { .name = "DC_CSW", .state = ARM_CP_STATE_AA64, | |
3096 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 2, | |
3097 | .access = PL1_W, .type = ARM_CP_NOP }, | |
3098 | { .name = "DC_CVAU", .state = ARM_CP_STATE_AA64, | |
3099 | .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 11, .opc2 = 1, | |
3100 | .access = PL0_W, .type = ARM_CP_NOP, | |
3101 | .accessfn = aa64_cacheop_access }, | |
3102 | { .name = "DC_CIVAC", .state = ARM_CP_STATE_AA64, | |
3103 | .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 14, .opc2 = 1, | |
3104 | .access = PL0_W, .type = ARM_CP_NOP, | |
3105 | .accessfn = aa64_cacheop_access }, | |
3106 | { .name = "DC_CISW", .state = ARM_CP_STATE_AA64, | |
3107 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 2, | |
3108 | .access = PL1_W, .type = ARM_CP_NOP }, | |
168aa23b PM |
3109 | /* TLBI operations */ |
3110 | { .name = "TLBI_VMALLE1IS", .state = ARM_CP_STATE_AA64, | |
6ab9f499 | 3111 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 0, |
7a0e58fa | 3112 | .access = PL1_W, .type = ARM_CP_NO_RAW, |
fd3ed969 | 3113 | .writefn = tlbi_aa64_vmalle1is_write }, |
168aa23b | 3114 | { .name = "TLBI_VAE1IS", .state = ARM_CP_STATE_AA64, |
6ab9f499 | 3115 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 1, |
7a0e58fa | 3116 | .access = PL1_W, .type = ARM_CP_NO_RAW, |
fd3ed969 | 3117 | .writefn = tlbi_aa64_vae1is_write }, |
168aa23b | 3118 | { .name = "TLBI_ASIDE1IS", .state = ARM_CP_STATE_AA64, |
6ab9f499 | 3119 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 2, |
7a0e58fa | 3120 | .access = PL1_W, .type = ARM_CP_NO_RAW, |
fd3ed969 | 3121 | .writefn = tlbi_aa64_vmalle1is_write }, |
168aa23b | 3122 | { .name = "TLBI_VAAE1IS", .state = ARM_CP_STATE_AA64, |
6ab9f499 | 3123 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 3, |
7a0e58fa | 3124 | .access = PL1_W, .type = ARM_CP_NO_RAW, |
fd3ed969 | 3125 | .writefn = tlbi_aa64_vae1is_write }, |
168aa23b | 3126 | { .name = "TLBI_VALE1IS", .state = ARM_CP_STATE_AA64, |
6ab9f499 | 3127 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 5, |
7a0e58fa | 3128 | .access = PL1_W, .type = ARM_CP_NO_RAW, |
fd3ed969 | 3129 | .writefn = tlbi_aa64_vae1is_write }, |
168aa23b | 3130 | { .name = "TLBI_VAALE1IS", .state = ARM_CP_STATE_AA64, |
6ab9f499 | 3131 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 7, |
7a0e58fa | 3132 | .access = PL1_W, .type = ARM_CP_NO_RAW, |
fd3ed969 | 3133 | .writefn = tlbi_aa64_vae1is_write }, |
168aa23b | 3134 | { .name = "TLBI_VMALLE1", .state = ARM_CP_STATE_AA64, |
6ab9f499 | 3135 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 0, |
7a0e58fa | 3136 | .access = PL1_W, .type = ARM_CP_NO_RAW, |
fd3ed969 | 3137 | .writefn = tlbi_aa64_vmalle1_write }, |
168aa23b | 3138 | { .name = "TLBI_VAE1", .state = ARM_CP_STATE_AA64, |
6ab9f499 | 3139 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 1, |
7a0e58fa | 3140 | .access = PL1_W, .type = ARM_CP_NO_RAW, |
fd3ed969 | 3141 | .writefn = tlbi_aa64_vae1_write }, |
168aa23b | 3142 | { .name = "TLBI_ASIDE1", .state = ARM_CP_STATE_AA64, |
6ab9f499 | 3143 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 2, |
7a0e58fa | 3144 | .access = PL1_W, .type = ARM_CP_NO_RAW, |
fd3ed969 | 3145 | .writefn = tlbi_aa64_vmalle1_write }, |
168aa23b | 3146 | { .name = "TLBI_VAAE1", .state = ARM_CP_STATE_AA64, |
6ab9f499 | 3147 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 3, |
7a0e58fa | 3148 | .access = PL1_W, .type = ARM_CP_NO_RAW, |
fd3ed969 | 3149 | .writefn = tlbi_aa64_vae1_write }, |
168aa23b | 3150 | { .name = "TLBI_VALE1", .state = ARM_CP_STATE_AA64, |
6ab9f499 | 3151 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 5, |
7a0e58fa | 3152 | .access = PL1_W, .type = ARM_CP_NO_RAW, |
fd3ed969 | 3153 | .writefn = tlbi_aa64_vae1_write }, |
168aa23b | 3154 | { .name = "TLBI_VAALE1", .state = ARM_CP_STATE_AA64, |
6ab9f499 | 3155 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 7, |
7a0e58fa | 3156 | .access = PL1_W, .type = ARM_CP_NO_RAW, |
fd3ed969 | 3157 | .writefn = tlbi_aa64_vae1_write }, |
cea66e91 PM |
3158 | { .name = "TLBI_IPAS2E1IS", .state = ARM_CP_STATE_AA64, |
3159 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 0, .opc2 = 1, | |
3160 | .access = PL2_W, .type = ARM_CP_NO_RAW, | |
3161 | .writefn = tlbi_aa64_ipas2e1is_write }, | |
3162 | { .name = "TLBI_IPAS2LE1IS", .state = ARM_CP_STATE_AA64, | |
3163 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 0, .opc2 = 5, | |
3164 | .access = PL2_W, .type = ARM_CP_NO_RAW, | |
3165 | .writefn = tlbi_aa64_ipas2e1is_write }, | |
83ddf975 PM |
3166 | { .name = "TLBI_ALLE1IS", .state = ARM_CP_STATE_AA64, |
3167 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 4, | |
3168 | .access = PL2_W, .type = ARM_CP_NO_RAW, | |
fd3ed969 | 3169 | .writefn = tlbi_aa64_alle1is_write }, |
43efaa33 PM |
3170 | { .name = "TLBI_VMALLS12E1IS", .state = ARM_CP_STATE_AA64, |
3171 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 6, | |
3172 | .access = PL2_W, .type = ARM_CP_NO_RAW, | |
3173 | .writefn = tlbi_aa64_alle1is_write }, | |
cea66e91 PM |
3174 | { .name = "TLBI_IPAS2E1", .state = ARM_CP_STATE_AA64, |
3175 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 1, | |
3176 | .access = PL2_W, .type = ARM_CP_NO_RAW, | |
3177 | .writefn = tlbi_aa64_ipas2e1_write }, | |
3178 | { .name = "TLBI_IPAS2LE1", .state = ARM_CP_STATE_AA64, | |
3179 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 5, | |
3180 | .access = PL2_W, .type = ARM_CP_NO_RAW, | |
3181 | .writefn = tlbi_aa64_ipas2e1_write }, | |
83ddf975 PM |
3182 | { .name = "TLBI_ALLE1", .state = ARM_CP_STATE_AA64, |
3183 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 4, | |
3184 | .access = PL2_W, .type = ARM_CP_NO_RAW, | |
fd3ed969 | 3185 | .writefn = tlbi_aa64_alle1_write }, |
43efaa33 PM |
3186 | { .name = "TLBI_VMALLS12E1", .state = ARM_CP_STATE_AA64, |
3187 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 6, | |
3188 | .access = PL2_W, .type = ARM_CP_NO_RAW, | |
3189 | .writefn = tlbi_aa64_alle1is_write }, | |
19525524 PM |
3190 | #ifndef CONFIG_USER_ONLY |
3191 | /* 64 bit address translation operations */ | |
3192 | { .name = "AT_S1E1R", .state = ARM_CP_STATE_AA64, | |
3193 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 0, | |
060e8a48 | 3194 | .access = PL1_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 }, |
19525524 PM |
3195 | { .name = "AT_S1E1W", .state = ARM_CP_STATE_AA64, |
3196 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 1, | |
060e8a48 | 3197 | .access = PL1_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 }, |
19525524 PM |
3198 | { .name = "AT_S1E0R", .state = ARM_CP_STATE_AA64, |
3199 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 2, | |
060e8a48 | 3200 | .access = PL1_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 }, |
19525524 PM |
3201 | { .name = "AT_S1E0W", .state = ARM_CP_STATE_AA64, |
3202 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 3, | |
060e8a48 | 3203 | .access = PL1_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 }, |
2a47df95 | 3204 | { .name = "AT_S12E1R", .state = ARM_CP_STATE_AA64, |
7a379c7e | 3205 | .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 4, |
2a47df95 PM |
3206 | .access = PL2_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 }, |
3207 | { .name = "AT_S12E1W", .state = ARM_CP_STATE_AA64, | |
7a379c7e | 3208 | .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 5, |
2a47df95 PM |
3209 | .access = PL2_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 }, |
3210 | { .name = "AT_S12E0R", .state = ARM_CP_STATE_AA64, | |
7a379c7e | 3211 | .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 6, |
2a47df95 PM |
3212 | .access = PL2_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 }, |
3213 | { .name = "AT_S12E0W", .state = ARM_CP_STATE_AA64, | |
7a379c7e | 3214 | .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 7, |
2a47df95 PM |
3215 | .access = PL2_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 }, |
3216 | /* AT S1E2* are elsewhere as they UNDEF from EL3 if EL2 is not present */ | |
3217 | { .name = "AT_S1E3R", .state = ARM_CP_STATE_AA64, | |
3218 | .opc0 = 1, .opc1 = 6, .crn = 7, .crm = 8, .opc2 = 0, | |
3219 | .access = PL3_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 }, | |
3220 | { .name = "AT_S1E3W", .state = ARM_CP_STATE_AA64, | |
3221 | .opc0 = 1, .opc1 = 6, .crn = 7, .crm = 8, .opc2 = 1, | |
3222 | .access = PL3_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 }, | |
c96fc9b5 EI |
3223 | { .name = "PAR_EL1", .state = ARM_CP_STATE_AA64, |
3224 | .type = ARM_CP_ALIAS, | |
3225 | .opc0 = 3, .opc1 = 0, .crn = 7, .crm = 4, .opc2 = 0, | |
3226 | .access = PL1_RW, .resetvalue = 0, | |
3227 | .fieldoffset = offsetof(CPUARMState, cp15.par_el[1]), | |
3228 | .writefn = par_write }, | |
19525524 | 3229 | #endif |
995939a6 | 3230 | /* TLB invalidate last level of translation table walk */ |
9449fdf6 | 3231 | { .name = "TLBIMVALIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 5, |
7a0e58fa | 3232 | .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimva_is_write }, |
9449fdf6 | 3233 | { .name = "TLBIMVAALIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 7, |
7a0e58fa | 3234 | .type = ARM_CP_NO_RAW, .access = PL1_W, |
fa439fc5 | 3235 | .writefn = tlbimvaa_is_write }, |
9449fdf6 | 3236 | { .name = "TLBIMVAL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 5, |
7a0e58fa | 3237 | .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimva_write }, |
9449fdf6 | 3238 | { .name = "TLBIMVAAL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 7, |
7a0e58fa | 3239 | .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimvaa_write }, |
9449fdf6 PM |
3240 | /* 32 bit cache operations */ |
3241 | { .name = "ICIALLUIS", .cp = 15, .opc1 = 0, .crn = 7, .crm = 1, .opc2 = 0, | |
3242 | .type = ARM_CP_NOP, .access = PL1_W }, | |
3243 | { .name = "BPIALLUIS", .cp = 15, .opc1 = 0, .crn = 7, .crm = 1, .opc2 = 6, | |
3244 | .type = ARM_CP_NOP, .access = PL1_W }, | |
3245 | { .name = "ICIALLU", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 0, | |
3246 | .type = ARM_CP_NOP, .access = PL1_W }, | |
3247 | { .name = "ICIMVAU", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 1, | |
3248 | .type = ARM_CP_NOP, .access = PL1_W }, | |
3249 | { .name = "BPIALL", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 6, | |
3250 | .type = ARM_CP_NOP, .access = PL1_W }, | |
3251 | { .name = "BPIMVA", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 7, | |
3252 | .type = ARM_CP_NOP, .access = PL1_W }, | |
3253 | { .name = "DCIMVAC", .cp = 15, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 1, | |
3254 | .type = ARM_CP_NOP, .access = PL1_W }, | |
3255 | { .name = "DCISW", .cp = 15, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 2, | |
3256 | .type = ARM_CP_NOP, .access = PL1_W }, | |
3257 | { .name = "DCCMVAC", .cp = 15, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 1, | |
3258 | .type = ARM_CP_NOP, .access = PL1_W }, | |
3259 | { .name = "DCCSW", .cp = 15, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 2, | |
3260 | .type = ARM_CP_NOP, .access = PL1_W }, | |
3261 | { .name = "DCCMVAU", .cp = 15, .opc1 = 0, .crn = 7, .crm = 11, .opc2 = 1, | |
3262 | .type = ARM_CP_NOP, .access = PL1_W }, | |
3263 | { .name = "DCCIMVAC", .cp = 15, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 1, | |
3264 | .type = ARM_CP_NOP, .access = PL1_W }, | |
3265 | { .name = "DCCISW", .cp = 15, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 2, | |
3266 | .type = ARM_CP_NOP, .access = PL1_W }, | |
3267 | /* MMU Domain access control / MPU write buffer control */ | |
0c17d68c FA |
3268 | { .name = "DACR", .cp = 15, .opc1 = 0, .crn = 3, .crm = 0, .opc2 = 0, |
3269 | .access = PL1_RW, .resetvalue = 0, | |
3270 | .writefn = dacr_write, .raw_writefn = raw_write, | |
3271 | .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.dacr_s), | |
3272 | offsetoflow32(CPUARMState, cp15.dacr_ns) } }, | |
a0618a19 | 3273 | { .name = "ELR_EL1", .state = ARM_CP_STATE_AA64, |
7a0e58fa | 3274 | .type = ARM_CP_ALIAS, |
a0618a19 | 3275 | .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 0, .opc2 = 1, |
6947f059 EI |
3276 | .access = PL1_RW, |
3277 | .fieldoffset = offsetof(CPUARMState, elr_el[1]) }, | |
a65f1de9 | 3278 | { .name = "SPSR_EL1", .state = ARM_CP_STATE_AA64, |
7a0e58fa | 3279 | .type = ARM_CP_ALIAS, |
a65f1de9 | 3280 | .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 0, .opc2 = 0, |
99a99c1f SB |
3281 | .access = PL1_RW, |
3282 | .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_SVC]) }, | |
f502cfc2 PM |
3283 | /* We rely on the access checks not allowing the guest to write to the |
3284 | * state field when SPSel indicates that it's being used as the stack | |
3285 | * pointer. | |
3286 | */ | |
3287 | { .name = "SP_EL0", .state = ARM_CP_STATE_AA64, | |
3288 | .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 1, .opc2 = 0, | |
3289 | .access = PL1_RW, .accessfn = sp_el0_access, | |
7a0e58fa | 3290 | .type = ARM_CP_ALIAS, |
f502cfc2 | 3291 | .fieldoffset = offsetof(CPUARMState, sp_el[0]) }, |
884b4dee GB |
3292 | { .name = "SP_EL1", .state = ARM_CP_STATE_AA64, |
3293 | .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 1, .opc2 = 0, | |
7a0e58fa | 3294 | .access = PL2_RW, .type = ARM_CP_ALIAS, |
884b4dee | 3295 | .fieldoffset = offsetof(CPUARMState, sp_el[1]) }, |
f502cfc2 PM |
3296 | { .name = "SPSel", .state = ARM_CP_STATE_AA64, |
3297 | .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 2, .opc2 = 0, | |
7a0e58fa | 3298 | .type = ARM_CP_NO_RAW, |
f502cfc2 | 3299 | .access = PL1_RW, .readfn = spsel_read, .writefn = spsel_write }, |
03fbf20f PM |
3300 | { .name = "FPEXC32_EL2", .state = ARM_CP_STATE_AA64, |
3301 | .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 3, .opc2 = 0, | |
3302 | .type = ARM_CP_ALIAS, | |
3303 | .fieldoffset = offsetof(CPUARMState, vfp.xregs[ARM_VFP_FPEXC]), | |
3304 | .access = PL2_RW, .accessfn = fpexc32_access }, | |
6a43e0b6 PM |
3305 | { .name = "DACR32_EL2", .state = ARM_CP_STATE_AA64, |
3306 | .opc0 = 3, .opc1 = 4, .crn = 3, .crm = 0, .opc2 = 0, | |
3307 | .access = PL2_RW, .resetvalue = 0, | |
3308 | .writefn = dacr_write, .raw_writefn = raw_write, | |
3309 | .fieldoffset = offsetof(CPUARMState, cp15.dacr32_el2) }, | |
3310 | { .name = "IFSR32_EL2", .state = ARM_CP_STATE_AA64, | |
3311 | .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 0, .opc2 = 1, | |
3312 | .access = PL2_RW, .resetvalue = 0, | |
3313 | .fieldoffset = offsetof(CPUARMState, cp15.ifsr32_el2) }, | |
3314 | { .name = "SPSR_IRQ", .state = ARM_CP_STATE_AA64, | |
3315 | .type = ARM_CP_ALIAS, | |
3316 | .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 3, .opc2 = 0, | |
3317 | .access = PL2_RW, | |
3318 | .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_IRQ]) }, | |
3319 | { .name = "SPSR_ABT", .state = ARM_CP_STATE_AA64, | |
3320 | .type = ARM_CP_ALIAS, | |
3321 | .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 3, .opc2 = 1, | |
3322 | .access = PL2_RW, | |
3323 | .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_ABT]) }, | |
3324 | { .name = "SPSR_UND", .state = ARM_CP_STATE_AA64, | |
3325 | .type = ARM_CP_ALIAS, | |
3326 | .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 3, .opc2 = 2, | |
3327 | .access = PL2_RW, | |
3328 | .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_UND]) }, | |
3329 | { .name = "SPSR_FIQ", .state = ARM_CP_STATE_AA64, | |
3330 | .type = ARM_CP_ALIAS, | |
3331 | .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 3, .opc2 = 3, | |
3332 | .access = PL2_RW, | |
3333 | .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_FIQ]) }, | |
b0d2b7d0 PM |
3334 | REGINFO_SENTINEL |
3335 | }; | |
3336 | ||
d42e3c26 | 3337 | /* Used to describe the behaviour of EL2 regs when EL2 does not exist. */ |
4771cd01 | 3338 | static const ARMCPRegInfo el3_no_el2_cp_reginfo[] = { |
d42e3c26 EI |
3339 | { .name = "VBAR_EL2", .state = ARM_CP_STATE_AA64, |
3340 | .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 0, .opc2 = 0, | |
3341 | .access = PL2_RW, | |
3342 | .readfn = arm_cp_read_zero, .writefn = arm_cp_write_ignore }, | |
f149e3e8 | 3343 | { .name = "HCR_EL2", .state = ARM_CP_STATE_AA64, |
7a0e58fa | 3344 | .type = ARM_CP_NO_RAW, |
f149e3e8 EI |
3345 | .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 0, |
3346 | .access = PL2_RW, | |
3347 | .readfn = arm_cp_read_zero, .writefn = arm_cp_write_ignore }, | |
c6f19164 GB |
3348 | { .name = "CPTR_EL2", .state = ARM_CP_STATE_BOTH, |
3349 | .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 2, | |
3350 | .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
95f949ac EI |
3351 | { .name = "MAIR_EL2", .state = ARM_CP_STATE_BOTH, |
3352 | .opc0 = 3, .opc1 = 4, .crn = 10, .crm = 2, .opc2 = 0, | |
3353 | .access = PL2_RW, .type = ARM_CP_CONST, | |
3354 | .resetvalue = 0 }, | |
3355 | { .name = "HMAIR1", .state = ARM_CP_STATE_AA32, | |
3356 | .opc1 = 4, .crn = 10, .crm = 2, .opc2 = 1, | |
3357 | .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
2179ef95 PM |
3358 | { .name = "AMAIR_EL2", .state = ARM_CP_STATE_BOTH, |
3359 | .opc0 = 3, .opc1 = 4, .crn = 10, .crm = 3, .opc2 = 0, | |
3360 | .access = PL2_RW, .type = ARM_CP_CONST, | |
3361 | .resetvalue = 0 }, | |
3362 | { .name = "HMAIR1", .state = ARM_CP_STATE_AA32, | |
3363 | .opc1 = 4, .crn = 10, .crm = 3, .opc2 = 1, | |
3364 | .access = PL2_RW, .type = ARM_CP_CONST, | |
3365 | .resetvalue = 0 }, | |
37cd6c24 PM |
3366 | { .name = "AFSR0_EL2", .state = ARM_CP_STATE_BOTH, |
3367 | .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 1, .opc2 = 0, | |
3368 | .access = PL2_RW, .type = ARM_CP_CONST, | |
3369 | .resetvalue = 0 }, | |
3370 | { .name = "AFSR1_EL2", .state = ARM_CP_STATE_BOTH, | |
3371 | .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 1, .opc2 = 1, | |
3372 | .access = PL2_RW, .type = ARM_CP_CONST, | |
3373 | .resetvalue = 0 }, | |
06ec4c8c EI |
3374 | { .name = "TCR_EL2", .state = ARM_CP_STATE_BOTH, |
3375 | .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 2, | |
3376 | .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
68e9c2fe EI |
3377 | { .name = "VTCR_EL2", .state = ARM_CP_STATE_BOTH, |
3378 | .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 2, | |
3379 | .access = PL2_RW, .accessfn = access_el3_aa32ns_aa64any, | |
3380 | .type = ARM_CP_CONST, .resetvalue = 0 }, | |
b698e9cf EI |
3381 | { .name = "VTTBR", .state = ARM_CP_STATE_AA32, |
3382 | .cp = 15, .opc1 = 6, .crm = 2, | |
3383 | .access = PL2_RW, .accessfn = access_el3_aa32ns, | |
3384 | .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 }, | |
3385 | { .name = "VTTBR_EL2", .state = ARM_CP_STATE_AA64, | |
3386 | .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 0, | |
3387 | .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
b9cb5323 EI |
3388 | { .name = "SCTLR_EL2", .state = ARM_CP_STATE_BOTH, |
3389 | .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 0, .opc2 = 0, | |
3390 | .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
ff05f37b EI |
3391 | { .name = "TPIDR_EL2", .state = ARM_CP_STATE_BOTH, |
3392 | .opc0 = 3, .opc1 = 4, .crn = 13, .crm = 0, .opc2 = 2, | |
3393 | .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
a57633c0 EI |
3394 | { .name = "TTBR0_EL2", .state = ARM_CP_STATE_AA64, |
3395 | .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 0, | |
3396 | .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
3397 | { .name = "HTTBR", .cp = 15, .opc1 = 4, .crm = 2, | |
3398 | .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_CONST, | |
3399 | .resetvalue = 0 }, | |
0b6440af EI |
3400 | { .name = "CNTHCTL_EL2", .state = ARM_CP_STATE_BOTH, |
3401 | .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 1, .opc2 = 0, | |
3402 | .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
edac4d8a EI |
3403 | { .name = "CNTVOFF_EL2", .state = ARM_CP_STATE_AA64, |
3404 | .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 0, .opc2 = 3, | |
3405 | .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
3406 | { .name = "CNTVOFF", .cp = 15, .opc1 = 4, .crm = 14, | |
3407 | .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_CONST, | |
3408 | .resetvalue = 0 }, | |
b0e66d95 EI |
3409 | { .name = "CNTHP_CVAL_EL2", .state = ARM_CP_STATE_AA64, |
3410 | .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 2, | |
3411 | .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
3412 | { .name = "CNTHP_CVAL", .cp = 15, .opc1 = 6, .crm = 14, | |
3413 | .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_CONST, | |
3414 | .resetvalue = 0 }, | |
3415 | { .name = "CNTHP_TVAL_EL2", .state = ARM_CP_STATE_BOTH, | |
3416 | .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 0, | |
3417 | .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
3418 | { .name = "CNTHP_CTL_EL2", .state = ARM_CP_STATE_BOTH, | |
3419 | .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 1, | |
3420 | .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
14cc7b54 SF |
3421 | { .name = "MDCR_EL2", .state = ARM_CP_STATE_BOTH, |
3422 | .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 1, | |
d6c8cf81 PM |
3423 | .access = PL2_RW, .accessfn = access_tda, |
3424 | .type = ARM_CP_CONST, .resetvalue = 0 }, | |
59e05530 EI |
3425 | { .name = "HPFAR_EL2", .state = ARM_CP_STATE_BOTH, |
3426 | .opc0 = 3, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 4, | |
3427 | .access = PL2_RW, .accessfn = access_el3_aa32ns_aa64any, | |
3428 | .type = ARM_CP_CONST, .resetvalue = 0 }, | |
d42e3c26 EI |
3429 | REGINFO_SENTINEL |
3430 | }; | |
3431 | ||
f149e3e8 EI |
3432 | static void hcr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) |
3433 | { | |
3434 | ARMCPU *cpu = arm_env_get_cpu(env); | |
3435 | uint64_t valid_mask = HCR_MASK; | |
3436 | ||
3437 | if (arm_feature(env, ARM_FEATURE_EL3)) { | |
3438 | valid_mask &= ~HCR_HCD; | |
3439 | } else { | |
3440 | valid_mask &= ~HCR_TSC; | |
3441 | } | |
3442 | ||
3443 | /* Clear RES0 bits. */ | |
3444 | value &= valid_mask; | |
3445 | ||
3446 | /* These bits change the MMU setup: | |
3447 | * HCR_VM enables stage 2 translation | |
3448 | * HCR_PTW forbids certain page-table setups | |
3449 | * HCR_DC Disables stage1 and enables stage2 translation | |
3450 | */ | |
3451 | if ((raw_read(env, ri) ^ value) & (HCR_VM | HCR_PTW | HCR_DC)) { | |
3452 | tlb_flush(CPU(cpu), 1); | |
3453 | } | |
3454 | raw_write(env, ri, value); | |
3455 | } | |
3456 | ||
4771cd01 | 3457 | static const ARMCPRegInfo el2_cp_reginfo[] = { |
f149e3e8 EI |
3458 | { .name = "HCR_EL2", .state = ARM_CP_STATE_AA64, |
3459 | .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 0, | |
3460 | .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.hcr_el2), | |
3461 | .writefn = hcr_write }, | |
3b685ba7 | 3462 | { .name = "ELR_EL2", .state = ARM_CP_STATE_AA64, |
7a0e58fa | 3463 | .type = ARM_CP_ALIAS, |
3b685ba7 EI |
3464 | .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 0, .opc2 = 1, |
3465 | .access = PL2_RW, | |
3466 | .fieldoffset = offsetof(CPUARMState, elr_el[2]) }, | |
f2c30f42 | 3467 | { .name = "ESR_EL2", .state = ARM_CP_STATE_AA64, |
7a0e58fa | 3468 | .type = ARM_CP_ALIAS, |
f2c30f42 EI |
3469 | .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 2, .opc2 = 0, |
3470 | .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.esr_el[2]) }, | |
63b60551 EI |
3471 | { .name = "FAR_EL2", .state = ARM_CP_STATE_AA64, |
3472 | .opc0 = 3, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 0, | |
3473 | .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.far_el[2]) }, | |
3b685ba7 | 3474 | { .name = "SPSR_EL2", .state = ARM_CP_STATE_AA64, |
7a0e58fa | 3475 | .type = ARM_CP_ALIAS, |
3b685ba7 | 3476 | .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 0, .opc2 = 0, |
99a99c1f SB |
3477 | .access = PL2_RW, |
3478 | .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_HYP]) }, | |
d42e3c26 EI |
3479 | { .name = "VBAR_EL2", .state = ARM_CP_STATE_AA64, |
3480 | .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 0, .opc2 = 0, | |
3481 | .access = PL2_RW, .writefn = vbar_write, | |
3482 | .fieldoffset = offsetof(CPUARMState, cp15.vbar_el[2]), | |
3483 | .resetvalue = 0 }, | |
884b4dee GB |
3484 | { .name = "SP_EL2", .state = ARM_CP_STATE_AA64, |
3485 | .opc0 = 3, .opc1 = 6, .crn = 4, .crm = 1, .opc2 = 0, | |
7a0e58fa | 3486 | .access = PL3_RW, .type = ARM_CP_ALIAS, |
884b4dee | 3487 | .fieldoffset = offsetof(CPUARMState, sp_el[2]) }, |
c6f19164 GB |
3488 | { .name = "CPTR_EL2", .state = ARM_CP_STATE_BOTH, |
3489 | .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 2, | |
3490 | .access = PL2_RW, .accessfn = cptr_access, .resetvalue = 0, | |
3491 | .fieldoffset = offsetof(CPUARMState, cp15.cptr_el[2]) }, | |
95f949ac EI |
3492 | { .name = "MAIR_EL2", .state = ARM_CP_STATE_BOTH, |
3493 | .opc0 = 3, .opc1 = 4, .crn = 10, .crm = 2, .opc2 = 0, | |
3494 | .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.mair_el[2]), | |
3495 | .resetvalue = 0 }, | |
3496 | { .name = "HMAIR1", .state = ARM_CP_STATE_AA32, | |
3497 | .opc1 = 4, .crn = 10, .crm = 2, .opc2 = 1, | |
3498 | .access = PL2_RW, .type = ARM_CP_ALIAS, | |
3499 | .fieldoffset = offsetofhigh32(CPUARMState, cp15.mair_el[2]) }, | |
2179ef95 PM |
3500 | { .name = "AMAIR_EL2", .state = ARM_CP_STATE_BOTH, |
3501 | .opc0 = 3, .opc1 = 4, .crn = 10, .crm = 3, .opc2 = 0, | |
3502 | .access = PL2_RW, .type = ARM_CP_CONST, | |
3503 | .resetvalue = 0 }, | |
3504 | /* HAMAIR1 is mapped to AMAIR_EL2[63:32] */ | |
3505 | { .name = "HMAIR1", .state = ARM_CP_STATE_AA32, | |
3506 | .opc1 = 4, .crn = 10, .crm = 3, .opc2 = 1, | |
3507 | .access = PL2_RW, .type = ARM_CP_CONST, | |
3508 | .resetvalue = 0 }, | |
37cd6c24 PM |
3509 | { .name = "AFSR0_EL2", .state = ARM_CP_STATE_BOTH, |
3510 | .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 1, .opc2 = 0, | |
3511 | .access = PL2_RW, .type = ARM_CP_CONST, | |
3512 | .resetvalue = 0 }, | |
3513 | { .name = "AFSR1_EL2", .state = ARM_CP_STATE_BOTH, | |
3514 | .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 1, .opc2 = 1, | |
3515 | .access = PL2_RW, .type = ARM_CP_CONST, | |
3516 | .resetvalue = 0 }, | |
06ec4c8c EI |
3517 | { .name = "TCR_EL2", .state = ARM_CP_STATE_BOTH, |
3518 | .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 2, | |
3519 | .access = PL2_RW, .writefn = vmsa_tcr_el1_write, | |
3520 | .resetfn = vmsa_ttbcr_reset, .raw_writefn = raw_write, | |
3521 | .fieldoffset = offsetof(CPUARMState, cp15.tcr_el[2]) }, | |
68e9c2fe EI |
3522 | { .name = "VTCR", .state = ARM_CP_STATE_AA32, |
3523 | .cp = 15, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 2, | |
3524 | .access = PL2_RW, .accessfn = access_el3_aa32ns, | |
3525 | .fieldoffset = offsetof(CPUARMState, cp15.vtcr_el2) }, | |
3526 | { .name = "VTCR_EL2", .state = ARM_CP_STATE_AA64, | |
3527 | .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 2, | |
3528 | .access = PL2_RW, .type = ARM_CP_ALIAS, | |
3529 | .fieldoffset = offsetof(CPUARMState, cp15.vtcr_el2) }, | |
b698e9cf EI |
3530 | { .name = "VTTBR", .state = ARM_CP_STATE_AA32, |
3531 | .cp = 15, .opc1 = 6, .crm = 2, | |
3532 | .type = ARM_CP_64BIT | ARM_CP_ALIAS, | |
3533 | .access = PL2_RW, .accessfn = access_el3_aa32ns, | |
3534 | .fieldoffset = offsetof(CPUARMState, cp15.vttbr_el2), | |
3535 | .writefn = vttbr_write }, | |
3536 | { .name = "VTTBR_EL2", .state = ARM_CP_STATE_AA64, | |
3537 | .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 0, | |
3538 | .access = PL2_RW, .writefn = vttbr_write, | |
3539 | .fieldoffset = offsetof(CPUARMState, cp15.vttbr_el2) }, | |
b9cb5323 EI |
3540 | { .name = "SCTLR_EL2", .state = ARM_CP_STATE_BOTH, |
3541 | .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 0, .opc2 = 0, | |
3542 | .access = PL2_RW, .raw_writefn = raw_write, .writefn = sctlr_write, | |
3543 | .fieldoffset = offsetof(CPUARMState, cp15.sctlr_el[2]) }, | |
ff05f37b EI |
3544 | { .name = "TPIDR_EL2", .state = ARM_CP_STATE_BOTH, |
3545 | .opc0 = 3, .opc1 = 4, .crn = 13, .crm = 0, .opc2 = 2, | |
3546 | .access = PL2_RW, .resetvalue = 0, | |
3547 | .fieldoffset = offsetof(CPUARMState, cp15.tpidr_el[2]) }, | |
a57633c0 EI |
3548 | { .name = "TTBR0_EL2", .state = ARM_CP_STATE_AA64, |
3549 | .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 0, | |
3550 | .access = PL2_RW, .resetvalue = 0, | |
3551 | .fieldoffset = offsetof(CPUARMState, cp15.ttbr0_el[2]) }, | |
3552 | { .name = "HTTBR", .cp = 15, .opc1 = 4, .crm = 2, | |
3553 | .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_ALIAS, | |
a57633c0 | 3554 | .fieldoffset = offsetof(CPUARMState, cp15.ttbr0_el[2]) }, |
51da9014 EI |
3555 | { .name = "TLBI_ALLE2", .state = ARM_CP_STATE_AA64, |
3556 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 0, | |
3557 | .type = ARM_CP_NO_RAW, .access = PL2_W, | |
fd3ed969 | 3558 | .writefn = tlbi_aa64_alle2_write }, |
8742d49d EI |
3559 | { .name = "TLBI_VAE2", .state = ARM_CP_STATE_AA64, |
3560 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 1, | |
3561 | .type = ARM_CP_NO_RAW, .access = PL2_W, | |
fd3ed969 | 3562 | .writefn = tlbi_aa64_vae2_write }, |
2bfb9d75 PM |
3563 | { .name = "TLBI_VALE2", .state = ARM_CP_STATE_AA64, |
3564 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 5, | |
3565 | .access = PL2_W, .type = ARM_CP_NO_RAW, | |
3566 | .writefn = tlbi_aa64_vae2_write }, | |
3567 | { .name = "TLBI_ALLE2IS", .state = ARM_CP_STATE_AA64, | |
3568 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 0, | |
3569 | .access = PL2_W, .type = ARM_CP_NO_RAW, | |
3570 | .writefn = tlbi_aa64_alle2is_write }, | |
8742d49d EI |
3571 | { .name = "TLBI_VAE2IS", .state = ARM_CP_STATE_AA64, |
3572 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 1, | |
3573 | .type = ARM_CP_NO_RAW, .access = PL2_W, | |
fd3ed969 | 3574 | .writefn = tlbi_aa64_vae2is_write }, |
2bfb9d75 PM |
3575 | { .name = "TLBI_VALE2IS", .state = ARM_CP_STATE_AA64, |
3576 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 5, | |
3577 | .access = PL2_W, .type = ARM_CP_NO_RAW, | |
3578 | .writefn = tlbi_aa64_vae2is_write }, | |
edac4d8a | 3579 | #ifndef CONFIG_USER_ONLY |
2a47df95 PM |
3580 | /* Unlike the other EL2-related AT operations, these must |
3581 | * UNDEF from EL3 if EL2 is not implemented, which is why we | |
3582 | * define them here rather than with the rest of the AT ops. | |
3583 | */ | |
3584 | { .name = "AT_S1E2R", .state = ARM_CP_STATE_AA64, | |
3585 | .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 0, | |
3586 | .access = PL2_W, .accessfn = at_s1e2_access, | |
3587 | .type = ARM_CP_NO_RAW, .writefn = ats_write64 }, | |
3588 | { .name = "AT_S1E2W", .state = ARM_CP_STATE_AA64, | |
3589 | .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 1, | |
3590 | .access = PL2_W, .accessfn = at_s1e2_access, | |
3591 | .type = ARM_CP_NO_RAW, .writefn = ats_write64 }, | |
14db7fe0 PM |
3592 | /* The AArch32 ATS1H* operations are CONSTRAINED UNPREDICTABLE |
3593 | * if EL2 is not implemented; we choose to UNDEF. Behaviour at EL3 | |
3594 | * with SCR.NS == 0 outside Monitor mode is UNPREDICTABLE; we choose | |
3595 | * to behave as if SCR.NS was 1. | |
3596 | */ | |
3597 | { .name = "ATS1HR", .cp = 15, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 0, | |
3598 | .access = PL2_W, | |
3599 | .writefn = ats1h_write, .type = ARM_CP_NO_RAW }, | |
3600 | { .name = "ATS1HW", .cp = 15, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 1, | |
3601 | .access = PL2_W, | |
3602 | .writefn = ats1h_write, .type = ARM_CP_NO_RAW }, | |
0b6440af EI |
3603 | { .name = "CNTHCTL_EL2", .state = ARM_CP_STATE_BOTH, |
3604 | .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 1, .opc2 = 0, | |
3605 | /* ARMv7 requires bit 0 and 1 to reset to 1. ARMv8 defines the | |
3606 | * reset values as IMPDEF. We choose to reset to 3 to comply with | |
3607 | * both ARMv7 and ARMv8. | |
3608 | */ | |
3609 | .access = PL2_RW, .resetvalue = 3, | |
3610 | .fieldoffset = offsetof(CPUARMState, cp15.cnthctl_el2) }, | |
edac4d8a EI |
3611 | { .name = "CNTVOFF_EL2", .state = ARM_CP_STATE_AA64, |
3612 | .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 0, .opc2 = 3, | |
3613 | .access = PL2_RW, .type = ARM_CP_IO, .resetvalue = 0, | |
3614 | .writefn = gt_cntvoff_write, | |
3615 | .fieldoffset = offsetof(CPUARMState, cp15.cntvoff_el2) }, | |
3616 | { .name = "CNTVOFF", .cp = 15, .opc1 = 4, .crm = 14, | |
3617 | .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_ALIAS | ARM_CP_IO, | |
3618 | .writefn = gt_cntvoff_write, | |
3619 | .fieldoffset = offsetof(CPUARMState, cp15.cntvoff_el2) }, | |
b0e66d95 EI |
3620 | { .name = "CNTHP_CVAL_EL2", .state = ARM_CP_STATE_AA64, |
3621 | .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 2, | |
3622 | .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_HYP].cval), | |
3623 | .type = ARM_CP_IO, .access = PL2_RW, | |
3624 | .writefn = gt_hyp_cval_write, .raw_writefn = raw_write }, | |
3625 | { .name = "CNTHP_CVAL", .cp = 15, .opc1 = 6, .crm = 14, | |
3626 | .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_HYP].cval), | |
3627 | .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_IO, | |
3628 | .writefn = gt_hyp_cval_write, .raw_writefn = raw_write }, | |
3629 | { .name = "CNTHP_TVAL_EL2", .state = ARM_CP_STATE_BOTH, | |
3630 | .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 0, | |
3631 | .type = ARM_CP_IO, .access = PL2_RW, | |
3632 | .resetfn = gt_hyp_timer_reset, | |
3633 | .readfn = gt_hyp_tval_read, .writefn = gt_hyp_tval_write }, | |
3634 | { .name = "CNTHP_CTL_EL2", .state = ARM_CP_STATE_BOTH, | |
3635 | .type = ARM_CP_IO, | |
3636 | .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 1, | |
3637 | .access = PL2_RW, | |
3638 | .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_HYP].ctl), | |
3639 | .resetvalue = 0, | |
3640 | .writefn = gt_hyp_ctl_write, .raw_writefn = raw_write }, | |
edac4d8a | 3641 | #endif |
14cc7b54 SF |
3642 | /* The only field of MDCR_EL2 that has a defined architectural reset value |
3643 | * is MDCR_EL2.HPMN which should reset to the value of PMCR_EL0.N; but we | |
3644 | * don't impelment any PMU event counters, so using zero as a reset | |
3645 | * value for MDCR_EL2 is okay | |
3646 | */ | |
3647 | { .name = "MDCR_EL2", .state = ARM_CP_STATE_BOTH, | |
3648 | .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 1, | |
3649 | .access = PL2_RW, .resetvalue = 0, | |
3650 | .fieldoffset = offsetof(CPUARMState, cp15.mdcr_el2), }, | |
59e05530 EI |
3651 | { .name = "HPFAR", .state = ARM_CP_STATE_AA32, |
3652 | .cp = 15, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 4, | |
3653 | .access = PL2_RW, .accessfn = access_el3_aa32ns, | |
3654 | .fieldoffset = offsetof(CPUARMState, cp15.hpfar_el2) }, | |
3655 | { .name = "HPFAR_EL2", .state = ARM_CP_STATE_AA64, | |
3656 | .opc0 = 3, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 4, | |
3657 | .access = PL2_RW, | |
3658 | .fieldoffset = offsetof(CPUARMState, cp15.hpfar_el2) }, | |
3b685ba7 EI |
3659 | REGINFO_SENTINEL |
3660 | }; | |
3661 | ||
2f027fc5 PM |
3662 | static CPAccessResult nsacr_access(CPUARMState *env, const ARMCPRegInfo *ri, |
3663 | bool isread) | |
3664 | { | |
3665 | /* The NSACR is RW at EL3, and RO for NS EL1 and NS EL2. | |
3666 | * At Secure EL1 it traps to EL3. | |
3667 | */ | |
3668 | if (arm_current_el(env) == 3) { | |
3669 | return CP_ACCESS_OK; | |
3670 | } | |
3671 | if (arm_is_secure_below_el3(env)) { | |
3672 | return CP_ACCESS_TRAP_EL3; | |
3673 | } | |
3674 | /* Accesses from EL1 NS and EL2 NS are UNDEF for write but allow reads. */ | |
3675 | if (isread) { | |
3676 | return CP_ACCESS_OK; | |
3677 | } | |
3678 | return CP_ACCESS_TRAP_UNCATEGORIZED; | |
3679 | } | |
3680 | ||
60fb1a87 GB |
3681 | static const ARMCPRegInfo el3_cp_reginfo[] = { |
3682 | { .name = "SCR_EL3", .state = ARM_CP_STATE_AA64, | |
3683 | .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 1, .opc2 = 0, | |
3684 | .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.scr_el3), | |
3685 | .resetvalue = 0, .writefn = scr_write }, | |
7a0e58fa | 3686 | { .name = "SCR", .type = ARM_CP_ALIAS, |
60fb1a87 | 3687 | .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 0, |
efe4a274 PM |
3688 | .access = PL1_RW, .accessfn = access_trap_aa32s_el1, |
3689 | .fieldoffset = offsetoflow32(CPUARMState, cp15.scr_el3), | |
b061a82b | 3690 | .writefn = scr_write }, |
5513c3ab PM |
3691 | { .name = "MDCR_EL3", .state = ARM_CP_STATE_AA64, |
3692 | .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 3, .opc2 = 1, | |
3693 | .resetvalue = 0, | |
3694 | .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.mdcr_el3) }, | |
3695 | { .name = "SDCR", .type = ARM_CP_ALIAS, | |
3696 | .cp = 15, .opc1 = 0, .crn = 1, .crm = 3, .opc2 = 1, | |
3697 | .access = PL1_RW, .accessfn = access_trap_aa32s_el1, | |
3698 | .fieldoffset = offsetoflow32(CPUARMState, cp15.mdcr_el3) }, | |
60fb1a87 GB |
3699 | { .name = "SDER32_EL3", .state = ARM_CP_STATE_AA64, |
3700 | .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 1, .opc2 = 1, | |
3701 | .access = PL3_RW, .resetvalue = 0, | |
3702 | .fieldoffset = offsetof(CPUARMState, cp15.sder) }, | |
3703 | { .name = "SDER", | |
3704 | .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 1, | |
3705 | .access = PL3_RW, .resetvalue = 0, | |
3706 | .fieldoffset = offsetoflow32(CPUARMState, cp15.sder) }, | |
60fb1a87 | 3707 | { .name = "MVBAR", .cp = 15, .opc1 = 0, .crn = 12, .crm = 0, .opc2 = 1, |
efe4a274 PM |
3708 | .access = PL1_RW, .accessfn = access_trap_aa32s_el1, |
3709 | .writefn = vbar_write, .resetvalue = 0, | |
60fb1a87 | 3710 | .fieldoffset = offsetof(CPUARMState, cp15.mvbar) }, |
137feaa9 | 3711 | { .name = "SCTLR_EL3", .state = ARM_CP_STATE_AA64, |
e46e1a74 | 3712 | .type = ARM_CP_ALIAS, /* reset handled by AArch32 view */ |
137feaa9 FA |
3713 | .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 0, .opc2 = 0, |
3714 | .access = PL3_RW, .raw_writefn = raw_write, .writefn = sctlr_write, | |
3715 | .fieldoffset = offsetof(CPUARMState, cp15.sctlr_el[3]) }, | |
7dd8c9af FA |
3716 | { .name = "TTBR0_EL3", .state = ARM_CP_STATE_AA64, |
3717 | .opc0 = 3, .opc1 = 6, .crn = 2, .crm = 0, .opc2 = 0, | |
3718 | .access = PL3_RW, .writefn = vmsa_ttbr_write, .resetvalue = 0, | |
3719 | .fieldoffset = offsetof(CPUARMState, cp15.ttbr0_el[3]) }, | |
11f136ee FA |
3720 | { .name = "TCR_EL3", .state = ARM_CP_STATE_AA64, |
3721 | .opc0 = 3, .opc1 = 6, .crn = 2, .crm = 0, .opc2 = 2, | |
3722 | .access = PL3_RW, .writefn = vmsa_tcr_el1_write, | |
3723 | .resetfn = vmsa_ttbcr_reset, .raw_writefn = raw_write, | |
3724 | .fieldoffset = offsetof(CPUARMState, cp15.tcr_el[3]) }, | |
81547d66 | 3725 | { .name = "ELR_EL3", .state = ARM_CP_STATE_AA64, |
7a0e58fa | 3726 | .type = ARM_CP_ALIAS, |
81547d66 EI |
3727 | .opc0 = 3, .opc1 = 6, .crn = 4, .crm = 0, .opc2 = 1, |
3728 | .access = PL3_RW, | |
3729 | .fieldoffset = offsetof(CPUARMState, elr_el[3]) }, | |
f2c30f42 | 3730 | { .name = "ESR_EL3", .state = ARM_CP_STATE_AA64, |
7a0e58fa | 3731 | .type = ARM_CP_ALIAS, |
f2c30f42 EI |
3732 | .opc0 = 3, .opc1 = 6, .crn = 5, .crm = 2, .opc2 = 0, |
3733 | .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.esr_el[3]) }, | |
63b60551 EI |
3734 | { .name = "FAR_EL3", .state = ARM_CP_STATE_AA64, |
3735 | .opc0 = 3, .opc1 = 6, .crn = 6, .crm = 0, .opc2 = 0, | |
3736 | .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.far_el[3]) }, | |
81547d66 | 3737 | { .name = "SPSR_EL3", .state = ARM_CP_STATE_AA64, |
7a0e58fa | 3738 | .type = ARM_CP_ALIAS, |
81547d66 | 3739 | .opc0 = 3, .opc1 = 6, .crn = 4, .crm = 0, .opc2 = 0, |
99a99c1f SB |
3740 | .access = PL3_RW, |
3741 | .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_MON]) }, | |
a1ba125c EI |
3742 | { .name = "VBAR_EL3", .state = ARM_CP_STATE_AA64, |
3743 | .opc0 = 3, .opc1 = 6, .crn = 12, .crm = 0, .opc2 = 0, | |
3744 | .access = PL3_RW, .writefn = vbar_write, | |
3745 | .fieldoffset = offsetof(CPUARMState, cp15.vbar_el[3]), | |
3746 | .resetvalue = 0 }, | |
c6f19164 GB |
3747 | { .name = "CPTR_EL3", .state = ARM_CP_STATE_AA64, |
3748 | .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 1, .opc2 = 2, | |
3749 | .access = PL3_RW, .accessfn = cptr_access, .resetvalue = 0, | |
3750 | .fieldoffset = offsetof(CPUARMState, cp15.cptr_el[3]) }, | |
4cfb8ad8 PM |
3751 | { .name = "TPIDR_EL3", .state = ARM_CP_STATE_AA64, |
3752 | .opc0 = 3, .opc1 = 6, .crn = 13, .crm = 0, .opc2 = 2, | |
3753 | .access = PL3_RW, .resetvalue = 0, | |
3754 | .fieldoffset = offsetof(CPUARMState, cp15.tpidr_el[3]) }, | |
2179ef95 PM |
3755 | { .name = "AMAIR_EL3", .state = ARM_CP_STATE_AA64, |
3756 | .opc0 = 3, .opc1 = 6, .crn = 10, .crm = 3, .opc2 = 0, | |
3757 | .access = PL3_RW, .type = ARM_CP_CONST, | |
3758 | .resetvalue = 0 }, | |
37cd6c24 PM |
3759 | { .name = "AFSR0_EL3", .state = ARM_CP_STATE_BOTH, |
3760 | .opc0 = 3, .opc1 = 6, .crn = 5, .crm = 1, .opc2 = 0, | |
3761 | .access = PL3_RW, .type = ARM_CP_CONST, | |
3762 | .resetvalue = 0 }, | |
3763 | { .name = "AFSR1_EL3", .state = ARM_CP_STATE_BOTH, | |
3764 | .opc0 = 3, .opc1 = 6, .crn = 5, .crm = 1, .opc2 = 1, | |
3765 | .access = PL3_RW, .type = ARM_CP_CONST, | |
3766 | .resetvalue = 0 }, | |
43efaa33 PM |
3767 | { .name = "TLBI_ALLE3IS", .state = ARM_CP_STATE_AA64, |
3768 | .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 3, .opc2 = 0, | |
3769 | .access = PL3_W, .type = ARM_CP_NO_RAW, | |
3770 | .writefn = tlbi_aa64_alle3is_write }, | |
3771 | { .name = "TLBI_VAE3IS", .state = ARM_CP_STATE_AA64, | |
3772 | .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 3, .opc2 = 1, | |
3773 | .access = PL3_W, .type = ARM_CP_NO_RAW, | |
3774 | .writefn = tlbi_aa64_vae3is_write }, | |
3775 | { .name = "TLBI_VALE3IS", .state = ARM_CP_STATE_AA64, | |
3776 | .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 3, .opc2 = 5, | |
3777 | .access = PL3_W, .type = ARM_CP_NO_RAW, | |
3778 | .writefn = tlbi_aa64_vae3is_write }, | |
3779 | { .name = "TLBI_ALLE3", .state = ARM_CP_STATE_AA64, | |
3780 | .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 7, .opc2 = 0, | |
3781 | .access = PL3_W, .type = ARM_CP_NO_RAW, | |
3782 | .writefn = tlbi_aa64_alle3_write }, | |
3783 | { .name = "TLBI_VAE3", .state = ARM_CP_STATE_AA64, | |
3784 | .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 7, .opc2 = 1, | |
3785 | .access = PL3_W, .type = ARM_CP_NO_RAW, | |
3786 | .writefn = tlbi_aa64_vae3_write }, | |
3787 | { .name = "TLBI_VALE3", .state = ARM_CP_STATE_AA64, | |
3788 | .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 7, .opc2 = 5, | |
3789 | .access = PL3_W, .type = ARM_CP_NO_RAW, | |
3790 | .writefn = tlbi_aa64_vae3_write }, | |
0f1a3b24 FA |
3791 | REGINFO_SENTINEL |
3792 | }; | |
3793 | ||
3f208fd7 PM |
3794 | static CPAccessResult ctr_el0_access(CPUARMState *env, const ARMCPRegInfo *ri, |
3795 | bool isread) | |
7da845b0 PM |
3796 | { |
3797 | /* Only accessible in EL0 if SCTLR.UCT is set (and only in AArch64, | |
3798 | * but the AArch32 CTR has its own reginfo struct) | |
3799 | */ | |
137feaa9 | 3800 | if (arm_current_el(env) == 0 && !(env->cp15.sctlr_el[1] & SCTLR_UCT)) { |
7da845b0 PM |
3801 | return CP_ACCESS_TRAP; |
3802 | } | |
3803 | return CP_ACCESS_OK; | |
3804 | } | |
3805 | ||
1424ca8d DM |
3806 | static void oslar_write(CPUARMState *env, const ARMCPRegInfo *ri, |
3807 | uint64_t value) | |
3808 | { | |
3809 | /* Writes to OSLAR_EL1 may update the OS lock status, which can be | |
3810 | * read via a bit in OSLSR_EL1. | |
3811 | */ | |
3812 | int oslock; | |
3813 | ||
3814 | if (ri->state == ARM_CP_STATE_AA32) { | |
3815 | oslock = (value == 0xC5ACCE55); | |
3816 | } else { | |
3817 | oslock = value & 1; | |
3818 | } | |
3819 | ||
3820 | env->cp15.oslsr_el1 = deposit32(env->cp15.oslsr_el1, 1, 1, oslock); | |
3821 | } | |
3822 | ||
50300698 | 3823 | static const ARMCPRegInfo debug_cp_reginfo[] = { |
50300698 | 3824 | /* DBGDRAR, DBGDSAR: always RAZ since we don't implement memory mapped |
10aae104 PM |
3825 | * debug components. The AArch64 version of DBGDRAR is named MDRAR_EL1; |
3826 | * unlike DBGDRAR it is never accessible from EL0. | |
3827 | * DBGDSAR is deprecated and must RAZ from v8 anyway, so it has no AArch64 | |
3828 | * accessor. | |
50300698 PM |
3829 | */ |
3830 | { .name = "DBGDRAR", .cp = 14, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 0, | |
91b0a238 PM |
3831 | .access = PL0_R, .accessfn = access_tdra, |
3832 | .type = ARM_CP_CONST, .resetvalue = 0 }, | |
10aae104 PM |
3833 | { .name = "MDRAR_EL1", .state = ARM_CP_STATE_AA64, |
3834 | .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 0, | |
91b0a238 PM |
3835 | .access = PL1_R, .accessfn = access_tdra, |
3836 | .type = ARM_CP_CONST, .resetvalue = 0 }, | |
50300698 | 3837 | { .name = "DBGDSAR", .cp = 14, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 0, |
91b0a238 PM |
3838 | .access = PL0_R, .accessfn = access_tdra, |
3839 | .type = ARM_CP_CONST, .resetvalue = 0 }, | |
17a9eb53 | 3840 | /* Monitor debug system control register; the 32-bit alias is DBGDSCRext. */ |
10aae104 PM |
3841 | { .name = "MDSCR_EL1", .state = ARM_CP_STATE_BOTH, |
3842 | .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 2, | |
d6c8cf81 | 3843 | .access = PL1_RW, .accessfn = access_tda, |
0e5e8935 PM |
3844 | .fieldoffset = offsetof(CPUARMState, cp15.mdscr_el1), |
3845 | .resetvalue = 0 }, | |
5e8b12ff PM |
3846 | /* MDCCSR_EL0, aka DBGDSCRint. This is a read-only mirror of MDSCR_EL1. |
3847 | * We don't implement the configurable EL0 access. | |
3848 | */ | |
3849 | { .name = "MDCCSR_EL0", .state = ARM_CP_STATE_BOTH, | |
3850 | .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 0, | |
7a0e58fa | 3851 | .type = ARM_CP_ALIAS, |
d6c8cf81 | 3852 | .access = PL1_R, .accessfn = access_tda, |
b061a82b | 3853 | .fieldoffset = offsetof(CPUARMState, cp15.mdscr_el1), }, |
10aae104 PM |
3854 | { .name = "OSLAR_EL1", .state = ARM_CP_STATE_BOTH, |
3855 | .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 4, | |
1424ca8d | 3856 | .access = PL1_W, .type = ARM_CP_NO_RAW, |
187f678d | 3857 | .accessfn = access_tdosa, |
1424ca8d DM |
3858 | .writefn = oslar_write }, |
3859 | { .name = "OSLSR_EL1", .state = ARM_CP_STATE_BOTH, | |
3860 | .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 4, | |
3861 | .access = PL1_R, .resetvalue = 10, | |
187f678d | 3862 | .accessfn = access_tdosa, |
1424ca8d | 3863 | .fieldoffset = offsetof(CPUARMState, cp15.oslsr_el1) }, |
5e8b12ff PM |
3864 | /* Dummy OSDLR_EL1: 32-bit Linux will read this */ |
3865 | { .name = "OSDLR_EL1", .state = ARM_CP_STATE_BOTH, | |
3866 | .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 3, .opc2 = 4, | |
187f678d PM |
3867 | .access = PL1_RW, .accessfn = access_tdosa, |
3868 | .type = ARM_CP_NOP }, | |
5e8b12ff PM |
3869 | /* Dummy DBGVCR: Linux wants to clear this on startup, but we don't |
3870 | * implement vector catch debug events yet. | |
3871 | */ | |
3872 | { .name = "DBGVCR", | |
3873 | .cp = 14, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 0, | |
d6c8cf81 PM |
3874 | .access = PL1_RW, .accessfn = access_tda, |
3875 | .type = ARM_CP_NOP }, | |
50300698 PM |
3876 | REGINFO_SENTINEL |
3877 | }; | |
3878 | ||
3879 | static const ARMCPRegInfo debug_lpae_cp_reginfo[] = { | |
3880 | /* 64 bit access versions of the (dummy) debug registers */ | |
3881 | { .name = "DBGDRAR", .cp = 14, .crm = 1, .opc1 = 0, | |
3882 | .access = PL0_R, .type = ARM_CP_CONST|ARM_CP_64BIT, .resetvalue = 0 }, | |
3883 | { .name = "DBGDSAR", .cp = 14, .crm = 2, .opc1 = 0, | |
3884 | .access = PL0_R, .type = ARM_CP_CONST|ARM_CP_64BIT, .resetvalue = 0 }, | |
3885 | REGINFO_SENTINEL | |
3886 | }; | |
3887 | ||
9ee98ce8 PM |
3888 | void hw_watchpoint_update(ARMCPU *cpu, int n) |
3889 | { | |
3890 | CPUARMState *env = &cpu->env; | |
3891 | vaddr len = 0; | |
3892 | vaddr wvr = env->cp15.dbgwvr[n]; | |
3893 | uint64_t wcr = env->cp15.dbgwcr[n]; | |
3894 | int mask; | |
3895 | int flags = BP_CPU | BP_STOP_BEFORE_ACCESS; | |
3896 | ||
3897 | if (env->cpu_watchpoint[n]) { | |
3898 | cpu_watchpoint_remove_by_ref(CPU(cpu), env->cpu_watchpoint[n]); | |
3899 | env->cpu_watchpoint[n] = NULL; | |
3900 | } | |
3901 | ||
3902 | if (!extract64(wcr, 0, 1)) { | |
3903 | /* E bit clear : watchpoint disabled */ | |
3904 | return; | |
3905 | } | |
3906 | ||
3907 | switch (extract64(wcr, 3, 2)) { | |
3908 | case 0: | |
3909 | /* LSC 00 is reserved and must behave as if the wp is disabled */ | |
3910 | return; | |
3911 | case 1: | |
3912 | flags |= BP_MEM_READ; | |
3913 | break; | |
3914 | case 2: | |
3915 | flags |= BP_MEM_WRITE; | |
3916 | break; | |
3917 | case 3: | |
3918 | flags |= BP_MEM_ACCESS; | |
3919 | break; | |
3920 | } | |
3921 | ||
3922 | /* Attempts to use both MASK and BAS fields simultaneously are | |
3923 | * CONSTRAINED UNPREDICTABLE; we opt to ignore BAS in this case, | |
3924 | * thus generating a watchpoint for every byte in the masked region. | |
3925 | */ | |
3926 | mask = extract64(wcr, 24, 4); | |
3927 | if (mask == 1 || mask == 2) { | |
3928 | /* Reserved values of MASK; we must act as if the mask value was | |
3929 | * some non-reserved value, or as if the watchpoint were disabled. | |
3930 | * We choose the latter. | |
3931 | */ | |
3932 | return; | |
3933 | } else if (mask) { | |
3934 | /* Watchpoint covers an aligned area up to 2GB in size */ | |
3935 | len = 1ULL << mask; | |
3936 | /* If masked bits in WVR are not zero it's CONSTRAINED UNPREDICTABLE | |
3937 | * whether the watchpoint fires when the unmasked bits match; we opt | |
3938 | * to generate the exceptions. | |
3939 | */ | |
3940 | wvr &= ~(len - 1); | |
3941 | } else { | |
3942 | /* Watchpoint covers bytes defined by the byte address select bits */ | |
3943 | int bas = extract64(wcr, 5, 8); | |
3944 | int basstart; | |
3945 | ||
3946 | if (bas == 0) { | |
3947 | /* This must act as if the watchpoint is disabled */ | |
3948 | return; | |
3949 | } | |
3950 | ||
3951 | if (extract64(wvr, 2, 1)) { | |
3952 | /* Deprecated case of an only 4-aligned address. BAS[7:4] are | |
3953 | * ignored, and BAS[3:0] define which bytes to watch. | |
3954 | */ | |
3955 | bas &= 0xf; | |
3956 | } | |
3957 | /* The BAS bits are supposed to be programmed to indicate a contiguous | |
3958 | * range of bytes. Otherwise it is CONSTRAINED UNPREDICTABLE whether | |
3959 | * we fire for each byte in the word/doubleword addressed by the WVR. | |
3960 | * We choose to ignore any non-zero bits after the first range of 1s. | |
3961 | */ | |
3962 | basstart = ctz32(bas); | |
3963 | len = cto32(bas >> basstart); | |
3964 | wvr += basstart; | |
3965 | } | |
3966 | ||
3967 | cpu_watchpoint_insert(CPU(cpu), wvr, len, flags, | |
3968 | &env->cpu_watchpoint[n]); | |
3969 | } | |
3970 | ||
3971 | void hw_watchpoint_update_all(ARMCPU *cpu) | |
3972 | { | |
3973 | int i; | |
3974 | CPUARMState *env = &cpu->env; | |
3975 | ||
3976 | /* Completely clear out existing QEMU watchpoints and our array, to | |
3977 | * avoid possible stale entries following migration load. | |
3978 | */ | |
3979 | cpu_watchpoint_remove_all(CPU(cpu), BP_CPU); | |
3980 | memset(env->cpu_watchpoint, 0, sizeof(env->cpu_watchpoint)); | |
3981 | ||
3982 | for (i = 0; i < ARRAY_SIZE(cpu->env.cpu_watchpoint); i++) { | |
3983 | hw_watchpoint_update(cpu, i); | |
3984 | } | |
3985 | } | |
3986 | ||
3987 | static void dbgwvr_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
3988 | uint64_t value) | |
3989 | { | |
3990 | ARMCPU *cpu = arm_env_get_cpu(env); | |
3991 | int i = ri->crm; | |
3992 | ||
3993 | /* Bits [63:49] are hardwired to the value of bit [48]; that is, the | |
3994 | * register reads and behaves as if values written are sign extended. | |
3995 | * Bits [1:0] are RES0. | |
3996 | */ | |
3997 | value = sextract64(value, 0, 49) & ~3ULL; | |
3998 | ||
3999 | raw_write(env, ri, value); | |
4000 | hw_watchpoint_update(cpu, i); | |
4001 | } | |
4002 | ||
4003 | static void dbgwcr_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
4004 | uint64_t value) | |
4005 | { | |
4006 | ARMCPU *cpu = arm_env_get_cpu(env); | |
4007 | int i = ri->crm; | |
4008 | ||
4009 | raw_write(env, ri, value); | |
4010 | hw_watchpoint_update(cpu, i); | |
4011 | } | |
4012 | ||
46747d15 PM |
4013 | void hw_breakpoint_update(ARMCPU *cpu, int n) |
4014 | { | |
4015 | CPUARMState *env = &cpu->env; | |
4016 | uint64_t bvr = env->cp15.dbgbvr[n]; | |
4017 | uint64_t bcr = env->cp15.dbgbcr[n]; | |
4018 | vaddr addr; | |
4019 | int bt; | |
4020 | int flags = BP_CPU; | |
4021 | ||
4022 | if (env->cpu_breakpoint[n]) { | |
4023 | cpu_breakpoint_remove_by_ref(CPU(cpu), env->cpu_breakpoint[n]); | |
4024 | env->cpu_breakpoint[n] = NULL; | |
4025 | } | |
4026 | ||
4027 | if (!extract64(bcr, 0, 1)) { | |
4028 | /* E bit clear : watchpoint disabled */ | |
4029 | return; | |
4030 | } | |
4031 | ||
4032 | bt = extract64(bcr, 20, 4); | |
4033 | ||
4034 | switch (bt) { | |
4035 | case 4: /* unlinked address mismatch (reserved if AArch64) */ | |
4036 | case 5: /* linked address mismatch (reserved if AArch64) */ | |
4037 | qemu_log_mask(LOG_UNIMP, | |
4038 | "arm: address mismatch breakpoint types not implemented"); | |
4039 | return; | |
4040 | case 0: /* unlinked address match */ | |
4041 | case 1: /* linked address match */ | |
4042 | { | |
4043 | /* Bits [63:49] are hardwired to the value of bit [48]; that is, | |
4044 | * we behave as if the register was sign extended. Bits [1:0] are | |
4045 | * RES0. The BAS field is used to allow setting breakpoints on 16 | |
4046 | * bit wide instructions; it is CONSTRAINED UNPREDICTABLE whether | |
4047 | * a bp will fire if the addresses covered by the bp and the addresses | |
4048 | * covered by the insn overlap but the insn doesn't start at the | |
4049 | * start of the bp address range. We choose to require the insn and | |
4050 | * the bp to have the same address. The constraints on writing to | |
4051 | * BAS enforced in dbgbcr_write mean we have only four cases: | |
4052 | * 0b0000 => no breakpoint | |
4053 | * 0b0011 => breakpoint on addr | |
4054 | * 0b1100 => breakpoint on addr + 2 | |
4055 | * 0b1111 => breakpoint on addr | |
4056 | * See also figure D2-3 in the v8 ARM ARM (DDI0487A.c). | |
4057 | */ | |
4058 | int bas = extract64(bcr, 5, 4); | |
4059 | addr = sextract64(bvr, 0, 49) & ~3ULL; | |
4060 | if (bas == 0) { | |
4061 | return; | |
4062 | } | |
4063 | if (bas == 0xc) { | |
4064 | addr += 2; | |
4065 | } | |
4066 | break; | |
4067 | } | |
4068 | case 2: /* unlinked context ID match */ | |
4069 | case 8: /* unlinked VMID match (reserved if no EL2) */ | |
4070 | case 10: /* unlinked context ID and VMID match (reserved if no EL2) */ | |
4071 | qemu_log_mask(LOG_UNIMP, | |
4072 | "arm: unlinked context breakpoint types not implemented"); | |
4073 | return; | |
4074 | case 9: /* linked VMID match (reserved if no EL2) */ | |
4075 | case 11: /* linked context ID and VMID match (reserved if no EL2) */ | |
4076 | case 3: /* linked context ID match */ | |
4077 | default: | |
4078 | /* We must generate no events for Linked context matches (unless | |
4079 | * they are linked to by some other bp/wp, which is handled in | |
4080 | * updates for the linking bp/wp). We choose to also generate no events | |
4081 | * for reserved values. | |
4082 | */ | |
4083 | return; | |
4084 | } | |
4085 | ||
4086 | cpu_breakpoint_insert(CPU(cpu), addr, flags, &env->cpu_breakpoint[n]); | |
4087 | } | |
4088 | ||
4089 | void hw_breakpoint_update_all(ARMCPU *cpu) | |
4090 | { | |
4091 | int i; | |
4092 | CPUARMState *env = &cpu->env; | |
4093 | ||
4094 | /* Completely clear out existing QEMU breakpoints and our array, to | |
4095 | * avoid possible stale entries following migration load. | |
4096 | */ | |
4097 | cpu_breakpoint_remove_all(CPU(cpu), BP_CPU); | |
4098 | memset(env->cpu_breakpoint, 0, sizeof(env->cpu_breakpoint)); | |
4099 | ||
4100 | for (i = 0; i < ARRAY_SIZE(cpu->env.cpu_breakpoint); i++) { | |
4101 | hw_breakpoint_update(cpu, i); | |
4102 | } | |
4103 | } | |
4104 | ||
4105 | static void dbgbvr_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
4106 | uint64_t value) | |
4107 | { | |
4108 | ARMCPU *cpu = arm_env_get_cpu(env); | |
4109 | int i = ri->crm; | |
4110 | ||
4111 | raw_write(env, ri, value); | |
4112 | hw_breakpoint_update(cpu, i); | |
4113 | } | |
4114 | ||
4115 | static void dbgbcr_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
4116 | uint64_t value) | |
4117 | { | |
4118 | ARMCPU *cpu = arm_env_get_cpu(env); | |
4119 | int i = ri->crm; | |
4120 | ||
4121 | /* BAS[3] is a read-only copy of BAS[2], and BAS[1] a read-only | |
4122 | * copy of BAS[0]. | |
4123 | */ | |
4124 | value = deposit64(value, 6, 1, extract64(value, 5, 1)); | |
4125 | value = deposit64(value, 8, 1, extract64(value, 7, 1)); | |
4126 | ||
4127 | raw_write(env, ri, value); | |
4128 | hw_breakpoint_update(cpu, i); | |
4129 | } | |
4130 | ||
50300698 | 4131 | static void define_debug_regs(ARMCPU *cpu) |
0b45451e | 4132 | { |
50300698 PM |
4133 | /* Define v7 and v8 architectural debug registers. |
4134 | * These are just dummy implementations for now. | |
0b45451e PM |
4135 | */ |
4136 | int i; | |
3ff6fc91 | 4137 | int wrps, brps, ctx_cmps; |
48eb3ae6 PM |
4138 | ARMCPRegInfo dbgdidr = { |
4139 | .name = "DBGDIDR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 0, | |
d6c8cf81 PM |
4140 | .access = PL0_R, .accessfn = access_tda, |
4141 | .type = ARM_CP_CONST, .resetvalue = cpu->dbgdidr, | |
48eb3ae6 PM |
4142 | }; |
4143 | ||
3ff6fc91 | 4144 | /* Note that all these register fields hold "number of Xs minus 1". */ |
48eb3ae6 PM |
4145 | brps = extract32(cpu->dbgdidr, 24, 4); |
4146 | wrps = extract32(cpu->dbgdidr, 28, 4); | |
3ff6fc91 PM |
4147 | ctx_cmps = extract32(cpu->dbgdidr, 20, 4); |
4148 | ||
4149 | assert(ctx_cmps <= brps); | |
48eb3ae6 PM |
4150 | |
4151 | /* The DBGDIDR and ID_AA64DFR0_EL1 define various properties | |
4152 | * of the debug registers such as number of breakpoints; | |
4153 | * check that if they both exist then they agree. | |
4154 | */ | |
4155 | if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { | |
4156 | assert(extract32(cpu->id_aa64dfr0, 12, 4) == brps); | |
4157 | assert(extract32(cpu->id_aa64dfr0, 20, 4) == wrps); | |
3ff6fc91 | 4158 | assert(extract32(cpu->id_aa64dfr0, 28, 4) == ctx_cmps); |
48eb3ae6 | 4159 | } |
0b45451e | 4160 | |
48eb3ae6 | 4161 | define_one_arm_cp_reg(cpu, &dbgdidr); |
50300698 PM |
4162 | define_arm_cp_regs(cpu, debug_cp_reginfo); |
4163 | ||
4164 | if (arm_feature(&cpu->env, ARM_FEATURE_LPAE)) { | |
4165 | define_arm_cp_regs(cpu, debug_lpae_cp_reginfo); | |
4166 | } | |
4167 | ||
48eb3ae6 | 4168 | for (i = 0; i < brps + 1; i++) { |
0b45451e | 4169 | ARMCPRegInfo dbgregs[] = { |
10aae104 PM |
4170 | { .name = "DBGBVR", .state = ARM_CP_STATE_BOTH, |
4171 | .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 4, | |
d6c8cf81 | 4172 | .access = PL1_RW, .accessfn = access_tda, |
46747d15 PM |
4173 | .fieldoffset = offsetof(CPUARMState, cp15.dbgbvr[i]), |
4174 | .writefn = dbgbvr_write, .raw_writefn = raw_write | |
4175 | }, | |
10aae104 PM |
4176 | { .name = "DBGBCR", .state = ARM_CP_STATE_BOTH, |
4177 | .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 5, | |
d6c8cf81 | 4178 | .access = PL1_RW, .accessfn = access_tda, |
46747d15 PM |
4179 | .fieldoffset = offsetof(CPUARMState, cp15.dbgbcr[i]), |
4180 | .writefn = dbgbcr_write, .raw_writefn = raw_write | |
4181 | }, | |
48eb3ae6 PM |
4182 | REGINFO_SENTINEL |
4183 | }; | |
4184 | define_arm_cp_regs(cpu, dbgregs); | |
4185 | } | |
4186 | ||
4187 | for (i = 0; i < wrps + 1; i++) { | |
4188 | ARMCPRegInfo dbgregs[] = { | |
10aae104 PM |
4189 | { .name = "DBGWVR", .state = ARM_CP_STATE_BOTH, |
4190 | .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 6, | |
d6c8cf81 | 4191 | .access = PL1_RW, .accessfn = access_tda, |
9ee98ce8 PM |
4192 | .fieldoffset = offsetof(CPUARMState, cp15.dbgwvr[i]), |
4193 | .writefn = dbgwvr_write, .raw_writefn = raw_write | |
4194 | }, | |
10aae104 PM |
4195 | { .name = "DBGWCR", .state = ARM_CP_STATE_BOTH, |
4196 | .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 7, | |
d6c8cf81 | 4197 | .access = PL1_RW, .accessfn = access_tda, |
9ee98ce8 PM |
4198 | .fieldoffset = offsetof(CPUARMState, cp15.dbgwcr[i]), |
4199 | .writefn = dbgwcr_write, .raw_writefn = raw_write | |
4200 | }, | |
4201 | REGINFO_SENTINEL | |
0b45451e PM |
4202 | }; |
4203 | define_arm_cp_regs(cpu, dbgregs); | |
4204 | } | |
4205 | } | |
4206 | ||
2ceb98c0 PM |
4207 | void register_cp_regs_for_features(ARMCPU *cpu) |
4208 | { | |
4209 | /* Register all the coprocessor registers based on feature bits */ | |
4210 | CPUARMState *env = &cpu->env; | |
4211 | if (arm_feature(env, ARM_FEATURE_M)) { | |
4212 | /* M profile has no coprocessor registers */ | |
4213 | return; | |
4214 | } | |
4215 | ||
e9aa6c21 | 4216 | define_arm_cp_regs(cpu, cp_reginfo); |
9449fdf6 PM |
4217 | if (!arm_feature(env, ARM_FEATURE_V8)) { |
4218 | /* Must go early as it is full of wildcards that may be | |
4219 | * overridden by later definitions. | |
4220 | */ | |
4221 | define_arm_cp_regs(cpu, not_v8_cp_reginfo); | |
4222 | } | |
4223 | ||
7d57f408 | 4224 | if (arm_feature(env, ARM_FEATURE_V6)) { |
8515a092 PM |
4225 | /* The ID registers all have impdef reset values */ |
4226 | ARMCPRegInfo v6_idregs[] = { | |
0ff644a7 PM |
4227 | { .name = "ID_PFR0", .state = ARM_CP_STATE_BOTH, |
4228 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 0, | |
4229 | .access = PL1_R, .type = ARM_CP_CONST, | |
8515a092 | 4230 | .resetvalue = cpu->id_pfr0 }, |
0ff644a7 PM |
4231 | { .name = "ID_PFR1", .state = ARM_CP_STATE_BOTH, |
4232 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 1, | |
4233 | .access = PL1_R, .type = ARM_CP_CONST, | |
8515a092 | 4234 | .resetvalue = cpu->id_pfr1 }, |
0ff644a7 PM |
4235 | { .name = "ID_DFR0", .state = ARM_CP_STATE_BOTH, |
4236 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 2, | |
4237 | .access = PL1_R, .type = ARM_CP_CONST, | |
8515a092 | 4238 | .resetvalue = cpu->id_dfr0 }, |
0ff644a7 PM |
4239 | { .name = "ID_AFR0", .state = ARM_CP_STATE_BOTH, |
4240 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 3, | |
4241 | .access = PL1_R, .type = ARM_CP_CONST, | |
8515a092 | 4242 | .resetvalue = cpu->id_afr0 }, |
0ff644a7 PM |
4243 | { .name = "ID_MMFR0", .state = ARM_CP_STATE_BOTH, |
4244 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 4, | |
4245 | .access = PL1_R, .type = ARM_CP_CONST, | |
8515a092 | 4246 | .resetvalue = cpu->id_mmfr0 }, |
0ff644a7 PM |
4247 | { .name = "ID_MMFR1", .state = ARM_CP_STATE_BOTH, |
4248 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 5, | |
4249 | .access = PL1_R, .type = ARM_CP_CONST, | |
8515a092 | 4250 | .resetvalue = cpu->id_mmfr1 }, |
0ff644a7 PM |
4251 | { .name = "ID_MMFR2", .state = ARM_CP_STATE_BOTH, |
4252 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 6, | |
4253 | .access = PL1_R, .type = ARM_CP_CONST, | |
8515a092 | 4254 | .resetvalue = cpu->id_mmfr2 }, |
0ff644a7 PM |
4255 | { .name = "ID_MMFR3", .state = ARM_CP_STATE_BOTH, |
4256 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 7, | |
4257 | .access = PL1_R, .type = ARM_CP_CONST, | |
8515a092 | 4258 | .resetvalue = cpu->id_mmfr3 }, |
0ff644a7 PM |
4259 | { .name = "ID_ISAR0", .state = ARM_CP_STATE_BOTH, |
4260 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 0, | |
4261 | .access = PL1_R, .type = ARM_CP_CONST, | |
8515a092 | 4262 | .resetvalue = cpu->id_isar0 }, |
0ff644a7 PM |
4263 | { .name = "ID_ISAR1", .state = ARM_CP_STATE_BOTH, |
4264 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 1, | |
4265 | .access = PL1_R, .type = ARM_CP_CONST, | |
8515a092 | 4266 | .resetvalue = cpu->id_isar1 }, |
0ff644a7 PM |
4267 | { .name = "ID_ISAR2", .state = ARM_CP_STATE_BOTH, |
4268 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 2, | |
4269 | .access = PL1_R, .type = ARM_CP_CONST, | |
8515a092 | 4270 | .resetvalue = cpu->id_isar2 }, |
0ff644a7 PM |
4271 | { .name = "ID_ISAR3", .state = ARM_CP_STATE_BOTH, |
4272 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 3, | |
4273 | .access = PL1_R, .type = ARM_CP_CONST, | |
8515a092 | 4274 | .resetvalue = cpu->id_isar3 }, |
0ff644a7 PM |
4275 | { .name = "ID_ISAR4", .state = ARM_CP_STATE_BOTH, |
4276 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 4, | |
4277 | .access = PL1_R, .type = ARM_CP_CONST, | |
8515a092 | 4278 | .resetvalue = cpu->id_isar4 }, |
0ff644a7 PM |
4279 | { .name = "ID_ISAR5", .state = ARM_CP_STATE_BOTH, |
4280 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 5, | |
4281 | .access = PL1_R, .type = ARM_CP_CONST, | |
8515a092 PM |
4282 | .resetvalue = cpu->id_isar5 }, |
4283 | /* 6..7 are as yet unallocated and must RAZ */ | |
4284 | { .name = "ID_ISAR6", .cp = 15, .crn = 0, .crm = 2, | |
4285 | .opc1 = 0, .opc2 = 6, .access = PL1_R, .type = ARM_CP_CONST, | |
4286 | .resetvalue = 0 }, | |
4287 | { .name = "ID_ISAR7", .cp = 15, .crn = 0, .crm = 2, | |
4288 | .opc1 = 0, .opc2 = 7, .access = PL1_R, .type = ARM_CP_CONST, | |
4289 | .resetvalue = 0 }, | |
4290 | REGINFO_SENTINEL | |
4291 | }; | |
4292 | define_arm_cp_regs(cpu, v6_idregs); | |
7d57f408 PM |
4293 | define_arm_cp_regs(cpu, v6_cp_reginfo); |
4294 | } else { | |
4295 | define_arm_cp_regs(cpu, not_v6_cp_reginfo); | |
4296 | } | |
4d31c596 PM |
4297 | if (arm_feature(env, ARM_FEATURE_V6K)) { |
4298 | define_arm_cp_regs(cpu, v6k_cp_reginfo); | |
4299 | } | |
5e5cf9e3 PC |
4300 | if (arm_feature(env, ARM_FEATURE_V7MP) && |
4301 | !arm_feature(env, ARM_FEATURE_MPU)) { | |
995939a6 PM |
4302 | define_arm_cp_regs(cpu, v7mp_cp_reginfo); |
4303 | } | |
e9aa6c21 | 4304 | if (arm_feature(env, ARM_FEATURE_V7)) { |
200ac0ef | 4305 | /* v7 performance monitor control register: same implementor |
7c2cb42b AF |
4306 | * field as main ID register, and we implement only the cycle |
4307 | * count register. | |
200ac0ef | 4308 | */ |
7c2cb42b | 4309 | #ifndef CONFIG_USER_ONLY |
200ac0ef PM |
4310 | ARMCPRegInfo pmcr = { |
4311 | .name = "PMCR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 0, | |
8521466b | 4312 | .access = PL0_RW, |
7a0e58fa | 4313 | .type = ARM_CP_IO | ARM_CP_ALIAS, |
8521466b | 4314 | .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmcr), |
fcd25206 PM |
4315 | .accessfn = pmreg_access, .writefn = pmcr_write, |
4316 | .raw_writefn = raw_write, | |
200ac0ef | 4317 | }; |
8521466b AF |
4318 | ARMCPRegInfo pmcr64 = { |
4319 | .name = "PMCR_EL0", .state = ARM_CP_STATE_AA64, | |
4320 | .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 0, | |
4321 | .access = PL0_RW, .accessfn = pmreg_access, | |
4322 | .type = ARM_CP_IO, | |
4323 | .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcr), | |
4324 | .resetvalue = cpu->midr & 0xff000000, | |
4325 | .writefn = pmcr_write, .raw_writefn = raw_write, | |
4326 | }; | |
7c2cb42b | 4327 | define_one_arm_cp_reg(cpu, &pmcr); |
8521466b | 4328 | define_one_arm_cp_reg(cpu, &pmcr64); |
7c2cb42b | 4329 | #endif |
776d4e5c | 4330 | ARMCPRegInfo clidr = { |
7da845b0 PM |
4331 | .name = "CLIDR", .state = ARM_CP_STATE_BOTH, |
4332 | .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 1, | |
776d4e5c PM |
4333 | .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = cpu->clidr |
4334 | }; | |
776d4e5c | 4335 | define_one_arm_cp_reg(cpu, &clidr); |
e9aa6c21 | 4336 | define_arm_cp_regs(cpu, v7_cp_reginfo); |
50300698 | 4337 | define_debug_regs(cpu); |
7d57f408 PM |
4338 | } else { |
4339 | define_arm_cp_regs(cpu, not_v7_cp_reginfo); | |
e9aa6c21 | 4340 | } |
b0d2b7d0 | 4341 | if (arm_feature(env, ARM_FEATURE_V8)) { |
e60cef86 PM |
4342 | /* AArch64 ID registers, which all have impdef reset values */ |
4343 | ARMCPRegInfo v8_idregs[] = { | |
4344 | { .name = "ID_AA64PFR0_EL1", .state = ARM_CP_STATE_AA64, | |
4345 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 0, | |
4346 | .access = PL1_R, .type = ARM_CP_CONST, | |
4347 | .resetvalue = cpu->id_aa64pfr0 }, | |
4348 | { .name = "ID_AA64PFR1_EL1", .state = ARM_CP_STATE_AA64, | |
4349 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 1, | |
4350 | .access = PL1_R, .type = ARM_CP_CONST, | |
4351 | .resetvalue = cpu->id_aa64pfr1}, | |
4352 | { .name = "ID_AA64DFR0_EL1", .state = ARM_CP_STATE_AA64, | |
4353 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 0, | |
4354 | .access = PL1_R, .type = ARM_CP_CONST, | |
5d831be2 | 4355 | /* We mask out the PMUVer field, because we don't currently |
9225d739 PM |
4356 | * implement the PMU. Not advertising it prevents the guest |
4357 | * from trying to use it and getting UNDEFs on registers we | |
4358 | * don't implement. | |
4359 | */ | |
4360 | .resetvalue = cpu->id_aa64dfr0 & ~0xf00 }, | |
e60cef86 PM |
4361 | { .name = "ID_AA64DFR1_EL1", .state = ARM_CP_STATE_AA64, |
4362 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 1, | |
4363 | .access = PL1_R, .type = ARM_CP_CONST, | |
4364 | .resetvalue = cpu->id_aa64dfr1 }, | |
4365 | { .name = "ID_AA64AFR0_EL1", .state = ARM_CP_STATE_AA64, | |
4366 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 4, | |
4367 | .access = PL1_R, .type = ARM_CP_CONST, | |
4368 | .resetvalue = cpu->id_aa64afr0 }, | |
4369 | { .name = "ID_AA64AFR1_EL1", .state = ARM_CP_STATE_AA64, | |
4370 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 5, | |
4371 | .access = PL1_R, .type = ARM_CP_CONST, | |
4372 | .resetvalue = cpu->id_aa64afr1 }, | |
4373 | { .name = "ID_AA64ISAR0_EL1", .state = ARM_CP_STATE_AA64, | |
4374 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 0, | |
4375 | .access = PL1_R, .type = ARM_CP_CONST, | |
4376 | .resetvalue = cpu->id_aa64isar0 }, | |
4377 | { .name = "ID_AA64ISAR1_EL1", .state = ARM_CP_STATE_AA64, | |
4378 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 1, | |
4379 | .access = PL1_R, .type = ARM_CP_CONST, | |
4380 | .resetvalue = cpu->id_aa64isar1 }, | |
4381 | { .name = "ID_AA64MMFR0_EL1", .state = ARM_CP_STATE_AA64, | |
4382 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 0, | |
4383 | .access = PL1_R, .type = ARM_CP_CONST, | |
4384 | .resetvalue = cpu->id_aa64mmfr0 }, | |
4385 | { .name = "ID_AA64MMFR1_EL1", .state = ARM_CP_STATE_AA64, | |
4386 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 1, | |
4387 | .access = PL1_R, .type = ARM_CP_CONST, | |
4388 | .resetvalue = cpu->id_aa64mmfr1 }, | |
a50c0f51 PM |
4389 | { .name = "MVFR0_EL1", .state = ARM_CP_STATE_AA64, |
4390 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 0, | |
4391 | .access = PL1_R, .type = ARM_CP_CONST, | |
4392 | .resetvalue = cpu->mvfr0 }, | |
4393 | { .name = "MVFR1_EL1", .state = ARM_CP_STATE_AA64, | |
4394 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 1, | |
4395 | .access = PL1_R, .type = ARM_CP_CONST, | |
4396 | .resetvalue = cpu->mvfr1 }, | |
4397 | { .name = "MVFR2_EL1", .state = ARM_CP_STATE_AA64, | |
4398 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 2, | |
4399 | .access = PL1_R, .type = ARM_CP_CONST, | |
4400 | .resetvalue = cpu->mvfr2 }, | |
4054bfa9 AF |
4401 | { .name = "PMCEID0", .state = ARM_CP_STATE_AA32, |
4402 | .cp = 15, .opc1 = 0, .crn = 9, .crm = 12, .opc2 = 6, | |
4403 | .access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST, | |
4404 | .resetvalue = cpu->pmceid0 }, | |
4405 | { .name = "PMCEID0_EL0", .state = ARM_CP_STATE_AA64, | |
4406 | .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 6, | |
4407 | .access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST, | |
4408 | .resetvalue = cpu->pmceid0 }, | |
4409 | { .name = "PMCEID1", .state = ARM_CP_STATE_AA32, | |
4410 | .cp = 15, .opc1 = 0, .crn = 9, .crm = 12, .opc2 = 7, | |
4411 | .access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST, | |
4412 | .resetvalue = cpu->pmceid1 }, | |
4413 | { .name = "PMCEID1_EL0", .state = ARM_CP_STATE_AA64, | |
4414 | .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 7, | |
4415 | .access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST, | |
4416 | .resetvalue = cpu->pmceid1 }, | |
e60cef86 PM |
4417 | REGINFO_SENTINEL |
4418 | }; | |
be8e8128 GB |
4419 | /* RVBAR_EL1 is only implemented if EL1 is the highest EL */ |
4420 | if (!arm_feature(env, ARM_FEATURE_EL3) && | |
4421 | !arm_feature(env, ARM_FEATURE_EL2)) { | |
4422 | ARMCPRegInfo rvbar = { | |
4423 | .name = "RVBAR_EL1", .state = ARM_CP_STATE_AA64, | |
4424 | .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 0, .opc2 = 1, | |
4425 | .type = ARM_CP_CONST, .access = PL1_R, .resetvalue = cpu->rvbar | |
4426 | }; | |
4427 | define_one_arm_cp_reg(cpu, &rvbar); | |
4428 | } | |
e60cef86 | 4429 | define_arm_cp_regs(cpu, v8_idregs); |
b0d2b7d0 PM |
4430 | define_arm_cp_regs(cpu, v8_cp_reginfo); |
4431 | } | |
3b685ba7 | 4432 | if (arm_feature(env, ARM_FEATURE_EL2)) { |
f0d574d6 | 4433 | uint64_t vmpidr_def = mpidr_read_val(env); |
731de9e6 EI |
4434 | ARMCPRegInfo vpidr_regs[] = { |
4435 | { .name = "VPIDR", .state = ARM_CP_STATE_AA32, | |
4436 | .cp = 15, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 0, | |
4437 | .access = PL2_RW, .accessfn = access_el3_aa32ns, | |
4438 | .resetvalue = cpu->midr, | |
4439 | .fieldoffset = offsetof(CPUARMState, cp15.vpidr_el2) }, | |
4440 | { .name = "VPIDR_EL2", .state = ARM_CP_STATE_AA64, | |
4441 | .opc0 = 3, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 0, | |
4442 | .access = PL2_RW, .resetvalue = cpu->midr, | |
4443 | .fieldoffset = offsetof(CPUARMState, cp15.vpidr_el2) }, | |
f0d574d6 EI |
4444 | { .name = "VMPIDR", .state = ARM_CP_STATE_AA32, |
4445 | .cp = 15, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 5, | |
4446 | .access = PL2_RW, .accessfn = access_el3_aa32ns, | |
4447 | .resetvalue = vmpidr_def, | |
4448 | .fieldoffset = offsetof(CPUARMState, cp15.vmpidr_el2) }, | |
4449 | { .name = "VMPIDR_EL2", .state = ARM_CP_STATE_AA64, | |
4450 | .opc0 = 3, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 5, | |
4451 | .access = PL2_RW, | |
4452 | .resetvalue = vmpidr_def, | |
4453 | .fieldoffset = offsetof(CPUARMState, cp15.vmpidr_el2) }, | |
731de9e6 EI |
4454 | REGINFO_SENTINEL |
4455 | }; | |
4456 | define_arm_cp_regs(cpu, vpidr_regs); | |
4771cd01 | 4457 | define_arm_cp_regs(cpu, el2_cp_reginfo); |
be8e8128 GB |
4458 | /* RVBAR_EL2 is only implemented if EL2 is the highest EL */ |
4459 | if (!arm_feature(env, ARM_FEATURE_EL3)) { | |
4460 | ARMCPRegInfo rvbar = { | |
4461 | .name = "RVBAR_EL2", .state = ARM_CP_STATE_AA64, | |
4462 | .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 0, .opc2 = 1, | |
4463 | .type = ARM_CP_CONST, .access = PL2_R, .resetvalue = cpu->rvbar | |
4464 | }; | |
4465 | define_one_arm_cp_reg(cpu, &rvbar); | |
4466 | } | |
d42e3c26 EI |
4467 | } else { |
4468 | /* If EL2 is missing but higher ELs are enabled, we need to | |
4469 | * register the no_el2 reginfos. | |
4470 | */ | |
4471 | if (arm_feature(env, ARM_FEATURE_EL3)) { | |
f0d574d6 EI |
4472 | /* When EL3 exists but not EL2, VPIDR and VMPIDR take the value |
4473 | * of MIDR_EL1 and MPIDR_EL1. | |
731de9e6 EI |
4474 | */ |
4475 | ARMCPRegInfo vpidr_regs[] = { | |
4476 | { .name = "VPIDR_EL2", .state = ARM_CP_STATE_BOTH, | |
4477 | .opc0 = 3, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 0, | |
4478 | .access = PL2_RW, .accessfn = access_el3_aa32ns_aa64any, | |
4479 | .type = ARM_CP_CONST, .resetvalue = cpu->midr, | |
4480 | .fieldoffset = offsetof(CPUARMState, cp15.vpidr_el2) }, | |
f0d574d6 EI |
4481 | { .name = "VMPIDR_EL2", .state = ARM_CP_STATE_BOTH, |
4482 | .opc0 = 3, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 5, | |
4483 | .access = PL2_RW, .accessfn = access_el3_aa32ns_aa64any, | |
4484 | .type = ARM_CP_NO_RAW, | |
4485 | .writefn = arm_cp_write_ignore, .readfn = mpidr_read }, | |
731de9e6 EI |
4486 | REGINFO_SENTINEL |
4487 | }; | |
4488 | define_arm_cp_regs(cpu, vpidr_regs); | |
4771cd01 | 4489 | define_arm_cp_regs(cpu, el3_no_el2_cp_reginfo); |
d42e3c26 | 4490 | } |
3b685ba7 | 4491 | } |
81547d66 | 4492 | if (arm_feature(env, ARM_FEATURE_EL3)) { |
0f1a3b24 | 4493 | define_arm_cp_regs(cpu, el3_cp_reginfo); |
be8e8128 GB |
4494 | ARMCPRegInfo rvbar = { |
4495 | .name = "RVBAR_EL3", .state = ARM_CP_STATE_AA64, | |
4496 | .opc0 = 3, .opc1 = 6, .crn = 12, .crm = 0, .opc2 = 1, | |
4497 | .type = ARM_CP_CONST, .access = PL3_R, .resetvalue = cpu->rvbar | |
4498 | }; | |
4499 | define_one_arm_cp_reg(cpu, &rvbar); | |
81547d66 | 4500 | } |
2f027fc5 PM |
4501 | /* The behaviour of NSACR is sufficiently various that we don't |
4502 | * try to describe it in a single reginfo: | |
4503 | * if EL3 is 64 bit, then trap to EL3 from S EL1, | |
4504 | * reads as constant 0xc00 from NS EL1 and NS EL2 | |
4505 | * if EL3 is 32 bit, then RW at EL3, RO at NS EL1 and NS EL2 | |
4506 | * if v7 without EL3, register doesn't exist | |
4507 | * if v8 without EL3, reads as constant 0xc00 from NS EL1 and NS EL2 | |
4508 | */ | |
4509 | if (arm_feature(env, ARM_FEATURE_EL3)) { | |
4510 | if (arm_feature(env, ARM_FEATURE_AARCH64)) { | |
4511 | ARMCPRegInfo nsacr = { | |
4512 | .name = "NSACR", .type = ARM_CP_CONST, | |
4513 | .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 2, | |
4514 | .access = PL1_RW, .accessfn = nsacr_access, | |
4515 | .resetvalue = 0xc00 | |
4516 | }; | |
4517 | define_one_arm_cp_reg(cpu, &nsacr); | |
4518 | } else { | |
4519 | ARMCPRegInfo nsacr = { | |
4520 | .name = "NSACR", | |
4521 | .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 2, | |
4522 | .access = PL3_RW | PL1_R, | |
4523 | .resetvalue = 0, | |
4524 | .fieldoffset = offsetof(CPUARMState, cp15.nsacr) | |
4525 | }; | |
4526 | define_one_arm_cp_reg(cpu, &nsacr); | |
4527 | } | |
4528 | } else { | |
4529 | if (arm_feature(env, ARM_FEATURE_V8)) { | |
4530 | ARMCPRegInfo nsacr = { | |
4531 | .name = "NSACR", .type = ARM_CP_CONST, | |
4532 | .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 2, | |
4533 | .access = PL1_R, | |
4534 | .resetvalue = 0xc00 | |
4535 | }; | |
4536 | define_one_arm_cp_reg(cpu, &nsacr); | |
4537 | } | |
4538 | } | |
4539 | ||
18032bec | 4540 | if (arm_feature(env, ARM_FEATURE_MPU)) { |
6cb0b013 PC |
4541 | if (arm_feature(env, ARM_FEATURE_V6)) { |
4542 | /* PMSAv6 not implemented */ | |
4543 | assert(arm_feature(env, ARM_FEATURE_V7)); | |
4544 | define_arm_cp_regs(cpu, vmsa_pmsa_cp_reginfo); | |
4545 | define_arm_cp_regs(cpu, pmsav7_cp_reginfo); | |
4546 | } else { | |
4547 | define_arm_cp_regs(cpu, pmsav5_cp_reginfo); | |
4548 | } | |
18032bec | 4549 | } else { |
8e5d75c9 | 4550 | define_arm_cp_regs(cpu, vmsa_pmsa_cp_reginfo); |
18032bec PM |
4551 | define_arm_cp_regs(cpu, vmsa_cp_reginfo); |
4552 | } | |
c326b979 PM |
4553 | if (arm_feature(env, ARM_FEATURE_THUMB2EE)) { |
4554 | define_arm_cp_regs(cpu, t2ee_cp_reginfo); | |
4555 | } | |
6cc7a3ae PM |
4556 | if (arm_feature(env, ARM_FEATURE_GENERIC_TIMER)) { |
4557 | define_arm_cp_regs(cpu, generic_timer_cp_reginfo); | |
4558 | } | |
4a501606 PM |
4559 | if (arm_feature(env, ARM_FEATURE_VAPA)) { |
4560 | define_arm_cp_regs(cpu, vapa_cp_reginfo); | |
4561 | } | |
c4804214 PM |
4562 | if (arm_feature(env, ARM_FEATURE_CACHE_TEST_CLEAN)) { |
4563 | define_arm_cp_regs(cpu, cache_test_clean_cp_reginfo); | |
4564 | } | |
4565 | if (arm_feature(env, ARM_FEATURE_CACHE_DIRTY_REG)) { | |
4566 | define_arm_cp_regs(cpu, cache_dirty_status_cp_reginfo); | |
4567 | } | |
4568 | if (arm_feature(env, ARM_FEATURE_CACHE_BLOCK_OPS)) { | |
4569 | define_arm_cp_regs(cpu, cache_block_ops_cp_reginfo); | |
4570 | } | |
18032bec PM |
4571 | if (arm_feature(env, ARM_FEATURE_OMAPCP)) { |
4572 | define_arm_cp_regs(cpu, omap_cp_reginfo); | |
4573 | } | |
34f90529 PM |
4574 | if (arm_feature(env, ARM_FEATURE_STRONGARM)) { |
4575 | define_arm_cp_regs(cpu, strongarm_cp_reginfo); | |
4576 | } | |
1047b9d7 PM |
4577 | if (arm_feature(env, ARM_FEATURE_XSCALE)) { |
4578 | define_arm_cp_regs(cpu, xscale_cp_reginfo); | |
4579 | } | |
4580 | if (arm_feature(env, ARM_FEATURE_DUMMY_C15_REGS)) { | |
4581 | define_arm_cp_regs(cpu, dummy_c15_cp_reginfo); | |
4582 | } | |
7ac681cf PM |
4583 | if (arm_feature(env, ARM_FEATURE_LPAE)) { |
4584 | define_arm_cp_regs(cpu, lpae_cp_reginfo); | |
4585 | } | |
7884849c PM |
4586 | /* Slightly awkwardly, the OMAP and StrongARM cores need all of |
4587 | * cp15 crn=0 to be writes-ignored, whereas for other cores they should | |
4588 | * be read-only (ie write causes UNDEF exception). | |
4589 | */ | |
4590 | { | |
00a29f3d PM |
4591 | ARMCPRegInfo id_pre_v8_midr_cp_reginfo[] = { |
4592 | /* Pre-v8 MIDR space. | |
4593 | * Note that the MIDR isn't a simple constant register because | |
7884849c PM |
4594 | * of the TI925 behaviour where writes to another register can |
4595 | * cause the MIDR value to change. | |
97ce8d61 PC |
4596 | * |
4597 | * Unimplemented registers in the c15 0 0 0 space default to | |
4598 | * MIDR. Define MIDR first as this entire space, then CTR, TCMTR | |
4599 | * and friends override accordingly. | |
7884849c PM |
4600 | */ |
4601 | { .name = "MIDR", | |
97ce8d61 | 4602 | .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = CP_ANY, |
7884849c | 4603 | .access = PL1_R, .resetvalue = cpu->midr, |
d4e6df63 | 4604 | .writefn = arm_cp_write_ignore, .raw_writefn = raw_write, |
731de9e6 | 4605 | .readfn = midr_read, |
97ce8d61 PC |
4606 | .fieldoffset = offsetof(CPUARMState, cp15.c0_cpuid), |
4607 | .type = ARM_CP_OVERRIDE }, | |
7884849c PM |
4608 | /* crn = 0 op1 = 0 crm = 3..7 : currently unassigned; we RAZ. */ |
4609 | { .name = "DUMMY", | |
4610 | .cp = 15, .crn = 0, .crm = 3, .opc1 = 0, .opc2 = CP_ANY, | |
4611 | .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
4612 | { .name = "DUMMY", | |
4613 | .cp = 15, .crn = 0, .crm = 4, .opc1 = 0, .opc2 = CP_ANY, | |
4614 | .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
4615 | { .name = "DUMMY", | |
4616 | .cp = 15, .crn = 0, .crm = 5, .opc1 = 0, .opc2 = CP_ANY, | |
4617 | .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
4618 | { .name = "DUMMY", | |
4619 | .cp = 15, .crn = 0, .crm = 6, .opc1 = 0, .opc2 = CP_ANY, | |
4620 | .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
4621 | { .name = "DUMMY", | |
4622 | .cp = 15, .crn = 0, .crm = 7, .opc1 = 0, .opc2 = CP_ANY, | |
4623 | .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
4624 | REGINFO_SENTINEL | |
4625 | }; | |
00a29f3d | 4626 | ARMCPRegInfo id_v8_midr_cp_reginfo[] = { |
00a29f3d PM |
4627 | { .name = "MIDR_EL1", .state = ARM_CP_STATE_BOTH, |
4628 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 0, .opc2 = 0, | |
731de9e6 EI |
4629 | .access = PL1_R, .type = ARM_CP_NO_RAW, .resetvalue = cpu->midr, |
4630 | .fieldoffset = offsetof(CPUARMState, cp15.c0_cpuid), | |
4631 | .readfn = midr_read }, | |
ac00c79f SF |
4632 | /* crn = 0 op1 = 0 crm = 0 op2 = 4,7 : AArch32 aliases of MIDR */ |
4633 | { .name = "MIDR", .type = ARM_CP_ALIAS | ARM_CP_CONST, | |
4634 | .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 4, | |
4635 | .access = PL1_R, .resetvalue = cpu->midr }, | |
4636 | { .name = "MIDR", .type = ARM_CP_ALIAS | ARM_CP_CONST, | |
4637 | .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 7, | |
4638 | .access = PL1_R, .resetvalue = cpu->midr }, | |
00a29f3d PM |
4639 | { .name = "REVIDR_EL1", .state = ARM_CP_STATE_BOTH, |
4640 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 0, .opc2 = 6, | |
13b72b2b | 4641 | .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = cpu->revidr }, |
00a29f3d PM |
4642 | REGINFO_SENTINEL |
4643 | }; | |
4644 | ARMCPRegInfo id_cp_reginfo[] = { | |
4645 | /* These are common to v8 and pre-v8 */ | |
4646 | { .name = "CTR", | |
4647 | .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 1, | |
4648 | .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = cpu->ctr }, | |
4649 | { .name = "CTR_EL0", .state = ARM_CP_STATE_AA64, | |
4650 | .opc0 = 3, .opc1 = 3, .opc2 = 1, .crn = 0, .crm = 0, | |
4651 | .access = PL0_R, .accessfn = ctr_el0_access, | |
4652 | .type = ARM_CP_CONST, .resetvalue = cpu->ctr }, | |
4653 | /* TCMTR and TLBTR exist in v8 but have no 64-bit versions */ | |
4654 | { .name = "TCMTR", | |
4655 | .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 2, | |
4656 | .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
00a29f3d PM |
4657 | REGINFO_SENTINEL |
4658 | }; | |
8085ce63 PC |
4659 | /* TLBTR is specific to VMSA */ |
4660 | ARMCPRegInfo id_tlbtr_reginfo = { | |
4661 | .name = "TLBTR", | |
4662 | .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 3, | |
4663 | .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0, | |
4664 | }; | |
3281af81 PC |
4665 | /* MPUIR is specific to PMSA V6+ */ |
4666 | ARMCPRegInfo id_mpuir_reginfo = { | |
4667 | .name = "MPUIR", | |
4668 | .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 4, | |
4669 | .access = PL1_R, .type = ARM_CP_CONST, | |
4670 | .resetvalue = cpu->pmsav7_dregion << 8 | |
4671 | }; | |
7884849c PM |
4672 | ARMCPRegInfo crn0_wi_reginfo = { |
4673 | .name = "CRN0_WI", .cp = 15, .crn = 0, .crm = CP_ANY, | |
4674 | .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_W, | |
4675 | .type = ARM_CP_NOP | ARM_CP_OVERRIDE | |
4676 | }; | |
4677 | if (arm_feature(env, ARM_FEATURE_OMAPCP) || | |
4678 | arm_feature(env, ARM_FEATURE_STRONGARM)) { | |
4679 | ARMCPRegInfo *r; | |
4680 | /* Register the blanket "writes ignored" value first to cover the | |
a703eda1 PC |
4681 | * whole space. Then update the specific ID registers to allow write |
4682 | * access, so that they ignore writes rather than causing them to | |
4683 | * UNDEF. | |
7884849c PM |
4684 | */ |
4685 | define_one_arm_cp_reg(cpu, &crn0_wi_reginfo); | |
00a29f3d PM |
4686 | for (r = id_pre_v8_midr_cp_reginfo; |
4687 | r->type != ARM_CP_SENTINEL; r++) { | |
4688 | r->access = PL1_RW; | |
4689 | } | |
7884849c PM |
4690 | for (r = id_cp_reginfo; r->type != ARM_CP_SENTINEL; r++) { |
4691 | r->access = PL1_RW; | |
7884849c | 4692 | } |
8085ce63 | 4693 | id_tlbtr_reginfo.access = PL1_RW; |
3281af81 | 4694 | id_tlbtr_reginfo.access = PL1_RW; |
7884849c | 4695 | } |
00a29f3d PM |
4696 | if (arm_feature(env, ARM_FEATURE_V8)) { |
4697 | define_arm_cp_regs(cpu, id_v8_midr_cp_reginfo); | |
4698 | } else { | |
4699 | define_arm_cp_regs(cpu, id_pre_v8_midr_cp_reginfo); | |
4700 | } | |
a703eda1 | 4701 | define_arm_cp_regs(cpu, id_cp_reginfo); |
8085ce63 PC |
4702 | if (!arm_feature(env, ARM_FEATURE_MPU)) { |
4703 | define_one_arm_cp_reg(cpu, &id_tlbtr_reginfo); | |
3281af81 PC |
4704 | } else if (arm_feature(env, ARM_FEATURE_V7)) { |
4705 | define_one_arm_cp_reg(cpu, &id_mpuir_reginfo); | |
8085ce63 | 4706 | } |
7884849c PM |
4707 | } |
4708 | ||
97ce8d61 PC |
4709 | if (arm_feature(env, ARM_FEATURE_MPIDR)) { |
4710 | define_arm_cp_regs(cpu, mpidr_cp_reginfo); | |
4711 | } | |
4712 | ||
2771db27 | 4713 | if (arm_feature(env, ARM_FEATURE_AUXCR)) { |
834a6c69 PM |
4714 | ARMCPRegInfo auxcr_reginfo[] = { |
4715 | { .name = "ACTLR_EL1", .state = ARM_CP_STATE_BOTH, | |
4716 | .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 1, | |
4717 | .access = PL1_RW, .type = ARM_CP_CONST, | |
4718 | .resetvalue = cpu->reset_auxcr }, | |
4719 | { .name = "ACTLR_EL2", .state = ARM_CP_STATE_BOTH, | |
4720 | .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 0, .opc2 = 1, | |
4721 | .access = PL2_RW, .type = ARM_CP_CONST, | |
4722 | .resetvalue = 0 }, | |
4723 | { .name = "ACTLR_EL3", .state = ARM_CP_STATE_AA64, | |
4724 | .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 0, .opc2 = 1, | |
4725 | .access = PL3_RW, .type = ARM_CP_CONST, | |
4726 | .resetvalue = 0 }, | |
4727 | REGINFO_SENTINEL | |
2771db27 | 4728 | }; |
834a6c69 | 4729 | define_arm_cp_regs(cpu, auxcr_reginfo); |
2771db27 PM |
4730 | } |
4731 | ||
d8ba780b | 4732 | if (arm_feature(env, ARM_FEATURE_CBAR)) { |
f318cec6 PM |
4733 | if (arm_feature(env, ARM_FEATURE_AARCH64)) { |
4734 | /* 32 bit view is [31:18] 0...0 [43:32]. */ | |
4735 | uint32_t cbar32 = (extract64(cpu->reset_cbar, 18, 14) << 18) | |
4736 | | extract64(cpu->reset_cbar, 32, 12); | |
4737 | ARMCPRegInfo cbar_reginfo[] = { | |
4738 | { .name = "CBAR", | |
4739 | .type = ARM_CP_CONST, | |
4740 | .cp = 15, .crn = 15, .crm = 0, .opc1 = 4, .opc2 = 0, | |
4741 | .access = PL1_R, .resetvalue = cpu->reset_cbar }, | |
4742 | { .name = "CBAR_EL1", .state = ARM_CP_STATE_AA64, | |
4743 | .type = ARM_CP_CONST, | |
4744 | .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 3, .opc2 = 0, | |
4745 | .access = PL1_R, .resetvalue = cbar32 }, | |
4746 | REGINFO_SENTINEL | |
4747 | }; | |
4748 | /* We don't implement a r/w 64 bit CBAR currently */ | |
4749 | assert(arm_feature(env, ARM_FEATURE_CBAR_RO)); | |
4750 | define_arm_cp_regs(cpu, cbar_reginfo); | |
4751 | } else { | |
4752 | ARMCPRegInfo cbar = { | |
4753 | .name = "CBAR", | |
4754 | .cp = 15, .crn = 15, .crm = 0, .opc1 = 4, .opc2 = 0, | |
4755 | .access = PL1_R|PL3_W, .resetvalue = cpu->reset_cbar, | |
4756 | .fieldoffset = offsetof(CPUARMState, | |
4757 | cp15.c15_config_base_address) | |
4758 | }; | |
4759 | if (arm_feature(env, ARM_FEATURE_CBAR_RO)) { | |
4760 | cbar.access = PL1_R; | |
4761 | cbar.fieldoffset = 0; | |
4762 | cbar.type = ARM_CP_CONST; | |
4763 | } | |
4764 | define_one_arm_cp_reg(cpu, &cbar); | |
4765 | } | |
d8ba780b PC |
4766 | } |
4767 | ||
2771db27 PM |
4768 | /* Generic registers whose values depend on the implementation */ |
4769 | { | |
4770 | ARMCPRegInfo sctlr = { | |
5ebafdf3 | 4771 | .name = "SCTLR", .state = ARM_CP_STATE_BOTH, |
137feaa9 FA |
4772 | .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 0, |
4773 | .access = PL1_RW, | |
4774 | .bank_fieldoffsets = { offsetof(CPUARMState, cp15.sctlr_s), | |
4775 | offsetof(CPUARMState, cp15.sctlr_ns) }, | |
d4e6df63 PM |
4776 | .writefn = sctlr_write, .resetvalue = cpu->reset_sctlr, |
4777 | .raw_writefn = raw_write, | |
2771db27 PM |
4778 | }; |
4779 | if (arm_feature(env, ARM_FEATURE_XSCALE)) { | |
4780 | /* Normally we would always end the TB on an SCTLR write, but Linux | |
4781 | * arch/arm/mach-pxa/sleep.S expects two instructions following | |
4782 | * an MMU enable to execute from cache. Imitate this behaviour. | |
4783 | */ | |
4784 | sctlr.type |= ARM_CP_SUPPRESS_TB_END; | |
4785 | } | |
4786 | define_one_arm_cp_reg(cpu, &sctlr); | |
4787 | } | |
2ceb98c0 PM |
4788 | } |
4789 | ||
778c3a06 | 4790 | ARMCPU *cpu_arm_init(const char *cpu_model) |
40f137e1 | 4791 | { |
9262685b | 4792 | return ARM_CPU(cpu_generic_init(TYPE_ARM_CPU, cpu_model)); |
14969266 AF |
4793 | } |
4794 | ||
4795 | void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu) | |
4796 | { | |
22169d41 | 4797 | CPUState *cs = CPU(cpu); |
14969266 AF |
4798 | CPUARMState *env = &cpu->env; |
4799 | ||
6a669427 PM |
4800 | if (arm_feature(env, ARM_FEATURE_AARCH64)) { |
4801 | gdb_register_coprocessor(cs, aarch64_fpu_gdb_get_reg, | |
4802 | aarch64_fpu_gdb_set_reg, | |
4803 | 34, "aarch64-fpu.xml", 0); | |
4804 | } else if (arm_feature(env, ARM_FEATURE_NEON)) { | |
22169d41 | 4805 | gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg, |
56aebc89 PB |
4806 | 51, "arm-neon.xml", 0); |
4807 | } else if (arm_feature(env, ARM_FEATURE_VFP3)) { | |
22169d41 | 4808 | gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg, |
56aebc89 PB |
4809 | 35, "arm-vfp3.xml", 0); |
4810 | } else if (arm_feature(env, ARM_FEATURE_VFP)) { | |
22169d41 | 4811 | gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg, |
56aebc89 PB |
4812 | 19, "arm-vfp.xml", 0); |
4813 | } | |
40f137e1 PB |
4814 | } |
4815 | ||
777dc784 PM |
4816 | /* Sort alphabetically by type name, except for "any". */ |
4817 | static gint arm_cpu_list_compare(gconstpointer a, gconstpointer b) | |
5adb4839 | 4818 | { |
777dc784 PM |
4819 | ObjectClass *class_a = (ObjectClass *)a; |
4820 | ObjectClass *class_b = (ObjectClass *)b; | |
4821 | const char *name_a, *name_b; | |
5adb4839 | 4822 | |
777dc784 PM |
4823 | name_a = object_class_get_name(class_a); |
4824 | name_b = object_class_get_name(class_b); | |
51492fd1 | 4825 | if (strcmp(name_a, "any-" TYPE_ARM_CPU) == 0) { |
777dc784 | 4826 | return 1; |
51492fd1 | 4827 | } else if (strcmp(name_b, "any-" TYPE_ARM_CPU) == 0) { |
777dc784 PM |
4828 | return -1; |
4829 | } else { | |
4830 | return strcmp(name_a, name_b); | |
5adb4839 PB |
4831 | } |
4832 | } | |
4833 | ||
777dc784 | 4834 | static void arm_cpu_list_entry(gpointer data, gpointer user_data) |
40f137e1 | 4835 | { |
777dc784 | 4836 | ObjectClass *oc = data; |
92a31361 | 4837 | CPUListState *s = user_data; |
51492fd1 AF |
4838 | const char *typename; |
4839 | char *name; | |
3371d272 | 4840 | |
51492fd1 AF |
4841 | typename = object_class_get_name(oc); |
4842 | name = g_strndup(typename, strlen(typename) - strlen("-" TYPE_ARM_CPU)); | |
777dc784 | 4843 | (*s->cpu_fprintf)(s->file, " %s\n", |
51492fd1 AF |
4844 | name); |
4845 | g_free(name); | |
777dc784 PM |
4846 | } |
4847 | ||
4848 | void arm_cpu_list(FILE *f, fprintf_function cpu_fprintf) | |
4849 | { | |
92a31361 | 4850 | CPUListState s = { |
777dc784 PM |
4851 | .file = f, |
4852 | .cpu_fprintf = cpu_fprintf, | |
4853 | }; | |
4854 | GSList *list; | |
4855 | ||
4856 | list = object_class_get_list(TYPE_ARM_CPU, false); | |
4857 | list = g_slist_sort(list, arm_cpu_list_compare); | |
4858 | (*cpu_fprintf)(f, "Available CPUs:\n"); | |
4859 | g_slist_foreach(list, arm_cpu_list_entry, &s); | |
4860 | g_slist_free(list); | |
a96c0514 PM |
4861 | #ifdef CONFIG_KVM |
4862 | /* The 'host' CPU type is dynamically registered only if KVM is | |
4863 | * enabled, so we have to special-case it here: | |
4864 | */ | |
4865 | (*cpu_fprintf)(f, " host (only available in KVM mode)\n"); | |
4866 | #endif | |
40f137e1 PB |
4867 | } |
4868 | ||
78027bb6 CR |
4869 | static void arm_cpu_add_definition(gpointer data, gpointer user_data) |
4870 | { | |
4871 | ObjectClass *oc = data; | |
4872 | CpuDefinitionInfoList **cpu_list = user_data; | |
4873 | CpuDefinitionInfoList *entry; | |
4874 | CpuDefinitionInfo *info; | |
4875 | const char *typename; | |
4876 | ||
4877 | typename = object_class_get_name(oc); | |
4878 | info = g_malloc0(sizeof(*info)); | |
4879 | info->name = g_strndup(typename, | |
4880 | strlen(typename) - strlen("-" TYPE_ARM_CPU)); | |
4881 | ||
4882 | entry = g_malloc0(sizeof(*entry)); | |
4883 | entry->value = info; | |
4884 | entry->next = *cpu_list; | |
4885 | *cpu_list = entry; | |
4886 | } | |
4887 | ||
4888 | CpuDefinitionInfoList *arch_query_cpu_definitions(Error **errp) | |
4889 | { | |
4890 | CpuDefinitionInfoList *cpu_list = NULL; | |
4891 | GSList *list; | |
4892 | ||
4893 | list = object_class_get_list(TYPE_ARM_CPU, false); | |
4894 | g_slist_foreach(list, arm_cpu_add_definition, &cpu_list); | |
4895 | g_slist_free(list); | |
4896 | ||
4897 | return cpu_list; | |
4898 | } | |
4899 | ||
6e6efd61 | 4900 | static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r, |
51a79b03 | 4901 | void *opaque, int state, int secstate, |
f5a0a5a5 | 4902 | int crm, int opc1, int opc2) |
6e6efd61 PM |
4903 | { |
4904 | /* Private utility function for define_one_arm_cp_reg_with_opaque(): | |
4905 | * add a single reginfo struct to the hash table. | |
4906 | */ | |
4907 | uint32_t *key = g_new(uint32_t, 1); | |
4908 | ARMCPRegInfo *r2 = g_memdup(r, sizeof(ARMCPRegInfo)); | |
4909 | int is64 = (r->type & ARM_CP_64BIT) ? 1 : 0; | |
3f3c82a5 FA |
4910 | int ns = (secstate & ARM_CP_SECSTATE_NS) ? 1 : 0; |
4911 | ||
4912 | /* Reset the secure state to the specific incoming state. This is | |
4913 | * necessary as the register may have been defined with both states. | |
4914 | */ | |
4915 | r2->secure = secstate; | |
4916 | ||
4917 | if (r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1]) { | |
4918 | /* Register is banked (using both entries in array). | |
4919 | * Overwriting fieldoffset as the array is only used to define | |
4920 | * banked registers but later only fieldoffset is used. | |
f5a0a5a5 | 4921 | */ |
3f3c82a5 FA |
4922 | r2->fieldoffset = r->bank_fieldoffsets[ns]; |
4923 | } | |
4924 | ||
4925 | if (state == ARM_CP_STATE_AA32) { | |
4926 | if (r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1]) { | |
4927 | /* If the register is banked then we don't need to migrate or | |
4928 | * reset the 32-bit instance in certain cases: | |
4929 | * | |
4930 | * 1) If the register has both 32-bit and 64-bit instances then we | |
4931 | * can count on the 64-bit instance taking care of the | |
4932 | * non-secure bank. | |
4933 | * 2) If ARMv8 is enabled then we can count on a 64-bit version | |
4934 | * taking care of the secure bank. This requires that separate | |
4935 | * 32 and 64-bit definitions are provided. | |
4936 | */ | |
4937 | if ((r->state == ARM_CP_STATE_BOTH && ns) || | |
4938 | (arm_feature(&cpu->env, ARM_FEATURE_V8) && !ns)) { | |
7a0e58fa | 4939 | r2->type |= ARM_CP_ALIAS; |
3f3c82a5 FA |
4940 | } |
4941 | } else if ((secstate != r->secure) && !ns) { | |
4942 | /* The register is not banked so we only want to allow migration of | |
4943 | * the non-secure instance. | |
4944 | */ | |
7a0e58fa | 4945 | r2->type |= ARM_CP_ALIAS; |
58a1d8ce | 4946 | } |
3f3c82a5 FA |
4947 | |
4948 | if (r->state == ARM_CP_STATE_BOTH) { | |
4949 | /* We assume it is a cp15 register if the .cp field is left unset. | |
4950 | */ | |
4951 | if (r2->cp == 0) { | |
4952 | r2->cp = 15; | |
4953 | } | |
4954 | ||
f5a0a5a5 | 4955 | #ifdef HOST_WORDS_BIGENDIAN |
3f3c82a5 FA |
4956 | if (r2->fieldoffset) { |
4957 | r2->fieldoffset += sizeof(uint32_t); | |
4958 | } | |
f5a0a5a5 | 4959 | #endif |
3f3c82a5 | 4960 | } |
f5a0a5a5 PM |
4961 | } |
4962 | if (state == ARM_CP_STATE_AA64) { | |
4963 | /* To allow abbreviation of ARMCPRegInfo | |
4964 | * definitions, we treat cp == 0 as equivalent to | |
4965 | * the value for "standard guest-visible sysreg". | |
58a1d8ce PM |
4966 | * STATE_BOTH definitions are also always "standard |
4967 | * sysreg" in their AArch64 view (the .cp value may | |
4968 | * be non-zero for the benefit of the AArch32 view). | |
f5a0a5a5 | 4969 | */ |
58a1d8ce | 4970 | if (r->cp == 0 || r->state == ARM_CP_STATE_BOTH) { |
f5a0a5a5 PM |
4971 | r2->cp = CP_REG_ARM64_SYSREG_CP; |
4972 | } | |
4973 | *key = ENCODE_AA64_CP_REG(r2->cp, r2->crn, crm, | |
4974 | r2->opc0, opc1, opc2); | |
4975 | } else { | |
51a79b03 | 4976 | *key = ENCODE_CP_REG(r2->cp, is64, ns, r2->crn, crm, opc1, opc2); |
f5a0a5a5 | 4977 | } |
6e6efd61 PM |
4978 | if (opaque) { |
4979 | r2->opaque = opaque; | |
4980 | } | |
67ed771d PM |
4981 | /* reginfo passed to helpers is correct for the actual access, |
4982 | * and is never ARM_CP_STATE_BOTH: | |
4983 | */ | |
4984 | r2->state = state; | |
6e6efd61 PM |
4985 | /* Make sure reginfo passed to helpers for wildcarded regs |
4986 | * has the correct crm/opc1/opc2 for this reg, not CP_ANY: | |
4987 | */ | |
4988 | r2->crm = crm; | |
4989 | r2->opc1 = opc1; | |
4990 | r2->opc2 = opc2; | |
4991 | /* By convention, for wildcarded registers only the first | |
4992 | * entry is used for migration; the others are marked as | |
7a0e58fa | 4993 | * ALIAS so we don't try to transfer the register |
6e6efd61 | 4994 | * multiple times. Special registers (ie NOP/WFI) are |
7a0e58fa | 4995 | * never migratable and not even raw-accessible. |
6e6efd61 | 4996 | */ |
7a0e58fa PM |
4997 | if ((r->type & ARM_CP_SPECIAL)) { |
4998 | r2->type |= ARM_CP_NO_RAW; | |
4999 | } | |
5000 | if (((r->crm == CP_ANY) && crm != 0) || | |
6e6efd61 PM |
5001 | ((r->opc1 == CP_ANY) && opc1 != 0) || |
5002 | ((r->opc2 == CP_ANY) && opc2 != 0)) { | |
7a0e58fa | 5003 | r2->type |= ARM_CP_ALIAS; |
6e6efd61 PM |
5004 | } |
5005 | ||
375421cc PM |
5006 | /* Check that raw accesses are either forbidden or handled. Note that |
5007 | * we can't assert this earlier because the setup of fieldoffset for | |
5008 | * banked registers has to be done first. | |
5009 | */ | |
5010 | if (!(r2->type & ARM_CP_NO_RAW)) { | |
5011 | assert(!raw_accessors_invalid(r2)); | |
5012 | } | |
5013 | ||
6e6efd61 PM |
5014 | /* Overriding of an existing definition must be explicitly |
5015 | * requested. | |
5016 | */ | |
5017 | if (!(r->type & ARM_CP_OVERRIDE)) { | |
5018 | ARMCPRegInfo *oldreg; | |
5019 | oldreg = g_hash_table_lookup(cpu->cp_regs, key); | |
5020 | if (oldreg && !(oldreg->type & ARM_CP_OVERRIDE)) { | |
5021 | fprintf(stderr, "Register redefined: cp=%d %d bit " | |
5022 | "crn=%d crm=%d opc1=%d opc2=%d, " | |
5023 | "was %s, now %s\n", r2->cp, 32 + 32 * is64, | |
5024 | r2->crn, r2->crm, r2->opc1, r2->opc2, | |
5025 | oldreg->name, r2->name); | |
5026 | g_assert_not_reached(); | |
5027 | } | |
5028 | } | |
5029 | g_hash_table_insert(cpu->cp_regs, key, r2); | |
5030 | } | |
5031 | ||
5032 | ||
4b6a83fb PM |
5033 | void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu, |
5034 | const ARMCPRegInfo *r, void *opaque) | |
5035 | { | |
5036 | /* Define implementations of coprocessor registers. | |
5037 | * We store these in a hashtable because typically | |
5038 | * there are less than 150 registers in a space which | |
5039 | * is 16*16*16*8*8 = 262144 in size. | |
5040 | * Wildcarding is supported for the crm, opc1 and opc2 fields. | |
5041 | * If a register is defined twice then the second definition is | |
5042 | * used, so this can be used to define some generic registers and | |
5043 | * then override them with implementation specific variations. | |
5044 | * At least one of the original and the second definition should | |
5045 | * include ARM_CP_OVERRIDE in its type bits -- this is just a guard | |
5046 | * against accidental use. | |
f5a0a5a5 PM |
5047 | * |
5048 | * The state field defines whether the register is to be | |
5049 | * visible in the AArch32 or AArch64 execution state. If the | |
5050 | * state is set to ARM_CP_STATE_BOTH then we synthesise a | |
5051 | * reginfo structure for the AArch32 view, which sees the lower | |
5052 | * 32 bits of the 64 bit register. | |
5053 | * | |
5054 | * Only registers visible in AArch64 may set r->opc0; opc0 cannot | |
5055 | * be wildcarded. AArch64 registers are always considered to be 64 | |
5056 | * bits; the ARM_CP_64BIT* flag applies only to the AArch32 view of | |
5057 | * the register, if any. | |
4b6a83fb | 5058 | */ |
f5a0a5a5 | 5059 | int crm, opc1, opc2, state; |
4b6a83fb PM |
5060 | int crmmin = (r->crm == CP_ANY) ? 0 : r->crm; |
5061 | int crmmax = (r->crm == CP_ANY) ? 15 : r->crm; | |
5062 | int opc1min = (r->opc1 == CP_ANY) ? 0 : r->opc1; | |
5063 | int opc1max = (r->opc1 == CP_ANY) ? 7 : r->opc1; | |
5064 | int opc2min = (r->opc2 == CP_ANY) ? 0 : r->opc2; | |
5065 | int opc2max = (r->opc2 == CP_ANY) ? 7 : r->opc2; | |
5066 | /* 64 bit registers have only CRm and Opc1 fields */ | |
5067 | assert(!((r->type & ARM_CP_64BIT) && (r->opc2 || r->crn))); | |
f5a0a5a5 PM |
5068 | /* op0 only exists in the AArch64 encodings */ |
5069 | assert((r->state != ARM_CP_STATE_AA32) || (r->opc0 == 0)); | |
5070 | /* AArch64 regs are all 64 bit so ARM_CP_64BIT is meaningless */ | |
5071 | assert((r->state != ARM_CP_STATE_AA64) || !(r->type & ARM_CP_64BIT)); | |
5072 | /* The AArch64 pseudocode CheckSystemAccess() specifies that op1 | |
5073 | * encodes a minimum access level for the register. We roll this | |
5074 | * runtime check into our general permission check code, so check | |
5075 | * here that the reginfo's specified permissions are strict enough | |
5076 | * to encompass the generic architectural permission check. | |
5077 | */ | |
5078 | if (r->state != ARM_CP_STATE_AA32) { | |
5079 | int mask = 0; | |
5080 | switch (r->opc1) { | |
5081 | case 0: case 1: case 2: | |
5082 | /* min_EL EL1 */ | |
5083 | mask = PL1_RW; | |
5084 | break; | |
5085 | case 3: | |
5086 | /* min_EL EL0 */ | |
5087 | mask = PL0_RW; | |
5088 | break; | |
5089 | case 4: | |
5090 | /* min_EL EL2 */ | |
5091 | mask = PL2_RW; | |
5092 | break; | |
5093 | case 5: | |
5094 | /* unallocated encoding, so not possible */ | |
5095 | assert(false); | |
5096 | break; | |
5097 | case 6: | |
5098 | /* min_EL EL3 */ | |
5099 | mask = PL3_RW; | |
5100 | break; | |
5101 | case 7: | |
5102 | /* min_EL EL1, secure mode only (we don't check the latter) */ | |
5103 | mask = PL1_RW; | |
5104 | break; | |
5105 | default: | |
5106 | /* broken reginfo with out-of-range opc1 */ | |
5107 | assert(false); | |
5108 | break; | |
5109 | } | |
5110 | /* assert our permissions are not too lax (stricter is fine) */ | |
5111 | assert((r->access & ~mask) == 0); | |
5112 | } | |
5113 | ||
4b6a83fb PM |
5114 | /* Check that the register definition has enough info to handle |
5115 | * reads and writes if they are permitted. | |
5116 | */ | |
5117 | if (!(r->type & (ARM_CP_SPECIAL|ARM_CP_CONST))) { | |
5118 | if (r->access & PL3_R) { | |
3f3c82a5 FA |
5119 | assert((r->fieldoffset || |
5120 | (r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1])) || | |
5121 | r->readfn); | |
4b6a83fb PM |
5122 | } |
5123 | if (r->access & PL3_W) { | |
3f3c82a5 FA |
5124 | assert((r->fieldoffset || |
5125 | (r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1])) || | |
5126 | r->writefn); | |
4b6a83fb PM |
5127 | } |
5128 | } | |
5129 | /* Bad type field probably means missing sentinel at end of reg list */ | |
5130 | assert(cptype_valid(r->type)); | |
5131 | for (crm = crmmin; crm <= crmmax; crm++) { | |
5132 | for (opc1 = opc1min; opc1 <= opc1max; opc1++) { | |
5133 | for (opc2 = opc2min; opc2 <= opc2max; opc2++) { | |
f5a0a5a5 PM |
5134 | for (state = ARM_CP_STATE_AA32; |
5135 | state <= ARM_CP_STATE_AA64; state++) { | |
5136 | if (r->state != state && r->state != ARM_CP_STATE_BOTH) { | |
5137 | continue; | |
5138 | } | |
3f3c82a5 FA |
5139 | if (state == ARM_CP_STATE_AA32) { |
5140 | /* Under AArch32 CP registers can be common | |
5141 | * (same for secure and non-secure world) or banked. | |
5142 | */ | |
5143 | switch (r->secure) { | |
5144 | case ARM_CP_SECSTATE_S: | |
5145 | case ARM_CP_SECSTATE_NS: | |
5146 | add_cpreg_to_hashtable(cpu, r, opaque, state, | |
5147 | r->secure, crm, opc1, opc2); | |
5148 | break; | |
5149 | default: | |
5150 | add_cpreg_to_hashtable(cpu, r, opaque, state, | |
5151 | ARM_CP_SECSTATE_S, | |
5152 | crm, opc1, opc2); | |
5153 | add_cpreg_to_hashtable(cpu, r, opaque, state, | |
5154 | ARM_CP_SECSTATE_NS, | |
5155 | crm, opc1, opc2); | |
5156 | break; | |
5157 | } | |
5158 | } else { | |
5159 | /* AArch64 registers get mapped to non-secure instance | |
5160 | * of AArch32 */ | |
5161 | add_cpreg_to_hashtable(cpu, r, opaque, state, | |
5162 | ARM_CP_SECSTATE_NS, | |
5163 | crm, opc1, opc2); | |
5164 | } | |
f5a0a5a5 | 5165 | } |
4b6a83fb PM |
5166 | } |
5167 | } | |
5168 | } | |
5169 | } | |
5170 | ||
5171 | void define_arm_cp_regs_with_opaque(ARMCPU *cpu, | |
5172 | const ARMCPRegInfo *regs, void *opaque) | |
5173 | { | |
5174 | /* Define a whole list of registers */ | |
5175 | const ARMCPRegInfo *r; | |
5176 | for (r = regs; r->type != ARM_CP_SENTINEL; r++) { | |
5177 | define_one_arm_cp_reg_with_opaque(cpu, r, opaque); | |
5178 | } | |
5179 | } | |
5180 | ||
60322b39 | 5181 | const ARMCPRegInfo *get_arm_cp_reginfo(GHashTable *cpregs, uint32_t encoded_cp) |
4b6a83fb | 5182 | { |
60322b39 | 5183 | return g_hash_table_lookup(cpregs, &encoded_cp); |
4b6a83fb PM |
5184 | } |
5185 | ||
c4241c7d PM |
5186 | void arm_cp_write_ignore(CPUARMState *env, const ARMCPRegInfo *ri, |
5187 | uint64_t value) | |
4b6a83fb PM |
5188 | { |
5189 | /* Helper coprocessor write function for write-ignore registers */ | |
4b6a83fb PM |
5190 | } |
5191 | ||
c4241c7d | 5192 | uint64_t arm_cp_read_zero(CPUARMState *env, const ARMCPRegInfo *ri) |
4b6a83fb PM |
5193 | { |
5194 | /* Helper coprocessor write function for read-as-zero registers */ | |
4b6a83fb PM |
5195 | return 0; |
5196 | } | |
5197 | ||
f5a0a5a5 PM |
5198 | void arm_cp_reset_ignore(CPUARMState *env, const ARMCPRegInfo *opaque) |
5199 | { | |
5200 | /* Helper coprocessor reset function for do-nothing-on-reset registers */ | |
5201 | } | |
5202 | ||
0ecb72a5 | 5203 | static int bad_mode_switch(CPUARMState *env, int mode) |
37064a8b PM |
5204 | { |
5205 | /* Return true if it is not valid for us to switch to | |
5206 | * this CPU mode (ie all the UNPREDICTABLE cases in | |
5207 | * the ARM ARM CPSRWriteByInstr pseudocode). | |
5208 | */ | |
5209 | switch (mode) { | |
5210 | case ARM_CPU_MODE_USR: | |
5211 | case ARM_CPU_MODE_SYS: | |
5212 | case ARM_CPU_MODE_SVC: | |
5213 | case ARM_CPU_MODE_ABT: | |
5214 | case ARM_CPU_MODE_UND: | |
5215 | case ARM_CPU_MODE_IRQ: | |
5216 | case ARM_CPU_MODE_FIQ: | |
5217 | return 0; | |
027fc527 SF |
5218 | case ARM_CPU_MODE_MON: |
5219 | return !arm_is_secure(env); | |
37064a8b PM |
5220 | default: |
5221 | return 1; | |
5222 | } | |
5223 | } | |
5224 | ||
2f4a40e5 AZ |
5225 | uint32_t cpsr_read(CPUARMState *env) |
5226 | { | |
5227 | int ZF; | |
6fbe23d5 PB |
5228 | ZF = (env->ZF == 0); |
5229 | return env->uncached_cpsr | (env->NF & 0x80000000) | (ZF << 30) | | |
2f4a40e5 AZ |
5230 | (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27) |
5231 | | (env->thumb << 5) | ((env->condexec_bits & 3) << 25) | |
5232 | | ((env->condexec_bits & 0xfc) << 8) | |
af519934 | 5233 | | (env->GE << 16) | (env->daif & CPSR_AIF); |
2f4a40e5 AZ |
5234 | } |
5235 | ||
50866ba5 PM |
5236 | void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask, |
5237 | CPSRWriteType write_type) | |
2f4a40e5 | 5238 | { |
6e8801f9 FA |
5239 | uint32_t changed_daif; |
5240 | ||
2f4a40e5 | 5241 | if (mask & CPSR_NZCV) { |
6fbe23d5 PB |
5242 | env->ZF = (~val) & CPSR_Z; |
5243 | env->NF = val; | |
2f4a40e5 AZ |
5244 | env->CF = (val >> 29) & 1; |
5245 | env->VF = (val << 3) & 0x80000000; | |
5246 | } | |
5247 | if (mask & CPSR_Q) | |
5248 | env->QF = ((val & CPSR_Q) != 0); | |
5249 | if (mask & CPSR_T) | |
5250 | env->thumb = ((val & CPSR_T) != 0); | |
5251 | if (mask & CPSR_IT_0_1) { | |
5252 | env->condexec_bits &= ~3; | |
5253 | env->condexec_bits |= (val >> 25) & 3; | |
5254 | } | |
5255 | if (mask & CPSR_IT_2_7) { | |
5256 | env->condexec_bits &= 3; | |
5257 | env->condexec_bits |= (val >> 8) & 0xfc; | |
5258 | } | |
5259 | if (mask & CPSR_GE) { | |
5260 | env->GE = (val >> 16) & 0xf; | |
5261 | } | |
5262 | ||
6e8801f9 FA |
5263 | /* In a V7 implementation that includes the security extensions but does |
5264 | * not include Virtualization Extensions the SCR.FW and SCR.AW bits control | |
5265 | * whether non-secure software is allowed to change the CPSR_F and CPSR_A | |
5266 | * bits respectively. | |
5267 | * | |
5268 | * In a V8 implementation, it is permitted for privileged software to | |
5269 | * change the CPSR A/F bits regardless of the SCR.AW/FW bits. | |
5270 | */ | |
f8c88bbc | 5271 | if (write_type != CPSRWriteRaw && !arm_feature(env, ARM_FEATURE_V8) && |
6e8801f9 FA |
5272 | arm_feature(env, ARM_FEATURE_EL3) && |
5273 | !arm_feature(env, ARM_FEATURE_EL2) && | |
5274 | !arm_is_secure(env)) { | |
5275 | ||
5276 | changed_daif = (env->daif ^ val) & mask; | |
5277 | ||
5278 | if (changed_daif & CPSR_A) { | |
5279 | /* Check to see if we are allowed to change the masking of async | |
5280 | * abort exceptions from a non-secure state. | |
5281 | */ | |
5282 | if (!(env->cp15.scr_el3 & SCR_AW)) { | |
5283 | qemu_log_mask(LOG_GUEST_ERROR, | |
5284 | "Ignoring attempt to switch CPSR_A flag from " | |
5285 | "non-secure world with SCR.AW bit clear\n"); | |
5286 | mask &= ~CPSR_A; | |
5287 | } | |
5288 | } | |
5289 | ||
5290 | if (changed_daif & CPSR_F) { | |
5291 | /* Check to see if we are allowed to change the masking of FIQ | |
5292 | * exceptions from a non-secure state. | |
5293 | */ | |
5294 | if (!(env->cp15.scr_el3 & SCR_FW)) { | |
5295 | qemu_log_mask(LOG_GUEST_ERROR, | |
5296 | "Ignoring attempt to switch CPSR_F flag from " | |
5297 | "non-secure world with SCR.FW bit clear\n"); | |
5298 | mask &= ~CPSR_F; | |
5299 | } | |
5300 | ||
5301 | /* Check whether non-maskable FIQ (NMFI) support is enabled. | |
5302 | * If this bit is set software is not allowed to mask | |
5303 | * FIQs, but is allowed to set CPSR_F to 0. | |
5304 | */ | |
5305 | if ((A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_NMFI) && | |
5306 | (val & CPSR_F)) { | |
5307 | qemu_log_mask(LOG_GUEST_ERROR, | |
5308 | "Ignoring attempt to enable CPSR_F flag " | |
5309 | "(non-maskable FIQ [NMFI] support enabled)\n"); | |
5310 | mask &= ~CPSR_F; | |
5311 | } | |
5312 | } | |
5313 | } | |
5314 | ||
4cc35614 PM |
5315 | env->daif &= ~(CPSR_AIF & mask); |
5316 | env->daif |= val & CPSR_AIF & mask; | |
5317 | ||
f8c88bbc | 5318 | if (write_type != CPSRWriteRaw && |
cb01d391 | 5319 | (env->uncached_cpsr & CPSR_M) != CPSR_USER && |
f8c88bbc | 5320 | ((env->uncached_cpsr ^ val) & mask & CPSR_M)) { |
37064a8b PM |
5321 | if (bad_mode_switch(env, val & CPSR_M)) { |
5322 | /* Attempt to switch to an invalid mode: this is UNPREDICTABLE. | |
5323 | * We choose to ignore the attempt and leave the CPSR M field | |
5324 | * untouched. | |
5325 | */ | |
5326 | mask &= ~CPSR_M; | |
5327 | } else { | |
5328 | switch_mode(env, val & CPSR_M); | |
5329 | } | |
2f4a40e5 AZ |
5330 | } |
5331 | mask &= ~CACHED_CPSR_BITS; | |
5332 | env->uncached_cpsr = (env->uncached_cpsr & ~mask) | (val & mask); | |
5333 | } | |
5334 | ||
b26eefb6 PB |
5335 | /* Sign/zero extend */ |
5336 | uint32_t HELPER(sxtb16)(uint32_t x) | |
5337 | { | |
5338 | uint32_t res; | |
5339 | res = (uint16_t)(int8_t)x; | |
5340 | res |= (uint32_t)(int8_t)(x >> 16) << 16; | |
5341 | return res; | |
5342 | } | |
5343 | ||
5344 | uint32_t HELPER(uxtb16)(uint32_t x) | |
5345 | { | |
5346 | uint32_t res; | |
5347 | res = (uint16_t)(uint8_t)x; | |
5348 | res |= (uint32_t)(uint8_t)(x >> 16) << 16; | |
5349 | return res; | |
5350 | } | |
5351 | ||
f51bbbfe PB |
5352 | uint32_t HELPER(clz)(uint32_t x) |
5353 | { | |
7bbcb0af | 5354 | return clz32(x); |
f51bbbfe PB |
5355 | } |
5356 | ||
3670669c PB |
5357 | int32_t HELPER(sdiv)(int32_t num, int32_t den) |
5358 | { | |
5359 | if (den == 0) | |
5360 | return 0; | |
686eeb93 AJ |
5361 | if (num == INT_MIN && den == -1) |
5362 | return INT_MIN; | |
3670669c PB |
5363 | return num / den; |
5364 | } | |
5365 | ||
5366 | uint32_t HELPER(udiv)(uint32_t num, uint32_t den) | |
5367 | { | |
5368 | if (den == 0) | |
5369 | return 0; | |
5370 | return num / den; | |
5371 | } | |
5372 | ||
5373 | uint32_t HELPER(rbit)(uint32_t x) | |
5374 | { | |
42fedbca | 5375 | return revbit32(x); |
3670669c PB |
5376 | } |
5377 | ||
5fafdf24 | 5378 | #if defined(CONFIG_USER_ONLY) |
b5ff1b31 | 5379 | |
9ee6e8bb | 5380 | /* These should probably raise undefined insn exceptions. */ |
0ecb72a5 | 5381 | void HELPER(v7m_msr)(CPUARMState *env, uint32_t reg, uint32_t val) |
9ee6e8bb | 5382 | { |
a47dddd7 AF |
5383 | ARMCPU *cpu = arm_env_get_cpu(env); |
5384 | ||
5385 | cpu_abort(CPU(cpu), "v7m_msr %d\n", reg); | |
9ee6e8bb PB |
5386 | } |
5387 | ||
0ecb72a5 | 5388 | uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg) |
9ee6e8bb | 5389 | { |
a47dddd7 AF |
5390 | ARMCPU *cpu = arm_env_get_cpu(env); |
5391 | ||
5392 | cpu_abort(CPU(cpu), "v7m_mrs %d\n", reg); | |
9ee6e8bb PB |
5393 | return 0; |
5394 | } | |
5395 | ||
0ecb72a5 | 5396 | void switch_mode(CPUARMState *env, int mode) |
b5ff1b31 | 5397 | { |
a47dddd7 AF |
5398 | ARMCPU *cpu = arm_env_get_cpu(env); |
5399 | ||
5400 | if (mode != ARM_CPU_MODE_USR) { | |
5401 | cpu_abort(CPU(cpu), "Tried to switch out of user mode\n"); | |
5402 | } | |
b5ff1b31 FB |
5403 | } |
5404 | ||
012a906b GB |
5405 | uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx, |
5406 | uint32_t cur_el, bool secure) | |
9e729b57 EI |
5407 | { |
5408 | return 1; | |
5409 | } | |
5410 | ||
ce02049d GB |
5411 | void aarch64_sync_64_to_32(CPUARMState *env) |
5412 | { | |
5413 | g_assert_not_reached(); | |
5414 | } | |
5415 | ||
b5ff1b31 FB |
5416 | #else |
5417 | ||
0ecb72a5 | 5418 | void switch_mode(CPUARMState *env, int mode) |
b5ff1b31 FB |
5419 | { |
5420 | int old_mode; | |
5421 | int i; | |
5422 | ||
5423 | old_mode = env->uncached_cpsr & CPSR_M; | |
5424 | if (mode == old_mode) | |
5425 | return; | |
5426 | ||
5427 | if (old_mode == ARM_CPU_MODE_FIQ) { | |
5428 | memcpy (env->fiq_regs, env->regs + 8, 5 * sizeof(uint32_t)); | |
8637c67f | 5429 | memcpy (env->regs + 8, env->usr_regs, 5 * sizeof(uint32_t)); |
b5ff1b31 FB |
5430 | } else if (mode == ARM_CPU_MODE_FIQ) { |
5431 | memcpy (env->usr_regs, env->regs + 8, 5 * sizeof(uint32_t)); | |
8637c67f | 5432 | memcpy (env->regs + 8, env->fiq_regs, 5 * sizeof(uint32_t)); |
b5ff1b31 FB |
5433 | } |
5434 | ||
f5206413 | 5435 | i = bank_number(old_mode); |
b5ff1b31 FB |
5436 | env->banked_r13[i] = env->regs[13]; |
5437 | env->banked_r14[i] = env->regs[14]; | |
5438 | env->banked_spsr[i] = env->spsr; | |
5439 | ||
f5206413 | 5440 | i = bank_number(mode); |
b5ff1b31 FB |
5441 | env->regs[13] = env->banked_r13[i]; |
5442 | env->regs[14] = env->banked_r14[i]; | |
5443 | env->spsr = env->banked_spsr[i]; | |
5444 | } | |
5445 | ||
0eeb17d6 GB |
5446 | /* Physical Interrupt Target EL Lookup Table |
5447 | * | |
5448 | * [ From ARM ARM section G1.13.4 (Table G1-15) ] | |
5449 | * | |
5450 | * The below multi-dimensional table is used for looking up the target | |
5451 | * exception level given numerous condition criteria. Specifically, the | |
5452 | * target EL is based on SCR and HCR routing controls as well as the | |
5453 | * currently executing EL and secure state. | |
5454 | * | |
5455 | * Dimensions: | |
5456 | * target_el_table[2][2][2][2][2][4] | |
5457 | * | | | | | +--- Current EL | |
5458 | * | | | | +------ Non-secure(0)/Secure(1) | |
5459 | * | | | +--------- HCR mask override | |
5460 | * | | +------------ SCR exec state control | |
5461 | * | +--------------- SCR mask override | |
5462 | * +------------------ 32-bit(0)/64-bit(1) EL3 | |
5463 | * | |
5464 | * The table values are as such: | |
5465 | * 0-3 = EL0-EL3 | |
5466 | * -1 = Cannot occur | |
5467 | * | |
5468 | * The ARM ARM target EL table includes entries indicating that an "exception | |
5469 | * is not taken". The two cases where this is applicable are: | |
5470 | * 1) An exception is taken from EL3 but the SCR does not have the exception | |
5471 | * routed to EL3. | |
5472 | * 2) An exception is taken from EL2 but the HCR does not have the exception | |
5473 | * routed to EL2. | |
5474 | * In these two cases, the below table contain a target of EL1. This value is | |
5475 | * returned as it is expected that the consumer of the table data will check | |
5476 | * for "target EL >= current EL" to ensure the exception is not taken. | |
5477 | * | |
5478 | * SCR HCR | |
5479 | * 64 EA AMO From | |
5480 | * BIT IRQ IMO Non-secure Secure | |
5481 | * EL3 FIQ RW FMO EL0 EL1 EL2 EL3 EL0 EL1 EL2 EL3 | |
5482 | */ | |
82c39f6a | 5483 | static const int8_t target_el_table[2][2][2][2][2][4] = { |
0eeb17d6 GB |
5484 | {{{{/* 0 0 0 0 */{ 1, 1, 2, -1 },{ 3, -1, -1, 3 },}, |
5485 | {/* 0 0 0 1 */{ 2, 2, 2, -1 },{ 3, -1, -1, 3 },},}, | |
5486 | {{/* 0 0 1 0 */{ 1, 1, 2, -1 },{ 3, -1, -1, 3 },}, | |
5487 | {/* 0 0 1 1 */{ 2, 2, 2, -1 },{ 3, -1, -1, 3 },},},}, | |
5488 | {{{/* 0 1 0 0 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },}, | |
5489 | {/* 0 1 0 1 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },},}, | |
5490 | {{/* 0 1 1 0 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },}, | |
5491 | {/* 0 1 1 1 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },},},},}, | |
5492 | {{{{/* 1 0 0 0 */{ 1, 1, 2, -1 },{ 1, 1, -1, 1 },}, | |
5493 | {/* 1 0 0 1 */{ 2, 2, 2, -1 },{ 1, 1, -1, 1 },},}, | |
5494 | {{/* 1 0 1 0 */{ 1, 1, 1, -1 },{ 1, 1, -1, 1 },}, | |
5495 | {/* 1 0 1 1 */{ 2, 2, 2, -1 },{ 1, 1, -1, 1 },},},}, | |
5496 | {{{/* 1 1 0 0 */{ 3, 3, 3, -1 },{ 3, 3, -1, 3 },}, | |
5497 | {/* 1 1 0 1 */{ 3, 3, 3, -1 },{ 3, 3, -1, 3 },},}, | |
5498 | {{/* 1 1 1 0 */{ 3, 3, 3, -1 },{ 3, 3, -1, 3 },}, | |
5499 | {/* 1 1 1 1 */{ 3, 3, 3, -1 },{ 3, 3, -1, 3 },},},},}, | |
5500 | }; | |
5501 | ||
5502 | /* | |
5503 | * Determine the target EL for physical exceptions | |
5504 | */ | |
012a906b GB |
5505 | uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx, |
5506 | uint32_t cur_el, bool secure) | |
0eeb17d6 GB |
5507 | { |
5508 | CPUARMState *env = cs->env_ptr; | |
2cde031f | 5509 | int rw; |
0eeb17d6 GB |
5510 | int scr; |
5511 | int hcr; | |
5512 | int target_el; | |
2cde031f SS |
5513 | /* Is the highest EL AArch64? */ |
5514 | int is64 = arm_feature(env, ARM_FEATURE_AARCH64); | |
5515 | ||
5516 | if (arm_feature(env, ARM_FEATURE_EL3)) { | |
5517 | rw = ((env->cp15.scr_el3 & SCR_RW) == SCR_RW); | |
5518 | } else { | |
5519 | /* Either EL2 is the highest EL (and so the EL2 register width | |
5520 | * is given by is64); or there is no EL2 or EL3, in which case | |
5521 | * the value of 'rw' does not affect the table lookup anyway. | |
5522 | */ | |
5523 | rw = is64; | |
5524 | } | |
0eeb17d6 GB |
5525 | |
5526 | switch (excp_idx) { | |
5527 | case EXCP_IRQ: | |
5528 | scr = ((env->cp15.scr_el3 & SCR_IRQ) == SCR_IRQ); | |
5529 | hcr = ((env->cp15.hcr_el2 & HCR_IMO) == HCR_IMO); | |
5530 | break; | |
5531 | case EXCP_FIQ: | |
5532 | scr = ((env->cp15.scr_el3 & SCR_FIQ) == SCR_FIQ); | |
5533 | hcr = ((env->cp15.hcr_el2 & HCR_FMO) == HCR_FMO); | |
5534 | break; | |
5535 | default: | |
5536 | scr = ((env->cp15.scr_el3 & SCR_EA) == SCR_EA); | |
5537 | hcr = ((env->cp15.hcr_el2 & HCR_AMO) == HCR_AMO); | |
5538 | break; | |
5539 | }; | |
5540 | ||
5541 | /* If HCR.TGE is set then HCR is treated as being 1 */ | |
5542 | hcr |= ((env->cp15.hcr_el2 & HCR_TGE) == HCR_TGE); | |
5543 | ||
5544 | /* Perform a table-lookup for the target EL given the current state */ | |
5545 | target_el = target_el_table[is64][scr][rw][hcr][secure][cur_el]; | |
5546 | ||
5547 | assert(target_el > 0); | |
5548 | ||
5549 | return target_el; | |
5550 | } | |
5551 | ||
9ee6e8bb PB |
5552 | static void v7m_push(CPUARMState *env, uint32_t val) |
5553 | { | |
70d74660 AF |
5554 | CPUState *cs = CPU(arm_env_get_cpu(env)); |
5555 | ||
9ee6e8bb | 5556 | env->regs[13] -= 4; |
ab1da857 | 5557 | stl_phys(cs->as, env->regs[13], val); |
9ee6e8bb PB |
5558 | } |
5559 | ||
5560 | static uint32_t v7m_pop(CPUARMState *env) | |
5561 | { | |
70d74660 | 5562 | CPUState *cs = CPU(arm_env_get_cpu(env)); |
9ee6e8bb | 5563 | uint32_t val; |
70d74660 | 5564 | |
fdfba1a2 | 5565 | val = ldl_phys(cs->as, env->regs[13]); |
9ee6e8bb PB |
5566 | env->regs[13] += 4; |
5567 | return val; | |
5568 | } | |
5569 | ||
5570 | /* Switch to V7M main or process stack pointer. */ | |
5571 | static void switch_v7m_sp(CPUARMState *env, int process) | |
5572 | { | |
5573 | uint32_t tmp; | |
5574 | if (env->v7m.current_sp != process) { | |
5575 | tmp = env->v7m.other_sp; | |
5576 | env->v7m.other_sp = env->regs[13]; | |
5577 | env->regs[13] = tmp; | |
5578 | env->v7m.current_sp = process; | |
5579 | } | |
5580 | } | |
5581 | ||
5582 | static void do_v7m_exception_exit(CPUARMState *env) | |
5583 | { | |
5584 | uint32_t type; | |
5585 | uint32_t xpsr; | |
5586 | ||
5587 | type = env->regs[15]; | |
5588 | if (env->v7m.exception != 0) | |
983fe826 | 5589 | armv7m_nvic_complete_irq(env->nvic, env->v7m.exception); |
9ee6e8bb PB |
5590 | |
5591 | /* Switch to the target stack. */ | |
5592 | switch_v7m_sp(env, (type & 4) != 0); | |
5593 | /* Pop registers. */ | |
5594 | env->regs[0] = v7m_pop(env); | |
5595 | env->regs[1] = v7m_pop(env); | |
5596 | env->regs[2] = v7m_pop(env); | |
5597 | env->regs[3] = v7m_pop(env); | |
5598 | env->regs[12] = v7m_pop(env); | |
5599 | env->regs[14] = v7m_pop(env); | |
5600 | env->regs[15] = v7m_pop(env); | |
fcf83ab1 PM |
5601 | if (env->regs[15] & 1) { |
5602 | qemu_log_mask(LOG_GUEST_ERROR, | |
5603 | "M profile return from interrupt with misaligned " | |
5604 | "PC is UNPREDICTABLE\n"); | |
5605 | /* Actual hardware seems to ignore the lsbit, and there are several | |
5606 | * RTOSes out there which incorrectly assume the r15 in the stack | |
5607 | * frame should be a Thumb-style "lsbit indicates ARM/Thumb" value. | |
5608 | */ | |
5609 | env->regs[15] &= ~1U; | |
5610 | } | |
9ee6e8bb PB |
5611 | xpsr = v7m_pop(env); |
5612 | xpsr_write(env, xpsr, 0xfffffdff); | |
5613 | /* Undo stack alignment. */ | |
5614 | if (xpsr & 0x200) | |
5615 | env->regs[13] |= 4; | |
5616 | /* ??? The exception return type specifies Thread/Handler mode. However | |
5617 | this is also implied by the xPSR value. Not sure what to do | |
5618 | if there is a mismatch. */ | |
5619 | /* ??? Likewise for mismatches between the CONTROL register and the stack | |
5620 | pointer. */ | |
5621 | } | |
5622 | ||
e6f010cc | 5623 | void arm_v7m_cpu_do_interrupt(CPUState *cs) |
9ee6e8bb | 5624 | { |
e6f010cc AF |
5625 | ARMCPU *cpu = ARM_CPU(cs); |
5626 | CPUARMState *env = &cpu->env; | |
9ee6e8bb PB |
5627 | uint32_t xpsr = xpsr_read(env); |
5628 | uint32_t lr; | |
5629 | uint32_t addr; | |
5630 | ||
27103424 | 5631 | arm_log_exception(cs->exception_index); |
3f1beaca | 5632 | |
9ee6e8bb PB |
5633 | lr = 0xfffffff1; |
5634 | if (env->v7m.current_sp) | |
5635 | lr |= 4; | |
5636 | if (env->v7m.exception == 0) | |
5637 | lr |= 8; | |
5638 | ||
5639 | /* For exceptions we just mark as pending on the NVIC, and let that | |
5640 | handle it. */ | |
5641 | /* TODO: Need to escalate if the current priority is higher than the | |
5642 | one we're raising. */ | |
27103424 | 5643 | switch (cs->exception_index) { |
9ee6e8bb | 5644 | case EXCP_UDEF: |
983fe826 | 5645 | armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE); |
9ee6e8bb PB |
5646 | return; |
5647 | case EXCP_SWI: | |
314e2296 | 5648 | /* The PC already points to the next instruction. */ |
983fe826 | 5649 | armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_SVC); |
9ee6e8bb PB |
5650 | return; |
5651 | case EXCP_PREFETCH_ABORT: | |
5652 | case EXCP_DATA_ABORT: | |
abf1172f PM |
5653 | /* TODO: if we implemented the MPU registers, this is where we |
5654 | * should set the MMFAR, etc from exception.fsr and exception.vaddress. | |
5655 | */ | |
983fe826 | 5656 | armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_MEM); |
9ee6e8bb PB |
5657 | return; |
5658 | case EXCP_BKPT: | |
cfe67cef | 5659 | if (semihosting_enabled()) { |
2ad207d4 | 5660 | int nr; |
d31dd73e | 5661 | nr = arm_lduw_code(env, env->regs[15], env->bswap_code) & 0xff; |
2ad207d4 PB |
5662 | if (nr == 0xab) { |
5663 | env->regs[15] += 2; | |
205ace55 CC |
5664 | qemu_log_mask(CPU_LOG_INT, |
5665 | "...handling as semihosting call 0x%x\n", | |
5666 | env->regs[0]); | |
2ad207d4 PB |
5667 | env->regs[0] = do_arm_semihosting(env); |
5668 | return; | |
5669 | } | |
5670 | } | |
983fe826 | 5671 | armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_DEBUG); |
9ee6e8bb PB |
5672 | return; |
5673 | case EXCP_IRQ: | |
983fe826 | 5674 | env->v7m.exception = armv7m_nvic_acknowledge_irq(env->nvic); |
9ee6e8bb PB |
5675 | break; |
5676 | case EXCP_EXCEPTION_EXIT: | |
5677 | do_v7m_exception_exit(env); | |
5678 | return; | |
5679 | default: | |
a47dddd7 | 5680 | cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index); |
9ee6e8bb PB |
5681 | return; /* Never happens. Keep compiler happy. */ |
5682 | } | |
5683 | ||
5684 | /* Align stack pointer. */ | |
5685 | /* ??? Should only do this if Configuration Control Register | |
5686 | STACKALIGN bit is set. */ | |
5687 | if (env->regs[13] & 4) { | |
ab19b0ec | 5688 | env->regs[13] -= 4; |
9ee6e8bb PB |
5689 | xpsr |= 0x200; |
5690 | } | |
6c95676b | 5691 | /* Switch to the handler mode. */ |
9ee6e8bb PB |
5692 | v7m_push(env, xpsr); |
5693 | v7m_push(env, env->regs[15]); | |
5694 | v7m_push(env, env->regs[14]); | |
5695 | v7m_push(env, env->regs[12]); | |
5696 | v7m_push(env, env->regs[3]); | |
5697 | v7m_push(env, env->regs[2]); | |
5698 | v7m_push(env, env->regs[1]); | |
5699 | v7m_push(env, env->regs[0]); | |
5700 | switch_v7m_sp(env, 0); | |
c98d174c PM |
5701 | /* Clear IT bits */ |
5702 | env->condexec_bits = 0; | |
9ee6e8bb | 5703 | env->regs[14] = lr; |
fdfba1a2 | 5704 | addr = ldl_phys(cs->as, env->v7m.vecbase + env->v7m.exception * 4); |
9ee6e8bb PB |
5705 | env->regs[15] = addr & 0xfffffffe; |
5706 | env->thumb = addr & 1; | |
5707 | } | |
5708 | ||
ce02049d GB |
5709 | /* Function used to synchronize QEMU's AArch64 register set with AArch32 |
5710 | * register set. This is necessary when switching between AArch32 and AArch64 | |
5711 | * execution state. | |
5712 | */ | |
5713 | void aarch64_sync_32_to_64(CPUARMState *env) | |
5714 | { | |
5715 | int i; | |
5716 | uint32_t mode = env->uncached_cpsr & CPSR_M; | |
5717 | ||
5718 | /* We can blanket copy R[0:7] to X[0:7] */ | |
5719 | for (i = 0; i < 8; i++) { | |
5720 | env->xregs[i] = env->regs[i]; | |
5721 | } | |
5722 | ||
5723 | /* Unless we are in FIQ mode, x8-x12 come from the user registers r8-r12. | |
5724 | * Otherwise, they come from the banked user regs. | |
5725 | */ | |
5726 | if (mode == ARM_CPU_MODE_FIQ) { | |
5727 | for (i = 8; i < 13; i++) { | |
5728 | env->xregs[i] = env->usr_regs[i - 8]; | |
5729 | } | |
5730 | } else { | |
5731 | for (i = 8; i < 13; i++) { | |
5732 | env->xregs[i] = env->regs[i]; | |
5733 | } | |
5734 | } | |
5735 | ||
5736 | /* Registers x13-x23 are the various mode SP and FP registers. Registers | |
5737 | * r13 and r14 are only copied if we are in that mode, otherwise we copy | |
5738 | * from the mode banked register. | |
5739 | */ | |
5740 | if (mode == ARM_CPU_MODE_USR || mode == ARM_CPU_MODE_SYS) { | |
5741 | env->xregs[13] = env->regs[13]; | |
5742 | env->xregs[14] = env->regs[14]; | |
5743 | } else { | |
5744 | env->xregs[13] = env->banked_r13[bank_number(ARM_CPU_MODE_USR)]; | |
5745 | /* HYP is an exception in that it is copied from r14 */ | |
5746 | if (mode == ARM_CPU_MODE_HYP) { | |
5747 | env->xregs[14] = env->regs[14]; | |
5748 | } else { | |
5749 | env->xregs[14] = env->banked_r14[bank_number(ARM_CPU_MODE_USR)]; | |
5750 | } | |
5751 | } | |
5752 | ||
5753 | if (mode == ARM_CPU_MODE_HYP) { | |
5754 | env->xregs[15] = env->regs[13]; | |
5755 | } else { | |
5756 | env->xregs[15] = env->banked_r13[bank_number(ARM_CPU_MODE_HYP)]; | |
5757 | } | |
5758 | ||
5759 | if (mode == ARM_CPU_MODE_IRQ) { | |
3a9148d0 SS |
5760 | env->xregs[16] = env->regs[14]; |
5761 | env->xregs[17] = env->regs[13]; | |
ce02049d | 5762 | } else { |
3a9148d0 SS |
5763 | env->xregs[16] = env->banked_r14[bank_number(ARM_CPU_MODE_IRQ)]; |
5764 | env->xregs[17] = env->banked_r13[bank_number(ARM_CPU_MODE_IRQ)]; | |
ce02049d GB |
5765 | } |
5766 | ||
5767 | if (mode == ARM_CPU_MODE_SVC) { | |
3a9148d0 SS |
5768 | env->xregs[18] = env->regs[14]; |
5769 | env->xregs[19] = env->regs[13]; | |
ce02049d | 5770 | } else { |
3a9148d0 SS |
5771 | env->xregs[18] = env->banked_r14[bank_number(ARM_CPU_MODE_SVC)]; |
5772 | env->xregs[19] = env->banked_r13[bank_number(ARM_CPU_MODE_SVC)]; | |
ce02049d GB |
5773 | } |
5774 | ||
5775 | if (mode == ARM_CPU_MODE_ABT) { | |
3a9148d0 SS |
5776 | env->xregs[20] = env->regs[14]; |
5777 | env->xregs[21] = env->regs[13]; | |
ce02049d | 5778 | } else { |
3a9148d0 SS |
5779 | env->xregs[20] = env->banked_r14[bank_number(ARM_CPU_MODE_ABT)]; |
5780 | env->xregs[21] = env->banked_r13[bank_number(ARM_CPU_MODE_ABT)]; | |
ce02049d GB |
5781 | } |
5782 | ||
5783 | if (mode == ARM_CPU_MODE_UND) { | |
3a9148d0 SS |
5784 | env->xregs[22] = env->regs[14]; |
5785 | env->xregs[23] = env->regs[13]; | |
ce02049d | 5786 | } else { |
3a9148d0 SS |
5787 | env->xregs[22] = env->banked_r14[bank_number(ARM_CPU_MODE_UND)]; |
5788 | env->xregs[23] = env->banked_r13[bank_number(ARM_CPU_MODE_UND)]; | |
ce02049d GB |
5789 | } |
5790 | ||
5791 | /* Registers x24-x30 are mapped to r8-r14 in FIQ mode. If we are in FIQ | |
5792 | * mode, then we can copy from r8-r14. Otherwise, we copy from the | |
5793 | * FIQ bank for r8-r14. | |
5794 | */ | |
5795 | if (mode == ARM_CPU_MODE_FIQ) { | |
5796 | for (i = 24; i < 31; i++) { | |
5797 | env->xregs[i] = env->regs[i - 16]; /* X[24:30] <- R[8:14] */ | |
5798 | } | |
5799 | } else { | |
5800 | for (i = 24; i < 29; i++) { | |
5801 | env->xregs[i] = env->fiq_regs[i - 24]; | |
5802 | } | |
5803 | env->xregs[29] = env->banked_r13[bank_number(ARM_CPU_MODE_FIQ)]; | |
5804 | env->xregs[30] = env->banked_r14[bank_number(ARM_CPU_MODE_FIQ)]; | |
5805 | } | |
5806 | ||
5807 | env->pc = env->regs[15]; | |
5808 | } | |
5809 | ||
5810 | /* Function used to synchronize QEMU's AArch32 register set with AArch64 | |
5811 | * register set. This is necessary when switching between AArch32 and AArch64 | |
5812 | * execution state. | |
5813 | */ | |
5814 | void aarch64_sync_64_to_32(CPUARMState *env) | |
5815 | { | |
5816 | int i; | |
5817 | uint32_t mode = env->uncached_cpsr & CPSR_M; | |
5818 | ||
5819 | /* We can blanket copy X[0:7] to R[0:7] */ | |
5820 | for (i = 0; i < 8; i++) { | |
5821 | env->regs[i] = env->xregs[i]; | |
5822 | } | |
5823 | ||
5824 | /* Unless we are in FIQ mode, r8-r12 come from the user registers x8-x12. | |
5825 | * Otherwise, we copy x8-x12 into the banked user regs. | |
5826 | */ | |
5827 | if (mode == ARM_CPU_MODE_FIQ) { | |
5828 | for (i = 8; i < 13; i++) { | |
5829 | env->usr_regs[i - 8] = env->xregs[i]; | |
5830 | } | |
5831 | } else { | |
5832 | for (i = 8; i < 13; i++) { | |
5833 | env->regs[i] = env->xregs[i]; | |
5834 | } | |
5835 | } | |
5836 | ||
5837 | /* Registers r13 & r14 depend on the current mode. | |
5838 | * If we are in a given mode, we copy the corresponding x registers to r13 | |
5839 | * and r14. Otherwise, we copy the x register to the banked r13 and r14 | |
5840 | * for the mode. | |
5841 | */ | |
5842 | if (mode == ARM_CPU_MODE_USR || mode == ARM_CPU_MODE_SYS) { | |
5843 | env->regs[13] = env->xregs[13]; | |
5844 | env->regs[14] = env->xregs[14]; | |
5845 | } else { | |
5846 | env->banked_r13[bank_number(ARM_CPU_MODE_USR)] = env->xregs[13]; | |
5847 | ||
5848 | /* HYP is an exception in that it does not have its own banked r14 but | |
5849 | * shares the USR r14 | |
5850 | */ | |
5851 | if (mode == ARM_CPU_MODE_HYP) { | |
5852 | env->regs[14] = env->xregs[14]; | |
5853 | } else { | |
5854 | env->banked_r14[bank_number(ARM_CPU_MODE_USR)] = env->xregs[14]; | |
5855 | } | |
5856 | } | |
5857 | ||
5858 | if (mode == ARM_CPU_MODE_HYP) { | |
5859 | env->regs[13] = env->xregs[15]; | |
5860 | } else { | |
5861 | env->banked_r13[bank_number(ARM_CPU_MODE_HYP)] = env->xregs[15]; | |
5862 | } | |
5863 | ||
5864 | if (mode == ARM_CPU_MODE_IRQ) { | |
3a9148d0 SS |
5865 | env->regs[14] = env->xregs[16]; |
5866 | env->regs[13] = env->xregs[17]; | |
ce02049d | 5867 | } else { |
3a9148d0 SS |
5868 | env->banked_r14[bank_number(ARM_CPU_MODE_IRQ)] = env->xregs[16]; |
5869 | env->banked_r13[bank_number(ARM_CPU_MODE_IRQ)] = env->xregs[17]; | |
ce02049d GB |
5870 | } |
5871 | ||
5872 | if (mode == ARM_CPU_MODE_SVC) { | |
3a9148d0 SS |
5873 | env->regs[14] = env->xregs[18]; |
5874 | env->regs[13] = env->xregs[19]; | |
ce02049d | 5875 | } else { |
3a9148d0 SS |
5876 | env->banked_r14[bank_number(ARM_CPU_MODE_SVC)] = env->xregs[18]; |
5877 | env->banked_r13[bank_number(ARM_CPU_MODE_SVC)] = env->xregs[19]; | |
ce02049d GB |
5878 | } |
5879 | ||
5880 | if (mode == ARM_CPU_MODE_ABT) { | |
3a9148d0 SS |
5881 | env->regs[14] = env->xregs[20]; |
5882 | env->regs[13] = env->xregs[21]; | |
ce02049d | 5883 | } else { |
3a9148d0 SS |
5884 | env->banked_r14[bank_number(ARM_CPU_MODE_ABT)] = env->xregs[20]; |
5885 | env->banked_r13[bank_number(ARM_CPU_MODE_ABT)] = env->xregs[21]; | |
ce02049d GB |
5886 | } |
5887 | ||
5888 | if (mode == ARM_CPU_MODE_UND) { | |
3a9148d0 SS |
5889 | env->regs[14] = env->xregs[22]; |
5890 | env->regs[13] = env->xregs[23]; | |
ce02049d | 5891 | } else { |
3a9148d0 SS |
5892 | env->banked_r14[bank_number(ARM_CPU_MODE_UND)] = env->xregs[22]; |
5893 | env->banked_r13[bank_number(ARM_CPU_MODE_UND)] = env->xregs[23]; | |
ce02049d GB |
5894 | } |
5895 | ||
5896 | /* Registers x24-x30 are mapped to r8-r14 in FIQ mode. If we are in FIQ | |
5897 | * mode, then we can copy to r8-r14. Otherwise, we copy to the | |
5898 | * FIQ bank for r8-r14. | |
5899 | */ | |
5900 | if (mode == ARM_CPU_MODE_FIQ) { | |
5901 | for (i = 24; i < 31; i++) { | |
5902 | env->regs[i - 16] = env->xregs[i]; /* X[24:30] -> R[8:14] */ | |
5903 | } | |
5904 | } else { | |
5905 | for (i = 24; i < 29; i++) { | |
5906 | env->fiq_regs[i - 24] = env->xregs[i]; | |
5907 | } | |
5908 | env->banked_r13[bank_number(ARM_CPU_MODE_FIQ)] = env->xregs[29]; | |
5909 | env->banked_r14[bank_number(ARM_CPU_MODE_FIQ)] = env->xregs[30]; | |
5910 | } | |
5911 | ||
5912 | env->regs[15] = env->pc; | |
5913 | } | |
5914 | ||
966f758c | 5915 | static void arm_cpu_do_interrupt_aarch32(CPUState *cs) |
b5ff1b31 | 5916 | { |
97a8ea5a AF |
5917 | ARMCPU *cpu = ARM_CPU(cs); |
5918 | CPUARMState *env = &cpu->env; | |
b5ff1b31 FB |
5919 | uint32_t addr; |
5920 | uint32_t mask; | |
5921 | int new_mode; | |
5922 | uint32_t offset; | |
16a906fd | 5923 | uint32_t moe; |
b5ff1b31 | 5924 | |
16a906fd PM |
5925 | /* If this is a debug exception we must update the DBGDSCR.MOE bits */ |
5926 | switch (env->exception.syndrome >> ARM_EL_EC_SHIFT) { | |
5927 | case EC_BREAKPOINT: | |
5928 | case EC_BREAKPOINT_SAME_EL: | |
5929 | moe = 1; | |
5930 | break; | |
5931 | case EC_WATCHPOINT: | |
5932 | case EC_WATCHPOINT_SAME_EL: | |
5933 | moe = 10; | |
5934 | break; | |
5935 | case EC_AA32_BKPT: | |
5936 | moe = 3; | |
5937 | break; | |
5938 | case EC_VECTORCATCH: | |
5939 | moe = 5; | |
5940 | break; | |
5941 | default: | |
5942 | moe = 0; | |
5943 | break; | |
5944 | } | |
5945 | ||
5946 | if (moe) { | |
5947 | env->cp15.mdscr_el1 = deposit64(env->cp15.mdscr_el1, 2, 4, moe); | |
5948 | } | |
5949 | ||
b5ff1b31 | 5950 | /* TODO: Vectored interrupt controller. */ |
27103424 | 5951 | switch (cs->exception_index) { |
b5ff1b31 FB |
5952 | case EXCP_UDEF: |
5953 | new_mode = ARM_CPU_MODE_UND; | |
5954 | addr = 0x04; | |
5955 | mask = CPSR_I; | |
5956 | if (env->thumb) | |
5957 | offset = 2; | |
5958 | else | |
5959 | offset = 4; | |
5960 | break; | |
5961 | case EXCP_SWI: | |
5962 | new_mode = ARM_CPU_MODE_SVC; | |
5963 | addr = 0x08; | |
5964 | mask = CPSR_I; | |
601d70b9 | 5965 | /* The PC already points to the next instruction. */ |
b5ff1b31 FB |
5966 | offset = 0; |
5967 | break; | |
06c949e6 | 5968 | case EXCP_BKPT: |
abf1172f | 5969 | env->exception.fsr = 2; |
9ee6e8bb PB |
5970 | /* Fall through to prefetch abort. */ |
5971 | case EXCP_PREFETCH_ABORT: | |
88ca1c2d | 5972 | A32_BANKED_CURRENT_REG_SET(env, ifsr, env->exception.fsr); |
b848ce2b | 5973 | A32_BANKED_CURRENT_REG_SET(env, ifar, env->exception.vaddress); |
3f1beaca | 5974 | qemu_log_mask(CPU_LOG_INT, "...with IFSR 0x%x IFAR 0x%x\n", |
88ca1c2d | 5975 | env->exception.fsr, (uint32_t)env->exception.vaddress); |
b5ff1b31 FB |
5976 | new_mode = ARM_CPU_MODE_ABT; |
5977 | addr = 0x0c; | |
5978 | mask = CPSR_A | CPSR_I; | |
5979 | offset = 4; | |
5980 | break; | |
5981 | case EXCP_DATA_ABORT: | |
4a7e2d73 | 5982 | A32_BANKED_CURRENT_REG_SET(env, dfsr, env->exception.fsr); |
b848ce2b | 5983 | A32_BANKED_CURRENT_REG_SET(env, dfar, env->exception.vaddress); |
3f1beaca | 5984 | qemu_log_mask(CPU_LOG_INT, "...with DFSR 0x%x DFAR 0x%x\n", |
4a7e2d73 | 5985 | env->exception.fsr, |
6cd8a264 | 5986 | (uint32_t)env->exception.vaddress); |
b5ff1b31 FB |
5987 | new_mode = ARM_CPU_MODE_ABT; |
5988 | addr = 0x10; | |
5989 | mask = CPSR_A | CPSR_I; | |
5990 | offset = 8; | |
5991 | break; | |
5992 | case EXCP_IRQ: | |
5993 | new_mode = ARM_CPU_MODE_IRQ; | |
5994 | addr = 0x18; | |
5995 | /* Disable IRQ and imprecise data aborts. */ | |
5996 | mask = CPSR_A | CPSR_I; | |
5997 | offset = 4; | |
de38d23b FA |
5998 | if (env->cp15.scr_el3 & SCR_IRQ) { |
5999 | /* IRQ routed to monitor mode */ | |
6000 | new_mode = ARM_CPU_MODE_MON; | |
6001 | mask |= CPSR_F; | |
6002 | } | |
b5ff1b31 FB |
6003 | break; |
6004 | case EXCP_FIQ: | |
6005 | new_mode = ARM_CPU_MODE_FIQ; | |
6006 | addr = 0x1c; | |
6007 | /* Disable FIQ, IRQ and imprecise data aborts. */ | |
6008 | mask = CPSR_A | CPSR_I | CPSR_F; | |
de38d23b FA |
6009 | if (env->cp15.scr_el3 & SCR_FIQ) { |
6010 | /* FIQ routed to monitor mode */ | |
6011 | new_mode = ARM_CPU_MODE_MON; | |
6012 | } | |
b5ff1b31 FB |
6013 | offset = 4; |
6014 | break; | |
dbe9d163 FA |
6015 | case EXCP_SMC: |
6016 | new_mode = ARM_CPU_MODE_MON; | |
6017 | addr = 0x08; | |
6018 | mask = CPSR_A | CPSR_I | CPSR_F; | |
6019 | offset = 0; | |
6020 | break; | |
b5ff1b31 | 6021 | default: |
a47dddd7 | 6022 | cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index); |
b5ff1b31 FB |
6023 | return; /* Never happens. Keep compiler happy. */ |
6024 | } | |
e89e51a1 FA |
6025 | |
6026 | if (new_mode == ARM_CPU_MODE_MON) { | |
6027 | addr += env->cp15.mvbar; | |
137feaa9 | 6028 | } else if (A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_V) { |
e89e51a1 | 6029 | /* High vectors. When enabled, base address cannot be remapped. */ |
b5ff1b31 | 6030 | addr += 0xffff0000; |
8641136c NR |
6031 | } else { |
6032 | /* ARM v7 architectures provide a vector base address register to remap | |
6033 | * the interrupt vector table. | |
e89e51a1 | 6034 | * This register is only followed in non-monitor mode, and is banked. |
8641136c NR |
6035 | * Note: only bits 31:5 are valid. |
6036 | */ | |
fb6c91ba | 6037 | addr += A32_BANKED_CURRENT_REG_GET(env, vbar); |
b5ff1b31 | 6038 | } |
dbe9d163 FA |
6039 | |
6040 | if ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_MON) { | |
6041 | env->cp15.scr_el3 &= ~SCR_NS; | |
6042 | } | |
6043 | ||
b5ff1b31 | 6044 | switch_mode (env, new_mode); |
662cefb7 PM |
6045 | /* For exceptions taken to AArch32 we must clear the SS bit in both |
6046 | * PSTATE and in the old-state value we save to SPSR_<mode>, so zero it now. | |
6047 | */ | |
6048 | env->uncached_cpsr &= ~PSTATE_SS; | |
b5ff1b31 | 6049 | env->spsr = cpsr_read(env); |
9ee6e8bb PB |
6050 | /* Clear IT bits. */ |
6051 | env->condexec_bits = 0; | |
30a8cac1 | 6052 | /* Switch to the new mode, and to the correct instruction set. */ |
6d7e6326 | 6053 | env->uncached_cpsr = (env->uncached_cpsr & ~CPSR_M) | new_mode; |
4cc35614 | 6054 | env->daif |= mask; |
be5e7a76 DES |
6055 | /* this is a lie, as the was no c1_sys on V4T/V5, but who cares |
6056 | * and we should just guard the thumb mode on V4 */ | |
6057 | if (arm_feature(env, ARM_FEATURE_V4T)) { | |
137feaa9 | 6058 | env->thumb = (A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_TE) != 0; |
be5e7a76 | 6059 | } |
b5ff1b31 FB |
6060 | env->regs[14] = env->regs[15] + offset; |
6061 | env->regs[15] = addr; | |
b5ff1b31 FB |
6062 | } |
6063 | ||
966f758c PM |
6064 | /* Handle exception entry to a target EL which is using AArch64 */ |
6065 | static void arm_cpu_do_interrupt_aarch64(CPUState *cs) | |
f3a9b694 PM |
6066 | { |
6067 | ARMCPU *cpu = ARM_CPU(cs); | |
6068 | CPUARMState *env = &cpu->env; | |
6069 | unsigned int new_el = env->exception.target_el; | |
6070 | target_ulong addr = env->cp15.vbar_el[new_el]; | |
6071 | unsigned int new_mode = aarch64_pstate_mode(new_el, true); | |
6072 | ||
6073 | if (arm_current_el(env) < new_el) { | |
3d6f7617 PM |
6074 | /* Entry vector offset depends on whether the implemented EL |
6075 | * immediately lower than the target level is using AArch32 or AArch64 | |
6076 | */ | |
6077 | bool is_aa64; | |
6078 | ||
6079 | switch (new_el) { | |
6080 | case 3: | |
6081 | is_aa64 = (env->cp15.scr_el3 & SCR_RW) != 0; | |
6082 | break; | |
6083 | case 2: | |
6084 | is_aa64 = (env->cp15.hcr_el2 & HCR_RW) != 0; | |
6085 | break; | |
6086 | case 1: | |
6087 | is_aa64 = is_a64(env); | |
6088 | break; | |
6089 | default: | |
6090 | g_assert_not_reached(); | |
6091 | } | |
6092 | ||
6093 | if (is_aa64) { | |
f3a9b694 PM |
6094 | addr += 0x400; |
6095 | } else { | |
6096 | addr += 0x600; | |
6097 | } | |
6098 | } else if (pstate_read(env) & PSTATE_SP) { | |
6099 | addr += 0x200; | |
6100 | } | |
6101 | ||
f3a9b694 PM |
6102 | switch (cs->exception_index) { |
6103 | case EXCP_PREFETCH_ABORT: | |
6104 | case EXCP_DATA_ABORT: | |
6105 | env->cp15.far_el[new_el] = env->exception.vaddress; | |
6106 | qemu_log_mask(CPU_LOG_INT, "...with FAR 0x%" PRIx64 "\n", | |
6107 | env->cp15.far_el[new_el]); | |
6108 | /* fall through */ | |
6109 | case EXCP_BKPT: | |
6110 | case EXCP_UDEF: | |
6111 | case EXCP_SWI: | |
6112 | case EXCP_HVC: | |
6113 | case EXCP_HYP_TRAP: | |
6114 | case EXCP_SMC: | |
6115 | env->cp15.esr_el[new_el] = env->exception.syndrome; | |
6116 | break; | |
6117 | case EXCP_IRQ: | |
6118 | case EXCP_VIRQ: | |
6119 | addr += 0x80; | |
6120 | break; | |
6121 | case EXCP_FIQ: | |
6122 | case EXCP_VFIQ: | |
6123 | addr += 0x100; | |
6124 | break; | |
6125 | case EXCP_SEMIHOST: | |
6126 | qemu_log_mask(CPU_LOG_INT, | |
6127 | "...handling as semihosting call 0x%" PRIx64 "\n", | |
6128 | env->xregs[0]); | |
6129 | env->xregs[0] = do_arm_semihosting(env); | |
6130 | return; | |
6131 | default: | |
6132 | cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index); | |
6133 | } | |
6134 | ||
6135 | if (is_a64(env)) { | |
6136 | env->banked_spsr[aarch64_banked_spsr_index(new_el)] = pstate_read(env); | |
6137 | aarch64_save_sp(env, arm_current_el(env)); | |
6138 | env->elr_el[new_el] = env->pc; | |
6139 | } else { | |
6140 | env->banked_spsr[aarch64_banked_spsr_index(new_el)] = cpsr_read(env); | |
6141 | if (!env->thumb) { | |
6142 | env->cp15.esr_el[new_el] |= 1 << 25; | |
6143 | } | |
6144 | env->elr_el[new_el] = env->regs[15]; | |
6145 | ||
6146 | aarch64_sync_32_to_64(env); | |
6147 | ||
6148 | env->condexec_bits = 0; | |
6149 | } | |
6150 | qemu_log_mask(CPU_LOG_INT, "...with ELR 0x%" PRIx64 "\n", | |
6151 | env->elr_el[new_el]); | |
6152 | ||
6153 | pstate_write(env, PSTATE_DAIF | new_mode); | |
6154 | env->aarch64 = 1; | |
6155 | aarch64_restore_sp(env, new_el); | |
6156 | ||
6157 | env->pc = addr; | |
6158 | ||
6159 | qemu_log_mask(CPU_LOG_INT, "...to EL%d PC 0x%" PRIx64 " PSTATE 0x%x\n", | |
6160 | new_el, env->pc, pstate_read(env)); | |
966f758c PM |
6161 | } |
6162 | ||
904c04de PM |
6163 | static inline bool check_for_semihosting(CPUState *cs) |
6164 | { | |
6165 | /* Check whether this exception is a semihosting call; if so | |
6166 | * then handle it and return true; otherwise return false. | |
6167 | */ | |
6168 | ARMCPU *cpu = ARM_CPU(cs); | |
6169 | CPUARMState *env = &cpu->env; | |
6170 | ||
6171 | if (is_a64(env)) { | |
6172 | if (cs->exception_index == EXCP_SEMIHOST) { | |
6173 | /* This is always the 64-bit semihosting exception. | |
6174 | * The "is this usermode" and "is semihosting enabled" | |
6175 | * checks have been done at translate time. | |
6176 | */ | |
6177 | qemu_log_mask(CPU_LOG_INT, | |
6178 | "...handling as semihosting call 0x%" PRIx64 "\n", | |
6179 | env->xregs[0]); | |
6180 | env->xregs[0] = do_arm_semihosting(env); | |
6181 | return true; | |
6182 | } | |
6183 | return false; | |
6184 | } else { | |
6185 | uint32_t imm; | |
6186 | ||
6187 | /* Only intercept calls from privileged modes, to provide some | |
6188 | * semblance of security. | |
6189 | */ | |
6190 | if (!semihosting_enabled() || | |
6191 | ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_USR)) { | |
6192 | return false; | |
6193 | } | |
6194 | ||
6195 | switch (cs->exception_index) { | |
6196 | case EXCP_SWI: | |
6197 | /* Check for semihosting interrupt. */ | |
6198 | if (env->thumb) { | |
6199 | imm = arm_lduw_code(env, env->regs[15] - 2, env->bswap_code) | |
6200 | & 0xff; | |
6201 | if (imm == 0xab) { | |
6202 | break; | |
6203 | } | |
6204 | } else { | |
6205 | imm = arm_ldl_code(env, env->regs[15] - 4, env->bswap_code) | |
6206 | & 0xffffff; | |
6207 | if (imm == 0x123456) { | |
6208 | break; | |
6209 | } | |
6210 | } | |
6211 | return false; | |
6212 | case EXCP_BKPT: | |
6213 | /* See if this is a semihosting syscall. */ | |
6214 | if (env->thumb) { | |
6215 | imm = arm_lduw_code(env, env->regs[15], env->bswap_code) | |
6216 | & 0xff; | |
6217 | if (imm == 0xab) { | |
6218 | env->regs[15] += 2; | |
6219 | break; | |
6220 | } | |
6221 | } | |
6222 | return false; | |
6223 | default: | |
6224 | return false; | |
6225 | } | |
6226 | ||
6227 | qemu_log_mask(CPU_LOG_INT, | |
6228 | "...handling as semihosting call 0x%x\n", | |
6229 | env->regs[0]); | |
6230 | env->regs[0] = do_arm_semihosting(env); | |
6231 | return true; | |
6232 | } | |
6233 | } | |
6234 | ||
966f758c PM |
6235 | /* Handle a CPU exception for A and R profile CPUs. |
6236 | * Do any appropriate logging, handle PSCI calls, and then hand off | |
6237 | * to the AArch64-entry or AArch32-entry function depending on the | |
6238 | * target exception level's register width. | |
6239 | */ | |
6240 | void arm_cpu_do_interrupt(CPUState *cs) | |
6241 | { | |
6242 | ARMCPU *cpu = ARM_CPU(cs); | |
6243 | CPUARMState *env = &cpu->env; | |
6244 | unsigned int new_el = env->exception.target_el; | |
6245 | ||
6246 | assert(!IS_M(env)); | |
6247 | ||
6248 | arm_log_exception(cs->exception_index); | |
6249 | qemu_log_mask(CPU_LOG_INT, "...from EL%d to EL%d\n", arm_current_el(env), | |
6250 | new_el); | |
6251 | if (qemu_loglevel_mask(CPU_LOG_INT) | |
6252 | && !excp_is_internal(cs->exception_index)) { | |
6253 | qemu_log_mask(CPU_LOG_INT, "...with ESR %x/0x%" PRIx32 "\n", | |
6254 | env->exception.syndrome >> ARM_EL_EC_SHIFT, | |
6255 | env->exception.syndrome); | |
6256 | } | |
6257 | ||
6258 | if (arm_is_psci_call(cpu, cs->exception_index)) { | |
6259 | arm_handle_psci_call(cpu); | |
6260 | qemu_log_mask(CPU_LOG_INT, "...handled as PSCI call\n"); | |
6261 | return; | |
6262 | } | |
6263 | ||
904c04de PM |
6264 | /* Semihosting semantics depend on the register width of the |
6265 | * code that caused the exception, not the target exception level, | |
6266 | * so must be handled here. | |
966f758c | 6267 | */ |
904c04de PM |
6268 | if (check_for_semihosting(cs)) { |
6269 | return; | |
6270 | } | |
6271 | ||
6272 | assert(!excp_is_internal(cs->exception_index)); | |
6273 | if (arm_el_is_aa64(env, new_el)) { | |
966f758c PM |
6274 | arm_cpu_do_interrupt_aarch64(cs); |
6275 | } else { | |
6276 | arm_cpu_do_interrupt_aarch32(cs); | |
6277 | } | |
f3a9b694 PM |
6278 | |
6279 | if (!kvm_enabled()) { | |
6280 | cs->interrupt_request |= CPU_INTERRUPT_EXITTB; | |
6281 | } | |
6282 | } | |
0480f69a PM |
6283 | |
6284 | /* Return the exception level which controls this address translation regime */ | |
6285 | static inline uint32_t regime_el(CPUARMState *env, ARMMMUIdx mmu_idx) | |
6286 | { | |
6287 | switch (mmu_idx) { | |
6288 | case ARMMMUIdx_S2NS: | |
6289 | case ARMMMUIdx_S1E2: | |
6290 | return 2; | |
6291 | case ARMMMUIdx_S1E3: | |
6292 | return 3; | |
6293 | case ARMMMUIdx_S1SE0: | |
6294 | return arm_el_is_aa64(env, 3) ? 1 : 3; | |
6295 | case ARMMMUIdx_S1SE1: | |
6296 | case ARMMMUIdx_S1NSE0: | |
6297 | case ARMMMUIdx_S1NSE1: | |
6298 | return 1; | |
6299 | default: | |
6300 | g_assert_not_reached(); | |
6301 | } | |
6302 | } | |
6303 | ||
8bf5b6a9 PM |
6304 | /* Return true if this address translation regime is secure */ |
6305 | static inline bool regime_is_secure(CPUARMState *env, ARMMMUIdx mmu_idx) | |
6306 | { | |
6307 | switch (mmu_idx) { | |
6308 | case ARMMMUIdx_S12NSE0: | |
6309 | case ARMMMUIdx_S12NSE1: | |
6310 | case ARMMMUIdx_S1NSE0: | |
6311 | case ARMMMUIdx_S1NSE1: | |
6312 | case ARMMMUIdx_S1E2: | |
6313 | case ARMMMUIdx_S2NS: | |
6314 | return false; | |
6315 | case ARMMMUIdx_S1E3: | |
6316 | case ARMMMUIdx_S1SE0: | |
6317 | case ARMMMUIdx_S1SE1: | |
6318 | return true; | |
6319 | default: | |
6320 | g_assert_not_reached(); | |
6321 | } | |
6322 | } | |
6323 | ||
0480f69a PM |
6324 | /* Return the SCTLR value which controls this address translation regime */ |
6325 | static inline uint32_t regime_sctlr(CPUARMState *env, ARMMMUIdx mmu_idx) | |
6326 | { | |
6327 | return env->cp15.sctlr_el[regime_el(env, mmu_idx)]; | |
6328 | } | |
6329 | ||
6330 | /* Return true if the specified stage of address translation is disabled */ | |
6331 | static inline bool regime_translation_disabled(CPUARMState *env, | |
6332 | ARMMMUIdx mmu_idx) | |
6333 | { | |
6334 | if (mmu_idx == ARMMMUIdx_S2NS) { | |
6335 | return (env->cp15.hcr_el2 & HCR_VM) == 0; | |
6336 | } | |
6337 | return (regime_sctlr(env, mmu_idx) & SCTLR_M) == 0; | |
6338 | } | |
6339 | ||
6340 | /* Return the TCR controlling this translation regime */ | |
6341 | static inline TCR *regime_tcr(CPUARMState *env, ARMMMUIdx mmu_idx) | |
6342 | { | |
6343 | if (mmu_idx == ARMMMUIdx_S2NS) { | |
68e9c2fe | 6344 | return &env->cp15.vtcr_el2; |
0480f69a PM |
6345 | } |
6346 | return &env->cp15.tcr_el[regime_el(env, mmu_idx)]; | |
6347 | } | |
6348 | ||
aef878be GB |
6349 | /* Return the TTBR associated with this translation regime */ |
6350 | static inline uint64_t regime_ttbr(CPUARMState *env, ARMMMUIdx mmu_idx, | |
6351 | int ttbrn) | |
6352 | { | |
6353 | if (mmu_idx == ARMMMUIdx_S2NS) { | |
b698e9cf | 6354 | return env->cp15.vttbr_el2; |
aef878be GB |
6355 | } |
6356 | if (ttbrn == 0) { | |
6357 | return env->cp15.ttbr0_el[regime_el(env, mmu_idx)]; | |
6358 | } else { | |
6359 | return env->cp15.ttbr1_el[regime_el(env, mmu_idx)]; | |
6360 | } | |
6361 | } | |
6362 | ||
0480f69a PM |
6363 | /* Return true if the translation regime is using LPAE format page tables */ |
6364 | static inline bool regime_using_lpae_format(CPUARMState *env, | |
6365 | ARMMMUIdx mmu_idx) | |
6366 | { | |
6367 | int el = regime_el(env, mmu_idx); | |
6368 | if (el == 2 || arm_el_is_aa64(env, el)) { | |
6369 | return true; | |
6370 | } | |
6371 | if (arm_feature(env, ARM_FEATURE_LPAE) | |
6372 | && (regime_tcr(env, mmu_idx)->raw_tcr & TTBCR_EAE)) { | |
6373 | return true; | |
6374 | } | |
6375 | return false; | |
6376 | } | |
6377 | ||
deb2db99 AR |
6378 | /* Returns true if the stage 1 translation regime is using LPAE format page |
6379 | * tables. Used when raising alignment exceptions, whose FSR changes depending | |
6380 | * on whether the long or short descriptor format is in use. */ | |
6381 | bool arm_s1_regime_using_lpae_format(CPUARMState *env, ARMMMUIdx mmu_idx) | |
30901475 | 6382 | { |
deb2db99 AR |
6383 | if (mmu_idx == ARMMMUIdx_S12NSE0 || mmu_idx == ARMMMUIdx_S12NSE1) { |
6384 | mmu_idx += ARMMMUIdx_S1NSE0; | |
6385 | } | |
6386 | ||
30901475 AB |
6387 | return regime_using_lpae_format(env, mmu_idx); |
6388 | } | |
6389 | ||
0480f69a PM |
6390 | static inline bool regime_is_user(CPUARMState *env, ARMMMUIdx mmu_idx) |
6391 | { | |
6392 | switch (mmu_idx) { | |
6393 | case ARMMMUIdx_S1SE0: | |
6394 | case ARMMMUIdx_S1NSE0: | |
6395 | return true; | |
6396 | default: | |
6397 | return false; | |
6398 | case ARMMMUIdx_S12NSE0: | |
6399 | case ARMMMUIdx_S12NSE1: | |
6400 | g_assert_not_reached(); | |
6401 | } | |
6402 | } | |
6403 | ||
0fbf5238 AJ |
6404 | /* Translate section/page access permissions to page |
6405 | * R/W protection flags | |
d76951b6 AJ |
6406 | * |
6407 | * @env: CPUARMState | |
6408 | * @mmu_idx: MMU index indicating required translation regime | |
6409 | * @ap: The 3-bit access permissions (AP[2:0]) | |
6410 | * @domain_prot: The 2-bit domain access permissions | |
0fbf5238 AJ |
6411 | */ |
6412 | static inline int ap_to_rw_prot(CPUARMState *env, ARMMMUIdx mmu_idx, | |
6413 | int ap, int domain_prot) | |
6414 | { | |
554b0b09 PM |
6415 | bool is_user = regime_is_user(env, mmu_idx); |
6416 | ||
6417 | if (domain_prot == 3) { | |
6418 | return PAGE_READ | PAGE_WRITE; | |
6419 | } | |
6420 | ||
554b0b09 PM |
6421 | switch (ap) { |
6422 | case 0: | |
6423 | if (arm_feature(env, ARM_FEATURE_V7)) { | |
6424 | return 0; | |
6425 | } | |
554b0b09 PM |
6426 | switch (regime_sctlr(env, mmu_idx) & (SCTLR_S | SCTLR_R)) { |
6427 | case SCTLR_S: | |
6428 | return is_user ? 0 : PAGE_READ; | |
6429 | case SCTLR_R: | |
6430 | return PAGE_READ; | |
6431 | default: | |
6432 | return 0; | |
6433 | } | |
6434 | case 1: | |
6435 | return is_user ? 0 : PAGE_READ | PAGE_WRITE; | |
6436 | case 2: | |
87c3d486 | 6437 | if (is_user) { |
0fbf5238 | 6438 | return PAGE_READ; |
87c3d486 | 6439 | } else { |
554b0b09 | 6440 | return PAGE_READ | PAGE_WRITE; |
87c3d486 | 6441 | } |
554b0b09 PM |
6442 | case 3: |
6443 | return PAGE_READ | PAGE_WRITE; | |
6444 | case 4: /* Reserved. */ | |
6445 | return 0; | |
6446 | case 5: | |
0fbf5238 | 6447 | return is_user ? 0 : PAGE_READ; |
554b0b09 | 6448 | case 6: |
0fbf5238 | 6449 | return PAGE_READ; |
554b0b09 | 6450 | case 7: |
87c3d486 | 6451 | if (!arm_feature(env, ARM_FEATURE_V6K)) { |
554b0b09 | 6452 | return 0; |
87c3d486 | 6453 | } |
0fbf5238 | 6454 | return PAGE_READ; |
554b0b09 | 6455 | default: |
0fbf5238 | 6456 | g_assert_not_reached(); |
554b0b09 | 6457 | } |
b5ff1b31 FB |
6458 | } |
6459 | ||
d76951b6 AJ |
6460 | /* Translate section/page access permissions to page |
6461 | * R/W protection flags. | |
6462 | * | |
d76951b6 | 6463 | * @ap: The 2-bit simple AP (AP[2:1]) |
d8e052b3 | 6464 | * @is_user: TRUE if accessing from PL0 |
d76951b6 | 6465 | */ |
d8e052b3 | 6466 | static inline int simple_ap_to_rw_prot_is_user(int ap, bool is_user) |
d76951b6 | 6467 | { |
d76951b6 AJ |
6468 | switch (ap) { |
6469 | case 0: | |
6470 | return is_user ? 0 : PAGE_READ | PAGE_WRITE; | |
6471 | case 1: | |
6472 | return PAGE_READ | PAGE_WRITE; | |
6473 | case 2: | |
6474 | return is_user ? 0 : PAGE_READ; | |
6475 | case 3: | |
6476 | return PAGE_READ; | |
6477 | default: | |
6478 | g_assert_not_reached(); | |
6479 | } | |
6480 | } | |
6481 | ||
d8e052b3 AJ |
6482 | static inline int |
6483 | simple_ap_to_rw_prot(CPUARMState *env, ARMMMUIdx mmu_idx, int ap) | |
6484 | { | |
6485 | return simple_ap_to_rw_prot_is_user(ap, regime_is_user(env, mmu_idx)); | |
6486 | } | |
6487 | ||
6ab1a5ee EI |
6488 | /* Translate S2 section/page access permissions to protection flags |
6489 | * | |
6490 | * @env: CPUARMState | |
6491 | * @s2ap: The 2-bit stage2 access permissions (S2AP) | |
6492 | * @xn: XN (execute-never) bit | |
6493 | */ | |
6494 | static int get_S2prot(CPUARMState *env, int s2ap, int xn) | |
6495 | { | |
6496 | int prot = 0; | |
6497 | ||
6498 | if (s2ap & 1) { | |
6499 | prot |= PAGE_READ; | |
6500 | } | |
6501 | if (s2ap & 2) { | |
6502 | prot |= PAGE_WRITE; | |
6503 | } | |
6504 | if (!xn) { | |
6505 | prot |= PAGE_EXEC; | |
6506 | } | |
6507 | return prot; | |
6508 | } | |
6509 | ||
d8e052b3 AJ |
6510 | /* Translate section/page access permissions to protection flags |
6511 | * | |
6512 | * @env: CPUARMState | |
6513 | * @mmu_idx: MMU index indicating required translation regime | |
6514 | * @is_aa64: TRUE if AArch64 | |
6515 | * @ap: The 2-bit simple AP (AP[2:1]) | |
6516 | * @ns: NS (non-secure) bit | |
6517 | * @xn: XN (execute-never) bit | |
6518 | * @pxn: PXN (privileged execute-never) bit | |
6519 | */ | |
6520 | static int get_S1prot(CPUARMState *env, ARMMMUIdx mmu_idx, bool is_aa64, | |
6521 | int ap, int ns, int xn, int pxn) | |
6522 | { | |
6523 | bool is_user = regime_is_user(env, mmu_idx); | |
6524 | int prot_rw, user_rw; | |
6525 | bool have_wxn; | |
6526 | int wxn = 0; | |
6527 | ||
6528 | assert(mmu_idx != ARMMMUIdx_S2NS); | |
6529 | ||
6530 | user_rw = simple_ap_to_rw_prot_is_user(ap, true); | |
6531 | if (is_user) { | |
6532 | prot_rw = user_rw; | |
6533 | } else { | |
6534 | prot_rw = simple_ap_to_rw_prot_is_user(ap, false); | |
6535 | } | |
6536 | ||
6537 | if (ns && arm_is_secure(env) && (env->cp15.scr_el3 & SCR_SIF)) { | |
6538 | return prot_rw; | |
6539 | } | |
6540 | ||
6541 | /* TODO have_wxn should be replaced with | |
6542 | * ARM_FEATURE_V8 || (ARM_FEATURE_V7 && ARM_FEATURE_EL2) | |
6543 | * when ARM_FEATURE_EL2 starts getting set. For now we assume all LPAE | |
6544 | * compatible processors have EL2, which is required for [U]WXN. | |
6545 | */ | |
6546 | have_wxn = arm_feature(env, ARM_FEATURE_LPAE); | |
6547 | ||
6548 | if (have_wxn) { | |
6549 | wxn = regime_sctlr(env, mmu_idx) & SCTLR_WXN; | |
6550 | } | |
6551 | ||
6552 | if (is_aa64) { | |
6553 | switch (regime_el(env, mmu_idx)) { | |
6554 | case 1: | |
6555 | if (!is_user) { | |
6556 | xn = pxn || (user_rw & PAGE_WRITE); | |
6557 | } | |
6558 | break; | |
6559 | case 2: | |
6560 | case 3: | |
6561 | break; | |
6562 | } | |
6563 | } else if (arm_feature(env, ARM_FEATURE_V7)) { | |
6564 | switch (regime_el(env, mmu_idx)) { | |
6565 | case 1: | |
6566 | case 3: | |
6567 | if (is_user) { | |
6568 | xn = xn || !(user_rw & PAGE_READ); | |
6569 | } else { | |
6570 | int uwxn = 0; | |
6571 | if (have_wxn) { | |
6572 | uwxn = regime_sctlr(env, mmu_idx) & SCTLR_UWXN; | |
6573 | } | |
6574 | xn = xn || !(prot_rw & PAGE_READ) || pxn || | |
6575 | (uwxn && (user_rw & PAGE_WRITE)); | |
6576 | } | |
6577 | break; | |
6578 | case 2: | |
6579 | break; | |
6580 | } | |
6581 | } else { | |
6582 | xn = wxn = 0; | |
6583 | } | |
6584 | ||
6585 | if (xn || (wxn && (prot_rw & PAGE_WRITE))) { | |
6586 | return prot_rw; | |
6587 | } | |
6588 | return prot_rw | PAGE_EXEC; | |
6589 | } | |
6590 | ||
0480f69a PM |
6591 | static bool get_level1_table_address(CPUARMState *env, ARMMMUIdx mmu_idx, |
6592 | uint32_t *table, uint32_t address) | |
b2fa1797 | 6593 | { |
0480f69a | 6594 | /* Note that we can only get here for an AArch32 PL0/PL1 lookup */ |
0480f69a | 6595 | TCR *tcr = regime_tcr(env, mmu_idx); |
11f136ee | 6596 | |
11f136ee FA |
6597 | if (address & tcr->mask) { |
6598 | if (tcr->raw_tcr & TTBCR_PD1) { | |
e389be16 FA |
6599 | /* Translation table walk disabled for TTBR1 */ |
6600 | return false; | |
6601 | } | |
aef878be | 6602 | *table = regime_ttbr(env, mmu_idx, 1) & 0xffffc000; |
e389be16 | 6603 | } else { |
11f136ee | 6604 | if (tcr->raw_tcr & TTBCR_PD0) { |
e389be16 FA |
6605 | /* Translation table walk disabled for TTBR0 */ |
6606 | return false; | |
6607 | } | |
aef878be | 6608 | *table = regime_ttbr(env, mmu_idx, 0) & tcr->base_mask; |
e389be16 FA |
6609 | } |
6610 | *table |= (address >> 18) & 0x3ffc; | |
6611 | return true; | |
b2fa1797 PB |
6612 | } |
6613 | ||
37785977 EI |
6614 | /* Translate a S1 pagetable walk through S2 if needed. */ |
6615 | static hwaddr S1_ptw_translate(CPUARMState *env, ARMMMUIdx mmu_idx, | |
6616 | hwaddr addr, MemTxAttrs txattrs, | |
6617 | uint32_t *fsr, | |
6618 | ARMMMUFaultInfo *fi) | |
6619 | { | |
6620 | if ((mmu_idx == ARMMMUIdx_S1NSE0 || mmu_idx == ARMMMUIdx_S1NSE1) && | |
6621 | !regime_translation_disabled(env, ARMMMUIdx_S2NS)) { | |
6622 | target_ulong s2size; | |
6623 | hwaddr s2pa; | |
6624 | int s2prot; | |
6625 | int ret; | |
6626 | ||
6627 | ret = get_phys_addr_lpae(env, addr, 0, ARMMMUIdx_S2NS, &s2pa, | |
6628 | &txattrs, &s2prot, &s2size, fsr, fi); | |
6629 | if (ret) { | |
6630 | fi->s2addr = addr; | |
6631 | fi->stage2 = true; | |
6632 | fi->s1ptw = true; | |
6633 | return ~0; | |
6634 | } | |
6635 | addr = s2pa; | |
6636 | } | |
6637 | return addr; | |
6638 | } | |
6639 | ||
ebca90e4 PM |
6640 | /* All loads done in the course of a page table walk go through here. |
6641 | * TODO: rather than ignoring errors from physical memory reads (which | |
6642 | * are external aborts in ARM terminology) we should propagate this | |
6643 | * error out so that we can turn it into a Data Abort if this walk | |
6644 | * was being done for a CPU load/store or an address translation instruction | |
6645 | * (but not if it was for a debug access). | |
6646 | */ | |
a614e698 EI |
6647 | static uint32_t arm_ldl_ptw(CPUState *cs, hwaddr addr, bool is_secure, |
6648 | ARMMMUIdx mmu_idx, uint32_t *fsr, | |
6649 | ARMMMUFaultInfo *fi) | |
ebca90e4 | 6650 | { |
a614e698 EI |
6651 | ARMCPU *cpu = ARM_CPU(cs); |
6652 | CPUARMState *env = &cpu->env; | |
ebca90e4 | 6653 | MemTxAttrs attrs = {}; |
5ce4ff65 | 6654 | AddressSpace *as; |
ebca90e4 PM |
6655 | |
6656 | attrs.secure = is_secure; | |
5ce4ff65 | 6657 | as = arm_addressspace(cs, attrs); |
a614e698 EI |
6658 | addr = S1_ptw_translate(env, mmu_idx, addr, attrs, fsr, fi); |
6659 | if (fi->s1ptw) { | |
6660 | return 0; | |
6661 | } | |
5ce4ff65 | 6662 | return address_space_ldl(as, addr, attrs, NULL); |
ebca90e4 PM |
6663 | } |
6664 | ||
37785977 EI |
6665 | static uint64_t arm_ldq_ptw(CPUState *cs, hwaddr addr, bool is_secure, |
6666 | ARMMMUIdx mmu_idx, uint32_t *fsr, | |
6667 | ARMMMUFaultInfo *fi) | |
ebca90e4 | 6668 | { |
37785977 EI |
6669 | ARMCPU *cpu = ARM_CPU(cs); |
6670 | CPUARMState *env = &cpu->env; | |
ebca90e4 | 6671 | MemTxAttrs attrs = {}; |
5ce4ff65 | 6672 | AddressSpace *as; |
ebca90e4 PM |
6673 | |
6674 | attrs.secure = is_secure; | |
5ce4ff65 | 6675 | as = arm_addressspace(cs, attrs); |
37785977 EI |
6676 | addr = S1_ptw_translate(env, mmu_idx, addr, attrs, fsr, fi); |
6677 | if (fi->s1ptw) { | |
6678 | return 0; | |
6679 | } | |
5ce4ff65 | 6680 | return address_space_ldq(as, addr, attrs, NULL); |
ebca90e4 PM |
6681 | } |
6682 | ||
b7cc4e82 PC |
6683 | static bool get_phys_addr_v5(CPUARMState *env, uint32_t address, |
6684 | int access_type, ARMMMUIdx mmu_idx, | |
6685 | hwaddr *phys_ptr, int *prot, | |
e14b5a23 EI |
6686 | target_ulong *page_size, uint32_t *fsr, |
6687 | ARMMMUFaultInfo *fi) | |
b5ff1b31 | 6688 | { |
70d74660 | 6689 | CPUState *cs = CPU(arm_env_get_cpu(env)); |
b5ff1b31 FB |
6690 | int code; |
6691 | uint32_t table; | |
6692 | uint32_t desc; | |
6693 | int type; | |
6694 | int ap; | |
e389be16 | 6695 | int domain = 0; |
dd4ebc2e | 6696 | int domain_prot; |
a8170e5e | 6697 | hwaddr phys_addr; |
0480f69a | 6698 | uint32_t dacr; |
b5ff1b31 | 6699 | |
9ee6e8bb PB |
6700 | /* Pagetable walk. */ |
6701 | /* Lookup l1 descriptor. */ | |
0480f69a | 6702 | if (!get_level1_table_address(env, mmu_idx, &table, address)) { |
e389be16 FA |
6703 | /* Section translation fault if page walk is disabled by PD0 or PD1 */ |
6704 | code = 5; | |
6705 | goto do_fault; | |
6706 | } | |
a614e698 EI |
6707 | desc = arm_ldl_ptw(cs, table, regime_is_secure(env, mmu_idx), |
6708 | mmu_idx, fsr, fi); | |
9ee6e8bb | 6709 | type = (desc & 3); |
dd4ebc2e | 6710 | domain = (desc >> 5) & 0x0f; |
0480f69a PM |
6711 | if (regime_el(env, mmu_idx) == 1) { |
6712 | dacr = env->cp15.dacr_ns; | |
6713 | } else { | |
6714 | dacr = env->cp15.dacr_s; | |
6715 | } | |
6716 | domain_prot = (dacr >> (domain * 2)) & 3; | |
9ee6e8bb | 6717 | if (type == 0) { |
601d70b9 | 6718 | /* Section translation fault. */ |
9ee6e8bb PB |
6719 | code = 5; |
6720 | goto do_fault; | |
6721 | } | |
dd4ebc2e | 6722 | if (domain_prot == 0 || domain_prot == 2) { |
9ee6e8bb PB |
6723 | if (type == 2) |
6724 | code = 9; /* Section domain fault. */ | |
6725 | else | |
6726 | code = 11; /* Page domain fault. */ | |
6727 | goto do_fault; | |
6728 | } | |
6729 | if (type == 2) { | |
6730 | /* 1Mb section. */ | |
6731 | phys_addr = (desc & 0xfff00000) | (address & 0x000fffff); | |
6732 | ap = (desc >> 10) & 3; | |
6733 | code = 13; | |
d4c430a8 | 6734 | *page_size = 1024 * 1024; |
9ee6e8bb PB |
6735 | } else { |
6736 | /* Lookup l2 entry. */ | |
554b0b09 PM |
6737 | if (type == 1) { |
6738 | /* Coarse pagetable. */ | |
6739 | table = (desc & 0xfffffc00) | ((address >> 10) & 0x3fc); | |
6740 | } else { | |
6741 | /* Fine pagetable. */ | |
6742 | table = (desc & 0xfffff000) | ((address >> 8) & 0xffc); | |
6743 | } | |
a614e698 EI |
6744 | desc = arm_ldl_ptw(cs, table, regime_is_secure(env, mmu_idx), |
6745 | mmu_idx, fsr, fi); | |
9ee6e8bb PB |
6746 | switch (desc & 3) { |
6747 | case 0: /* Page translation fault. */ | |
6748 | code = 7; | |
6749 | goto do_fault; | |
6750 | case 1: /* 64k page. */ | |
6751 | phys_addr = (desc & 0xffff0000) | (address & 0xffff); | |
6752 | ap = (desc >> (4 + ((address >> 13) & 6))) & 3; | |
d4c430a8 | 6753 | *page_size = 0x10000; |
ce819861 | 6754 | break; |
9ee6e8bb PB |
6755 | case 2: /* 4k page. */ |
6756 | phys_addr = (desc & 0xfffff000) | (address & 0xfff); | |
c10f7fc3 | 6757 | ap = (desc >> (4 + ((address >> 9) & 6))) & 3; |
d4c430a8 | 6758 | *page_size = 0x1000; |
ce819861 | 6759 | break; |
fc1891c7 | 6760 | case 3: /* 1k page, or ARMv6/XScale "extended small (4k) page" */ |
554b0b09 | 6761 | if (type == 1) { |
fc1891c7 PM |
6762 | /* ARMv6/XScale extended small page format */ |
6763 | if (arm_feature(env, ARM_FEATURE_XSCALE) | |
6764 | || arm_feature(env, ARM_FEATURE_V6)) { | |
554b0b09 | 6765 | phys_addr = (desc & 0xfffff000) | (address & 0xfff); |
fc1891c7 | 6766 | *page_size = 0x1000; |
554b0b09 | 6767 | } else { |
fc1891c7 PM |
6768 | /* UNPREDICTABLE in ARMv5; we choose to take a |
6769 | * page translation fault. | |
6770 | */ | |
554b0b09 PM |
6771 | code = 7; |
6772 | goto do_fault; | |
6773 | } | |
6774 | } else { | |
6775 | phys_addr = (desc & 0xfffffc00) | (address & 0x3ff); | |
fc1891c7 | 6776 | *page_size = 0x400; |
554b0b09 | 6777 | } |
9ee6e8bb | 6778 | ap = (desc >> 4) & 3; |
ce819861 PB |
6779 | break; |
6780 | default: | |
9ee6e8bb PB |
6781 | /* Never happens, but compiler isn't smart enough to tell. */ |
6782 | abort(); | |
ce819861 | 6783 | } |
9ee6e8bb PB |
6784 | code = 15; |
6785 | } | |
0fbf5238 AJ |
6786 | *prot = ap_to_rw_prot(env, mmu_idx, ap, domain_prot); |
6787 | *prot |= *prot ? PAGE_EXEC : 0; | |
6788 | if (!(*prot & (1 << access_type))) { | |
9ee6e8bb PB |
6789 | /* Access permission fault. */ |
6790 | goto do_fault; | |
6791 | } | |
6792 | *phys_ptr = phys_addr; | |
b7cc4e82 | 6793 | return false; |
9ee6e8bb | 6794 | do_fault: |
b7cc4e82 PC |
6795 | *fsr = code | (domain << 4); |
6796 | return true; | |
9ee6e8bb PB |
6797 | } |
6798 | ||
b7cc4e82 PC |
6799 | static bool get_phys_addr_v6(CPUARMState *env, uint32_t address, |
6800 | int access_type, ARMMMUIdx mmu_idx, | |
6801 | hwaddr *phys_ptr, MemTxAttrs *attrs, int *prot, | |
e14b5a23 EI |
6802 | target_ulong *page_size, uint32_t *fsr, |
6803 | ARMMMUFaultInfo *fi) | |
9ee6e8bb | 6804 | { |
70d74660 | 6805 | CPUState *cs = CPU(arm_env_get_cpu(env)); |
9ee6e8bb PB |
6806 | int code; |
6807 | uint32_t table; | |
6808 | uint32_t desc; | |
6809 | uint32_t xn; | |
de9b05b8 | 6810 | uint32_t pxn = 0; |
9ee6e8bb PB |
6811 | int type; |
6812 | int ap; | |
de9b05b8 | 6813 | int domain = 0; |
dd4ebc2e | 6814 | int domain_prot; |
a8170e5e | 6815 | hwaddr phys_addr; |
0480f69a | 6816 | uint32_t dacr; |
8bf5b6a9 | 6817 | bool ns; |
9ee6e8bb PB |
6818 | |
6819 | /* Pagetable walk. */ | |
6820 | /* Lookup l1 descriptor. */ | |
0480f69a | 6821 | if (!get_level1_table_address(env, mmu_idx, &table, address)) { |
e389be16 FA |
6822 | /* Section translation fault if page walk is disabled by PD0 or PD1 */ |
6823 | code = 5; | |
6824 | goto do_fault; | |
6825 | } | |
a614e698 EI |
6826 | desc = arm_ldl_ptw(cs, table, regime_is_secure(env, mmu_idx), |
6827 | mmu_idx, fsr, fi); | |
9ee6e8bb | 6828 | type = (desc & 3); |
de9b05b8 PM |
6829 | if (type == 0 || (type == 3 && !arm_feature(env, ARM_FEATURE_PXN))) { |
6830 | /* Section translation fault, or attempt to use the encoding | |
6831 | * which is Reserved on implementations without PXN. | |
6832 | */ | |
9ee6e8bb | 6833 | code = 5; |
9ee6e8bb | 6834 | goto do_fault; |
de9b05b8 PM |
6835 | } |
6836 | if ((type == 1) || !(desc & (1 << 18))) { | |
6837 | /* Page or Section. */ | |
dd4ebc2e | 6838 | domain = (desc >> 5) & 0x0f; |
9ee6e8bb | 6839 | } |
0480f69a PM |
6840 | if (regime_el(env, mmu_idx) == 1) { |
6841 | dacr = env->cp15.dacr_ns; | |
6842 | } else { | |
6843 | dacr = env->cp15.dacr_s; | |
6844 | } | |
6845 | domain_prot = (dacr >> (domain * 2)) & 3; | |
dd4ebc2e | 6846 | if (domain_prot == 0 || domain_prot == 2) { |
de9b05b8 | 6847 | if (type != 1) { |
9ee6e8bb | 6848 | code = 9; /* Section domain fault. */ |
de9b05b8 | 6849 | } else { |
9ee6e8bb | 6850 | code = 11; /* Page domain fault. */ |
de9b05b8 | 6851 | } |
9ee6e8bb PB |
6852 | goto do_fault; |
6853 | } | |
de9b05b8 | 6854 | if (type != 1) { |
9ee6e8bb PB |
6855 | if (desc & (1 << 18)) { |
6856 | /* Supersection. */ | |
6857 | phys_addr = (desc & 0xff000000) | (address & 0x00ffffff); | |
4e42a6ca SF |
6858 | phys_addr |= (uint64_t)extract32(desc, 20, 4) << 32; |
6859 | phys_addr |= (uint64_t)extract32(desc, 5, 4) << 36; | |
d4c430a8 | 6860 | *page_size = 0x1000000; |
b5ff1b31 | 6861 | } else { |
9ee6e8bb PB |
6862 | /* Section. */ |
6863 | phys_addr = (desc & 0xfff00000) | (address & 0x000fffff); | |
d4c430a8 | 6864 | *page_size = 0x100000; |
b5ff1b31 | 6865 | } |
9ee6e8bb PB |
6866 | ap = ((desc >> 10) & 3) | ((desc >> 13) & 4); |
6867 | xn = desc & (1 << 4); | |
de9b05b8 | 6868 | pxn = desc & 1; |
9ee6e8bb | 6869 | code = 13; |
8bf5b6a9 | 6870 | ns = extract32(desc, 19, 1); |
9ee6e8bb | 6871 | } else { |
de9b05b8 PM |
6872 | if (arm_feature(env, ARM_FEATURE_PXN)) { |
6873 | pxn = (desc >> 2) & 1; | |
6874 | } | |
8bf5b6a9 | 6875 | ns = extract32(desc, 3, 1); |
9ee6e8bb PB |
6876 | /* Lookup l2 entry. */ |
6877 | table = (desc & 0xfffffc00) | ((address >> 10) & 0x3fc); | |
a614e698 EI |
6878 | desc = arm_ldl_ptw(cs, table, regime_is_secure(env, mmu_idx), |
6879 | mmu_idx, fsr, fi); | |
9ee6e8bb PB |
6880 | ap = ((desc >> 4) & 3) | ((desc >> 7) & 4); |
6881 | switch (desc & 3) { | |
6882 | case 0: /* Page translation fault. */ | |
6883 | code = 7; | |
b5ff1b31 | 6884 | goto do_fault; |
9ee6e8bb PB |
6885 | case 1: /* 64k page. */ |
6886 | phys_addr = (desc & 0xffff0000) | (address & 0xffff); | |
6887 | xn = desc & (1 << 15); | |
d4c430a8 | 6888 | *page_size = 0x10000; |
9ee6e8bb PB |
6889 | break; |
6890 | case 2: case 3: /* 4k page. */ | |
6891 | phys_addr = (desc & 0xfffff000) | (address & 0xfff); | |
6892 | xn = desc & 1; | |
d4c430a8 | 6893 | *page_size = 0x1000; |
9ee6e8bb PB |
6894 | break; |
6895 | default: | |
6896 | /* Never happens, but compiler isn't smart enough to tell. */ | |
6897 | abort(); | |
b5ff1b31 | 6898 | } |
9ee6e8bb PB |
6899 | code = 15; |
6900 | } | |
dd4ebc2e | 6901 | if (domain_prot == 3) { |
c0034328 JR |
6902 | *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; |
6903 | } else { | |
0480f69a | 6904 | if (pxn && !regime_is_user(env, mmu_idx)) { |
de9b05b8 PM |
6905 | xn = 1; |
6906 | } | |
c0034328 JR |
6907 | if (xn && access_type == 2) |
6908 | goto do_fault; | |
9ee6e8bb | 6909 | |
d76951b6 AJ |
6910 | if (arm_feature(env, ARM_FEATURE_V6K) && |
6911 | (regime_sctlr(env, mmu_idx) & SCTLR_AFE)) { | |
6912 | /* The simplified model uses AP[0] as an access control bit. */ | |
6913 | if ((ap & 1) == 0) { | |
6914 | /* Access flag fault. */ | |
6915 | code = (code == 15) ? 6 : 3; | |
6916 | goto do_fault; | |
6917 | } | |
6918 | *prot = simple_ap_to_rw_prot(env, mmu_idx, ap >> 1); | |
6919 | } else { | |
6920 | *prot = ap_to_rw_prot(env, mmu_idx, ap, domain_prot); | |
c0034328 | 6921 | } |
0fbf5238 AJ |
6922 | if (*prot && !xn) { |
6923 | *prot |= PAGE_EXEC; | |
6924 | } | |
6925 | if (!(*prot & (1 << access_type))) { | |
c0034328 JR |
6926 | /* Access permission fault. */ |
6927 | goto do_fault; | |
6928 | } | |
3ad493fc | 6929 | } |
8bf5b6a9 PM |
6930 | if (ns) { |
6931 | /* The NS bit will (as required by the architecture) have no effect if | |
6932 | * the CPU doesn't support TZ or this is a non-secure translation | |
6933 | * regime, because the attribute will already be non-secure. | |
6934 | */ | |
6935 | attrs->secure = false; | |
6936 | } | |
9ee6e8bb | 6937 | *phys_ptr = phys_addr; |
b7cc4e82 | 6938 | return false; |
b5ff1b31 | 6939 | do_fault: |
b7cc4e82 PC |
6940 | *fsr = code | (domain << 4); |
6941 | return true; | |
b5ff1b31 FB |
6942 | } |
6943 | ||
3dde962f PM |
6944 | /* Fault type for long-descriptor MMU fault reporting; this corresponds |
6945 | * to bits [5..2] in the STATUS field in long-format DFSR/IFSR. | |
6946 | */ | |
6947 | typedef enum { | |
6948 | translation_fault = 1, | |
6949 | access_fault = 2, | |
6950 | permission_fault = 3, | |
6951 | } MMUFaultType; | |
6952 | ||
1853d5a9 | 6953 | /* |
a0e966c9 | 6954 | * check_s2_mmu_setup |
1853d5a9 EI |
6955 | * @cpu: ARMCPU |
6956 | * @is_aa64: True if the translation regime is in AArch64 state | |
6957 | * @startlevel: Suggested starting level | |
6958 | * @inputsize: Bitsize of IPAs | |
6959 | * @stride: Page-table stride (See the ARM ARM) | |
6960 | * | |
a0e966c9 EI |
6961 | * Returns true if the suggested S2 translation parameters are OK and |
6962 | * false otherwise. | |
1853d5a9 | 6963 | */ |
a0e966c9 EI |
6964 | static bool check_s2_mmu_setup(ARMCPU *cpu, bool is_aa64, int level, |
6965 | int inputsize, int stride) | |
1853d5a9 | 6966 | { |
98d68ec2 EI |
6967 | const int grainsize = stride + 3; |
6968 | int startsizecheck; | |
6969 | ||
1853d5a9 EI |
6970 | /* Negative levels are never allowed. */ |
6971 | if (level < 0) { | |
6972 | return false; | |
6973 | } | |
6974 | ||
98d68ec2 EI |
6975 | startsizecheck = inputsize - ((3 - level) * stride + grainsize); |
6976 | if (startsizecheck < 1 || startsizecheck > stride + 4) { | |
6977 | return false; | |
6978 | } | |
6979 | ||
1853d5a9 | 6980 | if (is_aa64) { |
3526423e | 6981 | CPUARMState *env = &cpu->env; |
1853d5a9 EI |
6982 | unsigned int pamax = arm_pamax(cpu); |
6983 | ||
6984 | switch (stride) { | |
6985 | case 13: /* 64KB Pages. */ | |
6986 | if (level == 0 || (level == 1 && pamax <= 42)) { | |
6987 | return false; | |
6988 | } | |
6989 | break; | |
6990 | case 11: /* 16KB Pages. */ | |
6991 | if (level == 0 || (level == 1 && pamax <= 40)) { | |
6992 | return false; | |
6993 | } | |
6994 | break; | |
6995 | case 9: /* 4KB Pages. */ | |
6996 | if (level == 0 && pamax <= 42) { | |
6997 | return false; | |
6998 | } | |
6999 | break; | |
7000 | default: | |
7001 | g_assert_not_reached(); | |
7002 | } | |
3526423e EI |
7003 | |
7004 | /* Inputsize checks. */ | |
7005 | if (inputsize > pamax && | |
7006 | (arm_el_is_aa64(env, 1) || inputsize > 40)) { | |
7007 | /* This is CONSTRAINED UNPREDICTABLE and we choose to fault. */ | |
7008 | return false; | |
7009 | } | |
1853d5a9 | 7010 | } else { |
1853d5a9 EI |
7011 | /* AArch32 only supports 4KB pages. Assert on that. */ |
7012 | assert(stride == 9); | |
7013 | ||
7014 | if (level == 0) { | |
7015 | return false; | |
7016 | } | |
1853d5a9 EI |
7017 | } |
7018 | return true; | |
7019 | } | |
7020 | ||
b7cc4e82 PC |
7021 | static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address, |
7022 | int access_type, ARMMMUIdx mmu_idx, | |
7023 | hwaddr *phys_ptr, MemTxAttrs *txattrs, int *prot, | |
e14b5a23 EI |
7024 | target_ulong *page_size_ptr, uint32_t *fsr, |
7025 | ARMMMUFaultInfo *fi) | |
3dde962f | 7026 | { |
1853d5a9 EI |
7027 | ARMCPU *cpu = arm_env_get_cpu(env); |
7028 | CPUState *cs = CPU(cpu); | |
3dde962f PM |
7029 | /* Read an LPAE long-descriptor translation table. */ |
7030 | MMUFaultType fault_type = translation_fault; | |
7031 | uint32_t level = 1; | |
0c5fbf3b | 7032 | uint32_t epd = 0; |
1f4c8c18 | 7033 | int32_t t0sz, t1sz; |
2c8dd318 | 7034 | uint32_t tg; |
3dde962f PM |
7035 | uint64_t ttbr; |
7036 | int ttbr_select; | |
2c8dd318 | 7037 | hwaddr descaddr, descmask; |
3dde962f PM |
7038 | uint32_t tableattrs; |
7039 | target_ulong page_size; | |
7040 | uint32_t attrs; | |
973a5434 | 7041 | int32_t stride = 9; |
2c8dd318 | 7042 | int32_t va_size = 32; |
4ca6a051 | 7043 | int inputsize; |
2c8dd318 | 7044 | int32_t tbi = 0; |
0480f69a | 7045 | TCR *tcr = regime_tcr(env, mmu_idx); |
d8e052b3 | 7046 | int ap, ns, xn, pxn; |
88e8add8 GB |
7047 | uint32_t el = regime_el(env, mmu_idx); |
7048 | bool ttbr1_valid = true; | |
6109769a | 7049 | uint64_t descaddrmask; |
0480f69a PM |
7050 | |
7051 | /* TODO: | |
88e8add8 GB |
7052 | * This code does not handle the different format TCR for VTCR_EL2. |
7053 | * This code also does not support shareability levels. | |
7054 | * Attribute and permission bit handling should also be checked when adding | |
7055 | * support for those page table walks. | |
0480f69a | 7056 | */ |
88e8add8 | 7057 | if (arm_el_is_aa64(env, el)) { |
2c8dd318 | 7058 | va_size = 64; |
88e8add8 | 7059 | if (el > 1) { |
1edee470 EI |
7060 | if (mmu_idx != ARMMMUIdx_S2NS) { |
7061 | tbi = extract64(tcr->raw_tcr, 20, 1); | |
7062 | } | |
88e8add8 GB |
7063 | } else { |
7064 | if (extract64(address, 55, 1)) { | |
7065 | tbi = extract64(tcr->raw_tcr, 38, 1); | |
7066 | } else { | |
7067 | tbi = extract64(tcr->raw_tcr, 37, 1); | |
7068 | } | |
7069 | } | |
2c8dd318 | 7070 | tbi *= 8; |
88e8add8 GB |
7071 | |
7072 | /* If we are in 64-bit EL2 or EL3 then there is no TTBR1, so mark it | |
7073 | * invalid. | |
7074 | */ | |
7075 | if (el > 1) { | |
7076 | ttbr1_valid = false; | |
7077 | } | |
d0a2cbce PM |
7078 | } else { |
7079 | /* There is no TTBR1 for EL2 */ | |
7080 | if (el == 2) { | |
7081 | ttbr1_valid = false; | |
7082 | } | |
2c8dd318 | 7083 | } |
3dde962f PM |
7084 | |
7085 | /* Determine whether this address is in the region controlled by | |
7086 | * TTBR0 or TTBR1 (or if it is in neither region and should fault). | |
7087 | * This is a Non-secure PL0/1 stage 1 translation, so controlled by | |
7088 | * TTBCR/TTBR0/TTBR1 in accordance with ARM ARM DDI0406C table B-32: | |
7089 | */ | |
0480f69a | 7090 | if (va_size == 64) { |
4ee38098 EI |
7091 | /* AArch64 translation. */ |
7092 | t0sz = extract32(tcr->raw_tcr, 0, 6); | |
2c8dd318 RH |
7093 | t0sz = MIN(t0sz, 39); |
7094 | t0sz = MAX(t0sz, 16); | |
4ee38098 EI |
7095 | } else if (mmu_idx != ARMMMUIdx_S2NS) { |
7096 | /* AArch32 stage 1 translation. */ | |
7097 | t0sz = extract32(tcr->raw_tcr, 0, 3); | |
7098 | } else { | |
7099 | /* AArch32 stage 2 translation. */ | |
7100 | bool sext = extract32(tcr->raw_tcr, 4, 1); | |
7101 | bool sign = extract32(tcr->raw_tcr, 3, 1); | |
7102 | t0sz = sextract32(tcr->raw_tcr, 0, 4); | |
7103 | ||
7104 | /* If the sign-extend bit is not the same as t0sz[3], the result | |
7105 | * is unpredictable. Flag this as a guest error. */ | |
7106 | if (sign != sext) { | |
7107 | qemu_log_mask(LOG_GUEST_ERROR, | |
7108 | "AArch32: VTCR.S / VTCR.T0SZ[3] missmatch\n"); | |
7109 | } | |
2c8dd318 | 7110 | } |
1f4c8c18 | 7111 | t1sz = extract32(tcr->raw_tcr, 16, 6); |
0480f69a | 7112 | if (va_size == 64) { |
2c8dd318 RH |
7113 | t1sz = MIN(t1sz, 39); |
7114 | t1sz = MAX(t1sz, 16); | |
7115 | } | |
7116 | if (t0sz && !extract64(address, va_size - t0sz, t0sz - tbi)) { | |
3dde962f PM |
7117 | /* there is a ttbr0 region and we are in it (high bits all zero) */ |
7118 | ttbr_select = 0; | |
88e8add8 GB |
7119 | } else if (ttbr1_valid && t1sz && |
7120 | !extract64(~address, va_size - t1sz, t1sz - tbi)) { | |
3dde962f PM |
7121 | /* there is a ttbr1 region and we are in it (high bits all one) */ |
7122 | ttbr_select = 1; | |
7123 | } else if (!t0sz) { | |
7124 | /* ttbr0 region is "everything not in the ttbr1 region" */ | |
7125 | ttbr_select = 0; | |
88e8add8 | 7126 | } else if (!t1sz && ttbr1_valid) { |
3dde962f PM |
7127 | /* ttbr1 region is "everything not in the ttbr0 region" */ |
7128 | ttbr_select = 1; | |
7129 | } else { | |
7130 | /* in the gap between the two regions, this is a Translation fault */ | |
7131 | fault_type = translation_fault; | |
7132 | goto do_fault; | |
7133 | } | |
7134 | ||
7135 | /* Note that QEMU ignores shareability and cacheability attributes, | |
7136 | * so we don't need to do anything with the SH, ORGN, IRGN fields | |
7137 | * in the TTBCR. Similarly, TTBCR:A1 selects whether we get the | |
7138 | * ASID from TTBR0 or TTBR1, but QEMU's TLB doesn't currently | |
7139 | * implement any ASID-like capability so we can ignore it (instead | |
7140 | * we will always flush the TLB any time the ASID is changed). | |
7141 | */ | |
7142 | if (ttbr_select == 0) { | |
aef878be | 7143 | ttbr = regime_ttbr(env, mmu_idx, 0); |
0c5fbf3b EI |
7144 | if (el < 2) { |
7145 | epd = extract32(tcr->raw_tcr, 7, 1); | |
7146 | } | |
4ca6a051 | 7147 | inputsize = va_size - t0sz; |
2c8dd318 | 7148 | |
11f136ee | 7149 | tg = extract32(tcr->raw_tcr, 14, 2); |
2c8dd318 | 7150 | if (tg == 1) { /* 64KB pages */ |
973a5434 | 7151 | stride = 13; |
2c8dd318 RH |
7152 | } |
7153 | if (tg == 2) { /* 16KB pages */ | |
973a5434 | 7154 | stride = 11; |
2c8dd318 | 7155 | } |
3dde962f | 7156 | } else { |
88e8add8 GB |
7157 | /* We should only be here if TTBR1 is valid */ |
7158 | assert(ttbr1_valid); | |
7159 | ||
aef878be | 7160 | ttbr = regime_ttbr(env, mmu_idx, 1); |
11f136ee | 7161 | epd = extract32(tcr->raw_tcr, 23, 1); |
4ca6a051 | 7162 | inputsize = va_size - t1sz; |
2c8dd318 | 7163 | |
11f136ee | 7164 | tg = extract32(tcr->raw_tcr, 30, 2); |
2c8dd318 | 7165 | if (tg == 3) { /* 64KB pages */ |
973a5434 | 7166 | stride = 13; |
2c8dd318 RH |
7167 | } |
7168 | if (tg == 1) { /* 16KB pages */ | |
973a5434 | 7169 | stride = 11; |
2c8dd318 | 7170 | } |
3dde962f PM |
7171 | } |
7172 | ||
0480f69a | 7173 | /* Here we should have set up all the parameters for the translation: |
973a5434 | 7174 | * va_size, inputsize, ttbr, epd, stride, tbi |
0480f69a PM |
7175 | */ |
7176 | ||
3dde962f | 7177 | if (epd) { |
88e8add8 GB |
7178 | /* Translation table walk disabled => Translation fault on TLB miss |
7179 | * Note: This is always 0 on 64-bit EL2 and EL3. | |
7180 | */ | |
3dde962f PM |
7181 | goto do_fault; |
7182 | } | |
7183 | ||
1853d5a9 EI |
7184 | if (mmu_idx != ARMMMUIdx_S2NS) { |
7185 | /* The starting level depends on the virtual address size (which can | |
7186 | * be up to 48 bits) and the translation granule size. It indicates | |
7187 | * the number of strides (stride bits at a time) needed to | |
7188 | * consume the bits of the input address. In the pseudocode this is: | |
7189 | * level = 4 - RoundUp((inputsize - grainsize) / stride) | |
7190 | * where their 'inputsize' is our 'inputsize', 'grainsize' is | |
7191 | * our 'stride + 3' and 'stride' is our 'stride'. | |
7192 | * Applying the usual "rounded up m/n is (m+n-1)/n" and simplifying: | |
7193 | * = 4 - (inputsize - stride - 3 + stride - 1) / stride | |
7194 | * = 4 - (inputsize - 4) / stride; | |
7195 | */ | |
7196 | level = 4 - (inputsize - 4) / stride; | |
7197 | } else { | |
7198 | /* For stage 2 translations the starting level is specified by the | |
7199 | * VTCR_EL2.SL0 field (whose interpretation depends on the page size) | |
7200 | */ | |
7201 | int startlevel = extract32(tcr->raw_tcr, 6, 2); | |
7202 | bool ok; | |
7203 | ||
7204 | if (va_size == 32 || stride == 9) { | |
7205 | /* AArch32 or 4KB pages */ | |
7206 | level = 2 - startlevel; | |
7207 | } else { | |
7208 | /* 16KB or 64KB pages */ | |
7209 | level = 3 - startlevel; | |
7210 | } | |
7211 | ||
7212 | /* Check that the starting level is valid. */ | |
a0e966c9 | 7213 | ok = check_s2_mmu_setup(cpu, va_size == 64, level, inputsize, stride); |
1853d5a9 EI |
7214 | if (!ok) { |
7215 | /* AArch64 reports these as level 0 faults. | |
7216 | * AArch32 reports these as level 1 faults. | |
7217 | */ | |
7218 | level = va_size == 64 ? 0 : 1; | |
7219 | fault_type = translation_fault; | |
7220 | goto do_fault; | |
7221 | } | |
7222 | } | |
3dde962f PM |
7223 | |
7224 | /* Clear the vaddr bits which aren't part of the within-region address, | |
7225 | * so that we don't have to special case things when calculating the | |
7226 | * first descriptor address. | |
7227 | */ | |
4ca6a051 EI |
7228 | if (va_size != inputsize) { |
7229 | address &= (1ULL << inputsize) - 1; | |
2c8dd318 RH |
7230 | } |
7231 | ||
973a5434 | 7232 | descmask = (1ULL << (stride + 3)) - 1; |
3dde962f PM |
7233 | |
7234 | /* Now we can extract the actual base address from the TTBR */ | |
2c8dd318 | 7235 | descaddr = extract64(ttbr, 0, 48); |
973a5434 | 7236 | descaddr &= ~((1ULL << (inputsize - (stride * (4 - level)))) - 1); |
3dde962f | 7237 | |
6109769a PM |
7238 | /* The address field in the descriptor goes up to bit 39 for ARMv7 |
7239 | * but up to bit 47 for ARMv8. | |
7240 | */ | |
7241 | if (arm_feature(env, ARM_FEATURE_V8)) { | |
7242 | descaddrmask = 0xfffffffff000ULL; | |
7243 | } else { | |
7244 | descaddrmask = 0xfffffff000ULL; | |
7245 | } | |
7246 | ||
ebca90e4 PM |
7247 | /* Secure accesses start with the page table in secure memory and |
7248 | * can be downgraded to non-secure at any step. Non-secure accesses | |
7249 | * remain non-secure. We implement this by just ORing in the NSTable/NS | |
7250 | * bits at each step. | |
7251 | */ | |
7252 | tableattrs = regime_is_secure(env, mmu_idx) ? 0 : (1 << 4); | |
3dde962f PM |
7253 | for (;;) { |
7254 | uint64_t descriptor; | |
ebca90e4 | 7255 | bool nstable; |
3dde962f | 7256 | |
973a5434 | 7257 | descaddr |= (address >> (stride * (4 - level))) & descmask; |
2c8dd318 | 7258 | descaddr &= ~7ULL; |
ebca90e4 | 7259 | nstable = extract32(tableattrs, 4, 1); |
37785977 EI |
7260 | descriptor = arm_ldq_ptw(cs, descaddr, !nstable, mmu_idx, fsr, fi); |
7261 | if (fi->s1ptw) { | |
7262 | goto do_fault; | |
7263 | } | |
7264 | ||
3dde962f PM |
7265 | if (!(descriptor & 1) || |
7266 | (!(descriptor & 2) && (level == 3))) { | |
7267 | /* Invalid, or the Reserved level 3 encoding */ | |
7268 | goto do_fault; | |
7269 | } | |
6109769a | 7270 | descaddr = descriptor & descaddrmask; |
3dde962f PM |
7271 | |
7272 | if ((descriptor & 2) && (level < 3)) { | |
7273 | /* Table entry. The top five bits are attributes which may | |
7274 | * propagate down through lower levels of the table (and | |
7275 | * which are all arranged so that 0 means "no effect", so | |
7276 | * we can gather them up by ORing in the bits at each level). | |
7277 | */ | |
7278 | tableattrs |= extract64(descriptor, 59, 5); | |
7279 | level++; | |
7280 | continue; | |
7281 | } | |
7282 | /* Block entry at level 1 or 2, or page entry at level 3. | |
7283 | * These are basically the same thing, although the number | |
7284 | * of bits we pull in from the vaddr varies. | |
7285 | */ | |
973a5434 | 7286 | page_size = (1ULL << ((stride * (4 - level)) + 3)); |
3dde962f | 7287 | descaddr |= (address & (page_size - 1)); |
6ab1a5ee | 7288 | /* Extract attributes from the descriptor */ |
d615efac IC |
7289 | attrs = extract64(descriptor, 2, 10) |
7290 | | (extract64(descriptor, 52, 12) << 10); | |
6ab1a5ee EI |
7291 | |
7292 | if (mmu_idx == ARMMMUIdx_S2NS) { | |
7293 | /* Stage 2 table descriptors do not include any attribute fields */ | |
7294 | break; | |
7295 | } | |
7296 | /* Merge in attributes from table descriptors */ | |
3dde962f PM |
7297 | attrs |= extract32(tableattrs, 0, 2) << 11; /* XN, PXN */ |
7298 | attrs |= extract32(tableattrs, 3, 1) << 5; /* APTable[1] => AP[2] */ | |
7299 | /* The sense of AP[1] vs APTable[0] is reversed, as APTable[0] == 1 | |
7300 | * means "force PL1 access only", which means forcing AP[1] to 0. | |
7301 | */ | |
7302 | if (extract32(tableattrs, 2, 1)) { | |
7303 | attrs &= ~(1 << 4); | |
7304 | } | |
ebca90e4 | 7305 | attrs |= nstable << 3; /* NS */ |
3dde962f PM |
7306 | break; |
7307 | } | |
7308 | /* Here descaddr is the final physical address, and attributes | |
7309 | * are all in attrs. | |
7310 | */ | |
7311 | fault_type = access_fault; | |
7312 | if ((attrs & (1 << 8)) == 0) { | |
7313 | /* Access flag */ | |
7314 | goto do_fault; | |
7315 | } | |
d8e052b3 AJ |
7316 | |
7317 | ap = extract32(attrs, 4, 2); | |
d8e052b3 | 7318 | xn = extract32(attrs, 12, 1); |
d8e052b3 | 7319 | |
6ab1a5ee EI |
7320 | if (mmu_idx == ARMMMUIdx_S2NS) { |
7321 | ns = true; | |
7322 | *prot = get_S2prot(env, ap, xn); | |
7323 | } else { | |
7324 | ns = extract32(attrs, 3, 1); | |
7325 | pxn = extract32(attrs, 11, 1); | |
7326 | *prot = get_S1prot(env, mmu_idx, va_size == 64, ap, ns, xn, pxn); | |
7327 | } | |
d8e052b3 | 7328 | |
3dde962f | 7329 | fault_type = permission_fault; |
d8e052b3 | 7330 | if (!(*prot & (1 << access_type))) { |
3dde962f PM |
7331 | goto do_fault; |
7332 | } | |
3dde962f | 7333 | |
8bf5b6a9 PM |
7334 | if (ns) { |
7335 | /* The NS bit will (as required by the architecture) have no effect if | |
7336 | * the CPU doesn't support TZ or this is a non-secure translation | |
7337 | * regime, because the attribute will already be non-secure. | |
7338 | */ | |
7339 | txattrs->secure = false; | |
7340 | } | |
3dde962f PM |
7341 | *phys_ptr = descaddr; |
7342 | *page_size_ptr = page_size; | |
b7cc4e82 | 7343 | return false; |
3dde962f PM |
7344 | |
7345 | do_fault: | |
7346 | /* Long-descriptor format IFSR/DFSR value */ | |
b7cc4e82 | 7347 | *fsr = (1 << 9) | (fault_type << 2) | level; |
37785977 EI |
7348 | /* Tag the error as S2 for failed S1 PTW at S2 or ordinary S2. */ |
7349 | fi->stage2 = fi->s1ptw || (mmu_idx == ARMMMUIdx_S2NS); | |
b7cc4e82 | 7350 | return true; |
3dde962f PM |
7351 | } |
7352 | ||
f6bda88f PC |
7353 | static inline void get_phys_addr_pmsav7_default(CPUARMState *env, |
7354 | ARMMMUIdx mmu_idx, | |
7355 | int32_t address, int *prot) | |
7356 | { | |
7357 | *prot = PAGE_READ | PAGE_WRITE; | |
7358 | switch (address) { | |
7359 | case 0xF0000000 ... 0xFFFFFFFF: | |
7360 | if (regime_sctlr(env, mmu_idx) & SCTLR_V) { /* hivecs execing is ok */ | |
7361 | *prot |= PAGE_EXEC; | |
7362 | } | |
7363 | break; | |
7364 | case 0x00000000 ... 0x7FFFFFFF: | |
7365 | *prot |= PAGE_EXEC; | |
7366 | break; | |
7367 | } | |
7368 | ||
7369 | } | |
7370 | ||
7371 | static bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address, | |
7372 | int access_type, ARMMMUIdx mmu_idx, | |
7373 | hwaddr *phys_ptr, int *prot, uint32_t *fsr) | |
7374 | { | |
7375 | ARMCPU *cpu = arm_env_get_cpu(env); | |
7376 | int n; | |
7377 | bool is_user = regime_is_user(env, mmu_idx); | |
7378 | ||
7379 | *phys_ptr = address; | |
7380 | *prot = 0; | |
7381 | ||
7382 | if (regime_translation_disabled(env, mmu_idx)) { /* MPU disabled */ | |
7383 | get_phys_addr_pmsav7_default(env, mmu_idx, address, prot); | |
7384 | } else { /* MPU enabled */ | |
7385 | for (n = (int)cpu->pmsav7_dregion - 1; n >= 0; n--) { | |
7386 | /* region search */ | |
7387 | uint32_t base = env->pmsav7.drbar[n]; | |
7388 | uint32_t rsize = extract32(env->pmsav7.drsr[n], 1, 5); | |
7389 | uint32_t rmask; | |
7390 | bool srdis = false; | |
7391 | ||
7392 | if (!(env->pmsav7.drsr[n] & 0x1)) { | |
7393 | continue; | |
7394 | } | |
7395 | ||
7396 | if (!rsize) { | |
7397 | qemu_log_mask(LOG_GUEST_ERROR, "DRSR.Rsize field can not be 0"); | |
7398 | continue; | |
7399 | } | |
7400 | rsize++; | |
7401 | rmask = (1ull << rsize) - 1; | |
7402 | ||
7403 | if (base & rmask) { | |
7404 | qemu_log_mask(LOG_GUEST_ERROR, "DRBAR %" PRIx32 " misaligned " | |
7405 | "to DRSR region size, mask = %" PRIx32, | |
7406 | base, rmask); | |
7407 | continue; | |
7408 | } | |
7409 | ||
7410 | if (address < base || address > base + rmask) { | |
7411 | continue; | |
7412 | } | |
7413 | ||
7414 | /* Region matched */ | |
7415 | ||
7416 | if (rsize >= 8) { /* no subregions for regions < 256 bytes */ | |
7417 | int i, snd; | |
7418 | uint32_t srdis_mask; | |
7419 | ||
7420 | rsize -= 3; /* sub region size (power of 2) */ | |
7421 | snd = ((address - base) >> rsize) & 0x7; | |
7422 | srdis = extract32(env->pmsav7.drsr[n], snd + 8, 1); | |
7423 | ||
7424 | srdis_mask = srdis ? 0x3 : 0x0; | |
7425 | for (i = 2; i <= 8 && rsize < TARGET_PAGE_BITS; i *= 2) { | |
7426 | /* This will check in groups of 2, 4 and then 8, whether | |
7427 | * the subregion bits are consistent. rsize is incremented | |
7428 | * back up to give the region size, considering consistent | |
7429 | * adjacent subregions as one region. Stop testing if rsize | |
7430 | * is already big enough for an entire QEMU page. | |
7431 | */ | |
7432 | int snd_rounded = snd & ~(i - 1); | |
7433 | uint32_t srdis_multi = extract32(env->pmsav7.drsr[n], | |
7434 | snd_rounded + 8, i); | |
7435 | if (srdis_mask ^ srdis_multi) { | |
7436 | break; | |
7437 | } | |
7438 | srdis_mask = (srdis_mask << i) | srdis_mask; | |
7439 | rsize++; | |
7440 | } | |
7441 | } | |
7442 | if (rsize < TARGET_PAGE_BITS) { | |
7443 | qemu_log_mask(LOG_UNIMP, "No support for MPU (sub)region" | |
7444 | "alignment of %" PRIu32 " bits. Minimum is %d\n", | |
7445 | rsize, TARGET_PAGE_BITS); | |
7446 | continue; | |
7447 | } | |
7448 | if (srdis) { | |
7449 | continue; | |
7450 | } | |
7451 | break; | |
7452 | } | |
7453 | ||
7454 | if (n == -1) { /* no hits */ | |
7455 | if (cpu->pmsav7_dregion && | |
7456 | (is_user || !(regime_sctlr(env, mmu_idx) & SCTLR_BR))) { | |
7457 | /* background fault */ | |
7458 | *fsr = 0; | |
7459 | return true; | |
7460 | } | |
7461 | get_phys_addr_pmsav7_default(env, mmu_idx, address, prot); | |
7462 | } else { /* a MPU hit! */ | |
7463 | uint32_t ap = extract32(env->pmsav7.dracr[n], 8, 3); | |
7464 | ||
7465 | if (is_user) { /* User mode AP bit decoding */ | |
7466 | switch (ap) { | |
7467 | case 0: | |
7468 | case 1: | |
7469 | case 5: | |
7470 | break; /* no access */ | |
7471 | case 3: | |
7472 | *prot |= PAGE_WRITE; | |
7473 | /* fall through */ | |
7474 | case 2: | |
7475 | case 6: | |
7476 | *prot |= PAGE_READ | PAGE_EXEC; | |
7477 | break; | |
7478 | default: | |
7479 | qemu_log_mask(LOG_GUEST_ERROR, | |
7480 | "Bad value for AP bits in DRACR %" | |
7481 | PRIx32 "\n", ap); | |
7482 | } | |
7483 | } else { /* Priv. mode AP bits decoding */ | |
7484 | switch (ap) { | |
7485 | case 0: | |
7486 | break; /* no access */ | |
7487 | case 1: | |
7488 | case 2: | |
7489 | case 3: | |
7490 | *prot |= PAGE_WRITE; | |
7491 | /* fall through */ | |
7492 | case 5: | |
7493 | case 6: | |
7494 | *prot |= PAGE_READ | PAGE_EXEC; | |
7495 | break; | |
7496 | default: | |
7497 | qemu_log_mask(LOG_GUEST_ERROR, | |
7498 | "Bad value for AP bits in DRACR %" | |
7499 | PRIx32 "\n", ap); | |
7500 | } | |
7501 | } | |
7502 | ||
7503 | /* execute never */ | |
7504 | if (env->pmsav7.dracr[n] & (1 << 12)) { | |
7505 | *prot &= ~PAGE_EXEC; | |
7506 | } | |
7507 | } | |
7508 | } | |
7509 | ||
7510 | *fsr = 0x00d; /* Permission fault */ | |
7511 | return !(*prot & (1 << access_type)); | |
7512 | } | |
7513 | ||
13689d43 PC |
7514 | static bool get_phys_addr_pmsav5(CPUARMState *env, uint32_t address, |
7515 | int access_type, ARMMMUIdx mmu_idx, | |
7516 | hwaddr *phys_ptr, int *prot, uint32_t *fsr) | |
9ee6e8bb PB |
7517 | { |
7518 | int n; | |
7519 | uint32_t mask; | |
7520 | uint32_t base; | |
0480f69a | 7521 | bool is_user = regime_is_user(env, mmu_idx); |
9ee6e8bb PB |
7522 | |
7523 | *phys_ptr = address; | |
7524 | for (n = 7; n >= 0; n--) { | |
554b0b09 | 7525 | base = env->cp15.c6_region[n]; |
87c3d486 | 7526 | if ((base & 1) == 0) { |
554b0b09 | 7527 | continue; |
87c3d486 | 7528 | } |
554b0b09 PM |
7529 | mask = 1 << ((base >> 1) & 0x1f); |
7530 | /* Keep this shift separate from the above to avoid an | |
7531 | (undefined) << 32. */ | |
7532 | mask = (mask << 1) - 1; | |
87c3d486 | 7533 | if (((base ^ address) & ~mask) == 0) { |
554b0b09 | 7534 | break; |
87c3d486 | 7535 | } |
9ee6e8bb | 7536 | } |
87c3d486 | 7537 | if (n < 0) { |
b7cc4e82 PC |
7538 | *fsr = 2; |
7539 | return true; | |
87c3d486 | 7540 | } |
9ee6e8bb PB |
7541 | |
7542 | if (access_type == 2) { | |
7e09797c | 7543 | mask = env->cp15.pmsav5_insn_ap; |
9ee6e8bb | 7544 | } else { |
7e09797c | 7545 | mask = env->cp15.pmsav5_data_ap; |
9ee6e8bb PB |
7546 | } |
7547 | mask = (mask >> (n * 4)) & 0xf; | |
7548 | switch (mask) { | |
7549 | case 0: | |
b7cc4e82 PC |
7550 | *fsr = 1; |
7551 | return true; | |
9ee6e8bb | 7552 | case 1: |
87c3d486 | 7553 | if (is_user) { |
b7cc4e82 PC |
7554 | *fsr = 1; |
7555 | return true; | |
87c3d486 | 7556 | } |
554b0b09 PM |
7557 | *prot = PAGE_READ | PAGE_WRITE; |
7558 | break; | |
9ee6e8bb | 7559 | case 2: |
554b0b09 | 7560 | *prot = PAGE_READ; |
87c3d486 | 7561 | if (!is_user) { |
554b0b09 | 7562 | *prot |= PAGE_WRITE; |
87c3d486 | 7563 | } |
554b0b09 | 7564 | break; |
9ee6e8bb | 7565 | case 3: |
554b0b09 PM |
7566 | *prot = PAGE_READ | PAGE_WRITE; |
7567 | break; | |
9ee6e8bb | 7568 | case 5: |
87c3d486 | 7569 | if (is_user) { |
b7cc4e82 PC |
7570 | *fsr = 1; |
7571 | return true; | |
87c3d486 | 7572 | } |
554b0b09 PM |
7573 | *prot = PAGE_READ; |
7574 | break; | |
9ee6e8bb | 7575 | case 6: |
554b0b09 PM |
7576 | *prot = PAGE_READ; |
7577 | break; | |
9ee6e8bb | 7578 | default: |
554b0b09 | 7579 | /* Bad permission. */ |
b7cc4e82 PC |
7580 | *fsr = 1; |
7581 | return true; | |
9ee6e8bb | 7582 | } |
3ad493fc | 7583 | *prot |= PAGE_EXEC; |
b7cc4e82 | 7584 | return false; |
9ee6e8bb PB |
7585 | } |
7586 | ||
702a9357 PM |
7587 | /* get_phys_addr - get the physical address for this virtual address |
7588 | * | |
7589 | * Find the physical address corresponding to the given virtual address, | |
7590 | * by doing a translation table walk on MMU based systems or using the | |
7591 | * MPU state on MPU based systems. | |
7592 | * | |
b7cc4e82 PC |
7593 | * Returns false if the translation was successful. Otherwise, phys_ptr, attrs, |
7594 | * prot and page_size may not be filled in, and the populated fsr value provides | |
702a9357 PM |
7595 | * information on why the translation aborted, in the format of a |
7596 | * DFSR/IFSR fault register, with the following caveats: | |
7597 | * * we honour the short vs long DFSR format differences. | |
7598 | * * the WnR bit is never set (the caller must do this). | |
f6bda88f | 7599 | * * for PSMAv5 based systems we don't bother to return a full FSR format |
702a9357 PM |
7600 | * value. |
7601 | * | |
7602 | * @env: CPUARMState | |
7603 | * @address: virtual address to get physical address for | |
7604 | * @access_type: 0 for read, 1 for write, 2 for execute | |
d3649702 | 7605 | * @mmu_idx: MMU index indicating required translation regime |
702a9357 | 7606 | * @phys_ptr: set to the physical address corresponding to the virtual address |
8bf5b6a9 | 7607 | * @attrs: set to the memory transaction attributes to use |
702a9357 PM |
7608 | * @prot: set to the permissions for the page containing phys_ptr |
7609 | * @page_size: set to the size of the page containing phys_ptr | |
b7cc4e82 | 7610 | * @fsr: set to the DFSR/IFSR value on failure |
702a9357 | 7611 | */ |
af51f566 EI |
7612 | static bool get_phys_addr(CPUARMState *env, target_ulong address, |
7613 | int access_type, ARMMMUIdx mmu_idx, | |
7614 | hwaddr *phys_ptr, MemTxAttrs *attrs, int *prot, | |
e14b5a23 EI |
7615 | target_ulong *page_size, uint32_t *fsr, |
7616 | ARMMMUFaultInfo *fi) | |
9ee6e8bb | 7617 | { |
0480f69a | 7618 | if (mmu_idx == ARMMMUIdx_S12NSE0 || mmu_idx == ARMMMUIdx_S12NSE1) { |
9b539263 EI |
7619 | /* Call ourselves recursively to do the stage 1 and then stage 2 |
7620 | * translations. | |
0480f69a | 7621 | */ |
9b539263 EI |
7622 | if (arm_feature(env, ARM_FEATURE_EL2)) { |
7623 | hwaddr ipa; | |
7624 | int s2_prot; | |
7625 | int ret; | |
7626 | ||
7627 | ret = get_phys_addr(env, address, access_type, | |
7628 | mmu_idx + ARMMMUIdx_S1NSE0, &ipa, attrs, | |
7629 | prot, page_size, fsr, fi); | |
7630 | ||
7631 | /* If S1 fails or S2 is disabled, return early. */ | |
7632 | if (ret || regime_translation_disabled(env, ARMMMUIdx_S2NS)) { | |
7633 | *phys_ptr = ipa; | |
7634 | return ret; | |
7635 | } | |
7636 | ||
7637 | /* S1 is done. Now do S2 translation. */ | |
7638 | ret = get_phys_addr_lpae(env, ipa, access_type, ARMMMUIdx_S2NS, | |
7639 | phys_ptr, attrs, &s2_prot, | |
7640 | page_size, fsr, fi); | |
7641 | fi->s2addr = ipa; | |
7642 | /* Combine the S1 and S2 perms. */ | |
7643 | *prot &= s2_prot; | |
7644 | return ret; | |
7645 | } else { | |
7646 | /* | |
7647 | * For non-EL2 CPUs a stage1+stage2 translation is just stage 1. | |
7648 | */ | |
7649 | mmu_idx += ARMMMUIdx_S1NSE0; | |
7650 | } | |
0480f69a | 7651 | } |
d3649702 | 7652 | |
8bf5b6a9 PM |
7653 | /* The page table entries may downgrade secure to non-secure, but |
7654 | * cannot upgrade an non-secure translation regime's attributes | |
7655 | * to secure. | |
7656 | */ | |
7657 | attrs->secure = regime_is_secure(env, mmu_idx); | |
0995bf8c | 7658 | attrs->user = regime_is_user(env, mmu_idx); |
8bf5b6a9 | 7659 | |
0480f69a PM |
7660 | /* Fast Context Switch Extension. This doesn't exist at all in v8. |
7661 | * In v7 and earlier it affects all stage 1 translations. | |
7662 | */ | |
7663 | if (address < 0x02000000 && mmu_idx != ARMMMUIdx_S2NS | |
7664 | && !arm_feature(env, ARM_FEATURE_V8)) { | |
7665 | if (regime_el(env, mmu_idx) == 3) { | |
7666 | address += env->cp15.fcseidr_s; | |
7667 | } else { | |
7668 | address += env->cp15.fcseidr_ns; | |
7669 | } | |
54bf36ed | 7670 | } |
9ee6e8bb | 7671 | |
f6bda88f PC |
7672 | /* pmsav7 has special handling for when MPU is disabled so call it before |
7673 | * the common MMU/MPU disabled check below. | |
7674 | */ | |
7675 | if (arm_feature(env, ARM_FEATURE_MPU) && | |
7676 | arm_feature(env, ARM_FEATURE_V7)) { | |
7677 | *page_size = TARGET_PAGE_SIZE; | |
7678 | return get_phys_addr_pmsav7(env, address, access_type, mmu_idx, | |
7679 | phys_ptr, prot, fsr); | |
7680 | } | |
7681 | ||
0480f69a | 7682 | if (regime_translation_disabled(env, mmu_idx)) { |
9ee6e8bb PB |
7683 | /* MMU/MPU disabled. */ |
7684 | *phys_ptr = address; | |
3ad493fc | 7685 | *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; |
d4c430a8 | 7686 | *page_size = TARGET_PAGE_SIZE; |
9ee6e8bb | 7687 | return 0; |
0480f69a PM |
7688 | } |
7689 | ||
7690 | if (arm_feature(env, ARM_FEATURE_MPU)) { | |
f6bda88f | 7691 | /* Pre-v7 MPU */ |
d4c430a8 | 7692 | *page_size = TARGET_PAGE_SIZE; |
13689d43 PC |
7693 | return get_phys_addr_pmsav5(env, address, access_type, mmu_idx, |
7694 | phys_ptr, prot, fsr); | |
0480f69a PM |
7695 | } |
7696 | ||
7697 | if (regime_using_lpae_format(env, mmu_idx)) { | |
7698 | return get_phys_addr_lpae(env, address, access_type, mmu_idx, phys_ptr, | |
e14b5a23 | 7699 | attrs, prot, page_size, fsr, fi); |
0480f69a PM |
7700 | } else if (regime_sctlr(env, mmu_idx) & SCTLR_XP) { |
7701 | return get_phys_addr_v6(env, address, access_type, mmu_idx, phys_ptr, | |
e14b5a23 | 7702 | attrs, prot, page_size, fsr, fi); |
9ee6e8bb | 7703 | } else { |
0480f69a | 7704 | return get_phys_addr_v5(env, address, access_type, mmu_idx, phys_ptr, |
e14b5a23 | 7705 | prot, page_size, fsr, fi); |
9ee6e8bb PB |
7706 | } |
7707 | } | |
7708 | ||
8c6084bf | 7709 | /* Walk the page table and (if the mapping exists) add the page |
b7cc4e82 PC |
7710 | * to the TLB. Return false on success, or true on failure. Populate |
7711 | * fsr with ARM DFSR/IFSR fault register format value on failure. | |
8c6084bf | 7712 | */ |
b7cc4e82 | 7713 | bool arm_tlb_fill(CPUState *cs, vaddr address, |
e14b5a23 EI |
7714 | int access_type, int mmu_idx, uint32_t *fsr, |
7715 | ARMMMUFaultInfo *fi) | |
b5ff1b31 | 7716 | { |
7510454e AF |
7717 | ARMCPU *cpu = ARM_CPU(cs); |
7718 | CPUARMState *env = &cpu->env; | |
a8170e5e | 7719 | hwaddr phys_addr; |
d4c430a8 | 7720 | target_ulong page_size; |
b5ff1b31 | 7721 | int prot; |
d3649702 | 7722 | int ret; |
8bf5b6a9 | 7723 | MemTxAttrs attrs = {}; |
b5ff1b31 | 7724 | |
8bf5b6a9 | 7725 | ret = get_phys_addr(env, address, access_type, mmu_idx, &phys_addr, |
e14b5a23 | 7726 | &attrs, &prot, &page_size, fsr, fi); |
b7cc4e82 | 7727 | if (!ret) { |
b5ff1b31 | 7728 | /* Map a single [sub]page. */ |
dcd82c11 AB |
7729 | phys_addr &= TARGET_PAGE_MASK; |
7730 | address &= TARGET_PAGE_MASK; | |
8bf5b6a9 PM |
7731 | tlb_set_page_with_attrs(cs, address, phys_addr, attrs, |
7732 | prot, mmu_idx, page_size); | |
d4c430a8 | 7733 | return 0; |
b5ff1b31 FB |
7734 | } |
7735 | ||
8c6084bf | 7736 | return ret; |
b5ff1b31 FB |
7737 | } |
7738 | ||
0faea0c7 PM |
7739 | hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cs, vaddr addr, |
7740 | MemTxAttrs *attrs) | |
b5ff1b31 | 7741 | { |
00b941e5 | 7742 | ARMCPU *cpu = ARM_CPU(cs); |
d3649702 | 7743 | CPUARMState *env = &cpu->env; |
a8170e5e | 7744 | hwaddr phys_addr; |
d4c430a8 | 7745 | target_ulong page_size; |
b5ff1b31 | 7746 | int prot; |
b7cc4e82 PC |
7747 | bool ret; |
7748 | uint32_t fsr; | |
e14b5a23 | 7749 | ARMMMUFaultInfo fi = {}; |
b5ff1b31 | 7750 | |
0faea0c7 PM |
7751 | *attrs = (MemTxAttrs) {}; |
7752 | ||
97ed5ccd | 7753 | ret = get_phys_addr(env, addr, 0, cpu_mmu_index(env, false), &phys_addr, |
0faea0c7 | 7754 | attrs, &prot, &page_size, &fsr, &fi); |
b5ff1b31 | 7755 | |
b7cc4e82 | 7756 | if (ret) { |
b5ff1b31 | 7757 | return -1; |
00b941e5 | 7758 | } |
b5ff1b31 FB |
7759 | return phys_addr; |
7760 | } | |
7761 | ||
0ecb72a5 | 7762 | uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg) |
9ee6e8bb | 7763 | { |
a47dddd7 AF |
7764 | ARMCPU *cpu = arm_env_get_cpu(env); |
7765 | ||
9ee6e8bb PB |
7766 | switch (reg) { |
7767 | case 0: /* APSR */ | |
7768 | return xpsr_read(env) & 0xf8000000; | |
7769 | case 1: /* IAPSR */ | |
7770 | return xpsr_read(env) & 0xf80001ff; | |
7771 | case 2: /* EAPSR */ | |
7772 | return xpsr_read(env) & 0xff00fc00; | |
7773 | case 3: /* xPSR */ | |
7774 | return xpsr_read(env) & 0xff00fdff; | |
7775 | case 5: /* IPSR */ | |
7776 | return xpsr_read(env) & 0x000001ff; | |
7777 | case 6: /* EPSR */ | |
7778 | return xpsr_read(env) & 0x0700fc00; | |
7779 | case 7: /* IEPSR */ | |
7780 | return xpsr_read(env) & 0x0700edff; | |
7781 | case 8: /* MSP */ | |
7782 | return env->v7m.current_sp ? env->v7m.other_sp : env->regs[13]; | |
7783 | case 9: /* PSP */ | |
7784 | return env->v7m.current_sp ? env->regs[13] : env->v7m.other_sp; | |
7785 | case 16: /* PRIMASK */ | |
4cc35614 | 7786 | return (env->daif & PSTATE_I) != 0; |
82845826 SH |
7787 | case 17: /* BASEPRI */ |
7788 | case 18: /* BASEPRI_MAX */ | |
9ee6e8bb | 7789 | return env->v7m.basepri; |
82845826 | 7790 | case 19: /* FAULTMASK */ |
4cc35614 | 7791 | return (env->daif & PSTATE_F) != 0; |
9ee6e8bb PB |
7792 | case 20: /* CONTROL */ |
7793 | return env->v7m.control; | |
7794 | default: | |
7795 | /* ??? For debugging only. */ | |
a47dddd7 | 7796 | cpu_abort(CPU(cpu), "Unimplemented system register read (%d)\n", reg); |
9ee6e8bb PB |
7797 | return 0; |
7798 | } | |
7799 | } | |
7800 | ||
0ecb72a5 | 7801 | void HELPER(v7m_msr)(CPUARMState *env, uint32_t reg, uint32_t val) |
9ee6e8bb | 7802 | { |
a47dddd7 AF |
7803 | ARMCPU *cpu = arm_env_get_cpu(env); |
7804 | ||
9ee6e8bb PB |
7805 | switch (reg) { |
7806 | case 0: /* APSR */ | |
7807 | xpsr_write(env, val, 0xf8000000); | |
7808 | break; | |
7809 | case 1: /* IAPSR */ | |
7810 | xpsr_write(env, val, 0xf8000000); | |
7811 | break; | |
7812 | case 2: /* EAPSR */ | |
7813 | xpsr_write(env, val, 0xfe00fc00); | |
7814 | break; | |
7815 | case 3: /* xPSR */ | |
7816 | xpsr_write(env, val, 0xfe00fc00); | |
7817 | break; | |
7818 | case 5: /* IPSR */ | |
7819 | /* IPSR bits are readonly. */ | |
7820 | break; | |
7821 | case 6: /* EPSR */ | |
7822 | xpsr_write(env, val, 0x0600fc00); | |
7823 | break; | |
7824 | case 7: /* IEPSR */ | |
7825 | xpsr_write(env, val, 0x0600fc00); | |
7826 | break; | |
7827 | case 8: /* MSP */ | |
7828 | if (env->v7m.current_sp) | |
7829 | env->v7m.other_sp = val; | |
7830 | else | |
7831 | env->regs[13] = val; | |
7832 | break; | |
7833 | case 9: /* PSP */ | |
7834 | if (env->v7m.current_sp) | |
7835 | env->regs[13] = val; | |
7836 | else | |
7837 | env->v7m.other_sp = val; | |
7838 | break; | |
7839 | case 16: /* PRIMASK */ | |
4cc35614 PM |
7840 | if (val & 1) { |
7841 | env->daif |= PSTATE_I; | |
7842 | } else { | |
7843 | env->daif &= ~PSTATE_I; | |
7844 | } | |
9ee6e8bb | 7845 | break; |
82845826 | 7846 | case 17: /* BASEPRI */ |
9ee6e8bb PB |
7847 | env->v7m.basepri = val & 0xff; |
7848 | break; | |
82845826 | 7849 | case 18: /* BASEPRI_MAX */ |
9ee6e8bb PB |
7850 | val &= 0xff; |
7851 | if (val != 0 && (val < env->v7m.basepri || env->v7m.basepri == 0)) | |
7852 | env->v7m.basepri = val; | |
7853 | break; | |
82845826 | 7854 | case 19: /* FAULTMASK */ |
4cc35614 PM |
7855 | if (val & 1) { |
7856 | env->daif |= PSTATE_F; | |
7857 | } else { | |
7858 | env->daif &= ~PSTATE_F; | |
7859 | } | |
82845826 | 7860 | break; |
9ee6e8bb PB |
7861 | case 20: /* CONTROL */ |
7862 | env->v7m.control = val & 3; | |
7863 | switch_v7m_sp(env, (val & 2) != 0); | |
7864 | break; | |
7865 | default: | |
7866 | /* ??? For debugging only. */ | |
a47dddd7 | 7867 | cpu_abort(CPU(cpu), "Unimplemented system register write (%d)\n", reg); |
9ee6e8bb PB |
7868 | return; |
7869 | } | |
7870 | } | |
7871 | ||
b5ff1b31 | 7872 | #endif |
6ddbc6e4 | 7873 | |
aca3f40b PM |
7874 | void HELPER(dc_zva)(CPUARMState *env, uint64_t vaddr_in) |
7875 | { | |
7876 | /* Implement DC ZVA, which zeroes a fixed-length block of memory. | |
7877 | * Note that we do not implement the (architecturally mandated) | |
7878 | * alignment fault for attempts to use this on Device memory | |
7879 | * (which matches the usual QEMU behaviour of not implementing either | |
7880 | * alignment faults or any memory attribute handling). | |
7881 | */ | |
7882 | ||
7883 | ARMCPU *cpu = arm_env_get_cpu(env); | |
7884 | uint64_t blocklen = 4 << cpu->dcz_blocksize; | |
7885 | uint64_t vaddr = vaddr_in & ~(blocklen - 1); | |
7886 | ||
7887 | #ifndef CONFIG_USER_ONLY | |
7888 | { | |
7889 | /* Slightly awkwardly, QEMU's TARGET_PAGE_SIZE may be less than | |
7890 | * the block size so we might have to do more than one TLB lookup. | |
7891 | * We know that in fact for any v8 CPU the page size is at least 4K | |
7892 | * and the block size must be 2K or less, but TARGET_PAGE_SIZE is only | |
7893 | * 1K as an artefact of legacy v5 subpage support being present in the | |
7894 | * same QEMU executable. | |
7895 | */ | |
7896 | int maxidx = DIV_ROUND_UP(blocklen, TARGET_PAGE_SIZE); | |
7897 | void *hostaddr[maxidx]; | |
7898 | int try, i; | |
97ed5ccd | 7899 | unsigned mmu_idx = cpu_mmu_index(env, false); |
3972ef6f | 7900 | TCGMemOpIdx oi = make_memop_idx(MO_UB, mmu_idx); |
aca3f40b PM |
7901 | |
7902 | for (try = 0; try < 2; try++) { | |
7903 | ||
7904 | for (i = 0; i < maxidx; i++) { | |
7905 | hostaddr[i] = tlb_vaddr_to_host(env, | |
7906 | vaddr + TARGET_PAGE_SIZE * i, | |
3972ef6f | 7907 | 1, mmu_idx); |
aca3f40b PM |
7908 | if (!hostaddr[i]) { |
7909 | break; | |
7910 | } | |
7911 | } | |
7912 | if (i == maxidx) { | |
7913 | /* If it's all in the TLB it's fair game for just writing to; | |
7914 | * we know we don't need to update dirty status, etc. | |
7915 | */ | |
7916 | for (i = 0; i < maxidx - 1; i++) { | |
7917 | memset(hostaddr[i], 0, TARGET_PAGE_SIZE); | |
7918 | } | |
7919 | memset(hostaddr[i], 0, blocklen - (i * TARGET_PAGE_SIZE)); | |
7920 | return; | |
7921 | } | |
7922 | /* OK, try a store and see if we can populate the tlb. This | |
7923 | * might cause an exception if the memory isn't writable, | |
7924 | * in which case we will longjmp out of here. We must for | |
7925 | * this purpose use the actual register value passed to us | |
7926 | * so that we get the fault address right. | |
7927 | */ | |
3972ef6f | 7928 | helper_ret_stb_mmu(env, vaddr_in, 0, oi, GETRA()); |
aca3f40b PM |
7929 | /* Now we can populate the other TLB entries, if any */ |
7930 | for (i = 0; i < maxidx; i++) { | |
7931 | uint64_t va = vaddr + TARGET_PAGE_SIZE * i; | |
7932 | if (va != (vaddr_in & TARGET_PAGE_MASK)) { | |
3972ef6f | 7933 | helper_ret_stb_mmu(env, va, 0, oi, GETRA()); |
aca3f40b PM |
7934 | } |
7935 | } | |
7936 | } | |
7937 | ||
7938 | /* Slow path (probably attempt to do this to an I/O device or | |
7939 | * similar, or clearing of a block of code we have translations | |
7940 | * cached for). Just do a series of byte writes as the architecture | |
7941 | * demands. It's not worth trying to use a cpu_physical_memory_map(), | |
7942 | * memset(), unmap() sequence here because: | |
7943 | * + we'd need to account for the blocksize being larger than a page | |
7944 | * + the direct-RAM access case is almost always going to be dealt | |
7945 | * with in the fastpath code above, so there's no speed benefit | |
7946 | * + we would have to deal with the map returning NULL because the | |
7947 | * bounce buffer was in use | |
7948 | */ | |
7949 | for (i = 0; i < blocklen; i++) { | |
3972ef6f | 7950 | helper_ret_stb_mmu(env, vaddr + i, 0, oi, GETRA()); |
aca3f40b PM |
7951 | } |
7952 | } | |
7953 | #else | |
7954 | memset(g2h(vaddr), 0, blocklen); | |
7955 | #endif | |
7956 | } | |
7957 | ||
6ddbc6e4 PB |
7958 | /* Note that signed overflow is undefined in C. The following routines are |
7959 | careful to use unsigned types where modulo arithmetic is required. | |
7960 | Failure to do so _will_ break on newer gcc. */ | |
7961 | ||
7962 | /* Signed saturating arithmetic. */ | |
7963 | ||
1654b2d6 | 7964 | /* Perform 16-bit signed saturating addition. */ |
6ddbc6e4 PB |
7965 | static inline uint16_t add16_sat(uint16_t a, uint16_t b) |
7966 | { | |
7967 | uint16_t res; | |
7968 | ||
7969 | res = a + b; | |
7970 | if (((res ^ a) & 0x8000) && !((a ^ b) & 0x8000)) { | |
7971 | if (a & 0x8000) | |
7972 | res = 0x8000; | |
7973 | else | |
7974 | res = 0x7fff; | |
7975 | } | |
7976 | return res; | |
7977 | } | |
7978 | ||
1654b2d6 | 7979 | /* Perform 8-bit signed saturating addition. */ |
6ddbc6e4 PB |
7980 | static inline uint8_t add8_sat(uint8_t a, uint8_t b) |
7981 | { | |
7982 | uint8_t res; | |
7983 | ||
7984 | res = a + b; | |
7985 | if (((res ^ a) & 0x80) && !((a ^ b) & 0x80)) { | |
7986 | if (a & 0x80) | |
7987 | res = 0x80; | |
7988 | else | |
7989 | res = 0x7f; | |
7990 | } | |
7991 | return res; | |
7992 | } | |
7993 | ||
1654b2d6 | 7994 | /* Perform 16-bit signed saturating subtraction. */ |
6ddbc6e4 PB |
7995 | static inline uint16_t sub16_sat(uint16_t a, uint16_t b) |
7996 | { | |
7997 | uint16_t res; | |
7998 | ||
7999 | res = a - b; | |
8000 | if (((res ^ a) & 0x8000) && ((a ^ b) & 0x8000)) { | |
8001 | if (a & 0x8000) | |
8002 | res = 0x8000; | |
8003 | else | |
8004 | res = 0x7fff; | |
8005 | } | |
8006 | return res; | |
8007 | } | |
8008 | ||
1654b2d6 | 8009 | /* Perform 8-bit signed saturating subtraction. */ |
6ddbc6e4 PB |
8010 | static inline uint8_t sub8_sat(uint8_t a, uint8_t b) |
8011 | { | |
8012 | uint8_t res; | |
8013 | ||
8014 | res = a - b; | |
8015 | if (((res ^ a) & 0x80) && ((a ^ b) & 0x80)) { | |
8016 | if (a & 0x80) | |
8017 | res = 0x80; | |
8018 | else | |
8019 | res = 0x7f; | |
8020 | } | |
8021 | return res; | |
8022 | } | |
8023 | ||
8024 | #define ADD16(a, b, n) RESULT(add16_sat(a, b), n, 16); | |
8025 | #define SUB16(a, b, n) RESULT(sub16_sat(a, b), n, 16); | |
8026 | #define ADD8(a, b, n) RESULT(add8_sat(a, b), n, 8); | |
8027 | #define SUB8(a, b, n) RESULT(sub8_sat(a, b), n, 8); | |
8028 | #define PFX q | |
8029 | ||
8030 | #include "op_addsub.h" | |
8031 | ||
8032 | /* Unsigned saturating arithmetic. */ | |
460a09c1 | 8033 | static inline uint16_t add16_usat(uint16_t a, uint16_t b) |
6ddbc6e4 PB |
8034 | { |
8035 | uint16_t res; | |
8036 | res = a + b; | |
8037 | if (res < a) | |
8038 | res = 0xffff; | |
8039 | return res; | |
8040 | } | |
8041 | ||
460a09c1 | 8042 | static inline uint16_t sub16_usat(uint16_t a, uint16_t b) |
6ddbc6e4 | 8043 | { |
4c4fd3f8 | 8044 | if (a > b) |
6ddbc6e4 PB |
8045 | return a - b; |
8046 | else | |
8047 | return 0; | |
8048 | } | |
8049 | ||
8050 | static inline uint8_t add8_usat(uint8_t a, uint8_t b) | |
8051 | { | |
8052 | uint8_t res; | |
8053 | res = a + b; | |
8054 | if (res < a) | |
8055 | res = 0xff; | |
8056 | return res; | |
8057 | } | |
8058 | ||
8059 | static inline uint8_t sub8_usat(uint8_t a, uint8_t b) | |
8060 | { | |
4c4fd3f8 | 8061 | if (a > b) |
6ddbc6e4 PB |
8062 | return a - b; |
8063 | else | |
8064 | return 0; | |
8065 | } | |
8066 | ||
8067 | #define ADD16(a, b, n) RESULT(add16_usat(a, b), n, 16); | |
8068 | #define SUB16(a, b, n) RESULT(sub16_usat(a, b), n, 16); | |
8069 | #define ADD8(a, b, n) RESULT(add8_usat(a, b), n, 8); | |
8070 | #define SUB8(a, b, n) RESULT(sub8_usat(a, b), n, 8); | |
8071 | #define PFX uq | |
8072 | ||
8073 | #include "op_addsub.h" | |
8074 | ||
8075 | /* Signed modulo arithmetic. */ | |
8076 | #define SARITH16(a, b, n, op) do { \ | |
8077 | int32_t sum; \ | |
db6e2e65 | 8078 | sum = (int32_t)(int16_t)(a) op (int32_t)(int16_t)(b); \ |
6ddbc6e4 PB |
8079 | RESULT(sum, n, 16); \ |
8080 | if (sum >= 0) \ | |
8081 | ge |= 3 << (n * 2); \ | |
8082 | } while(0) | |
8083 | ||
8084 | #define SARITH8(a, b, n, op) do { \ | |
8085 | int32_t sum; \ | |
db6e2e65 | 8086 | sum = (int32_t)(int8_t)(a) op (int32_t)(int8_t)(b); \ |
6ddbc6e4 PB |
8087 | RESULT(sum, n, 8); \ |
8088 | if (sum >= 0) \ | |
8089 | ge |= 1 << n; \ | |
8090 | } while(0) | |
8091 | ||
8092 | ||
8093 | #define ADD16(a, b, n) SARITH16(a, b, n, +) | |
8094 | #define SUB16(a, b, n) SARITH16(a, b, n, -) | |
8095 | #define ADD8(a, b, n) SARITH8(a, b, n, +) | |
8096 | #define SUB8(a, b, n) SARITH8(a, b, n, -) | |
8097 | #define PFX s | |
8098 | #define ARITH_GE | |
8099 | ||
8100 | #include "op_addsub.h" | |
8101 | ||
8102 | /* Unsigned modulo arithmetic. */ | |
8103 | #define ADD16(a, b, n) do { \ | |
8104 | uint32_t sum; \ | |
8105 | sum = (uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b); \ | |
8106 | RESULT(sum, n, 16); \ | |
a87aa10b | 8107 | if ((sum >> 16) == 1) \ |
6ddbc6e4 PB |
8108 | ge |= 3 << (n * 2); \ |
8109 | } while(0) | |
8110 | ||
8111 | #define ADD8(a, b, n) do { \ | |
8112 | uint32_t sum; \ | |
8113 | sum = (uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b); \ | |
8114 | RESULT(sum, n, 8); \ | |
a87aa10b AZ |
8115 | if ((sum >> 8) == 1) \ |
8116 | ge |= 1 << n; \ | |
6ddbc6e4 PB |
8117 | } while(0) |
8118 | ||
8119 | #define SUB16(a, b, n) do { \ | |
8120 | uint32_t sum; \ | |
8121 | sum = (uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b); \ | |
8122 | RESULT(sum, n, 16); \ | |
8123 | if ((sum >> 16) == 0) \ | |
8124 | ge |= 3 << (n * 2); \ | |
8125 | } while(0) | |
8126 | ||
8127 | #define SUB8(a, b, n) do { \ | |
8128 | uint32_t sum; \ | |
8129 | sum = (uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b); \ | |
8130 | RESULT(sum, n, 8); \ | |
8131 | if ((sum >> 8) == 0) \ | |
a87aa10b | 8132 | ge |= 1 << n; \ |
6ddbc6e4 PB |
8133 | } while(0) |
8134 | ||
8135 | #define PFX u | |
8136 | #define ARITH_GE | |
8137 | ||
8138 | #include "op_addsub.h" | |
8139 | ||
8140 | /* Halved signed arithmetic. */ | |
8141 | #define ADD16(a, b, n) \ | |
8142 | RESULT(((int32_t)(int16_t)(a) + (int32_t)(int16_t)(b)) >> 1, n, 16) | |
8143 | #define SUB16(a, b, n) \ | |
8144 | RESULT(((int32_t)(int16_t)(a) - (int32_t)(int16_t)(b)) >> 1, n, 16) | |
8145 | #define ADD8(a, b, n) \ | |
8146 | RESULT(((int32_t)(int8_t)(a) + (int32_t)(int8_t)(b)) >> 1, n, 8) | |
8147 | #define SUB8(a, b, n) \ | |
8148 | RESULT(((int32_t)(int8_t)(a) - (int32_t)(int8_t)(b)) >> 1, n, 8) | |
8149 | #define PFX sh | |
8150 | ||
8151 | #include "op_addsub.h" | |
8152 | ||
8153 | /* Halved unsigned arithmetic. */ | |
8154 | #define ADD16(a, b, n) \ | |
8155 | RESULT(((uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b)) >> 1, n, 16) | |
8156 | #define SUB16(a, b, n) \ | |
8157 | RESULT(((uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b)) >> 1, n, 16) | |
8158 | #define ADD8(a, b, n) \ | |
8159 | RESULT(((uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b)) >> 1, n, 8) | |
8160 | #define SUB8(a, b, n) \ | |
8161 | RESULT(((uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b)) >> 1, n, 8) | |
8162 | #define PFX uh | |
8163 | ||
8164 | #include "op_addsub.h" | |
8165 | ||
8166 | static inline uint8_t do_usad(uint8_t a, uint8_t b) | |
8167 | { | |
8168 | if (a > b) | |
8169 | return a - b; | |
8170 | else | |
8171 | return b - a; | |
8172 | } | |
8173 | ||
8174 | /* Unsigned sum of absolute byte differences. */ | |
8175 | uint32_t HELPER(usad8)(uint32_t a, uint32_t b) | |
8176 | { | |
8177 | uint32_t sum; | |
8178 | sum = do_usad(a, b); | |
8179 | sum += do_usad(a >> 8, b >> 8); | |
8180 | sum += do_usad(a >> 16, b >>16); | |
8181 | sum += do_usad(a >> 24, b >> 24); | |
8182 | return sum; | |
8183 | } | |
8184 | ||
8185 | /* For ARMv6 SEL instruction. */ | |
8186 | uint32_t HELPER(sel_flags)(uint32_t flags, uint32_t a, uint32_t b) | |
8187 | { | |
8188 | uint32_t mask; | |
8189 | ||
8190 | mask = 0; | |
8191 | if (flags & 1) | |
8192 | mask |= 0xff; | |
8193 | if (flags & 2) | |
8194 | mask |= 0xff00; | |
8195 | if (flags & 4) | |
8196 | mask |= 0xff0000; | |
8197 | if (flags & 8) | |
8198 | mask |= 0xff000000; | |
8199 | return (a & mask) | (b & ~mask); | |
8200 | } | |
8201 | ||
b90372ad PM |
8202 | /* VFP support. We follow the convention used for VFP instructions: |
8203 | Single precision routines have a "s" suffix, double precision a | |
4373f3ce PB |
8204 | "d" suffix. */ |
8205 | ||
8206 | /* Convert host exception flags to vfp form. */ | |
8207 | static inline int vfp_exceptbits_from_host(int host_bits) | |
8208 | { | |
8209 | int target_bits = 0; | |
8210 | ||
8211 | if (host_bits & float_flag_invalid) | |
8212 | target_bits |= 1; | |
8213 | if (host_bits & float_flag_divbyzero) | |
8214 | target_bits |= 2; | |
8215 | if (host_bits & float_flag_overflow) | |
8216 | target_bits |= 4; | |
36802b6b | 8217 | if (host_bits & (float_flag_underflow | float_flag_output_denormal)) |
4373f3ce PB |
8218 | target_bits |= 8; |
8219 | if (host_bits & float_flag_inexact) | |
8220 | target_bits |= 0x10; | |
cecd8504 PM |
8221 | if (host_bits & float_flag_input_denormal) |
8222 | target_bits |= 0x80; | |
4373f3ce PB |
8223 | return target_bits; |
8224 | } | |
8225 | ||
0ecb72a5 | 8226 | uint32_t HELPER(vfp_get_fpscr)(CPUARMState *env) |
4373f3ce PB |
8227 | { |
8228 | int i; | |
8229 | uint32_t fpscr; | |
8230 | ||
8231 | fpscr = (env->vfp.xregs[ARM_VFP_FPSCR] & 0xffc8ffff) | |
8232 | | (env->vfp.vec_len << 16) | |
8233 | | (env->vfp.vec_stride << 20); | |
8234 | i = get_float_exception_flags(&env->vfp.fp_status); | |
3a492f3a | 8235 | i |= get_float_exception_flags(&env->vfp.standard_fp_status); |
4373f3ce PB |
8236 | fpscr |= vfp_exceptbits_from_host(i); |
8237 | return fpscr; | |
8238 | } | |
8239 | ||
0ecb72a5 | 8240 | uint32_t vfp_get_fpscr(CPUARMState *env) |
01653295 PM |
8241 | { |
8242 | return HELPER(vfp_get_fpscr)(env); | |
8243 | } | |
8244 | ||
4373f3ce PB |
8245 | /* Convert vfp exception flags to target form. */ |
8246 | static inline int vfp_exceptbits_to_host(int target_bits) | |
8247 | { | |
8248 | int host_bits = 0; | |
8249 | ||
8250 | if (target_bits & 1) | |
8251 | host_bits |= float_flag_invalid; | |
8252 | if (target_bits & 2) | |
8253 | host_bits |= float_flag_divbyzero; | |
8254 | if (target_bits & 4) | |
8255 | host_bits |= float_flag_overflow; | |
8256 | if (target_bits & 8) | |
8257 | host_bits |= float_flag_underflow; | |
8258 | if (target_bits & 0x10) | |
8259 | host_bits |= float_flag_inexact; | |
cecd8504 PM |
8260 | if (target_bits & 0x80) |
8261 | host_bits |= float_flag_input_denormal; | |
4373f3ce PB |
8262 | return host_bits; |
8263 | } | |
8264 | ||
0ecb72a5 | 8265 | void HELPER(vfp_set_fpscr)(CPUARMState *env, uint32_t val) |
4373f3ce PB |
8266 | { |
8267 | int i; | |
8268 | uint32_t changed; | |
8269 | ||
8270 | changed = env->vfp.xregs[ARM_VFP_FPSCR]; | |
8271 | env->vfp.xregs[ARM_VFP_FPSCR] = (val & 0xffc8ffff); | |
8272 | env->vfp.vec_len = (val >> 16) & 7; | |
8273 | env->vfp.vec_stride = (val >> 20) & 3; | |
8274 | ||
8275 | changed ^= val; | |
8276 | if (changed & (3 << 22)) { | |
8277 | i = (val >> 22) & 3; | |
8278 | switch (i) { | |
4d3da0f3 | 8279 | case FPROUNDING_TIEEVEN: |
4373f3ce PB |
8280 | i = float_round_nearest_even; |
8281 | break; | |
4d3da0f3 | 8282 | case FPROUNDING_POSINF: |
4373f3ce PB |
8283 | i = float_round_up; |
8284 | break; | |
4d3da0f3 | 8285 | case FPROUNDING_NEGINF: |
4373f3ce PB |
8286 | i = float_round_down; |
8287 | break; | |
4d3da0f3 | 8288 | case FPROUNDING_ZERO: |
4373f3ce PB |
8289 | i = float_round_to_zero; |
8290 | break; | |
8291 | } | |
8292 | set_float_rounding_mode(i, &env->vfp.fp_status); | |
8293 | } | |
cecd8504 | 8294 | if (changed & (1 << 24)) { |
fe76d976 | 8295 | set_flush_to_zero((val & (1 << 24)) != 0, &env->vfp.fp_status); |
cecd8504 PM |
8296 | set_flush_inputs_to_zero((val & (1 << 24)) != 0, &env->vfp.fp_status); |
8297 | } | |
5c7908ed PB |
8298 | if (changed & (1 << 25)) |
8299 | set_default_nan_mode((val & (1 << 25)) != 0, &env->vfp.fp_status); | |
4373f3ce | 8300 | |
b12c390b | 8301 | i = vfp_exceptbits_to_host(val); |
4373f3ce | 8302 | set_float_exception_flags(i, &env->vfp.fp_status); |
3a492f3a | 8303 | set_float_exception_flags(0, &env->vfp.standard_fp_status); |
4373f3ce PB |
8304 | } |
8305 | ||
0ecb72a5 | 8306 | void vfp_set_fpscr(CPUARMState *env, uint32_t val) |
01653295 PM |
8307 | { |
8308 | HELPER(vfp_set_fpscr)(env, val); | |
8309 | } | |
8310 | ||
4373f3ce PB |
8311 | #define VFP_HELPER(name, p) HELPER(glue(glue(vfp_,name),p)) |
8312 | ||
8313 | #define VFP_BINOP(name) \ | |
ae1857ec | 8314 | float32 VFP_HELPER(name, s)(float32 a, float32 b, void *fpstp) \ |
4373f3ce | 8315 | { \ |
ae1857ec PM |
8316 | float_status *fpst = fpstp; \ |
8317 | return float32_ ## name(a, b, fpst); \ | |
4373f3ce | 8318 | } \ |
ae1857ec | 8319 | float64 VFP_HELPER(name, d)(float64 a, float64 b, void *fpstp) \ |
4373f3ce | 8320 | { \ |
ae1857ec PM |
8321 | float_status *fpst = fpstp; \ |
8322 | return float64_ ## name(a, b, fpst); \ | |
4373f3ce PB |
8323 | } |
8324 | VFP_BINOP(add) | |
8325 | VFP_BINOP(sub) | |
8326 | VFP_BINOP(mul) | |
8327 | VFP_BINOP(div) | |
f71a2ae5 PM |
8328 | VFP_BINOP(min) |
8329 | VFP_BINOP(max) | |
8330 | VFP_BINOP(minnum) | |
8331 | VFP_BINOP(maxnum) | |
4373f3ce PB |
8332 | #undef VFP_BINOP |
8333 | ||
8334 | float32 VFP_HELPER(neg, s)(float32 a) | |
8335 | { | |
8336 | return float32_chs(a); | |
8337 | } | |
8338 | ||
8339 | float64 VFP_HELPER(neg, d)(float64 a) | |
8340 | { | |
66230e0d | 8341 | return float64_chs(a); |
4373f3ce PB |
8342 | } |
8343 | ||
8344 | float32 VFP_HELPER(abs, s)(float32 a) | |
8345 | { | |
8346 | return float32_abs(a); | |
8347 | } | |
8348 | ||
8349 | float64 VFP_HELPER(abs, d)(float64 a) | |
8350 | { | |
66230e0d | 8351 | return float64_abs(a); |
4373f3ce PB |
8352 | } |
8353 | ||
0ecb72a5 | 8354 | float32 VFP_HELPER(sqrt, s)(float32 a, CPUARMState *env) |
4373f3ce PB |
8355 | { |
8356 | return float32_sqrt(a, &env->vfp.fp_status); | |
8357 | } | |
8358 | ||
0ecb72a5 | 8359 | float64 VFP_HELPER(sqrt, d)(float64 a, CPUARMState *env) |
4373f3ce PB |
8360 | { |
8361 | return float64_sqrt(a, &env->vfp.fp_status); | |
8362 | } | |
8363 | ||
8364 | /* XXX: check quiet/signaling case */ | |
8365 | #define DO_VFP_cmp(p, type) \ | |
0ecb72a5 | 8366 | void VFP_HELPER(cmp, p)(type a, type b, CPUARMState *env) \ |
4373f3ce PB |
8367 | { \ |
8368 | uint32_t flags; \ | |
8369 | switch(type ## _compare_quiet(a, b, &env->vfp.fp_status)) { \ | |
8370 | case 0: flags = 0x6; break; \ | |
8371 | case -1: flags = 0x8; break; \ | |
8372 | case 1: flags = 0x2; break; \ | |
8373 | default: case 2: flags = 0x3; break; \ | |
8374 | } \ | |
8375 | env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \ | |
8376 | | (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \ | |
8377 | } \ | |
0ecb72a5 | 8378 | void VFP_HELPER(cmpe, p)(type a, type b, CPUARMState *env) \ |
4373f3ce PB |
8379 | { \ |
8380 | uint32_t flags; \ | |
8381 | switch(type ## _compare(a, b, &env->vfp.fp_status)) { \ | |
8382 | case 0: flags = 0x6; break; \ | |
8383 | case -1: flags = 0x8; break; \ | |
8384 | case 1: flags = 0x2; break; \ | |
8385 | default: case 2: flags = 0x3; break; \ | |
8386 | } \ | |
8387 | env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \ | |
8388 | | (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \ | |
8389 | } | |
8390 | DO_VFP_cmp(s, float32) | |
8391 | DO_VFP_cmp(d, float64) | |
8392 | #undef DO_VFP_cmp | |
8393 | ||
5500b06c | 8394 | /* Integer to float and float to integer conversions */ |
4373f3ce | 8395 | |
5500b06c PM |
8396 | #define CONV_ITOF(name, fsz, sign) \ |
8397 | float##fsz HELPER(name)(uint32_t x, void *fpstp) \ | |
8398 | { \ | |
8399 | float_status *fpst = fpstp; \ | |
85836979 | 8400 | return sign##int32_to_##float##fsz((sign##int32_t)x, fpst); \ |
4373f3ce PB |
8401 | } |
8402 | ||
5500b06c PM |
8403 | #define CONV_FTOI(name, fsz, sign, round) \ |
8404 | uint32_t HELPER(name)(float##fsz x, void *fpstp) \ | |
8405 | { \ | |
8406 | float_status *fpst = fpstp; \ | |
8407 | if (float##fsz##_is_any_nan(x)) { \ | |
8408 | float_raise(float_flag_invalid, fpst); \ | |
8409 | return 0; \ | |
8410 | } \ | |
8411 | return float##fsz##_to_##sign##int32##round(x, fpst); \ | |
4373f3ce PB |
8412 | } |
8413 | ||
5500b06c PM |
8414 | #define FLOAT_CONVS(name, p, fsz, sign) \ |
8415 | CONV_ITOF(vfp_##name##to##p, fsz, sign) \ | |
8416 | CONV_FTOI(vfp_to##name##p, fsz, sign, ) \ | |
8417 | CONV_FTOI(vfp_to##name##z##p, fsz, sign, _round_to_zero) | |
4373f3ce | 8418 | |
5500b06c PM |
8419 | FLOAT_CONVS(si, s, 32, ) |
8420 | FLOAT_CONVS(si, d, 64, ) | |
8421 | FLOAT_CONVS(ui, s, 32, u) | |
8422 | FLOAT_CONVS(ui, d, 64, u) | |
4373f3ce | 8423 | |
5500b06c PM |
8424 | #undef CONV_ITOF |
8425 | #undef CONV_FTOI | |
8426 | #undef FLOAT_CONVS | |
4373f3ce PB |
8427 | |
8428 | /* floating point conversion */ | |
0ecb72a5 | 8429 | float64 VFP_HELPER(fcvtd, s)(float32 x, CPUARMState *env) |
4373f3ce | 8430 | { |
2d627737 PM |
8431 | float64 r = float32_to_float64(x, &env->vfp.fp_status); |
8432 | /* ARM requires that S<->D conversion of any kind of NaN generates | |
8433 | * a quiet NaN by forcing the most significant frac bit to 1. | |
8434 | */ | |
8435 | return float64_maybe_silence_nan(r); | |
4373f3ce PB |
8436 | } |
8437 | ||
0ecb72a5 | 8438 | float32 VFP_HELPER(fcvts, d)(float64 x, CPUARMState *env) |
4373f3ce | 8439 | { |
2d627737 PM |
8440 | float32 r = float64_to_float32(x, &env->vfp.fp_status); |
8441 | /* ARM requires that S<->D conversion of any kind of NaN generates | |
8442 | * a quiet NaN by forcing the most significant frac bit to 1. | |
8443 | */ | |
8444 | return float32_maybe_silence_nan(r); | |
4373f3ce PB |
8445 | } |
8446 | ||
8447 | /* VFP3 fixed point conversion. */ | |
16d5b3ca | 8448 | #define VFP_CONV_FIX_FLOAT(name, p, fsz, isz, itype) \ |
8ed697e8 WN |
8449 | float##fsz HELPER(vfp_##name##to##p)(uint##isz##_t x, uint32_t shift, \ |
8450 | void *fpstp) \ | |
4373f3ce | 8451 | { \ |
5500b06c | 8452 | float_status *fpst = fpstp; \ |
622465e1 | 8453 | float##fsz tmp; \ |
8ed697e8 | 8454 | tmp = itype##_to_##float##fsz(x, fpst); \ |
5500b06c | 8455 | return float##fsz##_scalbn(tmp, -(int)shift, fpst); \ |
16d5b3ca WN |
8456 | } |
8457 | ||
abe66f70 PM |
8458 | /* Notice that we want only input-denormal exception flags from the |
8459 | * scalbn operation: the other possible flags (overflow+inexact if | |
8460 | * we overflow to infinity, output-denormal) aren't correct for the | |
8461 | * complete scale-and-convert operation. | |
8462 | */ | |
16d5b3ca WN |
8463 | #define VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, round) \ |
8464 | uint##isz##_t HELPER(vfp_to##name##p##round)(float##fsz x, \ | |
8465 | uint32_t shift, \ | |
8466 | void *fpstp) \ | |
4373f3ce | 8467 | { \ |
5500b06c | 8468 | float_status *fpst = fpstp; \ |
abe66f70 | 8469 | int old_exc_flags = get_float_exception_flags(fpst); \ |
622465e1 PM |
8470 | float##fsz tmp; \ |
8471 | if (float##fsz##_is_any_nan(x)) { \ | |
5500b06c | 8472 | float_raise(float_flag_invalid, fpst); \ |
622465e1 | 8473 | return 0; \ |
09d9487f | 8474 | } \ |
5500b06c | 8475 | tmp = float##fsz##_scalbn(x, shift, fpst); \ |
abe66f70 PM |
8476 | old_exc_flags |= get_float_exception_flags(fpst) \ |
8477 | & float_flag_input_denormal; \ | |
8478 | set_float_exception_flags(old_exc_flags, fpst); \ | |
16d5b3ca | 8479 | return float##fsz##_to_##itype##round(tmp, fpst); \ |
622465e1 PM |
8480 | } |
8481 | ||
16d5b3ca WN |
8482 | #define VFP_CONV_FIX(name, p, fsz, isz, itype) \ |
8483 | VFP_CONV_FIX_FLOAT(name, p, fsz, isz, itype) \ | |
3c6a074a WN |
8484 | VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, _round_to_zero) \ |
8485 | VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, ) | |
8486 | ||
8487 | #define VFP_CONV_FIX_A64(name, p, fsz, isz, itype) \ | |
8488 | VFP_CONV_FIX_FLOAT(name, p, fsz, isz, itype) \ | |
8489 | VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, ) | |
16d5b3ca | 8490 | |
8ed697e8 WN |
8491 | VFP_CONV_FIX(sh, d, 64, 64, int16) |
8492 | VFP_CONV_FIX(sl, d, 64, 64, int32) | |
3c6a074a | 8493 | VFP_CONV_FIX_A64(sq, d, 64, 64, int64) |
8ed697e8 WN |
8494 | VFP_CONV_FIX(uh, d, 64, 64, uint16) |
8495 | VFP_CONV_FIX(ul, d, 64, 64, uint32) | |
3c6a074a | 8496 | VFP_CONV_FIX_A64(uq, d, 64, 64, uint64) |
8ed697e8 WN |
8497 | VFP_CONV_FIX(sh, s, 32, 32, int16) |
8498 | VFP_CONV_FIX(sl, s, 32, 32, int32) | |
3c6a074a | 8499 | VFP_CONV_FIX_A64(sq, s, 32, 64, int64) |
8ed697e8 WN |
8500 | VFP_CONV_FIX(uh, s, 32, 32, uint16) |
8501 | VFP_CONV_FIX(ul, s, 32, 32, uint32) | |
3c6a074a | 8502 | VFP_CONV_FIX_A64(uq, s, 32, 64, uint64) |
4373f3ce | 8503 | #undef VFP_CONV_FIX |
16d5b3ca WN |
8504 | #undef VFP_CONV_FIX_FLOAT |
8505 | #undef VFP_CONV_FLOAT_FIX_ROUND | |
4373f3ce | 8506 | |
52a1f6a3 AG |
8507 | /* Set the current fp rounding mode and return the old one. |
8508 | * The argument is a softfloat float_round_ value. | |
8509 | */ | |
8510 | uint32_t HELPER(set_rmode)(uint32_t rmode, CPUARMState *env) | |
8511 | { | |
8512 | float_status *fp_status = &env->vfp.fp_status; | |
8513 | ||
8514 | uint32_t prev_rmode = get_float_rounding_mode(fp_status); | |
8515 | set_float_rounding_mode(rmode, fp_status); | |
8516 | ||
8517 | return prev_rmode; | |
8518 | } | |
8519 | ||
43630e58 WN |
8520 | /* Set the current fp rounding mode in the standard fp status and return |
8521 | * the old one. This is for NEON instructions that need to change the | |
8522 | * rounding mode but wish to use the standard FPSCR values for everything | |
8523 | * else. Always set the rounding mode back to the correct value after | |
8524 | * modifying it. | |
8525 | * The argument is a softfloat float_round_ value. | |
8526 | */ | |
8527 | uint32_t HELPER(set_neon_rmode)(uint32_t rmode, CPUARMState *env) | |
8528 | { | |
8529 | float_status *fp_status = &env->vfp.standard_fp_status; | |
8530 | ||
8531 | uint32_t prev_rmode = get_float_rounding_mode(fp_status); | |
8532 | set_float_rounding_mode(rmode, fp_status); | |
8533 | ||
8534 | return prev_rmode; | |
8535 | } | |
8536 | ||
60011498 | 8537 | /* Half precision conversions. */ |
0ecb72a5 | 8538 | static float32 do_fcvt_f16_to_f32(uint32_t a, CPUARMState *env, float_status *s) |
60011498 | 8539 | { |
60011498 | 8540 | int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0; |
fb91678d PM |
8541 | float32 r = float16_to_float32(make_float16(a), ieee, s); |
8542 | if (ieee) { | |
8543 | return float32_maybe_silence_nan(r); | |
8544 | } | |
8545 | return r; | |
60011498 PB |
8546 | } |
8547 | ||
0ecb72a5 | 8548 | static uint32_t do_fcvt_f32_to_f16(float32 a, CPUARMState *env, float_status *s) |
60011498 | 8549 | { |
60011498 | 8550 | int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0; |
fb91678d PM |
8551 | float16 r = float32_to_float16(a, ieee, s); |
8552 | if (ieee) { | |
8553 | r = float16_maybe_silence_nan(r); | |
8554 | } | |
8555 | return float16_val(r); | |
60011498 PB |
8556 | } |
8557 | ||
0ecb72a5 | 8558 | float32 HELPER(neon_fcvt_f16_to_f32)(uint32_t a, CPUARMState *env) |
2d981da7 PM |
8559 | { |
8560 | return do_fcvt_f16_to_f32(a, env, &env->vfp.standard_fp_status); | |
8561 | } | |
8562 | ||
0ecb72a5 | 8563 | uint32_t HELPER(neon_fcvt_f32_to_f16)(float32 a, CPUARMState *env) |
2d981da7 PM |
8564 | { |
8565 | return do_fcvt_f32_to_f16(a, env, &env->vfp.standard_fp_status); | |
8566 | } | |
8567 | ||
0ecb72a5 | 8568 | float32 HELPER(vfp_fcvt_f16_to_f32)(uint32_t a, CPUARMState *env) |
2d981da7 PM |
8569 | { |
8570 | return do_fcvt_f16_to_f32(a, env, &env->vfp.fp_status); | |
8571 | } | |
8572 | ||
0ecb72a5 | 8573 | uint32_t HELPER(vfp_fcvt_f32_to_f16)(float32 a, CPUARMState *env) |
2d981da7 PM |
8574 | { |
8575 | return do_fcvt_f32_to_f16(a, env, &env->vfp.fp_status); | |
8576 | } | |
8577 | ||
8900aad2 PM |
8578 | float64 HELPER(vfp_fcvt_f16_to_f64)(uint32_t a, CPUARMState *env) |
8579 | { | |
8580 | int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0; | |
8581 | float64 r = float16_to_float64(make_float16(a), ieee, &env->vfp.fp_status); | |
8582 | if (ieee) { | |
8583 | return float64_maybe_silence_nan(r); | |
8584 | } | |
8585 | return r; | |
8586 | } | |
8587 | ||
8588 | uint32_t HELPER(vfp_fcvt_f64_to_f16)(float64 a, CPUARMState *env) | |
8589 | { | |
8590 | int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0; | |
8591 | float16 r = float64_to_float16(a, ieee, &env->vfp.fp_status); | |
8592 | if (ieee) { | |
8593 | r = float16_maybe_silence_nan(r); | |
8594 | } | |
8595 | return float16_val(r); | |
8596 | } | |
8597 | ||
dda3ec49 | 8598 | #define float32_two make_float32(0x40000000) |
6aae3df1 PM |
8599 | #define float32_three make_float32(0x40400000) |
8600 | #define float32_one_point_five make_float32(0x3fc00000) | |
dda3ec49 | 8601 | |
0ecb72a5 | 8602 | float32 HELPER(recps_f32)(float32 a, float32 b, CPUARMState *env) |
4373f3ce | 8603 | { |
dda3ec49 PM |
8604 | float_status *s = &env->vfp.standard_fp_status; |
8605 | if ((float32_is_infinity(a) && float32_is_zero_or_denormal(b)) || | |
8606 | (float32_is_infinity(b) && float32_is_zero_or_denormal(a))) { | |
43fe9bdb PM |
8607 | if (!(float32_is_zero(a) || float32_is_zero(b))) { |
8608 | float_raise(float_flag_input_denormal, s); | |
8609 | } | |
dda3ec49 PM |
8610 | return float32_two; |
8611 | } | |
8612 | return float32_sub(float32_two, float32_mul(a, b, s), s); | |
4373f3ce PB |
8613 | } |
8614 | ||
0ecb72a5 | 8615 | float32 HELPER(rsqrts_f32)(float32 a, float32 b, CPUARMState *env) |
4373f3ce | 8616 | { |
71826966 | 8617 | float_status *s = &env->vfp.standard_fp_status; |
9ea62f57 PM |
8618 | float32 product; |
8619 | if ((float32_is_infinity(a) && float32_is_zero_or_denormal(b)) || | |
8620 | (float32_is_infinity(b) && float32_is_zero_or_denormal(a))) { | |
43fe9bdb PM |
8621 | if (!(float32_is_zero(a) || float32_is_zero(b))) { |
8622 | float_raise(float_flag_input_denormal, s); | |
8623 | } | |
6aae3df1 | 8624 | return float32_one_point_five; |
9ea62f57 | 8625 | } |
6aae3df1 PM |
8626 | product = float32_mul(a, b, s); |
8627 | return float32_div(float32_sub(float32_three, product, s), float32_two, s); | |
4373f3ce PB |
8628 | } |
8629 | ||
8f8e3aa4 PB |
8630 | /* NEON helpers. */ |
8631 | ||
56bf4fe2 CL |
8632 | /* Constants 256 and 512 are used in some helpers; we avoid relying on |
8633 | * int->float conversions at run-time. */ | |
8634 | #define float64_256 make_float64(0x4070000000000000LL) | |
8635 | #define float64_512 make_float64(0x4080000000000000LL) | |
b6d4443a AB |
8636 | #define float32_maxnorm make_float32(0x7f7fffff) |
8637 | #define float64_maxnorm make_float64(0x7fefffffffffffffLL) | |
56bf4fe2 | 8638 | |
b6d4443a AB |
8639 | /* Reciprocal functions |
8640 | * | |
8641 | * The algorithm that must be used to calculate the estimate | |
8642 | * is specified by the ARM ARM, see FPRecipEstimate() | |
fe0e4872 | 8643 | */ |
b6d4443a AB |
8644 | |
8645 | static float64 recip_estimate(float64 a, float_status *real_fp_status) | |
fe0e4872 | 8646 | { |
1146a817 PM |
8647 | /* These calculations mustn't set any fp exception flags, |
8648 | * so we use a local copy of the fp_status. | |
8649 | */ | |
b6d4443a | 8650 | float_status dummy_status = *real_fp_status; |
1146a817 | 8651 | float_status *s = &dummy_status; |
fe0e4872 CL |
8652 | /* q = (int)(a * 512.0) */ |
8653 | float64 q = float64_mul(float64_512, a, s); | |
8654 | int64_t q_int = float64_to_int64_round_to_zero(q, s); | |
8655 | ||
8656 | /* r = 1.0 / (((double)q + 0.5) / 512.0) */ | |
8657 | q = int64_to_float64(q_int, s); | |
8658 | q = float64_add(q, float64_half, s); | |
8659 | q = float64_div(q, float64_512, s); | |
8660 | q = float64_div(float64_one, q, s); | |
8661 | ||
8662 | /* s = (int)(256.0 * r + 0.5) */ | |
8663 | q = float64_mul(q, float64_256, s); | |
8664 | q = float64_add(q, float64_half, s); | |
8665 | q_int = float64_to_int64_round_to_zero(q, s); | |
8666 | ||
8667 | /* return (double)s / 256.0 */ | |
8668 | return float64_div(int64_to_float64(q_int, s), float64_256, s); | |
8669 | } | |
8670 | ||
b6d4443a AB |
8671 | /* Common wrapper to call recip_estimate */ |
8672 | static float64 call_recip_estimate(float64 num, int off, float_status *fpst) | |
4373f3ce | 8673 | { |
b6d4443a AB |
8674 | uint64_t val64 = float64_val(num); |
8675 | uint64_t frac = extract64(val64, 0, 52); | |
8676 | int64_t exp = extract64(val64, 52, 11); | |
8677 | uint64_t sbit; | |
8678 | float64 scaled, estimate; | |
fe0e4872 | 8679 | |
b6d4443a AB |
8680 | /* Generate the scaled number for the estimate function */ |
8681 | if (exp == 0) { | |
8682 | if (extract64(frac, 51, 1) == 0) { | |
8683 | exp = -1; | |
8684 | frac = extract64(frac, 0, 50) << 2; | |
8685 | } else { | |
8686 | frac = extract64(frac, 0, 51) << 1; | |
8687 | } | |
8688 | } | |
fe0e4872 | 8689 | |
b6d4443a AB |
8690 | /* scaled = '0' : '01111111110' : fraction<51:44> : Zeros(44); */ |
8691 | scaled = make_float64((0x3feULL << 52) | |
8692 | | extract64(frac, 44, 8) << 44); | |
8693 | ||
8694 | estimate = recip_estimate(scaled, fpst); | |
8695 | ||
8696 | /* Build new result */ | |
8697 | val64 = float64_val(estimate); | |
8698 | sbit = 0x8000000000000000ULL & val64; | |
8699 | exp = off - exp; | |
8700 | frac = extract64(val64, 0, 52); | |
8701 | ||
8702 | if (exp == 0) { | |
8703 | frac = 1ULL << 51 | extract64(frac, 1, 51); | |
8704 | } else if (exp == -1) { | |
8705 | frac = 1ULL << 50 | extract64(frac, 2, 50); | |
8706 | exp = 0; | |
8707 | } | |
8708 | ||
8709 | return make_float64(sbit | (exp << 52) | frac); | |
8710 | } | |
8711 | ||
8712 | static bool round_to_inf(float_status *fpst, bool sign_bit) | |
8713 | { | |
8714 | switch (fpst->float_rounding_mode) { | |
8715 | case float_round_nearest_even: /* Round to Nearest */ | |
8716 | return true; | |
8717 | case float_round_up: /* Round to +Inf */ | |
8718 | return !sign_bit; | |
8719 | case float_round_down: /* Round to -Inf */ | |
8720 | return sign_bit; | |
8721 | case float_round_to_zero: /* Round to Zero */ | |
8722 | return false; | |
8723 | } | |
8724 | ||
8725 | g_assert_not_reached(); | |
8726 | } | |
8727 | ||
8728 | float32 HELPER(recpe_f32)(float32 input, void *fpstp) | |
8729 | { | |
8730 | float_status *fpst = fpstp; | |
8731 | float32 f32 = float32_squash_input_denormal(input, fpst); | |
8732 | uint32_t f32_val = float32_val(f32); | |
8733 | uint32_t f32_sbit = 0x80000000ULL & f32_val; | |
8734 | int32_t f32_exp = extract32(f32_val, 23, 8); | |
8735 | uint32_t f32_frac = extract32(f32_val, 0, 23); | |
8736 | float64 f64, r64; | |
8737 | uint64_t r64_val; | |
8738 | int64_t r64_exp; | |
8739 | uint64_t r64_frac; | |
8740 | ||
8741 | if (float32_is_any_nan(f32)) { | |
8742 | float32 nan = f32; | |
8743 | if (float32_is_signaling_nan(f32)) { | |
8744 | float_raise(float_flag_invalid, fpst); | |
8745 | nan = float32_maybe_silence_nan(f32); | |
fe0e4872 | 8746 | } |
b6d4443a AB |
8747 | if (fpst->default_nan_mode) { |
8748 | nan = float32_default_nan; | |
43fe9bdb | 8749 | } |
b6d4443a AB |
8750 | return nan; |
8751 | } else if (float32_is_infinity(f32)) { | |
8752 | return float32_set_sign(float32_zero, float32_is_neg(f32)); | |
8753 | } else if (float32_is_zero(f32)) { | |
8754 | float_raise(float_flag_divbyzero, fpst); | |
8755 | return float32_set_sign(float32_infinity, float32_is_neg(f32)); | |
8756 | } else if ((f32_val & ~(1ULL << 31)) < (1ULL << 21)) { | |
8757 | /* Abs(value) < 2.0^-128 */ | |
8758 | float_raise(float_flag_overflow | float_flag_inexact, fpst); | |
8759 | if (round_to_inf(fpst, f32_sbit)) { | |
8760 | return float32_set_sign(float32_infinity, float32_is_neg(f32)); | |
8761 | } else { | |
8762 | return float32_set_sign(float32_maxnorm, float32_is_neg(f32)); | |
8763 | } | |
8764 | } else if (f32_exp >= 253 && fpst->flush_to_zero) { | |
8765 | float_raise(float_flag_underflow, fpst); | |
8766 | return float32_set_sign(float32_zero, float32_is_neg(f32)); | |
fe0e4872 CL |
8767 | } |
8768 | ||
fe0e4872 | 8769 | |
b6d4443a AB |
8770 | f64 = make_float64(((int64_t)(f32_exp) << 52) | (int64_t)(f32_frac) << 29); |
8771 | r64 = call_recip_estimate(f64, 253, fpst); | |
8772 | r64_val = float64_val(r64); | |
8773 | r64_exp = extract64(r64_val, 52, 11); | |
8774 | r64_frac = extract64(r64_val, 0, 52); | |
8775 | ||
8776 | /* result = sign : result_exp<7:0> : fraction<51:29>; */ | |
8777 | return make_float32(f32_sbit | | |
8778 | (r64_exp & 0xff) << 23 | | |
8779 | extract64(r64_frac, 29, 24)); | |
8780 | } | |
8781 | ||
8782 | float64 HELPER(recpe_f64)(float64 input, void *fpstp) | |
8783 | { | |
8784 | float_status *fpst = fpstp; | |
8785 | float64 f64 = float64_squash_input_denormal(input, fpst); | |
8786 | uint64_t f64_val = float64_val(f64); | |
8787 | uint64_t f64_sbit = 0x8000000000000000ULL & f64_val; | |
8788 | int64_t f64_exp = extract64(f64_val, 52, 11); | |
8789 | float64 r64; | |
8790 | uint64_t r64_val; | |
8791 | int64_t r64_exp; | |
8792 | uint64_t r64_frac; | |
8793 | ||
8794 | /* Deal with any special cases */ | |
8795 | if (float64_is_any_nan(f64)) { | |
8796 | float64 nan = f64; | |
8797 | if (float64_is_signaling_nan(f64)) { | |
8798 | float_raise(float_flag_invalid, fpst); | |
8799 | nan = float64_maybe_silence_nan(f64); | |
8800 | } | |
8801 | if (fpst->default_nan_mode) { | |
8802 | nan = float64_default_nan; | |
8803 | } | |
8804 | return nan; | |
8805 | } else if (float64_is_infinity(f64)) { | |
8806 | return float64_set_sign(float64_zero, float64_is_neg(f64)); | |
8807 | } else if (float64_is_zero(f64)) { | |
8808 | float_raise(float_flag_divbyzero, fpst); | |
8809 | return float64_set_sign(float64_infinity, float64_is_neg(f64)); | |
8810 | } else if ((f64_val & ~(1ULL << 63)) < (1ULL << 50)) { | |
8811 | /* Abs(value) < 2.0^-1024 */ | |
8812 | float_raise(float_flag_overflow | float_flag_inexact, fpst); | |
8813 | if (round_to_inf(fpst, f64_sbit)) { | |
8814 | return float64_set_sign(float64_infinity, float64_is_neg(f64)); | |
8815 | } else { | |
8816 | return float64_set_sign(float64_maxnorm, float64_is_neg(f64)); | |
8817 | } | |
fc1792e9 | 8818 | } else if (f64_exp >= 2045 && fpst->flush_to_zero) { |
b6d4443a AB |
8819 | float_raise(float_flag_underflow, fpst); |
8820 | return float64_set_sign(float64_zero, float64_is_neg(f64)); | |
8821 | } | |
fe0e4872 | 8822 | |
b6d4443a AB |
8823 | r64 = call_recip_estimate(f64, 2045, fpst); |
8824 | r64_val = float64_val(r64); | |
8825 | r64_exp = extract64(r64_val, 52, 11); | |
8826 | r64_frac = extract64(r64_val, 0, 52); | |
fe0e4872 | 8827 | |
b6d4443a AB |
8828 | /* result = sign : result_exp<10:0> : fraction<51:0> */ |
8829 | return make_float64(f64_sbit | | |
8830 | ((r64_exp & 0x7ff) << 52) | | |
8831 | r64_frac); | |
4373f3ce PB |
8832 | } |
8833 | ||
e07be5d2 CL |
8834 | /* The algorithm that must be used to calculate the estimate |
8835 | * is specified by the ARM ARM. | |
8836 | */ | |
c2fb418e | 8837 | static float64 recip_sqrt_estimate(float64 a, float_status *real_fp_status) |
e07be5d2 | 8838 | { |
1146a817 PM |
8839 | /* These calculations mustn't set any fp exception flags, |
8840 | * so we use a local copy of the fp_status. | |
8841 | */ | |
c2fb418e | 8842 | float_status dummy_status = *real_fp_status; |
1146a817 | 8843 | float_status *s = &dummy_status; |
e07be5d2 CL |
8844 | float64 q; |
8845 | int64_t q_int; | |
8846 | ||
8847 | if (float64_lt(a, float64_half, s)) { | |
8848 | /* range 0.25 <= a < 0.5 */ | |
8849 | ||
8850 | /* a in units of 1/512 rounded down */ | |
8851 | /* q0 = (int)(a * 512.0); */ | |
8852 | q = float64_mul(float64_512, a, s); | |
8853 | q_int = float64_to_int64_round_to_zero(q, s); | |
8854 | ||
8855 | /* reciprocal root r */ | |
8856 | /* r = 1.0 / sqrt(((double)q0 + 0.5) / 512.0); */ | |
8857 | q = int64_to_float64(q_int, s); | |
8858 | q = float64_add(q, float64_half, s); | |
8859 | q = float64_div(q, float64_512, s); | |
8860 | q = float64_sqrt(q, s); | |
8861 | q = float64_div(float64_one, q, s); | |
8862 | } else { | |
8863 | /* range 0.5 <= a < 1.0 */ | |
8864 | ||
8865 | /* a in units of 1/256 rounded down */ | |
8866 | /* q1 = (int)(a * 256.0); */ | |
8867 | q = float64_mul(float64_256, a, s); | |
8868 | int64_t q_int = float64_to_int64_round_to_zero(q, s); | |
8869 | ||
8870 | /* reciprocal root r */ | |
8871 | /* r = 1.0 /sqrt(((double)q1 + 0.5) / 256); */ | |
8872 | q = int64_to_float64(q_int, s); | |
8873 | q = float64_add(q, float64_half, s); | |
8874 | q = float64_div(q, float64_256, s); | |
8875 | q = float64_sqrt(q, s); | |
8876 | q = float64_div(float64_one, q, s); | |
8877 | } | |
8878 | /* r in units of 1/256 rounded to nearest */ | |
8879 | /* s = (int)(256.0 * r + 0.5); */ | |
8880 | ||
8881 | q = float64_mul(q, float64_256,s ); | |
8882 | q = float64_add(q, float64_half, s); | |
8883 | q_int = float64_to_int64_round_to_zero(q, s); | |
8884 | ||
8885 | /* return (double)s / 256.0;*/ | |
8886 | return float64_div(int64_to_float64(q_int, s), float64_256, s); | |
8887 | } | |
8888 | ||
c2fb418e | 8889 | float32 HELPER(rsqrte_f32)(float32 input, void *fpstp) |
4373f3ce | 8890 | { |
c2fb418e AB |
8891 | float_status *s = fpstp; |
8892 | float32 f32 = float32_squash_input_denormal(input, s); | |
8893 | uint32_t val = float32_val(f32); | |
8894 | uint32_t f32_sbit = 0x80000000 & val; | |
8895 | int32_t f32_exp = extract32(val, 23, 8); | |
8896 | uint32_t f32_frac = extract32(val, 0, 23); | |
8897 | uint64_t f64_frac; | |
8898 | uint64_t val64; | |
e07be5d2 CL |
8899 | int result_exp; |
8900 | float64 f64; | |
e07be5d2 | 8901 | |
c2fb418e AB |
8902 | if (float32_is_any_nan(f32)) { |
8903 | float32 nan = f32; | |
8904 | if (float32_is_signaling_nan(f32)) { | |
e07be5d2 | 8905 | float_raise(float_flag_invalid, s); |
c2fb418e | 8906 | nan = float32_maybe_silence_nan(f32); |
e07be5d2 | 8907 | } |
c2fb418e AB |
8908 | if (s->default_nan_mode) { |
8909 | nan = float32_default_nan; | |
43fe9bdb | 8910 | } |
c2fb418e AB |
8911 | return nan; |
8912 | } else if (float32_is_zero(f32)) { | |
e07be5d2 | 8913 | float_raise(float_flag_divbyzero, s); |
c2fb418e AB |
8914 | return float32_set_sign(float32_infinity, float32_is_neg(f32)); |
8915 | } else if (float32_is_neg(f32)) { | |
e07be5d2 CL |
8916 | float_raise(float_flag_invalid, s); |
8917 | return float32_default_nan; | |
c2fb418e | 8918 | } else if (float32_is_infinity(f32)) { |
e07be5d2 CL |
8919 | return float32_zero; |
8920 | } | |
8921 | ||
c2fb418e | 8922 | /* Scale and normalize to a double-precision value between 0.25 and 1.0, |
e07be5d2 | 8923 | * preserving the parity of the exponent. */ |
c2fb418e AB |
8924 | |
8925 | f64_frac = ((uint64_t) f32_frac) << 29; | |
8926 | if (f32_exp == 0) { | |
8927 | while (extract64(f64_frac, 51, 1) == 0) { | |
8928 | f64_frac = f64_frac << 1; | |
8929 | f32_exp = f32_exp-1; | |
8930 | } | |
8931 | f64_frac = extract64(f64_frac, 0, 51) << 1; | |
8932 | } | |
8933 | ||
8934 | if (extract64(f32_exp, 0, 1) == 0) { | |
8935 | f64 = make_float64(((uint64_t) f32_sbit) << 32 | |
e07be5d2 | 8936 | | (0x3feULL << 52) |
c2fb418e | 8937 | | f64_frac); |
e07be5d2 | 8938 | } else { |
c2fb418e | 8939 | f64 = make_float64(((uint64_t) f32_sbit) << 32 |
e07be5d2 | 8940 | | (0x3fdULL << 52) |
c2fb418e | 8941 | | f64_frac); |
e07be5d2 CL |
8942 | } |
8943 | ||
c2fb418e | 8944 | result_exp = (380 - f32_exp) / 2; |
e07be5d2 | 8945 | |
c2fb418e | 8946 | f64 = recip_sqrt_estimate(f64, s); |
e07be5d2 CL |
8947 | |
8948 | val64 = float64_val(f64); | |
8949 | ||
26cc6abf | 8950 | val = ((result_exp & 0xff) << 23) |
e07be5d2 CL |
8951 | | ((val64 >> 29) & 0x7fffff); |
8952 | return make_float32(val); | |
4373f3ce PB |
8953 | } |
8954 | ||
c2fb418e AB |
8955 | float64 HELPER(rsqrte_f64)(float64 input, void *fpstp) |
8956 | { | |
8957 | float_status *s = fpstp; | |
8958 | float64 f64 = float64_squash_input_denormal(input, s); | |
8959 | uint64_t val = float64_val(f64); | |
8960 | uint64_t f64_sbit = 0x8000000000000000ULL & val; | |
8961 | int64_t f64_exp = extract64(val, 52, 11); | |
8962 | uint64_t f64_frac = extract64(val, 0, 52); | |
8963 | int64_t result_exp; | |
8964 | uint64_t result_frac; | |
8965 | ||
8966 | if (float64_is_any_nan(f64)) { | |
8967 | float64 nan = f64; | |
8968 | if (float64_is_signaling_nan(f64)) { | |
8969 | float_raise(float_flag_invalid, s); | |
8970 | nan = float64_maybe_silence_nan(f64); | |
8971 | } | |
8972 | if (s->default_nan_mode) { | |
8973 | nan = float64_default_nan; | |
8974 | } | |
8975 | return nan; | |
8976 | } else if (float64_is_zero(f64)) { | |
8977 | float_raise(float_flag_divbyzero, s); | |
8978 | return float64_set_sign(float64_infinity, float64_is_neg(f64)); | |
8979 | } else if (float64_is_neg(f64)) { | |
8980 | float_raise(float_flag_invalid, s); | |
8981 | return float64_default_nan; | |
8982 | } else if (float64_is_infinity(f64)) { | |
8983 | return float64_zero; | |
8984 | } | |
8985 | ||
8986 | /* Scale and normalize to a double-precision value between 0.25 and 1.0, | |
8987 | * preserving the parity of the exponent. */ | |
8988 | ||
8989 | if (f64_exp == 0) { | |
8990 | while (extract64(f64_frac, 51, 1) == 0) { | |
8991 | f64_frac = f64_frac << 1; | |
8992 | f64_exp = f64_exp - 1; | |
8993 | } | |
8994 | f64_frac = extract64(f64_frac, 0, 51) << 1; | |
8995 | } | |
8996 | ||
8997 | if (extract64(f64_exp, 0, 1) == 0) { | |
8998 | f64 = make_float64(f64_sbit | |
8999 | | (0x3feULL << 52) | |
9000 | | f64_frac); | |
9001 | } else { | |
9002 | f64 = make_float64(f64_sbit | |
9003 | | (0x3fdULL << 52) | |
9004 | | f64_frac); | |
9005 | } | |
9006 | ||
9007 | result_exp = (3068 - f64_exp) / 2; | |
9008 | ||
9009 | f64 = recip_sqrt_estimate(f64, s); | |
9010 | ||
9011 | result_frac = extract64(float64_val(f64), 0, 52); | |
9012 | ||
9013 | return make_float64(f64_sbit | | |
9014 | ((result_exp & 0x7ff) << 52) | | |
9015 | result_frac); | |
9016 | } | |
9017 | ||
b6d4443a | 9018 | uint32_t HELPER(recpe_u32)(uint32_t a, void *fpstp) |
4373f3ce | 9019 | { |
b6d4443a | 9020 | float_status *s = fpstp; |
fe0e4872 CL |
9021 | float64 f64; |
9022 | ||
9023 | if ((a & 0x80000000) == 0) { | |
9024 | return 0xffffffff; | |
9025 | } | |
9026 | ||
9027 | f64 = make_float64((0x3feULL << 52) | |
9028 | | ((int64_t)(a & 0x7fffffff) << 21)); | |
9029 | ||
b6d4443a | 9030 | f64 = recip_estimate(f64, s); |
fe0e4872 CL |
9031 | |
9032 | return 0x80000000 | ((float64_val(f64) >> 21) & 0x7fffffff); | |
4373f3ce PB |
9033 | } |
9034 | ||
c2fb418e | 9035 | uint32_t HELPER(rsqrte_u32)(uint32_t a, void *fpstp) |
4373f3ce | 9036 | { |
c2fb418e | 9037 | float_status *fpst = fpstp; |
e07be5d2 CL |
9038 | float64 f64; |
9039 | ||
9040 | if ((a & 0xc0000000) == 0) { | |
9041 | return 0xffffffff; | |
9042 | } | |
9043 | ||
9044 | if (a & 0x80000000) { | |
9045 | f64 = make_float64((0x3feULL << 52) | |
9046 | | ((uint64_t)(a & 0x7fffffff) << 21)); | |
9047 | } else { /* bits 31-30 == '01' */ | |
9048 | f64 = make_float64((0x3fdULL << 52) | |
9049 | | ((uint64_t)(a & 0x3fffffff) << 22)); | |
9050 | } | |
9051 | ||
c2fb418e | 9052 | f64 = recip_sqrt_estimate(f64, fpst); |
e07be5d2 CL |
9053 | |
9054 | return 0x80000000 | ((float64_val(f64) >> 21) & 0x7fffffff); | |
4373f3ce | 9055 | } |
fe1479c3 | 9056 | |
da97f52c PM |
9057 | /* VFPv4 fused multiply-accumulate */ |
9058 | float32 VFP_HELPER(muladd, s)(float32 a, float32 b, float32 c, void *fpstp) | |
9059 | { | |
9060 | float_status *fpst = fpstp; | |
9061 | return float32_muladd(a, b, c, 0, fpst); | |
9062 | } | |
9063 | ||
9064 | float64 VFP_HELPER(muladd, d)(float64 a, float64 b, float64 c, void *fpstp) | |
9065 | { | |
9066 | float_status *fpst = fpstp; | |
9067 | return float64_muladd(a, b, c, 0, fpst); | |
9068 | } | |
d9b0848d PM |
9069 | |
9070 | /* ARMv8 round to integral */ | |
9071 | float32 HELPER(rints_exact)(float32 x, void *fp_status) | |
9072 | { | |
9073 | return float32_round_to_int(x, fp_status); | |
9074 | } | |
9075 | ||
9076 | float64 HELPER(rintd_exact)(float64 x, void *fp_status) | |
9077 | { | |
9078 | return float64_round_to_int(x, fp_status); | |
9079 | } | |
9080 | ||
9081 | float32 HELPER(rints)(float32 x, void *fp_status) | |
9082 | { | |
9083 | int old_flags = get_float_exception_flags(fp_status), new_flags; | |
9084 | float32 ret; | |
9085 | ||
9086 | ret = float32_round_to_int(x, fp_status); | |
9087 | ||
9088 | /* Suppress any inexact exceptions the conversion produced */ | |
9089 | if (!(old_flags & float_flag_inexact)) { | |
9090 | new_flags = get_float_exception_flags(fp_status); | |
9091 | set_float_exception_flags(new_flags & ~float_flag_inexact, fp_status); | |
9092 | } | |
9093 | ||
9094 | return ret; | |
9095 | } | |
9096 | ||
9097 | float64 HELPER(rintd)(float64 x, void *fp_status) | |
9098 | { | |
9099 | int old_flags = get_float_exception_flags(fp_status), new_flags; | |
9100 | float64 ret; | |
9101 | ||
9102 | ret = float64_round_to_int(x, fp_status); | |
9103 | ||
9104 | new_flags = get_float_exception_flags(fp_status); | |
9105 | ||
9106 | /* Suppress any inexact exceptions the conversion produced */ | |
9107 | if (!(old_flags & float_flag_inexact)) { | |
9108 | new_flags = get_float_exception_flags(fp_status); | |
9109 | set_float_exception_flags(new_flags & ~float_flag_inexact, fp_status); | |
9110 | } | |
9111 | ||
9112 | return ret; | |
9113 | } | |
9972da66 WN |
9114 | |
9115 | /* Convert ARM rounding mode to softfloat */ | |
9116 | int arm_rmode_to_sf(int rmode) | |
9117 | { | |
9118 | switch (rmode) { | |
9119 | case FPROUNDING_TIEAWAY: | |
9120 | rmode = float_round_ties_away; | |
9121 | break; | |
9122 | case FPROUNDING_ODD: | |
9123 | /* FIXME: add support for TIEAWAY and ODD */ | |
9124 | qemu_log_mask(LOG_UNIMP, "arm: unimplemented rounding mode: %d\n", | |
9125 | rmode); | |
9126 | case FPROUNDING_TIEEVEN: | |
9127 | default: | |
9128 | rmode = float_round_nearest_even; | |
9129 | break; | |
9130 | case FPROUNDING_POSINF: | |
9131 | rmode = float_round_up; | |
9132 | break; | |
9133 | case FPROUNDING_NEGINF: | |
9134 | rmode = float_round_down; | |
9135 | break; | |
9136 | case FPROUNDING_ZERO: | |
9137 | rmode = float_round_to_zero; | |
9138 | break; | |
9139 | } | |
9140 | return rmode; | |
9141 | } | |
eb0ecd5a | 9142 | |
aa633469 PM |
9143 | /* CRC helpers. |
9144 | * The upper bytes of val (above the number specified by 'bytes') must have | |
9145 | * been zeroed out by the caller. | |
9146 | */ | |
eb0ecd5a WN |
9147 | uint32_t HELPER(crc32)(uint32_t acc, uint32_t val, uint32_t bytes) |
9148 | { | |
9149 | uint8_t buf[4]; | |
9150 | ||
aa633469 | 9151 | stl_le_p(buf, val); |
eb0ecd5a WN |
9152 | |
9153 | /* zlib crc32 converts the accumulator and output to one's complement. */ | |
9154 | return crc32(acc ^ 0xffffffff, buf, bytes) ^ 0xffffffff; | |
9155 | } | |
9156 | ||
9157 | uint32_t HELPER(crc32c)(uint32_t acc, uint32_t val, uint32_t bytes) | |
9158 | { | |
9159 | uint8_t buf[4]; | |
9160 | ||
aa633469 | 9161 | stl_le_p(buf, val); |
eb0ecd5a WN |
9162 | |
9163 | /* Linux crc32c converts the output to one's complement. */ | |
9164 | return crc32c(acc, buf, bytes) ^ 0xffffffff; | |
9165 | } |