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Commit | Line | Data |
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b5ff1b31 | 1 | #include "cpu.h" |
ccd38087 | 2 | #include "internals.h" |
022c62cb | 3 | #include "exec/gdbstub.h" |
7b59220e | 4 | #include "helper.h" |
1de7afc9 | 5 | #include "qemu/host-utils.h" |
78027bb6 | 6 | #include "sysemu/arch_init.h" |
9c17d615 | 7 | #include "sysemu/sysemu.h" |
1de7afc9 | 8 | #include "qemu/bitops.h" |
eb0ecd5a WN |
9 | #include "qemu/crc32c.h" |
10 | #include <zlib.h> /* For crc32 */ | |
0b03bdfc | 11 | |
4a501606 PM |
12 | #ifndef CONFIG_USER_ONLY |
13 | static inline int get_phys_addr(CPUARMState *env, uint32_t address, | |
14 | int access_type, int is_user, | |
a8170e5e | 15 | hwaddr *phys_ptr, int *prot, |
4a501606 | 16 | target_ulong *page_size); |
7c2cb42b AF |
17 | |
18 | /* Definitions for the PMCCNTR and PMCR registers */ | |
19 | #define PMCRD 0x8 | |
20 | #define PMCRC 0x4 | |
21 | #define PMCRE 0x1 | |
4a501606 PM |
22 | #endif |
23 | ||
0ecb72a5 | 24 | static int vfp_gdb_get_reg(CPUARMState *env, uint8_t *buf, int reg) |
56aebc89 PB |
25 | { |
26 | int nregs; | |
27 | ||
28 | /* VFP data registers are always little-endian. */ | |
29 | nregs = arm_feature(env, ARM_FEATURE_VFP3) ? 32 : 16; | |
30 | if (reg < nregs) { | |
31 | stfq_le_p(buf, env->vfp.regs[reg]); | |
32 | return 8; | |
33 | } | |
34 | if (arm_feature(env, ARM_FEATURE_NEON)) { | |
35 | /* Aliases for Q regs. */ | |
36 | nregs += 16; | |
37 | if (reg < nregs) { | |
38 | stfq_le_p(buf, env->vfp.regs[(reg - 32) * 2]); | |
39 | stfq_le_p(buf + 8, env->vfp.regs[(reg - 32) * 2 + 1]); | |
40 | return 16; | |
41 | } | |
42 | } | |
43 | switch (reg - nregs) { | |
44 | case 0: stl_p(buf, env->vfp.xregs[ARM_VFP_FPSID]); return 4; | |
45 | case 1: stl_p(buf, env->vfp.xregs[ARM_VFP_FPSCR]); return 4; | |
46 | case 2: stl_p(buf, env->vfp.xregs[ARM_VFP_FPEXC]); return 4; | |
47 | } | |
48 | return 0; | |
49 | } | |
50 | ||
0ecb72a5 | 51 | static int vfp_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg) |
56aebc89 PB |
52 | { |
53 | int nregs; | |
54 | ||
55 | nregs = arm_feature(env, ARM_FEATURE_VFP3) ? 32 : 16; | |
56 | if (reg < nregs) { | |
57 | env->vfp.regs[reg] = ldfq_le_p(buf); | |
58 | return 8; | |
59 | } | |
60 | if (arm_feature(env, ARM_FEATURE_NEON)) { | |
61 | nregs += 16; | |
62 | if (reg < nregs) { | |
63 | env->vfp.regs[(reg - 32) * 2] = ldfq_le_p(buf); | |
64 | env->vfp.regs[(reg - 32) * 2 + 1] = ldfq_le_p(buf + 8); | |
65 | return 16; | |
66 | } | |
67 | } | |
68 | switch (reg - nregs) { | |
69 | case 0: env->vfp.xregs[ARM_VFP_FPSID] = ldl_p(buf); return 4; | |
70 | case 1: env->vfp.xregs[ARM_VFP_FPSCR] = ldl_p(buf); return 4; | |
71b3c3de | 71 | case 2: env->vfp.xregs[ARM_VFP_FPEXC] = ldl_p(buf) & (1 << 30); return 4; |
56aebc89 PB |
72 | } |
73 | return 0; | |
74 | } | |
75 | ||
6a669427 PM |
76 | static int aarch64_fpu_gdb_get_reg(CPUARMState *env, uint8_t *buf, int reg) |
77 | { | |
78 | switch (reg) { | |
79 | case 0 ... 31: | |
80 | /* 128 bit FP register */ | |
81 | stfq_le_p(buf, env->vfp.regs[reg * 2]); | |
82 | stfq_le_p(buf + 8, env->vfp.regs[reg * 2 + 1]); | |
83 | return 16; | |
84 | case 32: | |
85 | /* FPSR */ | |
86 | stl_p(buf, vfp_get_fpsr(env)); | |
87 | return 4; | |
88 | case 33: | |
89 | /* FPCR */ | |
90 | stl_p(buf, vfp_get_fpcr(env)); | |
91 | return 4; | |
92 | default: | |
93 | return 0; | |
94 | } | |
95 | } | |
96 | ||
97 | static int aarch64_fpu_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg) | |
98 | { | |
99 | switch (reg) { | |
100 | case 0 ... 31: | |
101 | /* 128 bit FP register */ | |
102 | env->vfp.regs[reg * 2] = ldfq_le_p(buf); | |
103 | env->vfp.regs[reg * 2 + 1] = ldfq_le_p(buf + 8); | |
104 | return 16; | |
105 | case 32: | |
106 | /* FPSR */ | |
107 | vfp_set_fpsr(env, ldl_p(buf)); | |
108 | return 4; | |
109 | case 33: | |
110 | /* FPCR */ | |
111 | vfp_set_fpcr(env, ldl_p(buf)); | |
112 | return 4; | |
113 | default: | |
114 | return 0; | |
115 | } | |
116 | } | |
117 | ||
c4241c7d | 118 | static uint64_t raw_read(CPUARMState *env, const ARMCPRegInfo *ri) |
d4e6df63 | 119 | { |
67ed771d | 120 | if (cpreg_field_is_64bit(ri)) { |
c4241c7d | 121 | return CPREG_FIELD64(env, ri); |
22d9e1a9 | 122 | } else { |
c4241c7d | 123 | return CPREG_FIELD32(env, ri); |
22d9e1a9 | 124 | } |
d4e6df63 PM |
125 | } |
126 | ||
c4241c7d PM |
127 | static void raw_write(CPUARMState *env, const ARMCPRegInfo *ri, |
128 | uint64_t value) | |
d4e6df63 | 129 | { |
67ed771d | 130 | if (cpreg_field_is_64bit(ri)) { |
22d9e1a9 PM |
131 | CPREG_FIELD64(env, ri) = value; |
132 | } else { | |
133 | CPREG_FIELD32(env, ri) = value; | |
134 | } | |
d4e6df63 PM |
135 | } |
136 | ||
59a1c327 | 137 | static uint64_t read_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri) |
721fae12 | 138 | { |
59a1c327 | 139 | /* Raw read of a coprocessor register (as needed for migration, etc). */ |
721fae12 | 140 | if (ri->type & ARM_CP_CONST) { |
59a1c327 | 141 | return ri->resetvalue; |
721fae12 | 142 | } else if (ri->raw_readfn) { |
59a1c327 | 143 | return ri->raw_readfn(env, ri); |
721fae12 | 144 | } else if (ri->readfn) { |
59a1c327 | 145 | return ri->readfn(env, ri); |
721fae12 | 146 | } else { |
59a1c327 | 147 | return raw_read(env, ri); |
721fae12 | 148 | } |
721fae12 PM |
149 | } |
150 | ||
59a1c327 | 151 | static void write_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri, |
7900e9f1 | 152 | uint64_t v) |
721fae12 PM |
153 | { |
154 | /* Raw write of a coprocessor register (as needed for migration, etc). | |
721fae12 PM |
155 | * Note that constant registers are treated as write-ignored; the |
156 | * caller should check for success by whether a readback gives the | |
157 | * value written. | |
158 | */ | |
159 | if (ri->type & ARM_CP_CONST) { | |
59a1c327 | 160 | return; |
721fae12 | 161 | } else if (ri->raw_writefn) { |
c4241c7d | 162 | ri->raw_writefn(env, ri, v); |
721fae12 | 163 | } else if (ri->writefn) { |
c4241c7d | 164 | ri->writefn(env, ri, v); |
721fae12 | 165 | } else { |
afb2530f | 166 | raw_write(env, ri, v); |
721fae12 | 167 | } |
721fae12 PM |
168 | } |
169 | ||
170 | bool write_cpustate_to_list(ARMCPU *cpu) | |
171 | { | |
172 | /* Write the coprocessor state from cpu->env to the (index,value) list. */ | |
173 | int i; | |
174 | bool ok = true; | |
175 | ||
176 | for (i = 0; i < cpu->cpreg_array_len; i++) { | |
177 | uint32_t regidx = kvm_to_cpreg_id(cpu->cpreg_indexes[i]); | |
178 | const ARMCPRegInfo *ri; | |
59a1c327 | 179 | |
60322b39 | 180 | ri = get_arm_cp_reginfo(cpu->cp_regs, regidx); |
721fae12 PM |
181 | if (!ri) { |
182 | ok = false; | |
183 | continue; | |
184 | } | |
185 | if (ri->type & ARM_CP_NO_MIGRATE) { | |
186 | continue; | |
187 | } | |
59a1c327 | 188 | cpu->cpreg_values[i] = read_raw_cp_reg(&cpu->env, ri); |
721fae12 PM |
189 | } |
190 | return ok; | |
191 | } | |
192 | ||
193 | bool write_list_to_cpustate(ARMCPU *cpu) | |
194 | { | |
195 | int i; | |
196 | bool ok = true; | |
197 | ||
198 | for (i = 0; i < cpu->cpreg_array_len; i++) { | |
199 | uint32_t regidx = kvm_to_cpreg_id(cpu->cpreg_indexes[i]); | |
200 | uint64_t v = cpu->cpreg_values[i]; | |
721fae12 PM |
201 | const ARMCPRegInfo *ri; |
202 | ||
60322b39 | 203 | ri = get_arm_cp_reginfo(cpu->cp_regs, regidx); |
721fae12 PM |
204 | if (!ri) { |
205 | ok = false; | |
206 | continue; | |
207 | } | |
208 | if (ri->type & ARM_CP_NO_MIGRATE) { | |
209 | continue; | |
210 | } | |
211 | /* Write value and confirm it reads back as written | |
212 | * (to catch read-only registers and partially read-only | |
213 | * registers where the incoming migration value doesn't match) | |
214 | */ | |
59a1c327 PM |
215 | write_raw_cp_reg(&cpu->env, ri, v); |
216 | if (read_raw_cp_reg(&cpu->env, ri) != v) { | |
721fae12 PM |
217 | ok = false; |
218 | } | |
219 | } | |
220 | return ok; | |
221 | } | |
222 | ||
223 | static void add_cpreg_to_list(gpointer key, gpointer opaque) | |
224 | { | |
225 | ARMCPU *cpu = opaque; | |
226 | uint64_t regidx; | |
227 | const ARMCPRegInfo *ri; | |
228 | ||
229 | regidx = *(uint32_t *)key; | |
60322b39 | 230 | ri = get_arm_cp_reginfo(cpu->cp_regs, regidx); |
721fae12 PM |
231 | |
232 | if (!(ri->type & ARM_CP_NO_MIGRATE)) { | |
233 | cpu->cpreg_indexes[cpu->cpreg_array_len] = cpreg_to_kvm_id(regidx); | |
234 | /* The value array need not be initialized at this point */ | |
235 | cpu->cpreg_array_len++; | |
236 | } | |
237 | } | |
238 | ||
239 | static void count_cpreg(gpointer key, gpointer opaque) | |
240 | { | |
241 | ARMCPU *cpu = opaque; | |
242 | uint64_t regidx; | |
243 | const ARMCPRegInfo *ri; | |
244 | ||
245 | regidx = *(uint32_t *)key; | |
60322b39 | 246 | ri = get_arm_cp_reginfo(cpu->cp_regs, regidx); |
721fae12 PM |
247 | |
248 | if (!(ri->type & ARM_CP_NO_MIGRATE)) { | |
249 | cpu->cpreg_array_len++; | |
250 | } | |
251 | } | |
252 | ||
253 | static gint cpreg_key_compare(gconstpointer a, gconstpointer b) | |
254 | { | |
cbf239b7 AR |
255 | uint64_t aidx = cpreg_to_kvm_id(*(uint32_t *)a); |
256 | uint64_t bidx = cpreg_to_kvm_id(*(uint32_t *)b); | |
721fae12 | 257 | |
cbf239b7 AR |
258 | if (aidx > bidx) { |
259 | return 1; | |
260 | } | |
261 | if (aidx < bidx) { | |
262 | return -1; | |
263 | } | |
264 | return 0; | |
721fae12 PM |
265 | } |
266 | ||
82a3a118 PM |
267 | static void cpreg_make_keylist(gpointer key, gpointer value, gpointer udata) |
268 | { | |
269 | GList **plist = udata; | |
270 | ||
271 | *plist = g_list_prepend(*plist, key); | |
272 | } | |
273 | ||
721fae12 PM |
274 | void init_cpreg_list(ARMCPU *cpu) |
275 | { | |
276 | /* Initialise the cpreg_tuples[] array based on the cp_regs hash. | |
277 | * Note that we require cpreg_tuples[] to be sorted by key ID. | |
278 | */ | |
82a3a118 | 279 | GList *keys = NULL; |
721fae12 PM |
280 | int arraylen; |
281 | ||
82a3a118 PM |
282 | g_hash_table_foreach(cpu->cp_regs, cpreg_make_keylist, &keys); |
283 | ||
721fae12 PM |
284 | keys = g_list_sort(keys, cpreg_key_compare); |
285 | ||
286 | cpu->cpreg_array_len = 0; | |
287 | ||
288 | g_list_foreach(keys, count_cpreg, cpu); | |
289 | ||
290 | arraylen = cpu->cpreg_array_len; | |
291 | cpu->cpreg_indexes = g_new(uint64_t, arraylen); | |
292 | cpu->cpreg_values = g_new(uint64_t, arraylen); | |
293 | cpu->cpreg_vmstate_indexes = g_new(uint64_t, arraylen); | |
294 | cpu->cpreg_vmstate_values = g_new(uint64_t, arraylen); | |
295 | cpu->cpreg_vmstate_array_len = cpu->cpreg_array_len; | |
296 | cpu->cpreg_array_len = 0; | |
297 | ||
298 | g_list_foreach(keys, add_cpreg_to_list, cpu); | |
299 | ||
300 | assert(cpu->cpreg_array_len == arraylen); | |
301 | ||
302 | g_list_free(keys); | |
303 | } | |
304 | ||
c4241c7d | 305 | static void dacr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) |
c983fe6c | 306 | { |
00c8cb0a AF |
307 | ARMCPU *cpu = arm_env_get_cpu(env); |
308 | ||
c983fe6c | 309 | env->cp15.c3 = value; |
00c8cb0a | 310 | tlb_flush(CPU(cpu), 1); /* Flush TLB as domain not tracked in TLB */ |
c983fe6c PM |
311 | } |
312 | ||
c4241c7d | 313 | static void fcse_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) |
08de207b | 314 | { |
00c8cb0a AF |
315 | ARMCPU *cpu = arm_env_get_cpu(env); |
316 | ||
08de207b PM |
317 | if (env->cp15.c13_fcse != value) { |
318 | /* Unlike real hardware the qemu TLB uses virtual addresses, | |
319 | * not modified virtual addresses, so this causes a TLB flush. | |
320 | */ | |
00c8cb0a | 321 | tlb_flush(CPU(cpu), 1); |
08de207b PM |
322 | env->cp15.c13_fcse = value; |
323 | } | |
08de207b | 324 | } |
c4241c7d PM |
325 | |
326 | static void contextidr_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
327 | uint64_t value) | |
08de207b | 328 | { |
00c8cb0a AF |
329 | ARMCPU *cpu = arm_env_get_cpu(env); |
330 | ||
08de207b PM |
331 | if (env->cp15.c13_context != value && !arm_feature(env, ARM_FEATURE_MPU)) { |
332 | /* For VMSA (when not using the LPAE long descriptor page table | |
333 | * format) this register includes the ASID, so do a TLB flush. | |
334 | * For PMSA it is purely a process ID and no action is needed. | |
335 | */ | |
00c8cb0a | 336 | tlb_flush(CPU(cpu), 1); |
08de207b PM |
337 | } |
338 | env->cp15.c13_context = value; | |
08de207b PM |
339 | } |
340 | ||
c4241c7d PM |
341 | static void tlbiall_write(CPUARMState *env, const ARMCPRegInfo *ri, |
342 | uint64_t value) | |
d929823f PM |
343 | { |
344 | /* Invalidate all (TLBIALL) */ | |
00c8cb0a AF |
345 | ARMCPU *cpu = arm_env_get_cpu(env); |
346 | ||
347 | tlb_flush(CPU(cpu), 1); | |
d929823f PM |
348 | } |
349 | ||
c4241c7d PM |
350 | static void tlbimva_write(CPUARMState *env, const ARMCPRegInfo *ri, |
351 | uint64_t value) | |
d929823f PM |
352 | { |
353 | /* Invalidate single TLB entry by MVA and ASID (TLBIMVA) */ | |
31b030d4 AF |
354 | ARMCPU *cpu = arm_env_get_cpu(env); |
355 | ||
356 | tlb_flush_page(CPU(cpu), value & TARGET_PAGE_MASK); | |
d929823f PM |
357 | } |
358 | ||
c4241c7d PM |
359 | static void tlbiasid_write(CPUARMState *env, const ARMCPRegInfo *ri, |
360 | uint64_t value) | |
d929823f PM |
361 | { |
362 | /* Invalidate by ASID (TLBIASID) */ | |
00c8cb0a AF |
363 | ARMCPU *cpu = arm_env_get_cpu(env); |
364 | ||
365 | tlb_flush(CPU(cpu), value == 0); | |
d929823f PM |
366 | } |
367 | ||
c4241c7d PM |
368 | static void tlbimvaa_write(CPUARMState *env, const ARMCPRegInfo *ri, |
369 | uint64_t value) | |
d929823f PM |
370 | { |
371 | /* Invalidate single entry by MVA, all ASIDs (TLBIMVAA) */ | |
31b030d4 AF |
372 | ARMCPU *cpu = arm_env_get_cpu(env); |
373 | ||
374 | tlb_flush_page(CPU(cpu), value & TARGET_PAGE_MASK); | |
d929823f PM |
375 | } |
376 | ||
e9aa6c21 PM |
377 | static const ARMCPRegInfo cp_reginfo[] = { |
378 | /* DBGDIDR: just RAZ. In particular this means the "debug architecture | |
379 | * version" bits will read as a reserved value, which should cause | |
380 | * Linux to not try to use the debug hardware. | |
381 | */ | |
382 | { .name = "DBGDIDR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 0, | |
383 | .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
c983fe6c PM |
384 | /* MMU Domain access control / MPU write buffer control */ |
385 | { .name = "DACR", .cp = 15, | |
386 | .crn = 3, .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY, | |
387 | .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c3), | |
d4e6df63 | 388 | .resetvalue = 0, .writefn = dacr_write, .raw_writefn = raw_write, }, |
08de207b PM |
389 | { .name = "FCSEIDR", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 0, |
390 | .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c13_fcse), | |
d4e6df63 | 391 | .resetvalue = 0, .writefn = fcse_write, .raw_writefn = raw_write, }, |
08de207b | 392 | { .name = "CONTEXTIDR", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 1, |
a4f0cec6 | 393 | .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c13_context), |
d4e6df63 | 394 | .resetvalue = 0, .writefn = contextidr_write, .raw_writefn = raw_write, }, |
4fdd17dd PM |
395 | /* ??? This covers not just the impdef TLB lockdown registers but also |
396 | * some v7VMSA registers relating to TEX remap, so it is overly broad. | |
397 | */ | |
398 | { .name = "TLB_LOCKDOWN", .cp = 15, .crn = 10, .crm = CP_ANY, | |
399 | .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_NOP }, | |
d929823f PM |
400 | /* MMU TLB control. Note that the wildcarding means we cover not just |
401 | * the unified TLB ops but also the dside/iside/inner-shareable variants. | |
402 | */ | |
403 | { .name = "TLBIALL", .cp = 15, .crn = 8, .crm = CP_ANY, | |
d4e6df63 PM |
404 | .opc1 = CP_ANY, .opc2 = 0, .access = PL1_W, .writefn = tlbiall_write, |
405 | .type = ARM_CP_NO_MIGRATE }, | |
d929823f | 406 | { .name = "TLBIMVA", .cp = 15, .crn = 8, .crm = CP_ANY, |
d4e6df63 PM |
407 | .opc1 = CP_ANY, .opc2 = 1, .access = PL1_W, .writefn = tlbimva_write, |
408 | .type = ARM_CP_NO_MIGRATE }, | |
d929823f | 409 | { .name = "TLBIASID", .cp = 15, .crn = 8, .crm = CP_ANY, |
d4e6df63 PM |
410 | .opc1 = CP_ANY, .opc2 = 2, .access = PL1_W, .writefn = tlbiasid_write, |
411 | .type = ARM_CP_NO_MIGRATE }, | |
d929823f | 412 | { .name = "TLBIMVAA", .cp = 15, .crn = 8, .crm = CP_ANY, |
d4e6df63 PM |
413 | .opc1 = CP_ANY, .opc2 = 3, .access = PL1_W, .writefn = tlbimvaa_write, |
414 | .type = ARM_CP_NO_MIGRATE }, | |
c4804214 PM |
415 | /* Cache maintenance ops; some of this space may be overridden later. */ |
416 | { .name = "CACHEMAINT", .cp = 15, .crn = 7, .crm = CP_ANY, | |
417 | .opc1 = 0, .opc2 = CP_ANY, .access = PL1_W, | |
418 | .type = ARM_CP_NOP | ARM_CP_OVERRIDE }, | |
e9aa6c21 PM |
419 | REGINFO_SENTINEL |
420 | }; | |
421 | ||
7d57f408 PM |
422 | static const ARMCPRegInfo not_v6_cp_reginfo[] = { |
423 | /* Not all pre-v6 cores implemented this WFI, so this is slightly | |
424 | * over-broad. | |
425 | */ | |
426 | { .name = "WFI_v5", .cp = 15, .crn = 7, .crm = 8, .opc1 = 0, .opc2 = 2, | |
427 | .access = PL1_W, .type = ARM_CP_WFI }, | |
428 | REGINFO_SENTINEL | |
429 | }; | |
430 | ||
431 | static const ARMCPRegInfo not_v7_cp_reginfo[] = { | |
432 | /* Standard v6 WFI (also used in some pre-v6 cores); not in v7 (which | |
433 | * is UNPREDICTABLE; we choose to NOP as most implementations do). | |
434 | */ | |
435 | { .name = "WFI_v6", .cp = 15, .crn = 7, .crm = 0, .opc1 = 0, .opc2 = 4, | |
436 | .access = PL1_W, .type = ARM_CP_WFI }, | |
34f90529 PM |
437 | /* L1 cache lockdown. Not architectural in v6 and earlier but in practice |
438 | * implemented in 926, 946, 1026, 1136, 1176 and 11MPCore. StrongARM and | |
439 | * OMAPCP will override this space. | |
440 | */ | |
441 | { .name = "DLOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 0, .opc2 = 0, | |
442 | .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_data), | |
443 | .resetvalue = 0 }, | |
444 | { .name = "ILOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 0, .opc2 = 1, | |
445 | .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_insn), | |
446 | .resetvalue = 0 }, | |
776d4e5c PM |
447 | /* v6 doesn't have the cache ID registers but Linux reads them anyway */ |
448 | { .name = "DUMMY", .cp = 15, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = CP_ANY, | |
d4e6df63 PM |
449 | .access = PL1_R, .type = ARM_CP_CONST | ARM_CP_NO_MIGRATE, |
450 | .resetvalue = 0 }, | |
7d57f408 PM |
451 | REGINFO_SENTINEL |
452 | }; | |
453 | ||
c4241c7d PM |
454 | static void cpacr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
455 | uint64_t value) | |
2771db27 PM |
456 | { |
457 | if (env->cp15.c1_coproc != value) { | |
458 | env->cp15.c1_coproc = value; | |
459 | /* ??? Is this safe when called from within a TB? */ | |
460 | tb_flush(env); | |
461 | } | |
2771db27 PM |
462 | } |
463 | ||
7d57f408 PM |
464 | static const ARMCPRegInfo v6_cp_reginfo[] = { |
465 | /* prefetch by MVA in v6, NOP in v7 */ | |
466 | { .name = "MVA_prefetch", | |
467 | .cp = 15, .crn = 7, .crm = 13, .opc1 = 0, .opc2 = 1, | |
468 | .access = PL1_W, .type = ARM_CP_NOP }, | |
469 | { .name = "ISB", .cp = 15, .crn = 7, .crm = 5, .opc1 = 0, .opc2 = 4, | |
470 | .access = PL0_W, .type = ARM_CP_NOP }, | |
091fd17c | 471 | { .name = "DSB", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 4, |
7d57f408 | 472 | .access = PL0_W, .type = ARM_CP_NOP }, |
091fd17c | 473 | { .name = "DMB", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 5, |
7d57f408 | 474 | .access = PL0_W, .type = ARM_CP_NOP }, |
06d76f31 PM |
475 | { .name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 2, |
476 | .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c6_insn), | |
477 | .resetvalue = 0, }, | |
478 | /* Watchpoint Fault Address Register : should actually only be present | |
479 | * for 1136, 1176, 11MPCore. | |
480 | */ | |
481 | { .name = "WFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1, | |
482 | .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0, }, | |
34222fb8 PM |
483 | { .name = "CPACR", .state = ARM_CP_STATE_BOTH, .opc0 = 3, |
484 | .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 2, | |
2771db27 PM |
485 | .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c1_coproc), |
486 | .resetvalue = 0, .writefn = cpacr_write }, | |
7d57f408 PM |
487 | REGINFO_SENTINEL |
488 | }; | |
489 | ||
fcd25206 | 490 | static CPAccessResult pmreg_access(CPUARMState *env, const ARMCPRegInfo *ri) |
200ac0ef | 491 | { |
3b163b01 | 492 | /* Performance monitor registers user accessibility is controlled |
fcd25206 | 493 | * by PMUSERENR. |
200ac0ef PM |
494 | */ |
495 | if (arm_current_pl(env) == 0 && !env->cp15.c9_pmuserenr) { | |
fcd25206 | 496 | return CP_ACCESS_TRAP; |
200ac0ef | 497 | } |
fcd25206 | 498 | return CP_ACCESS_OK; |
200ac0ef PM |
499 | } |
500 | ||
7c2cb42b | 501 | #ifndef CONFIG_USER_ONLY |
c4241c7d PM |
502 | static void pmcr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
503 | uint64_t value) | |
200ac0ef | 504 | { |
7c2cb42b AF |
505 | /* Don't computer the number of ticks in user mode */ |
506 | uint32_t temp_ticks; | |
507 | ||
508 | temp_ticks = qemu_clock_get_us(QEMU_CLOCK_VIRTUAL) * | |
509 | get_ticks_per_sec() / 1000000; | |
510 | ||
511 | if (env->cp15.c9_pmcr & PMCRE) { | |
512 | /* If the counter is enabled */ | |
513 | if (env->cp15.c9_pmcr & PMCRD) { | |
514 | /* Increment once every 64 processor clock cycles */ | |
515 | env->cp15.c15_ccnt = (temp_ticks/64) - env->cp15.c15_ccnt; | |
516 | } else { | |
517 | env->cp15.c15_ccnt = temp_ticks - env->cp15.c15_ccnt; | |
518 | } | |
519 | } | |
520 | ||
521 | if (value & PMCRC) { | |
522 | /* The counter has been reset */ | |
523 | env->cp15.c15_ccnt = 0; | |
524 | } | |
525 | ||
200ac0ef PM |
526 | /* only the DP, X, D and E bits are writable */ |
527 | env->cp15.c9_pmcr &= ~0x39; | |
528 | env->cp15.c9_pmcr |= (value & 0x39); | |
7c2cb42b AF |
529 | |
530 | if (env->cp15.c9_pmcr & PMCRE) { | |
531 | if (env->cp15.c9_pmcr & PMCRD) { | |
532 | /* Increment once every 64 processor clock cycles */ | |
533 | temp_ticks /= 64; | |
534 | } | |
535 | env->cp15.c15_ccnt = temp_ticks - env->cp15.c15_ccnt; | |
536 | } | |
537 | } | |
538 | ||
539 | static uint64_t pmccntr_read(CPUARMState *env, const ARMCPRegInfo *ri) | |
540 | { | |
541 | uint32_t total_ticks; | |
542 | ||
543 | if (!(env->cp15.c9_pmcr & PMCRE)) { | |
544 | /* Counter is disabled, do not change value */ | |
545 | return env->cp15.c15_ccnt; | |
546 | } | |
547 | ||
548 | total_ticks = qemu_clock_get_us(QEMU_CLOCK_VIRTUAL) * | |
549 | get_ticks_per_sec() / 1000000; | |
550 | ||
551 | if (env->cp15.c9_pmcr & PMCRD) { | |
552 | /* Increment once every 64 processor clock cycles */ | |
553 | total_ticks /= 64; | |
554 | } | |
555 | return total_ticks - env->cp15.c15_ccnt; | |
556 | } | |
557 | ||
558 | static void pmccntr_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
559 | uint64_t value) | |
560 | { | |
561 | uint32_t total_ticks; | |
562 | ||
563 | if (!(env->cp15.c9_pmcr & PMCRE)) { | |
564 | /* Counter is disabled, set the absolute value */ | |
565 | env->cp15.c15_ccnt = value; | |
566 | return; | |
567 | } | |
568 | ||
569 | total_ticks = qemu_clock_get_us(QEMU_CLOCK_VIRTUAL) * | |
570 | get_ticks_per_sec() / 1000000; | |
571 | ||
572 | if (env->cp15.c9_pmcr & PMCRD) { | |
573 | /* Increment once every 64 processor clock cycles */ | |
574 | total_ticks /= 64; | |
575 | } | |
576 | env->cp15.c15_ccnt = total_ticks - value; | |
200ac0ef | 577 | } |
7c2cb42b | 578 | #endif |
200ac0ef | 579 | |
c4241c7d | 580 | static void pmcntenset_write(CPUARMState *env, const ARMCPRegInfo *ri, |
200ac0ef PM |
581 | uint64_t value) |
582 | { | |
200ac0ef PM |
583 | value &= (1 << 31); |
584 | env->cp15.c9_pmcnten |= value; | |
200ac0ef PM |
585 | } |
586 | ||
c4241c7d PM |
587 | static void pmcntenclr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
588 | uint64_t value) | |
200ac0ef | 589 | { |
200ac0ef PM |
590 | value &= (1 << 31); |
591 | env->cp15.c9_pmcnten &= ~value; | |
200ac0ef PM |
592 | } |
593 | ||
c4241c7d PM |
594 | static void pmovsr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
595 | uint64_t value) | |
200ac0ef | 596 | { |
200ac0ef | 597 | env->cp15.c9_pmovsr &= ~value; |
200ac0ef PM |
598 | } |
599 | ||
c4241c7d PM |
600 | static void pmxevtyper_write(CPUARMState *env, const ARMCPRegInfo *ri, |
601 | uint64_t value) | |
200ac0ef | 602 | { |
200ac0ef | 603 | env->cp15.c9_pmxevtyper = value & 0xff; |
200ac0ef PM |
604 | } |
605 | ||
c4241c7d | 606 | static void pmuserenr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
200ac0ef PM |
607 | uint64_t value) |
608 | { | |
609 | env->cp15.c9_pmuserenr = value & 1; | |
200ac0ef PM |
610 | } |
611 | ||
c4241c7d PM |
612 | static void pmintenset_write(CPUARMState *env, const ARMCPRegInfo *ri, |
613 | uint64_t value) | |
200ac0ef PM |
614 | { |
615 | /* We have no event counters so only the C bit can be changed */ | |
616 | value &= (1 << 31); | |
617 | env->cp15.c9_pminten |= value; | |
200ac0ef PM |
618 | } |
619 | ||
c4241c7d PM |
620 | static void pmintenclr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
621 | uint64_t value) | |
200ac0ef PM |
622 | { |
623 | value &= (1 << 31); | |
624 | env->cp15.c9_pminten &= ~value; | |
200ac0ef PM |
625 | } |
626 | ||
c4241c7d PM |
627 | static void vbar_write(CPUARMState *env, const ARMCPRegInfo *ri, |
628 | uint64_t value) | |
8641136c | 629 | { |
a505d7fe PM |
630 | /* Note that even though the AArch64 view of this register has bits |
631 | * [10:0] all RES0 we can only mask the bottom 5, to comply with the | |
632 | * architectural requirements for bits which are RES0 only in some | |
633 | * contexts. (ARMv8 would permit us to do no masking at all, but ARMv7 | |
634 | * requires the bottom five bits to be RAZ/WI because they're UNK/SBZP.) | |
635 | */ | |
8641136c | 636 | env->cp15.c12_vbar = value & ~0x1Ful; |
8641136c NR |
637 | } |
638 | ||
c4241c7d | 639 | static uint64_t ccsidr_read(CPUARMState *env, const ARMCPRegInfo *ri) |
776d4e5c PM |
640 | { |
641 | ARMCPU *cpu = arm_env_get_cpu(env); | |
c4241c7d | 642 | return cpu->ccsidr[env->cp15.c0_cssel]; |
776d4e5c PM |
643 | } |
644 | ||
c4241c7d PM |
645 | static void csselr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
646 | uint64_t value) | |
776d4e5c PM |
647 | { |
648 | env->cp15.c0_cssel = value & 0xf; | |
776d4e5c PM |
649 | } |
650 | ||
e9aa6c21 PM |
651 | static const ARMCPRegInfo v7_cp_reginfo[] = { |
652 | /* DBGDRAR, DBGDSAR: always RAZ since we don't implement memory mapped | |
653 | * debug components | |
654 | */ | |
655 | { .name = "DBGDRAR", .cp = 14, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 0, | |
656 | .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
091fd17c | 657 | { .name = "DBGDSAR", .cp = 14, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 0, |
e9aa6c21 | 658 | .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 }, |
7d57f408 PM |
659 | /* the old v6 WFI, UNPREDICTABLE in v7 but we choose to NOP */ |
660 | { .name = "NOP", .cp = 15, .crn = 7, .crm = 0, .opc1 = 0, .opc2 = 4, | |
661 | .access = PL1_W, .type = ARM_CP_NOP }, | |
200ac0ef PM |
662 | /* Performance monitors are implementation defined in v7, |
663 | * but with an ARM recommended set of registers, which we | |
664 | * follow (although we don't actually implement any counters) | |
665 | * | |
666 | * Performance registers fall into three categories: | |
667 | * (a) always UNDEF in PL0, RW in PL1 (PMINTENSET, PMINTENCLR) | |
668 | * (b) RO in PL0 (ie UNDEF on write), RW in PL1 (PMUSERENR) | |
669 | * (c) UNDEF in PL0 if PMUSERENR.EN==0, otherwise accessible (all others) | |
670 | * For the cases controlled by PMUSERENR we must set .access to PL0_RW | |
671 | * or PL0_RO as appropriate and then check PMUSERENR in the helper fn. | |
672 | */ | |
673 | { .name = "PMCNTENSET", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 1, | |
674 | .access = PL0_RW, .resetvalue = 0, | |
675 | .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcnten), | |
fcd25206 PM |
676 | .writefn = pmcntenset_write, |
677 | .accessfn = pmreg_access, | |
678 | .raw_writefn = raw_write }, | |
200ac0ef PM |
679 | { .name = "PMCNTENCLR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 2, |
680 | .access = PL0_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcnten), | |
fcd25206 PM |
681 | .accessfn = pmreg_access, |
682 | .writefn = pmcntenclr_write, | |
d4e6df63 | 683 | .type = ARM_CP_NO_MIGRATE }, |
200ac0ef PM |
684 | { .name = "PMOVSR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 3, |
685 | .access = PL0_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_pmovsr), | |
fcd25206 PM |
686 | .accessfn = pmreg_access, |
687 | .writefn = pmovsr_write, | |
688 | .raw_writefn = raw_write }, | |
689 | /* Unimplemented so WI. */ | |
200ac0ef | 690 | { .name = "PMSWINC", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 4, |
fcd25206 | 691 | .access = PL0_W, .accessfn = pmreg_access, .type = ARM_CP_NOP }, |
200ac0ef | 692 | /* Since we don't implement any events, writing to PMSELR is UNPREDICTABLE. |
fcd25206 | 693 | * We choose to RAZ/WI. |
200ac0ef PM |
694 | */ |
695 | { .name = "PMSELR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 5, | |
fcd25206 PM |
696 | .access = PL0_RW, .type = ARM_CP_CONST, .resetvalue = 0, |
697 | .accessfn = pmreg_access }, | |
7c2cb42b | 698 | #ifndef CONFIG_USER_ONLY |
200ac0ef | 699 | { .name = "PMCCNTR", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 0, |
7c2cb42b AF |
700 | .access = PL0_RW, .resetvalue = 0, .type = ARM_CP_IO, |
701 | .readfn = pmccntr_read, .writefn = pmccntr_write, | |
fcd25206 | 702 | .accessfn = pmreg_access }, |
7c2cb42b | 703 | #endif |
200ac0ef PM |
704 | { .name = "PMXEVTYPER", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 1, |
705 | .access = PL0_RW, | |
706 | .fieldoffset = offsetof(CPUARMState, cp15.c9_pmxevtyper), | |
fcd25206 PM |
707 | .accessfn = pmreg_access, .writefn = pmxevtyper_write, |
708 | .raw_writefn = raw_write }, | |
709 | /* Unimplemented, RAZ/WI. */ | |
200ac0ef | 710 | { .name = "PMXEVCNTR", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 2, |
fcd25206 PM |
711 | .access = PL0_RW, .type = ARM_CP_CONST, .resetvalue = 0, |
712 | .accessfn = pmreg_access }, | |
200ac0ef PM |
713 | { .name = "PMUSERENR", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 0, |
714 | .access = PL0_R | PL1_RW, | |
715 | .fieldoffset = offsetof(CPUARMState, cp15.c9_pmuserenr), | |
716 | .resetvalue = 0, | |
d4e6df63 | 717 | .writefn = pmuserenr_write, .raw_writefn = raw_write }, |
200ac0ef PM |
718 | { .name = "PMINTENSET", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 1, |
719 | .access = PL1_RW, | |
720 | .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten), | |
721 | .resetvalue = 0, | |
d4e6df63 | 722 | .writefn = pmintenset_write, .raw_writefn = raw_write }, |
200ac0ef | 723 | { .name = "PMINTENCLR", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 2, |
d4e6df63 | 724 | .access = PL1_RW, .type = ARM_CP_NO_MIGRATE, |
200ac0ef | 725 | .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten), |
d4e6df63 | 726 | .resetvalue = 0, .writefn = pmintenclr_write, }, |
a505d7fe PM |
727 | { .name = "VBAR", .state = ARM_CP_STATE_BOTH, |
728 | .opc0 = 3, .crn = 12, .crm = 0, .opc1 = 0, .opc2 = 0, | |
8641136c NR |
729 | .access = PL1_RW, .writefn = vbar_write, |
730 | .fieldoffset = offsetof(CPUARMState, cp15.c12_vbar), | |
731 | .resetvalue = 0 }, | |
2771db27 PM |
732 | { .name = "SCR", .cp = 15, .crn = 1, .crm = 1, .opc1 = 0, .opc2 = 0, |
733 | .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c1_scr), | |
734 | .resetvalue = 0, }, | |
7da845b0 PM |
735 | { .name = "CCSIDR", .state = ARM_CP_STATE_BOTH, |
736 | .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 0, | |
d4e6df63 | 737 | .access = PL1_R, .readfn = ccsidr_read, .type = ARM_CP_NO_MIGRATE }, |
7da845b0 PM |
738 | { .name = "CSSELR", .state = ARM_CP_STATE_BOTH, |
739 | .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 2, .opc2 = 0, | |
776d4e5c PM |
740 | .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c0_cssel), |
741 | .writefn = csselr_write, .resetvalue = 0 }, | |
742 | /* Auxiliary ID register: this actually has an IMPDEF value but for now | |
743 | * just RAZ for all cores: | |
744 | */ | |
745 | { .name = "AIDR", .cp = 15, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 7, | |
746 | .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
b0fe2427 PM |
747 | /* MAIR can just read-as-written because we don't implement caches |
748 | * and so don't need to care about memory attributes. | |
749 | */ | |
750 | { .name = "MAIR_EL1", .state = ARM_CP_STATE_AA64, | |
751 | .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 2, .opc2 = 0, | |
752 | .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.mair_el1), | |
753 | .resetvalue = 0 }, | |
754 | /* For non-long-descriptor page tables these are PRRR and NMRR; | |
755 | * regardless they still act as reads-as-written for QEMU. | |
756 | * The override is necessary because of the overly-broad TLB_LOCKDOWN | |
757 | * definition. | |
758 | */ | |
759 | { .name = "MAIR0", .state = ARM_CP_STATE_AA32, .type = ARM_CP_OVERRIDE, | |
760 | .cp = 15, .opc1 = 0, .crn = 10, .crm = 2, .opc2 = 0, .access = PL1_RW, | |
761 | .fieldoffset = offsetoflow32(CPUARMState, cp15.mair_el1), | |
762 | .resetfn = arm_cp_reset_ignore }, | |
763 | { .name = "MAIR1", .state = ARM_CP_STATE_AA32, .type = ARM_CP_OVERRIDE, | |
764 | .cp = 15, .opc1 = 0, .crn = 10, .crm = 2, .opc2 = 1, .access = PL1_RW, | |
765 | .fieldoffset = offsetofhigh32(CPUARMState, cp15.mair_el1), | |
766 | .resetfn = arm_cp_reset_ignore }, | |
e9aa6c21 PM |
767 | REGINFO_SENTINEL |
768 | }; | |
769 | ||
c4241c7d PM |
770 | static void teecr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
771 | uint64_t value) | |
c326b979 PM |
772 | { |
773 | value &= 1; | |
774 | env->teecr = value; | |
c326b979 PM |
775 | } |
776 | ||
c4241c7d | 777 | static CPAccessResult teehbr_access(CPUARMState *env, const ARMCPRegInfo *ri) |
c326b979 | 778 | { |
c326b979 | 779 | if (arm_current_pl(env) == 0 && (env->teecr & 1)) { |
92611c00 | 780 | return CP_ACCESS_TRAP; |
c326b979 | 781 | } |
92611c00 | 782 | return CP_ACCESS_OK; |
c326b979 PM |
783 | } |
784 | ||
785 | static const ARMCPRegInfo t2ee_cp_reginfo[] = { | |
786 | { .name = "TEECR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 6, .opc2 = 0, | |
787 | .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, teecr), | |
788 | .resetvalue = 0, | |
789 | .writefn = teecr_write }, | |
790 | { .name = "TEEHBR", .cp = 14, .crn = 1, .crm = 0, .opc1 = 6, .opc2 = 0, | |
791 | .access = PL0_RW, .fieldoffset = offsetof(CPUARMState, teehbr), | |
92611c00 | 792 | .accessfn = teehbr_access, .resetvalue = 0 }, |
c326b979 PM |
793 | REGINFO_SENTINEL |
794 | }; | |
795 | ||
4d31c596 | 796 | static const ARMCPRegInfo v6k_cp_reginfo[] = { |
e4fe830b PM |
797 | { .name = "TPIDR_EL0", .state = ARM_CP_STATE_AA64, |
798 | .opc0 = 3, .opc1 = 3, .opc2 = 2, .crn = 13, .crm = 0, | |
799 | .access = PL0_RW, | |
800 | .fieldoffset = offsetof(CPUARMState, cp15.tpidr_el0), .resetvalue = 0 }, | |
4d31c596 PM |
801 | { .name = "TPIDRURW", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 2, |
802 | .access = PL0_RW, | |
e4fe830b PM |
803 | .fieldoffset = offsetoflow32(CPUARMState, cp15.tpidr_el0), |
804 | .resetfn = arm_cp_reset_ignore }, | |
805 | { .name = "TPIDRRO_EL0", .state = ARM_CP_STATE_AA64, | |
806 | .opc0 = 3, .opc1 = 3, .opc2 = 3, .crn = 13, .crm = 0, | |
807 | .access = PL0_R|PL1_W, | |
808 | .fieldoffset = offsetof(CPUARMState, cp15.tpidrro_el0), .resetvalue = 0 }, | |
4d31c596 PM |
809 | { .name = "TPIDRURO", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 3, |
810 | .access = PL0_R|PL1_W, | |
e4fe830b PM |
811 | .fieldoffset = offsetoflow32(CPUARMState, cp15.tpidrro_el0), |
812 | .resetfn = arm_cp_reset_ignore }, | |
813 | { .name = "TPIDR_EL1", .state = ARM_CP_STATE_BOTH, | |
814 | .opc0 = 3, .opc1 = 0, .opc2 = 4, .crn = 13, .crm = 0, | |
4d31c596 | 815 | .access = PL1_RW, |
e4fe830b | 816 | .fieldoffset = offsetof(CPUARMState, cp15.tpidr_el1), .resetvalue = 0 }, |
4d31c596 PM |
817 | REGINFO_SENTINEL |
818 | }; | |
819 | ||
55d284af PM |
820 | #ifndef CONFIG_USER_ONLY |
821 | ||
00108f2d PM |
822 | static CPAccessResult gt_cntfrq_access(CPUARMState *env, const ARMCPRegInfo *ri) |
823 | { | |
824 | /* CNTFRQ: not visible from PL0 if both PL0PCTEN and PL0VCTEN are zero */ | |
825 | if (arm_current_pl(env) == 0 && !extract32(env->cp15.c14_cntkctl, 0, 2)) { | |
826 | return CP_ACCESS_TRAP; | |
827 | } | |
828 | return CP_ACCESS_OK; | |
829 | } | |
830 | ||
831 | static CPAccessResult gt_counter_access(CPUARMState *env, int timeridx) | |
832 | { | |
833 | /* CNT[PV]CT: not visible from PL0 if ELO[PV]CTEN is zero */ | |
834 | if (arm_current_pl(env) == 0 && | |
835 | !extract32(env->cp15.c14_cntkctl, timeridx, 1)) { | |
836 | return CP_ACCESS_TRAP; | |
837 | } | |
838 | return CP_ACCESS_OK; | |
839 | } | |
840 | ||
841 | static CPAccessResult gt_timer_access(CPUARMState *env, int timeridx) | |
842 | { | |
843 | /* CNT[PV]_CVAL, CNT[PV]_CTL, CNT[PV]_TVAL: not visible from PL0 if | |
844 | * EL0[PV]TEN is zero. | |
845 | */ | |
846 | if (arm_current_pl(env) == 0 && | |
847 | !extract32(env->cp15.c14_cntkctl, 9 - timeridx, 1)) { | |
848 | return CP_ACCESS_TRAP; | |
849 | } | |
850 | return CP_ACCESS_OK; | |
851 | } | |
852 | ||
853 | static CPAccessResult gt_pct_access(CPUARMState *env, | |
854 | const ARMCPRegInfo *ri) | |
855 | { | |
856 | return gt_counter_access(env, GTIMER_PHYS); | |
857 | } | |
858 | ||
859 | static CPAccessResult gt_vct_access(CPUARMState *env, | |
860 | const ARMCPRegInfo *ri) | |
861 | { | |
862 | return gt_counter_access(env, GTIMER_VIRT); | |
863 | } | |
864 | ||
865 | static CPAccessResult gt_ptimer_access(CPUARMState *env, const ARMCPRegInfo *ri) | |
866 | { | |
867 | return gt_timer_access(env, GTIMER_PHYS); | |
868 | } | |
869 | ||
870 | static CPAccessResult gt_vtimer_access(CPUARMState *env, const ARMCPRegInfo *ri) | |
871 | { | |
872 | return gt_timer_access(env, GTIMER_VIRT); | |
873 | } | |
874 | ||
55d284af PM |
875 | static uint64_t gt_get_countervalue(CPUARMState *env) |
876 | { | |
bc72ad67 | 877 | return qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) / GTIMER_SCALE; |
55d284af PM |
878 | } |
879 | ||
880 | static void gt_recalc_timer(ARMCPU *cpu, int timeridx) | |
881 | { | |
882 | ARMGenericTimer *gt = &cpu->env.cp15.c14_timer[timeridx]; | |
883 | ||
884 | if (gt->ctl & 1) { | |
885 | /* Timer enabled: calculate and set current ISTATUS, irq, and | |
886 | * reset timer to when ISTATUS next has to change | |
887 | */ | |
888 | uint64_t count = gt_get_countervalue(&cpu->env); | |
889 | /* Note that this must be unsigned 64 bit arithmetic: */ | |
890 | int istatus = count >= gt->cval; | |
891 | uint64_t nexttick; | |
892 | ||
893 | gt->ctl = deposit32(gt->ctl, 2, 1, istatus); | |
894 | qemu_set_irq(cpu->gt_timer_outputs[timeridx], | |
895 | (istatus && !(gt->ctl & 2))); | |
896 | if (istatus) { | |
897 | /* Next transition is when count rolls back over to zero */ | |
898 | nexttick = UINT64_MAX; | |
899 | } else { | |
900 | /* Next transition is when we hit cval */ | |
901 | nexttick = gt->cval; | |
902 | } | |
903 | /* Note that the desired next expiry time might be beyond the | |
904 | * signed-64-bit range of a QEMUTimer -- in this case we just | |
905 | * set the timer for as far in the future as possible. When the | |
906 | * timer expires we will reset the timer for any remaining period. | |
907 | */ | |
908 | if (nexttick > INT64_MAX / GTIMER_SCALE) { | |
909 | nexttick = INT64_MAX / GTIMER_SCALE; | |
910 | } | |
bc72ad67 | 911 | timer_mod(cpu->gt_timer[timeridx], nexttick); |
55d284af PM |
912 | } else { |
913 | /* Timer disabled: ISTATUS and timer output always clear */ | |
914 | gt->ctl &= ~4; | |
915 | qemu_set_irq(cpu->gt_timer_outputs[timeridx], 0); | |
bc72ad67 | 916 | timer_del(cpu->gt_timer[timeridx]); |
55d284af PM |
917 | } |
918 | } | |
919 | ||
55d284af PM |
920 | static void gt_cnt_reset(CPUARMState *env, const ARMCPRegInfo *ri) |
921 | { | |
922 | ARMCPU *cpu = arm_env_get_cpu(env); | |
923 | int timeridx = ri->opc1 & 1; | |
924 | ||
bc72ad67 | 925 | timer_del(cpu->gt_timer[timeridx]); |
55d284af PM |
926 | } |
927 | ||
c4241c7d | 928 | static uint64_t gt_cnt_read(CPUARMState *env, const ARMCPRegInfo *ri) |
55d284af | 929 | { |
c4241c7d | 930 | return gt_get_countervalue(env); |
55d284af PM |
931 | } |
932 | ||
c4241c7d PM |
933 | static void gt_cval_write(CPUARMState *env, const ARMCPRegInfo *ri, |
934 | uint64_t value) | |
55d284af PM |
935 | { |
936 | int timeridx = ri->opc1 & 1; | |
937 | ||
938 | env->cp15.c14_timer[timeridx].cval = value; | |
939 | gt_recalc_timer(arm_env_get_cpu(env), timeridx); | |
55d284af | 940 | } |
c4241c7d PM |
941 | |
942 | static uint64_t gt_tval_read(CPUARMState *env, const ARMCPRegInfo *ri) | |
55d284af PM |
943 | { |
944 | int timeridx = ri->crm & 1; | |
945 | ||
c4241c7d PM |
946 | return (uint32_t)(env->cp15.c14_timer[timeridx].cval - |
947 | gt_get_countervalue(env)); | |
55d284af PM |
948 | } |
949 | ||
c4241c7d PM |
950 | static void gt_tval_write(CPUARMState *env, const ARMCPRegInfo *ri, |
951 | uint64_t value) | |
55d284af PM |
952 | { |
953 | int timeridx = ri->crm & 1; | |
954 | ||
955 | env->cp15.c14_timer[timeridx].cval = gt_get_countervalue(env) + | |
956 | + sextract64(value, 0, 32); | |
957 | gt_recalc_timer(arm_env_get_cpu(env), timeridx); | |
55d284af PM |
958 | } |
959 | ||
c4241c7d PM |
960 | static void gt_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri, |
961 | uint64_t value) | |
55d284af PM |
962 | { |
963 | ARMCPU *cpu = arm_env_get_cpu(env); | |
964 | int timeridx = ri->crm & 1; | |
965 | uint32_t oldval = env->cp15.c14_timer[timeridx].ctl; | |
966 | ||
967 | env->cp15.c14_timer[timeridx].ctl = value & 3; | |
968 | if ((oldval ^ value) & 1) { | |
969 | /* Enable toggled */ | |
970 | gt_recalc_timer(cpu, timeridx); | |
971 | } else if ((oldval & value) & 2) { | |
972 | /* IMASK toggled: don't need to recalculate, | |
973 | * just set the interrupt line based on ISTATUS | |
974 | */ | |
975 | qemu_set_irq(cpu->gt_timer_outputs[timeridx], | |
976 | (oldval & 4) && (value & 2)); | |
977 | } | |
55d284af PM |
978 | } |
979 | ||
980 | void arm_gt_ptimer_cb(void *opaque) | |
981 | { | |
982 | ARMCPU *cpu = opaque; | |
983 | ||
984 | gt_recalc_timer(cpu, GTIMER_PHYS); | |
985 | } | |
986 | ||
987 | void arm_gt_vtimer_cb(void *opaque) | |
988 | { | |
989 | ARMCPU *cpu = opaque; | |
990 | ||
991 | gt_recalc_timer(cpu, GTIMER_VIRT); | |
992 | } | |
993 | ||
994 | static const ARMCPRegInfo generic_timer_cp_reginfo[] = { | |
995 | /* Note that CNTFRQ is purely reads-as-written for the benefit | |
996 | * of software; writing it doesn't actually change the timer frequency. | |
997 | * Our reset value matches the fixed frequency we implement the timer at. | |
998 | */ | |
999 | { .name = "CNTFRQ", .cp = 15, .crn = 14, .crm = 0, .opc1 = 0, .opc2 = 0, | |
a7adc4b7 PM |
1000 | .type = ARM_CP_NO_MIGRATE, |
1001 | .access = PL1_RW | PL0_R, .accessfn = gt_cntfrq_access, | |
1002 | .fieldoffset = offsetoflow32(CPUARMState, cp15.c14_cntfrq), | |
1003 | .resetfn = arm_cp_reset_ignore, | |
1004 | }, | |
1005 | { .name = "CNTFRQ_EL0", .state = ARM_CP_STATE_AA64, | |
1006 | .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 0, | |
1007 | .access = PL1_RW | PL0_R, .accessfn = gt_cntfrq_access, | |
55d284af PM |
1008 | .fieldoffset = offsetof(CPUARMState, cp15.c14_cntfrq), |
1009 | .resetvalue = (1000 * 1000 * 1000) / GTIMER_SCALE, | |
55d284af PM |
1010 | }, |
1011 | /* overall control: mostly access permissions */ | |
a7adc4b7 PM |
1012 | { .name = "CNTKCTL", .state = ARM_CP_STATE_BOTH, |
1013 | .opc0 = 3, .opc1 = 0, .crn = 14, .crm = 1, .opc2 = 0, | |
55d284af PM |
1014 | .access = PL1_RW, |
1015 | .fieldoffset = offsetof(CPUARMState, cp15.c14_cntkctl), | |
1016 | .resetvalue = 0, | |
1017 | }, | |
1018 | /* per-timer control */ | |
1019 | { .name = "CNTP_CTL", .cp = 15, .crn = 14, .crm = 2, .opc1 = 0, .opc2 = 1, | |
a7adc4b7 PM |
1020 | .type = ARM_CP_IO | ARM_CP_NO_MIGRATE, .access = PL1_RW | PL0_R, |
1021 | .accessfn = gt_ptimer_access, | |
1022 | .fieldoffset = offsetoflow32(CPUARMState, | |
1023 | cp15.c14_timer[GTIMER_PHYS].ctl), | |
1024 | .resetfn = arm_cp_reset_ignore, | |
1025 | .writefn = gt_ctl_write, .raw_writefn = raw_write, | |
1026 | }, | |
1027 | { .name = "CNTP_CTL_EL0", .state = ARM_CP_STATE_AA64, | |
1028 | .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 2, .opc2 = 1, | |
55d284af | 1029 | .type = ARM_CP_IO, .access = PL1_RW | PL0_R, |
a7adc4b7 | 1030 | .accessfn = gt_ptimer_access, |
55d284af PM |
1031 | .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].ctl), |
1032 | .resetvalue = 0, | |
00108f2d | 1033 | .writefn = gt_ctl_write, .raw_writefn = raw_write, |
55d284af PM |
1034 | }, |
1035 | { .name = "CNTV_CTL", .cp = 15, .crn = 14, .crm = 3, .opc1 = 0, .opc2 = 1, | |
a7adc4b7 PM |
1036 | .type = ARM_CP_IO | ARM_CP_NO_MIGRATE, .access = PL1_RW | PL0_R, |
1037 | .accessfn = gt_vtimer_access, | |
1038 | .fieldoffset = offsetoflow32(CPUARMState, | |
1039 | cp15.c14_timer[GTIMER_VIRT].ctl), | |
1040 | .resetfn = arm_cp_reset_ignore, | |
1041 | .writefn = gt_ctl_write, .raw_writefn = raw_write, | |
1042 | }, | |
1043 | { .name = "CNTV_CTL_EL0", .state = ARM_CP_STATE_AA64, | |
1044 | .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 3, .opc2 = 1, | |
55d284af | 1045 | .type = ARM_CP_IO, .access = PL1_RW | PL0_R, |
a7adc4b7 | 1046 | .accessfn = gt_vtimer_access, |
55d284af PM |
1047 | .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].ctl), |
1048 | .resetvalue = 0, | |
00108f2d | 1049 | .writefn = gt_ctl_write, .raw_writefn = raw_write, |
55d284af PM |
1050 | }, |
1051 | /* TimerValue views: a 32 bit downcounting view of the underlying state */ | |
1052 | { .name = "CNTP_TVAL", .cp = 15, .crn = 14, .crm = 2, .opc1 = 0, .opc2 = 0, | |
1053 | .type = ARM_CP_NO_MIGRATE | ARM_CP_IO, .access = PL1_RW | PL0_R, | |
00108f2d | 1054 | .accessfn = gt_ptimer_access, |
55d284af PM |
1055 | .readfn = gt_tval_read, .writefn = gt_tval_write, |
1056 | }, | |
a7adc4b7 PM |
1057 | { .name = "CNTP_TVAL_EL0", .state = ARM_CP_STATE_AA64, |
1058 | .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 2, .opc2 = 0, | |
1059 | .type = ARM_CP_NO_MIGRATE | ARM_CP_IO, .access = PL1_RW | PL0_R, | |
1060 | .readfn = gt_tval_read, .writefn = gt_tval_write, | |
1061 | }, | |
55d284af PM |
1062 | { .name = "CNTV_TVAL", .cp = 15, .crn = 14, .crm = 3, .opc1 = 0, .opc2 = 0, |
1063 | .type = ARM_CP_NO_MIGRATE | ARM_CP_IO, .access = PL1_RW | PL0_R, | |
00108f2d | 1064 | .accessfn = gt_vtimer_access, |
55d284af PM |
1065 | .readfn = gt_tval_read, .writefn = gt_tval_write, |
1066 | }, | |
a7adc4b7 PM |
1067 | { .name = "CNTV_TVAL_EL0", .state = ARM_CP_STATE_AA64, |
1068 | .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 3, .opc2 = 0, | |
1069 | .type = ARM_CP_NO_MIGRATE | ARM_CP_IO, .access = PL1_RW | PL0_R, | |
1070 | .readfn = gt_tval_read, .writefn = gt_tval_write, | |
1071 | }, | |
55d284af PM |
1072 | /* The counter itself */ |
1073 | { .name = "CNTPCT", .cp = 15, .crm = 14, .opc1 = 0, | |
1074 | .access = PL0_R, .type = ARM_CP_64BIT | ARM_CP_NO_MIGRATE | ARM_CP_IO, | |
00108f2d | 1075 | .accessfn = gt_pct_access, |
a7adc4b7 PM |
1076 | .readfn = gt_cnt_read, .resetfn = arm_cp_reset_ignore, |
1077 | }, | |
1078 | { .name = "CNTPCT_EL0", .state = ARM_CP_STATE_AA64, | |
1079 | .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 1, | |
1080 | .access = PL0_R, .type = ARM_CP_NO_MIGRATE | ARM_CP_IO, | |
1081 | .accessfn = gt_pct_access, | |
55d284af PM |
1082 | .readfn = gt_cnt_read, .resetfn = gt_cnt_reset, |
1083 | }, | |
1084 | { .name = "CNTVCT", .cp = 15, .crm = 14, .opc1 = 1, | |
1085 | .access = PL0_R, .type = ARM_CP_64BIT | ARM_CP_NO_MIGRATE | ARM_CP_IO, | |
00108f2d | 1086 | .accessfn = gt_vct_access, |
a7adc4b7 PM |
1087 | .readfn = gt_cnt_read, .resetfn = arm_cp_reset_ignore, |
1088 | }, | |
1089 | { .name = "CNTVCT_EL0", .state = ARM_CP_STATE_AA64, | |
1090 | .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 2, | |
1091 | .access = PL0_R, .type = ARM_CP_NO_MIGRATE | ARM_CP_IO, | |
1092 | .accessfn = gt_vct_access, | |
55d284af PM |
1093 | .readfn = gt_cnt_read, .resetfn = gt_cnt_reset, |
1094 | }, | |
1095 | /* Comparison value, indicating when the timer goes off */ | |
1096 | { .name = "CNTP_CVAL", .cp = 15, .crm = 14, .opc1 = 2, | |
1097 | .access = PL1_RW | PL0_R, | |
a7adc4b7 | 1098 | .type = ARM_CP_64BIT | ARM_CP_IO | ARM_CP_NO_MIGRATE, |
55d284af | 1099 | .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].cval), |
a7adc4b7 PM |
1100 | .accessfn = gt_ptimer_access, .resetfn = arm_cp_reset_ignore, |
1101 | .writefn = gt_cval_write, .raw_writefn = raw_write, | |
1102 | }, | |
1103 | { .name = "CNTP_CVAL_EL0", .state = ARM_CP_STATE_AA64, | |
1104 | .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 2, .opc2 = 2, | |
1105 | .access = PL1_RW | PL0_R, | |
1106 | .type = ARM_CP_IO, | |
1107 | .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].cval), | |
1108 | .resetvalue = 0, .accessfn = gt_vtimer_access, | |
00108f2d | 1109 | .writefn = gt_cval_write, .raw_writefn = raw_write, |
55d284af PM |
1110 | }, |
1111 | { .name = "CNTV_CVAL", .cp = 15, .crm = 14, .opc1 = 3, | |
1112 | .access = PL1_RW | PL0_R, | |
a7adc4b7 | 1113 | .type = ARM_CP_64BIT | ARM_CP_IO | ARM_CP_NO_MIGRATE, |
55d284af | 1114 | .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].cval), |
a7adc4b7 PM |
1115 | .accessfn = gt_vtimer_access, .resetfn = arm_cp_reset_ignore, |
1116 | .writefn = gt_cval_write, .raw_writefn = raw_write, | |
1117 | }, | |
1118 | { .name = "CNTV_CVAL_EL0", .state = ARM_CP_STATE_AA64, | |
1119 | .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 3, .opc2 = 2, | |
1120 | .access = PL1_RW | PL0_R, | |
1121 | .type = ARM_CP_IO, | |
1122 | .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].cval), | |
1123 | .resetvalue = 0, .accessfn = gt_vtimer_access, | |
00108f2d | 1124 | .writefn = gt_cval_write, .raw_writefn = raw_write, |
55d284af PM |
1125 | }, |
1126 | REGINFO_SENTINEL | |
1127 | }; | |
1128 | ||
1129 | #else | |
1130 | /* In user-mode none of the generic timer registers are accessible, | |
bc72ad67 | 1131 | * and their implementation depends on QEMU_CLOCK_VIRTUAL and qdev gpio outputs, |
55d284af PM |
1132 | * so instead just don't register any of them. |
1133 | */ | |
6cc7a3ae | 1134 | static const ARMCPRegInfo generic_timer_cp_reginfo[] = { |
6cc7a3ae PM |
1135 | REGINFO_SENTINEL |
1136 | }; | |
1137 | ||
55d284af PM |
1138 | #endif |
1139 | ||
c4241c7d | 1140 | static void par_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) |
4a501606 | 1141 | { |
891a2fe7 PM |
1142 | if (arm_feature(env, ARM_FEATURE_LPAE)) { |
1143 | env->cp15.c7_par = value; | |
1144 | } else if (arm_feature(env, ARM_FEATURE_V7)) { | |
4a501606 PM |
1145 | env->cp15.c7_par = value & 0xfffff6ff; |
1146 | } else { | |
1147 | env->cp15.c7_par = value & 0xfffff1ff; | |
1148 | } | |
4a501606 PM |
1149 | } |
1150 | ||
1151 | #ifndef CONFIG_USER_ONLY | |
1152 | /* get_phys_addr() isn't present for user-mode-only targets */ | |
702a9357 PM |
1153 | |
1154 | /* Return true if extended addresses are enabled, ie this is an | |
1155 | * LPAE implementation and we are using the long-descriptor translation | |
1156 | * table format because the TTBCR EAE bit is set. | |
1157 | */ | |
1158 | static inline bool extended_addresses_enabled(CPUARMState *env) | |
1159 | { | |
1160 | return arm_feature(env, ARM_FEATURE_LPAE) | |
78dbbbe4 | 1161 | && (env->cp15.c2_control & (1U << 31)); |
702a9357 PM |
1162 | } |
1163 | ||
92611c00 PM |
1164 | static CPAccessResult ats_access(CPUARMState *env, const ARMCPRegInfo *ri) |
1165 | { | |
1166 | if (ri->opc2 & 4) { | |
1167 | /* Other states are only available with TrustZone; in | |
1168 | * a non-TZ implementation these registers don't exist | |
1169 | * at all, which is an Uncategorized trap. This underdecoding | |
1170 | * is safe because the reginfo is NO_MIGRATE. | |
1171 | */ | |
1172 | return CP_ACCESS_TRAP_UNCATEGORIZED; | |
1173 | } | |
1174 | return CP_ACCESS_OK; | |
1175 | } | |
1176 | ||
c4241c7d | 1177 | static void ats_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) |
4a501606 | 1178 | { |
a8170e5e | 1179 | hwaddr phys_addr; |
4a501606 PM |
1180 | target_ulong page_size; |
1181 | int prot; | |
1182 | int ret, is_user = ri->opc2 & 2; | |
1183 | int access_type = ri->opc2 & 1; | |
1184 | ||
4a501606 PM |
1185 | ret = get_phys_addr(env, value, access_type, is_user, |
1186 | &phys_addr, &prot, &page_size); | |
702a9357 PM |
1187 | if (extended_addresses_enabled(env)) { |
1188 | /* ret is a DFSR/IFSR value for the long descriptor | |
1189 | * translation table format, but with WnR always clear. | |
1190 | * Convert it to a 64-bit PAR. | |
1191 | */ | |
1192 | uint64_t par64 = (1 << 11); /* LPAE bit always set */ | |
1193 | if (ret == 0) { | |
1194 | par64 |= phys_addr & ~0xfffULL; | |
1195 | /* We don't set the ATTR or SH fields in the PAR. */ | |
4a501606 | 1196 | } else { |
702a9357 PM |
1197 | par64 |= 1; /* F */ |
1198 | par64 |= (ret & 0x3f) << 1; /* FS */ | |
1199 | /* Note that S2WLK and FSTAGE are always zero, because we don't | |
1200 | * implement virtualization and therefore there can't be a stage 2 | |
1201 | * fault. | |
1202 | */ | |
4a501606 | 1203 | } |
702a9357 PM |
1204 | env->cp15.c7_par = par64; |
1205 | env->cp15.c7_par_hi = par64 >> 32; | |
4a501606 | 1206 | } else { |
702a9357 PM |
1207 | /* ret is a DFSR/IFSR value for the short descriptor |
1208 | * translation table format (with WnR always clear). | |
1209 | * Convert it to a 32-bit PAR. | |
1210 | */ | |
1211 | if (ret == 0) { | |
1212 | /* We do not set any attribute bits in the PAR */ | |
1213 | if (page_size == (1 << 24) | |
1214 | && arm_feature(env, ARM_FEATURE_V7)) { | |
1215 | env->cp15.c7_par = (phys_addr & 0xff000000) | 1 << 1; | |
1216 | } else { | |
1217 | env->cp15.c7_par = phys_addr & 0xfffff000; | |
1218 | } | |
1219 | } else { | |
775fda92 PM |
1220 | env->cp15.c7_par = ((ret & (1 << 10)) >> 5) | |
1221 | ((ret & (1 << 12)) >> 6) | | |
702a9357 PM |
1222 | ((ret & 0xf) << 1) | 1; |
1223 | } | |
1224 | env->cp15.c7_par_hi = 0; | |
4a501606 | 1225 | } |
4a501606 PM |
1226 | } |
1227 | #endif | |
1228 | ||
1229 | static const ARMCPRegInfo vapa_cp_reginfo[] = { | |
1230 | { .name = "PAR", .cp = 15, .crn = 7, .crm = 4, .opc1 = 0, .opc2 = 0, | |
1231 | .access = PL1_RW, .resetvalue = 0, | |
1232 | .fieldoffset = offsetof(CPUARMState, cp15.c7_par), | |
1233 | .writefn = par_write }, | |
1234 | #ifndef CONFIG_USER_ONLY | |
1235 | { .name = "ATS", .cp = 15, .crn = 7, .crm = 8, .opc1 = 0, .opc2 = CP_ANY, | |
92611c00 PM |
1236 | .access = PL1_W, .accessfn = ats_access, |
1237 | .writefn = ats_write, .type = ARM_CP_NO_MIGRATE }, | |
4a501606 PM |
1238 | #endif |
1239 | REGINFO_SENTINEL | |
1240 | }; | |
1241 | ||
18032bec PM |
1242 | /* Return basic MPU access permission bits. */ |
1243 | static uint32_t simple_mpu_ap_bits(uint32_t val) | |
1244 | { | |
1245 | uint32_t ret; | |
1246 | uint32_t mask; | |
1247 | int i; | |
1248 | ret = 0; | |
1249 | mask = 3; | |
1250 | for (i = 0; i < 16; i += 2) { | |
1251 | ret |= (val >> i) & mask; | |
1252 | mask <<= 2; | |
1253 | } | |
1254 | return ret; | |
1255 | } | |
1256 | ||
1257 | /* Pad basic MPU access permission bits to extended format. */ | |
1258 | static uint32_t extended_mpu_ap_bits(uint32_t val) | |
1259 | { | |
1260 | uint32_t ret; | |
1261 | uint32_t mask; | |
1262 | int i; | |
1263 | ret = 0; | |
1264 | mask = 3; | |
1265 | for (i = 0; i < 16; i += 2) { | |
1266 | ret |= (val & mask) << i; | |
1267 | mask <<= 2; | |
1268 | } | |
1269 | return ret; | |
1270 | } | |
1271 | ||
c4241c7d PM |
1272 | static void pmsav5_data_ap_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1273 | uint64_t value) | |
18032bec PM |
1274 | { |
1275 | env->cp15.c5_data = extended_mpu_ap_bits(value); | |
18032bec PM |
1276 | } |
1277 | ||
c4241c7d | 1278 | static uint64_t pmsav5_data_ap_read(CPUARMState *env, const ARMCPRegInfo *ri) |
18032bec | 1279 | { |
c4241c7d | 1280 | return simple_mpu_ap_bits(env->cp15.c5_data); |
18032bec PM |
1281 | } |
1282 | ||
c4241c7d PM |
1283 | static void pmsav5_insn_ap_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1284 | uint64_t value) | |
18032bec PM |
1285 | { |
1286 | env->cp15.c5_insn = extended_mpu_ap_bits(value); | |
18032bec PM |
1287 | } |
1288 | ||
c4241c7d | 1289 | static uint64_t pmsav5_insn_ap_read(CPUARMState *env, const ARMCPRegInfo *ri) |
18032bec | 1290 | { |
c4241c7d | 1291 | return simple_mpu_ap_bits(env->cp15.c5_insn); |
18032bec PM |
1292 | } |
1293 | ||
1294 | static const ARMCPRegInfo pmsav5_cp_reginfo[] = { | |
1295 | { .name = "DATA_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 0, | |
d4e6df63 | 1296 | .access = PL1_RW, .type = ARM_CP_NO_MIGRATE, |
18032bec PM |
1297 | .fieldoffset = offsetof(CPUARMState, cp15.c5_data), .resetvalue = 0, |
1298 | .readfn = pmsav5_data_ap_read, .writefn = pmsav5_data_ap_write, }, | |
1299 | { .name = "INSN_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 1, | |
d4e6df63 | 1300 | .access = PL1_RW, .type = ARM_CP_NO_MIGRATE, |
18032bec PM |
1301 | .fieldoffset = offsetof(CPUARMState, cp15.c5_insn), .resetvalue = 0, |
1302 | .readfn = pmsav5_insn_ap_read, .writefn = pmsav5_insn_ap_write, }, | |
1303 | { .name = "DATA_EXT_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 2, | |
1304 | .access = PL1_RW, | |
1305 | .fieldoffset = offsetof(CPUARMState, cp15.c5_data), .resetvalue = 0, }, | |
1306 | { .name = "INSN_EXT_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 3, | |
1307 | .access = PL1_RW, | |
1308 | .fieldoffset = offsetof(CPUARMState, cp15.c5_insn), .resetvalue = 0, }, | |
ecce5c3c PM |
1309 | { .name = "DCACHE_CFG", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 0, |
1310 | .access = PL1_RW, | |
1311 | .fieldoffset = offsetof(CPUARMState, cp15.c2_data), .resetvalue = 0, }, | |
1312 | { .name = "ICACHE_CFG", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 1, | |
1313 | .access = PL1_RW, | |
1314 | .fieldoffset = offsetof(CPUARMState, cp15.c2_insn), .resetvalue = 0, }, | |
06d76f31 | 1315 | /* Protection region base and size registers */ |
e508a92b PM |
1316 | { .name = "946_PRBS0", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, |
1317 | .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0, | |
1318 | .fieldoffset = offsetof(CPUARMState, cp15.c6_region[0]) }, | |
1319 | { .name = "946_PRBS1", .cp = 15, .crn = 6, .crm = 1, .opc1 = 0, | |
1320 | .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0, | |
1321 | .fieldoffset = offsetof(CPUARMState, cp15.c6_region[1]) }, | |
1322 | { .name = "946_PRBS2", .cp = 15, .crn = 6, .crm = 2, .opc1 = 0, | |
1323 | .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0, | |
1324 | .fieldoffset = offsetof(CPUARMState, cp15.c6_region[2]) }, | |
1325 | { .name = "946_PRBS3", .cp = 15, .crn = 6, .crm = 3, .opc1 = 0, | |
1326 | .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0, | |
1327 | .fieldoffset = offsetof(CPUARMState, cp15.c6_region[3]) }, | |
1328 | { .name = "946_PRBS4", .cp = 15, .crn = 6, .crm = 4, .opc1 = 0, | |
1329 | .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0, | |
1330 | .fieldoffset = offsetof(CPUARMState, cp15.c6_region[4]) }, | |
1331 | { .name = "946_PRBS5", .cp = 15, .crn = 6, .crm = 5, .opc1 = 0, | |
1332 | .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0, | |
1333 | .fieldoffset = offsetof(CPUARMState, cp15.c6_region[5]) }, | |
1334 | { .name = "946_PRBS6", .cp = 15, .crn = 6, .crm = 6, .opc1 = 0, | |
1335 | .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0, | |
1336 | .fieldoffset = offsetof(CPUARMState, cp15.c6_region[6]) }, | |
1337 | { .name = "946_PRBS7", .cp = 15, .crn = 6, .crm = 7, .opc1 = 0, | |
1338 | .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0, | |
1339 | .fieldoffset = offsetof(CPUARMState, cp15.c6_region[7]) }, | |
18032bec PM |
1340 | REGINFO_SENTINEL |
1341 | }; | |
1342 | ||
c4241c7d PM |
1343 | static void vmsa_ttbcr_raw_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1344 | uint64_t value) | |
ecce5c3c | 1345 | { |
2ebcebe2 PM |
1346 | int maskshift = extract32(value, 0, 3); |
1347 | ||
74f1c6dd | 1348 | if (arm_feature(env, ARM_FEATURE_LPAE) && (value & (1 << 31))) { |
e42c4db3 | 1349 | value &= ~((7 << 19) | (3 << 14) | (0xf << 3)); |
e42c4db3 PM |
1350 | } else { |
1351 | value &= 7; | |
1352 | } | |
1353 | /* Note that we always calculate c2_mask and c2_base_mask, but | |
1354 | * they are only used for short-descriptor tables (ie if EAE is 0); | |
1355 | * for long-descriptor tables the TTBCR fields are used differently | |
1356 | * and the c2_mask and c2_base_mask values are meaningless. | |
1357 | */ | |
ecce5c3c | 1358 | env->cp15.c2_control = value; |
2ebcebe2 PM |
1359 | env->cp15.c2_mask = ~(((uint32_t)0xffffffffu) >> maskshift); |
1360 | env->cp15.c2_base_mask = ~((uint32_t)0x3fffu >> maskshift); | |
ecce5c3c PM |
1361 | } |
1362 | ||
c4241c7d PM |
1363 | static void vmsa_ttbcr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1364 | uint64_t value) | |
d4e6df63 | 1365 | { |
00c8cb0a AF |
1366 | ARMCPU *cpu = arm_env_get_cpu(env); |
1367 | ||
d4e6df63 PM |
1368 | if (arm_feature(env, ARM_FEATURE_LPAE)) { |
1369 | /* With LPAE the TTBCR could result in a change of ASID | |
1370 | * via the TTBCR.A1 bit, so do a TLB flush. | |
1371 | */ | |
00c8cb0a | 1372 | tlb_flush(CPU(cpu), 1); |
d4e6df63 | 1373 | } |
c4241c7d | 1374 | vmsa_ttbcr_raw_write(env, ri, value); |
d4e6df63 PM |
1375 | } |
1376 | ||
ecce5c3c PM |
1377 | static void vmsa_ttbcr_reset(CPUARMState *env, const ARMCPRegInfo *ri) |
1378 | { | |
1379 | env->cp15.c2_base_mask = 0xffffc000u; | |
1380 | env->cp15.c2_control = 0; | |
1381 | env->cp15.c2_mask = 0; | |
1382 | } | |
1383 | ||
cb2e37df PM |
1384 | static void vmsa_tcr_el1_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1385 | uint64_t value) | |
1386 | { | |
00c8cb0a AF |
1387 | ARMCPU *cpu = arm_env_get_cpu(env); |
1388 | ||
cb2e37df | 1389 | /* For AArch64 the A1 bit could result in a change of ASID, so TLB flush. */ |
00c8cb0a | 1390 | tlb_flush(CPU(cpu), 1); |
cb2e37df PM |
1391 | env->cp15.c2_control = value; |
1392 | } | |
1393 | ||
327ed10f PM |
1394 | static void vmsa_ttbr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1395 | uint64_t value) | |
1396 | { | |
1397 | /* 64 bit accesses to the TTBRs can change the ASID and so we | |
1398 | * must flush the TLB. | |
1399 | */ | |
1400 | if (cpreg_field_is_64bit(ri)) { | |
00c8cb0a AF |
1401 | ARMCPU *cpu = arm_env_get_cpu(env); |
1402 | ||
1403 | tlb_flush(CPU(cpu), 1); | |
327ed10f PM |
1404 | } |
1405 | raw_write(env, ri, value); | |
1406 | } | |
1407 | ||
18032bec PM |
1408 | static const ARMCPRegInfo vmsa_cp_reginfo[] = { |
1409 | { .name = "DFSR", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 0, | |
1410 | .access = PL1_RW, | |
1411 | .fieldoffset = offsetof(CPUARMState, cp15.c5_data), .resetvalue = 0, }, | |
1412 | { .name = "IFSR", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 1, | |
1413 | .access = PL1_RW, | |
1414 | .fieldoffset = offsetof(CPUARMState, cp15.c5_insn), .resetvalue = 0, }, | |
327ed10f PM |
1415 | { .name = "TTBR0_EL1", .state = ARM_CP_STATE_BOTH, |
1416 | .opc0 = 3, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 0, | |
1417 | .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.ttbr0_el1), | |
1418 | .writefn = vmsa_ttbr_write, .resetvalue = 0 }, | |
1419 | { .name = "TTBR1_EL1", .state = ARM_CP_STATE_BOTH, | |
1420 | .opc0 = 3, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 1, | |
1421 | .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.ttbr1_el1), | |
1422 | .writefn = vmsa_ttbr_write, .resetvalue = 0 }, | |
cb2e37df PM |
1423 | { .name = "TCR_EL1", .state = ARM_CP_STATE_AA64, |
1424 | .opc0 = 3, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 2, | |
1425 | .access = PL1_RW, .writefn = vmsa_tcr_el1_write, | |
1426 | .resetfn = vmsa_ttbcr_reset, .raw_writefn = raw_write, | |
ecce5c3c | 1427 | .fieldoffset = offsetof(CPUARMState, cp15.c2_control) }, |
cb2e37df PM |
1428 | { .name = "TTBCR", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 2, |
1429 | .access = PL1_RW, .type = ARM_CP_NO_MIGRATE, .writefn = vmsa_ttbcr_write, | |
1430 | .resetfn = arm_cp_reset_ignore, .raw_writefn = vmsa_ttbcr_raw_write, | |
1431 | .fieldoffset = offsetoflow32(CPUARMState, cp15.c2_control) }, | |
06d76f31 PM |
1432 | { .name = "DFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 0, |
1433 | .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c6_data), | |
1434 | .resetvalue = 0, }, | |
18032bec PM |
1435 | REGINFO_SENTINEL |
1436 | }; | |
1437 | ||
c4241c7d PM |
1438 | static void omap_ticonfig_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1439 | uint64_t value) | |
1047b9d7 PM |
1440 | { |
1441 | env->cp15.c15_ticonfig = value & 0xe7; | |
1442 | /* The OS_TYPE bit in this register changes the reported CPUID! */ | |
1443 | env->cp15.c0_cpuid = (value & (1 << 5)) ? | |
1444 | ARM_CPUID_TI915T : ARM_CPUID_TI925T; | |
1047b9d7 PM |
1445 | } |
1446 | ||
c4241c7d PM |
1447 | static void omap_threadid_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1448 | uint64_t value) | |
1047b9d7 PM |
1449 | { |
1450 | env->cp15.c15_threadid = value & 0xffff; | |
1047b9d7 PM |
1451 | } |
1452 | ||
c4241c7d PM |
1453 | static void omap_wfi_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1454 | uint64_t value) | |
1047b9d7 PM |
1455 | { |
1456 | /* Wait-for-interrupt (deprecated) */ | |
c3affe56 | 1457 | cpu_interrupt(CPU(arm_env_get_cpu(env)), CPU_INTERRUPT_HALT); |
1047b9d7 PM |
1458 | } |
1459 | ||
c4241c7d PM |
1460 | static void omap_cachemaint_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1461 | uint64_t value) | |
c4804214 PM |
1462 | { |
1463 | /* On OMAP there are registers indicating the max/min index of dcache lines | |
1464 | * containing a dirty line; cache flush operations have to reset these. | |
1465 | */ | |
1466 | env->cp15.c15_i_max = 0x000; | |
1467 | env->cp15.c15_i_min = 0xff0; | |
c4804214 PM |
1468 | } |
1469 | ||
18032bec PM |
1470 | static const ARMCPRegInfo omap_cp_reginfo[] = { |
1471 | { .name = "DFSR", .cp = 15, .crn = 5, .crm = CP_ANY, | |
1472 | .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_OVERRIDE, | |
1473 | .fieldoffset = offsetof(CPUARMState, cp15.c5_data), .resetvalue = 0, }, | |
1047b9d7 PM |
1474 | { .name = "", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0, |
1475 | .access = PL1_RW, .type = ARM_CP_NOP }, | |
1476 | { .name = "TICONFIG", .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0, | |
1477 | .access = PL1_RW, | |
1478 | .fieldoffset = offsetof(CPUARMState, cp15.c15_ticonfig), .resetvalue = 0, | |
1479 | .writefn = omap_ticonfig_write }, | |
1480 | { .name = "IMAX", .cp = 15, .crn = 15, .crm = 2, .opc1 = 0, .opc2 = 0, | |
1481 | .access = PL1_RW, | |
1482 | .fieldoffset = offsetof(CPUARMState, cp15.c15_i_max), .resetvalue = 0, }, | |
1483 | { .name = "IMIN", .cp = 15, .crn = 15, .crm = 3, .opc1 = 0, .opc2 = 0, | |
1484 | .access = PL1_RW, .resetvalue = 0xff0, | |
1485 | .fieldoffset = offsetof(CPUARMState, cp15.c15_i_min) }, | |
1486 | { .name = "THREADID", .cp = 15, .crn = 15, .crm = 4, .opc1 = 0, .opc2 = 0, | |
1487 | .access = PL1_RW, | |
1488 | .fieldoffset = offsetof(CPUARMState, cp15.c15_threadid), .resetvalue = 0, | |
1489 | .writefn = omap_threadid_write }, | |
1490 | { .name = "TI925T_STATUS", .cp = 15, .crn = 15, | |
1491 | .crm = 8, .opc1 = 0, .opc2 = 0, .access = PL1_RW, | |
d4e6df63 | 1492 | .type = ARM_CP_NO_MIGRATE, |
1047b9d7 PM |
1493 | .readfn = arm_cp_read_zero, .writefn = omap_wfi_write, }, |
1494 | /* TODO: Peripheral port remap register: | |
1495 | * On OMAP2 mcr p15, 0, rn, c15, c2, 4 sets up the interrupt controller | |
1496 | * base address at $rn & ~0xfff and map size of 0x200 << ($rn & 0xfff), | |
1497 | * when MMU is off. | |
1498 | */ | |
c4804214 | 1499 | { .name = "OMAP_CACHEMAINT", .cp = 15, .crn = 7, .crm = CP_ANY, |
d4e6df63 PM |
1500 | .opc1 = 0, .opc2 = CP_ANY, .access = PL1_W, |
1501 | .type = ARM_CP_OVERRIDE | ARM_CP_NO_MIGRATE, | |
c4804214 | 1502 | .writefn = omap_cachemaint_write }, |
34f90529 PM |
1503 | { .name = "C9", .cp = 15, .crn = 9, |
1504 | .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, | |
1505 | .type = ARM_CP_CONST | ARM_CP_OVERRIDE, .resetvalue = 0 }, | |
1047b9d7 PM |
1506 | REGINFO_SENTINEL |
1507 | }; | |
1508 | ||
c4241c7d PM |
1509 | static void xscale_cpar_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1510 | uint64_t value) | |
1047b9d7 PM |
1511 | { |
1512 | value &= 0x3fff; | |
1513 | if (env->cp15.c15_cpar != value) { | |
1514 | /* Changes cp0 to cp13 behavior, so needs a TB flush. */ | |
1515 | tb_flush(env); | |
1516 | env->cp15.c15_cpar = value; | |
1517 | } | |
1047b9d7 PM |
1518 | } |
1519 | ||
1520 | static const ARMCPRegInfo xscale_cp_reginfo[] = { | |
1521 | { .name = "XSCALE_CPAR", | |
1522 | .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0, .access = PL1_RW, | |
1523 | .fieldoffset = offsetof(CPUARMState, cp15.c15_cpar), .resetvalue = 0, | |
1524 | .writefn = xscale_cpar_write, }, | |
2771db27 PM |
1525 | { .name = "XSCALE_AUXCR", |
1526 | .cp = 15, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 1, .access = PL1_RW, | |
1527 | .fieldoffset = offsetof(CPUARMState, cp15.c1_xscaleauxcr), | |
1528 | .resetvalue = 0, }, | |
1047b9d7 PM |
1529 | REGINFO_SENTINEL |
1530 | }; | |
1531 | ||
1532 | static const ARMCPRegInfo dummy_c15_cp_reginfo[] = { | |
1533 | /* RAZ/WI the whole crn=15 space, when we don't have a more specific | |
1534 | * implementation of this implementation-defined space. | |
1535 | * Ideally this should eventually disappear in favour of actually | |
1536 | * implementing the correct behaviour for all cores. | |
1537 | */ | |
1538 | { .name = "C15_IMPDEF", .cp = 15, .crn = 15, | |
1539 | .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY, | |
3671cd87 PC |
1540 | .access = PL1_RW, |
1541 | .type = ARM_CP_CONST | ARM_CP_NO_MIGRATE | ARM_CP_OVERRIDE, | |
d4e6df63 | 1542 | .resetvalue = 0 }, |
18032bec PM |
1543 | REGINFO_SENTINEL |
1544 | }; | |
1545 | ||
c4804214 PM |
1546 | static const ARMCPRegInfo cache_dirty_status_cp_reginfo[] = { |
1547 | /* Cache status: RAZ because we have no cache so it's always clean */ | |
1548 | { .name = "CDSR", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 6, | |
d4e6df63 PM |
1549 | .access = PL1_R, .type = ARM_CP_CONST | ARM_CP_NO_MIGRATE, |
1550 | .resetvalue = 0 }, | |
c4804214 PM |
1551 | REGINFO_SENTINEL |
1552 | }; | |
1553 | ||
1554 | static const ARMCPRegInfo cache_block_ops_cp_reginfo[] = { | |
1555 | /* We never have a a block transfer operation in progress */ | |
1556 | { .name = "BXSR", .cp = 15, .crn = 7, .crm = 12, .opc1 = 0, .opc2 = 4, | |
d4e6df63 PM |
1557 | .access = PL0_R, .type = ARM_CP_CONST | ARM_CP_NO_MIGRATE, |
1558 | .resetvalue = 0 }, | |
30b05bba PM |
1559 | /* The cache ops themselves: these all NOP for QEMU */ |
1560 | { .name = "IICR", .cp = 15, .crm = 5, .opc1 = 0, | |
1561 | .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT }, | |
1562 | { .name = "IDCR", .cp = 15, .crm = 6, .opc1 = 0, | |
1563 | .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT }, | |
1564 | { .name = "CDCR", .cp = 15, .crm = 12, .opc1 = 0, | |
1565 | .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT }, | |
1566 | { .name = "PIR", .cp = 15, .crm = 12, .opc1 = 1, | |
1567 | .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT }, | |
1568 | { .name = "PDR", .cp = 15, .crm = 12, .opc1 = 2, | |
1569 | .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT }, | |
1570 | { .name = "CIDCR", .cp = 15, .crm = 14, .opc1 = 0, | |
1571 | .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT }, | |
c4804214 PM |
1572 | REGINFO_SENTINEL |
1573 | }; | |
1574 | ||
1575 | static const ARMCPRegInfo cache_test_clean_cp_reginfo[] = { | |
1576 | /* The cache test-and-clean instructions always return (1 << 30) | |
1577 | * to indicate that there are no dirty cache lines. | |
1578 | */ | |
1579 | { .name = "TC_DCACHE", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 3, | |
d4e6df63 PM |
1580 | .access = PL0_R, .type = ARM_CP_CONST | ARM_CP_NO_MIGRATE, |
1581 | .resetvalue = (1 << 30) }, | |
c4804214 | 1582 | { .name = "TCI_DCACHE", .cp = 15, .crn = 7, .crm = 14, .opc1 = 0, .opc2 = 3, |
d4e6df63 PM |
1583 | .access = PL0_R, .type = ARM_CP_CONST | ARM_CP_NO_MIGRATE, |
1584 | .resetvalue = (1 << 30) }, | |
c4804214 PM |
1585 | REGINFO_SENTINEL |
1586 | }; | |
1587 | ||
34f90529 PM |
1588 | static const ARMCPRegInfo strongarm_cp_reginfo[] = { |
1589 | /* Ignore ReadBuffer accesses */ | |
1590 | { .name = "C9_READBUFFER", .cp = 15, .crn = 9, | |
1591 | .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY, | |
d4e6df63 PM |
1592 | .access = PL1_RW, .resetvalue = 0, |
1593 | .type = ARM_CP_CONST | ARM_CP_OVERRIDE | ARM_CP_NO_MIGRATE }, | |
34f90529 PM |
1594 | REGINFO_SENTINEL |
1595 | }; | |
1596 | ||
c4241c7d | 1597 | static uint64_t mpidr_read(CPUARMState *env, const ARMCPRegInfo *ri) |
81bdde9d | 1598 | { |
55e5c285 AF |
1599 | CPUState *cs = CPU(arm_env_get_cpu(env)); |
1600 | uint32_t mpidr = cs->cpu_index; | |
4b7fff2f PM |
1601 | /* We don't support setting cluster ID ([8..11]) (known as Aff1 |
1602 | * in later ARM ARM versions), or any of the higher affinity level fields, | |
81bdde9d PM |
1603 | * so these bits always RAZ. |
1604 | */ | |
1605 | if (arm_feature(env, ARM_FEATURE_V7MP)) { | |
78dbbbe4 | 1606 | mpidr |= (1U << 31); |
81bdde9d PM |
1607 | /* Cores which are uniprocessor (non-coherent) |
1608 | * but still implement the MP extensions set | |
1609 | * bit 30. (For instance, A9UP.) However we do | |
1610 | * not currently model any of those cores. | |
1611 | */ | |
1612 | } | |
c4241c7d | 1613 | return mpidr; |
81bdde9d PM |
1614 | } |
1615 | ||
1616 | static const ARMCPRegInfo mpidr_cp_reginfo[] = { | |
4b7fff2f PM |
1617 | { .name = "MPIDR", .state = ARM_CP_STATE_BOTH, |
1618 | .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 5, | |
d4e6df63 | 1619 | .access = PL1_R, .readfn = mpidr_read, .type = ARM_CP_NO_MIGRATE }, |
81bdde9d PM |
1620 | REGINFO_SENTINEL |
1621 | }; | |
1622 | ||
c4241c7d | 1623 | static uint64_t par64_read(CPUARMState *env, const ARMCPRegInfo *ri) |
891a2fe7 | 1624 | { |
c4241c7d | 1625 | return ((uint64_t)env->cp15.c7_par_hi << 32) | env->cp15.c7_par; |
891a2fe7 PM |
1626 | } |
1627 | ||
c4241c7d PM |
1628 | static void par64_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1629 | uint64_t value) | |
891a2fe7 PM |
1630 | { |
1631 | env->cp15.c7_par_hi = value >> 32; | |
1632 | env->cp15.c7_par = value; | |
891a2fe7 PM |
1633 | } |
1634 | ||
1635 | static void par64_reset(CPUARMState *env, const ARMCPRegInfo *ri) | |
1636 | { | |
1637 | env->cp15.c7_par_hi = 0; | |
1638 | env->cp15.c7_par = 0; | |
1639 | } | |
1640 | ||
7ac681cf | 1641 | static const ARMCPRegInfo lpae_cp_reginfo[] = { |
b90372ad | 1642 | /* NOP AMAIR0/1: the override is because these clash with the rather |
7ac681cf PM |
1643 | * broadly specified TLB_LOCKDOWN entry in the generic cp_reginfo. |
1644 | */ | |
b0fe2427 PM |
1645 | { .name = "AMAIR0", .state = ARM_CP_STATE_BOTH, |
1646 | .opc0 = 3, .crn = 10, .crm = 3, .opc1 = 0, .opc2 = 0, | |
7ac681cf PM |
1647 | .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_OVERRIDE, |
1648 | .resetvalue = 0 }, | |
b0fe2427 | 1649 | /* AMAIR1 is mapped to AMAIR_EL1[63:32] */ |
7ac681cf PM |
1650 | { .name = "AMAIR1", .cp = 15, .crn = 10, .crm = 3, .opc1 = 0, .opc2 = 1, |
1651 | .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_OVERRIDE, | |
1652 | .resetvalue = 0 }, | |
f9fc619a PM |
1653 | /* 64 bit access versions of the (dummy) debug registers */ |
1654 | { .name = "DBGDRAR", .cp = 14, .crm = 1, .opc1 = 0, | |
1655 | .access = PL0_R, .type = ARM_CP_CONST|ARM_CP_64BIT, .resetvalue = 0 }, | |
1656 | { .name = "DBGDSAR", .cp = 14, .crm = 2, .opc1 = 0, | |
1657 | .access = PL0_R, .type = ARM_CP_CONST|ARM_CP_64BIT, .resetvalue = 0 }, | |
891a2fe7 PM |
1658 | { .name = "PAR", .cp = 15, .crm = 7, .opc1 = 0, |
1659 | .access = PL1_RW, .type = ARM_CP_64BIT, | |
1660 | .readfn = par64_read, .writefn = par64_write, .resetfn = par64_reset }, | |
1661 | { .name = "TTBR0", .cp = 15, .crm = 2, .opc1 = 0, | |
327ed10f PM |
1662 | .access = PL1_RW, .type = ARM_CP_64BIT | ARM_CP_NO_MIGRATE, |
1663 | .fieldoffset = offsetof(CPUARMState, cp15.ttbr0_el1), | |
1664 | .writefn = vmsa_ttbr_write, .resetfn = arm_cp_reset_ignore }, | |
891a2fe7 | 1665 | { .name = "TTBR1", .cp = 15, .crm = 2, .opc1 = 1, |
327ed10f PM |
1666 | .access = PL1_RW, .type = ARM_CP_64BIT | ARM_CP_NO_MIGRATE, |
1667 | .fieldoffset = offsetof(CPUARMState, cp15.ttbr1_el1), | |
1668 | .writefn = vmsa_ttbr_write, .resetfn = arm_cp_reset_ignore }, | |
7ac681cf PM |
1669 | REGINFO_SENTINEL |
1670 | }; | |
1671 | ||
c4241c7d | 1672 | static uint64_t aa64_fpcr_read(CPUARMState *env, const ARMCPRegInfo *ri) |
b0d2b7d0 | 1673 | { |
c4241c7d | 1674 | return vfp_get_fpcr(env); |
b0d2b7d0 PM |
1675 | } |
1676 | ||
c4241c7d PM |
1677 | static void aa64_fpcr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1678 | uint64_t value) | |
b0d2b7d0 PM |
1679 | { |
1680 | vfp_set_fpcr(env, value); | |
b0d2b7d0 PM |
1681 | } |
1682 | ||
c4241c7d | 1683 | static uint64_t aa64_fpsr_read(CPUARMState *env, const ARMCPRegInfo *ri) |
b0d2b7d0 | 1684 | { |
c4241c7d | 1685 | return vfp_get_fpsr(env); |
b0d2b7d0 PM |
1686 | } |
1687 | ||
c4241c7d PM |
1688 | static void aa64_fpsr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1689 | uint64_t value) | |
b0d2b7d0 PM |
1690 | { |
1691 | vfp_set_fpsr(env, value); | |
b0d2b7d0 PM |
1692 | } |
1693 | ||
8af35c37 PM |
1694 | static CPAccessResult aa64_cacheop_access(CPUARMState *env, |
1695 | const ARMCPRegInfo *ri) | |
1696 | { | |
1697 | /* Cache invalidate/clean: NOP, but EL0 must UNDEF unless | |
1698 | * SCTLR_EL1.UCI is set. | |
1699 | */ | |
1700 | if (arm_current_pl(env) == 0 && !(env->cp15.c1_sys & SCTLR_UCI)) { | |
1701 | return CP_ACCESS_TRAP; | |
1702 | } | |
1703 | return CP_ACCESS_OK; | |
1704 | } | |
1705 | ||
168aa23b PM |
1706 | static void tlbi_aa64_va_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1707 | uint64_t value) | |
1708 | { | |
1709 | /* Invalidate by VA (AArch64 version) */ | |
31b030d4 | 1710 | ARMCPU *cpu = arm_env_get_cpu(env); |
168aa23b | 1711 | uint64_t pageaddr = value << 12; |
31b030d4 | 1712 | tlb_flush_page(CPU(cpu), pageaddr); |
168aa23b PM |
1713 | } |
1714 | ||
1715 | static void tlbi_aa64_vaa_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
1716 | uint64_t value) | |
1717 | { | |
1718 | /* Invalidate by VA, all ASIDs (AArch64 version) */ | |
31b030d4 | 1719 | ARMCPU *cpu = arm_env_get_cpu(env); |
168aa23b | 1720 | uint64_t pageaddr = value << 12; |
31b030d4 | 1721 | tlb_flush_page(CPU(cpu), pageaddr); |
168aa23b PM |
1722 | } |
1723 | ||
1724 | static void tlbi_aa64_asid_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
1725 | uint64_t value) | |
1726 | { | |
1727 | /* Invalidate by ASID (AArch64 version) */ | |
00c8cb0a | 1728 | ARMCPU *cpu = arm_env_get_cpu(env); |
168aa23b | 1729 | int asid = extract64(value, 48, 16); |
00c8cb0a | 1730 | tlb_flush(CPU(cpu), asid == 0); |
168aa23b PM |
1731 | } |
1732 | ||
b0d2b7d0 PM |
1733 | static const ARMCPRegInfo v8_cp_reginfo[] = { |
1734 | /* Minimal set of EL0-visible registers. This will need to be expanded | |
1735 | * significantly for system emulation of AArch64 CPUs. | |
1736 | */ | |
1737 | { .name = "NZCV", .state = ARM_CP_STATE_AA64, | |
1738 | .opc0 = 3, .opc1 = 3, .opc2 = 0, .crn = 4, .crm = 2, | |
1739 | .access = PL0_RW, .type = ARM_CP_NZCV }, | |
1740 | { .name = "FPCR", .state = ARM_CP_STATE_AA64, | |
1741 | .opc0 = 3, .opc1 = 3, .opc2 = 0, .crn = 4, .crm = 4, | |
1742 | .access = PL0_RW, .readfn = aa64_fpcr_read, .writefn = aa64_fpcr_write }, | |
1743 | { .name = "FPSR", .state = ARM_CP_STATE_AA64, | |
1744 | .opc0 = 3, .opc1 = 3, .opc2 = 1, .crn = 4, .crm = 4, | |
1745 | .access = PL0_RW, .readfn = aa64_fpsr_read, .writefn = aa64_fpsr_write }, | |
b0d2b7d0 PM |
1746 | /* Prohibit use of DC ZVA. OPTME: implement DC ZVA and allow its use. |
1747 | * For system mode the DZP bit here will need to be computed, not constant. | |
1748 | */ | |
1749 | { .name = "DCZID_EL0", .state = ARM_CP_STATE_AA64, | |
1750 | .opc0 = 3, .opc1 = 3, .opc2 = 7, .crn = 0, .crm = 0, | |
1751 | .access = PL0_R, .type = ARM_CP_CONST, | |
1752 | .resetvalue = 0x10 }, | |
0eef9d98 PM |
1753 | { .name = "CURRENTEL", .state = ARM_CP_STATE_AA64, |
1754 | .opc0 = 3, .opc1 = 0, .opc2 = 2, .crn = 4, .crm = 2, | |
1755 | .access = PL1_R, .type = ARM_CP_CURRENTEL }, | |
8af35c37 PM |
1756 | /* Cache ops: all NOPs since we don't emulate caches */ |
1757 | { .name = "IC_IALLUIS", .state = ARM_CP_STATE_AA64, | |
1758 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 1, .opc2 = 0, | |
1759 | .access = PL1_W, .type = ARM_CP_NOP }, | |
1760 | { .name = "IC_IALLU", .state = ARM_CP_STATE_AA64, | |
1761 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 0, | |
1762 | .access = PL1_W, .type = ARM_CP_NOP }, | |
1763 | { .name = "IC_IVAU", .state = ARM_CP_STATE_AA64, | |
1764 | .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 5, .opc2 = 1, | |
1765 | .access = PL0_W, .type = ARM_CP_NOP, | |
1766 | .accessfn = aa64_cacheop_access }, | |
1767 | { .name = "DC_IVAC", .state = ARM_CP_STATE_AA64, | |
1768 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 1, | |
1769 | .access = PL1_W, .type = ARM_CP_NOP }, | |
1770 | { .name = "DC_ISW", .state = ARM_CP_STATE_AA64, | |
1771 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 2, | |
1772 | .access = PL1_W, .type = ARM_CP_NOP }, | |
1773 | { .name = "DC_CVAC", .state = ARM_CP_STATE_AA64, | |
1774 | .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 10, .opc2 = 1, | |
1775 | .access = PL0_W, .type = ARM_CP_NOP, | |
1776 | .accessfn = aa64_cacheop_access }, | |
1777 | { .name = "DC_CSW", .state = ARM_CP_STATE_AA64, | |
1778 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 2, | |
1779 | .access = PL1_W, .type = ARM_CP_NOP }, | |
1780 | { .name = "DC_CVAU", .state = ARM_CP_STATE_AA64, | |
1781 | .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 11, .opc2 = 1, | |
1782 | .access = PL0_W, .type = ARM_CP_NOP, | |
1783 | .accessfn = aa64_cacheop_access }, | |
1784 | { .name = "DC_CIVAC", .state = ARM_CP_STATE_AA64, | |
1785 | .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 14, .opc2 = 1, | |
1786 | .access = PL0_W, .type = ARM_CP_NOP, | |
1787 | .accessfn = aa64_cacheop_access }, | |
1788 | { .name = "DC_CISW", .state = ARM_CP_STATE_AA64, | |
1789 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 2, | |
1790 | .access = PL1_W, .type = ARM_CP_NOP }, | |
168aa23b PM |
1791 | /* TLBI operations */ |
1792 | { .name = "TLBI_VMALLE1IS", .state = ARM_CP_STATE_AA64, | |
1793 | .opc0 = 1, .opc2 = 0, .crn = 8, .crm = 3, .opc2 = 0, | |
1794 | .access = PL1_W, .type = ARM_CP_NO_MIGRATE, | |
1795 | .writefn = tlbiall_write }, | |
1796 | { .name = "TLBI_VAE1IS", .state = ARM_CP_STATE_AA64, | |
1797 | .opc0 = 1, .opc2 = 0, .crn = 8, .crm = 3, .opc2 = 1, | |
1798 | .access = PL1_W, .type = ARM_CP_NO_MIGRATE, | |
1799 | .writefn = tlbi_aa64_va_write }, | |
1800 | { .name = "TLBI_ASIDE1IS", .state = ARM_CP_STATE_AA64, | |
1801 | .opc0 = 1, .opc2 = 0, .crn = 8, .crm = 3, .opc2 = 2, | |
1802 | .access = PL1_W, .type = ARM_CP_NO_MIGRATE, | |
1803 | .writefn = tlbi_aa64_asid_write }, | |
1804 | { .name = "TLBI_VAAE1IS", .state = ARM_CP_STATE_AA64, | |
1805 | .opc0 = 1, .opc2 = 0, .crn = 8, .crm = 3, .opc2 = 3, | |
1806 | .access = PL1_W, .type = ARM_CP_NO_MIGRATE, | |
1807 | .writefn = tlbi_aa64_vaa_write }, | |
1808 | { .name = "TLBI_VALE1IS", .state = ARM_CP_STATE_AA64, | |
1809 | .opc0 = 1, .opc2 = 0, .crn = 8, .crm = 3, .opc2 = 5, | |
1810 | .access = PL1_W, .type = ARM_CP_NO_MIGRATE, | |
1811 | .writefn = tlbi_aa64_va_write }, | |
1812 | { .name = "TLBI_VAALE1IS", .state = ARM_CP_STATE_AA64, | |
1813 | .opc0 = 1, .opc2 = 0, .crn = 8, .crm = 3, .opc2 = 7, | |
1814 | .access = PL1_W, .type = ARM_CP_NO_MIGRATE, | |
1815 | .writefn = tlbi_aa64_vaa_write }, | |
1816 | { .name = "TLBI_VMALLE1", .state = ARM_CP_STATE_AA64, | |
1817 | .opc0 = 1, .opc2 = 0, .crn = 8, .crm = 7, .opc2 = 0, | |
1818 | .access = PL1_W, .type = ARM_CP_NO_MIGRATE, | |
1819 | .writefn = tlbiall_write }, | |
1820 | { .name = "TLBI_VAE1", .state = ARM_CP_STATE_AA64, | |
1821 | .opc0 = 1, .opc2 = 0, .crn = 8, .crm = 7, .opc2 = 1, | |
1822 | .access = PL1_W, .type = ARM_CP_NO_MIGRATE, | |
1823 | .writefn = tlbi_aa64_va_write }, | |
1824 | { .name = "TLBI_ASIDE1", .state = ARM_CP_STATE_AA64, | |
1825 | .opc0 = 1, .opc2 = 0, .crn = 8, .crm = 7, .opc2 = 2, | |
1826 | .access = PL1_W, .type = ARM_CP_NO_MIGRATE, | |
1827 | .writefn = tlbi_aa64_asid_write }, | |
1828 | { .name = "TLBI_VAAE1", .state = ARM_CP_STATE_AA64, | |
1829 | .opc0 = 1, .opc2 = 0, .crn = 8, .crm = 7, .opc2 = 3, | |
1830 | .access = PL1_W, .type = ARM_CP_NO_MIGRATE, | |
1831 | .writefn = tlbi_aa64_vaa_write }, | |
1832 | { .name = "TLBI_VALE1", .state = ARM_CP_STATE_AA64, | |
1833 | .opc0 = 1, .opc2 = 0, .crn = 8, .crm = 7, .opc2 = 5, | |
1834 | .access = PL1_W, .type = ARM_CP_NO_MIGRATE, | |
1835 | .writefn = tlbi_aa64_va_write }, | |
1836 | { .name = "TLBI_VAALE1", .state = ARM_CP_STATE_AA64, | |
1837 | .opc0 = 1, .opc2 = 0, .crn = 8, .crm = 7, .opc2 = 7, | |
1838 | .access = PL1_W, .type = ARM_CP_NO_MIGRATE, | |
1839 | .writefn = tlbi_aa64_vaa_write }, | |
91e24069 PM |
1840 | /* Dummy implementation of monitor debug system control register: |
1841 | * we don't support debug. | |
1842 | */ | |
1843 | { .name = "MDSCR_EL1", .state = ARM_CP_STATE_AA64, | |
1844 | .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 2, | |
1845 | .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
cd5c11b8 PM |
1846 | /* We define a dummy WI OSLAR_EL1, because Linux writes to it. */ |
1847 | { .name = "OSLAR_EL1", .state = ARM_CP_STATE_AA64, | |
1848 | .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 4, | |
1849 | .access = PL1_W, .type = ARM_CP_NOP }, | |
b0d2b7d0 PM |
1850 | REGINFO_SENTINEL |
1851 | }; | |
1852 | ||
c4241c7d PM |
1853 | static void sctlr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1854 | uint64_t value) | |
2771db27 | 1855 | { |
00c8cb0a AF |
1856 | ARMCPU *cpu = arm_env_get_cpu(env); |
1857 | ||
2771db27 PM |
1858 | env->cp15.c1_sys = value; |
1859 | /* ??? Lots of these bits are not implemented. */ | |
1860 | /* This may enable/disable the MMU, so do a TLB flush. */ | |
00c8cb0a | 1861 | tlb_flush(CPU(cpu), 1); |
2771db27 PM |
1862 | } |
1863 | ||
7da845b0 PM |
1864 | static CPAccessResult ctr_el0_access(CPUARMState *env, const ARMCPRegInfo *ri) |
1865 | { | |
1866 | /* Only accessible in EL0 if SCTLR.UCT is set (and only in AArch64, | |
1867 | * but the AArch32 CTR has its own reginfo struct) | |
1868 | */ | |
1869 | if (arm_current_pl(env) == 0 && !(env->cp15.c1_sys & SCTLR_UCT)) { | |
1870 | return CP_ACCESS_TRAP; | |
1871 | } | |
1872 | return CP_ACCESS_OK; | |
1873 | } | |
1874 | ||
0b45451e PM |
1875 | static void define_aarch64_debug_regs(ARMCPU *cpu) |
1876 | { | |
1877 | /* Define breakpoint and watchpoint registers. These do nothing | |
1878 | * but read as written, for now. | |
1879 | */ | |
1880 | int i; | |
1881 | ||
1882 | for (i = 0; i < 16; i++) { | |
1883 | ARMCPRegInfo dbgregs[] = { | |
1884 | { .name = "DBGBVR", .state = ARM_CP_STATE_AA64, | |
1885 | .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 4, | |
1886 | .access = PL1_RW, | |
1887 | .fieldoffset = offsetof(CPUARMState, cp15.dbgbvr[i]) }, | |
1888 | { .name = "DBGBCR", .state = ARM_CP_STATE_AA64, | |
1889 | .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 5, | |
1890 | .access = PL1_RW, | |
1891 | .fieldoffset = offsetof(CPUARMState, cp15.dbgbcr[i]) }, | |
1892 | { .name = "DBGWVR", .state = ARM_CP_STATE_AA64, | |
1893 | .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 6, | |
1894 | .access = PL1_RW, | |
1895 | .fieldoffset = offsetof(CPUARMState, cp15.dbgwvr[i]) }, | |
1896 | { .name = "DBGWCR", .state = ARM_CP_STATE_AA64, | |
1897 | .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 7, | |
1898 | .access = PL1_RW, | |
1899 | .fieldoffset = offsetof(CPUARMState, cp15.dbgwcr[i]) }, | |
1900 | REGINFO_SENTINEL | |
1901 | }; | |
1902 | define_arm_cp_regs(cpu, dbgregs); | |
1903 | } | |
1904 | } | |
1905 | ||
2ceb98c0 PM |
1906 | void register_cp_regs_for_features(ARMCPU *cpu) |
1907 | { | |
1908 | /* Register all the coprocessor registers based on feature bits */ | |
1909 | CPUARMState *env = &cpu->env; | |
1910 | if (arm_feature(env, ARM_FEATURE_M)) { | |
1911 | /* M profile has no coprocessor registers */ | |
1912 | return; | |
1913 | } | |
1914 | ||
e9aa6c21 | 1915 | define_arm_cp_regs(cpu, cp_reginfo); |
7d57f408 | 1916 | if (arm_feature(env, ARM_FEATURE_V6)) { |
8515a092 PM |
1917 | /* The ID registers all have impdef reset values */ |
1918 | ARMCPRegInfo v6_idregs[] = { | |
1919 | { .name = "ID_PFR0", .cp = 15, .crn = 0, .crm = 1, | |
1920 | .opc1 = 0, .opc2 = 0, .access = PL1_R, .type = ARM_CP_CONST, | |
1921 | .resetvalue = cpu->id_pfr0 }, | |
1922 | { .name = "ID_PFR1", .cp = 15, .crn = 0, .crm = 1, | |
1923 | .opc1 = 0, .opc2 = 1, .access = PL1_R, .type = ARM_CP_CONST, | |
1924 | .resetvalue = cpu->id_pfr1 }, | |
1925 | { .name = "ID_DFR0", .cp = 15, .crn = 0, .crm = 1, | |
1926 | .opc1 = 0, .opc2 = 2, .access = PL1_R, .type = ARM_CP_CONST, | |
1927 | .resetvalue = cpu->id_dfr0 }, | |
1928 | { .name = "ID_AFR0", .cp = 15, .crn = 0, .crm = 1, | |
1929 | .opc1 = 0, .opc2 = 3, .access = PL1_R, .type = ARM_CP_CONST, | |
1930 | .resetvalue = cpu->id_afr0 }, | |
1931 | { .name = "ID_MMFR0", .cp = 15, .crn = 0, .crm = 1, | |
1932 | .opc1 = 0, .opc2 = 4, .access = PL1_R, .type = ARM_CP_CONST, | |
1933 | .resetvalue = cpu->id_mmfr0 }, | |
1934 | { .name = "ID_MMFR1", .cp = 15, .crn = 0, .crm = 1, | |
1935 | .opc1 = 0, .opc2 = 5, .access = PL1_R, .type = ARM_CP_CONST, | |
1936 | .resetvalue = cpu->id_mmfr1 }, | |
1937 | { .name = "ID_MMFR2", .cp = 15, .crn = 0, .crm = 1, | |
1938 | .opc1 = 0, .opc2 = 6, .access = PL1_R, .type = ARM_CP_CONST, | |
1939 | .resetvalue = cpu->id_mmfr2 }, | |
1940 | { .name = "ID_MMFR3", .cp = 15, .crn = 0, .crm = 1, | |
1941 | .opc1 = 0, .opc2 = 7, .access = PL1_R, .type = ARM_CP_CONST, | |
1942 | .resetvalue = cpu->id_mmfr3 }, | |
1943 | { .name = "ID_ISAR0", .cp = 15, .crn = 0, .crm = 2, | |
1944 | .opc1 = 0, .opc2 = 0, .access = PL1_R, .type = ARM_CP_CONST, | |
1945 | .resetvalue = cpu->id_isar0 }, | |
1946 | { .name = "ID_ISAR1", .cp = 15, .crn = 0, .crm = 2, | |
1947 | .opc1 = 0, .opc2 = 1, .access = PL1_R, .type = ARM_CP_CONST, | |
1948 | .resetvalue = cpu->id_isar1 }, | |
1949 | { .name = "ID_ISAR2", .cp = 15, .crn = 0, .crm = 2, | |
1950 | .opc1 = 0, .opc2 = 2, .access = PL1_R, .type = ARM_CP_CONST, | |
1951 | .resetvalue = cpu->id_isar2 }, | |
1952 | { .name = "ID_ISAR3", .cp = 15, .crn = 0, .crm = 2, | |
1953 | .opc1 = 0, .opc2 = 3, .access = PL1_R, .type = ARM_CP_CONST, | |
1954 | .resetvalue = cpu->id_isar3 }, | |
1955 | { .name = "ID_ISAR4", .cp = 15, .crn = 0, .crm = 2, | |
1956 | .opc1 = 0, .opc2 = 4, .access = PL1_R, .type = ARM_CP_CONST, | |
1957 | .resetvalue = cpu->id_isar4 }, | |
1958 | { .name = "ID_ISAR5", .cp = 15, .crn = 0, .crm = 2, | |
1959 | .opc1 = 0, .opc2 = 5, .access = PL1_R, .type = ARM_CP_CONST, | |
1960 | .resetvalue = cpu->id_isar5 }, | |
1961 | /* 6..7 are as yet unallocated and must RAZ */ | |
1962 | { .name = "ID_ISAR6", .cp = 15, .crn = 0, .crm = 2, | |
1963 | .opc1 = 0, .opc2 = 6, .access = PL1_R, .type = ARM_CP_CONST, | |
1964 | .resetvalue = 0 }, | |
1965 | { .name = "ID_ISAR7", .cp = 15, .crn = 0, .crm = 2, | |
1966 | .opc1 = 0, .opc2 = 7, .access = PL1_R, .type = ARM_CP_CONST, | |
1967 | .resetvalue = 0 }, | |
1968 | REGINFO_SENTINEL | |
1969 | }; | |
1970 | define_arm_cp_regs(cpu, v6_idregs); | |
7d57f408 PM |
1971 | define_arm_cp_regs(cpu, v6_cp_reginfo); |
1972 | } else { | |
1973 | define_arm_cp_regs(cpu, not_v6_cp_reginfo); | |
1974 | } | |
4d31c596 PM |
1975 | if (arm_feature(env, ARM_FEATURE_V6K)) { |
1976 | define_arm_cp_regs(cpu, v6k_cp_reginfo); | |
1977 | } | |
e9aa6c21 | 1978 | if (arm_feature(env, ARM_FEATURE_V7)) { |
200ac0ef | 1979 | /* v7 performance monitor control register: same implementor |
7c2cb42b AF |
1980 | * field as main ID register, and we implement only the cycle |
1981 | * count register. | |
200ac0ef | 1982 | */ |
7c2cb42b | 1983 | #ifndef CONFIG_USER_ONLY |
200ac0ef PM |
1984 | ARMCPRegInfo pmcr = { |
1985 | .name = "PMCR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 0, | |
1986 | .access = PL0_RW, .resetvalue = cpu->midr & 0xff000000, | |
d6d60581 | 1987 | .type = ARM_CP_IO, |
200ac0ef | 1988 | .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcr), |
fcd25206 PM |
1989 | .accessfn = pmreg_access, .writefn = pmcr_write, |
1990 | .raw_writefn = raw_write, | |
200ac0ef | 1991 | }; |
7c2cb42b AF |
1992 | define_one_arm_cp_reg(cpu, &pmcr); |
1993 | #endif | |
776d4e5c | 1994 | ARMCPRegInfo clidr = { |
7da845b0 PM |
1995 | .name = "CLIDR", .state = ARM_CP_STATE_BOTH, |
1996 | .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 1, | |
776d4e5c PM |
1997 | .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = cpu->clidr |
1998 | }; | |
776d4e5c | 1999 | define_one_arm_cp_reg(cpu, &clidr); |
e9aa6c21 | 2000 | define_arm_cp_regs(cpu, v7_cp_reginfo); |
7d57f408 PM |
2001 | } else { |
2002 | define_arm_cp_regs(cpu, not_v7_cp_reginfo); | |
e9aa6c21 | 2003 | } |
b0d2b7d0 | 2004 | if (arm_feature(env, ARM_FEATURE_V8)) { |
e60cef86 PM |
2005 | /* AArch64 ID registers, which all have impdef reset values */ |
2006 | ARMCPRegInfo v8_idregs[] = { | |
2007 | { .name = "ID_AA64PFR0_EL1", .state = ARM_CP_STATE_AA64, | |
2008 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 0, | |
2009 | .access = PL1_R, .type = ARM_CP_CONST, | |
2010 | .resetvalue = cpu->id_aa64pfr0 }, | |
2011 | { .name = "ID_AA64PFR1_EL1", .state = ARM_CP_STATE_AA64, | |
2012 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 1, | |
2013 | .access = PL1_R, .type = ARM_CP_CONST, | |
2014 | .resetvalue = cpu->id_aa64pfr1}, | |
2015 | { .name = "ID_AA64DFR0_EL1", .state = ARM_CP_STATE_AA64, | |
2016 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 0, | |
2017 | .access = PL1_R, .type = ARM_CP_CONST, | |
2018 | .resetvalue = cpu->id_aa64dfr0 }, | |
2019 | { .name = "ID_AA64DFR1_EL1", .state = ARM_CP_STATE_AA64, | |
2020 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 1, | |
2021 | .access = PL1_R, .type = ARM_CP_CONST, | |
2022 | .resetvalue = cpu->id_aa64dfr1 }, | |
2023 | { .name = "ID_AA64AFR0_EL1", .state = ARM_CP_STATE_AA64, | |
2024 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 4, | |
2025 | .access = PL1_R, .type = ARM_CP_CONST, | |
2026 | .resetvalue = cpu->id_aa64afr0 }, | |
2027 | { .name = "ID_AA64AFR1_EL1", .state = ARM_CP_STATE_AA64, | |
2028 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 5, | |
2029 | .access = PL1_R, .type = ARM_CP_CONST, | |
2030 | .resetvalue = cpu->id_aa64afr1 }, | |
2031 | { .name = "ID_AA64ISAR0_EL1", .state = ARM_CP_STATE_AA64, | |
2032 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 0, | |
2033 | .access = PL1_R, .type = ARM_CP_CONST, | |
2034 | .resetvalue = cpu->id_aa64isar0 }, | |
2035 | { .name = "ID_AA64ISAR1_EL1", .state = ARM_CP_STATE_AA64, | |
2036 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 1, | |
2037 | .access = PL1_R, .type = ARM_CP_CONST, | |
2038 | .resetvalue = cpu->id_aa64isar1 }, | |
2039 | { .name = "ID_AA64MMFR0_EL1", .state = ARM_CP_STATE_AA64, | |
2040 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 0, | |
2041 | .access = PL1_R, .type = ARM_CP_CONST, | |
2042 | .resetvalue = cpu->id_aa64mmfr0 }, | |
2043 | { .name = "ID_AA64MMFR1_EL1", .state = ARM_CP_STATE_AA64, | |
2044 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 1, | |
2045 | .access = PL1_R, .type = ARM_CP_CONST, | |
2046 | .resetvalue = cpu->id_aa64mmfr1 }, | |
2047 | REGINFO_SENTINEL | |
2048 | }; | |
2049 | define_arm_cp_regs(cpu, v8_idregs); | |
b0d2b7d0 | 2050 | define_arm_cp_regs(cpu, v8_cp_reginfo); |
0b45451e | 2051 | define_aarch64_debug_regs(cpu); |
b0d2b7d0 | 2052 | } |
18032bec PM |
2053 | if (arm_feature(env, ARM_FEATURE_MPU)) { |
2054 | /* These are the MPU registers prior to PMSAv6. Any new | |
2055 | * PMSA core later than the ARM946 will require that we | |
2056 | * implement the PMSAv6 or PMSAv7 registers, which are | |
2057 | * completely different. | |
2058 | */ | |
2059 | assert(!arm_feature(env, ARM_FEATURE_V6)); | |
2060 | define_arm_cp_regs(cpu, pmsav5_cp_reginfo); | |
2061 | } else { | |
2062 | define_arm_cp_regs(cpu, vmsa_cp_reginfo); | |
2063 | } | |
c326b979 PM |
2064 | if (arm_feature(env, ARM_FEATURE_THUMB2EE)) { |
2065 | define_arm_cp_regs(cpu, t2ee_cp_reginfo); | |
2066 | } | |
6cc7a3ae PM |
2067 | if (arm_feature(env, ARM_FEATURE_GENERIC_TIMER)) { |
2068 | define_arm_cp_regs(cpu, generic_timer_cp_reginfo); | |
2069 | } | |
4a501606 PM |
2070 | if (arm_feature(env, ARM_FEATURE_VAPA)) { |
2071 | define_arm_cp_regs(cpu, vapa_cp_reginfo); | |
2072 | } | |
c4804214 PM |
2073 | if (arm_feature(env, ARM_FEATURE_CACHE_TEST_CLEAN)) { |
2074 | define_arm_cp_regs(cpu, cache_test_clean_cp_reginfo); | |
2075 | } | |
2076 | if (arm_feature(env, ARM_FEATURE_CACHE_DIRTY_REG)) { | |
2077 | define_arm_cp_regs(cpu, cache_dirty_status_cp_reginfo); | |
2078 | } | |
2079 | if (arm_feature(env, ARM_FEATURE_CACHE_BLOCK_OPS)) { | |
2080 | define_arm_cp_regs(cpu, cache_block_ops_cp_reginfo); | |
2081 | } | |
18032bec PM |
2082 | if (arm_feature(env, ARM_FEATURE_OMAPCP)) { |
2083 | define_arm_cp_regs(cpu, omap_cp_reginfo); | |
2084 | } | |
34f90529 PM |
2085 | if (arm_feature(env, ARM_FEATURE_STRONGARM)) { |
2086 | define_arm_cp_regs(cpu, strongarm_cp_reginfo); | |
2087 | } | |
1047b9d7 PM |
2088 | if (arm_feature(env, ARM_FEATURE_XSCALE)) { |
2089 | define_arm_cp_regs(cpu, xscale_cp_reginfo); | |
2090 | } | |
2091 | if (arm_feature(env, ARM_FEATURE_DUMMY_C15_REGS)) { | |
2092 | define_arm_cp_regs(cpu, dummy_c15_cp_reginfo); | |
2093 | } | |
7ac681cf PM |
2094 | if (arm_feature(env, ARM_FEATURE_LPAE)) { |
2095 | define_arm_cp_regs(cpu, lpae_cp_reginfo); | |
2096 | } | |
7884849c PM |
2097 | /* Slightly awkwardly, the OMAP and StrongARM cores need all of |
2098 | * cp15 crn=0 to be writes-ignored, whereas for other cores they should | |
2099 | * be read-only (ie write causes UNDEF exception). | |
2100 | */ | |
2101 | { | |
2102 | ARMCPRegInfo id_cp_reginfo[] = { | |
2103 | /* Note that the MIDR isn't a simple constant register because | |
2104 | * of the TI925 behaviour where writes to another register can | |
2105 | * cause the MIDR value to change. | |
97ce8d61 PC |
2106 | * |
2107 | * Unimplemented registers in the c15 0 0 0 space default to | |
2108 | * MIDR. Define MIDR first as this entire space, then CTR, TCMTR | |
2109 | * and friends override accordingly. | |
7884849c PM |
2110 | */ |
2111 | { .name = "MIDR", | |
97ce8d61 | 2112 | .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = CP_ANY, |
7884849c | 2113 | .access = PL1_R, .resetvalue = cpu->midr, |
d4e6df63 | 2114 | .writefn = arm_cp_write_ignore, .raw_writefn = raw_write, |
97ce8d61 PC |
2115 | .fieldoffset = offsetof(CPUARMState, cp15.c0_cpuid), |
2116 | .type = ARM_CP_OVERRIDE }, | |
cd4da631 PM |
2117 | { .name = "MIDR_EL1", .state = ARM_CP_STATE_AA64, |
2118 | .opc0 = 3, .opc1 = 0, .opc2 = 0, .crn = 0, .crm = 0, | |
2119 | .access = PL1_R, .resetvalue = cpu->midr, .type = ARM_CP_CONST }, | |
7884849c PM |
2120 | { .name = "CTR", |
2121 | .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 1, | |
2122 | .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = cpu->ctr }, | |
7da845b0 PM |
2123 | { .name = "CTR_EL0", .state = ARM_CP_STATE_AA64, |
2124 | .opc0 = 3, .opc1 = 3, .opc2 = 1, .crn = 0, .crm = 0, | |
2125 | .access = PL0_R, .accessfn = ctr_el0_access, | |
2126 | .type = ARM_CP_CONST, .resetvalue = cpu->ctr }, | |
7884849c PM |
2127 | { .name = "TCMTR", |
2128 | .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 2, | |
2129 | .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
2130 | { .name = "TLBTR", | |
2131 | .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 3, | |
2132 | .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
2133 | /* crn = 0 op1 = 0 crm = 3..7 : currently unassigned; we RAZ. */ | |
2134 | { .name = "DUMMY", | |
2135 | .cp = 15, .crn = 0, .crm = 3, .opc1 = 0, .opc2 = CP_ANY, | |
2136 | .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
2137 | { .name = "DUMMY", | |
2138 | .cp = 15, .crn = 0, .crm = 4, .opc1 = 0, .opc2 = CP_ANY, | |
2139 | .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
2140 | { .name = "DUMMY", | |
2141 | .cp = 15, .crn = 0, .crm = 5, .opc1 = 0, .opc2 = CP_ANY, | |
2142 | .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
2143 | { .name = "DUMMY", | |
2144 | .cp = 15, .crn = 0, .crm = 6, .opc1 = 0, .opc2 = CP_ANY, | |
2145 | .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
2146 | { .name = "DUMMY", | |
2147 | .cp = 15, .crn = 0, .crm = 7, .opc1 = 0, .opc2 = CP_ANY, | |
2148 | .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
2149 | REGINFO_SENTINEL | |
2150 | }; | |
2151 | ARMCPRegInfo crn0_wi_reginfo = { | |
2152 | .name = "CRN0_WI", .cp = 15, .crn = 0, .crm = CP_ANY, | |
2153 | .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_W, | |
2154 | .type = ARM_CP_NOP | ARM_CP_OVERRIDE | |
2155 | }; | |
2156 | if (arm_feature(env, ARM_FEATURE_OMAPCP) || | |
2157 | arm_feature(env, ARM_FEATURE_STRONGARM)) { | |
2158 | ARMCPRegInfo *r; | |
2159 | /* Register the blanket "writes ignored" value first to cover the | |
a703eda1 PC |
2160 | * whole space. Then update the specific ID registers to allow write |
2161 | * access, so that they ignore writes rather than causing them to | |
2162 | * UNDEF. | |
7884849c PM |
2163 | */ |
2164 | define_one_arm_cp_reg(cpu, &crn0_wi_reginfo); | |
2165 | for (r = id_cp_reginfo; r->type != ARM_CP_SENTINEL; r++) { | |
2166 | r->access = PL1_RW; | |
7884849c | 2167 | } |
7884849c | 2168 | } |
a703eda1 | 2169 | define_arm_cp_regs(cpu, id_cp_reginfo); |
7884849c PM |
2170 | } |
2171 | ||
97ce8d61 PC |
2172 | if (arm_feature(env, ARM_FEATURE_MPIDR)) { |
2173 | define_arm_cp_regs(cpu, mpidr_cp_reginfo); | |
2174 | } | |
2175 | ||
2771db27 PM |
2176 | if (arm_feature(env, ARM_FEATURE_AUXCR)) { |
2177 | ARMCPRegInfo auxcr = { | |
2178 | .name = "AUXCR", .cp = 15, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 1, | |
2179 | .access = PL1_RW, .type = ARM_CP_CONST, | |
2180 | .resetvalue = cpu->reset_auxcr | |
2181 | }; | |
2182 | define_one_arm_cp_reg(cpu, &auxcr); | |
2183 | } | |
2184 | ||
d8ba780b PC |
2185 | if (arm_feature(env, ARM_FEATURE_CBAR)) { |
2186 | ARMCPRegInfo cbar = { | |
2187 | .name = "CBAR", .cp = 15, .crn = 15, .crm = 0, .opc1 = 4, .opc2 = 0, | |
2188 | .access = PL1_R|PL3_W, .resetvalue = cpu->reset_cbar, | |
2189 | .fieldoffset = offsetof(CPUARMState, cp15.c15_config_base_address) | |
2190 | }; | |
2191 | define_one_arm_cp_reg(cpu, &cbar); | |
2192 | } | |
2193 | ||
2771db27 PM |
2194 | /* Generic registers whose values depend on the implementation */ |
2195 | { | |
2196 | ARMCPRegInfo sctlr = { | |
5ebafdf3 PM |
2197 | .name = "SCTLR", .state = ARM_CP_STATE_BOTH, |
2198 | .opc0 = 3, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 0, | |
2771db27 | 2199 | .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c1_sys), |
d4e6df63 PM |
2200 | .writefn = sctlr_write, .resetvalue = cpu->reset_sctlr, |
2201 | .raw_writefn = raw_write, | |
2771db27 PM |
2202 | }; |
2203 | if (arm_feature(env, ARM_FEATURE_XSCALE)) { | |
2204 | /* Normally we would always end the TB on an SCTLR write, but Linux | |
2205 | * arch/arm/mach-pxa/sleep.S expects two instructions following | |
2206 | * an MMU enable to execute from cache. Imitate this behaviour. | |
2207 | */ | |
2208 | sctlr.type |= ARM_CP_SUPPRESS_TB_END; | |
2209 | } | |
2210 | define_one_arm_cp_reg(cpu, &sctlr); | |
2211 | } | |
2ceb98c0 PM |
2212 | } |
2213 | ||
778c3a06 | 2214 | ARMCPU *cpu_arm_init(const char *cpu_model) |
40f137e1 | 2215 | { |
9262685b | 2216 | return ARM_CPU(cpu_generic_init(TYPE_ARM_CPU, cpu_model)); |
14969266 AF |
2217 | } |
2218 | ||
2219 | void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu) | |
2220 | { | |
22169d41 | 2221 | CPUState *cs = CPU(cpu); |
14969266 AF |
2222 | CPUARMState *env = &cpu->env; |
2223 | ||
6a669427 PM |
2224 | if (arm_feature(env, ARM_FEATURE_AARCH64)) { |
2225 | gdb_register_coprocessor(cs, aarch64_fpu_gdb_get_reg, | |
2226 | aarch64_fpu_gdb_set_reg, | |
2227 | 34, "aarch64-fpu.xml", 0); | |
2228 | } else if (arm_feature(env, ARM_FEATURE_NEON)) { | |
22169d41 | 2229 | gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg, |
56aebc89 PB |
2230 | 51, "arm-neon.xml", 0); |
2231 | } else if (arm_feature(env, ARM_FEATURE_VFP3)) { | |
22169d41 | 2232 | gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg, |
56aebc89 PB |
2233 | 35, "arm-vfp3.xml", 0); |
2234 | } else if (arm_feature(env, ARM_FEATURE_VFP)) { | |
22169d41 | 2235 | gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg, |
56aebc89 PB |
2236 | 19, "arm-vfp.xml", 0); |
2237 | } | |
40f137e1 PB |
2238 | } |
2239 | ||
777dc784 PM |
2240 | /* Sort alphabetically by type name, except for "any". */ |
2241 | static gint arm_cpu_list_compare(gconstpointer a, gconstpointer b) | |
5adb4839 | 2242 | { |
777dc784 PM |
2243 | ObjectClass *class_a = (ObjectClass *)a; |
2244 | ObjectClass *class_b = (ObjectClass *)b; | |
2245 | const char *name_a, *name_b; | |
5adb4839 | 2246 | |
777dc784 PM |
2247 | name_a = object_class_get_name(class_a); |
2248 | name_b = object_class_get_name(class_b); | |
51492fd1 | 2249 | if (strcmp(name_a, "any-" TYPE_ARM_CPU) == 0) { |
777dc784 | 2250 | return 1; |
51492fd1 | 2251 | } else if (strcmp(name_b, "any-" TYPE_ARM_CPU) == 0) { |
777dc784 PM |
2252 | return -1; |
2253 | } else { | |
2254 | return strcmp(name_a, name_b); | |
5adb4839 PB |
2255 | } |
2256 | } | |
2257 | ||
777dc784 | 2258 | static void arm_cpu_list_entry(gpointer data, gpointer user_data) |
40f137e1 | 2259 | { |
777dc784 | 2260 | ObjectClass *oc = data; |
92a31361 | 2261 | CPUListState *s = user_data; |
51492fd1 AF |
2262 | const char *typename; |
2263 | char *name; | |
3371d272 | 2264 | |
51492fd1 AF |
2265 | typename = object_class_get_name(oc); |
2266 | name = g_strndup(typename, strlen(typename) - strlen("-" TYPE_ARM_CPU)); | |
777dc784 | 2267 | (*s->cpu_fprintf)(s->file, " %s\n", |
51492fd1 AF |
2268 | name); |
2269 | g_free(name); | |
777dc784 PM |
2270 | } |
2271 | ||
2272 | void arm_cpu_list(FILE *f, fprintf_function cpu_fprintf) | |
2273 | { | |
92a31361 | 2274 | CPUListState s = { |
777dc784 PM |
2275 | .file = f, |
2276 | .cpu_fprintf = cpu_fprintf, | |
2277 | }; | |
2278 | GSList *list; | |
2279 | ||
2280 | list = object_class_get_list(TYPE_ARM_CPU, false); | |
2281 | list = g_slist_sort(list, arm_cpu_list_compare); | |
2282 | (*cpu_fprintf)(f, "Available CPUs:\n"); | |
2283 | g_slist_foreach(list, arm_cpu_list_entry, &s); | |
2284 | g_slist_free(list); | |
a96c0514 PM |
2285 | #ifdef CONFIG_KVM |
2286 | /* The 'host' CPU type is dynamically registered only if KVM is | |
2287 | * enabled, so we have to special-case it here: | |
2288 | */ | |
2289 | (*cpu_fprintf)(f, " host (only available in KVM mode)\n"); | |
2290 | #endif | |
40f137e1 PB |
2291 | } |
2292 | ||
78027bb6 CR |
2293 | static void arm_cpu_add_definition(gpointer data, gpointer user_data) |
2294 | { | |
2295 | ObjectClass *oc = data; | |
2296 | CpuDefinitionInfoList **cpu_list = user_data; | |
2297 | CpuDefinitionInfoList *entry; | |
2298 | CpuDefinitionInfo *info; | |
2299 | const char *typename; | |
2300 | ||
2301 | typename = object_class_get_name(oc); | |
2302 | info = g_malloc0(sizeof(*info)); | |
2303 | info->name = g_strndup(typename, | |
2304 | strlen(typename) - strlen("-" TYPE_ARM_CPU)); | |
2305 | ||
2306 | entry = g_malloc0(sizeof(*entry)); | |
2307 | entry->value = info; | |
2308 | entry->next = *cpu_list; | |
2309 | *cpu_list = entry; | |
2310 | } | |
2311 | ||
2312 | CpuDefinitionInfoList *arch_query_cpu_definitions(Error **errp) | |
2313 | { | |
2314 | CpuDefinitionInfoList *cpu_list = NULL; | |
2315 | GSList *list; | |
2316 | ||
2317 | list = object_class_get_list(TYPE_ARM_CPU, false); | |
2318 | g_slist_foreach(list, arm_cpu_add_definition, &cpu_list); | |
2319 | g_slist_free(list); | |
2320 | ||
2321 | return cpu_list; | |
2322 | } | |
2323 | ||
6e6efd61 | 2324 | static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r, |
f5a0a5a5 PM |
2325 | void *opaque, int state, |
2326 | int crm, int opc1, int opc2) | |
6e6efd61 PM |
2327 | { |
2328 | /* Private utility function for define_one_arm_cp_reg_with_opaque(): | |
2329 | * add a single reginfo struct to the hash table. | |
2330 | */ | |
2331 | uint32_t *key = g_new(uint32_t, 1); | |
2332 | ARMCPRegInfo *r2 = g_memdup(r, sizeof(ARMCPRegInfo)); | |
2333 | int is64 = (r->type & ARM_CP_64BIT) ? 1 : 0; | |
f5a0a5a5 PM |
2334 | if (r->state == ARM_CP_STATE_BOTH && state == ARM_CP_STATE_AA32) { |
2335 | /* The AArch32 view of a shared register sees the lower 32 bits | |
2336 | * of a 64 bit backing field. It is not migratable as the AArch64 | |
2337 | * view handles that. AArch64 also handles reset. | |
2338 | * We assume it is a cp15 register. | |
2339 | */ | |
2340 | r2->cp = 15; | |
2341 | r2->type |= ARM_CP_NO_MIGRATE; | |
2342 | r2->resetfn = arm_cp_reset_ignore; | |
2343 | #ifdef HOST_WORDS_BIGENDIAN | |
2344 | if (r2->fieldoffset) { | |
2345 | r2->fieldoffset += sizeof(uint32_t); | |
2346 | } | |
2347 | #endif | |
2348 | } | |
2349 | if (state == ARM_CP_STATE_AA64) { | |
2350 | /* To allow abbreviation of ARMCPRegInfo | |
2351 | * definitions, we treat cp == 0 as equivalent to | |
2352 | * the value for "standard guest-visible sysreg". | |
2353 | */ | |
2354 | if (r->cp == 0) { | |
2355 | r2->cp = CP_REG_ARM64_SYSREG_CP; | |
2356 | } | |
2357 | *key = ENCODE_AA64_CP_REG(r2->cp, r2->crn, crm, | |
2358 | r2->opc0, opc1, opc2); | |
2359 | } else { | |
2360 | *key = ENCODE_CP_REG(r2->cp, is64, r2->crn, crm, opc1, opc2); | |
2361 | } | |
6e6efd61 PM |
2362 | if (opaque) { |
2363 | r2->opaque = opaque; | |
2364 | } | |
67ed771d PM |
2365 | /* reginfo passed to helpers is correct for the actual access, |
2366 | * and is never ARM_CP_STATE_BOTH: | |
2367 | */ | |
2368 | r2->state = state; | |
6e6efd61 PM |
2369 | /* Make sure reginfo passed to helpers for wildcarded regs |
2370 | * has the correct crm/opc1/opc2 for this reg, not CP_ANY: | |
2371 | */ | |
2372 | r2->crm = crm; | |
2373 | r2->opc1 = opc1; | |
2374 | r2->opc2 = opc2; | |
2375 | /* By convention, for wildcarded registers only the first | |
2376 | * entry is used for migration; the others are marked as | |
2377 | * NO_MIGRATE so we don't try to transfer the register | |
2378 | * multiple times. Special registers (ie NOP/WFI) are | |
2379 | * never migratable. | |
2380 | */ | |
2381 | if ((r->type & ARM_CP_SPECIAL) || | |
2382 | ((r->crm == CP_ANY) && crm != 0) || | |
2383 | ((r->opc1 == CP_ANY) && opc1 != 0) || | |
2384 | ((r->opc2 == CP_ANY) && opc2 != 0)) { | |
2385 | r2->type |= ARM_CP_NO_MIGRATE; | |
2386 | } | |
2387 | ||
2388 | /* Overriding of an existing definition must be explicitly | |
2389 | * requested. | |
2390 | */ | |
2391 | if (!(r->type & ARM_CP_OVERRIDE)) { | |
2392 | ARMCPRegInfo *oldreg; | |
2393 | oldreg = g_hash_table_lookup(cpu->cp_regs, key); | |
2394 | if (oldreg && !(oldreg->type & ARM_CP_OVERRIDE)) { | |
2395 | fprintf(stderr, "Register redefined: cp=%d %d bit " | |
2396 | "crn=%d crm=%d opc1=%d opc2=%d, " | |
2397 | "was %s, now %s\n", r2->cp, 32 + 32 * is64, | |
2398 | r2->crn, r2->crm, r2->opc1, r2->opc2, | |
2399 | oldreg->name, r2->name); | |
2400 | g_assert_not_reached(); | |
2401 | } | |
2402 | } | |
2403 | g_hash_table_insert(cpu->cp_regs, key, r2); | |
2404 | } | |
2405 | ||
2406 | ||
4b6a83fb PM |
2407 | void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu, |
2408 | const ARMCPRegInfo *r, void *opaque) | |
2409 | { | |
2410 | /* Define implementations of coprocessor registers. | |
2411 | * We store these in a hashtable because typically | |
2412 | * there are less than 150 registers in a space which | |
2413 | * is 16*16*16*8*8 = 262144 in size. | |
2414 | * Wildcarding is supported for the crm, opc1 and opc2 fields. | |
2415 | * If a register is defined twice then the second definition is | |
2416 | * used, so this can be used to define some generic registers and | |
2417 | * then override them with implementation specific variations. | |
2418 | * At least one of the original and the second definition should | |
2419 | * include ARM_CP_OVERRIDE in its type bits -- this is just a guard | |
2420 | * against accidental use. | |
f5a0a5a5 PM |
2421 | * |
2422 | * The state field defines whether the register is to be | |
2423 | * visible in the AArch32 or AArch64 execution state. If the | |
2424 | * state is set to ARM_CP_STATE_BOTH then we synthesise a | |
2425 | * reginfo structure for the AArch32 view, which sees the lower | |
2426 | * 32 bits of the 64 bit register. | |
2427 | * | |
2428 | * Only registers visible in AArch64 may set r->opc0; opc0 cannot | |
2429 | * be wildcarded. AArch64 registers are always considered to be 64 | |
2430 | * bits; the ARM_CP_64BIT* flag applies only to the AArch32 view of | |
2431 | * the register, if any. | |
4b6a83fb | 2432 | */ |
f5a0a5a5 | 2433 | int crm, opc1, opc2, state; |
4b6a83fb PM |
2434 | int crmmin = (r->crm == CP_ANY) ? 0 : r->crm; |
2435 | int crmmax = (r->crm == CP_ANY) ? 15 : r->crm; | |
2436 | int opc1min = (r->opc1 == CP_ANY) ? 0 : r->opc1; | |
2437 | int opc1max = (r->opc1 == CP_ANY) ? 7 : r->opc1; | |
2438 | int opc2min = (r->opc2 == CP_ANY) ? 0 : r->opc2; | |
2439 | int opc2max = (r->opc2 == CP_ANY) ? 7 : r->opc2; | |
2440 | /* 64 bit registers have only CRm and Opc1 fields */ | |
2441 | assert(!((r->type & ARM_CP_64BIT) && (r->opc2 || r->crn))); | |
f5a0a5a5 PM |
2442 | /* op0 only exists in the AArch64 encodings */ |
2443 | assert((r->state != ARM_CP_STATE_AA32) || (r->opc0 == 0)); | |
2444 | /* AArch64 regs are all 64 bit so ARM_CP_64BIT is meaningless */ | |
2445 | assert((r->state != ARM_CP_STATE_AA64) || !(r->type & ARM_CP_64BIT)); | |
2446 | /* The AArch64 pseudocode CheckSystemAccess() specifies that op1 | |
2447 | * encodes a minimum access level for the register. We roll this | |
2448 | * runtime check into our general permission check code, so check | |
2449 | * here that the reginfo's specified permissions are strict enough | |
2450 | * to encompass the generic architectural permission check. | |
2451 | */ | |
2452 | if (r->state != ARM_CP_STATE_AA32) { | |
2453 | int mask = 0; | |
2454 | switch (r->opc1) { | |
2455 | case 0: case 1: case 2: | |
2456 | /* min_EL EL1 */ | |
2457 | mask = PL1_RW; | |
2458 | break; | |
2459 | case 3: | |
2460 | /* min_EL EL0 */ | |
2461 | mask = PL0_RW; | |
2462 | break; | |
2463 | case 4: | |
2464 | /* min_EL EL2 */ | |
2465 | mask = PL2_RW; | |
2466 | break; | |
2467 | case 5: | |
2468 | /* unallocated encoding, so not possible */ | |
2469 | assert(false); | |
2470 | break; | |
2471 | case 6: | |
2472 | /* min_EL EL3 */ | |
2473 | mask = PL3_RW; | |
2474 | break; | |
2475 | case 7: | |
2476 | /* min_EL EL1, secure mode only (we don't check the latter) */ | |
2477 | mask = PL1_RW; | |
2478 | break; | |
2479 | default: | |
2480 | /* broken reginfo with out-of-range opc1 */ | |
2481 | assert(false); | |
2482 | break; | |
2483 | } | |
2484 | /* assert our permissions are not too lax (stricter is fine) */ | |
2485 | assert((r->access & ~mask) == 0); | |
2486 | } | |
2487 | ||
4b6a83fb PM |
2488 | /* Check that the register definition has enough info to handle |
2489 | * reads and writes if they are permitted. | |
2490 | */ | |
2491 | if (!(r->type & (ARM_CP_SPECIAL|ARM_CP_CONST))) { | |
2492 | if (r->access & PL3_R) { | |
2493 | assert(r->fieldoffset || r->readfn); | |
2494 | } | |
2495 | if (r->access & PL3_W) { | |
2496 | assert(r->fieldoffset || r->writefn); | |
2497 | } | |
2498 | } | |
2499 | /* Bad type field probably means missing sentinel at end of reg list */ | |
2500 | assert(cptype_valid(r->type)); | |
2501 | for (crm = crmmin; crm <= crmmax; crm++) { | |
2502 | for (opc1 = opc1min; opc1 <= opc1max; opc1++) { | |
2503 | for (opc2 = opc2min; opc2 <= opc2max; opc2++) { | |
f5a0a5a5 PM |
2504 | for (state = ARM_CP_STATE_AA32; |
2505 | state <= ARM_CP_STATE_AA64; state++) { | |
2506 | if (r->state != state && r->state != ARM_CP_STATE_BOTH) { | |
2507 | continue; | |
2508 | } | |
2509 | add_cpreg_to_hashtable(cpu, r, opaque, state, | |
2510 | crm, opc1, opc2); | |
2511 | } | |
4b6a83fb PM |
2512 | } |
2513 | } | |
2514 | } | |
2515 | } | |
2516 | ||
2517 | void define_arm_cp_regs_with_opaque(ARMCPU *cpu, | |
2518 | const ARMCPRegInfo *regs, void *opaque) | |
2519 | { | |
2520 | /* Define a whole list of registers */ | |
2521 | const ARMCPRegInfo *r; | |
2522 | for (r = regs; r->type != ARM_CP_SENTINEL; r++) { | |
2523 | define_one_arm_cp_reg_with_opaque(cpu, r, opaque); | |
2524 | } | |
2525 | } | |
2526 | ||
60322b39 | 2527 | const ARMCPRegInfo *get_arm_cp_reginfo(GHashTable *cpregs, uint32_t encoded_cp) |
4b6a83fb | 2528 | { |
60322b39 | 2529 | return g_hash_table_lookup(cpregs, &encoded_cp); |
4b6a83fb PM |
2530 | } |
2531 | ||
c4241c7d PM |
2532 | void arm_cp_write_ignore(CPUARMState *env, const ARMCPRegInfo *ri, |
2533 | uint64_t value) | |
4b6a83fb PM |
2534 | { |
2535 | /* Helper coprocessor write function for write-ignore registers */ | |
4b6a83fb PM |
2536 | } |
2537 | ||
c4241c7d | 2538 | uint64_t arm_cp_read_zero(CPUARMState *env, const ARMCPRegInfo *ri) |
4b6a83fb PM |
2539 | { |
2540 | /* Helper coprocessor write function for read-as-zero registers */ | |
4b6a83fb PM |
2541 | return 0; |
2542 | } | |
2543 | ||
f5a0a5a5 PM |
2544 | void arm_cp_reset_ignore(CPUARMState *env, const ARMCPRegInfo *opaque) |
2545 | { | |
2546 | /* Helper coprocessor reset function for do-nothing-on-reset registers */ | |
2547 | } | |
2548 | ||
0ecb72a5 | 2549 | static int bad_mode_switch(CPUARMState *env, int mode) |
37064a8b PM |
2550 | { |
2551 | /* Return true if it is not valid for us to switch to | |
2552 | * this CPU mode (ie all the UNPREDICTABLE cases in | |
2553 | * the ARM ARM CPSRWriteByInstr pseudocode). | |
2554 | */ | |
2555 | switch (mode) { | |
2556 | case ARM_CPU_MODE_USR: | |
2557 | case ARM_CPU_MODE_SYS: | |
2558 | case ARM_CPU_MODE_SVC: | |
2559 | case ARM_CPU_MODE_ABT: | |
2560 | case ARM_CPU_MODE_UND: | |
2561 | case ARM_CPU_MODE_IRQ: | |
2562 | case ARM_CPU_MODE_FIQ: | |
2563 | return 0; | |
2564 | default: | |
2565 | return 1; | |
2566 | } | |
2567 | } | |
2568 | ||
2f4a40e5 AZ |
2569 | uint32_t cpsr_read(CPUARMState *env) |
2570 | { | |
2571 | int ZF; | |
6fbe23d5 PB |
2572 | ZF = (env->ZF == 0); |
2573 | return env->uncached_cpsr | (env->NF & 0x80000000) | (ZF << 30) | | |
2f4a40e5 AZ |
2574 | (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27) |
2575 | | (env->thumb << 5) | ((env->condexec_bits & 3) << 25) | |
2576 | | ((env->condexec_bits & 0xfc) << 8) | |
af519934 | 2577 | | (env->GE << 16) | (env->daif & CPSR_AIF); |
2f4a40e5 AZ |
2578 | } |
2579 | ||
2580 | void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask) | |
2581 | { | |
2f4a40e5 | 2582 | if (mask & CPSR_NZCV) { |
6fbe23d5 PB |
2583 | env->ZF = (~val) & CPSR_Z; |
2584 | env->NF = val; | |
2f4a40e5 AZ |
2585 | env->CF = (val >> 29) & 1; |
2586 | env->VF = (val << 3) & 0x80000000; | |
2587 | } | |
2588 | if (mask & CPSR_Q) | |
2589 | env->QF = ((val & CPSR_Q) != 0); | |
2590 | if (mask & CPSR_T) | |
2591 | env->thumb = ((val & CPSR_T) != 0); | |
2592 | if (mask & CPSR_IT_0_1) { | |
2593 | env->condexec_bits &= ~3; | |
2594 | env->condexec_bits |= (val >> 25) & 3; | |
2595 | } | |
2596 | if (mask & CPSR_IT_2_7) { | |
2597 | env->condexec_bits &= 3; | |
2598 | env->condexec_bits |= (val >> 8) & 0xfc; | |
2599 | } | |
2600 | if (mask & CPSR_GE) { | |
2601 | env->GE = (val >> 16) & 0xf; | |
2602 | } | |
2603 | ||
4cc35614 PM |
2604 | env->daif &= ~(CPSR_AIF & mask); |
2605 | env->daif |= val & CPSR_AIF & mask; | |
2606 | ||
2f4a40e5 | 2607 | if ((env->uncached_cpsr ^ val) & mask & CPSR_M) { |
37064a8b PM |
2608 | if (bad_mode_switch(env, val & CPSR_M)) { |
2609 | /* Attempt to switch to an invalid mode: this is UNPREDICTABLE. | |
2610 | * We choose to ignore the attempt and leave the CPSR M field | |
2611 | * untouched. | |
2612 | */ | |
2613 | mask &= ~CPSR_M; | |
2614 | } else { | |
2615 | switch_mode(env, val & CPSR_M); | |
2616 | } | |
2f4a40e5 AZ |
2617 | } |
2618 | mask &= ~CACHED_CPSR_BITS; | |
2619 | env->uncached_cpsr = (env->uncached_cpsr & ~mask) | (val & mask); | |
2620 | } | |
2621 | ||
b26eefb6 PB |
2622 | /* Sign/zero extend */ |
2623 | uint32_t HELPER(sxtb16)(uint32_t x) | |
2624 | { | |
2625 | uint32_t res; | |
2626 | res = (uint16_t)(int8_t)x; | |
2627 | res |= (uint32_t)(int8_t)(x >> 16) << 16; | |
2628 | return res; | |
2629 | } | |
2630 | ||
2631 | uint32_t HELPER(uxtb16)(uint32_t x) | |
2632 | { | |
2633 | uint32_t res; | |
2634 | res = (uint16_t)(uint8_t)x; | |
2635 | res |= (uint32_t)(uint8_t)(x >> 16) << 16; | |
2636 | return res; | |
2637 | } | |
2638 | ||
f51bbbfe PB |
2639 | uint32_t HELPER(clz)(uint32_t x) |
2640 | { | |
7bbcb0af | 2641 | return clz32(x); |
f51bbbfe PB |
2642 | } |
2643 | ||
3670669c PB |
2644 | int32_t HELPER(sdiv)(int32_t num, int32_t den) |
2645 | { | |
2646 | if (den == 0) | |
2647 | return 0; | |
686eeb93 AJ |
2648 | if (num == INT_MIN && den == -1) |
2649 | return INT_MIN; | |
3670669c PB |
2650 | return num / den; |
2651 | } | |
2652 | ||
2653 | uint32_t HELPER(udiv)(uint32_t num, uint32_t den) | |
2654 | { | |
2655 | if (den == 0) | |
2656 | return 0; | |
2657 | return num / den; | |
2658 | } | |
2659 | ||
2660 | uint32_t HELPER(rbit)(uint32_t x) | |
2661 | { | |
2662 | x = ((x & 0xff000000) >> 24) | |
2663 | | ((x & 0x00ff0000) >> 8) | |
2664 | | ((x & 0x0000ff00) << 8) | |
2665 | | ((x & 0x000000ff) << 24); | |
2666 | x = ((x & 0xf0f0f0f0) >> 4) | |
2667 | | ((x & 0x0f0f0f0f) << 4); | |
2668 | x = ((x & 0x88888888) >> 3) | |
2669 | | ((x & 0x44444444) >> 1) | |
2670 | | ((x & 0x22222222) << 1) | |
2671 | | ((x & 0x11111111) << 3); | |
2672 | return x; | |
2673 | } | |
2674 | ||
5fafdf24 | 2675 | #if defined(CONFIG_USER_ONLY) |
b5ff1b31 | 2676 | |
97a8ea5a | 2677 | void arm_cpu_do_interrupt(CPUState *cs) |
b5ff1b31 | 2678 | { |
27103424 | 2679 | cs->exception_index = -1; |
b5ff1b31 FB |
2680 | } |
2681 | ||
7510454e AF |
2682 | int arm_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw, |
2683 | int mmu_idx) | |
b5ff1b31 | 2684 | { |
7510454e AF |
2685 | ARMCPU *cpu = ARM_CPU(cs); |
2686 | CPUARMState *env = &cpu->env; | |
2687 | ||
b5ff1b31 | 2688 | if (rw == 2) { |
27103424 | 2689 | cs->exception_index = EXCP_PREFETCH_ABORT; |
b5ff1b31 FB |
2690 | env->cp15.c6_insn = address; |
2691 | } else { | |
27103424 | 2692 | cs->exception_index = EXCP_DATA_ABORT; |
b5ff1b31 FB |
2693 | env->cp15.c6_data = address; |
2694 | } | |
2695 | return 1; | |
2696 | } | |
2697 | ||
9ee6e8bb | 2698 | /* These should probably raise undefined insn exceptions. */ |
0ecb72a5 | 2699 | void HELPER(v7m_msr)(CPUARMState *env, uint32_t reg, uint32_t val) |
9ee6e8bb | 2700 | { |
a47dddd7 AF |
2701 | ARMCPU *cpu = arm_env_get_cpu(env); |
2702 | ||
2703 | cpu_abort(CPU(cpu), "v7m_msr %d\n", reg); | |
9ee6e8bb PB |
2704 | } |
2705 | ||
0ecb72a5 | 2706 | uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg) |
9ee6e8bb | 2707 | { |
a47dddd7 AF |
2708 | ARMCPU *cpu = arm_env_get_cpu(env); |
2709 | ||
2710 | cpu_abort(CPU(cpu), "v7m_mrs %d\n", reg); | |
9ee6e8bb PB |
2711 | return 0; |
2712 | } | |
2713 | ||
0ecb72a5 | 2714 | void switch_mode(CPUARMState *env, int mode) |
b5ff1b31 | 2715 | { |
a47dddd7 AF |
2716 | ARMCPU *cpu = arm_env_get_cpu(env); |
2717 | ||
2718 | if (mode != ARM_CPU_MODE_USR) { | |
2719 | cpu_abort(CPU(cpu), "Tried to switch out of user mode\n"); | |
2720 | } | |
b5ff1b31 FB |
2721 | } |
2722 | ||
0ecb72a5 | 2723 | void HELPER(set_r13_banked)(CPUARMState *env, uint32_t mode, uint32_t val) |
9ee6e8bb | 2724 | { |
a47dddd7 AF |
2725 | ARMCPU *cpu = arm_env_get_cpu(env); |
2726 | ||
2727 | cpu_abort(CPU(cpu), "banked r13 write\n"); | |
9ee6e8bb PB |
2728 | } |
2729 | ||
0ecb72a5 | 2730 | uint32_t HELPER(get_r13_banked)(CPUARMState *env, uint32_t mode) |
9ee6e8bb | 2731 | { |
a47dddd7 AF |
2732 | ARMCPU *cpu = arm_env_get_cpu(env); |
2733 | ||
2734 | cpu_abort(CPU(cpu), "banked r13 read\n"); | |
9ee6e8bb PB |
2735 | return 0; |
2736 | } | |
2737 | ||
b5ff1b31 FB |
2738 | #else |
2739 | ||
2740 | /* Map CPU modes onto saved register banks. */ | |
494b00c7 | 2741 | int bank_number(int mode) |
b5ff1b31 FB |
2742 | { |
2743 | switch (mode) { | |
2744 | case ARM_CPU_MODE_USR: | |
2745 | case ARM_CPU_MODE_SYS: | |
2746 | return 0; | |
2747 | case ARM_CPU_MODE_SVC: | |
2748 | return 1; | |
2749 | case ARM_CPU_MODE_ABT: | |
2750 | return 2; | |
2751 | case ARM_CPU_MODE_UND: | |
2752 | return 3; | |
2753 | case ARM_CPU_MODE_IRQ: | |
2754 | return 4; | |
2755 | case ARM_CPU_MODE_FIQ: | |
2756 | return 5; | |
2757 | } | |
f5206413 | 2758 | hw_error("bank number requested for bad CPSR mode value 0x%x\n", mode); |
b5ff1b31 FB |
2759 | } |
2760 | ||
0ecb72a5 | 2761 | void switch_mode(CPUARMState *env, int mode) |
b5ff1b31 FB |
2762 | { |
2763 | int old_mode; | |
2764 | int i; | |
2765 | ||
2766 | old_mode = env->uncached_cpsr & CPSR_M; | |
2767 | if (mode == old_mode) | |
2768 | return; | |
2769 | ||
2770 | if (old_mode == ARM_CPU_MODE_FIQ) { | |
2771 | memcpy (env->fiq_regs, env->regs + 8, 5 * sizeof(uint32_t)); | |
8637c67f | 2772 | memcpy (env->regs + 8, env->usr_regs, 5 * sizeof(uint32_t)); |
b5ff1b31 FB |
2773 | } else if (mode == ARM_CPU_MODE_FIQ) { |
2774 | memcpy (env->usr_regs, env->regs + 8, 5 * sizeof(uint32_t)); | |
8637c67f | 2775 | memcpy (env->regs + 8, env->fiq_regs, 5 * sizeof(uint32_t)); |
b5ff1b31 FB |
2776 | } |
2777 | ||
f5206413 | 2778 | i = bank_number(old_mode); |
b5ff1b31 FB |
2779 | env->banked_r13[i] = env->regs[13]; |
2780 | env->banked_r14[i] = env->regs[14]; | |
2781 | env->banked_spsr[i] = env->spsr; | |
2782 | ||
f5206413 | 2783 | i = bank_number(mode); |
b5ff1b31 FB |
2784 | env->regs[13] = env->banked_r13[i]; |
2785 | env->regs[14] = env->banked_r14[i]; | |
2786 | env->spsr = env->banked_spsr[i]; | |
2787 | } | |
2788 | ||
9ee6e8bb PB |
2789 | static void v7m_push(CPUARMState *env, uint32_t val) |
2790 | { | |
70d74660 AF |
2791 | CPUState *cs = CPU(arm_env_get_cpu(env)); |
2792 | ||
9ee6e8bb | 2793 | env->regs[13] -= 4; |
ab1da857 | 2794 | stl_phys(cs->as, env->regs[13], val); |
9ee6e8bb PB |
2795 | } |
2796 | ||
2797 | static uint32_t v7m_pop(CPUARMState *env) | |
2798 | { | |
70d74660 | 2799 | CPUState *cs = CPU(arm_env_get_cpu(env)); |
9ee6e8bb | 2800 | uint32_t val; |
70d74660 | 2801 | |
fdfba1a2 | 2802 | val = ldl_phys(cs->as, env->regs[13]); |
9ee6e8bb PB |
2803 | env->regs[13] += 4; |
2804 | return val; | |
2805 | } | |
2806 | ||
2807 | /* Switch to V7M main or process stack pointer. */ | |
2808 | static void switch_v7m_sp(CPUARMState *env, int process) | |
2809 | { | |
2810 | uint32_t tmp; | |
2811 | if (env->v7m.current_sp != process) { | |
2812 | tmp = env->v7m.other_sp; | |
2813 | env->v7m.other_sp = env->regs[13]; | |
2814 | env->regs[13] = tmp; | |
2815 | env->v7m.current_sp = process; | |
2816 | } | |
2817 | } | |
2818 | ||
2819 | static void do_v7m_exception_exit(CPUARMState *env) | |
2820 | { | |
2821 | uint32_t type; | |
2822 | uint32_t xpsr; | |
2823 | ||
2824 | type = env->regs[15]; | |
2825 | if (env->v7m.exception != 0) | |
983fe826 | 2826 | armv7m_nvic_complete_irq(env->nvic, env->v7m.exception); |
9ee6e8bb PB |
2827 | |
2828 | /* Switch to the target stack. */ | |
2829 | switch_v7m_sp(env, (type & 4) != 0); | |
2830 | /* Pop registers. */ | |
2831 | env->regs[0] = v7m_pop(env); | |
2832 | env->regs[1] = v7m_pop(env); | |
2833 | env->regs[2] = v7m_pop(env); | |
2834 | env->regs[3] = v7m_pop(env); | |
2835 | env->regs[12] = v7m_pop(env); | |
2836 | env->regs[14] = v7m_pop(env); | |
2837 | env->regs[15] = v7m_pop(env); | |
2838 | xpsr = v7m_pop(env); | |
2839 | xpsr_write(env, xpsr, 0xfffffdff); | |
2840 | /* Undo stack alignment. */ | |
2841 | if (xpsr & 0x200) | |
2842 | env->regs[13] |= 4; | |
2843 | /* ??? The exception return type specifies Thread/Handler mode. However | |
2844 | this is also implied by the xPSR value. Not sure what to do | |
2845 | if there is a mismatch. */ | |
2846 | /* ??? Likewise for mismatches between the CONTROL register and the stack | |
2847 | pointer. */ | |
2848 | } | |
2849 | ||
3f1beaca PM |
2850 | /* Exception names for debug logging; note that not all of these |
2851 | * precisely correspond to architectural exceptions. | |
2852 | */ | |
2853 | static const char * const excnames[] = { | |
2854 | [EXCP_UDEF] = "Undefined Instruction", | |
2855 | [EXCP_SWI] = "SVC", | |
2856 | [EXCP_PREFETCH_ABORT] = "Prefetch Abort", | |
2857 | [EXCP_DATA_ABORT] = "Data Abort", | |
2858 | [EXCP_IRQ] = "IRQ", | |
2859 | [EXCP_FIQ] = "FIQ", | |
2860 | [EXCP_BKPT] = "Breakpoint", | |
2861 | [EXCP_EXCEPTION_EXIT] = "QEMU v7M exception exit", | |
2862 | [EXCP_KERNEL_TRAP] = "QEMU intercept of kernel commpage", | |
2863 | [EXCP_STREX] = "QEMU intercept of STREX", | |
2864 | }; | |
2865 | ||
2866 | static inline void arm_log_exception(int idx) | |
2867 | { | |
2868 | if (qemu_loglevel_mask(CPU_LOG_INT)) { | |
2869 | const char *exc = NULL; | |
2870 | ||
2871 | if (idx >= 0 && idx < ARRAY_SIZE(excnames)) { | |
2872 | exc = excnames[idx]; | |
2873 | } | |
2874 | if (!exc) { | |
2875 | exc = "unknown"; | |
2876 | } | |
2877 | qemu_log_mask(CPU_LOG_INT, "Taking exception %d [%s]\n", idx, exc); | |
2878 | } | |
2879 | } | |
2880 | ||
e6f010cc | 2881 | void arm_v7m_cpu_do_interrupt(CPUState *cs) |
9ee6e8bb | 2882 | { |
e6f010cc AF |
2883 | ARMCPU *cpu = ARM_CPU(cs); |
2884 | CPUARMState *env = &cpu->env; | |
9ee6e8bb PB |
2885 | uint32_t xpsr = xpsr_read(env); |
2886 | uint32_t lr; | |
2887 | uint32_t addr; | |
2888 | ||
27103424 | 2889 | arm_log_exception(cs->exception_index); |
3f1beaca | 2890 | |
9ee6e8bb PB |
2891 | lr = 0xfffffff1; |
2892 | if (env->v7m.current_sp) | |
2893 | lr |= 4; | |
2894 | if (env->v7m.exception == 0) | |
2895 | lr |= 8; | |
2896 | ||
2897 | /* For exceptions we just mark as pending on the NVIC, and let that | |
2898 | handle it. */ | |
2899 | /* TODO: Need to escalate if the current priority is higher than the | |
2900 | one we're raising. */ | |
27103424 | 2901 | switch (cs->exception_index) { |
9ee6e8bb | 2902 | case EXCP_UDEF: |
983fe826 | 2903 | armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE); |
9ee6e8bb PB |
2904 | return; |
2905 | case EXCP_SWI: | |
314e2296 | 2906 | /* The PC already points to the next instruction. */ |
983fe826 | 2907 | armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_SVC); |
9ee6e8bb PB |
2908 | return; |
2909 | case EXCP_PREFETCH_ABORT: | |
2910 | case EXCP_DATA_ABORT: | |
983fe826 | 2911 | armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_MEM); |
9ee6e8bb PB |
2912 | return; |
2913 | case EXCP_BKPT: | |
2ad207d4 PB |
2914 | if (semihosting_enabled) { |
2915 | int nr; | |
d31dd73e | 2916 | nr = arm_lduw_code(env, env->regs[15], env->bswap_code) & 0xff; |
2ad207d4 PB |
2917 | if (nr == 0xab) { |
2918 | env->regs[15] += 2; | |
2919 | env->regs[0] = do_arm_semihosting(env); | |
3f1beaca | 2920 | qemu_log_mask(CPU_LOG_INT, "...handled as semihosting call\n"); |
2ad207d4 PB |
2921 | return; |
2922 | } | |
2923 | } | |
983fe826 | 2924 | armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_DEBUG); |
9ee6e8bb PB |
2925 | return; |
2926 | case EXCP_IRQ: | |
983fe826 | 2927 | env->v7m.exception = armv7m_nvic_acknowledge_irq(env->nvic); |
9ee6e8bb PB |
2928 | break; |
2929 | case EXCP_EXCEPTION_EXIT: | |
2930 | do_v7m_exception_exit(env); | |
2931 | return; | |
2932 | default: | |
a47dddd7 | 2933 | cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index); |
9ee6e8bb PB |
2934 | return; /* Never happens. Keep compiler happy. */ |
2935 | } | |
2936 | ||
2937 | /* Align stack pointer. */ | |
2938 | /* ??? Should only do this if Configuration Control Register | |
2939 | STACKALIGN bit is set. */ | |
2940 | if (env->regs[13] & 4) { | |
ab19b0ec | 2941 | env->regs[13] -= 4; |
9ee6e8bb PB |
2942 | xpsr |= 0x200; |
2943 | } | |
6c95676b | 2944 | /* Switch to the handler mode. */ |
9ee6e8bb PB |
2945 | v7m_push(env, xpsr); |
2946 | v7m_push(env, env->regs[15]); | |
2947 | v7m_push(env, env->regs[14]); | |
2948 | v7m_push(env, env->regs[12]); | |
2949 | v7m_push(env, env->regs[3]); | |
2950 | v7m_push(env, env->regs[2]); | |
2951 | v7m_push(env, env->regs[1]); | |
2952 | v7m_push(env, env->regs[0]); | |
2953 | switch_v7m_sp(env, 0); | |
c98d174c PM |
2954 | /* Clear IT bits */ |
2955 | env->condexec_bits = 0; | |
9ee6e8bb | 2956 | env->regs[14] = lr; |
fdfba1a2 | 2957 | addr = ldl_phys(cs->as, env->v7m.vecbase + env->v7m.exception * 4); |
9ee6e8bb PB |
2958 | env->regs[15] = addr & 0xfffffffe; |
2959 | env->thumb = addr & 1; | |
2960 | } | |
2961 | ||
b5ff1b31 | 2962 | /* Handle a CPU exception. */ |
97a8ea5a | 2963 | void arm_cpu_do_interrupt(CPUState *cs) |
b5ff1b31 | 2964 | { |
97a8ea5a AF |
2965 | ARMCPU *cpu = ARM_CPU(cs); |
2966 | CPUARMState *env = &cpu->env; | |
b5ff1b31 FB |
2967 | uint32_t addr; |
2968 | uint32_t mask; | |
2969 | int new_mode; | |
2970 | uint32_t offset; | |
2971 | ||
e6f010cc AF |
2972 | assert(!IS_M(env)); |
2973 | ||
27103424 | 2974 | arm_log_exception(cs->exception_index); |
3f1beaca | 2975 | |
b5ff1b31 | 2976 | /* TODO: Vectored interrupt controller. */ |
27103424 | 2977 | switch (cs->exception_index) { |
b5ff1b31 FB |
2978 | case EXCP_UDEF: |
2979 | new_mode = ARM_CPU_MODE_UND; | |
2980 | addr = 0x04; | |
2981 | mask = CPSR_I; | |
2982 | if (env->thumb) | |
2983 | offset = 2; | |
2984 | else | |
2985 | offset = 4; | |
2986 | break; | |
2987 | case EXCP_SWI: | |
8e71621f PB |
2988 | if (semihosting_enabled) { |
2989 | /* Check for semihosting interrupt. */ | |
2990 | if (env->thumb) { | |
d31dd73e BS |
2991 | mask = arm_lduw_code(env, env->regs[15] - 2, env->bswap_code) |
2992 | & 0xff; | |
8e71621f | 2993 | } else { |
d31dd73e | 2994 | mask = arm_ldl_code(env, env->regs[15] - 4, env->bswap_code) |
d8fd2954 | 2995 | & 0xffffff; |
8e71621f PB |
2996 | } |
2997 | /* Only intercept calls from privileged modes, to provide some | |
2998 | semblance of security. */ | |
2999 | if (((mask == 0x123456 && !env->thumb) | |
3000 | || (mask == 0xab && env->thumb)) | |
3001 | && (env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR) { | |
3002 | env->regs[0] = do_arm_semihosting(env); | |
3f1beaca | 3003 | qemu_log_mask(CPU_LOG_INT, "...handled as semihosting call\n"); |
8e71621f PB |
3004 | return; |
3005 | } | |
3006 | } | |
b5ff1b31 FB |
3007 | new_mode = ARM_CPU_MODE_SVC; |
3008 | addr = 0x08; | |
3009 | mask = CPSR_I; | |
601d70b9 | 3010 | /* The PC already points to the next instruction. */ |
b5ff1b31 FB |
3011 | offset = 0; |
3012 | break; | |
06c949e6 | 3013 | case EXCP_BKPT: |
9ee6e8bb | 3014 | /* See if this is a semihosting syscall. */ |
2ad207d4 | 3015 | if (env->thumb && semihosting_enabled) { |
d31dd73e | 3016 | mask = arm_lduw_code(env, env->regs[15], env->bswap_code) & 0xff; |
9ee6e8bb PB |
3017 | if (mask == 0xab |
3018 | && (env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR) { | |
3019 | env->regs[15] += 2; | |
3020 | env->regs[0] = do_arm_semihosting(env); | |
3f1beaca | 3021 | qemu_log_mask(CPU_LOG_INT, "...handled as semihosting call\n"); |
9ee6e8bb PB |
3022 | return; |
3023 | } | |
3024 | } | |
81c05daf | 3025 | env->cp15.c5_insn = 2; |
9ee6e8bb PB |
3026 | /* Fall through to prefetch abort. */ |
3027 | case EXCP_PREFETCH_ABORT: | |
3f1beaca PM |
3028 | qemu_log_mask(CPU_LOG_INT, "...with IFSR 0x%x IFAR 0x%x\n", |
3029 | env->cp15.c5_insn, env->cp15.c6_insn); | |
b5ff1b31 FB |
3030 | new_mode = ARM_CPU_MODE_ABT; |
3031 | addr = 0x0c; | |
3032 | mask = CPSR_A | CPSR_I; | |
3033 | offset = 4; | |
3034 | break; | |
3035 | case EXCP_DATA_ABORT: | |
3f1beaca PM |
3036 | qemu_log_mask(CPU_LOG_INT, "...with DFSR 0x%x DFAR 0x%x\n", |
3037 | env->cp15.c5_data, env->cp15.c6_data); | |
b5ff1b31 FB |
3038 | new_mode = ARM_CPU_MODE_ABT; |
3039 | addr = 0x10; | |
3040 | mask = CPSR_A | CPSR_I; | |
3041 | offset = 8; | |
3042 | break; | |
3043 | case EXCP_IRQ: | |
3044 | new_mode = ARM_CPU_MODE_IRQ; | |
3045 | addr = 0x18; | |
3046 | /* Disable IRQ and imprecise data aborts. */ | |
3047 | mask = CPSR_A | CPSR_I; | |
3048 | offset = 4; | |
3049 | break; | |
3050 | case EXCP_FIQ: | |
3051 | new_mode = ARM_CPU_MODE_FIQ; | |
3052 | addr = 0x1c; | |
3053 | /* Disable FIQ, IRQ and imprecise data aborts. */ | |
3054 | mask = CPSR_A | CPSR_I | CPSR_F; | |
3055 | offset = 4; | |
3056 | break; | |
3057 | default: | |
a47dddd7 | 3058 | cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index); |
b5ff1b31 FB |
3059 | return; /* Never happens. Keep compiler happy. */ |
3060 | } | |
3061 | /* High vectors. */ | |
76e3e1bc | 3062 | if (env->cp15.c1_sys & SCTLR_V) { |
8641136c | 3063 | /* when enabled, base address cannot be remapped. */ |
b5ff1b31 | 3064 | addr += 0xffff0000; |
8641136c NR |
3065 | } else { |
3066 | /* ARM v7 architectures provide a vector base address register to remap | |
3067 | * the interrupt vector table. | |
3068 | * This register is only followed in non-monitor mode, and has a secure | |
3069 | * and un-secure copy. Since the cpu is always in a un-secure operation | |
3070 | * and is never in monitor mode this feature is always active. | |
3071 | * Note: only bits 31:5 are valid. | |
3072 | */ | |
3073 | addr += env->cp15.c12_vbar; | |
b5ff1b31 FB |
3074 | } |
3075 | switch_mode (env, new_mode); | |
3076 | env->spsr = cpsr_read(env); | |
9ee6e8bb PB |
3077 | /* Clear IT bits. */ |
3078 | env->condexec_bits = 0; | |
30a8cac1 | 3079 | /* Switch to the new mode, and to the correct instruction set. */ |
6d7e6326 | 3080 | env->uncached_cpsr = (env->uncached_cpsr & ~CPSR_M) | new_mode; |
4cc35614 | 3081 | env->daif |= mask; |
be5e7a76 DES |
3082 | /* this is a lie, as the was no c1_sys on V4T/V5, but who cares |
3083 | * and we should just guard the thumb mode on V4 */ | |
3084 | if (arm_feature(env, ARM_FEATURE_V4T)) { | |
76e3e1bc | 3085 | env->thumb = (env->cp15.c1_sys & SCTLR_TE) != 0; |
be5e7a76 | 3086 | } |
b5ff1b31 FB |
3087 | env->regs[14] = env->regs[15] + offset; |
3088 | env->regs[15] = addr; | |
259186a7 | 3089 | cs->interrupt_request |= CPU_INTERRUPT_EXITTB; |
b5ff1b31 FB |
3090 | } |
3091 | ||
3092 | /* Check section/page access permissions. | |
3093 | Returns the page protection flags, or zero if the access is not | |
3094 | permitted. */ | |
0ecb72a5 | 3095 | static inline int check_ap(CPUARMState *env, int ap, int domain_prot, |
dd4ebc2e | 3096 | int access_type, int is_user) |
b5ff1b31 | 3097 | { |
9ee6e8bb PB |
3098 | int prot_ro; |
3099 | ||
dd4ebc2e | 3100 | if (domain_prot == 3) { |
b5ff1b31 | 3101 | return PAGE_READ | PAGE_WRITE; |
dd4ebc2e | 3102 | } |
b5ff1b31 | 3103 | |
9ee6e8bb PB |
3104 | if (access_type == 1) |
3105 | prot_ro = 0; | |
3106 | else | |
3107 | prot_ro = PAGE_READ; | |
3108 | ||
b5ff1b31 FB |
3109 | switch (ap) { |
3110 | case 0: | |
99f678a6 PM |
3111 | if (arm_feature(env, ARM_FEATURE_V7)) { |
3112 | return 0; | |
3113 | } | |
78600320 | 3114 | if (access_type == 1) |
b5ff1b31 | 3115 | return 0; |
76e3e1bc PM |
3116 | switch (env->cp15.c1_sys & (SCTLR_S | SCTLR_R)) { |
3117 | case SCTLR_S: | |
b5ff1b31 | 3118 | return is_user ? 0 : PAGE_READ; |
76e3e1bc | 3119 | case SCTLR_R: |
b5ff1b31 FB |
3120 | return PAGE_READ; |
3121 | default: | |
3122 | return 0; | |
3123 | } | |
3124 | case 1: | |
3125 | return is_user ? 0 : PAGE_READ | PAGE_WRITE; | |
3126 | case 2: | |
3127 | if (is_user) | |
9ee6e8bb | 3128 | return prot_ro; |
b5ff1b31 FB |
3129 | else |
3130 | return PAGE_READ | PAGE_WRITE; | |
3131 | case 3: | |
3132 | return PAGE_READ | PAGE_WRITE; | |
d4934d18 | 3133 | case 4: /* Reserved. */ |
9ee6e8bb PB |
3134 | return 0; |
3135 | case 5: | |
3136 | return is_user ? 0 : prot_ro; | |
3137 | case 6: | |
3138 | return prot_ro; | |
d4934d18 | 3139 | case 7: |
0ab06d83 | 3140 | if (!arm_feature (env, ARM_FEATURE_V6K)) |
d4934d18 PB |
3141 | return 0; |
3142 | return prot_ro; | |
b5ff1b31 FB |
3143 | default: |
3144 | abort(); | |
3145 | } | |
3146 | } | |
3147 | ||
0ecb72a5 | 3148 | static uint32_t get_level1_table_address(CPUARMState *env, uint32_t address) |
b2fa1797 PB |
3149 | { |
3150 | uint32_t table; | |
3151 | ||
3152 | if (address & env->cp15.c2_mask) | |
327ed10f | 3153 | table = env->cp15.ttbr1_el1 & 0xffffc000; |
b2fa1797 | 3154 | else |
327ed10f | 3155 | table = env->cp15.ttbr0_el1 & env->cp15.c2_base_mask; |
b2fa1797 PB |
3156 | |
3157 | table |= (address >> 18) & 0x3ffc; | |
3158 | return table; | |
3159 | } | |
3160 | ||
0ecb72a5 | 3161 | static int get_phys_addr_v5(CPUARMState *env, uint32_t address, int access_type, |
a8170e5e | 3162 | int is_user, hwaddr *phys_ptr, |
77a71dd1 | 3163 | int *prot, target_ulong *page_size) |
b5ff1b31 | 3164 | { |
70d74660 | 3165 | CPUState *cs = CPU(arm_env_get_cpu(env)); |
b5ff1b31 FB |
3166 | int code; |
3167 | uint32_t table; | |
3168 | uint32_t desc; | |
3169 | int type; | |
3170 | int ap; | |
3171 | int domain; | |
dd4ebc2e | 3172 | int domain_prot; |
a8170e5e | 3173 | hwaddr phys_addr; |
b5ff1b31 | 3174 | |
9ee6e8bb PB |
3175 | /* Pagetable walk. */ |
3176 | /* Lookup l1 descriptor. */ | |
b2fa1797 | 3177 | table = get_level1_table_address(env, address); |
fdfba1a2 | 3178 | desc = ldl_phys(cs->as, table); |
9ee6e8bb | 3179 | type = (desc & 3); |
dd4ebc2e JCD |
3180 | domain = (desc >> 5) & 0x0f; |
3181 | domain_prot = (env->cp15.c3 >> (domain * 2)) & 3; | |
9ee6e8bb | 3182 | if (type == 0) { |
601d70b9 | 3183 | /* Section translation fault. */ |
9ee6e8bb PB |
3184 | code = 5; |
3185 | goto do_fault; | |
3186 | } | |
dd4ebc2e | 3187 | if (domain_prot == 0 || domain_prot == 2) { |
9ee6e8bb PB |
3188 | if (type == 2) |
3189 | code = 9; /* Section domain fault. */ | |
3190 | else | |
3191 | code = 11; /* Page domain fault. */ | |
3192 | goto do_fault; | |
3193 | } | |
3194 | if (type == 2) { | |
3195 | /* 1Mb section. */ | |
3196 | phys_addr = (desc & 0xfff00000) | (address & 0x000fffff); | |
3197 | ap = (desc >> 10) & 3; | |
3198 | code = 13; | |
d4c430a8 | 3199 | *page_size = 1024 * 1024; |
9ee6e8bb PB |
3200 | } else { |
3201 | /* Lookup l2 entry. */ | |
3202 | if (type == 1) { | |
3203 | /* Coarse pagetable. */ | |
3204 | table = (desc & 0xfffffc00) | ((address >> 10) & 0x3fc); | |
3205 | } else { | |
3206 | /* Fine pagetable. */ | |
3207 | table = (desc & 0xfffff000) | ((address >> 8) & 0xffc); | |
3208 | } | |
fdfba1a2 | 3209 | desc = ldl_phys(cs->as, table); |
9ee6e8bb PB |
3210 | switch (desc & 3) { |
3211 | case 0: /* Page translation fault. */ | |
3212 | code = 7; | |
3213 | goto do_fault; | |
3214 | case 1: /* 64k page. */ | |
3215 | phys_addr = (desc & 0xffff0000) | (address & 0xffff); | |
3216 | ap = (desc >> (4 + ((address >> 13) & 6))) & 3; | |
d4c430a8 | 3217 | *page_size = 0x10000; |
ce819861 | 3218 | break; |
9ee6e8bb PB |
3219 | case 2: /* 4k page. */ |
3220 | phys_addr = (desc & 0xfffff000) | (address & 0xfff); | |
c10f7fc3 | 3221 | ap = (desc >> (4 + ((address >> 9) & 6))) & 3; |
d4c430a8 | 3222 | *page_size = 0x1000; |
ce819861 | 3223 | break; |
9ee6e8bb PB |
3224 | case 3: /* 1k page. */ |
3225 | if (type == 1) { | |
3226 | if (arm_feature(env, ARM_FEATURE_XSCALE)) { | |
3227 | phys_addr = (desc & 0xfffff000) | (address & 0xfff); | |
3228 | } else { | |
3229 | /* Page translation fault. */ | |
3230 | code = 7; | |
3231 | goto do_fault; | |
3232 | } | |
3233 | } else { | |
3234 | phys_addr = (desc & 0xfffffc00) | (address & 0x3ff); | |
3235 | } | |
3236 | ap = (desc >> 4) & 3; | |
d4c430a8 | 3237 | *page_size = 0x400; |
ce819861 PB |
3238 | break; |
3239 | default: | |
9ee6e8bb PB |
3240 | /* Never happens, but compiler isn't smart enough to tell. */ |
3241 | abort(); | |
ce819861 | 3242 | } |
9ee6e8bb PB |
3243 | code = 15; |
3244 | } | |
dd4ebc2e | 3245 | *prot = check_ap(env, ap, domain_prot, access_type, is_user); |
9ee6e8bb PB |
3246 | if (!*prot) { |
3247 | /* Access permission fault. */ | |
3248 | goto do_fault; | |
3249 | } | |
3ad493fc | 3250 | *prot |= PAGE_EXEC; |
9ee6e8bb PB |
3251 | *phys_ptr = phys_addr; |
3252 | return 0; | |
3253 | do_fault: | |
3254 | return code | (domain << 4); | |
3255 | } | |
3256 | ||
0ecb72a5 | 3257 | static int get_phys_addr_v6(CPUARMState *env, uint32_t address, int access_type, |
a8170e5e | 3258 | int is_user, hwaddr *phys_ptr, |
77a71dd1 | 3259 | int *prot, target_ulong *page_size) |
9ee6e8bb | 3260 | { |
70d74660 | 3261 | CPUState *cs = CPU(arm_env_get_cpu(env)); |
9ee6e8bb PB |
3262 | int code; |
3263 | uint32_t table; | |
3264 | uint32_t desc; | |
3265 | uint32_t xn; | |
de9b05b8 | 3266 | uint32_t pxn = 0; |
9ee6e8bb PB |
3267 | int type; |
3268 | int ap; | |
de9b05b8 | 3269 | int domain = 0; |
dd4ebc2e | 3270 | int domain_prot; |
a8170e5e | 3271 | hwaddr phys_addr; |
9ee6e8bb PB |
3272 | |
3273 | /* Pagetable walk. */ | |
3274 | /* Lookup l1 descriptor. */ | |
b2fa1797 | 3275 | table = get_level1_table_address(env, address); |
fdfba1a2 | 3276 | desc = ldl_phys(cs->as, table); |
9ee6e8bb | 3277 | type = (desc & 3); |
de9b05b8 PM |
3278 | if (type == 0 || (type == 3 && !arm_feature(env, ARM_FEATURE_PXN))) { |
3279 | /* Section translation fault, or attempt to use the encoding | |
3280 | * which is Reserved on implementations without PXN. | |
3281 | */ | |
9ee6e8bb | 3282 | code = 5; |
9ee6e8bb | 3283 | goto do_fault; |
de9b05b8 PM |
3284 | } |
3285 | if ((type == 1) || !(desc & (1 << 18))) { | |
3286 | /* Page or Section. */ | |
dd4ebc2e | 3287 | domain = (desc >> 5) & 0x0f; |
9ee6e8bb | 3288 | } |
dd4ebc2e JCD |
3289 | domain_prot = (env->cp15.c3 >> (domain * 2)) & 3; |
3290 | if (domain_prot == 0 || domain_prot == 2) { | |
de9b05b8 | 3291 | if (type != 1) { |
9ee6e8bb | 3292 | code = 9; /* Section domain fault. */ |
de9b05b8 | 3293 | } else { |
9ee6e8bb | 3294 | code = 11; /* Page domain fault. */ |
de9b05b8 | 3295 | } |
9ee6e8bb PB |
3296 | goto do_fault; |
3297 | } | |
de9b05b8 | 3298 | if (type != 1) { |
9ee6e8bb PB |
3299 | if (desc & (1 << 18)) { |
3300 | /* Supersection. */ | |
3301 | phys_addr = (desc & 0xff000000) | (address & 0x00ffffff); | |
d4c430a8 | 3302 | *page_size = 0x1000000; |
b5ff1b31 | 3303 | } else { |
9ee6e8bb PB |
3304 | /* Section. */ |
3305 | phys_addr = (desc & 0xfff00000) | (address & 0x000fffff); | |
d4c430a8 | 3306 | *page_size = 0x100000; |
b5ff1b31 | 3307 | } |
9ee6e8bb PB |
3308 | ap = ((desc >> 10) & 3) | ((desc >> 13) & 4); |
3309 | xn = desc & (1 << 4); | |
de9b05b8 | 3310 | pxn = desc & 1; |
9ee6e8bb PB |
3311 | code = 13; |
3312 | } else { | |
de9b05b8 PM |
3313 | if (arm_feature(env, ARM_FEATURE_PXN)) { |
3314 | pxn = (desc >> 2) & 1; | |
3315 | } | |
9ee6e8bb PB |
3316 | /* Lookup l2 entry. */ |
3317 | table = (desc & 0xfffffc00) | ((address >> 10) & 0x3fc); | |
fdfba1a2 | 3318 | desc = ldl_phys(cs->as, table); |
9ee6e8bb PB |
3319 | ap = ((desc >> 4) & 3) | ((desc >> 7) & 4); |
3320 | switch (desc & 3) { | |
3321 | case 0: /* Page translation fault. */ | |
3322 | code = 7; | |
b5ff1b31 | 3323 | goto do_fault; |
9ee6e8bb PB |
3324 | case 1: /* 64k page. */ |
3325 | phys_addr = (desc & 0xffff0000) | (address & 0xffff); | |
3326 | xn = desc & (1 << 15); | |
d4c430a8 | 3327 | *page_size = 0x10000; |
9ee6e8bb PB |
3328 | break; |
3329 | case 2: case 3: /* 4k page. */ | |
3330 | phys_addr = (desc & 0xfffff000) | (address & 0xfff); | |
3331 | xn = desc & 1; | |
d4c430a8 | 3332 | *page_size = 0x1000; |
9ee6e8bb PB |
3333 | break; |
3334 | default: | |
3335 | /* Never happens, but compiler isn't smart enough to tell. */ | |
3336 | abort(); | |
b5ff1b31 | 3337 | } |
9ee6e8bb PB |
3338 | code = 15; |
3339 | } | |
dd4ebc2e | 3340 | if (domain_prot == 3) { |
c0034328 JR |
3341 | *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; |
3342 | } else { | |
de9b05b8 PM |
3343 | if (pxn && !is_user) { |
3344 | xn = 1; | |
3345 | } | |
c0034328 JR |
3346 | if (xn && access_type == 2) |
3347 | goto do_fault; | |
9ee6e8bb | 3348 | |
c0034328 | 3349 | /* The simplified model uses AP[0] as an access control bit. */ |
76e3e1bc | 3350 | if ((env->cp15.c1_sys & SCTLR_AFE) && (ap & 1) == 0) { |
c0034328 JR |
3351 | /* Access flag fault. */ |
3352 | code = (code == 15) ? 6 : 3; | |
3353 | goto do_fault; | |
3354 | } | |
dd4ebc2e | 3355 | *prot = check_ap(env, ap, domain_prot, access_type, is_user); |
c0034328 JR |
3356 | if (!*prot) { |
3357 | /* Access permission fault. */ | |
3358 | goto do_fault; | |
3359 | } | |
3360 | if (!xn) { | |
3361 | *prot |= PAGE_EXEC; | |
3362 | } | |
3ad493fc | 3363 | } |
9ee6e8bb | 3364 | *phys_ptr = phys_addr; |
b5ff1b31 FB |
3365 | return 0; |
3366 | do_fault: | |
3367 | return code | (domain << 4); | |
3368 | } | |
3369 | ||
3dde962f PM |
3370 | /* Fault type for long-descriptor MMU fault reporting; this corresponds |
3371 | * to bits [5..2] in the STATUS field in long-format DFSR/IFSR. | |
3372 | */ | |
3373 | typedef enum { | |
3374 | translation_fault = 1, | |
3375 | access_fault = 2, | |
3376 | permission_fault = 3, | |
3377 | } MMUFaultType; | |
3378 | ||
3379 | static int get_phys_addr_lpae(CPUARMState *env, uint32_t address, | |
3380 | int access_type, int is_user, | |
a8170e5e | 3381 | hwaddr *phys_ptr, int *prot, |
3dde962f PM |
3382 | target_ulong *page_size_ptr) |
3383 | { | |
70d74660 | 3384 | CPUState *cs = CPU(arm_env_get_cpu(env)); |
3dde962f PM |
3385 | /* Read an LPAE long-descriptor translation table. */ |
3386 | MMUFaultType fault_type = translation_fault; | |
3387 | uint32_t level = 1; | |
3388 | uint32_t epd; | |
3389 | uint32_t tsz; | |
3390 | uint64_t ttbr; | |
3391 | int ttbr_select; | |
3392 | int n; | |
a8170e5e | 3393 | hwaddr descaddr; |
3dde962f PM |
3394 | uint32_t tableattrs; |
3395 | target_ulong page_size; | |
3396 | uint32_t attrs; | |
3397 | ||
3398 | /* Determine whether this address is in the region controlled by | |
3399 | * TTBR0 or TTBR1 (or if it is in neither region and should fault). | |
3400 | * This is a Non-secure PL0/1 stage 1 translation, so controlled by | |
3401 | * TTBCR/TTBR0/TTBR1 in accordance with ARM ARM DDI0406C table B-32: | |
3402 | */ | |
3403 | uint32_t t0sz = extract32(env->cp15.c2_control, 0, 3); | |
3404 | uint32_t t1sz = extract32(env->cp15.c2_control, 16, 3); | |
3405 | if (t0sz && !extract32(address, 32 - t0sz, t0sz)) { | |
3406 | /* there is a ttbr0 region and we are in it (high bits all zero) */ | |
3407 | ttbr_select = 0; | |
3408 | } else if (t1sz && !extract32(~address, 32 - t1sz, t1sz)) { | |
3409 | /* there is a ttbr1 region and we are in it (high bits all one) */ | |
3410 | ttbr_select = 1; | |
3411 | } else if (!t0sz) { | |
3412 | /* ttbr0 region is "everything not in the ttbr1 region" */ | |
3413 | ttbr_select = 0; | |
3414 | } else if (!t1sz) { | |
3415 | /* ttbr1 region is "everything not in the ttbr0 region" */ | |
3416 | ttbr_select = 1; | |
3417 | } else { | |
3418 | /* in the gap between the two regions, this is a Translation fault */ | |
3419 | fault_type = translation_fault; | |
3420 | goto do_fault; | |
3421 | } | |
3422 | ||
3423 | /* Note that QEMU ignores shareability and cacheability attributes, | |
3424 | * so we don't need to do anything with the SH, ORGN, IRGN fields | |
3425 | * in the TTBCR. Similarly, TTBCR:A1 selects whether we get the | |
3426 | * ASID from TTBR0 or TTBR1, but QEMU's TLB doesn't currently | |
3427 | * implement any ASID-like capability so we can ignore it (instead | |
3428 | * we will always flush the TLB any time the ASID is changed). | |
3429 | */ | |
3430 | if (ttbr_select == 0) { | |
327ed10f | 3431 | ttbr = env->cp15.ttbr0_el1; |
3dde962f PM |
3432 | epd = extract32(env->cp15.c2_control, 7, 1); |
3433 | tsz = t0sz; | |
3434 | } else { | |
327ed10f | 3435 | ttbr = env->cp15.ttbr1_el1; |
3dde962f PM |
3436 | epd = extract32(env->cp15.c2_control, 23, 1); |
3437 | tsz = t1sz; | |
3438 | } | |
3439 | ||
3440 | if (epd) { | |
3441 | /* Translation table walk disabled => Translation fault on TLB miss */ | |
3442 | goto do_fault; | |
3443 | } | |
3444 | ||
3445 | /* If the region is small enough we will skip straight to a 2nd level | |
3446 | * lookup. This affects the number of bits of the address used in | |
3447 | * combination with the TTBR to find the first descriptor. ('n' here | |
3448 | * matches the usage in the ARM ARM sB3.6.6, where bits [39..n] are | |
3449 | * from the TTBR, [n-1..3] from the vaddr, and [2..0] always zero). | |
3450 | */ | |
3451 | if (tsz > 1) { | |
3452 | level = 2; | |
3453 | n = 14 - tsz; | |
3454 | } else { | |
3455 | n = 5 - tsz; | |
3456 | } | |
3457 | ||
3458 | /* Clear the vaddr bits which aren't part of the within-region address, | |
3459 | * so that we don't have to special case things when calculating the | |
3460 | * first descriptor address. | |
3461 | */ | |
3462 | address &= (0xffffffffU >> tsz); | |
3463 | ||
3464 | /* Now we can extract the actual base address from the TTBR */ | |
3465 | descaddr = extract64(ttbr, 0, 40); | |
3466 | descaddr &= ~((1ULL << n) - 1); | |
3467 | ||
3468 | tableattrs = 0; | |
3469 | for (;;) { | |
3470 | uint64_t descriptor; | |
3471 | ||
3472 | descaddr |= ((address >> (9 * (4 - level))) & 0xff8); | |
2c17449b | 3473 | descriptor = ldq_phys(cs->as, descaddr); |
3dde962f PM |
3474 | if (!(descriptor & 1) || |
3475 | (!(descriptor & 2) && (level == 3))) { | |
3476 | /* Invalid, or the Reserved level 3 encoding */ | |
3477 | goto do_fault; | |
3478 | } | |
3479 | descaddr = descriptor & 0xfffffff000ULL; | |
3480 | ||
3481 | if ((descriptor & 2) && (level < 3)) { | |
3482 | /* Table entry. The top five bits are attributes which may | |
3483 | * propagate down through lower levels of the table (and | |
3484 | * which are all arranged so that 0 means "no effect", so | |
3485 | * we can gather them up by ORing in the bits at each level). | |
3486 | */ | |
3487 | tableattrs |= extract64(descriptor, 59, 5); | |
3488 | level++; | |
3489 | continue; | |
3490 | } | |
3491 | /* Block entry at level 1 or 2, or page entry at level 3. | |
3492 | * These are basically the same thing, although the number | |
3493 | * of bits we pull in from the vaddr varies. | |
3494 | */ | |
3495 | page_size = (1 << (39 - (9 * level))); | |
3496 | descaddr |= (address & (page_size - 1)); | |
3497 | /* Extract attributes from the descriptor and merge with table attrs */ | |
3498 | attrs = extract64(descriptor, 2, 10) | |
3499 | | (extract64(descriptor, 52, 12) << 10); | |
3500 | attrs |= extract32(tableattrs, 0, 2) << 11; /* XN, PXN */ | |
3501 | attrs |= extract32(tableattrs, 3, 1) << 5; /* APTable[1] => AP[2] */ | |
3502 | /* The sense of AP[1] vs APTable[0] is reversed, as APTable[0] == 1 | |
3503 | * means "force PL1 access only", which means forcing AP[1] to 0. | |
3504 | */ | |
3505 | if (extract32(tableattrs, 2, 1)) { | |
3506 | attrs &= ~(1 << 4); | |
3507 | } | |
3508 | /* Since we're always in the Non-secure state, NSTable is ignored. */ | |
3509 | break; | |
3510 | } | |
3511 | /* Here descaddr is the final physical address, and attributes | |
3512 | * are all in attrs. | |
3513 | */ | |
3514 | fault_type = access_fault; | |
3515 | if ((attrs & (1 << 8)) == 0) { | |
3516 | /* Access flag */ | |
3517 | goto do_fault; | |
3518 | } | |
3519 | fault_type = permission_fault; | |
3520 | if (is_user && !(attrs & (1 << 4))) { | |
3521 | /* Unprivileged access not enabled */ | |
3522 | goto do_fault; | |
3523 | } | |
3524 | *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; | |
3525 | if (attrs & (1 << 12) || (!is_user && (attrs & (1 << 11)))) { | |
3526 | /* XN or PXN */ | |
3527 | if (access_type == 2) { | |
3528 | goto do_fault; | |
3529 | } | |
3530 | *prot &= ~PAGE_EXEC; | |
3531 | } | |
3532 | if (attrs & (1 << 5)) { | |
3533 | /* Write access forbidden */ | |
3534 | if (access_type == 1) { | |
3535 | goto do_fault; | |
3536 | } | |
3537 | *prot &= ~PAGE_WRITE; | |
3538 | } | |
3539 | ||
3540 | *phys_ptr = descaddr; | |
3541 | *page_size_ptr = page_size; | |
3542 | return 0; | |
3543 | ||
3544 | do_fault: | |
3545 | /* Long-descriptor format IFSR/DFSR value */ | |
3546 | return (1 << 9) | (fault_type << 2) | level; | |
3547 | } | |
3548 | ||
77a71dd1 PM |
3549 | static int get_phys_addr_mpu(CPUARMState *env, uint32_t address, |
3550 | int access_type, int is_user, | |
a8170e5e | 3551 | hwaddr *phys_ptr, int *prot) |
9ee6e8bb PB |
3552 | { |
3553 | int n; | |
3554 | uint32_t mask; | |
3555 | uint32_t base; | |
3556 | ||
3557 | *phys_ptr = address; | |
3558 | for (n = 7; n >= 0; n--) { | |
3559 | base = env->cp15.c6_region[n]; | |
3560 | if ((base & 1) == 0) | |
3561 | continue; | |
3562 | mask = 1 << ((base >> 1) & 0x1f); | |
3563 | /* Keep this shift separate from the above to avoid an | |
3564 | (undefined) << 32. */ | |
3565 | mask = (mask << 1) - 1; | |
3566 | if (((base ^ address) & ~mask) == 0) | |
3567 | break; | |
3568 | } | |
3569 | if (n < 0) | |
3570 | return 2; | |
3571 | ||
3572 | if (access_type == 2) { | |
3573 | mask = env->cp15.c5_insn; | |
3574 | } else { | |
3575 | mask = env->cp15.c5_data; | |
3576 | } | |
3577 | mask = (mask >> (n * 4)) & 0xf; | |
3578 | switch (mask) { | |
3579 | case 0: | |
3580 | return 1; | |
3581 | case 1: | |
3582 | if (is_user) | |
3583 | return 1; | |
3584 | *prot = PAGE_READ | PAGE_WRITE; | |
3585 | break; | |
3586 | case 2: | |
3587 | *prot = PAGE_READ; | |
3588 | if (!is_user) | |
3589 | *prot |= PAGE_WRITE; | |
3590 | break; | |
3591 | case 3: | |
3592 | *prot = PAGE_READ | PAGE_WRITE; | |
3593 | break; | |
3594 | case 5: | |
3595 | if (is_user) | |
3596 | return 1; | |
3597 | *prot = PAGE_READ; | |
3598 | break; | |
3599 | case 6: | |
3600 | *prot = PAGE_READ; | |
3601 | break; | |
3602 | default: | |
3603 | /* Bad permission. */ | |
3604 | return 1; | |
3605 | } | |
3ad493fc | 3606 | *prot |= PAGE_EXEC; |
9ee6e8bb PB |
3607 | return 0; |
3608 | } | |
3609 | ||
702a9357 PM |
3610 | /* get_phys_addr - get the physical address for this virtual address |
3611 | * | |
3612 | * Find the physical address corresponding to the given virtual address, | |
3613 | * by doing a translation table walk on MMU based systems or using the | |
3614 | * MPU state on MPU based systems. | |
3615 | * | |
3616 | * Returns 0 if the translation was successful. Otherwise, phys_ptr, | |
3617 | * prot and page_size are not filled in, and the return value provides | |
3618 | * information on why the translation aborted, in the format of a | |
3619 | * DFSR/IFSR fault register, with the following caveats: | |
3620 | * * we honour the short vs long DFSR format differences. | |
3621 | * * the WnR bit is never set (the caller must do this). | |
3622 | * * for MPU based systems we don't bother to return a full FSR format | |
3623 | * value. | |
3624 | * | |
3625 | * @env: CPUARMState | |
3626 | * @address: virtual address to get physical address for | |
3627 | * @access_type: 0 for read, 1 for write, 2 for execute | |
3628 | * @is_user: 0 for privileged access, 1 for user | |
3629 | * @phys_ptr: set to the physical address corresponding to the virtual address | |
3630 | * @prot: set to the permissions for the page containing phys_ptr | |
3631 | * @page_size: set to the size of the page containing phys_ptr | |
3632 | */ | |
0ecb72a5 | 3633 | static inline int get_phys_addr(CPUARMState *env, uint32_t address, |
9ee6e8bb | 3634 | int access_type, int is_user, |
a8170e5e | 3635 | hwaddr *phys_ptr, int *prot, |
d4c430a8 | 3636 | target_ulong *page_size) |
9ee6e8bb PB |
3637 | { |
3638 | /* Fast Context Switch Extension. */ | |
3639 | if (address < 0x02000000) | |
3640 | address += env->cp15.c13_fcse; | |
3641 | ||
76e3e1bc | 3642 | if ((env->cp15.c1_sys & SCTLR_M) == 0) { |
9ee6e8bb PB |
3643 | /* MMU/MPU disabled. */ |
3644 | *phys_ptr = address; | |
3ad493fc | 3645 | *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; |
d4c430a8 | 3646 | *page_size = TARGET_PAGE_SIZE; |
9ee6e8bb PB |
3647 | return 0; |
3648 | } else if (arm_feature(env, ARM_FEATURE_MPU)) { | |
d4c430a8 | 3649 | *page_size = TARGET_PAGE_SIZE; |
9ee6e8bb PB |
3650 | return get_phys_addr_mpu(env, address, access_type, is_user, phys_ptr, |
3651 | prot); | |
3dde962f PM |
3652 | } else if (extended_addresses_enabled(env)) { |
3653 | return get_phys_addr_lpae(env, address, access_type, is_user, phys_ptr, | |
3654 | prot, page_size); | |
76e3e1bc | 3655 | } else if (env->cp15.c1_sys & SCTLR_XP) { |
9ee6e8bb | 3656 | return get_phys_addr_v6(env, address, access_type, is_user, phys_ptr, |
d4c430a8 | 3657 | prot, page_size); |
9ee6e8bb PB |
3658 | } else { |
3659 | return get_phys_addr_v5(env, address, access_type, is_user, phys_ptr, | |
d4c430a8 | 3660 | prot, page_size); |
9ee6e8bb PB |
3661 | } |
3662 | } | |
3663 | ||
7510454e AF |
3664 | int arm_cpu_handle_mmu_fault(CPUState *cs, vaddr address, |
3665 | int access_type, int mmu_idx) | |
b5ff1b31 | 3666 | { |
7510454e AF |
3667 | ARMCPU *cpu = ARM_CPU(cs); |
3668 | CPUARMState *env = &cpu->env; | |
a8170e5e | 3669 | hwaddr phys_addr; |
d4c430a8 | 3670 | target_ulong page_size; |
b5ff1b31 | 3671 | int prot; |
6ebbf390 | 3672 | int ret, is_user; |
b5ff1b31 | 3673 | |
6ebbf390 | 3674 | is_user = mmu_idx == MMU_USER_IDX; |
d4c430a8 PB |
3675 | ret = get_phys_addr(env, address, access_type, is_user, &phys_addr, &prot, |
3676 | &page_size); | |
b5ff1b31 FB |
3677 | if (ret == 0) { |
3678 | /* Map a single [sub]page. */ | |
a8170e5e | 3679 | phys_addr &= ~(hwaddr)0x3ff; |
b5ff1b31 | 3680 | address &= ~(uint32_t)0x3ff; |
0c591eb0 | 3681 | tlb_set_page(cs, address, phys_addr, prot, mmu_idx, page_size); |
d4c430a8 | 3682 | return 0; |
b5ff1b31 FB |
3683 | } |
3684 | ||
3685 | if (access_type == 2) { | |
3686 | env->cp15.c5_insn = ret; | |
3687 | env->cp15.c6_insn = address; | |
27103424 | 3688 | cs->exception_index = EXCP_PREFETCH_ABORT; |
b5ff1b31 FB |
3689 | } else { |
3690 | env->cp15.c5_data = ret; | |
9ee6e8bb PB |
3691 | if (access_type == 1 && arm_feature(env, ARM_FEATURE_V6)) |
3692 | env->cp15.c5_data |= (1 << 11); | |
b5ff1b31 | 3693 | env->cp15.c6_data = address; |
27103424 | 3694 | cs->exception_index = EXCP_DATA_ABORT; |
b5ff1b31 FB |
3695 | } |
3696 | return 1; | |
3697 | } | |
3698 | ||
00b941e5 | 3699 | hwaddr arm_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) |
b5ff1b31 | 3700 | { |
00b941e5 | 3701 | ARMCPU *cpu = ARM_CPU(cs); |
a8170e5e | 3702 | hwaddr phys_addr; |
d4c430a8 | 3703 | target_ulong page_size; |
b5ff1b31 FB |
3704 | int prot; |
3705 | int ret; | |
3706 | ||
00b941e5 | 3707 | ret = get_phys_addr(&cpu->env, addr, 0, 0, &phys_addr, &prot, &page_size); |
b5ff1b31 | 3708 | |
00b941e5 | 3709 | if (ret != 0) { |
b5ff1b31 | 3710 | return -1; |
00b941e5 | 3711 | } |
b5ff1b31 FB |
3712 | |
3713 | return phys_addr; | |
3714 | } | |
3715 | ||
0ecb72a5 | 3716 | void HELPER(set_r13_banked)(CPUARMState *env, uint32_t mode, uint32_t val) |
9ee6e8bb | 3717 | { |
39ea3d4e PM |
3718 | if ((env->uncached_cpsr & CPSR_M) == mode) { |
3719 | env->regs[13] = val; | |
3720 | } else { | |
f5206413 | 3721 | env->banked_r13[bank_number(mode)] = val; |
39ea3d4e | 3722 | } |
9ee6e8bb PB |
3723 | } |
3724 | ||
0ecb72a5 | 3725 | uint32_t HELPER(get_r13_banked)(CPUARMState *env, uint32_t mode) |
9ee6e8bb | 3726 | { |
39ea3d4e PM |
3727 | if ((env->uncached_cpsr & CPSR_M) == mode) { |
3728 | return env->regs[13]; | |
3729 | } else { | |
f5206413 | 3730 | return env->banked_r13[bank_number(mode)]; |
39ea3d4e | 3731 | } |
9ee6e8bb PB |
3732 | } |
3733 | ||
0ecb72a5 | 3734 | uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg) |
9ee6e8bb | 3735 | { |
a47dddd7 AF |
3736 | ARMCPU *cpu = arm_env_get_cpu(env); |
3737 | ||
9ee6e8bb PB |
3738 | switch (reg) { |
3739 | case 0: /* APSR */ | |
3740 | return xpsr_read(env) & 0xf8000000; | |
3741 | case 1: /* IAPSR */ | |
3742 | return xpsr_read(env) & 0xf80001ff; | |
3743 | case 2: /* EAPSR */ | |
3744 | return xpsr_read(env) & 0xff00fc00; | |
3745 | case 3: /* xPSR */ | |
3746 | return xpsr_read(env) & 0xff00fdff; | |
3747 | case 5: /* IPSR */ | |
3748 | return xpsr_read(env) & 0x000001ff; | |
3749 | case 6: /* EPSR */ | |
3750 | return xpsr_read(env) & 0x0700fc00; | |
3751 | case 7: /* IEPSR */ | |
3752 | return xpsr_read(env) & 0x0700edff; | |
3753 | case 8: /* MSP */ | |
3754 | return env->v7m.current_sp ? env->v7m.other_sp : env->regs[13]; | |
3755 | case 9: /* PSP */ | |
3756 | return env->v7m.current_sp ? env->regs[13] : env->v7m.other_sp; | |
3757 | case 16: /* PRIMASK */ | |
4cc35614 | 3758 | return (env->daif & PSTATE_I) != 0; |
82845826 SH |
3759 | case 17: /* BASEPRI */ |
3760 | case 18: /* BASEPRI_MAX */ | |
9ee6e8bb | 3761 | return env->v7m.basepri; |
82845826 | 3762 | case 19: /* FAULTMASK */ |
4cc35614 | 3763 | return (env->daif & PSTATE_F) != 0; |
9ee6e8bb PB |
3764 | case 20: /* CONTROL */ |
3765 | return env->v7m.control; | |
3766 | default: | |
3767 | /* ??? For debugging only. */ | |
a47dddd7 | 3768 | cpu_abort(CPU(cpu), "Unimplemented system register read (%d)\n", reg); |
9ee6e8bb PB |
3769 | return 0; |
3770 | } | |
3771 | } | |
3772 | ||
0ecb72a5 | 3773 | void HELPER(v7m_msr)(CPUARMState *env, uint32_t reg, uint32_t val) |
9ee6e8bb | 3774 | { |
a47dddd7 AF |
3775 | ARMCPU *cpu = arm_env_get_cpu(env); |
3776 | ||
9ee6e8bb PB |
3777 | switch (reg) { |
3778 | case 0: /* APSR */ | |
3779 | xpsr_write(env, val, 0xf8000000); | |
3780 | break; | |
3781 | case 1: /* IAPSR */ | |
3782 | xpsr_write(env, val, 0xf8000000); | |
3783 | break; | |
3784 | case 2: /* EAPSR */ | |
3785 | xpsr_write(env, val, 0xfe00fc00); | |
3786 | break; | |
3787 | case 3: /* xPSR */ | |
3788 | xpsr_write(env, val, 0xfe00fc00); | |
3789 | break; | |
3790 | case 5: /* IPSR */ | |
3791 | /* IPSR bits are readonly. */ | |
3792 | break; | |
3793 | case 6: /* EPSR */ | |
3794 | xpsr_write(env, val, 0x0600fc00); | |
3795 | break; | |
3796 | case 7: /* IEPSR */ | |
3797 | xpsr_write(env, val, 0x0600fc00); | |
3798 | break; | |
3799 | case 8: /* MSP */ | |
3800 | if (env->v7m.current_sp) | |
3801 | env->v7m.other_sp = val; | |
3802 | else | |
3803 | env->regs[13] = val; | |
3804 | break; | |
3805 | case 9: /* PSP */ | |
3806 | if (env->v7m.current_sp) | |
3807 | env->regs[13] = val; | |
3808 | else | |
3809 | env->v7m.other_sp = val; | |
3810 | break; | |
3811 | case 16: /* PRIMASK */ | |
4cc35614 PM |
3812 | if (val & 1) { |
3813 | env->daif |= PSTATE_I; | |
3814 | } else { | |
3815 | env->daif &= ~PSTATE_I; | |
3816 | } | |
9ee6e8bb | 3817 | break; |
82845826 | 3818 | case 17: /* BASEPRI */ |
9ee6e8bb PB |
3819 | env->v7m.basepri = val & 0xff; |
3820 | break; | |
82845826 | 3821 | case 18: /* BASEPRI_MAX */ |
9ee6e8bb PB |
3822 | val &= 0xff; |
3823 | if (val != 0 && (val < env->v7m.basepri || env->v7m.basepri == 0)) | |
3824 | env->v7m.basepri = val; | |
3825 | break; | |
82845826 | 3826 | case 19: /* FAULTMASK */ |
4cc35614 PM |
3827 | if (val & 1) { |
3828 | env->daif |= PSTATE_F; | |
3829 | } else { | |
3830 | env->daif &= ~PSTATE_F; | |
3831 | } | |
82845826 | 3832 | break; |
9ee6e8bb PB |
3833 | case 20: /* CONTROL */ |
3834 | env->v7m.control = val & 3; | |
3835 | switch_v7m_sp(env, (val & 2) != 0); | |
3836 | break; | |
3837 | default: | |
3838 | /* ??? For debugging only. */ | |
a47dddd7 | 3839 | cpu_abort(CPU(cpu), "Unimplemented system register write (%d)\n", reg); |
9ee6e8bb PB |
3840 | return; |
3841 | } | |
3842 | } | |
3843 | ||
b5ff1b31 | 3844 | #endif |
6ddbc6e4 PB |
3845 | |
3846 | /* Note that signed overflow is undefined in C. The following routines are | |
3847 | careful to use unsigned types where modulo arithmetic is required. | |
3848 | Failure to do so _will_ break on newer gcc. */ | |
3849 | ||
3850 | /* Signed saturating arithmetic. */ | |
3851 | ||
1654b2d6 | 3852 | /* Perform 16-bit signed saturating addition. */ |
6ddbc6e4 PB |
3853 | static inline uint16_t add16_sat(uint16_t a, uint16_t b) |
3854 | { | |
3855 | uint16_t res; | |
3856 | ||
3857 | res = a + b; | |
3858 | if (((res ^ a) & 0x8000) && !((a ^ b) & 0x8000)) { | |
3859 | if (a & 0x8000) | |
3860 | res = 0x8000; | |
3861 | else | |
3862 | res = 0x7fff; | |
3863 | } | |
3864 | return res; | |
3865 | } | |
3866 | ||
1654b2d6 | 3867 | /* Perform 8-bit signed saturating addition. */ |
6ddbc6e4 PB |
3868 | static inline uint8_t add8_sat(uint8_t a, uint8_t b) |
3869 | { | |
3870 | uint8_t res; | |
3871 | ||
3872 | res = a + b; | |
3873 | if (((res ^ a) & 0x80) && !((a ^ b) & 0x80)) { | |
3874 | if (a & 0x80) | |
3875 | res = 0x80; | |
3876 | else | |
3877 | res = 0x7f; | |
3878 | } | |
3879 | return res; | |
3880 | } | |
3881 | ||
1654b2d6 | 3882 | /* Perform 16-bit signed saturating subtraction. */ |
6ddbc6e4 PB |
3883 | static inline uint16_t sub16_sat(uint16_t a, uint16_t b) |
3884 | { | |
3885 | uint16_t res; | |
3886 | ||
3887 | res = a - b; | |
3888 | if (((res ^ a) & 0x8000) && ((a ^ b) & 0x8000)) { | |
3889 | if (a & 0x8000) | |
3890 | res = 0x8000; | |
3891 | else | |
3892 | res = 0x7fff; | |
3893 | } | |
3894 | return res; | |
3895 | } | |
3896 | ||
1654b2d6 | 3897 | /* Perform 8-bit signed saturating subtraction. */ |
6ddbc6e4 PB |
3898 | static inline uint8_t sub8_sat(uint8_t a, uint8_t b) |
3899 | { | |
3900 | uint8_t res; | |
3901 | ||
3902 | res = a - b; | |
3903 | if (((res ^ a) & 0x80) && ((a ^ b) & 0x80)) { | |
3904 | if (a & 0x80) | |
3905 | res = 0x80; | |
3906 | else | |
3907 | res = 0x7f; | |
3908 | } | |
3909 | return res; | |
3910 | } | |
3911 | ||
3912 | #define ADD16(a, b, n) RESULT(add16_sat(a, b), n, 16); | |
3913 | #define SUB16(a, b, n) RESULT(sub16_sat(a, b), n, 16); | |
3914 | #define ADD8(a, b, n) RESULT(add8_sat(a, b), n, 8); | |
3915 | #define SUB8(a, b, n) RESULT(sub8_sat(a, b), n, 8); | |
3916 | #define PFX q | |
3917 | ||
3918 | #include "op_addsub.h" | |
3919 | ||
3920 | /* Unsigned saturating arithmetic. */ | |
460a09c1 | 3921 | static inline uint16_t add16_usat(uint16_t a, uint16_t b) |
6ddbc6e4 PB |
3922 | { |
3923 | uint16_t res; | |
3924 | res = a + b; | |
3925 | if (res < a) | |
3926 | res = 0xffff; | |
3927 | return res; | |
3928 | } | |
3929 | ||
460a09c1 | 3930 | static inline uint16_t sub16_usat(uint16_t a, uint16_t b) |
6ddbc6e4 | 3931 | { |
4c4fd3f8 | 3932 | if (a > b) |
6ddbc6e4 PB |
3933 | return a - b; |
3934 | else | |
3935 | return 0; | |
3936 | } | |
3937 | ||
3938 | static inline uint8_t add8_usat(uint8_t a, uint8_t b) | |
3939 | { | |
3940 | uint8_t res; | |
3941 | res = a + b; | |
3942 | if (res < a) | |
3943 | res = 0xff; | |
3944 | return res; | |
3945 | } | |
3946 | ||
3947 | static inline uint8_t sub8_usat(uint8_t a, uint8_t b) | |
3948 | { | |
4c4fd3f8 | 3949 | if (a > b) |
6ddbc6e4 PB |
3950 | return a - b; |
3951 | else | |
3952 | return 0; | |
3953 | } | |
3954 | ||
3955 | #define ADD16(a, b, n) RESULT(add16_usat(a, b), n, 16); | |
3956 | #define SUB16(a, b, n) RESULT(sub16_usat(a, b), n, 16); | |
3957 | #define ADD8(a, b, n) RESULT(add8_usat(a, b), n, 8); | |
3958 | #define SUB8(a, b, n) RESULT(sub8_usat(a, b), n, 8); | |
3959 | #define PFX uq | |
3960 | ||
3961 | #include "op_addsub.h" | |
3962 | ||
3963 | /* Signed modulo arithmetic. */ | |
3964 | #define SARITH16(a, b, n, op) do { \ | |
3965 | int32_t sum; \ | |
db6e2e65 | 3966 | sum = (int32_t)(int16_t)(a) op (int32_t)(int16_t)(b); \ |
6ddbc6e4 PB |
3967 | RESULT(sum, n, 16); \ |
3968 | if (sum >= 0) \ | |
3969 | ge |= 3 << (n * 2); \ | |
3970 | } while(0) | |
3971 | ||
3972 | #define SARITH8(a, b, n, op) do { \ | |
3973 | int32_t sum; \ | |
db6e2e65 | 3974 | sum = (int32_t)(int8_t)(a) op (int32_t)(int8_t)(b); \ |
6ddbc6e4 PB |
3975 | RESULT(sum, n, 8); \ |
3976 | if (sum >= 0) \ | |
3977 | ge |= 1 << n; \ | |
3978 | } while(0) | |
3979 | ||
3980 | ||
3981 | #define ADD16(a, b, n) SARITH16(a, b, n, +) | |
3982 | #define SUB16(a, b, n) SARITH16(a, b, n, -) | |
3983 | #define ADD8(a, b, n) SARITH8(a, b, n, +) | |
3984 | #define SUB8(a, b, n) SARITH8(a, b, n, -) | |
3985 | #define PFX s | |
3986 | #define ARITH_GE | |
3987 | ||
3988 | #include "op_addsub.h" | |
3989 | ||
3990 | /* Unsigned modulo arithmetic. */ | |
3991 | #define ADD16(a, b, n) do { \ | |
3992 | uint32_t sum; \ | |
3993 | sum = (uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b); \ | |
3994 | RESULT(sum, n, 16); \ | |
a87aa10b | 3995 | if ((sum >> 16) == 1) \ |
6ddbc6e4 PB |
3996 | ge |= 3 << (n * 2); \ |
3997 | } while(0) | |
3998 | ||
3999 | #define ADD8(a, b, n) do { \ | |
4000 | uint32_t sum; \ | |
4001 | sum = (uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b); \ | |
4002 | RESULT(sum, n, 8); \ | |
a87aa10b AZ |
4003 | if ((sum >> 8) == 1) \ |
4004 | ge |= 1 << n; \ | |
6ddbc6e4 PB |
4005 | } while(0) |
4006 | ||
4007 | #define SUB16(a, b, n) do { \ | |
4008 | uint32_t sum; \ | |
4009 | sum = (uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b); \ | |
4010 | RESULT(sum, n, 16); \ | |
4011 | if ((sum >> 16) == 0) \ | |
4012 | ge |= 3 << (n * 2); \ | |
4013 | } while(0) | |
4014 | ||
4015 | #define SUB8(a, b, n) do { \ | |
4016 | uint32_t sum; \ | |
4017 | sum = (uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b); \ | |
4018 | RESULT(sum, n, 8); \ | |
4019 | if ((sum >> 8) == 0) \ | |
a87aa10b | 4020 | ge |= 1 << n; \ |
6ddbc6e4 PB |
4021 | } while(0) |
4022 | ||
4023 | #define PFX u | |
4024 | #define ARITH_GE | |
4025 | ||
4026 | #include "op_addsub.h" | |
4027 | ||
4028 | /* Halved signed arithmetic. */ | |
4029 | #define ADD16(a, b, n) \ | |
4030 | RESULT(((int32_t)(int16_t)(a) + (int32_t)(int16_t)(b)) >> 1, n, 16) | |
4031 | #define SUB16(a, b, n) \ | |
4032 | RESULT(((int32_t)(int16_t)(a) - (int32_t)(int16_t)(b)) >> 1, n, 16) | |
4033 | #define ADD8(a, b, n) \ | |
4034 | RESULT(((int32_t)(int8_t)(a) + (int32_t)(int8_t)(b)) >> 1, n, 8) | |
4035 | #define SUB8(a, b, n) \ | |
4036 | RESULT(((int32_t)(int8_t)(a) - (int32_t)(int8_t)(b)) >> 1, n, 8) | |
4037 | #define PFX sh | |
4038 | ||
4039 | #include "op_addsub.h" | |
4040 | ||
4041 | /* Halved unsigned arithmetic. */ | |
4042 | #define ADD16(a, b, n) \ | |
4043 | RESULT(((uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b)) >> 1, n, 16) | |
4044 | #define SUB16(a, b, n) \ | |
4045 | RESULT(((uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b)) >> 1, n, 16) | |
4046 | #define ADD8(a, b, n) \ | |
4047 | RESULT(((uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b)) >> 1, n, 8) | |
4048 | #define SUB8(a, b, n) \ | |
4049 | RESULT(((uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b)) >> 1, n, 8) | |
4050 | #define PFX uh | |
4051 | ||
4052 | #include "op_addsub.h" | |
4053 | ||
4054 | static inline uint8_t do_usad(uint8_t a, uint8_t b) | |
4055 | { | |
4056 | if (a > b) | |
4057 | return a - b; | |
4058 | else | |
4059 | return b - a; | |
4060 | } | |
4061 | ||
4062 | /* Unsigned sum of absolute byte differences. */ | |
4063 | uint32_t HELPER(usad8)(uint32_t a, uint32_t b) | |
4064 | { | |
4065 | uint32_t sum; | |
4066 | sum = do_usad(a, b); | |
4067 | sum += do_usad(a >> 8, b >> 8); | |
4068 | sum += do_usad(a >> 16, b >>16); | |
4069 | sum += do_usad(a >> 24, b >> 24); | |
4070 | return sum; | |
4071 | } | |
4072 | ||
4073 | /* For ARMv6 SEL instruction. */ | |
4074 | uint32_t HELPER(sel_flags)(uint32_t flags, uint32_t a, uint32_t b) | |
4075 | { | |
4076 | uint32_t mask; | |
4077 | ||
4078 | mask = 0; | |
4079 | if (flags & 1) | |
4080 | mask |= 0xff; | |
4081 | if (flags & 2) | |
4082 | mask |= 0xff00; | |
4083 | if (flags & 4) | |
4084 | mask |= 0xff0000; | |
4085 | if (flags & 8) | |
4086 | mask |= 0xff000000; | |
4087 | return (a & mask) | (b & ~mask); | |
4088 | } | |
4089 | ||
b90372ad PM |
4090 | /* VFP support. We follow the convention used for VFP instructions: |
4091 | Single precision routines have a "s" suffix, double precision a | |
4373f3ce PB |
4092 | "d" suffix. */ |
4093 | ||
4094 | /* Convert host exception flags to vfp form. */ | |
4095 | static inline int vfp_exceptbits_from_host(int host_bits) | |
4096 | { | |
4097 | int target_bits = 0; | |
4098 | ||
4099 | if (host_bits & float_flag_invalid) | |
4100 | target_bits |= 1; | |
4101 | if (host_bits & float_flag_divbyzero) | |
4102 | target_bits |= 2; | |
4103 | if (host_bits & float_flag_overflow) | |
4104 | target_bits |= 4; | |
36802b6b | 4105 | if (host_bits & (float_flag_underflow | float_flag_output_denormal)) |
4373f3ce PB |
4106 | target_bits |= 8; |
4107 | if (host_bits & float_flag_inexact) | |
4108 | target_bits |= 0x10; | |
cecd8504 PM |
4109 | if (host_bits & float_flag_input_denormal) |
4110 | target_bits |= 0x80; | |
4373f3ce PB |
4111 | return target_bits; |
4112 | } | |
4113 | ||
0ecb72a5 | 4114 | uint32_t HELPER(vfp_get_fpscr)(CPUARMState *env) |
4373f3ce PB |
4115 | { |
4116 | int i; | |
4117 | uint32_t fpscr; | |
4118 | ||
4119 | fpscr = (env->vfp.xregs[ARM_VFP_FPSCR] & 0xffc8ffff) | |
4120 | | (env->vfp.vec_len << 16) | |
4121 | | (env->vfp.vec_stride << 20); | |
4122 | i = get_float_exception_flags(&env->vfp.fp_status); | |
3a492f3a | 4123 | i |= get_float_exception_flags(&env->vfp.standard_fp_status); |
4373f3ce PB |
4124 | fpscr |= vfp_exceptbits_from_host(i); |
4125 | return fpscr; | |
4126 | } | |
4127 | ||
0ecb72a5 | 4128 | uint32_t vfp_get_fpscr(CPUARMState *env) |
01653295 PM |
4129 | { |
4130 | return HELPER(vfp_get_fpscr)(env); | |
4131 | } | |
4132 | ||
4373f3ce PB |
4133 | /* Convert vfp exception flags to target form. */ |
4134 | static inline int vfp_exceptbits_to_host(int target_bits) | |
4135 | { | |
4136 | int host_bits = 0; | |
4137 | ||
4138 | if (target_bits & 1) | |
4139 | host_bits |= float_flag_invalid; | |
4140 | if (target_bits & 2) | |
4141 | host_bits |= float_flag_divbyzero; | |
4142 | if (target_bits & 4) | |
4143 | host_bits |= float_flag_overflow; | |
4144 | if (target_bits & 8) | |
4145 | host_bits |= float_flag_underflow; | |
4146 | if (target_bits & 0x10) | |
4147 | host_bits |= float_flag_inexact; | |
cecd8504 PM |
4148 | if (target_bits & 0x80) |
4149 | host_bits |= float_flag_input_denormal; | |
4373f3ce PB |
4150 | return host_bits; |
4151 | } | |
4152 | ||
0ecb72a5 | 4153 | void HELPER(vfp_set_fpscr)(CPUARMState *env, uint32_t val) |
4373f3ce PB |
4154 | { |
4155 | int i; | |
4156 | uint32_t changed; | |
4157 | ||
4158 | changed = env->vfp.xregs[ARM_VFP_FPSCR]; | |
4159 | env->vfp.xregs[ARM_VFP_FPSCR] = (val & 0xffc8ffff); | |
4160 | env->vfp.vec_len = (val >> 16) & 7; | |
4161 | env->vfp.vec_stride = (val >> 20) & 3; | |
4162 | ||
4163 | changed ^= val; | |
4164 | if (changed & (3 << 22)) { | |
4165 | i = (val >> 22) & 3; | |
4166 | switch (i) { | |
4d3da0f3 | 4167 | case FPROUNDING_TIEEVEN: |
4373f3ce PB |
4168 | i = float_round_nearest_even; |
4169 | break; | |
4d3da0f3 | 4170 | case FPROUNDING_POSINF: |
4373f3ce PB |
4171 | i = float_round_up; |
4172 | break; | |
4d3da0f3 | 4173 | case FPROUNDING_NEGINF: |
4373f3ce PB |
4174 | i = float_round_down; |
4175 | break; | |
4d3da0f3 | 4176 | case FPROUNDING_ZERO: |
4373f3ce PB |
4177 | i = float_round_to_zero; |
4178 | break; | |
4179 | } | |
4180 | set_float_rounding_mode(i, &env->vfp.fp_status); | |
4181 | } | |
cecd8504 | 4182 | if (changed & (1 << 24)) { |
fe76d976 | 4183 | set_flush_to_zero((val & (1 << 24)) != 0, &env->vfp.fp_status); |
cecd8504 PM |
4184 | set_flush_inputs_to_zero((val & (1 << 24)) != 0, &env->vfp.fp_status); |
4185 | } | |
5c7908ed PB |
4186 | if (changed & (1 << 25)) |
4187 | set_default_nan_mode((val & (1 << 25)) != 0, &env->vfp.fp_status); | |
4373f3ce | 4188 | |
b12c390b | 4189 | i = vfp_exceptbits_to_host(val); |
4373f3ce | 4190 | set_float_exception_flags(i, &env->vfp.fp_status); |
3a492f3a | 4191 | set_float_exception_flags(0, &env->vfp.standard_fp_status); |
4373f3ce PB |
4192 | } |
4193 | ||
0ecb72a5 | 4194 | void vfp_set_fpscr(CPUARMState *env, uint32_t val) |
01653295 PM |
4195 | { |
4196 | HELPER(vfp_set_fpscr)(env, val); | |
4197 | } | |
4198 | ||
4373f3ce PB |
4199 | #define VFP_HELPER(name, p) HELPER(glue(glue(vfp_,name),p)) |
4200 | ||
4201 | #define VFP_BINOP(name) \ | |
ae1857ec | 4202 | float32 VFP_HELPER(name, s)(float32 a, float32 b, void *fpstp) \ |
4373f3ce | 4203 | { \ |
ae1857ec PM |
4204 | float_status *fpst = fpstp; \ |
4205 | return float32_ ## name(a, b, fpst); \ | |
4373f3ce | 4206 | } \ |
ae1857ec | 4207 | float64 VFP_HELPER(name, d)(float64 a, float64 b, void *fpstp) \ |
4373f3ce | 4208 | { \ |
ae1857ec PM |
4209 | float_status *fpst = fpstp; \ |
4210 | return float64_ ## name(a, b, fpst); \ | |
4373f3ce PB |
4211 | } |
4212 | VFP_BINOP(add) | |
4213 | VFP_BINOP(sub) | |
4214 | VFP_BINOP(mul) | |
4215 | VFP_BINOP(div) | |
f71a2ae5 PM |
4216 | VFP_BINOP(min) |
4217 | VFP_BINOP(max) | |
4218 | VFP_BINOP(minnum) | |
4219 | VFP_BINOP(maxnum) | |
4373f3ce PB |
4220 | #undef VFP_BINOP |
4221 | ||
4222 | float32 VFP_HELPER(neg, s)(float32 a) | |
4223 | { | |
4224 | return float32_chs(a); | |
4225 | } | |
4226 | ||
4227 | float64 VFP_HELPER(neg, d)(float64 a) | |
4228 | { | |
66230e0d | 4229 | return float64_chs(a); |
4373f3ce PB |
4230 | } |
4231 | ||
4232 | float32 VFP_HELPER(abs, s)(float32 a) | |
4233 | { | |
4234 | return float32_abs(a); | |
4235 | } | |
4236 | ||
4237 | float64 VFP_HELPER(abs, d)(float64 a) | |
4238 | { | |
66230e0d | 4239 | return float64_abs(a); |
4373f3ce PB |
4240 | } |
4241 | ||
0ecb72a5 | 4242 | float32 VFP_HELPER(sqrt, s)(float32 a, CPUARMState *env) |
4373f3ce PB |
4243 | { |
4244 | return float32_sqrt(a, &env->vfp.fp_status); | |
4245 | } | |
4246 | ||
0ecb72a5 | 4247 | float64 VFP_HELPER(sqrt, d)(float64 a, CPUARMState *env) |
4373f3ce PB |
4248 | { |
4249 | return float64_sqrt(a, &env->vfp.fp_status); | |
4250 | } | |
4251 | ||
4252 | /* XXX: check quiet/signaling case */ | |
4253 | #define DO_VFP_cmp(p, type) \ | |
0ecb72a5 | 4254 | void VFP_HELPER(cmp, p)(type a, type b, CPUARMState *env) \ |
4373f3ce PB |
4255 | { \ |
4256 | uint32_t flags; \ | |
4257 | switch(type ## _compare_quiet(a, b, &env->vfp.fp_status)) { \ | |
4258 | case 0: flags = 0x6; break; \ | |
4259 | case -1: flags = 0x8; break; \ | |
4260 | case 1: flags = 0x2; break; \ | |
4261 | default: case 2: flags = 0x3; break; \ | |
4262 | } \ | |
4263 | env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \ | |
4264 | | (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \ | |
4265 | } \ | |
0ecb72a5 | 4266 | void VFP_HELPER(cmpe, p)(type a, type b, CPUARMState *env) \ |
4373f3ce PB |
4267 | { \ |
4268 | uint32_t flags; \ | |
4269 | switch(type ## _compare(a, b, &env->vfp.fp_status)) { \ | |
4270 | case 0: flags = 0x6; break; \ | |
4271 | case -1: flags = 0x8; break; \ | |
4272 | case 1: flags = 0x2; break; \ | |
4273 | default: case 2: flags = 0x3; break; \ | |
4274 | } \ | |
4275 | env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \ | |
4276 | | (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \ | |
4277 | } | |
4278 | DO_VFP_cmp(s, float32) | |
4279 | DO_VFP_cmp(d, float64) | |
4280 | #undef DO_VFP_cmp | |
4281 | ||
5500b06c | 4282 | /* Integer to float and float to integer conversions */ |
4373f3ce | 4283 | |
5500b06c PM |
4284 | #define CONV_ITOF(name, fsz, sign) \ |
4285 | float##fsz HELPER(name)(uint32_t x, void *fpstp) \ | |
4286 | { \ | |
4287 | float_status *fpst = fpstp; \ | |
85836979 | 4288 | return sign##int32_to_##float##fsz((sign##int32_t)x, fpst); \ |
4373f3ce PB |
4289 | } |
4290 | ||
5500b06c PM |
4291 | #define CONV_FTOI(name, fsz, sign, round) \ |
4292 | uint32_t HELPER(name)(float##fsz x, void *fpstp) \ | |
4293 | { \ | |
4294 | float_status *fpst = fpstp; \ | |
4295 | if (float##fsz##_is_any_nan(x)) { \ | |
4296 | float_raise(float_flag_invalid, fpst); \ | |
4297 | return 0; \ | |
4298 | } \ | |
4299 | return float##fsz##_to_##sign##int32##round(x, fpst); \ | |
4373f3ce PB |
4300 | } |
4301 | ||
5500b06c PM |
4302 | #define FLOAT_CONVS(name, p, fsz, sign) \ |
4303 | CONV_ITOF(vfp_##name##to##p, fsz, sign) \ | |
4304 | CONV_FTOI(vfp_to##name##p, fsz, sign, ) \ | |
4305 | CONV_FTOI(vfp_to##name##z##p, fsz, sign, _round_to_zero) | |
4373f3ce | 4306 | |
5500b06c PM |
4307 | FLOAT_CONVS(si, s, 32, ) |
4308 | FLOAT_CONVS(si, d, 64, ) | |
4309 | FLOAT_CONVS(ui, s, 32, u) | |
4310 | FLOAT_CONVS(ui, d, 64, u) | |
4373f3ce | 4311 | |
5500b06c PM |
4312 | #undef CONV_ITOF |
4313 | #undef CONV_FTOI | |
4314 | #undef FLOAT_CONVS | |
4373f3ce PB |
4315 | |
4316 | /* floating point conversion */ | |
0ecb72a5 | 4317 | float64 VFP_HELPER(fcvtd, s)(float32 x, CPUARMState *env) |
4373f3ce | 4318 | { |
2d627737 PM |
4319 | float64 r = float32_to_float64(x, &env->vfp.fp_status); |
4320 | /* ARM requires that S<->D conversion of any kind of NaN generates | |
4321 | * a quiet NaN by forcing the most significant frac bit to 1. | |
4322 | */ | |
4323 | return float64_maybe_silence_nan(r); | |
4373f3ce PB |
4324 | } |
4325 | ||
0ecb72a5 | 4326 | float32 VFP_HELPER(fcvts, d)(float64 x, CPUARMState *env) |
4373f3ce | 4327 | { |
2d627737 PM |
4328 | float32 r = float64_to_float32(x, &env->vfp.fp_status); |
4329 | /* ARM requires that S<->D conversion of any kind of NaN generates | |
4330 | * a quiet NaN by forcing the most significant frac bit to 1. | |
4331 | */ | |
4332 | return float32_maybe_silence_nan(r); | |
4373f3ce PB |
4333 | } |
4334 | ||
4335 | /* VFP3 fixed point conversion. */ | |
16d5b3ca | 4336 | #define VFP_CONV_FIX_FLOAT(name, p, fsz, isz, itype) \ |
8ed697e8 WN |
4337 | float##fsz HELPER(vfp_##name##to##p)(uint##isz##_t x, uint32_t shift, \ |
4338 | void *fpstp) \ | |
4373f3ce | 4339 | { \ |
5500b06c | 4340 | float_status *fpst = fpstp; \ |
622465e1 | 4341 | float##fsz tmp; \ |
8ed697e8 | 4342 | tmp = itype##_to_##float##fsz(x, fpst); \ |
5500b06c | 4343 | return float##fsz##_scalbn(tmp, -(int)shift, fpst); \ |
16d5b3ca WN |
4344 | } |
4345 | ||
abe66f70 PM |
4346 | /* Notice that we want only input-denormal exception flags from the |
4347 | * scalbn operation: the other possible flags (overflow+inexact if | |
4348 | * we overflow to infinity, output-denormal) aren't correct for the | |
4349 | * complete scale-and-convert operation. | |
4350 | */ | |
16d5b3ca WN |
4351 | #define VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, round) \ |
4352 | uint##isz##_t HELPER(vfp_to##name##p##round)(float##fsz x, \ | |
4353 | uint32_t shift, \ | |
4354 | void *fpstp) \ | |
4373f3ce | 4355 | { \ |
5500b06c | 4356 | float_status *fpst = fpstp; \ |
abe66f70 | 4357 | int old_exc_flags = get_float_exception_flags(fpst); \ |
622465e1 PM |
4358 | float##fsz tmp; \ |
4359 | if (float##fsz##_is_any_nan(x)) { \ | |
5500b06c | 4360 | float_raise(float_flag_invalid, fpst); \ |
622465e1 | 4361 | return 0; \ |
09d9487f | 4362 | } \ |
5500b06c | 4363 | tmp = float##fsz##_scalbn(x, shift, fpst); \ |
abe66f70 PM |
4364 | old_exc_flags |= get_float_exception_flags(fpst) \ |
4365 | & float_flag_input_denormal; \ | |
4366 | set_float_exception_flags(old_exc_flags, fpst); \ | |
16d5b3ca | 4367 | return float##fsz##_to_##itype##round(tmp, fpst); \ |
622465e1 PM |
4368 | } |
4369 | ||
16d5b3ca WN |
4370 | #define VFP_CONV_FIX(name, p, fsz, isz, itype) \ |
4371 | VFP_CONV_FIX_FLOAT(name, p, fsz, isz, itype) \ | |
3c6a074a WN |
4372 | VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, _round_to_zero) \ |
4373 | VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, ) | |
4374 | ||
4375 | #define VFP_CONV_FIX_A64(name, p, fsz, isz, itype) \ | |
4376 | VFP_CONV_FIX_FLOAT(name, p, fsz, isz, itype) \ | |
4377 | VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, ) | |
16d5b3ca | 4378 | |
8ed697e8 WN |
4379 | VFP_CONV_FIX(sh, d, 64, 64, int16) |
4380 | VFP_CONV_FIX(sl, d, 64, 64, int32) | |
3c6a074a | 4381 | VFP_CONV_FIX_A64(sq, d, 64, 64, int64) |
8ed697e8 WN |
4382 | VFP_CONV_FIX(uh, d, 64, 64, uint16) |
4383 | VFP_CONV_FIX(ul, d, 64, 64, uint32) | |
3c6a074a | 4384 | VFP_CONV_FIX_A64(uq, d, 64, 64, uint64) |
8ed697e8 WN |
4385 | VFP_CONV_FIX(sh, s, 32, 32, int16) |
4386 | VFP_CONV_FIX(sl, s, 32, 32, int32) | |
3c6a074a | 4387 | VFP_CONV_FIX_A64(sq, s, 32, 64, int64) |
8ed697e8 WN |
4388 | VFP_CONV_FIX(uh, s, 32, 32, uint16) |
4389 | VFP_CONV_FIX(ul, s, 32, 32, uint32) | |
3c6a074a | 4390 | VFP_CONV_FIX_A64(uq, s, 32, 64, uint64) |
4373f3ce | 4391 | #undef VFP_CONV_FIX |
16d5b3ca WN |
4392 | #undef VFP_CONV_FIX_FLOAT |
4393 | #undef VFP_CONV_FLOAT_FIX_ROUND | |
4373f3ce | 4394 | |
52a1f6a3 AG |
4395 | /* Set the current fp rounding mode and return the old one. |
4396 | * The argument is a softfloat float_round_ value. | |
4397 | */ | |
4398 | uint32_t HELPER(set_rmode)(uint32_t rmode, CPUARMState *env) | |
4399 | { | |
4400 | float_status *fp_status = &env->vfp.fp_status; | |
4401 | ||
4402 | uint32_t prev_rmode = get_float_rounding_mode(fp_status); | |
4403 | set_float_rounding_mode(rmode, fp_status); | |
4404 | ||
4405 | return prev_rmode; | |
4406 | } | |
4407 | ||
43630e58 WN |
4408 | /* Set the current fp rounding mode in the standard fp status and return |
4409 | * the old one. This is for NEON instructions that need to change the | |
4410 | * rounding mode but wish to use the standard FPSCR values for everything | |
4411 | * else. Always set the rounding mode back to the correct value after | |
4412 | * modifying it. | |
4413 | * The argument is a softfloat float_round_ value. | |
4414 | */ | |
4415 | uint32_t HELPER(set_neon_rmode)(uint32_t rmode, CPUARMState *env) | |
4416 | { | |
4417 | float_status *fp_status = &env->vfp.standard_fp_status; | |
4418 | ||
4419 | uint32_t prev_rmode = get_float_rounding_mode(fp_status); | |
4420 | set_float_rounding_mode(rmode, fp_status); | |
4421 | ||
4422 | return prev_rmode; | |
4423 | } | |
4424 | ||
60011498 | 4425 | /* Half precision conversions. */ |
0ecb72a5 | 4426 | static float32 do_fcvt_f16_to_f32(uint32_t a, CPUARMState *env, float_status *s) |
60011498 | 4427 | { |
60011498 | 4428 | int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0; |
fb91678d PM |
4429 | float32 r = float16_to_float32(make_float16(a), ieee, s); |
4430 | if (ieee) { | |
4431 | return float32_maybe_silence_nan(r); | |
4432 | } | |
4433 | return r; | |
60011498 PB |
4434 | } |
4435 | ||
0ecb72a5 | 4436 | static uint32_t do_fcvt_f32_to_f16(float32 a, CPUARMState *env, float_status *s) |
60011498 | 4437 | { |
60011498 | 4438 | int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0; |
fb91678d PM |
4439 | float16 r = float32_to_float16(a, ieee, s); |
4440 | if (ieee) { | |
4441 | r = float16_maybe_silence_nan(r); | |
4442 | } | |
4443 | return float16_val(r); | |
60011498 PB |
4444 | } |
4445 | ||
0ecb72a5 | 4446 | float32 HELPER(neon_fcvt_f16_to_f32)(uint32_t a, CPUARMState *env) |
2d981da7 PM |
4447 | { |
4448 | return do_fcvt_f16_to_f32(a, env, &env->vfp.standard_fp_status); | |
4449 | } | |
4450 | ||
0ecb72a5 | 4451 | uint32_t HELPER(neon_fcvt_f32_to_f16)(float32 a, CPUARMState *env) |
2d981da7 PM |
4452 | { |
4453 | return do_fcvt_f32_to_f16(a, env, &env->vfp.standard_fp_status); | |
4454 | } | |
4455 | ||
0ecb72a5 | 4456 | float32 HELPER(vfp_fcvt_f16_to_f32)(uint32_t a, CPUARMState *env) |
2d981da7 PM |
4457 | { |
4458 | return do_fcvt_f16_to_f32(a, env, &env->vfp.fp_status); | |
4459 | } | |
4460 | ||
0ecb72a5 | 4461 | uint32_t HELPER(vfp_fcvt_f32_to_f16)(float32 a, CPUARMState *env) |
2d981da7 PM |
4462 | { |
4463 | return do_fcvt_f32_to_f16(a, env, &env->vfp.fp_status); | |
4464 | } | |
4465 | ||
8900aad2 PM |
4466 | float64 HELPER(vfp_fcvt_f16_to_f64)(uint32_t a, CPUARMState *env) |
4467 | { | |
4468 | int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0; | |
4469 | float64 r = float16_to_float64(make_float16(a), ieee, &env->vfp.fp_status); | |
4470 | if (ieee) { | |
4471 | return float64_maybe_silence_nan(r); | |
4472 | } | |
4473 | return r; | |
4474 | } | |
4475 | ||
4476 | uint32_t HELPER(vfp_fcvt_f64_to_f16)(float64 a, CPUARMState *env) | |
4477 | { | |
4478 | int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0; | |
4479 | float16 r = float64_to_float16(a, ieee, &env->vfp.fp_status); | |
4480 | if (ieee) { | |
4481 | r = float16_maybe_silence_nan(r); | |
4482 | } | |
4483 | return float16_val(r); | |
4484 | } | |
4485 | ||
dda3ec49 | 4486 | #define float32_two make_float32(0x40000000) |
6aae3df1 PM |
4487 | #define float32_three make_float32(0x40400000) |
4488 | #define float32_one_point_five make_float32(0x3fc00000) | |
dda3ec49 | 4489 | |
0ecb72a5 | 4490 | float32 HELPER(recps_f32)(float32 a, float32 b, CPUARMState *env) |
4373f3ce | 4491 | { |
dda3ec49 PM |
4492 | float_status *s = &env->vfp.standard_fp_status; |
4493 | if ((float32_is_infinity(a) && float32_is_zero_or_denormal(b)) || | |
4494 | (float32_is_infinity(b) && float32_is_zero_or_denormal(a))) { | |
43fe9bdb PM |
4495 | if (!(float32_is_zero(a) || float32_is_zero(b))) { |
4496 | float_raise(float_flag_input_denormal, s); | |
4497 | } | |
dda3ec49 PM |
4498 | return float32_two; |
4499 | } | |
4500 | return float32_sub(float32_two, float32_mul(a, b, s), s); | |
4373f3ce PB |
4501 | } |
4502 | ||
0ecb72a5 | 4503 | float32 HELPER(rsqrts_f32)(float32 a, float32 b, CPUARMState *env) |
4373f3ce | 4504 | { |
71826966 | 4505 | float_status *s = &env->vfp.standard_fp_status; |
9ea62f57 PM |
4506 | float32 product; |
4507 | if ((float32_is_infinity(a) && float32_is_zero_or_denormal(b)) || | |
4508 | (float32_is_infinity(b) && float32_is_zero_or_denormal(a))) { | |
43fe9bdb PM |
4509 | if (!(float32_is_zero(a) || float32_is_zero(b))) { |
4510 | float_raise(float_flag_input_denormal, s); | |
4511 | } | |
6aae3df1 | 4512 | return float32_one_point_five; |
9ea62f57 | 4513 | } |
6aae3df1 PM |
4514 | product = float32_mul(a, b, s); |
4515 | return float32_div(float32_sub(float32_three, product, s), float32_two, s); | |
4373f3ce PB |
4516 | } |
4517 | ||
8f8e3aa4 PB |
4518 | /* NEON helpers. */ |
4519 | ||
56bf4fe2 CL |
4520 | /* Constants 256 and 512 are used in some helpers; we avoid relying on |
4521 | * int->float conversions at run-time. */ | |
4522 | #define float64_256 make_float64(0x4070000000000000LL) | |
4523 | #define float64_512 make_float64(0x4080000000000000LL) | |
b6d4443a AB |
4524 | #define float32_maxnorm make_float32(0x7f7fffff) |
4525 | #define float64_maxnorm make_float64(0x7fefffffffffffffLL) | |
56bf4fe2 | 4526 | |
b6d4443a AB |
4527 | /* Reciprocal functions |
4528 | * | |
4529 | * The algorithm that must be used to calculate the estimate | |
4530 | * is specified by the ARM ARM, see FPRecipEstimate() | |
fe0e4872 | 4531 | */ |
b6d4443a AB |
4532 | |
4533 | static float64 recip_estimate(float64 a, float_status *real_fp_status) | |
fe0e4872 | 4534 | { |
1146a817 PM |
4535 | /* These calculations mustn't set any fp exception flags, |
4536 | * so we use a local copy of the fp_status. | |
4537 | */ | |
b6d4443a | 4538 | float_status dummy_status = *real_fp_status; |
1146a817 | 4539 | float_status *s = &dummy_status; |
fe0e4872 CL |
4540 | /* q = (int)(a * 512.0) */ |
4541 | float64 q = float64_mul(float64_512, a, s); | |
4542 | int64_t q_int = float64_to_int64_round_to_zero(q, s); | |
4543 | ||
4544 | /* r = 1.0 / (((double)q + 0.5) / 512.0) */ | |
4545 | q = int64_to_float64(q_int, s); | |
4546 | q = float64_add(q, float64_half, s); | |
4547 | q = float64_div(q, float64_512, s); | |
4548 | q = float64_div(float64_one, q, s); | |
4549 | ||
4550 | /* s = (int)(256.0 * r + 0.5) */ | |
4551 | q = float64_mul(q, float64_256, s); | |
4552 | q = float64_add(q, float64_half, s); | |
4553 | q_int = float64_to_int64_round_to_zero(q, s); | |
4554 | ||
4555 | /* return (double)s / 256.0 */ | |
4556 | return float64_div(int64_to_float64(q_int, s), float64_256, s); | |
4557 | } | |
4558 | ||
b6d4443a AB |
4559 | /* Common wrapper to call recip_estimate */ |
4560 | static float64 call_recip_estimate(float64 num, int off, float_status *fpst) | |
4373f3ce | 4561 | { |
b6d4443a AB |
4562 | uint64_t val64 = float64_val(num); |
4563 | uint64_t frac = extract64(val64, 0, 52); | |
4564 | int64_t exp = extract64(val64, 52, 11); | |
4565 | uint64_t sbit; | |
4566 | float64 scaled, estimate; | |
fe0e4872 | 4567 | |
b6d4443a AB |
4568 | /* Generate the scaled number for the estimate function */ |
4569 | if (exp == 0) { | |
4570 | if (extract64(frac, 51, 1) == 0) { | |
4571 | exp = -1; | |
4572 | frac = extract64(frac, 0, 50) << 2; | |
4573 | } else { | |
4574 | frac = extract64(frac, 0, 51) << 1; | |
4575 | } | |
4576 | } | |
fe0e4872 | 4577 | |
b6d4443a AB |
4578 | /* scaled = '0' : '01111111110' : fraction<51:44> : Zeros(44); */ |
4579 | scaled = make_float64((0x3feULL << 52) | |
4580 | | extract64(frac, 44, 8) << 44); | |
4581 | ||
4582 | estimate = recip_estimate(scaled, fpst); | |
4583 | ||
4584 | /* Build new result */ | |
4585 | val64 = float64_val(estimate); | |
4586 | sbit = 0x8000000000000000ULL & val64; | |
4587 | exp = off - exp; | |
4588 | frac = extract64(val64, 0, 52); | |
4589 | ||
4590 | if (exp == 0) { | |
4591 | frac = 1ULL << 51 | extract64(frac, 1, 51); | |
4592 | } else if (exp == -1) { | |
4593 | frac = 1ULL << 50 | extract64(frac, 2, 50); | |
4594 | exp = 0; | |
4595 | } | |
4596 | ||
4597 | return make_float64(sbit | (exp << 52) | frac); | |
4598 | } | |
4599 | ||
4600 | static bool round_to_inf(float_status *fpst, bool sign_bit) | |
4601 | { | |
4602 | switch (fpst->float_rounding_mode) { | |
4603 | case float_round_nearest_even: /* Round to Nearest */ | |
4604 | return true; | |
4605 | case float_round_up: /* Round to +Inf */ | |
4606 | return !sign_bit; | |
4607 | case float_round_down: /* Round to -Inf */ | |
4608 | return sign_bit; | |
4609 | case float_round_to_zero: /* Round to Zero */ | |
4610 | return false; | |
4611 | } | |
4612 | ||
4613 | g_assert_not_reached(); | |
4614 | } | |
4615 | ||
4616 | float32 HELPER(recpe_f32)(float32 input, void *fpstp) | |
4617 | { | |
4618 | float_status *fpst = fpstp; | |
4619 | float32 f32 = float32_squash_input_denormal(input, fpst); | |
4620 | uint32_t f32_val = float32_val(f32); | |
4621 | uint32_t f32_sbit = 0x80000000ULL & f32_val; | |
4622 | int32_t f32_exp = extract32(f32_val, 23, 8); | |
4623 | uint32_t f32_frac = extract32(f32_val, 0, 23); | |
4624 | float64 f64, r64; | |
4625 | uint64_t r64_val; | |
4626 | int64_t r64_exp; | |
4627 | uint64_t r64_frac; | |
4628 | ||
4629 | if (float32_is_any_nan(f32)) { | |
4630 | float32 nan = f32; | |
4631 | if (float32_is_signaling_nan(f32)) { | |
4632 | float_raise(float_flag_invalid, fpst); | |
4633 | nan = float32_maybe_silence_nan(f32); | |
fe0e4872 | 4634 | } |
b6d4443a AB |
4635 | if (fpst->default_nan_mode) { |
4636 | nan = float32_default_nan; | |
43fe9bdb | 4637 | } |
b6d4443a AB |
4638 | return nan; |
4639 | } else if (float32_is_infinity(f32)) { | |
4640 | return float32_set_sign(float32_zero, float32_is_neg(f32)); | |
4641 | } else if (float32_is_zero(f32)) { | |
4642 | float_raise(float_flag_divbyzero, fpst); | |
4643 | return float32_set_sign(float32_infinity, float32_is_neg(f32)); | |
4644 | } else if ((f32_val & ~(1ULL << 31)) < (1ULL << 21)) { | |
4645 | /* Abs(value) < 2.0^-128 */ | |
4646 | float_raise(float_flag_overflow | float_flag_inexact, fpst); | |
4647 | if (round_to_inf(fpst, f32_sbit)) { | |
4648 | return float32_set_sign(float32_infinity, float32_is_neg(f32)); | |
4649 | } else { | |
4650 | return float32_set_sign(float32_maxnorm, float32_is_neg(f32)); | |
4651 | } | |
4652 | } else if (f32_exp >= 253 && fpst->flush_to_zero) { | |
4653 | float_raise(float_flag_underflow, fpst); | |
4654 | return float32_set_sign(float32_zero, float32_is_neg(f32)); | |
fe0e4872 CL |
4655 | } |
4656 | ||
fe0e4872 | 4657 | |
b6d4443a AB |
4658 | f64 = make_float64(((int64_t)(f32_exp) << 52) | (int64_t)(f32_frac) << 29); |
4659 | r64 = call_recip_estimate(f64, 253, fpst); | |
4660 | r64_val = float64_val(r64); | |
4661 | r64_exp = extract64(r64_val, 52, 11); | |
4662 | r64_frac = extract64(r64_val, 0, 52); | |
4663 | ||
4664 | /* result = sign : result_exp<7:0> : fraction<51:29>; */ | |
4665 | return make_float32(f32_sbit | | |
4666 | (r64_exp & 0xff) << 23 | | |
4667 | extract64(r64_frac, 29, 24)); | |
4668 | } | |
4669 | ||
4670 | float64 HELPER(recpe_f64)(float64 input, void *fpstp) | |
4671 | { | |
4672 | float_status *fpst = fpstp; | |
4673 | float64 f64 = float64_squash_input_denormal(input, fpst); | |
4674 | uint64_t f64_val = float64_val(f64); | |
4675 | uint64_t f64_sbit = 0x8000000000000000ULL & f64_val; | |
4676 | int64_t f64_exp = extract64(f64_val, 52, 11); | |
4677 | float64 r64; | |
4678 | uint64_t r64_val; | |
4679 | int64_t r64_exp; | |
4680 | uint64_t r64_frac; | |
4681 | ||
4682 | /* Deal with any special cases */ | |
4683 | if (float64_is_any_nan(f64)) { | |
4684 | float64 nan = f64; | |
4685 | if (float64_is_signaling_nan(f64)) { | |
4686 | float_raise(float_flag_invalid, fpst); | |
4687 | nan = float64_maybe_silence_nan(f64); | |
4688 | } | |
4689 | if (fpst->default_nan_mode) { | |
4690 | nan = float64_default_nan; | |
4691 | } | |
4692 | return nan; | |
4693 | } else if (float64_is_infinity(f64)) { | |
4694 | return float64_set_sign(float64_zero, float64_is_neg(f64)); | |
4695 | } else if (float64_is_zero(f64)) { | |
4696 | float_raise(float_flag_divbyzero, fpst); | |
4697 | return float64_set_sign(float64_infinity, float64_is_neg(f64)); | |
4698 | } else if ((f64_val & ~(1ULL << 63)) < (1ULL << 50)) { | |
4699 | /* Abs(value) < 2.0^-1024 */ | |
4700 | float_raise(float_flag_overflow | float_flag_inexact, fpst); | |
4701 | if (round_to_inf(fpst, f64_sbit)) { | |
4702 | return float64_set_sign(float64_infinity, float64_is_neg(f64)); | |
4703 | } else { | |
4704 | return float64_set_sign(float64_maxnorm, float64_is_neg(f64)); | |
4705 | } | |
4706 | } else if (f64_exp >= 1023 && fpst->flush_to_zero) { | |
4707 | float_raise(float_flag_underflow, fpst); | |
4708 | return float64_set_sign(float64_zero, float64_is_neg(f64)); | |
4709 | } | |
fe0e4872 | 4710 | |
b6d4443a AB |
4711 | r64 = call_recip_estimate(f64, 2045, fpst); |
4712 | r64_val = float64_val(r64); | |
4713 | r64_exp = extract64(r64_val, 52, 11); | |
4714 | r64_frac = extract64(r64_val, 0, 52); | |
fe0e4872 | 4715 | |
b6d4443a AB |
4716 | /* result = sign : result_exp<10:0> : fraction<51:0> */ |
4717 | return make_float64(f64_sbit | | |
4718 | ((r64_exp & 0x7ff) << 52) | | |
4719 | r64_frac); | |
4373f3ce PB |
4720 | } |
4721 | ||
e07be5d2 CL |
4722 | /* The algorithm that must be used to calculate the estimate |
4723 | * is specified by the ARM ARM. | |
4724 | */ | |
c2fb418e | 4725 | static float64 recip_sqrt_estimate(float64 a, float_status *real_fp_status) |
e07be5d2 | 4726 | { |
1146a817 PM |
4727 | /* These calculations mustn't set any fp exception flags, |
4728 | * so we use a local copy of the fp_status. | |
4729 | */ | |
c2fb418e | 4730 | float_status dummy_status = *real_fp_status; |
1146a817 | 4731 | float_status *s = &dummy_status; |
e07be5d2 CL |
4732 | float64 q; |
4733 | int64_t q_int; | |
4734 | ||
4735 | if (float64_lt(a, float64_half, s)) { | |
4736 | /* range 0.25 <= a < 0.5 */ | |
4737 | ||
4738 | /* a in units of 1/512 rounded down */ | |
4739 | /* q0 = (int)(a * 512.0); */ | |
4740 | q = float64_mul(float64_512, a, s); | |
4741 | q_int = float64_to_int64_round_to_zero(q, s); | |
4742 | ||
4743 | /* reciprocal root r */ | |
4744 | /* r = 1.0 / sqrt(((double)q0 + 0.5) / 512.0); */ | |
4745 | q = int64_to_float64(q_int, s); | |
4746 | q = float64_add(q, float64_half, s); | |
4747 | q = float64_div(q, float64_512, s); | |
4748 | q = float64_sqrt(q, s); | |
4749 | q = float64_div(float64_one, q, s); | |
4750 | } else { | |
4751 | /* range 0.5 <= a < 1.0 */ | |
4752 | ||
4753 | /* a in units of 1/256 rounded down */ | |
4754 | /* q1 = (int)(a * 256.0); */ | |
4755 | q = float64_mul(float64_256, a, s); | |
4756 | int64_t q_int = float64_to_int64_round_to_zero(q, s); | |
4757 | ||
4758 | /* reciprocal root r */ | |
4759 | /* r = 1.0 /sqrt(((double)q1 + 0.5) / 256); */ | |
4760 | q = int64_to_float64(q_int, s); | |
4761 | q = float64_add(q, float64_half, s); | |
4762 | q = float64_div(q, float64_256, s); | |
4763 | q = float64_sqrt(q, s); | |
4764 | q = float64_div(float64_one, q, s); | |
4765 | } | |
4766 | /* r in units of 1/256 rounded to nearest */ | |
4767 | /* s = (int)(256.0 * r + 0.5); */ | |
4768 | ||
4769 | q = float64_mul(q, float64_256,s ); | |
4770 | q = float64_add(q, float64_half, s); | |
4771 | q_int = float64_to_int64_round_to_zero(q, s); | |
4772 | ||
4773 | /* return (double)s / 256.0;*/ | |
4774 | return float64_div(int64_to_float64(q_int, s), float64_256, s); | |
4775 | } | |
4776 | ||
c2fb418e | 4777 | float32 HELPER(rsqrte_f32)(float32 input, void *fpstp) |
4373f3ce | 4778 | { |
c2fb418e AB |
4779 | float_status *s = fpstp; |
4780 | float32 f32 = float32_squash_input_denormal(input, s); | |
4781 | uint32_t val = float32_val(f32); | |
4782 | uint32_t f32_sbit = 0x80000000 & val; | |
4783 | int32_t f32_exp = extract32(val, 23, 8); | |
4784 | uint32_t f32_frac = extract32(val, 0, 23); | |
4785 | uint64_t f64_frac; | |
4786 | uint64_t val64; | |
e07be5d2 CL |
4787 | int result_exp; |
4788 | float64 f64; | |
e07be5d2 | 4789 | |
c2fb418e AB |
4790 | if (float32_is_any_nan(f32)) { |
4791 | float32 nan = f32; | |
4792 | if (float32_is_signaling_nan(f32)) { | |
e07be5d2 | 4793 | float_raise(float_flag_invalid, s); |
c2fb418e | 4794 | nan = float32_maybe_silence_nan(f32); |
e07be5d2 | 4795 | } |
c2fb418e AB |
4796 | if (s->default_nan_mode) { |
4797 | nan = float32_default_nan; | |
43fe9bdb | 4798 | } |
c2fb418e AB |
4799 | return nan; |
4800 | } else if (float32_is_zero(f32)) { | |
e07be5d2 | 4801 | float_raise(float_flag_divbyzero, s); |
c2fb418e AB |
4802 | return float32_set_sign(float32_infinity, float32_is_neg(f32)); |
4803 | } else if (float32_is_neg(f32)) { | |
e07be5d2 CL |
4804 | float_raise(float_flag_invalid, s); |
4805 | return float32_default_nan; | |
c2fb418e | 4806 | } else if (float32_is_infinity(f32)) { |
e07be5d2 CL |
4807 | return float32_zero; |
4808 | } | |
4809 | ||
c2fb418e | 4810 | /* Scale and normalize to a double-precision value between 0.25 and 1.0, |
e07be5d2 | 4811 | * preserving the parity of the exponent. */ |
c2fb418e AB |
4812 | |
4813 | f64_frac = ((uint64_t) f32_frac) << 29; | |
4814 | if (f32_exp == 0) { | |
4815 | while (extract64(f64_frac, 51, 1) == 0) { | |
4816 | f64_frac = f64_frac << 1; | |
4817 | f32_exp = f32_exp-1; | |
4818 | } | |
4819 | f64_frac = extract64(f64_frac, 0, 51) << 1; | |
4820 | } | |
4821 | ||
4822 | if (extract64(f32_exp, 0, 1) == 0) { | |
4823 | f64 = make_float64(((uint64_t) f32_sbit) << 32 | |
e07be5d2 | 4824 | | (0x3feULL << 52) |
c2fb418e | 4825 | | f64_frac); |
e07be5d2 | 4826 | } else { |
c2fb418e | 4827 | f64 = make_float64(((uint64_t) f32_sbit) << 32 |
e07be5d2 | 4828 | | (0x3fdULL << 52) |
c2fb418e | 4829 | | f64_frac); |
e07be5d2 CL |
4830 | } |
4831 | ||
c2fb418e | 4832 | result_exp = (380 - f32_exp) / 2; |
e07be5d2 | 4833 | |
c2fb418e | 4834 | f64 = recip_sqrt_estimate(f64, s); |
e07be5d2 CL |
4835 | |
4836 | val64 = float64_val(f64); | |
4837 | ||
26cc6abf | 4838 | val = ((result_exp & 0xff) << 23) |
e07be5d2 CL |
4839 | | ((val64 >> 29) & 0x7fffff); |
4840 | return make_float32(val); | |
4373f3ce PB |
4841 | } |
4842 | ||
c2fb418e AB |
4843 | float64 HELPER(rsqrte_f64)(float64 input, void *fpstp) |
4844 | { | |
4845 | float_status *s = fpstp; | |
4846 | float64 f64 = float64_squash_input_denormal(input, s); | |
4847 | uint64_t val = float64_val(f64); | |
4848 | uint64_t f64_sbit = 0x8000000000000000ULL & val; | |
4849 | int64_t f64_exp = extract64(val, 52, 11); | |
4850 | uint64_t f64_frac = extract64(val, 0, 52); | |
4851 | int64_t result_exp; | |
4852 | uint64_t result_frac; | |
4853 | ||
4854 | if (float64_is_any_nan(f64)) { | |
4855 | float64 nan = f64; | |
4856 | if (float64_is_signaling_nan(f64)) { | |
4857 | float_raise(float_flag_invalid, s); | |
4858 | nan = float64_maybe_silence_nan(f64); | |
4859 | } | |
4860 | if (s->default_nan_mode) { | |
4861 | nan = float64_default_nan; | |
4862 | } | |
4863 | return nan; | |
4864 | } else if (float64_is_zero(f64)) { | |
4865 | float_raise(float_flag_divbyzero, s); | |
4866 | return float64_set_sign(float64_infinity, float64_is_neg(f64)); | |
4867 | } else if (float64_is_neg(f64)) { | |
4868 | float_raise(float_flag_invalid, s); | |
4869 | return float64_default_nan; | |
4870 | } else if (float64_is_infinity(f64)) { | |
4871 | return float64_zero; | |
4872 | } | |
4873 | ||
4874 | /* Scale and normalize to a double-precision value between 0.25 and 1.0, | |
4875 | * preserving the parity of the exponent. */ | |
4876 | ||
4877 | if (f64_exp == 0) { | |
4878 | while (extract64(f64_frac, 51, 1) == 0) { | |
4879 | f64_frac = f64_frac << 1; | |
4880 | f64_exp = f64_exp - 1; | |
4881 | } | |
4882 | f64_frac = extract64(f64_frac, 0, 51) << 1; | |
4883 | } | |
4884 | ||
4885 | if (extract64(f64_exp, 0, 1) == 0) { | |
4886 | f64 = make_float64(f64_sbit | |
4887 | | (0x3feULL << 52) | |
4888 | | f64_frac); | |
4889 | } else { | |
4890 | f64 = make_float64(f64_sbit | |
4891 | | (0x3fdULL << 52) | |
4892 | | f64_frac); | |
4893 | } | |
4894 | ||
4895 | result_exp = (3068 - f64_exp) / 2; | |
4896 | ||
4897 | f64 = recip_sqrt_estimate(f64, s); | |
4898 | ||
4899 | result_frac = extract64(float64_val(f64), 0, 52); | |
4900 | ||
4901 | return make_float64(f64_sbit | | |
4902 | ((result_exp & 0x7ff) << 52) | | |
4903 | result_frac); | |
4904 | } | |
4905 | ||
b6d4443a | 4906 | uint32_t HELPER(recpe_u32)(uint32_t a, void *fpstp) |
4373f3ce | 4907 | { |
b6d4443a | 4908 | float_status *s = fpstp; |
fe0e4872 CL |
4909 | float64 f64; |
4910 | ||
4911 | if ((a & 0x80000000) == 0) { | |
4912 | return 0xffffffff; | |
4913 | } | |
4914 | ||
4915 | f64 = make_float64((0x3feULL << 52) | |
4916 | | ((int64_t)(a & 0x7fffffff) << 21)); | |
4917 | ||
b6d4443a | 4918 | f64 = recip_estimate(f64, s); |
fe0e4872 CL |
4919 | |
4920 | return 0x80000000 | ((float64_val(f64) >> 21) & 0x7fffffff); | |
4373f3ce PB |
4921 | } |
4922 | ||
c2fb418e | 4923 | uint32_t HELPER(rsqrte_u32)(uint32_t a, void *fpstp) |
4373f3ce | 4924 | { |
c2fb418e | 4925 | float_status *fpst = fpstp; |
e07be5d2 CL |
4926 | float64 f64; |
4927 | ||
4928 | if ((a & 0xc0000000) == 0) { | |
4929 | return 0xffffffff; | |
4930 | } | |
4931 | ||
4932 | if (a & 0x80000000) { | |
4933 | f64 = make_float64((0x3feULL << 52) | |
4934 | | ((uint64_t)(a & 0x7fffffff) << 21)); | |
4935 | } else { /* bits 31-30 == '01' */ | |
4936 | f64 = make_float64((0x3fdULL << 52) | |
4937 | | ((uint64_t)(a & 0x3fffffff) << 22)); | |
4938 | } | |
4939 | ||
c2fb418e | 4940 | f64 = recip_sqrt_estimate(f64, fpst); |
e07be5d2 CL |
4941 | |
4942 | return 0x80000000 | ((float64_val(f64) >> 21) & 0x7fffffff); | |
4373f3ce | 4943 | } |
fe1479c3 | 4944 | |
da97f52c PM |
4945 | /* VFPv4 fused multiply-accumulate */ |
4946 | float32 VFP_HELPER(muladd, s)(float32 a, float32 b, float32 c, void *fpstp) | |
4947 | { | |
4948 | float_status *fpst = fpstp; | |
4949 | return float32_muladd(a, b, c, 0, fpst); | |
4950 | } | |
4951 | ||
4952 | float64 VFP_HELPER(muladd, d)(float64 a, float64 b, float64 c, void *fpstp) | |
4953 | { | |
4954 | float_status *fpst = fpstp; | |
4955 | return float64_muladd(a, b, c, 0, fpst); | |
4956 | } | |
d9b0848d PM |
4957 | |
4958 | /* ARMv8 round to integral */ | |
4959 | float32 HELPER(rints_exact)(float32 x, void *fp_status) | |
4960 | { | |
4961 | return float32_round_to_int(x, fp_status); | |
4962 | } | |
4963 | ||
4964 | float64 HELPER(rintd_exact)(float64 x, void *fp_status) | |
4965 | { | |
4966 | return float64_round_to_int(x, fp_status); | |
4967 | } | |
4968 | ||
4969 | float32 HELPER(rints)(float32 x, void *fp_status) | |
4970 | { | |
4971 | int old_flags = get_float_exception_flags(fp_status), new_flags; | |
4972 | float32 ret; | |
4973 | ||
4974 | ret = float32_round_to_int(x, fp_status); | |
4975 | ||
4976 | /* Suppress any inexact exceptions the conversion produced */ | |
4977 | if (!(old_flags & float_flag_inexact)) { | |
4978 | new_flags = get_float_exception_flags(fp_status); | |
4979 | set_float_exception_flags(new_flags & ~float_flag_inexact, fp_status); | |
4980 | } | |
4981 | ||
4982 | return ret; | |
4983 | } | |
4984 | ||
4985 | float64 HELPER(rintd)(float64 x, void *fp_status) | |
4986 | { | |
4987 | int old_flags = get_float_exception_flags(fp_status), new_flags; | |
4988 | float64 ret; | |
4989 | ||
4990 | ret = float64_round_to_int(x, fp_status); | |
4991 | ||
4992 | new_flags = get_float_exception_flags(fp_status); | |
4993 | ||
4994 | /* Suppress any inexact exceptions the conversion produced */ | |
4995 | if (!(old_flags & float_flag_inexact)) { | |
4996 | new_flags = get_float_exception_flags(fp_status); | |
4997 | set_float_exception_flags(new_flags & ~float_flag_inexact, fp_status); | |
4998 | } | |
4999 | ||
5000 | return ret; | |
5001 | } | |
9972da66 WN |
5002 | |
5003 | /* Convert ARM rounding mode to softfloat */ | |
5004 | int arm_rmode_to_sf(int rmode) | |
5005 | { | |
5006 | switch (rmode) { | |
5007 | case FPROUNDING_TIEAWAY: | |
5008 | rmode = float_round_ties_away; | |
5009 | break; | |
5010 | case FPROUNDING_ODD: | |
5011 | /* FIXME: add support for TIEAWAY and ODD */ | |
5012 | qemu_log_mask(LOG_UNIMP, "arm: unimplemented rounding mode: %d\n", | |
5013 | rmode); | |
5014 | case FPROUNDING_TIEEVEN: | |
5015 | default: | |
5016 | rmode = float_round_nearest_even; | |
5017 | break; | |
5018 | case FPROUNDING_POSINF: | |
5019 | rmode = float_round_up; | |
5020 | break; | |
5021 | case FPROUNDING_NEGINF: | |
5022 | rmode = float_round_down; | |
5023 | break; | |
5024 | case FPROUNDING_ZERO: | |
5025 | rmode = float_round_to_zero; | |
5026 | break; | |
5027 | } | |
5028 | return rmode; | |
5029 | } | |
eb0ecd5a WN |
5030 | |
5031 | static void crc_init_buffer(uint8_t *buf, uint32_t val, uint32_t bytes) | |
5032 | { | |
5033 | memset(buf, 0, 4); | |
5034 | ||
5035 | if (bytes == 1) { | |
5036 | buf[0] = val & 0xff; | |
5037 | } else if (bytes == 2) { | |
5038 | buf[0] = val & 0xff; | |
5039 | buf[1] = (val >> 8) & 0xff; | |
5040 | } else { | |
5041 | buf[0] = val & 0xff; | |
5042 | buf[1] = (val >> 8) & 0xff; | |
5043 | buf[2] = (val >> 16) & 0xff; | |
5044 | buf[3] = (val >> 24) & 0xff; | |
5045 | } | |
5046 | } | |
5047 | ||
5048 | uint32_t HELPER(crc32)(uint32_t acc, uint32_t val, uint32_t bytes) | |
5049 | { | |
5050 | uint8_t buf[4]; | |
5051 | ||
5052 | crc_init_buffer(buf, val, bytes); | |
5053 | ||
5054 | /* zlib crc32 converts the accumulator and output to one's complement. */ | |
5055 | return crc32(acc ^ 0xffffffff, buf, bytes) ^ 0xffffffff; | |
5056 | } | |
5057 | ||
5058 | uint32_t HELPER(crc32c)(uint32_t acc, uint32_t val, uint32_t bytes) | |
5059 | { | |
5060 | uint8_t buf[4]; | |
5061 | ||
5062 | crc_init_buffer(buf, val, bytes); | |
5063 | ||
5064 | /* Linux crc32c converts the output to one's complement. */ | |
5065 | return crc32c(acc, buf, bytes) ^ 0xffffffff; | |
5066 | } |