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target-arm: Add 64 bit variants of DBGDRAR and DBGDSAR for LPAE
[mirror_qemu.git] / target-arm / helper.c
CommitLineData
b5ff1b31 1#include "cpu.h"
9ee6e8bb 2#include "gdbstub.h"
7b59220e 3#include "helper.h"
7bbcb0af 4#include "host-utils.h"
0b03bdfc
PM		 5#include "sysemu.h"
6
4a501606
PM		 7#ifndef CONFIG_USER_ONLY
8static inline int get_phys_addr(CPUARMState *env, uint32_t address,
9 int access_type, int is_user,
10 uint32_t *phys_ptr, int *prot,
11 target_ulong *page_size);
12#endif
13
0ecb72a5 14static int vfp_gdb_get_reg(CPUARMState *env, uint8_t *buf, int reg)
56aebc89
PB		 15{
16 int nregs;
17
18 /* VFP data registers are always little-endian. */
19 nregs = arm_feature(env, ARM_FEATURE_VFP3) ? 32 : 16;
20 if (reg < nregs) {
21 stfq_le_p(buf, env->vfp.regs[reg]);
22 return 8;
23 }
24 if (arm_feature(env, ARM_FEATURE_NEON)) {
25 /* Aliases for Q regs. */
26 nregs += 16;
27 if (reg < nregs) {
28 stfq_le_p(buf, env->vfp.regs[(reg - 32) * 2]);
29 stfq_le_p(buf + 8, env->vfp.regs[(reg - 32) * 2 + 1]);
30 return 16;
31 }
32 }
33 switch (reg - nregs) {
34 case 0: stl_p(buf, env->vfp.xregs[ARM_VFP_FPSID]); return 4;
35 case 1: stl_p(buf, env->vfp.xregs[ARM_VFP_FPSCR]); return 4;
36 case 2: stl_p(buf, env->vfp.xregs[ARM_VFP_FPEXC]); return 4;
37 }
38 return 0;
39}
40
0ecb72a5 41static int vfp_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg)
56aebc89
PB		 42{
43 int nregs;
44
45 nregs = arm_feature(env, ARM_FEATURE_VFP3) ? 32 : 16;
46 if (reg < nregs) {
47 env->vfp.regs[reg] = ldfq_le_p(buf);
48 return 8;
49 }
50 if (arm_feature(env, ARM_FEATURE_NEON)) {
51 nregs += 16;
52 if (reg < nregs) {
53 env->vfp.regs[(reg - 32) * 2] = ldfq_le_p(buf);
54 env->vfp.regs[(reg - 32) * 2 + 1] = ldfq_le_p(buf + 8);
55 return 16;
56 }
57 }
58 switch (reg - nregs) {
59 case 0: env->vfp.xregs[ARM_VFP_FPSID] = ldl_p(buf); return 4;
60 case 1: env->vfp.xregs[ARM_VFP_FPSCR] = ldl_p(buf); return 4;
71b3c3de 61 case 2: env->vfp.xregs[ARM_VFP_FPEXC] = ldl_p(buf) & (1 << 30); return 4;
56aebc89
PB		 62 }
63 return 0;
64}
65
c983fe6c
PM		 66static int dacr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
67{
68 env->cp15.c3 = value;
69 tlb_flush(env, 1); /* Flush TLB as domain not tracked in TLB */
70 return 0;
71}
72
08de207b
PM		 73static int fcse_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
74{
75 if (env->cp15.c13_fcse != value) {
76 /* Unlike real hardware the qemu TLB uses virtual addresses,
77 * not modified virtual addresses, so this causes a TLB flush.
78 */
79 tlb_flush(env, 1);
80 env->cp15.c13_fcse = value;
81 }
82 return 0;
83}
84static int contextidr_write(CPUARMState *env, const ARMCPRegInfo *ri,
85 uint64_t value)
86{
87 if (env->cp15.c13_context != value && !arm_feature(env, ARM_FEATURE_MPU)) {
88 /* For VMSA (when not using the LPAE long descriptor page table
89 * format) this register includes the ASID, so do a TLB flush.
90 * For PMSA it is purely a process ID and no action is needed.
91 */
92 tlb_flush(env, 1);
93 }
94 env->cp15.c13_context = value;
95 return 0;
96}
97
d929823f
PM		 98static int tlbiall_write(CPUARMState *env, const ARMCPRegInfo *ri,
99 uint64_t value)
100{
101 /* Invalidate all (TLBIALL) */
102 tlb_flush(env, 1);
103 return 0;
104}
105
106static int tlbimva_write(CPUARMState *env, const ARMCPRegInfo *ri,
107 uint64_t value)
108{
109 /* Invalidate single TLB entry by MVA and ASID (TLBIMVA) */
110 tlb_flush_page(env, value & TARGET_PAGE_MASK);
111 return 0;
112}
113
114static int tlbiasid_write(CPUARMState *env, const ARMCPRegInfo *ri,
115 uint64_t value)
116{
117 /* Invalidate by ASID (TLBIASID) */
118 tlb_flush(env, value == 0);
119 return 0;
120}
121
122static int tlbimvaa_write(CPUARMState *env, const ARMCPRegInfo *ri,
123 uint64_t value)
124{
125 /* Invalidate single entry by MVA, all ASIDs (TLBIMVAA) */
126 tlb_flush_page(env, value & TARGET_PAGE_MASK);
127 return 0;
128}
129
e9aa6c21
PM		 130static const ARMCPRegInfo cp_reginfo[] = {
131 /* DBGDIDR: just RAZ. In particular this means the "debug architecture
132 * version" bits will read as a reserved value, which should cause
133 * Linux to not try to use the debug hardware.
134 */
135 { .name = "DBGDIDR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 0,
136 .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 },
c983fe6c
PM		 137 /* MMU Domain access control / MPU write buffer control */
138 { .name = "DACR", .cp = 15,
139 .crn = 3, .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY,
140 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c3),
141 .resetvalue = 0, .writefn = dacr_write },
08de207b
PM		 142 { .name = "FCSEIDR", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 0,
143 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c13_fcse),
144 .resetvalue = 0, .writefn = fcse_write },
145 { .name = "CONTEXTIDR", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 1,
146 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c13_fcse),
147 .resetvalue = 0, .writefn = contextidr_write },
4fdd17dd
PM		 148 /* ??? This covers not just the impdef TLB lockdown registers but also
149 * some v7VMSA registers relating to TEX remap, so it is overly broad.
150 */
151 { .name = "TLB_LOCKDOWN", .cp = 15, .crn = 10, .crm = CP_ANY,
152 .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_NOP },
d929823f
PM		 153 /* MMU TLB control. Note that the wildcarding means we cover not just
154 * the unified TLB ops but also the dside/iside/inner-shareable variants.
155 */
156 { .name = "TLBIALL", .cp = 15, .crn = 8, .crm = CP_ANY,
157 .opc1 = CP_ANY, .opc2 = 0, .access = PL1_W, .writefn = tlbiall_write, },
158 { .name = "TLBIMVA", .cp = 15, .crn = 8, .crm = CP_ANY,
159 .opc1 = CP_ANY, .opc2 = 1, .access = PL1_W, .writefn = tlbimva_write, },
160 { .name = "TLBIASID", .cp = 15, .crn = 8, .crm = CP_ANY,
161 .opc1 = CP_ANY, .opc2 = 2, .access = PL1_W, .writefn = tlbiasid_write, },
162 { .name = "TLBIMVAA", .cp = 15, .crn = 8, .crm = CP_ANY,
163 .opc1 = CP_ANY, .opc2 = 3, .access = PL1_W, .writefn = tlbimvaa_write, },
c4804214
PM		 164 /* Cache maintenance ops; some of this space may be overridden later. */
165 { .name = "CACHEMAINT", .cp = 15, .crn = 7, .crm = CP_ANY,
166 .opc1 = 0, .opc2 = CP_ANY, .access = PL1_W,
167 .type = ARM_CP_NOP | ARM_CP_OVERRIDE },
e9aa6c21
PM		 168 REGINFO_SENTINEL
169};
170
7d57f408
PM		 171static const ARMCPRegInfo not_v6_cp_reginfo[] = {
172 /* Not all pre-v6 cores implemented this WFI, so this is slightly
173 * over-broad.
174 */
175 { .name = "WFI_v5", .cp = 15, .crn = 7, .crm = 8, .opc1 = 0, .opc2 = 2,
176 .access = PL1_W, .type = ARM_CP_WFI },
177 REGINFO_SENTINEL
178};
179
180static const ARMCPRegInfo not_v7_cp_reginfo[] = {
181 /* Standard v6 WFI (also used in some pre-v6 cores); not in v7 (which
182 * is UNPREDICTABLE; we choose to NOP as most implementations do).
183 */
184 { .name = "WFI_v6", .cp = 15, .crn = 7, .crm = 0, .opc1 = 0, .opc2 = 4,
185 .access = PL1_W, .type = ARM_CP_WFI },
34f90529
PM		 186 /* L1 cache lockdown. Not architectural in v6 and earlier but in practice
187 * implemented in 926, 946, 1026, 1136, 1176 and 11MPCore. StrongARM and
188 * OMAPCP will override this space.
189 */
190 { .name = "DLOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 0, .opc2 = 0,
191 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_data),
192 .resetvalue = 0 },
193 { .name = "ILOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 0, .opc2 = 1,
194 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_insn),
195 .resetvalue = 0 },
776d4e5c
PM		 196 /* v6 doesn't have the cache ID registers but Linux reads them anyway */
197 { .name = "DUMMY", .cp = 15, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = CP_ANY,
198 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
7d57f408
PM		 199 REGINFO_SENTINEL
200};
201
2771db27
PM		 202static int cpacr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
203{
204 if (env->cp15.c1_coproc != value) {
205 env->cp15.c1_coproc = value;
206 /* ??? Is this safe when called from within a TB? */
207 tb_flush(env);
208 }
209 return 0;
210}
211
7d57f408
PM		 212static const ARMCPRegInfo v6_cp_reginfo[] = {
213 /* prefetch by MVA in v6, NOP in v7 */
214 { .name = "MVA_prefetch",
215 .cp = 15, .crn = 7, .crm = 13, .opc1 = 0, .opc2 = 1,
216 .access = PL1_W, .type = ARM_CP_NOP },
217 { .name = "ISB", .cp = 15, .crn = 7, .crm = 5, .opc1 = 0, .opc2 = 4,
218 .access = PL0_W, .type = ARM_CP_NOP },
091fd17c 219 { .name = "DSB", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 4,
7d57f408 220 .access = PL0_W, .type = ARM_CP_NOP },
091fd17c 221 { .name = "DMB", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 5,
7d57f408 222 .access = PL0_W, .type = ARM_CP_NOP },
06d76f31
PM		 223 { .name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 2,
224 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c6_insn),
225 .resetvalue = 0, },
226 /* Watchpoint Fault Address Register : should actually only be present
227 * for 1136, 1176, 11MPCore.
228 */
229 { .name = "WFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1,
230 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0, },
2771db27
PM		 231 { .name = "CPACR", .cp = 15, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 2,
232 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c1_coproc),
233 .resetvalue = 0, .writefn = cpacr_write },
7d57f408
PM		 234 REGINFO_SENTINEL
235};
236
200ac0ef
PM		 237static int pmreg_read(CPUARMState *env, const ARMCPRegInfo *ri,
238 uint64_t *value)
239{
240 /* Generic performance monitor register read function for where
241 * user access may be allowed by PMUSERENR.
242 */
243 if (arm_current_pl(env) == 0 && !env->cp15.c9_pmuserenr) {
244 return EXCP_UDEF;
245 }
246 *value = CPREG_FIELD32(env, ri);
247 return 0;
248}
249
250static int pmcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
251 uint64_t value)
252{
253 if (arm_current_pl(env) == 0 && !env->cp15.c9_pmuserenr) {
254 return EXCP_UDEF;
255 }
256 /* only the DP, X, D and E bits are writable */
257 env->cp15.c9_pmcr &= ~0x39;
258 env->cp15.c9_pmcr |= (value & 0x39);
259 return 0;
260}
261
262static int pmcntenset_write(CPUARMState *env, const ARMCPRegInfo *ri,
263 uint64_t value)
264{
265 if (arm_current_pl(env) == 0 && !env->cp15.c9_pmuserenr) {
266 return EXCP_UDEF;
267 }
268 value &= (1 << 31);
269 env->cp15.c9_pmcnten |= value;
270 return 0;
271}
272
273static int pmcntenclr_write(CPUARMState *env, const ARMCPRegInfo *ri,
274 uint64_t value)
275{
276 if (arm_current_pl(env) == 0 && !env->cp15.c9_pmuserenr) {
277 return EXCP_UDEF;
278 }
279 value &= (1 << 31);
280 env->cp15.c9_pmcnten &= ~value;
281 return 0;
282}
283
284static int pmovsr_write(CPUARMState *env, const ARMCPRegInfo *ri,
285 uint64_t value)
286{
287 if (arm_current_pl(env) == 0 && !env->cp15.c9_pmuserenr) {
288 return EXCP_UDEF;
289 }
290 env->cp15.c9_pmovsr &= ~value;
291 return 0;
292}
293
294static int pmxevtyper_write(CPUARMState *env, const ARMCPRegInfo *ri,
295 uint64_t value)
296{
297 if (arm_current_pl(env) == 0 && !env->cp15.c9_pmuserenr) {
298 return EXCP_UDEF;
299 }
300 env->cp15.c9_pmxevtyper = value & 0xff;
301 return 0;
302}
303
304static int pmuserenr_write(CPUARMState *env, const ARMCPRegInfo *ri,
305 uint64_t value)
306{
307 env->cp15.c9_pmuserenr = value & 1;
308 return 0;
309}
310
311static int pmintenset_write(CPUARMState *env, const ARMCPRegInfo *ri,
312 uint64_t value)
313{
314 /* We have no event counters so only the C bit can be changed */
315 value &= (1 << 31);
316 env->cp15.c9_pminten |= value;
317 return 0;
318}
319
320static int pmintenclr_write(CPUARMState *env, const ARMCPRegInfo *ri,
321 uint64_t value)
322{
323 value &= (1 << 31);
324 env->cp15.c9_pminten &= ~value;
325 return 0;
326}
327
776d4e5c
PM		 328static int ccsidr_read(CPUARMState *env, const ARMCPRegInfo *ri,
329 uint64_t *value)
330{
331 ARMCPU *cpu = arm_env_get_cpu(env);
332 *value = cpu->ccsidr[env->cp15.c0_cssel];
333 return 0;
334}
335
336static int csselr_write(CPUARMState *env, const ARMCPRegInfo *ri,
337 uint64_t value)
338{
339 env->cp15.c0_cssel = value & 0xf;
340 return 0;
341}
342
e9aa6c21
PM		 343static const ARMCPRegInfo v7_cp_reginfo[] = {
344 /* DBGDRAR, DBGDSAR: always RAZ since we don't implement memory mapped
345 * debug components
346 */
347 { .name = "DBGDRAR", .cp = 14, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 0,
348 .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 },
091fd17c 349 { .name = "DBGDSAR", .cp = 14, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 0,
e9aa6c21 350 .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 },
7d57f408
PM		 351 /* the old v6 WFI, UNPREDICTABLE in v7 but we choose to NOP */
352 { .name = "NOP", .cp = 15, .crn = 7, .crm = 0, .opc1 = 0, .opc2 = 4,
353 .access = PL1_W, .type = ARM_CP_NOP },
200ac0ef
PM		 354 /* Performance monitors are implementation defined in v7,
355 * but with an ARM recommended set of registers, which we
356 * follow (although we don't actually implement any counters)
357 *
358 * Performance registers fall into three categories:
359 * (a) always UNDEF in PL0, RW in PL1 (PMINTENSET, PMINTENCLR)
360 * (b) RO in PL0 (ie UNDEF on write), RW in PL1 (PMUSERENR)
361 * (c) UNDEF in PL0 if PMUSERENR.EN==0, otherwise accessible (all others)
362 * For the cases controlled by PMUSERENR we must set .access to PL0_RW
363 * or PL0_RO as appropriate and then check PMUSERENR in the helper fn.
364 */
365 { .name = "PMCNTENSET", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 1,
366 .access = PL0_RW, .resetvalue = 0,
367 .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcnten),
368 .readfn = pmreg_read, .writefn = pmcntenset_write },
369 { .name = "PMCNTENCLR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 2,
370 .access = PL0_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcnten),
371 .readfn = pmreg_read, .writefn = pmcntenclr_write },
372 { .name = "PMOVSR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 3,
373 .access = PL0_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_pmovsr),
374 .readfn = pmreg_read, .writefn = pmovsr_write },
375 /* Unimplemented so WI. Strictly speaking write accesses in PL0 should
376 * respect PMUSERENR.
377 */
378 { .name = "PMSWINC", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 4,
379 .access = PL0_W, .type = ARM_CP_NOP },
380 /* Since we don't implement any events, writing to PMSELR is UNPREDICTABLE.
381 * We choose to RAZ/WI. XXX should respect PMUSERENR.
382 */
383 { .name = "PMSELR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 5,
384 .access = PL0_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
385 /* Unimplemented, RAZ/WI. XXX PMUSERENR */
386 { .name = "PMCCNTR", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 0,
387 .access = PL0_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
388 { .name = "PMXEVTYPER", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 1,
389 .access = PL0_RW,
390 .fieldoffset = offsetof(CPUARMState, cp15.c9_pmxevtyper),
391 .readfn = pmreg_read, .writefn = pmxevtyper_write },
392 /* Unimplemented, RAZ/WI. XXX PMUSERENR */
393 { .name = "PMXEVCNTR", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 2,
394 .access = PL0_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
395 { .name = "PMUSERENR", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 0,
396 .access = PL0_R | PL1_RW,
397 .fieldoffset = offsetof(CPUARMState, cp15.c9_pmuserenr),
398 .resetvalue = 0,
399 .writefn = pmuserenr_write },
400 { .name = "PMINTENSET", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 1,
401 .access = PL1_RW,
402 .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten),
403 .resetvalue = 0,
404 .writefn = pmintenset_write },
405 { .name = "PMINTENCLR", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 2,
406 .access = PL1_RW,
407 .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten),
408 .resetvalue = 0,
409 .writefn = pmintenclr_write },
2771db27
PM		 410 { .name = "SCR", .cp = 15, .crn = 1, .crm = 1, .opc1 = 0, .opc2 = 0,
411 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c1_scr),
412 .resetvalue = 0, },
776d4e5c
PM		 413 { .name = "CCSIDR", .cp = 15, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 0,
414 .access = PL1_R, .readfn = ccsidr_read },
415 { .name = "CSSELR", .cp = 15, .crn = 0, .crm = 0, .opc1 = 2, .opc2 = 0,
416 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c0_cssel),
417 .writefn = csselr_write, .resetvalue = 0 },
418 /* Auxiliary ID register: this actually has an IMPDEF value but for now
419 * just RAZ for all cores:
420 */
421 { .name = "AIDR", .cp = 15, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 7,
422 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
e9aa6c21
PM		 423 REGINFO_SENTINEL
424};
425
c326b979
PM		 426static int teecr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
427{
428 value &= 1;
429 env->teecr = value;
430 return 0;
431}
432
433static int teehbr_read(CPUARMState *env, const ARMCPRegInfo *ri,
434 uint64_t *value)
435{
436 /* This is a helper function because the user access rights
437 * depend on the value of the TEECR.
438 */
439 if (arm_current_pl(env) == 0 && (env->teecr & 1)) {
440 return EXCP_UDEF;
441 }
442 *value = env->teehbr;
443 return 0;
444}
445
446static int teehbr_write(CPUARMState *env, const ARMCPRegInfo *ri,
447 uint64_t value)
448{
449 if (arm_current_pl(env) == 0 && (env->teecr & 1)) {
450 return EXCP_UDEF;
451 }
452 env->teehbr = value;
453 return 0;
454}
455
456static const ARMCPRegInfo t2ee_cp_reginfo[] = {
457 { .name = "TEECR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 6, .opc2 = 0,
458 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, teecr),
459 .resetvalue = 0,
460 .writefn = teecr_write },
461 { .name = "TEEHBR", .cp = 14, .crn = 1, .crm = 0, .opc1 = 6, .opc2 = 0,
462 .access = PL0_RW, .fieldoffset = offsetof(CPUARMState, teehbr),
463 .resetvalue = 0,
464 .readfn = teehbr_read, .writefn = teehbr_write },
465 REGINFO_SENTINEL
466};
467
4d31c596
PM		 468static const ARMCPRegInfo v6k_cp_reginfo[] = {
469 { .name = "TPIDRURW", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 2,
470 .access = PL0_RW,
471 .fieldoffset = offsetof(CPUARMState, cp15.c13_tls1),
472 .resetvalue = 0 },
473 { .name = "TPIDRURO", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 3,
474 .access = PL0_R|PL1_W,
475 .fieldoffset = offsetof(CPUARMState, cp15.c13_tls2),
476 .resetvalue = 0 },
477 { .name = "TPIDRPRW", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 4,
478 .access = PL1_RW,
479 .fieldoffset = offsetof(CPUARMState, cp15.c13_tls3),
480 .resetvalue = 0 },
481 REGINFO_SENTINEL
482};
483
6cc7a3ae
PM		 484static const ARMCPRegInfo generic_timer_cp_reginfo[] = {
485 /* Dummy implementation: RAZ/WI the whole crn=14 space */
486 { .name = "GENERIC_TIMER", .cp = 15, .crn = 14,
487 .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY,
488 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
489 REGINFO_SENTINEL
490};
491
4a501606
PM		 492static int par_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
493{
494 if (arm_feature(env, ARM_FEATURE_V7)) {
495 env->cp15.c7_par = value & 0xfffff6ff;
496 } else {
497 env->cp15.c7_par = value & 0xfffff1ff;
498 }
499 return 0;
500}
501
502#ifndef CONFIG_USER_ONLY
503/* get_phys_addr() isn't present for user-mode-only targets */
504static int ats_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
505{
506 uint32_t phys_addr;
507 target_ulong page_size;
508 int prot;
509 int ret, is_user = ri->opc2 & 2;
510 int access_type = ri->opc2 & 1;
511
512 if (ri->opc2 & 4) {
513 /* Other states are only available with TrustZone */
514 return EXCP_UDEF;
515 }
516 ret = get_phys_addr(env, value, access_type, is_user,
517 &phys_addr, &prot, &page_size);
518 if (ret == 0) {
519 /* We do not set any attribute bits in the PAR */
520 if (page_size == (1 << 24)
521 && arm_feature(env, ARM_FEATURE_V7)) {
522 env->cp15.c7_par = (phys_addr & 0xff000000) | 1 << 1;
523 } else {
524 env->cp15.c7_par = phys_addr & 0xfffff000;
525 }
526 } else {
527 env->cp15.c7_par = ((ret & (10 << 1)) >> 5) |
528 ((ret & (12 << 1)) >> 6) |
529 ((ret & 0xf) << 1) | 1;
530 }
531 return 0;
532}
533#endif
534
535static const ARMCPRegInfo vapa_cp_reginfo[] = {
536 { .name = "PAR", .cp = 15, .crn = 7, .crm = 4, .opc1 = 0, .opc2 = 0,
537 .access = PL1_RW, .resetvalue = 0,
538 .fieldoffset = offsetof(CPUARMState, cp15.c7_par),
539 .writefn = par_write },
540#ifndef CONFIG_USER_ONLY
541 { .name = "ATS", .cp = 15, .crn = 7, .crm = 8, .opc1 = 0, .opc2 = CP_ANY,
542 .access = PL1_W, .writefn = ats_write },
543#endif
544 REGINFO_SENTINEL
545};
546
18032bec
PM		 547/* Return basic MPU access permission bits. */
548static uint32_t simple_mpu_ap_bits(uint32_t val)
549{
550 uint32_t ret;
551 uint32_t mask;
552 int i;
553 ret = 0;
554 mask = 3;
555 for (i = 0; i < 16; i += 2) {
556 ret |= (val >> i) & mask;
557 mask <<= 2;
558 }
559 return ret;
560}
561
562/* Pad basic MPU access permission bits to extended format. */
563static uint32_t extended_mpu_ap_bits(uint32_t val)
564{
565 uint32_t ret;
566 uint32_t mask;
567 int i;
568 ret = 0;
569 mask = 3;
570 for (i = 0; i < 16; i += 2) {
571 ret |= (val & mask) << i;
572 mask <<= 2;
573 }
574 return ret;
575}
576
577static int pmsav5_data_ap_write(CPUARMState *env, const ARMCPRegInfo *ri,
578 uint64_t value)
579{
580 env->cp15.c5_data = extended_mpu_ap_bits(value);
581 return 0;
582}
583
584static int pmsav5_data_ap_read(CPUARMState *env, const ARMCPRegInfo *ri,
585 uint64_t *value)
586{
587 *value = simple_mpu_ap_bits(env->cp15.c5_data);
588 return 0;
589}
590
591static int pmsav5_insn_ap_write(CPUARMState *env, const ARMCPRegInfo *ri,
592 uint64_t value)
593{
594 env->cp15.c5_insn = extended_mpu_ap_bits(value);
595 return 0;
596}
597
598static int pmsav5_insn_ap_read(CPUARMState *env, const ARMCPRegInfo *ri,
599 uint64_t *value)
600{
601 *value = simple_mpu_ap_bits(env->cp15.c5_insn);
602 return 0;
603}
604
06d76f31
PM		 605static int arm946_prbs_read(CPUARMState *env, const ARMCPRegInfo *ri,
606 uint64_t *value)
607{
608 if (ri->crm > 8) {
609 return EXCP_UDEF;
610 }
611 *value = env->cp15.c6_region[ri->crm];
612 return 0;
613}
614
615static int arm946_prbs_write(CPUARMState *env, const ARMCPRegInfo *ri,
616 uint64_t value)
617{
618 if (ri->crm > 8) {
619 return EXCP_UDEF;
620 }
621 env->cp15.c6_region[ri->crm] = value;
622 return 0;
623}
624
18032bec
PM		 625static const ARMCPRegInfo pmsav5_cp_reginfo[] = {
626 { .name = "DATA_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 0,
627 .access = PL1_RW,
628 .fieldoffset = offsetof(CPUARMState, cp15.c5_data), .resetvalue = 0,
629 .readfn = pmsav5_data_ap_read, .writefn = pmsav5_data_ap_write, },
630 { .name = "INSN_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 1,
631 .access = PL1_RW,
632 .fieldoffset = offsetof(CPUARMState, cp15.c5_insn), .resetvalue = 0,
633 .readfn = pmsav5_insn_ap_read, .writefn = pmsav5_insn_ap_write, },
634 { .name = "DATA_EXT_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 2,
635 .access = PL1_RW,
636 .fieldoffset = offsetof(CPUARMState, cp15.c5_data), .resetvalue = 0, },
637 { .name = "INSN_EXT_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 3,
638 .access = PL1_RW,
639 .fieldoffset = offsetof(CPUARMState, cp15.c5_insn), .resetvalue = 0, },
ecce5c3c
PM		 640 { .name = "DCACHE_CFG", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 0,
641 .access = PL1_RW,
642 .fieldoffset = offsetof(CPUARMState, cp15.c2_data), .resetvalue = 0, },
643 { .name = "ICACHE_CFG", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 1,
644 .access = PL1_RW,
645 .fieldoffset = offsetof(CPUARMState, cp15.c2_insn), .resetvalue = 0, },
06d76f31
PM		 646 /* Protection region base and size registers */
647 { .name = "946_PRBS", .cp = 15, .crn = 6, .crm = CP_ANY, .opc1 = 0,
648 .opc2 = CP_ANY, .access = PL1_RW,
649 .readfn = arm946_prbs_read, .writefn = arm946_prbs_write, },
18032bec
PM		 650 REGINFO_SENTINEL
651};
652
ecce5c3c
PM		 653static int vmsa_ttbcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
654 uint64_t value)
655{
656 value &= 7;
657 env->cp15.c2_control = value;
658 env->cp15.c2_mask = ~(((uint32_t)0xffffffffu) >> value);
659 env->cp15.c2_base_mask = ~((uint32_t)0x3fffu >> value);
660 return 0;
661}
662
663static void vmsa_ttbcr_reset(CPUARMState *env, const ARMCPRegInfo *ri)
664{
665 env->cp15.c2_base_mask = 0xffffc000u;
666 env->cp15.c2_control = 0;
667 env->cp15.c2_mask = 0;
668}
669
18032bec
PM		 670static const ARMCPRegInfo vmsa_cp_reginfo[] = {
671 { .name = "DFSR", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 0,
672 .access = PL1_RW,
673 .fieldoffset = offsetof(CPUARMState, cp15.c5_data), .resetvalue = 0, },
674 { .name = "IFSR", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 1,
675 .access = PL1_RW,
676 .fieldoffset = offsetof(CPUARMState, cp15.c5_insn), .resetvalue = 0, },
ecce5c3c
PM		 677 { .name = "TTBR0", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 0,
678 .access = PL1_RW,
679 .fieldoffset = offsetof(CPUARMState, cp15.c2_base0), .resetvalue = 0, },
680 { .name = "TTBR1", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 1,
681 .access = PL1_RW,
81a60ada 682 .fieldoffset = offsetof(CPUARMState, cp15.c2_base1), .resetvalue = 0, },
ecce5c3c
PM		 683 { .name = "TTBCR", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 2,
684 .access = PL1_RW, .writefn = vmsa_ttbcr_write,
685 .resetfn = vmsa_ttbcr_reset,
686 .fieldoffset = offsetof(CPUARMState, cp15.c2_control) },
06d76f31
PM		 687 { .name = "DFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 0,
688 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c6_data),
689 .resetvalue = 0, },
18032bec
PM		 690 REGINFO_SENTINEL
691};
692
1047b9d7
PM		 693static int omap_ticonfig_write(CPUARMState *env, const ARMCPRegInfo *ri,
694 uint64_t value)
695{
696 env->cp15.c15_ticonfig = value & 0xe7;
697 /* The OS_TYPE bit in this register changes the reported CPUID! */
698 env->cp15.c0_cpuid = (value & (1 << 5)) ?
699 ARM_CPUID_TI915T : ARM_CPUID_TI925T;
700 return 0;
701}
702
703static int omap_threadid_write(CPUARMState *env, const ARMCPRegInfo *ri,
704 uint64_t value)
705{
706 env->cp15.c15_threadid = value & 0xffff;
707 return 0;
708}
709
710static int omap_wfi_write(CPUARMState *env, const ARMCPRegInfo *ri,
711 uint64_t value)
712{
713 /* Wait-for-interrupt (deprecated) */
714 cpu_interrupt(env, CPU_INTERRUPT_HALT);
715 return 0;
716}
717
c4804214
PM		 718static int omap_cachemaint_write(CPUARMState *env, const ARMCPRegInfo *ri,
719 uint64_t value)
720{
721 /* On OMAP there are registers indicating the max/min index of dcache lines
722 * containing a dirty line; cache flush operations have to reset these.
723 */
724 env->cp15.c15_i_max = 0x000;
725 env->cp15.c15_i_min = 0xff0;
726 return 0;
727}
728
18032bec
PM		 729static const ARMCPRegInfo omap_cp_reginfo[] = {
730 { .name = "DFSR", .cp = 15, .crn = 5, .crm = CP_ANY,
731 .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_OVERRIDE,
732 .fieldoffset = offsetof(CPUARMState, cp15.c5_data), .resetvalue = 0, },
1047b9d7
PM		 733 { .name = "", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0,
734 .access = PL1_RW, .type = ARM_CP_NOP },
735 { .name = "TICONFIG", .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0,
736 .access = PL1_RW,
737 .fieldoffset = offsetof(CPUARMState, cp15.c15_ticonfig), .resetvalue = 0,
738 .writefn = omap_ticonfig_write },
739 { .name = "IMAX", .cp = 15, .crn = 15, .crm = 2, .opc1 = 0, .opc2 = 0,
740 .access = PL1_RW,
741 .fieldoffset = offsetof(CPUARMState, cp15.c15_i_max), .resetvalue = 0, },
742 { .name = "IMIN", .cp = 15, .crn = 15, .crm = 3, .opc1 = 0, .opc2 = 0,
743 .access = PL1_RW, .resetvalue = 0xff0,
744 .fieldoffset = offsetof(CPUARMState, cp15.c15_i_min) },
745 { .name = "THREADID", .cp = 15, .crn = 15, .crm = 4, .opc1 = 0, .opc2 = 0,
746 .access = PL1_RW,
747 .fieldoffset = offsetof(CPUARMState, cp15.c15_threadid), .resetvalue = 0,
748 .writefn = omap_threadid_write },
749 { .name = "TI925T_STATUS", .cp = 15, .crn = 15,
750 .crm = 8, .opc1 = 0, .opc2 = 0, .access = PL1_RW,
751 .readfn = arm_cp_read_zero, .writefn = omap_wfi_write, },
752 /* TODO: Peripheral port remap register:
753 * On OMAP2 mcr p15, 0, rn, c15, c2, 4 sets up the interrupt controller
754 * base address at $rn & ~0xfff and map size of 0x200 << ($rn & 0xfff),
755 * when MMU is off.
756 */
c4804214
PM		 757 { .name = "OMAP_CACHEMAINT", .cp = 15, .crn = 7, .crm = CP_ANY,
758 .opc1 = 0, .opc2 = CP_ANY, .access = PL1_W, .type = ARM_CP_OVERRIDE,
759 .writefn = omap_cachemaint_write },
34f90529
PM		 760 { .name = "C9", .cp = 15, .crn = 9,
761 .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW,
762 .type = ARM_CP_CONST | ARM_CP_OVERRIDE, .resetvalue = 0 },
1047b9d7
PM		 763 REGINFO_SENTINEL
764};
765
766static int xscale_cpar_write(CPUARMState *env, const ARMCPRegInfo *ri,
767 uint64_t value)
768{
769 value &= 0x3fff;
770 if (env->cp15.c15_cpar != value) {
771 /* Changes cp0 to cp13 behavior, so needs a TB flush. */
772 tb_flush(env);
773 env->cp15.c15_cpar = value;
774 }
775 return 0;
776}
777
778static const ARMCPRegInfo xscale_cp_reginfo[] = {
779 { .name = "XSCALE_CPAR",
780 .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0, .access = PL1_RW,
781 .fieldoffset = offsetof(CPUARMState, cp15.c15_cpar), .resetvalue = 0,
782 .writefn = xscale_cpar_write, },
2771db27
PM		 783 { .name = "XSCALE_AUXCR",
784 .cp = 15, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 1, .access = PL1_RW,
785 .fieldoffset = offsetof(CPUARMState, cp15.c1_xscaleauxcr),
786 .resetvalue = 0, },
1047b9d7
PM		 787 REGINFO_SENTINEL
788};
789
790static const ARMCPRegInfo dummy_c15_cp_reginfo[] = {
791 /* RAZ/WI the whole crn=15 space, when we don't have a more specific
792 * implementation of this implementation-defined space.
793 * Ideally this should eventually disappear in favour of actually
794 * implementing the correct behaviour for all cores.
795 */
796 { .name = "C15_IMPDEF", .cp = 15, .crn = 15,
797 .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY,
798 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
18032bec
PM		 799 REGINFO_SENTINEL
800};
801
c4804214
PM		 802static const ARMCPRegInfo cache_dirty_status_cp_reginfo[] = {
803 /* Cache status: RAZ because we have no cache so it's always clean */
804 { .name = "CDSR", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 6,
805 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
806 REGINFO_SENTINEL
807};
808
809static const ARMCPRegInfo cache_block_ops_cp_reginfo[] = {
810 /* We never have a a block transfer operation in progress */
811 { .name = "BXSR", .cp = 15, .crn = 7, .crm = 12, .opc1 = 0, .opc2 = 4,
812 .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 },
30b05bba
PM		 813 /* The cache ops themselves: these all NOP for QEMU */
814 { .name = "IICR", .cp = 15, .crm = 5, .opc1 = 0,
815 .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
816 { .name = "IDCR", .cp = 15, .crm = 6, .opc1 = 0,
817 .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
818 { .name = "CDCR", .cp = 15, .crm = 12, .opc1 = 0,
819 .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
820 { .name = "PIR", .cp = 15, .crm = 12, .opc1 = 1,
821 .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
822 { .name = "PDR", .cp = 15, .crm = 12, .opc1 = 2,
823 .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
824 { .name = "CIDCR", .cp = 15, .crm = 14, .opc1 = 0,
825 .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
c4804214
PM		 826 REGINFO_SENTINEL
827};
828
829static const ARMCPRegInfo cache_test_clean_cp_reginfo[] = {
830 /* The cache test-and-clean instructions always return (1 << 30)
831 * to indicate that there are no dirty cache lines.
832 */
833 { .name = "TC_DCACHE", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 3,
834 .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = (1 << 30) },
835 { .name = "TCI_DCACHE", .cp = 15, .crn = 7, .crm = 14, .opc1 = 0, .opc2 = 3,
836 .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = (1 << 30) },
837 REGINFO_SENTINEL
838};
839
34f90529
PM		 840static const ARMCPRegInfo strongarm_cp_reginfo[] = {
841 /* Ignore ReadBuffer accesses */
842 { .name = "C9_READBUFFER", .cp = 15, .crn = 9,
843 .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY,
844 .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_OVERRIDE,
845 .resetvalue = 0 },
846 REGINFO_SENTINEL
847};
848
81bdde9d
PM		 849static int mpidr_read(CPUARMState *env, const ARMCPRegInfo *ri,
850 uint64_t *value)
851{
852 uint32_t mpidr = env->cpu_index;
853 /* We don't support setting cluster ID ([8..11])
854 * so these bits always RAZ.
855 */
856 if (arm_feature(env, ARM_FEATURE_V7MP)) {
857 mpidr |= (1 << 31);
858 /* Cores which are uniprocessor (non-coherent)
859 * but still implement the MP extensions set
860 * bit 30. (For instance, A9UP.) However we do
861 * not currently model any of those cores.
862 */
863 }
864 *value = mpidr;
865 return 0;
866}
867
868static const ARMCPRegInfo mpidr_cp_reginfo[] = {
869 { .name = "MPIDR", .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 5,
870 .access = PL1_R, .readfn = mpidr_read },
871 REGINFO_SENTINEL
872};
873
7ac681cf
PM		 874static const ARMCPRegInfo lpae_cp_reginfo[] = {
875 /* NOP AMAIR0/1: the override is because these clash with tha rather
876 * broadly specified TLB_LOCKDOWN entry in the generic cp_reginfo.
877 */
878 { .name = "AMAIR0", .cp = 15, .crn = 10, .crm = 3, .opc1 = 0, .opc2 = 0,
879 .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_OVERRIDE,
880 .resetvalue = 0 },
881 { .name = "AMAIR1", .cp = 15, .crn = 10, .crm = 3, .opc1 = 0, .opc2 = 1,
882 .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_OVERRIDE,
883 .resetvalue = 0 },
f9fc619a
PM		 884 /* 64 bit access versions of the (dummy) debug registers */
885 { .name = "DBGDRAR", .cp = 14, .crm = 1, .opc1 = 0,
886 .access = PL0_R, .type = ARM_CP_CONST|ARM_CP_64BIT, .resetvalue = 0 },
887 { .name = "DBGDSAR", .cp = 14, .crm = 2, .opc1 = 0,
888 .access = PL0_R, .type = ARM_CP_CONST|ARM_CP_64BIT, .resetvalue = 0 },
7ac681cf
PM		 889 REGINFO_SENTINEL
890};
891
2771db27
PM		 892static int sctlr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
893{
894 env->cp15.c1_sys = value;
895 /* ??? Lots of these bits are not implemented. */
896 /* This may enable/disable the MMU, so do a TLB flush. */
897 tlb_flush(env, 1);
898 return 0;
899}
900
2ceb98c0
PM		 901void register_cp_regs_for_features(ARMCPU *cpu)
902{
903 /* Register all the coprocessor registers based on feature bits */
904 CPUARMState *env = &cpu->env;
905 if (arm_feature(env, ARM_FEATURE_M)) {
906 /* M profile has no coprocessor registers */
907 return;
908 }
909
e9aa6c21 910 define_arm_cp_regs(cpu, cp_reginfo);
7d57f408 911 if (arm_feature(env, ARM_FEATURE_V6)) {
8515a092
PM		 912 /* The ID registers all have impdef reset values */
913 ARMCPRegInfo v6_idregs[] = {
914 { .name = "ID_PFR0", .cp = 15, .crn = 0, .crm = 1,
915 .opc1 = 0, .opc2 = 0, .access = PL1_R, .type = ARM_CP_CONST,
916 .resetvalue = cpu->id_pfr0 },
917 { .name = "ID_PFR1", .cp = 15, .crn = 0, .crm = 1,
918 .opc1 = 0, .opc2 = 1, .access = PL1_R, .type = ARM_CP_CONST,
919 .resetvalue = cpu->id_pfr1 },
920 { .name = "ID_DFR0", .cp = 15, .crn = 0, .crm = 1,
921 .opc1 = 0, .opc2 = 2, .access = PL1_R, .type = ARM_CP_CONST,
922 .resetvalue = cpu->id_dfr0 },
923 { .name = "ID_AFR0", .cp = 15, .crn = 0, .crm = 1,
924 .opc1 = 0, .opc2 = 3, .access = PL1_R, .type = ARM_CP_CONST,
925 .resetvalue = cpu->id_afr0 },
926 { .name = "ID_MMFR0", .cp = 15, .crn = 0, .crm = 1,
927 .opc1 = 0, .opc2 = 4, .access = PL1_R, .type = ARM_CP_CONST,
928 .resetvalue = cpu->id_mmfr0 },
929 { .name = "ID_MMFR1", .cp = 15, .crn = 0, .crm = 1,
930 .opc1 = 0, .opc2 = 5, .access = PL1_R, .type = ARM_CP_CONST,
931 .resetvalue = cpu->id_mmfr1 },
932 { .name = "ID_MMFR2", .cp = 15, .crn = 0, .crm = 1,
933 .opc1 = 0, .opc2 = 6, .access = PL1_R, .type = ARM_CP_CONST,
934 .resetvalue = cpu->id_mmfr2 },
935 { .name = "ID_MMFR3", .cp = 15, .crn = 0, .crm = 1,
936 .opc1 = 0, .opc2 = 7, .access = PL1_R, .type = ARM_CP_CONST,
937 .resetvalue = cpu->id_mmfr3 },
938 { .name = "ID_ISAR0", .cp = 15, .crn = 0, .crm = 2,
939 .opc1 = 0, .opc2 = 0, .access = PL1_R, .type = ARM_CP_CONST,
940 .resetvalue = cpu->id_isar0 },
941 { .name = "ID_ISAR1", .cp = 15, .crn = 0, .crm = 2,
942 .opc1 = 0, .opc2 = 1, .access = PL1_R, .type = ARM_CP_CONST,
943 .resetvalue = cpu->id_isar1 },
944 { .name = "ID_ISAR2", .cp = 15, .crn = 0, .crm = 2,
945 .opc1 = 0, .opc2 = 2, .access = PL1_R, .type = ARM_CP_CONST,
946 .resetvalue = cpu->id_isar2 },
947 { .name = "ID_ISAR3", .cp = 15, .crn = 0, .crm = 2,
948 .opc1 = 0, .opc2 = 3, .access = PL1_R, .type = ARM_CP_CONST,
949 .resetvalue = cpu->id_isar3 },
950 { .name = "ID_ISAR4", .cp = 15, .crn = 0, .crm = 2,
951 .opc1 = 0, .opc2 = 4, .access = PL1_R, .type = ARM_CP_CONST,
952 .resetvalue = cpu->id_isar4 },
953 { .name = "ID_ISAR5", .cp = 15, .crn = 0, .crm = 2,
954 .opc1 = 0, .opc2 = 5, .access = PL1_R, .type = ARM_CP_CONST,
955 .resetvalue = cpu->id_isar5 },
956 /* 6..7 are as yet unallocated and must RAZ */
957 { .name = "ID_ISAR6", .cp = 15, .crn = 0, .crm = 2,
958 .opc1 = 0, .opc2 = 6, .access = PL1_R, .type = ARM_CP_CONST,
959 .resetvalue = 0 },
960 { .name = "ID_ISAR7", .cp = 15, .crn = 0, .crm = 2,
961 .opc1 = 0, .opc2 = 7, .access = PL1_R, .type = ARM_CP_CONST,
962 .resetvalue = 0 },
963 REGINFO_SENTINEL
964 };
965 define_arm_cp_regs(cpu, v6_idregs);
7d57f408
PM		 966 define_arm_cp_regs(cpu, v6_cp_reginfo);
967 } else {
968 define_arm_cp_regs(cpu, not_v6_cp_reginfo);
969 }
4d31c596
PM		 970 if (arm_feature(env, ARM_FEATURE_V6K)) {
971 define_arm_cp_regs(cpu, v6k_cp_reginfo);
972 }
e9aa6c21 973 if (arm_feature(env, ARM_FEATURE_V7)) {
200ac0ef
PM		 974 /* v7 performance monitor control register: same implementor
975 * field as main ID register, and we implement no event counters.
976 */
977 ARMCPRegInfo pmcr = {
978 .name = "PMCR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 0,
979 .access = PL0_RW, .resetvalue = cpu->midr & 0xff000000,
980 .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcr),
981 .readfn = pmreg_read, .writefn = pmcr_write
982 };
776d4e5c
PM		 983 ARMCPRegInfo clidr = {
984 .name = "CLIDR", .cp = 15, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 1,
985 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = cpu->clidr
986 };
200ac0ef 987 define_one_arm_cp_reg(cpu, &pmcr);
776d4e5c 988 define_one_arm_cp_reg(cpu, &clidr);
e9aa6c21 989 define_arm_cp_regs(cpu, v7_cp_reginfo);
7d57f408
PM		 990 } else {
991 define_arm_cp_regs(cpu, not_v7_cp_reginfo);
e9aa6c21 992 }
18032bec
PM		 993 if (arm_feature(env, ARM_FEATURE_MPU)) {
994 /* These are the MPU registers prior to PMSAv6. Any new
995 * PMSA core later than the ARM946 will require that we
996 * implement the PMSAv6 or PMSAv7 registers, which are
997 * completely different.
998 */
999 assert(!arm_feature(env, ARM_FEATURE_V6));
1000 define_arm_cp_regs(cpu, pmsav5_cp_reginfo);
1001 } else {
1002 define_arm_cp_regs(cpu, vmsa_cp_reginfo);
1003 }
c326b979
PM		 1004 if (arm_feature(env, ARM_FEATURE_THUMB2EE)) {
1005 define_arm_cp_regs(cpu, t2ee_cp_reginfo);
1006 }
6cc7a3ae
PM		 1007 if (arm_feature(env, ARM_FEATURE_GENERIC_TIMER)) {
1008 define_arm_cp_regs(cpu, generic_timer_cp_reginfo);
1009 }
4a501606
PM		 1010 if (arm_feature(env, ARM_FEATURE_VAPA)) {
1011 define_arm_cp_regs(cpu, vapa_cp_reginfo);
1012 }
c4804214
PM		 1013 if (arm_feature(env, ARM_FEATURE_CACHE_TEST_CLEAN)) {
1014 define_arm_cp_regs(cpu, cache_test_clean_cp_reginfo);
1015 }
1016 if (arm_feature(env, ARM_FEATURE_CACHE_DIRTY_REG)) {
1017 define_arm_cp_regs(cpu, cache_dirty_status_cp_reginfo);
1018 }
1019 if (arm_feature(env, ARM_FEATURE_CACHE_BLOCK_OPS)) {
1020 define_arm_cp_regs(cpu, cache_block_ops_cp_reginfo);
1021 }
18032bec
PM		 1022 if (arm_feature(env, ARM_FEATURE_OMAPCP)) {
1023 define_arm_cp_regs(cpu, omap_cp_reginfo);
1024 }
34f90529
PM		 1025 if (arm_feature(env, ARM_FEATURE_STRONGARM)) {
1026 define_arm_cp_regs(cpu, strongarm_cp_reginfo);
1027 }
1047b9d7
PM		 1028 if (arm_feature(env, ARM_FEATURE_XSCALE)) {
1029 define_arm_cp_regs(cpu, xscale_cp_reginfo);
1030 }
1031 if (arm_feature(env, ARM_FEATURE_DUMMY_C15_REGS)) {
1032 define_arm_cp_regs(cpu, dummy_c15_cp_reginfo);
1033 }
81bdde9d
PM		 1034 if (arm_feature(env, ARM_FEATURE_MPIDR)) {
1035 define_arm_cp_regs(cpu, mpidr_cp_reginfo);
1036 }
7ac681cf
PM		 1037 if (arm_feature(env, ARM_FEATURE_LPAE)) {
1038 define_arm_cp_regs(cpu, lpae_cp_reginfo);
1039 }
7884849c
PM		 1040 /* Slightly awkwardly, the OMAP and StrongARM cores need all of
1041 * cp15 crn=0 to be writes-ignored, whereas for other cores they should
1042 * be read-only (ie write causes UNDEF exception).
1043 */
1044 {
1045 ARMCPRegInfo id_cp_reginfo[] = {
1046 /* Note that the MIDR isn't a simple constant register because
1047 * of the TI925 behaviour where writes to another register can
1048 * cause the MIDR value to change.
1049 */
1050 { .name = "MIDR",
1051 .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 0,
1052 .access = PL1_R, .resetvalue = cpu->midr,
1053 .writefn = arm_cp_write_ignore,
1054 .fieldoffset = offsetof(CPUARMState, cp15.c0_cpuid) },
1055 { .name = "CTR",
1056 .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 1,
1057 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = cpu->ctr },
1058 { .name = "TCMTR",
1059 .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 2,
1060 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
1061 { .name = "TLBTR",
1062 .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 3,
1063 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
1064 /* crn = 0 op1 = 0 crm = 3..7 : currently unassigned; we RAZ. */
1065 { .name = "DUMMY",
1066 .cp = 15, .crn = 0, .crm = 3, .opc1 = 0, .opc2 = CP_ANY,
1067 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
1068 { .name = "DUMMY",
1069 .cp = 15, .crn = 0, .crm = 4, .opc1 = 0, .opc2 = CP_ANY,
1070 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
1071 { .name = "DUMMY",
1072 .cp = 15, .crn = 0, .crm = 5, .opc1 = 0, .opc2 = CP_ANY,
1073 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
1074 { .name = "DUMMY",
1075 .cp = 15, .crn = 0, .crm = 6, .opc1 = 0, .opc2 = CP_ANY,
1076 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
1077 { .name = "DUMMY",
1078 .cp = 15, .crn = 0, .crm = 7, .opc1 = 0, .opc2 = CP_ANY,
1079 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
1080 REGINFO_SENTINEL
1081 };
1082 ARMCPRegInfo crn0_wi_reginfo = {
1083 .name = "CRN0_WI", .cp = 15, .crn = 0, .crm = CP_ANY,
1084 .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_W,
1085 .type = ARM_CP_NOP | ARM_CP_OVERRIDE
1086 };
1087 if (arm_feature(env, ARM_FEATURE_OMAPCP) ||
1088 arm_feature(env, ARM_FEATURE_STRONGARM)) {
1089 ARMCPRegInfo *r;
1090 /* Register the blanket "writes ignored" value first to cover the
1091 * whole space. Then define the specific ID registers, but update
1092 * their access field to allow write access, so that they ignore
1093 * writes rather than causing them to UNDEF.
1094 */
1095 define_one_arm_cp_reg(cpu, &crn0_wi_reginfo);
1096 for (r = id_cp_reginfo; r->type != ARM_CP_SENTINEL; r++) {
1097 r->access = PL1_RW;
1098 define_one_arm_cp_reg(cpu, r);
1099 }
1100 } else {
1101 /* Just register the standard ID registers (read-only, meaning
1102 * that writes will UNDEF).
1103 */
1104 define_arm_cp_regs(cpu, id_cp_reginfo);
1105 }
1106 }
1107
2771db27
PM		 1108 if (arm_feature(env, ARM_FEATURE_AUXCR)) {
1109 ARMCPRegInfo auxcr = {
1110 .name = "AUXCR", .cp = 15, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 1,
1111 .access = PL1_RW, .type = ARM_CP_CONST,
1112 .resetvalue = cpu->reset_auxcr
1113 };
1114 define_one_arm_cp_reg(cpu, &auxcr);
1115 }
1116
1117 /* Generic registers whose values depend on the implementation */
1118 {
1119 ARMCPRegInfo sctlr = {
1120 .name = "SCTLR", .cp = 15, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 0,
1121 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c1_sys),
1122 .writefn = sctlr_write, .resetvalue = cpu->reset_sctlr
1123 };
1124 if (arm_feature(env, ARM_FEATURE_XSCALE)) {
1125 /* Normally we would always end the TB on an SCTLR write, but Linux
1126 * arch/arm/mach-pxa/sleep.S expects two instructions following
1127 * an MMU enable to execute from cache. Imitate this behaviour.
1128 */
1129 sctlr.type |= ARM_CP_SUPPRESS_TB_END;
1130 }
1131 define_one_arm_cp_reg(cpu, &sctlr);
1132 }
2ceb98c0
PM		 1133}
1134
778c3a06 1135ARMCPU *cpu_arm_init(const char *cpu_model)
40f137e1 1136{
dec9c2d4 1137 ARMCPU *cpu;
40f137e1 1138 CPUARMState *env;
b26eefb6 1139 static int inited = 0;
40f137e1 1140
777dc784 1141 if (!object_class_by_name(cpu_model)) {
aaed909a 1142 return NULL;
777dc784
PM		 1143 }
1144 cpu = ARM_CPU(object_new(cpu_model));
dec9c2d4 1145 env = &cpu->env;
777dc784 1146 env->cpu_model_str = cpu_model;
581be094 1147 arm_cpu_realize(cpu);
777dc784 1148
f4fc247b 1149 if (tcg_enabled() && !inited) {
b26eefb6
PB		 1150 inited = 1;
1151 arm_translate_init();
1152 }
1153
df90dadb 1154 cpu_reset(CPU(cpu));
56aebc89
PB		 1155 if (arm_feature(env, ARM_FEATURE_NEON)) {
1156 gdb_register_coprocessor(env, vfp_gdb_get_reg, vfp_gdb_set_reg,
1157 51, "arm-neon.xml", 0);
1158 } else if (arm_feature(env, ARM_FEATURE_VFP3)) {
1159 gdb_register_coprocessor(env, vfp_gdb_get_reg, vfp_gdb_set_reg,
1160 35, "arm-vfp3.xml", 0);
1161 } else if (arm_feature(env, ARM_FEATURE_VFP)) {
1162 gdb_register_coprocessor(env, vfp_gdb_get_reg, vfp_gdb_set_reg,
1163 19, "arm-vfp.xml", 0);
1164 }
0bf46a40 1165 qemu_init_vcpu(env);
778c3a06 1166 return cpu;
40f137e1
PB		 1167}
1168
777dc784
PM		 1169typedef struct ARMCPUListState {
1170 fprintf_function cpu_fprintf;
1171 FILE *file;
1172} ARMCPUListState;
3371d272 1173
777dc784
PM		 1174/* Sort alphabetically by type name, except for "any". */
1175static gint arm_cpu_list_compare(gconstpointer a, gconstpointer b)
5adb4839 1176{
777dc784
PM		 1177 ObjectClass *class_a = (ObjectClass *)a;
1178 ObjectClass *class_b = (ObjectClass *)b;
1179 const char *name_a, *name_b;
5adb4839 1180
777dc784
PM		 1181 name_a = object_class_get_name(class_a);
1182 name_b = object_class_get_name(class_b);
1183 if (strcmp(name_a, "any") == 0) {
1184 return 1;
1185 } else if (strcmp(name_b, "any") == 0) {
1186 return -1;
1187 } else {
1188 return strcmp(name_a, name_b);
5adb4839
PB		 1189 }
1190}
1191
777dc784 1192static void arm_cpu_list_entry(gpointer data, gpointer user_data)
40f137e1 1193{
777dc784
PM		 1194 ObjectClass *oc = data;
1195 ARMCPUListState *s = user_data;
3371d272 1196
777dc784
PM		 1197 (*s->cpu_fprintf)(s->file, " %s\n",
1198 object_class_get_name(oc));
1199}
1200
1201void arm_cpu_list(FILE *f, fprintf_function cpu_fprintf)
1202{
1203 ARMCPUListState s = {
1204 .file = f,
1205 .cpu_fprintf = cpu_fprintf,
1206 };
1207 GSList *list;
1208
1209 list = object_class_get_list(TYPE_ARM_CPU, false);
1210 list = g_slist_sort(list, arm_cpu_list_compare);
1211 (*cpu_fprintf)(f, "Available CPUs:\n");
1212 g_slist_foreach(list, arm_cpu_list_entry, &s);
1213 g_slist_free(list);
40f137e1
PB		 1214}
1215
4b6a83fb
PM		 1216void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu,
1217 const ARMCPRegInfo *r, void *opaque)
1218{
1219 /* Define implementations of coprocessor registers.
1220 * We store these in a hashtable because typically
1221 * there are less than 150 registers in a space which
1222 * is 16*16*16*8*8 = 262144 in size.
1223 * Wildcarding is supported for the crm, opc1 and opc2 fields.
1224 * If a register is defined twice then the second definition is
1225 * used, so this can be used to define some generic registers and
1226 * then override them with implementation specific variations.
1227 * At least one of the original and the second definition should
1228 * include ARM_CP_OVERRIDE in its type bits -- this is just a guard
1229 * against accidental use.
1230 */
1231 int crm, opc1, opc2;
1232 int crmmin = (r->crm == CP_ANY) ? 0 : r->crm;
1233 int crmmax = (r->crm == CP_ANY) ? 15 : r->crm;
1234 int opc1min = (r->opc1 == CP_ANY) ? 0 : r->opc1;
1235 int opc1max = (r->opc1 == CP_ANY) ? 7 : r->opc1;
1236 int opc2min = (r->opc2 == CP_ANY) ? 0 : r->opc2;
1237 int opc2max = (r->opc2 == CP_ANY) ? 7 : r->opc2;
1238 /* 64 bit registers have only CRm and Opc1 fields */
1239 assert(!((r->type & ARM_CP_64BIT) && (r->opc2 || r->crn)));
1240 /* Check that the register definition has enough info to handle
1241 * reads and writes if they are permitted.
1242 */
1243 if (!(r->type & (ARM_CP_SPECIAL|ARM_CP_CONST))) {
1244 if (r->access & PL3_R) {
1245 assert(r->fieldoffset || r->readfn);
1246 }
1247 if (r->access & PL3_W) {
1248 assert(r->fieldoffset || r->writefn);
1249 }
1250 }
1251 /* Bad type field probably means missing sentinel at end of reg list */
1252 assert(cptype_valid(r->type));
1253 for (crm = crmmin; crm <= crmmax; crm++) {
1254 for (opc1 = opc1min; opc1 <= opc1max; opc1++) {
1255 for (opc2 = opc2min; opc2 <= opc2max; opc2++) {
1256 uint32_t *key = g_new(uint32_t, 1);
1257 ARMCPRegInfo *r2 = g_memdup(r, sizeof(ARMCPRegInfo));
1258 int is64 = (r->type & ARM_CP_64BIT) ? 1 : 0;
1259 *key = ENCODE_CP_REG(r->cp, is64, r->crn, crm, opc1, opc2);
1260 r2->opaque = opaque;
1261 /* Make sure reginfo passed to helpers for wildcarded regs
1262 * has the correct crm/opc1/opc2 for this reg, not CP_ANY:
1263 */
1264 r2->crm = crm;
1265 r2->opc1 = opc1;
1266 r2->opc2 = opc2;
1267 /* Overriding of an existing definition must be explicitly
1268 * requested.
1269 */
1270 if (!(r->type & ARM_CP_OVERRIDE)) {
1271 ARMCPRegInfo *oldreg;
1272 oldreg = g_hash_table_lookup(cpu->cp_regs, key);
1273 if (oldreg && !(oldreg->type & ARM_CP_OVERRIDE)) {
1274 fprintf(stderr, "Register redefined: cp=%d %d bit "
1275 "crn=%d crm=%d opc1=%d opc2=%d, "
1276 "was %s, now %s\n", r2->cp, 32 + 32 * is64,
1277 r2->crn, r2->crm, r2->opc1, r2->opc2,
1278 oldreg->name, r2->name);
1279 assert(0);
1280 }
1281 }
1282 g_hash_table_insert(cpu->cp_regs, key, r2);
1283 }
1284 }
1285 }
1286}
1287
1288void define_arm_cp_regs_with_opaque(ARMCPU *cpu,
1289 const ARMCPRegInfo *regs, void *opaque)
1290{
1291 /* Define a whole list of registers */
1292 const ARMCPRegInfo *r;
1293 for (r = regs; r->type != ARM_CP_SENTINEL; r++) {
1294 define_one_arm_cp_reg_with_opaque(cpu, r, opaque);
1295 }
1296}
1297
1298const ARMCPRegInfo *get_arm_cp_reginfo(ARMCPU *cpu, uint32_t encoded_cp)
1299{
1300 return g_hash_table_lookup(cpu->cp_regs, &encoded_cp);
1301}
1302
1303int arm_cp_write_ignore(CPUARMState *env, const ARMCPRegInfo *ri,
1304 uint64_t value)
1305{
1306 /* Helper coprocessor write function for write-ignore registers */
1307 return 0;
1308}
1309
1310int arm_cp_read_zero(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t *value)
1311{
1312 /* Helper coprocessor write function for read-as-zero registers */
1313 *value = 0;
1314 return 0;
1315}
1316
0ecb72a5 1317static int bad_mode_switch(CPUARMState *env, int mode)
37064a8b
PM		 1318{
1319 /* Return true if it is not valid for us to switch to
1320 * this CPU mode (ie all the UNPREDICTABLE cases in
1321 * the ARM ARM CPSRWriteByInstr pseudocode).
1322 */
1323 switch (mode) {
1324 case ARM_CPU_MODE_USR:
1325 case ARM_CPU_MODE_SYS:
1326 case ARM_CPU_MODE_SVC:
1327 case ARM_CPU_MODE_ABT:
1328 case ARM_CPU_MODE_UND:
1329 case ARM_CPU_MODE_IRQ:
1330 case ARM_CPU_MODE_FIQ:
1331 return 0;
1332 default:
1333 return 1;
1334 }
1335}
1336
2f4a40e5
AZ		 1337uint32_t cpsr_read(CPUARMState *env)
1338{
1339 int ZF;
6fbe23d5
PB		 1340 ZF = (env->ZF == 0);
1341 return env->uncached_cpsr | (env->NF & 0x80000000) | (ZF << 30) |
2f4a40e5
AZ		 1342 (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27)
1343 | (env->thumb << 5) | ((env->condexec_bits & 3) << 25)
1344 | ((env->condexec_bits & 0xfc) << 8)
1345 | (env->GE << 16);
1346}
1347
1348void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask)
1349{
2f4a40e5 1350 if (mask & CPSR_NZCV) {
6fbe23d5
PB		 1351 env->ZF = (~val) & CPSR_Z;
1352 env->NF = val;
2f4a40e5
AZ		 1353 env->CF = (val >> 29) & 1;
1354 env->VF = (val << 3) & 0x80000000;
1355 }
1356 if (mask & CPSR_Q)
1357 env->QF = ((val & CPSR_Q) != 0);
1358 if (mask & CPSR_T)
1359 env->thumb = ((val & CPSR_T) != 0);
1360 if (mask & CPSR_IT_0_1) {
1361 env->condexec_bits &= ~3;
1362 env->condexec_bits |= (val >> 25) & 3;
1363 }
1364 if (mask & CPSR_IT_2_7) {
1365 env->condexec_bits &= 3;
1366 env->condexec_bits |= (val >> 8) & 0xfc;
1367 }
1368 if (mask & CPSR_GE) {
1369 env->GE = (val >> 16) & 0xf;
1370 }
1371
1372 if ((env->uncached_cpsr ^ val) & mask & CPSR_M) {
37064a8b
PM		 1373 if (bad_mode_switch(env, val & CPSR_M)) {
1374 /* Attempt to switch to an invalid mode: this is UNPREDICTABLE.
1375 * We choose to ignore the attempt and leave the CPSR M field
1376 * untouched.
1377 */
1378 mask &= ~CPSR_M;
1379 } else {
1380 switch_mode(env, val & CPSR_M);
1381 }
2f4a40e5
AZ		 1382 }
1383 mask &= ~CACHED_CPSR_BITS;
1384 env->uncached_cpsr = (env->uncached_cpsr & ~mask) | (val & mask);
1385}
1386
b26eefb6
PB		 1387/* Sign/zero extend */
1388uint32_t HELPER(sxtb16)(uint32_t x)
1389{
1390 uint32_t res;
1391 res = (uint16_t)(int8_t)x;
1392 res |= (uint32_t)(int8_t)(x >> 16) << 16;
1393 return res;
1394}
1395
1396uint32_t HELPER(uxtb16)(uint32_t x)
1397{
1398 uint32_t res;
1399 res = (uint16_t)(uint8_t)x;
1400 res |= (uint32_t)(uint8_t)(x >> 16) << 16;
1401 return res;
1402}
1403
f51bbbfe
PB		 1404uint32_t HELPER(clz)(uint32_t x)
1405{
7bbcb0af 1406 return clz32(x);
f51bbbfe
PB		 1407}
1408
3670669c
PB		 1409int32_t HELPER(sdiv)(int32_t num, int32_t den)
1410{
1411 if (den == 0)
1412 return 0;
686eeb93
AJ		 1413 if (num == INT_MIN && den == -1)
1414 return INT_MIN;
3670669c
PB		 1415 return num / den;
1416}
1417
1418uint32_t HELPER(udiv)(uint32_t num, uint32_t den)
1419{
1420 if (den == 0)
1421 return 0;
1422 return num / den;
1423}
1424
1425uint32_t HELPER(rbit)(uint32_t x)
1426{
1427 x = ((x & 0xff000000) >> 24)
1428 | ((x & 0x00ff0000) >> 8)
1429 | ((x & 0x0000ff00) << 8)
1430 | ((x & 0x000000ff) << 24);
1431 x = ((x & 0xf0f0f0f0) >> 4)
1432 | ((x & 0x0f0f0f0f) << 4);
1433 x = ((x & 0x88888888) >> 3)
1434 | ((x & 0x44444444) >> 1)
1435 | ((x & 0x22222222) << 1)
1436 | ((x & 0x11111111) << 3);
1437 return x;
1438}
1439
ad69471c
PB		 1440uint32_t HELPER(abs)(uint32_t x)
1441{
1442 return ((int32_t)x < 0) ? -x : x;
1443}
1444
5fafdf24 1445#if defined(CONFIG_USER_ONLY)
b5ff1b31 1446
0ecb72a5 1447void do_interrupt (CPUARMState *env)
b5ff1b31
FB		 1448{
1449 env->exception_index = -1;
1450}
1451
0ecb72a5 1452int cpu_arm_handle_mmu_fault (CPUARMState *env, target_ulong address, int rw,
97b348e7 1453 int mmu_idx)
b5ff1b31
FB		 1454{
1455 if (rw == 2) {
1456 env->exception_index = EXCP_PREFETCH_ABORT;
1457 env->cp15.c6_insn = address;
1458 } else {
1459 env->exception_index = EXCP_DATA_ABORT;
1460 env->cp15.c6_data = address;
1461 }
1462 return 1;
1463}
1464
9ee6e8bb 1465/* These should probably raise undefined insn exceptions. */
0ecb72a5 1466void HELPER(v7m_msr)(CPUARMState *env, uint32_t reg, uint32_t val)
9ee6e8bb
PB		 1467{
1468 cpu_abort(env, "v7m_mrs %d\n", reg);
1469}
1470
0ecb72a5 1471uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg)
9ee6e8bb
PB		 1472{
1473 cpu_abort(env, "v7m_mrs %d\n", reg);
1474 return 0;
1475}
1476
0ecb72a5 1477void switch_mode(CPUARMState *env, int mode)
b5ff1b31
FB		 1478{
1479 if (mode != ARM_CPU_MODE_USR)
1480 cpu_abort(env, "Tried to switch out of user mode\n");
1481}
1482
0ecb72a5 1483void HELPER(set_r13_banked)(CPUARMState *env, uint32_t mode, uint32_t val)
9ee6e8bb
PB		 1484{
1485 cpu_abort(env, "banked r13 write\n");
1486}
1487
0ecb72a5 1488uint32_t HELPER(get_r13_banked)(CPUARMState *env, uint32_t mode)
9ee6e8bb
PB		 1489{
1490 cpu_abort(env, "banked r13 read\n");
1491 return 0;
1492}
1493
b5ff1b31
FB		 1494#else
1495
1496/* Map CPU modes onto saved register banks. */
0ecb72a5 1497static inline int bank_number(CPUARMState *env, int mode)
b5ff1b31
FB		 1498{
1499 switch (mode) {
1500 case ARM_CPU_MODE_USR:
1501 case ARM_CPU_MODE_SYS:
1502 return 0;
1503 case ARM_CPU_MODE_SVC:
1504 return 1;
1505 case ARM_CPU_MODE_ABT:
1506 return 2;
1507 case ARM_CPU_MODE_UND:
1508 return 3;
1509 case ARM_CPU_MODE_IRQ:
1510 return 4;
1511 case ARM_CPU_MODE_FIQ:
1512 return 5;
1513 }
1b9e01c1 1514 cpu_abort(env, "Bad mode %x\n", mode);
b5ff1b31
FB		 1515 return -1;
1516}
1517
0ecb72a5 1518void switch_mode(CPUARMState *env, int mode)
b5ff1b31
FB		 1519{
1520 int old_mode;
1521 int i;
1522
1523 old_mode = env->uncached_cpsr & CPSR_M;
1524 if (mode == old_mode)
1525 return;
1526
1527 if (old_mode == ARM_CPU_MODE_FIQ) {
1528 memcpy (env->fiq_regs, env->regs + 8, 5 * sizeof(uint32_t));
8637c67f 1529 memcpy (env->regs + 8, env->usr_regs, 5 * sizeof(uint32_t));
b5ff1b31
FB		 1530 } else if (mode == ARM_CPU_MODE_FIQ) {
1531 memcpy (env->usr_regs, env->regs + 8, 5 * sizeof(uint32_t));
8637c67f 1532 memcpy (env->regs + 8, env->fiq_regs, 5 * sizeof(uint32_t));
b5ff1b31
FB		 1533 }
1534
1b9e01c1 1535 i = bank_number(env, old_mode);
b5ff1b31
FB		 1536 env->banked_r13[i] = env->regs[13];
1537 env->banked_r14[i] = env->regs[14];
1538 env->banked_spsr[i] = env->spsr;
1539
1b9e01c1 1540 i = bank_number(env, mode);
b5ff1b31
FB		 1541 env->regs[13] = env->banked_r13[i];
1542 env->regs[14] = env->banked_r14[i];
1543 env->spsr = env->banked_spsr[i];
1544}
1545
9ee6e8bb
PB		 1546static void v7m_push(CPUARMState *env, uint32_t val)
1547{
1548 env->regs[13] -= 4;
1549 stl_phys(env->regs[13], val);
1550}
1551
1552static uint32_t v7m_pop(CPUARMState *env)
1553{
1554 uint32_t val;
1555 val = ldl_phys(env->regs[13]);
1556 env->regs[13] += 4;
1557 return val;
1558}
1559
1560/* Switch to V7M main or process stack pointer. */
1561static void switch_v7m_sp(CPUARMState *env, int process)
1562{
1563 uint32_t tmp;
1564 if (env->v7m.current_sp != process) {
1565 tmp = env->v7m.other_sp;
1566 env->v7m.other_sp = env->regs[13];
1567 env->regs[13] = tmp;
1568 env->v7m.current_sp = process;
1569 }
1570}
1571
1572static void do_v7m_exception_exit(CPUARMState *env)
1573{
1574 uint32_t type;
1575 uint32_t xpsr;
1576
1577 type = env->regs[15];
1578 if (env->v7m.exception != 0)
983fe826 1579 armv7m_nvic_complete_irq(env->nvic, env->v7m.exception);
9ee6e8bb
PB		 1580
1581 /* Switch to the target stack. */
1582 switch_v7m_sp(env, (type & 4) != 0);
1583 /* Pop registers. */
1584 env->regs[0] = v7m_pop(env);
1585 env->regs[1] = v7m_pop(env);
1586 env->regs[2] = v7m_pop(env);
1587 env->regs[3] = v7m_pop(env);
1588 env->regs[12] = v7m_pop(env);
1589 env->regs[14] = v7m_pop(env);
1590 env->regs[15] = v7m_pop(env);
1591 xpsr = v7m_pop(env);
1592 xpsr_write(env, xpsr, 0xfffffdff);
1593 /* Undo stack alignment. */
1594 if (xpsr & 0x200)
1595 env->regs[13] |= 4;
1596 /* ??? The exception return type specifies Thread/Handler mode. However
1597 this is also implied by the xPSR value. Not sure what to do
1598 if there is a mismatch. */
1599 /* ??? Likewise for mismatches between the CONTROL register and the stack
1600 pointer. */
1601}
1602
2b3ea315 1603static void do_interrupt_v7m(CPUARMState *env)
9ee6e8bb
PB		 1604{
1605 uint32_t xpsr = xpsr_read(env);
1606 uint32_t lr;
1607 uint32_t addr;
1608
1609 lr = 0xfffffff1;
1610 if (env->v7m.current_sp)
1611 lr |= 4;
1612 if (env->v7m.exception == 0)
1613 lr |= 8;
1614
1615 /* For exceptions we just mark as pending on the NVIC, and let that
1616 handle it. */
1617 /* TODO: Need to escalate if the current priority is higher than the
1618 one we're raising. */
1619 switch (env->exception_index) {
1620 case EXCP_UDEF:
983fe826 1621 armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE);
9ee6e8bb
PB		 1622 return;
1623 case EXCP_SWI:
1624 env->regs[15] += 2;
983fe826 1625 armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_SVC);
9ee6e8bb
PB		 1626 return;
1627 case EXCP_PREFETCH_ABORT:
1628 case EXCP_DATA_ABORT:
983fe826 1629 armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_MEM);
9ee6e8bb
PB		 1630 return;
1631 case EXCP_BKPT:
2ad207d4
PB		 1632 if (semihosting_enabled) {
1633 int nr;
d8fd2954 1634 nr = arm_lduw_code(env->regs[15], env->bswap_code) & 0xff;
2ad207d4
PB		 1635 if (nr == 0xab) {
1636 env->regs[15] += 2;
1637 env->regs[0] = do_arm_semihosting(env);
1638 return;
1639 }
1640 }
983fe826 1641 armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_DEBUG);
9ee6e8bb
PB		 1642 return;
1643 case EXCP_IRQ:
983fe826 1644 env->v7m.exception = armv7m_nvic_acknowledge_irq(env->nvic);
9ee6e8bb
PB		 1645 break;
1646 case EXCP_EXCEPTION_EXIT:
1647 do_v7m_exception_exit(env);
1648 return;
1649 default:
1650 cpu_abort(env, "Unhandled exception 0x%x\n", env->exception_index);
1651 return; /* Never happens. Keep compiler happy. */
1652 }
1653
1654 /* Align stack pointer. */
1655 /* ??? Should only do this if Configuration Control Register
1656 STACKALIGN bit is set. */
1657 if (env->regs[13] & 4) {
ab19b0ec 1658 env->regs[13] -= 4;
9ee6e8bb
PB		 1659 xpsr |= 0x200;
1660 }
6c95676b 1661 /* Switch to the handler mode. */
9ee6e8bb
PB		 1662 v7m_push(env, xpsr);
1663 v7m_push(env, env->regs[15]);
1664 v7m_push(env, env->regs[14]);
1665 v7m_push(env, env->regs[12]);
1666 v7m_push(env, env->regs[3]);
1667 v7m_push(env, env->regs[2]);
1668 v7m_push(env, env->regs[1]);
1669 v7m_push(env, env->regs[0]);
1670 switch_v7m_sp(env, 0);
c98d174c
PM		 1671 /* Clear IT bits */
1672 env->condexec_bits = 0;
9ee6e8bb
PB		 1673 env->regs[14] = lr;
1674 addr = ldl_phys(env->v7m.vecbase + env->v7m.exception * 4);
1675 env->regs[15] = addr & 0xfffffffe;
1676 env->thumb = addr & 1;
1677}
1678
b5ff1b31
FB		 1679/* Handle a CPU exception. */
1680void do_interrupt(CPUARMState *env)
1681{
1682 uint32_t addr;
1683 uint32_t mask;
1684 int new_mode;
1685 uint32_t offset;
1686
9ee6e8bb
PB		 1687 if (IS_M(env)) {
1688 do_interrupt_v7m(env);
1689 return;
1690 }
b5ff1b31
FB		 1691 /* TODO: Vectored interrupt controller. */
1692 switch (env->exception_index) {
1693 case EXCP_UDEF:
1694 new_mode = ARM_CPU_MODE_UND;
1695 addr = 0x04;
1696 mask = CPSR_I;
1697 if (env->thumb)
1698 offset = 2;
1699 else
1700 offset = 4;
1701 break;
1702 case EXCP_SWI:
8e71621f
PB		 1703 if (semihosting_enabled) {
1704 /* Check for semihosting interrupt. */
1705 if (env->thumb) {
d8fd2954 1706 mask = arm_lduw_code(env->regs[15] - 2, env->bswap_code) & 0xff;
8e71621f 1707 } else {
d8fd2954
PB		 1708 mask = arm_ldl_code(env->regs[15] - 4, env->bswap_code)
1709 & 0xffffff;
8e71621f
PB		 1710 }
1711 /* Only intercept calls from privileged modes, to provide some
1712 semblance of security. */
1713 if (((mask == 0x123456 && !env->thumb)
1714 || (mask == 0xab && env->thumb))
1715 && (env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR) {
1716 env->regs[0] = do_arm_semihosting(env);
1717 return;
1718 }
1719 }
b5ff1b31
FB		 1720 new_mode = ARM_CPU_MODE_SVC;
1721 addr = 0x08;
1722 mask = CPSR_I;
601d70b9 1723 /* The PC already points to the next instruction. */
b5ff1b31
FB		 1724 offset = 0;
1725 break;
06c949e6 1726 case EXCP_BKPT:
9ee6e8bb 1727 /* See if this is a semihosting syscall. */
2ad207d4 1728 if (env->thumb && semihosting_enabled) {
d8fd2954 1729 mask = arm_lduw_code(env->regs[15], env->bswap_code) & 0xff;
9ee6e8bb
PB		 1730 if (mask == 0xab
1731 && (env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR) {
1732 env->regs[15] += 2;
1733 env->regs[0] = do_arm_semihosting(env);
1734 return;
1735 }
1736 }
81c05daf 1737 env->cp15.c5_insn = 2;
9ee6e8bb
PB		 1738 /* Fall through to prefetch abort. */
1739 case EXCP_PREFETCH_ABORT:
b5ff1b31
FB		 1740 new_mode = ARM_CPU_MODE_ABT;
1741 addr = 0x0c;
1742 mask = CPSR_A | CPSR_I;
1743 offset = 4;
1744 break;
1745 case EXCP_DATA_ABORT:
1746 new_mode = ARM_CPU_MODE_ABT;
1747 addr = 0x10;
1748 mask = CPSR_A | CPSR_I;
1749 offset = 8;
1750 break;
1751 case EXCP_IRQ:
1752 new_mode = ARM_CPU_MODE_IRQ;
1753 addr = 0x18;
1754 /* Disable IRQ and imprecise data aborts. */
1755 mask = CPSR_A | CPSR_I;
1756 offset = 4;
1757 break;
1758 case EXCP_FIQ:
1759 new_mode = ARM_CPU_MODE_FIQ;
1760 addr = 0x1c;
1761 /* Disable FIQ, IRQ and imprecise data aborts. */
1762 mask = CPSR_A | CPSR_I | CPSR_F;
1763 offset = 4;
1764 break;
1765 default:
1766 cpu_abort(env, "Unhandled exception 0x%x\n", env->exception_index);
1767 return; /* Never happens. Keep compiler happy. */
1768 }
1769 /* High vectors. */
1770 if (env->cp15.c1_sys & (1 << 13)) {
1771 addr += 0xffff0000;
1772 }
1773 switch_mode (env, new_mode);
1774 env->spsr = cpsr_read(env);
9ee6e8bb
PB		 1775 /* Clear IT bits. */
1776 env->condexec_bits = 0;
30a8cac1 1777 /* Switch to the new mode, and to the correct instruction set. */
6d7e6326 1778 env->uncached_cpsr = (env->uncached_cpsr & ~CPSR_M) | new_mode;
b5ff1b31 1779 env->uncached_cpsr |= mask;
be5e7a76
DES		 1780 /* this is a lie, as the was no c1_sys on V4T/V5, but who cares
1781 * and we should just guard the thumb mode on V4 */
1782 if (arm_feature(env, ARM_FEATURE_V4T)) {
1783 env->thumb = (env->cp15.c1_sys & (1 << 30)) != 0;
1784 }
b5ff1b31
FB		 1785 env->regs[14] = env->regs[15] + offset;
1786 env->regs[15] = addr;
1787 env->interrupt_request |= CPU_INTERRUPT_EXITTB;
1788}
1789
1790/* Check section/page access permissions.
1791 Returns the page protection flags, or zero if the access is not
1792 permitted. */
0ecb72a5 1793static inline int check_ap(CPUARMState *env, int ap, int domain_prot,
dd4ebc2e 1794 int access_type, int is_user)
b5ff1b31 1795{
9ee6e8bb
PB		 1796 int prot_ro;
1797
dd4ebc2e 1798 if (domain_prot == 3) {
b5ff1b31 1799 return PAGE_READ | PAGE_WRITE;
dd4ebc2e 1800 }
b5ff1b31 1801
9ee6e8bb
PB		 1802 if (access_type == 1)
1803 prot_ro = 0;
1804 else
1805 prot_ro = PAGE_READ;
1806
b5ff1b31
FB		 1807 switch (ap) {
1808 case 0:
78600320 1809 if (access_type == 1)
b5ff1b31
FB		 1810 return 0;
1811 switch ((env->cp15.c1_sys >> 8) & 3) {
1812 case 1:
1813 return is_user ? 0 : PAGE_READ;
1814 case 2:
1815 return PAGE_READ;
1816 default:
1817 return 0;
1818 }
1819 case 1:
1820 return is_user ? 0 : PAGE_READ | PAGE_WRITE;
1821 case 2:
1822 if (is_user)
9ee6e8bb 1823 return prot_ro;
b5ff1b31
FB		 1824 else
1825 return PAGE_READ | PAGE_WRITE;
1826 case 3:
1827 return PAGE_READ | PAGE_WRITE;
d4934d18 1828 case 4: /* Reserved. */
9ee6e8bb
PB		 1829 return 0;
1830 case 5:
1831 return is_user ? 0 : prot_ro;
1832 case 6:
1833 return prot_ro;
d4934d18 1834 case 7:
0ab06d83 1835 if (!arm_feature (env, ARM_FEATURE_V6K))
d4934d18
PB		 1836 return 0;
1837 return prot_ro;
b5ff1b31
FB		 1838 default:
1839 abort();
1840 }
1841}
1842
0ecb72a5 1843static uint32_t get_level1_table_address(CPUARMState *env, uint32_t address)
b2fa1797
PB		 1844{
1845 uint32_t table;
1846
1847 if (address & env->cp15.c2_mask)
1848 table = env->cp15.c2_base1 & 0xffffc000;
1849 else
1850 table = env->cp15.c2_base0 & env->cp15.c2_base_mask;
1851
1852 table |= (address >> 18) & 0x3ffc;
1853 return table;
1854}
1855
0ecb72a5 1856static int get_phys_addr_v5(CPUARMState *env, uint32_t address, int access_type,
d4c430a8
PB		 1857 int is_user, uint32_t *phys_ptr, int *prot,
1858 target_ulong *page_size)
b5ff1b31
FB		 1859{
1860 int code;
1861 uint32_t table;
1862 uint32_t desc;
1863 int type;
1864 int ap;
1865 int domain;
dd4ebc2e 1866 int domain_prot;
b5ff1b31
FB		 1867 uint32_t phys_addr;
1868
9ee6e8bb
PB		 1869 /* Pagetable walk. */
1870 /* Lookup l1 descriptor. */
b2fa1797 1871 table = get_level1_table_address(env, address);
9ee6e8bb
PB		 1872 desc = ldl_phys(table);
1873 type = (desc & 3);
dd4ebc2e
JCD		 1874 domain = (desc >> 5) & 0x0f;
1875 domain_prot = (env->cp15.c3 >> (domain * 2)) & 3;
9ee6e8bb 1876 if (type == 0) {
601d70b9 1877 /* Section translation fault. */
9ee6e8bb
PB		 1878 code = 5;
1879 goto do_fault;
1880 }
dd4ebc2e 1881 if (domain_prot == 0 || domain_prot == 2) {
9ee6e8bb
PB		 1882 if (type == 2)
1883 code = 9; /* Section domain fault. */
1884 else
1885 code = 11; /* Page domain fault. */
1886 goto do_fault;
1887 }
1888 if (type == 2) {
1889 /* 1Mb section. */
1890 phys_addr = (desc & 0xfff00000) | (address & 0x000fffff);
1891 ap = (desc >> 10) & 3;
1892 code = 13;
d4c430a8 1893 *page_size = 1024 * 1024;
9ee6e8bb
PB		 1894 } else {
1895 /* Lookup l2 entry. */
1896 if (type == 1) {
1897 /* Coarse pagetable. */
1898 table = (desc & 0xfffffc00) | ((address >> 10) & 0x3fc);
1899 } else {
1900 /* Fine pagetable. */
1901 table = (desc & 0xfffff000) | ((address >> 8) & 0xffc);
1902 }
1903 desc = ldl_phys(table);
1904 switch (desc & 3) {
1905 case 0: /* Page translation fault. */
1906 code = 7;
1907 goto do_fault;
1908 case 1: /* 64k page. */
1909 phys_addr = (desc & 0xffff0000) | (address & 0xffff);
1910 ap = (desc >> (4 + ((address >> 13) & 6))) & 3;
d4c430a8 1911 *page_size = 0x10000;
ce819861 1912 break;
9ee6e8bb
PB		 1913 case 2: /* 4k page. */
1914 phys_addr = (desc & 0xfffff000) | (address & 0xfff);
1915 ap = (desc >> (4 + ((address >> 13) & 6))) & 3;
d4c430a8 1916 *page_size = 0x1000;
ce819861 1917 break;
9ee6e8bb
PB		 1918 case 3: /* 1k page. */
1919 if (type == 1) {
1920 if (arm_feature(env, ARM_FEATURE_XSCALE)) {
1921 phys_addr = (desc & 0xfffff000) | (address & 0xfff);
1922 } else {
1923 /* Page translation fault. */
1924 code = 7;
1925 goto do_fault;
1926 }
1927 } else {
1928 phys_addr = (desc & 0xfffffc00) | (address & 0x3ff);
1929 }
1930 ap = (desc >> 4) & 3;
d4c430a8 1931 *page_size = 0x400;
ce819861
PB		 1932 break;
1933 default:
9ee6e8bb
PB		 1934 /* Never happens, but compiler isn't smart enough to tell. */
1935 abort();
ce819861 1936 }
9ee6e8bb
PB		 1937 code = 15;
1938 }
dd4ebc2e 1939 *prot = check_ap(env, ap, domain_prot, access_type, is_user);
9ee6e8bb
PB		 1940 if (!*prot) {
1941 /* Access permission fault. */
1942 goto do_fault;
1943 }
3ad493fc 1944 *prot |= PAGE_EXEC;
9ee6e8bb
PB		 1945 *phys_ptr = phys_addr;
1946 return 0;
1947do_fault:
1948 return code | (domain << 4);
1949}
1950
0ecb72a5 1951static int get_phys_addr_v6(CPUARMState *env, uint32_t address, int access_type,
d4c430a8
PB		 1952 int is_user, uint32_t *phys_ptr, int *prot,
1953 target_ulong *page_size)
9ee6e8bb
PB		 1954{
1955 int code;
1956 uint32_t table;
1957 uint32_t desc;
1958 uint32_t xn;
de9b05b8 1959 uint32_t pxn = 0;
9ee6e8bb
PB		 1960 int type;
1961 int ap;
de9b05b8 1962 int domain = 0;
dd4ebc2e 1963 int domain_prot;
9ee6e8bb
PB		 1964 uint32_t phys_addr;
1965
1966 /* Pagetable walk. */
1967 /* Lookup l1 descriptor. */
b2fa1797 1968 table = get_level1_table_address(env, address);
9ee6e8bb
PB		 1969 desc = ldl_phys(table);
1970 type = (desc & 3);
de9b05b8
PM		 1971 if (type == 0 || (type == 3 && !arm_feature(env, ARM_FEATURE_PXN))) {
1972 /* Section translation fault, or attempt to use the encoding
1973 * which is Reserved on implementations without PXN.
1974 */
9ee6e8bb 1975 code = 5;
9ee6e8bb 1976 goto do_fault;
de9b05b8
PM		 1977 }
1978 if ((type == 1) || !(desc & (1 << 18))) {
1979 /* Page or Section. */
dd4ebc2e 1980 domain = (desc >> 5) & 0x0f;
9ee6e8bb 1981 }
dd4ebc2e
JCD		 1982 domain_prot = (env->cp15.c3 >> (domain * 2)) & 3;
1983 if (domain_prot == 0 || domain_prot == 2) {
de9b05b8 1984 if (type != 1) {
9ee6e8bb 1985 code = 9; /* Section domain fault. */
de9b05b8 1986 } else {
9ee6e8bb 1987 code = 11; /* Page domain fault. */
de9b05b8 1988 }
9ee6e8bb
PB		 1989 goto do_fault;
1990 }
de9b05b8 1991 if (type != 1) {
9ee6e8bb
PB		 1992 if (desc & (1 << 18)) {
1993 /* Supersection. */
1994 phys_addr = (desc & 0xff000000) | (address & 0x00ffffff);
d4c430a8 1995 *page_size = 0x1000000;
b5ff1b31 1996 } else {
9ee6e8bb
PB		 1997 /* Section. */
1998 phys_addr = (desc & 0xfff00000) | (address & 0x000fffff);
d4c430a8 1999 *page_size = 0x100000;
b5ff1b31 2000 }
9ee6e8bb
PB		 2001 ap = ((desc >> 10) & 3) | ((desc >> 13) & 4);
2002 xn = desc & (1 << 4);
de9b05b8 2003 pxn = desc & 1;
9ee6e8bb
PB		 2004 code = 13;
2005 } else {
de9b05b8
PM		 2006 if (arm_feature(env, ARM_FEATURE_PXN)) {
2007 pxn = (desc >> 2) & 1;
2008 }
9ee6e8bb
PB		 2009 /* Lookup l2 entry. */
2010 table = (desc & 0xfffffc00) | ((address >> 10) & 0x3fc);
2011 desc = ldl_phys(table);
2012 ap = ((desc >> 4) & 3) | ((desc >> 7) & 4);
2013 switch (desc & 3) {
2014 case 0: /* Page translation fault. */
2015 code = 7;
b5ff1b31 2016 goto do_fault;
9ee6e8bb
PB		 2017 case 1: /* 64k page. */
2018 phys_addr = (desc & 0xffff0000) | (address & 0xffff);
2019 xn = desc & (1 << 15);
d4c430a8 2020 *page_size = 0x10000;
9ee6e8bb
PB		 2021 break;
2022 case 2: case 3: /* 4k page. */
2023 phys_addr = (desc & 0xfffff000) | (address & 0xfff);
2024 xn = desc & 1;
d4c430a8 2025 *page_size = 0x1000;
9ee6e8bb
PB		 2026 break;
2027 default:
2028 /* Never happens, but compiler isn't smart enough to tell. */
2029 abort();
b5ff1b31 2030 }
9ee6e8bb
PB		 2031 code = 15;
2032 }
dd4ebc2e 2033 if (domain_prot == 3) {
c0034328
JR		 2034 *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
2035 } else {
de9b05b8
PM		 2036 if (pxn && !is_user) {
2037 xn = 1;
2038 }
c0034328
JR		 2039 if (xn && access_type == 2)
2040 goto do_fault;
9ee6e8bb 2041
c0034328
JR		 2042 /* The simplified model uses AP[0] as an access control bit. */
2043 if ((env->cp15.c1_sys & (1 << 29)) && (ap & 1) == 0) {
2044 /* Access flag fault. */
2045 code = (code == 15) ? 6 : 3;
2046 goto do_fault;
2047 }
dd4ebc2e 2048 *prot = check_ap(env, ap, domain_prot, access_type, is_user);
c0034328
JR		 2049 if (!*prot) {
2050 /* Access permission fault. */
2051 goto do_fault;
2052 }
2053 if (!xn) {
2054 *prot |= PAGE_EXEC;
2055 }
3ad493fc 2056 }
9ee6e8bb 2057 *phys_ptr = phys_addr;
b5ff1b31
FB		 2058 return 0;
2059do_fault:
2060 return code | (domain << 4);
2061}
2062
0ecb72a5 2063static int get_phys_addr_mpu(CPUARMState *env, uint32_t address, int access_type,
9ee6e8bb
PB		 2064 int is_user, uint32_t *phys_ptr, int *prot)
2065{
2066 int n;
2067 uint32_t mask;
2068 uint32_t base;
2069
2070 *phys_ptr = address;
2071 for (n = 7; n >= 0; n--) {
2072 base = env->cp15.c6_region[n];
2073 if ((base & 1) == 0)
2074 continue;
2075 mask = 1 << ((base >> 1) & 0x1f);
2076 /* Keep this shift separate from the above to avoid an
2077 (undefined) << 32. */
2078 mask = (mask << 1) - 1;
2079 if (((base ^ address) & ~mask) == 0)
2080 break;
2081 }
2082 if (n < 0)
2083 return 2;
2084
2085 if (access_type == 2) {
2086 mask = env->cp15.c5_insn;
2087 } else {
2088 mask = env->cp15.c5_data;
2089 }
2090 mask = (mask >> (n * 4)) & 0xf;
2091 switch (mask) {
2092 case 0:
2093 return 1;
2094 case 1:
2095 if (is_user)
2096 return 1;
2097 *prot = PAGE_READ | PAGE_WRITE;
2098 break;
2099 case 2:
2100 *prot = PAGE_READ;
2101 if (!is_user)
2102 *prot |= PAGE_WRITE;
2103 break;
2104 case 3:
2105 *prot = PAGE_READ | PAGE_WRITE;
2106 break;
2107 case 5:
2108 if (is_user)
2109 return 1;
2110 *prot = PAGE_READ;
2111 break;
2112 case 6:
2113 *prot = PAGE_READ;
2114 break;
2115 default:
2116 /* Bad permission. */
2117 return 1;
2118 }
3ad493fc 2119 *prot |= PAGE_EXEC;
9ee6e8bb
PB		 2120 return 0;
2121}
2122
0ecb72a5 2123static inline int get_phys_addr(CPUARMState *env, uint32_t address,
9ee6e8bb 2124 int access_type, int is_user,
d4c430a8
PB		 2125 uint32_t *phys_ptr, int *prot,
2126 target_ulong *page_size)
9ee6e8bb
PB		 2127{
2128 /* Fast Context Switch Extension. */
2129 if (address < 0x02000000)
2130 address += env->cp15.c13_fcse;
2131
2132 if ((env->cp15.c1_sys & 1) == 0) {
2133 /* MMU/MPU disabled. */
2134 *phys_ptr = address;
3ad493fc 2135 *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
d4c430a8 2136 *page_size = TARGET_PAGE_SIZE;
9ee6e8bb
PB		 2137 return 0;
2138 } else if (arm_feature(env, ARM_FEATURE_MPU)) {
d4c430a8 2139 *page_size = TARGET_PAGE_SIZE;
9ee6e8bb
PB		 2140 return get_phys_addr_mpu(env, address, access_type, is_user, phys_ptr,
2141 prot);
2142 } else if (env->cp15.c1_sys & (1 << 23)) {
2143 return get_phys_addr_v6(env, address, access_type, is_user, phys_ptr,
d4c430a8 2144 prot, page_size);
9ee6e8bb
PB		 2145 } else {
2146 return get_phys_addr_v5(env, address, access_type, is_user, phys_ptr,
d4c430a8 2147 prot, page_size);
9ee6e8bb
PB		 2148 }
2149}
2150
0ecb72a5 2151int cpu_arm_handle_mmu_fault (CPUARMState *env, target_ulong address,
97b348e7 2152 int access_type, int mmu_idx)
b5ff1b31
FB		 2153{
2154 uint32_t phys_addr;
d4c430a8 2155 target_ulong page_size;
b5ff1b31 2156 int prot;
6ebbf390 2157 int ret, is_user;
b5ff1b31 2158
6ebbf390 2159 is_user = mmu_idx == MMU_USER_IDX;
d4c430a8
PB		 2160 ret = get_phys_addr(env, address, access_type, is_user, &phys_addr, &prot,
2161 &page_size);
b5ff1b31
FB		 2162 if (ret == 0) {
2163 /* Map a single [sub]page. */
2164 phys_addr &= ~(uint32_t)0x3ff;
2165 address &= ~(uint32_t)0x3ff;
3ad493fc 2166 tlb_set_page (env, address, phys_addr, prot, mmu_idx, page_size);
d4c430a8 2167 return 0;
b5ff1b31
FB		 2168 }
2169
2170 if (access_type == 2) {
2171 env->cp15.c5_insn = ret;
2172 env->cp15.c6_insn = address;
2173 env->exception_index = EXCP_PREFETCH_ABORT;
2174 } else {
2175 env->cp15.c5_data = ret;
9ee6e8bb
PB		 2176 if (access_type == 1 && arm_feature(env, ARM_FEATURE_V6))
2177 env->cp15.c5_data |= (1 << 11);
b5ff1b31
FB		 2178 env->cp15.c6_data = address;
2179 env->exception_index = EXCP_DATA_ABORT;
2180 }
2181 return 1;
2182}
2183
0ecb72a5 2184target_phys_addr_t cpu_get_phys_page_debug(CPUARMState *env, target_ulong addr)
b5ff1b31
FB		 2185{
2186 uint32_t phys_addr;
d4c430a8 2187 target_ulong page_size;
b5ff1b31
FB		 2188 int prot;
2189 int ret;
2190
d4c430a8 2191 ret = get_phys_addr(env, addr, 0, 0, &phys_addr, &prot, &page_size);
b5ff1b31
FB		 2192
2193 if (ret != 0)
2194 return -1;
2195
2196 return phys_addr;
2197}
2198
0ecb72a5 2199void HELPER(set_r13_banked)(CPUARMState *env, uint32_t mode, uint32_t val)
9ee6e8bb 2200{
39ea3d4e
PM		 2201 if ((env->uncached_cpsr & CPSR_M) == mode) {
2202 env->regs[13] = val;
2203 } else {
1b9e01c1 2204 env->banked_r13[bank_number(env, mode)] = val;
39ea3d4e 2205 }
9ee6e8bb
PB		 2206}
2207
0ecb72a5 2208uint32_t HELPER(get_r13_banked)(CPUARMState *env, uint32_t mode)
9ee6e8bb 2209{
39ea3d4e
PM		 2210 if ((env->uncached_cpsr & CPSR_M) == mode) {
2211 return env->regs[13];
2212 } else {
1b9e01c1 2213 return env->banked_r13[bank_number(env, mode)];
39ea3d4e 2214 }
9ee6e8bb
PB		 2215}
2216
0ecb72a5 2217uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg)
9ee6e8bb
PB		 2218{
2219 switch (reg) {
2220 case 0: /* APSR */
2221 return xpsr_read(env) & 0xf8000000;
2222 case 1: /* IAPSR */
2223 return xpsr_read(env) & 0xf80001ff;
2224 case 2: /* EAPSR */
2225 return xpsr_read(env) & 0xff00fc00;
2226 case 3: /* xPSR */
2227 return xpsr_read(env) & 0xff00fdff;
2228 case 5: /* IPSR */
2229 return xpsr_read(env) & 0x000001ff;
2230 case 6: /* EPSR */
2231 return xpsr_read(env) & 0x0700fc00;
2232 case 7: /* IEPSR */
2233 return xpsr_read(env) & 0x0700edff;
2234 case 8: /* MSP */
2235 return env->v7m.current_sp ? env->v7m.other_sp : env->regs[13];
2236 case 9: /* PSP */
2237 return env->v7m.current_sp ? env->regs[13] : env->v7m.other_sp;
2238 case 16: /* PRIMASK */
2239 return (env->uncached_cpsr & CPSR_I) != 0;
82845826
SH		 2240 case 17: /* BASEPRI */
2241 case 18: /* BASEPRI_MAX */
9ee6e8bb 2242 return env->v7m.basepri;
82845826
SH		 2243 case 19: /* FAULTMASK */
2244 return (env->uncached_cpsr & CPSR_F) != 0;
9ee6e8bb
PB		 2245 case 20: /* CONTROL */
2246 return env->v7m.control;
2247 default:
2248 /* ??? For debugging only. */
2249 cpu_abort(env, "Unimplemented system register read (%d)\n", reg);
2250 return 0;
2251 }
2252}
2253
0ecb72a5 2254void HELPER(v7m_msr)(CPUARMState *env, uint32_t reg, uint32_t val)
9ee6e8bb
PB		 2255{
2256 switch (reg) {
2257 case 0: /* APSR */
2258 xpsr_write(env, val, 0xf8000000);
2259 break;
2260 case 1: /* IAPSR */
2261 xpsr_write(env, val, 0xf8000000);
2262 break;
2263 case 2: /* EAPSR */
2264 xpsr_write(env, val, 0xfe00fc00);
2265 break;
2266 case 3: /* xPSR */
2267 xpsr_write(env, val, 0xfe00fc00);
2268 break;
2269 case 5: /* IPSR */
2270 /* IPSR bits are readonly. */
2271 break;
2272 case 6: /* EPSR */
2273 xpsr_write(env, val, 0x0600fc00);
2274 break;
2275 case 7: /* IEPSR */
2276 xpsr_write(env, val, 0x0600fc00);
2277 break;
2278 case 8: /* MSP */
2279 if (env->v7m.current_sp)
2280 env->v7m.other_sp = val;
2281 else
2282 env->regs[13] = val;
2283 break;
2284 case 9: /* PSP */
2285 if (env->v7m.current_sp)
2286 env->regs[13] = val;
2287 else
2288 env->v7m.other_sp = val;
2289 break;
2290 case 16: /* PRIMASK */
2291 if (val & 1)
2292 env->uncached_cpsr |= CPSR_I;
2293 else
2294 env->uncached_cpsr &= ~CPSR_I;
2295 break;
82845826 2296 case 17: /* BASEPRI */
9ee6e8bb
PB		 2297 env->v7m.basepri = val & 0xff;
2298 break;
82845826 2299 case 18: /* BASEPRI_MAX */
9ee6e8bb
PB		 2300 val &= 0xff;
2301 if (val != 0 && (val < env->v7m.basepri || env->v7m.basepri == 0))
2302 env->v7m.basepri = val;
2303 break;
82845826
SH		 2304 case 19: /* FAULTMASK */
2305 if (val & 1)
2306 env->uncached_cpsr |= CPSR_F;
2307 else
2308 env->uncached_cpsr &= ~CPSR_F;
2309 break;
9ee6e8bb
PB		 2310 case 20: /* CONTROL */
2311 env->v7m.control = val & 3;
2312 switch_v7m_sp(env, (val & 2) != 0);
2313 break;
2314 default:
2315 /* ??? For debugging only. */
2316 cpu_abort(env, "Unimplemented system register write (%d)\n", reg);
2317 return;
2318 }
2319}
2320
b5ff1b31 2321#endif
6ddbc6e4
PB		 2322
2323/* Note that signed overflow is undefined in C. The following routines are
2324 careful to use unsigned types where modulo arithmetic is required.
2325 Failure to do so _will_ break on newer gcc. */
2326
2327/* Signed saturating arithmetic. */
2328
1654b2d6 2329/* Perform 16-bit signed saturating addition. */
6ddbc6e4
PB		 2330static inline uint16_t add16_sat(uint16_t a, uint16_t b)
2331{
2332 uint16_t res;
2333
2334 res = a + b;
2335 if (((res ^ a) & 0x8000) && !((a ^ b) & 0x8000)) {
2336 if (a & 0x8000)
2337 res = 0x8000;
2338 else
2339 res = 0x7fff;
2340 }
2341 return res;
2342}
2343
1654b2d6 2344/* Perform 8-bit signed saturating addition. */
6ddbc6e4
PB		 2345static inline uint8_t add8_sat(uint8_t a, uint8_t b)
2346{
2347 uint8_t res;
2348
2349 res = a + b;
2350 if (((res ^ a) & 0x80) && !((a ^ b) & 0x80)) {
2351 if (a & 0x80)
2352 res = 0x80;
2353 else
2354 res = 0x7f;
2355 }
2356 return res;
2357}
2358
1654b2d6 2359/* Perform 16-bit signed saturating subtraction. */
6ddbc6e4
PB		 2360static inline uint16_t sub16_sat(uint16_t a, uint16_t b)
2361{
2362 uint16_t res;
2363
2364 res = a - b;
2365 if (((res ^ a) & 0x8000) && ((a ^ b) & 0x8000)) {
2366 if (a & 0x8000)
2367 res = 0x8000;
2368 else
2369 res = 0x7fff;
2370 }
2371 return res;
2372}
2373
1654b2d6 2374/* Perform 8-bit signed saturating subtraction. */
6ddbc6e4
PB		 2375static inline uint8_t sub8_sat(uint8_t a, uint8_t b)
2376{
2377 uint8_t res;
2378
2379 res = a - b;
2380 if (((res ^ a) & 0x80) && ((a ^ b) & 0x80)) {
2381 if (a & 0x80)
2382 res = 0x80;
2383 else
2384 res = 0x7f;
2385 }
2386 return res;
2387}
2388
2389#define ADD16(a, b, n) RESULT(add16_sat(a, b), n, 16);
2390#define SUB16(a, b, n) RESULT(sub16_sat(a, b), n, 16);
2391#define ADD8(a, b, n) RESULT(add8_sat(a, b), n, 8);
2392#define SUB8(a, b, n) RESULT(sub8_sat(a, b), n, 8);
2393#define PFX q
2394
2395#include "op_addsub.h"
2396
2397/* Unsigned saturating arithmetic. */
460a09c1 2398static inline uint16_t add16_usat(uint16_t a, uint16_t b)
6ddbc6e4
PB		 2399{
2400 uint16_t res;
2401 res = a + b;
2402 if (res < a)
2403 res = 0xffff;
2404 return res;
2405}
2406
460a09c1 2407static inline uint16_t sub16_usat(uint16_t a, uint16_t b)
6ddbc6e4 2408{
4c4fd3f8 2409 if (a > b)
6ddbc6e4
PB		 2410 return a - b;
2411 else
2412 return 0;
2413}
2414
2415static inline uint8_t add8_usat(uint8_t a, uint8_t b)
2416{
2417 uint8_t res;
2418 res = a + b;
2419 if (res < a)
2420 res = 0xff;
2421 return res;
2422}
2423
2424static inline uint8_t sub8_usat(uint8_t a, uint8_t b)
2425{
4c4fd3f8 2426 if (a > b)
6ddbc6e4
PB		 2427 return a - b;
2428 else
2429 return 0;
2430}
2431
2432#define ADD16(a, b, n) RESULT(add16_usat(a, b), n, 16);
2433#define SUB16(a, b, n) RESULT(sub16_usat(a, b), n, 16);
2434#define ADD8(a, b, n) RESULT(add8_usat(a, b), n, 8);
2435#define SUB8(a, b, n) RESULT(sub8_usat(a, b), n, 8);
2436#define PFX uq
2437
2438#include "op_addsub.h"
2439
2440/* Signed modulo arithmetic. */
2441#define SARITH16(a, b, n, op) do { \
2442 int32_t sum; \
db6e2e65 2443 sum = (int32_t)(int16_t)(a) op (int32_t)(int16_t)(b); \
6ddbc6e4
PB		 2444 RESULT(sum, n, 16); \
2445 if (sum >= 0) \
2446 ge |= 3 << (n * 2); \
2447 } while(0)
2448
2449#define SARITH8(a, b, n, op) do { \
2450 int32_t sum; \
db6e2e65 2451 sum = (int32_t)(int8_t)(a) op (int32_t)(int8_t)(b); \
6ddbc6e4
PB		 2452 RESULT(sum, n, 8); \
2453 if (sum >= 0) \
2454 ge |= 1 << n; \
2455 } while(0)
2456
2457
2458#define ADD16(a, b, n) SARITH16(a, b, n, +)
2459#define SUB16(a, b, n) SARITH16(a, b, n, -)
2460#define ADD8(a, b, n) SARITH8(a, b, n, +)
2461#define SUB8(a, b, n) SARITH8(a, b, n, -)
2462#define PFX s
2463#define ARITH_GE
2464
2465#include "op_addsub.h"
2466
2467/* Unsigned modulo arithmetic. */
2468#define ADD16(a, b, n) do { \
2469 uint32_t sum; \
2470 sum = (uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b); \
2471 RESULT(sum, n, 16); \
a87aa10b 2472 if ((sum >> 16) == 1) \
6ddbc6e4
PB		 2473 ge |= 3 << (n * 2); \
2474 } while(0)
2475
2476#define ADD8(a, b, n) do { \
2477 uint32_t sum; \
2478 sum = (uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b); \
2479 RESULT(sum, n, 8); \
a87aa10b
AZ		 2480 if ((sum >> 8) == 1) \
2481 ge |= 1 << n; \
6ddbc6e4
PB		 2482 } while(0)
2483
2484#define SUB16(a, b, n) do { \
2485 uint32_t sum; \
2486 sum = (uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b); \
2487 RESULT(sum, n, 16); \
2488 if ((sum >> 16) == 0) \
2489 ge |= 3 << (n * 2); \
2490 } while(0)
2491
2492#define SUB8(a, b, n) do { \
2493 uint32_t sum; \
2494 sum = (uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b); \
2495 RESULT(sum, n, 8); \
2496 if ((sum >> 8) == 0) \
a87aa10b 2497 ge |= 1 << n; \
6ddbc6e4
PB		 2498 } while(0)
2499
2500#define PFX u
2501#define ARITH_GE
2502
2503#include "op_addsub.h"
2504
2505/* Halved signed arithmetic. */
2506#define ADD16(a, b, n) \
2507 RESULT(((int32_t)(int16_t)(a) + (int32_t)(int16_t)(b)) >> 1, n, 16)
2508#define SUB16(a, b, n) \
2509 RESULT(((int32_t)(int16_t)(a) - (int32_t)(int16_t)(b)) >> 1, n, 16)
2510#define ADD8(a, b, n) \
2511 RESULT(((int32_t)(int8_t)(a) + (int32_t)(int8_t)(b)) >> 1, n, 8)
2512#define SUB8(a, b, n) \
2513 RESULT(((int32_t)(int8_t)(a) - (int32_t)(int8_t)(b)) >> 1, n, 8)
2514#define PFX sh
2515
2516#include "op_addsub.h"
2517
2518/* Halved unsigned arithmetic. */
2519#define ADD16(a, b, n) \
2520 RESULT(((uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b)) >> 1, n, 16)
2521#define SUB16(a, b, n) \
2522 RESULT(((uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b)) >> 1, n, 16)
2523#define ADD8(a, b, n) \
2524 RESULT(((uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b)) >> 1, n, 8)
2525#define SUB8(a, b, n) \
2526 RESULT(((uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b)) >> 1, n, 8)
2527#define PFX uh
2528
2529#include "op_addsub.h"
2530
2531static inline uint8_t do_usad(uint8_t a, uint8_t b)
2532{
2533 if (a > b)
2534 return a - b;
2535 else
2536 return b - a;
2537}
2538
2539/* Unsigned sum of absolute byte differences. */
2540uint32_t HELPER(usad8)(uint32_t a, uint32_t b)
2541{
2542 uint32_t sum;
2543 sum = do_usad(a, b);
2544 sum += do_usad(a >> 8, b >> 8);
2545 sum += do_usad(a >> 16, b >>16);
2546 sum += do_usad(a >> 24, b >> 24);
2547 return sum;
2548}
2549
2550/* For ARMv6 SEL instruction. */
2551uint32_t HELPER(sel_flags)(uint32_t flags, uint32_t a, uint32_t b)
2552{
2553 uint32_t mask;
2554
2555 mask = 0;
2556 if (flags & 1)
2557 mask |= 0xff;
2558 if (flags & 2)
2559 mask |= 0xff00;
2560 if (flags & 4)
2561 mask |= 0xff0000;
2562 if (flags & 8)
2563 mask |= 0xff000000;
2564 return (a & mask) | (b & ~mask);
2565}
2566
5e3f878a
PB		 2567uint32_t HELPER(logicq_cc)(uint64_t val)
2568{
2569 return (val >> 32) | (val != 0);
2570}
4373f3ce
PB		 2571
2572/* VFP support. We follow the convention used for VFP instrunctions:
2573 Single precition routines have a "s" suffix, double precision a
2574 "d" suffix. */
2575
2576/* Convert host exception flags to vfp form. */
2577static inline int vfp_exceptbits_from_host(int host_bits)
2578{
2579 int target_bits = 0;
2580
2581 if (host_bits & float_flag_invalid)
2582 target_bits |= 1;
2583 if (host_bits & float_flag_divbyzero)
2584 target_bits |= 2;
2585 if (host_bits & float_flag_overflow)
2586 target_bits |= 4;
36802b6b 2587 if (host_bits & (float_flag_underflow | float_flag_output_denormal))
4373f3ce
PB		 2588 target_bits |= 8;
2589 if (host_bits & float_flag_inexact)
2590 target_bits |= 0x10;
cecd8504
PM		 2591 if (host_bits & float_flag_input_denormal)
2592 target_bits |= 0x80;
4373f3ce
PB		 2593 return target_bits;
2594}
2595
0ecb72a5 2596uint32_t HELPER(vfp_get_fpscr)(CPUARMState *env)
4373f3ce
PB		 2597{
2598 int i;
2599 uint32_t fpscr;
2600
2601 fpscr = (env->vfp.xregs[ARM_VFP_FPSCR] & 0xffc8ffff)
2602 | (env->vfp.vec_len << 16)
2603 | (env->vfp.vec_stride << 20);
2604 i = get_float_exception_flags(&env->vfp.fp_status);
3a492f3a 2605 i |= get_float_exception_flags(&env->vfp.standard_fp_status);
4373f3ce
PB		 2606 fpscr |= vfp_exceptbits_from_host(i);
2607 return fpscr;
2608}
2609
0ecb72a5 2610uint32_t vfp_get_fpscr(CPUARMState *env)
01653295
PM		 2611{
2612 return HELPER(vfp_get_fpscr)(env);
2613}
2614
4373f3ce
PB		 2615/* Convert vfp exception flags to target form. */
2616static inline int vfp_exceptbits_to_host(int target_bits)
2617{
2618 int host_bits = 0;
2619
2620 if (target_bits & 1)
2621 host_bits |= float_flag_invalid;
2622 if (target_bits & 2)
2623 host_bits |= float_flag_divbyzero;
2624 if (target_bits & 4)
2625 host_bits |= float_flag_overflow;
2626 if (target_bits & 8)
2627 host_bits |= float_flag_underflow;
2628 if (target_bits & 0x10)
2629 host_bits |= float_flag_inexact;
cecd8504
PM		 2630 if (target_bits & 0x80)
2631 host_bits |= float_flag_input_denormal;
4373f3ce
PB		 2632 return host_bits;
2633}
2634
0ecb72a5 2635void HELPER(vfp_set_fpscr)(CPUARMState *env, uint32_t val)
4373f3ce
PB		 2636{
2637 int i;
2638 uint32_t changed;
2639
2640 changed = env->vfp.xregs[ARM_VFP_FPSCR];
2641 env->vfp.xregs[ARM_VFP_FPSCR] = (val & 0xffc8ffff);
2642 env->vfp.vec_len = (val >> 16) & 7;
2643 env->vfp.vec_stride = (val >> 20) & 3;
2644
2645 changed ^= val;
2646 if (changed & (3 << 22)) {
2647 i = (val >> 22) & 3;
2648 switch (i) {
2649 case 0:
2650 i = float_round_nearest_even;
2651 break;
2652 case 1:
2653 i = float_round_up;
2654 break;
2655 case 2:
2656 i = float_round_down;
2657 break;
2658 case 3:
2659 i = float_round_to_zero;
2660 break;
2661 }
2662 set_float_rounding_mode(i, &env->vfp.fp_status);
2663 }
cecd8504 2664 if (changed & (1 << 24)) {
fe76d976 2665 set_flush_to_zero((val & (1 << 24)) != 0, &env->vfp.fp_status);
cecd8504
PM		 2666 set_flush_inputs_to_zero((val & (1 << 24)) != 0, &env->vfp.fp_status);
2667 }
5c7908ed
PB		 2668 if (changed & (1 << 25))
2669 set_default_nan_mode((val & (1 << 25)) != 0, &env->vfp.fp_status);
4373f3ce 2670
b12c390b 2671 i = vfp_exceptbits_to_host(val);
4373f3ce 2672 set_float_exception_flags(i, &env->vfp.fp_status);
3a492f3a 2673 set_float_exception_flags(0, &env->vfp.standard_fp_status);
4373f3ce
PB		 2674}
2675
0ecb72a5 2676void vfp_set_fpscr(CPUARMState *env, uint32_t val)
01653295
PM		 2677{
2678 HELPER(vfp_set_fpscr)(env, val);
2679}
2680
4373f3ce
PB		 2681#define VFP_HELPER(name, p) HELPER(glue(glue(vfp_,name),p))
2682
2683#define VFP_BINOP(name) \
ae1857ec 2684float32 VFP_HELPER(name, s)(float32 a, float32 b, void *fpstp) \
4373f3ce 2685{ \
ae1857ec
PM		 2686 float_status *fpst = fpstp; \
2687 return float32_ ## name(a, b, fpst); \
4373f3ce 2688} \
ae1857ec 2689float64 VFP_HELPER(name, d)(float64 a, float64 b, void *fpstp) \
4373f3ce 2690{ \
ae1857ec
PM		 2691 float_status *fpst = fpstp; \
2692 return float64_ ## name(a, b, fpst); \
4373f3ce
PB		 2693}
2694VFP_BINOP(add)
2695VFP_BINOP(sub)
2696VFP_BINOP(mul)
2697VFP_BINOP(div)
2698#undef VFP_BINOP
2699
2700float32 VFP_HELPER(neg, s)(float32 a)
2701{
2702 return float32_chs(a);
2703}
2704
2705float64 VFP_HELPER(neg, d)(float64 a)
2706{
66230e0d 2707 return float64_chs(a);
4373f3ce
PB		 2708}
2709
2710float32 VFP_HELPER(abs, s)(float32 a)
2711{
2712 return float32_abs(a);
2713}
2714
2715float64 VFP_HELPER(abs, d)(float64 a)
2716{
66230e0d 2717 return float64_abs(a);
4373f3ce
PB		 2718}
2719
0ecb72a5 2720float32 VFP_HELPER(sqrt, s)(float32 a, CPUARMState *env)
4373f3ce
PB		 2721{
2722 return float32_sqrt(a, &env->vfp.fp_status);
2723}
2724
0ecb72a5 2725float64 VFP_HELPER(sqrt, d)(float64 a, CPUARMState *env)
4373f3ce
PB		 2726{
2727 return float64_sqrt(a, &env->vfp.fp_status);
2728}
2729
2730/* XXX: check quiet/signaling case */
2731#define DO_VFP_cmp(p, type) \
0ecb72a5 2732void VFP_HELPER(cmp, p)(type a, type b, CPUARMState *env) \
4373f3ce
PB		 2733{ \
2734 uint32_t flags; \
2735 switch(type ## _compare_quiet(a, b, &env->vfp.fp_status)) { \
2736 case 0: flags = 0x6; break; \
2737 case -1: flags = 0x8; break; \
2738 case 1: flags = 0x2; break; \
2739 default: case 2: flags = 0x3; break; \
2740 } \
2741 env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \
2742 | (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \
2743} \
0ecb72a5 2744void VFP_HELPER(cmpe, p)(type a, type b, CPUARMState *env) \
4373f3ce
PB		 2745{ \
2746 uint32_t flags; \
2747 switch(type ## _compare(a, b, &env->vfp.fp_status)) { \
2748 case 0: flags = 0x6; break; \
2749 case -1: flags = 0x8; break; \
2750 case 1: flags = 0x2; break; \
2751 default: case 2: flags = 0x3; break; \
2752 } \
2753 env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \
2754 | (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \
2755}
2756DO_VFP_cmp(s, float32)
2757DO_VFP_cmp(d, float64)
2758#undef DO_VFP_cmp
2759
5500b06c 2760/* Integer to float and float to integer conversions */
4373f3ce 2761
5500b06c
PM		 2762#define CONV_ITOF(name, fsz, sign) \
2763 float##fsz HELPER(name)(uint32_t x, void *fpstp) \
2764{ \
2765 float_status *fpst = fpstp; \
85836979 2766 return sign##int32_to_##float##fsz((sign##int32_t)x, fpst); \
4373f3ce
PB		 2767}
2768
5500b06c
PM		 2769#define CONV_FTOI(name, fsz, sign, round) \
2770uint32_t HELPER(name)(float##fsz x, void *fpstp) \
2771{ \
2772 float_status *fpst = fpstp; \
2773 if (float##fsz##_is_any_nan(x)) { \
2774 float_raise(float_flag_invalid, fpst); \
2775 return 0; \
2776 } \
2777 return float##fsz##_to_##sign##int32##round(x, fpst); \
4373f3ce
PB		 2778}
2779
5500b06c
PM		 2780#define FLOAT_CONVS(name, p, fsz, sign) \
2781CONV_ITOF(vfp_##name##to##p, fsz, sign) \
2782CONV_FTOI(vfp_to##name##p, fsz, sign, ) \
2783CONV_FTOI(vfp_to##name##z##p, fsz, sign, _round_to_zero)
4373f3ce 2784
5500b06c
PM		 2785FLOAT_CONVS(si, s, 32, )
2786FLOAT_CONVS(si, d, 64, )
2787FLOAT_CONVS(ui, s, 32, u)
2788FLOAT_CONVS(ui, d, 64, u)
4373f3ce 2789
5500b06c
PM		 2790#undef CONV_ITOF
2791#undef CONV_FTOI
2792#undef FLOAT_CONVS
4373f3ce
PB		 2793
2794/* floating point conversion */
0ecb72a5 2795float64 VFP_HELPER(fcvtd, s)(float32 x, CPUARMState *env)
4373f3ce 2796{
2d627737
PM		 2797 float64 r = float32_to_float64(x, &env->vfp.fp_status);
2798 /* ARM requires that S<->D conversion of any kind of NaN generates
2799 * a quiet NaN by forcing the most significant frac bit to 1.
2800 */
2801 return float64_maybe_silence_nan(r);
4373f3ce
PB		 2802}
2803
0ecb72a5 2804float32 VFP_HELPER(fcvts, d)(float64 x, CPUARMState *env)
4373f3ce 2805{
2d627737
PM		 2806 float32 r = float64_to_float32(x, &env->vfp.fp_status);
2807 /* ARM requires that S<->D conversion of any kind of NaN generates
2808 * a quiet NaN by forcing the most significant frac bit to 1.
2809 */
2810 return float32_maybe_silence_nan(r);
4373f3ce
PB		 2811}
2812
2813/* VFP3 fixed point conversion. */
622465e1 2814#define VFP_CONV_FIX(name, p, fsz, itype, sign) \
5500b06c
PM		 2815float##fsz HELPER(vfp_##name##to##p)(uint##fsz##_t x, uint32_t shift, \
2816 void *fpstp) \
4373f3ce 2817{ \
5500b06c 2818 float_status *fpst = fpstp; \
622465e1 2819 float##fsz tmp; \
5500b06c
PM		 2820 tmp = sign##int32_to_##float##fsz((itype##_t)x, fpst); \
2821 return float##fsz##_scalbn(tmp, -(int)shift, fpst); \
4373f3ce 2822} \
5500b06c
PM		 2823uint##fsz##_t HELPER(vfp_to##name##p)(float##fsz x, uint32_t shift, \
2824 void *fpstp) \
4373f3ce 2825{ \
5500b06c 2826 float_status *fpst = fpstp; \
622465e1
PM		 2827 float##fsz tmp; \
2828 if (float##fsz##_is_any_nan(x)) { \
5500b06c 2829 float_raise(float_flag_invalid, fpst); \
622465e1 2830 return 0; \
09d9487f 2831 } \
5500b06c
PM		 2832 tmp = float##fsz##_scalbn(x, shift, fpst); \
2833 return float##fsz##_to_##itype##_round_to_zero(tmp, fpst); \
622465e1
PM		 2834}
2835
2836VFP_CONV_FIX(sh, d, 64, int16, )
2837VFP_CONV_FIX(sl, d, 64, int32, )
2838VFP_CONV_FIX(uh, d, 64, uint16, u)
2839VFP_CONV_FIX(ul, d, 64, uint32, u)
2840VFP_CONV_FIX(sh, s, 32, int16, )
2841VFP_CONV_FIX(sl, s, 32, int32, )
2842VFP_CONV_FIX(uh, s, 32, uint16, u)
2843VFP_CONV_FIX(ul, s, 32, uint32, u)
4373f3ce
PB		 2844#undef VFP_CONV_FIX
2845
60011498 2846/* Half precision conversions. */
0ecb72a5 2847static float32 do_fcvt_f16_to_f32(uint32_t a, CPUARMState *env, float_status *s)
60011498 2848{
60011498 2849 int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0;
fb91678d
PM		 2850 float32 r = float16_to_float32(make_float16(a), ieee, s);
2851 if (ieee) {
2852 return float32_maybe_silence_nan(r);
2853 }
2854 return r;
60011498
PB		 2855}
2856
0ecb72a5 2857static uint32_t do_fcvt_f32_to_f16(float32 a, CPUARMState *env, float_status *s)
60011498 2858{
60011498 2859 int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0;
fb91678d
PM		 2860 float16 r = float32_to_float16(a, ieee, s);
2861 if (ieee) {
2862 r = float16_maybe_silence_nan(r);
2863 }
2864 return float16_val(r);
60011498
PB		 2865}
2866
0ecb72a5 2867float32 HELPER(neon_fcvt_f16_to_f32)(uint32_t a, CPUARMState *env)
2d981da7
PM		 2868{
2869 return do_fcvt_f16_to_f32(a, env, &env->vfp.standard_fp_status);
2870}
2871
0ecb72a5 2872uint32_t HELPER(neon_fcvt_f32_to_f16)(float32 a, CPUARMState *env)
2d981da7
PM		 2873{
2874 return do_fcvt_f32_to_f16(a, env, &env->vfp.standard_fp_status);
2875}
2876
0ecb72a5 2877float32 HELPER(vfp_fcvt_f16_to_f32)(uint32_t a, CPUARMState *env)
2d981da7
PM		 2878{
2879 return do_fcvt_f16_to_f32(a, env, &env->vfp.fp_status);
2880}
2881
0ecb72a5 2882uint32_t HELPER(vfp_fcvt_f32_to_f16)(float32 a, CPUARMState *env)
2d981da7
PM		 2883{
2884 return do_fcvt_f32_to_f16(a, env, &env->vfp.fp_status);
2885}
2886
dda3ec49 2887#define float32_two make_float32(0x40000000)
6aae3df1
PM		 2888#define float32_three make_float32(0x40400000)
2889#define float32_one_point_five make_float32(0x3fc00000)
dda3ec49 2890
0ecb72a5 2891float32 HELPER(recps_f32)(float32 a, float32 b, CPUARMState *env)
4373f3ce 2892{
dda3ec49
PM		 2893 float_status *s = &env->vfp.standard_fp_status;
2894 if ((float32_is_infinity(a) && float32_is_zero_or_denormal(b)) ||
2895 (float32_is_infinity(b) && float32_is_zero_or_denormal(a))) {
43fe9bdb
PM		 2896 if (!(float32_is_zero(a) || float32_is_zero(b))) {
2897 float_raise(float_flag_input_denormal, s);
2898 }
dda3ec49
PM		 2899 return float32_two;
2900 }
2901 return float32_sub(float32_two, float32_mul(a, b, s), s);
4373f3ce
PB		 2902}
2903
0ecb72a5 2904float32 HELPER(rsqrts_f32)(float32 a, float32 b, CPUARMState *env)
4373f3ce 2905{
71826966 2906 float_status *s = &env->vfp.standard_fp_status;
9ea62f57
PM		 2907 float32 product;
2908 if ((float32_is_infinity(a) && float32_is_zero_or_denormal(b)) ||
2909 (float32_is_infinity(b) && float32_is_zero_or_denormal(a))) {
43fe9bdb
PM		 2910 if (!(float32_is_zero(a) || float32_is_zero(b))) {
2911 float_raise(float_flag_input_denormal, s);
2912 }
6aae3df1 2913 return float32_one_point_five;
9ea62f57 2914 }
6aae3df1
PM		 2915 product = float32_mul(a, b, s);
2916 return float32_div(float32_sub(float32_three, product, s), float32_two, s);
4373f3ce
PB		 2917}
2918
8f8e3aa4
PB		 2919/* NEON helpers. */
2920
56bf4fe2
CL		 2921/* Constants 256 and 512 are used in some helpers; we avoid relying on
2922 * int->float conversions at run-time. */
2923#define float64_256 make_float64(0x4070000000000000LL)
2924#define float64_512 make_float64(0x4080000000000000LL)
2925
fe0e4872
CL		 2926/* The algorithm that must be used to calculate the estimate
2927 * is specified by the ARM ARM.
2928 */
0ecb72a5 2929static float64 recip_estimate(float64 a, CPUARMState *env)
fe0e4872 2930{
1146a817
PM		 2931 /* These calculations mustn't set any fp exception flags,
2932 * so we use a local copy of the fp_status.
2933 */
2934 float_status dummy_status = env->vfp.standard_fp_status;
2935 float_status *s = &dummy_status;
fe0e4872
CL		 2936 /* q = (int)(a * 512.0) */
2937 float64 q = float64_mul(float64_512, a, s);
2938 int64_t q_int = float64_to_int64_round_to_zero(q, s);
2939
2940 /* r = 1.0 / (((double)q + 0.5) / 512.0) */
2941 q = int64_to_float64(q_int, s);
2942 q = float64_add(q, float64_half, s);
2943 q = float64_div(q, float64_512, s);
2944 q = float64_div(float64_one, q, s);
2945
2946 /* s = (int)(256.0 * r + 0.5) */
2947 q = float64_mul(q, float64_256, s);
2948 q = float64_add(q, float64_half, s);
2949 q_int = float64_to_int64_round_to_zero(q, s);
2950
2951 /* return (double)s / 256.0 */
2952 return float64_div(int64_to_float64(q_int, s), float64_256, s);
2953}
2954
0ecb72a5 2955float32 HELPER(recpe_f32)(float32 a, CPUARMState *env)
4373f3ce 2956{
fe0e4872
CL		 2957 float_status *s = &env->vfp.standard_fp_status;
2958 float64 f64;
2959 uint32_t val32 = float32_val(a);
2960
2961 int result_exp;
2962 int a_exp = (val32 & 0x7f800000) >> 23;
2963 int sign = val32 & 0x80000000;
2964
2965 if (float32_is_any_nan(a)) {
2966 if (float32_is_signaling_nan(a)) {
2967 float_raise(float_flag_invalid, s);
2968 }
2969 return float32_default_nan;
2970 } else if (float32_is_infinity(a)) {
2971 return float32_set_sign(float32_zero, float32_is_neg(a));
2972 } else if (float32_is_zero_or_denormal(a)) {
43fe9bdb
PM		 2973 if (!float32_is_zero(a)) {
2974 float_raise(float_flag_input_denormal, s);
2975 }
fe0e4872
CL		 2976 float_raise(float_flag_divbyzero, s);
2977 return float32_set_sign(float32_infinity, float32_is_neg(a));
2978 } else if (a_exp >= 253) {
2979 float_raise(float_flag_underflow, s);
2980 return float32_set_sign(float32_zero, float32_is_neg(a));
2981 }
2982
2983 f64 = make_float64((0x3feULL << 52)
2984 | ((int64_t)(val32 & 0x7fffff) << 29));
2985
2986 result_exp = 253 - a_exp;
2987
2988 f64 = recip_estimate(f64, env);
2989
2990 val32 = sign
2991 | ((result_exp & 0xff) << 23)
2992 | ((float64_val(f64) >> 29) & 0x7fffff);
2993 return make_float32(val32);
4373f3ce
PB		 2994}
2995
e07be5d2
CL		 2996/* The algorithm that must be used to calculate the estimate
2997 * is specified by the ARM ARM.
2998 */
0ecb72a5 2999static float64 recip_sqrt_estimate(float64 a, CPUARMState *env)
e07be5d2 3000{
1146a817
PM		 3001 /* These calculations mustn't set any fp exception flags,
3002 * so we use a local copy of the fp_status.
3003 */
3004 float_status dummy_status = env->vfp.standard_fp_status;
3005 float_status *s = &dummy_status;
e07be5d2
CL		 3006 float64 q;
3007 int64_t q_int;
3008
3009 if (float64_lt(a, float64_half, s)) {
3010 /* range 0.25 <= a < 0.5 */
3011
3012 /* a in units of 1/512 rounded down */
3013 /* q0 = (int)(a * 512.0); */
3014 q = float64_mul(float64_512, a, s);
3015 q_int = float64_to_int64_round_to_zero(q, s);
3016
3017 /* reciprocal root r */
3018 /* r = 1.0 / sqrt(((double)q0 + 0.5) / 512.0); */
3019 q = int64_to_float64(q_int, s);
3020 q = float64_add(q, float64_half, s);
3021 q = float64_div(q, float64_512, s);
3022 q = float64_sqrt(q, s);
3023 q = float64_div(float64_one, q, s);
3024 } else {
3025 /* range 0.5 <= a < 1.0 */
3026
3027 /* a in units of 1/256 rounded down */
3028 /* q1 = (int)(a * 256.0); */
3029 q = float64_mul(float64_256, a, s);
3030 int64_t q_int = float64_to_int64_round_to_zero(q, s);
3031
3032 /* reciprocal root r */
3033 /* r = 1.0 /sqrt(((double)q1 + 0.5) / 256); */
3034 q = int64_to_float64(q_int, s);
3035 q = float64_add(q, float64_half, s);
3036 q = float64_div(q, float64_256, s);
3037 q = float64_sqrt(q, s);
3038 q = float64_div(float64_one, q, s);
3039 }
3040 /* r in units of 1/256 rounded to nearest */
3041 /* s = (int)(256.0 * r + 0.5); */
3042
3043 q = float64_mul(q, float64_256,s );
3044 q = float64_add(q, float64_half, s);
3045 q_int = float64_to_int64_round_to_zero(q, s);
3046
3047 /* return (double)s / 256.0;*/
3048 return float64_div(int64_to_float64(q_int, s), float64_256, s);
3049}
3050
0ecb72a5 3051float32 HELPER(rsqrte_f32)(float32 a, CPUARMState *env)
4373f3ce 3052{
e07be5d2
CL		 3053 float_status *s = &env->vfp.standard_fp_status;
3054 int result_exp;
3055 float64 f64;
3056 uint32_t val;
3057 uint64_t val64;
3058
3059 val = float32_val(a);
3060
3061 if (float32_is_any_nan(a)) {
3062 if (float32_is_signaling_nan(a)) {
3063 float_raise(float_flag_invalid, s);
3064 }
3065 return float32_default_nan;
3066 } else if (float32_is_zero_or_denormal(a)) {
43fe9bdb
PM		 3067 if (!float32_is_zero(a)) {
3068 float_raise(float_flag_input_denormal, s);
3069 }
e07be5d2
CL		 3070 float_raise(float_flag_divbyzero, s);
3071 return float32_set_sign(float32_infinity, float32_is_neg(a));
3072 } else if (float32_is_neg(a)) {
3073 float_raise(float_flag_invalid, s);
3074 return float32_default_nan;
3075 } else if (float32_is_infinity(a)) {
3076 return float32_zero;
3077 }
3078
3079 /* Normalize to a double-precision value between 0.25 and 1.0,
3080 * preserving the parity of the exponent. */
3081 if ((val & 0x800000) == 0) {
3082 f64 = make_float64(((uint64_t)(val & 0x80000000) << 32)
3083 | (0x3feULL << 52)
3084 | ((uint64_t)(val & 0x7fffff) << 29));
3085 } else {
3086 f64 = make_float64(((uint64_t)(val & 0x80000000) << 32)
3087 | (0x3fdULL << 52)
3088 | ((uint64_t)(val & 0x7fffff) << 29));
3089 }
3090
3091 result_exp = (380 - ((val & 0x7f800000) >> 23)) / 2;
3092
3093 f64 = recip_sqrt_estimate(f64, env);
3094
3095 val64 = float64_val(f64);
3096
26cc6abf 3097 val = ((result_exp & 0xff) << 23)
e07be5d2
CL		 3098 | ((val64 >> 29) & 0x7fffff);
3099 return make_float32(val);
4373f3ce
PB		 3100}
3101
0ecb72a5 3102uint32_t HELPER(recpe_u32)(uint32_t a, CPUARMState *env)
4373f3ce 3103{
fe0e4872
CL		 3104 float64 f64;
3105
3106 if ((a & 0x80000000) == 0) {
3107 return 0xffffffff;
3108 }
3109
3110 f64 = make_float64((0x3feULL << 52)
3111 | ((int64_t)(a & 0x7fffffff) << 21));
3112
3113 f64 = recip_estimate (f64, env);
3114
3115 return 0x80000000 | ((float64_val(f64) >> 21) & 0x7fffffff);
4373f3ce
PB		 3116}
3117
0ecb72a5 3118uint32_t HELPER(rsqrte_u32)(uint32_t a, CPUARMState *env)
4373f3ce 3119{
e07be5d2
CL		 3120 float64 f64;
3121
3122 if ((a & 0xc0000000) == 0) {
3123 return 0xffffffff;
3124 }
3125
3126 if (a & 0x80000000) {
3127 f64 = make_float64((0x3feULL << 52)
3128 | ((uint64_t)(a & 0x7fffffff) << 21));
3129 } else { /* bits 31-30 == '01' */
3130 f64 = make_float64((0x3fdULL << 52)
3131 | ((uint64_t)(a & 0x3fffffff) << 22));
3132 }
3133
3134 f64 = recip_sqrt_estimate(f64, env);
3135
3136 return 0x80000000 | ((float64_val(f64) >> 21) & 0x7fffffff);
4373f3ce 3137}
fe1479c3 3138
da97f52c
PM		 3139/* VFPv4 fused multiply-accumulate */
3140float32 VFP_HELPER(muladd, s)(float32 a, float32 b, float32 c, void *fpstp)
3141{
3142 float_status *fpst = fpstp;
3143 return float32_muladd(a, b, c, 0, fpst);
3144}
3145
3146float64 VFP_HELPER(muladd, d)(float64 a, float64 b, float64 c, void *fpstp)
3147{
3148 float_status *fpst = fpstp;
3149 return float64_muladd(a, b, c, 0, fpst);
3150}
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