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ccd38087 PM |
1 | /* |
2 | * QEMU ARM CPU -- internal functions and types | |
3 | * | |
4 | * Copyright (c) 2014 Linaro Ltd | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU General Public License | |
8 | * as published by the Free Software Foundation; either version 2 | |
9 | * of the License, or (at your option) any later version. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program; if not, see | |
18 | * <http://www.gnu.org/licenses/gpl-2.0.html> | |
19 | * | |
20 | * This header defines functions, types, etc which need to be shared | |
21 | * between different source files within target-arm/ but which are | |
22 | * private to it and not required by the rest of QEMU. | |
23 | */ | |
24 | ||
25 | #ifndef TARGET_ARM_INTERNALS_H | |
26 | #define TARGET_ARM_INTERNALS_H | |
27 | ||
99a99c1f SB |
28 | /* register banks for CPU modes */ |
29 | #define BANK_USRSYS 0 | |
30 | #define BANK_SVC 1 | |
31 | #define BANK_ABT 2 | |
32 | #define BANK_UND 3 | |
33 | #define BANK_IRQ 4 | |
34 | #define BANK_FIQ 5 | |
35 | #define BANK_HYP 6 | |
36 | #define BANK_MON 7 | |
37 | ||
d4a2dc67 PM |
38 | static inline bool excp_is_internal(int excp) |
39 | { | |
40 | /* Return true if this exception number represents a QEMU-internal | |
41 | * exception that will not be passed to the guest. | |
42 | */ | |
43 | return excp == EXCP_INTERRUPT | |
44 | || excp == EXCP_HLT | |
45 | || excp == EXCP_DEBUG | |
46 | || excp == EXCP_HALTED | |
47 | || excp == EXCP_EXCEPTION_EXIT | |
48 | || excp == EXCP_KERNEL_TRAP | |
8012c84f | 49 | || excp == EXCP_SEMIHOST |
d4a2dc67 PM |
50 | || excp == EXCP_STREX; |
51 | } | |
52 | ||
2f2a00ae PM |
53 | /* Exception names for debug logging; note that not all of these |
54 | * precisely correspond to architectural exceptions. | |
55 | */ | |
56 | static const char * const excnames[] = { | |
57 | [EXCP_UDEF] = "Undefined Instruction", | |
58 | [EXCP_SWI] = "SVC", | |
59 | [EXCP_PREFETCH_ABORT] = "Prefetch Abort", | |
60 | [EXCP_DATA_ABORT] = "Data Abort", | |
61 | [EXCP_IRQ] = "IRQ", | |
62 | [EXCP_FIQ] = "FIQ", | |
63 | [EXCP_BKPT] = "Breakpoint", | |
64 | [EXCP_EXCEPTION_EXIT] = "QEMU v7M exception exit", | |
65 | [EXCP_KERNEL_TRAP] = "QEMU intercept of kernel commpage", | |
66 | [EXCP_STREX] = "QEMU intercept of STREX", | |
35979d71 | 67 | [EXCP_HVC] = "Hypervisor Call", |
607d98b8 | 68 | [EXCP_HYP_TRAP] = "Hypervisor Trap", |
e0d6e6a5 | 69 | [EXCP_SMC] = "Secure Monitor Call", |
136e67e9 EI |
70 | [EXCP_VIRQ] = "Virtual IRQ", |
71 | [EXCP_VFIQ] = "Virtual FIQ", | |
8012c84f | 72 | [EXCP_SEMIHOST] = "Semihosting call", |
2f2a00ae PM |
73 | }; |
74 | ||
75 | static inline void arm_log_exception(int idx) | |
76 | { | |
77 | if (qemu_loglevel_mask(CPU_LOG_INT)) { | |
78 | const char *exc = NULL; | |
79 | ||
80 | if (idx >= 0 && idx < ARRAY_SIZE(excnames)) { | |
81 | exc = excnames[idx]; | |
82 | } | |
83 | if (!exc) { | |
84 | exc = "unknown"; | |
85 | } | |
86 | qemu_log_mask(CPU_LOG_INT, "Taking exception %d [%s]\n", idx, exc); | |
87 | } | |
88 | } | |
89 | ||
ccd38087 PM |
90 | /* Scale factor for generic timers, ie number of ns per tick. |
91 | * This gives a 62.5MHz timer. | |
92 | */ | |
93 | #define GTIMER_SCALE 16 | |
94 | ||
2a923c4d EI |
95 | /* |
96 | * For AArch64, map a given EL to an index in the banked_spsr array. | |
7847f9ea PM |
97 | * Note that this mapping and the AArch32 mapping defined in bank_number() |
98 | * must agree such that the AArch64<->AArch32 SPSRs have the architecturally | |
99 | * mandated mapping between each other. | |
2a923c4d EI |
100 | */ |
101 | static inline unsigned int aarch64_banked_spsr_index(unsigned int el) | |
102 | { | |
103 | static const unsigned int map[4] = { | |
99a99c1f SB |
104 | [1] = BANK_SVC, /* EL1. */ |
105 | [2] = BANK_HYP, /* EL2. */ | |
106 | [3] = BANK_MON, /* EL3. */ | |
2a923c4d EI |
107 | }; |
108 | assert(el >= 1 && el <= 3); | |
109 | return map[el]; | |
110 | } | |
111 | ||
ccd38087 PM |
112 | int bank_number(int mode); |
113 | void switch_mode(CPUARMState *, int); | |
114 | void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu); | |
115 | void arm_translate_init(void); | |
116 | ||
117 | enum arm_fprounding { | |
118 | FPROUNDING_TIEEVEN, | |
119 | FPROUNDING_POSINF, | |
120 | FPROUNDING_NEGINF, | |
121 | FPROUNDING_ZERO, | |
122 | FPROUNDING_TIEAWAY, | |
123 | FPROUNDING_ODD | |
124 | }; | |
125 | ||
126 | int arm_rmode_to_sf(int rmode); | |
127 | ||
9208b961 EI |
128 | static inline void aarch64_save_sp(CPUARMState *env, int el) |
129 | { | |
130 | if (env->pstate & PSTATE_SP) { | |
131 | env->sp_el[el] = env->xregs[31]; | |
132 | } else { | |
133 | env->sp_el[0] = env->xregs[31]; | |
134 | } | |
135 | } | |
136 | ||
137 | static inline void aarch64_restore_sp(CPUARMState *env, int el) | |
138 | { | |
139 | if (env->pstate & PSTATE_SP) { | |
140 | env->xregs[31] = env->sp_el[el]; | |
141 | } else { | |
142 | env->xregs[31] = env->sp_el[0]; | |
143 | } | |
144 | } | |
145 | ||
f502cfc2 PM |
146 | static inline void update_spsel(CPUARMState *env, uint32_t imm) |
147 | { | |
dcbff19b | 148 | unsigned int cur_el = arm_current_el(env); |
f502cfc2 PM |
149 | /* Update PSTATE SPSel bit; this requires us to update the |
150 | * working stack pointer in xregs[31]. | |
151 | */ | |
152 | if (!((imm ^ env->pstate) & PSTATE_SP)) { | |
153 | return; | |
154 | } | |
9208b961 | 155 | aarch64_save_sp(env, cur_el); |
f502cfc2 PM |
156 | env->pstate = deposit32(env->pstate, 0, 1, imm); |
157 | ||
61d4b215 EI |
158 | /* We rely on illegal updates to SPsel from EL0 to get trapped |
159 | * at translation time. | |
f502cfc2 | 160 | */ |
61d4b215 | 161 | assert(cur_el >= 1 && cur_el <= 3); |
9208b961 | 162 | aarch64_restore_sp(env, cur_el); |
f502cfc2 PM |
163 | } |
164 | ||
1853d5a9 EI |
165 | /* |
166 | * arm_pamax | |
167 | * @cpu: ARMCPU | |
168 | * | |
169 | * Returns the implementation defined bit-width of physical addresses. | |
170 | * The ARMv8 reference manuals refer to this as PAMax(). | |
171 | */ | |
172 | static inline unsigned int arm_pamax(ARMCPU *cpu) | |
173 | { | |
174 | static const unsigned int pamax_map[] = { | |
175 | [0] = 32, | |
176 | [1] = 36, | |
177 | [2] = 40, | |
178 | [3] = 42, | |
179 | [4] = 44, | |
180 | [5] = 48, | |
181 | }; | |
182 | unsigned int parange = extract32(cpu->id_aa64mmfr0, 0, 4); | |
183 | ||
184 | /* id_aa64mmfr0 is a read-only register so values outside of the | |
185 | * supported mappings can be considered an implementation error. */ | |
186 | assert(parange < ARRAY_SIZE(pamax_map)); | |
187 | return pamax_map[parange]; | |
188 | } | |
189 | ||
73c5211b PM |
190 | /* Return true if extended addresses are enabled. |
191 | * This is always the case if our translation regime is 64 bit, | |
192 | * but depends on TTBCR.EAE for 32 bit. | |
193 | */ | |
194 | static inline bool extended_addresses_enabled(CPUARMState *env) | |
195 | { | |
11f136ee FA |
196 | TCR *tcr = &env->cp15.tcr_el[arm_is_secure(env) ? 3 : 1]; |
197 | return arm_el_is_aa64(env, 1) || | |
198 | (arm_feature(env, ARM_FEATURE_LPAE) && (tcr->raw_tcr & TTBCR_EAE)); | |
73c5211b PM |
199 | } |
200 | ||
8bcbf37c PM |
201 | /* Valid Syndrome Register EC field values */ |
202 | enum arm_exception_class { | |
203 | EC_UNCATEGORIZED = 0x00, | |
204 | EC_WFX_TRAP = 0x01, | |
205 | EC_CP15RTTRAP = 0x03, | |
206 | EC_CP15RRTTRAP = 0x04, | |
207 | EC_CP14RTTRAP = 0x05, | |
208 | EC_CP14DTTRAP = 0x06, | |
209 | EC_ADVSIMDFPACCESSTRAP = 0x07, | |
210 | EC_FPIDTRAP = 0x08, | |
211 | EC_CP14RRTTRAP = 0x0c, | |
212 | EC_ILLEGALSTATE = 0x0e, | |
213 | EC_AA32_SVC = 0x11, | |
214 | EC_AA32_HVC = 0x12, | |
215 | EC_AA32_SMC = 0x13, | |
216 | EC_AA64_SVC = 0x15, | |
217 | EC_AA64_HVC = 0x16, | |
218 | EC_AA64_SMC = 0x17, | |
219 | EC_SYSTEMREGISTERTRAP = 0x18, | |
220 | EC_INSNABORT = 0x20, | |
221 | EC_INSNABORT_SAME_EL = 0x21, | |
222 | EC_PCALIGNMENT = 0x22, | |
223 | EC_DATAABORT = 0x24, | |
224 | EC_DATAABORT_SAME_EL = 0x25, | |
225 | EC_SPALIGNMENT = 0x26, | |
226 | EC_AA32_FPTRAP = 0x28, | |
227 | EC_AA64_FPTRAP = 0x2c, | |
228 | EC_SERROR = 0x2f, | |
229 | EC_BREAKPOINT = 0x30, | |
230 | EC_BREAKPOINT_SAME_EL = 0x31, | |
231 | EC_SOFTWARESTEP = 0x32, | |
232 | EC_SOFTWARESTEP_SAME_EL = 0x33, | |
233 | EC_WATCHPOINT = 0x34, | |
234 | EC_WATCHPOINT_SAME_EL = 0x35, | |
235 | EC_AA32_BKPT = 0x38, | |
236 | EC_VECTORCATCH = 0x3a, | |
237 | EC_AA64_BKPT = 0x3c, | |
238 | }; | |
239 | ||
240 | #define ARM_EL_EC_SHIFT 26 | |
241 | #define ARM_EL_IL_SHIFT 25 | |
242 | #define ARM_EL_IL (1 << ARM_EL_IL_SHIFT) | |
243 | ||
244 | /* Utility functions for constructing various kinds of syndrome value. | |
245 | * Note that in general we follow the AArch64 syndrome values; in a | |
246 | * few cases the value in HSR for exceptions taken to AArch32 Hyp | |
247 | * mode differs slightly, so if we ever implemented Hyp mode then the | |
248 | * syndrome value would need some massaging on exception entry. | |
249 | * (One example of this is that AArch64 defaults to IL bit set for | |
250 | * exceptions which don't specifically indicate information about the | |
251 | * trapping instruction, whereas AArch32 defaults to IL bit clear.) | |
252 | */ | |
253 | static inline uint32_t syn_uncategorized(void) | |
254 | { | |
255 | return (EC_UNCATEGORIZED << ARM_EL_EC_SHIFT) | ARM_EL_IL; | |
256 | } | |
257 | ||
258 | static inline uint32_t syn_aa64_svc(uint32_t imm16) | |
259 | { | |
260 | return (EC_AA64_SVC << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff); | |
261 | } | |
262 | ||
35979d71 EI |
263 | static inline uint32_t syn_aa64_hvc(uint32_t imm16) |
264 | { | |
265 | return (EC_AA64_HVC << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff); | |
266 | } | |
267 | ||
e0d6e6a5 EI |
268 | static inline uint32_t syn_aa64_smc(uint32_t imm16) |
269 | { | |
270 | return (EC_AA64_SMC << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff); | |
271 | } | |
272 | ||
fc05f4a6 | 273 | static inline uint32_t syn_aa32_svc(uint32_t imm16, bool is_16bit) |
8bcbf37c PM |
274 | { |
275 | return (EC_AA32_SVC << ARM_EL_EC_SHIFT) | (imm16 & 0xffff) | |
fc05f4a6 | 276 | | (is_16bit ? 0 : ARM_EL_IL); |
8bcbf37c PM |
277 | } |
278 | ||
37e6456e PM |
279 | static inline uint32_t syn_aa32_hvc(uint32_t imm16) |
280 | { | |
281 | return (EC_AA32_HVC << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff); | |
282 | } | |
283 | ||
284 | static inline uint32_t syn_aa32_smc(void) | |
285 | { | |
286 | return (EC_AA32_SMC << ARM_EL_EC_SHIFT) | ARM_EL_IL; | |
287 | } | |
288 | ||
8bcbf37c PM |
289 | static inline uint32_t syn_aa64_bkpt(uint32_t imm16) |
290 | { | |
291 | return (EC_AA64_BKPT << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff); | |
292 | } | |
293 | ||
fc05f4a6 | 294 | static inline uint32_t syn_aa32_bkpt(uint32_t imm16, bool is_16bit) |
8bcbf37c PM |
295 | { |
296 | return (EC_AA32_BKPT << ARM_EL_EC_SHIFT) | (imm16 & 0xffff) | |
fc05f4a6 | 297 | | (is_16bit ? 0 : ARM_EL_IL); |
8bcbf37c PM |
298 | } |
299 | ||
300 | static inline uint32_t syn_aa64_sysregtrap(int op0, int op1, int op2, | |
301 | int crn, int crm, int rt, | |
302 | int isread) | |
303 | { | |
304 | return (EC_SYSTEMREGISTERTRAP << ARM_EL_EC_SHIFT) | ARM_EL_IL | |
305 | | (op0 << 20) | (op2 << 17) | (op1 << 14) | (crn << 10) | (rt << 5) | |
306 | | (crm << 1) | isread; | |
307 | } | |
308 | ||
309 | static inline uint32_t syn_cp14_rt_trap(int cv, int cond, int opc1, int opc2, | |
310 | int crn, int crm, int rt, int isread, | |
fc05f4a6 | 311 | bool is_16bit) |
8bcbf37c PM |
312 | { |
313 | return (EC_CP14RTTRAP << ARM_EL_EC_SHIFT) | |
fc05f4a6 | 314 | | (is_16bit ? 0 : ARM_EL_IL) |
8bcbf37c PM |
315 | | (cv << 24) | (cond << 20) | (opc2 << 17) | (opc1 << 14) |
316 | | (crn << 10) | (rt << 5) | (crm << 1) | isread; | |
317 | } | |
318 | ||
319 | static inline uint32_t syn_cp15_rt_trap(int cv, int cond, int opc1, int opc2, | |
320 | int crn, int crm, int rt, int isread, | |
fc05f4a6 | 321 | bool is_16bit) |
8bcbf37c PM |
322 | { |
323 | return (EC_CP15RTTRAP << ARM_EL_EC_SHIFT) | |
fc05f4a6 | 324 | | (is_16bit ? 0 : ARM_EL_IL) |
8bcbf37c PM |
325 | | (cv << 24) | (cond << 20) | (opc2 << 17) | (opc1 << 14) |
326 | | (crn << 10) | (rt << 5) | (crm << 1) | isread; | |
327 | } | |
328 | ||
329 | static inline uint32_t syn_cp14_rrt_trap(int cv, int cond, int opc1, int crm, | |
330 | int rt, int rt2, int isread, | |
fc05f4a6 | 331 | bool is_16bit) |
8bcbf37c PM |
332 | { |
333 | return (EC_CP14RRTTRAP << ARM_EL_EC_SHIFT) | |
fc05f4a6 | 334 | | (is_16bit ? 0 : ARM_EL_IL) |
8bcbf37c PM |
335 | | (cv << 24) | (cond << 20) | (opc1 << 16) |
336 | | (rt2 << 10) | (rt << 5) | (crm << 1) | isread; | |
337 | } | |
338 | ||
339 | static inline uint32_t syn_cp15_rrt_trap(int cv, int cond, int opc1, int crm, | |
340 | int rt, int rt2, int isread, | |
fc05f4a6 | 341 | bool is_16bit) |
8bcbf37c PM |
342 | { |
343 | return (EC_CP15RRTTRAP << ARM_EL_EC_SHIFT) | |
fc05f4a6 | 344 | | (is_16bit ? 0 : ARM_EL_IL) |
8bcbf37c PM |
345 | | (cv << 24) | (cond << 20) | (opc1 << 16) |
346 | | (rt2 << 10) | (rt << 5) | (crm << 1) | isread; | |
347 | } | |
348 | ||
fc05f4a6 | 349 | static inline uint32_t syn_fp_access_trap(int cv, int cond, bool is_16bit) |
8c6afa6a PM |
350 | { |
351 | return (EC_ADVSIMDFPACCESSTRAP << ARM_EL_EC_SHIFT) | |
fc05f4a6 | 352 | | (is_16bit ? 0 : ARM_EL_IL) |
8c6afa6a PM |
353 | | (cv << 24) | (cond << 20); |
354 | } | |
355 | ||
00892383 RH |
356 | static inline uint32_t syn_insn_abort(int same_el, int ea, int s1ptw, int fsc) |
357 | { | |
358 | return (EC_INSNABORT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT) | |
359 | | (ea << 9) | (s1ptw << 7) | fsc; | |
360 | } | |
361 | ||
362 | static inline uint32_t syn_data_abort(int same_el, int ea, int cm, int s1ptw, | |
363 | int wnr, int fsc) | |
364 | { | |
365 | return (EC_DATAABORT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT) | |
366 | | (ea << 9) | (cm << 8) | (s1ptw << 7) | (wnr << 6) | fsc; | |
367 | } | |
368 | ||
7ea47fe7 PM |
369 | static inline uint32_t syn_swstep(int same_el, int isv, int ex) |
370 | { | |
371 | return (EC_SOFTWARESTEP << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT) | |
372 | | (isv << 24) | (ex << 6) | 0x22; | |
373 | } | |
374 | ||
3ff6fc91 PM |
375 | static inline uint32_t syn_watchpoint(int same_el, int cm, int wnr) |
376 | { | |
377 | return (EC_WATCHPOINT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT) | |
378 | | (cm << 8) | (wnr << 6) | 0x22; | |
379 | } | |
380 | ||
0eacea70 PM |
381 | static inline uint32_t syn_breakpoint(int same_el) |
382 | { | |
383 | return (EC_BREAKPOINT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT) | |
384 | | ARM_EL_IL | 0x22; | |
385 | } | |
386 | ||
06fbb2fd GB |
387 | static inline uint32_t syn_wfx(int cv, int cond, int ti) |
388 | { | |
389 | return (EC_WFX_TRAP << ARM_EL_EC_SHIFT) | | |
390 | (cv << 24) | (cond << 20) | ti; | |
391 | } | |
392 | ||
9ee98ce8 PM |
393 | /* Update a QEMU watchpoint based on the information the guest has set in the |
394 | * DBGWCR<n>_EL1 and DBGWVR<n>_EL1 registers. | |
395 | */ | |
396 | void hw_watchpoint_update(ARMCPU *cpu, int n); | |
397 | /* Update the QEMU watchpoints for every guest watchpoint. This does a | |
398 | * complete delete-and-reinstate of the QEMU watchpoint list and so is | |
399 | * suitable for use after migration or on reset. | |
400 | */ | |
401 | void hw_watchpoint_update_all(ARMCPU *cpu); | |
46747d15 PM |
402 | /* Update a QEMU breakpoint based on the information the guest has set in the |
403 | * DBGBCR<n>_EL1 and DBGBVR<n>_EL1 registers. | |
404 | */ | |
405 | void hw_breakpoint_update(ARMCPU *cpu, int n); | |
406 | /* Update the QEMU breakpoints for every guest breakpoint. This does a | |
407 | * complete delete-and-reinstate of the QEMU breakpoint list and so is | |
408 | * suitable for use after migration or on reset. | |
409 | */ | |
410 | void hw_breakpoint_update_all(ARMCPU *cpu); | |
9ee98ce8 | 411 | |
3826121d SF |
412 | /* Callback function for checking if a watchpoint should trigger. */ |
413 | bool arm_debug_check_watchpoint(CPUState *cs, CPUWatchpoint *wp); | |
414 | ||
3ff6fc91 PM |
415 | /* Callback function for when a watchpoint or breakpoint triggers. */ |
416 | void arm_debug_excp_handler(CPUState *cs); | |
417 | ||
98128601 RH |
418 | #ifdef CONFIG_USER_ONLY |
419 | static inline bool arm_is_psci_call(ARMCPU *cpu, int excp_type) | |
420 | { | |
421 | return false; | |
422 | } | |
423 | #else | |
424 | /* Return true if the r0/x0 value indicates that this SMC/HVC is a PSCI call. */ | |
425 | bool arm_is_psci_call(ARMCPU *cpu, int excp_type); | |
426 | /* Actually handle a PSCI call */ | |
427 | void arm_handle_psci_call(ARMCPU *cpu); | |
428 | #endif | |
429 | ||
e14b5a23 EI |
430 | /** |
431 | * ARMMMUFaultInfo: Information describing an ARM MMU Fault | |
432 | * @s2addr: Address that caused a fault at stage 2 | |
433 | * @stage2: True if we faulted at stage 2 | |
434 | * @s1ptw: True if we faulted at stage 2 while doing a stage 1 page-table walk | |
435 | */ | |
436 | typedef struct ARMMMUFaultInfo ARMMMUFaultInfo; | |
437 | struct ARMMMUFaultInfo { | |
438 | target_ulong s2addr; | |
439 | bool stage2; | |
440 | bool s1ptw; | |
441 | }; | |
442 | ||
8c6084bf | 443 | /* Do a page table walk and add page to TLB if possible */ |
b7cc4e82 | 444 | bool arm_tlb_fill(CPUState *cpu, vaddr address, int rw, int mmu_idx, |
e14b5a23 | 445 | uint32_t *fsr, ARMMMUFaultInfo *fi); |
8c6084bf | 446 | |
deb2db99 AR |
447 | /* Return true if the stage 1 translation regime is using LPAE format page |
448 | * tables */ | |
449 | bool arm_s1_regime_using_lpae_format(CPUARMState *env, ARMMMUIdx mmu_idx); | |
30901475 AB |
450 | |
451 | /* Raise a data fault alignment exception for the specified virtual address */ | |
452 | void arm_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr, int is_write, | |
453 | int is_user, uintptr_t retaddr); | |
454 | ||
ccd38087 | 455 | #endif |