projects / mirror_qemu.git / blame
| Commit | Line | Data |
|---|---|---|
| 72b0cd35 PM |
1 | /* |
| 2 | * KVM ARM ABI constant definitions | |
| 3 | * | |
| 4 | * Copyright (c) 2013 Linaro Limited | |
| 5 | * | |
| 6 | * Provide versions of KVM constant defines that can be used even | |
| 7 | * when CONFIG_KVM is not set and we don't have access to the | |
| 8 | * KVM headers. If CONFIG_KVM is set, we do a compile-time check | |
| 9 | * that we haven't got out of sync somehow. | |
| 10 | * | |
| 11 | * This work is licensed under the terms of the GNU GPL, version 2 or later. | |
| 12 | * See the COPYING file in the top-level directory. | |
| 13 | */ | |
| 14 | #ifndef ARM_KVM_CONSTS_H | |
| 15 | #define ARM_KVM_CONSTS_H | |
| 16 | ||
| 17 | #ifdef CONFIG_KVM | |
| 18 | #include "qemu/compiler.h" | |
| 19 | #include <linux/kvm.h> | |
| 20 | ||
| 21 | #define MISMATCH_CHECK(X, Y) QEMU_BUILD_BUG_ON(X != Y) | |
| 22 | ||
| 23 | #else | |
| 24 | #define MISMATCH_CHECK(X, Y) | |
| 25 | #endif | |
| 26 | ||
| 27 | #define CP_REG_SIZE_SHIFT 52 | |
| 28 | #define CP_REG_SIZE_MASK 0x00f0000000000000ULL | |
| 29 | #define CP_REG_SIZE_U32 0x0020000000000000ULL | |
| 30 | #define CP_REG_SIZE_U64 0x0030000000000000ULL | |
| 31 | #define CP_REG_ARM 0x4000000000000000ULL | |
| f5a0a5a5 | 32 | #define CP_REG_ARCH_MASK 0xff00000000000000ULL |
| 72b0cd35 PM |
33 | |
| 34 | MISMATCH_CHECK(CP_REG_SIZE_SHIFT, KVM_REG_SIZE_SHIFT) | |
| 35 | MISMATCH_CHECK(CP_REG_SIZE_MASK, KVM_REG_SIZE_MASK) | |
| 36 | MISMATCH_CHECK(CP_REG_SIZE_U32, KVM_REG_SIZE_U32) | |
| 37 | MISMATCH_CHECK(CP_REG_SIZE_U64, KVM_REG_SIZE_U64) | |
| 38 | MISMATCH_CHECK(CP_REG_ARM, KVM_REG_ARM) | |
| f5a0a5a5 | 39 | MISMATCH_CHECK(CP_REG_ARCH_MASK, KVM_REG_ARCH_MASK) |
| 72b0cd35 | 40 | |
| a22ec1e6 PM |
41 | #define PSCI_FN_BASE 0x95c1ba5e |
| 42 | #define PSCI_FN(n) (PSCI_FN_BASE + (n)) | |
| 43 | #define PSCI_FN_CPU_SUSPEND PSCI_FN(0) | |
| 44 | #define PSCI_FN_CPU_OFF PSCI_FN(1) | |
| 45 | #define PSCI_FN_CPU_ON PSCI_FN(2) | |
| 46 | #define PSCI_FN_MIGRATE PSCI_FN(3) | |
| 47 | ||
| 48 | MISMATCH_CHECK(PSCI_FN_CPU_SUSPEND, KVM_PSCI_FN_CPU_SUSPEND) | |
| 49 | MISMATCH_CHECK(PSCI_FN_CPU_OFF, KVM_PSCI_FN_CPU_OFF) | |
| 50 | MISMATCH_CHECK(PSCI_FN_CPU_ON, KVM_PSCI_FN_CPU_ON) | |
| 51 | MISMATCH_CHECK(PSCI_FN_MIGRATE, KVM_PSCI_FN_MIGRATE) | |
| 52 | ||
| 83e9a4ae PM |
53 | /* Note that KVM uses overlapping values for AArch32 and AArch64 |
| 54 | * target CPU numbers. AArch32 targets: | |
| 55 | */ | |
| 3541addc | 56 | #define QEMU_KVM_ARM_TARGET_CORTEX_A15 0 |
| 83e9a4ae PM |
57 | #define QEMU_KVM_ARM_TARGET_CORTEX_A7 1 |
| 58 | ||
| 59 | /* AArch64 targets: */ | |
| 60 | #define QEMU_KVM_ARM_TARGET_AEM_V8 0 | |
| 61 | #define QEMU_KVM_ARM_TARGET_FOUNDATION_V8 1 | |
| 62 | #define QEMU_KVM_ARM_TARGET_CORTEX_A57 2 | |
| 3541addc PM |
63 | |
| 64 | /* There's no kernel define for this: sentinel value which | |
| 65 | * matches no KVM target value for either 64 or 32 bit | |
| 66 | */ | |
| 67 | #define QEMU_KVM_ARM_TARGET_NONE UINT_MAX | |
| 68 | ||
| 83e9a4ae PM |
69 | #ifdef TARGET_AARCH64 |
| 70 | MISMATCH_CHECK(QEMU_KVM_ARM_TARGET_AEM_V8, KVM_ARM_TARGET_AEM_V8) | |
| 71 | MISMATCH_CHECK(QEMU_KVM_ARM_TARGET_FOUNDATION_V8, KVM_ARM_TARGET_FOUNDATION_V8) | |
| 72 | MISMATCH_CHECK(QEMU_KVM_ARM_TARGET_CORTEX_A57, KVM_ARM_TARGET_CORTEX_A57) | |
| 73 | #else | |
| 3541addc | 74 | MISMATCH_CHECK(QEMU_KVM_ARM_TARGET_CORTEX_A15, KVM_ARM_TARGET_CORTEX_A15) |
| 83e9a4ae | 75 | MISMATCH_CHECK(QEMU_KVM_ARM_TARGET_CORTEX_A7, KVM_ARM_TARGET_CORTEX_A7) |
| 3541addc PM |
76 | #endif |
| 77 | ||
| f5a0a5a5 PM |
78 | #define CP_REG_ARM64 0x6000000000000000ULL |
| 79 | #define CP_REG_ARM_COPROC_MASK 0x000000000FFF0000 | |
| 80 | #define CP_REG_ARM_COPROC_SHIFT 16 | |
| 81 | #define CP_REG_ARM64_SYSREG (0x0013 << CP_REG_ARM_COPROC_SHIFT) | |
| 82 | #define CP_REG_ARM64_SYSREG_OP0_MASK 0x000000000000c000 | |
| 83 | #define CP_REG_ARM64_SYSREG_OP0_SHIFT 14 | |
| 84 | #define CP_REG_ARM64_SYSREG_OP1_MASK 0x0000000000003800 | |
| 85 | #define CP_REG_ARM64_SYSREG_OP1_SHIFT 11 | |
| 86 | #define CP_REG_ARM64_SYSREG_CRN_MASK 0x0000000000000780 | |
| 87 | #define CP_REG_ARM64_SYSREG_CRN_SHIFT 7 | |
| 88 | #define CP_REG_ARM64_SYSREG_CRM_MASK 0x0000000000000078 | |
| 89 | #define CP_REG_ARM64_SYSREG_CRM_SHIFT 3 | |
| 90 | #define CP_REG_ARM64_SYSREG_OP2_MASK 0x0000000000000007 | |
| 91 | #define CP_REG_ARM64_SYSREG_OP2_SHIFT 0 | |
| 92 | ||
| 93 | /* No kernel define but it's useful to QEMU */ | |
| 94 | #define CP_REG_ARM64_SYSREG_CP (CP_REG_ARM64_SYSREG >> CP_REG_ARM_COPROC_SHIFT) | |
| 95 | ||
| 96 | #ifdef TARGET_AARCH64 | |
| 97 | MISMATCH_CHECK(CP_REG_ARM64, KVM_REG_ARM64) | |
| 98 | MISMATCH_CHECK(CP_REG_ARM_COPROC_MASK, KVM_REG_ARM_COPROC_MASK) | |
| 99 | MISMATCH_CHECK(CP_REG_ARM_COPROC_SHIFT, KVM_REG_ARM_COPROC_SHIFT) | |
| 100 | MISMATCH_CHECK(CP_REG_ARM64_SYSREG, KVM_REG_ARM64_SYSREG) | |
| 101 | MISMATCH_CHECK(CP_REG_ARM64_SYSREG_OP0_MASK, KVM_REG_ARM64_SYSREG_OP0_MASK) | |
| 102 | MISMATCH_CHECK(CP_REG_ARM64_SYSREG_OP0_SHIFT, KVM_REG_ARM64_SYSREG_OP0_SHIFT) | |
| 103 | MISMATCH_CHECK(CP_REG_ARM64_SYSREG_OP1_MASK, KVM_REG_ARM64_SYSREG_OP1_MASK) | |
| 104 | MISMATCH_CHECK(CP_REG_ARM64_SYSREG_OP1_SHIFT, KVM_REG_ARM64_SYSREG_OP1_SHIFT) | |
| 105 | MISMATCH_CHECK(CP_REG_ARM64_SYSREG_CRN_MASK, KVM_REG_ARM64_SYSREG_CRN_MASK) | |
| 106 | MISMATCH_CHECK(CP_REG_ARM64_SYSREG_CRN_SHIFT, KVM_REG_ARM64_SYSREG_CRN_SHIFT) | |
| 107 | MISMATCH_CHECK(CP_REG_ARM64_SYSREG_CRM_MASK, KVM_REG_ARM64_SYSREG_CRM_MASK) | |
| 108 | MISMATCH_CHECK(CP_REG_ARM64_SYSREG_CRM_SHIFT, KVM_REG_ARM64_SYSREG_CRM_SHIFT) | |
| 109 | MISMATCH_CHECK(CP_REG_ARM64_SYSREG_OP2_MASK, KVM_REG_ARM64_SYSREG_OP2_MASK) | |
| 110 | MISMATCH_CHECK(CP_REG_ARM64_SYSREG_OP2_SHIFT, KVM_REG_ARM64_SYSREG_OP2_SHIFT) | |
| 111 | #endif | |
| 112 | ||
| 72b0cd35 PM |
113 | #undef MISMATCH_CHECK |
| 114 | ||
| 115 | #endif |