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14ade10f AG |
1 | /* |
2 | * AArch64 translation | |
3 | * | |
4 | * Copyright (c) 2013 Alexander Graf <agraf@suse.de> | |
5 | * | |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
9 | * version 2 of the License, or (at your option) any later version. | |
10 | * | |
11 | * This library is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU Lesser General Public | |
17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. | |
18 | */ | |
19 | #include <stdarg.h> | |
20 | #include <stdlib.h> | |
21 | #include <stdio.h> | |
22 | #include <string.h> | |
23 | #include <inttypes.h> | |
24 | ||
25 | #include "cpu.h" | |
26 | #include "tcg-op.h" | |
27 | #include "qemu/log.h" | |
28 | #include "translate.h" | |
29 | #include "qemu/host-utils.h" | |
30 | ||
40f860cd PM |
31 | #include "exec/gen-icount.h" |
32 | ||
14ade10f AG |
33 | #include "helper.h" |
34 | #define GEN_HELPER 1 | |
35 | #include "helper.h" | |
36 | ||
37 | static TCGv_i64 cpu_X[32]; | |
38 | static TCGv_i64 cpu_pc; | |
832ffa1c | 39 | static TCGv_i32 cpu_NF, cpu_ZF, cpu_CF, cpu_VF; |
14ade10f | 40 | |
fa2ef212 MM |
41 | /* Load/store exclusive handling */ |
42 | static TCGv_i64 cpu_exclusive_addr; | |
43 | static TCGv_i64 cpu_exclusive_val; | |
44 | static TCGv_i64 cpu_exclusive_high; | |
45 | #ifdef CONFIG_USER_ONLY | |
46 | static TCGv_i64 cpu_exclusive_test; | |
47 | static TCGv_i32 cpu_exclusive_info; | |
48 | #endif | |
49 | ||
14ade10f AG |
50 | static const char *regnames[] = { |
51 | "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", | |
52 | "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15", | |
53 | "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23", | |
54 | "x24", "x25", "x26", "x27", "x28", "x29", "lr", "sp" | |
55 | }; | |
56 | ||
832ffa1c AG |
57 | enum a64_shift_type { |
58 | A64_SHIFT_TYPE_LSL = 0, | |
59 | A64_SHIFT_TYPE_LSR = 1, | |
60 | A64_SHIFT_TYPE_ASR = 2, | |
61 | A64_SHIFT_TYPE_ROR = 3 | |
62 | }; | |
63 | ||
384b26fb AB |
64 | /* Table based decoder typedefs - used when the relevant bits for decode |
65 | * are too awkwardly scattered across the instruction (eg SIMD). | |
66 | */ | |
67 | typedef void AArch64DecodeFn(DisasContext *s, uint32_t insn); | |
68 | ||
69 | typedef struct AArch64DecodeTable { | |
70 | uint32_t pattern; | |
71 | uint32_t mask; | |
72 | AArch64DecodeFn *disas_fn; | |
73 | } AArch64DecodeTable; | |
74 | ||
1f8a73af PM |
75 | /* Function prototype for gen_ functions for calling Neon helpers */ |
76 | typedef void NeonGenTwoOpFn(TCGv_i32, TCGv_i32, TCGv_i32); | |
6d9571f7 | 77 | typedef void NeonGenTwoOpEnvFn(TCGv_i32, TCGv_ptr, TCGv_i32, TCGv_i32); |
70d7f984 | 78 | typedef void NeonGenTwo64OpFn(TCGv_i64, TCGv_i64, TCGv_i64); |
d980fd59 PM |
79 | typedef void NeonGenNarrowFn(TCGv_i32, TCGv_i64); |
80 | typedef void NeonGenNarrowEnvFn(TCGv_i32, TCGv_ptr, TCGv_i64); | |
70d7f984 | 81 | typedef void NeonGenWidenFn(TCGv_i64, TCGv_i32); |
8908f4d1 AB |
82 | typedef void NeonGenTwoSingleOPFn(TCGv_i32, TCGv_i32, TCGv_i32, TCGv_ptr); |
83 | typedef void NeonGenTwoDoubleOPFn(TCGv_i64, TCGv_i64, TCGv_i64, TCGv_ptr); | |
1f8a73af | 84 | |
14ade10f AG |
85 | /* initialize TCG globals. */ |
86 | void a64_translate_init(void) | |
87 | { | |
88 | int i; | |
89 | ||
90 | cpu_pc = tcg_global_mem_new_i64(TCG_AREG0, | |
91 | offsetof(CPUARMState, pc), | |
92 | "pc"); | |
93 | for (i = 0; i < 32; i++) { | |
94 | cpu_X[i] = tcg_global_mem_new_i64(TCG_AREG0, | |
95 | offsetof(CPUARMState, xregs[i]), | |
96 | regnames[i]); | |
97 | } | |
98 | ||
832ffa1c AG |
99 | cpu_NF = tcg_global_mem_new_i32(TCG_AREG0, offsetof(CPUARMState, NF), "NF"); |
100 | cpu_ZF = tcg_global_mem_new_i32(TCG_AREG0, offsetof(CPUARMState, ZF), "ZF"); | |
101 | cpu_CF = tcg_global_mem_new_i32(TCG_AREG0, offsetof(CPUARMState, CF), "CF"); | |
102 | cpu_VF = tcg_global_mem_new_i32(TCG_AREG0, offsetof(CPUARMState, VF), "VF"); | |
fa2ef212 MM |
103 | |
104 | cpu_exclusive_addr = tcg_global_mem_new_i64(TCG_AREG0, | |
105 | offsetof(CPUARMState, exclusive_addr), "exclusive_addr"); | |
106 | cpu_exclusive_val = tcg_global_mem_new_i64(TCG_AREG0, | |
107 | offsetof(CPUARMState, exclusive_val), "exclusive_val"); | |
108 | cpu_exclusive_high = tcg_global_mem_new_i64(TCG_AREG0, | |
109 | offsetof(CPUARMState, exclusive_high), "exclusive_high"); | |
110 | #ifdef CONFIG_USER_ONLY | |
111 | cpu_exclusive_test = tcg_global_mem_new_i64(TCG_AREG0, | |
112 | offsetof(CPUARMState, exclusive_test), "exclusive_test"); | |
113 | cpu_exclusive_info = tcg_global_mem_new_i32(TCG_AREG0, | |
114 | offsetof(CPUARMState, exclusive_info), "exclusive_info"); | |
115 | #endif | |
14ade10f AG |
116 | } |
117 | ||
118 | void aarch64_cpu_dump_state(CPUState *cs, FILE *f, | |
119 | fprintf_function cpu_fprintf, int flags) | |
120 | { | |
121 | ARMCPU *cpu = ARM_CPU(cs); | |
122 | CPUARMState *env = &cpu->env; | |
d356312f | 123 | uint32_t psr = pstate_read(env); |
14ade10f AG |
124 | int i; |
125 | ||
126 | cpu_fprintf(f, "PC=%016"PRIx64" SP=%016"PRIx64"\n", | |
127 | env->pc, env->xregs[31]); | |
128 | for (i = 0; i < 31; i++) { | |
129 | cpu_fprintf(f, "X%02d=%016"PRIx64, i, env->xregs[i]); | |
130 | if ((i % 4) == 3) { | |
131 | cpu_fprintf(f, "\n"); | |
132 | } else { | |
133 | cpu_fprintf(f, " "); | |
134 | } | |
135 | } | |
d356312f PM |
136 | cpu_fprintf(f, "PSTATE=%08x (flags %c%c%c%c)\n", |
137 | psr, | |
138 | psr & PSTATE_N ? 'N' : '-', | |
139 | psr & PSTATE_Z ? 'Z' : '-', | |
140 | psr & PSTATE_C ? 'C' : '-', | |
141 | psr & PSTATE_V ? 'V' : '-'); | |
14ade10f | 142 | cpu_fprintf(f, "\n"); |
f6d8a314 AG |
143 | |
144 | if (flags & CPU_DUMP_FPU) { | |
145 | int numvfpregs = 32; | |
146 | for (i = 0; i < numvfpregs; i += 2) { | |
147 | uint64_t vlo = float64_val(env->vfp.regs[i * 2]); | |
148 | uint64_t vhi = float64_val(env->vfp.regs[(i * 2) + 1]); | |
149 | cpu_fprintf(f, "q%02d=%016" PRIx64 ":%016" PRIx64 " ", | |
150 | i, vhi, vlo); | |
151 | vlo = float64_val(env->vfp.regs[(i + 1) * 2]); | |
152 | vhi = float64_val(env->vfp.regs[((i + 1) * 2) + 1]); | |
153 | cpu_fprintf(f, "q%02d=%016" PRIx64 ":%016" PRIx64 "\n", | |
154 | i + 1, vhi, vlo); | |
155 | } | |
156 | cpu_fprintf(f, "FPCR: %08x FPSR: %08x\n", | |
157 | vfp_get_fpcr(env), vfp_get_fpsr(env)); | |
158 | } | |
14ade10f AG |
159 | } |
160 | ||
4a08d475 PM |
161 | static int get_mem_index(DisasContext *s) |
162 | { | |
163 | #ifdef CONFIG_USER_ONLY | |
164 | return 1; | |
165 | #else | |
166 | return s->user; | |
167 | #endif | |
168 | } | |
169 | ||
14ade10f AG |
170 | void gen_a64_set_pc_im(uint64_t val) |
171 | { | |
172 | tcg_gen_movi_i64(cpu_pc, val); | |
173 | } | |
174 | ||
175 | static void gen_exception(int excp) | |
176 | { | |
177 | TCGv_i32 tmp = tcg_temp_new_i32(); | |
178 | tcg_gen_movi_i32(tmp, excp); | |
179 | gen_helper_exception(cpu_env, tmp); | |
180 | tcg_temp_free_i32(tmp); | |
181 | } | |
182 | ||
183 | static void gen_exception_insn(DisasContext *s, int offset, int excp) | |
184 | { | |
185 | gen_a64_set_pc_im(s->pc - offset); | |
186 | gen_exception(excp); | |
40f860cd PM |
187 | s->is_jmp = DISAS_EXC; |
188 | } | |
189 | ||
190 | static inline bool use_goto_tb(DisasContext *s, int n, uint64_t dest) | |
191 | { | |
192 | /* No direct tb linking with singlestep or deterministic io */ | |
193 | if (s->singlestep_enabled || (s->tb->cflags & CF_LAST_IO)) { | |
194 | return false; | |
195 | } | |
196 | ||
197 | /* Only link tbs from inside the same guest page */ | |
198 | if ((s->tb->pc & TARGET_PAGE_MASK) != (dest & TARGET_PAGE_MASK)) { | |
199 | return false; | |
200 | } | |
201 | ||
202 | return true; | |
203 | } | |
204 | ||
205 | static inline void gen_goto_tb(DisasContext *s, int n, uint64_t dest) | |
206 | { | |
207 | TranslationBlock *tb; | |
208 | ||
209 | tb = s->tb; | |
210 | if (use_goto_tb(s, n, dest)) { | |
211 | tcg_gen_goto_tb(n); | |
212 | gen_a64_set_pc_im(dest); | |
0624976f | 213 | tcg_gen_exit_tb((intptr_t)tb + n); |
40f860cd PM |
214 | s->is_jmp = DISAS_TB_JUMP; |
215 | } else { | |
216 | gen_a64_set_pc_im(dest); | |
217 | if (s->singlestep_enabled) { | |
218 | gen_exception(EXCP_DEBUG); | |
219 | } | |
220 | tcg_gen_exit_tb(0); | |
221 | s->is_jmp = DISAS_JUMP; | |
222 | } | |
14ade10f AG |
223 | } |
224 | ||
ad7ee8a2 | 225 | static void unallocated_encoding(DisasContext *s) |
14ade10f | 226 | { |
14ade10f AG |
227 | gen_exception_insn(s, 4, EXCP_UDEF); |
228 | } | |
229 | ||
ad7ee8a2 CF |
230 | #define unsupported_encoding(s, insn) \ |
231 | do { \ | |
232 | qemu_log_mask(LOG_UNIMP, \ | |
233 | "%s:%d: unsupported instruction encoding 0x%08x " \ | |
234 | "at pc=%016" PRIx64 "\n", \ | |
235 | __FILE__, __LINE__, insn, s->pc - 4); \ | |
236 | unallocated_encoding(s); \ | |
237 | } while (0); | |
14ade10f | 238 | |
11e169de AG |
239 | static void init_tmp_a64_array(DisasContext *s) |
240 | { | |
241 | #ifdef CONFIG_DEBUG_TCG | |
242 | int i; | |
243 | for (i = 0; i < ARRAY_SIZE(s->tmp_a64); i++) { | |
244 | TCGV_UNUSED_I64(s->tmp_a64[i]); | |
245 | } | |
246 | #endif | |
247 | s->tmp_a64_count = 0; | |
248 | } | |
249 | ||
250 | static void free_tmp_a64(DisasContext *s) | |
251 | { | |
252 | int i; | |
253 | for (i = 0; i < s->tmp_a64_count; i++) { | |
254 | tcg_temp_free_i64(s->tmp_a64[i]); | |
255 | } | |
256 | init_tmp_a64_array(s); | |
257 | } | |
258 | ||
259 | static TCGv_i64 new_tmp_a64(DisasContext *s) | |
260 | { | |
261 | assert(s->tmp_a64_count < TMP_A64_MAX); | |
262 | return s->tmp_a64[s->tmp_a64_count++] = tcg_temp_new_i64(); | |
263 | } | |
264 | ||
265 | static TCGv_i64 new_tmp_a64_zero(DisasContext *s) | |
266 | { | |
267 | TCGv_i64 t = new_tmp_a64(s); | |
268 | tcg_gen_movi_i64(t, 0); | |
269 | return t; | |
270 | } | |
271 | ||
71b46089 AG |
272 | /* |
273 | * Register access functions | |
274 | * | |
275 | * These functions are used for directly accessing a register in where | |
276 | * changes to the final register value are likely to be made. If you | |
277 | * need to use a register for temporary calculation (e.g. index type | |
278 | * operations) use the read_* form. | |
279 | * | |
280 | * B1.2.1 Register mappings | |
281 | * | |
282 | * In instruction register encoding 31 can refer to ZR (zero register) or | |
283 | * the SP (stack pointer) depending on context. In QEMU's case we map SP | |
284 | * to cpu_X[31] and ZR accesses to a temporary which can be discarded. | |
285 | * This is the point of the _sp forms. | |
286 | */ | |
11e169de AG |
287 | static TCGv_i64 cpu_reg(DisasContext *s, int reg) |
288 | { | |
289 | if (reg == 31) { | |
290 | return new_tmp_a64_zero(s); | |
291 | } else { | |
292 | return cpu_X[reg]; | |
293 | } | |
294 | } | |
295 | ||
71b46089 AG |
296 | /* register access for when 31 == SP */ |
297 | static TCGv_i64 cpu_reg_sp(DisasContext *s, int reg) | |
298 | { | |
299 | return cpu_X[reg]; | |
300 | } | |
301 | ||
60e53388 AG |
302 | /* read a cpu register in 32bit/64bit mode. Returns a TCGv_i64 |
303 | * representing the register contents. This TCGv is an auto-freed | |
304 | * temporary so it need not be explicitly freed, and may be modified. | |
305 | */ | |
306 | static TCGv_i64 read_cpu_reg(DisasContext *s, int reg, int sf) | |
307 | { | |
308 | TCGv_i64 v = new_tmp_a64(s); | |
309 | if (reg != 31) { | |
310 | if (sf) { | |
311 | tcg_gen_mov_i64(v, cpu_X[reg]); | |
312 | } else { | |
313 | tcg_gen_ext32u_i64(v, cpu_X[reg]); | |
314 | } | |
315 | } else { | |
316 | tcg_gen_movi_i64(v, 0); | |
317 | } | |
318 | return v; | |
319 | } | |
320 | ||
4a08d475 PM |
321 | static TCGv_i64 read_cpu_reg_sp(DisasContext *s, int reg, int sf) |
322 | { | |
323 | TCGv_i64 v = new_tmp_a64(s); | |
324 | if (sf) { | |
325 | tcg_gen_mov_i64(v, cpu_X[reg]); | |
326 | } else { | |
327 | tcg_gen_ext32u_i64(v, cpu_X[reg]); | |
328 | } | |
329 | return v; | |
330 | } | |
331 | ||
72430bf5 AB |
332 | /* Return the offset into CPUARMState of an element of specified |
333 | * size, 'element' places in from the least significant end of | |
334 | * the FP/vector register Qn. | |
335 | */ | |
336 | static inline int vec_reg_offset(int regno, int element, TCGMemOp size) | |
337 | { | |
338 | int offs = offsetof(CPUARMState, vfp.regs[regno * 2]); | |
339 | #ifdef HOST_WORDS_BIGENDIAN | |
340 | /* This is complicated slightly because vfp.regs[2n] is | |
341 | * still the low half and vfp.regs[2n+1] the high half | |
342 | * of the 128 bit vector, even on big endian systems. | |
343 | * Calculate the offset assuming a fully bigendian 128 bits, | |
344 | * then XOR to account for the order of the two 64 bit halves. | |
345 | */ | |
346 | offs += (16 - ((element + 1) * (1 << size))); | |
347 | offs ^= 8; | |
348 | #else | |
349 | offs += element * (1 << size); | |
350 | #endif | |
351 | return offs; | |
352 | } | |
353 | ||
e2f90565 PM |
354 | /* Return the offset into CPUARMState of a slice (from |
355 | * the least significant end) of FP register Qn (ie | |
356 | * Dn, Sn, Hn or Bn). | |
357 | * (Note that this is not the same mapping as for A32; see cpu.h) | |
358 | */ | |
359 | static inline int fp_reg_offset(int regno, TCGMemOp size) | |
360 | { | |
361 | int offs = offsetof(CPUARMState, vfp.regs[regno * 2]); | |
362 | #ifdef HOST_WORDS_BIGENDIAN | |
363 | offs += (8 - (1 << size)); | |
364 | #endif | |
365 | return offs; | |
366 | } | |
367 | ||
368 | /* Offset of the high half of the 128 bit vector Qn */ | |
369 | static inline int fp_reg_hi_offset(int regno) | |
370 | { | |
371 | return offsetof(CPUARMState, vfp.regs[regno * 2 + 1]); | |
372 | } | |
373 | ||
ec73d2e0 AG |
374 | /* Convenience accessors for reading and writing single and double |
375 | * FP registers. Writing clears the upper parts of the associated | |
376 | * 128 bit vector register, as required by the architecture. | |
377 | * Note that unlike the GP register accessors, the values returned | |
378 | * by the read functions must be manually freed. | |
379 | */ | |
380 | static TCGv_i64 read_fp_dreg(DisasContext *s, int reg) | |
381 | { | |
382 | TCGv_i64 v = tcg_temp_new_i64(); | |
383 | ||
384 | tcg_gen_ld_i64(v, cpu_env, fp_reg_offset(reg, MO_64)); | |
385 | return v; | |
386 | } | |
387 | ||
388 | static TCGv_i32 read_fp_sreg(DisasContext *s, int reg) | |
389 | { | |
390 | TCGv_i32 v = tcg_temp_new_i32(); | |
391 | ||
392 | tcg_gen_ld_i32(v, cpu_env, fp_reg_offset(reg, MO_32)); | |
393 | return v; | |
394 | } | |
395 | ||
396 | static void write_fp_dreg(DisasContext *s, int reg, TCGv_i64 v) | |
397 | { | |
398 | TCGv_i64 tcg_zero = tcg_const_i64(0); | |
399 | ||
400 | tcg_gen_st_i64(v, cpu_env, fp_reg_offset(reg, MO_64)); | |
401 | tcg_gen_st_i64(tcg_zero, cpu_env, fp_reg_hi_offset(reg)); | |
402 | tcg_temp_free_i64(tcg_zero); | |
403 | } | |
404 | ||
405 | static void write_fp_sreg(DisasContext *s, int reg, TCGv_i32 v) | |
406 | { | |
407 | TCGv_i64 tmp = tcg_temp_new_i64(); | |
408 | ||
409 | tcg_gen_extu_i32_i64(tmp, v); | |
410 | write_fp_dreg(s, reg, tmp); | |
411 | tcg_temp_free_i64(tmp); | |
412 | } | |
413 | ||
414 | static TCGv_ptr get_fpstatus_ptr(void) | |
415 | { | |
416 | TCGv_ptr statusptr = tcg_temp_new_ptr(); | |
417 | int offset; | |
418 | ||
419 | /* In A64 all instructions (both FP and Neon) use the FPCR; | |
420 | * there is no equivalent of the A32 Neon "standard FPSCR value" | |
421 | * and all operations use vfp.fp_status. | |
422 | */ | |
423 | offset = offsetof(CPUARMState, vfp.fp_status); | |
424 | tcg_gen_addi_ptr(statusptr, cpu_env, offset); | |
425 | return statusptr; | |
426 | } | |
427 | ||
832ffa1c AG |
428 | /* Set ZF and NF based on a 64 bit result. This is alas fiddlier |
429 | * than the 32 bit equivalent. | |
430 | */ | |
431 | static inline void gen_set_NZ64(TCGv_i64 result) | |
432 | { | |
433 | TCGv_i64 flag = tcg_temp_new_i64(); | |
434 | ||
435 | tcg_gen_setcondi_i64(TCG_COND_NE, flag, result, 0); | |
436 | tcg_gen_trunc_i64_i32(cpu_ZF, flag); | |
437 | tcg_gen_shri_i64(flag, result, 32); | |
438 | tcg_gen_trunc_i64_i32(cpu_NF, flag); | |
439 | tcg_temp_free_i64(flag); | |
440 | } | |
441 | ||
442 | /* Set NZCV as for a logical operation: NZ as per result, CV cleared. */ | |
443 | static inline void gen_logic_CC(int sf, TCGv_i64 result) | |
444 | { | |
445 | if (sf) { | |
446 | gen_set_NZ64(result); | |
447 | } else { | |
448 | tcg_gen_trunc_i64_i32(cpu_ZF, result); | |
449 | tcg_gen_trunc_i64_i32(cpu_NF, result); | |
450 | } | |
451 | tcg_gen_movi_i32(cpu_CF, 0); | |
452 | tcg_gen_movi_i32(cpu_VF, 0); | |
453 | } | |
454 | ||
b0ff21b4 AB |
455 | /* dest = T0 + T1; compute C, N, V and Z flags */ |
456 | static void gen_add_CC(int sf, TCGv_i64 dest, TCGv_i64 t0, TCGv_i64 t1) | |
457 | { | |
458 | if (sf) { | |
459 | TCGv_i64 result, flag, tmp; | |
460 | result = tcg_temp_new_i64(); | |
461 | flag = tcg_temp_new_i64(); | |
462 | tmp = tcg_temp_new_i64(); | |
463 | ||
464 | tcg_gen_movi_i64(tmp, 0); | |
465 | tcg_gen_add2_i64(result, flag, t0, tmp, t1, tmp); | |
466 | ||
467 | tcg_gen_trunc_i64_i32(cpu_CF, flag); | |
468 | ||
469 | gen_set_NZ64(result); | |
470 | ||
471 | tcg_gen_xor_i64(flag, result, t0); | |
472 | tcg_gen_xor_i64(tmp, t0, t1); | |
473 | tcg_gen_andc_i64(flag, flag, tmp); | |
474 | tcg_temp_free_i64(tmp); | |
475 | tcg_gen_shri_i64(flag, flag, 32); | |
476 | tcg_gen_trunc_i64_i32(cpu_VF, flag); | |
477 | ||
478 | tcg_gen_mov_i64(dest, result); | |
479 | tcg_temp_free_i64(result); | |
480 | tcg_temp_free_i64(flag); | |
481 | } else { | |
482 | /* 32 bit arithmetic */ | |
483 | TCGv_i32 t0_32 = tcg_temp_new_i32(); | |
484 | TCGv_i32 t1_32 = tcg_temp_new_i32(); | |
485 | TCGv_i32 tmp = tcg_temp_new_i32(); | |
486 | ||
487 | tcg_gen_movi_i32(tmp, 0); | |
488 | tcg_gen_trunc_i64_i32(t0_32, t0); | |
489 | tcg_gen_trunc_i64_i32(t1_32, t1); | |
490 | tcg_gen_add2_i32(cpu_NF, cpu_CF, t0_32, tmp, t1_32, tmp); | |
491 | tcg_gen_mov_i32(cpu_ZF, cpu_NF); | |
492 | tcg_gen_xor_i32(cpu_VF, cpu_NF, t0_32); | |
493 | tcg_gen_xor_i32(tmp, t0_32, t1_32); | |
494 | tcg_gen_andc_i32(cpu_VF, cpu_VF, tmp); | |
495 | tcg_gen_extu_i32_i64(dest, cpu_NF); | |
496 | ||
497 | tcg_temp_free_i32(tmp); | |
498 | tcg_temp_free_i32(t0_32); | |
499 | tcg_temp_free_i32(t1_32); | |
500 | } | |
501 | } | |
502 | ||
503 | /* dest = T0 - T1; compute C, N, V and Z flags */ | |
504 | static void gen_sub_CC(int sf, TCGv_i64 dest, TCGv_i64 t0, TCGv_i64 t1) | |
505 | { | |
506 | if (sf) { | |
507 | /* 64 bit arithmetic */ | |
508 | TCGv_i64 result, flag, tmp; | |
509 | ||
510 | result = tcg_temp_new_i64(); | |
511 | flag = tcg_temp_new_i64(); | |
512 | tcg_gen_sub_i64(result, t0, t1); | |
513 | ||
514 | gen_set_NZ64(result); | |
515 | ||
516 | tcg_gen_setcond_i64(TCG_COND_GEU, flag, t0, t1); | |
517 | tcg_gen_trunc_i64_i32(cpu_CF, flag); | |
518 | ||
519 | tcg_gen_xor_i64(flag, result, t0); | |
520 | tmp = tcg_temp_new_i64(); | |
521 | tcg_gen_xor_i64(tmp, t0, t1); | |
522 | tcg_gen_and_i64(flag, flag, tmp); | |
523 | tcg_temp_free_i64(tmp); | |
524 | tcg_gen_shri_i64(flag, flag, 32); | |
525 | tcg_gen_trunc_i64_i32(cpu_VF, flag); | |
526 | tcg_gen_mov_i64(dest, result); | |
527 | tcg_temp_free_i64(flag); | |
528 | tcg_temp_free_i64(result); | |
529 | } else { | |
530 | /* 32 bit arithmetic */ | |
531 | TCGv_i32 t0_32 = tcg_temp_new_i32(); | |
532 | TCGv_i32 t1_32 = tcg_temp_new_i32(); | |
533 | TCGv_i32 tmp; | |
534 | ||
535 | tcg_gen_trunc_i64_i32(t0_32, t0); | |
536 | tcg_gen_trunc_i64_i32(t1_32, t1); | |
537 | tcg_gen_sub_i32(cpu_NF, t0_32, t1_32); | |
538 | tcg_gen_mov_i32(cpu_ZF, cpu_NF); | |
539 | tcg_gen_setcond_i32(TCG_COND_GEU, cpu_CF, t0_32, t1_32); | |
540 | tcg_gen_xor_i32(cpu_VF, cpu_NF, t0_32); | |
541 | tmp = tcg_temp_new_i32(); | |
542 | tcg_gen_xor_i32(tmp, t0_32, t1_32); | |
543 | tcg_temp_free_i32(t0_32); | |
544 | tcg_temp_free_i32(t1_32); | |
545 | tcg_gen_and_i32(cpu_VF, cpu_VF, tmp); | |
546 | tcg_temp_free_i32(tmp); | |
547 | tcg_gen_extu_i32_i64(dest, cpu_NF); | |
548 | } | |
549 | } | |
550 | ||
643dbb07 CF |
551 | /* dest = T0 + T1 + CF; do not compute flags. */ |
552 | static void gen_adc(int sf, TCGv_i64 dest, TCGv_i64 t0, TCGv_i64 t1) | |
553 | { | |
554 | TCGv_i64 flag = tcg_temp_new_i64(); | |
555 | tcg_gen_extu_i32_i64(flag, cpu_CF); | |
556 | tcg_gen_add_i64(dest, t0, t1); | |
557 | tcg_gen_add_i64(dest, dest, flag); | |
558 | tcg_temp_free_i64(flag); | |
559 | ||
560 | if (!sf) { | |
561 | tcg_gen_ext32u_i64(dest, dest); | |
562 | } | |
563 | } | |
564 | ||
565 | /* dest = T0 + T1 + CF; compute C, N, V and Z flags. */ | |
566 | static void gen_adc_CC(int sf, TCGv_i64 dest, TCGv_i64 t0, TCGv_i64 t1) | |
567 | { | |
568 | if (sf) { | |
569 | TCGv_i64 result, cf_64, vf_64, tmp; | |
570 | result = tcg_temp_new_i64(); | |
571 | cf_64 = tcg_temp_new_i64(); | |
572 | vf_64 = tcg_temp_new_i64(); | |
573 | tmp = tcg_const_i64(0); | |
574 | ||
575 | tcg_gen_extu_i32_i64(cf_64, cpu_CF); | |
576 | tcg_gen_add2_i64(result, cf_64, t0, tmp, cf_64, tmp); | |
577 | tcg_gen_add2_i64(result, cf_64, result, cf_64, t1, tmp); | |
578 | tcg_gen_trunc_i64_i32(cpu_CF, cf_64); | |
579 | gen_set_NZ64(result); | |
580 | ||
581 | tcg_gen_xor_i64(vf_64, result, t0); | |
582 | tcg_gen_xor_i64(tmp, t0, t1); | |
583 | tcg_gen_andc_i64(vf_64, vf_64, tmp); | |
584 | tcg_gen_shri_i64(vf_64, vf_64, 32); | |
585 | tcg_gen_trunc_i64_i32(cpu_VF, vf_64); | |
586 | ||
587 | tcg_gen_mov_i64(dest, result); | |
588 | ||
589 | tcg_temp_free_i64(tmp); | |
590 | tcg_temp_free_i64(vf_64); | |
591 | tcg_temp_free_i64(cf_64); | |
592 | tcg_temp_free_i64(result); | |
593 | } else { | |
594 | TCGv_i32 t0_32, t1_32, tmp; | |
595 | t0_32 = tcg_temp_new_i32(); | |
596 | t1_32 = tcg_temp_new_i32(); | |
597 | tmp = tcg_const_i32(0); | |
598 | ||
599 | tcg_gen_trunc_i64_i32(t0_32, t0); | |
600 | tcg_gen_trunc_i64_i32(t1_32, t1); | |
601 | tcg_gen_add2_i32(cpu_NF, cpu_CF, t0_32, tmp, cpu_CF, tmp); | |
602 | tcg_gen_add2_i32(cpu_NF, cpu_CF, cpu_NF, cpu_CF, t1_32, tmp); | |
603 | ||
604 | tcg_gen_mov_i32(cpu_ZF, cpu_NF); | |
605 | tcg_gen_xor_i32(cpu_VF, cpu_NF, t0_32); | |
606 | tcg_gen_xor_i32(tmp, t0_32, t1_32); | |
607 | tcg_gen_andc_i32(cpu_VF, cpu_VF, tmp); | |
608 | tcg_gen_extu_i32_i64(dest, cpu_NF); | |
609 | ||
610 | tcg_temp_free_i32(tmp); | |
611 | tcg_temp_free_i32(t1_32); | |
612 | tcg_temp_free_i32(t0_32); | |
613 | } | |
614 | } | |
615 | ||
4a08d475 PM |
616 | /* |
617 | * Load/Store generators | |
618 | */ | |
619 | ||
620 | /* | |
60510aed | 621 | * Store from GPR register to memory. |
4a08d475 | 622 | */ |
60510aed PM |
623 | static void do_gpr_st_memidx(DisasContext *s, TCGv_i64 source, |
624 | TCGv_i64 tcg_addr, int size, int memidx) | |
625 | { | |
626 | g_assert(size <= 3); | |
627 | tcg_gen_qemu_st_i64(source, tcg_addr, memidx, MO_TE + size); | |
628 | } | |
629 | ||
4a08d475 PM |
630 | static void do_gpr_st(DisasContext *s, TCGv_i64 source, |
631 | TCGv_i64 tcg_addr, int size) | |
632 | { | |
60510aed | 633 | do_gpr_st_memidx(s, source, tcg_addr, size, get_mem_index(s)); |
4a08d475 PM |
634 | } |
635 | ||
636 | /* | |
637 | * Load from memory to GPR register | |
638 | */ | |
60510aed PM |
639 | static void do_gpr_ld_memidx(DisasContext *s, TCGv_i64 dest, TCGv_i64 tcg_addr, |
640 | int size, bool is_signed, bool extend, int memidx) | |
4a08d475 PM |
641 | { |
642 | TCGMemOp memop = MO_TE + size; | |
643 | ||
644 | g_assert(size <= 3); | |
645 | ||
646 | if (is_signed) { | |
647 | memop += MO_SIGN; | |
648 | } | |
649 | ||
60510aed | 650 | tcg_gen_qemu_ld_i64(dest, tcg_addr, memidx, memop); |
4a08d475 PM |
651 | |
652 | if (extend && is_signed) { | |
653 | g_assert(size < 3); | |
654 | tcg_gen_ext32u_i64(dest, dest); | |
655 | } | |
656 | } | |
657 | ||
60510aed PM |
658 | static void do_gpr_ld(DisasContext *s, TCGv_i64 dest, TCGv_i64 tcg_addr, |
659 | int size, bool is_signed, bool extend) | |
660 | { | |
661 | do_gpr_ld_memidx(s, dest, tcg_addr, size, is_signed, extend, | |
662 | get_mem_index(s)); | |
663 | } | |
664 | ||
4a08d475 PM |
665 | /* |
666 | * Store from FP register to memory | |
667 | */ | |
668 | static void do_fp_st(DisasContext *s, int srcidx, TCGv_i64 tcg_addr, int size) | |
669 | { | |
670 | /* This writes the bottom N bits of a 128 bit wide vector to memory */ | |
4a08d475 | 671 | TCGv_i64 tmp = tcg_temp_new_i64(); |
e2f90565 | 672 | tcg_gen_ld_i64(tmp, cpu_env, fp_reg_offset(srcidx, MO_64)); |
4a08d475 | 673 | if (size < 4) { |
4a08d475 PM |
674 | tcg_gen_qemu_st_i64(tmp, tcg_addr, get_mem_index(s), MO_TE + size); |
675 | } else { | |
676 | TCGv_i64 tcg_hiaddr = tcg_temp_new_i64(); | |
4a08d475 PM |
677 | tcg_gen_qemu_st_i64(tmp, tcg_addr, get_mem_index(s), MO_TEQ); |
678 | tcg_gen_qemu_st64(tmp, tcg_addr, get_mem_index(s)); | |
e2f90565 | 679 | tcg_gen_ld_i64(tmp, cpu_env, fp_reg_hi_offset(srcidx)); |
4a08d475 PM |
680 | tcg_gen_addi_i64(tcg_hiaddr, tcg_addr, 8); |
681 | tcg_gen_qemu_st_i64(tmp, tcg_hiaddr, get_mem_index(s), MO_TEQ); | |
682 | tcg_temp_free_i64(tcg_hiaddr); | |
683 | } | |
684 | ||
685 | tcg_temp_free_i64(tmp); | |
686 | } | |
687 | ||
688 | /* | |
689 | * Load from memory to FP register | |
690 | */ | |
691 | static void do_fp_ld(DisasContext *s, int destidx, TCGv_i64 tcg_addr, int size) | |
692 | { | |
693 | /* This always zero-extends and writes to a full 128 bit wide vector */ | |
4a08d475 PM |
694 | TCGv_i64 tmplo = tcg_temp_new_i64(); |
695 | TCGv_i64 tmphi; | |
696 | ||
697 | if (size < 4) { | |
698 | TCGMemOp memop = MO_TE + size; | |
699 | tmphi = tcg_const_i64(0); | |
700 | tcg_gen_qemu_ld_i64(tmplo, tcg_addr, get_mem_index(s), memop); | |
701 | } else { | |
702 | TCGv_i64 tcg_hiaddr; | |
703 | tmphi = tcg_temp_new_i64(); | |
704 | tcg_hiaddr = tcg_temp_new_i64(); | |
705 | ||
706 | tcg_gen_qemu_ld_i64(tmplo, tcg_addr, get_mem_index(s), MO_TEQ); | |
707 | tcg_gen_addi_i64(tcg_hiaddr, tcg_addr, 8); | |
708 | tcg_gen_qemu_ld_i64(tmphi, tcg_hiaddr, get_mem_index(s), MO_TEQ); | |
709 | tcg_temp_free_i64(tcg_hiaddr); | |
710 | } | |
711 | ||
e2f90565 PM |
712 | tcg_gen_st_i64(tmplo, cpu_env, fp_reg_offset(destidx, MO_64)); |
713 | tcg_gen_st_i64(tmphi, cpu_env, fp_reg_hi_offset(destidx)); | |
4a08d475 PM |
714 | |
715 | tcg_temp_free_i64(tmplo); | |
716 | tcg_temp_free_i64(tmphi); | |
717 | } | |
718 | ||
72430bf5 AB |
719 | /* |
720 | * Vector load/store helpers. | |
721 | * | |
722 | * The principal difference between this and a FP load is that we don't | |
723 | * zero extend as we are filling a partial chunk of the vector register. | |
724 | * These functions don't support 128 bit loads/stores, which would be | |
725 | * normal load/store operations. | |
a08582f4 PM |
726 | * |
727 | * The _i32 versions are useful when operating on 32 bit quantities | |
728 | * (eg for floating point single or using Neon helper functions). | |
72430bf5 AB |
729 | */ |
730 | ||
731 | /* Get value of an element within a vector register */ | |
732 | static void read_vec_element(DisasContext *s, TCGv_i64 tcg_dest, int srcidx, | |
733 | int element, TCGMemOp memop) | |
734 | { | |
735 | int vect_off = vec_reg_offset(srcidx, element, memop & MO_SIZE); | |
736 | switch (memop) { | |
737 | case MO_8: | |
738 | tcg_gen_ld8u_i64(tcg_dest, cpu_env, vect_off); | |
739 | break; | |
740 | case MO_16: | |
741 | tcg_gen_ld16u_i64(tcg_dest, cpu_env, vect_off); | |
742 | break; | |
743 | case MO_32: | |
744 | tcg_gen_ld32u_i64(tcg_dest, cpu_env, vect_off); | |
745 | break; | |
746 | case MO_8|MO_SIGN: | |
747 | tcg_gen_ld8s_i64(tcg_dest, cpu_env, vect_off); | |
748 | break; | |
749 | case MO_16|MO_SIGN: | |
750 | tcg_gen_ld16s_i64(tcg_dest, cpu_env, vect_off); | |
751 | break; | |
752 | case MO_32|MO_SIGN: | |
753 | tcg_gen_ld32s_i64(tcg_dest, cpu_env, vect_off); | |
754 | break; | |
755 | case MO_64: | |
756 | case MO_64|MO_SIGN: | |
757 | tcg_gen_ld_i64(tcg_dest, cpu_env, vect_off); | |
758 | break; | |
759 | default: | |
760 | g_assert_not_reached(); | |
761 | } | |
762 | } | |
763 | ||
a08582f4 PM |
764 | static void read_vec_element_i32(DisasContext *s, TCGv_i32 tcg_dest, int srcidx, |
765 | int element, TCGMemOp memop) | |
766 | { | |
767 | int vect_off = vec_reg_offset(srcidx, element, memop & MO_SIZE); | |
768 | switch (memop) { | |
769 | case MO_8: | |
770 | tcg_gen_ld8u_i32(tcg_dest, cpu_env, vect_off); | |
771 | break; | |
772 | case MO_16: | |
773 | tcg_gen_ld16u_i32(tcg_dest, cpu_env, vect_off); | |
774 | break; | |
775 | case MO_8|MO_SIGN: | |
776 | tcg_gen_ld8s_i32(tcg_dest, cpu_env, vect_off); | |
777 | break; | |
778 | case MO_16|MO_SIGN: | |
779 | tcg_gen_ld16s_i32(tcg_dest, cpu_env, vect_off); | |
780 | break; | |
781 | case MO_32: | |
782 | case MO_32|MO_SIGN: | |
783 | tcg_gen_ld_i32(tcg_dest, cpu_env, vect_off); | |
784 | break; | |
785 | default: | |
786 | g_assert_not_reached(); | |
787 | } | |
788 | } | |
789 | ||
72430bf5 AB |
790 | /* Set value of an element within a vector register */ |
791 | static void write_vec_element(DisasContext *s, TCGv_i64 tcg_src, int destidx, | |
792 | int element, TCGMemOp memop) | |
793 | { | |
794 | int vect_off = vec_reg_offset(destidx, element, memop & MO_SIZE); | |
795 | switch (memop) { | |
796 | case MO_8: | |
797 | tcg_gen_st8_i64(tcg_src, cpu_env, vect_off); | |
798 | break; | |
799 | case MO_16: | |
800 | tcg_gen_st16_i64(tcg_src, cpu_env, vect_off); | |
801 | break; | |
802 | case MO_32: | |
803 | tcg_gen_st32_i64(tcg_src, cpu_env, vect_off); | |
804 | break; | |
805 | case MO_64: | |
806 | tcg_gen_st_i64(tcg_src, cpu_env, vect_off); | |
807 | break; | |
808 | default: | |
809 | g_assert_not_reached(); | |
810 | } | |
811 | } | |
812 | ||
1f8a73af PM |
813 | static void write_vec_element_i32(DisasContext *s, TCGv_i32 tcg_src, |
814 | int destidx, int element, TCGMemOp memop) | |
815 | { | |
816 | int vect_off = vec_reg_offset(destidx, element, memop & MO_SIZE); | |
817 | switch (memop) { | |
818 | case MO_8: | |
819 | tcg_gen_st8_i32(tcg_src, cpu_env, vect_off); | |
820 | break; | |
821 | case MO_16: | |
822 | tcg_gen_st16_i32(tcg_src, cpu_env, vect_off); | |
823 | break; | |
824 | case MO_32: | |
825 | tcg_gen_st_i32(tcg_src, cpu_env, vect_off); | |
826 | break; | |
827 | default: | |
828 | g_assert_not_reached(); | |
829 | } | |
830 | } | |
831 | ||
72430bf5 AB |
832 | /* Clear the high 64 bits of a 128 bit vector (in general non-quad |
833 | * vector ops all need to do this). | |
834 | */ | |
835 | static void clear_vec_high(DisasContext *s, int rd) | |
836 | { | |
837 | TCGv_i64 tcg_zero = tcg_const_i64(0); | |
838 | ||
839 | write_vec_element(s, tcg_zero, rd, 1, MO_64); | |
840 | tcg_temp_free_i64(tcg_zero); | |
841 | } | |
842 | ||
843 | /* Store from vector register to memory */ | |
844 | static void do_vec_st(DisasContext *s, int srcidx, int element, | |
845 | TCGv_i64 tcg_addr, int size) | |
846 | { | |
847 | TCGMemOp memop = MO_TE + size; | |
848 | TCGv_i64 tcg_tmp = tcg_temp_new_i64(); | |
849 | ||
850 | read_vec_element(s, tcg_tmp, srcidx, element, size); | |
851 | tcg_gen_qemu_st_i64(tcg_tmp, tcg_addr, get_mem_index(s), memop); | |
852 | ||
853 | tcg_temp_free_i64(tcg_tmp); | |
854 | } | |
855 | ||
856 | /* Load from memory to vector register */ | |
857 | static void do_vec_ld(DisasContext *s, int destidx, int element, | |
858 | TCGv_i64 tcg_addr, int size) | |
859 | { | |
860 | TCGMemOp memop = MO_TE + size; | |
861 | TCGv_i64 tcg_tmp = tcg_temp_new_i64(); | |
862 | ||
863 | tcg_gen_qemu_ld_i64(tcg_tmp, tcg_addr, get_mem_index(s), memop); | |
864 | write_vec_element(s, tcg_tmp, destidx, element, size); | |
865 | ||
866 | tcg_temp_free_i64(tcg_tmp); | |
867 | } | |
868 | ||
229b7a05 AB |
869 | /* |
870 | * This utility function is for doing register extension with an | |
871 | * optional shift. You will likely want to pass a temporary for the | |
872 | * destination register. See DecodeRegExtend() in the ARM ARM. | |
873 | */ | |
874 | static void ext_and_shift_reg(TCGv_i64 tcg_out, TCGv_i64 tcg_in, | |
875 | int option, unsigned int shift) | |
876 | { | |
877 | int extsize = extract32(option, 0, 2); | |
878 | bool is_signed = extract32(option, 2, 1); | |
879 | ||
880 | if (is_signed) { | |
881 | switch (extsize) { | |
882 | case 0: | |
883 | tcg_gen_ext8s_i64(tcg_out, tcg_in); | |
884 | break; | |
885 | case 1: | |
886 | tcg_gen_ext16s_i64(tcg_out, tcg_in); | |
887 | break; | |
888 | case 2: | |
889 | tcg_gen_ext32s_i64(tcg_out, tcg_in); | |
890 | break; | |
891 | case 3: | |
892 | tcg_gen_mov_i64(tcg_out, tcg_in); | |
893 | break; | |
894 | } | |
895 | } else { | |
896 | switch (extsize) { | |
897 | case 0: | |
898 | tcg_gen_ext8u_i64(tcg_out, tcg_in); | |
899 | break; | |
900 | case 1: | |
901 | tcg_gen_ext16u_i64(tcg_out, tcg_in); | |
902 | break; | |
903 | case 2: | |
904 | tcg_gen_ext32u_i64(tcg_out, tcg_in); | |
905 | break; | |
906 | case 3: | |
907 | tcg_gen_mov_i64(tcg_out, tcg_in); | |
908 | break; | |
909 | } | |
910 | } | |
911 | ||
912 | if (shift) { | |
913 | tcg_gen_shli_i64(tcg_out, tcg_out, shift); | |
914 | } | |
915 | } | |
916 | ||
4a08d475 PM |
917 | static inline void gen_check_sp_alignment(DisasContext *s) |
918 | { | |
919 | /* The AArch64 architecture mandates that (if enabled via PSTATE | |
920 | * or SCTLR bits) there is a check that SP is 16-aligned on every | |
921 | * SP-relative load or store (with an exception generated if it is not). | |
922 | * In line with general QEMU practice regarding misaligned accesses, | |
923 | * we omit these checks for the sake of guest program performance. | |
924 | * This function is provided as a hook so we can more easily add these | |
925 | * checks in future (possibly as a "favour catching guest program bugs | |
926 | * over speed" user selectable option). | |
927 | */ | |
928 | } | |
929 | ||
384b26fb AB |
930 | /* |
931 | * This provides a simple table based table lookup decoder. It is | |
932 | * intended to be used when the relevant bits for decode are too | |
933 | * awkwardly placed and switch/if based logic would be confusing and | |
934 | * deeply nested. Since it's a linear search through the table, tables | |
935 | * should be kept small. | |
936 | * | |
937 | * It returns the first handler where insn & mask == pattern, or | |
938 | * NULL if there is no match. | |
939 | * The table is terminated by an empty mask (i.e. 0) | |
940 | */ | |
941 | static inline AArch64DecodeFn *lookup_disas_fn(const AArch64DecodeTable *table, | |
942 | uint32_t insn) | |
943 | { | |
944 | const AArch64DecodeTable *tptr = table; | |
945 | ||
946 | while (tptr->mask) { | |
947 | if ((insn & tptr->mask) == tptr->pattern) { | |
948 | return tptr->disas_fn; | |
949 | } | |
950 | tptr++; | |
951 | } | |
952 | return NULL; | |
953 | } | |
954 | ||
ad7ee8a2 CF |
955 | /* |
956 | * the instruction disassembly implemented here matches | |
957 | * the instruction encoding classifications in chapter 3 (C3) | |
958 | * of the ARM Architecture Reference Manual (DDI0487A_a) | |
959 | */ | |
960 | ||
11e169de AG |
961 | /* C3.2.7 Unconditional branch (immediate) |
962 | * 31 30 26 25 0 | |
963 | * +----+-----------+-------------------------------------+ | |
964 | * | op | 0 0 1 0 1 | imm26 | | |
965 | * +----+-----------+-------------------------------------+ | |
966 | */ | |
ad7ee8a2 CF |
967 | static void disas_uncond_b_imm(DisasContext *s, uint32_t insn) |
968 | { | |
11e169de AG |
969 | uint64_t addr = s->pc + sextract32(insn, 0, 26) * 4 - 4; |
970 | ||
971 | if (insn & (1 << 31)) { | |
972 | /* C5.6.26 BL Branch with link */ | |
973 | tcg_gen_movi_i64(cpu_reg(s, 30), s->pc); | |
974 | } | |
975 | ||
976 | /* C5.6.20 B Branch / C5.6.26 BL Branch with link */ | |
977 | gen_goto_tb(s, 0, addr); | |
ad7ee8a2 CF |
978 | } |
979 | ||
60e53388 AG |
980 | /* C3.2.1 Compare & branch (immediate) |
981 | * 31 30 25 24 23 5 4 0 | |
982 | * +----+-------------+----+---------------------+--------+ | |
983 | * | sf | 0 1 1 0 1 0 | op | imm19 | Rt | | |
984 | * +----+-------------+----+---------------------+--------+ | |
985 | */ | |
ad7ee8a2 CF |
986 | static void disas_comp_b_imm(DisasContext *s, uint32_t insn) |
987 | { | |
60e53388 AG |
988 | unsigned int sf, op, rt; |
989 | uint64_t addr; | |
990 | int label_match; | |
991 | TCGv_i64 tcg_cmp; | |
992 | ||
993 | sf = extract32(insn, 31, 1); | |
994 | op = extract32(insn, 24, 1); /* 0: CBZ; 1: CBNZ */ | |
995 | rt = extract32(insn, 0, 5); | |
996 | addr = s->pc + sextract32(insn, 5, 19) * 4 - 4; | |
997 | ||
998 | tcg_cmp = read_cpu_reg(s, rt, sf); | |
999 | label_match = gen_new_label(); | |
1000 | ||
1001 | tcg_gen_brcondi_i64(op ? TCG_COND_NE : TCG_COND_EQ, | |
1002 | tcg_cmp, 0, label_match); | |
1003 | ||
1004 | gen_goto_tb(s, 0, s->pc); | |
1005 | gen_set_label(label_match); | |
1006 | gen_goto_tb(s, 1, addr); | |
ad7ee8a2 CF |
1007 | } |
1008 | ||
db0f7958 AG |
1009 | /* C3.2.5 Test & branch (immediate) |
1010 | * 31 30 25 24 23 19 18 5 4 0 | |
1011 | * +----+-------------+----+-------+-------------+------+ | |
1012 | * | b5 | 0 1 1 0 1 1 | op | b40 | imm14 | Rt | | |
1013 | * +----+-------------+----+-------+-------------+------+ | |
1014 | */ | |
ad7ee8a2 CF |
1015 | static void disas_test_b_imm(DisasContext *s, uint32_t insn) |
1016 | { | |
db0f7958 AG |
1017 | unsigned int bit_pos, op, rt; |
1018 | uint64_t addr; | |
1019 | int label_match; | |
1020 | TCGv_i64 tcg_cmp; | |
1021 | ||
1022 | bit_pos = (extract32(insn, 31, 1) << 5) | extract32(insn, 19, 5); | |
1023 | op = extract32(insn, 24, 1); /* 0: TBZ; 1: TBNZ */ | |
1024 | addr = s->pc + sextract32(insn, 5, 14) * 4 - 4; | |
1025 | rt = extract32(insn, 0, 5); | |
1026 | ||
1027 | tcg_cmp = tcg_temp_new_i64(); | |
1028 | tcg_gen_andi_i64(tcg_cmp, cpu_reg(s, rt), (1ULL << bit_pos)); | |
1029 | label_match = gen_new_label(); | |
1030 | tcg_gen_brcondi_i64(op ? TCG_COND_NE : TCG_COND_EQ, | |
1031 | tcg_cmp, 0, label_match); | |
1032 | tcg_temp_free_i64(tcg_cmp); | |
1033 | gen_goto_tb(s, 0, s->pc); | |
1034 | gen_set_label(label_match); | |
1035 | gen_goto_tb(s, 1, addr); | |
ad7ee8a2 CF |
1036 | } |
1037 | ||
39fb730a AG |
1038 | /* C3.2.2 / C5.6.19 Conditional branch (immediate) |
1039 | * 31 25 24 23 5 4 3 0 | |
1040 | * +---------------+----+---------------------+----+------+ | |
1041 | * | 0 1 0 1 0 1 0 | o1 | imm19 | o0 | cond | | |
1042 | * +---------------+----+---------------------+----+------+ | |
1043 | */ | |
ad7ee8a2 CF |
1044 | static void disas_cond_b_imm(DisasContext *s, uint32_t insn) |
1045 | { | |
39fb730a AG |
1046 | unsigned int cond; |
1047 | uint64_t addr; | |
1048 | ||
1049 | if ((insn & (1 << 4)) || (insn & (1 << 24))) { | |
1050 | unallocated_encoding(s); | |
1051 | return; | |
1052 | } | |
1053 | addr = s->pc + sextract32(insn, 5, 19) * 4 - 4; | |
1054 | cond = extract32(insn, 0, 4); | |
1055 | ||
1056 | if (cond < 0x0e) { | |
1057 | /* genuinely conditional branches */ | |
1058 | int label_match = gen_new_label(); | |
1059 | arm_gen_test_cc(cond, label_match); | |
1060 | gen_goto_tb(s, 0, s->pc); | |
1061 | gen_set_label(label_match); | |
1062 | gen_goto_tb(s, 1, addr); | |
1063 | } else { | |
1064 | /* 0xe and 0xf are both "always" conditions */ | |
1065 | gen_goto_tb(s, 0, addr); | |
1066 | } | |
ad7ee8a2 CF |
1067 | } |
1068 | ||
87462e0f CF |
1069 | /* C5.6.68 HINT */ |
1070 | static void handle_hint(DisasContext *s, uint32_t insn, | |
1071 | unsigned int op1, unsigned int op2, unsigned int crm) | |
1072 | { | |
1073 | unsigned int selector = crm << 3 | op2; | |
1074 | ||
1075 | if (op1 != 3) { | |
1076 | unallocated_encoding(s); | |
1077 | return; | |
1078 | } | |
1079 | ||
1080 | switch (selector) { | |
1081 | case 0: /* NOP */ | |
1082 | return; | |
1ed69e82 PM |
1083 | case 3: /* WFI */ |
1084 | s->is_jmp = DISAS_WFI; | |
1085 | return; | |
87462e0f CF |
1086 | case 1: /* YIELD */ |
1087 | case 2: /* WFE */ | |
87462e0f CF |
1088 | case 4: /* SEV */ |
1089 | case 5: /* SEVL */ | |
1090 | /* we treat all as NOP at least for now */ | |
1091 | return; | |
1092 | default: | |
1093 | /* default specified as NOP equivalent */ | |
1094 | return; | |
1095 | } | |
1096 | } | |
1097 | ||
fa2ef212 MM |
1098 | static void gen_clrex(DisasContext *s, uint32_t insn) |
1099 | { | |
1100 | tcg_gen_movi_i64(cpu_exclusive_addr, -1); | |
1101 | } | |
1102 | ||
87462e0f CF |
1103 | /* CLREX, DSB, DMB, ISB */ |
1104 | static void handle_sync(DisasContext *s, uint32_t insn, | |
1105 | unsigned int op1, unsigned int op2, unsigned int crm) | |
1106 | { | |
1107 | if (op1 != 3) { | |
1108 | unallocated_encoding(s); | |
1109 | return; | |
1110 | } | |
1111 | ||
1112 | switch (op2) { | |
1113 | case 2: /* CLREX */ | |
fa2ef212 | 1114 | gen_clrex(s, insn); |
87462e0f CF |
1115 | return; |
1116 | case 4: /* DSB */ | |
1117 | case 5: /* DMB */ | |
1118 | case 6: /* ISB */ | |
1119 | /* We don't emulate caches so barriers are no-ops */ | |
1120 | return; | |
1121 | default: | |
1122 | unallocated_encoding(s); | |
1123 | return; | |
1124 | } | |
1125 | } | |
1126 | ||
1127 | /* C5.6.130 MSR (immediate) - move immediate to processor state field */ | |
1128 | static void handle_msr_i(DisasContext *s, uint32_t insn, | |
1129 | unsigned int op1, unsigned int op2, unsigned int crm) | |
1130 | { | |
9cfa0b4e PM |
1131 | int op = op1 << 3 | op2; |
1132 | switch (op) { | |
1133 | case 0x05: /* SPSel */ | |
1134 | if (s->current_pl == 0) { | |
1135 | unallocated_encoding(s); | |
1136 | return; | |
1137 | } | |
1138 | /* fall through */ | |
1139 | case 0x1e: /* DAIFSet */ | |
1140 | case 0x1f: /* DAIFClear */ | |
1141 | { | |
1142 | TCGv_i32 tcg_imm = tcg_const_i32(crm); | |
1143 | TCGv_i32 tcg_op = tcg_const_i32(op); | |
1144 | gen_a64_set_pc_im(s->pc - 4); | |
1145 | gen_helper_msr_i_pstate(cpu_env, tcg_op, tcg_imm); | |
1146 | tcg_temp_free_i32(tcg_imm); | |
1147 | tcg_temp_free_i32(tcg_op); | |
1148 | s->is_jmp = DISAS_UPDATE; | |
1149 | break; | |
1150 | } | |
1151 | default: | |
1152 | unallocated_encoding(s); | |
1153 | return; | |
1154 | } | |
87462e0f CF |
1155 | } |
1156 | ||
b0d2b7d0 PM |
1157 | static void gen_get_nzcv(TCGv_i64 tcg_rt) |
1158 | { | |
1159 | TCGv_i32 tmp = tcg_temp_new_i32(); | |
1160 | TCGv_i32 nzcv = tcg_temp_new_i32(); | |
1161 | ||
1162 | /* build bit 31, N */ | |
1163 | tcg_gen_andi_i32(nzcv, cpu_NF, (1 << 31)); | |
1164 | /* build bit 30, Z */ | |
1165 | tcg_gen_setcondi_i32(TCG_COND_EQ, tmp, cpu_ZF, 0); | |
1166 | tcg_gen_deposit_i32(nzcv, nzcv, tmp, 30, 1); | |
1167 | /* build bit 29, C */ | |
1168 | tcg_gen_deposit_i32(nzcv, nzcv, cpu_CF, 29, 1); | |
1169 | /* build bit 28, V */ | |
1170 | tcg_gen_shri_i32(tmp, cpu_VF, 31); | |
1171 | tcg_gen_deposit_i32(nzcv, nzcv, tmp, 28, 1); | |
1172 | /* generate result */ | |
1173 | tcg_gen_extu_i32_i64(tcg_rt, nzcv); | |
1174 | ||
1175 | tcg_temp_free_i32(nzcv); | |
1176 | tcg_temp_free_i32(tmp); | |
1177 | } | |
1178 | ||
1179 | static void gen_set_nzcv(TCGv_i64 tcg_rt) | |
1180 | ||
1181 | { | |
1182 | TCGv_i32 nzcv = tcg_temp_new_i32(); | |
1183 | ||
1184 | /* take NZCV from R[t] */ | |
1185 | tcg_gen_trunc_i64_i32(nzcv, tcg_rt); | |
1186 | ||
1187 | /* bit 31, N */ | |
1188 | tcg_gen_andi_i32(cpu_NF, nzcv, (1 << 31)); | |
1189 | /* bit 30, Z */ | |
1190 | tcg_gen_andi_i32(cpu_ZF, nzcv, (1 << 30)); | |
1191 | tcg_gen_setcondi_i32(TCG_COND_EQ, cpu_ZF, cpu_ZF, 0); | |
1192 | /* bit 29, C */ | |
1193 | tcg_gen_andi_i32(cpu_CF, nzcv, (1 << 29)); | |
1194 | tcg_gen_shri_i32(cpu_CF, cpu_CF, 29); | |
1195 | /* bit 28, V */ | |
1196 | tcg_gen_andi_i32(cpu_VF, nzcv, (1 << 28)); | |
1197 | tcg_gen_shli_i32(cpu_VF, cpu_VF, 3); | |
1198 | tcg_temp_free_i32(nzcv); | |
1199 | } | |
1200 | ||
fea50522 PM |
1201 | /* C5.6.129 MRS - move from system register |
1202 | * C5.6.131 MSR (register) - move to system register | |
1203 | * C5.6.204 SYS | |
1204 | * C5.6.205 SYSL | |
1205 | * These are all essentially the same insn in 'read' and 'write' | |
1206 | * versions, with varying op0 fields. | |
1207 | */ | |
1208 | static void handle_sys(DisasContext *s, uint32_t insn, bool isread, | |
1209 | unsigned int op0, unsigned int op1, unsigned int op2, | |
87462e0f CF |
1210 | unsigned int crn, unsigned int crm, unsigned int rt) |
1211 | { | |
fea50522 PM |
1212 | const ARMCPRegInfo *ri; |
1213 | TCGv_i64 tcg_rt; | |
87462e0f | 1214 | |
fea50522 PM |
1215 | ri = get_arm_cp_reginfo(s->cp_regs, |
1216 | ENCODE_AA64_CP_REG(CP_REG_ARM64_SYSREG_CP, | |
1217 | crn, crm, op0, op1, op2)); | |
87462e0f | 1218 | |
fea50522 | 1219 | if (!ri) { |
626187d8 PM |
1220 | /* Unknown register; this might be a guest error or a QEMU |
1221 | * unimplemented feature. | |
1222 | */ | |
1223 | qemu_log_mask(LOG_UNIMP, "%s access to unsupported AArch64 " | |
1224 | "system register op0:%d op1:%d crn:%d crm:%d op2:%d\n", | |
1225 | isread ? "read" : "write", op0, op1, crn, crm, op2); | |
fea50522 PM |
1226 | unallocated_encoding(s); |
1227 | return; | |
1228 | } | |
1229 | ||
1230 | /* Check access permissions */ | |
1231 | if (!cp_access_ok(s->current_pl, ri, isread)) { | |
1232 | unallocated_encoding(s); | |
1233 | return; | |
1234 | } | |
1235 | ||
f59df3f2 PM |
1236 | if (ri->accessfn) { |
1237 | /* Emit code to perform further access permissions checks at | |
1238 | * runtime; this may result in an exception. | |
1239 | */ | |
1240 | TCGv_ptr tmpptr; | |
1241 | gen_a64_set_pc_im(s->pc - 4); | |
1242 | tmpptr = tcg_const_ptr(ri); | |
1243 | gen_helper_access_check_cp_reg(cpu_env, tmpptr); | |
1244 | tcg_temp_free_ptr(tmpptr); | |
1245 | } | |
1246 | ||
fea50522 PM |
1247 | /* Handle special cases first */ |
1248 | switch (ri->type & ~(ARM_CP_FLAG_MASK & ~ARM_CP_SPECIAL)) { | |
1249 | case ARM_CP_NOP: | |
1250 | return; | |
b0d2b7d0 PM |
1251 | case ARM_CP_NZCV: |
1252 | tcg_rt = cpu_reg(s, rt); | |
1253 | if (isread) { | |
1254 | gen_get_nzcv(tcg_rt); | |
1255 | } else { | |
1256 | gen_set_nzcv(tcg_rt); | |
1257 | } | |
1258 | return; | |
0eef9d98 PM |
1259 | case ARM_CP_CURRENTEL: |
1260 | /* Reads as current EL value from pstate, which is | |
1261 | * guaranteed to be constant by the tb flags. | |
1262 | */ | |
1263 | tcg_rt = cpu_reg(s, rt); | |
1264 | tcg_gen_movi_i64(tcg_rt, s->current_pl << 2); | |
1265 | return; | |
fea50522 PM |
1266 | default: |
1267 | break; | |
1268 | } | |
1269 | ||
1270 | if (use_icount && (ri->type & ARM_CP_IO)) { | |
1271 | gen_io_start(); | |
1272 | } | |
1273 | ||
1274 | tcg_rt = cpu_reg(s, rt); | |
1275 | ||
1276 | if (isread) { | |
1277 | if (ri->type & ARM_CP_CONST) { | |
1278 | tcg_gen_movi_i64(tcg_rt, ri->resetvalue); | |
1279 | } else if (ri->readfn) { | |
1280 | TCGv_ptr tmpptr; | |
fea50522 PM |
1281 | tmpptr = tcg_const_ptr(ri); |
1282 | gen_helper_get_cp_reg64(tcg_rt, cpu_env, tmpptr); | |
1283 | tcg_temp_free_ptr(tmpptr); | |
1284 | } else { | |
1285 | tcg_gen_ld_i64(tcg_rt, cpu_env, ri->fieldoffset); | |
1286 | } | |
1287 | } else { | |
1288 | if (ri->type & ARM_CP_CONST) { | |
1289 | /* If not forbidden by access permissions, treat as WI */ | |
1290 | return; | |
1291 | } else if (ri->writefn) { | |
1292 | TCGv_ptr tmpptr; | |
fea50522 PM |
1293 | tmpptr = tcg_const_ptr(ri); |
1294 | gen_helper_set_cp_reg64(cpu_env, tmpptr, tcg_rt); | |
1295 | tcg_temp_free_ptr(tmpptr); | |
1296 | } else { | |
1297 | tcg_gen_st_i64(tcg_rt, cpu_env, ri->fieldoffset); | |
1298 | } | |
1299 | } | |
1300 | ||
1301 | if (use_icount && (ri->type & ARM_CP_IO)) { | |
1302 | /* I/O operations must end the TB here (whether read or write) */ | |
1303 | gen_io_end(); | |
1304 | s->is_jmp = DISAS_UPDATE; | |
1305 | } else if (!isread && !(ri->type & ARM_CP_SUPPRESS_TB_END)) { | |
1306 | /* We default to ending the TB on a coprocessor register write, | |
1307 | * but allow this to be suppressed by the register definition | |
1308 | * (usually only necessary to work around guest bugs). | |
1309 | */ | |
1310 | s->is_jmp = DISAS_UPDATE; | |
1311 | } | |
ad7ee8a2 CF |
1312 | } |
1313 | ||
87462e0f CF |
1314 | /* C3.2.4 System |
1315 | * 31 22 21 20 19 18 16 15 12 11 8 7 5 4 0 | |
1316 | * +---------------------+---+-----+-----+-------+-------+-----+------+ | |
1317 | * | 1 1 0 1 0 1 0 1 0 0 | L | op0 | op1 | CRn | CRm | op2 | Rt | | |
1318 | * +---------------------+---+-----+-----+-------+-------+-----+------+ | |
1319 | */ | |
1320 | static void disas_system(DisasContext *s, uint32_t insn) | |
1321 | { | |
1322 | unsigned int l, op0, op1, crn, crm, op2, rt; | |
1323 | l = extract32(insn, 21, 1); | |
1324 | op0 = extract32(insn, 19, 2); | |
1325 | op1 = extract32(insn, 16, 3); | |
1326 | crn = extract32(insn, 12, 4); | |
1327 | crm = extract32(insn, 8, 4); | |
1328 | op2 = extract32(insn, 5, 3); | |
1329 | rt = extract32(insn, 0, 5); | |
1330 | ||
1331 | if (op0 == 0) { | |
1332 | if (l || rt != 31) { | |
1333 | unallocated_encoding(s); | |
1334 | return; | |
1335 | } | |
1336 | switch (crn) { | |
1337 | case 2: /* C5.6.68 HINT */ | |
1338 | handle_hint(s, insn, op1, op2, crm); | |
1339 | break; | |
1340 | case 3: /* CLREX, DSB, DMB, ISB */ | |
1341 | handle_sync(s, insn, op1, op2, crm); | |
1342 | break; | |
1343 | case 4: /* C5.6.130 MSR (immediate) */ | |
1344 | handle_msr_i(s, insn, op1, op2, crm); | |
1345 | break; | |
1346 | default: | |
1347 | unallocated_encoding(s); | |
1348 | break; | |
1349 | } | |
1350 | return; | |
1351 | } | |
fea50522 | 1352 | handle_sys(s, insn, l, op0, op1, op2, crn, crm, rt); |
87462e0f CF |
1353 | } |
1354 | ||
9618e809 AG |
1355 | /* C3.2.3 Exception generation |
1356 | * | |
1357 | * 31 24 23 21 20 5 4 2 1 0 | |
1358 | * +-----------------+-----+------------------------+-----+----+ | |
1359 | * | 1 1 0 1 0 1 0 0 | opc | imm16 | op2 | LL | | |
1360 | * +-----------------------+------------------------+----------+ | |
1361 | */ | |
ad7ee8a2 CF |
1362 | static void disas_exc(DisasContext *s, uint32_t insn) |
1363 | { | |
9618e809 AG |
1364 | int opc = extract32(insn, 21, 3); |
1365 | int op2_ll = extract32(insn, 0, 5); | |
1366 | ||
1367 | switch (opc) { | |
1368 | case 0: | |
1369 | /* SVC, HVC, SMC; since we don't support the Virtualization | |
1370 | * or TrustZone extensions these all UNDEF except SVC. | |
1371 | */ | |
1372 | if (op2_ll != 1) { | |
1373 | unallocated_encoding(s); | |
1374 | break; | |
1375 | } | |
1376 | gen_exception_insn(s, 0, EXCP_SWI); | |
1377 | break; | |
1378 | case 1: | |
1379 | if (op2_ll != 0) { | |
1380 | unallocated_encoding(s); | |
1381 | break; | |
1382 | } | |
1383 | /* BRK */ | |
1384 | gen_exception_insn(s, 0, EXCP_BKPT); | |
1385 | break; | |
1386 | case 2: | |
1387 | if (op2_ll != 0) { | |
1388 | unallocated_encoding(s); | |
1389 | break; | |
1390 | } | |
1391 | /* HLT */ | |
1392 | unsupported_encoding(s, insn); | |
1393 | break; | |
1394 | case 5: | |
1395 | if (op2_ll < 1 || op2_ll > 3) { | |
1396 | unallocated_encoding(s); | |
1397 | break; | |
1398 | } | |
1399 | /* DCPS1, DCPS2, DCPS3 */ | |
1400 | unsupported_encoding(s, insn); | |
1401 | break; | |
1402 | default: | |
1403 | unallocated_encoding(s); | |
1404 | break; | |
1405 | } | |
ad7ee8a2 CF |
1406 | } |
1407 | ||
b001c8c3 AG |
1408 | /* C3.2.7 Unconditional branch (register) |
1409 | * 31 25 24 21 20 16 15 10 9 5 4 0 | |
1410 | * +---------------+-------+-------+-------+------+-------+ | |
1411 | * | 1 1 0 1 0 1 1 | opc | op2 | op3 | Rn | op4 | | |
1412 | * +---------------+-------+-------+-------+------+-------+ | |
1413 | */ | |
ad7ee8a2 CF |
1414 | static void disas_uncond_b_reg(DisasContext *s, uint32_t insn) |
1415 | { | |
b001c8c3 AG |
1416 | unsigned int opc, op2, op3, rn, op4; |
1417 | ||
1418 | opc = extract32(insn, 21, 4); | |
1419 | op2 = extract32(insn, 16, 5); | |
1420 | op3 = extract32(insn, 10, 6); | |
1421 | rn = extract32(insn, 5, 5); | |
1422 | op4 = extract32(insn, 0, 5); | |
1423 | ||
1424 | if (op4 != 0x0 || op3 != 0x0 || op2 != 0x1f) { | |
1425 | unallocated_encoding(s); | |
1426 | return; | |
1427 | } | |
1428 | ||
1429 | switch (opc) { | |
1430 | case 0: /* BR */ | |
1431 | case 2: /* RET */ | |
1432 | break; | |
1433 | case 1: /* BLR */ | |
1434 | tcg_gen_movi_i64(cpu_reg(s, 30), s->pc); | |
1435 | break; | |
1436 | case 4: /* ERET */ | |
1437 | case 5: /* DRPS */ | |
1438 | if (rn != 0x1f) { | |
1439 | unallocated_encoding(s); | |
1440 | } else { | |
1441 | unsupported_encoding(s, insn); | |
1442 | } | |
1443 | return; | |
1444 | default: | |
1445 | unallocated_encoding(s); | |
1446 | return; | |
1447 | } | |
1448 | ||
1449 | tcg_gen_mov_i64(cpu_pc, cpu_reg(s, rn)); | |
1450 | s->is_jmp = DISAS_JUMP; | |
ad7ee8a2 CF |
1451 | } |
1452 | ||
1453 | /* C3.2 Branches, exception generating and system instructions */ | |
1454 | static void disas_b_exc_sys(DisasContext *s, uint32_t insn) | |
1455 | { | |
1456 | switch (extract32(insn, 25, 7)) { | |
1457 | case 0x0a: case 0x0b: | |
1458 | case 0x4a: case 0x4b: /* Unconditional branch (immediate) */ | |
1459 | disas_uncond_b_imm(s, insn); | |
1460 | break; | |
1461 | case 0x1a: case 0x5a: /* Compare & branch (immediate) */ | |
1462 | disas_comp_b_imm(s, insn); | |
1463 | break; | |
1464 | case 0x1b: case 0x5b: /* Test & branch (immediate) */ | |
1465 | disas_test_b_imm(s, insn); | |
1466 | break; | |
1467 | case 0x2a: /* Conditional branch (immediate) */ | |
1468 | disas_cond_b_imm(s, insn); | |
1469 | break; | |
1470 | case 0x6a: /* Exception generation / System */ | |
1471 | if (insn & (1 << 24)) { | |
1472 | disas_system(s, insn); | |
1473 | } else { | |
1474 | disas_exc(s, insn); | |
1475 | } | |
1476 | break; | |
1477 | case 0x6b: /* Unconditional branch (register) */ | |
1478 | disas_uncond_b_reg(s, insn); | |
1479 | break; | |
1480 | default: | |
1481 | unallocated_encoding(s); | |
1482 | break; | |
1483 | } | |
1484 | } | |
1485 | ||
fa2ef212 MM |
1486 | /* |
1487 | * Load/Store exclusive instructions are implemented by remembering | |
1488 | * the value/address loaded, and seeing if these are the same | |
1489 | * when the store is performed. This is not actually the architecturally | |
1490 | * mandated semantics, but it works for typical guest code sequences | |
1491 | * and avoids having to monitor regular stores. | |
1492 | * | |
1493 | * In system emulation mode only one CPU will be running at once, so | |
1494 | * this sequence is effectively atomic. In user emulation mode we | |
1495 | * throw an exception and handle the atomic operation elsewhere. | |
1496 | */ | |
1497 | static void gen_load_exclusive(DisasContext *s, int rt, int rt2, | |
1498 | TCGv_i64 addr, int size, bool is_pair) | |
1499 | { | |
1500 | TCGv_i64 tmp = tcg_temp_new_i64(); | |
1501 | TCGMemOp memop = MO_TE + size; | |
1502 | ||
1503 | g_assert(size <= 3); | |
1504 | tcg_gen_qemu_ld_i64(tmp, addr, get_mem_index(s), memop); | |
1505 | ||
1506 | if (is_pair) { | |
1507 | TCGv_i64 addr2 = tcg_temp_new_i64(); | |
1508 | TCGv_i64 hitmp = tcg_temp_new_i64(); | |
1509 | ||
1510 | g_assert(size >= 2); | |
1511 | tcg_gen_addi_i64(addr2, addr, 1 << size); | |
1512 | tcg_gen_qemu_ld_i64(hitmp, addr2, get_mem_index(s), memop); | |
1513 | tcg_temp_free_i64(addr2); | |
1514 | tcg_gen_mov_i64(cpu_exclusive_high, hitmp); | |
1515 | tcg_gen_mov_i64(cpu_reg(s, rt2), hitmp); | |
1516 | tcg_temp_free_i64(hitmp); | |
1517 | } | |
1518 | ||
1519 | tcg_gen_mov_i64(cpu_exclusive_val, tmp); | |
1520 | tcg_gen_mov_i64(cpu_reg(s, rt), tmp); | |
1521 | ||
1522 | tcg_temp_free_i64(tmp); | |
1523 | tcg_gen_mov_i64(cpu_exclusive_addr, addr); | |
1524 | } | |
1525 | ||
1526 | #ifdef CONFIG_USER_ONLY | |
1527 | static void gen_store_exclusive(DisasContext *s, int rd, int rt, int rt2, | |
1528 | TCGv_i64 addr, int size, int is_pair) | |
1529 | { | |
1530 | tcg_gen_mov_i64(cpu_exclusive_test, addr); | |
1531 | tcg_gen_movi_i32(cpu_exclusive_info, | |
1532 | size | is_pair << 2 | (rd << 4) | (rt << 9) | (rt2 << 14)); | |
1533 | gen_exception_insn(s, 4, EXCP_STREX); | |
1534 | } | |
1535 | #else | |
1536 | static void gen_store_exclusive(DisasContext *s, int rd, int rt, int rt2, | |
d324b36a | 1537 | TCGv_i64 inaddr, int size, int is_pair) |
fa2ef212 | 1538 | { |
d324b36a PM |
1539 | /* if (env->exclusive_addr == addr && env->exclusive_val == [addr] |
1540 | * && (!is_pair || env->exclusive_high == [addr + datasize])) { | |
1541 | * [addr] = {Rt}; | |
1542 | * if (is_pair) { | |
1543 | * [addr + datasize] = {Rt2}; | |
1544 | * } | |
1545 | * {Rd} = 0; | |
1546 | * } else { | |
1547 | * {Rd} = 1; | |
1548 | * } | |
1549 | * env->exclusive_addr = -1; | |
1550 | */ | |
1551 | int fail_label = gen_new_label(); | |
1552 | int done_label = gen_new_label(); | |
1553 | TCGv_i64 addr = tcg_temp_local_new_i64(); | |
1554 | TCGv_i64 tmp; | |
1555 | ||
1556 | /* Copy input into a local temp so it is not trashed when the | |
1557 | * basic block ends at the branch insn. | |
1558 | */ | |
1559 | tcg_gen_mov_i64(addr, inaddr); | |
1560 | tcg_gen_brcond_i64(TCG_COND_NE, addr, cpu_exclusive_addr, fail_label); | |
1561 | ||
1562 | tmp = tcg_temp_new_i64(); | |
1563 | tcg_gen_qemu_ld_i64(tmp, addr, get_mem_index(s), MO_TE + size); | |
1564 | tcg_gen_brcond_i64(TCG_COND_NE, tmp, cpu_exclusive_val, fail_label); | |
1565 | tcg_temp_free_i64(tmp); | |
1566 | ||
1567 | if (is_pair) { | |
1568 | TCGv_i64 addrhi = tcg_temp_new_i64(); | |
1569 | TCGv_i64 tmphi = tcg_temp_new_i64(); | |
1570 | ||
1571 | tcg_gen_addi_i64(addrhi, addr, 1 << size); | |
1572 | tcg_gen_qemu_ld_i64(tmphi, addrhi, get_mem_index(s), MO_TE + size); | |
1573 | tcg_gen_brcond_i64(TCG_COND_NE, tmphi, cpu_exclusive_high, fail_label); | |
1574 | ||
1575 | tcg_temp_free_i64(tmphi); | |
1576 | tcg_temp_free_i64(addrhi); | |
1577 | } | |
1578 | ||
1579 | /* We seem to still have the exclusive monitor, so do the store */ | |
1580 | tcg_gen_qemu_st_i64(cpu_reg(s, rt), addr, get_mem_index(s), MO_TE + size); | |
1581 | if (is_pair) { | |
1582 | TCGv_i64 addrhi = tcg_temp_new_i64(); | |
1583 | ||
1584 | tcg_gen_addi_i64(addrhi, addr, 1 << size); | |
1585 | tcg_gen_qemu_st_i64(cpu_reg(s, rt2), addrhi, | |
1586 | get_mem_index(s), MO_TE + size); | |
1587 | tcg_temp_free_i64(addrhi); | |
1588 | } | |
1589 | ||
1590 | tcg_temp_free_i64(addr); | |
1591 | ||
1592 | tcg_gen_movi_i64(cpu_reg(s, rd), 0); | |
1593 | tcg_gen_br(done_label); | |
1594 | gen_set_label(fail_label); | |
1595 | tcg_gen_movi_i64(cpu_reg(s, rd), 1); | |
1596 | gen_set_label(done_label); | |
1597 | tcg_gen_movi_i64(cpu_exclusive_addr, -1); | |
1598 | ||
fa2ef212 MM |
1599 | } |
1600 | #endif | |
1601 | ||
1602 | /* C3.3.6 Load/store exclusive | |
1603 | * | |
1604 | * 31 30 29 24 23 22 21 20 16 15 14 10 9 5 4 0 | |
1605 | * +-----+-------------+----+---+----+------+----+-------+------+------+ | |
1606 | * | sz | 0 0 1 0 0 0 | o2 | L | o1 | Rs | o0 | Rt2 | Rn | Rt | | |
1607 | * +-----+-------------+----+---+----+------+----+-------+------+------+ | |
1608 | * | |
1609 | * sz: 00 -> 8 bit, 01 -> 16 bit, 10 -> 32 bit, 11 -> 64 bit | |
1610 | * L: 0 -> store, 1 -> load | |
1611 | * o2: 0 -> exclusive, 1 -> not | |
1612 | * o1: 0 -> single register, 1 -> register pair | |
1613 | * o0: 1 -> load-acquire/store-release, 0 -> not | |
1614 | * | |
1615 | * o0 == 0 AND o2 == 1 is un-allocated | |
1616 | * o1 == 1 is un-allocated except for 32 and 64 bit sizes | |
1617 | */ | |
ad7ee8a2 CF |
1618 | static void disas_ldst_excl(DisasContext *s, uint32_t insn) |
1619 | { | |
fa2ef212 MM |
1620 | int rt = extract32(insn, 0, 5); |
1621 | int rn = extract32(insn, 5, 5); | |
1622 | int rt2 = extract32(insn, 10, 5); | |
1623 | int is_lasr = extract32(insn, 15, 1); | |
1624 | int rs = extract32(insn, 16, 5); | |
1625 | int is_pair = extract32(insn, 21, 1); | |
1626 | int is_store = !extract32(insn, 22, 1); | |
1627 | int is_excl = !extract32(insn, 23, 1); | |
1628 | int size = extract32(insn, 30, 2); | |
1629 | TCGv_i64 tcg_addr; | |
1630 | ||
1631 | if ((!is_excl && !is_lasr) || | |
1632 | (is_pair && size < 2)) { | |
1633 | unallocated_encoding(s); | |
1634 | return; | |
1635 | } | |
1636 | ||
1637 | if (rn == 31) { | |
1638 | gen_check_sp_alignment(s); | |
1639 | } | |
1640 | tcg_addr = read_cpu_reg_sp(s, rn, 1); | |
1641 | ||
1642 | /* Note that since TCG is single threaded load-acquire/store-release | |
1643 | * semantics require no extra if (is_lasr) { ... } handling. | |
1644 | */ | |
1645 | ||
1646 | if (is_excl) { | |
1647 | if (!is_store) { | |
1648 | gen_load_exclusive(s, rt, rt2, tcg_addr, size, is_pair); | |
1649 | } else { | |
1650 | gen_store_exclusive(s, rs, rt, rt2, tcg_addr, size, is_pair); | |
1651 | } | |
1652 | } else { | |
1653 | TCGv_i64 tcg_rt = cpu_reg(s, rt); | |
1654 | if (is_store) { | |
1655 | do_gpr_st(s, tcg_rt, tcg_addr, size); | |
1656 | } else { | |
1657 | do_gpr_ld(s, tcg_rt, tcg_addr, size, false, false); | |
1658 | } | |
1659 | if (is_pair) { | |
1660 | TCGv_i64 tcg_rt2 = cpu_reg(s, rt); | |
1661 | tcg_gen_addi_i64(tcg_addr, tcg_addr, 1 << size); | |
1662 | if (is_store) { | |
1663 | do_gpr_st(s, tcg_rt2, tcg_addr, size); | |
1664 | } else { | |
1665 | do_gpr_ld(s, tcg_rt2, tcg_addr, size, false, false); | |
1666 | } | |
1667 | } | |
1668 | } | |
ad7ee8a2 CF |
1669 | } |
1670 | ||
32b64e86 AG |
1671 | /* |
1672 | * C3.3.5 Load register (literal) | |
1673 | * | |
1674 | * 31 30 29 27 26 25 24 23 5 4 0 | |
1675 | * +-----+-------+---+-----+-------------------+-------+ | |
1676 | * | opc | 0 1 1 | V | 0 0 | imm19 | Rt | | |
1677 | * +-----+-------+---+-----+-------------------+-------+ | |
1678 | * | |
1679 | * V: 1 -> vector (simd/fp) | |
1680 | * opc (non-vector): 00 -> 32 bit, 01 -> 64 bit, | |
1681 | * 10-> 32 bit signed, 11 -> prefetch | |
1682 | * opc (vector): 00 -> 32 bit, 01 -> 64 bit, 10 -> 128 bit (11 unallocated) | |
1683 | */ | |
ad7ee8a2 CF |
1684 | static void disas_ld_lit(DisasContext *s, uint32_t insn) |
1685 | { | |
32b64e86 AG |
1686 | int rt = extract32(insn, 0, 5); |
1687 | int64_t imm = sextract32(insn, 5, 19) << 2; | |
1688 | bool is_vector = extract32(insn, 26, 1); | |
1689 | int opc = extract32(insn, 30, 2); | |
1690 | bool is_signed = false; | |
1691 | int size = 2; | |
1692 | TCGv_i64 tcg_rt, tcg_addr; | |
1693 | ||
1694 | if (is_vector) { | |
1695 | if (opc == 3) { | |
1696 | unallocated_encoding(s); | |
1697 | return; | |
1698 | } | |
1699 | size = 2 + opc; | |
1700 | } else { | |
1701 | if (opc == 3) { | |
1702 | /* PRFM (literal) : prefetch */ | |
1703 | return; | |
1704 | } | |
1705 | size = 2 + extract32(opc, 0, 1); | |
1706 | is_signed = extract32(opc, 1, 1); | |
1707 | } | |
1708 | ||
1709 | tcg_rt = cpu_reg(s, rt); | |
1710 | ||
1711 | tcg_addr = tcg_const_i64((s->pc - 4) + imm); | |
1712 | if (is_vector) { | |
1713 | do_fp_ld(s, rt, tcg_addr, size); | |
1714 | } else { | |
1715 | do_gpr_ld(s, tcg_rt, tcg_addr, size, is_signed, false); | |
1716 | } | |
1717 | tcg_temp_free_i64(tcg_addr); | |
ad7ee8a2 CF |
1718 | } |
1719 | ||
4a08d475 PM |
1720 | /* |
1721 | * C5.6.80 LDNP (Load Pair - non-temporal hint) | |
1722 | * C5.6.81 LDP (Load Pair - non vector) | |
1723 | * C5.6.82 LDPSW (Load Pair Signed Word - non vector) | |
1724 | * C5.6.176 STNP (Store Pair - non-temporal hint) | |
1725 | * C5.6.177 STP (Store Pair - non vector) | |
1726 | * C6.3.165 LDNP (Load Pair of SIMD&FP - non-temporal hint) | |
1727 | * C6.3.165 LDP (Load Pair of SIMD&FP) | |
1728 | * C6.3.284 STNP (Store Pair of SIMD&FP - non-temporal hint) | |
1729 | * C6.3.284 STP (Store Pair of SIMD&FP) | |
1730 | * | |
1731 | * 31 30 29 27 26 25 24 23 22 21 15 14 10 9 5 4 0 | |
1732 | * +-----+-------+---+---+-------+---+-----------------------------+ | |
1733 | * | opc | 1 0 1 | V | 0 | index | L | imm7 | Rt2 | Rn | Rt | | |
1734 | * +-----+-------+---+---+-------+---+-------+-------+------+------+ | |
1735 | * | |
1736 | * opc: LDP/STP/LDNP/STNP 00 -> 32 bit, 10 -> 64 bit | |
1737 | * LDPSW 01 | |
1738 | * LDP/STP/LDNP/STNP (SIMD) 00 -> 32 bit, 01 -> 64 bit, 10 -> 128 bit | |
1739 | * V: 0 -> GPR, 1 -> Vector | |
1740 | * idx: 00 -> signed offset with non-temporal hint, 01 -> post-index, | |
1741 | * 10 -> signed offset, 11 -> pre-index | |
1742 | * L: 0 -> Store 1 -> Load | |
1743 | * | |
1744 | * Rt, Rt2 = GPR or SIMD registers to be stored | |
1745 | * Rn = general purpose register containing address | |
1746 | * imm7 = signed offset (multiple of 4 or 8 depending on size) | |
1747 | */ | |
ad7ee8a2 CF |
1748 | static void disas_ldst_pair(DisasContext *s, uint32_t insn) |
1749 | { | |
4a08d475 PM |
1750 | int rt = extract32(insn, 0, 5); |
1751 | int rn = extract32(insn, 5, 5); | |
1752 | int rt2 = extract32(insn, 10, 5); | |
1753 | int64_t offset = sextract32(insn, 15, 7); | |
1754 | int index = extract32(insn, 23, 2); | |
1755 | bool is_vector = extract32(insn, 26, 1); | |
1756 | bool is_load = extract32(insn, 22, 1); | |
1757 | int opc = extract32(insn, 30, 2); | |
1758 | ||
1759 | bool is_signed = false; | |
1760 | bool postindex = false; | |
1761 | bool wback = false; | |
1762 | ||
1763 | TCGv_i64 tcg_addr; /* calculated address */ | |
1764 | int size; | |
1765 | ||
1766 | if (opc == 3) { | |
1767 | unallocated_encoding(s); | |
1768 | return; | |
1769 | } | |
1770 | ||
1771 | if (is_vector) { | |
1772 | size = 2 + opc; | |
1773 | } else { | |
1774 | size = 2 + extract32(opc, 1, 1); | |
1775 | is_signed = extract32(opc, 0, 1); | |
1776 | if (!is_load && is_signed) { | |
1777 | unallocated_encoding(s); | |
1778 | return; | |
1779 | } | |
1780 | } | |
1781 | ||
1782 | switch (index) { | |
1783 | case 1: /* post-index */ | |
1784 | postindex = true; | |
1785 | wback = true; | |
1786 | break; | |
1787 | case 0: | |
1788 | /* signed offset with "non-temporal" hint. Since we don't emulate | |
1789 | * caches we don't care about hints to the cache system about | |
1790 | * data access patterns, and handle this identically to plain | |
1791 | * signed offset. | |
1792 | */ | |
1793 | if (is_signed) { | |
1794 | /* There is no non-temporal-hint version of LDPSW */ | |
1795 | unallocated_encoding(s); | |
1796 | return; | |
1797 | } | |
1798 | postindex = false; | |
1799 | break; | |
1800 | case 2: /* signed offset, rn not updated */ | |
1801 | postindex = false; | |
1802 | break; | |
1803 | case 3: /* pre-index */ | |
1804 | postindex = false; | |
1805 | wback = true; | |
1806 | break; | |
1807 | } | |
1808 | ||
1809 | offset <<= size; | |
1810 | ||
1811 | if (rn == 31) { | |
1812 | gen_check_sp_alignment(s); | |
1813 | } | |
1814 | ||
1815 | tcg_addr = read_cpu_reg_sp(s, rn, 1); | |
1816 | ||
1817 | if (!postindex) { | |
1818 | tcg_gen_addi_i64(tcg_addr, tcg_addr, offset); | |
1819 | } | |
1820 | ||
1821 | if (is_vector) { | |
1822 | if (is_load) { | |
1823 | do_fp_ld(s, rt, tcg_addr, size); | |
1824 | } else { | |
1825 | do_fp_st(s, rt, tcg_addr, size); | |
1826 | } | |
1827 | } else { | |
1828 | TCGv_i64 tcg_rt = cpu_reg(s, rt); | |
1829 | if (is_load) { | |
1830 | do_gpr_ld(s, tcg_rt, tcg_addr, size, is_signed, false); | |
1831 | } else { | |
1832 | do_gpr_st(s, tcg_rt, tcg_addr, size); | |
1833 | } | |
1834 | } | |
1835 | tcg_gen_addi_i64(tcg_addr, tcg_addr, 1 << size); | |
1836 | if (is_vector) { | |
1837 | if (is_load) { | |
1838 | do_fp_ld(s, rt2, tcg_addr, size); | |
1839 | } else { | |
1840 | do_fp_st(s, rt2, tcg_addr, size); | |
1841 | } | |
1842 | } else { | |
1843 | TCGv_i64 tcg_rt2 = cpu_reg(s, rt2); | |
1844 | if (is_load) { | |
1845 | do_gpr_ld(s, tcg_rt2, tcg_addr, size, is_signed, false); | |
1846 | } else { | |
1847 | do_gpr_st(s, tcg_rt2, tcg_addr, size); | |
1848 | } | |
1849 | } | |
1850 | ||
1851 | if (wback) { | |
1852 | if (postindex) { | |
1853 | tcg_gen_addi_i64(tcg_addr, tcg_addr, offset - (1 << size)); | |
1854 | } else { | |
1855 | tcg_gen_subi_i64(tcg_addr, tcg_addr, 1 << size); | |
1856 | } | |
1857 | tcg_gen_mov_i64(cpu_reg_sp(s, rn), tcg_addr); | |
1858 | } | |
ad7ee8a2 CF |
1859 | } |
1860 | ||
a5e94a9d AB |
1861 | /* |
1862 | * C3.3.8 Load/store (immediate post-indexed) | |
1863 | * C3.3.9 Load/store (immediate pre-indexed) | |
1864 | * C3.3.12 Load/store (unscaled immediate) | |
1865 | * | |
1866 | * 31 30 29 27 26 25 24 23 22 21 20 12 11 10 9 5 4 0 | |
1867 | * +----+-------+---+-----+-----+---+--------+-----+------+------+ | |
1868 | * |size| 1 1 1 | V | 0 0 | opc | 0 | imm9 | idx | Rn | Rt | | |
1869 | * +----+-------+---+-----+-----+---+--------+-----+------+------+ | |
1870 | * | |
1871 | * idx = 01 -> post-indexed, 11 pre-indexed, 00 unscaled imm. (no writeback) | |
60510aed | 1872 | 10 -> unprivileged |
a5e94a9d AB |
1873 | * V = 0 -> non-vector |
1874 | * size: 00 -> 8 bit, 01 -> 16 bit, 10 -> 32 bit, 11 -> 64bit | |
1875 | * opc: 00 -> store, 01 -> loadu, 10 -> loads 64, 11 -> loads 32 | |
1876 | */ | |
1877 | static void disas_ldst_reg_imm9(DisasContext *s, uint32_t insn) | |
1878 | { | |
1879 | int rt = extract32(insn, 0, 5); | |
1880 | int rn = extract32(insn, 5, 5); | |
1881 | int imm9 = sextract32(insn, 12, 9); | |
1882 | int opc = extract32(insn, 22, 2); | |
1883 | int size = extract32(insn, 30, 2); | |
1884 | int idx = extract32(insn, 10, 2); | |
1885 | bool is_signed = false; | |
1886 | bool is_store = false; | |
1887 | bool is_extended = false; | |
60510aed | 1888 | bool is_unpriv = (idx == 2); |
a5e94a9d AB |
1889 | bool is_vector = extract32(insn, 26, 1); |
1890 | bool post_index; | |
1891 | bool writeback; | |
1892 | ||
1893 | TCGv_i64 tcg_addr; | |
1894 | ||
1895 | if (is_vector) { | |
1896 | size |= (opc & 2) << 1; | |
60510aed | 1897 | if (size > 4 || is_unpriv) { |
a5e94a9d AB |
1898 | unallocated_encoding(s); |
1899 | return; | |
1900 | } | |
1901 | is_store = ((opc & 1) == 0); | |
1902 | } else { | |
1903 | if (size == 3 && opc == 2) { | |
1904 | /* PRFM - prefetch */ | |
60510aed PM |
1905 | if (is_unpriv) { |
1906 | unallocated_encoding(s); | |
1907 | return; | |
1908 | } | |
a5e94a9d AB |
1909 | return; |
1910 | } | |
1911 | if (opc == 3 && size > 1) { | |
1912 | unallocated_encoding(s); | |
1913 | return; | |
1914 | } | |
1915 | is_store = (opc == 0); | |
1916 | is_signed = opc & (1<<1); | |
1917 | is_extended = (size < 3) && (opc & 1); | |
1918 | } | |
1919 | ||
1920 | switch (idx) { | |
1921 | case 0: | |
60510aed | 1922 | case 2: |
a5e94a9d AB |
1923 | post_index = false; |
1924 | writeback = false; | |
1925 | break; | |
1926 | case 1: | |
1927 | post_index = true; | |
1928 | writeback = true; | |
1929 | break; | |
1930 | case 3: | |
1931 | post_index = false; | |
1932 | writeback = true; | |
1933 | break; | |
a5e94a9d AB |
1934 | } |
1935 | ||
1936 | if (rn == 31) { | |
1937 | gen_check_sp_alignment(s); | |
1938 | } | |
1939 | tcg_addr = read_cpu_reg_sp(s, rn, 1); | |
1940 | ||
1941 | if (!post_index) { | |
1942 | tcg_gen_addi_i64(tcg_addr, tcg_addr, imm9); | |
1943 | } | |
1944 | ||
1945 | if (is_vector) { | |
1946 | if (is_store) { | |
1947 | do_fp_st(s, rt, tcg_addr, size); | |
1948 | } else { | |
1949 | do_fp_ld(s, rt, tcg_addr, size); | |
1950 | } | |
1951 | } else { | |
1952 | TCGv_i64 tcg_rt = cpu_reg(s, rt); | |
60510aed PM |
1953 | int memidx = is_unpriv ? 1 : get_mem_index(s); |
1954 | ||
a5e94a9d | 1955 | if (is_store) { |
60510aed | 1956 | do_gpr_st_memidx(s, tcg_rt, tcg_addr, size, memidx); |
a5e94a9d | 1957 | } else { |
60510aed PM |
1958 | do_gpr_ld_memidx(s, tcg_rt, tcg_addr, size, |
1959 | is_signed, is_extended, memidx); | |
a5e94a9d AB |
1960 | } |
1961 | } | |
1962 | ||
1963 | if (writeback) { | |
1964 | TCGv_i64 tcg_rn = cpu_reg_sp(s, rn); | |
1965 | if (post_index) { | |
1966 | tcg_gen_addi_i64(tcg_addr, tcg_addr, imm9); | |
1967 | } | |
1968 | tcg_gen_mov_i64(tcg_rn, tcg_addr); | |
1969 | } | |
1970 | } | |
1971 | ||
229b7a05 AB |
1972 | /* |
1973 | * C3.3.10 Load/store (register offset) | |
1974 | * | |
1975 | * 31 30 29 27 26 25 24 23 22 21 20 16 15 13 12 11 10 9 5 4 0 | |
1976 | * +----+-------+---+-----+-----+---+------+-----+--+-----+----+----+ | |
1977 | * |size| 1 1 1 | V | 0 0 | opc | 1 | Rm | opt | S| 1 0 | Rn | Rt | | |
1978 | * +----+-------+---+-----+-----+---+------+-----+--+-----+----+----+ | |
1979 | * | |
1980 | * For non-vector: | |
1981 | * size: 00-> byte, 01 -> 16 bit, 10 -> 32bit, 11 -> 64bit | |
1982 | * opc: 00 -> store, 01 -> loadu, 10 -> loads 64, 11 -> loads 32 | |
1983 | * For vector: | |
1984 | * size is opc<1>:size<1:0> so 100 -> 128 bit; 110 and 111 unallocated | |
1985 | * opc<0>: 0 -> store, 1 -> load | |
1986 | * V: 1 -> vector/simd | |
1987 | * opt: extend encoding (see DecodeRegExtend) | |
1988 | * S: if S=1 then scale (essentially index by sizeof(size)) | |
1989 | * Rt: register to transfer into/out of | |
1990 | * Rn: address register or SP for base | |
1991 | * Rm: offset register or ZR for offset | |
1992 | */ | |
1993 | static void disas_ldst_reg_roffset(DisasContext *s, uint32_t insn) | |
1994 | { | |
1995 | int rt = extract32(insn, 0, 5); | |
1996 | int rn = extract32(insn, 5, 5); | |
1997 | int shift = extract32(insn, 12, 1); | |
1998 | int rm = extract32(insn, 16, 5); | |
1999 | int opc = extract32(insn, 22, 2); | |
2000 | int opt = extract32(insn, 13, 3); | |
2001 | int size = extract32(insn, 30, 2); | |
2002 | bool is_signed = false; | |
2003 | bool is_store = false; | |
2004 | bool is_extended = false; | |
2005 | bool is_vector = extract32(insn, 26, 1); | |
2006 | ||
2007 | TCGv_i64 tcg_rm; | |
2008 | TCGv_i64 tcg_addr; | |
2009 | ||
2010 | if (extract32(opt, 1, 1) == 0) { | |
2011 | unallocated_encoding(s); | |
2012 | return; | |
2013 | } | |
2014 | ||
2015 | if (is_vector) { | |
2016 | size |= (opc & 2) << 1; | |
2017 | if (size > 4) { | |
2018 | unallocated_encoding(s); | |
2019 | return; | |
2020 | } | |
2021 | is_store = !extract32(opc, 0, 1); | |
2022 | } else { | |
2023 | if (size == 3 && opc == 2) { | |
2024 | /* PRFM - prefetch */ | |
2025 | return; | |
2026 | } | |
2027 | if (opc == 3 && size > 1) { | |
2028 | unallocated_encoding(s); | |
2029 | return; | |
2030 | } | |
2031 | is_store = (opc == 0); | |
2032 | is_signed = extract32(opc, 1, 1); | |
2033 | is_extended = (size < 3) && extract32(opc, 0, 1); | |
2034 | } | |
2035 | ||
2036 | if (rn == 31) { | |
2037 | gen_check_sp_alignment(s); | |
2038 | } | |
2039 | tcg_addr = read_cpu_reg_sp(s, rn, 1); | |
2040 | ||
2041 | tcg_rm = read_cpu_reg(s, rm, 1); | |
2042 | ext_and_shift_reg(tcg_rm, tcg_rm, opt, shift ? size : 0); | |
2043 | ||
2044 | tcg_gen_add_i64(tcg_addr, tcg_addr, tcg_rm); | |
2045 | ||
2046 | if (is_vector) { | |
2047 | if (is_store) { | |
2048 | do_fp_st(s, rt, tcg_addr, size); | |
2049 | } else { | |
2050 | do_fp_ld(s, rt, tcg_addr, size); | |
2051 | } | |
2052 | } else { | |
2053 | TCGv_i64 tcg_rt = cpu_reg(s, rt); | |
2054 | if (is_store) { | |
2055 | do_gpr_st(s, tcg_rt, tcg_addr, size); | |
2056 | } else { | |
2057 | do_gpr_ld(s, tcg_rt, tcg_addr, size, is_signed, is_extended); | |
2058 | } | |
2059 | } | |
2060 | } | |
2061 | ||
d5612f10 AB |
2062 | /* |
2063 | * C3.3.13 Load/store (unsigned immediate) | |
2064 | * | |
2065 | * 31 30 29 27 26 25 24 23 22 21 10 9 5 | |
2066 | * +----+-------+---+-----+-----+------------+-------+------+ | |
2067 | * |size| 1 1 1 | V | 0 1 | opc | imm12 | Rn | Rt | | |
2068 | * +----+-------+---+-----+-----+------------+-------+------+ | |
2069 | * | |
2070 | * For non-vector: | |
2071 | * size: 00-> byte, 01 -> 16 bit, 10 -> 32bit, 11 -> 64bit | |
2072 | * opc: 00 -> store, 01 -> loadu, 10 -> loads 64, 11 -> loads 32 | |
2073 | * For vector: | |
2074 | * size is opc<1>:size<1:0> so 100 -> 128 bit; 110 and 111 unallocated | |
2075 | * opc<0>: 0 -> store, 1 -> load | |
2076 | * Rn: base address register (inc SP) | |
2077 | * Rt: target register | |
2078 | */ | |
2079 | static void disas_ldst_reg_unsigned_imm(DisasContext *s, uint32_t insn) | |
2080 | { | |
2081 | int rt = extract32(insn, 0, 5); | |
2082 | int rn = extract32(insn, 5, 5); | |
2083 | unsigned int imm12 = extract32(insn, 10, 12); | |
2084 | bool is_vector = extract32(insn, 26, 1); | |
2085 | int size = extract32(insn, 30, 2); | |
2086 | int opc = extract32(insn, 22, 2); | |
2087 | unsigned int offset; | |
2088 | ||
2089 | TCGv_i64 tcg_addr; | |
2090 | ||
2091 | bool is_store; | |
2092 | bool is_signed = false; | |
2093 | bool is_extended = false; | |
2094 | ||
2095 | if (is_vector) { | |
2096 | size |= (opc & 2) << 1; | |
2097 | if (size > 4) { | |
2098 | unallocated_encoding(s); | |
2099 | return; | |
2100 | } | |
2101 | is_store = !extract32(opc, 0, 1); | |
2102 | } else { | |
2103 | if (size == 3 && opc == 2) { | |
2104 | /* PRFM - prefetch */ | |
2105 | return; | |
2106 | } | |
2107 | if (opc == 3 && size > 1) { | |
2108 | unallocated_encoding(s); | |
2109 | return; | |
2110 | } | |
2111 | is_store = (opc == 0); | |
2112 | is_signed = extract32(opc, 1, 1); | |
2113 | is_extended = (size < 3) && extract32(opc, 0, 1); | |
2114 | } | |
2115 | ||
2116 | if (rn == 31) { | |
2117 | gen_check_sp_alignment(s); | |
2118 | } | |
2119 | tcg_addr = read_cpu_reg_sp(s, rn, 1); | |
2120 | offset = imm12 << size; | |
2121 | tcg_gen_addi_i64(tcg_addr, tcg_addr, offset); | |
2122 | ||
2123 | if (is_vector) { | |
2124 | if (is_store) { | |
2125 | do_fp_st(s, rt, tcg_addr, size); | |
2126 | } else { | |
2127 | do_fp_ld(s, rt, tcg_addr, size); | |
2128 | } | |
2129 | } else { | |
2130 | TCGv_i64 tcg_rt = cpu_reg(s, rt); | |
2131 | if (is_store) { | |
2132 | do_gpr_st(s, tcg_rt, tcg_addr, size); | |
2133 | } else { | |
2134 | do_gpr_ld(s, tcg_rt, tcg_addr, size, is_signed, is_extended); | |
2135 | } | |
2136 | } | |
2137 | } | |
2138 | ||
ad7ee8a2 CF |
2139 | /* Load/store register (all forms) */ |
2140 | static void disas_ldst_reg(DisasContext *s, uint32_t insn) | |
2141 | { | |
d5612f10 AB |
2142 | switch (extract32(insn, 24, 2)) { |
2143 | case 0: | |
229b7a05 AB |
2144 | if (extract32(insn, 21, 1) == 1 && extract32(insn, 10, 2) == 2) { |
2145 | disas_ldst_reg_roffset(s, insn); | |
2146 | } else { | |
60510aed PM |
2147 | /* Load/store register (unscaled immediate) |
2148 | * Load/store immediate pre/post-indexed | |
2149 | * Load/store register unprivileged | |
2150 | */ | |
2151 | disas_ldst_reg_imm9(s, insn); | |
229b7a05 | 2152 | } |
d5612f10 AB |
2153 | break; |
2154 | case 1: | |
2155 | disas_ldst_reg_unsigned_imm(s, insn); | |
2156 | break; | |
2157 | default: | |
2158 | unallocated_encoding(s); | |
2159 | break; | |
2160 | } | |
ad7ee8a2 CF |
2161 | } |
2162 | ||
72430bf5 AB |
2163 | /* C3.3.1 AdvSIMD load/store multiple structures |
2164 | * | |
2165 | * 31 30 29 23 22 21 16 15 12 11 10 9 5 4 0 | |
2166 | * +---+---+---------------+---+-------------+--------+------+------+------+ | |
2167 | * | 0 | Q | 0 0 1 1 0 0 0 | L | 0 0 0 0 0 0 | opcode | size | Rn | Rt | | |
2168 | * +---+---+---------------+---+-------------+--------+------+------+------+ | |
2169 | * | |
2170 | * C3.3.2 AdvSIMD load/store multiple structures (post-indexed) | |
2171 | * | |
2172 | * 31 30 29 23 22 21 20 16 15 12 11 10 9 5 4 0 | |
2173 | * +---+---+---------------+---+---+---------+--------+------+------+------+ | |
2174 | * | 0 | Q | 0 0 1 1 0 0 1 | L | 0 | Rm | opcode | size | Rn | Rt | | |
2175 | * +---+---+---------------+---+---+---------+--------+------+------+------+ | |
2176 | * | |
2177 | * Rt: first (or only) SIMD&FP register to be transferred | |
2178 | * Rn: base address or SP | |
2179 | * Rm (post-index only): post-index register (when !31) or size dependent #imm | |
2180 | */ | |
ad7ee8a2 CF |
2181 | static void disas_ldst_multiple_struct(DisasContext *s, uint32_t insn) |
2182 | { | |
72430bf5 AB |
2183 | int rt = extract32(insn, 0, 5); |
2184 | int rn = extract32(insn, 5, 5); | |
2185 | int size = extract32(insn, 10, 2); | |
2186 | int opcode = extract32(insn, 12, 4); | |
2187 | bool is_store = !extract32(insn, 22, 1); | |
2188 | bool is_postidx = extract32(insn, 23, 1); | |
2189 | bool is_q = extract32(insn, 30, 1); | |
2190 | TCGv_i64 tcg_addr, tcg_rn; | |
2191 | ||
2192 | int ebytes = 1 << size; | |
2193 | int elements = (is_q ? 128 : 64) / (8 << size); | |
2194 | int rpt; /* num iterations */ | |
2195 | int selem; /* structure elements */ | |
2196 | int r; | |
2197 | ||
2198 | if (extract32(insn, 31, 1) || extract32(insn, 21, 1)) { | |
2199 | unallocated_encoding(s); | |
2200 | return; | |
2201 | } | |
2202 | ||
2203 | /* From the shared decode logic */ | |
2204 | switch (opcode) { | |
2205 | case 0x0: | |
2206 | rpt = 1; | |
2207 | selem = 4; | |
2208 | break; | |
2209 | case 0x2: | |
2210 | rpt = 4; | |
2211 | selem = 1; | |
2212 | break; | |
2213 | case 0x4: | |
2214 | rpt = 1; | |
2215 | selem = 3; | |
2216 | break; | |
2217 | case 0x6: | |
2218 | rpt = 3; | |
2219 | selem = 1; | |
2220 | break; | |
2221 | case 0x7: | |
2222 | rpt = 1; | |
2223 | selem = 1; | |
2224 | break; | |
2225 | case 0x8: | |
2226 | rpt = 1; | |
2227 | selem = 2; | |
2228 | break; | |
2229 | case 0xa: | |
2230 | rpt = 2; | |
2231 | selem = 1; | |
2232 | break; | |
2233 | default: | |
2234 | unallocated_encoding(s); | |
2235 | return; | |
2236 | } | |
2237 | ||
2238 | if (size == 3 && !is_q && selem != 1) { | |
2239 | /* reserved */ | |
2240 | unallocated_encoding(s); | |
2241 | return; | |
2242 | } | |
2243 | ||
2244 | if (rn == 31) { | |
2245 | gen_check_sp_alignment(s); | |
2246 | } | |
2247 | ||
2248 | tcg_rn = cpu_reg_sp(s, rn); | |
2249 | tcg_addr = tcg_temp_new_i64(); | |
2250 | tcg_gen_mov_i64(tcg_addr, tcg_rn); | |
2251 | ||
2252 | for (r = 0; r < rpt; r++) { | |
2253 | int e; | |
2254 | for (e = 0; e < elements; e++) { | |
2255 | int tt = (rt + r) % 32; | |
2256 | int xs; | |
2257 | for (xs = 0; xs < selem; xs++) { | |
2258 | if (is_store) { | |
2259 | do_vec_st(s, tt, e, tcg_addr, size); | |
2260 | } else { | |
2261 | do_vec_ld(s, tt, e, tcg_addr, size); | |
2262 | ||
2263 | /* For non-quad operations, setting a slice of the low | |
2264 | * 64 bits of the register clears the high 64 bits (in | |
2265 | * the ARM ARM pseudocode this is implicit in the fact | |
2266 | * that 'rval' is a 64 bit wide variable). We optimize | |
2267 | * by noticing that we only need to do this the first | |
2268 | * time we touch a register. | |
2269 | */ | |
2270 | if (!is_q && e == 0 && (r == 0 || xs == selem - 1)) { | |
2271 | clear_vec_high(s, tt); | |
2272 | } | |
2273 | } | |
2274 | tcg_gen_addi_i64(tcg_addr, tcg_addr, ebytes); | |
2275 | tt = (tt + 1) % 32; | |
2276 | } | |
2277 | } | |
2278 | } | |
2279 | ||
2280 | if (is_postidx) { | |
2281 | int rm = extract32(insn, 16, 5); | |
2282 | if (rm == 31) { | |
2283 | tcg_gen_mov_i64(tcg_rn, tcg_addr); | |
2284 | } else { | |
2285 | tcg_gen_add_i64(tcg_rn, tcg_rn, cpu_reg(s, rm)); | |
2286 | } | |
2287 | } | |
2288 | tcg_temp_free_i64(tcg_addr); | |
ad7ee8a2 CF |
2289 | } |
2290 | ||
df54e47d PM |
2291 | /* C3.3.3 AdvSIMD load/store single structure |
2292 | * | |
2293 | * 31 30 29 23 22 21 20 16 15 13 12 11 10 9 5 4 0 | |
2294 | * +---+---+---------------+-----+-----------+-----+---+------+------+------+ | |
2295 | * | 0 | Q | 0 0 1 1 0 1 0 | L R | 0 0 0 0 0 | opc | S | size | Rn | Rt | | |
2296 | * +---+---+---------------+-----+-----------+-----+---+------+------+------+ | |
2297 | * | |
2298 | * C3.3.4 AdvSIMD load/store single structure (post-indexed) | |
2299 | * | |
2300 | * 31 30 29 23 22 21 20 16 15 13 12 11 10 9 5 4 0 | |
2301 | * +---+---+---------------+-----+-----------+-----+---+------+------+------+ | |
2302 | * | 0 | Q | 0 0 1 1 0 1 1 | L R | Rm | opc | S | size | Rn | Rt | | |
2303 | * +---+---+---------------+-----+-----------+-----+---+------+------+------+ | |
2304 | * | |
2305 | * Rt: first (or only) SIMD&FP register to be transferred | |
2306 | * Rn: base address or SP | |
2307 | * Rm (post-index only): post-index register (when !31) or size dependent #imm | |
2308 | * index = encoded in Q:S:size dependent on size | |
2309 | * | |
2310 | * lane_size = encoded in R, opc | |
2311 | * transfer width = encoded in opc, S, size | |
2312 | */ | |
ad7ee8a2 CF |
2313 | static void disas_ldst_single_struct(DisasContext *s, uint32_t insn) |
2314 | { | |
df54e47d PM |
2315 | int rt = extract32(insn, 0, 5); |
2316 | int rn = extract32(insn, 5, 5); | |
2317 | int size = extract32(insn, 10, 2); | |
2318 | int S = extract32(insn, 12, 1); | |
2319 | int opc = extract32(insn, 13, 3); | |
2320 | int R = extract32(insn, 21, 1); | |
2321 | int is_load = extract32(insn, 22, 1); | |
2322 | int is_postidx = extract32(insn, 23, 1); | |
2323 | int is_q = extract32(insn, 30, 1); | |
2324 | ||
2325 | int scale = extract32(opc, 1, 2); | |
2326 | int selem = (extract32(opc, 0, 1) << 1 | R) + 1; | |
2327 | bool replicate = false; | |
2328 | int index = is_q << 3 | S << 2 | size; | |
2329 | int ebytes, xs; | |
2330 | TCGv_i64 tcg_addr, tcg_rn; | |
2331 | ||
2332 | switch (scale) { | |
2333 | case 3: | |
2334 | if (!is_load || S) { | |
2335 | unallocated_encoding(s); | |
2336 | return; | |
2337 | } | |
2338 | scale = size; | |
2339 | replicate = true; | |
2340 | break; | |
2341 | case 0: | |
2342 | break; | |
2343 | case 1: | |
2344 | if (extract32(size, 0, 1)) { | |
2345 | unallocated_encoding(s); | |
2346 | return; | |
2347 | } | |
2348 | index >>= 1; | |
2349 | break; | |
2350 | case 2: | |
2351 | if (extract32(size, 1, 1)) { | |
2352 | unallocated_encoding(s); | |
2353 | return; | |
2354 | } | |
2355 | if (!extract32(size, 0, 1)) { | |
2356 | index >>= 2; | |
2357 | } else { | |
2358 | if (S) { | |
2359 | unallocated_encoding(s); | |
2360 | return; | |
2361 | } | |
2362 | index >>= 3; | |
2363 | scale = 3; | |
2364 | } | |
2365 | break; | |
2366 | default: | |
2367 | g_assert_not_reached(); | |
2368 | } | |
2369 | ||
2370 | ebytes = 1 << scale; | |
2371 | ||
2372 | if (rn == 31) { | |
2373 | gen_check_sp_alignment(s); | |
2374 | } | |
2375 | ||
2376 | tcg_rn = cpu_reg_sp(s, rn); | |
2377 | tcg_addr = tcg_temp_new_i64(); | |
2378 | tcg_gen_mov_i64(tcg_addr, tcg_rn); | |
2379 | ||
2380 | for (xs = 0; xs < selem; xs++) { | |
2381 | if (replicate) { | |
2382 | /* Load and replicate to all elements */ | |
2383 | uint64_t mulconst; | |
2384 | TCGv_i64 tcg_tmp = tcg_temp_new_i64(); | |
2385 | ||
2386 | tcg_gen_qemu_ld_i64(tcg_tmp, tcg_addr, | |
2387 | get_mem_index(s), MO_TE + scale); | |
2388 | switch (scale) { | |
2389 | case 0: | |
2390 | mulconst = 0x0101010101010101ULL; | |
2391 | break; | |
2392 | case 1: | |
2393 | mulconst = 0x0001000100010001ULL; | |
2394 | break; | |
2395 | case 2: | |
2396 | mulconst = 0x0000000100000001ULL; | |
2397 | break; | |
2398 | case 3: | |
2399 | mulconst = 0; | |
2400 | break; | |
2401 | default: | |
2402 | g_assert_not_reached(); | |
2403 | } | |
2404 | if (mulconst) { | |
2405 | tcg_gen_muli_i64(tcg_tmp, tcg_tmp, mulconst); | |
2406 | } | |
2407 | write_vec_element(s, tcg_tmp, rt, 0, MO_64); | |
2408 | if (is_q) { | |
2409 | write_vec_element(s, tcg_tmp, rt, 1, MO_64); | |
2410 | } else { | |
2411 | clear_vec_high(s, rt); | |
2412 | } | |
2413 | tcg_temp_free_i64(tcg_tmp); | |
2414 | } else { | |
2415 | /* Load/store one element per register */ | |
2416 | if (is_load) { | |
2417 | do_vec_ld(s, rt, index, tcg_addr, MO_TE + scale); | |
2418 | } else { | |
2419 | do_vec_st(s, rt, index, tcg_addr, MO_TE + scale); | |
2420 | } | |
2421 | } | |
2422 | tcg_gen_addi_i64(tcg_addr, tcg_addr, ebytes); | |
2423 | rt = (rt + 1) % 32; | |
2424 | } | |
2425 | ||
2426 | if (is_postidx) { | |
2427 | int rm = extract32(insn, 16, 5); | |
2428 | if (rm == 31) { | |
2429 | tcg_gen_mov_i64(tcg_rn, tcg_addr); | |
2430 | } else { | |
2431 | tcg_gen_add_i64(tcg_rn, tcg_rn, cpu_reg(s, rm)); | |
2432 | } | |
2433 | } | |
2434 | tcg_temp_free_i64(tcg_addr); | |
ad7ee8a2 CF |
2435 | } |
2436 | ||
2437 | /* C3.3 Loads and stores */ | |
2438 | static void disas_ldst(DisasContext *s, uint32_t insn) | |
2439 | { | |
2440 | switch (extract32(insn, 24, 6)) { | |
2441 | case 0x08: /* Load/store exclusive */ | |
2442 | disas_ldst_excl(s, insn); | |
2443 | break; | |
2444 | case 0x18: case 0x1c: /* Load register (literal) */ | |
2445 | disas_ld_lit(s, insn); | |
2446 | break; | |
2447 | case 0x28: case 0x29: | |
2448 | case 0x2c: case 0x2d: /* Load/store pair (all forms) */ | |
2449 | disas_ldst_pair(s, insn); | |
2450 | break; | |
2451 | case 0x38: case 0x39: | |
2452 | case 0x3c: case 0x3d: /* Load/store register (all forms) */ | |
2453 | disas_ldst_reg(s, insn); | |
2454 | break; | |
2455 | case 0x0c: /* AdvSIMD load/store multiple structures */ | |
2456 | disas_ldst_multiple_struct(s, insn); | |
2457 | break; | |
2458 | case 0x0d: /* AdvSIMD load/store single structure */ | |
2459 | disas_ldst_single_struct(s, insn); | |
2460 | break; | |
2461 | default: | |
2462 | unallocated_encoding(s); | |
2463 | break; | |
2464 | } | |
2465 | } | |
2466 | ||
15bfe8b6 AG |
2467 | /* C3.4.6 PC-rel. addressing |
2468 | * 31 30 29 28 24 23 5 4 0 | |
2469 | * +----+-------+-----------+-------------------+------+ | |
2470 | * | op | immlo | 1 0 0 0 0 | immhi | Rd | | |
2471 | * +----+-------+-----------+-------------------+------+ | |
2472 | */ | |
ad7ee8a2 CF |
2473 | static void disas_pc_rel_adr(DisasContext *s, uint32_t insn) |
2474 | { | |
15bfe8b6 AG |
2475 | unsigned int page, rd; |
2476 | uint64_t base; | |
2477 | int64_t offset; | |
2478 | ||
2479 | page = extract32(insn, 31, 1); | |
2480 | /* SignExtend(immhi:immlo) -> offset */ | |
2481 | offset = ((int64_t)sextract32(insn, 5, 19) << 2) | extract32(insn, 29, 2); | |
2482 | rd = extract32(insn, 0, 5); | |
2483 | base = s->pc - 4; | |
2484 | ||
2485 | if (page) { | |
2486 | /* ADRP (page based) */ | |
2487 | base &= ~0xfff; | |
2488 | offset <<= 12; | |
2489 | } | |
2490 | ||
2491 | tcg_gen_movi_i64(cpu_reg(s, rd), base + offset); | |
ad7ee8a2 CF |
2492 | } |
2493 | ||
b0ff21b4 AB |
2494 | /* |
2495 | * C3.4.1 Add/subtract (immediate) | |
2496 | * | |
2497 | * 31 30 29 28 24 23 22 21 10 9 5 4 0 | |
2498 | * +--+--+--+-----------+-----+-------------+-----+-----+ | |
2499 | * |sf|op| S| 1 0 0 0 1 |shift| imm12 | Rn | Rd | | |
2500 | * +--+--+--+-----------+-----+-------------+-----+-----+ | |
2501 | * | |
2502 | * sf: 0 -> 32bit, 1 -> 64bit | |
2503 | * op: 0 -> add , 1 -> sub | |
2504 | * S: 1 -> set flags | |
2505 | * shift: 00 -> LSL imm by 0, 01 -> LSL imm by 12 | |
2506 | */ | |
ad7ee8a2 CF |
2507 | static void disas_add_sub_imm(DisasContext *s, uint32_t insn) |
2508 | { | |
b0ff21b4 AB |
2509 | int rd = extract32(insn, 0, 5); |
2510 | int rn = extract32(insn, 5, 5); | |
2511 | uint64_t imm = extract32(insn, 10, 12); | |
2512 | int shift = extract32(insn, 22, 2); | |
2513 | bool setflags = extract32(insn, 29, 1); | |
2514 | bool sub_op = extract32(insn, 30, 1); | |
2515 | bool is_64bit = extract32(insn, 31, 1); | |
2516 | ||
2517 | TCGv_i64 tcg_rn = cpu_reg_sp(s, rn); | |
2518 | TCGv_i64 tcg_rd = setflags ? cpu_reg(s, rd) : cpu_reg_sp(s, rd); | |
2519 | TCGv_i64 tcg_result; | |
2520 | ||
2521 | switch (shift) { | |
2522 | case 0x0: | |
2523 | break; | |
2524 | case 0x1: | |
2525 | imm <<= 12; | |
2526 | break; | |
2527 | default: | |
2528 | unallocated_encoding(s); | |
2529 | return; | |
2530 | } | |
2531 | ||
2532 | tcg_result = tcg_temp_new_i64(); | |
2533 | if (!setflags) { | |
2534 | if (sub_op) { | |
2535 | tcg_gen_subi_i64(tcg_result, tcg_rn, imm); | |
2536 | } else { | |
2537 | tcg_gen_addi_i64(tcg_result, tcg_rn, imm); | |
2538 | } | |
2539 | } else { | |
2540 | TCGv_i64 tcg_imm = tcg_const_i64(imm); | |
2541 | if (sub_op) { | |
2542 | gen_sub_CC(is_64bit, tcg_result, tcg_rn, tcg_imm); | |
2543 | } else { | |
2544 | gen_add_CC(is_64bit, tcg_result, tcg_rn, tcg_imm); | |
2545 | } | |
2546 | tcg_temp_free_i64(tcg_imm); | |
2547 | } | |
2548 | ||
2549 | if (is_64bit) { | |
2550 | tcg_gen_mov_i64(tcg_rd, tcg_result); | |
2551 | } else { | |
2552 | tcg_gen_ext32u_i64(tcg_rd, tcg_result); | |
2553 | } | |
2554 | ||
2555 | tcg_temp_free_i64(tcg_result); | |
ad7ee8a2 CF |
2556 | } |
2557 | ||
71b46089 AG |
2558 | /* The input should be a value in the bottom e bits (with higher |
2559 | * bits zero); returns that value replicated into every element | |
2560 | * of size e in a 64 bit integer. | |
2561 | */ | |
2562 | static uint64_t bitfield_replicate(uint64_t mask, unsigned int e) | |
2563 | { | |
2564 | assert(e != 0); | |
2565 | while (e < 64) { | |
2566 | mask |= mask << e; | |
2567 | e *= 2; | |
2568 | } | |
2569 | return mask; | |
2570 | } | |
2571 | ||
2572 | /* Return a value with the bottom len bits set (where 0 < len <= 64) */ | |
2573 | static inline uint64_t bitmask64(unsigned int length) | |
2574 | { | |
2575 | assert(length > 0 && length <= 64); | |
2576 | return ~0ULL >> (64 - length); | |
2577 | } | |
2578 | ||
2579 | /* Simplified variant of pseudocode DecodeBitMasks() for the case where we | |
2580 | * only require the wmask. Returns false if the imms/immr/immn are a reserved | |
2581 | * value (ie should cause a guest UNDEF exception), and true if they are | |
2582 | * valid, in which case the decoded bit pattern is written to result. | |
2583 | */ | |
2584 | static bool logic_imm_decode_wmask(uint64_t *result, unsigned int immn, | |
2585 | unsigned int imms, unsigned int immr) | |
2586 | { | |
2587 | uint64_t mask; | |
2588 | unsigned e, levels, s, r; | |
2589 | int len; | |
2590 | ||
2591 | assert(immn < 2 && imms < 64 && immr < 64); | |
2592 | ||
2593 | /* The bit patterns we create here are 64 bit patterns which | |
2594 | * are vectors of identical elements of size e = 2, 4, 8, 16, 32 or | |
2595 | * 64 bits each. Each element contains the same value: a run | |
2596 | * of between 1 and e-1 non-zero bits, rotated within the | |
2597 | * element by between 0 and e-1 bits. | |
2598 | * | |
2599 | * The element size and run length are encoded into immn (1 bit) | |
2600 | * and imms (6 bits) as follows: | |
2601 | * 64 bit elements: immn = 1, imms = <length of run - 1> | |
2602 | * 32 bit elements: immn = 0, imms = 0 : <length of run - 1> | |
2603 | * 16 bit elements: immn = 0, imms = 10 : <length of run - 1> | |
2604 | * 8 bit elements: immn = 0, imms = 110 : <length of run - 1> | |
2605 | * 4 bit elements: immn = 0, imms = 1110 : <length of run - 1> | |
2606 | * 2 bit elements: immn = 0, imms = 11110 : <length of run - 1> | |
2607 | * Notice that immn = 0, imms = 11111x is the only combination | |
2608 | * not covered by one of the above options; this is reserved. | |
2609 | * Further, <length of run - 1> all-ones is a reserved pattern. | |
2610 | * | |
2611 | * In all cases the rotation is by immr % e (and immr is 6 bits). | |
2612 | */ | |
2613 | ||
2614 | /* First determine the element size */ | |
2615 | len = 31 - clz32((immn << 6) | (~imms & 0x3f)); | |
2616 | if (len < 1) { | |
2617 | /* This is the immn == 0, imms == 0x11111x case */ | |
2618 | return false; | |
2619 | } | |
2620 | e = 1 << len; | |
2621 | ||
2622 | levels = e - 1; | |
2623 | s = imms & levels; | |
2624 | r = immr & levels; | |
2625 | ||
2626 | if (s == levels) { | |
2627 | /* <length of run - 1> mustn't be all-ones. */ | |
2628 | return false; | |
2629 | } | |
2630 | ||
2631 | /* Create the value of one element: s+1 set bits rotated | |
2632 | * by r within the element (which is e bits wide)... | |
2633 | */ | |
2634 | mask = bitmask64(s + 1); | |
2635 | mask = (mask >> r) | (mask << (e - r)); | |
2636 | /* ...then replicate the element over the whole 64 bit value */ | |
2637 | mask = bitfield_replicate(mask, e); | |
2638 | *result = mask; | |
2639 | return true; | |
2640 | } | |
2641 | ||
2642 | /* C3.4.4 Logical (immediate) | |
2643 | * 31 30 29 28 23 22 21 16 15 10 9 5 4 0 | |
2644 | * +----+-----+-------------+---+------+------+------+------+ | |
2645 | * | sf | opc | 1 0 0 1 0 0 | N | immr | imms | Rn | Rd | | |
2646 | * +----+-----+-------------+---+------+------+------+------+ | |
2647 | */ | |
ad7ee8a2 CF |
2648 | static void disas_logic_imm(DisasContext *s, uint32_t insn) |
2649 | { | |
71b46089 AG |
2650 | unsigned int sf, opc, is_n, immr, imms, rn, rd; |
2651 | TCGv_i64 tcg_rd, tcg_rn; | |
2652 | uint64_t wmask; | |
2653 | bool is_and = false; | |
2654 | ||
2655 | sf = extract32(insn, 31, 1); | |
2656 | opc = extract32(insn, 29, 2); | |
2657 | is_n = extract32(insn, 22, 1); | |
2658 | immr = extract32(insn, 16, 6); | |
2659 | imms = extract32(insn, 10, 6); | |
2660 | rn = extract32(insn, 5, 5); | |
2661 | rd = extract32(insn, 0, 5); | |
2662 | ||
2663 | if (!sf && is_n) { | |
2664 | unallocated_encoding(s); | |
2665 | return; | |
2666 | } | |
2667 | ||
2668 | if (opc == 0x3) { /* ANDS */ | |
2669 | tcg_rd = cpu_reg(s, rd); | |
2670 | } else { | |
2671 | tcg_rd = cpu_reg_sp(s, rd); | |
2672 | } | |
2673 | tcg_rn = cpu_reg(s, rn); | |
2674 | ||
2675 | if (!logic_imm_decode_wmask(&wmask, is_n, imms, immr)) { | |
2676 | /* some immediate field values are reserved */ | |
2677 | unallocated_encoding(s); | |
2678 | return; | |
2679 | } | |
2680 | ||
2681 | if (!sf) { | |
2682 | wmask &= 0xffffffff; | |
2683 | } | |
2684 | ||
2685 | switch (opc) { | |
2686 | case 0x3: /* ANDS */ | |
2687 | case 0x0: /* AND */ | |
2688 | tcg_gen_andi_i64(tcg_rd, tcg_rn, wmask); | |
2689 | is_and = true; | |
2690 | break; | |
2691 | case 0x1: /* ORR */ | |
2692 | tcg_gen_ori_i64(tcg_rd, tcg_rn, wmask); | |
2693 | break; | |
2694 | case 0x2: /* EOR */ | |
2695 | tcg_gen_xori_i64(tcg_rd, tcg_rn, wmask); | |
2696 | break; | |
2697 | default: | |
2698 | assert(FALSE); /* must handle all above */ | |
2699 | break; | |
2700 | } | |
2701 | ||
2702 | if (!sf && !is_and) { | |
2703 | /* zero extend final result; we know we can skip this for AND | |
2704 | * since the immediate had the high 32 bits clear. | |
2705 | */ | |
2706 | tcg_gen_ext32u_i64(tcg_rd, tcg_rd); | |
2707 | } | |
2708 | ||
2709 | if (opc == 3) { /* ANDS */ | |
2710 | gen_logic_CC(sf, tcg_rd); | |
2711 | } | |
ad7ee8a2 CF |
2712 | } |
2713 | ||
ed6ec679 AB |
2714 | /* |
2715 | * C3.4.5 Move wide (immediate) | |
2716 | * | |
2717 | * 31 30 29 28 23 22 21 20 5 4 0 | |
2718 | * +--+-----+-------------+-----+----------------+------+ | |
2719 | * |sf| opc | 1 0 0 1 0 1 | hw | imm16 | Rd | | |
2720 | * +--+-----+-------------+-----+----------------+------+ | |
2721 | * | |
2722 | * sf: 0 -> 32 bit, 1 -> 64 bit | |
2723 | * opc: 00 -> N, 10 -> Z, 11 -> K | |
2724 | * hw: shift/16 (0,16, and sf only 32, 48) | |
2725 | */ | |
ad7ee8a2 CF |
2726 | static void disas_movw_imm(DisasContext *s, uint32_t insn) |
2727 | { | |
ed6ec679 AB |
2728 | int rd = extract32(insn, 0, 5); |
2729 | uint64_t imm = extract32(insn, 5, 16); | |
2730 | int sf = extract32(insn, 31, 1); | |
2731 | int opc = extract32(insn, 29, 2); | |
2732 | int pos = extract32(insn, 21, 2) << 4; | |
2733 | TCGv_i64 tcg_rd = cpu_reg(s, rd); | |
2734 | TCGv_i64 tcg_imm; | |
2735 | ||
2736 | if (!sf && (pos >= 32)) { | |
2737 | unallocated_encoding(s); | |
2738 | return; | |
2739 | } | |
2740 | ||
2741 | switch (opc) { | |
2742 | case 0: /* MOVN */ | |
2743 | case 2: /* MOVZ */ | |
2744 | imm <<= pos; | |
2745 | if (opc == 0) { | |
2746 | imm = ~imm; | |
2747 | } | |
2748 | if (!sf) { | |
2749 | imm &= 0xffffffffu; | |
2750 | } | |
2751 | tcg_gen_movi_i64(tcg_rd, imm); | |
2752 | break; | |
2753 | case 3: /* MOVK */ | |
2754 | tcg_imm = tcg_const_i64(imm); | |
2755 | tcg_gen_deposit_i64(tcg_rd, tcg_rd, tcg_imm, pos, 16); | |
2756 | tcg_temp_free_i64(tcg_imm); | |
2757 | if (!sf) { | |
2758 | tcg_gen_ext32u_i64(tcg_rd, tcg_rd); | |
2759 | } | |
2760 | break; | |
2761 | default: | |
2762 | unallocated_encoding(s); | |
2763 | break; | |
2764 | } | |
ad7ee8a2 CF |
2765 | } |
2766 | ||
88077742 CF |
2767 | /* C3.4.2 Bitfield |
2768 | * 31 30 29 28 23 22 21 16 15 10 9 5 4 0 | |
2769 | * +----+-----+-------------+---+------+------+------+------+ | |
2770 | * | sf | opc | 1 0 0 1 1 0 | N | immr | imms | Rn | Rd | | |
2771 | * +----+-----+-------------+---+------+------+------+------+ | |
2772 | */ | |
ad7ee8a2 CF |
2773 | static void disas_bitfield(DisasContext *s, uint32_t insn) |
2774 | { | |
88077742 CF |
2775 | unsigned int sf, n, opc, ri, si, rn, rd, bitsize, pos, len; |
2776 | TCGv_i64 tcg_rd, tcg_tmp; | |
2777 | ||
2778 | sf = extract32(insn, 31, 1); | |
2779 | opc = extract32(insn, 29, 2); | |
2780 | n = extract32(insn, 22, 1); | |
2781 | ri = extract32(insn, 16, 6); | |
2782 | si = extract32(insn, 10, 6); | |
2783 | rn = extract32(insn, 5, 5); | |
2784 | rd = extract32(insn, 0, 5); | |
2785 | bitsize = sf ? 64 : 32; | |
2786 | ||
2787 | if (sf != n || ri >= bitsize || si >= bitsize || opc > 2) { | |
2788 | unallocated_encoding(s); | |
2789 | return; | |
2790 | } | |
2791 | ||
2792 | tcg_rd = cpu_reg(s, rd); | |
2793 | tcg_tmp = read_cpu_reg(s, rn, sf); | |
2794 | ||
2795 | /* OPTME: probably worth recognizing common cases of ext{8,16,32}{u,s} */ | |
2796 | ||
2797 | if (opc != 1) { /* SBFM or UBFM */ | |
2798 | tcg_gen_movi_i64(tcg_rd, 0); | |
2799 | } | |
2800 | ||
2801 | /* do the bit move operation */ | |
2802 | if (si >= ri) { | |
2803 | /* Wd<s-r:0> = Wn<s:r> */ | |
2804 | tcg_gen_shri_i64(tcg_tmp, tcg_tmp, ri); | |
2805 | pos = 0; | |
2806 | len = (si - ri) + 1; | |
2807 | } else { | |
2808 | /* Wd<32+s-r,32-r> = Wn<s:0> */ | |
2809 | pos = bitsize - ri; | |
2810 | len = si + 1; | |
2811 | } | |
2812 | ||
2813 | tcg_gen_deposit_i64(tcg_rd, tcg_rd, tcg_tmp, pos, len); | |
2814 | ||
2815 | if (opc == 0) { /* SBFM - sign extend the destination field */ | |
2816 | tcg_gen_shli_i64(tcg_rd, tcg_rd, 64 - (pos + len)); | |
2817 | tcg_gen_sari_i64(tcg_rd, tcg_rd, 64 - (pos + len)); | |
2818 | } | |
2819 | ||
2820 | if (!sf) { /* zero extend final result */ | |
2821 | tcg_gen_ext32u_i64(tcg_rd, tcg_rd); | |
2822 | } | |
ad7ee8a2 CF |
2823 | } |
2824 | ||
e801de93 AG |
2825 | /* C3.4.3 Extract |
2826 | * 31 30 29 28 23 22 21 20 16 15 10 9 5 4 0 | |
2827 | * +----+------+-------------+---+----+------+--------+------+------+ | |
2828 | * | sf | op21 | 1 0 0 1 1 1 | N | o0 | Rm | imms | Rn | Rd | | |
2829 | * +----+------+-------------+---+----+------+--------+------+------+ | |
2830 | */ | |
ad7ee8a2 CF |
2831 | static void disas_extract(DisasContext *s, uint32_t insn) |
2832 | { | |
e801de93 AG |
2833 | unsigned int sf, n, rm, imm, rn, rd, bitsize, op21, op0; |
2834 | ||
2835 | sf = extract32(insn, 31, 1); | |
2836 | n = extract32(insn, 22, 1); | |
2837 | rm = extract32(insn, 16, 5); | |
2838 | imm = extract32(insn, 10, 6); | |
2839 | rn = extract32(insn, 5, 5); | |
2840 | rd = extract32(insn, 0, 5); | |
2841 | op21 = extract32(insn, 29, 2); | |
2842 | op0 = extract32(insn, 21, 1); | |
2843 | bitsize = sf ? 64 : 32; | |
2844 | ||
2845 | if (sf != n || op21 || op0 || imm >= bitsize) { | |
2846 | unallocated_encoding(s); | |
2847 | } else { | |
2848 | TCGv_i64 tcg_rd, tcg_rm, tcg_rn; | |
2849 | ||
2850 | tcg_rd = cpu_reg(s, rd); | |
2851 | ||
2852 | if (imm) { | |
2853 | /* OPTME: we can special case rm==rn as a rotate */ | |
2854 | tcg_rm = read_cpu_reg(s, rm, sf); | |
2855 | tcg_rn = read_cpu_reg(s, rn, sf); | |
2856 | tcg_gen_shri_i64(tcg_rm, tcg_rm, imm); | |
2857 | tcg_gen_shli_i64(tcg_rn, tcg_rn, bitsize - imm); | |
2858 | tcg_gen_or_i64(tcg_rd, tcg_rm, tcg_rn); | |
2859 | if (!sf) { | |
2860 | tcg_gen_ext32u_i64(tcg_rd, tcg_rd); | |
2861 | } | |
2862 | } else { | |
2863 | /* tcg shl_i32/shl_i64 is undefined for 32/64 bit shifts, | |
2864 | * so an extract from bit 0 is a special case. | |
2865 | */ | |
2866 | if (sf) { | |
2867 | tcg_gen_mov_i64(tcg_rd, cpu_reg(s, rm)); | |
2868 | } else { | |
2869 | tcg_gen_ext32u_i64(tcg_rd, cpu_reg(s, rm)); | |
2870 | } | |
2871 | } | |
2872 | ||
2873 | } | |
ad7ee8a2 CF |
2874 | } |
2875 | ||
2876 | /* C3.4 Data processing - immediate */ | |
2877 | static void disas_data_proc_imm(DisasContext *s, uint32_t insn) | |
2878 | { | |
2879 | switch (extract32(insn, 23, 6)) { | |
2880 | case 0x20: case 0x21: /* PC-rel. addressing */ | |
2881 | disas_pc_rel_adr(s, insn); | |
2882 | break; | |
2883 | case 0x22: case 0x23: /* Add/subtract (immediate) */ | |
2884 | disas_add_sub_imm(s, insn); | |
2885 | break; | |
2886 | case 0x24: /* Logical (immediate) */ | |
2887 | disas_logic_imm(s, insn); | |
2888 | break; | |
2889 | case 0x25: /* Move wide (immediate) */ | |
2890 | disas_movw_imm(s, insn); | |
2891 | break; | |
2892 | case 0x26: /* Bitfield */ | |
2893 | disas_bitfield(s, insn); | |
2894 | break; | |
2895 | case 0x27: /* Extract */ | |
2896 | disas_extract(s, insn); | |
2897 | break; | |
2898 | default: | |
2899 | unallocated_encoding(s); | |
2900 | break; | |
2901 | } | |
2902 | } | |
2903 | ||
832ffa1c AG |
2904 | /* Shift a TCGv src by TCGv shift_amount, put result in dst. |
2905 | * Note that it is the caller's responsibility to ensure that the | |
2906 | * shift amount is in range (ie 0..31 or 0..63) and provide the ARM | |
2907 | * mandated semantics for out of range shifts. | |
2908 | */ | |
2909 | static void shift_reg(TCGv_i64 dst, TCGv_i64 src, int sf, | |
2910 | enum a64_shift_type shift_type, TCGv_i64 shift_amount) | |
2911 | { | |
2912 | switch (shift_type) { | |
2913 | case A64_SHIFT_TYPE_LSL: | |
2914 | tcg_gen_shl_i64(dst, src, shift_amount); | |
2915 | break; | |
2916 | case A64_SHIFT_TYPE_LSR: | |
2917 | tcg_gen_shr_i64(dst, src, shift_amount); | |
2918 | break; | |
2919 | case A64_SHIFT_TYPE_ASR: | |
2920 | if (!sf) { | |
2921 | tcg_gen_ext32s_i64(dst, src); | |
2922 | } | |
2923 | tcg_gen_sar_i64(dst, sf ? src : dst, shift_amount); | |
2924 | break; | |
2925 | case A64_SHIFT_TYPE_ROR: | |
2926 | if (sf) { | |
2927 | tcg_gen_rotr_i64(dst, src, shift_amount); | |
2928 | } else { | |
2929 | TCGv_i32 t0, t1; | |
2930 | t0 = tcg_temp_new_i32(); | |
2931 | t1 = tcg_temp_new_i32(); | |
2932 | tcg_gen_trunc_i64_i32(t0, src); | |
2933 | tcg_gen_trunc_i64_i32(t1, shift_amount); | |
2934 | tcg_gen_rotr_i32(t0, t0, t1); | |
2935 | tcg_gen_extu_i32_i64(dst, t0); | |
2936 | tcg_temp_free_i32(t0); | |
2937 | tcg_temp_free_i32(t1); | |
2938 | } | |
2939 | break; | |
2940 | default: | |
2941 | assert(FALSE); /* all shift types should be handled */ | |
2942 | break; | |
2943 | } | |
2944 | ||
2945 | if (!sf) { /* zero extend final result */ | |
2946 | tcg_gen_ext32u_i64(dst, dst); | |
2947 | } | |
2948 | } | |
2949 | ||
2950 | /* Shift a TCGv src by immediate, put result in dst. | |
2951 | * The shift amount must be in range (this should always be true as the | |
2952 | * relevant instructions will UNDEF on bad shift immediates). | |
2953 | */ | |
2954 | static void shift_reg_imm(TCGv_i64 dst, TCGv_i64 src, int sf, | |
2955 | enum a64_shift_type shift_type, unsigned int shift_i) | |
2956 | { | |
2957 | assert(shift_i < (sf ? 64 : 32)); | |
2958 | ||
2959 | if (shift_i == 0) { | |
2960 | tcg_gen_mov_i64(dst, src); | |
2961 | } else { | |
2962 | TCGv_i64 shift_const; | |
2963 | ||
2964 | shift_const = tcg_const_i64(shift_i); | |
2965 | shift_reg(dst, src, sf, shift_type, shift_const); | |
2966 | tcg_temp_free_i64(shift_const); | |
2967 | } | |
2968 | } | |
2969 | ||
2970 | /* C3.5.10 Logical (shifted register) | |
2971 | * 31 30 29 28 24 23 22 21 20 16 15 10 9 5 4 0 | |
2972 | * +----+-----+-----------+-------+---+------+--------+------+------+ | |
2973 | * | sf | opc | 0 1 0 1 0 | shift | N | Rm | imm6 | Rn | Rd | | |
2974 | * +----+-----+-----------+-------+---+------+--------+------+------+ | |
2975 | */ | |
ad7ee8a2 CF |
2976 | static void disas_logic_reg(DisasContext *s, uint32_t insn) |
2977 | { | |
832ffa1c AG |
2978 | TCGv_i64 tcg_rd, tcg_rn, tcg_rm; |
2979 | unsigned int sf, opc, shift_type, invert, rm, shift_amount, rn, rd; | |
2980 | ||
2981 | sf = extract32(insn, 31, 1); | |
2982 | opc = extract32(insn, 29, 2); | |
2983 | shift_type = extract32(insn, 22, 2); | |
2984 | invert = extract32(insn, 21, 1); | |
2985 | rm = extract32(insn, 16, 5); | |
2986 | shift_amount = extract32(insn, 10, 6); | |
2987 | rn = extract32(insn, 5, 5); | |
2988 | rd = extract32(insn, 0, 5); | |
2989 | ||
2990 | if (!sf && (shift_amount & (1 << 5))) { | |
2991 | unallocated_encoding(s); | |
2992 | return; | |
2993 | } | |
2994 | ||
2995 | tcg_rd = cpu_reg(s, rd); | |
2996 | ||
2997 | if (opc == 1 && shift_amount == 0 && shift_type == 0 && rn == 31) { | |
2998 | /* Unshifted ORR and ORN with WZR/XZR is the standard encoding for | |
2999 | * register-register MOV and MVN, so it is worth special casing. | |
3000 | */ | |
3001 | tcg_rm = cpu_reg(s, rm); | |
3002 | if (invert) { | |
3003 | tcg_gen_not_i64(tcg_rd, tcg_rm); | |
3004 | if (!sf) { | |
3005 | tcg_gen_ext32u_i64(tcg_rd, tcg_rd); | |
3006 | } | |
3007 | } else { | |
3008 | if (sf) { | |
3009 | tcg_gen_mov_i64(tcg_rd, tcg_rm); | |
3010 | } else { | |
3011 | tcg_gen_ext32u_i64(tcg_rd, tcg_rm); | |
3012 | } | |
3013 | } | |
3014 | return; | |
3015 | } | |
3016 | ||
3017 | tcg_rm = read_cpu_reg(s, rm, sf); | |
3018 | ||
3019 | if (shift_amount) { | |
3020 | shift_reg_imm(tcg_rm, tcg_rm, sf, shift_type, shift_amount); | |
3021 | } | |
3022 | ||
3023 | tcg_rn = cpu_reg(s, rn); | |
3024 | ||
3025 | switch (opc | (invert << 2)) { | |
3026 | case 0: /* AND */ | |
3027 | case 3: /* ANDS */ | |
3028 | tcg_gen_and_i64(tcg_rd, tcg_rn, tcg_rm); | |
3029 | break; | |
3030 | case 1: /* ORR */ | |
3031 | tcg_gen_or_i64(tcg_rd, tcg_rn, tcg_rm); | |
3032 | break; | |
3033 | case 2: /* EOR */ | |
3034 | tcg_gen_xor_i64(tcg_rd, tcg_rn, tcg_rm); | |
3035 | break; | |
3036 | case 4: /* BIC */ | |
3037 | case 7: /* BICS */ | |
3038 | tcg_gen_andc_i64(tcg_rd, tcg_rn, tcg_rm); | |
3039 | break; | |
3040 | case 5: /* ORN */ | |
3041 | tcg_gen_orc_i64(tcg_rd, tcg_rn, tcg_rm); | |
3042 | break; | |
3043 | case 6: /* EON */ | |
3044 | tcg_gen_eqv_i64(tcg_rd, tcg_rn, tcg_rm); | |
3045 | break; | |
3046 | default: | |
3047 | assert(FALSE); | |
3048 | break; | |
3049 | } | |
3050 | ||
3051 | if (!sf) { | |
3052 | tcg_gen_ext32u_i64(tcg_rd, tcg_rd); | |
3053 | } | |
3054 | ||
3055 | if (opc == 3) { | |
3056 | gen_logic_CC(sf, tcg_rd); | |
3057 | } | |
ad7ee8a2 CF |
3058 | } |
3059 | ||
b0ff21b4 AB |
3060 | /* |
3061 | * C3.5.1 Add/subtract (extended register) | |
3062 | * | |
3063 | * 31|30|29|28 24|23 22|21|20 16|15 13|12 10|9 5|4 0| | |
3064 | * +--+--+--+-----------+-----+--+-------+------+------+----+----+ | |
3065 | * |sf|op| S| 0 1 0 1 1 | opt | 1| Rm |option| imm3 | Rn | Rd | | |
3066 | * +--+--+--+-----------+-----+--+-------+------+------+----+----+ | |
3067 | * | |
3068 | * sf: 0 -> 32bit, 1 -> 64bit | |
3069 | * op: 0 -> add , 1 -> sub | |
3070 | * S: 1 -> set flags | |
3071 | * opt: 00 | |
3072 | * option: extension type (see DecodeRegExtend) | |
3073 | * imm3: optional shift to Rm | |
3074 | * | |
3075 | * Rd = Rn + LSL(extend(Rm), amount) | |
3076 | */ | |
ad7ee8a2 CF |
3077 | static void disas_add_sub_ext_reg(DisasContext *s, uint32_t insn) |
3078 | { | |
b0ff21b4 AB |
3079 | int rd = extract32(insn, 0, 5); |
3080 | int rn = extract32(insn, 5, 5); | |
3081 | int imm3 = extract32(insn, 10, 3); | |
3082 | int option = extract32(insn, 13, 3); | |
3083 | int rm = extract32(insn, 16, 5); | |
3084 | bool setflags = extract32(insn, 29, 1); | |
3085 | bool sub_op = extract32(insn, 30, 1); | |
3086 | bool sf = extract32(insn, 31, 1); | |
3087 | ||
3088 | TCGv_i64 tcg_rm, tcg_rn; /* temps */ | |
3089 | TCGv_i64 tcg_rd; | |
3090 | TCGv_i64 tcg_result; | |
3091 | ||
3092 | if (imm3 > 4) { | |
3093 | unallocated_encoding(s); | |
3094 | return; | |
3095 | } | |
3096 | ||
3097 | /* non-flag setting ops may use SP */ | |
3098 | if (!setflags) { | |
3099 | tcg_rn = read_cpu_reg_sp(s, rn, sf); | |
3100 | tcg_rd = cpu_reg_sp(s, rd); | |
3101 | } else { | |
3102 | tcg_rn = read_cpu_reg(s, rn, sf); | |
3103 | tcg_rd = cpu_reg(s, rd); | |
3104 | } | |
3105 | ||
3106 | tcg_rm = read_cpu_reg(s, rm, sf); | |
3107 | ext_and_shift_reg(tcg_rm, tcg_rm, option, imm3); | |
3108 | ||
3109 | tcg_result = tcg_temp_new_i64(); | |
3110 | ||
3111 | if (!setflags) { | |
3112 | if (sub_op) { | |
3113 | tcg_gen_sub_i64(tcg_result, tcg_rn, tcg_rm); | |
3114 | } else { | |
3115 | tcg_gen_add_i64(tcg_result, tcg_rn, tcg_rm); | |
3116 | } | |
3117 | } else { | |
3118 | if (sub_op) { | |
3119 | gen_sub_CC(sf, tcg_result, tcg_rn, tcg_rm); | |
3120 | } else { | |
3121 | gen_add_CC(sf, tcg_result, tcg_rn, tcg_rm); | |
3122 | } | |
3123 | } | |
3124 | ||
3125 | if (sf) { | |
3126 | tcg_gen_mov_i64(tcg_rd, tcg_result); | |
3127 | } else { | |
3128 | tcg_gen_ext32u_i64(tcg_rd, tcg_result); | |
3129 | } | |
3130 | ||
3131 | tcg_temp_free_i64(tcg_result); | |
ad7ee8a2 CF |
3132 | } |
3133 | ||
b0ff21b4 AB |
3134 | /* |
3135 | * C3.5.2 Add/subtract (shifted register) | |
3136 | * | |
3137 | * 31 30 29 28 24 23 22 21 20 16 15 10 9 5 4 0 | |
3138 | * +--+--+--+-----------+-----+--+-------+---------+------+------+ | |
3139 | * |sf|op| S| 0 1 0 1 1 |shift| 0| Rm | imm6 | Rn | Rd | | |
3140 | * +--+--+--+-----------+-----+--+-------+---------+------+------+ | |
3141 | * | |
3142 | * sf: 0 -> 32bit, 1 -> 64bit | |
3143 | * op: 0 -> add , 1 -> sub | |
3144 | * S: 1 -> set flags | |
3145 | * shift: 00 -> LSL, 01 -> LSR, 10 -> ASR, 11 -> RESERVED | |
3146 | * imm6: Shift amount to apply to Rm before the add/sub | |
3147 | */ | |
ad7ee8a2 CF |
3148 | static void disas_add_sub_reg(DisasContext *s, uint32_t insn) |
3149 | { | |
b0ff21b4 AB |
3150 | int rd = extract32(insn, 0, 5); |
3151 | int rn = extract32(insn, 5, 5); | |
3152 | int imm6 = extract32(insn, 10, 6); | |
3153 | int rm = extract32(insn, 16, 5); | |
3154 | int shift_type = extract32(insn, 22, 2); | |
3155 | bool setflags = extract32(insn, 29, 1); | |
3156 | bool sub_op = extract32(insn, 30, 1); | |
3157 | bool sf = extract32(insn, 31, 1); | |
3158 | ||
3159 | TCGv_i64 tcg_rd = cpu_reg(s, rd); | |
3160 | TCGv_i64 tcg_rn, tcg_rm; | |
3161 | TCGv_i64 tcg_result; | |
3162 | ||
3163 | if ((shift_type == 3) || (!sf && (imm6 > 31))) { | |
3164 | unallocated_encoding(s); | |
3165 | return; | |
3166 | } | |
3167 | ||
3168 | tcg_rn = read_cpu_reg(s, rn, sf); | |
3169 | tcg_rm = read_cpu_reg(s, rm, sf); | |
3170 | ||
3171 | shift_reg_imm(tcg_rm, tcg_rm, sf, shift_type, imm6); | |
3172 | ||
3173 | tcg_result = tcg_temp_new_i64(); | |
3174 | ||
3175 | if (!setflags) { | |
3176 | if (sub_op) { | |
3177 | tcg_gen_sub_i64(tcg_result, tcg_rn, tcg_rm); | |
3178 | } else { | |
3179 | tcg_gen_add_i64(tcg_result, tcg_rn, tcg_rm); | |
3180 | } | |
3181 | } else { | |
3182 | if (sub_op) { | |
3183 | gen_sub_CC(sf, tcg_result, tcg_rn, tcg_rm); | |
3184 | } else { | |
3185 | gen_add_CC(sf, tcg_result, tcg_rn, tcg_rm); | |
3186 | } | |
3187 | } | |
3188 | ||
3189 | if (sf) { | |
3190 | tcg_gen_mov_i64(tcg_rd, tcg_result); | |
3191 | } else { | |
3192 | tcg_gen_ext32u_i64(tcg_rd, tcg_result); | |
3193 | } | |
3194 | ||
3195 | tcg_temp_free_i64(tcg_result); | |
ad7ee8a2 CF |
3196 | } |
3197 | ||
52c8b9af AG |
3198 | /* C3.5.9 Data-processing (3 source) |
3199 | ||
3200 | 31 30 29 28 24 23 21 20 16 15 14 10 9 5 4 0 | |
3201 | +--+------+-----------+------+------+----+------+------+------+ | |
3202 | |sf| op54 | 1 1 0 1 1 | op31 | Rm | o0 | Ra | Rn | Rd | | |
3203 | +--+------+-----------+------+------+----+------+------+------+ | |
3204 | ||
3205 | */ | |
ad7ee8a2 CF |
3206 | static void disas_data_proc_3src(DisasContext *s, uint32_t insn) |
3207 | { | |
52c8b9af AG |
3208 | int rd = extract32(insn, 0, 5); |
3209 | int rn = extract32(insn, 5, 5); | |
3210 | int ra = extract32(insn, 10, 5); | |
3211 | int rm = extract32(insn, 16, 5); | |
3212 | int op_id = (extract32(insn, 29, 3) << 4) | | |
3213 | (extract32(insn, 21, 3) << 1) | | |
3214 | extract32(insn, 15, 1); | |
3215 | bool sf = extract32(insn, 31, 1); | |
3216 | bool is_sub = extract32(op_id, 0, 1); | |
3217 | bool is_high = extract32(op_id, 2, 1); | |
3218 | bool is_signed = false; | |
3219 | TCGv_i64 tcg_op1; | |
3220 | TCGv_i64 tcg_op2; | |
3221 | TCGv_i64 tcg_tmp; | |
3222 | ||
3223 | /* Note that op_id is sf:op54:op31:o0 so it includes the 32/64 size flag */ | |
3224 | switch (op_id) { | |
3225 | case 0x42: /* SMADDL */ | |
3226 | case 0x43: /* SMSUBL */ | |
3227 | case 0x44: /* SMULH */ | |
3228 | is_signed = true; | |
3229 | break; | |
3230 | case 0x0: /* MADD (32bit) */ | |
3231 | case 0x1: /* MSUB (32bit) */ | |
3232 | case 0x40: /* MADD (64bit) */ | |
3233 | case 0x41: /* MSUB (64bit) */ | |
3234 | case 0x4a: /* UMADDL */ | |
3235 | case 0x4b: /* UMSUBL */ | |
3236 | case 0x4c: /* UMULH */ | |
3237 | break; | |
3238 | default: | |
3239 | unallocated_encoding(s); | |
3240 | return; | |
3241 | } | |
3242 | ||
3243 | if (is_high) { | |
3244 | TCGv_i64 low_bits = tcg_temp_new_i64(); /* low bits discarded */ | |
3245 | TCGv_i64 tcg_rd = cpu_reg(s, rd); | |
3246 | TCGv_i64 tcg_rn = cpu_reg(s, rn); | |
3247 | TCGv_i64 tcg_rm = cpu_reg(s, rm); | |
3248 | ||
3249 | if (is_signed) { | |
3250 | tcg_gen_muls2_i64(low_bits, tcg_rd, tcg_rn, tcg_rm); | |
3251 | } else { | |
3252 | tcg_gen_mulu2_i64(low_bits, tcg_rd, tcg_rn, tcg_rm); | |
3253 | } | |
3254 | ||
3255 | tcg_temp_free_i64(low_bits); | |
3256 | return; | |
3257 | } | |
3258 | ||
3259 | tcg_op1 = tcg_temp_new_i64(); | |
3260 | tcg_op2 = tcg_temp_new_i64(); | |
3261 | tcg_tmp = tcg_temp_new_i64(); | |
3262 | ||
3263 | if (op_id < 0x42) { | |
3264 | tcg_gen_mov_i64(tcg_op1, cpu_reg(s, rn)); | |
3265 | tcg_gen_mov_i64(tcg_op2, cpu_reg(s, rm)); | |
3266 | } else { | |
3267 | if (is_signed) { | |
3268 | tcg_gen_ext32s_i64(tcg_op1, cpu_reg(s, rn)); | |
3269 | tcg_gen_ext32s_i64(tcg_op2, cpu_reg(s, rm)); | |
3270 | } else { | |
3271 | tcg_gen_ext32u_i64(tcg_op1, cpu_reg(s, rn)); | |
3272 | tcg_gen_ext32u_i64(tcg_op2, cpu_reg(s, rm)); | |
3273 | } | |
3274 | } | |
3275 | ||
3276 | if (ra == 31 && !is_sub) { | |
3277 | /* Special-case MADD with rA == XZR; it is the standard MUL alias */ | |
3278 | tcg_gen_mul_i64(cpu_reg(s, rd), tcg_op1, tcg_op2); | |
3279 | } else { | |
3280 | tcg_gen_mul_i64(tcg_tmp, tcg_op1, tcg_op2); | |
3281 | if (is_sub) { | |
3282 | tcg_gen_sub_i64(cpu_reg(s, rd), cpu_reg(s, ra), tcg_tmp); | |
3283 | } else { | |
3284 | tcg_gen_add_i64(cpu_reg(s, rd), cpu_reg(s, ra), tcg_tmp); | |
3285 | } | |
3286 | } | |
3287 | ||
3288 | if (!sf) { | |
3289 | tcg_gen_ext32u_i64(cpu_reg(s, rd), cpu_reg(s, rd)); | |
3290 | } | |
3291 | ||
3292 | tcg_temp_free_i64(tcg_op1); | |
3293 | tcg_temp_free_i64(tcg_op2); | |
3294 | tcg_temp_free_i64(tcg_tmp); | |
ad7ee8a2 CF |
3295 | } |
3296 | ||
643dbb07 CF |
3297 | /* C3.5.3 - Add/subtract (with carry) |
3298 | * 31 30 29 28 27 26 25 24 23 22 21 20 16 15 10 9 5 4 0 | |
3299 | * +--+--+--+------------------------+------+---------+------+-----+ | |
3300 | * |sf|op| S| 1 1 0 1 0 0 0 0 | rm | opcode2 | Rn | Rd | | |
3301 | * +--+--+--+------------------------+------+---------+------+-----+ | |
3302 | * [000000] | |
3303 | */ | |
3304 | ||
ad7ee8a2 CF |
3305 | static void disas_adc_sbc(DisasContext *s, uint32_t insn) |
3306 | { | |
643dbb07 CF |
3307 | unsigned int sf, op, setflags, rm, rn, rd; |
3308 | TCGv_i64 tcg_y, tcg_rn, tcg_rd; | |
3309 | ||
3310 | if (extract32(insn, 10, 6) != 0) { | |
3311 | unallocated_encoding(s); | |
3312 | return; | |
3313 | } | |
3314 | ||
3315 | sf = extract32(insn, 31, 1); | |
3316 | op = extract32(insn, 30, 1); | |
3317 | setflags = extract32(insn, 29, 1); | |
3318 | rm = extract32(insn, 16, 5); | |
3319 | rn = extract32(insn, 5, 5); | |
3320 | rd = extract32(insn, 0, 5); | |
3321 | ||
3322 | tcg_rd = cpu_reg(s, rd); | |
3323 | tcg_rn = cpu_reg(s, rn); | |
3324 | ||
3325 | if (op) { | |
3326 | tcg_y = new_tmp_a64(s); | |
3327 | tcg_gen_not_i64(tcg_y, cpu_reg(s, rm)); | |
3328 | } else { | |
3329 | tcg_y = cpu_reg(s, rm); | |
3330 | } | |
3331 | ||
3332 | if (setflags) { | |
3333 | gen_adc_CC(sf, tcg_rd, tcg_rn, tcg_y); | |
3334 | } else { | |
3335 | gen_adc(sf, tcg_rd, tcg_rn, tcg_y); | |
3336 | } | |
ad7ee8a2 CF |
3337 | } |
3338 | ||
750813cf CF |
3339 | /* C3.5.4 - C3.5.5 Conditional compare (immediate / register) |
3340 | * 31 30 29 28 27 26 25 24 23 22 21 20 16 15 12 11 10 9 5 4 3 0 | |
3341 | * +--+--+--+------------------------+--------+------+----+--+------+--+-----+ | |
3342 | * |sf|op| S| 1 1 0 1 0 0 1 0 |imm5/rm | cond |i/r |o2| Rn |o3|nzcv | | |
3343 | * +--+--+--+------------------------+--------+------+----+--+------+--+-----+ | |
3344 | * [1] y [0] [0] | |
3345 | */ | |
3346 | static void disas_cc(DisasContext *s, uint32_t insn) | |
ad7ee8a2 | 3347 | { |
750813cf CF |
3348 | unsigned int sf, op, y, cond, rn, nzcv, is_imm; |
3349 | int label_continue = -1; | |
3350 | TCGv_i64 tcg_tmp, tcg_y, tcg_rn; | |
ad7ee8a2 | 3351 | |
750813cf CF |
3352 | if (!extract32(insn, 29, 1)) { |
3353 | unallocated_encoding(s); | |
3354 | return; | |
3355 | } | |
3356 | if (insn & (1 << 10 | 1 << 4)) { | |
3357 | unallocated_encoding(s); | |
3358 | return; | |
3359 | } | |
3360 | sf = extract32(insn, 31, 1); | |
3361 | op = extract32(insn, 30, 1); | |
3362 | is_imm = extract32(insn, 11, 1); | |
3363 | y = extract32(insn, 16, 5); /* y = rm (reg) or imm5 (imm) */ | |
3364 | cond = extract32(insn, 12, 4); | |
3365 | rn = extract32(insn, 5, 5); | |
3366 | nzcv = extract32(insn, 0, 4); | |
3367 | ||
3368 | if (cond < 0x0e) { /* not always */ | |
3369 | int label_match = gen_new_label(); | |
3370 | label_continue = gen_new_label(); | |
3371 | arm_gen_test_cc(cond, label_match); | |
3372 | /* nomatch: */ | |
3373 | tcg_tmp = tcg_temp_new_i64(); | |
3374 | tcg_gen_movi_i64(tcg_tmp, nzcv << 28); | |
3375 | gen_set_nzcv(tcg_tmp); | |
3376 | tcg_temp_free_i64(tcg_tmp); | |
3377 | tcg_gen_br(label_continue); | |
3378 | gen_set_label(label_match); | |
3379 | } | |
3380 | /* match, or condition is always */ | |
3381 | if (is_imm) { | |
3382 | tcg_y = new_tmp_a64(s); | |
3383 | tcg_gen_movi_i64(tcg_y, y); | |
3384 | } else { | |
3385 | tcg_y = cpu_reg(s, y); | |
3386 | } | |
3387 | tcg_rn = cpu_reg(s, rn); | |
3388 | ||
3389 | tcg_tmp = tcg_temp_new_i64(); | |
3390 | if (op) { | |
3391 | gen_sub_CC(sf, tcg_tmp, tcg_rn, tcg_y); | |
3392 | } else { | |
3393 | gen_add_CC(sf, tcg_tmp, tcg_rn, tcg_y); | |
3394 | } | |
3395 | tcg_temp_free_i64(tcg_tmp); | |
3396 | ||
3397 | if (cond < 0x0e) { /* continue */ | |
3398 | gen_set_label(label_continue); | |
3399 | } | |
ad7ee8a2 CF |
3400 | } |
3401 | ||
e952d8c7 CF |
3402 | /* C3.5.6 Conditional select |
3403 | * 31 30 29 28 21 20 16 15 12 11 10 9 5 4 0 | |
3404 | * +----+----+---+-----------------+------+------+-----+------+------+ | |
3405 | * | sf | op | S | 1 1 0 1 0 1 0 0 | Rm | cond | op2 | Rn | Rd | | |
3406 | * +----+----+---+-----------------+------+------+-----+------+------+ | |
3407 | */ | |
ad7ee8a2 CF |
3408 | static void disas_cond_select(DisasContext *s, uint32_t insn) |
3409 | { | |
e952d8c7 CF |
3410 | unsigned int sf, else_inv, rm, cond, else_inc, rn, rd; |
3411 | TCGv_i64 tcg_rd, tcg_src; | |
3412 | ||
3413 | if (extract32(insn, 29, 1) || extract32(insn, 11, 1)) { | |
3414 | /* S == 1 or op2<1> == 1 */ | |
3415 | unallocated_encoding(s); | |
3416 | return; | |
3417 | } | |
3418 | sf = extract32(insn, 31, 1); | |
3419 | else_inv = extract32(insn, 30, 1); | |
3420 | rm = extract32(insn, 16, 5); | |
3421 | cond = extract32(insn, 12, 4); | |
3422 | else_inc = extract32(insn, 10, 1); | |
3423 | rn = extract32(insn, 5, 5); | |
3424 | rd = extract32(insn, 0, 5); | |
3425 | ||
3426 | if (rd == 31) { | |
3427 | /* silly no-op write; until we use movcond we must special-case | |
3428 | * this to avoid a dead temporary across basic blocks. | |
3429 | */ | |
3430 | return; | |
3431 | } | |
3432 | ||
3433 | tcg_rd = cpu_reg(s, rd); | |
3434 | ||
3435 | if (cond >= 0x0e) { /* condition "always" */ | |
3436 | tcg_src = read_cpu_reg(s, rn, sf); | |
3437 | tcg_gen_mov_i64(tcg_rd, tcg_src); | |
3438 | } else { | |
3439 | /* OPTME: we could use movcond here, at the cost of duplicating | |
3440 | * a lot of the arm_gen_test_cc() logic. | |
3441 | */ | |
3442 | int label_match = gen_new_label(); | |
3443 | int label_continue = gen_new_label(); | |
3444 | ||
3445 | arm_gen_test_cc(cond, label_match); | |
3446 | /* nomatch: */ | |
3447 | tcg_src = cpu_reg(s, rm); | |
3448 | ||
3449 | if (else_inv && else_inc) { | |
3450 | tcg_gen_neg_i64(tcg_rd, tcg_src); | |
3451 | } else if (else_inv) { | |
3452 | tcg_gen_not_i64(tcg_rd, tcg_src); | |
3453 | } else if (else_inc) { | |
3454 | tcg_gen_addi_i64(tcg_rd, tcg_src, 1); | |
3455 | } else { | |
3456 | tcg_gen_mov_i64(tcg_rd, tcg_src); | |
3457 | } | |
3458 | if (!sf) { | |
3459 | tcg_gen_ext32u_i64(tcg_rd, tcg_rd); | |
3460 | } | |
3461 | tcg_gen_br(label_continue); | |
3462 | /* match: */ | |
3463 | gen_set_label(label_match); | |
3464 | tcg_src = read_cpu_reg(s, rn, sf); | |
3465 | tcg_gen_mov_i64(tcg_rd, tcg_src); | |
3466 | /* continue: */ | |
3467 | gen_set_label(label_continue); | |
3468 | } | |
ad7ee8a2 CF |
3469 | } |
3470 | ||
680ead21 CF |
3471 | static void handle_clz(DisasContext *s, unsigned int sf, |
3472 | unsigned int rn, unsigned int rd) | |
3473 | { | |
3474 | TCGv_i64 tcg_rd, tcg_rn; | |
3475 | tcg_rd = cpu_reg(s, rd); | |
3476 | tcg_rn = cpu_reg(s, rn); | |
3477 | ||
3478 | if (sf) { | |
3479 | gen_helper_clz64(tcg_rd, tcg_rn); | |
3480 | } else { | |
3481 | TCGv_i32 tcg_tmp32 = tcg_temp_new_i32(); | |
3482 | tcg_gen_trunc_i64_i32(tcg_tmp32, tcg_rn); | |
3483 | gen_helper_clz(tcg_tmp32, tcg_tmp32); | |
3484 | tcg_gen_extu_i32_i64(tcg_rd, tcg_tmp32); | |
3485 | tcg_temp_free_i32(tcg_tmp32); | |
3486 | } | |
3487 | } | |
3488 | ||
e80c5020 CF |
3489 | static void handle_cls(DisasContext *s, unsigned int sf, |
3490 | unsigned int rn, unsigned int rd) | |
3491 | { | |
3492 | TCGv_i64 tcg_rd, tcg_rn; | |
3493 | tcg_rd = cpu_reg(s, rd); | |
3494 | tcg_rn = cpu_reg(s, rn); | |
3495 | ||
3496 | if (sf) { | |
3497 | gen_helper_cls64(tcg_rd, tcg_rn); | |
3498 | } else { | |
3499 | TCGv_i32 tcg_tmp32 = tcg_temp_new_i32(); | |
3500 | tcg_gen_trunc_i64_i32(tcg_tmp32, tcg_rn); | |
3501 | gen_helper_cls32(tcg_tmp32, tcg_tmp32); | |
3502 | tcg_gen_extu_i32_i64(tcg_rd, tcg_tmp32); | |
3503 | tcg_temp_free_i32(tcg_tmp32); | |
3504 | } | |
3505 | } | |
3506 | ||
82e14b02 AG |
3507 | static void handle_rbit(DisasContext *s, unsigned int sf, |
3508 | unsigned int rn, unsigned int rd) | |
3509 | { | |
3510 | TCGv_i64 tcg_rd, tcg_rn; | |
3511 | tcg_rd = cpu_reg(s, rd); | |
3512 | tcg_rn = cpu_reg(s, rn); | |
3513 | ||
3514 | if (sf) { | |
3515 | gen_helper_rbit64(tcg_rd, tcg_rn); | |
3516 | } else { | |
3517 | TCGv_i32 tcg_tmp32 = tcg_temp_new_i32(); | |
3518 | tcg_gen_trunc_i64_i32(tcg_tmp32, tcg_rn); | |
3519 | gen_helper_rbit(tcg_tmp32, tcg_tmp32); | |
3520 | tcg_gen_extu_i32_i64(tcg_rd, tcg_tmp32); | |
3521 | tcg_temp_free_i32(tcg_tmp32); | |
3522 | } | |
3523 | } | |
3524 | ||
45323209 CF |
3525 | /* C5.6.149 REV with sf==1, opcode==3 ("REV64") */ |
3526 | static void handle_rev64(DisasContext *s, unsigned int sf, | |
3527 | unsigned int rn, unsigned int rd) | |
3528 | { | |
3529 | if (!sf) { | |
3530 | unallocated_encoding(s); | |
3531 | return; | |
3532 | } | |
3533 | tcg_gen_bswap64_i64(cpu_reg(s, rd), cpu_reg(s, rn)); | |
3534 | } | |
3535 | ||
3536 | /* C5.6.149 REV with sf==0, opcode==2 | |
3537 | * C5.6.151 REV32 (sf==1, opcode==2) | |
3538 | */ | |
3539 | static void handle_rev32(DisasContext *s, unsigned int sf, | |
3540 | unsigned int rn, unsigned int rd) | |
3541 | { | |
3542 | TCGv_i64 tcg_rd = cpu_reg(s, rd); | |
3543 | ||
3544 | if (sf) { | |
3545 | TCGv_i64 tcg_tmp = tcg_temp_new_i64(); | |
3546 | TCGv_i64 tcg_rn = read_cpu_reg(s, rn, sf); | |
3547 | ||
3548 | /* bswap32_i64 requires zero high word */ | |
3549 | tcg_gen_ext32u_i64(tcg_tmp, tcg_rn); | |
3550 | tcg_gen_bswap32_i64(tcg_rd, tcg_tmp); | |
3551 | tcg_gen_shri_i64(tcg_tmp, tcg_rn, 32); | |
3552 | tcg_gen_bswap32_i64(tcg_tmp, tcg_tmp); | |
3553 | tcg_gen_concat32_i64(tcg_rd, tcg_rd, tcg_tmp); | |
3554 | ||
3555 | tcg_temp_free_i64(tcg_tmp); | |
3556 | } else { | |
3557 | tcg_gen_ext32u_i64(tcg_rd, cpu_reg(s, rn)); | |
3558 | tcg_gen_bswap32_i64(tcg_rd, tcg_rd); | |
3559 | } | |
3560 | } | |
3561 | ||
3562 | /* C5.6.150 REV16 (opcode==1) */ | |
3563 | static void handle_rev16(DisasContext *s, unsigned int sf, | |
3564 | unsigned int rn, unsigned int rd) | |
3565 | { | |
3566 | TCGv_i64 tcg_rd = cpu_reg(s, rd); | |
3567 | TCGv_i64 tcg_tmp = tcg_temp_new_i64(); | |
3568 | TCGv_i64 tcg_rn = read_cpu_reg(s, rn, sf); | |
3569 | ||
3570 | tcg_gen_andi_i64(tcg_tmp, tcg_rn, 0xffff); | |
3571 | tcg_gen_bswap16_i64(tcg_rd, tcg_tmp); | |
3572 | ||
3573 | tcg_gen_shri_i64(tcg_tmp, tcg_rn, 16); | |
3574 | tcg_gen_andi_i64(tcg_tmp, tcg_tmp, 0xffff); | |
3575 | tcg_gen_bswap16_i64(tcg_tmp, tcg_tmp); | |
3576 | tcg_gen_deposit_i64(tcg_rd, tcg_rd, tcg_tmp, 16, 16); | |
3577 | ||
3578 | if (sf) { | |
3579 | tcg_gen_shri_i64(tcg_tmp, tcg_rn, 32); | |
3580 | tcg_gen_andi_i64(tcg_tmp, tcg_tmp, 0xffff); | |
3581 | tcg_gen_bswap16_i64(tcg_tmp, tcg_tmp); | |
3582 | tcg_gen_deposit_i64(tcg_rd, tcg_rd, tcg_tmp, 32, 16); | |
3583 | ||
3584 | tcg_gen_shri_i64(tcg_tmp, tcg_rn, 48); | |
3585 | tcg_gen_bswap16_i64(tcg_tmp, tcg_tmp); | |
3586 | tcg_gen_deposit_i64(tcg_rd, tcg_rd, tcg_tmp, 48, 16); | |
3587 | } | |
3588 | ||
3589 | tcg_temp_free_i64(tcg_tmp); | |
3590 | } | |
3591 | ||
680ead21 CF |
3592 | /* C3.5.7 Data-processing (1 source) |
3593 | * 31 30 29 28 21 20 16 15 10 9 5 4 0 | |
3594 | * +----+---+---+-----------------+---------+--------+------+------+ | |
3595 | * | sf | 1 | S | 1 1 0 1 0 1 1 0 | opcode2 | opcode | Rn | Rd | | |
3596 | * +----+---+---+-----------------+---------+--------+------+------+ | |
3597 | */ | |
ad7ee8a2 CF |
3598 | static void disas_data_proc_1src(DisasContext *s, uint32_t insn) |
3599 | { | |
680ead21 CF |
3600 | unsigned int sf, opcode, rn, rd; |
3601 | ||
3602 | if (extract32(insn, 29, 1) || extract32(insn, 16, 5)) { | |
3603 | unallocated_encoding(s); | |
3604 | return; | |
3605 | } | |
3606 | ||
3607 | sf = extract32(insn, 31, 1); | |
3608 | opcode = extract32(insn, 10, 6); | |
3609 | rn = extract32(insn, 5, 5); | |
3610 | rd = extract32(insn, 0, 5); | |
3611 | ||
3612 | switch (opcode) { | |
3613 | case 0: /* RBIT */ | |
82e14b02 AG |
3614 | handle_rbit(s, sf, rn, rd); |
3615 | break; | |
680ead21 | 3616 | case 1: /* REV16 */ |
45323209 CF |
3617 | handle_rev16(s, sf, rn, rd); |
3618 | break; | |
680ead21 | 3619 | case 2: /* REV32 */ |
45323209 CF |
3620 | handle_rev32(s, sf, rn, rd); |
3621 | break; | |
680ead21 | 3622 | case 3: /* REV64 */ |
45323209 | 3623 | handle_rev64(s, sf, rn, rd); |
680ead21 CF |
3624 | break; |
3625 | case 4: /* CLZ */ | |
3626 | handle_clz(s, sf, rn, rd); | |
3627 | break; | |
3628 | case 5: /* CLS */ | |
e80c5020 | 3629 | handle_cls(s, sf, rn, rd); |
680ead21 CF |
3630 | break; |
3631 | } | |
ad7ee8a2 CF |
3632 | } |
3633 | ||
8220e911 AG |
3634 | static void handle_div(DisasContext *s, bool is_signed, unsigned int sf, |
3635 | unsigned int rm, unsigned int rn, unsigned int rd) | |
3636 | { | |
3637 | TCGv_i64 tcg_n, tcg_m, tcg_rd; | |
3638 | tcg_rd = cpu_reg(s, rd); | |
3639 | ||
3640 | if (!sf && is_signed) { | |
3641 | tcg_n = new_tmp_a64(s); | |
3642 | tcg_m = new_tmp_a64(s); | |
3643 | tcg_gen_ext32s_i64(tcg_n, cpu_reg(s, rn)); | |
3644 | tcg_gen_ext32s_i64(tcg_m, cpu_reg(s, rm)); | |
3645 | } else { | |
3646 | tcg_n = read_cpu_reg(s, rn, sf); | |
3647 | tcg_m = read_cpu_reg(s, rm, sf); | |
3648 | } | |
3649 | ||
3650 | if (is_signed) { | |
3651 | gen_helper_sdiv64(tcg_rd, tcg_n, tcg_m); | |
3652 | } else { | |
3653 | gen_helper_udiv64(tcg_rd, tcg_n, tcg_m); | |
3654 | } | |
3655 | ||
3656 | if (!sf) { /* zero extend final result */ | |
3657 | tcg_gen_ext32u_i64(tcg_rd, tcg_rd); | |
3658 | } | |
3659 | } | |
3660 | ||
6c1adc91 AG |
3661 | /* C5.6.115 LSLV, C5.6.118 LSRV, C5.6.17 ASRV, C5.6.154 RORV */ |
3662 | static void handle_shift_reg(DisasContext *s, | |
3663 | enum a64_shift_type shift_type, unsigned int sf, | |
3664 | unsigned int rm, unsigned int rn, unsigned int rd) | |
3665 | { | |
3666 | TCGv_i64 tcg_shift = tcg_temp_new_i64(); | |
3667 | TCGv_i64 tcg_rd = cpu_reg(s, rd); | |
3668 | TCGv_i64 tcg_rn = read_cpu_reg(s, rn, sf); | |
3669 | ||
3670 | tcg_gen_andi_i64(tcg_shift, cpu_reg(s, rm), sf ? 63 : 31); | |
3671 | shift_reg(tcg_rd, tcg_rn, sf, shift_type, tcg_shift); | |
3672 | tcg_temp_free_i64(tcg_shift); | |
3673 | } | |
3674 | ||
8220e911 AG |
3675 | /* C3.5.8 Data-processing (2 source) |
3676 | * 31 30 29 28 21 20 16 15 10 9 5 4 0 | |
3677 | * +----+---+---+-----------------+------+--------+------+------+ | |
3678 | * | sf | 0 | S | 1 1 0 1 0 1 1 0 | Rm | opcode | Rn | Rd | | |
3679 | * +----+---+---+-----------------+------+--------+------+------+ | |
3680 | */ | |
ad7ee8a2 CF |
3681 | static void disas_data_proc_2src(DisasContext *s, uint32_t insn) |
3682 | { | |
8220e911 AG |
3683 | unsigned int sf, rm, opcode, rn, rd; |
3684 | sf = extract32(insn, 31, 1); | |
3685 | rm = extract32(insn, 16, 5); | |
3686 | opcode = extract32(insn, 10, 6); | |
3687 | rn = extract32(insn, 5, 5); | |
3688 | rd = extract32(insn, 0, 5); | |
3689 | ||
3690 | if (extract32(insn, 29, 1)) { | |
3691 | unallocated_encoding(s); | |
3692 | return; | |
3693 | } | |
3694 | ||
3695 | switch (opcode) { | |
3696 | case 2: /* UDIV */ | |
3697 | handle_div(s, false, sf, rm, rn, rd); | |
3698 | break; | |
3699 | case 3: /* SDIV */ | |
3700 | handle_div(s, true, sf, rm, rn, rd); | |
3701 | break; | |
3702 | case 8: /* LSLV */ | |
6c1adc91 AG |
3703 | handle_shift_reg(s, A64_SHIFT_TYPE_LSL, sf, rm, rn, rd); |
3704 | break; | |
8220e911 | 3705 | case 9: /* LSRV */ |
6c1adc91 AG |
3706 | handle_shift_reg(s, A64_SHIFT_TYPE_LSR, sf, rm, rn, rd); |
3707 | break; | |
8220e911 | 3708 | case 10: /* ASRV */ |
6c1adc91 AG |
3709 | handle_shift_reg(s, A64_SHIFT_TYPE_ASR, sf, rm, rn, rd); |
3710 | break; | |
8220e911 | 3711 | case 11: /* RORV */ |
6c1adc91 AG |
3712 | handle_shift_reg(s, A64_SHIFT_TYPE_ROR, sf, rm, rn, rd); |
3713 | break; | |
8220e911 AG |
3714 | case 16: |
3715 | case 17: | |
3716 | case 18: | |
3717 | case 19: | |
3718 | case 20: | |
3719 | case 21: | |
3720 | case 22: | |
3721 | case 23: /* CRC32 */ | |
3722 | unsupported_encoding(s, insn); | |
3723 | break; | |
3724 | default: | |
3725 | unallocated_encoding(s); | |
3726 | break; | |
3727 | } | |
ad7ee8a2 CF |
3728 | } |
3729 | ||
3730 | /* C3.5 Data processing - register */ | |
3731 | static void disas_data_proc_reg(DisasContext *s, uint32_t insn) | |
3732 | { | |
3733 | switch (extract32(insn, 24, 5)) { | |
3734 | case 0x0a: /* Logical (shifted register) */ | |
3735 | disas_logic_reg(s, insn); | |
3736 | break; | |
3737 | case 0x0b: /* Add/subtract */ | |
3738 | if (insn & (1 << 21)) { /* (extended register) */ | |
3739 | disas_add_sub_ext_reg(s, insn); | |
3740 | } else { | |
3741 | disas_add_sub_reg(s, insn); | |
3742 | } | |
3743 | break; | |
3744 | case 0x1b: /* Data-processing (3 source) */ | |
3745 | disas_data_proc_3src(s, insn); | |
3746 | break; | |
3747 | case 0x1a: | |
3748 | switch (extract32(insn, 21, 3)) { | |
3749 | case 0x0: /* Add/subtract (with carry) */ | |
3750 | disas_adc_sbc(s, insn); | |
3751 | break; | |
3752 | case 0x2: /* Conditional compare */ | |
750813cf | 3753 | disas_cc(s, insn); /* both imm and reg forms */ |
ad7ee8a2 CF |
3754 | break; |
3755 | case 0x4: /* Conditional select */ | |
3756 | disas_cond_select(s, insn); | |
3757 | break; | |
3758 | case 0x6: /* Data-processing */ | |
3759 | if (insn & (1 << 30)) { /* (1 source) */ | |
3760 | disas_data_proc_1src(s, insn); | |
3761 | } else { /* (2 source) */ | |
3762 | disas_data_proc_2src(s, insn); | |
3763 | } | |
3764 | break; | |
3765 | default: | |
3766 | unallocated_encoding(s); | |
3767 | break; | |
3768 | } | |
3769 | break; | |
3770 | default: | |
3771 | unallocated_encoding(s); | |
3772 | break; | |
3773 | } | |
3774 | } | |
3775 | ||
da7dafe7 CF |
3776 | static void handle_fp_compare(DisasContext *s, bool is_double, |
3777 | unsigned int rn, unsigned int rm, | |
3778 | bool cmp_with_zero, bool signal_all_nans) | |
3779 | { | |
3780 | TCGv_i64 tcg_flags = tcg_temp_new_i64(); | |
3781 | TCGv_ptr fpst = get_fpstatus_ptr(); | |
3782 | ||
3783 | if (is_double) { | |
3784 | TCGv_i64 tcg_vn, tcg_vm; | |
3785 | ||
3786 | tcg_vn = read_fp_dreg(s, rn); | |
3787 | if (cmp_with_zero) { | |
3788 | tcg_vm = tcg_const_i64(0); | |
3789 | } else { | |
3790 | tcg_vm = read_fp_dreg(s, rm); | |
3791 | } | |
3792 | if (signal_all_nans) { | |
3793 | gen_helper_vfp_cmped_a64(tcg_flags, tcg_vn, tcg_vm, fpst); | |
3794 | } else { | |
3795 | gen_helper_vfp_cmpd_a64(tcg_flags, tcg_vn, tcg_vm, fpst); | |
3796 | } | |
3797 | tcg_temp_free_i64(tcg_vn); | |
3798 | tcg_temp_free_i64(tcg_vm); | |
3799 | } else { | |
3800 | TCGv_i32 tcg_vn, tcg_vm; | |
3801 | ||
3802 | tcg_vn = read_fp_sreg(s, rn); | |
3803 | if (cmp_with_zero) { | |
3804 | tcg_vm = tcg_const_i32(0); | |
3805 | } else { | |
3806 | tcg_vm = read_fp_sreg(s, rm); | |
3807 | } | |
3808 | if (signal_all_nans) { | |
3809 | gen_helper_vfp_cmpes_a64(tcg_flags, tcg_vn, tcg_vm, fpst); | |
3810 | } else { | |
3811 | gen_helper_vfp_cmps_a64(tcg_flags, tcg_vn, tcg_vm, fpst); | |
3812 | } | |
3813 | tcg_temp_free_i32(tcg_vn); | |
3814 | tcg_temp_free_i32(tcg_vm); | |
3815 | } | |
3816 | ||
3817 | tcg_temp_free_ptr(fpst); | |
3818 | ||
3819 | gen_set_nzcv(tcg_flags); | |
3820 | ||
3821 | tcg_temp_free_i64(tcg_flags); | |
3822 | } | |
3823 | ||
faa0ba46 PM |
3824 | /* C3.6.22 Floating point compare |
3825 | * 31 30 29 28 24 23 22 21 20 16 15 14 13 10 9 5 4 0 | |
3826 | * +---+---+---+-----------+------+---+------+-----+---------+------+-------+ | |
3827 | * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | op | 1 0 0 0 | Rn | op2 | | |
3828 | * +---+---+---+-----------+------+---+------+-----+---------+------+-------+ | |
3829 | */ | |
3830 | static void disas_fp_compare(DisasContext *s, uint32_t insn) | |
3831 | { | |
da7dafe7 CF |
3832 | unsigned int mos, type, rm, op, rn, opc, op2r; |
3833 | ||
3834 | mos = extract32(insn, 29, 3); | |
3835 | type = extract32(insn, 22, 2); /* 0 = single, 1 = double */ | |
3836 | rm = extract32(insn, 16, 5); | |
3837 | op = extract32(insn, 14, 2); | |
3838 | rn = extract32(insn, 5, 5); | |
3839 | opc = extract32(insn, 3, 2); | |
3840 | op2r = extract32(insn, 0, 3); | |
3841 | ||
3842 | if (mos || op || op2r || type > 1) { | |
3843 | unallocated_encoding(s); | |
3844 | return; | |
3845 | } | |
3846 | ||
3847 | handle_fp_compare(s, type, rn, rm, opc & 1, opc & 2); | |
faa0ba46 PM |
3848 | } |
3849 | ||
3850 | /* C3.6.23 Floating point conditional compare | |
3851 | * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 3 0 | |
3852 | * +---+---+---+-----------+------+---+------+------+-----+------+----+------+ | |
3853 | * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | cond | 0 1 | Rn | op | nzcv | | |
3854 | * +---+---+---+-----------+------+---+------+------+-----+------+----+------+ | |
3855 | */ | |
3856 | static void disas_fp_ccomp(DisasContext *s, uint32_t insn) | |
3857 | { | |
513f1d76 CF |
3858 | unsigned int mos, type, rm, cond, rn, op, nzcv; |
3859 | TCGv_i64 tcg_flags; | |
3860 | int label_continue = -1; | |
3861 | ||
3862 | mos = extract32(insn, 29, 3); | |
3863 | type = extract32(insn, 22, 2); /* 0 = single, 1 = double */ | |
3864 | rm = extract32(insn, 16, 5); | |
3865 | cond = extract32(insn, 12, 4); | |
3866 | rn = extract32(insn, 5, 5); | |
3867 | op = extract32(insn, 4, 1); | |
3868 | nzcv = extract32(insn, 0, 4); | |
3869 | ||
3870 | if (mos || type > 1) { | |
3871 | unallocated_encoding(s); | |
3872 | return; | |
3873 | } | |
3874 | ||
3875 | if (cond < 0x0e) { /* not always */ | |
3876 | int label_match = gen_new_label(); | |
3877 | label_continue = gen_new_label(); | |
3878 | arm_gen_test_cc(cond, label_match); | |
3879 | /* nomatch: */ | |
3880 | tcg_flags = tcg_const_i64(nzcv << 28); | |
3881 | gen_set_nzcv(tcg_flags); | |
3882 | tcg_temp_free_i64(tcg_flags); | |
3883 | tcg_gen_br(label_continue); | |
3884 | gen_set_label(label_match); | |
3885 | } | |
3886 | ||
3887 | handle_fp_compare(s, type, rn, rm, false, op); | |
3888 | ||
3889 | if (cond < 0x0e) { | |
3890 | gen_set_label(label_continue); | |
3891 | } | |
faa0ba46 PM |
3892 | } |
3893 | ||
5640ff62 CF |
3894 | /* copy src FP register to dst FP register; type specifies single or double */ |
3895 | static void gen_mov_fp2fp(DisasContext *s, int type, int dst, int src) | |
3896 | { | |
3897 | if (type) { | |
3898 | TCGv_i64 v = read_fp_dreg(s, src); | |
3899 | write_fp_dreg(s, dst, v); | |
3900 | tcg_temp_free_i64(v); | |
3901 | } else { | |
3902 | TCGv_i32 v = read_fp_sreg(s, src); | |
3903 | write_fp_sreg(s, dst, v); | |
3904 | tcg_temp_free_i32(v); | |
3905 | } | |
3906 | } | |
3907 | ||
faa0ba46 PM |
3908 | /* C3.6.24 Floating point conditional select |
3909 | * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0 | |
3910 | * +---+---+---+-----------+------+---+------+------+-----+------+------+ | |
3911 | * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | cond | 1 1 | Rn | Rd | | |
3912 | * +---+---+---+-----------+------+---+------+------+-----+------+------+ | |
3913 | */ | |
3914 | static void disas_fp_csel(DisasContext *s, uint32_t insn) | |
3915 | { | |
5640ff62 CF |
3916 | unsigned int mos, type, rm, cond, rn, rd; |
3917 | int label_continue = -1; | |
3918 | ||
3919 | mos = extract32(insn, 29, 3); | |
3920 | type = extract32(insn, 22, 2); /* 0 = single, 1 = double */ | |
3921 | rm = extract32(insn, 16, 5); | |
3922 | cond = extract32(insn, 12, 4); | |
3923 | rn = extract32(insn, 5, 5); | |
3924 | rd = extract32(insn, 0, 5); | |
3925 | ||
3926 | if (mos || type > 1) { | |
3927 | unallocated_encoding(s); | |
3928 | return; | |
3929 | } | |
3930 | ||
3931 | if (cond < 0x0e) { /* not always */ | |
3932 | int label_match = gen_new_label(); | |
3933 | label_continue = gen_new_label(); | |
3934 | arm_gen_test_cc(cond, label_match); | |
3935 | /* nomatch: */ | |
3936 | gen_mov_fp2fp(s, type, rd, rm); | |
3937 | tcg_gen_br(label_continue); | |
3938 | gen_set_label(label_match); | |
3939 | } | |
3940 | ||
3941 | gen_mov_fp2fp(s, type, rd, rn); | |
3942 | ||
3943 | if (cond < 0x0e) { /* continue */ | |
3944 | gen_set_label(label_continue); | |
3945 | } | |
faa0ba46 PM |
3946 | } |
3947 | ||
d9b0848d PM |
3948 | /* C3.6.25 Floating-point data-processing (1 source) - single precision */ |
3949 | static void handle_fp_1src_single(DisasContext *s, int opcode, int rd, int rn) | |
3950 | { | |
3951 | TCGv_ptr fpst; | |
3952 | TCGv_i32 tcg_op; | |
3953 | TCGv_i32 tcg_res; | |
3954 | ||
3955 | fpst = get_fpstatus_ptr(); | |
3956 | tcg_op = read_fp_sreg(s, rn); | |
3957 | tcg_res = tcg_temp_new_i32(); | |
3958 | ||
3959 | switch (opcode) { | |
3960 | case 0x0: /* FMOV */ | |
3961 | tcg_gen_mov_i32(tcg_res, tcg_op); | |
3962 | break; | |
3963 | case 0x1: /* FABS */ | |
3964 | gen_helper_vfp_abss(tcg_res, tcg_op); | |
3965 | break; | |
3966 | case 0x2: /* FNEG */ | |
3967 | gen_helper_vfp_negs(tcg_res, tcg_op); | |
3968 | break; | |
3969 | case 0x3: /* FSQRT */ | |
3970 | gen_helper_vfp_sqrts(tcg_res, tcg_op, cpu_env); | |
3971 | break; | |
3972 | case 0x8: /* FRINTN */ | |
3973 | case 0x9: /* FRINTP */ | |
3974 | case 0xa: /* FRINTM */ | |
3975 | case 0xb: /* FRINTZ */ | |
3976 | case 0xc: /* FRINTA */ | |
3977 | { | |
3978 | TCGv_i32 tcg_rmode = tcg_const_i32(arm_rmode_to_sf(opcode & 7)); | |
3979 | ||
3980 | gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env); | |
3981 | gen_helper_rints(tcg_res, tcg_op, fpst); | |
3982 | ||
3983 | gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env); | |
3984 | tcg_temp_free_i32(tcg_rmode); | |
3985 | break; | |
3986 | } | |
3987 | case 0xe: /* FRINTX */ | |
3988 | gen_helper_rints_exact(tcg_res, tcg_op, fpst); | |
3989 | break; | |
3990 | case 0xf: /* FRINTI */ | |
3991 | gen_helper_rints(tcg_res, tcg_op, fpst); | |
3992 | break; | |
3993 | default: | |
3994 | abort(); | |
3995 | } | |
3996 | ||
3997 | write_fp_sreg(s, rd, tcg_res); | |
3998 | ||
3999 | tcg_temp_free_ptr(fpst); | |
4000 | tcg_temp_free_i32(tcg_op); | |
4001 | tcg_temp_free_i32(tcg_res); | |
4002 | } | |
4003 | ||
4004 | /* C3.6.25 Floating-point data-processing (1 source) - double precision */ | |
4005 | static void handle_fp_1src_double(DisasContext *s, int opcode, int rd, int rn) | |
4006 | { | |
4007 | TCGv_ptr fpst; | |
4008 | TCGv_i64 tcg_op; | |
4009 | TCGv_i64 tcg_res; | |
4010 | ||
4011 | fpst = get_fpstatus_ptr(); | |
4012 | tcg_op = read_fp_dreg(s, rn); | |
4013 | tcg_res = tcg_temp_new_i64(); | |
4014 | ||
4015 | switch (opcode) { | |
4016 | case 0x0: /* FMOV */ | |
4017 | tcg_gen_mov_i64(tcg_res, tcg_op); | |
4018 | break; | |
4019 | case 0x1: /* FABS */ | |
4020 | gen_helper_vfp_absd(tcg_res, tcg_op); | |
4021 | break; | |
4022 | case 0x2: /* FNEG */ | |
4023 | gen_helper_vfp_negd(tcg_res, tcg_op); | |
4024 | break; | |
4025 | case 0x3: /* FSQRT */ | |
4026 | gen_helper_vfp_sqrtd(tcg_res, tcg_op, cpu_env); | |
4027 | break; | |
4028 | case 0x8: /* FRINTN */ | |
4029 | case 0x9: /* FRINTP */ | |
4030 | case 0xa: /* FRINTM */ | |
4031 | case 0xb: /* FRINTZ */ | |
4032 | case 0xc: /* FRINTA */ | |
4033 | { | |
4034 | TCGv_i32 tcg_rmode = tcg_const_i32(arm_rmode_to_sf(opcode & 7)); | |
4035 | ||
4036 | gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env); | |
4037 | gen_helper_rintd(tcg_res, tcg_op, fpst); | |
4038 | ||
4039 | gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env); | |
4040 | tcg_temp_free_i32(tcg_rmode); | |
4041 | break; | |
4042 | } | |
4043 | case 0xe: /* FRINTX */ | |
4044 | gen_helper_rintd_exact(tcg_res, tcg_op, fpst); | |
4045 | break; | |
4046 | case 0xf: /* FRINTI */ | |
4047 | gen_helper_rintd(tcg_res, tcg_op, fpst); | |
4048 | break; | |
4049 | default: | |
4050 | abort(); | |
4051 | } | |
4052 | ||
4053 | write_fp_dreg(s, rd, tcg_res); | |
4054 | ||
4055 | tcg_temp_free_ptr(fpst); | |
4056 | tcg_temp_free_i64(tcg_op); | |
4057 | tcg_temp_free_i64(tcg_res); | |
4058 | } | |
4059 | ||
8900aad2 PM |
4060 | static void handle_fp_fcvt(DisasContext *s, int opcode, |
4061 | int rd, int rn, int dtype, int ntype) | |
4062 | { | |
4063 | switch (ntype) { | |
4064 | case 0x0: | |
4065 | { | |
4066 | TCGv_i32 tcg_rn = read_fp_sreg(s, rn); | |
4067 | if (dtype == 1) { | |
4068 | /* Single to double */ | |
4069 | TCGv_i64 tcg_rd = tcg_temp_new_i64(); | |
4070 | gen_helper_vfp_fcvtds(tcg_rd, tcg_rn, cpu_env); | |
4071 | write_fp_dreg(s, rd, tcg_rd); | |
4072 | tcg_temp_free_i64(tcg_rd); | |
4073 | } else { | |
4074 | /* Single to half */ | |
4075 | TCGv_i32 tcg_rd = tcg_temp_new_i32(); | |
4076 | gen_helper_vfp_fcvt_f32_to_f16(tcg_rd, tcg_rn, cpu_env); | |
4077 | /* write_fp_sreg is OK here because top half of tcg_rd is zero */ | |
4078 | write_fp_sreg(s, rd, tcg_rd); | |
4079 | tcg_temp_free_i32(tcg_rd); | |
4080 | } | |
4081 | tcg_temp_free_i32(tcg_rn); | |
4082 | break; | |
4083 | } | |
4084 | case 0x1: | |
4085 | { | |
4086 | TCGv_i64 tcg_rn = read_fp_dreg(s, rn); | |
4087 | TCGv_i32 tcg_rd = tcg_temp_new_i32(); | |
4088 | if (dtype == 0) { | |
4089 | /* Double to single */ | |
4090 | gen_helper_vfp_fcvtsd(tcg_rd, tcg_rn, cpu_env); | |
4091 | } else { | |
4092 | /* Double to half */ | |
4093 | gen_helper_vfp_fcvt_f64_to_f16(tcg_rd, tcg_rn, cpu_env); | |
4094 | /* write_fp_sreg is OK here because top half of tcg_rd is zero */ | |
4095 | } | |
4096 | write_fp_sreg(s, rd, tcg_rd); | |
4097 | tcg_temp_free_i32(tcg_rd); | |
4098 | tcg_temp_free_i64(tcg_rn); | |
4099 | break; | |
4100 | } | |
4101 | case 0x3: | |
4102 | { | |
4103 | TCGv_i32 tcg_rn = read_fp_sreg(s, rn); | |
4104 | tcg_gen_ext16u_i32(tcg_rn, tcg_rn); | |
4105 | if (dtype == 0) { | |
4106 | /* Half to single */ | |
4107 | TCGv_i32 tcg_rd = tcg_temp_new_i32(); | |
4108 | gen_helper_vfp_fcvt_f16_to_f32(tcg_rd, tcg_rn, cpu_env); | |
4109 | write_fp_sreg(s, rd, tcg_rd); | |
4110 | tcg_temp_free_i32(tcg_rd); | |
4111 | } else { | |
4112 | /* Half to double */ | |
4113 | TCGv_i64 tcg_rd = tcg_temp_new_i64(); | |
4114 | gen_helper_vfp_fcvt_f16_to_f64(tcg_rd, tcg_rn, cpu_env); | |
4115 | write_fp_dreg(s, rd, tcg_rd); | |
4116 | tcg_temp_free_i64(tcg_rd); | |
4117 | } | |
4118 | tcg_temp_free_i32(tcg_rn); | |
4119 | break; | |
4120 | } | |
4121 | default: | |
4122 | abort(); | |
4123 | } | |
4124 | } | |
4125 | ||
faa0ba46 PM |
4126 | /* C3.6.25 Floating point data-processing (1 source) |
4127 | * 31 30 29 28 24 23 22 21 20 15 14 10 9 5 4 0 | |
4128 | * +---+---+---+-----------+------+---+--------+-----------+------+------+ | |
4129 | * | M | 0 | S | 1 1 1 1 0 | type | 1 | opcode | 1 0 0 0 0 | Rn | Rd | | |
4130 | * +---+---+---+-----------+------+---+--------+-----------+------+------+ | |
4131 | */ | |
4132 | static void disas_fp_1src(DisasContext *s, uint32_t insn) | |
4133 | { | |
d9b0848d PM |
4134 | int type = extract32(insn, 22, 2); |
4135 | int opcode = extract32(insn, 15, 6); | |
4136 | int rn = extract32(insn, 5, 5); | |
4137 | int rd = extract32(insn, 0, 5); | |
4138 | ||
4139 | switch (opcode) { | |
4140 | case 0x4: case 0x5: case 0x7: | |
8900aad2 | 4141 | { |
d9b0848d | 4142 | /* FCVT between half, single and double precision */ |
8900aad2 PM |
4143 | int dtype = extract32(opcode, 0, 2); |
4144 | if (type == 2 || dtype == type) { | |
4145 | unallocated_encoding(s); | |
4146 | return; | |
4147 | } | |
4148 | handle_fp_fcvt(s, opcode, rd, rn, dtype, type); | |
d9b0848d | 4149 | break; |
8900aad2 | 4150 | } |
d9b0848d PM |
4151 | case 0x0 ... 0x3: |
4152 | case 0x8 ... 0xc: | |
4153 | case 0xe ... 0xf: | |
4154 | /* 32-to-32 and 64-to-64 ops */ | |
4155 | switch (type) { | |
4156 | case 0: | |
4157 | handle_fp_1src_single(s, opcode, rd, rn); | |
4158 | break; | |
4159 | case 1: | |
4160 | handle_fp_1src_double(s, opcode, rd, rn); | |
4161 | break; | |
4162 | default: | |
4163 | unallocated_encoding(s); | |
4164 | } | |
4165 | break; | |
4166 | default: | |
4167 | unallocated_encoding(s); | |
4168 | break; | |
4169 | } | |
faa0ba46 PM |
4170 | } |
4171 | ||
ec73d2e0 AG |
4172 | /* C3.6.26 Floating-point data-processing (2 source) - single precision */ |
4173 | static void handle_fp_2src_single(DisasContext *s, int opcode, | |
4174 | int rd, int rn, int rm) | |
4175 | { | |
4176 | TCGv_i32 tcg_op1; | |
4177 | TCGv_i32 tcg_op2; | |
4178 | TCGv_i32 tcg_res; | |
4179 | TCGv_ptr fpst; | |
4180 | ||
4181 | tcg_res = tcg_temp_new_i32(); | |
4182 | fpst = get_fpstatus_ptr(); | |
4183 | tcg_op1 = read_fp_sreg(s, rn); | |
4184 | tcg_op2 = read_fp_sreg(s, rm); | |
4185 | ||
4186 | switch (opcode) { | |
4187 | case 0x0: /* FMUL */ | |
4188 | gen_helper_vfp_muls(tcg_res, tcg_op1, tcg_op2, fpst); | |
4189 | break; | |
4190 | case 0x1: /* FDIV */ | |
4191 | gen_helper_vfp_divs(tcg_res, tcg_op1, tcg_op2, fpst); | |
4192 | break; | |
4193 | case 0x2: /* FADD */ | |
4194 | gen_helper_vfp_adds(tcg_res, tcg_op1, tcg_op2, fpst); | |
4195 | break; | |
4196 | case 0x3: /* FSUB */ | |
4197 | gen_helper_vfp_subs(tcg_res, tcg_op1, tcg_op2, fpst); | |
4198 | break; | |
4199 | case 0x4: /* FMAX */ | |
4200 | gen_helper_vfp_maxs(tcg_res, tcg_op1, tcg_op2, fpst); | |
4201 | break; | |
4202 | case 0x5: /* FMIN */ | |
4203 | gen_helper_vfp_mins(tcg_res, tcg_op1, tcg_op2, fpst); | |
4204 | break; | |
4205 | case 0x6: /* FMAXNM */ | |
4206 | gen_helper_vfp_maxnums(tcg_res, tcg_op1, tcg_op2, fpst); | |
4207 | break; | |
4208 | case 0x7: /* FMINNM */ | |
4209 | gen_helper_vfp_minnums(tcg_res, tcg_op1, tcg_op2, fpst); | |
4210 | break; | |
4211 | case 0x8: /* FNMUL */ | |
4212 | gen_helper_vfp_muls(tcg_res, tcg_op1, tcg_op2, fpst); | |
4213 | gen_helper_vfp_negs(tcg_res, tcg_res); | |
4214 | break; | |
4215 | } | |
4216 | ||
4217 | write_fp_sreg(s, rd, tcg_res); | |
4218 | ||
4219 | tcg_temp_free_ptr(fpst); | |
4220 | tcg_temp_free_i32(tcg_op1); | |
4221 | tcg_temp_free_i32(tcg_op2); | |
4222 | tcg_temp_free_i32(tcg_res); | |
4223 | } | |
4224 | ||
4225 | /* C3.6.26 Floating-point data-processing (2 source) - double precision */ | |
4226 | static void handle_fp_2src_double(DisasContext *s, int opcode, | |
4227 | int rd, int rn, int rm) | |
4228 | { | |
4229 | TCGv_i64 tcg_op1; | |
4230 | TCGv_i64 tcg_op2; | |
4231 | TCGv_i64 tcg_res; | |
4232 | TCGv_ptr fpst; | |
4233 | ||
4234 | tcg_res = tcg_temp_new_i64(); | |
4235 | fpst = get_fpstatus_ptr(); | |
4236 | tcg_op1 = read_fp_dreg(s, rn); | |
4237 | tcg_op2 = read_fp_dreg(s, rm); | |
4238 | ||
4239 | switch (opcode) { | |
4240 | case 0x0: /* FMUL */ | |
4241 | gen_helper_vfp_muld(tcg_res, tcg_op1, tcg_op2, fpst); | |
4242 | break; | |
4243 | case 0x1: /* FDIV */ | |
4244 | gen_helper_vfp_divd(tcg_res, tcg_op1, tcg_op2, fpst); | |
4245 | break; | |
4246 | case 0x2: /* FADD */ | |
4247 | gen_helper_vfp_addd(tcg_res, tcg_op1, tcg_op2, fpst); | |
4248 | break; | |
4249 | case 0x3: /* FSUB */ | |
4250 | gen_helper_vfp_subd(tcg_res, tcg_op1, tcg_op2, fpst); | |
4251 | break; | |
4252 | case 0x4: /* FMAX */ | |
4253 | gen_helper_vfp_maxd(tcg_res, tcg_op1, tcg_op2, fpst); | |
4254 | break; | |
4255 | case 0x5: /* FMIN */ | |
4256 | gen_helper_vfp_mind(tcg_res, tcg_op1, tcg_op2, fpst); | |
4257 | break; | |
4258 | case 0x6: /* FMAXNM */ | |
4259 | gen_helper_vfp_maxnumd(tcg_res, tcg_op1, tcg_op2, fpst); | |
4260 | break; | |
4261 | case 0x7: /* FMINNM */ | |
4262 | gen_helper_vfp_minnumd(tcg_res, tcg_op1, tcg_op2, fpst); | |
4263 | break; | |
4264 | case 0x8: /* FNMUL */ | |
4265 | gen_helper_vfp_muld(tcg_res, tcg_op1, tcg_op2, fpst); | |
4266 | gen_helper_vfp_negd(tcg_res, tcg_res); | |
4267 | break; | |
4268 | } | |
4269 | ||
4270 | write_fp_dreg(s, rd, tcg_res); | |
4271 | ||
4272 | tcg_temp_free_ptr(fpst); | |
4273 | tcg_temp_free_i64(tcg_op1); | |
4274 | tcg_temp_free_i64(tcg_op2); | |
4275 | tcg_temp_free_i64(tcg_res); | |
4276 | } | |
4277 | ||
faa0ba46 PM |
4278 | /* C3.6.26 Floating point data-processing (2 source) |
4279 | * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0 | |
4280 | * +---+---+---+-----------+------+---+------+--------+-----+------+------+ | |
4281 | * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | opcode | 1 0 | Rn | Rd | | |
4282 | * +---+---+---+-----------+------+---+------+--------+-----+------+------+ | |
4283 | */ | |
4284 | static void disas_fp_2src(DisasContext *s, uint32_t insn) | |
4285 | { | |
ec73d2e0 AG |
4286 | int type = extract32(insn, 22, 2); |
4287 | int rd = extract32(insn, 0, 5); | |
4288 | int rn = extract32(insn, 5, 5); | |
4289 | int rm = extract32(insn, 16, 5); | |
4290 | int opcode = extract32(insn, 12, 4); | |
4291 | ||
4292 | if (opcode > 8) { | |
4293 | unallocated_encoding(s); | |
4294 | return; | |
4295 | } | |
4296 | ||
4297 | switch (type) { | |
4298 | case 0: | |
4299 | handle_fp_2src_single(s, opcode, rd, rn, rm); | |
4300 | break; | |
4301 | case 1: | |
4302 | handle_fp_2src_double(s, opcode, rd, rn, rm); | |
4303 | break; | |
4304 | default: | |
4305 | unallocated_encoding(s); | |
4306 | } | |
faa0ba46 PM |
4307 | } |
4308 | ||
6a30667f AG |
4309 | /* C3.6.27 Floating-point data-processing (3 source) - single precision */ |
4310 | static void handle_fp_3src_single(DisasContext *s, bool o0, bool o1, | |
4311 | int rd, int rn, int rm, int ra) | |
4312 | { | |
4313 | TCGv_i32 tcg_op1, tcg_op2, tcg_op3; | |
4314 | TCGv_i32 tcg_res = tcg_temp_new_i32(); | |
4315 | TCGv_ptr fpst = get_fpstatus_ptr(); | |
4316 | ||
4317 | tcg_op1 = read_fp_sreg(s, rn); | |
4318 | tcg_op2 = read_fp_sreg(s, rm); | |
4319 | tcg_op3 = read_fp_sreg(s, ra); | |
4320 | ||
4321 | /* These are fused multiply-add, and must be done as one | |
4322 | * floating point operation with no rounding between the | |
4323 | * multiplication and addition steps. | |
4324 | * NB that doing the negations here as separate steps is | |
4325 | * correct : an input NaN should come out with its sign bit | |
4326 | * flipped if it is a negated-input. | |
4327 | */ | |
4328 | if (o1 == true) { | |
4329 | gen_helper_vfp_negs(tcg_op3, tcg_op3); | |
4330 | } | |
4331 | ||
4332 | if (o0 != o1) { | |
4333 | gen_helper_vfp_negs(tcg_op1, tcg_op1); | |
4334 | } | |
4335 | ||
4336 | gen_helper_vfp_muladds(tcg_res, tcg_op1, tcg_op2, tcg_op3, fpst); | |
4337 | ||
4338 | write_fp_sreg(s, rd, tcg_res); | |
4339 | ||
4340 | tcg_temp_free_ptr(fpst); | |
4341 | tcg_temp_free_i32(tcg_op1); | |
4342 | tcg_temp_free_i32(tcg_op2); | |
4343 | tcg_temp_free_i32(tcg_op3); | |
4344 | tcg_temp_free_i32(tcg_res); | |
4345 | } | |
4346 | ||
4347 | /* C3.6.27 Floating-point data-processing (3 source) - double precision */ | |
4348 | static void handle_fp_3src_double(DisasContext *s, bool o0, bool o1, | |
4349 | int rd, int rn, int rm, int ra) | |
4350 | { | |
4351 | TCGv_i64 tcg_op1, tcg_op2, tcg_op3; | |
4352 | TCGv_i64 tcg_res = tcg_temp_new_i64(); | |
4353 | TCGv_ptr fpst = get_fpstatus_ptr(); | |
4354 | ||
4355 | tcg_op1 = read_fp_dreg(s, rn); | |
4356 | tcg_op2 = read_fp_dreg(s, rm); | |
4357 | tcg_op3 = read_fp_dreg(s, ra); | |
4358 | ||
4359 | /* These are fused multiply-add, and must be done as one | |
4360 | * floating point operation with no rounding between the | |
4361 | * multiplication and addition steps. | |
4362 | * NB that doing the negations here as separate steps is | |
4363 | * correct : an input NaN should come out with its sign bit | |
4364 | * flipped if it is a negated-input. | |
4365 | */ | |
4366 | if (o1 == true) { | |
4367 | gen_helper_vfp_negd(tcg_op3, tcg_op3); | |
4368 | } | |
4369 | ||
4370 | if (o0 != o1) { | |
4371 | gen_helper_vfp_negd(tcg_op1, tcg_op1); | |
4372 | } | |
4373 | ||
4374 | gen_helper_vfp_muladdd(tcg_res, tcg_op1, tcg_op2, tcg_op3, fpst); | |
4375 | ||
4376 | write_fp_dreg(s, rd, tcg_res); | |
4377 | ||
4378 | tcg_temp_free_ptr(fpst); | |
4379 | tcg_temp_free_i64(tcg_op1); | |
4380 | tcg_temp_free_i64(tcg_op2); | |
4381 | tcg_temp_free_i64(tcg_op3); | |
4382 | tcg_temp_free_i64(tcg_res); | |
4383 | } | |
4384 | ||
faa0ba46 PM |
4385 | /* C3.6.27 Floating point data-processing (3 source) |
4386 | * 31 30 29 28 24 23 22 21 20 16 15 14 10 9 5 4 0 | |
4387 | * +---+---+---+-----------+------+----+------+----+------+------+------+ | |
4388 | * | M | 0 | S | 1 1 1 1 1 | type | o1 | Rm | o0 | Ra | Rn | Rd | | |
4389 | * +---+---+---+-----------+------+----+------+----+------+------+------+ | |
4390 | */ | |
4391 | static void disas_fp_3src(DisasContext *s, uint32_t insn) | |
4392 | { | |
6a30667f AG |
4393 | int type = extract32(insn, 22, 2); |
4394 | int rd = extract32(insn, 0, 5); | |
4395 | int rn = extract32(insn, 5, 5); | |
4396 | int ra = extract32(insn, 10, 5); | |
4397 | int rm = extract32(insn, 16, 5); | |
4398 | bool o0 = extract32(insn, 15, 1); | |
4399 | bool o1 = extract32(insn, 21, 1); | |
4400 | ||
4401 | switch (type) { | |
4402 | case 0: | |
4403 | handle_fp_3src_single(s, o0, o1, rd, rn, rm, ra); | |
4404 | break; | |
4405 | case 1: | |
4406 | handle_fp_3src_double(s, o0, o1, rd, rn, rm, ra); | |
4407 | break; | |
4408 | default: | |
4409 | unallocated_encoding(s); | |
4410 | } | |
faa0ba46 PM |
4411 | } |
4412 | ||
4413 | /* C3.6.28 Floating point immediate | |
4414 | * 31 30 29 28 24 23 22 21 20 13 12 10 9 5 4 0 | |
4415 | * +---+---+---+-----------+------+---+------------+-------+------+------+ | |
4416 | * | M | 0 | S | 1 1 1 1 0 | type | 1 | imm8 | 1 0 0 | imm5 | Rd | | |
4417 | * +---+---+---+-----------+------+---+------------+-------+------+------+ | |
4418 | */ | |
4419 | static void disas_fp_imm(DisasContext *s, uint32_t insn) | |
4420 | { | |
6163f868 AG |
4421 | int rd = extract32(insn, 0, 5); |
4422 | int imm8 = extract32(insn, 13, 8); | |
4423 | int is_double = extract32(insn, 22, 2); | |
4424 | uint64_t imm; | |
4425 | TCGv_i64 tcg_res; | |
4426 | ||
4427 | if (is_double > 1) { | |
4428 | unallocated_encoding(s); | |
4429 | return; | |
4430 | } | |
4431 | ||
4432 | /* The imm8 encodes the sign bit, enough bits to represent | |
4433 | * an exponent in the range 01....1xx to 10....0xx, | |
4434 | * and the most significant 4 bits of the mantissa; see | |
4435 | * VFPExpandImm() in the v8 ARM ARM. | |
4436 | */ | |
4437 | if (is_double) { | |
4438 | imm = (extract32(imm8, 7, 1) ? 0x8000 : 0) | | |
4439 | (extract32(imm8, 6, 1) ? 0x3fc0 : 0x4000) | | |
4440 | extract32(imm8, 0, 6); | |
4441 | imm <<= 48; | |
4442 | } else { | |
4443 | imm = (extract32(imm8, 7, 1) ? 0x8000 : 0) | | |
4444 | (extract32(imm8, 6, 1) ? 0x3e00 : 0x4000) | | |
4445 | (extract32(imm8, 0, 6) << 3); | |
4446 | imm <<= 16; | |
4447 | } | |
4448 | ||
4449 | tcg_res = tcg_const_i64(imm); | |
4450 | write_fp_dreg(s, rd, tcg_res); | |
4451 | tcg_temp_free_i64(tcg_res); | |
faa0ba46 PM |
4452 | } |
4453 | ||
52a1f6a3 AG |
4454 | /* Handle floating point <=> fixed point conversions. Note that we can |
4455 | * also deal with fp <=> integer conversions as a special case (scale == 64) | |
4456 | * OPTME: consider handling that special case specially or at least skipping | |
4457 | * the call to scalbn in the helpers for zero shifts. | |
4458 | */ | |
4459 | static void handle_fpfpcvt(DisasContext *s, int rd, int rn, int opcode, | |
4460 | bool itof, int rmode, int scale, int sf, int type) | |
4461 | { | |
4462 | bool is_signed = !(opcode & 1); | |
4463 | bool is_double = type; | |
4464 | TCGv_ptr tcg_fpstatus; | |
4465 | TCGv_i32 tcg_shift; | |
4466 | ||
4467 | tcg_fpstatus = get_fpstatus_ptr(); | |
4468 | ||
4469 | tcg_shift = tcg_const_i32(64 - scale); | |
4470 | ||
4471 | if (itof) { | |
4472 | TCGv_i64 tcg_int = cpu_reg(s, rn); | |
4473 | if (!sf) { | |
4474 | TCGv_i64 tcg_extend = new_tmp_a64(s); | |
4475 | ||
4476 | if (is_signed) { | |
4477 | tcg_gen_ext32s_i64(tcg_extend, tcg_int); | |
4478 | } else { | |
4479 | tcg_gen_ext32u_i64(tcg_extend, tcg_int); | |
4480 | } | |
4481 | ||
4482 | tcg_int = tcg_extend; | |
4483 | } | |
4484 | ||
4485 | if (is_double) { | |
4486 | TCGv_i64 tcg_double = tcg_temp_new_i64(); | |
4487 | if (is_signed) { | |
4488 | gen_helper_vfp_sqtod(tcg_double, tcg_int, | |
4489 | tcg_shift, tcg_fpstatus); | |
4490 | } else { | |
4491 | gen_helper_vfp_uqtod(tcg_double, tcg_int, | |
4492 | tcg_shift, tcg_fpstatus); | |
4493 | } | |
4494 | write_fp_dreg(s, rd, tcg_double); | |
4495 | tcg_temp_free_i64(tcg_double); | |
4496 | } else { | |
4497 | TCGv_i32 tcg_single = tcg_temp_new_i32(); | |
4498 | if (is_signed) { | |
4499 | gen_helper_vfp_sqtos(tcg_single, tcg_int, | |
4500 | tcg_shift, tcg_fpstatus); | |
4501 | } else { | |
4502 | gen_helper_vfp_uqtos(tcg_single, tcg_int, | |
4503 | tcg_shift, tcg_fpstatus); | |
4504 | } | |
4505 | write_fp_sreg(s, rd, tcg_single); | |
4506 | tcg_temp_free_i32(tcg_single); | |
4507 | } | |
4508 | } else { | |
4509 | TCGv_i64 tcg_int = cpu_reg(s, rd); | |
4510 | TCGv_i32 tcg_rmode; | |
4511 | ||
4512 | if (extract32(opcode, 2, 1)) { | |
4513 | /* There are too many rounding modes to all fit into rmode, | |
4514 | * so FCVTA[US] is a special case. | |
4515 | */ | |
4516 | rmode = FPROUNDING_TIEAWAY; | |
4517 | } | |
4518 | ||
4519 | tcg_rmode = tcg_const_i32(arm_rmode_to_sf(rmode)); | |
4520 | ||
4521 | gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env); | |
4522 | ||
4523 | if (is_double) { | |
4524 | TCGv_i64 tcg_double = read_fp_dreg(s, rn); | |
4525 | if (is_signed) { | |
4526 | if (!sf) { | |
4527 | gen_helper_vfp_tosld(tcg_int, tcg_double, | |
4528 | tcg_shift, tcg_fpstatus); | |
4529 | } else { | |
4530 | gen_helper_vfp_tosqd(tcg_int, tcg_double, | |
4531 | tcg_shift, tcg_fpstatus); | |
4532 | } | |
4533 | } else { | |
4534 | if (!sf) { | |
4535 | gen_helper_vfp_tould(tcg_int, tcg_double, | |
4536 | tcg_shift, tcg_fpstatus); | |
4537 | } else { | |
4538 | gen_helper_vfp_touqd(tcg_int, tcg_double, | |
4539 | tcg_shift, tcg_fpstatus); | |
4540 | } | |
4541 | } | |
4542 | tcg_temp_free_i64(tcg_double); | |
4543 | } else { | |
4544 | TCGv_i32 tcg_single = read_fp_sreg(s, rn); | |
4545 | if (sf) { | |
4546 | if (is_signed) { | |
4547 | gen_helper_vfp_tosqs(tcg_int, tcg_single, | |
4548 | tcg_shift, tcg_fpstatus); | |
4549 | } else { | |
4550 | gen_helper_vfp_touqs(tcg_int, tcg_single, | |
4551 | tcg_shift, tcg_fpstatus); | |
4552 | } | |
4553 | } else { | |
4554 | TCGv_i32 tcg_dest = tcg_temp_new_i32(); | |
4555 | if (is_signed) { | |
4556 | gen_helper_vfp_tosls(tcg_dest, tcg_single, | |
4557 | tcg_shift, tcg_fpstatus); | |
4558 | } else { | |
4559 | gen_helper_vfp_touls(tcg_dest, tcg_single, | |
4560 | tcg_shift, tcg_fpstatus); | |
4561 | } | |
4562 | tcg_gen_extu_i32_i64(tcg_int, tcg_dest); | |
4563 | tcg_temp_free_i32(tcg_dest); | |
4564 | } | |
4565 | tcg_temp_free_i32(tcg_single); | |
4566 | } | |
4567 | ||
4568 | gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env); | |
4569 | tcg_temp_free_i32(tcg_rmode); | |
4570 | ||
4571 | if (!sf) { | |
4572 | tcg_gen_ext32u_i64(tcg_int, tcg_int); | |
4573 | } | |
4574 | } | |
4575 | ||
4576 | tcg_temp_free_ptr(tcg_fpstatus); | |
4577 | tcg_temp_free_i32(tcg_shift); | |
4578 | } | |
4579 | ||
faa0ba46 PM |
4580 | /* C3.6.29 Floating point <-> fixed point conversions |
4581 | * 31 30 29 28 24 23 22 21 20 19 18 16 15 10 9 5 4 0 | |
4582 | * +----+---+---+-----------+------+---+-------+--------+-------+------+------+ | |
4583 | * | sf | 0 | S | 1 1 1 1 0 | type | 0 | rmode | opcode | scale | Rn | Rd | | |
4584 | * +----+---+---+-----------+------+---+-------+--------+-------+------+------+ | |
4585 | */ | |
4586 | static void disas_fp_fixed_conv(DisasContext *s, uint32_t insn) | |
4587 | { | |
52a1f6a3 AG |
4588 | int rd = extract32(insn, 0, 5); |
4589 | int rn = extract32(insn, 5, 5); | |
4590 | int scale = extract32(insn, 10, 6); | |
4591 | int opcode = extract32(insn, 16, 3); | |
4592 | int rmode = extract32(insn, 19, 2); | |
4593 | int type = extract32(insn, 22, 2); | |
4594 | bool sbit = extract32(insn, 29, 1); | |
4595 | bool sf = extract32(insn, 31, 1); | |
4596 | bool itof; | |
4597 | ||
4598 | if (sbit || (type > 1) | |
4599 | || (!sf && scale < 32)) { | |
4600 | unallocated_encoding(s); | |
4601 | return; | |
4602 | } | |
4603 | ||
4604 | switch ((rmode << 3) | opcode) { | |
4605 | case 0x2: /* SCVTF */ | |
4606 | case 0x3: /* UCVTF */ | |
4607 | itof = true; | |
4608 | break; | |
4609 | case 0x18: /* FCVTZS */ | |
4610 | case 0x19: /* FCVTZU */ | |
4611 | itof = false; | |
4612 | break; | |
4613 | default: | |
4614 | unallocated_encoding(s); | |
4615 | return; | |
4616 | } | |
4617 | ||
4618 | handle_fpfpcvt(s, rd, rn, opcode, itof, FPROUNDING_ZERO, scale, sf, type); | |
faa0ba46 PM |
4619 | } |
4620 | ||
ce5458e8 PM |
4621 | static void handle_fmov(DisasContext *s, int rd, int rn, int type, bool itof) |
4622 | { | |
4623 | /* FMOV: gpr to or from float, double, or top half of quad fp reg, | |
4624 | * without conversion. | |
4625 | */ | |
4626 | ||
4627 | if (itof) { | |
ce5458e8 PM |
4628 | TCGv_i64 tcg_rn = cpu_reg(s, rn); |
4629 | ||
4630 | switch (type) { | |
4631 | case 0: | |
4632 | { | |
4633 | /* 32 bit */ | |
4634 | TCGv_i64 tmp = tcg_temp_new_i64(); | |
4635 | tcg_gen_ext32u_i64(tmp, tcg_rn); | |
e2f90565 | 4636 | tcg_gen_st_i64(tmp, cpu_env, fp_reg_offset(rd, MO_64)); |
ce5458e8 | 4637 | tcg_gen_movi_i64(tmp, 0); |
e2f90565 | 4638 | tcg_gen_st_i64(tmp, cpu_env, fp_reg_hi_offset(rd)); |
ce5458e8 PM |
4639 | tcg_temp_free_i64(tmp); |
4640 | break; | |
4641 | } | |
4642 | case 1: | |
4643 | { | |
4644 | /* 64 bit */ | |
4645 | TCGv_i64 tmp = tcg_const_i64(0); | |
e2f90565 PM |
4646 | tcg_gen_st_i64(tcg_rn, cpu_env, fp_reg_offset(rd, MO_64)); |
4647 | tcg_gen_st_i64(tmp, cpu_env, fp_reg_hi_offset(rd)); | |
ce5458e8 PM |
4648 | tcg_temp_free_i64(tmp); |
4649 | break; | |
4650 | } | |
4651 | case 2: | |
4652 | /* 64 bit to top half. */ | |
e2f90565 | 4653 | tcg_gen_st_i64(tcg_rn, cpu_env, fp_reg_hi_offset(rd)); |
ce5458e8 PM |
4654 | break; |
4655 | } | |
4656 | } else { | |
ce5458e8 PM |
4657 | TCGv_i64 tcg_rd = cpu_reg(s, rd); |
4658 | ||
4659 | switch (type) { | |
4660 | case 0: | |
4661 | /* 32 bit */ | |
e2f90565 | 4662 | tcg_gen_ld32u_i64(tcg_rd, cpu_env, fp_reg_offset(rn, MO_32)); |
ce5458e8 | 4663 | break; |
ce5458e8 PM |
4664 | case 1: |
4665 | /* 64 bit */ | |
e2f90565 PM |
4666 | tcg_gen_ld_i64(tcg_rd, cpu_env, fp_reg_offset(rn, MO_64)); |
4667 | break; | |
4668 | case 2: | |
4669 | /* 64 bits from top half */ | |
4670 | tcg_gen_ld_i64(tcg_rd, cpu_env, fp_reg_hi_offset(rn)); | |
ce5458e8 PM |
4671 | break; |
4672 | } | |
4673 | } | |
4674 | } | |
4675 | ||
faa0ba46 PM |
4676 | /* C3.6.30 Floating point <-> integer conversions |
4677 | * 31 30 29 28 24 23 22 21 20 19 18 16 15 10 9 5 4 0 | |
4678 | * +----+---+---+-----------+------+---+-------+-----+-------------+----+----+ | |
c436d406 | 4679 | * | sf | 0 | S | 1 1 1 1 0 | type | 1 | rmode | opc | 0 0 0 0 0 0 | Rn | Rd | |
faa0ba46 PM |
4680 | * +----+---+---+-----------+------+---+-------+-----+-------------+----+----+ |
4681 | */ | |
4682 | static void disas_fp_int_conv(DisasContext *s, uint32_t insn) | |
4683 | { | |
ce5458e8 PM |
4684 | int rd = extract32(insn, 0, 5); |
4685 | int rn = extract32(insn, 5, 5); | |
4686 | int opcode = extract32(insn, 16, 3); | |
4687 | int rmode = extract32(insn, 19, 2); | |
4688 | int type = extract32(insn, 22, 2); | |
4689 | bool sbit = extract32(insn, 29, 1); | |
4690 | bool sf = extract32(insn, 31, 1); | |
4691 | ||
c436d406 WN |
4692 | if (sbit) { |
4693 | unallocated_encoding(s); | |
4694 | return; | |
4695 | } | |
4696 | ||
4697 | if (opcode > 5) { | |
ce5458e8 PM |
4698 | /* FMOV */ |
4699 | bool itof = opcode & 1; | |
4700 | ||
c436d406 WN |
4701 | if (rmode >= 2) { |
4702 | unallocated_encoding(s); | |
4703 | return; | |
4704 | } | |
4705 | ||
ce5458e8 PM |
4706 | switch (sf << 3 | type << 1 | rmode) { |
4707 | case 0x0: /* 32 bit */ | |
4708 | case 0xa: /* 64 bit */ | |
4709 | case 0xd: /* 64 bit to top half of quad */ | |
4710 | break; | |
4711 | default: | |
4712 | /* all other sf/type/rmode combinations are invalid */ | |
4713 | unallocated_encoding(s); | |
4714 | break; | |
4715 | } | |
4716 | ||
4717 | handle_fmov(s, rd, rn, type, itof); | |
4718 | } else { | |
4719 | /* actual FP conversions */ | |
c436d406 WN |
4720 | bool itof = extract32(opcode, 1, 1); |
4721 | ||
4722 | if (type > 1 || (rmode != 0 && opcode > 1)) { | |
4723 | unallocated_encoding(s); | |
4724 | return; | |
4725 | } | |
4726 | ||
4727 | handle_fpfpcvt(s, rd, rn, opcode, itof, rmode, 64, sf, type); | |
ce5458e8 | 4728 | } |
faa0ba46 PM |
4729 | } |
4730 | ||
4731 | /* FP-specific subcases of table C3-6 (SIMD and FP data processing) | |
4732 | * 31 30 29 28 25 24 0 | |
4733 | * +---+---+---+---------+-----------------------------+ | |
4734 | * | | 0 | | 1 1 1 1 | | | |
4735 | * +---+---+---+---------+-----------------------------+ | |
4736 | */ | |
4737 | static void disas_data_proc_fp(DisasContext *s, uint32_t insn) | |
4738 | { | |
4739 | if (extract32(insn, 24, 1)) { | |
4740 | /* Floating point data-processing (3 source) */ | |
4741 | disas_fp_3src(s, insn); | |
4742 | } else if (extract32(insn, 21, 1) == 0) { | |
4743 | /* Floating point to fixed point conversions */ | |
4744 | disas_fp_fixed_conv(s, insn); | |
4745 | } else { | |
4746 | switch (extract32(insn, 10, 2)) { | |
4747 | case 1: | |
4748 | /* Floating point conditional compare */ | |
4749 | disas_fp_ccomp(s, insn); | |
4750 | break; | |
4751 | case 2: | |
4752 | /* Floating point data-processing (2 source) */ | |
4753 | disas_fp_2src(s, insn); | |
4754 | break; | |
4755 | case 3: | |
4756 | /* Floating point conditional select */ | |
4757 | disas_fp_csel(s, insn); | |
4758 | break; | |
4759 | case 0: | |
4760 | switch (ctz32(extract32(insn, 12, 4))) { | |
4761 | case 0: /* [15:12] == xxx1 */ | |
4762 | /* Floating point immediate */ | |
4763 | disas_fp_imm(s, insn); | |
4764 | break; | |
4765 | case 1: /* [15:12] == xx10 */ | |
4766 | /* Floating point compare */ | |
4767 | disas_fp_compare(s, insn); | |
4768 | break; | |
4769 | case 2: /* [15:12] == x100 */ | |
4770 | /* Floating point data-processing (1 source) */ | |
4771 | disas_fp_1src(s, insn); | |
4772 | break; | |
4773 | case 3: /* [15:12] == 1000 */ | |
4774 | unallocated_encoding(s); | |
4775 | break; | |
4776 | default: /* [15:12] == 0000 */ | |
4777 | /* Floating point <-> integer conversions */ | |
4778 | disas_fp_int_conv(s, insn); | |
4779 | break; | |
4780 | } | |
4781 | break; | |
4782 | } | |
4783 | } | |
4784 | } | |
4785 | ||
5c73747f PM |
4786 | static void do_ext64(DisasContext *s, TCGv_i64 tcg_left, TCGv_i64 tcg_right, |
4787 | int pos) | |
4788 | { | |
4789 | /* Extract 64 bits from the middle of two concatenated 64 bit | |
4790 | * vector register slices left:right. The extracted bits start | |
4791 | * at 'pos' bits into the right (least significant) side. | |
4792 | * We return the result in tcg_right, and guarantee not to | |
4793 | * trash tcg_left. | |
4794 | */ | |
4795 | TCGv_i64 tcg_tmp = tcg_temp_new_i64(); | |
4796 | assert(pos > 0 && pos < 64); | |
4797 | ||
4798 | tcg_gen_shri_i64(tcg_right, tcg_right, pos); | |
4799 | tcg_gen_shli_i64(tcg_tmp, tcg_left, 64 - pos); | |
4800 | tcg_gen_or_i64(tcg_right, tcg_right, tcg_tmp); | |
4801 | ||
4802 | tcg_temp_free_i64(tcg_tmp); | |
4803 | } | |
4804 | ||
384b26fb AB |
4805 | /* C3.6.1 EXT |
4806 | * 31 30 29 24 23 22 21 20 16 15 14 11 10 9 5 4 0 | |
4807 | * +---+---+-------------+-----+---+------+---+------+---+------+------+ | |
4808 | * | 0 | Q | 1 0 1 1 1 0 | op2 | 0 | Rm | 0 | imm4 | 0 | Rn | Rd | | |
4809 | * +---+---+-------------+-----+---+------+---+------+---+------+------+ | |
4810 | */ | |
4811 | static void disas_simd_ext(DisasContext *s, uint32_t insn) | |
4812 | { | |
5c73747f PM |
4813 | int is_q = extract32(insn, 30, 1); |
4814 | int op2 = extract32(insn, 22, 2); | |
4815 | int imm4 = extract32(insn, 11, 4); | |
4816 | int rm = extract32(insn, 16, 5); | |
4817 | int rn = extract32(insn, 5, 5); | |
4818 | int rd = extract32(insn, 0, 5); | |
4819 | int pos = imm4 << 3; | |
4820 | TCGv_i64 tcg_resl, tcg_resh; | |
4821 | ||
4822 | if (op2 != 0 || (!is_q && extract32(imm4, 3, 1))) { | |
4823 | unallocated_encoding(s); | |
4824 | return; | |
4825 | } | |
4826 | ||
4827 | tcg_resh = tcg_temp_new_i64(); | |
4828 | tcg_resl = tcg_temp_new_i64(); | |
4829 | ||
4830 | /* Vd gets bits starting at pos bits into Vm:Vn. This is | |
4831 | * either extracting 128 bits from a 128:128 concatenation, or | |
4832 | * extracting 64 bits from a 64:64 concatenation. | |
4833 | */ | |
4834 | if (!is_q) { | |
4835 | read_vec_element(s, tcg_resl, rn, 0, MO_64); | |
4836 | if (pos != 0) { | |
4837 | read_vec_element(s, tcg_resh, rm, 0, MO_64); | |
4838 | do_ext64(s, tcg_resh, tcg_resl, pos); | |
4839 | } | |
4840 | tcg_gen_movi_i64(tcg_resh, 0); | |
4841 | } else { | |
4842 | TCGv_i64 tcg_hh; | |
4843 | typedef struct { | |
4844 | int reg; | |
4845 | int elt; | |
4846 | } EltPosns; | |
4847 | EltPosns eltposns[] = { {rn, 0}, {rn, 1}, {rm, 0}, {rm, 1} }; | |
4848 | EltPosns *elt = eltposns; | |
4849 | ||
4850 | if (pos >= 64) { | |
4851 | elt++; | |
4852 | pos -= 64; | |
4853 | } | |
4854 | ||
4855 | read_vec_element(s, tcg_resl, elt->reg, elt->elt, MO_64); | |
4856 | elt++; | |
4857 | read_vec_element(s, tcg_resh, elt->reg, elt->elt, MO_64); | |
4858 | elt++; | |
4859 | if (pos != 0) { | |
4860 | do_ext64(s, tcg_resh, tcg_resl, pos); | |
4861 | tcg_hh = tcg_temp_new_i64(); | |
4862 | read_vec_element(s, tcg_hh, elt->reg, elt->elt, MO_64); | |
4863 | do_ext64(s, tcg_hh, tcg_resh, pos); | |
4864 | tcg_temp_free_i64(tcg_hh); | |
4865 | } | |
4866 | } | |
4867 | ||
4868 | write_vec_element(s, tcg_resl, rd, 0, MO_64); | |
4869 | tcg_temp_free_i64(tcg_resl); | |
4870 | write_vec_element(s, tcg_resh, rd, 1, MO_64); | |
4871 | tcg_temp_free_i64(tcg_resh); | |
384b26fb AB |
4872 | } |
4873 | ||
4874 | /* C3.6.2 TBL/TBX | |
4875 | * 31 30 29 24 23 22 21 20 16 15 14 13 12 11 10 9 5 4 0 | |
4876 | * +---+---+-------------+-----+---+------+---+-----+----+-----+------+------+ | |
4877 | * | 0 | Q | 0 0 1 1 1 0 | op2 | 0 | Rm | 0 | len | op | 0 0 | Rn | Rd | | |
4878 | * +---+---+-------------+-----+---+------+---+-----+----+-----+------+------+ | |
4879 | */ | |
4880 | static void disas_simd_tb(DisasContext *s, uint32_t insn) | |
4881 | { | |
7c51048f MM |
4882 | int op2 = extract32(insn, 22, 2); |
4883 | int is_q = extract32(insn, 30, 1); | |
4884 | int rm = extract32(insn, 16, 5); | |
4885 | int rn = extract32(insn, 5, 5); | |
4886 | int rd = extract32(insn, 0, 5); | |
4887 | int is_tblx = extract32(insn, 12, 1); | |
4888 | int len = extract32(insn, 13, 2); | |
4889 | TCGv_i64 tcg_resl, tcg_resh, tcg_idx; | |
4890 | TCGv_i32 tcg_regno, tcg_numregs; | |
4891 | ||
4892 | if (op2 != 0) { | |
4893 | unallocated_encoding(s); | |
4894 | return; | |
4895 | } | |
4896 | ||
4897 | /* This does a table lookup: for every byte element in the input | |
4898 | * we index into a table formed from up to four vector registers, | |
4899 | * and then the output is the result of the lookups. Our helper | |
4900 | * function does the lookup operation for a single 64 bit part of | |
4901 | * the input. | |
4902 | */ | |
4903 | tcg_resl = tcg_temp_new_i64(); | |
4904 | tcg_resh = tcg_temp_new_i64(); | |
4905 | ||
4906 | if (is_tblx) { | |
4907 | read_vec_element(s, tcg_resl, rd, 0, MO_64); | |
4908 | } else { | |
4909 | tcg_gen_movi_i64(tcg_resl, 0); | |
4910 | } | |
4911 | if (is_tblx && is_q) { | |
4912 | read_vec_element(s, tcg_resh, rd, 1, MO_64); | |
4913 | } else { | |
4914 | tcg_gen_movi_i64(tcg_resh, 0); | |
4915 | } | |
4916 | ||
4917 | tcg_idx = tcg_temp_new_i64(); | |
4918 | tcg_regno = tcg_const_i32(rn); | |
4919 | tcg_numregs = tcg_const_i32(len + 1); | |
4920 | read_vec_element(s, tcg_idx, rm, 0, MO_64); | |
4921 | gen_helper_simd_tbl(tcg_resl, cpu_env, tcg_resl, tcg_idx, | |
4922 | tcg_regno, tcg_numregs); | |
4923 | if (is_q) { | |
4924 | read_vec_element(s, tcg_idx, rm, 1, MO_64); | |
4925 | gen_helper_simd_tbl(tcg_resh, cpu_env, tcg_resh, tcg_idx, | |
4926 | tcg_regno, tcg_numregs); | |
4927 | } | |
4928 | tcg_temp_free_i64(tcg_idx); | |
4929 | tcg_temp_free_i32(tcg_regno); | |
4930 | tcg_temp_free_i32(tcg_numregs); | |
4931 | ||
4932 | write_vec_element(s, tcg_resl, rd, 0, MO_64); | |
4933 | tcg_temp_free_i64(tcg_resl); | |
4934 | write_vec_element(s, tcg_resh, rd, 1, MO_64); | |
4935 | tcg_temp_free_i64(tcg_resh); | |
384b26fb AB |
4936 | } |
4937 | ||
4938 | /* C3.6.3 ZIP/UZP/TRN | |
4939 | * 31 30 29 24 23 22 21 20 16 15 14 12 11 10 9 5 4 0 | |
4940 | * +---+---+-------------+------+---+------+---+------------------+------+ | |
4941 | * | 0 | Q | 0 0 1 1 1 0 | size | 0 | Rm | 0 | opc | 1 0 | Rn | Rd | | |
4942 | * +---+---+-------------+------+---+------+---+------------------+------+ | |
4943 | */ | |
4944 | static void disas_simd_zip_trn(DisasContext *s, uint32_t insn) | |
4945 | { | |
5fa5469c MM |
4946 | int rd = extract32(insn, 0, 5); |
4947 | int rn = extract32(insn, 5, 5); | |
4948 | int rm = extract32(insn, 16, 5); | |
4949 | int size = extract32(insn, 22, 2); | |
4950 | /* opc field bits [1:0] indicate ZIP/UZP/TRN; | |
4951 | * bit 2 indicates 1 vs 2 variant of the insn. | |
4952 | */ | |
4953 | int opcode = extract32(insn, 12, 2); | |
4954 | bool part = extract32(insn, 14, 1); | |
4955 | bool is_q = extract32(insn, 30, 1); | |
4956 | int esize = 8 << size; | |
4957 | int i, ofs; | |
4958 | int datasize = is_q ? 128 : 64; | |
4959 | int elements = datasize / esize; | |
4960 | TCGv_i64 tcg_res, tcg_resl, tcg_resh; | |
4961 | ||
4962 | if (opcode == 0 || (size == 3 && !is_q)) { | |
4963 | unallocated_encoding(s); | |
4964 | return; | |
4965 | } | |
4966 | ||
4967 | tcg_resl = tcg_const_i64(0); | |
4968 | tcg_resh = tcg_const_i64(0); | |
4969 | tcg_res = tcg_temp_new_i64(); | |
4970 | ||
4971 | for (i = 0; i < elements; i++) { | |
4972 | switch (opcode) { | |
4973 | case 1: /* UZP1/2 */ | |
4974 | { | |
4975 | int midpoint = elements / 2; | |
4976 | if (i < midpoint) { | |
4977 | read_vec_element(s, tcg_res, rn, 2 * i + part, size); | |
4978 | } else { | |
4979 | read_vec_element(s, tcg_res, rm, | |
4980 | 2 * (i - midpoint) + part, size); | |
4981 | } | |
4982 | break; | |
4983 | } | |
4984 | case 2: /* TRN1/2 */ | |
4985 | if (i & 1) { | |
4986 | read_vec_element(s, tcg_res, rm, (i & ~1) + part, size); | |
4987 | } else { | |
4988 | read_vec_element(s, tcg_res, rn, (i & ~1) + part, size); | |
4989 | } | |
4990 | break; | |
4991 | case 3: /* ZIP1/2 */ | |
4992 | { | |
4993 | int base = part * elements / 2; | |
4994 | if (i & 1) { | |
4995 | read_vec_element(s, tcg_res, rm, base + (i >> 1), size); | |
4996 | } else { | |
4997 | read_vec_element(s, tcg_res, rn, base + (i >> 1), size); | |
4998 | } | |
4999 | break; | |
5000 | } | |
5001 | default: | |
5002 | g_assert_not_reached(); | |
5003 | } | |
5004 | ||
5005 | ofs = i * esize; | |
5006 | if (ofs < 64) { | |
5007 | tcg_gen_shli_i64(tcg_res, tcg_res, ofs); | |
5008 | tcg_gen_or_i64(tcg_resl, tcg_resl, tcg_res); | |
5009 | } else { | |
5010 | tcg_gen_shli_i64(tcg_res, tcg_res, ofs - 64); | |
5011 | tcg_gen_or_i64(tcg_resh, tcg_resh, tcg_res); | |
5012 | } | |
5013 | } | |
5014 | ||
5015 | tcg_temp_free_i64(tcg_res); | |
5016 | ||
5017 | write_vec_element(s, tcg_resl, rd, 0, MO_64); | |
5018 | tcg_temp_free_i64(tcg_resl); | |
5019 | write_vec_element(s, tcg_resh, rd, 1, MO_64); | |
5020 | tcg_temp_free_i64(tcg_resh); | |
384b26fb AB |
5021 | } |
5022 | ||
4a0ff1ce MM |
5023 | static void do_minmaxop(DisasContext *s, TCGv_i32 tcg_elt1, TCGv_i32 tcg_elt2, |
5024 | int opc, bool is_min, TCGv_ptr fpst) | |
5025 | { | |
5026 | /* Helper function for disas_simd_across_lanes: do a single precision | |
5027 | * min/max operation on the specified two inputs, | |
5028 | * and return the result in tcg_elt1. | |
5029 | */ | |
5030 | if (opc == 0xc) { | |
5031 | if (is_min) { | |
5032 | gen_helper_vfp_minnums(tcg_elt1, tcg_elt1, tcg_elt2, fpst); | |
5033 | } else { | |
5034 | gen_helper_vfp_maxnums(tcg_elt1, tcg_elt1, tcg_elt2, fpst); | |
5035 | } | |
5036 | } else { | |
5037 | assert(opc == 0xf); | |
5038 | if (is_min) { | |
5039 | gen_helper_vfp_mins(tcg_elt1, tcg_elt1, tcg_elt2, fpst); | |
5040 | } else { | |
5041 | gen_helper_vfp_maxs(tcg_elt1, tcg_elt1, tcg_elt2, fpst); | |
5042 | } | |
5043 | } | |
5044 | } | |
5045 | ||
384b26fb AB |
5046 | /* C3.6.4 AdvSIMD across lanes |
5047 | * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0 | |
5048 | * +---+---+---+-----------+------+-----------+--------+-----+------+------+ | |
5049 | * | 0 | Q | U | 0 1 1 1 0 | size | 1 1 0 0 0 | opcode | 1 0 | Rn | Rd | | |
5050 | * +---+---+---+-----------+------+-----------+--------+-----+------+------+ | |
5051 | */ | |
5052 | static void disas_simd_across_lanes(DisasContext *s, uint32_t insn) | |
5053 | { | |
4a0ff1ce MM |
5054 | int rd = extract32(insn, 0, 5); |
5055 | int rn = extract32(insn, 5, 5); | |
5056 | int size = extract32(insn, 22, 2); | |
5057 | int opcode = extract32(insn, 12, 5); | |
5058 | bool is_q = extract32(insn, 30, 1); | |
5059 | bool is_u = extract32(insn, 29, 1); | |
5060 | bool is_fp = false; | |
5061 | bool is_min = false; | |
5062 | int esize; | |
5063 | int elements; | |
5064 | int i; | |
5065 | TCGv_i64 tcg_res, tcg_elt; | |
5066 | ||
5067 | switch (opcode) { | |
5068 | case 0x1b: /* ADDV */ | |
5069 | if (is_u) { | |
5070 | unallocated_encoding(s); | |
5071 | return; | |
5072 | } | |
5073 | /* fall through */ | |
5074 | case 0x3: /* SADDLV, UADDLV */ | |
5075 | case 0xa: /* SMAXV, UMAXV */ | |
5076 | case 0x1a: /* SMINV, UMINV */ | |
5077 | if (size == 3 || (size == 2 && !is_q)) { | |
5078 | unallocated_encoding(s); | |
5079 | return; | |
5080 | } | |
5081 | break; | |
5082 | case 0xc: /* FMAXNMV, FMINNMV */ | |
5083 | case 0xf: /* FMAXV, FMINV */ | |
5084 | if (!is_u || !is_q || extract32(size, 0, 1)) { | |
5085 | unallocated_encoding(s); | |
5086 | return; | |
5087 | } | |
5088 | /* Bit 1 of size field encodes min vs max, and actual size is always | |
5089 | * 32 bits: adjust the size variable so following code can rely on it | |
5090 | */ | |
5091 | is_min = extract32(size, 1, 1); | |
5092 | is_fp = true; | |
5093 | size = 2; | |
5094 | break; | |
5095 | default: | |
5096 | unallocated_encoding(s); | |
5097 | return; | |
5098 | } | |
5099 | ||
5100 | esize = 8 << size; | |
5101 | elements = (is_q ? 128 : 64) / esize; | |
5102 | ||
5103 | tcg_res = tcg_temp_new_i64(); | |
5104 | tcg_elt = tcg_temp_new_i64(); | |
5105 | ||
5106 | /* These instructions operate across all lanes of a vector | |
5107 | * to produce a single result. We can guarantee that a 64 | |
5108 | * bit intermediate is sufficient: | |
5109 | * + for [US]ADDLV the maximum element size is 32 bits, and | |
5110 | * the result type is 64 bits | |
5111 | * + for FMAX*V, FMIN*V, ADDV the intermediate type is the | |
5112 | * same as the element size, which is 32 bits at most | |
5113 | * For the integer operations we can choose to work at 64 | |
5114 | * or 32 bits and truncate at the end; for simplicity | |
5115 | * we use 64 bits always. The floating point | |
5116 | * ops do require 32 bit intermediates, though. | |
5117 | */ | |
5118 | if (!is_fp) { | |
5119 | read_vec_element(s, tcg_res, rn, 0, size | (is_u ? 0 : MO_SIGN)); | |
5120 | ||
5121 | for (i = 1; i < elements; i++) { | |
5122 | read_vec_element(s, tcg_elt, rn, i, size | (is_u ? 0 : MO_SIGN)); | |
5123 | ||
5124 | switch (opcode) { | |
5125 | case 0x03: /* SADDLV / UADDLV */ | |
5126 | case 0x1b: /* ADDV */ | |
5127 | tcg_gen_add_i64(tcg_res, tcg_res, tcg_elt); | |
5128 | break; | |
5129 | case 0x0a: /* SMAXV / UMAXV */ | |
5130 | tcg_gen_movcond_i64(is_u ? TCG_COND_GEU : TCG_COND_GE, | |
5131 | tcg_res, | |
5132 | tcg_res, tcg_elt, tcg_res, tcg_elt); | |
5133 | break; | |
5134 | case 0x1a: /* SMINV / UMINV */ | |
5135 | tcg_gen_movcond_i64(is_u ? TCG_COND_LEU : TCG_COND_LE, | |
5136 | tcg_res, | |
5137 | tcg_res, tcg_elt, tcg_res, tcg_elt); | |
5138 | break; | |
5139 | break; | |
5140 | default: | |
5141 | g_assert_not_reached(); | |
5142 | } | |
5143 | ||
5144 | } | |
5145 | } else { | |
5146 | /* Floating point ops which work on 32 bit (single) intermediates. | |
5147 | * Note that correct NaN propagation requires that we do these | |
5148 | * operations in exactly the order specified by the pseudocode. | |
5149 | */ | |
5150 | TCGv_i32 tcg_elt1 = tcg_temp_new_i32(); | |
5151 | TCGv_i32 tcg_elt2 = tcg_temp_new_i32(); | |
5152 | TCGv_i32 tcg_elt3 = tcg_temp_new_i32(); | |
5153 | TCGv_ptr fpst = get_fpstatus_ptr(); | |
5154 | ||
5155 | assert(esize == 32); | |
5156 | assert(elements == 4); | |
5157 | ||
5158 | read_vec_element(s, tcg_elt, rn, 0, MO_32); | |
5159 | tcg_gen_trunc_i64_i32(tcg_elt1, tcg_elt); | |
5160 | read_vec_element(s, tcg_elt, rn, 1, MO_32); | |
5161 | tcg_gen_trunc_i64_i32(tcg_elt2, tcg_elt); | |
5162 | ||
5163 | do_minmaxop(s, tcg_elt1, tcg_elt2, opcode, is_min, fpst); | |
5164 | ||
5165 | read_vec_element(s, tcg_elt, rn, 2, MO_32); | |
5166 | tcg_gen_trunc_i64_i32(tcg_elt2, tcg_elt); | |
5167 | read_vec_element(s, tcg_elt, rn, 3, MO_32); | |
5168 | tcg_gen_trunc_i64_i32(tcg_elt3, tcg_elt); | |
5169 | ||
5170 | do_minmaxop(s, tcg_elt2, tcg_elt3, opcode, is_min, fpst); | |
5171 | ||
5172 | do_minmaxop(s, tcg_elt1, tcg_elt2, opcode, is_min, fpst); | |
5173 | ||
5174 | tcg_gen_extu_i32_i64(tcg_res, tcg_elt1); | |
5175 | tcg_temp_free_i32(tcg_elt1); | |
5176 | tcg_temp_free_i32(tcg_elt2); | |
5177 | tcg_temp_free_i32(tcg_elt3); | |
5178 | tcg_temp_free_ptr(fpst); | |
5179 | } | |
5180 | ||
5181 | tcg_temp_free_i64(tcg_elt); | |
5182 | ||
5183 | /* Now truncate the result to the width required for the final output */ | |
5184 | if (opcode == 0x03) { | |
5185 | /* SADDLV, UADDLV: result is 2*esize */ | |
5186 | size++; | |
5187 | } | |
5188 | ||
5189 | switch (size) { | |
5190 | case 0: | |
5191 | tcg_gen_ext8u_i64(tcg_res, tcg_res); | |
5192 | break; | |
5193 | case 1: | |
5194 | tcg_gen_ext16u_i64(tcg_res, tcg_res); | |
5195 | break; | |
5196 | case 2: | |
5197 | tcg_gen_ext32u_i64(tcg_res, tcg_res); | |
5198 | break; | |
5199 | case 3: | |
5200 | break; | |
5201 | default: | |
5202 | g_assert_not_reached(); | |
5203 | } | |
5204 | ||
5205 | write_fp_dreg(s, rd, tcg_res); | |
5206 | tcg_temp_free_i64(tcg_res); | |
384b26fb AB |
5207 | } |
5208 | ||
67bb9389 AB |
5209 | /* C6.3.31 DUP (Element, Vector) |
5210 | * | |
5211 | * 31 30 29 21 20 16 15 10 9 5 4 0 | |
5212 | * +---+---+-------------------+--------+-------------+------+------+ | |
5213 | * | 0 | Q | 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 0 0 0 1 | Rn | Rd | | |
5214 | * +---+---+-------------------+--------+-------------+------+------+ | |
5215 | * | |
5216 | * size: encoded in imm5 (see ARM ARM LowestSetBit()) | |
5217 | */ | |
5218 | static void handle_simd_dupe(DisasContext *s, int is_q, int rd, int rn, | |
5219 | int imm5) | |
5220 | { | |
5221 | int size = ctz32(imm5); | |
5222 | int esize = 8 << size; | |
5223 | int elements = (is_q ? 128 : 64) / esize; | |
5224 | int index, i; | |
5225 | TCGv_i64 tmp; | |
5226 | ||
5227 | if (size > 3 || (size == 3 && !is_q)) { | |
5228 | unallocated_encoding(s); | |
5229 | return; | |
5230 | } | |
5231 | ||
5232 | index = imm5 >> (size + 1); | |
5233 | ||
5234 | tmp = tcg_temp_new_i64(); | |
5235 | read_vec_element(s, tmp, rn, index, size); | |
5236 | ||
5237 | for (i = 0; i < elements; i++) { | |
5238 | write_vec_element(s, tmp, rd, i, size); | |
5239 | } | |
5240 | ||
5241 | if (!is_q) { | |
5242 | clear_vec_high(s, rd); | |
5243 | } | |
5244 | ||
5245 | tcg_temp_free_i64(tmp); | |
5246 | } | |
5247 | ||
360a6f2d PM |
5248 | /* C6.3.31 DUP (element, scalar) |
5249 | * 31 21 20 16 15 10 9 5 4 0 | |
5250 | * +-----------------------+--------+-------------+------+------+ | |
5251 | * | 0 1 0 1 1 1 1 0 0 0 0 | imm5 | 0 0 0 0 0 1 | Rn | Rd | | |
5252 | * +-----------------------+--------+-------------+------+------+ | |
5253 | */ | |
5254 | static void handle_simd_dupes(DisasContext *s, int rd, int rn, | |
5255 | int imm5) | |
5256 | { | |
5257 | int size = ctz32(imm5); | |
5258 | int index; | |
5259 | TCGv_i64 tmp; | |
5260 | ||
5261 | if (size > 3) { | |
5262 | unallocated_encoding(s); | |
5263 | return; | |
5264 | } | |
5265 | ||
5266 | index = imm5 >> (size + 1); | |
5267 | ||
5268 | /* This instruction just extracts the specified element and | |
5269 | * zero-extends it into the bottom of the destination register. | |
5270 | */ | |
5271 | tmp = tcg_temp_new_i64(); | |
5272 | read_vec_element(s, tmp, rn, index, size); | |
5273 | write_fp_dreg(s, rd, tmp); | |
5274 | tcg_temp_free_i64(tmp); | |
5275 | } | |
5276 | ||
67bb9389 AB |
5277 | /* C6.3.32 DUP (General) |
5278 | * | |
5279 | * 31 30 29 21 20 16 15 10 9 5 4 0 | |
5280 | * +---+---+-------------------+--------+-------------+------+------+ | |
5281 | * | 0 | Q | 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 0 0 1 1 | Rn | Rd | | |
5282 | * +---+---+-------------------+--------+-------------+------+------+ | |
5283 | * | |
5284 | * size: encoded in imm5 (see ARM ARM LowestSetBit()) | |
5285 | */ | |
5286 | static void handle_simd_dupg(DisasContext *s, int is_q, int rd, int rn, | |
5287 | int imm5) | |
5288 | { | |
5289 | int size = ctz32(imm5); | |
5290 | int esize = 8 << size; | |
5291 | int elements = (is_q ? 128 : 64)/esize; | |
5292 | int i = 0; | |
5293 | ||
5294 | if (size > 3 || ((size == 3) && !is_q)) { | |
5295 | unallocated_encoding(s); | |
5296 | return; | |
5297 | } | |
5298 | for (i = 0; i < elements; i++) { | |
5299 | write_vec_element(s, cpu_reg(s, rn), rd, i, size); | |
5300 | } | |
5301 | if (!is_q) { | |
5302 | clear_vec_high(s, rd); | |
5303 | } | |
5304 | } | |
5305 | ||
5306 | /* C6.3.150 INS (Element) | |
5307 | * | |
5308 | * 31 21 20 16 15 14 11 10 9 5 4 0 | |
5309 | * +-----------------------+--------+------------+---+------+------+ | |
5310 | * | 0 1 1 0 1 1 1 0 0 0 0 | imm5 | 0 | imm4 | 1 | Rn | Rd | | |
5311 | * +-----------------------+--------+------------+---+------+------+ | |
5312 | * | |
5313 | * size: encoded in imm5 (see ARM ARM LowestSetBit()) | |
5314 | * index: encoded in imm5<4:size+1> | |
5315 | */ | |
5316 | static void handle_simd_inse(DisasContext *s, int rd, int rn, | |
5317 | int imm4, int imm5) | |
5318 | { | |
5319 | int size = ctz32(imm5); | |
5320 | int src_index, dst_index; | |
5321 | TCGv_i64 tmp; | |
5322 | ||
5323 | if (size > 3) { | |
5324 | unallocated_encoding(s); | |
5325 | return; | |
5326 | } | |
5327 | dst_index = extract32(imm5, 1+size, 5); | |
5328 | src_index = extract32(imm4, size, 4); | |
5329 | ||
5330 | tmp = tcg_temp_new_i64(); | |
5331 | ||
5332 | read_vec_element(s, tmp, rn, src_index, size); | |
5333 | write_vec_element(s, tmp, rd, dst_index, size); | |
5334 | ||
5335 | tcg_temp_free_i64(tmp); | |
5336 | } | |
5337 | ||
5338 | ||
5339 | /* C6.3.151 INS (General) | |
5340 | * | |
5341 | * 31 21 20 16 15 10 9 5 4 0 | |
5342 | * +-----------------------+--------+-------------+------+------+ | |
5343 | * | 0 1 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 0 1 1 1 | Rn | Rd | | |
5344 | * +-----------------------+--------+-------------+------+------+ | |
5345 | * | |
5346 | * size: encoded in imm5 (see ARM ARM LowestSetBit()) | |
5347 | * index: encoded in imm5<4:size+1> | |
5348 | */ | |
5349 | static void handle_simd_insg(DisasContext *s, int rd, int rn, int imm5) | |
5350 | { | |
5351 | int size = ctz32(imm5); | |
5352 | int idx; | |
5353 | ||
5354 | if (size > 3) { | |
5355 | unallocated_encoding(s); | |
5356 | return; | |
5357 | } | |
5358 | ||
5359 | idx = extract32(imm5, 1 + size, 4 - size); | |
5360 | write_vec_element(s, cpu_reg(s, rn), rd, idx, size); | |
5361 | } | |
5362 | ||
5363 | /* | |
5364 | * C6.3.321 UMOV (General) | |
5365 | * C6.3.237 SMOV (General) | |
5366 | * | |
5367 | * 31 30 29 21 20 16 15 12 10 9 5 4 0 | |
5368 | * +---+---+-------------------+--------+-------------+------+------+ | |
5369 | * | 0 | Q | 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 1 U 1 1 | Rn | Rd | | |
5370 | * +---+---+-------------------+--------+-------------+------+------+ | |
5371 | * | |
5372 | * U: unsigned when set | |
5373 | * size: encoded in imm5 (see ARM ARM LowestSetBit()) | |
5374 | */ | |
5375 | static void handle_simd_umov_smov(DisasContext *s, int is_q, int is_signed, | |
5376 | int rn, int rd, int imm5) | |
5377 | { | |
5378 | int size = ctz32(imm5); | |
5379 | int element; | |
5380 | TCGv_i64 tcg_rd; | |
5381 | ||
5382 | /* Check for UnallocatedEncodings */ | |
5383 | if (is_signed) { | |
5384 | if (size > 2 || (size == 2 && !is_q)) { | |
5385 | unallocated_encoding(s); | |
5386 | return; | |
5387 | } | |
5388 | } else { | |
5389 | if (size > 3 | |
5390 | || (size < 3 && is_q) | |
5391 | || (size == 3 && !is_q)) { | |
5392 | unallocated_encoding(s); | |
5393 | return; | |
5394 | } | |
5395 | } | |
5396 | element = extract32(imm5, 1+size, 4); | |
5397 | ||
5398 | tcg_rd = cpu_reg(s, rd); | |
5399 | read_vec_element(s, tcg_rd, rn, element, size | (is_signed ? MO_SIGN : 0)); | |
5400 | if (is_signed && !is_q) { | |
5401 | tcg_gen_ext32u_i64(tcg_rd, tcg_rd); | |
5402 | } | |
5403 | } | |
5404 | ||
384b26fb AB |
5405 | /* C3.6.5 AdvSIMD copy |
5406 | * 31 30 29 28 21 20 16 15 14 11 10 9 5 4 0 | |
5407 | * +---+---+----+-----------------+------+---+------+---+------+------+ | |
5408 | * | 0 | Q | op | 0 1 1 1 0 0 0 0 | imm5 | 0 | imm4 | 1 | Rn | Rd | | |
5409 | * +---+---+----+-----------------+------+---+------+---+------+------+ | |
5410 | */ | |
5411 | static void disas_simd_copy(DisasContext *s, uint32_t insn) | |
5412 | { | |
67bb9389 AB |
5413 | int rd = extract32(insn, 0, 5); |
5414 | int rn = extract32(insn, 5, 5); | |
5415 | int imm4 = extract32(insn, 11, 4); | |
5416 | int op = extract32(insn, 29, 1); | |
5417 | int is_q = extract32(insn, 30, 1); | |
5418 | int imm5 = extract32(insn, 16, 5); | |
5419 | ||
5420 | if (op) { | |
5421 | if (is_q) { | |
5422 | /* INS (element) */ | |
5423 | handle_simd_inse(s, rd, rn, imm4, imm5); | |
5424 | } else { | |
5425 | unallocated_encoding(s); | |
5426 | } | |
5427 | } else { | |
5428 | switch (imm4) { | |
5429 | case 0: | |
5430 | /* DUP (element - vector) */ | |
5431 | handle_simd_dupe(s, is_q, rd, rn, imm5); | |
5432 | break; | |
5433 | case 1: | |
5434 | /* DUP (general) */ | |
5435 | handle_simd_dupg(s, is_q, rd, rn, imm5); | |
5436 | break; | |
5437 | case 3: | |
5438 | if (is_q) { | |
5439 | /* INS (general) */ | |
5440 | handle_simd_insg(s, rd, rn, imm5); | |
5441 | } else { | |
5442 | unallocated_encoding(s); | |
5443 | } | |
5444 | break; | |
5445 | case 5: | |
5446 | case 7: | |
5447 | /* UMOV/SMOV (is_q indicates 32/64; imm4 indicates signedness) */ | |
5448 | handle_simd_umov_smov(s, is_q, (imm4 == 5), rn, rd, imm5); | |
5449 | break; | |
5450 | default: | |
5451 | unallocated_encoding(s); | |
5452 | break; | |
5453 | } | |
5454 | } | |
384b26fb AB |
5455 | } |
5456 | ||
5457 | /* C3.6.6 AdvSIMD modified immediate | |
5458 | * 31 30 29 28 19 18 16 15 12 11 10 9 5 4 0 | |
5459 | * +---+---+----+---------------------+-----+-------+----+---+-------+------+ | |
5460 | * | 0 | Q | op | 0 1 1 1 1 0 0 0 0 0 | abc | cmode | o2 | 1 | defgh | Rd | | |
5461 | * +---+---+----+---------------------+-----+-------+----+---+-------+------+ | |
f3f8c4f4 AB |
5462 | * |
5463 | * There are a number of operations that can be carried out here: | |
5464 | * MOVI - move (shifted) imm into register | |
5465 | * MVNI - move inverted (shifted) imm into register | |
5466 | * ORR - bitwise OR of (shifted) imm with register | |
5467 | * BIC - bitwise clear of (shifted) imm with register | |
384b26fb AB |
5468 | */ |
5469 | static void disas_simd_mod_imm(DisasContext *s, uint32_t insn) | |
5470 | { | |
f3f8c4f4 AB |
5471 | int rd = extract32(insn, 0, 5); |
5472 | int cmode = extract32(insn, 12, 4); | |
5473 | int cmode_3_1 = extract32(cmode, 1, 3); | |
5474 | int cmode_0 = extract32(cmode, 0, 1); | |
5475 | int o2 = extract32(insn, 11, 1); | |
5476 | uint64_t abcdefgh = extract32(insn, 5, 5) | (extract32(insn, 16, 3) << 5); | |
5477 | bool is_neg = extract32(insn, 29, 1); | |
5478 | bool is_q = extract32(insn, 30, 1); | |
5479 | uint64_t imm = 0; | |
5480 | TCGv_i64 tcg_rd, tcg_imm; | |
5481 | int i; | |
5482 | ||
5483 | if (o2 != 0 || ((cmode == 0xf) && is_neg && !is_q)) { | |
5484 | unallocated_encoding(s); | |
5485 | return; | |
5486 | } | |
5487 | ||
5488 | /* See AdvSIMDExpandImm() in ARM ARM */ | |
5489 | switch (cmode_3_1) { | |
5490 | case 0: /* Replicate(Zeros(24):imm8, 2) */ | |
5491 | case 1: /* Replicate(Zeros(16):imm8:Zeros(8), 2) */ | |
5492 | case 2: /* Replicate(Zeros(8):imm8:Zeros(16), 2) */ | |
5493 | case 3: /* Replicate(imm8:Zeros(24), 2) */ | |
5494 | { | |
5495 | int shift = cmode_3_1 * 8; | |
5496 | imm = bitfield_replicate(abcdefgh << shift, 32); | |
5497 | break; | |
5498 | } | |
5499 | case 4: /* Replicate(Zeros(8):imm8, 4) */ | |
5500 | case 5: /* Replicate(imm8:Zeros(8), 4) */ | |
5501 | { | |
5502 | int shift = (cmode_3_1 & 0x1) * 8; | |
5503 | imm = bitfield_replicate(abcdefgh << shift, 16); | |
5504 | break; | |
5505 | } | |
5506 | case 6: | |
5507 | if (cmode_0) { | |
5508 | /* Replicate(Zeros(8):imm8:Ones(16), 2) */ | |
5509 | imm = (abcdefgh << 16) | 0xffff; | |
5510 | } else { | |
5511 | /* Replicate(Zeros(16):imm8:Ones(8), 2) */ | |
5512 | imm = (abcdefgh << 8) | 0xff; | |
5513 | } | |
5514 | imm = bitfield_replicate(imm, 32); | |
5515 | break; | |
5516 | case 7: | |
5517 | if (!cmode_0 && !is_neg) { | |
5518 | imm = bitfield_replicate(abcdefgh, 8); | |
5519 | } else if (!cmode_0 && is_neg) { | |
5520 | int i; | |
5521 | imm = 0; | |
5522 | for (i = 0; i < 8; i++) { | |
5523 | if ((abcdefgh) & (1 << i)) { | |
5524 | imm |= 0xffULL << (i * 8); | |
5525 | } | |
5526 | } | |
5527 | } else if (cmode_0) { | |
5528 | if (is_neg) { | |
5529 | imm = (abcdefgh & 0x3f) << 48; | |
5530 | if (abcdefgh & 0x80) { | |
5531 | imm |= 0x8000000000000000ULL; | |
5532 | } | |
5533 | if (abcdefgh & 0x40) { | |
5534 | imm |= 0x3fc0000000000000ULL; | |
5535 | } else { | |
5536 | imm |= 0x4000000000000000ULL; | |
5537 | } | |
5538 | } else { | |
5539 | imm = (abcdefgh & 0x3f) << 19; | |
5540 | if (abcdefgh & 0x80) { | |
5541 | imm |= 0x80000000; | |
5542 | } | |
5543 | if (abcdefgh & 0x40) { | |
5544 | imm |= 0x3e000000; | |
5545 | } else { | |
5546 | imm |= 0x40000000; | |
5547 | } | |
5548 | imm |= (imm << 32); | |
5549 | } | |
5550 | } | |
5551 | break; | |
5552 | } | |
5553 | ||
5554 | if (cmode_3_1 != 7 && is_neg) { | |
5555 | imm = ~imm; | |
5556 | } | |
5557 | ||
5558 | tcg_imm = tcg_const_i64(imm); | |
5559 | tcg_rd = new_tmp_a64(s); | |
5560 | ||
5561 | for (i = 0; i < 2; i++) { | |
5562 | int foffs = i ? fp_reg_hi_offset(rd) : fp_reg_offset(rd, MO_64); | |
5563 | ||
5564 | if (i == 1 && !is_q) { | |
5565 | /* non-quad ops clear high half of vector */ | |
5566 | tcg_gen_movi_i64(tcg_rd, 0); | |
5567 | } else if ((cmode & 0x9) == 0x1 || (cmode & 0xd) == 0x9) { | |
5568 | tcg_gen_ld_i64(tcg_rd, cpu_env, foffs); | |
5569 | if (is_neg) { | |
5570 | /* AND (BIC) */ | |
5571 | tcg_gen_and_i64(tcg_rd, tcg_rd, tcg_imm); | |
5572 | } else { | |
5573 | /* ORR */ | |
5574 | tcg_gen_or_i64(tcg_rd, tcg_rd, tcg_imm); | |
5575 | } | |
5576 | } else { | |
5577 | /* MOVI */ | |
5578 | tcg_gen_mov_i64(tcg_rd, tcg_imm); | |
5579 | } | |
5580 | tcg_gen_st_i64(tcg_rd, cpu_env, foffs); | |
5581 | } | |
5582 | ||
5583 | tcg_temp_free_i64(tcg_imm); | |
384b26fb AB |
5584 | } |
5585 | ||
5586 | /* C3.6.7 AdvSIMD scalar copy | |
5587 | * 31 30 29 28 21 20 16 15 14 11 10 9 5 4 0 | |
5588 | * +-----+----+-----------------+------+---+------+---+------+------+ | |
5589 | * | 0 1 | op | 1 1 1 1 0 0 0 0 | imm5 | 0 | imm4 | 1 | Rn | Rd | | |
5590 | * +-----+----+-----------------+------+---+------+---+------+------+ | |
5591 | */ | |
5592 | static void disas_simd_scalar_copy(DisasContext *s, uint32_t insn) | |
5593 | { | |
360a6f2d PM |
5594 | int rd = extract32(insn, 0, 5); |
5595 | int rn = extract32(insn, 5, 5); | |
5596 | int imm4 = extract32(insn, 11, 4); | |
5597 | int imm5 = extract32(insn, 16, 5); | |
5598 | int op = extract32(insn, 29, 1); | |
5599 | ||
5600 | if (op != 0 || imm4 != 0) { | |
5601 | unallocated_encoding(s); | |
5602 | return; | |
5603 | } | |
5604 | ||
5605 | /* DUP (element, scalar) */ | |
5606 | handle_simd_dupes(s, rd, rn, imm5); | |
384b26fb AB |
5607 | } |
5608 | ||
5609 | /* C3.6.8 AdvSIMD scalar pairwise | |
5610 | * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0 | |
5611 | * +-----+---+-----------+------+-----------+--------+-----+------+------+ | |
5612 | * | 0 1 | U | 1 1 1 1 0 | size | 1 1 0 0 0 | opcode | 1 0 | Rn | Rd | | |
5613 | * +-----+---+-----------+------+-----------+--------+-----+------+------+ | |
5614 | */ | |
5615 | static void disas_simd_scalar_pairwise(DisasContext *s, uint32_t insn) | |
5616 | { | |
3720a7ea PM |
5617 | int u = extract32(insn, 29, 1); |
5618 | int size = extract32(insn, 22, 2); | |
5619 | int opcode = extract32(insn, 12, 5); | |
5620 | int rn = extract32(insn, 5, 5); | |
5621 | int rd = extract32(insn, 0, 5); | |
5622 | TCGv_ptr fpst; | |
5623 | ||
5624 | /* For some ops (the FP ones), size[1] is part of the encoding. | |
5625 | * For ADDP strictly it is not but size[1] is always 1 for valid | |
5626 | * encodings. | |
5627 | */ | |
5628 | opcode |= (extract32(size, 1, 1) << 5); | |
5629 | ||
5630 | switch (opcode) { | |
5631 | case 0x3b: /* ADDP */ | |
5632 | if (u || size != 3) { | |
5633 | unallocated_encoding(s); | |
5634 | return; | |
5635 | } | |
5636 | TCGV_UNUSED_PTR(fpst); | |
5637 | break; | |
5638 | case 0xc: /* FMAXNMP */ | |
5639 | case 0xd: /* FADDP */ | |
5640 | case 0xf: /* FMAXP */ | |
5641 | case 0x2c: /* FMINNMP */ | |
5642 | case 0x2f: /* FMINP */ | |
5643 | /* FP op, size[0] is 32 or 64 bit */ | |
5644 | if (!u) { | |
5645 | unallocated_encoding(s); | |
5646 | return; | |
5647 | } | |
5648 | size = extract32(size, 0, 1) ? 3 : 2; | |
5649 | fpst = get_fpstatus_ptr(); | |
5650 | break; | |
5651 | default: | |
5652 | unallocated_encoding(s); | |
5653 | return; | |
5654 | } | |
5655 | ||
5656 | if (size == 3) { | |
5657 | TCGv_i64 tcg_op1 = tcg_temp_new_i64(); | |
5658 | TCGv_i64 tcg_op2 = tcg_temp_new_i64(); | |
5659 | TCGv_i64 tcg_res = tcg_temp_new_i64(); | |
5660 | ||
5661 | read_vec_element(s, tcg_op1, rn, 0, MO_64); | |
5662 | read_vec_element(s, tcg_op2, rn, 1, MO_64); | |
5663 | ||
5664 | switch (opcode) { | |
5665 | case 0x3b: /* ADDP */ | |
5666 | tcg_gen_add_i64(tcg_res, tcg_op1, tcg_op2); | |
5667 | break; | |
5668 | case 0xc: /* FMAXNMP */ | |
5669 | gen_helper_vfp_maxnumd(tcg_res, tcg_op1, tcg_op2, fpst); | |
5670 | break; | |
5671 | case 0xd: /* FADDP */ | |
5672 | gen_helper_vfp_addd(tcg_res, tcg_op1, tcg_op2, fpst); | |
5673 | break; | |
5674 | case 0xf: /* FMAXP */ | |
5675 | gen_helper_vfp_maxd(tcg_res, tcg_op1, tcg_op2, fpst); | |
5676 | break; | |
5677 | case 0x2c: /* FMINNMP */ | |
5678 | gen_helper_vfp_minnumd(tcg_res, tcg_op1, tcg_op2, fpst); | |
5679 | break; | |
5680 | case 0x2f: /* FMINP */ | |
5681 | gen_helper_vfp_mind(tcg_res, tcg_op1, tcg_op2, fpst); | |
5682 | break; | |
5683 | default: | |
5684 | g_assert_not_reached(); | |
5685 | } | |
5686 | ||
5687 | write_fp_dreg(s, rd, tcg_res); | |
5688 | ||
5689 | tcg_temp_free_i64(tcg_op1); | |
5690 | tcg_temp_free_i64(tcg_op2); | |
5691 | tcg_temp_free_i64(tcg_res); | |
5692 | } else { | |
5693 | TCGv_i32 tcg_op1 = tcg_temp_new_i32(); | |
5694 | TCGv_i32 tcg_op2 = tcg_temp_new_i32(); | |
5695 | TCGv_i32 tcg_res = tcg_temp_new_i32(); | |
5696 | ||
5697 | read_vec_element_i32(s, tcg_op1, rn, 0, MO_32); | |
5698 | read_vec_element_i32(s, tcg_op2, rn, 1, MO_32); | |
5699 | ||
5700 | switch (opcode) { | |
5701 | case 0xc: /* FMAXNMP */ | |
5702 | gen_helper_vfp_maxnums(tcg_res, tcg_op1, tcg_op2, fpst); | |
5703 | break; | |
5704 | case 0xd: /* FADDP */ | |
5705 | gen_helper_vfp_adds(tcg_res, tcg_op1, tcg_op2, fpst); | |
5706 | break; | |
5707 | case 0xf: /* FMAXP */ | |
5708 | gen_helper_vfp_maxs(tcg_res, tcg_op1, tcg_op2, fpst); | |
5709 | break; | |
5710 | case 0x2c: /* FMINNMP */ | |
5711 | gen_helper_vfp_minnums(tcg_res, tcg_op1, tcg_op2, fpst); | |
5712 | break; | |
5713 | case 0x2f: /* FMINP */ | |
5714 | gen_helper_vfp_mins(tcg_res, tcg_op1, tcg_op2, fpst); | |
5715 | break; | |
5716 | default: | |
5717 | g_assert_not_reached(); | |
5718 | } | |
5719 | ||
5720 | write_fp_sreg(s, rd, tcg_res); | |
5721 | ||
5722 | tcg_temp_free_i32(tcg_op1); | |
5723 | tcg_temp_free_i32(tcg_op2); | |
5724 | tcg_temp_free_i32(tcg_res); | |
5725 | } | |
5726 | ||
5727 | if (!TCGV_IS_UNUSED_PTR(fpst)) { | |
5728 | tcg_temp_free_ptr(fpst); | |
5729 | } | |
384b26fb AB |
5730 | } |
5731 | ||
4d1cef84 AB |
5732 | /* |
5733 | * Common SSHR[RA]/USHR[RA] - Shift right (optional rounding/accumulate) | |
5734 | * | |
5735 | * This code is handles the common shifting code and is used by both | |
5736 | * the vector and scalar code. | |
5737 | */ | |
5738 | static void handle_shri_with_rndacc(TCGv_i64 tcg_res, TCGv_i64 tcg_src, | |
5739 | TCGv_i64 tcg_rnd, bool accumulate, | |
5740 | bool is_u, int size, int shift) | |
5741 | { | |
5742 | bool extended_result = false; | |
5743 | bool round = !TCGV_IS_UNUSED_I64(tcg_rnd); | |
5744 | int ext_lshift = 0; | |
5745 | TCGv_i64 tcg_src_hi; | |
5746 | ||
5747 | if (round && size == 3) { | |
5748 | extended_result = true; | |
5749 | ext_lshift = 64 - shift; | |
5750 | tcg_src_hi = tcg_temp_new_i64(); | |
5751 | } else if (shift == 64) { | |
5752 | if (!accumulate && is_u) { | |
5753 | /* result is zero */ | |
5754 | tcg_gen_movi_i64(tcg_res, 0); | |
5755 | return; | |
5756 | } | |
5757 | } | |
5758 | ||
5759 | /* Deal with the rounding step */ | |
5760 | if (round) { | |
5761 | if (extended_result) { | |
5762 | TCGv_i64 tcg_zero = tcg_const_i64(0); | |
5763 | if (!is_u) { | |
5764 | /* take care of sign extending tcg_res */ | |
5765 | tcg_gen_sari_i64(tcg_src_hi, tcg_src, 63); | |
5766 | tcg_gen_add2_i64(tcg_src, tcg_src_hi, | |
5767 | tcg_src, tcg_src_hi, | |
5768 | tcg_rnd, tcg_zero); | |
5769 | } else { | |
5770 | tcg_gen_add2_i64(tcg_src, tcg_src_hi, | |
5771 | tcg_src, tcg_zero, | |
5772 | tcg_rnd, tcg_zero); | |
5773 | } | |
5774 | tcg_temp_free_i64(tcg_zero); | |
5775 | } else { | |
5776 | tcg_gen_add_i64(tcg_src, tcg_src, tcg_rnd); | |
5777 | } | |
5778 | } | |
5779 | ||
5780 | /* Now do the shift right */ | |
5781 | if (round && extended_result) { | |
5782 | /* extended case, >64 bit precision required */ | |
5783 | if (ext_lshift == 0) { | |
5784 | /* special case, only high bits matter */ | |
5785 | tcg_gen_mov_i64(tcg_src, tcg_src_hi); | |
5786 | } else { | |
5787 | tcg_gen_shri_i64(tcg_src, tcg_src, shift); | |
5788 | tcg_gen_shli_i64(tcg_src_hi, tcg_src_hi, ext_lshift); | |
5789 | tcg_gen_or_i64(tcg_src, tcg_src, tcg_src_hi); | |
5790 | } | |
5791 | } else { | |
5792 | if (is_u) { | |
5793 | if (shift == 64) { | |
5794 | /* essentially shifting in 64 zeros */ | |
5795 | tcg_gen_movi_i64(tcg_src, 0); | |
5796 | } else { | |
5797 | tcg_gen_shri_i64(tcg_src, tcg_src, shift); | |
5798 | } | |
5799 | } else { | |
5800 | if (shift == 64) { | |
5801 | /* effectively extending the sign-bit */ | |
5802 | tcg_gen_sari_i64(tcg_src, tcg_src, 63); | |
5803 | } else { | |
5804 | tcg_gen_sari_i64(tcg_src, tcg_src, shift); | |
5805 | } | |
5806 | } | |
5807 | } | |
5808 | ||
5809 | if (accumulate) { | |
5810 | tcg_gen_add_i64(tcg_res, tcg_res, tcg_src); | |
5811 | } else { | |
5812 | tcg_gen_mov_i64(tcg_res, tcg_src); | |
5813 | } | |
5814 | ||
5815 | if (extended_result) { | |
5816 | tcg_temp_free_i64(tcg_src_hi); | |
5817 | } | |
5818 | } | |
5819 | ||
5820 | /* Common SHL/SLI - Shift left with an optional insert */ | |
5821 | static void handle_shli_with_ins(TCGv_i64 tcg_res, TCGv_i64 tcg_src, | |
5822 | bool insert, int shift) | |
5823 | { | |
5824 | if (insert) { /* SLI */ | |
5825 | tcg_gen_deposit_i64(tcg_res, tcg_res, tcg_src, shift, 64 - shift); | |
5826 | } else { /* SHL */ | |
5827 | tcg_gen_shli_i64(tcg_res, tcg_src, shift); | |
5828 | } | |
5829 | } | |
5830 | ||
5831 | /* SSHR[RA]/USHR[RA] - Scalar shift right (optional rounding/accumulate) */ | |
5832 | static void handle_scalar_simd_shri(DisasContext *s, | |
5833 | bool is_u, int immh, int immb, | |
5834 | int opcode, int rn, int rd) | |
5835 | { | |
5836 | const int size = 3; | |
5837 | int immhb = immh << 3 | immb; | |
5838 | int shift = 2 * (8 << size) - immhb; | |
5839 | bool accumulate = false; | |
5840 | bool round = false; | |
5841 | TCGv_i64 tcg_rn; | |
5842 | TCGv_i64 tcg_rd; | |
5843 | TCGv_i64 tcg_round; | |
5844 | ||
5845 | if (!extract32(immh, 3, 1)) { | |
5846 | unallocated_encoding(s); | |
5847 | return; | |
5848 | } | |
5849 | ||
5850 | switch (opcode) { | |
5851 | case 0x02: /* SSRA / USRA (accumulate) */ | |
5852 | accumulate = true; | |
5853 | break; | |
5854 | case 0x04: /* SRSHR / URSHR (rounding) */ | |
5855 | round = true; | |
5856 | break; | |
5857 | case 0x06: /* SRSRA / URSRA (accum + rounding) */ | |
5858 | accumulate = round = true; | |
5859 | break; | |
5860 | } | |
5861 | ||
5862 | if (round) { | |
5863 | uint64_t round_const = 1ULL << (shift - 1); | |
5864 | tcg_round = tcg_const_i64(round_const); | |
5865 | } else { | |
5866 | TCGV_UNUSED_I64(tcg_round); | |
5867 | } | |
5868 | ||
5869 | tcg_rn = read_fp_dreg(s, rn); | |
5870 | tcg_rd = accumulate ? read_fp_dreg(s, rd) : tcg_temp_new_i64(); | |
5871 | ||
5872 | handle_shri_with_rndacc(tcg_rd, tcg_rn, tcg_round, | |
5873 | accumulate, is_u, size, shift); | |
5874 | ||
5875 | write_fp_dreg(s, rd, tcg_rd); | |
5876 | ||
5877 | tcg_temp_free_i64(tcg_rn); | |
5878 | tcg_temp_free_i64(tcg_rd); | |
5879 | if (round) { | |
5880 | tcg_temp_free_i64(tcg_round); | |
5881 | } | |
5882 | } | |
5883 | ||
5884 | /* SHL/SLI - Scalar shift left */ | |
5885 | static void handle_scalar_simd_shli(DisasContext *s, bool insert, | |
5886 | int immh, int immb, int opcode, | |
5887 | int rn, int rd) | |
5888 | { | |
5889 | int size = 32 - clz32(immh) - 1; | |
5890 | int immhb = immh << 3 | immb; | |
5891 | int shift = immhb - (8 << size); | |
5892 | TCGv_i64 tcg_rn = new_tmp_a64(s); | |
5893 | TCGv_i64 tcg_rd = new_tmp_a64(s); | |
5894 | ||
5895 | if (!extract32(immh, 3, 1)) { | |
5896 | unallocated_encoding(s); | |
5897 | return; | |
5898 | } | |
5899 | ||
5900 | tcg_rn = read_fp_dreg(s, rn); | |
5901 | tcg_rd = insert ? read_fp_dreg(s, rd) : tcg_temp_new_i64(); | |
5902 | ||
5903 | handle_shli_with_ins(tcg_rd, tcg_rn, insert, shift); | |
5904 | ||
5905 | write_fp_dreg(s, rd, tcg_rd); | |
5906 | ||
5907 | tcg_temp_free_i64(tcg_rn); | |
5908 | tcg_temp_free_i64(tcg_rd); | |
5909 | } | |
5910 | ||
384b26fb AB |
5911 | /* C3.6.9 AdvSIMD scalar shift by immediate |
5912 | * 31 30 29 28 23 22 19 18 16 15 11 10 9 5 4 0 | |
5913 | * +-----+---+-------------+------+------+--------+---+------+------+ | |
5914 | * | 0 1 | U | 1 1 1 1 1 0 | immh | immb | opcode | 1 | Rn | Rd | | |
5915 | * +-----+---+-------------+------+------+--------+---+------+------+ | |
4d1cef84 AB |
5916 | * |
5917 | * This is the scalar version so it works on a fixed sized registers | |
384b26fb AB |
5918 | */ |
5919 | static void disas_simd_scalar_shift_imm(DisasContext *s, uint32_t insn) | |
5920 | { | |
4d1cef84 AB |
5921 | int rd = extract32(insn, 0, 5); |
5922 | int rn = extract32(insn, 5, 5); | |
5923 | int opcode = extract32(insn, 11, 5); | |
5924 | int immb = extract32(insn, 16, 3); | |
5925 | int immh = extract32(insn, 19, 4); | |
5926 | bool is_u = extract32(insn, 29, 1); | |
5927 | ||
5928 | switch (opcode) { | |
5929 | case 0x00: /* SSHR / USHR */ | |
5930 | case 0x02: /* SSRA / USRA */ | |
5931 | case 0x04: /* SRSHR / URSHR */ | |
5932 | case 0x06: /* SRSRA / URSRA */ | |
5933 | handle_scalar_simd_shri(s, is_u, immh, immb, opcode, rn, rd); | |
5934 | break; | |
5935 | case 0x0a: /* SHL / SLI */ | |
5936 | handle_scalar_simd_shli(s, is_u, immh, immb, opcode, rn, rd); | |
5937 | break; | |
5938 | default: | |
5939 | unsupported_encoding(s, insn); | |
5940 | break; | |
5941 | } | |
384b26fb AB |
5942 | } |
5943 | ||
5944 | /* C3.6.10 AdvSIMD scalar three different | |
5945 | * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0 | |
5946 | * +-----+---+-----------+------+---+------+--------+-----+------+------+ | |
5947 | * | 0 1 | U | 1 1 1 1 0 | size | 1 | Rm | opcode | 0 0 | Rn | Rd | | |
5948 | * +-----+---+-----------+------+---+------+--------+-----+------+------+ | |
5949 | */ | |
5950 | static void disas_simd_scalar_three_reg_diff(DisasContext *s, uint32_t insn) | |
5951 | { | |
b033cd3d PM |
5952 | bool is_u = extract32(insn, 29, 1); |
5953 | int size = extract32(insn, 22, 2); | |
5954 | int opcode = extract32(insn, 12, 4); | |
5955 | int rm = extract32(insn, 16, 5); | |
5956 | int rn = extract32(insn, 5, 5); | |
5957 | int rd = extract32(insn, 0, 5); | |
5958 | ||
5959 | if (is_u) { | |
5960 | unallocated_encoding(s); | |
5961 | return; | |
5962 | } | |
5963 | ||
5964 | switch (opcode) { | |
5965 | case 0x9: /* SQDMLAL, SQDMLAL2 */ | |
5966 | case 0xb: /* SQDMLSL, SQDMLSL2 */ | |
5967 | case 0xd: /* SQDMULL, SQDMULL2 */ | |
5968 | if (size == 0 || size == 3) { | |
5969 | unallocated_encoding(s); | |
5970 | return; | |
5971 | } | |
5972 | break; | |
5973 | default: | |
5974 | unallocated_encoding(s); | |
5975 | return; | |
5976 | } | |
5977 | ||
5978 | if (size == 2) { | |
5979 | TCGv_i64 tcg_op1 = tcg_temp_new_i64(); | |
5980 | TCGv_i64 tcg_op2 = tcg_temp_new_i64(); | |
5981 | TCGv_i64 tcg_res = tcg_temp_new_i64(); | |
5982 | ||
5983 | read_vec_element(s, tcg_op1, rn, 0, MO_32 | MO_SIGN); | |
5984 | read_vec_element(s, tcg_op2, rm, 0, MO_32 | MO_SIGN); | |
5985 | ||
5986 | tcg_gen_mul_i64(tcg_res, tcg_op1, tcg_op2); | |
5987 | gen_helper_neon_addl_saturate_s64(tcg_res, cpu_env, tcg_res, tcg_res); | |
5988 | ||
5989 | switch (opcode) { | |
5990 | case 0xd: /* SQDMULL, SQDMULL2 */ | |
5991 | break; | |
5992 | case 0xb: /* SQDMLSL, SQDMLSL2 */ | |
5993 | tcg_gen_neg_i64(tcg_res, tcg_res); | |
5994 | /* fall through */ | |
5995 | case 0x9: /* SQDMLAL, SQDMLAL2 */ | |
5996 | read_vec_element(s, tcg_op1, rd, 0, MO_64); | |
5997 | gen_helper_neon_addl_saturate_s64(tcg_res, cpu_env, | |
5998 | tcg_res, tcg_op1); | |
5999 | break; | |
6000 | default: | |
6001 | g_assert_not_reached(); | |
6002 | } | |
6003 | ||
6004 | write_fp_dreg(s, rd, tcg_res); | |
6005 | ||
6006 | tcg_temp_free_i64(tcg_op1); | |
6007 | tcg_temp_free_i64(tcg_op2); | |
6008 | tcg_temp_free_i64(tcg_res); | |
6009 | } else { | |
6010 | TCGv_i32 tcg_op1 = tcg_temp_new_i32(); | |
6011 | TCGv_i32 tcg_op2 = tcg_temp_new_i32(); | |
6012 | TCGv_i64 tcg_res = tcg_temp_new_i64(); | |
6013 | ||
6014 | read_vec_element_i32(s, tcg_op1, rn, 0, MO_16); | |
6015 | read_vec_element_i32(s, tcg_op2, rm, 0, MO_16); | |
6016 | ||
6017 | gen_helper_neon_mull_s16(tcg_res, tcg_op1, tcg_op2); | |
6018 | gen_helper_neon_addl_saturate_s32(tcg_res, cpu_env, tcg_res, tcg_res); | |
6019 | ||
6020 | switch (opcode) { | |
6021 | case 0xd: /* SQDMULL, SQDMULL2 */ | |
6022 | break; | |
6023 | case 0xb: /* SQDMLSL, SQDMLSL2 */ | |
6024 | gen_helper_neon_negl_u32(tcg_res, tcg_res); | |
6025 | /* fall through */ | |
6026 | case 0x9: /* SQDMLAL, SQDMLAL2 */ | |
6027 | { | |
6028 | TCGv_i64 tcg_op3 = tcg_temp_new_i64(); | |
6029 | read_vec_element(s, tcg_op3, rd, 0, MO_32); | |
6030 | gen_helper_neon_addl_saturate_s32(tcg_res, cpu_env, | |
6031 | tcg_res, tcg_op3); | |
6032 | tcg_temp_free_i64(tcg_op3); | |
6033 | break; | |
6034 | } | |
6035 | default: | |
6036 | g_assert_not_reached(); | |
6037 | } | |
6038 | ||
6039 | tcg_gen_ext32u_i64(tcg_res, tcg_res); | |
6040 | write_fp_dreg(s, rd, tcg_res); | |
6041 | ||
6042 | tcg_temp_free_i32(tcg_op1); | |
6043 | tcg_temp_free_i32(tcg_op2); | |
6044 | tcg_temp_free_i64(tcg_res); | |
6045 | } | |
384b26fb AB |
6046 | } |
6047 | ||
b305dba6 PM |
6048 | static void handle_3same_64(DisasContext *s, int opcode, bool u, |
6049 | TCGv_i64 tcg_rd, TCGv_i64 tcg_rn, TCGv_i64 tcg_rm) | |
6050 | { | |
6051 | /* Handle 64x64->64 opcodes which are shared between the scalar | |
6052 | * and vector 3-same groups. We cover every opcode where size == 3 | |
6053 | * is valid in either the three-reg-same (integer, not pairwise) | |
6054 | * or scalar-three-reg-same groups. (Some opcodes are not yet | |
6055 | * implemented.) | |
6056 | */ | |
6057 | TCGCond cond; | |
6058 | ||
6059 | switch (opcode) { | |
6d9571f7 PM |
6060 | case 0x1: /* SQADD */ |
6061 | if (u) { | |
6062 | gen_helper_neon_qadd_u64(tcg_rd, cpu_env, tcg_rn, tcg_rm); | |
6063 | } else { | |
6064 | gen_helper_neon_qadd_s64(tcg_rd, cpu_env, tcg_rn, tcg_rm); | |
6065 | } | |
6066 | break; | |
6067 | case 0x5: /* SQSUB */ | |
6068 | if (u) { | |
6069 | gen_helper_neon_qsub_u64(tcg_rd, cpu_env, tcg_rn, tcg_rm); | |
6070 | } else { | |
6071 | gen_helper_neon_qsub_s64(tcg_rd, cpu_env, tcg_rn, tcg_rm); | |
6072 | } | |
6073 | break; | |
b305dba6 PM |
6074 | case 0x6: /* CMGT, CMHI */ |
6075 | /* 64 bit integer comparison, result = test ? (2^64 - 1) : 0. | |
6076 | * We implement this using setcond (test) and then negating. | |
6077 | */ | |
6078 | cond = u ? TCG_COND_GTU : TCG_COND_GT; | |
6079 | do_cmop: | |
6080 | tcg_gen_setcond_i64(cond, tcg_rd, tcg_rn, tcg_rm); | |
6081 | tcg_gen_neg_i64(tcg_rd, tcg_rd); | |
6082 | break; | |
6083 | case 0x7: /* CMGE, CMHS */ | |
6084 | cond = u ? TCG_COND_GEU : TCG_COND_GE; | |
6085 | goto do_cmop; | |
6086 | case 0x11: /* CMTST, CMEQ */ | |
6087 | if (u) { | |
6088 | cond = TCG_COND_EQ; | |
6089 | goto do_cmop; | |
6090 | } | |
6091 | /* CMTST : test is "if (X & Y != 0)". */ | |
6092 | tcg_gen_and_i64(tcg_rd, tcg_rn, tcg_rm); | |
6093 | tcg_gen_setcondi_i64(TCG_COND_NE, tcg_rd, tcg_rd, 0); | |
6094 | tcg_gen_neg_i64(tcg_rd, tcg_rd); | |
6095 | break; | |
6d9571f7 | 6096 | case 0x8: /* SSHL, USHL */ |
b305dba6 | 6097 | if (u) { |
6d9571f7 | 6098 | gen_helper_neon_shl_u64(tcg_rd, tcg_rn, tcg_rm); |
b305dba6 | 6099 | } else { |
6d9571f7 | 6100 | gen_helper_neon_shl_s64(tcg_rd, tcg_rn, tcg_rm); |
b305dba6 PM |
6101 | } |
6102 | break; | |
b305dba6 | 6103 | case 0x9: /* SQSHL, UQSHL */ |
6d9571f7 PM |
6104 | if (u) { |
6105 | gen_helper_neon_qshl_u64(tcg_rd, cpu_env, tcg_rn, tcg_rm); | |
6106 | } else { | |
6107 | gen_helper_neon_qshl_s64(tcg_rd, cpu_env, tcg_rn, tcg_rm); | |
6108 | } | |
6109 | break; | |
b305dba6 | 6110 | case 0xa: /* SRSHL, URSHL */ |
6d9571f7 PM |
6111 | if (u) { |
6112 | gen_helper_neon_rshl_u64(tcg_rd, tcg_rn, tcg_rm); | |
6113 | } else { | |
6114 | gen_helper_neon_rshl_s64(tcg_rd, tcg_rn, tcg_rm); | |
6115 | } | |
6116 | break; | |
b305dba6 | 6117 | case 0xb: /* SQRSHL, UQRSHL */ |
6d9571f7 PM |
6118 | if (u) { |
6119 | gen_helper_neon_qrshl_u64(tcg_rd, cpu_env, tcg_rn, tcg_rm); | |
6120 | } else { | |
6121 | gen_helper_neon_qrshl_s64(tcg_rd, cpu_env, tcg_rn, tcg_rm); | |
6122 | } | |
6123 | break; | |
6124 | case 0x10: /* ADD, SUB */ | |
6125 | if (u) { | |
6126 | tcg_gen_sub_i64(tcg_rd, tcg_rn, tcg_rm); | |
6127 | } else { | |
6128 | tcg_gen_add_i64(tcg_rd, tcg_rn, tcg_rm); | |
6129 | } | |
6130 | break; | |
b305dba6 PM |
6131 | default: |
6132 | g_assert_not_reached(); | |
6133 | } | |
6134 | } | |
6135 | ||
845ea09a PM |
6136 | /* Handle the 3-same-operands float operations; shared by the scalar |
6137 | * and vector encodings. The caller must filter out any encodings | |
6138 | * not allocated for the encoding it is dealing with. | |
6139 | */ | |
6140 | static void handle_3same_float(DisasContext *s, int size, int elements, | |
6141 | int fpopcode, int rd, int rn, int rm) | |
6142 | { | |
6143 | int pass; | |
6144 | TCGv_ptr fpst = get_fpstatus_ptr(); | |
6145 | ||
6146 | for (pass = 0; pass < elements; pass++) { | |
6147 | if (size) { | |
6148 | /* Double */ | |
6149 | TCGv_i64 tcg_op1 = tcg_temp_new_i64(); | |
6150 | TCGv_i64 tcg_op2 = tcg_temp_new_i64(); | |
6151 | TCGv_i64 tcg_res = tcg_temp_new_i64(); | |
6152 | ||
6153 | read_vec_element(s, tcg_op1, rn, pass, MO_64); | |
6154 | read_vec_element(s, tcg_op2, rm, pass, MO_64); | |
6155 | ||
6156 | switch (fpopcode) { | |
057d5f62 PM |
6157 | case 0x39: /* FMLS */ |
6158 | /* As usual for ARM, separate negation for fused multiply-add */ | |
6159 | gen_helper_vfp_negd(tcg_op1, tcg_op1); | |
6160 | /* fall through */ | |
6161 | case 0x19: /* FMLA */ | |
6162 | read_vec_element(s, tcg_res, rd, pass, MO_64); | |
6163 | gen_helper_vfp_muladdd(tcg_res, tcg_op1, tcg_op2, | |
6164 | tcg_res, fpst); | |
6165 | break; | |
845ea09a PM |
6166 | case 0x18: /* FMAXNM */ |
6167 | gen_helper_vfp_maxnumd(tcg_res, tcg_op1, tcg_op2, fpst); | |
6168 | break; | |
6169 | case 0x1a: /* FADD */ | |
6170 | gen_helper_vfp_addd(tcg_res, tcg_op1, tcg_op2, fpst); | |
6171 | break; | |
057d5f62 PM |
6172 | case 0x1b: /* FMULX */ |
6173 | gen_helper_vfp_mulxd(tcg_res, tcg_op1, tcg_op2, fpst); | |
6174 | break; | |
8908f4d1 AB |
6175 | case 0x1c: /* FCMEQ */ |
6176 | gen_helper_neon_ceq_f64(tcg_res, tcg_op1, tcg_op2, fpst); | |
6177 | break; | |
845ea09a PM |
6178 | case 0x1e: /* FMAX */ |
6179 | gen_helper_vfp_maxd(tcg_res, tcg_op1, tcg_op2, fpst); | |
6180 | break; | |
057d5f62 PM |
6181 | case 0x1f: /* FRECPS */ |
6182 | gen_helper_recpsf_f64(tcg_res, tcg_op1, tcg_op2, fpst); | |
6183 | break; | |
845ea09a PM |
6184 | case 0x38: /* FMINNM */ |
6185 | gen_helper_vfp_minnumd(tcg_res, tcg_op1, tcg_op2, fpst); | |
6186 | break; | |
6187 | case 0x3a: /* FSUB */ | |
6188 | gen_helper_vfp_subd(tcg_res, tcg_op1, tcg_op2, fpst); | |
6189 | break; | |
6190 | case 0x3e: /* FMIN */ | |
6191 | gen_helper_vfp_mind(tcg_res, tcg_op1, tcg_op2, fpst); | |
6192 | break; | |
057d5f62 PM |
6193 | case 0x3f: /* FRSQRTS */ |
6194 | gen_helper_rsqrtsf_f64(tcg_res, tcg_op1, tcg_op2, fpst); | |
6195 | break; | |
845ea09a PM |
6196 | case 0x5b: /* FMUL */ |
6197 | gen_helper_vfp_muld(tcg_res, tcg_op1, tcg_op2, fpst); | |
6198 | break; | |
8908f4d1 AB |
6199 | case 0x5c: /* FCMGE */ |
6200 | gen_helper_neon_cge_f64(tcg_res, tcg_op1, tcg_op2, fpst); | |
6201 | break; | |
057d5f62 PM |
6202 | case 0x5d: /* FACGE */ |
6203 | gen_helper_neon_acge_f64(tcg_res, tcg_op1, tcg_op2, fpst); | |
6204 | break; | |
845ea09a PM |
6205 | case 0x5f: /* FDIV */ |
6206 | gen_helper_vfp_divd(tcg_res, tcg_op1, tcg_op2, fpst); | |
6207 | break; | |
6208 | case 0x7a: /* FABD */ | |
6209 | gen_helper_vfp_subd(tcg_res, tcg_op1, tcg_op2, fpst); | |
6210 | gen_helper_vfp_absd(tcg_res, tcg_res); | |
6211 | break; | |
8908f4d1 AB |
6212 | case 0x7c: /* FCMGT */ |
6213 | gen_helper_neon_cgt_f64(tcg_res, tcg_op1, tcg_op2, fpst); | |
6214 | break; | |
057d5f62 PM |
6215 | case 0x7d: /* FACGT */ |
6216 | gen_helper_neon_acgt_f64(tcg_res, tcg_op1, tcg_op2, fpst); | |
6217 | break; | |
845ea09a PM |
6218 | default: |
6219 | g_assert_not_reached(); | |
6220 | } | |
6221 | ||
6222 | write_vec_element(s, tcg_res, rd, pass, MO_64); | |
6223 | ||
6224 | tcg_temp_free_i64(tcg_res); | |
6225 | tcg_temp_free_i64(tcg_op1); | |
6226 | tcg_temp_free_i64(tcg_op2); | |
6227 | } else { | |
6228 | /* Single */ | |
6229 | TCGv_i32 tcg_op1 = tcg_temp_new_i32(); | |
6230 | TCGv_i32 tcg_op2 = tcg_temp_new_i32(); | |
6231 | TCGv_i32 tcg_res = tcg_temp_new_i32(); | |
6232 | ||
6233 | read_vec_element_i32(s, tcg_op1, rn, pass, MO_32); | |
6234 | read_vec_element_i32(s, tcg_op2, rm, pass, MO_32); | |
6235 | ||
6236 | switch (fpopcode) { | |
057d5f62 PM |
6237 | case 0x39: /* FMLS */ |
6238 | /* As usual for ARM, separate negation for fused multiply-add */ | |
6239 | gen_helper_vfp_negs(tcg_op1, tcg_op1); | |
6240 | /* fall through */ | |
6241 | case 0x19: /* FMLA */ | |
6242 | read_vec_element_i32(s, tcg_res, rd, pass, MO_32); | |
6243 | gen_helper_vfp_muladds(tcg_res, tcg_op1, tcg_op2, | |
6244 | tcg_res, fpst); | |
6245 | break; | |
845ea09a PM |
6246 | case 0x1a: /* FADD */ |
6247 | gen_helper_vfp_adds(tcg_res, tcg_op1, tcg_op2, fpst); | |
6248 | break; | |
057d5f62 PM |
6249 | case 0x1b: /* FMULX */ |
6250 | gen_helper_vfp_mulxs(tcg_res, tcg_op1, tcg_op2, fpst); | |
6251 | break; | |
8908f4d1 AB |
6252 | case 0x1c: /* FCMEQ */ |
6253 | gen_helper_neon_ceq_f32(tcg_res, tcg_op1, tcg_op2, fpst); | |
6254 | break; | |
845ea09a PM |
6255 | case 0x1e: /* FMAX */ |
6256 | gen_helper_vfp_maxs(tcg_res, tcg_op1, tcg_op2, fpst); | |
6257 | break; | |
057d5f62 PM |
6258 | case 0x1f: /* FRECPS */ |
6259 | gen_helper_recpsf_f32(tcg_res, tcg_op1, tcg_op2, fpst); | |
6260 | break; | |
845ea09a PM |
6261 | case 0x18: /* FMAXNM */ |
6262 | gen_helper_vfp_maxnums(tcg_res, tcg_op1, tcg_op2, fpst); | |
6263 | break; | |
6264 | case 0x38: /* FMINNM */ | |
6265 | gen_helper_vfp_minnums(tcg_res, tcg_op1, tcg_op2, fpst); | |
6266 | break; | |
6267 | case 0x3a: /* FSUB */ | |
6268 | gen_helper_vfp_subs(tcg_res, tcg_op1, tcg_op2, fpst); | |
6269 | break; | |
6270 | case 0x3e: /* FMIN */ | |
6271 | gen_helper_vfp_mins(tcg_res, tcg_op1, tcg_op2, fpst); | |
6272 | break; | |
057d5f62 PM |
6273 | case 0x3f: /* FRSQRTS */ |
6274 | gen_helper_rsqrtsf_f32(tcg_res, tcg_op1, tcg_op2, fpst); | |
6275 | break; | |
845ea09a PM |
6276 | case 0x5b: /* FMUL */ |
6277 | gen_helper_vfp_muls(tcg_res, tcg_op1, tcg_op2, fpst); | |
6278 | break; | |
8908f4d1 AB |
6279 | case 0x5c: /* FCMGE */ |
6280 | gen_helper_neon_cge_f32(tcg_res, tcg_op1, tcg_op2, fpst); | |
6281 | break; | |
057d5f62 PM |
6282 | case 0x5d: /* FACGE */ |
6283 | gen_helper_neon_acge_f32(tcg_res, tcg_op1, tcg_op2, fpst); | |
6284 | break; | |
845ea09a PM |
6285 | case 0x5f: /* FDIV */ |
6286 | gen_helper_vfp_divs(tcg_res, tcg_op1, tcg_op2, fpst); | |
6287 | break; | |
6288 | case 0x7a: /* FABD */ | |
6289 | gen_helper_vfp_subs(tcg_res, tcg_op1, tcg_op2, fpst); | |
6290 | gen_helper_vfp_abss(tcg_res, tcg_res); | |
6291 | break; | |
8908f4d1 AB |
6292 | case 0x7c: /* FCMGT */ |
6293 | gen_helper_neon_cgt_f32(tcg_res, tcg_op1, tcg_op2, fpst); | |
6294 | break; | |
057d5f62 PM |
6295 | case 0x7d: /* FACGT */ |
6296 | gen_helper_neon_acgt_f32(tcg_res, tcg_op1, tcg_op2, fpst); | |
6297 | break; | |
845ea09a PM |
6298 | default: |
6299 | g_assert_not_reached(); | |
6300 | } | |
6301 | ||
6302 | if (elements == 1) { | |
6303 | /* scalar single so clear high part */ | |
6304 | TCGv_i64 tcg_tmp = tcg_temp_new_i64(); | |
6305 | ||
6306 | tcg_gen_extu_i32_i64(tcg_tmp, tcg_res); | |
6307 | write_vec_element(s, tcg_tmp, rd, pass, MO_64); | |
6308 | tcg_temp_free_i64(tcg_tmp); | |
6309 | } else { | |
6310 | write_vec_element_i32(s, tcg_res, rd, pass, MO_32); | |
6311 | } | |
6312 | ||
6313 | tcg_temp_free_i32(tcg_res); | |
6314 | tcg_temp_free_i32(tcg_op1); | |
6315 | tcg_temp_free_i32(tcg_op2); | |
6316 | } | |
6317 | } | |
6318 | ||
6319 | tcg_temp_free_ptr(fpst); | |
6320 | ||
6321 | if ((elements << size) < 4) { | |
6322 | /* scalar, or non-quad vector op */ | |
6323 | clear_vec_high(s, rd); | |
6324 | } | |
6325 | } | |
6326 | ||
384b26fb AB |
6327 | /* C3.6.11 AdvSIMD scalar three same |
6328 | * 31 30 29 28 24 23 22 21 20 16 15 11 10 9 5 4 0 | |
6329 | * +-----+---+-----------+------+---+------+--------+---+------+------+ | |
6330 | * | 0 1 | U | 1 1 1 1 0 | size | 1 | Rm | opcode | 1 | Rn | Rd | | |
6331 | * +-----+---+-----------+------+---+------+--------+---+------+------+ | |
6332 | */ | |
6333 | static void disas_simd_scalar_three_reg_same(DisasContext *s, uint32_t insn) | |
6334 | { | |
b305dba6 PM |
6335 | int rd = extract32(insn, 0, 5); |
6336 | int rn = extract32(insn, 5, 5); | |
6337 | int opcode = extract32(insn, 11, 5); | |
6338 | int rm = extract32(insn, 16, 5); | |
6339 | int size = extract32(insn, 22, 2); | |
6340 | bool u = extract32(insn, 29, 1); | |
b305dba6 PM |
6341 | TCGv_i64 tcg_rd; |
6342 | ||
6343 | if (opcode >= 0x18) { | |
6344 | /* Floating point: U, size[1] and opcode indicate operation */ | |
6345 | int fpopcode = opcode | (extract32(size, 1, 1) << 5) | (u << 6); | |
6346 | switch (fpopcode) { | |
6347 | case 0x1b: /* FMULX */ | |
b305dba6 PM |
6348 | case 0x1f: /* FRECPS */ |
6349 | case 0x3f: /* FRSQRTS */ | |
b305dba6 | 6350 | case 0x5d: /* FACGE */ |
b305dba6 | 6351 | case 0x7d: /* FACGT */ |
8908f4d1 AB |
6352 | case 0x1c: /* FCMEQ */ |
6353 | case 0x5c: /* FCMGE */ | |
6354 | case 0x7c: /* FCMGT */ | |
845ea09a PM |
6355 | case 0x7a: /* FABD */ |
6356 | break; | |
b305dba6 PM |
6357 | default: |
6358 | unallocated_encoding(s); | |
6359 | return; | |
6360 | } | |
845ea09a PM |
6361 | |
6362 | handle_3same_float(s, extract32(size, 0, 1), 1, fpopcode, rd, rn, rm); | |
6363 | return; | |
b305dba6 PM |
6364 | } |
6365 | ||
6366 | switch (opcode) { | |
6367 | case 0x1: /* SQADD, UQADD */ | |
6368 | case 0x5: /* SQSUB, UQSUB */ | |
c0b2b5fa PM |
6369 | case 0x9: /* SQSHL, UQSHL */ |
6370 | case 0xb: /* SQRSHL, UQRSHL */ | |
6371 | break; | |
6d9571f7 PM |
6372 | case 0x8: /* SSHL, USHL */ |
6373 | case 0xa: /* SRSHL, URSHL */ | |
b305dba6 PM |
6374 | case 0x6: /* CMGT, CMHI */ |
6375 | case 0x7: /* CMGE, CMHS */ | |
6376 | case 0x11: /* CMTST, CMEQ */ | |
6377 | case 0x10: /* ADD, SUB (vector) */ | |
6378 | if (size != 3) { | |
6379 | unallocated_encoding(s); | |
6380 | return; | |
6381 | } | |
6382 | break; | |
b305dba6 PM |
6383 | case 0x16: /* SQDMULH, SQRDMULH (vector) */ |
6384 | if (size != 1 && size != 2) { | |
6385 | unallocated_encoding(s); | |
6386 | return; | |
6387 | } | |
c0b2b5fa | 6388 | break; |
b305dba6 PM |
6389 | default: |
6390 | unallocated_encoding(s); | |
6391 | return; | |
6392 | } | |
6393 | ||
b305dba6 PM |
6394 | tcg_rd = tcg_temp_new_i64(); |
6395 | ||
c0b2b5fa PM |
6396 | if (size == 3) { |
6397 | TCGv_i64 tcg_rn = read_fp_dreg(s, rn); | |
6398 | TCGv_i64 tcg_rm = read_fp_dreg(s, rm); | |
6399 | ||
6400 | handle_3same_64(s, opcode, u, tcg_rd, tcg_rn, tcg_rm); | |
6401 | tcg_temp_free_i64(tcg_rn); | |
6402 | tcg_temp_free_i64(tcg_rm); | |
6403 | } else { | |
6404 | /* Do a single operation on the lowest element in the vector. | |
6405 | * We use the standard Neon helpers and rely on 0 OP 0 == 0 with | |
6406 | * no side effects for all these operations. | |
6407 | * OPTME: special-purpose helpers would avoid doing some | |
6408 | * unnecessary work in the helper for the 8 and 16 bit cases. | |
6409 | */ | |
6410 | NeonGenTwoOpEnvFn *genenvfn; | |
6411 | TCGv_i32 tcg_rn = tcg_temp_new_i32(); | |
6412 | TCGv_i32 tcg_rm = tcg_temp_new_i32(); | |
6413 | TCGv_i32 tcg_rd32 = tcg_temp_new_i32(); | |
6414 | ||
6415 | read_vec_element_i32(s, tcg_rn, rn, 0, size); | |
6416 | read_vec_element_i32(s, tcg_rm, rm, 0, size); | |
6417 | ||
6418 | switch (opcode) { | |
6419 | case 0x1: /* SQADD, UQADD */ | |
6420 | { | |
6421 | static NeonGenTwoOpEnvFn * const fns[3][2] = { | |
6422 | { gen_helper_neon_qadd_s8, gen_helper_neon_qadd_u8 }, | |
6423 | { gen_helper_neon_qadd_s16, gen_helper_neon_qadd_u16 }, | |
6424 | { gen_helper_neon_qadd_s32, gen_helper_neon_qadd_u32 }, | |
6425 | }; | |
6426 | genenvfn = fns[size][u]; | |
6427 | break; | |
6428 | } | |
6429 | case 0x5: /* SQSUB, UQSUB */ | |
6430 | { | |
6431 | static NeonGenTwoOpEnvFn * const fns[3][2] = { | |
6432 | { gen_helper_neon_qsub_s8, gen_helper_neon_qsub_u8 }, | |
6433 | { gen_helper_neon_qsub_s16, gen_helper_neon_qsub_u16 }, | |
6434 | { gen_helper_neon_qsub_s32, gen_helper_neon_qsub_u32 }, | |
6435 | }; | |
6436 | genenvfn = fns[size][u]; | |
6437 | break; | |
6438 | } | |
6439 | case 0x9: /* SQSHL, UQSHL */ | |
6440 | { | |
6441 | static NeonGenTwoOpEnvFn * const fns[3][2] = { | |
6442 | { gen_helper_neon_qshl_s8, gen_helper_neon_qshl_u8 }, | |
6443 | { gen_helper_neon_qshl_s16, gen_helper_neon_qshl_u16 }, | |
6444 | { gen_helper_neon_qshl_s32, gen_helper_neon_qshl_u32 }, | |
6445 | }; | |
6446 | genenvfn = fns[size][u]; | |
6447 | break; | |
6448 | } | |
6449 | case 0xb: /* SQRSHL, UQRSHL */ | |
6450 | { | |
6451 | static NeonGenTwoOpEnvFn * const fns[3][2] = { | |
6452 | { gen_helper_neon_qrshl_s8, gen_helper_neon_qrshl_u8 }, | |
6453 | { gen_helper_neon_qrshl_s16, gen_helper_neon_qrshl_u16 }, | |
6454 | { gen_helper_neon_qrshl_s32, gen_helper_neon_qrshl_u32 }, | |
6455 | }; | |
6456 | genenvfn = fns[size][u]; | |
6457 | break; | |
6458 | } | |
6459 | case 0x16: /* SQDMULH, SQRDMULH */ | |
6460 | { | |
6461 | static NeonGenTwoOpEnvFn * const fns[2][2] = { | |
6462 | { gen_helper_neon_qdmulh_s16, gen_helper_neon_qrdmulh_s16 }, | |
6463 | { gen_helper_neon_qdmulh_s32, gen_helper_neon_qrdmulh_s32 }, | |
6464 | }; | |
6465 | assert(size == 1 || size == 2); | |
6466 | genenvfn = fns[size - 1][u]; | |
6467 | break; | |
6468 | } | |
6469 | default: | |
6470 | g_assert_not_reached(); | |
6471 | } | |
6472 | ||
6473 | genenvfn(tcg_rd32, cpu_env, tcg_rn, tcg_rm); | |
6474 | tcg_gen_extu_i32_i64(tcg_rd, tcg_rd32); | |
6475 | tcg_temp_free_i32(tcg_rd32); | |
6476 | tcg_temp_free_i32(tcg_rn); | |
6477 | tcg_temp_free_i32(tcg_rm); | |
6478 | } | |
b305dba6 PM |
6479 | |
6480 | write_fp_dreg(s, rd, tcg_rd); | |
6481 | ||
b305dba6 | 6482 | tcg_temp_free_i64(tcg_rd); |
384b26fb AB |
6483 | } |
6484 | ||
effa8e06 PM |
6485 | static void handle_2misc_64(DisasContext *s, int opcode, bool u, |
6486 | TCGv_i64 tcg_rd, TCGv_i64 tcg_rn) | |
6487 | { | |
6488 | /* Handle 64->64 opcodes which are shared between the scalar and | |
6489 | * vector 2-reg-misc groups. We cover every integer opcode where size == 3 | |
f93d0138 | 6490 | * is valid in either group and also the double-precision fp ops. |
effa8e06 PM |
6491 | */ |
6492 | TCGCond cond; | |
6493 | ||
6494 | switch (opcode) { | |
86cbc418 PM |
6495 | case 0x5: /* NOT */ |
6496 | /* This opcode is shared with CNT and RBIT but we have earlier | |
6497 | * enforced that size == 3 if and only if this is the NOT insn. | |
6498 | */ | |
6499 | tcg_gen_not_i64(tcg_rd, tcg_rn); | |
6500 | break; | |
effa8e06 PM |
6501 | case 0xa: /* CMLT */ |
6502 | /* 64 bit integer comparison against zero, result is | |
6503 | * test ? (2^64 - 1) : 0. We implement via setcond(!test) and | |
6504 | * subtracting 1. | |
6505 | */ | |
6506 | cond = TCG_COND_LT; | |
6507 | do_cmop: | |
6508 | tcg_gen_setcondi_i64(cond, tcg_rd, tcg_rn, 0); | |
6509 | tcg_gen_neg_i64(tcg_rd, tcg_rd); | |
6510 | break; | |
6511 | case 0x8: /* CMGT, CMGE */ | |
6512 | cond = u ? TCG_COND_GE : TCG_COND_GT; | |
6513 | goto do_cmop; | |
6514 | case 0x9: /* CMEQ, CMLE */ | |
6515 | cond = u ? TCG_COND_LE : TCG_COND_EQ; | |
6516 | goto do_cmop; | |
6517 | case 0xb: /* ABS, NEG */ | |
6518 | if (u) { | |
6519 | tcg_gen_neg_i64(tcg_rd, tcg_rn); | |
6520 | } else { | |
6521 | TCGv_i64 tcg_zero = tcg_const_i64(0); | |
6522 | tcg_gen_neg_i64(tcg_rd, tcg_rn); | |
6523 | tcg_gen_movcond_i64(TCG_COND_GT, tcg_rd, tcg_rn, tcg_zero, | |
6524 | tcg_rn, tcg_rd); | |
6525 | tcg_temp_free_i64(tcg_zero); | |
6526 | } | |
6527 | break; | |
f93d0138 PM |
6528 | case 0x2f: /* FABS */ |
6529 | gen_helper_vfp_absd(tcg_rd, tcg_rn); | |
6530 | break; | |
6531 | case 0x6f: /* FNEG */ | |
6532 | gen_helper_vfp_negd(tcg_rd, tcg_rn); | |
6533 | break; | |
effa8e06 PM |
6534 | default: |
6535 | g_assert_not_reached(); | |
6536 | } | |
6537 | } | |
6538 | ||
8908f4d1 AB |
6539 | static void handle_2misc_fcmp_zero(DisasContext *s, int opcode, |
6540 | bool is_scalar, bool is_u, bool is_q, | |
6541 | int size, int rn, int rd) | |
6542 | { | |
6543 | bool is_double = (size == 3); | |
6544 | TCGv_ptr fpst = get_fpstatus_ptr(); | |
6545 | ||
6546 | if (is_double) { | |
6547 | TCGv_i64 tcg_op = tcg_temp_new_i64(); | |
6548 | TCGv_i64 tcg_zero = tcg_const_i64(0); | |
6549 | TCGv_i64 tcg_res = tcg_temp_new_i64(); | |
6550 | NeonGenTwoDoubleOPFn *genfn; | |
6551 | bool swap = false; | |
6552 | int pass; | |
6553 | ||
6554 | switch (opcode) { | |
6555 | case 0x2e: /* FCMLT (zero) */ | |
6556 | swap = true; | |
6557 | /* fallthrough */ | |
6558 | case 0x2c: /* FCMGT (zero) */ | |
6559 | genfn = gen_helper_neon_cgt_f64; | |
6560 | break; | |
6561 | case 0x2d: /* FCMEQ (zero) */ | |
6562 | genfn = gen_helper_neon_ceq_f64; | |
6563 | break; | |
6564 | case 0x6d: /* FCMLE (zero) */ | |
6565 | swap = true; | |
6566 | /* fall through */ | |
6567 | case 0x6c: /* FCMGE (zero) */ | |
6568 | genfn = gen_helper_neon_cge_f64; | |
6569 | break; | |
6570 | default: | |
6571 | g_assert_not_reached(); | |
6572 | } | |
6573 | ||
6574 | for (pass = 0; pass < (is_scalar ? 1 : 2); pass++) { | |
6575 | read_vec_element(s, tcg_op, rn, pass, MO_64); | |
6576 | if (swap) { | |
6577 | genfn(tcg_res, tcg_zero, tcg_op, fpst); | |
6578 | } else { | |
6579 | genfn(tcg_res, tcg_op, tcg_zero, fpst); | |
6580 | } | |
6581 | write_vec_element(s, tcg_res, rd, pass, MO_64); | |
6582 | } | |
6583 | if (is_scalar) { | |
6584 | clear_vec_high(s, rd); | |
6585 | } | |
6586 | ||
6587 | tcg_temp_free_i64(tcg_res); | |
6588 | tcg_temp_free_i64(tcg_zero); | |
6589 | tcg_temp_free_i64(tcg_op); | |
6590 | } else { | |
6591 | TCGv_i32 tcg_op = tcg_temp_new_i32(); | |
6592 | TCGv_i32 tcg_zero = tcg_const_i32(0); | |
6593 | TCGv_i32 tcg_res = tcg_temp_new_i32(); | |
6594 | NeonGenTwoSingleOPFn *genfn; | |
6595 | bool swap = false; | |
6596 | int pass, maxpasses; | |
6597 | ||
6598 | switch (opcode) { | |
6599 | case 0x2e: /* FCMLT (zero) */ | |
6600 | swap = true; | |
6601 | /* fall through */ | |
6602 | case 0x2c: /* FCMGT (zero) */ | |
6603 | genfn = gen_helper_neon_cgt_f32; | |
6604 | break; | |
6605 | case 0x2d: /* FCMEQ (zero) */ | |
6606 | genfn = gen_helper_neon_ceq_f32; | |
6607 | break; | |
6608 | case 0x6d: /* FCMLE (zero) */ | |
6609 | swap = true; | |
6610 | /* fall through */ | |
6611 | case 0x6c: /* FCMGE (zero) */ | |
6612 | genfn = gen_helper_neon_cge_f32; | |
6613 | break; | |
6614 | default: | |
6615 | g_assert_not_reached(); | |
6616 | } | |
6617 | ||
6618 | if (is_scalar) { | |
6619 | maxpasses = 1; | |
6620 | } else { | |
6621 | maxpasses = is_q ? 4 : 2; | |
6622 | } | |
6623 | ||
6624 | for (pass = 0; pass < maxpasses; pass++) { | |
6625 | read_vec_element_i32(s, tcg_op, rn, pass, MO_32); | |
6626 | if (swap) { | |
6627 | genfn(tcg_res, tcg_zero, tcg_op, fpst); | |
6628 | } else { | |
6629 | genfn(tcg_res, tcg_op, tcg_zero, fpst); | |
6630 | } | |
6631 | if (is_scalar) { | |
6632 | write_fp_sreg(s, rd, tcg_res); | |
6633 | } else { | |
6634 | write_vec_element_i32(s, tcg_res, rd, pass, MO_32); | |
6635 | } | |
6636 | } | |
6637 | tcg_temp_free_i32(tcg_res); | |
6638 | tcg_temp_free_i32(tcg_zero); | |
6639 | tcg_temp_free_i32(tcg_op); | |
6640 | if (!is_q && !is_scalar) { | |
6641 | clear_vec_high(s, rd); | |
6642 | } | |
6643 | } | |
6644 | ||
6645 | tcg_temp_free_ptr(fpst); | |
6646 | } | |
6647 | ||
384b26fb AB |
6648 | /* C3.6.12 AdvSIMD scalar two reg misc |
6649 | * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0 | |
6650 | * +-----+---+-----------+------+-----------+--------+-----+------+------+ | |
6651 | * | 0 1 | U | 1 1 1 1 0 | size | 1 0 0 0 0 | opcode | 1 0 | Rn | Rd | | |
6652 | * +-----+---+-----------+------+-----------+--------+-----+------+------+ | |
6653 | */ | |
6654 | static void disas_simd_scalar_two_reg_misc(DisasContext *s, uint32_t insn) | |
6655 | { | |
effa8e06 PM |
6656 | int rd = extract32(insn, 0, 5); |
6657 | int rn = extract32(insn, 5, 5); | |
6658 | int opcode = extract32(insn, 12, 5); | |
6659 | int size = extract32(insn, 22, 2); | |
6660 | bool u = extract32(insn, 29, 1); | |
6661 | ||
6662 | switch (opcode) { | |
6663 | case 0xa: /* CMLT */ | |
6664 | if (u) { | |
6665 | unallocated_encoding(s); | |
6666 | return; | |
6667 | } | |
6668 | /* fall through */ | |
6669 | case 0x8: /* CMGT, CMGE */ | |
6670 | case 0x9: /* CMEQ, CMLE */ | |
6671 | case 0xb: /* ABS, NEG */ | |
6672 | if (size != 3) { | |
6673 | unallocated_encoding(s); | |
6674 | return; | |
6675 | } | |
6676 | break; | |
8908f4d1 AB |
6677 | case 0xc ... 0xf: |
6678 | case 0x16 ... 0x1d: | |
6679 | case 0x1f: | |
6680 | /* Floating point: U, size[1] and opcode indicate operation; | |
6681 | * size[0] indicates single or double precision. | |
6682 | */ | |
6683 | opcode |= (extract32(size, 1, 1) << 5) | (u << 6); | |
6684 | size = extract32(size, 0, 1) ? 3 : 2; | |
6685 | switch (opcode) { | |
6686 | case 0x2c: /* FCMGT (zero) */ | |
6687 | case 0x2d: /* FCMEQ (zero) */ | |
6688 | case 0x2e: /* FCMLT (zero) */ | |
6689 | case 0x6c: /* FCMGE (zero) */ | |
6690 | case 0x6d: /* FCMLE (zero) */ | |
6691 | handle_2misc_fcmp_zero(s, opcode, true, u, true, size, rn, rd); | |
6692 | return; | |
6693 | case 0x1a: /* FCVTNS */ | |
6694 | case 0x1b: /* FCVTMS */ | |
6695 | case 0x1c: /* FCVTAS */ | |
6696 | case 0x1d: /* SCVTF */ | |
6697 | case 0x3a: /* FCVTPS */ | |
6698 | case 0x3b: /* FCVTZS */ | |
6699 | case 0x3d: /* FRECPE */ | |
6700 | case 0x3f: /* FRECPX */ | |
6701 | case 0x56: /* FCVTXN, FCVTXN2 */ | |
6702 | case 0x5a: /* FCVTNU */ | |
6703 | case 0x5b: /* FCVTMU */ | |
6704 | case 0x5c: /* FCVTAU */ | |
6705 | case 0x5d: /* UCVTF */ | |
6706 | case 0x7a: /* FCVTPU */ | |
6707 | case 0x7b: /* FCVTZU */ | |
6708 | case 0x7d: /* FRSQRTE */ | |
6709 | unsupported_encoding(s, insn); | |
6710 | return; | |
6711 | default: | |
6712 | unallocated_encoding(s); | |
6713 | return; | |
6714 | } | |
6715 | break; | |
effa8e06 PM |
6716 | default: |
6717 | /* Other categories of encoding in this class: | |
effa8e06 PM |
6718 | * + SUQADD/USQADD/SQABS/SQNEG : size 8, 16, 32 or 64 |
6719 | * + SQXTN/SQXTN2/SQXTUN/SQXTUN2/UQXTN/UQXTN2: | |
6720 | * narrowing saturate ops: size 64/32/16 -> 32/16/8 | |
6721 | */ | |
6722 | unsupported_encoding(s, insn); | |
6723 | return; | |
6724 | } | |
6725 | ||
6726 | if (size == 3) { | |
6727 | TCGv_i64 tcg_rn = read_fp_dreg(s, rn); | |
6728 | TCGv_i64 tcg_rd = tcg_temp_new_i64(); | |
6729 | ||
6730 | handle_2misc_64(s, opcode, u, tcg_rd, tcg_rn); | |
6731 | write_fp_dreg(s, rd, tcg_rd); | |
6732 | tcg_temp_free_i64(tcg_rd); | |
6733 | tcg_temp_free_i64(tcg_rn); | |
6734 | } else { | |
6735 | /* the 'size might not be 64' ops aren't implemented yet */ | |
6736 | g_assert_not_reached(); | |
6737 | } | |
384b26fb AB |
6738 | } |
6739 | ||
4d1cef84 AB |
6740 | /* SSHR[RA]/USHR[RA] - Vector shift right (optional rounding/accumulate) */ |
6741 | static void handle_vec_simd_shri(DisasContext *s, bool is_q, bool is_u, | |
6742 | int immh, int immb, int opcode, int rn, int rd) | |
6743 | { | |
6744 | int size = 32 - clz32(immh) - 1; | |
6745 | int immhb = immh << 3 | immb; | |
6746 | int shift = 2 * (8 << size) - immhb; | |
6747 | bool accumulate = false; | |
6748 | bool round = false; | |
6749 | int dsize = is_q ? 128 : 64; | |
6750 | int esize = 8 << size; | |
6751 | int elements = dsize/esize; | |
6752 | TCGMemOp memop = size | (is_u ? 0 : MO_SIGN); | |
6753 | TCGv_i64 tcg_rn = new_tmp_a64(s); | |
6754 | TCGv_i64 tcg_rd = new_tmp_a64(s); | |
6755 | TCGv_i64 tcg_round; | |
6756 | int i; | |
6757 | ||
6758 | if (extract32(immh, 3, 1) && !is_q) { | |
6759 | unallocated_encoding(s); | |
6760 | return; | |
6761 | } | |
6762 | ||
6763 | if (size > 3 && !is_q) { | |
6764 | unallocated_encoding(s); | |
6765 | return; | |
6766 | } | |
6767 | ||
6768 | switch (opcode) { | |
6769 | case 0x02: /* SSRA / USRA (accumulate) */ | |
6770 | accumulate = true; | |
6771 | break; | |
6772 | case 0x04: /* SRSHR / URSHR (rounding) */ | |
6773 | round = true; | |
6774 | break; | |
6775 | case 0x06: /* SRSRA / URSRA (accum + rounding) */ | |
6776 | accumulate = round = true; | |
6777 | break; | |
6778 | } | |
6779 | ||
6780 | if (round) { | |
6781 | uint64_t round_const = 1ULL << (shift - 1); | |
6782 | tcg_round = tcg_const_i64(round_const); | |
6783 | } else { | |
6784 | TCGV_UNUSED_I64(tcg_round); | |
6785 | } | |
6786 | ||
6787 | for (i = 0; i < elements; i++) { | |
6788 | read_vec_element(s, tcg_rn, rn, i, memop); | |
6789 | if (accumulate) { | |
6790 | read_vec_element(s, tcg_rd, rd, i, memop); | |
6791 | } | |
6792 | ||
6793 | handle_shri_with_rndacc(tcg_rd, tcg_rn, tcg_round, | |
6794 | accumulate, is_u, size, shift); | |
6795 | ||
6796 | write_vec_element(s, tcg_rd, rd, i, size); | |
6797 | } | |
6798 | ||
6799 | if (!is_q) { | |
6800 | clear_vec_high(s, rd); | |
6801 | } | |
6802 | ||
6803 | if (round) { | |
6804 | tcg_temp_free_i64(tcg_round); | |
6805 | } | |
6806 | } | |
6807 | ||
6808 | /* SHL/SLI - Vector shift left */ | |
6809 | static void handle_vec_simd_shli(DisasContext *s, bool is_q, bool insert, | |
6810 | int immh, int immb, int opcode, int rn, int rd) | |
6811 | { | |
6812 | int size = 32 - clz32(immh) - 1; | |
6813 | int immhb = immh << 3 | immb; | |
6814 | int shift = immhb - (8 << size); | |
6815 | int dsize = is_q ? 128 : 64; | |
6816 | int esize = 8 << size; | |
6817 | int elements = dsize/esize; | |
6818 | TCGv_i64 tcg_rn = new_tmp_a64(s); | |
6819 | TCGv_i64 tcg_rd = new_tmp_a64(s); | |
6820 | int i; | |
6821 | ||
6822 | if (extract32(immh, 3, 1) && !is_q) { | |
6823 | unallocated_encoding(s); | |
6824 | return; | |
6825 | } | |
6826 | ||
6827 | if (size > 3 && !is_q) { | |
6828 | unallocated_encoding(s); | |
6829 | return; | |
6830 | } | |
6831 | ||
6832 | for (i = 0; i < elements; i++) { | |
6833 | read_vec_element(s, tcg_rn, rn, i, size); | |
6834 | if (insert) { | |
6835 | read_vec_element(s, tcg_rd, rd, i, size); | |
6836 | } | |
6837 | ||
6838 | handle_shli_with_ins(tcg_rd, tcg_rn, insert, shift); | |
6839 | ||
6840 | write_vec_element(s, tcg_rd, rd, i, size); | |
6841 | } | |
6842 | ||
6843 | if (!is_q) { | |
6844 | clear_vec_high(s, rd); | |
6845 | } | |
6846 | } | |
6847 | ||
6848 | /* USHLL/SHLL - Vector shift left with widening */ | |
6849 | static void handle_vec_simd_wshli(DisasContext *s, bool is_q, bool is_u, | |
6850 | int immh, int immb, int opcode, int rn, int rd) | |
6851 | { | |
6852 | int size = 32 - clz32(immh) - 1; | |
6853 | int immhb = immh << 3 | immb; | |
6854 | int shift = immhb - (8 << size); | |
6855 | int dsize = 64; | |
6856 | int esize = 8 << size; | |
6857 | int elements = dsize/esize; | |
6858 | TCGv_i64 tcg_rn = new_tmp_a64(s); | |
6859 | TCGv_i64 tcg_rd = new_tmp_a64(s); | |
6860 | int i; | |
6861 | ||
6862 | if (size >= 3) { | |
6863 | unallocated_encoding(s); | |
6864 | return; | |
6865 | } | |
6866 | ||
6867 | /* For the LL variants the store is larger than the load, | |
6868 | * so if rd == rn we would overwrite parts of our input. | |
6869 | * So load everything right now and use shifts in the main loop. | |
6870 | */ | |
6871 | read_vec_element(s, tcg_rn, rn, is_q ? 1 : 0, MO_64); | |
6872 | ||
6873 | for (i = 0; i < elements; i++) { | |
6874 | tcg_gen_shri_i64(tcg_rd, tcg_rn, i * esize); | |
6875 | ext_and_shift_reg(tcg_rd, tcg_rd, size | (!is_u << 2), 0); | |
6876 | tcg_gen_shli_i64(tcg_rd, tcg_rd, shift); | |
6877 | write_vec_element(s, tcg_rd, rd, i, size + 1); | |
6878 | } | |
6879 | } | |
6880 | ||
6881 | ||
384b26fb AB |
6882 | /* C3.6.14 AdvSIMD shift by immediate |
6883 | * 31 30 29 28 23 22 19 18 16 15 11 10 9 5 4 0 | |
6884 | * +---+---+---+-------------+------+------+--------+---+------+------+ | |
6885 | * | 0 | Q | U | 0 1 1 1 1 0 | immh | immb | opcode | 1 | Rn | Rd | | |
6886 | * +---+---+---+-------------+------+------+--------+---+------+------+ | |
6887 | */ | |
6888 | static void disas_simd_shift_imm(DisasContext *s, uint32_t insn) | |
6889 | { | |
4d1cef84 AB |
6890 | int rd = extract32(insn, 0, 5); |
6891 | int rn = extract32(insn, 5, 5); | |
6892 | int opcode = extract32(insn, 11, 5); | |
6893 | int immb = extract32(insn, 16, 3); | |
6894 | int immh = extract32(insn, 19, 4); | |
6895 | bool is_u = extract32(insn, 29, 1); | |
6896 | bool is_q = extract32(insn, 30, 1); | |
6897 | ||
6898 | switch (opcode) { | |
6899 | case 0x00: /* SSHR / USHR */ | |
6900 | case 0x02: /* SSRA / USRA (accumulate) */ | |
6901 | case 0x04: /* SRSHR / URSHR (rounding) */ | |
6902 | case 0x06: /* SRSRA / URSRA (accum + rounding) */ | |
6903 | handle_vec_simd_shri(s, is_q, is_u, immh, immb, opcode, rn, rd); | |
6904 | break; | |
6905 | case 0x0a: /* SHL / SLI */ | |
6906 | handle_vec_simd_shli(s, is_q, is_u, immh, immb, opcode, rn, rd); | |
6907 | break; | |
6908 | case 0x14: /* SSHLL / USHLL */ | |
6909 | handle_vec_simd_wshli(s, is_q, is_u, immh, immb, opcode, rn, rd); | |
6910 | break; | |
6911 | default: | |
6912 | /* We don't currently implement any of the Narrow or saturating shifts; | |
6913 | * nor do we implement the fixed-point conversions in this | |
6914 | * encoding group (SCVTF, FCVTZS, UCVTF, FCVTZU). | |
6915 | */ | |
6916 | unsupported_encoding(s, insn); | |
6917 | return; | |
6918 | } | |
384b26fb AB |
6919 | } |
6920 | ||
70d7f984 PM |
6921 | /* Generate code to do a "long" addition or subtraction, ie one done in |
6922 | * TCGv_i64 on vector lanes twice the width specified by size. | |
6923 | */ | |
6924 | static void gen_neon_addl(int size, bool is_sub, TCGv_i64 tcg_res, | |
6925 | TCGv_i64 tcg_op1, TCGv_i64 tcg_op2) | |
6926 | { | |
6927 | static NeonGenTwo64OpFn * const fns[3][2] = { | |
6928 | { gen_helper_neon_addl_u16, gen_helper_neon_subl_u16 }, | |
6929 | { gen_helper_neon_addl_u32, gen_helper_neon_subl_u32 }, | |
6930 | { tcg_gen_add_i64, tcg_gen_sub_i64 }, | |
6931 | }; | |
6932 | NeonGenTwo64OpFn *genfn; | |
6933 | assert(size < 3); | |
6934 | ||
6935 | genfn = fns[size][is_sub]; | |
6936 | genfn(tcg_res, tcg_op1, tcg_op2); | |
6937 | } | |
6938 | ||
a08582f4 PM |
6939 | static void handle_3rd_widening(DisasContext *s, int is_q, int is_u, int size, |
6940 | int opcode, int rd, int rn, int rm) | |
6941 | { | |
6942 | /* 3-reg-different widening insns: 64 x 64 -> 128 */ | |
6943 | TCGv_i64 tcg_res[2]; | |
6944 | int pass, accop; | |
6945 | ||
6946 | tcg_res[0] = tcg_temp_new_i64(); | |
6947 | tcg_res[1] = tcg_temp_new_i64(); | |
6948 | ||
6949 | /* Does this op do an adding accumulate, a subtracting accumulate, | |
6950 | * or no accumulate at all? | |
6951 | */ | |
6952 | switch (opcode) { | |
6953 | case 5: | |
6954 | case 8: | |
6955 | case 9: | |
6956 | accop = 1; | |
6957 | break; | |
6958 | case 10: | |
6959 | case 11: | |
6960 | accop = -1; | |
6961 | break; | |
6962 | default: | |
6963 | accop = 0; | |
6964 | break; | |
6965 | } | |
6966 | ||
6967 | if (accop != 0) { | |
6968 | read_vec_element(s, tcg_res[0], rd, 0, MO_64); | |
6969 | read_vec_element(s, tcg_res[1], rd, 1, MO_64); | |
6970 | } | |
6971 | ||
6972 | /* size == 2 means two 32x32->64 operations; this is worth special | |
6973 | * casing because we can generally handle it inline. | |
6974 | */ | |
6975 | if (size == 2) { | |
6976 | for (pass = 0; pass < 2; pass++) { | |
6977 | TCGv_i64 tcg_op1 = tcg_temp_new_i64(); | |
6978 | TCGv_i64 tcg_op2 = tcg_temp_new_i64(); | |
6979 | TCGv_i64 tcg_passres; | |
6980 | TCGMemOp memop = MO_32 | (is_u ? 0 : MO_SIGN); | |
6981 | ||
6982 | int elt = pass + is_q * 2; | |
6983 | ||
6984 | read_vec_element(s, tcg_op1, rn, elt, memop); | |
6985 | read_vec_element(s, tcg_op2, rm, elt, memop); | |
6986 | ||
6987 | if (accop == 0) { | |
6988 | tcg_passres = tcg_res[pass]; | |
6989 | } else { | |
6990 | tcg_passres = tcg_temp_new_i64(); | |
6991 | } | |
6992 | ||
6993 | switch (opcode) { | |
70d7f984 PM |
6994 | case 0: /* SADDL, SADDL2, UADDL, UADDL2 */ |
6995 | tcg_gen_add_i64(tcg_passres, tcg_op1, tcg_op2); | |
6996 | break; | |
6997 | case 2: /* SSUBL, SSUBL2, USUBL, USUBL2 */ | |
6998 | tcg_gen_sub_i64(tcg_passres, tcg_op1, tcg_op2); | |
6999 | break; | |
0ae39320 PM |
7000 | case 5: /* SABAL, SABAL2, UABAL, UABAL2 */ |
7001 | case 7: /* SABDL, SABDL2, UABDL, UABDL2 */ | |
7002 | { | |
7003 | TCGv_i64 tcg_tmp1 = tcg_temp_new_i64(); | |
7004 | TCGv_i64 tcg_tmp2 = tcg_temp_new_i64(); | |
7005 | ||
7006 | tcg_gen_sub_i64(tcg_tmp1, tcg_op1, tcg_op2); | |
7007 | tcg_gen_sub_i64(tcg_tmp2, tcg_op2, tcg_op1); | |
7008 | tcg_gen_movcond_i64(is_u ? TCG_COND_GEU : TCG_COND_GE, | |
7009 | tcg_passres, | |
7010 | tcg_op1, tcg_op2, tcg_tmp1, tcg_tmp2); | |
7011 | tcg_temp_free_i64(tcg_tmp1); | |
7012 | tcg_temp_free_i64(tcg_tmp2); | |
7013 | break; | |
7014 | } | |
a08582f4 PM |
7015 | case 8: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */ |
7016 | case 10: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */ | |
7017 | case 12: /* UMULL, UMULL2, SMULL, SMULL2 */ | |
7018 | tcg_gen_mul_i64(tcg_passres, tcg_op1, tcg_op2); | |
7019 | break; | |
70d7f984 PM |
7020 | case 9: /* SQDMLAL, SQDMLAL2 */ |
7021 | case 11: /* SQDMLSL, SQDMLSL2 */ | |
7022 | case 13: /* SQDMULL, SQDMULL2 */ | |
7023 | tcg_gen_mul_i64(tcg_passres, tcg_op1, tcg_op2); | |
7024 | gen_helper_neon_addl_saturate_s64(tcg_passres, cpu_env, | |
7025 | tcg_passres, tcg_passres); | |
7026 | break; | |
a08582f4 PM |
7027 | default: |
7028 | g_assert_not_reached(); | |
7029 | } | |
7030 | ||
70d7f984 PM |
7031 | if (opcode == 9 || opcode == 11) { |
7032 | /* saturating accumulate ops */ | |
7033 | if (accop < 0) { | |
7034 | tcg_gen_neg_i64(tcg_passres, tcg_passres); | |
7035 | } | |
7036 | gen_helper_neon_addl_saturate_s64(tcg_res[pass], cpu_env, | |
7037 | tcg_res[pass], tcg_passres); | |
7038 | } else if (accop > 0) { | |
a08582f4 | 7039 | tcg_gen_add_i64(tcg_res[pass], tcg_res[pass], tcg_passres); |
a08582f4 PM |
7040 | } else if (accop < 0) { |
7041 | tcg_gen_sub_i64(tcg_res[pass], tcg_res[pass], tcg_passres); | |
70d7f984 PM |
7042 | } |
7043 | ||
7044 | if (accop != 0) { | |
a08582f4 PM |
7045 | tcg_temp_free_i64(tcg_passres); |
7046 | } | |
7047 | ||
7048 | tcg_temp_free_i64(tcg_op1); | |
7049 | tcg_temp_free_i64(tcg_op2); | |
7050 | } | |
7051 | } else { | |
7052 | /* size 0 or 1, generally helper functions */ | |
7053 | for (pass = 0; pass < 2; pass++) { | |
7054 | TCGv_i32 tcg_op1 = tcg_temp_new_i32(); | |
7055 | TCGv_i32 tcg_op2 = tcg_temp_new_i32(); | |
7056 | TCGv_i64 tcg_passres; | |
7057 | int elt = pass + is_q * 2; | |
7058 | ||
7059 | read_vec_element_i32(s, tcg_op1, rn, elt, MO_32); | |
7060 | read_vec_element_i32(s, tcg_op2, rm, elt, MO_32); | |
7061 | ||
7062 | if (accop == 0) { | |
7063 | tcg_passres = tcg_res[pass]; | |
7064 | } else { | |
7065 | tcg_passres = tcg_temp_new_i64(); | |
7066 | } | |
7067 | ||
7068 | switch (opcode) { | |
70d7f984 PM |
7069 | case 0: /* SADDL, SADDL2, UADDL, UADDL2 */ |
7070 | case 2: /* SSUBL, SSUBL2, USUBL, USUBL2 */ | |
7071 | { | |
7072 | TCGv_i64 tcg_op2_64 = tcg_temp_new_i64(); | |
7073 | static NeonGenWidenFn * const widenfns[2][2] = { | |
7074 | { gen_helper_neon_widen_s8, gen_helper_neon_widen_u8 }, | |
7075 | { gen_helper_neon_widen_s16, gen_helper_neon_widen_u16 }, | |
7076 | }; | |
7077 | NeonGenWidenFn *widenfn = widenfns[size][is_u]; | |
7078 | ||
7079 | widenfn(tcg_op2_64, tcg_op2); | |
7080 | widenfn(tcg_passres, tcg_op1); | |
7081 | gen_neon_addl(size, (opcode == 2), tcg_passres, | |
7082 | tcg_passres, tcg_op2_64); | |
7083 | tcg_temp_free_i64(tcg_op2_64); | |
7084 | break; | |
7085 | } | |
0ae39320 PM |
7086 | case 5: /* SABAL, SABAL2, UABAL, UABAL2 */ |
7087 | case 7: /* SABDL, SABDL2, UABDL, UABDL2 */ | |
7088 | if (size == 0) { | |
7089 | if (is_u) { | |
7090 | gen_helper_neon_abdl_u16(tcg_passres, tcg_op1, tcg_op2); | |
7091 | } else { | |
7092 | gen_helper_neon_abdl_s16(tcg_passres, tcg_op1, tcg_op2); | |
7093 | } | |
7094 | } else { | |
7095 | if (is_u) { | |
7096 | gen_helper_neon_abdl_u32(tcg_passres, tcg_op1, tcg_op2); | |
7097 | } else { | |
7098 | gen_helper_neon_abdl_s32(tcg_passres, tcg_op1, tcg_op2); | |
7099 | } | |
7100 | } | |
7101 | break; | |
a08582f4 PM |
7102 | case 8: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */ |
7103 | case 10: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */ | |
7104 | case 12: /* UMULL, UMULL2, SMULL, SMULL2 */ | |
7105 | if (size == 0) { | |
7106 | if (is_u) { | |
7107 | gen_helper_neon_mull_u8(tcg_passres, tcg_op1, tcg_op2); | |
7108 | } else { | |
7109 | gen_helper_neon_mull_s8(tcg_passres, tcg_op1, tcg_op2); | |
7110 | } | |
7111 | } else { | |
7112 | if (is_u) { | |
7113 | gen_helper_neon_mull_u16(tcg_passres, tcg_op1, tcg_op2); | |
7114 | } else { | |
7115 | gen_helper_neon_mull_s16(tcg_passres, tcg_op1, tcg_op2); | |
7116 | } | |
7117 | } | |
7118 | break; | |
70d7f984 PM |
7119 | case 9: /* SQDMLAL, SQDMLAL2 */ |
7120 | case 11: /* SQDMLSL, SQDMLSL2 */ | |
7121 | case 13: /* SQDMULL, SQDMULL2 */ | |
7122 | assert(size == 1); | |
7123 | gen_helper_neon_mull_s16(tcg_passres, tcg_op1, tcg_op2); | |
7124 | gen_helper_neon_addl_saturate_s32(tcg_passres, cpu_env, | |
7125 | tcg_passres, tcg_passres); | |
7126 | break; | |
a08582f4 PM |
7127 | default: |
7128 | g_assert_not_reached(); | |
7129 | } | |
7130 | tcg_temp_free_i32(tcg_op1); | |
7131 | tcg_temp_free_i32(tcg_op2); | |
7132 | ||
70d7f984 PM |
7133 | if (accop != 0) { |
7134 | if (opcode == 9 || opcode == 11) { | |
7135 | /* saturating accumulate ops */ | |
7136 | if (accop < 0) { | |
7137 | gen_helper_neon_negl_u32(tcg_passres, tcg_passres); | |
7138 | } | |
7139 | gen_helper_neon_addl_saturate_s32(tcg_res[pass], cpu_env, | |
7140 | tcg_res[pass], | |
7141 | tcg_passres); | |
a08582f4 | 7142 | } else { |
70d7f984 PM |
7143 | gen_neon_addl(size, (accop < 0), tcg_res[pass], |
7144 | tcg_res[pass], tcg_passres); | |
a08582f4 PM |
7145 | } |
7146 | tcg_temp_free_i64(tcg_passres); | |
7147 | } | |
7148 | } | |
7149 | } | |
7150 | ||
7151 | write_vec_element(s, tcg_res[0], rd, 0, MO_64); | |
7152 | write_vec_element(s, tcg_res[1], rd, 1, MO_64); | |
7153 | tcg_temp_free_i64(tcg_res[0]); | |
7154 | tcg_temp_free_i64(tcg_res[1]); | |
7155 | } | |
7156 | ||
dfc15c7c PM |
7157 | static void handle_3rd_wide(DisasContext *s, int is_q, int is_u, int size, |
7158 | int opcode, int rd, int rn, int rm) | |
7159 | { | |
7160 | TCGv_i64 tcg_res[2]; | |
7161 | int part = is_q ? 2 : 0; | |
7162 | int pass; | |
7163 | ||
7164 | for (pass = 0; pass < 2; pass++) { | |
7165 | TCGv_i64 tcg_op1 = tcg_temp_new_i64(); | |
7166 | TCGv_i32 tcg_op2 = tcg_temp_new_i32(); | |
7167 | TCGv_i64 tcg_op2_wide = tcg_temp_new_i64(); | |
7168 | static NeonGenWidenFn * const widenfns[3][2] = { | |
7169 | { gen_helper_neon_widen_s8, gen_helper_neon_widen_u8 }, | |
7170 | { gen_helper_neon_widen_s16, gen_helper_neon_widen_u16 }, | |
7171 | { tcg_gen_ext_i32_i64, tcg_gen_extu_i32_i64 }, | |
7172 | }; | |
7173 | NeonGenWidenFn *widenfn = widenfns[size][is_u]; | |
7174 | ||
7175 | read_vec_element(s, tcg_op1, rn, pass, MO_64); | |
7176 | read_vec_element_i32(s, tcg_op2, rm, part + pass, MO_32); | |
7177 | widenfn(tcg_op2_wide, tcg_op2); | |
7178 | tcg_temp_free_i32(tcg_op2); | |
7179 | tcg_res[pass] = tcg_temp_new_i64(); | |
7180 | gen_neon_addl(size, (opcode == 3), | |
7181 | tcg_res[pass], tcg_op1, tcg_op2_wide); | |
7182 | tcg_temp_free_i64(tcg_op1); | |
7183 | tcg_temp_free_i64(tcg_op2_wide); | |
7184 | } | |
7185 | ||
7186 | for (pass = 0; pass < 2; pass++) { | |
7187 | write_vec_element(s, tcg_res[pass], rd, pass, MO_64); | |
7188 | tcg_temp_free_i64(tcg_res[pass]); | |
7189 | } | |
7190 | } | |
7191 | ||
e4b998d4 PM |
7192 | static void do_narrow_high_u32(TCGv_i32 res, TCGv_i64 in) |
7193 | { | |
7194 | tcg_gen_shri_i64(in, in, 32); | |
7195 | tcg_gen_trunc_i64_i32(res, in); | |
7196 | } | |
7197 | ||
7198 | static void do_narrow_round_high_u32(TCGv_i32 res, TCGv_i64 in) | |
7199 | { | |
7200 | tcg_gen_addi_i64(in, in, 1U << 31); | |
7201 | do_narrow_high_u32(res, in); | |
7202 | } | |
7203 | ||
7204 | static void handle_3rd_narrowing(DisasContext *s, int is_q, int is_u, int size, | |
7205 | int opcode, int rd, int rn, int rm) | |
7206 | { | |
7207 | TCGv_i32 tcg_res[2]; | |
7208 | int part = is_q ? 2 : 0; | |
7209 | int pass; | |
7210 | ||
7211 | for (pass = 0; pass < 2; pass++) { | |
7212 | TCGv_i64 tcg_op1 = tcg_temp_new_i64(); | |
7213 | TCGv_i64 tcg_op2 = tcg_temp_new_i64(); | |
7214 | TCGv_i64 tcg_wideres = tcg_temp_new_i64(); | |
7215 | static NeonGenNarrowFn * const narrowfns[3][2] = { | |
7216 | { gen_helper_neon_narrow_high_u8, | |
7217 | gen_helper_neon_narrow_round_high_u8 }, | |
7218 | { gen_helper_neon_narrow_high_u16, | |
7219 | gen_helper_neon_narrow_round_high_u16 }, | |
7220 | { do_narrow_high_u32, do_narrow_round_high_u32 }, | |
7221 | }; | |
7222 | NeonGenNarrowFn *gennarrow = narrowfns[size][is_u]; | |
7223 | ||
7224 | read_vec_element(s, tcg_op1, rn, pass, MO_64); | |
7225 | read_vec_element(s, tcg_op2, rm, pass, MO_64); | |
7226 | ||
7227 | gen_neon_addl(size, (opcode == 6), tcg_wideres, tcg_op1, tcg_op2); | |
7228 | ||
7229 | tcg_temp_free_i64(tcg_op1); | |
7230 | tcg_temp_free_i64(tcg_op2); | |
7231 | ||
7232 | tcg_res[pass] = tcg_temp_new_i32(); | |
7233 | gennarrow(tcg_res[pass], tcg_wideres); | |
7234 | tcg_temp_free_i64(tcg_wideres); | |
7235 | } | |
7236 | ||
7237 | for (pass = 0; pass < 2; pass++) { | |
7238 | write_vec_element_i32(s, tcg_res[pass], rd, pass + part, MO_32); | |
7239 | tcg_temp_free_i32(tcg_res[pass]); | |
7240 | } | |
7241 | if (!is_q) { | |
7242 | clear_vec_high(s, rd); | |
7243 | } | |
7244 | } | |
7245 | ||
384b26fb AB |
7246 | /* C3.6.15 AdvSIMD three different |
7247 | * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0 | |
7248 | * +---+---+---+-----------+------+---+------+--------+-----+------+------+ | |
7249 | * | 0 | Q | U | 0 1 1 1 0 | size | 1 | Rm | opcode | 0 0 | Rn | Rd | | |
7250 | * +---+---+---+-----------+------+---+------+--------+-----+------+------+ | |
7251 | */ | |
7252 | static void disas_simd_three_reg_diff(DisasContext *s, uint32_t insn) | |
7253 | { | |
a08582f4 PM |
7254 | /* Instructions in this group fall into three basic classes |
7255 | * (in each case with the operation working on each element in | |
7256 | * the input vectors): | |
7257 | * (1) widening 64 x 64 -> 128 (with possibly Vd as an extra | |
7258 | * 128 bit input) | |
7259 | * (2) wide 64 x 128 -> 128 | |
7260 | * (3) narrowing 128 x 128 -> 64 | |
7261 | * Here we do initial decode, catch unallocated cases and | |
7262 | * dispatch to separate functions for each class. | |
7263 | */ | |
7264 | int is_q = extract32(insn, 30, 1); | |
7265 | int is_u = extract32(insn, 29, 1); | |
7266 | int size = extract32(insn, 22, 2); | |
7267 | int opcode = extract32(insn, 12, 4); | |
7268 | int rm = extract32(insn, 16, 5); | |
7269 | int rn = extract32(insn, 5, 5); | |
7270 | int rd = extract32(insn, 0, 5); | |
7271 | ||
7272 | switch (opcode) { | |
7273 | case 1: /* SADDW, SADDW2, UADDW, UADDW2 */ | |
7274 | case 3: /* SSUBW, SSUBW2, USUBW, USUBW2 */ | |
7275 | /* 64 x 128 -> 128 */ | |
dfc15c7c PM |
7276 | if (size == 3) { |
7277 | unallocated_encoding(s); | |
7278 | return; | |
7279 | } | |
7280 | handle_3rd_wide(s, is_q, is_u, size, opcode, rd, rn, rm); | |
a08582f4 PM |
7281 | break; |
7282 | case 4: /* ADDHN, ADDHN2, RADDHN, RADDHN2 */ | |
7283 | case 6: /* SUBHN, SUBHN2, RSUBHN, RSUBHN2 */ | |
7284 | /* 128 x 128 -> 64 */ | |
e4b998d4 PM |
7285 | if (size == 3) { |
7286 | unallocated_encoding(s); | |
7287 | return; | |
7288 | } | |
7289 | handle_3rd_narrowing(s, is_q, is_u, size, opcode, rd, rn, rm); | |
a08582f4 | 7290 | break; |
70d7f984 PM |
7291 | case 14: /* PMULL, PMULL2 */ |
7292 | if (is_u || size == 1 || size == 2) { | |
7293 | unallocated_encoding(s); | |
7294 | return; | |
7295 | } | |
7296 | unsupported_encoding(s, insn); | |
7297 | break; | |
13caf1fd PM |
7298 | case 9: /* SQDMLAL, SQDMLAL2 */ |
7299 | case 11: /* SQDMLSL, SQDMLSL2 */ | |
7300 | case 13: /* SQDMULL, SQDMULL2 */ | |
70d7f984 | 7301 | if (is_u || size == 0) { |
a08582f4 PM |
7302 | unallocated_encoding(s); |
7303 | return; | |
7304 | } | |
7305 | /* fall through */ | |
13caf1fd PM |
7306 | case 0: /* SADDL, SADDL2, UADDL, UADDL2 */ |
7307 | case 2: /* SSUBL, SSUBL2, USUBL, USUBL2 */ | |
13caf1fd PM |
7308 | case 5: /* SABAL, SABAL2, UABAL, UABAL2 */ |
7309 | case 7: /* SABDL, SABDL2, UABDL, UABDL2 */ | |
7310 | case 8: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */ | |
7311 | case 10: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */ | |
7312 | case 12: /* SMULL, SMULL2, UMULL, UMULL2 */ | |
a08582f4 PM |
7313 | /* 64 x 64 -> 128 */ |
7314 | if (size == 3) { | |
7315 | unallocated_encoding(s); | |
7316 | return; | |
7317 | } | |
7318 | handle_3rd_widening(s, is_q, is_u, size, opcode, rd, rn, rm); | |
7319 | break; | |
7320 | default: | |
7321 | /* opcode 15 not allocated */ | |
7322 | unallocated_encoding(s); | |
7323 | break; | |
7324 | } | |
384b26fb AB |
7325 | } |
7326 | ||
e1cea114 PM |
7327 | /* Logic op (opcode == 3) subgroup of C3.6.16. */ |
7328 | static void disas_simd_3same_logic(DisasContext *s, uint32_t insn) | |
7329 | { | |
956d272e PM |
7330 | int rd = extract32(insn, 0, 5); |
7331 | int rn = extract32(insn, 5, 5); | |
7332 | int rm = extract32(insn, 16, 5); | |
7333 | int size = extract32(insn, 22, 2); | |
7334 | bool is_u = extract32(insn, 29, 1); | |
7335 | bool is_q = extract32(insn, 30, 1); | |
7336 | TCGv_i64 tcg_op1 = tcg_temp_new_i64(); | |
7337 | TCGv_i64 tcg_op2 = tcg_temp_new_i64(); | |
7338 | TCGv_i64 tcg_res[2]; | |
7339 | int pass; | |
7340 | ||
7341 | tcg_res[0] = tcg_temp_new_i64(); | |
7342 | tcg_res[1] = tcg_temp_new_i64(); | |
7343 | ||
7344 | for (pass = 0; pass < (is_q ? 2 : 1); pass++) { | |
7345 | read_vec_element(s, tcg_op1, rn, pass, MO_64); | |
7346 | read_vec_element(s, tcg_op2, rm, pass, MO_64); | |
7347 | ||
7348 | if (!is_u) { | |
7349 | switch (size) { | |
7350 | case 0: /* AND */ | |
7351 | tcg_gen_and_i64(tcg_res[pass], tcg_op1, tcg_op2); | |
7352 | break; | |
7353 | case 1: /* BIC */ | |
7354 | tcg_gen_andc_i64(tcg_res[pass], tcg_op1, tcg_op2); | |
7355 | break; | |
7356 | case 2: /* ORR */ | |
7357 | tcg_gen_or_i64(tcg_res[pass], tcg_op1, tcg_op2); | |
7358 | break; | |
7359 | case 3: /* ORN */ | |
7360 | tcg_gen_orc_i64(tcg_res[pass], tcg_op1, tcg_op2); | |
7361 | break; | |
7362 | } | |
7363 | } else { | |
7364 | if (size != 0) { | |
7365 | /* B* ops need res loaded to operate on */ | |
7366 | read_vec_element(s, tcg_res[pass], rd, pass, MO_64); | |
7367 | } | |
7368 | ||
7369 | switch (size) { | |
7370 | case 0: /* EOR */ | |
7371 | tcg_gen_xor_i64(tcg_res[pass], tcg_op1, tcg_op2); | |
7372 | break; | |
7373 | case 1: /* BSL bitwise select */ | |
7374 | tcg_gen_xor_i64(tcg_op1, tcg_op1, tcg_op2); | |
7375 | tcg_gen_and_i64(tcg_op1, tcg_op1, tcg_res[pass]); | |
7376 | tcg_gen_xor_i64(tcg_res[pass], tcg_op2, tcg_op1); | |
7377 | break; | |
7378 | case 2: /* BIT, bitwise insert if true */ | |
7379 | tcg_gen_xor_i64(tcg_op1, tcg_op1, tcg_res[pass]); | |
7380 | tcg_gen_and_i64(tcg_op1, tcg_op1, tcg_op2); | |
7381 | tcg_gen_xor_i64(tcg_res[pass], tcg_res[pass], tcg_op1); | |
7382 | break; | |
7383 | case 3: /* BIF, bitwise insert if false */ | |
7384 | tcg_gen_xor_i64(tcg_op1, tcg_op1, tcg_res[pass]); | |
7385 | tcg_gen_andc_i64(tcg_op1, tcg_op1, tcg_op2); | |
7386 | tcg_gen_xor_i64(tcg_res[pass], tcg_res[pass], tcg_op1); | |
7387 | break; | |
7388 | } | |
7389 | } | |
7390 | } | |
7391 | ||
7392 | write_vec_element(s, tcg_res[0], rd, 0, MO_64); | |
7393 | if (!is_q) { | |
7394 | tcg_gen_movi_i64(tcg_res[1], 0); | |
7395 | } | |
7396 | write_vec_element(s, tcg_res[1], rd, 1, MO_64); | |
7397 | ||
7398 | tcg_temp_free_i64(tcg_op1); | |
7399 | tcg_temp_free_i64(tcg_op2); | |
7400 | tcg_temp_free_i64(tcg_res[0]); | |
7401 | tcg_temp_free_i64(tcg_res[1]); | |
e1cea114 PM |
7402 | } |
7403 | ||
8b12a0cf PM |
7404 | /* Helper functions for 32 bit comparisons */ |
7405 | static void gen_max_s32(TCGv_i32 res, TCGv_i32 op1, TCGv_i32 op2) | |
7406 | { | |
7407 | tcg_gen_movcond_i32(TCG_COND_GE, res, op1, op2, op1, op2); | |
7408 | } | |
7409 | ||
7410 | static void gen_max_u32(TCGv_i32 res, TCGv_i32 op1, TCGv_i32 op2) | |
7411 | { | |
7412 | tcg_gen_movcond_i32(TCG_COND_GEU, res, op1, op2, op1, op2); | |
7413 | } | |
7414 | ||
7415 | static void gen_min_s32(TCGv_i32 res, TCGv_i32 op1, TCGv_i32 op2) | |
7416 | { | |
7417 | tcg_gen_movcond_i32(TCG_COND_LE, res, op1, op2, op1, op2); | |
7418 | } | |
7419 | ||
7420 | static void gen_min_u32(TCGv_i32 res, TCGv_i32 op1, TCGv_i32 op2) | |
7421 | { | |
7422 | tcg_gen_movcond_i32(TCG_COND_LEU, res, op1, op2, op1, op2); | |
7423 | } | |
7424 | ||
bc242f9b AB |
7425 | /* Pairwise op subgroup of C3.6.16. |
7426 | * | |
7427 | * This is called directly or via the handle_3same_float for float pairwise | |
7428 | * operations where the opcode and size are calculated differently. | |
7429 | */ | |
7430 | static void handle_simd_3same_pair(DisasContext *s, int is_q, int u, int opcode, | |
7431 | int size, int rn, int rm, int rd) | |
e1cea114 | 7432 | { |
bc242f9b | 7433 | TCGv_ptr fpst; |
0173a005 PM |
7434 | int pass; |
7435 | ||
bc242f9b AB |
7436 | /* Floating point operations need fpst */ |
7437 | if (opcode >= 0x58) { | |
7438 | fpst = get_fpstatus_ptr(); | |
7439 | } else { | |
7440 | TCGV_UNUSED_PTR(fpst); | |
0173a005 PM |
7441 | } |
7442 | ||
7443 | /* These operations work on the concatenated rm:rn, with each pair of | |
7444 | * adjacent elements being operated on to produce an element in the result. | |
7445 | */ | |
7446 | if (size == 3) { | |
7447 | TCGv_i64 tcg_res[2]; | |
7448 | ||
7449 | for (pass = 0; pass < 2; pass++) { | |
7450 | TCGv_i64 tcg_op1 = tcg_temp_new_i64(); | |
7451 | TCGv_i64 tcg_op2 = tcg_temp_new_i64(); | |
7452 | int passreg = (pass == 0) ? rn : rm; | |
7453 | ||
7454 | read_vec_element(s, tcg_op1, passreg, 0, MO_64); | |
7455 | read_vec_element(s, tcg_op2, passreg, 1, MO_64); | |
7456 | tcg_res[pass] = tcg_temp_new_i64(); | |
7457 | ||
bc242f9b AB |
7458 | switch (opcode) { |
7459 | case 0x17: /* ADDP */ | |
7460 | tcg_gen_add_i64(tcg_res[pass], tcg_op1, tcg_op2); | |
7461 | break; | |
7462 | case 0x58: /* FMAXNMP */ | |
7463 | gen_helper_vfp_maxnumd(tcg_res[pass], tcg_op1, tcg_op2, fpst); | |
7464 | break; | |
7465 | case 0x5a: /* FADDP */ | |
7466 | gen_helper_vfp_addd(tcg_res[pass], tcg_op1, tcg_op2, fpst); | |
7467 | break; | |
7468 | case 0x5e: /* FMAXP */ | |
7469 | gen_helper_vfp_maxd(tcg_res[pass], tcg_op1, tcg_op2, fpst); | |
7470 | break; | |
7471 | case 0x78: /* FMINNMP */ | |
7472 | gen_helper_vfp_minnumd(tcg_res[pass], tcg_op1, tcg_op2, fpst); | |
7473 | break; | |
7474 | case 0x7e: /* FMINP */ | |
7475 | gen_helper_vfp_mind(tcg_res[pass], tcg_op1, tcg_op2, fpst); | |
7476 | break; | |
7477 | default: | |
7478 | g_assert_not_reached(); | |
7479 | } | |
0173a005 PM |
7480 | |
7481 | tcg_temp_free_i64(tcg_op1); | |
7482 | tcg_temp_free_i64(tcg_op2); | |
7483 | } | |
7484 | ||
7485 | for (pass = 0; pass < 2; pass++) { | |
7486 | write_vec_element(s, tcg_res[pass], rd, pass, MO_64); | |
7487 | tcg_temp_free_i64(tcg_res[pass]); | |
7488 | } | |
7489 | } else { | |
7490 | int maxpass = is_q ? 4 : 2; | |
7491 | TCGv_i32 tcg_res[4]; | |
7492 | ||
7493 | for (pass = 0; pass < maxpass; pass++) { | |
7494 | TCGv_i32 tcg_op1 = tcg_temp_new_i32(); | |
7495 | TCGv_i32 tcg_op2 = tcg_temp_new_i32(); | |
bc242f9b | 7496 | NeonGenTwoOpFn *genfn = NULL; |
0173a005 PM |
7497 | int passreg = pass < (maxpass / 2) ? rn : rm; |
7498 | int passelt = (is_q && (pass & 1)) ? 2 : 0; | |
7499 | ||
7500 | read_vec_element_i32(s, tcg_op1, passreg, passelt, MO_32); | |
7501 | read_vec_element_i32(s, tcg_op2, passreg, passelt + 1, MO_32); | |
7502 | tcg_res[pass] = tcg_temp_new_i32(); | |
7503 | ||
7504 | switch (opcode) { | |
7505 | case 0x17: /* ADDP */ | |
7506 | { | |
7507 | static NeonGenTwoOpFn * const fns[3] = { | |
7508 | gen_helper_neon_padd_u8, | |
7509 | gen_helper_neon_padd_u16, | |
7510 | tcg_gen_add_i32, | |
7511 | }; | |
7512 | genfn = fns[size]; | |
7513 | break; | |
7514 | } | |
7515 | case 0x14: /* SMAXP, UMAXP */ | |
7516 | { | |
7517 | static NeonGenTwoOpFn * const fns[3][2] = { | |
7518 | { gen_helper_neon_pmax_s8, gen_helper_neon_pmax_u8 }, | |
7519 | { gen_helper_neon_pmax_s16, gen_helper_neon_pmax_u16 }, | |
7520 | { gen_max_s32, gen_max_u32 }, | |
7521 | }; | |
7522 | genfn = fns[size][u]; | |
7523 | break; | |
7524 | } | |
7525 | case 0x15: /* SMINP, UMINP */ | |
7526 | { | |
7527 | static NeonGenTwoOpFn * const fns[3][2] = { | |
7528 | { gen_helper_neon_pmin_s8, gen_helper_neon_pmin_u8 }, | |
7529 | { gen_helper_neon_pmin_s16, gen_helper_neon_pmin_u16 }, | |
7530 | { gen_min_s32, gen_min_u32 }, | |
7531 | }; | |
7532 | genfn = fns[size][u]; | |
7533 | break; | |
7534 | } | |
bc242f9b AB |
7535 | /* The FP operations are all on single floats (32 bit) */ |
7536 | case 0x58: /* FMAXNMP */ | |
7537 | gen_helper_vfp_maxnums(tcg_res[pass], tcg_op1, tcg_op2, fpst); | |
7538 | break; | |
7539 | case 0x5a: /* FADDP */ | |
7540 | gen_helper_vfp_adds(tcg_res[pass], tcg_op1, tcg_op2, fpst); | |
7541 | break; | |
7542 | case 0x5e: /* FMAXP */ | |
7543 | gen_helper_vfp_maxs(tcg_res[pass], tcg_op1, tcg_op2, fpst); | |
7544 | break; | |
7545 | case 0x78: /* FMINNMP */ | |
7546 | gen_helper_vfp_minnums(tcg_res[pass], tcg_op1, tcg_op2, fpst); | |
7547 | break; | |
7548 | case 0x7e: /* FMINP */ | |
7549 | gen_helper_vfp_mins(tcg_res[pass], tcg_op1, tcg_op2, fpst); | |
7550 | break; | |
0173a005 PM |
7551 | default: |
7552 | g_assert_not_reached(); | |
7553 | } | |
7554 | ||
bc242f9b AB |
7555 | /* FP ops called directly, otherwise call now */ |
7556 | if (genfn) { | |
7557 | genfn(tcg_res[pass], tcg_op1, tcg_op2); | |
7558 | } | |
0173a005 PM |
7559 | |
7560 | tcg_temp_free_i32(tcg_op1); | |
7561 | tcg_temp_free_i32(tcg_op2); | |
7562 | } | |
7563 | ||
7564 | for (pass = 0; pass < maxpass; pass++) { | |
7565 | write_vec_element_i32(s, tcg_res[pass], rd, pass, MO_32); | |
7566 | tcg_temp_free_i32(tcg_res[pass]); | |
7567 | } | |
7568 | if (!is_q) { | |
7569 | clear_vec_high(s, rd); | |
7570 | } | |
7571 | } | |
bc242f9b AB |
7572 | |
7573 | if (!TCGV_IS_UNUSED_PTR(fpst)) { | |
7574 | tcg_temp_free_ptr(fpst); | |
7575 | } | |
e1cea114 PM |
7576 | } |
7577 | ||
7578 | /* Floating point op subgroup of C3.6.16. */ | |
7579 | static void disas_simd_3same_float(DisasContext *s, uint32_t insn) | |
7580 | { | |
845ea09a PM |
7581 | /* For floating point ops, the U, size[1] and opcode bits |
7582 | * together indicate the operation. size[0] indicates single | |
7583 | * or double. | |
7584 | */ | |
7585 | int fpopcode = extract32(insn, 11, 5) | |
7586 | | (extract32(insn, 23, 1) << 5) | |
7587 | | (extract32(insn, 29, 1) << 6); | |
7588 | int is_q = extract32(insn, 30, 1); | |
7589 | int size = extract32(insn, 22, 1); | |
7590 | int rm = extract32(insn, 16, 5); | |
7591 | int rn = extract32(insn, 5, 5); | |
7592 | int rd = extract32(insn, 0, 5); | |
7593 | ||
7594 | int datasize = is_q ? 128 : 64; | |
7595 | int esize = 32 << size; | |
7596 | int elements = datasize / esize; | |
7597 | ||
7598 | if (size == 1 && !is_q) { | |
7599 | unallocated_encoding(s); | |
7600 | return; | |
7601 | } | |
7602 | ||
7603 | switch (fpopcode) { | |
7604 | case 0x58: /* FMAXNMP */ | |
7605 | case 0x5a: /* FADDP */ | |
7606 | case 0x5e: /* FMAXP */ | |
7607 | case 0x78: /* FMINNMP */ | |
7608 | case 0x7e: /* FMINP */ | |
bc242f9b AB |
7609 | if (size && !is_q) { |
7610 | unallocated_encoding(s); | |
7611 | return; | |
7612 | } | |
7613 | handle_simd_3same_pair(s, is_q, 0, fpopcode, size ? MO_64 : MO_32, | |
7614 | rn, rm, rd); | |
845ea09a PM |
7615 | return; |
7616 | case 0x1b: /* FMULX */ | |
845ea09a PM |
7617 | case 0x1f: /* FRECPS */ |
7618 | case 0x3f: /* FRSQRTS */ | |
845ea09a | 7619 | case 0x5d: /* FACGE */ |
845ea09a PM |
7620 | case 0x7d: /* FACGT */ |
7621 | case 0x19: /* FMLA */ | |
7622 | case 0x39: /* FMLS */ | |
845ea09a PM |
7623 | case 0x18: /* FMAXNM */ |
7624 | case 0x1a: /* FADD */ | |
8908f4d1 | 7625 | case 0x1c: /* FCMEQ */ |
845ea09a PM |
7626 | case 0x1e: /* FMAX */ |
7627 | case 0x38: /* FMINNM */ | |
7628 | case 0x3a: /* FSUB */ | |
7629 | case 0x3e: /* FMIN */ | |
7630 | case 0x5b: /* FMUL */ | |
8908f4d1 | 7631 | case 0x5c: /* FCMGE */ |
845ea09a PM |
7632 | case 0x5f: /* FDIV */ |
7633 | case 0x7a: /* FABD */ | |
8908f4d1 | 7634 | case 0x7c: /* FCMGT */ |
845ea09a PM |
7635 | handle_3same_float(s, size, elements, fpopcode, rd, rn, rm); |
7636 | return; | |
7637 | default: | |
7638 | unallocated_encoding(s); | |
7639 | return; | |
7640 | } | |
e1cea114 PM |
7641 | } |
7642 | ||
7643 | /* Integer op subgroup of C3.6.16. */ | |
7644 | static void disas_simd_3same_int(DisasContext *s, uint32_t insn) | |
7645 | { | |
1f8a73af PM |
7646 | int is_q = extract32(insn, 30, 1); |
7647 | int u = extract32(insn, 29, 1); | |
7648 | int size = extract32(insn, 22, 2); | |
7649 | int opcode = extract32(insn, 11, 5); | |
7650 | int rm = extract32(insn, 16, 5); | |
7651 | int rn = extract32(insn, 5, 5); | |
7652 | int rd = extract32(insn, 0, 5); | |
7653 | int pass; | |
7654 | ||
7655 | switch (opcode) { | |
7656 | case 0x13: /* MUL, PMUL */ | |
7657 | if (u && size != 0) { | |
7658 | unallocated_encoding(s); | |
7659 | return; | |
7660 | } | |
7661 | /* fall through */ | |
7662 | case 0x0: /* SHADD, UHADD */ | |
7663 | case 0x2: /* SRHADD, URHADD */ | |
7664 | case 0x4: /* SHSUB, UHSUB */ | |
7665 | case 0xc: /* SMAX, UMAX */ | |
7666 | case 0xd: /* SMIN, UMIN */ | |
7667 | case 0xe: /* SABD, UABD */ | |
7668 | case 0xf: /* SABA, UABA */ | |
7669 | case 0x12: /* MLA, MLS */ | |
7670 | if (size == 3) { | |
7671 | unallocated_encoding(s); | |
7672 | return; | |
7673 | } | |
8b12a0cf | 7674 | break; |
1f8a73af PM |
7675 | case 0x16: /* SQDMULH, SQRDMULH */ |
7676 | if (size == 0 || size == 3) { | |
7677 | unallocated_encoding(s); | |
7678 | return; | |
7679 | } | |
8b12a0cf | 7680 | break; |
1f8a73af PM |
7681 | default: |
7682 | if (size == 3 && !is_q) { | |
7683 | unallocated_encoding(s); | |
7684 | return; | |
7685 | } | |
7686 | break; | |
7687 | } | |
7688 | ||
7689 | if (size == 3) { | |
7690 | for (pass = 0; pass < (is_q ? 2 : 1); pass++) { | |
7691 | TCGv_i64 tcg_op1 = tcg_temp_new_i64(); | |
7692 | TCGv_i64 tcg_op2 = tcg_temp_new_i64(); | |
7693 | TCGv_i64 tcg_res = tcg_temp_new_i64(); | |
7694 | ||
7695 | read_vec_element(s, tcg_op1, rn, pass, MO_64); | |
7696 | read_vec_element(s, tcg_op2, rm, pass, MO_64); | |
7697 | ||
7698 | handle_3same_64(s, opcode, u, tcg_res, tcg_op1, tcg_op2); | |
7699 | ||
7700 | write_vec_element(s, tcg_res, rd, pass, MO_64); | |
7701 | ||
7702 | tcg_temp_free_i64(tcg_res); | |
7703 | tcg_temp_free_i64(tcg_op1); | |
7704 | tcg_temp_free_i64(tcg_op2); | |
7705 | } | |
7706 | } else { | |
7707 | for (pass = 0; pass < (is_q ? 4 : 2); pass++) { | |
7708 | TCGv_i32 tcg_op1 = tcg_temp_new_i32(); | |
7709 | TCGv_i32 tcg_op2 = tcg_temp_new_i32(); | |
7710 | TCGv_i32 tcg_res = tcg_temp_new_i32(); | |
6d9571f7 PM |
7711 | NeonGenTwoOpFn *genfn = NULL; |
7712 | NeonGenTwoOpEnvFn *genenvfn = NULL; | |
1f8a73af PM |
7713 | |
7714 | read_vec_element_i32(s, tcg_op1, rn, pass, MO_32); | |
7715 | read_vec_element_i32(s, tcg_op2, rm, pass, MO_32); | |
7716 | ||
7717 | switch (opcode) { | |
8b12a0cf PM |
7718 | case 0x0: /* SHADD, UHADD */ |
7719 | { | |
7720 | static NeonGenTwoOpFn * const fns[3][2] = { | |
7721 | { gen_helper_neon_hadd_s8, gen_helper_neon_hadd_u8 }, | |
7722 | { gen_helper_neon_hadd_s16, gen_helper_neon_hadd_u16 }, | |
7723 | { gen_helper_neon_hadd_s32, gen_helper_neon_hadd_u32 }, | |
7724 | }; | |
7725 | genfn = fns[size][u]; | |
7726 | break; | |
7727 | } | |
6d9571f7 PM |
7728 | case 0x1: /* SQADD, UQADD */ |
7729 | { | |
7730 | static NeonGenTwoOpEnvFn * const fns[3][2] = { | |
7731 | { gen_helper_neon_qadd_s8, gen_helper_neon_qadd_u8 }, | |
7732 | { gen_helper_neon_qadd_s16, gen_helper_neon_qadd_u16 }, | |
7733 | { gen_helper_neon_qadd_s32, gen_helper_neon_qadd_u32 }, | |
7734 | }; | |
7735 | genenvfn = fns[size][u]; | |
7736 | break; | |
7737 | } | |
8b12a0cf PM |
7738 | case 0x2: /* SRHADD, URHADD */ |
7739 | { | |
7740 | static NeonGenTwoOpFn * const fns[3][2] = { | |
7741 | { gen_helper_neon_rhadd_s8, gen_helper_neon_rhadd_u8 }, | |
7742 | { gen_helper_neon_rhadd_s16, gen_helper_neon_rhadd_u16 }, | |
7743 | { gen_helper_neon_rhadd_s32, gen_helper_neon_rhadd_u32 }, | |
7744 | }; | |
7745 | genfn = fns[size][u]; | |
7746 | break; | |
7747 | } | |
7748 | case 0x4: /* SHSUB, UHSUB */ | |
7749 | { | |
7750 | static NeonGenTwoOpFn * const fns[3][2] = { | |
7751 | { gen_helper_neon_hsub_s8, gen_helper_neon_hsub_u8 }, | |
7752 | { gen_helper_neon_hsub_s16, gen_helper_neon_hsub_u16 }, | |
7753 | { gen_helper_neon_hsub_s32, gen_helper_neon_hsub_u32 }, | |
7754 | }; | |
7755 | genfn = fns[size][u]; | |
7756 | break; | |
7757 | } | |
6d9571f7 PM |
7758 | case 0x5: /* SQSUB, UQSUB */ |
7759 | { | |
7760 | static NeonGenTwoOpEnvFn * const fns[3][2] = { | |
7761 | { gen_helper_neon_qsub_s8, gen_helper_neon_qsub_u8 }, | |
7762 | { gen_helper_neon_qsub_s16, gen_helper_neon_qsub_u16 }, | |
7763 | { gen_helper_neon_qsub_s32, gen_helper_neon_qsub_u32 }, | |
7764 | }; | |
7765 | genenvfn = fns[size][u]; | |
7766 | break; | |
7767 | } | |
1f8a73af PM |
7768 | case 0x6: /* CMGT, CMHI */ |
7769 | { | |
7770 | static NeonGenTwoOpFn * const fns[3][2] = { | |
7771 | { gen_helper_neon_cgt_s8, gen_helper_neon_cgt_u8 }, | |
7772 | { gen_helper_neon_cgt_s16, gen_helper_neon_cgt_u16 }, | |
7773 | { gen_helper_neon_cgt_s32, gen_helper_neon_cgt_u32 }, | |
7774 | }; | |
7775 | genfn = fns[size][u]; | |
7776 | break; | |
7777 | } | |
7778 | case 0x7: /* CMGE, CMHS */ | |
7779 | { | |
7780 | static NeonGenTwoOpFn * const fns[3][2] = { | |
7781 | { gen_helper_neon_cge_s8, gen_helper_neon_cge_u8 }, | |
7782 | { gen_helper_neon_cge_s16, gen_helper_neon_cge_u16 }, | |
7783 | { gen_helper_neon_cge_s32, gen_helper_neon_cge_u32 }, | |
7784 | }; | |
7785 | genfn = fns[size][u]; | |
7786 | break; | |
7787 | } | |
6d9571f7 PM |
7788 | case 0x8: /* SSHL, USHL */ |
7789 | { | |
7790 | static NeonGenTwoOpFn * const fns[3][2] = { | |
7791 | { gen_helper_neon_shl_s8, gen_helper_neon_shl_u8 }, | |
7792 | { gen_helper_neon_shl_s16, gen_helper_neon_shl_u16 }, | |
7793 | { gen_helper_neon_shl_s32, gen_helper_neon_shl_u32 }, | |
7794 | }; | |
7795 | genfn = fns[size][u]; | |
7796 | break; | |
7797 | } | |
7798 | case 0x9: /* SQSHL, UQSHL */ | |
7799 | { | |
7800 | static NeonGenTwoOpEnvFn * const fns[3][2] = { | |
7801 | { gen_helper_neon_qshl_s8, gen_helper_neon_qshl_u8 }, | |
7802 | { gen_helper_neon_qshl_s16, gen_helper_neon_qshl_u16 }, | |
7803 | { gen_helper_neon_qshl_s32, gen_helper_neon_qshl_u32 }, | |
7804 | }; | |
7805 | genenvfn = fns[size][u]; | |
7806 | break; | |
7807 | } | |
7808 | case 0xa: /* SRSHL, URSHL */ | |
7809 | { | |
7810 | static NeonGenTwoOpFn * const fns[3][2] = { | |
7811 | { gen_helper_neon_rshl_s8, gen_helper_neon_rshl_u8 }, | |
7812 | { gen_helper_neon_rshl_s16, gen_helper_neon_rshl_u16 }, | |
7813 | { gen_helper_neon_rshl_s32, gen_helper_neon_rshl_u32 }, | |
7814 | }; | |
7815 | genfn = fns[size][u]; | |
7816 | break; | |
7817 | } | |
7818 | case 0xb: /* SQRSHL, UQRSHL */ | |
7819 | { | |
7820 | static NeonGenTwoOpEnvFn * const fns[3][2] = { | |
7821 | { gen_helper_neon_qrshl_s8, gen_helper_neon_qrshl_u8 }, | |
7822 | { gen_helper_neon_qrshl_s16, gen_helper_neon_qrshl_u16 }, | |
7823 | { gen_helper_neon_qrshl_s32, gen_helper_neon_qrshl_u32 }, | |
7824 | }; | |
7825 | genenvfn = fns[size][u]; | |
7826 | break; | |
7827 | } | |
8b12a0cf PM |
7828 | case 0xc: /* SMAX, UMAX */ |
7829 | { | |
7830 | static NeonGenTwoOpFn * const fns[3][2] = { | |
7831 | { gen_helper_neon_max_s8, gen_helper_neon_max_u8 }, | |
7832 | { gen_helper_neon_max_s16, gen_helper_neon_max_u16 }, | |
7833 | { gen_max_s32, gen_max_u32 }, | |
7834 | }; | |
7835 | genfn = fns[size][u]; | |
7836 | break; | |
7837 | } | |
7838 | ||
7839 | case 0xd: /* SMIN, UMIN */ | |
7840 | { | |
7841 | static NeonGenTwoOpFn * const fns[3][2] = { | |
7842 | { gen_helper_neon_min_s8, gen_helper_neon_min_u8 }, | |
7843 | { gen_helper_neon_min_s16, gen_helper_neon_min_u16 }, | |
7844 | { gen_min_s32, gen_min_u32 }, | |
7845 | }; | |
7846 | genfn = fns[size][u]; | |
7847 | break; | |
7848 | } | |
7849 | case 0xe: /* SABD, UABD */ | |
7850 | case 0xf: /* SABA, UABA */ | |
7851 | { | |
7852 | static NeonGenTwoOpFn * const fns[3][2] = { | |
7853 | { gen_helper_neon_abd_s8, gen_helper_neon_abd_u8 }, | |
7854 | { gen_helper_neon_abd_s16, gen_helper_neon_abd_u16 }, | |
7855 | { gen_helper_neon_abd_s32, gen_helper_neon_abd_u32 }, | |
7856 | }; | |
7857 | genfn = fns[size][u]; | |
7858 | break; | |
7859 | } | |
1f8a73af PM |
7860 | case 0x10: /* ADD, SUB */ |
7861 | { | |
7862 | static NeonGenTwoOpFn * const fns[3][2] = { | |
7863 | { gen_helper_neon_add_u8, gen_helper_neon_sub_u8 }, | |
7864 | { gen_helper_neon_add_u16, gen_helper_neon_sub_u16 }, | |
7865 | { tcg_gen_add_i32, tcg_gen_sub_i32 }, | |
7866 | }; | |
7867 | genfn = fns[size][u]; | |
7868 | break; | |
7869 | } | |
7870 | case 0x11: /* CMTST, CMEQ */ | |
7871 | { | |
7872 | static NeonGenTwoOpFn * const fns[3][2] = { | |
7873 | { gen_helper_neon_tst_u8, gen_helper_neon_ceq_u8 }, | |
7874 | { gen_helper_neon_tst_u16, gen_helper_neon_ceq_u16 }, | |
7875 | { gen_helper_neon_tst_u32, gen_helper_neon_ceq_u32 }, | |
7876 | }; | |
7877 | genfn = fns[size][u]; | |
7878 | break; | |
7879 | } | |
8b12a0cf PM |
7880 | case 0x13: /* MUL, PMUL */ |
7881 | if (u) { | |
7882 | /* PMUL */ | |
7883 | assert(size == 0); | |
7884 | genfn = gen_helper_neon_mul_p8; | |
7885 | break; | |
7886 | } | |
7887 | /* fall through : MUL */ | |
7888 | case 0x12: /* MLA, MLS */ | |
7889 | { | |
7890 | static NeonGenTwoOpFn * const fns[3] = { | |
7891 | gen_helper_neon_mul_u8, | |
7892 | gen_helper_neon_mul_u16, | |
7893 | tcg_gen_mul_i32, | |
7894 | }; | |
7895 | genfn = fns[size]; | |
7896 | break; | |
7897 | } | |
7898 | case 0x16: /* SQDMULH, SQRDMULH */ | |
7899 | { | |
7900 | static NeonGenTwoOpEnvFn * const fns[2][2] = { | |
7901 | { gen_helper_neon_qdmulh_s16, gen_helper_neon_qrdmulh_s16 }, | |
7902 | { gen_helper_neon_qdmulh_s32, gen_helper_neon_qrdmulh_s32 }, | |
7903 | }; | |
7904 | assert(size == 1 || size == 2); | |
7905 | genenvfn = fns[size - 1][u]; | |
7906 | break; | |
7907 | } | |
1f8a73af PM |
7908 | default: |
7909 | g_assert_not_reached(); | |
7910 | } | |
7911 | ||
6d9571f7 PM |
7912 | if (genenvfn) { |
7913 | genenvfn(tcg_res, cpu_env, tcg_op1, tcg_op2); | |
7914 | } else { | |
7915 | genfn(tcg_res, tcg_op1, tcg_op2); | |
7916 | } | |
1f8a73af | 7917 | |
8b12a0cf PM |
7918 | if (opcode == 0xf || opcode == 0x12) { |
7919 | /* SABA, UABA, MLA, MLS: accumulating ops */ | |
7920 | static NeonGenTwoOpFn * const fns[3][2] = { | |
7921 | { gen_helper_neon_add_u8, gen_helper_neon_sub_u8 }, | |
7922 | { gen_helper_neon_add_u16, gen_helper_neon_sub_u16 }, | |
7923 | { tcg_gen_add_i32, tcg_gen_sub_i32 }, | |
7924 | }; | |
7925 | bool is_sub = (opcode == 0x12 && u); /* MLS */ | |
7926 | ||
7927 | genfn = fns[size][is_sub]; | |
7928 | read_vec_element_i32(s, tcg_op1, rd, pass, MO_32); | |
7929 | genfn(tcg_res, tcg_res, tcg_op1); | |
7930 | } | |
7931 | ||
1f8a73af PM |
7932 | write_vec_element_i32(s, tcg_res, rd, pass, MO_32); |
7933 | ||
7934 | tcg_temp_free_i32(tcg_res); | |
7935 | tcg_temp_free_i32(tcg_op1); | |
7936 | tcg_temp_free_i32(tcg_op2); | |
7937 | } | |
7938 | } | |
7939 | ||
7940 | if (!is_q) { | |
7941 | clear_vec_high(s, rd); | |
7942 | } | |
e1cea114 PM |
7943 | } |
7944 | ||
384b26fb AB |
7945 | /* C3.6.16 AdvSIMD three same |
7946 | * 31 30 29 28 24 23 22 21 20 16 15 11 10 9 5 4 0 | |
7947 | * +---+---+---+-----------+------+---+------+--------+---+------+------+ | |
7948 | * | 0 | Q | U | 0 1 1 1 0 | size | 1 | Rm | opcode | 1 | Rn | Rd | | |
7949 | * +---+---+---+-----------+------+---+------+--------+---+------+------+ | |
7950 | */ | |
7951 | static void disas_simd_three_reg_same(DisasContext *s, uint32_t insn) | |
7952 | { | |
e1cea114 PM |
7953 | int opcode = extract32(insn, 11, 5); |
7954 | ||
7955 | switch (opcode) { | |
7956 | case 0x3: /* logic ops */ | |
7957 | disas_simd_3same_logic(s, insn); | |
7958 | break; | |
7959 | case 0x17: /* ADDP */ | |
7960 | case 0x14: /* SMAXP, UMAXP */ | |
7961 | case 0x15: /* SMINP, UMINP */ | |
bc242f9b | 7962 | { |
e1cea114 | 7963 | /* Pairwise operations */ |
bc242f9b AB |
7964 | int is_q = extract32(insn, 30, 1); |
7965 | int u = extract32(insn, 29, 1); | |
7966 | int size = extract32(insn, 22, 2); | |
7967 | int rm = extract32(insn, 16, 5); | |
7968 | int rn = extract32(insn, 5, 5); | |
7969 | int rd = extract32(insn, 0, 5); | |
7970 | if (opcode == 0x17) { | |
7971 | if (u || (size == 3 && !is_q)) { | |
7972 | unallocated_encoding(s); | |
7973 | return; | |
7974 | } | |
7975 | } else { | |
7976 | if (size == 3) { | |
7977 | unallocated_encoding(s); | |
7978 | return; | |
7979 | } | |
7980 | } | |
7981 | handle_simd_3same_pair(s, is_q, u, opcode, size, rn, rm, rd); | |
e1cea114 | 7982 | break; |
bc242f9b | 7983 | } |
e1cea114 PM |
7984 | case 0x18 ... 0x31: |
7985 | /* floating point ops, sz[1] and U are part of opcode */ | |
7986 | disas_simd_3same_float(s, insn); | |
7987 | break; | |
7988 | default: | |
7989 | disas_simd_3same_int(s, insn); | |
7990 | break; | |
7991 | } | |
384b26fb AB |
7992 | } |
7993 | ||
d980fd59 PM |
7994 | static void handle_2misc_narrow(DisasContext *s, int opcode, bool u, bool is_q, |
7995 | int size, int rn, int rd) | |
7996 | { | |
7997 | /* Handle 2-reg-misc ops which are narrowing (so each 2*size element | |
7998 | * in the source becomes a size element in the destination). | |
7999 | */ | |
8000 | int pass; | |
8001 | TCGv_i32 tcg_res[2]; | |
8002 | int destelt = is_q ? 2 : 0; | |
8003 | ||
8004 | for (pass = 0; pass < 2; pass++) { | |
8005 | TCGv_i64 tcg_op = tcg_temp_new_i64(); | |
8006 | NeonGenNarrowFn *genfn = NULL; | |
8007 | NeonGenNarrowEnvFn *genenvfn = NULL; | |
8008 | ||
8009 | read_vec_element(s, tcg_op, rn, pass, MO_64); | |
8010 | tcg_res[pass] = tcg_temp_new_i32(); | |
8011 | ||
8012 | switch (opcode) { | |
8013 | case 0x12: /* XTN, SQXTUN */ | |
8014 | { | |
8015 | static NeonGenNarrowFn * const xtnfns[3] = { | |
8016 | gen_helper_neon_narrow_u8, | |
8017 | gen_helper_neon_narrow_u16, | |
8018 | tcg_gen_trunc_i64_i32, | |
8019 | }; | |
8020 | static NeonGenNarrowEnvFn * const sqxtunfns[3] = { | |
8021 | gen_helper_neon_unarrow_sat8, | |
8022 | gen_helper_neon_unarrow_sat16, | |
8023 | gen_helper_neon_unarrow_sat32, | |
8024 | }; | |
8025 | if (u) { | |
8026 | genenvfn = sqxtunfns[size]; | |
8027 | } else { | |
8028 | genfn = xtnfns[size]; | |
8029 | } | |
8030 | break; | |
8031 | } | |
8032 | case 0x14: /* SQXTN, UQXTN */ | |
8033 | { | |
8034 | static NeonGenNarrowEnvFn * const fns[3][2] = { | |
8035 | { gen_helper_neon_narrow_sat_s8, | |
8036 | gen_helper_neon_narrow_sat_u8 }, | |
8037 | { gen_helper_neon_narrow_sat_s16, | |
8038 | gen_helper_neon_narrow_sat_u16 }, | |
8039 | { gen_helper_neon_narrow_sat_s32, | |
8040 | gen_helper_neon_narrow_sat_u32 }, | |
8041 | }; | |
8042 | genenvfn = fns[size][u]; | |
8043 | break; | |
8044 | } | |
8045 | default: | |
8046 | g_assert_not_reached(); | |
8047 | } | |
8048 | ||
8049 | if (genfn) { | |
8050 | genfn(tcg_res[pass], tcg_op); | |
8051 | } else { | |
8052 | genenvfn(tcg_res[pass], cpu_env, tcg_op); | |
8053 | } | |
8054 | ||
8055 | tcg_temp_free_i64(tcg_op); | |
8056 | } | |
8057 | ||
8058 | for (pass = 0; pass < 2; pass++) { | |
8059 | write_vec_element_i32(s, tcg_res[pass], rd, destelt + pass, MO_32); | |
8060 | tcg_temp_free_i32(tcg_res[pass]); | |
8061 | } | |
8062 | if (!is_q) { | |
8063 | clear_vec_high(s, rd); | |
8064 | } | |
8065 | } | |
8066 | ||
39d82118 AB |
8067 | static void handle_rev(DisasContext *s, int opcode, bool u, |
8068 | bool is_q, int size, int rn, int rd) | |
8069 | { | |
8070 | int op = (opcode << 1) | u; | |
8071 | int opsz = op + size; | |
8072 | int grp_size = 3 - opsz; | |
8073 | int dsize = is_q ? 128 : 64; | |
8074 | int i; | |
8075 | ||
8076 | if (opsz >= 3) { | |
8077 | unallocated_encoding(s); | |
8078 | return; | |
8079 | } | |
8080 | ||
8081 | if (size == 0) { | |
8082 | /* Special case bytes, use bswap op on each group of elements */ | |
8083 | int groups = dsize / (8 << grp_size); | |
8084 | ||
8085 | for (i = 0; i < groups; i++) { | |
8086 | TCGv_i64 tcg_tmp = tcg_temp_new_i64(); | |
8087 | ||
8088 | read_vec_element(s, tcg_tmp, rn, i, grp_size); | |
8089 | switch (grp_size) { | |
8090 | case MO_16: | |
8091 | tcg_gen_bswap16_i64(tcg_tmp, tcg_tmp); | |
8092 | break; | |
8093 | case MO_32: | |
8094 | tcg_gen_bswap32_i64(tcg_tmp, tcg_tmp); | |
8095 | break; | |
8096 | case MO_64: | |
8097 | tcg_gen_bswap64_i64(tcg_tmp, tcg_tmp); | |
8098 | break; | |
8099 | default: | |
8100 | g_assert_not_reached(); | |
8101 | } | |
8102 | write_vec_element(s, tcg_tmp, rd, i, grp_size); | |
8103 | tcg_temp_free_i64(tcg_tmp); | |
8104 | } | |
8105 | if (!is_q) { | |
8106 | clear_vec_high(s, rd); | |
8107 | } | |
8108 | } else { | |
8109 | int revmask = (1 << grp_size) - 1; | |
8110 | int esize = 8 << size; | |
8111 | int elements = dsize / esize; | |
8112 | TCGv_i64 tcg_rn = tcg_temp_new_i64(); | |
8113 | TCGv_i64 tcg_rd = tcg_const_i64(0); | |
8114 | TCGv_i64 tcg_rd_hi = tcg_const_i64(0); | |
8115 | ||
8116 | for (i = 0; i < elements; i++) { | |
8117 | int e_rev = (i & 0xf) ^ revmask; | |
8118 | int off = e_rev * esize; | |
8119 | read_vec_element(s, tcg_rn, rn, i, size); | |
8120 | if (off >= 64) { | |
8121 | tcg_gen_deposit_i64(tcg_rd_hi, tcg_rd_hi, | |
8122 | tcg_rn, off - 64, esize); | |
8123 | } else { | |
8124 | tcg_gen_deposit_i64(tcg_rd, tcg_rd, tcg_rn, off, esize); | |
8125 | } | |
8126 | } | |
8127 | write_vec_element(s, tcg_rd, rd, 0, MO_64); | |
8128 | write_vec_element(s, tcg_rd_hi, rd, 1, MO_64); | |
8129 | ||
8130 | tcg_temp_free_i64(tcg_rd_hi); | |
8131 | tcg_temp_free_i64(tcg_rd); | |
8132 | tcg_temp_free_i64(tcg_rn); | |
8133 | } | |
8134 | } | |
8135 | ||
384b26fb AB |
8136 | /* C3.6.17 AdvSIMD two reg misc |
8137 | * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0 | |
8138 | * +---+---+---+-----------+------+-----------+--------+-----+------+------+ | |
8139 | * | 0 | Q | U | 0 1 1 1 0 | size | 1 0 0 0 0 | opcode | 1 0 | Rn | Rd | | |
8140 | * +---+---+---+-----------+------+-----------+--------+-----+------+------+ | |
8141 | */ | |
8142 | static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn) | |
8143 | { | |
45aecc6d PM |
8144 | int size = extract32(insn, 22, 2); |
8145 | int opcode = extract32(insn, 12, 5); | |
8146 | bool u = extract32(insn, 29, 1); | |
8147 | bool is_q = extract32(insn, 30, 1); | |
94b6c911 PM |
8148 | int rn = extract32(insn, 5, 5); |
8149 | int rd = extract32(insn, 0, 5); | |
45aecc6d PM |
8150 | |
8151 | switch (opcode) { | |
8152 | case 0x0: /* REV64, REV32 */ | |
8153 | case 0x1: /* REV16 */ | |
39d82118 | 8154 | handle_rev(s, opcode, u, is_q, size, rn, rd); |
45aecc6d | 8155 | return; |
86cbc418 PM |
8156 | case 0x5: /* CNT, NOT, RBIT */ |
8157 | if (u && size == 0) { | |
8158 | /* NOT: adjust size so we can use the 64-bits-at-a-time loop. */ | |
8159 | size = 3; | |
8160 | break; | |
8161 | } else if (u && size == 1) { | |
8162 | /* RBIT */ | |
8163 | break; | |
8164 | } else if (!u && size == 0) { | |
8165 | /* CNT */ | |
8166 | break; | |
45aecc6d | 8167 | } |
86cbc418 | 8168 | unallocated_encoding(s); |
45aecc6d | 8169 | return; |
d980fd59 PM |
8170 | case 0x12: /* XTN, XTN2, SQXTUN, SQXTUN2 */ |
8171 | case 0x14: /* SQXTN, SQXTN2, UQXTN, UQXTN2 */ | |
8172 | if (size == 3) { | |
8173 | unallocated_encoding(s); | |
8174 | return; | |
8175 | } | |
8176 | handle_2misc_narrow(s, opcode, u, is_q, size, rn, rd); | |
8177 | return; | |
45aecc6d PM |
8178 | case 0x2: /* SADDLP, UADDLP */ |
8179 | case 0x4: /* CLS, CLZ */ | |
8180 | case 0x6: /* SADALP, UADALP */ | |
45aecc6d PM |
8181 | if (size == 3) { |
8182 | unallocated_encoding(s); | |
8183 | return; | |
8184 | } | |
8185 | unsupported_encoding(s, insn); | |
8186 | return; | |
8187 | case 0x13: /* SHLL, SHLL2 */ | |
8188 | if (u == 0 || size == 3) { | |
8189 | unallocated_encoding(s); | |
8190 | return; | |
8191 | } | |
8192 | unsupported_encoding(s, insn); | |
8193 | return; | |
8194 | case 0xa: /* CMLT */ | |
8195 | if (u == 1) { | |
8196 | unallocated_encoding(s); | |
8197 | return; | |
8198 | } | |
8199 | /* fall through */ | |
45aecc6d PM |
8200 | case 0x8: /* CMGT, CMGE */ |
8201 | case 0x9: /* CMEQ, CMLE */ | |
8202 | case 0xb: /* ABS, NEG */ | |
94b6c911 PM |
8203 | if (size == 3 && !is_q) { |
8204 | unallocated_encoding(s); | |
8205 | return; | |
8206 | } | |
8207 | break; | |
8208 | case 0x3: /* SUQADD, USQADD */ | |
8209 | case 0x7: /* SQABS, SQNEG */ | |
45aecc6d PM |
8210 | if (size == 3 && !is_q) { |
8211 | unallocated_encoding(s); | |
8212 | return; | |
8213 | } | |
8214 | unsupported_encoding(s, insn); | |
8215 | return; | |
8216 | case 0xc ... 0xf: | |
8217 | case 0x16 ... 0x1d: | |
8218 | case 0x1f: | |
8219 | { | |
8220 | /* Floating point: U, size[1] and opcode indicate operation; | |
8221 | * size[0] indicates single or double precision. | |
8222 | */ | |
8223 | opcode |= (extract32(size, 1, 1) << 5) | (u << 6); | |
8224 | size = extract32(size, 0, 1) ? 3 : 2; | |
8225 | switch (opcode) { | |
f93d0138 PM |
8226 | case 0x2f: /* FABS */ |
8227 | case 0x6f: /* FNEG */ | |
8228 | if (size == 3 && !is_q) { | |
8229 | unallocated_encoding(s); | |
8230 | return; | |
8231 | } | |
8232 | break; | |
8908f4d1 AB |
8233 | case 0x2c: /* FCMGT (zero) */ |
8234 | case 0x2d: /* FCMEQ (zero) */ | |
8235 | case 0x2e: /* FCMLT (zero) */ | |
8236 | case 0x6c: /* FCMGE (zero) */ | |
8237 | case 0x6d: /* FCMLE (zero) */ | |
8238 | if (size == 3 && !is_q) { | |
8239 | unallocated_encoding(s); | |
8240 | return; | |
8241 | } | |
8242 | handle_2misc_fcmp_zero(s, opcode, false, u, is_q, size, rn, rd); | |
8243 | return; | |
45aecc6d PM |
8244 | case 0x16: /* FCVTN, FCVTN2 */ |
8245 | case 0x17: /* FCVTL, FCVTL2 */ | |
8246 | case 0x18: /* FRINTN */ | |
8247 | case 0x19: /* FRINTM */ | |
8248 | case 0x1a: /* FCVTNS */ | |
8249 | case 0x1b: /* FCVTMS */ | |
8250 | case 0x1c: /* FCVTAS */ | |
8251 | case 0x1d: /* SCVTF */ | |
45aecc6d PM |
8252 | case 0x38: /* FRINTP */ |
8253 | case 0x39: /* FRINTZ */ | |
8254 | case 0x3a: /* FCVTPS */ | |
8255 | case 0x3b: /* FCVTZS */ | |
8256 | case 0x3c: /* URECPE */ | |
8257 | case 0x3d: /* FRECPE */ | |
8258 | case 0x56: /* FCVTXN, FCVTXN2 */ | |
8259 | case 0x58: /* FRINTA */ | |
8260 | case 0x59: /* FRINTX */ | |
8261 | case 0x5a: /* FCVTNU */ | |
8262 | case 0x5b: /* FCVTMU */ | |
8263 | case 0x5c: /* FCVTAU */ | |
8264 | case 0x5d: /* UCVTF */ | |
45aecc6d PM |
8265 | case 0x79: /* FRINTI */ |
8266 | case 0x7a: /* FCVTPU */ | |
8267 | case 0x7b: /* FCVTZU */ | |
8268 | case 0x7c: /* URSQRTE */ | |
8269 | case 0x7d: /* FRSQRTE */ | |
8270 | case 0x7f: /* FSQRT */ | |
8271 | unsupported_encoding(s, insn); | |
8272 | return; | |
8273 | default: | |
8274 | unallocated_encoding(s); | |
8275 | return; | |
8276 | } | |
8277 | break; | |
8278 | } | |
8279 | default: | |
8280 | unallocated_encoding(s); | |
8281 | return; | |
8282 | } | |
94b6c911 PM |
8283 | |
8284 | if (size == 3) { | |
8285 | /* All 64-bit element operations can be shared with scalar 2misc */ | |
8286 | int pass; | |
8287 | ||
8288 | for (pass = 0; pass < (is_q ? 2 : 1); pass++) { | |
8289 | TCGv_i64 tcg_op = tcg_temp_new_i64(); | |
8290 | TCGv_i64 tcg_res = tcg_temp_new_i64(); | |
8291 | ||
8292 | read_vec_element(s, tcg_op, rn, pass, MO_64); | |
8293 | ||
8294 | handle_2misc_64(s, opcode, u, tcg_res, tcg_op); | |
8295 | ||
8296 | write_vec_element(s, tcg_res, rd, pass, MO_64); | |
8297 | ||
8298 | tcg_temp_free_i64(tcg_res); | |
8299 | tcg_temp_free_i64(tcg_op); | |
8300 | } | |
8301 | } else { | |
8302 | int pass; | |
8303 | ||
8304 | for (pass = 0; pass < (is_q ? 4 : 2); pass++) { | |
8305 | TCGv_i32 tcg_op = tcg_temp_new_i32(); | |
8306 | TCGv_i32 tcg_res = tcg_temp_new_i32(); | |
8307 | TCGCond cond; | |
8308 | ||
8309 | read_vec_element_i32(s, tcg_op, rn, pass, MO_32); | |
8310 | ||
8311 | if (size == 2) { | |
8312 | /* Special cases for 32 bit elements */ | |
8313 | switch (opcode) { | |
8314 | case 0xa: /* CMLT */ | |
8315 | /* 32 bit integer comparison against zero, result is | |
8316 | * test ? (2^32 - 1) : 0. We implement via setcond(test) | |
8317 | * and inverting. | |
8318 | */ | |
8319 | cond = TCG_COND_LT; | |
8320 | do_cmop: | |
8321 | tcg_gen_setcondi_i32(cond, tcg_res, tcg_op, 0); | |
8322 | tcg_gen_neg_i32(tcg_res, tcg_res); | |
8323 | break; | |
8324 | case 0x8: /* CMGT, CMGE */ | |
8325 | cond = u ? TCG_COND_GE : TCG_COND_GT; | |
8326 | goto do_cmop; | |
8327 | case 0x9: /* CMEQ, CMLE */ | |
8328 | cond = u ? TCG_COND_LE : TCG_COND_EQ; | |
8329 | goto do_cmop; | |
8330 | case 0xb: /* ABS, NEG */ | |
8331 | if (u) { | |
8332 | tcg_gen_neg_i32(tcg_res, tcg_op); | |
8333 | } else { | |
8334 | TCGv_i32 tcg_zero = tcg_const_i32(0); | |
8335 | tcg_gen_neg_i32(tcg_res, tcg_op); | |
8336 | tcg_gen_movcond_i32(TCG_COND_GT, tcg_res, tcg_op, | |
8337 | tcg_zero, tcg_op, tcg_res); | |
8338 | tcg_temp_free_i32(tcg_zero); | |
8339 | } | |
8340 | break; | |
f93d0138 PM |
8341 | case 0x2f: /* FABS */ |
8342 | gen_helper_vfp_abss(tcg_res, tcg_op); | |
8343 | break; | |
8344 | case 0x6f: /* FNEG */ | |
8345 | gen_helper_vfp_negs(tcg_res, tcg_op); | |
8346 | break; | |
94b6c911 PM |
8347 | default: |
8348 | g_assert_not_reached(); | |
8349 | } | |
8350 | } else { | |
8351 | /* Use helpers for 8 and 16 bit elements */ | |
8352 | switch (opcode) { | |
86cbc418 PM |
8353 | case 0x5: /* CNT, RBIT */ |
8354 | /* For these two insns size is part of the opcode specifier | |
8355 | * (handled earlier); they always operate on byte elements. | |
8356 | */ | |
8357 | if (u) { | |
8358 | gen_helper_neon_rbit_u8(tcg_res, tcg_op); | |
8359 | } else { | |
8360 | gen_helper_neon_cnt_u8(tcg_res, tcg_op); | |
8361 | } | |
8362 | break; | |
94b6c911 PM |
8363 | case 0x8: /* CMGT, CMGE */ |
8364 | case 0x9: /* CMEQ, CMLE */ | |
8365 | case 0xa: /* CMLT */ | |
8366 | { | |
8367 | static NeonGenTwoOpFn * const fns[3][2] = { | |
8368 | { gen_helper_neon_cgt_s8, gen_helper_neon_cgt_s16 }, | |
8369 | { gen_helper_neon_cge_s8, gen_helper_neon_cge_s16 }, | |
8370 | { gen_helper_neon_ceq_u8, gen_helper_neon_ceq_u16 }, | |
8371 | }; | |
8372 | NeonGenTwoOpFn *genfn; | |
8373 | int comp; | |
8374 | bool reverse; | |
8375 | TCGv_i32 tcg_zero = tcg_const_i32(0); | |
8376 | ||
8377 | /* comp = index into [CMGT, CMGE, CMEQ, CMLE, CMLT] */ | |
8378 | comp = (opcode - 0x8) * 2 + u; | |
8379 | /* ...but LE, LT are implemented as reverse GE, GT */ | |
8380 | reverse = (comp > 2); | |
8381 | if (reverse) { | |
8382 | comp = 4 - comp; | |
8383 | } | |
8384 | genfn = fns[comp][size]; | |
8385 | if (reverse) { | |
8386 | genfn(tcg_res, tcg_zero, tcg_op); | |
8387 | } else { | |
8388 | genfn(tcg_res, tcg_op, tcg_zero); | |
8389 | } | |
8390 | tcg_temp_free_i32(tcg_zero); | |
8391 | break; | |
8392 | } | |
8393 | case 0xb: /* ABS, NEG */ | |
8394 | if (u) { | |
8395 | TCGv_i32 tcg_zero = tcg_const_i32(0); | |
8396 | if (size) { | |
8397 | gen_helper_neon_sub_u16(tcg_res, tcg_zero, tcg_op); | |
8398 | } else { | |
8399 | gen_helper_neon_sub_u8(tcg_res, tcg_zero, tcg_op); | |
8400 | } | |
8401 | tcg_temp_free_i32(tcg_zero); | |
8402 | } else { | |
8403 | if (size) { | |
8404 | gen_helper_neon_abs_s16(tcg_res, tcg_op); | |
8405 | } else { | |
8406 | gen_helper_neon_abs_s8(tcg_res, tcg_op); | |
8407 | } | |
8408 | } | |
8409 | break; | |
8410 | default: | |
8411 | g_assert_not_reached(); | |
8412 | } | |
8413 | } | |
8414 | ||
8415 | write_vec_element_i32(s, tcg_res, rd, pass, MO_32); | |
8416 | ||
8417 | tcg_temp_free_i32(tcg_res); | |
8418 | tcg_temp_free_i32(tcg_op); | |
8419 | } | |
8420 | } | |
8421 | if (!is_q) { | |
8422 | clear_vec_high(s, rd); | |
8423 | } | |
384b26fb AB |
8424 | } |
8425 | ||
9f82e0ff PM |
8426 | /* C3.6.13 AdvSIMD scalar x indexed element |
8427 | * 31 30 29 28 24 23 22 21 20 19 16 15 12 11 10 9 5 4 0 | |
8428 | * +-----+---+-----------+------+---+---+------+-----+---+---+------+------+ | |
8429 | * | 0 1 | U | 1 1 1 1 1 | size | L | M | Rm | opc | H | 0 | Rn | Rd | | |
8430 | * +-----+---+-----------+------+---+---+------+-----+---+---+------+------+ | |
8431 | * C3.6.18 AdvSIMD vector x indexed element | |
384b26fb AB |
8432 | * 31 30 29 28 24 23 22 21 20 19 16 15 12 11 10 9 5 4 0 |
8433 | * +---+---+---+-----------+------+---+---+------+-----+---+---+------+------+ | |
8434 | * | 0 | Q | U | 0 1 1 1 1 | size | L | M | Rm | opc | H | 0 | Rn | Rd | | |
8435 | * +---+---+---+-----------+------+---+---+------+-----+---+---+------+------+ | |
8436 | */ | |
9f82e0ff | 8437 | static void disas_simd_indexed(DisasContext *s, uint32_t insn) |
384b26fb | 8438 | { |
f5e51e7f PM |
8439 | /* This encoding has two kinds of instruction: |
8440 | * normal, where we perform elt x idxelt => elt for each | |
8441 | * element in the vector | |
8442 | * long, where we perform elt x idxelt and generate a result of | |
8443 | * double the width of the input element | |
8444 | * The long ops have a 'part' specifier (ie come in INSN, INSN2 pairs). | |
8445 | */ | |
9f82e0ff | 8446 | bool is_scalar = extract32(insn, 28, 1); |
f5e51e7f PM |
8447 | bool is_q = extract32(insn, 30, 1); |
8448 | bool u = extract32(insn, 29, 1); | |
8449 | int size = extract32(insn, 22, 2); | |
8450 | int l = extract32(insn, 21, 1); | |
8451 | int m = extract32(insn, 20, 1); | |
8452 | /* Note that the Rm field here is only 4 bits, not 5 as it usually is */ | |
8453 | int rm = extract32(insn, 16, 4); | |
8454 | int opcode = extract32(insn, 12, 4); | |
8455 | int h = extract32(insn, 11, 1); | |
8456 | int rn = extract32(insn, 5, 5); | |
8457 | int rd = extract32(insn, 0, 5); | |
8458 | bool is_long = false; | |
8459 | bool is_fp = false; | |
8460 | int index; | |
8461 | TCGv_ptr fpst; | |
8462 | ||
8463 | switch (opcode) { | |
8464 | case 0x0: /* MLA */ | |
8465 | case 0x4: /* MLS */ | |
9f82e0ff | 8466 | if (!u || is_scalar) { |
f5e51e7f PM |
8467 | unallocated_encoding(s); |
8468 | return; | |
8469 | } | |
8470 | break; | |
8471 | case 0x2: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */ | |
8472 | case 0x6: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */ | |
8473 | case 0xa: /* SMULL, SMULL2, UMULL, UMULL2 */ | |
9f82e0ff PM |
8474 | if (is_scalar) { |
8475 | unallocated_encoding(s); | |
8476 | return; | |
8477 | } | |
f5e51e7f PM |
8478 | is_long = true; |
8479 | break; | |
8480 | case 0x3: /* SQDMLAL, SQDMLAL2 */ | |
8481 | case 0x7: /* SQDMLSL, SQDMLSL2 */ | |
8482 | case 0xb: /* SQDMULL, SQDMULL2 */ | |
8483 | is_long = true; | |
8484 | /* fall through */ | |
8485 | case 0xc: /* SQDMULH */ | |
8486 | case 0xd: /* SQRDMULH */ | |
f5e51e7f PM |
8487 | if (u) { |
8488 | unallocated_encoding(s); | |
8489 | return; | |
8490 | } | |
8491 | break; | |
9f82e0ff PM |
8492 | case 0x8: /* MUL */ |
8493 | if (u || is_scalar) { | |
8494 | unallocated_encoding(s); | |
8495 | return; | |
8496 | } | |
8497 | break; | |
f5e51e7f PM |
8498 | case 0x1: /* FMLA */ |
8499 | case 0x5: /* FMLS */ | |
8500 | if (u) { | |
8501 | unallocated_encoding(s); | |
8502 | return; | |
8503 | } | |
8504 | /* fall through */ | |
8505 | case 0x9: /* FMUL, FMULX */ | |
8506 | if (!extract32(size, 1, 1)) { | |
8507 | unallocated_encoding(s); | |
8508 | return; | |
8509 | } | |
8510 | is_fp = true; | |
8511 | break; | |
8512 | default: | |
8513 | unallocated_encoding(s); | |
8514 | return; | |
8515 | } | |
8516 | ||
8517 | if (is_fp) { | |
8518 | /* low bit of size indicates single/double */ | |
8519 | size = extract32(size, 0, 1) ? 3 : 2; | |
8520 | if (size == 2) { | |
8521 | index = h << 1 | l; | |
8522 | } else { | |
8523 | if (l || !is_q) { | |
8524 | unallocated_encoding(s); | |
8525 | return; | |
8526 | } | |
8527 | index = h; | |
8528 | } | |
8529 | rm |= (m << 4); | |
8530 | } else { | |
8531 | switch (size) { | |
8532 | case 1: | |
8533 | index = h << 2 | l << 1 | m; | |
8534 | break; | |
8535 | case 2: | |
8536 | index = h << 1 | l; | |
8537 | rm |= (m << 4); | |
8538 | break; | |
8539 | default: | |
8540 | unallocated_encoding(s); | |
8541 | return; | |
8542 | } | |
8543 | } | |
8544 | ||
f5e51e7f PM |
8545 | if (is_fp) { |
8546 | fpst = get_fpstatus_ptr(); | |
8547 | } else { | |
8548 | TCGV_UNUSED_PTR(fpst); | |
8549 | } | |
8550 | ||
8551 | if (size == 3) { | |
8552 | TCGv_i64 tcg_idx = tcg_temp_new_i64(); | |
8553 | int pass; | |
8554 | ||
8555 | assert(is_fp && is_q && !is_long); | |
8556 | ||
8557 | read_vec_element(s, tcg_idx, rm, index, MO_64); | |
8558 | ||
9f82e0ff | 8559 | for (pass = 0; pass < (is_scalar ? 1 : 2); pass++) { |
f5e51e7f PM |
8560 | TCGv_i64 tcg_op = tcg_temp_new_i64(); |
8561 | TCGv_i64 tcg_res = tcg_temp_new_i64(); | |
8562 | ||
8563 | read_vec_element(s, tcg_op, rn, pass, MO_64); | |
8564 | ||
8565 | switch (opcode) { | |
8566 | case 0x5: /* FMLS */ | |
8567 | /* As usual for ARM, separate negation for fused multiply-add */ | |
8568 | gen_helper_vfp_negd(tcg_op, tcg_op); | |
8569 | /* fall through */ | |
8570 | case 0x1: /* FMLA */ | |
8571 | read_vec_element(s, tcg_res, rd, pass, MO_64); | |
8572 | gen_helper_vfp_muladdd(tcg_res, tcg_op, tcg_idx, tcg_res, fpst); | |
8573 | break; | |
8574 | case 0x9: /* FMUL, FMULX */ | |
8575 | if (u) { | |
8576 | gen_helper_vfp_mulxd(tcg_res, tcg_op, tcg_idx, fpst); | |
8577 | } else { | |
8578 | gen_helper_vfp_muld(tcg_res, tcg_op, tcg_idx, fpst); | |
8579 | } | |
8580 | break; | |
8581 | default: | |
8582 | g_assert_not_reached(); | |
8583 | } | |
8584 | ||
8585 | write_vec_element(s, tcg_res, rd, pass, MO_64); | |
8586 | tcg_temp_free_i64(tcg_op); | |
8587 | tcg_temp_free_i64(tcg_res); | |
8588 | } | |
8589 | ||
9f82e0ff PM |
8590 | if (is_scalar) { |
8591 | clear_vec_high(s, rd); | |
8592 | } | |
8593 | ||
f5e51e7f PM |
8594 | tcg_temp_free_i64(tcg_idx); |
8595 | } else if (!is_long) { | |
9f82e0ff PM |
8596 | /* 32 bit floating point, or 16 or 32 bit integer. |
8597 | * For the 16 bit scalar case we use the usual Neon helpers and | |
8598 | * rely on the fact that 0 op 0 == 0 with no side effects. | |
8599 | */ | |
f5e51e7f | 8600 | TCGv_i32 tcg_idx = tcg_temp_new_i32(); |
9f82e0ff PM |
8601 | int pass, maxpasses; |
8602 | ||
8603 | if (is_scalar) { | |
8604 | maxpasses = 1; | |
8605 | } else { | |
8606 | maxpasses = is_q ? 4 : 2; | |
8607 | } | |
f5e51e7f PM |
8608 | |
8609 | read_vec_element_i32(s, tcg_idx, rm, index, size); | |
8610 | ||
9f82e0ff | 8611 | if (size == 1 && !is_scalar) { |
f5e51e7f PM |
8612 | /* The simplest way to handle the 16x16 indexed ops is to duplicate |
8613 | * the index into both halves of the 32 bit tcg_idx and then use | |
8614 | * the usual Neon helpers. | |
8615 | */ | |
8616 | tcg_gen_deposit_i32(tcg_idx, tcg_idx, tcg_idx, 16, 16); | |
8617 | } | |
8618 | ||
9f82e0ff | 8619 | for (pass = 0; pass < maxpasses; pass++) { |
f5e51e7f PM |
8620 | TCGv_i32 tcg_op = tcg_temp_new_i32(); |
8621 | TCGv_i32 tcg_res = tcg_temp_new_i32(); | |
8622 | ||
9f82e0ff | 8623 | read_vec_element_i32(s, tcg_op, rn, pass, is_scalar ? size : MO_32); |
f5e51e7f PM |
8624 | |
8625 | switch (opcode) { | |
8626 | case 0x0: /* MLA */ | |
8627 | case 0x4: /* MLS */ | |
8628 | case 0x8: /* MUL */ | |
8629 | { | |
8630 | static NeonGenTwoOpFn * const fns[2][2] = { | |
8631 | { gen_helper_neon_add_u16, gen_helper_neon_sub_u16 }, | |
8632 | { tcg_gen_add_i32, tcg_gen_sub_i32 }, | |
8633 | }; | |
8634 | NeonGenTwoOpFn *genfn; | |
8635 | bool is_sub = opcode == 0x4; | |
8636 | ||
8637 | if (size == 1) { | |
8638 | gen_helper_neon_mul_u16(tcg_res, tcg_op, tcg_idx); | |
8639 | } else { | |
8640 | tcg_gen_mul_i32(tcg_res, tcg_op, tcg_idx); | |
8641 | } | |
8642 | if (opcode == 0x8) { | |
8643 | break; | |
8644 | } | |
8645 | read_vec_element_i32(s, tcg_op, rd, pass, MO_32); | |
8646 | genfn = fns[size - 1][is_sub]; | |
8647 | genfn(tcg_res, tcg_op, tcg_res); | |
8648 | break; | |
8649 | } | |
8650 | case 0x5: /* FMLS */ | |
8651 | /* As usual for ARM, separate negation for fused multiply-add */ | |
8652 | gen_helper_vfp_negs(tcg_op, tcg_op); | |
8653 | /* fall through */ | |
8654 | case 0x1: /* FMLA */ | |
8655 | read_vec_element_i32(s, tcg_res, rd, pass, MO_32); | |
8656 | gen_helper_vfp_muladds(tcg_res, tcg_op, tcg_idx, tcg_res, fpst); | |
8657 | break; | |
8658 | case 0x9: /* FMUL, FMULX */ | |
8659 | if (u) { | |
8660 | gen_helper_vfp_mulxs(tcg_res, tcg_op, tcg_idx, fpst); | |
8661 | } else { | |
8662 | gen_helper_vfp_muls(tcg_res, tcg_op, tcg_idx, fpst); | |
8663 | } | |
8664 | break; | |
8665 | case 0xc: /* SQDMULH */ | |
8666 | if (size == 1) { | |
8667 | gen_helper_neon_qdmulh_s16(tcg_res, cpu_env, | |
8668 | tcg_op, tcg_idx); | |
8669 | } else { | |
8670 | gen_helper_neon_qdmulh_s32(tcg_res, cpu_env, | |
8671 | tcg_op, tcg_idx); | |
8672 | } | |
8673 | break; | |
8674 | case 0xd: /* SQRDMULH */ | |
8675 | if (size == 1) { | |
8676 | gen_helper_neon_qrdmulh_s16(tcg_res, cpu_env, | |
8677 | tcg_op, tcg_idx); | |
8678 | } else { | |
8679 | gen_helper_neon_qrdmulh_s32(tcg_res, cpu_env, | |
8680 | tcg_op, tcg_idx); | |
8681 | } | |
8682 | break; | |
8683 | default: | |
8684 | g_assert_not_reached(); | |
8685 | } | |
8686 | ||
9f82e0ff PM |
8687 | if (is_scalar) { |
8688 | write_fp_sreg(s, rd, tcg_res); | |
8689 | } else { | |
8690 | write_vec_element_i32(s, tcg_res, rd, pass, MO_32); | |
8691 | } | |
8692 | ||
f5e51e7f PM |
8693 | tcg_temp_free_i32(tcg_op); |
8694 | tcg_temp_free_i32(tcg_res); | |
8695 | } | |
8696 | ||
8697 | tcg_temp_free_i32(tcg_idx); | |
8698 | ||
8699 | if (!is_q) { | |
8700 | clear_vec_high(s, rd); | |
8701 | } | |
8702 | } else { | |
8703 | /* long ops: 16x16->32 or 32x32->64 */ | |
c44ad1fd PM |
8704 | TCGv_i64 tcg_res[2]; |
8705 | int pass; | |
8706 | bool satop = extract32(opcode, 0, 1); | |
8707 | TCGMemOp memop = MO_32; | |
8708 | ||
8709 | if (satop || !u) { | |
8710 | memop |= MO_SIGN; | |
8711 | } | |
8712 | ||
8713 | if (size == 2) { | |
8714 | TCGv_i64 tcg_idx = tcg_temp_new_i64(); | |
8715 | ||
8716 | read_vec_element(s, tcg_idx, rm, index, memop); | |
8717 | ||
9f82e0ff | 8718 | for (pass = 0; pass < (is_scalar ? 1 : 2); pass++) { |
c44ad1fd PM |
8719 | TCGv_i64 tcg_op = tcg_temp_new_i64(); |
8720 | TCGv_i64 tcg_passres; | |
9f82e0ff | 8721 | int passelt; |
c44ad1fd | 8722 | |
9f82e0ff PM |
8723 | if (is_scalar) { |
8724 | passelt = 0; | |
8725 | } else { | |
8726 | passelt = pass + (is_q * 2); | |
8727 | } | |
8728 | ||
8729 | read_vec_element(s, tcg_op, rn, passelt, memop); | |
c44ad1fd PM |
8730 | |
8731 | tcg_res[pass] = tcg_temp_new_i64(); | |
8732 | ||
8733 | if (opcode == 0xa || opcode == 0xb) { | |
8734 | /* Non-accumulating ops */ | |
8735 | tcg_passres = tcg_res[pass]; | |
8736 | } else { | |
8737 | tcg_passres = tcg_temp_new_i64(); | |
8738 | } | |
8739 | ||
8740 | tcg_gen_mul_i64(tcg_passres, tcg_op, tcg_idx); | |
8741 | tcg_temp_free_i64(tcg_op); | |
8742 | ||
8743 | if (satop) { | |
8744 | /* saturating, doubling */ | |
8745 | gen_helper_neon_addl_saturate_s64(tcg_passres, cpu_env, | |
8746 | tcg_passres, tcg_passres); | |
8747 | } | |
8748 | ||
8749 | if (opcode == 0xa || opcode == 0xb) { | |
8750 | continue; | |
8751 | } | |
8752 | ||
8753 | /* Accumulating op: handle accumulate step */ | |
8754 | read_vec_element(s, tcg_res[pass], rd, pass, MO_64); | |
8755 | ||
8756 | switch (opcode) { | |
8757 | case 0x2: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */ | |
8758 | tcg_gen_add_i64(tcg_res[pass], tcg_res[pass], tcg_passres); | |
8759 | break; | |
8760 | case 0x6: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */ | |
8761 | tcg_gen_sub_i64(tcg_res[pass], tcg_res[pass], tcg_passres); | |
8762 | break; | |
8763 | case 0x7: /* SQDMLSL, SQDMLSL2 */ | |
8764 | tcg_gen_neg_i64(tcg_passres, tcg_passres); | |
8765 | /* fall through */ | |
8766 | case 0x3: /* SQDMLAL, SQDMLAL2 */ | |
8767 | gen_helper_neon_addl_saturate_s64(tcg_res[pass], cpu_env, | |
8768 | tcg_res[pass], | |
8769 | tcg_passres); | |
8770 | break; | |
8771 | default: | |
8772 | g_assert_not_reached(); | |
8773 | } | |
8774 | tcg_temp_free_i64(tcg_passres); | |
8775 | } | |
8776 | tcg_temp_free_i64(tcg_idx); | |
9f82e0ff PM |
8777 | |
8778 | if (is_scalar) { | |
8779 | clear_vec_high(s, rd); | |
8780 | } | |
c44ad1fd PM |
8781 | } else { |
8782 | TCGv_i32 tcg_idx = tcg_temp_new_i32(); | |
8783 | ||
8784 | assert(size == 1); | |
8785 | read_vec_element_i32(s, tcg_idx, rm, index, size); | |
8786 | ||
9f82e0ff PM |
8787 | if (!is_scalar) { |
8788 | /* The simplest way to handle the 16x16 indexed ops is to | |
8789 | * duplicate the index into both halves of the 32 bit tcg_idx | |
8790 | * and then use the usual Neon helpers. | |
8791 | */ | |
8792 | tcg_gen_deposit_i32(tcg_idx, tcg_idx, tcg_idx, 16, 16); | |
8793 | } | |
c44ad1fd | 8794 | |
9f82e0ff | 8795 | for (pass = 0; pass < (is_scalar ? 1 : 2); pass++) { |
c44ad1fd PM |
8796 | TCGv_i32 tcg_op = tcg_temp_new_i32(); |
8797 | TCGv_i64 tcg_passres; | |
8798 | ||
9f82e0ff PM |
8799 | if (is_scalar) { |
8800 | read_vec_element_i32(s, tcg_op, rn, pass, size); | |
8801 | } else { | |
8802 | read_vec_element_i32(s, tcg_op, rn, | |
8803 | pass + (is_q * 2), MO_32); | |
8804 | } | |
8805 | ||
c44ad1fd PM |
8806 | tcg_res[pass] = tcg_temp_new_i64(); |
8807 | ||
8808 | if (opcode == 0xa || opcode == 0xb) { | |
8809 | /* Non-accumulating ops */ | |
8810 | tcg_passres = tcg_res[pass]; | |
8811 | } else { | |
8812 | tcg_passres = tcg_temp_new_i64(); | |
8813 | } | |
8814 | ||
8815 | if (memop & MO_SIGN) { | |
8816 | gen_helper_neon_mull_s16(tcg_passres, tcg_op, tcg_idx); | |
8817 | } else { | |
8818 | gen_helper_neon_mull_u16(tcg_passres, tcg_op, tcg_idx); | |
8819 | } | |
8820 | if (satop) { | |
8821 | gen_helper_neon_addl_saturate_s32(tcg_passres, cpu_env, | |
8822 | tcg_passres, tcg_passres); | |
8823 | } | |
8824 | tcg_temp_free_i32(tcg_op); | |
8825 | ||
8826 | if (opcode == 0xa || opcode == 0xb) { | |
8827 | continue; | |
8828 | } | |
8829 | ||
8830 | /* Accumulating op: handle accumulate step */ | |
8831 | read_vec_element(s, tcg_res[pass], rd, pass, MO_64); | |
8832 | ||
8833 | switch (opcode) { | |
8834 | case 0x2: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */ | |
8835 | gen_helper_neon_addl_u32(tcg_res[pass], tcg_res[pass], | |
8836 | tcg_passres); | |
8837 | break; | |
8838 | case 0x6: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */ | |
8839 | gen_helper_neon_subl_u32(tcg_res[pass], tcg_res[pass], | |
8840 | tcg_passres); | |
8841 | break; | |
8842 | case 0x7: /* SQDMLSL, SQDMLSL2 */ | |
8843 | gen_helper_neon_negl_u32(tcg_passres, tcg_passres); | |
8844 | /* fall through */ | |
8845 | case 0x3: /* SQDMLAL, SQDMLAL2 */ | |
8846 | gen_helper_neon_addl_saturate_s32(tcg_res[pass], cpu_env, | |
8847 | tcg_res[pass], | |
8848 | tcg_passres); | |
8849 | break; | |
8850 | default: | |
8851 | g_assert_not_reached(); | |
8852 | } | |
8853 | tcg_temp_free_i64(tcg_passres); | |
8854 | } | |
8855 | tcg_temp_free_i32(tcg_idx); | |
9f82e0ff PM |
8856 | |
8857 | if (is_scalar) { | |
8858 | tcg_gen_ext32u_i64(tcg_res[0], tcg_res[0]); | |
8859 | } | |
8860 | } | |
8861 | ||
8862 | if (is_scalar) { | |
8863 | tcg_res[1] = tcg_const_i64(0); | |
c44ad1fd PM |
8864 | } |
8865 | ||
8866 | for (pass = 0; pass < 2; pass++) { | |
8867 | write_vec_element(s, tcg_res[pass], rd, pass, MO_64); | |
8868 | tcg_temp_free_i64(tcg_res[pass]); | |
8869 | } | |
f5e51e7f PM |
8870 | } |
8871 | ||
8872 | if (!TCGV_IS_UNUSED_PTR(fpst)) { | |
8873 | tcg_temp_free_ptr(fpst); | |
8874 | } | |
384b26fb AB |
8875 | } |
8876 | ||
8877 | /* C3.6.19 Crypto AES | |
8878 | * 31 24 23 22 21 17 16 12 11 10 9 5 4 0 | |
8879 | * +-----------------+------+-----------+--------+-----+------+------+ | |
8880 | * | 0 1 0 0 1 1 1 0 | size | 1 0 1 0 0 | opcode | 1 0 | Rn | Rd | | |
8881 | * +-----------------+------+-----------+--------+-----+------+------+ | |
8882 | */ | |
8883 | static void disas_crypto_aes(DisasContext *s, uint32_t insn) | |
8884 | { | |
8885 | unsupported_encoding(s, insn); | |
8886 | } | |
8887 | ||
8888 | /* C3.6.20 Crypto three-reg SHA | |
8889 | * 31 24 23 22 21 20 16 15 14 12 11 10 9 5 4 0 | |
8890 | * +-----------------+------+---+------+---+--------+-----+------+------+ | |
8891 | * | 0 1 0 1 1 1 1 0 | size | 0 | Rm | 0 | opcode | 0 0 | Rn | Rd | | |
8892 | * +-----------------+------+---+------+---+--------+-----+------+------+ | |
8893 | */ | |
8894 | static void disas_crypto_three_reg_sha(DisasContext *s, uint32_t insn) | |
8895 | { | |
8896 | unsupported_encoding(s, insn); | |
8897 | } | |
8898 | ||
8899 | /* C3.6.21 Crypto two-reg SHA | |
8900 | * 31 24 23 22 21 17 16 12 11 10 9 5 4 0 | |
8901 | * +-----------------+------+-----------+--------+-----+------+------+ | |
8902 | * | 0 1 0 1 1 1 1 0 | size | 1 0 1 0 0 | opcode | 1 0 | Rn | Rd | | |
8903 | * +-----------------+------+-----------+--------+-----+------+------+ | |
8904 | */ | |
8905 | static void disas_crypto_two_reg_sha(DisasContext *s, uint32_t insn) | |
8906 | { | |
8907 | unsupported_encoding(s, insn); | |
8908 | } | |
8909 | ||
8910 | /* C3.6 Data processing - SIMD, inc Crypto | |
8911 | * | |
8912 | * As the decode gets a little complex we are using a table based | |
8913 | * approach for this part of the decode. | |
8914 | */ | |
8915 | static const AArch64DecodeTable data_proc_simd[] = { | |
8916 | /* pattern , mask , fn */ | |
8917 | { 0x0e200400, 0x9f200400, disas_simd_three_reg_same }, | |
8918 | { 0x0e200000, 0x9f200c00, disas_simd_three_reg_diff }, | |
8919 | { 0x0e200800, 0x9f3e0c00, disas_simd_two_reg_misc }, | |
8920 | { 0x0e300800, 0x9f3e0c00, disas_simd_across_lanes }, | |
8921 | { 0x0e000400, 0x9fe08400, disas_simd_copy }, | |
9f82e0ff | 8922 | { 0x0f000000, 0x9f000400, disas_simd_indexed }, /* vector indexed */ |
384b26fb AB |
8923 | /* simd_mod_imm decode is a subset of simd_shift_imm, so must precede it */ |
8924 | { 0x0f000400, 0x9ff80400, disas_simd_mod_imm }, | |
8925 | { 0x0f000400, 0x9f800400, disas_simd_shift_imm }, | |
8926 | { 0x0e000000, 0xbf208c00, disas_simd_tb }, | |
8927 | { 0x0e000800, 0xbf208c00, disas_simd_zip_trn }, | |
8928 | { 0x2e000000, 0xbf208400, disas_simd_ext }, | |
8929 | { 0x5e200400, 0xdf200400, disas_simd_scalar_three_reg_same }, | |
8930 | { 0x5e200000, 0xdf200c00, disas_simd_scalar_three_reg_diff }, | |
8931 | { 0x5e200800, 0xdf3e0c00, disas_simd_scalar_two_reg_misc }, | |
8932 | { 0x5e300800, 0xdf3e0c00, disas_simd_scalar_pairwise }, | |
8933 | { 0x5e000400, 0xdfe08400, disas_simd_scalar_copy }, | |
9f82e0ff | 8934 | { 0x5f000000, 0xdf000400, disas_simd_indexed }, /* scalar indexed */ |
384b26fb AB |
8935 | { 0x5f000400, 0xdf800400, disas_simd_scalar_shift_imm }, |
8936 | { 0x4e280800, 0xff3e0c00, disas_crypto_aes }, | |
8937 | { 0x5e000000, 0xff208c00, disas_crypto_three_reg_sha }, | |
8938 | { 0x5e280800, 0xff3e0c00, disas_crypto_two_reg_sha }, | |
8939 | { 0x00000000, 0x00000000, NULL } | |
8940 | }; | |
8941 | ||
faa0ba46 PM |
8942 | static void disas_data_proc_simd(DisasContext *s, uint32_t insn) |
8943 | { | |
8944 | /* Note that this is called with all non-FP cases from | |
8945 | * table C3-6 so it must UNDEF for entries not specifically | |
8946 | * allocated to instructions in that table. | |
8947 | */ | |
384b26fb AB |
8948 | AArch64DecodeFn *fn = lookup_disas_fn(&data_proc_simd[0], insn); |
8949 | if (fn) { | |
8950 | fn(s, insn); | |
8951 | } else { | |
8952 | unallocated_encoding(s); | |
8953 | } | |
faa0ba46 PM |
8954 | } |
8955 | ||
ad7ee8a2 CF |
8956 | /* C3.6 Data processing - SIMD and floating point */ |
8957 | static void disas_data_proc_simd_fp(DisasContext *s, uint32_t insn) | |
8958 | { | |
faa0ba46 PM |
8959 | if (extract32(insn, 28, 1) == 1 && extract32(insn, 30, 1) == 0) { |
8960 | disas_data_proc_fp(s, insn); | |
8961 | } else { | |
8962 | /* SIMD, including crypto */ | |
8963 | disas_data_proc_simd(s, insn); | |
8964 | } | |
ad7ee8a2 CF |
8965 | } |
8966 | ||
8967 | /* C3.1 A64 instruction index by encoding */ | |
40f860cd | 8968 | static void disas_a64_insn(CPUARMState *env, DisasContext *s) |
14ade10f AG |
8969 | { |
8970 | uint32_t insn; | |
8971 | ||
8972 | insn = arm_ldl_code(env, s->pc, s->bswap_code); | |
8973 | s->insn = insn; | |
8974 | s->pc += 4; | |
8975 | ||
ad7ee8a2 CF |
8976 | switch (extract32(insn, 25, 4)) { |
8977 | case 0x0: case 0x1: case 0x2: case 0x3: /* UNALLOCATED */ | |
14ade10f AG |
8978 | unallocated_encoding(s); |
8979 | break; | |
ad7ee8a2 CF |
8980 | case 0x8: case 0x9: /* Data processing - immediate */ |
8981 | disas_data_proc_imm(s, insn); | |
8982 | break; | |
8983 | case 0xa: case 0xb: /* Branch, exception generation and system insns */ | |
8984 | disas_b_exc_sys(s, insn); | |
8985 | break; | |
8986 | case 0x4: | |
8987 | case 0x6: | |
8988 | case 0xc: | |
8989 | case 0xe: /* Loads and stores */ | |
8990 | disas_ldst(s, insn); | |
8991 | break; | |
8992 | case 0x5: | |
8993 | case 0xd: /* Data processing - register */ | |
8994 | disas_data_proc_reg(s, insn); | |
8995 | break; | |
8996 | case 0x7: | |
8997 | case 0xf: /* Data processing - SIMD and floating point */ | |
8998 | disas_data_proc_simd_fp(s, insn); | |
8999 | break; | |
9000 | default: | |
9001 | assert(FALSE); /* all 15 cases should be handled above */ | |
9002 | break; | |
14ade10f | 9003 | } |
11e169de AG |
9004 | |
9005 | /* if we allocated any temporaries, free them here */ | |
9006 | free_tmp_a64(s); | |
40f860cd | 9007 | } |
14ade10f | 9008 | |
40f860cd PM |
9009 | void gen_intermediate_code_internal_a64(ARMCPU *cpu, |
9010 | TranslationBlock *tb, | |
9011 | bool search_pc) | |
9012 | { | |
9013 | CPUState *cs = CPU(cpu); | |
9014 | CPUARMState *env = &cpu->env; | |
9015 | DisasContext dc1, *dc = &dc1; | |
9016 | CPUBreakpoint *bp; | |
9017 | uint16_t *gen_opc_end; | |
9018 | int j, lj; | |
9019 | target_ulong pc_start; | |
9020 | target_ulong next_page_start; | |
9021 | int num_insns; | |
9022 | int max_insns; | |
9023 | ||
9024 | pc_start = tb->pc; | |
9025 | ||
9026 | dc->tb = tb; | |
9027 | ||
9028 | gen_opc_end = tcg_ctx.gen_opc_buf + OPC_MAX_SIZE; | |
9029 | ||
9030 | dc->is_jmp = DISAS_NEXT; | |
9031 | dc->pc = pc_start; | |
9032 | dc->singlestep_enabled = cs->singlestep_enabled; | |
9033 | dc->condjmp = 0; | |
9034 | ||
9035 | dc->aarch64 = 1; | |
9036 | dc->thumb = 0; | |
9037 | dc->bswap_code = 0; | |
9038 | dc->condexec_mask = 0; | |
9039 | dc->condexec_cond = 0; | |
9040 | #if !defined(CONFIG_USER_ONLY) | |
d9ea7d29 | 9041 | dc->user = (ARM_TBFLAG_AA64_EL(tb->flags) == 0); |
40f860cd PM |
9042 | #endif |
9043 | dc->vfp_enabled = 0; | |
9044 | dc->vec_len = 0; | |
9045 | dc->vec_stride = 0; | |
60322b39 PM |
9046 | dc->cp_regs = cpu->cp_regs; |
9047 | dc->current_pl = arm_current_pl(env); | |
40f860cd | 9048 | |
11e169de AG |
9049 | init_tmp_a64_array(dc); |
9050 | ||
40f860cd PM |
9051 | next_page_start = (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE; |
9052 | lj = -1; | |
9053 | num_insns = 0; | |
9054 | max_insns = tb->cflags & CF_COUNT_MASK; | |
9055 | if (max_insns == 0) { | |
9056 | max_insns = CF_COUNT_MASK; | |
9057 | } | |
9058 | ||
9059 | gen_tb_start(); | |
9060 | ||
9061 | tcg_clear_temp_count(); | |
9062 | ||
9063 | do { | |
9064 | if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) { | |
9065 | QTAILQ_FOREACH(bp, &env->breakpoints, entry) { | |
9066 | if (bp->pc == dc->pc) { | |
9067 | gen_exception_insn(dc, 0, EXCP_DEBUG); | |
9068 | /* Advance PC so that clearing the breakpoint will | |
9069 | invalidate this TB. */ | |
9070 | dc->pc += 2; | |
9071 | goto done_generating; | |
9072 | } | |
9073 | } | |
9074 | } | |
9075 | ||
9076 | if (search_pc) { | |
9077 | j = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf; | |
9078 | if (lj < j) { | |
9079 | lj++; | |
9080 | while (lj < j) { | |
9081 | tcg_ctx.gen_opc_instr_start[lj++] = 0; | |
9082 | } | |
9083 | } | |
9084 | tcg_ctx.gen_opc_pc[lj] = dc->pc; | |
9085 | tcg_ctx.gen_opc_instr_start[lj] = 1; | |
9086 | tcg_ctx.gen_opc_icount[lj] = num_insns; | |
9087 | } | |
9088 | ||
9089 | if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO)) { | |
9090 | gen_io_start(); | |
9091 | } | |
9092 | ||
9093 | if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) { | |
9094 | tcg_gen_debug_insn_start(dc->pc); | |
9095 | } | |
9096 | ||
9097 | disas_a64_insn(env, dc); | |
9098 | ||
9099 | if (tcg_check_temp_count()) { | |
9100 | fprintf(stderr, "TCG temporary leak before "TARGET_FMT_lx"\n", | |
9101 | dc->pc); | |
9102 | } | |
9103 | ||
9104 | /* Translation stops when a conditional branch is encountered. | |
9105 | * Otherwise the subsequent code could get translated several times. | |
9106 | * Also stop translation when a page boundary is reached. This | |
9107 | * ensures prefetch aborts occur at the right place. | |
9108 | */ | |
9109 | num_insns++; | |
9110 | } while (!dc->is_jmp && tcg_ctx.gen_opc_ptr < gen_opc_end && | |
9111 | !cs->singlestep_enabled && | |
9112 | !singlestep && | |
9113 | dc->pc < next_page_start && | |
9114 | num_insns < max_insns); | |
9115 | ||
9116 | if (tb->cflags & CF_LAST_IO) { | |
9117 | gen_io_end(); | |
9118 | } | |
9119 | ||
9120 | if (unlikely(cs->singlestep_enabled) && dc->is_jmp != DISAS_EXC) { | |
9121 | /* Note that this means single stepping WFI doesn't halt the CPU. | |
9122 | * For conditional branch insns this is harmless unreachable code as | |
9123 | * gen_goto_tb() has already handled emitting the debug exception | |
9124 | * (and thus a tb-jump is not possible when singlestepping). | |
9125 | */ | |
9126 | assert(dc->is_jmp != DISAS_TB_JUMP); | |
9127 | if (dc->is_jmp != DISAS_JUMP) { | |
9128 | gen_a64_set_pc_im(dc->pc); | |
9129 | } | |
9130 | gen_exception(EXCP_DEBUG); | |
9131 | } else { | |
9132 | switch (dc->is_jmp) { | |
9133 | case DISAS_NEXT: | |
9134 | gen_goto_tb(dc, 1, dc->pc); | |
9135 | break; | |
9136 | default: | |
40f860cd | 9137 | case DISAS_UPDATE: |
fea50522 PM |
9138 | gen_a64_set_pc_im(dc->pc); |
9139 | /* fall through */ | |
9140 | case DISAS_JUMP: | |
40f860cd PM |
9141 | /* indicate that the hash table must be used to find the next TB */ |
9142 | tcg_gen_exit_tb(0); | |
9143 | break; | |
9144 | case DISAS_TB_JUMP: | |
9145 | case DISAS_EXC: | |
9146 | case DISAS_SWI: | |
9147 | break; | |
9148 | case DISAS_WFI: | |
9149 | /* This is a special case because we don't want to just halt the CPU | |
9150 | * if trying to debug across a WFI. | |
9151 | */ | |
1ed69e82 | 9152 | gen_a64_set_pc_im(dc->pc); |
40f860cd PM |
9153 | gen_helper_wfi(cpu_env); |
9154 | break; | |
9155 | } | |
9156 | } | |
9157 | ||
9158 | done_generating: | |
9159 | gen_tb_end(tb, num_insns); | |
9160 | *tcg_ctx.gen_opc_ptr = INDEX_op_end; | |
9161 | ||
9162 | #ifdef DEBUG_DISAS | |
9163 | if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) { | |
9164 | qemu_log("----------------\n"); | |
9165 | qemu_log("IN: %s\n", lookup_symbol(pc_start)); | |
9166 | log_target_disas(env, pc_start, dc->pc - pc_start, | |
999b53ec | 9167 | 4 | (dc->bswap_code << 1)); |
40f860cd PM |
9168 | qemu_log("\n"); |
9169 | } | |
9170 | #endif | |
9171 | if (search_pc) { | |
9172 | j = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf; | |
9173 | lj++; | |
9174 | while (lj <= j) { | |
9175 | tcg_ctx.gen_opc_instr_start[lj++] = 0; | |
9176 | } | |
9177 | } else { | |
9178 | tb->size = dc->pc - pc_start; | |
9179 | tb->icount = num_insns; | |
14ade10f AG |
9180 | } |
9181 | } |