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ARM: Fix decoding of VFP forms of VCVT between float and int/fixed
[mirror_qemu.git] / target-arm / translate.c
CommitLineData
2c0262af
FB		 1/*
2 * ARM translation
5fafdf24 3 *
2c0262af 4 * Copyright (c) 2003 Fabrice Bellard
9ee6e8bb 5 * Copyright (c) 2005-2007 CodeSourcery
18c9b560 6 * Copyright (c) 2007 OpenedHand, Ltd.
2c0262af
FB		 7 *
8 * This library is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU Lesser General Public
10 * License as published by the Free Software Foundation; either
11 * version 2 of the License, or (at your option) any later version.
12 *
13 * This library is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * Lesser General Public License for more details.
17 *
18 * You should have received a copy of the GNU Lesser General Public
8167ee88 19 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
2c0262af
FB		 20 */
21#include <stdarg.h>
22#include <stdlib.h>
23#include <stdio.h>
24#include <string.h>
25#include <inttypes.h>
26
27#include "cpu.h"
28#include "exec-all.h"
29#include "disas.h"
57fec1fe 30#include "tcg-op.h"
79383c9c 31#include "qemu-log.h"
1497c961 32
a7812ae4 33#include "helpers.h"
1497c961 34#define GEN_HELPER 1
b26eefb6 35#include "helpers.h"
2c0262af 36
9ee6e8bb
PB		 37#define ENABLE_ARCH_5J 0
38#define ENABLE_ARCH_6 arm_feature(env, ARM_FEATURE_V6)
39#define ENABLE_ARCH_6K arm_feature(env, ARM_FEATURE_V6K)
40#define ENABLE_ARCH_6T2 arm_feature(env, ARM_FEATURE_THUMB2)
41#define ENABLE_ARCH_7 arm_feature(env, ARM_FEATURE_V7)
b5ff1b31 42
86753403 43#define ARCH(x) do { if (!ENABLE_ARCH_##x) goto illegal_op; } while(0)
b5ff1b31 44
2c0262af
FB		 45/* internal defines */
46typedef struct DisasContext {
0fa85d43 47 target_ulong pc;
2c0262af 48 int is_jmp;
e50e6a20
FB		 49 /* Nonzero if this instruction has been conditionally skipped. */
50 int condjmp;
51 /* The label that will be jumped to when the instruction is skipped. */
52 int condlabel;
9ee6e8bb
PB		 53 /* Thumb-2 condtional execution bits. */
54 int condexec_mask;
55 int condexec_cond;
2c0262af 56 struct TranslationBlock *tb;
8aaca4c0 57 int singlestep_enabled;
5899f386 58 int thumb;
b5ff1b31
FB		 59#if !defined(CONFIG_USER_ONLY)
60 int user;
61#endif
2c0262af
FB		 62} DisasContext;
63
b5ff1b31
FB		 64#if defined(CONFIG_USER_ONLY)
65#define IS_USER(s) 1
66#else
67#define IS_USER(s) (s->user)
68#endif
69
9ee6e8bb
PB		 70/* These instructions trap after executing, so defer them until after the
71 conditional executions state has been updated. */
72#define DISAS_WFI 4
73#define DISAS_SWI 5
2c0262af 74
a7812ae4 75static TCGv_ptr cpu_env;
ad69471c 76/* We reuse the same 64-bit temporaries for efficiency. */
a7812ae4 77static TCGv_i64 cpu_V0, cpu_V1, cpu_M0;
155c3eac 78static TCGv_i32 cpu_R[16];
426f5abc
PB		 79static TCGv_i32 cpu_exclusive_addr;
80static TCGv_i32 cpu_exclusive_val;
81static TCGv_i32 cpu_exclusive_high;
82#ifdef CONFIG_USER_ONLY
83static TCGv_i32 cpu_exclusive_test;
84static TCGv_i32 cpu_exclusive_info;
85#endif
ad69471c 86
b26eefb6 87/* FIXME: These should be removed. */
a7812ae4
PB		 88static TCGv cpu_F0s, cpu_F1s;
89static TCGv_i64 cpu_F0d, cpu_F1d;
b26eefb6 90
2e70f6ef
PB		 91#include "gen-icount.h"
92
155c3eac
FN		 93static const char *regnames[] =
94 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
95 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "pc" };
96
b26eefb6
PB		 97/* initialize TCG globals. */
98void arm_translate_init(void)
99{
155c3eac
FN		 100 int i;
101
a7812ae4
PB		 102 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
103
155c3eac
FN		 104 for (i = 0; i < 16; i++) {
105 cpu_R[i] = tcg_global_mem_new_i32(TCG_AREG0,
106 offsetof(CPUState, regs[i]),
107 regnames[i]);
108 }
426f5abc
PB		 109 cpu_exclusive_addr = tcg_global_mem_new_i32(TCG_AREG0,
110 offsetof(CPUState, exclusive_addr), "exclusive_addr");
111 cpu_exclusive_val = tcg_global_mem_new_i32(TCG_AREG0,
112 offsetof(CPUState, exclusive_val), "exclusive_val");
113 cpu_exclusive_high = tcg_global_mem_new_i32(TCG_AREG0,
114 offsetof(CPUState, exclusive_high), "exclusive_high");
115#ifdef CONFIG_USER_ONLY
116 cpu_exclusive_test = tcg_global_mem_new_i32(TCG_AREG0,
117 offsetof(CPUState, exclusive_test), "exclusive_test");
118 cpu_exclusive_info = tcg_global_mem_new_i32(TCG_AREG0,
119 offsetof(CPUState, exclusive_info), "exclusive_info");
120#endif
155c3eac 121
a7812ae4
PB		 122#define GEN_HELPER 2
123#include "helpers.h"
b26eefb6
PB		 124}
125
b26eefb6 126static int num_temps;
b26eefb6
PB		 127
128/* Allocate a temporary variable. */
a7812ae4 129static TCGv_i32 new_tmp(void)
b26eefb6 130{
12edd4f2
FN		 131 num_temps++;
132 return tcg_temp_new_i32();
b26eefb6
PB		 133}
134
135/* Release a temporary variable. */
136static void dead_tmp(TCGv tmp)
137{
12edd4f2 138 tcg_temp_free(tmp);
b26eefb6 139 num_temps--;
b26eefb6
PB		 140}
141
d9ba4830
PB		 142static inline TCGv load_cpu_offset(int offset)
143{
144 TCGv tmp = new_tmp();
145 tcg_gen_ld_i32(tmp, cpu_env, offset);
146 return tmp;
147}
148
149#define load_cpu_field(name) load_cpu_offset(offsetof(CPUState, name))
150
151static inline void store_cpu_offset(TCGv var, int offset)
152{
153 tcg_gen_st_i32(var, cpu_env, offset);
154 dead_tmp(var);
155}
156
157#define store_cpu_field(var, name) \
158 store_cpu_offset(var, offsetof(CPUState, name))
159
b26eefb6
PB		 160/* Set a variable to the value of a CPU register. */
161static void load_reg_var(DisasContext *s, TCGv var, int reg)
162{
163 if (reg == 15) {
164 uint32_t addr;
165 /* normaly, since we updated PC, we need only to add one insn */
166 if (s->thumb)
167 addr = (long)s->pc + 2;
168 else
169 addr = (long)s->pc + 4;
170 tcg_gen_movi_i32(var, addr);
171 } else {
155c3eac 172 tcg_gen_mov_i32(var, cpu_R[reg]);
b26eefb6
PB		 173 }
174}
175
176/* Create a new temporary and set it to the value of a CPU register. */
177static inline TCGv load_reg(DisasContext *s, int reg)
178{
179 TCGv tmp = new_tmp();
180 load_reg_var(s, tmp, reg);
181 return tmp;
182}
183
184/* Set a CPU register. The source must be a temporary and will be
185 marked as dead. */
186static void store_reg(DisasContext *s, int reg, TCGv var)
187{
188 if (reg == 15) {
189 tcg_gen_andi_i32(var, var, ~1);
190 s->is_jmp = DISAS_JUMP;
191 }
155c3eac 192 tcg_gen_mov_i32(cpu_R[reg], var);
b26eefb6
PB		 193 dead_tmp(var);
194}
195
b26eefb6 196/* Value extensions. */
86831435
PB		 197#define gen_uxtb(var) tcg_gen_ext8u_i32(var, var)
198#define gen_uxth(var) tcg_gen_ext16u_i32(var, var)
b26eefb6
PB		 199#define gen_sxtb(var) tcg_gen_ext8s_i32(var, var)
200#define gen_sxth(var) tcg_gen_ext16s_i32(var, var)
201
1497c961
PB		 202#define gen_sxtb16(var) gen_helper_sxtb16(var, var)
203#define gen_uxtb16(var) gen_helper_uxtb16(var, var)
8f01245e 204
b26eefb6 205
b75263d6
JR		 206static inline void gen_set_cpsr(TCGv var, uint32_t mask)
207{
208 TCGv tmp_mask = tcg_const_i32(mask);
209 gen_helper_cpsr_write(var, tmp_mask);
210 tcg_temp_free_i32(tmp_mask);
211}
d9ba4830
PB		 212/* Set NZCV flags from the high 4 bits of var. */
213#define gen_set_nzcv(var) gen_set_cpsr(var, CPSR_NZCV)
214
215static void gen_exception(int excp)
216{
217 TCGv tmp = new_tmp();
218 tcg_gen_movi_i32(tmp, excp);
219 gen_helper_exception(tmp);
220 dead_tmp(tmp);
221}
222
3670669c
PB		 223static void gen_smul_dual(TCGv a, TCGv b)
224{
225 TCGv tmp1 = new_tmp();
226 TCGv tmp2 = new_tmp();
22478e79
AZ		 227 tcg_gen_ext16s_i32(tmp1, a);
228 tcg_gen_ext16s_i32(tmp2, b);
3670669c
PB		 229 tcg_gen_mul_i32(tmp1, tmp1, tmp2);
230 dead_tmp(tmp2);
231 tcg_gen_sari_i32(a, a, 16);
232 tcg_gen_sari_i32(b, b, 16);
233 tcg_gen_mul_i32(b, b, a);
234 tcg_gen_mov_i32(a, tmp1);
235 dead_tmp(tmp1);
236}
237
238/* Byteswap each halfword. */
239static void gen_rev16(TCGv var)
240{
241 TCGv tmp = new_tmp();
242 tcg_gen_shri_i32(tmp, var, 8);
243 tcg_gen_andi_i32(tmp, tmp, 0x00ff00ff);
244 tcg_gen_shli_i32(var, var, 8);
245 tcg_gen_andi_i32(var, var, 0xff00ff00);
246 tcg_gen_or_i32(var, var, tmp);
247 dead_tmp(tmp);
248}
249
250/* Byteswap low halfword and sign extend. */
251static void gen_revsh(TCGv var)
252{
253 TCGv tmp = new_tmp();
254 tcg_gen_shri_i32(tmp, var, 8);
255 tcg_gen_andi_i32(tmp, tmp, 0x00ff);
256 tcg_gen_shli_i32(var, var, 8);
257 tcg_gen_ext8s_i32(var, var);
258 tcg_gen_or_i32(var, var, tmp);
259 dead_tmp(tmp);
260}
261
262/* Unsigned bitfield extract. */
263static void gen_ubfx(TCGv var, int shift, uint32_t mask)
264{
265 if (shift)
266 tcg_gen_shri_i32(var, var, shift);
267 tcg_gen_andi_i32(var, var, mask);
268}
269
270/* Signed bitfield extract. */
271static void gen_sbfx(TCGv var, int shift, int width)
272{
273 uint32_t signbit;
274
275 if (shift)
276 tcg_gen_sari_i32(var, var, shift);
277 if (shift + width < 32) {
278 signbit = 1u << (width - 1);
279 tcg_gen_andi_i32(var, var, (1u << width) - 1);
280 tcg_gen_xori_i32(var, var, signbit);
281 tcg_gen_subi_i32(var, var, signbit);
282 }
283}
284
285/* Bitfield insertion. Insert val into base. Clobbers base and val. */
286static void gen_bfi(TCGv dest, TCGv base, TCGv val, int shift, uint32_t mask)
287{
3670669c 288 tcg_gen_andi_i32(val, val, mask);
8f8e3aa4
PB		 289 tcg_gen_shli_i32(val, val, shift);
290 tcg_gen_andi_i32(base, base, ~(mask << shift));
3670669c
PB		 291 tcg_gen_or_i32(dest, base, val);
292}
293
d9ba4830
PB		 294/* Round the top 32 bits of a 64-bit value. */
295static void gen_roundqd(TCGv a, TCGv b)
3670669c 296{
d9ba4830
PB		 297 tcg_gen_shri_i32(a, a, 31);
298 tcg_gen_add_i32(a, a, b);
3670669c
PB		 299}
300
8f01245e
PB		 301/* FIXME: Most targets have native widening multiplication.
302 It would be good to use that instead of a full wide multiply. */
5e3f878a 303/* 32x32->64 multiply. Marks inputs as dead. */
a7812ae4 304static TCGv_i64 gen_mulu_i64_i32(TCGv a, TCGv b)
5e3f878a 305{
a7812ae4
PB		 306 TCGv_i64 tmp1 = tcg_temp_new_i64();
307 TCGv_i64 tmp2 = tcg_temp_new_i64();
5e3f878a
PB		 308
309 tcg_gen_extu_i32_i64(tmp1, a);
310 dead_tmp(a);
311 tcg_gen_extu_i32_i64(tmp2, b);
312 dead_tmp(b);
313 tcg_gen_mul_i64(tmp1, tmp1, tmp2);
b75263d6 314 tcg_temp_free_i64(tmp2);
5e3f878a
PB		 315 return tmp1;
316}
317
a7812ae4 318static TCGv_i64 gen_muls_i64_i32(TCGv a, TCGv b)
5e3f878a 319{
a7812ae4
PB		 320 TCGv_i64 tmp1 = tcg_temp_new_i64();
321 TCGv_i64 tmp2 = tcg_temp_new_i64();
5e3f878a
PB		 322
323 tcg_gen_ext_i32_i64(tmp1, a);
324 dead_tmp(a);
325 tcg_gen_ext_i32_i64(tmp2, b);
326 dead_tmp(b);
327 tcg_gen_mul_i64(tmp1, tmp1, tmp2);
b75263d6 328 tcg_temp_free_i64(tmp2);
5e3f878a
PB		 329 return tmp1;
330}
331
8f01245e 332/* Signed 32x32->64 multiply. */
d9ba4830 333static void gen_imull(TCGv a, TCGv b)
8f01245e 334{
a7812ae4
PB		 335 TCGv_i64 tmp1 = tcg_temp_new_i64();
336 TCGv_i64 tmp2 = tcg_temp_new_i64();
8f01245e 337
d9ba4830
PB		 338 tcg_gen_ext_i32_i64(tmp1, a);
339 tcg_gen_ext_i32_i64(tmp2, b);
8f01245e 340 tcg_gen_mul_i64(tmp1, tmp1, tmp2);
b75263d6 341 tcg_temp_free_i64(tmp2);
d9ba4830 342 tcg_gen_trunc_i64_i32(a, tmp1);
8f01245e 343 tcg_gen_shri_i64(tmp1, tmp1, 32);
d9ba4830 344 tcg_gen_trunc_i64_i32(b, tmp1);
b75263d6 345 tcg_temp_free_i64(tmp1);
d9ba4830 346}
d9ba4830 347
8f01245e
PB		 348/* Swap low and high halfwords. */
349static void gen_swap_half(TCGv var)
350{
351 TCGv tmp = new_tmp();
352 tcg_gen_shri_i32(tmp, var, 16);
353 tcg_gen_shli_i32(var, var, 16);
354 tcg_gen_or_i32(var, var, tmp);
3670669c 355 dead_tmp(tmp);
8f01245e
PB		 356}
357
b26eefb6
PB		 358/* Dual 16-bit add. Result placed in t0 and t1 is marked as dead.
359 tmp = (t0 ^ t1) & 0x8000;
360 t0 &= ~0x8000;
361 t1 &= ~0x8000;
362 t0 = (t0 + t1) ^ tmp;
363 */
364
365static void gen_add16(TCGv t0, TCGv t1)
366{
367 TCGv tmp = new_tmp();
368 tcg_gen_xor_i32(tmp, t0, t1);
369 tcg_gen_andi_i32(tmp, tmp, 0x8000);
370 tcg_gen_andi_i32(t0, t0, ~0x8000);
371 tcg_gen_andi_i32(t1, t1, ~0x8000);
372 tcg_gen_add_i32(t0, t0, t1);
373 tcg_gen_xor_i32(t0, t0, tmp);
374 dead_tmp(tmp);
375 dead_tmp(t1);
376}
377
9a119ff6
PB		 378#define gen_set_CF(var) tcg_gen_st_i32(var, cpu_env, offsetof(CPUState, CF))
379
b26eefb6
PB		 380/* Set CF to the top bit of var. */
381static void gen_set_CF_bit31(TCGv var)
382{
383 TCGv tmp = new_tmp();
384 tcg_gen_shri_i32(tmp, var, 31);
4cc633c3 385 gen_set_CF(tmp);
b26eefb6
PB		 386 dead_tmp(tmp);
387}
388
389/* Set N and Z flags from var. */
390static inline void gen_logic_CC(TCGv var)
391{
6fbe23d5
PB		 392 tcg_gen_st_i32(var, cpu_env, offsetof(CPUState, NF));
393 tcg_gen_st_i32(var, cpu_env, offsetof(CPUState, ZF));
b26eefb6
PB		 394}
395
396/* T0 += T1 + CF. */
396e467c 397static void gen_adc(TCGv t0, TCGv t1)
b26eefb6 398{
d9ba4830 399 TCGv tmp;
396e467c 400 tcg_gen_add_i32(t0, t0, t1);
d9ba4830 401 tmp = load_cpu_field(CF);
396e467c 402 tcg_gen_add_i32(t0, t0, tmp);
b26eefb6
PB		 403 dead_tmp(tmp);
404}
405
e9bb4aa9
JR		 406/* dest = T0 + T1 + CF. */
407static void gen_add_carry(TCGv dest, TCGv t0, TCGv t1)
408{
409 TCGv tmp;
410 tcg_gen_add_i32(dest, t0, t1);
411 tmp = load_cpu_field(CF);
412 tcg_gen_add_i32(dest, dest, tmp);
413 dead_tmp(tmp);
414}
415
3670669c
PB		 416/* dest = T0 - T1 + CF - 1. */
417static void gen_sub_carry(TCGv dest, TCGv t0, TCGv t1)
418{
d9ba4830 419 TCGv tmp;
3670669c 420 tcg_gen_sub_i32(dest, t0, t1);
d9ba4830 421 tmp = load_cpu_field(CF);
3670669c
PB		 422 tcg_gen_add_i32(dest, dest, tmp);
423 tcg_gen_subi_i32(dest, dest, 1);
424 dead_tmp(tmp);
425}
426
ad69471c
PB		 427/* FIXME: Implement this natively. */
428#define tcg_gen_abs_i32(t0, t1) gen_helper_abs(t0, t1)
429
9a119ff6 430static void shifter_out_im(TCGv var, int shift)
b26eefb6 431{
9a119ff6
PB		 432 TCGv tmp = new_tmp();
433 if (shift == 0) {
434 tcg_gen_andi_i32(tmp, var, 1);
b26eefb6 435 } else {
9a119ff6 436 tcg_gen_shri_i32(tmp, var, shift);
4cc633c3 437 if (shift != 31)
9a119ff6
PB		 438 tcg_gen_andi_i32(tmp, tmp, 1);
439 }
440 gen_set_CF(tmp);
441 dead_tmp(tmp);
442}
b26eefb6 443
9a119ff6
PB		 444/* Shift by immediate. Includes special handling for shift == 0. */
445static inline void gen_arm_shift_im(TCGv var, int shiftop, int shift, int flags)
446{
447 switch (shiftop) {
448 case 0: /* LSL */
449 if (shift != 0) {
450 if (flags)
451 shifter_out_im(var, 32 - shift);
452 tcg_gen_shli_i32(var, var, shift);
453 }
454 break;
455 case 1: /* LSR */
456 if (shift == 0) {
457 if (flags) {
458 tcg_gen_shri_i32(var, var, 31);
459 gen_set_CF(var);
460 }
461 tcg_gen_movi_i32(var, 0);
462 } else {
463 if (flags)
464 shifter_out_im(var, shift - 1);
465 tcg_gen_shri_i32(var, var, shift);
466 }
467 break;
468 case 2: /* ASR */
469 if (shift == 0)
470 shift = 32;
471 if (flags)
472 shifter_out_im(var, shift - 1);
473 if (shift == 32)
474 shift = 31;
475 tcg_gen_sari_i32(var, var, shift);
476 break;
477 case 3: /* ROR/RRX */
478 if (shift != 0) {
479 if (flags)
480 shifter_out_im(var, shift - 1);
f669df27 481 tcg_gen_rotri_i32(var, var, shift); break;
9a119ff6 482 } else {
d9ba4830 483 TCGv tmp = load_cpu_field(CF);
9a119ff6
PB		 484 if (flags)
485 shifter_out_im(var, 0);
486 tcg_gen_shri_i32(var, var, 1);
b26eefb6
PB		 487 tcg_gen_shli_i32(tmp, tmp, 31);
488 tcg_gen_or_i32(var, var, tmp);
489 dead_tmp(tmp);
b26eefb6
PB		 490 }
491 }
492};
493
8984bd2e
PB		 494static inline void gen_arm_shift_reg(TCGv var, int shiftop,
495 TCGv shift, int flags)
496{
497 if (flags) {
498 switch (shiftop) {
499 case 0: gen_helper_shl_cc(var, var, shift); break;
500 case 1: gen_helper_shr_cc(var, var, shift); break;
501 case 2: gen_helper_sar_cc(var, var, shift); break;
502 case 3: gen_helper_ror_cc(var, var, shift); break;
503 }
504 } else {
505 switch (shiftop) {
506 case 0: gen_helper_shl(var, var, shift); break;
507 case 1: gen_helper_shr(var, var, shift); break;
508 case 2: gen_helper_sar(var, var, shift); break;
f669df27
AJ		 509 case 3: tcg_gen_andi_i32(shift, shift, 0x1f);
510 tcg_gen_rotr_i32(var, var, shift); break;
8984bd2e
PB		 511 }
512 }
513 dead_tmp(shift);
514}
515
6ddbc6e4
PB		 516#define PAS_OP(pfx) \
517 switch (op2) { \
518 case 0: gen_pas_helper(glue(pfx,add16)); break; \
519 case 1: gen_pas_helper(glue(pfx,addsubx)); break; \
520 case 2: gen_pas_helper(glue(pfx,subaddx)); break; \
521 case 3: gen_pas_helper(glue(pfx,sub16)); break; \
522 case 4: gen_pas_helper(glue(pfx,add8)); break; \
523 case 7: gen_pas_helper(glue(pfx,sub8)); break; \
524 }
d9ba4830 525static void gen_arm_parallel_addsub(int op1, int op2, TCGv a, TCGv b)
6ddbc6e4 526{
a7812ae4 527 TCGv_ptr tmp;
6ddbc6e4
PB		 528
529 switch (op1) {
530#define gen_pas_helper(name) glue(gen_helper_,name)(a, a, b, tmp)
531 case 1:
a7812ae4 532 tmp = tcg_temp_new_ptr();
6ddbc6e4
PB		 533 tcg_gen_addi_ptr(tmp, cpu_env, offsetof(CPUState, GE));
534 PAS_OP(s)
b75263d6 535 tcg_temp_free_ptr(tmp);
6ddbc6e4
PB		 536 break;
537 case 5:
a7812ae4 538 tmp = tcg_temp_new_ptr();
6ddbc6e4
PB		 539 tcg_gen_addi_ptr(tmp, cpu_env, offsetof(CPUState, GE));
540 PAS_OP(u)
b75263d6 541 tcg_temp_free_ptr(tmp);
6ddbc6e4
PB		 542 break;
543#undef gen_pas_helper
544#define gen_pas_helper(name) glue(gen_helper_,name)(a, a, b)
545 case 2:
546 PAS_OP(q);
547 break;
548 case 3:
549 PAS_OP(sh);
550 break;
551 case 6:
552 PAS_OP(uq);
553 break;
554 case 7:
555 PAS_OP(uh);
556 break;
557#undef gen_pas_helper
558 }
559}
9ee6e8bb
PB		 560#undef PAS_OP
561
6ddbc6e4
PB		 562/* For unknown reasons Arm and Thumb-2 use arbitrarily different encodings. */
563#define PAS_OP(pfx) \
ed89a2f1 564 switch (op1) { \
6ddbc6e4
PB		 565 case 0: gen_pas_helper(glue(pfx,add8)); break; \
566 case 1: gen_pas_helper(glue(pfx,add16)); break; \
567 case 2: gen_pas_helper(glue(pfx,addsubx)); break; \
568 case 4: gen_pas_helper(glue(pfx,sub8)); break; \
569 case 5: gen_pas_helper(glue(pfx,sub16)); break; \
570 case 6: gen_pas_helper(glue(pfx,subaddx)); break; \
571 }
d9ba4830 572static void gen_thumb2_parallel_addsub(int op1, int op2, TCGv a, TCGv b)
6ddbc6e4 573{
a7812ae4 574 TCGv_ptr tmp;
6ddbc6e4 575
ed89a2f1 576 switch (op2) {
6ddbc6e4
PB		 577#define gen_pas_helper(name) glue(gen_helper_,name)(a, a, b, tmp)
578 case 0:
a7812ae4 579 tmp = tcg_temp_new_ptr();
6ddbc6e4
PB		 580 tcg_gen_addi_ptr(tmp, cpu_env, offsetof(CPUState, GE));
581 PAS_OP(s)
b75263d6 582 tcg_temp_free_ptr(tmp);
6ddbc6e4
PB		 583 break;
584 case 4:
a7812ae4 585 tmp = tcg_temp_new_ptr();
6ddbc6e4
PB		 586 tcg_gen_addi_ptr(tmp, cpu_env, offsetof(CPUState, GE));
587 PAS_OP(u)
b75263d6 588 tcg_temp_free_ptr(tmp);
6ddbc6e4
PB		 589 break;
590#undef gen_pas_helper
591#define gen_pas_helper(name) glue(gen_helper_,name)(a, a, b)
592 case 1:
593 PAS_OP(q);
594 break;
595 case 2:
596 PAS_OP(sh);
597 break;
598 case 5:
599 PAS_OP(uq);
600 break;
601 case 6:
602 PAS_OP(uh);
603 break;
604#undef gen_pas_helper
605 }
606}
9ee6e8bb
PB		 607#undef PAS_OP
608
d9ba4830
PB		 609static void gen_test_cc(int cc, int label)
610{
611 TCGv tmp;
612 TCGv tmp2;
d9ba4830
PB		 613 int inv;
614
d9ba4830
PB		 615 switch (cc) {
616 case 0: /* eq: Z */
6fbe23d5 617 tmp = load_cpu_field(ZF);
cb63669a 618 tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, label);
d9ba4830
PB		 619 break;
620 case 1: /* ne: !Z */
6fbe23d5 621 tmp = load_cpu_field(ZF);
cb63669a 622 tcg_gen_brcondi_i32(TCG_COND_NE, tmp, 0, label);
d9ba4830
PB		 623 break;
624 case 2: /* cs: C */
625 tmp = load_cpu_field(CF);
cb63669a 626 tcg_gen_brcondi_i32(TCG_COND_NE, tmp, 0, label);
d9ba4830
PB		 627 break;
628 case 3: /* cc: !C */
629 tmp = load_cpu_field(CF);
cb63669a 630 tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, label);
d9ba4830
PB		 631 break;
632 case 4: /* mi: N */
6fbe23d5 633 tmp = load_cpu_field(NF);
cb63669a 634 tcg_gen_brcondi_i32(TCG_COND_LT, tmp, 0, label);
d9ba4830
PB		 635 break;
636 case 5: /* pl: !N */
6fbe23d5 637 tmp = load_cpu_field(NF);
cb63669a 638 tcg_gen_brcondi_i32(TCG_COND_GE, tmp, 0, label);
d9ba4830
PB		 639 break;
640 case 6: /* vs: V */
641 tmp = load_cpu_field(VF);
cb63669a 642 tcg_gen_brcondi_i32(TCG_COND_LT, tmp, 0, label);
d9ba4830
PB		 643 break;
644 case 7: /* vc: !V */
645 tmp = load_cpu_field(VF);
cb63669a 646 tcg_gen_brcondi_i32(TCG_COND_GE, tmp, 0, label);
d9ba4830
PB		 647 break;
648 case 8: /* hi: C && !Z */
649 inv = gen_new_label();
650 tmp = load_cpu_field(CF);
cb63669a 651 tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, inv);
d9ba4830 652 dead_tmp(tmp);
6fbe23d5 653 tmp = load_cpu_field(ZF);
cb63669a 654 tcg_gen_brcondi_i32(TCG_COND_NE, tmp, 0, label);
d9ba4830
PB		 655 gen_set_label(inv);
656 break;
657 case 9: /* ls: !C || Z */
658 tmp = load_cpu_field(CF);
cb63669a 659 tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, label);
d9ba4830 660 dead_tmp(tmp);
6fbe23d5 661 tmp = load_cpu_field(ZF);
cb63669a 662 tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, label);
d9ba4830
PB		 663 break;
664 case 10: /* ge: N == V -> N ^ V == 0 */
665 tmp = load_cpu_field(VF);
6fbe23d5 666 tmp2 = load_cpu_field(NF);
d9ba4830
PB		 667 tcg_gen_xor_i32(tmp, tmp, tmp2);
668 dead_tmp(tmp2);
cb63669a 669 tcg_gen_brcondi_i32(TCG_COND_GE, tmp, 0, label);
d9ba4830
PB		 670 break;
671 case 11: /* lt: N != V -> N ^ V != 0 */
672 tmp = load_cpu_field(VF);
6fbe23d5 673 tmp2 = load_cpu_field(NF);
d9ba4830
PB		 674 tcg_gen_xor_i32(tmp, tmp, tmp2);
675 dead_tmp(tmp2);
cb63669a 676 tcg_gen_brcondi_i32(TCG_COND_LT, tmp, 0, label);
d9ba4830
PB		 677 break;
678 case 12: /* gt: !Z && N == V */
679 inv = gen_new_label();
6fbe23d5 680 tmp = load_cpu_field(ZF);
cb63669a 681 tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, inv);
d9ba4830
PB		 682 dead_tmp(tmp);
683 tmp = load_cpu_field(VF);
6fbe23d5 684 tmp2 = load_cpu_field(NF);
d9ba4830
PB		 685 tcg_gen_xor_i32(tmp, tmp, tmp2);
686 dead_tmp(tmp2);
cb63669a 687 tcg_gen_brcondi_i32(TCG_COND_GE, tmp, 0, label);
d9ba4830
PB		 688 gen_set_label(inv);
689 break;
690 case 13: /* le: Z || N != V */
6fbe23d5 691 tmp = load_cpu_field(ZF);
cb63669a 692 tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, label);
d9ba4830
PB		 693 dead_tmp(tmp);
694 tmp = load_cpu_field(VF);
6fbe23d5 695 tmp2 = load_cpu_field(NF);
d9ba4830
PB		 696 tcg_gen_xor_i32(tmp, tmp, tmp2);
697 dead_tmp(tmp2);
cb63669a 698 tcg_gen_brcondi_i32(TCG_COND_LT, tmp, 0, label);
d9ba4830
PB		 699 break;
700 default:
701 fprintf(stderr, "Bad condition code 0x%x\n", cc);
702 abort();
703 }
704 dead_tmp(tmp);
705}
2c0262af 706
b1d8e52e 707static const uint8_t table_logic_cc[16] = {
2c0262af
FB		 708 1, /* and */
709 1, /* xor */
710 0, /* sub */
711 0, /* rsb */
712 0, /* add */
713 0, /* adc */
714 0, /* sbc */
715 0, /* rsc */
716 1, /* andl */
717 1, /* xorl */
718 0, /* cmp */
719 0, /* cmn */
720 1, /* orr */
721 1, /* mov */
722 1, /* bic */
723 1, /* mvn */
724};
3b46e624 725
d9ba4830
PB		 726/* Set PC and Thumb state from an immediate address. */
727static inline void gen_bx_im(DisasContext *s, uint32_t addr)
99c475ab 728{
b26eefb6 729 TCGv tmp;
99c475ab 730
b26eefb6 731 s->is_jmp = DISAS_UPDATE;
d9ba4830 732 if (s->thumb != (addr & 1)) {
155c3eac 733 tmp = new_tmp();
d9ba4830
PB		 734 tcg_gen_movi_i32(tmp, addr & 1);
735 tcg_gen_st_i32(tmp, cpu_env, offsetof(CPUState, thumb));
155c3eac 736 dead_tmp(tmp);
d9ba4830 737 }
155c3eac 738 tcg_gen_movi_i32(cpu_R[15], addr & ~1);
d9ba4830
PB		 739}
740
741/* Set PC and Thumb state from var. var is marked as dead. */
742static inline void gen_bx(DisasContext *s, TCGv var)
743{
d9ba4830 744 s->is_jmp = DISAS_UPDATE;
155c3eac
FN		 745 tcg_gen_andi_i32(cpu_R[15], var, ~1);
746 tcg_gen_andi_i32(var, var, 1);
747 store_cpu_field(var, thumb);
d9ba4830
PB		 748}
749
21aeb343
JR		 750/* Variant of store_reg which uses branch&exchange logic when storing
751 to r15 in ARM architecture v7 and above. The source must be a temporary
752 and will be marked as dead. */
753static inline void store_reg_bx(CPUState *env, DisasContext *s,
754 int reg, TCGv var)
755{
756 if (reg == 15 && ENABLE_ARCH_7) {
757 gen_bx(s, var);
758 } else {
759 store_reg(s, reg, var);
760 }
761}
762
b0109805
PB		 763static inline TCGv gen_ld8s(TCGv addr, int index)
764{
765 TCGv tmp = new_tmp();
766 tcg_gen_qemu_ld8s(tmp, addr, index);
767 return tmp;
768}
769static inline TCGv gen_ld8u(TCGv addr, int index)
770{
771 TCGv tmp = new_tmp();
772 tcg_gen_qemu_ld8u(tmp, addr, index);
773 return tmp;
774}
775static inline TCGv gen_ld16s(TCGv addr, int index)
776{
777 TCGv tmp = new_tmp();
778 tcg_gen_qemu_ld16s(tmp, addr, index);
779 return tmp;
780}
781static inline TCGv gen_ld16u(TCGv addr, int index)
782{
783 TCGv tmp = new_tmp();
784 tcg_gen_qemu_ld16u(tmp, addr, index);
785 return tmp;
786}
787static inline TCGv gen_ld32(TCGv addr, int index)
788{
789 TCGv tmp = new_tmp();
790 tcg_gen_qemu_ld32u(tmp, addr, index);
791 return tmp;
792}
84496233
JR		 793static inline TCGv_i64 gen_ld64(TCGv addr, int index)
794{
795 TCGv_i64 tmp = tcg_temp_new_i64();
796 tcg_gen_qemu_ld64(tmp, addr, index);
797 return tmp;
798}
b0109805
PB		 799static inline void gen_st8(TCGv val, TCGv addr, int index)
800{
801 tcg_gen_qemu_st8(val, addr, index);
802 dead_tmp(val);
803}
804static inline void gen_st16(TCGv val, TCGv addr, int index)
805{
806 tcg_gen_qemu_st16(val, addr, index);
807 dead_tmp(val);
808}
809static inline void gen_st32(TCGv val, TCGv addr, int index)
810{
811 tcg_gen_qemu_st32(val, addr, index);
812 dead_tmp(val);
813}
84496233
JR		 814static inline void gen_st64(TCGv_i64 val, TCGv addr, int index)
815{
816 tcg_gen_qemu_st64(val, addr, index);
817 tcg_temp_free_i64(val);
818}
b5ff1b31 819
5e3f878a
PB		 820static inline void gen_set_pc_im(uint32_t val)
821{
155c3eac 822 tcg_gen_movi_i32(cpu_R[15], val);
5e3f878a
PB		 823}
824
b5ff1b31
FB		 825/* Force a TB lookup after an instruction that changes the CPU state. */
826static inline void gen_lookup_tb(DisasContext *s)
827{
a6445c52 828 tcg_gen_movi_i32(cpu_R[15], s->pc & ~1);
b5ff1b31
FB		 829 s->is_jmp = DISAS_UPDATE;
830}
831
b0109805
PB		 832static inline void gen_add_data_offset(DisasContext *s, unsigned int insn,
833 TCGv var)
2c0262af 834{
1e8d4eec 835 int val, rm, shift, shiftop;
b26eefb6 836 TCGv offset;
2c0262af
FB		 837
838 if (!(insn & (1 << 25))) {
839 /* immediate */
840 val = insn & 0xfff;
841 if (!(insn & (1 << 23)))
842 val = -val;
537730b9 843 if (val != 0)
b0109805 844 tcg_gen_addi_i32(var, var, val);
2c0262af
FB		 845 } else {
846 /* shift/register */
847 rm = (insn) & 0xf;
848 shift = (insn >> 7) & 0x1f;
1e8d4eec 849 shiftop = (insn >> 5) & 3;
b26eefb6 850 offset = load_reg(s, rm);
9a119ff6 851 gen_arm_shift_im(offset, shiftop, shift, 0);
2c0262af 852 if (!(insn & (1 << 23)))
b0109805 853 tcg_gen_sub_i32(var, var, offset);
2c0262af 854 else
b0109805 855 tcg_gen_add_i32(var, var, offset);
b26eefb6 856 dead_tmp(offset);
2c0262af
FB		 857 }
858}
859
191f9a93 860static inline void gen_add_datah_offset(DisasContext *s, unsigned int insn,
b0109805 861 int extra, TCGv var)
2c0262af
FB		 862{
863 int val, rm;
b26eefb6 864 TCGv offset;
3b46e624 865
2c0262af
FB		 866 if (insn & (1 << 22)) {
867 /* immediate */
868 val = (insn & 0xf) | ((insn >> 4) & 0xf0);
869 if (!(insn & (1 << 23)))
870 val = -val;
18acad92 871 val += extra;
537730b9 872 if (val != 0)
b0109805 873 tcg_gen_addi_i32(var, var, val);
2c0262af
FB		 874 } else {
875 /* register */
191f9a93 876 if (extra)
b0109805 877 tcg_gen_addi_i32(var, var, extra);
2c0262af 878 rm = (insn) & 0xf;
b26eefb6 879 offset = load_reg(s, rm);
2c0262af 880 if (!(insn & (1 << 23)))
b0109805 881 tcg_gen_sub_i32(var, var, offset);
2c0262af 882 else
b0109805 883 tcg_gen_add_i32(var, var, offset);
b26eefb6 884 dead_tmp(offset);
2c0262af
FB		 885 }
886}
887
4373f3ce
PB		 888#define VFP_OP2(name) \
889static inline void gen_vfp_##name(int dp) \
890{ \
891 if (dp) \
892 gen_helper_vfp_##name##d(cpu_F0d, cpu_F0d, cpu_F1d, cpu_env); \
893 else \
894 gen_helper_vfp_##name##s(cpu_F0s, cpu_F0s, cpu_F1s, cpu_env); \
b7bcbe95
FB		 895}
896
4373f3ce
PB		 897VFP_OP2(add)
898VFP_OP2(sub)
899VFP_OP2(mul)
900VFP_OP2(div)
901
902#undef VFP_OP2
903
904static inline void gen_vfp_abs(int dp)
905{
906 if (dp)
907 gen_helper_vfp_absd(cpu_F0d, cpu_F0d);
908 else
909 gen_helper_vfp_abss(cpu_F0s, cpu_F0s);
910}
911
912static inline void gen_vfp_neg(int dp)
913{
914 if (dp)
915 gen_helper_vfp_negd(cpu_F0d, cpu_F0d);
916 else
917 gen_helper_vfp_negs(cpu_F0s, cpu_F0s);
918}
919
920static inline void gen_vfp_sqrt(int dp)
921{
922 if (dp)
923 gen_helper_vfp_sqrtd(cpu_F0d, cpu_F0d, cpu_env);
924 else
925 gen_helper_vfp_sqrts(cpu_F0s, cpu_F0s, cpu_env);
926}
927
928static inline void gen_vfp_cmp(int dp)
929{
930 if (dp)
931 gen_helper_vfp_cmpd(cpu_F0d, cpu_F1d, cpu_env);
932 else
933 gen_helper_vfp_cmps(cpu_F0s, cpu_F1s, cpu_env);
934}
935
936static inline void gen_vfp_cmpe(int dp)
937{
938 if (dp)
939 gen_helper_vfp_cmped(cpu_F0d, cpu_F1d, cpu_env);
940 else
941 gen_helper_vfp_cmpes(cpu_F0s, cpu_F1s, cpu_env);
942}
943
944static inline void gen_vfp_F1_ld0(int dp)
945{
946 if (dp)
5b340b51 947 tcg_gen_movi_i64(cpu_F1d, 0);
4373f3ce 948 else
5b340b51 949 tcg_gen_movi_i32(cpu_F1s, 0);
4373f3ce
PB		 950}
951
952static inline void gen_vfp_uito(int dp)
953{
954 if (dp)
955 gen_helper_vfp_uitod(cpu_F0d, cpu_F0s, cpu_env);
956 else
957 gen_helper_vfp_uitos(cpu_F0s, cpu_F0s, cpu_env);
958}
959
960static inline void gen_vfp_sito(int dp)
961{
962 if (dp)
66230e0d 963 gen_helper_vfp_sitod(cpu_F0d, cpu_F0s, cpu_env);
4373f3ce 964 else
66230e0d 965 gen_helper_vfp_sitos(cpu_F0s, cpu_F0s, cpu_env);
4373f3ce
PB		 966}
967
968static inline void gen_vfp_toui(int dp)
969{
970 if (dp)
971 gen_helper_vfp_touid(cpu_F0s, cpu_F0d, cpu_env);
972 else
973 gen_helper_vfp_touis(cpu_F0s, cpu_F0s, cpu_env);
974}
975
976static inline void gen_vfp_touiz(int dp)
977{
978 if (dp)
979 gen_helper_vfp_touizd(cpu_F0s, cpu_F0d, cpu_env);
980 else
981 gen_helper_vfp_touizs(cpu_F0s, cpu_F0s, cpu_env);
982}
983
984static inline void gen_vfp_tosi(int dp)
985{
986 if (dp)
987 gen_helper_vfp_tosid(cpu_F0s, cpu_F0d, cpu_env);
988 else
989 gen_helper_vfp_tosis(cpu_F0s, cpu_F0s, cpu_env);
990}
991
992static inline void gen_vfp_tosiz(int dp)
9ee6e8bb
PB		 993{
994 if (dp)
4373f3ce 995 gen_helper_vfp_tosizd(cpu_F0s, cpu_F0d, cpu_env);
9ee6e8bb 996 else
4373f3ce
PB		 997 gen_helper_vfp_tosizs(cpu_F0s, cpu_F0s, cpu_env);
998}
999
1000#define VFP_GEN_FIX(name) \
1001static inline void gen_vfp_##name(int dp, int shift) \
1002{ \
b75263d6 1003 TCGv tmp_shift = tcg_const_i32(shift); \
4373f3ce 1004 if (dp) \
b75263d6 1005 gen_helper_vfp_##name##d(cpu_F0d, cpu_F0d, tmp_shift, cpu_env);\
4373f3ce 1006 else \
b75263d6
JR		 1007 gen_helper_vfp_##name##s(cpu_F0s, cpu_F0s, tmp_shift, cpu_env);\
1008 tcg_temp_free_i32(tmp_shift); \
9ee6e8bb 1009}
4373f3ce
PB		 1010VFP_GEN_FIX(tosh)
1011VFP_GEN_FIX(tosl)
1012VFP_GEN_FIX(touh)
1013VFP_GEN_FIX(toul)
1014VFP_GEN_FIX(shto)
1015VFP_GEN_FIX(slto)
1016VFP_GEN_FIX(uhto)
1017VFP_GEN_FIX(ulto)
1018#undef VFP_GEN_FIX
9ee6e8bb 1019
312eea9f 1020static inline void gen_vfp_ld(DisasContext *s, int dp, TCGv addr)
b5ff1b31
FB		 1021{
1022 if (dp)
312eea9f 1023 tcg_gen_qemu_ld64(cpu_F0d, addr, IS_USER(s));
b5ff1b31 1024 else
312eea9f 1025 tcg_gen_qemu_ld32u(cpu_F0s, addr, IS_USER(s));
b5ff1b31
FB		 1026}
1027
312eea9f 1028static inline void gen_vfp_st(DisasContext *s, int dp, TCGv addr)
b5ff1b31
FB		 1029{
1030 if (dp)
312eea9f 1031 tcg_gen_qemu_st64(cpu_F0d, addr, IS_USER(s));
b5ff1b31 1032 else
312eea9f 1033 tcg_gen_qemu_st32(cpu_F0s, addr, IS_USER(s));
b5ff1b31
FB		 1034}
1035
8e96005d
FB		 1036static inline long
1037vfp_reg_offset (int dp, int reg)
1038{
1039 if (dp)
1040 return offsetof(CPUARMState, vfp.regs[reg]);
1041 else if (reg & 1) {
1042 return offsetof(CPUARMState, vfp.regs[reg >> 1])
1043 + offsetof(CPU_DoubleU, l.upper);
1044 } else {
1045 return offsetof(CPUARMState, vfp.regs[reg >> 1])
1046 + offsetof(CPU_DoubleU, l.lower);
1047 }
1048}
9ee6e8bb
PB		 1049
1050/* Return the offset of a 32-bit piece of a NEON register.
1051 zero is the least significant end of the register. */
1052static inline long
1053neon_reg_offset (int reg, int n)
1054{
1055 int sreg;
1056 sreg = reg * 2 + n;
1057 return vfp_reg_offset(0, sreg);
1058}
1059
8f8e3aa4
PB		 1060static TCGv neon_load_reg(int reg, int pass)
1061{
1062 TCGv tmp = new_tmp();
1063 tcg_gen_ld_i32(tmp, cpu_env, neon_reg_offset(reg, pass));
1064 return tmp;
1065}
1066
1067static void neon_store_reg(int reg, int pass, TCGv var)
1068{
1069 tcg_gen_st_i32(var, cpu_env, neon_reg_offset(reg, pass));
1070 dead_tmp(var);
1071}
1072
a7812ae4 1073static inline void neon_load_reg64(TCGv_i64 var, int reg)
ad69471c
PB		 1074{
1075 tcg_gen_ld_i64(var, cpu_env, vfp_reg_offset(1, reg));
1076}
1077
a7812ae4 1078static inline void neon_store_reg64(TCGv_i64 var, int reg)
ad69471c
PB		 1079{
1080 tcg_gen_st_i64(var, cpu_env, vfp_reg_offset(1, reg));
1081}
1082
4373f3ce
PB		 1083#define tcg_gen_ld_f32 tcg_gen_ld_i32
1084#define tcg_gen_ld_f64 tcg_gen_ld_i64
1085#define tcg_gen_st_f32 tcg_gen_st_i32
1086#define tcg_gen_st_f64 tcg_gen_st_i64
1087
b7bcbe95
FB		 1088static inline void gen_mov_F0_vreg(int dp, int reg)
1089{
1090 if (dp)
4373f3ce 1091 tcg_gen_ld_f64(cpu_F0d, cpu_env, vfp_reg_offset(dp, reg));
b7bcbe95 1092 else
4373f3ce 1093 tcg_gen_ld_f32(cpu_F0s, cpu_env, vfp_reg_offset(dp, reg));
b7bcbe95
FB		 1094}
1095
1096static inline void gen_mov_F1_vreg(int dp, int reg)
1097{
1098 if (dp)
4373f3ce 1099 tcg_gen_ld_f64(cpu_F1d, cpu_env, vfp_reg_offset(dp, reg));
b7bcbe95 1100 else
4373f3ce 1101 tcg_gen_ld_f32(cpu_F1s, cpu_env, vfp_reg_offset(dp, reg));
b7bcbe95
FB		 1102}
1103
1104static inline void gen_mov_vreg_F0(int dp, int reg)
1105{
1106 if (dp)
4373f3ce 1107 tcg_gen_st_f64(cpu_F0d, cpu_env, vfp_reg_offset(dp, reg));
b7bcbe95 1108 else
4373f3ce 1109 tcg_gen_st_f32(cpu_F0s, cpu_env, vfp_reg_offset(dp, reg));
b7bcbe95
FB		 1110}
1111
18c9b560
AZ		 1112#define ARM_CP_RW_BIT (1 << 20)
1113
a7812ae4 1114static inline void iwmmxt_load_reg(TCGv_i64 var, int reg)
e677137d
PB		 1115{
1116 tcg_gen_ld_i64(var, cpu_env, offsetof(CPUState, iwmmxt.regs[reg]));
1117}
1118
a7812ae4 1119static inline void iwmmxt_store_reg(TCGv_i64 var, int reg)
e677137d
PB		 1120{
1121 tcg_gen_st_i64(var, cpu_env, offsetof(CPUState, iwmmxt.regs[reg]));
1122}
1123
da6b5335 1124static inline TCGv iwmmxt_load_creg(int reg)
e677137d 1125{
da6b5335
FN		 1126 TCGv var = new_tmp();
1127 tcg_gen_ld_i32(var, cpu_env, offsetof(CPUState, iwmmxt.cregs[reg]));
1128 return var;
e677137d
PB		 1129}
1130
da6b5335 1131static inline void iwmmxt_store_creg(int reg, TCGv var)
e677137d 1132{
da6b5335 1133 tcg_gen_st_i32(var, cpu_env, offsetof(CPUState, iwmmxt.cregs[reg]));
d9968827 1134 dead_tmp(var);
e677137d
PB		 1135}
1136
1137static inline void gen_op_iwmmxt_movq_wRn_M0(int rn)
1138{
1139 iwmmxt_store_reg(cpu_M0, rn);
1140}
1141
1142static inline void gen_op_iwmmxt_movq_M0_wRn(int rn)
1143{
1144 iwmmxt_load_reg(cpu_M0, rn);
1145}
1146
1147static inline void gen_op_iwmmxt_orq_M0_wRn(int rn)
1148{
1149 iwmmxt_load_reg(cpu_V1, rn);
1150 tcg_gen_or_i64(cpu_M0, cpu_M0, cpu_V1);
1151}
1152
1153static inline void gen_op_iwmmxt_andq_M0_wRn(int rn)
1154{
1155 iwmmxt_load_reg(cpu_V1, rn);
1156 tcg_gen_and_i64(cpu_M0, cpu_M0, cpu_V1);
1157}
1158
1159static inline void gen_op_iwmmxt_xorq_M0_wRn(int rn)
1160{
1161 iwmmxt_load_reg(cpu_V1, rn);
1162 tcg_gen_xor_i64(cpu_M0, cpu_M0, cpu_V1);
1163}
1164
1165#define IWMMXT_OP(name) \
1166static inline void gen_op_iwmmxt_##name##_M0_wRn(int rn) \
1167{ \
1168 iwmmxt_load_reg(cpu_V1, rn); \
1169 gen_helper_iwmmxt_##name(cpu_M0, cpu_M0, cpu_V1); \
1170}
1171
1172#define IWMMXT_OP_ENV(name) \
1173static inline void gen_op_iwmmxt_##name##_M0_wRn(int rn) \
1174{ \
1175 iwmmxt_load_reg(cpu_V1, rn); \
1176 gen_helper_iwmmxt_##name(cpu_M0, cpu_env, cpu_M0, cpu_V1); \
1177}
1178
1179#define IWMMXT_OP_ENV_SIZE(name) \
1180IWMMXT_OP_ENV(name##b) \
1181IWMMXT_OP_ENV(name##w) \
1182IWMMXT_OP_ENV(name##l)
1183
1184#define IWMMXT_OP_ENV1(name) \
1185static inline void gen_op_iwmmxt_##name##_M0(void) \
1186{ \
1187 gen_helper_iwmmxt_##name(cpu_M0, cpu_env, cpu_M0); \
1188}
1189
1190IWMMXT_OP(maddsq)
1191IWMMXT_OP(madduq)
1192IWMMXT_OP(sadb)
1193IWMMXT_OP(sadw)
1194IWMMXT_OP(mulslw)
1195IWMMXT_OP(mulshw)
1196IWMMXT_OP(mululw)
1197IWMMXT_OP(muluhw)
1198IWMMXT_OP(macsw)
1199IWMMXT_OP(macuw)
1200
1201IWMMXT_OP_ENV_SIZE(unpackl)
1202IWMMXT_OP_ENV_SIZE(unpackh)
1203
1204IWMMXT_OP_ENV1(unpacklub)
1205IWMMXT_OP_ENV1(unpackluw)
1206IWMMXT_OP_ENV1(unpacklul)
1207IWMMXT_OP_ENV1(unpackhub)
1208IWMMXT_OP_ENV1(unpackhuw)
1209IWMMXT_OP_ENV1(unpackhul)
1210IWMMXT_OP_ENV1(unpacklsb)
1211IWMMXT_OP_ENV1(unpacklsw)
1212IWMMXT_OP_ENV1(unpacklsl)
1213IWMMXT_OP_ENV1(unpackhsb)
1214IWMMXT_OP_ENV1(unpackhsw)
1215IWMMXT_OP_ENV1(unpackhsl)
1216
1217IWMMXT_OP_ENV_SIZE(cmpeq)
1218IWMMXT_OP_ENV_SIZE(cmpgtu)
1219IWMMXT_OP_ENV_SIZE(cmpgts)
1220
1221IWMMXT_OP_ENV_SIZE(mins)
1222IWMMXT_OP_ENV_SIZE(minu)
1223IWMMXT_OP_ENV_SIZE(maxs)
1224IWMMXT_OP_ENV_SIZE(maxu)
1225
1226IWMMXT_OP_ENV_SIZE(subn)
1227IWMMXT_OP_ENV_SIZE(addn)
1228IWMMXT_OP_ENV_SIZE(subu)
1229IWMMXT_OP_ENV_SIZE(addu)
1230IWMMXT_OP_ENV_SIZE(subs)
1231IWMMXT_OP_ENV_SIZE(adds)
1232
1233IWMMXT_OP_ENV(avgb0)
1234IWMMXT_OP_ENV(avgb1)
1235IWMMXT_OP_ENV(avgw0)
1236IWMMXT_OP_ENV(avgw1)
1237
1238IWMMXT_OP(msadb)
1239
1240IWMMXT_OP_ENV(packuw)
1241IWMMXT_OP_ENV(packul)
1242IWMMXT_OP_ENV(packuq)
1243IWMMXT_OP_ENV(packsw)
1244IWMMXT_OP_ENV(packsl)
1245IWMMXT_OP_ENV(packsq)
1246
e677137d
PB		 1247static void gen_op_iwmmxt_set_mup(void)
1248{
1249 TCGv tmp;
1250 tmp = load_cpu_field(iwmmxt.cregs[ARM_IWMMXT_wCon]);
1251 tcg_gen_ori_i32(tmp, tmp, 2);
1252 store_cpu_field(tmp, iwmmxt.cregs[ARM_IWMMXT_wCon]);
1253}
1254
1255static void gen_op_iwmmxt_set_cup(void)
1256{
1257 TCGv tmp;
1258 tmp = load_cpu_field(iwmmxt.cregs[ARM_IWMMXT_wCon]);
1259 tcg_gen_ori_i32(tmp, tmp, 1);
1260 store_cpu_field(tmp, iwmmxt.cregs[ARM_IWMMXT_wCon]);
1261}
1262
1263static void gen_op_iwmmxt_setpsr_nz(void)
1264{
1265 TCGv tmp = new_tmp();
1266 gen_helper_iwmmxt_setpsr_nz(tmp, cpu_M0);
1267 store_cpu_field(tmp, iwmmxt.cregs[ARM_IWMMXT_wCASF]);
1268}
1269
1270static inline void gen_op_iwmmxt_addl_M0_wRn(int rn)
1271{
1272 iwmmxt_load_reg(cpu_V1, rn);
86831435 1273 tcg_gen_ext32u_i64(cpu_V1, cpu_V1);
e677137d
PB		 1274 tcg_gen_add_i64(cpu_M0, cpu_M0, cpu_V1);
1275}
1276
da6b5335 1277static inline int gen_iwmmxt_address(DisasContext *s, uint32_t insn, TCGv dest)
18c9b560
AZ		 1278{
1279 int rd;
1280 uint32_t offset;
da6b5335 1281 TCGv tmp;
18c9b560
AZ		 1282
1283 rd = (insn >> 16) & 0xf;
da6b5335 1284 tmp = load_reg(s, rd);
18c9b560
AZ		 1285
1286 offset = (insn & 0xff) << ((insn >> 7) & 2);
1287 if (insn & (1 << 24)) {
1288 /* Pre indexed */
1289 if (insn & (1 << 23))
da6b5335 1290 tcg_gen_addi_i32(tmp, tmp, offset);
18c9b560 1291 else
da6b5335
FN		 1292 tcg_gen_addi_i32(tmp, tmp, -offset);
1293 tcg_gen_mov_i32(dest, tmp);
18c9b560 1294 if (insn & (1 << 21))
da6b5335
FN		 1295 store_reg(s, rd, tmp);
1296 else
1297 dead_tmp(tmp);
18c9b560
AZ		 1298 } else if (insn & (1 << 21)) {
1299 /* Post indexed */
da6b5335 1300 tcg_gen_mov_i32(dest, tmp);
18c9b560 1301 if (insn & (1 << 23))
da6b5335 1302 tcg_gen_addi_i32(tmp, tmp, offset);
18c9b560 1303 else
da6b5335
FN		 1304 tcg_gen_addi_i32(tmp, tmp, -offset);
1305 store_reg(s, rd, tmp);
18c9b560
AZ		 1306 } else if (!(insn & (1 << 23)))
1307 return 1;
1308 return 0;
1309}
1310
da6b5335 1311static inline int gen_iwmmxt_shift(uint32_t insn, uint32_t mask, TCGv dest)
18c9b560
AZ		 1312{
1313 int rd = (insn >> 0) & 0xf;
da6b5335 1314 TCGv tmp;
18c9b560 1315
da6b5335
FN		 1316 if (insn & (1 << 8)) {
1317 if (rd < ARM_IWMMXT_wCGR0 || rd > ARM_IWMMXT_wCGR3) {
18c9b560 1318 return 1;
da6b5335
FN		 1319 } else {
1320 tmp = iwmmxt_load_creg(rd);
1321 }
1322 } else {
1323 tmp = new_tmp();
1324 iwmmxt_load_reg(cpu_V0, rd);
1325 tcg_gen_trunc_i64_i32(tmp, cpu_V0);
1326 }
1327 tcg_gen_andi_i32(tmp, tmp, mask);
1328 tcg_gen_mov_i32(dest, tmp);
1329 dead_tmp(tmp);
18c9b560
AZ		 1330 return 0;
1331}
1332
1333/* Disassemble an iwMMXt instruction. Returns nonzero if an error occured
1334 (ie. an undefined instruction). */
1335static int disas_iwmmxt_insn(CPUState *env, DisasContext *s, uint32_t insn)
1336{
1337 int rd, wrd;
1338 int rdhi, rdlo, rd0, rd1, i;
da6b5335
FN		 1339 TCGv addr;
1340 TCGv tmp, tmp2, tmp3;
18c9b560
AZ		 1341
1342 if ((insn & 0x0e000e00) == 0x0c000000) {
1343 if ((insn & 0x0fe00ff0) == 0x0c400000) {
1344 wrd = insn & 0xf;
1345 rdlo = (insn >> 12) & 0xf;
1346 rdhi = (insn >> 16) & 0xf;
1347 if (insn & ARM_CP_RW_BIT) { /* TMRRC */
da6b5335
FN		 1348 iwmmxt_load_reg(cpu_V0, wrd);
1349 tcg_gen_trunc_i64_i32(cpu_R[rdlo], cpu_V0);
1350 tcg_gen_shri_i64(cpu_V0, cpu_V0, 32);
1351 tcg_gen_trunc_i64_i32(cpu_R[rdhi], cpu_V0);
18c9b560 1352 } else { /* TMCRR */
da6b5335
FN		 1353 tcg_gen_concat_i32_i64(cpu_V0, cpu_R[rdlo], cpu_R[rdhi]);
1354 iwmmxt_store_reg(cpu_V0, wrd);
18c9b560
AZ		 1355 gen_op_iwmmxt_set_mup();
1356 }
1357 return 0;
1358 }
1359
1360 wrd = (insn >> 12) & 0xf;
da6b5335
FN		 1361 addr = new_tmp();
1362 if (gen_iwmmxt_address(s, insn, addr)) {
1363 dead_tmp(addr);
18c9b560 1364 return 1;
da6b5335 1365 }
18c9b560
AZ		 1366 if (insn & ARM_CP_RW_BIT) {
1367 if ((insn >> 28) == 0xf) { /* WLDRW wCx */
da6b5335
FN		 1368 tmp = new_tmp();
1369 tcg_gen_qemu_ld32u(tmp, addr, IS_USER(s));
1370 iwmmxt_store_creg(wrd, tmp);
18c9b560 1371 } else {
e677137d
PB		 1372 i = 1;
1373 if (insn & (1 << 8)) {
1374 if (insn & (1 << 22)) { /* WLDRD */
da6b5335 1375 tcg_gen_qemu_ld64(cpu_M0, addr, IS_USER(s));
e677137d
PB		 1376 i = 0;
1377 } else { /* WLDRW wRd */
da6b5335 1378 tmp = gen_ld32(addr, IS_USER(s));
e677137d
PB		 1379 }
1380 } else {
1381 if (insn & (1 << 22)) { /* WLDRH */
da6b5335 1382 tmp = gen_ld16u(addr, IS_USER(s));
e677137d 1383 } else { /* WLDRB */
da6b5335 1384 tmp = gen_ld8u(addr, IS_USER(s));
e677137d
PB		 1385 }
1386 }
1387 if (i) {
1388 tcg_gen_extu_i32_i64(cpu_M0, tmp);
1389 dead_tmp(tmp);
1390 }
18c9b560
AZ		 1391 gen_op_iwmmxt_movq_wRn_M0(wrd);
1392 }
1393 } else {
1394 if ((insn >> 28) == 0xf) { /* WSTRW wCx */
da6b5335
FN		 1395 tmp = iwmmxt_load_creg(wrd);
1396 gen_st32(tmp, addr, IS_USER(s));
18c9b560
AZ		 1397 } else {
1398 gen_op_iwmmxt_movq_M0_wRn(wrd);
e677137d
PB		 1399 tmp = new_tmp();
1400 if (insn & (1 << 8)) {
1401 if (insn & (1 << 22)) { /* WSTRD */
1402 dead_tmp(tmp);
da6b5335 1403 tcg_gen_qemu_st64(cpu_M0, addr, IS_USER(s));
e677137d
PB		 1404 } else { /* WSTRW wRd */
1405 tcg_gen_trunc_i64_i32(tmp, cpu_M0);
da6b5335 1406 gen_st32(tmp, addr, IS_USER(s));
e677137d
PB		 1407 }
1408 } else {
1409 if (insn & (1 << 22)) { /* WSTRH */
1410 tcg_gen_trunc_i64_i32(tmp, cpu_M0);
da6b5335 1411 gen_st16(tmp, addr, IS_USER(s));
e677137d
PB		 1412 } else { /* WSTRB */
1413 tcg_gen_trunc_i64_i32(tmp, cpu_M0);
da6b5335 1414 gen_st8(tmp, addr, IS_USER(s));
e677137d
PB		 1415 }
1416 }
18c9b560
AZ		 1417 }
1418 }
d9968827 1419 dead_tmp(addr);
18c9b560
AZ		 1420 return 0;
1421 }
1422
1423 if ((insn & 0x0f000000) != 0x0e000000)
1424 return 1;
1425
1426 switch (((insn >> 12) & 0xf00) | ((insn >> 4) & 0xff)) {
1427 case 0x000: /* WOR */
1428 wrd = (insn >> 12) & 0xf;
1429 rd0 = (insn >> 0) & 0xf;
1430 rd1 = (insn >> 16) & 0xf;
1431 gen_op_iwmmxt_movq_M0_wRn(rd0);
1432 gen_op_iwmmxt_orq_M0_wRn(rd1);
1433 gen_op_iwmmxt_setpsr_nz();
1434 gen_op_iwmmxt_movq_wRn_M0(wrd);
1435 gen_op_iwmmxt_set_mup();
1436 gen_op_iwmmxt_set_cup();
1437 break;
1438 case 0x011: /* TMCR */
1439 if (insn & 0xf)
1440 return 1;
1441 rd = (insn >> 12) & 0xf;
1442 wrd = (insn >> 16) & 0xf;
1443 switch (wrd) {
1444 case ARM_IWMMXT_wCID:
1445 case ARM_IWMMXT_wCASF:
1446 break;
1447 case ARM_IWMMXT_wCon:
1448 gen_op_iwmmxt_set_cup();
1449 /* Fall through. */
1450 case ARM_IWMMXT_wCSSF:
da6b5335
FN		 1451 tmp = iwmmxt_load_creg(wrd);
1452 tmp2 = load_reg(s, rd);
f669df27 1453 tcg_gen_andc_i32(tmp, tmp, tmp2);
da6b5335
FN		 1454 dead_tmp(tmp2);
1455 iwmmxt_store_creg(wrd, tmp);
18c9b560
AZ		 1456 break;
1457 case ARM_IWMMXT_wCGR0:
1458 case ARM_IWMMXT_wCGR1:
1459 case ARM_IWMMXT_wCGR2:
1460 case ARM_IWMMXT_wCGR3:
1461 gen_op_iwmmxt_set_cup();
da6b5335
FN		 1462 tmp = load_reg(s, rd);
1463 iwmmxt_store_creg(wrd, tmp);
18c9b560
AZ		 1464 break;
1465 default:
1466 return 1;
1467 }
1468 break;
1469 case 0x100: /* WXOR */
1470 wrd = (insn >> 12) & 0xf;
1471 rd0 = (insn >> 0) & 0xf;
1472 rd1 = (insn >> 16) & 0xf;
1473 gen_op_iwmmxt_movq_M0_wRn(rd0);
1474 gen_op_iwmmxt_xorq_M0_wRn(rd1);
1475 gen_op_iwmmxt_setpsr_nz();
1476 gen_op_iwmmxt_movq_wRn_M0(wrd);
1477 gen_op_iwmmxt_set_mup();
1478 gen_op_iwmmxt_set_cup();
1479 break;
1480 case 0x111: /* TMRC */
1481 if (insn & 0xf)
1482 return 1;
1483 rd = (insn >> 12) & 0xf;
1484 wrd = (insn >> 16) & 0xf;
da6b5335
FN		 1485 tmp = iwmmxt_load_creg(wrd);
1486 store_reg(s, rd, tmp);
18c9b560
AZ		 1487 break;
1488 case 0x300: /* WANDN */
1489 wrd = (insn >> 12) & 0xf;
1490 rd0 = (insn >> 0) & 0xf;
1491 rd1 = (insn >> 16) & 0xf;
1492 gen_op_iwmmxt_movq_M0_wRn(rd0);
e677137d 1493 tcg_gen_neg_i64(cpu_M0, cpu_M0);
18c9b560
AZ		 1494 gen_op_iwmmxt_andq_M0_wRn(rd1);
1495 gen_op_iwmmxt_setpsr_nz();
1496 gen_op_iwmmxt_movq_wRn_M0(wrd);
1497 gen_op_iwmmxt_set_mup();
1498 gen_op_iwmmxt_set_cup();
1499 break;
1500 case 0x200: /* WAND */
1501 wrd = (insn >> 12) & 0xf;
1502 rd0 = (insn >> 0) & 0xf;
1503 rd1 = (insn >> 16) & 0xf;
1504 gen_op_iwmmxt_movq_M0_wRn(rd0);
1505 gen_op_iwmmxt_andq_M0_wRn(rd1);
1506 gen_op_iwmmxt_setpsr_nz();
1507 gen_op_iwmmxt_movq_wRn_M0(wrd);
1508 gen_op_iwmmxt_set_mup();
1509 gen_op_iwmmxt_set_cup();
1510 break;
1511 case 0x810: case 0xa10: /* WMADD */
1512 wrd = (insn >> 12) & 0xf;
1513 rd0 = (insn >> 0) & 0xf;
1514 rd1 = (insn >> 16) & 0xf;
1515 gen_op_iwmmxt_movq_M0_wRn(rd0);
1516 if (insn & (1 << 21))
1517 gen_op_iwmmxt_maddsq_M0_wRn(rd1);
1518 else
1519 gen_op_iwmmxt_madduq_M0_wRn(rd1);
1520 gen_op_iwmmxt_movq_wRn_M0(wrd);
1521 gen_op_iwmmxt_set_mup();
1522 break;
1523 case 0x10e: case 0x50e: case 0x90e: case 0xd0e: /* WUNPCKIL */
1524 wrd = (insn >> 12) & 0xf;
1525 rd0 = (insn >> 16) & 0xf;
1526 rd1 = (insn >> 0) & 0xf;
1527 gen_op_iwmmxt_movq_M0_wRn(rd0);
1528 switch ((insn >> 22) & 3) {
1529 case 0:
1530 gen_op_iwmmxt_unpacklb_M0_wRn(rd1);
1531 break;
1532 case 1:
1533 gen_op_iwmmxt_unpacklw_M0_wRn(rd1);
1534 break;
1535 case 2:
1536 gen_op_iwmmxt_unpackll_M0_wRn(rd1);
1537 break;
1538 case 3:
1539 return 1;
1540 }
1541 gen_op_iwmmxt_movq_wRn_M0(wrd);
1542 gen_op_iwmmxt_set_mup();
1543 gen_op_iwmmxt_set_cup();
1544 break;
1545 case 0x10c: case 0x50c: case 0x90c: case 0xd0c: /* WUNPCKIH */
1546 wrd = (insn >> 12) & 0xf;
1547 rd0 = (insn >> 16) & 0xf;
1548 rd1 = (insn >> 0) & 0xf;
1549 gen_op_iwmmxt_movq_M0_wRn(rd0);
1550 switch ((insn >> 22) & 3) {
1551 case 0:
1552 gen_op_iwmmxt_unpackhb_M0_wRn(rd1);
1553 break;
1554 case 1:
1555 gen_op_iwmmxt_unpackhw_M0_wRn(rd1);
1556 break;
1557 case 2:
1558 gen_op_iwmmxt_unpackhl_M0_wRn(rd1);
1559 break;
1560 case 3:
1561 return 1;
1562 }
1563 gen_op_iwmmxt_movq_wRn_M0(wrd);
1564 gen_op_iwmmxt_set_mup();
1565 gen_op_iwmmxt_set_cup();
1566 break;
1567 case 0x012: case 0x112: case 0x412: case 0x512: /* WSAD */
1568 wrd = (insn >> 12) & 0xf;
1569 rd0 = (insn >> 16) & 0xf;
1570 rd1 = (insn >> 0) & 0xf;
1571 gen_op_iwmmxt_movq_M0_wRn(rd0);
1572 if (insn & (1 << 22))
1573 gen_op_iwmmxt_sadw_M0_wRn(rd1);
1574 else
1575 gen_op_iwmmxt_sadb_M0_wRn(rd1);
1576 if (!(insn & (1 << 20)))
1577 gen_op_iwmmxt_addl_M0_wRn(wrd);
1578 gen_op_iwmmxt_movq_wRn_M0(wrd);
1579 gen_op_iwmmxt_set_mup();
1580 break;
1581 case 0x010: case 0x110: case 0x210: case 0x310: /* WMUL */
1582 wrd = (insn >> 12) & 0xf;
1583 rd0 = (insn >> 16) & 0xf;
1584 rd1 = (insn >> 0) & 0xf;
1585 gen_op_iwmmxt_movq_M0_wRn(rd0);
e677137d
PB		 1586 if (insn & (1 << 21)) {
1587 if (insn & (1 << 20))
1588 gen_op_iwmmxt_mulshw_M0_wRn(rd1);
1589 else
1590 gen_op_iwmmxt_mulslw_M0_wRn(rd1);
1591 } else {
1592 if (insn & (1 << 20))
1593 gen_op_iwmmxt_muluhw_M0_wRn(rd1);
1594 else
1595 gen_op_iwmmxt_mululw_M0_wRn(rd1);
1596 }
18c9b560
AZ		 1597 gen_op_iwmmxt_movq_wRn_M0(wrd);
1598 gen_op_iwmmxt_set_mup();
1599 break;
1600 case 0x410: case 0x510: case 0x610: case 0x710: /* WMAC */
1601 wrd = (insn >> 12) & 0xf;
1602 rd0 = (insn >> 16) & 0xf;
1603 rd1 = (insn >> 0) & 0xf;
1604 gen_op_iwmmxt_movq_M0_wRn(rd0);
1605 if (insn & (1 << 21))
1606 gen_op_iwmmxt_macsw_M0_wRn(rd1);
1607 else
1608 gen_op_iwmmxt_macuw_M0_wRn(rd1);
1609 if (!(insn & (1 << 20))) {
e677137d
PB		 1610 iwmmxt_load_reg(cpu_V1, wrd);
1611 tcg_gen_add_i64(cpu_M0, cpu_M0, cpu_V1);
18c9b560
AZ		 1612 }
1613 gen_op_iwmmxt_movq_wRn_M0(wrd);
1614 gen_op_iwmmxt_set_mup();
1615 break;
1616 case 0x006: case 0x406: case 0x806: case 0xc06: /* WCMPEQ */
1617 wrd = (insn >> 12) & 0xf;
1618 rd0 = (insn >> 16) & 0xf;
1619 rd1 = (insn >> 0) & 0xf;
1620 gen_op_iwmmxt_movq_M0_wRn(rd0);
1621 switch ((insn >> 22) & 3) {
1622 case 0:
1623 gen_op_iwmmxt_cmpeqb_M0_wRn(rd1);
1624 break;
1625 case 1:
1626 gen_op_iwmmxt_cmpeqw_M0_wRn(rd1);
1627 break;
1628 case 2:
1629 gen_op_iwmmxt_cmpeql_M0_wRn(rd1);
1630 break;
1631 case 3:
1632 return 1;
1633 }
1634 gen_op_iwmmxt_movq_wRn_M0(wrd);
1635 gen_op_iwmmxt_set_mup();
1636 gen_op_iwmmxt_set_cup();
1637 break;
1638 case 0x800: case 0x900: case 0xc00: case 0xd00: /* WAVG2 */
1639 wrd = (insn >> 12) & 0xf;
1640 rd0 = (insn >> 16) & 0xf;
1641 rd1 = (insn >> 0) & 0xf;
1642 gen_op_iwmmxt_movq_M0_wRn(rd0);
e677137d
PB		 1643 if (insn & (1 << 22)) {
1644 if (insn & (1 << 20))
1645 gen_op_iwmmxt_avgw1_M0_wRn(rd1);
1646 else
1647 gen_op_iwmmxt_avgw0_M0_wRn(rd1);
1648 } else {
1649 if (insn & (1 << 20))
1650 gen_op_iwmmxt_avgb1_M0_wRn(rd1);
1651 else
1652 gen_op_iwmmxt_avgb0_M0_wRn(rd1);
1653 }
18c9b560
AZ		 1654 gen_op_iwmmxt_movq_wRn_M0(wrd);
1655 gen_op_iwmmxt_set_mup();
1656 gen_op_iwmmxt_set_cup();
1657 break;
1658 case 0x802: case 0x902: case 0xa02: case 0xb02: /* WALIGNR */
1659 wrd = (insn >> 12) & 0xf;
1660 rd0 = (insn >> 16) & 0xf;
1661 rd1 = (insn >> 0) & 0xf;
1662 gen_op_iwmmxt_movq_M0_wRn(rd0);
da6b5335
FN		 1663 tmp = iwmmxt_load_creg(ARM_IWMMXT_wCGR0 + ((insn >> 20) & 3));
1664 tcg_gen_andi_i32(tmp, tmp, 7);
1665 iwmmxt_load_reg(cpu_V1, rd1);
1666 gen_helper_iwmmxt_align(cpu_M0, cpu_M0, cpu_V1, tmp);
1667 dead_tmp(tmp);
18c9b560
AZ		 1668 gen_op_iwmmxt_movq_wRn_M0(wrd);
1669 gen_op_iwmmxt_set_mup();
1670 break;
1671 case 0x601: case 0x605: case 0x609: case 0x60d: /* TINSR */
da6b5335
FN		 1672 if (((insn >> 6) & 3) == 3)
1673 return 1;
18c9b560
AZ		 1674 rd = (insn >> 12) & 0xf;
1675 wrd = (insn >> 16) & 0xf;
da6b5335 1676 tmp = load_reg(s, rd);
18c9b560
AZ		 1677 gen_op_iwmmxt_movq_M0_wRn(wrd);
1678 switch ((insn >> 6) & 3) {
1679 case 0:
da6b5335
FN		 1680 tmp2 = tcg_const_i32(0xff);
1681 tmp3 = tcg_const_i32((insn & 7) << 3);
18c9b560
AZ		 1682 break;
1683 case 1:
da6b5335
FN		 1684 tmp2 = tcg_const_i32(0xffff);
1685 tmp3 = tcg_const_i32((insn & 3) << 4);
18c9b560
AZ		 1686 break;
1687 case 2:
da6b5335
FN		 1688 tmp2 = tcg_const_i32(0xffffffff);
1689 tmp3 = tcg_const_i32((insn & 1) << 5);
18c9b560 1690 break;
da6b5335
FN		 1691 default:
1692 TCGV_UNUSED(tmp2);
1693 TCGV_UNUSED(tmp3);
18c9b560 1694 }
da6b5335
FN		 1695 gen_helper_iwmmxt_insr(cpu_M0, cpu_M0, tmp, tmp2, tmp3);
1696 tcg_temp_free(tmp3);
1697 tcg_temp_free(tmp2);
1698 dead_tmp(tmp);
18c9b560
AZ		 1699 gen_op_iwmmxt_movq_wRn_M0(wrd);
1700 gen_op_iwmmxt_set_mup();
1701 break;
1702 case 0x107: case 0x507: case 0x907: case 0xd07: /* TEXTRM */
1703 rd = (insn >> 12) & 0xf;
1704 wrd = (insn >> 16) & 0xf;
da6b5335 1705 if (rd == 15 || ((insn >> 22) & 3) == 3)
18c9b560
AZ		 1706 return 1;
1707 gen_op_iwmmxt_movq_M0_wRn(wrd);
da6b5335 1708 tmp = new_tmp();
18c9b560
AZ		 1709 switch ((insn >> 22) & 3) {
1710 case 0:
da6b5335
FN		 1711 tcg_gen_shri_i64(cpu_M0, cpu_M0, (insn & 7) << 3);
1712 tcg_gen_trunc_i64_i32(tmp, cpu_M0);
1713 if (insn & 8) {
1714 tcg_gen_ext8s_i32(tmp, tmp);
1715 } else {
1716 tcg_gen_andi_i32(tmp, tmp, 0xff);
18c9b560
AZ		 1717 }
1718 break;
1719 case 1:
da6b5335
FN		 1720 tcg_gen_shri_i64(cpu_M0, cpu_M0, (insn & 3) << 4);
1721 tcg_gen_trunc_i64_i32(tmp, cpu_M0);
1722 if (insn & 8) {
1723 tcg_gen_ext16s_i32(tmp, tmp);
1724 } else {
1725 tcg_gen_andi_i32(tmp, tmp, 0xffff);
18c9b560
AZ		 1726 }
1727 break;
1728 case 2:
da6b5335
FN		 1729 tcg_gen_shri_i64(cpu_M0, cpu_M0, (insn & 1) << 5);
1730 tcg_gen_trunc_i64_i32(tmp, cpu_M0);
18c9b560 1731 break;
18c9b560 1732 }
da6b5335 1733 store_reg(s, rd, tmp);
18c9b560
AZ		 1734 break;
1735 case 0x117: case 0x517: case 0x917: case 0xd17: /* TEXTRC */
da6b5335 1736 if ((insn & 0x000ff008) != 0x0003f000 || ((insn >> 22) & 3) == 3)
18c9b560 1737 return 1;
da6b5335 1738 tmp = iwmmxt_load_creg(ARM_IWMMXT_wCASF);
18c9b560
AZ		 1739 switch ((insn >> 22) & 3) {
1740 case 0:
da6b5335 1741 tcg_gen_shri_i32(tmp, tmp, ((insn & 7) << 2) + 0);
18c9b560
AZ		 1742 break;
1743 case 1:
da6b5335 1744 tcg_gen_shri_i32(tmp, tmp, ((insn & 3) << 3) + 4);
18c9b560
AZ		 1745 break;
1746 case 2:
da6b5335 1747 tcg_gen_shri_i32(tmp, tmp, ((insn & 1) << 4) + 12);
18c9b560 1748 break;
18c9b560 1749 }
da6b5335
FN		 1750 tcg_gen_shli_i32(tmp, tmp, 28);
1751 gen_set_nzcv(tmp);
1752 dead_tmp(tmp);
18c9b560
AZ		 1753 break;
1754 case 0x401: case 0x405: case 0x409: case 0x40d: /* TBCST */
da6b5335
FN		 1755 if (((insn >> 6) & 3) == 3)
1756 return 1;
18c9b560
AZ		 1757 rd = (insn >> 12) & 0xf;
1758 wrd = (insn >> 16) & 0xf;
da6b5335 1759 tmp = load_reg(s, rd);
18c9b560
AZ		 1760 switch ((insn >> 6) & 3) {
1761 case 0:
da6b5335 1762 gen_helper_iwmmxt_bcstb(cpu_M0, tmp);
18c9b560
AZ		 1763 break;
1764 case 1:
da6b5335 1765 gen_helper_iwmmxt_bcstw(cpu_M0, tmp);
18c9b560
AZ		 1766 break;
1767 case 2:
da6b5335 1768 gen_helper_iwmmxt_bcstl(cpu_M0, tmp);
18c9b560 1769 break;
18c9b560 1770 }
da6b5335 1771 dead_tmp(tmp);
18c9b560
AZ		 1772 gen_op_iwmmxt_movq_wRn_M0(wrd);
1773 gen_op_iwmmxt_set_mup();
1774 break;
1775 case 0x113: case 0x513: case 0x913: case 0xd13: /* TANDC */
da6b5335 1776 if ((insn & 0x000ff00f) != 0x0003f000 || ((insn >> 22) & 3) == 3)
18c9b560 1777 return 1;
da6b5335
FN		 1778 tmp = iwmmxt_load_creg(ARM_IWMMXT_wCASF);
1779 tmp2 = new_tmp();
1780 tcg_gen_mov_i32(tmp2, tmp);
18c9b560
AZ		 1781 switch ((insn >> 22) & 3) {
1782 case 0:
1783 for (i = 0; i < 7; i ++) {
da6b5335
FN		 1784 tcg_gen_shli_i32(tmp2, tmp2, 4);
1785 tcg_gen_and_i32(tmp, tmp, tmp2);
18c9b560
AZ		 1786 }
1787 break;
1788 case 1:
1789 for (i = 0; i < 3; i ++) {
da6b5335
FN		 1790 tcg_gen_shli_i32(tmp2, tmp2, 8);
1791 tcg_gen_and_i32(tmp, tmp, tmp2);
18c9b560
AZ		 1792 }
1793 break;
1794 case 2:
da6b5335
FN		 1795 tcg_gen_shli_i32(tmp2, tmp2, 16);
1796 tcg_gen_and_i32(tmp, tmp, tmp2);
18c9b560 1797 break;
18c9b560 1798 }
da6b5335
FN		 1799 gen_set_nzcv(tmp);
1800 dead_tmp(tmp2);
1801 dead_tmp(tmp);
18c9b560
AZ		 1802 break;
1803 case 0x01c: case 0x41c: case 0x81c: case 0xc1c: /* WACC */
1804 wrd = (insn >> 12) & 0xf;
1805 rd0 = (insn >> 16) & 0xf;
1806 gen_op_iwmmxt_movq_M0_wRn(rd0);
1807 switch ((insn >> 22) & 3) {
1808 case 0:
e677137d 1809 gen_helper_iwmmxt_addcb(cpu_M0, cpu_M0);
18c9b560
AZ		 1810 break;
1811 case 1:
e677137d 1812 gen_helper_iwmmxt_addcw(cpu_M0, cpu_M0);
18c9b560
AZ		 1813 break;
1814 case 2:
e677137d 1815 gen_helper_iwmmxt_addcl(cpu_M0, cpu_M0);
18c9b560
AZ		 1816 break;
1817 case 3:
1818 return 1;
1819 }
1820 gen_op_iwmmxt_movq_wRn_M0(wrd);
1821 gen_op_iwmmxt_set_mup();
1822 break;
1823 case 0x115: case 0x515: case 0x915: case 0xd15: /* TORC */
da6b5335 1824 if ((insn & 0x000ff00f) != 0x0003f000 || ((insn >> 22) & 3) == 3)
18c9b560 1825 return 1;
da6b5335
FN		 1826 tmp = iwmmxt_load_creg(ARM_IWMMXT_wCASF);
1827 tmp2 = new_tmp();
1828 tcg_gen_mov_i32(tmp2, tmp);
18c9b560
AZ		 1829 switch ((insn >> 22) & 3) {
1830 case 0:
1831 for (i = 0; i < 7; i ++) {
da6b5335
FN		 1832 tcg_gen_shli_i32(tmp2, tmp2, 4);
1833 tcg_gen_or_i32(tmp, tmp, tmp2);
18c9b560
AZ		 1834 }
1835 break;
1836 case 1:
1837 for (i = 0; i < 3; i ++) {
da6b5335
FN		 1838 tcg_gen_shli_i32(tmp2, tmp2, 8);
1839 tcg_gen_or_i32(tmp, tmp, tmp2);
18c9b560
AZ		 1840 }
1841 break;
1842 case 2:
da6b5335
FN		 1843 tcg_gen_shli_i32(tmp2, tmp2, 16);
1844 tcg_gen_or_i32(tmp, tmp, tmp2);
18c9b560 1845 break;
18c9b560 1846 }
da6b5335
FN		 1847 gen_set_nzcv(tmp);
1848 dead_tmp(tmp2);
1849 dead_tmp(tmp);
18c9b560
AZ		 1850 break;
1851 case 0x103: case 0x503: case 0x903: case 0xd03: /* TMOVMSK */
1852 rd = (insn >> 12) & 0xf;
1853 rd0 = (insn >> 16) & 0xf;
da6b5335 1854 if ((insn & 0xf) != 0 || ((insn >> 22) & 3) == 3)
18c9b560
AZ		 1855 return 1;
1856 gen_op_iwmmxt_movq_M0_wRn(rd0);
da6b5335 1857 tmp = new_tmp();
18c9b560
AZ		 1858 switch ((insn >> 22) & 3) {
1859 case 0:
da6b5335 1860 gen_helper_iwmmxt_msbb(tmp, cpu_M0);
18c9b560
AZ		 1861 break;
1862 case 1:
da6b5335 1863 gen_helper_iwmmxt_msbw(tmp, cpu_M0);
18c9b560
AZ		 1864 break;
1865 case 2:
da6b5335 1866 gen_helper_iwmmxt_msbl(tmp, cpu_M0);
18c9b560 1867 break;
18c9b560 1868 }
da6b5335 1869 store_reg(s, rd, tmp);
18c9b560
AZ		 1870 break;
1871 case 0x106: case 0x306: case 0x506: case 0x706: /* WCMPGT */
1872 case 0x906: case 0xb06: case 0xd06: case 0xf06:
1873 wrd = (insn >> 12) & 0xf;
1874 rd0 = (insn >> 16) & 0xf;
1875 rd1 = (insn >> 0) & 0xf;
1876 gen_op_iwmmxt_movq_M0_wRn(rd0);
1877 switch ((insn >> 22) & 3) {
1878 case 0:
1879 if (insn & (1 << 21))
1880 gen_op_iwmmxt_cmpgtsb_M0_wRn(rd1);
1881 else
1882 gen_op_iwmmxt_cmpgtub_M0_wRn(rd1);
1883 break;
1884 case 1:
1885 if (insn & (1 << 21))
1886 gen_op_iwmmxt_cmpgtsw_M0_wRn(rd1);
1887 else
1888 gen_op_iwmmxt_cmpgtuw_M0_wRn(rd1);
1889 break;
1890 case 2:
1891 if (insn & (1 << 21))
1892 gen_op_iwmmxt_cmpgtsl_M0_wRn(rd1);
1893 else
1894 gen_op_iwmmxt_cmpgtul_M0_wRn(rd1);
1895 break;
1896 case 3:
1897 return 1;
1898 }
1899 gen_op_iwmmxt_movq_wRn_M0(wrd);
1900 gen_op_iwmmxt_set_mup();
1901 gen_op_iwmmxt_set_cup();
1902 break;
1903 case 0x00e: case 0x20e: case 0x40e: case 0x60e: /* WUNPCKEL */
1904 case 0x80e: case 0xa0e: case 0xc0e: case 0xe0e:
1905 wrd = (insn >> 12) & 0xf;
1906 rd0 = (insn >> 16) & 0xf;
1907 gen_op_iwmmxt_movq_M0_wRn(rd0);
1908 switch ((insn >> 22) & 3) {
1909 case 0:
1910 if (insn & (1 << 21))
1911 gen_op_iwmmxt_unpacklsb_M0();
1912 else
1913 gen_op_iwmmxt_unpacklub_M0();
1914 break;
1915 case 1:
1916 if (insn & (1 << 21))
1917 gen_op_iwmmxt_unpacklsw_M0();
1918 else
1919 gen_op_iwmmxt_unpackluw_M0();
1920 break;
1921 case 2:
1922 if (insn & (1 << 21))
1923 gen_op_iwmmxt_unpacklsl_M0();
1924 else
1925 gen_op_iwmmxt_unpacklul_M0();
1926 break;
1927 case 3:
1928 return 1;
1929 }
1930 gen_op_iwmmxt_movq_wRn_M0(wrd);
1931 gen_op_iwmmxt_set_mup();
1932 gen_op_iwmmxt_set_cup();
1933 break;
1934 case 0x00c: case 0x20c: case 0x40c: case 0x60c: /* WUNPCKEH */
1935 case 0x80c: case 0xa0c: case 0xc0c: case 0xe0c:
1936 wrd = (insn >> 12) & 0xf;
1937 rd0 = (insn >> 16) & 0xf;
1938 gen_op_iwmmxt_movq_M0_wRn(rd0);
1939 switch ((insn >> 22) & 3) {
1940 case 0:
1941 if (insn & (1 << 21))
1942 gen_op_iwmmxt_unpackhsb_M0();
1943 else
1944 gen_op_iwmmxt_unpackhub_M0();
1945 break;
1946 case 1:
1947 if (insn & (1 << 21))
1948 gen_op_iwmmxt_unpackhsw_M0();
1949 else
1950 gen_op_iwmmxt_unpackhuw_M0();
1951 break;
1952 case 2:
1953 if (insn & (1 << 21))
1954 gen_op_iwmmxt_unpackhsl_M0();
1955 else
1956 gen_op_iwmmxt_unpackhul_M0();
1957 break;
1958 case 3:
1959 return 1;
1960 }
1961 gen_op_iwmmxt_movq_wRn_M0(wrd);
1962 gen_op_iwmmxt_set_mup();
1963 gen_op_iwmmxt_set_cup();
1964 break;
1965 case 0x204: case 0x604: case 0xa04: case 0xe04: /* WSRL */
1966 case 0x214: case 0x614: case 0xa14: case 0xe14:
da6b5335
FN		 1967 if (((insn >> 22) & 3) == 0)
1968 return 1;
18c9b560
AZ		 1969 wrd = (insn >> 12) & 0xf;
1970 rd0 = (insn >> 16) & 0xf;
1971 gen_op_iwmmxt_movq_M0_wRn(rd0);
da6b5335
FN		 1972 tmp = new_tmp();
1973 if (gen_iwmmxt_shift(insn, 0xff, tmp)) {
1974 dead_tmp(tmp);
18c9b560 1975 return 1;
da6b5335 1976 }
18c9b560 1977 switch ((insn >> 22) & 3) {
18c9b560 1978 case 1:
da6b5335 1979 gen_helper_iwmmxt_srlw(cpu_M0, cpu_env, cpu_M0, tmp);
18c9b560
AZ		 1980 break;
1981 case 2:
da6b5335 1982 gen_helper_iwmmxt_srll(cpu_M0, cpu_env, cpu_M0, tmp);
18c9b560
AZ		 1983 break;
1984 case 3:
da6b5335 1985 gen_helper_iwmmxt_srlq(cpu_M0, cpu_env, cpu_M0, tmp);
18c9b560
AZ		 1986 break;
1987 }
da6b5335 1988 dead_tmp(tmp);
18c9b560
AZ		 1989 gen_op_iwmmxt_movq_wRn_M0(wrd);
1990 gen_op_iwmmxt_set_mup();
1991 gen_op_iwmmxt_set_cup();
1992 break;
1993 case 0x004: case 0x404: case 0x804: case 0xc04: /* WSRA */
1994 case 0x014: case 0x414: case 0x814: case 0xc14:
da6b5335
FN		 1995 if (((insn >> 22) & 3) == 0)
1996 return 1;
18c9b560
AZ		 1997 wrd = (insn >> 12) & 0xf;
1998 rd0 = (insn >> 16) & 0xf;
1999 gen_op_iwmmxt_movq_M0_wRn(rd0);
da6b5335
FN		 2000 tmp = new_tmp();
2001 if (gen_iwmmxt_shift(insn, 0xff, tmp)) {
2002 dead_tmp(tmp);
18c9b560 2003 return 1;
da6b5335 2004 }
18c9b560 2005 switch ((insn >> 22) & 3) {
18c9b560 2006 case 1:
da6b5335 2007 gen_helper_iwmmxt_sraw(cpu_M0, cpu_env, cpu_M0, tmp);
18c9b560
AZ		 2008 break;
2009 case 2:
da6b5335 2010 gen_helper_iwmmxt_sral(cpu_M0, cpu_env, cpu_M0, tmp);
18c9b560
AZ		 2011 break;
2012 case 3:
da6b5335 2013 gen_helper_iwmmxt_sraq(cpu_M0, cpu_env, cpu_M0, tmp);
18c9b560
AZ		 2014 break;
2015 }
da6b5335 2016 dead_tmp(tmp);
18c9b560
AZ		 2017 gen_op_iwmmxt_movq_wRn_M0(wrd);
2018 gen_op_iwmmxt_set_mup();
2019 gen_op_iwmmxt_set_cup();
2020 break;
2021 case 0x104: case 0x504: case 0x904: case 0xd04: /* WSLL */
2022 case 0x114: case 0x514: case 0x914: case 0xd14:
da6b5335
FN		 2023 if (((insn >> 22) & 3) == 0)
2024 return 1;
18c9b560
AZ		 2025 wrd = (insn >> 12) & 0xf;
2026 rd0 = (insn >> 16) & 0xf;
2027 gen_op_iwmmxt_movq_M0_wRn(rd0);
da6b5335
FN		 2028 tmp = new_tmp();
2029 if (gen_iwmmxt_shift(insn, 0xff, tmp)) {
2030 dead_tmp(tmp);
18c9b560 2031 return 1;
da6b5335 2032 }
18c9b560 2033 switch ((insn >> 22) & 3) {
18c9b560 2034 case 1:
da6b5335 2035 gen_helper_iwmmxt_sllw(cpu_M0, cpu_env, cpu_M0, tmp);
18c9b560
AZ		 2036 break;
2037 case 2:
da6b5335 2038 gen_helper_iwmmxt_slll(cpu_M0, cpu_env, cpu_M0, tmp);
18c9b560
AZ		 2039 break;
2040 case 3:
da6b5335 2041 gen_helper_iwmmxt_sllq(cpu_M0, cpu_env, cpu_M0, tmp);
18c9b560
AZ		 2042 break;
2043 }
da6b5335 2044 dead_tmp(tmp);
18c9b560
AZ		 2045 gen_op_iwmmxt_movq_wRn_M0(wrd);
2046 gen_op_iwmmxt_set_mup();
2047 gen_op_iwmmxt_set_cup();
2048 break;
2049 case 0x304: case 0x704: case 0xb04: case 0xf04: /* WROR */
2050 case 0x314: case 0x714: case 0xb14: case 0xf14:
da6b5335
FN		 2051 if (((insn >> 22) & 3) == 0)
2052 return 1;
18c9b560
AZ		 2053 wrd = (insn >> 12) & 0xf;
2054 rd0 = (insn >> 16) & 0xf;
2055 gen_op_iwmmxt_movq_M0_wRn(rd0);
da6b5335 2056 tmp = new_tmp();
18c9b560 2057 switch ((insn >> 22) & 3) {
18c9b560 2058 case 1:
da6b5335
FN		 2059 if (gen_iwmmxt_shift(insn, 0xf, tmp)) {
2060 dead_tmp(tmp);
18c9b560 2061 return 1;
da6b5335
FN		 2062 }
2063 gen_helper_iwmmxt_rorw(cpu_M0, cpu_env, cpu_M0, tmp);
18c9b560
AZ		 2064 break;
2065 case 2:
da6b5335
FN		 2066 if (gen_iwmmxt_shift(insn, 0x1f, tmp)) {
2067 dead_tmp(tmp);
18c9b560 2068 return 1;
da6b5335
FN		 2069 }
2070 gen_helper_iwmmxt_rorl(cpu_M0, cpu_env, cpu_M0, tmp);
18c9b560
AZ		 2071 break;
2072 case 3:
da6b5335
FN		 2073 if (gen_iwmmxt_shift(insn, 0x3f, tmp)) {
2074 dead_tmp(tmp);
18c9b560 2075 return 1;
da6b5335
FN		 2076 }
2077 gen_helper_iwmmxt_rorq(cpu_M0, cpu_env, cpu_M0, tmp);
18c9b560
AZ		 2078 break;
2079 }
da6b5335 2080 dead_tmp(tmp);
18c9b560
AZ		 2081 gen_op_iwmmxt_movq_wRn_M0(wrd);
2082 gen_op_iwmmxt_set_mup();
2083 gen_op_iwmmxt_set_cup();
2084 break;
2085 case 0x116: case 0x316: case 0x516: case 0x716: /* WMIN */
2086 case 0x916: case 0xb16: case 0xd16: case 0xf16:
2087 wrd = (insn >> 12) & 0xf;
2088 rd0 = (insn >> 16) & 0xf;
2089 rd1 = (insn >> 0) & 0xf;
2090 gen_op_iwmmxt_movq_M0_wRn(rd0);
2091 switch ((insn >> 22) & 3) {
2092 case 0:
2093 if (insn & (1 << 21))
2094 gen_op_iwmmxt_minsb_M0_wRn(rd1);
2095 else
2096 gen_op_iwmmxt_minub_M0_wRn(rd1);
2097 break;
2098 case 1:
2099 if (insn & (1 << 21))
2100 gen_op_iwmmxt_minsw_M0_wRn(rd1);
2101 else
2102 gen_op_iwmmxt_minuw_M0_wRn(rd1);
2103 break;
2104 case 2:
2105 if (insn & (1 << 21))
2106 gen_op_iwmmxt_minsl_M0_wRn(rd1);
2107 else
2108 gen_op_iwmmxt_minul_M0_wRn(rd1);
2109 break;
2110 case 3:
2111 return 1;
2112 }
2113 gen_op_iwmmxt_movq_wRn_M0(wrd);
2114 gen_op_iwmmxt_set_mup();
2115 break;
2116 case 0x016: case 0x216: case 0x416: case 0x616: /* WMAX */
2117 case 0x816: case 0xa16: case 0xc16: case 0xe16:
2118 wrd = (insn >> 12) & 0xf;
2119 rd0 = (insn >> 16) & 0xf;
2120 rd1 = (insn >> 0) & 0xf;
2121 gen_op_iwmmxt_movq_M0_wRn(rd0);
2122 switch ((insn >> 22) & 3) {
2123 case 0:
2124 if (insn & (1 << 21))
2125 gen_op_iwmmxt_maxsb_M0_wRn(rd1);
2126 else
2127 gen_op_iwmmxt_maxub_M0_wRn(rd1);
2128 break;
2129 case 1:
2130 if (insn & (1 << 21))
2131 gen_op_iwmmxt_maxsw_M0_wRn(rd1);
2132 else
2133 gen_op_iwmmxt_maxuw_M0_wRn(rd1);
2134 break;
2135 case 2:
2136 if (insn & (1 << 21))
2137 gen_op_iwmmxt_maxsl_M0_wRn(rd1);
2138 else
2139 gen_op_iwmmxt_maxul_M0_wRn(rd1);
2140 break;
2141 case 3:
2142 return 1;
2143 }
2144 gen_op_iwmmxt_movq_wRn_M0(wrd);
2145 gen_op_iwmmxt_set_mup();
2146 break;
2147 case 0x002: case 0x102: case 0x202: case 0x302: /* WALIGNI */
2148 case 0x402: case 0x502: case 0x602: case 0x702:
2149 wrd = (insn >> 12) & 0xf;
2150 rd0 = (insn >> 16) & 0xf;
2151 rd1 = (insn >> 0) & 0xf;
2152 gen_op_iwmmxt_movq_M0_wRn(rd0);
da6b5335
FN		 2153 tmp = tcg_const_i32((insn >> 20) & 3);
2154 iwmmxt_load_reg(cpu_V1, rd1);
2155 gen_helper_iwmmxt_align(cpu_M0, cpu_M0, cpu_V1, tmp);
2156 tcg_temp_free(tmp);
18c9b560
AZ		 2157 gen_op_iwmmxt_movq_wRn_M0(wrd);
2158 gen_op_iwmmxt_set_mup();
2159 break;
2160 case 0x01a: case 0x11a: case 0x21a: case 0x31a: /* WSUB */
2161 case 0x41a: case 0x51a: case 0x61a: case 0x71a:
2162 case 0x81a: case 0x91a: case 0xa1a: case 0xb1a:
2163 case 0xc1a: case 0xd1a: case 0xe1a: case 0xf1a:
2164 wrd = (insn >> 12) & 0xf;
2165 rd0 = (insn >> 16) & 0xf;
2166 rd1 = (insn >> 0) & 0xf;
2167 gen_op_iwmmxt_movq_M0_wRn(rd0);
2168 switch ((insn >> 20) & 0xf) {
2169 case 0x0:
2170 gen_op_iwmmxt_subnb_M0_wRn(rd1);
2171 break;
2172 case 0x1:
2173 gen_op_iwmmxt_subub_M0_wRn(rd1);
2174 break;
2175 case 0x3:
2176 gen_op_iwmmxt_subsb_M0_wRn(rd1);
2177 break;
2178 case 0x4:
2179 gen_op_iwmmxt_subnw_M0_wRn(rd1);
2180 break;
2181 case 0x5:
2182 gen_op_iwmmxt_subuw_M0_wRn(rd1);
2183 break;
2184 case 0x7:
2185 gen_op_iwmmxt_subsw_M0_wRn(rd1);
2186 break;
2187 case 0x8:
2188 gen_op_iwmmxt_subnl_M0_wRn(rd1);
2189 break;
2190 case 0x9:
2191 gen_op_iwmmxt_subul_M0_wRn(rd1);
2192 break;
2193 case 0xb:
2194 gen_op_iwmmxt_subsl_M0_wRn(rd1);
2195 break;
2196 default:
2197 return 1;
2198 }
2199 gen_op_iwmmxt_movq_wRn_M0(wrd);
2200 gen_op_iwmmxt_set_mup();
2201 gen_op_iwmmxt_set_cup();
2202 break;
2203 case 0x01e: case 0x11e: case 0x21e: case 0x31e: /* WSHUFH */
2204 case 0x41e: case 0x51e: case 0x61e: case 0x71e:
2205 case 0x81e: case 0x91e: case 0xa1e: case 0xb1e:
2206 case 0xc1e: case 0xd1e: case 0xe1e: case 0xf1e:
2207 wrd = (insn >> 12) & 0xf;
2208 rd0 = (insn >> 16) & 0xf;
2209 gen_op_iwmmxt_movq_M0_wRn(rd0);
da6b5335
FN		 2210 tmp = tcg_const_i32(((insn >> 16) & 0xf0) | (insn & 0x0f));
2211 gen_helper_iwmmxt_shufh(cpu_M0, cpu_env, cpu_M0, tmp);
2212 tcg_temp_free(tmp);
18c9b560
AZ		 2213 gen_op_iwmmxt_movq_wRn_M0(wrd);
2214 gen_op_iwmmxt_set_mup();
2215 gen_op_iwmmxt_set_cup();
2216 break;
2217 case 0x018: case 0x118: case 0x218: case 0x318: /* WADD */
2218 case 0x418: case 0x518: case 0x618: case 0x718:
2219 case 0x818: case 0x918: case 0xa18: case 0xb18:
2220 case 0xc18: case 0xd18: case 0xe18: case 0xf18:
2221 wrd = (insn >> 12) & 0xf;
2222 rd0 = (insn >> 16) & 0xf;
2223 rd1 = (insn >> 0) & 0xf;
2224 gen_op_iwmmxt_movq_M0_wRn(rd0);
2225 switch ((insn >> 20) & 0xf) {
2226 case 0x0:
2227 gen_op_iwmmxt_addnb_M0_wRn(rd1);
2228 break;
2229 case 0x1:
2230 gen_op_iwmmxt_addub_M0_wRn(rd1);
2231 break;
2232 case 0x3:
2233 gen_op_iwmmxt_addsb_M0_wRn(rd1);
2234 break;
2235 case 0x4:
2236 gen_op_iwmmxt_addnw_M0_wRn(rd1);
2237 break;
2238 case 0x5:
2239 gen_op_iwmmxt_adduw_M0_wRn(rd1);
2240 break;
2241 case 0x7:
2242 gen_op_iwmmxt_addsw_M0_wRn(rd1);
2243 break;
2244 case 0x8:
2245 gen_op_iwmmxt_addnl_M0_wRn(rd1);
2246 break;
2247 case 0x9:
2248 gen_op_iwmmxt_addul_M0_wRn(rd1);
2249 break;
2250 case 0xb:
2251 gen_op_iwmmxt_addsl_M0_wRn(rd1);
2252 break;
2253 default:
2254 return 1;
2255 }
2256 gen_op_iwmmxt_movq_wRn_M0(wrd);
2257 gen_op_iwmmxt_set_mup();
2258 gen_op_iwmmxt_set_cup();
2259 break;
2260 case 0x008: case 0x108: case 0x208: case 0x308: /* WPACK */
2261 case 0x408: case 0x508: case 0x608: case 0x708:
2262 case 0x808: case 0x908: case 0xa08: case 0xb08:
2263 case 0xc08: case 0xd08: case 0xe08: case 0xf08:
da6b5335
FN		 2264 if (!(insn & (1 << 20)) || ((insn >> 22) & 3) == 0)
2265 return 1;
18c9b560
AZ		 2266 wrd = (insn >> 12) & 0xf;
2267 rd0 = (insn >> 16) & 0xf;
2268 rd1 = (insn >> 0) & 0xf;
2269 gen_op_iwmmxt_movq_M0_wRn(rd0);
18c9b560 2270 switch ((insn >> 22) & 3) {
18c9b560
AZ		 2271 case 1:
2272 if (insn & (1 << 21))
2273 gen_op_iwmmxt_packsw_M0_wRn(rd1);
2274 else
2275 gen_op_iwmmxt_packuw_M0_wRn(rd1);
2276 break;
2277 case 2:
2278 if (insn & (1 << 21))
2279 gen_op_iwmmxt_packsl_M0_wRn(rd1);
2280 else
2281 gen_op_iwmmxt_packul_M0_wRn(rd1);
2282 break;
2283 case 3:
2284 if (insn & (1 << 21))
2285 gen_op_iwmmxt_packsq_M0_wRn(rd1);
2286 else
2287 gen_op_iwmmxt_packuq_M0_wRn(rd1);
2288 break;
2289 }
2290 gen_op_iwmmxt_movq_wRn_M0(wrd);
2291 gen_op_iwmmxt_set_mup();
2292 gen_op_iwmmxt_set_cup();
2293 break;
2294 case 0x201: case 0x203: case 0x205: case 0x207:
2295 case 0x209: case 0x20b: case 0x20d: case 0x20f:
2296 case 0x211: case 0x213: case 0x215: case 0x217:
2297 case 0x219: case 0x21b: case 0x21d: case 0x21f:
2298 wrd = (insn >> 5) & 0xf;
2299 rd0 = (insn >> 12) & 0xf;
2300 rd1 = (insn >> 0) & 0xf;
2301 if (rd0 == 0xf || rd1 == 0xf)
2302 return 1;
2303 gen_op_iwmmxt_movq_M0_wRn(wrd);
da6b5335
FN		 2304 tmp = load_reg(s, rd0);
2305 tmp2 = load_reg(s, rd1);
18c9b560
AZ		 2306 switch ((insn >> 16) & 0xf) {
2307 case 0x0: /* TMIA */
da6b5335 2308 gen_helper_iwmmxt_muladdsl(cpu_M0, cpu_M0, tmp, tmp2);
18c9b560
AZ		 2309 break;
2310 case 0x8: /* TMIAPH */
da6b5335 2311 gen_helper_iwmmxt_muladdsw(cpu_M0, cpu_M0, tmp, tmp2);
18c9b560
AZ		 2312 break;
2313 case 0xc: case 0xd: case 0xe: case 0xf: /* TMIAxy */
18c9b560 2314 if (insn & (1 << 16))
da6b5335 2315 tcg_gen_shri_i32(tmp, tmp, 16);
18c9b560 2316 if (insn & (1 << 17))
da6b5335
FN		 2317 tcg_gen_shri_i32(tmp2, tmp2, 16);
2318 gen_helper_iwmmxt_muladdswl(cpu_M0, cpu_M0, tmp, tmp2);
18c9b560
AZ		 2319 break;
2320 default:
da6b5335
FN		 2321 dead_tmp(tmp2);
2322 dead_tmp(tmp);
18c9b560
AZ		 2323 return 1;
2324 }
da6b5335
FN		 2325 dead_tmp(tmp2);
2326 dead_tmp(tmp);
18c9b560
AZ		 2327 gen_op_iwmmxt_movq_wRn_M0(wrd);
2328 gen_op_iwmmxt_set_mup();
2329 break;
2330 default:
2331 return 1;
2332 }
2333
2334 return 0;
2335}
2336
2337/* Disassemble an XScale DSP instruction. Returns nonzero if an error occured
2338 (ie. an undefined instruction). */
2339static int disas_dsp_insn(CPUState *env, DisasContext *s, uint32_t insn)
2340{
2341 int acc, rd0, rd1, rdhi, rdlo;
3a554c0f 2342 TCGv tmp, tmp2;
18c9b560
AZ		 2343
2344 if ((insn & 0x0ff00f10) == 0x0e200010) {
2345 /* Multiply with Internal Accumulate Format */
2346 rd0 = (insn >> 12) & 0xf;
2347 rd1 = insn & 0xf;
2348 acc = (insn >> 5) & 7;
2349
2350 if (acc != 0)
2351 return 1;
2352
3a554c0f
FN		 2353 tmp = load_reg(s, rd0);
2354 tmp2 = load_reg(s, rd1);
18c9b560
AZ		 2355 switch ((insn >> 16) & 0xf) {
2356 case 0x0: /* MIA */
3a554c0f 2357 gen_helper_iwmmxt_muladdsl(cpu_M0, cpu_M0, tmp, tmp2);
18c9b560
AZ		 2358 break;
2359 case 0x8: /* MIAPH */
3a554c0f 2360 gen_helper_iwmmxt_muladdsw(cpu_M0, cpu_M0, tmp, tmp2);
18c9b560
AZ		 2361 break;
2362 case 0xc: /* MIABB */
2363 case 0xd: /* MIABT */
2364 case 0xe: /* MIATB */
2365 case 0xf: /* MIATT */
18c9b560 2366 if (insn & (1 << 16))
3a554c0f 2367 tcg_gen_shri_i32(tmp, tmp, 16);
18c9b560 2368 if (insn & (1 << 17))
3a554c0f
FN		 2369 tcg_gen_shri_i32(tmp2, tmp2, 16);
2370 gen_helper_iwmmxt_muladdswl(cpu_M0, cpu_M0, tmp, tmp2);
18c9b560
AZ		 2371 break;
2372 default:
2373 return 1;
2374 }
3a554c0f
FN		 2375 dead_tmp(tmp2);
2376 dead_tmp(tmp);
18c9b560
AZ		 2377
2378 gen_op_iwmmxt_movq_wRn_M0(acc);
2379 return 0;
2380 }
2381
2382 if ((insn & 0x0fe00ff8) == 0x0c400000) {
2383 /* Internal Accumulator Access Format */
2384 rdhi = (insn >> 16) & 0xf;
2385 rdlo = (insn >> 12) & 0xf;
2386 acc = insn & 7;
2387
2388 if (acc != 0)
2389 return 1;
2390
2391 if (insn & ARM_CP_RW_BIT) { /* MRA */
3a554c0f
FN		 2392 iwmmxt_load_reg(cpu_V0, acc);
2393 tcg_gen_trunc_i64_i32(cpu_R[rdlo], cpu_V0);
2394 tcg_gen_shri_i64(cpu_V0, cpu_V0, 32);
2395 tcg_gen_trunc_i64_i32(cpu_R[rdhi], cpu_V0);
2396 tcg_gen_andi_i32(cpu_R[rdhi], cpu_R[rdhi], (1 << (40 - 32)) - 1);
18c9b560 2397 } else { /* MAR */
3a554c0f
FN		 2398 tcg_gen_concat_i32_i64(cpu_V0, cpu_R[rdlo], cpu_R[rdhi]);
2399 iwmmxt_store_reg(cpu_V0, acc);
18c9b560
AZ		 2400 }
2401 return 0;
2402 }
2403
2404 return 1;
2405}
2406
c1713132
AZ		 2407/* Disassemble system coprocessor instruction. Return nonzero if
2408 instruction is not defined. */
2409static int disas_cp_insn(CPUState *env, DisasContext *s, uint32_t insn)
2410{
b75263d6 2411 TCGv tmp, tmp2;
c1713132
AZ		 2412 uint32_t rd = (insn >> 12) & 0xf;
2413 uint32_t cp = (insn >> 8) & 0xf;
2414 if (IS_USER(s)) {
2415 return 1;
2416 }
2417
18c9b560 2418 if (insn & ARM_CP_RW_BIT) {
c1713132
AZ		 2419 if (!env->cp[cp].cp_read)
2420 return 1;
8984bd2e
PB		 2421 gen_set_pc_im(s->pc);
2422 tmp = new_tmp();
b75263d6
JR		 2423 tmp2 = tcg_const_i32(insn);
2424 gen_helper_get_cp(tmp, cpu_env, tmp2);
2425 tcg_temp_free(tmp2);
8984bd2e 2426 store_reg(s, rd, tmp);
c1713132
AZ		 2427 } else {
2428 if (!env->cp[cp].cp_write)
2429 return 1;
8984bd2e
PB		 2430 gen_set_pc_im(s->pc);
2431 tmp = load_reg(s, rd);
b75263d6
JR		 2432 tmp2 = tcg_const_i32(insn);
2433 gen_helper_set_cp(cpu_env, tmp2, tmp);
2434 tcg_temp_free(tmp2);
a60de947 2435 dead_tmp(tmp);
c1713132
AZ		 2436 }
2437 return 0;
2438}
2439
9ee6e8bb
PB		 2440static int cp15_user_ok(uint32_t insn)
2441{
2442 int cpn = (insn >> 16) & 0xf;
2443 int cpm = insn & 0xf;
2444 int op = ((insn >> 5) & 7) | ((insn >> 18) & 0x38);
2445
2446 if (cpn == 13 && cpm == 0) {
2447 /* TLS register. */
2448 if (op == 2 || (op == 3 && (insn & ARM_CP_RW_BIT)))
2449 return 1;
2450 }
2451 if (cpn == 7) {
2452 /* ISB, DSB, DMB. */
2453 if ((cpm == 5 && op == 4)
2454 || (cpm == 10 && (op == 4 || op == 5)))
2455 return 1;
2456 }
2457 return 0;
2458}
2459
3f26c122
RV		 2460static int cp15_tls_load_store(CPUState *env, DisasContext *s, uint32_t insn, uint32_t rd)
2461{
2462 TCGv tmp;
2463 int cpn = (insn >> 16) & 0xf;
2464 int cpm = insn & 0xf;
2465 int op = ((insn >> 5) & 7) | ((insn >> 18) & 0x38);
2466
2467 if (!arm_feature(env, ARM_FEATURE_V6K))
2468 return 0;
2469
2470 if (!(cpn == 13 && cpm == 0))
2471 return 0;
2472
2473 if (insn & ARM_CP_RW_BIT) {
3f26c122
RV		 2474 switch (op) {
2475 case 2:
c5883be2 2476 tmp = load_cpu_field(cp15.c13_tls1);
3f26c122
RV		 2477 break;
2478 case 3:
c5883be2 2479 tmp = load_cpu_field(cp15.c13_tls2);
3f26c122
RV		 2480 break;
2481 case 4:
c5883be2 2482 tmp = load_cpu_field(cp15.c13_tls3);
3f26c122
RV		 2483 break;
2484 default:
3f26c122
RV		 2485 return 0;
2486 }
2487 store_reg(s, rd, tmp);
2488
2489 } else {
2490 tmp = load_reg(s, rd);
2491 switch (op) {
2492 case 2:
c5883be2 2493 store_cpu_field(tmp, cp15.c13_tls1);
3f26c122
RV		 2494 break;
2495 case 3:
c5883be2 2496 store_cpu_field(tmp, cp15.c13_tls2);
3f26c122
RV		 2497 break;
2498 case 4:
c5883be2 2499 store_cpu_field(tmp, cp15.c13_tls3);
3f26c122
RV		 2500 break;
2501 default:
c5883be2 2502 dead_tmp(tmp);
3f26c122
RV		 2503 return 0;
2504 }
3f26c122
RV		 2505 }
2506 return 1;
2507}
2508
b5ff1b31
FB		 2509/* Disassemble system coprocessor (cp15) instruction. Return nonzero if
2510 instruction is not defined. */
a90b7318 2511static int disas_cp15_insn(CPUState *env, DisasContext *s, uint32_t insn)
b5ff1b31
FB		 2512{
2513 uint32_t rd;
b75263d6 2514 TCGv tmp, tmp2;
b5ff1b31 2515
9ee6e8bb
PB		 2516 /* M profile cores use memory mapped registers instead of cp15. */
2517 if (arm_feature(env, ARM_FEATURE_M))
2518 return 1;
2519
2520 if ((insn & (1 << 25)) == 0) {
2521 if (insn & (1 << 20)) {
2522 /* mrrc */
2523 return 1;
2524 }
2525 /* mcrr. Used for block cache operations, so implement as no-op. */
2526 return 0;
2527 }
2528 if ((insn & (1 << 4)) == 0) {
2529 /* cdp */
2530 return 1;
2531 }
2532 if (IS_USER(s) && !cp15_user_ok(insn)) {
b5ff1b31
FB		 2533 return 1;
2534 }
9332f9da
FB		 2535 if ((insn & 0x0fff0fff) == 0x0e070f90
2536 || (insn & 0x0fff0fff) == 0x0e070f58) {
2537 /* Wait for interrupt. */
8984bd2e 2538 gen_set_pc_im(s->pc);
9ee6e8bb 2539 s->is_jmp = DISAS_WFI;
9332f9da
FB		 2540 return 0;
2541 }
b5ff1b31 2542 rd = (insn >> 12) & 0xf;
3f26c122
RV		 2543
2544 if (cp15_tls_load_store(env, s, insn, rd))
2545 return 0;
2546
b75263d6 2547 tmp2 = tcg_const_i32(insn);
18c9b560 2548 if (insn & ARM_CP_RW_BIT) {
8984bd2e 2549 tmp = new_tmp();
b75263d6 2550 gen_helper_get_cp15(tmp, cpu_env, tmp2);
b5ff1b31
FB		 2551 /* If the destination register is r15 then sets condition codes. */
2552 if (rd != 15)
8984bd2e
PB		 2553 store_reg(s, rd, tmp);
2554 else
2555 dead_tmp(tmp);
b5ff1b31 2556 } else {
8984bd2e 2557 tmp = load_reg(s, rd);
b75263d6 2558 gen_helper_set_cp15(cpu_env, tmp2, tmp);
8984bd2e 2559 dead_tmp(tmp);
a90b7318
AZ		 2560 /* Normally we would always end the TB here, but Linux
2561 * arch/arm/mach-pxa/sleep.S expects two instructions following
2562 * an MMU enable to execute from cache. Imitate this behaviour. */
2563 if (!arm_feature(env, ARM_FEATURE_XSCALE) ||
2564 (insn & 0x0fff0fff) != 0x0e010f10)
2565 gen_lookup_tb(s);
b5ff1b31 2566 }
b75263d6 2567 tcg_temp_free_i32(tmp2);
b5ff1b31
FB		 2568 return 0;
2569}
2570
9ee6e8bb
PB		 2571#define VFP_REG_SHR(x, n) (((n) > 0) ? (x) >> (n) : (x) << -(n))
2572#define VFP_SREG(insn, bigbit, smallbit) \
2573 ((VFP_REG_SHR(insn, bigbit - 1) & 0x1e) | (((insn) >> (smallbit)) & 1))
2574#define VFP_DREG(reg, insn, bigbit, smallbit) do { \
2575 if (arm_feature(env, ARM_FEATURE_VFP3)) { \
2576 reg = (((insn) >> (bigbit)) & 0x0f) \
2577 | (((insn) >> ((smallbit) - 4)) & 0x10); \
2578 } else { \
2579 if (insn & (1 << (smallbit))) \
2580 return 1; \
2581 reg = ((insn) >> (bigbit)) & 0x0f; \
2582 }} while (0)
2583
2584#define VFP_SREG_D(insn) VFP_SREG(insn, 12, 22)
2585#define VFP_DREG_D(reg, insn) VFP_DREG(reg, insn, 12, 22)
2586#define VFP_SREG_N(insn) VFP_SREG(insn, 16, 7)
2587#define VFP_DREG_N(reg, insn) VFP_DREG(reg, insn, 16, 7)
2588#define VFP_SREG_M(insn) VFP_SREG(insn, 0, 5)
2589#define VFP_DREG_M(reg, insn) VFP_DREG(reg, insn, 0, 5)
2590
4373f3ce
PB		 2591/* Move between integer and VFP cores. */
2592static TCGv gen_vfp_mrs(void)
2593{
2594 TCGv tmp = new_tmp();
2595 tcg_gen_mov_i32(tmp, cpu_F0s);
2596 return tmp;
2597}
2598
2599static void gen_vfp_msr(TCGv tmp)
2600{
2601 tcg_gen_mov_i32(cpu_F0s, tmp);
2602 dead_tmp(tmp);
2603}
2604
9ee6e8bb
PB		 2605static inline int
2606vfp_enabled(CPUState * env)
2607{
2608 return ((env->vfp.xregs[ARM_VFP_FPEXC] & (1 << 30)) != 0);
2609}
2610
ad69471c
PB		 2611static void gen_neon_dup_u8(TCGv var, int shift)
2612{
2613 TCGv tmp = new_tmp();
2614 if (shift)
2615 tcg_gen_shri_i32(var, var, shift);
86831435 2616 tcg_gen_ext8u_i32(var, var);
ad69471c
PB		 2617 tcg_gen_shli_i32(tmp, var, 8);
2618 tcg_gen_or_i32(var, var, tmp);
2619 tcg_gen_shli_i32(tmp, var, 16);
2620 tcg_gen_or_i32(var, var, tmp);
2621 dead_tmp(tmp);
2622}
2623
2624static void gen_neon_dup_low16(TCGv var)
2625{
2626 TCGv tmp = new_tmp();
86831435 2627 tcg_gen_ext16u_i32(var, var);
ad69471c
PB		 2628 tcg_gen_shli_i32(tmp, var, 16);
2629 tcg_gen_or_i32(var, var, tmp);
2630 dead_tmp(tmp);
2631}
2632
2633static void gen_neon_dup_high16(TCGv var)
2634{
2635 TCGv tmp = new_tmp();
2636 tcg_gen_andi_i32(var, var, 0xffff0000);
2637 tcg_gen_shri_i32(tmp, var, 16);
2638 tcg_gen_or_i32(var, var, tmp);
2639 dead_tmp(tmp);
2640}
2641
b7bcbe95
FB		 2642/* Disassemble a VFP instruction. Returns nonzero if an error occured
2643 (ie. an undefined instruction). */
2644static int disas_vfp_insn(CPUState * env, DisasContext *s, uint32_t insn)
2645{
2646 uint32_t rd, rn, rm, op, i, n, offset, delta_d, delta_m, bank_mask;
2647 int dp, veclen;
312eea9f 2648 TCGv addr;
4373f3ce 2649 TCGv tmp;
ad69471c 2650 TCGv tmp2;
b7bcbe95 2651
40f137e1
PB		 2652 if (!arm_feature(env, ARM_FEATURE_VFP))
2653 return 1;
2654
9ee6e8bb
PB		 2655 if (!vfp_enabled(env)) {
2656 /* VFP disabled. Only allow fmxr/fmrx to/from some control regs. */
40f137e1
PB		 2657 if ((insn & 0x0fe00fff) != 0x0ee00a10)
2658 return 1;
2659 rn = (insn >> 16) & 0xf;
9ee6e8bb
PB		 2660 if (rn != ARM_VFP_FPSID && rn != ARM_VFP_FPEXC
2661 && rn != ARM_VFP_MVFR1 && rn != ARM_VFP_MVFR0)
40f137e1
PB		 2662 return 1;
2663 }
b7bcbe95
FB		 2664 dp = ((insn & 0xf00) == 0xb00);
2665 switch ((insn >> 24) & 0xf) {
2666 case 0xe:
2667 if (insn & (1 << 4)) {
2668 /* single register transfer */
b7bcbe95
FB		 2669 rd = (insn >> 12) & 0xf;
2670 if (dp) {
9ee6e8bb
PB		 2671 int size;
2672 int pass;
2673
2674 VFP_DREG_N(rn, insn);
2675 if (insn & 0xf)
b7bcbe95 2676 return 1;
9ee6e8bb
PB		 2677 if (insn & 0x00c00060
2678 && !arm_feature(env, ARM_FEATURE_NEON))
2679 return 1;
2680
2681 pass = (insn >> 21) & 1;
2682 if (insn & (1 << 22)) {
2683 size = 0;
2684 offset = ((insn >> 5) & 3) * 8;
2685 } else if (insn & (1 << 5)) {
2686 size = 1;
2687 offset = (insn & (1 << 6)) ? 16 : 0;
2688 } else {
2689 size = 2;
2690 offset = 0;
2691 }
18c9b560 2692 if (insn & ARM_CP_RW_BIT) {
b7bcbe95 2693 /* vfp->arm */
ad69471c 2694 tmp = neon_load_reg(rn, pass);
9ee6e8bb
PB		 2695 switch (size) {
2696 case 0:
9ee6e8bb 2697 if (offset)
ad69471c 2698 tcg_gen_shri_i32(tmp, tmp, offset);
9ee6e8bb 2699 if (insn & (1 << 23))
ad69471c 2700 gen_uxtb(tmp);
9ee6e8bb 2701 else
ad69471c 2702 gen_sxtb(tmp);
9ee6e8bb
PB		 2703 break;
2704 case 1:
9ee6e8bb
PB		 2705 if (insn & (1 << 23)) {
2706 if (offset) {
ad69471c 2707 tcg_gen_shri_i32(tmp, tmp, 16);
9ee6e8bb 2708 } else {
ad69471c 2709 gen_uxth(tmp);
9ee6e8bb
PB		 2710 }
2711 } else {
2712 if (offset) {
ad69471c 2713 tcg_gen_sari_i32(tmp, tmp, 16);
9ee6e8bb 2714 } else {
ad69471c 2715 gen_sxth(tmp);
9ee6e8bb
PB		 2716 }
2717 }
2718 break;
2719 case 2:
9ee6e8bb
PB		 2720 break;
2721 }
ad69471c 2722 store_reg(s, rd, tmp);
b7bcbe95
FB		 2723 } else {
2724 /* arm->vfp */
ad69471c 2725 tmp = load_reg(s, rd);
9ee6e8bb
PB		 2726 if (insn & (1 << 23)) {
2727 /* VDUP */
2728 if (size == 0) {
ad69471c 2729 gen_neon_dup_u8(tmp, 0);
9ee6e8bb 2730 } else if (size == 1) {
ad69471c 2731 gen_neon_dup_low16(tmp);
9ee6e8bb 2732 }
cbbccffc
PB		 2733 for (n = 0; n <= pass * 2; n++) {
2734 tmp2 = new_tmp();
2735 tcg_gen_mov_i32(tmp2, tmp);
2736 neon_store_reg(rn, n, tmp2);
2737 }
2738 neon_store_reg(rn, n, tmp);
9ee6e8bb
PB		 2739 } else {
2740 /* VMOV */
2741 switch (size) {
2742 case 0:
ad69471c
PB		 2743 tmp2 = neon_load_reg(rn, pass);
2744 gen_bfi(tmp, tmp2, tmp, offset, 0xff);
2745 dead_tmp(tmp2);
9ee6e8bb
PB		 2746 break;
2747 case 1:
ad69471c
PB		 2748 tmp2 = neon_load_reg(rn, pass);
2749 gen_bfi(tmp, tmp2, tmp, offset, 0xffff);
2750 dead_tmp(tmp2);
9ee6e8bb
PB		 2751 break;
2752 case 2:
9ee6e8bb
PB		 2753 break;
2754 }
ad69471c 2755 neon_store_reg(rn, pass, tmp);
9ee6e8bb 2756 }
b7bcbe95 2757 }
9ee6e8bb
PB		 2758 } else { /* !dp */
2759 if ((insn & 0x6f) != 0x00)
2760 return 1;
2761 rn = VFP_SREG_N(insn);
18c9b560 2762 if (insn & ARM_CP_RW_BIT) {
b7bcbe95
FB		 2763 /* vfp->arm */
2764 if (insn & (1 << 21)) {
2765 /* system register */
40f137e1 2766 rn >>= 1;
9ee6e8bb 2767
b7bcbe95 2768 switch (rn) {
40f137e1 2769 case ARM_VFP_FPSID:
4373f3ce 2770 /* VFP2 allows access to FSID from userspace.
9ee6e8bb
PB		 2771 VFP3 restricts all id registers to privileged
2772 accesses. */
2773 if (IS_USER(s)
2774 && arm_feature(env, ARM_FEATURE_VFP3))
2775 return 1;
4373f3ce 2776 tmp = load_cpu_field(vfp.xregs[rn]);
9ee6e8bb 2777 break;
40f137e1 2778 case ARM_VFP_FPEXC:
9ee6e8bb
PB		 2779 if (IS_USER(s))
2780 return 1;
4373f3ce 2781 tmp = load_cpu_field(vfp.xregs[rn]);
9ee6e8bb 2782 break;
40f137e1
PB		 2783 case ARM_VFP_FPINST:
2784 case ARM_VFP_FPINST2:
9ee6e8bb
PB		 2785 /* Not present in VFP3. */
2786 if (IS_USER(s)
2787 || arm_feature(env, ARM_FEATURE_VFP3))
2788 return 1;
4373f3ce 2789 tmp = load_cpu_field(vfp.xregs[rn]);
b7bcbe95 2790 break;
40f137e1 2791 case ARM_VFP_FPSCR:
601d70b9 2792 if (rd == 15) {
4373f3ce
PB		 2793 tmp = load_cpu_field(vfp.xregs[ARM_VFP_FPSCR]);
2794 tcg_gen_andi_i32(tmp, tmp, 0xf0000000);
2795 } else {
2796 tmp = new_tmp();
2797 gen_helper_vfp_get_fpscr(tmp, cpu_env);
2798 }
b7bcbe95 2799 break;
9ee6e8bb
PB		 2800 case ARM_VFP_MVFR0:
2801 case ARM_VFP_MVFR1:
2802 if (IS_USER(s)
2803 || !arm_feature(env, ARM_FEATURE_VFP3))
2804 return 1;
4373f3ce 2805 tmp = load_cpu_field(vfp.xregs[rn]);
9ee6e8bb 2806 break;
b7bcbe95
FB		 2807 default:
2808 return 1;
2809 }
2810 } else {
2811 gen_mov_F0_vreg(0, rn);
4373f3ce 2812 tmp = gen_vfp_mrs();
b7bcbe95
FB		 2813 }
2814 if (rd == 15) {
b5ff1b31 2815 /* Set the 4 flag bits in the CPSR. */
4373f3ce
PB		 2816 gen_set_nzcv(tmp);
2817 dead_tmp(tmp);
2818 } else {
2819 store_reg(s, rd, tmp);
2820 }
b7bcbe95
FB		 2821 } else {
2822 /* arm->vfp */
4373f3ce 2823 tmp = load_reg(s, rd);
b7bcbe95 2824 if (insn & (1 << 21)) {
40f137e1 2825 rn >>= 1;
b7bcbe95
FB		 2826 /* system register */
2827 switch (rn) {
40f137e1 2828 case ARM_VFP_FPSID:
9ee6e8bb
PB		 2829 case ARM_VFP_MVFR0:
2830 case ARM_VFP_MVFR1:
b7bcbe95
FB		 2831 /* Writes are ignored. */
2832 break;
40f137e1 2833 case ARM_VFP_FPSCR:
4373f3ce
PB		 2834 gen_helper_vfp_set_fpscr(cpu_env, tmp);
2835 dead_tmp(tmp);
b5ff1b31 2836 gen_lookup_tb(s);
b7bcbe95 2837 break;
40f137e1 2838 case ARM_VFP_FPEXC:
9ee6e8bb
PB		 2839 if (IS_USER(s))
2840 return 1;
71b3c3de
JR		 2841 /* TODO: VFP subarchitecture support.
2842 * For now, keep the EN bit only */
2843 tcg_gen_andi_i32(tmp, tmp, 1 << 30);
4373f3ce 2844 store_cpu_field(tmp, vfp.xregs[rn]);
40f137e1
PB		 2845 gen_lookup_tb(s);
2846 break;
2847 case ARM_VFP_FPINST:
2848 case ARM_VFP_FPINST2:
4373f3ce 2849 store_cpu_field(tmp, vfp.xregs[rn]);
40f137e1 2850 break;
b7bcbe95
FB		 2851 default:
2852 return 1;
2853 }
2854 } else {
4373f3ce 2855 gen_vfp_msr(tmp);
b7bcbe95
FB		 2856 gen_mov_vreg_F0(0, rn);
2857 }
2858 }
2859 }
2860 } else {
2861 /* data processing */
2862 /* The opcode is in bits 23, 21, 20 and 6. */
2863 op = ((insn >> 20) & 8) | ((insn >> 19) & 6) | ((insn >> 6) & 1);
2864 if (dp) {
2865 if (op == 15) {
2866 /* rn is opcode */
2867 rn = ((insn >> 15) & 0x1e) | ((insn >> 7) & 1);
2868 } else {
2869 /* rn is register number */
9ee6e8bb 2870 VFP_DREG_N(rn, insn);
b7bcbe95
FB		 2871 }
2872
04595bf6 2873 if (op == 15 && (rn == 15 || ((rn & 0x1c) == 0x18))) {
b7bcbe95 2874 /* Integer or single precision destination. */
9ee6e8bb 2875 rd = VFP_SREG_D(insn);
b7bcbe95 2876 } else {
9ee6e8bb 2877 VFP_DREG_D(rd, insn);
b7bcbe95 2878 }
04595bf6
PM		 2879 if (op == 15 &&
2880 (((rn & 0x1c) == 0x10) || ((rn & 0x14) == 0x14))) {
2881 /* VCVT from int is always from S reg regardless of dp bit.
2882 * VCVT with immediate frac_bits has same format as SREG_M
2883 */
2884 rm = VFP_SREG_M(insn);
b7bcbe95 2885 } else {
9ee6e8bb 2886 VFP_DREG_M(rm, insn);
b7bcbe95
FB		 2887 }
2888 } else {
9ee6e8bb 2889 rn = VFP_SREG_N(insn);
b7bcbe95
FB		 2890 if (op == 15 && rn == 15) {
2891 /* Double precision destination. */
9ee6e8bb
PB		 2892 VFP_DREG_D(rd, insn);
2893 } else {
2894 rd = VFP_SREG_D(insn);
2895 }
04595bf6
PM		 2896 /* NB that we implicitly rely on the encoding for the frac_bits
2897 * in VCVT of fixed to float being the same as that of an SREG_M
2898 */
9ee6e8bb 2899 rm = VFP_SREG_M(insn);
b7bcbe95
FB		 2900 }
2901
2902 veclen = env->vfp.vec_len;
2903 if (op == 15 && rn > 3)
2904 veclen = 0;
2905
2906 /* Shut up compiler warnings. */
2907 delta_m = 0;
2908 delta_d = 0;
2909 bank_mask = 0;
3b46e624 2910
b7bcbe95
FB		 2911 if (veclen > 0) {
2912 if (dp)
2913 bank_mask = 0xc;
2914 else
2915 bank_mask = 0x18;
2916
2917 /* Figure out what type of vector operation this is. */
2918 if ((rd & bank_mask) == 0) {
2919 /* scalar */
2920 veclen = 0;
2921 } else {
2922 if (dp)
2923 delta_d = (env->vfp.vec_stride >> 1) + 1;
2924 else
2925 delta_d = env->vfp.vec_stride + 1;
2926
2927 if ((rm & bank_mask) == 0) {
2928 /* mixed scalar/vector */
2929 delta_m = 0;
2930 } else {
2931 /* vector */
2932 delta_m = delta_d;
2933 }
2934 }
2935 }
2936
2937 /* Load the initial operands. */
2938 if (op == 15) {
2939 switch (rn) {
2940 case 16:
2941 case 17:
2942 /* Integer source */
2943 gen_mov_F0_vreg(0, rm);
2944 break;
2945 case 8:
2946 case 9:
2947 /* Compare */
2948 gen_mov_F0_vreg(dp, rd);
2949 gen_mov_F1_vreg(dp, rm);
2950 break;
2951 case 10:
2952 case 11:
2953 /* Compare with zero */
2954 gen_mov_F0_vreg(dp, rd);
2955 gen_vfp_F1_ld0(dp);
2956 break;
9ee6e8bb
PB		 2957 case 20:
2958 case 21:
2959 case 22:
2960 case 23:
644ad806
PB		 2961 case 28:
2962 case 29:
2963 case 30:
2964 case 31:
9ee6e8bb
PB		 2965 /* Source and destination the same. */
2966 gen_mov_F0_vreg(dp, rd);
2967 break;
b7bcbe95
FB		 2968 default:
2969 /* One source operand. */
2970 gen_mov_F0_vreg(dp, rm);
9ee6e8bb 2971 break;
b7bcbe95
FB		 2972 }
2973 } else {
2974 /* Two source operands. */
2975 gen_mov_F0_vreg(dp, rn);
2976 gen_mov_F1_vreg(dp, rm);
2977 }
2978
2979 for (;;) {
2980 /* Perform the calculation. */
2981 switch (op) {
2982 case 0: /* mac: fd + (fn * fm) */
2983 gen_vfp_mul(dp);
2984 gen_mov_F1_vreg(dp, rd);
2985 gen_vfp_add(dp);
2986 break;
2987 case 1: /* nmac: fd - (fn * fm) */
2988 gen_vfp_mul(dp);
2989 gen_vfp_neg(dp);
2990 gen_mov_F1_vreg(dp, rd);
2991 gen_vfp_add(dp);
2992 break;
2993 case 2: /* msc: -fd + (fn * fm) */
2994 gen_vfp_mul(dp);
2995 gen_mov_F1_vreg(dp, rd);
2996 gen_vfp_sub(dp);
2997 break;
2998 case 3: /* nmsc: -fd - (fn * fm) */
2999 gen_vfp_mul(dp);
b7bcbe95 3000 gen_vfp_neg(dp);
c9fb531a
PB		 3001 gen_mov_F1_vreg(dp, rd);
3002 gen_vfp_sub(dp);
b7bcbe95
FB		 3003 break;
3004 case 4: /* mul: fn * fm */
3005 gen_vfp_mul(dp);
3006 break;
3007 case 5: /* nmul: -(fn * fm) */
3008 gen_vfp_mul(dp);
3009 gen_vfp_neg(dp);
3010 break;
3011 case 6: /* add: fn + fm */
3012 gen_vfp_add(dp);
3013 break;
3014 case 7: /* sub: fn - fm */
3015 gen_vfp_sub(dp);
3016 break;
3017 case 8: /* div: fn / fm */
3018 gen_vfp_div(dp);
3019 break;
9ee6e8bb
PB		 3020 case 14: /* fconst */
3021 if (!arm_feature(env, ARM_FEATURE_VFP3))
3022 return 1;
3023
3024 n = (insn << 12) & 0x80000000;
3025 i = ((insn >> 12) & 0x70) | (insn & 0xf);
3026 if (dp) {
3027 if (i & 0x40)
3028 i |= 0x3f80;
3029 else
3030 i |= 0x4000;
3031 n |= i << 16;
4373f3ce 3032 tcg_gen_movi_i64(cpu_F0d, ((uint64_t)n) << 32);
9ee6e8bb
PB		 3033 } else {
3034 if (i & 0x40)
3035 i |= 0x780;
3036 else
3037 i |= 0x800;
3038 n |= i << 19;
5b340b51 3039 tcg_gen_movi_i32(cpu_F0s, n);
9ee6e8bb 3040 }
9ee6e8bb 3041 break;
b7bcbe95
FB		 3042 case 15: /* extension space */
3043 switch (rn) {
3044 case 0: /* cpy */
3045 /* no-op */
3046 break;
3047 case 1: /* abs */
3048 gen_vfp_abs(dp);
3049 break;
3050 case 2: /* neg */
3051 gen_vfp_neg(dp);
3052 break;
3053 case 3: /* sqrt */
3054 gen_vfp_sqrt(dp);
3055 break;
60011498
PB		 3056 case 4: /* vcvtb.f32.f16 */
3057 if (!arm_feature(env, ARM_FEATURE_VFP_FP16))
3058 return 1;
3059 tmp = gen_vfp_mrs();
3060 tcg_gen_ext16u_i32(tmp, tmp);
3061 gen_helper_vfp_fcvt_f16_to_f32(cpu_F0s, tmp, cpu_env);
3062 dead_tmp(tmp);
3063 break;
3064 case 5: /* vcvtt.f32.f16 */
3065 if (!arm_feature(env, ARM_FEATURE_VFP_FP16))
3066 return 1;
3067 tmp = gen_vfp_mrs();
3068 tcg_gen_shri_i32(tmp, tmp, 16);
3069 gen_helper_vfp_fcvt_f16_to_f32(cpu_F0s, tmp, cpu_env);
3070 dead_tmp(tmp);
3071 break;
3072 case 6: /* vcvtb.f16.f32 */
3073 if (!arm_feature(env, ARM_FEATURE_VFP_FP16))
3074 return 1;
3075 tmp = new_tmp();
3076 gen_helper_vfp_fcvt_f32_to_f16(tmp, cpu_F0s, cpu_env);
3077 gen_mov_F0_vreg(0, rd);
3078 tmp2 = gen_vfp_mrs();
3079 tcg_gen_andi_i32(tmp2, tmp2, 0xffff0000);
3080 tcg_gen_or_i32(tmp, tmp, tmp2);
3081 dead_tmp(tmp2);
3082 gen_vfp_msr(tmp);
3083 break;
3084 case 7: /* vcvtt.f16.f32 */
3085 if (!arm_feature(env, ARM_FEATURE_VFP_FP16))
3086 return 1;
3087 tmp = new_tmp();
3088 gen_helper_vfp_fcvt_f32_to_f16(tmp, cpu_F0s, cpu_env);
3089 tcg_gen_shli_i32(tmp, tmp, 16);
3090 gen_mov_F0_vreg(0, rd);
3091 tmp2 = gen_vfp_mrs();
3092 tcg_gen_ext16u_i32(tmp2, tmp2);
3093 tcg_gen_or_i32(tmp, tmp, tmp2);
3094 dead_tmp(tmp2);
3095 gen_vfp_msr(tmp);
3096 break;
b7bcbe95
FB		 3097 case 8: /* cmp */
3098 gen_vfp_cmp(dp);
3099 break;
3100 case 9: /* cmpe */
3101 gen_vfp_cmpe(dp);
3102 break;
3103 case 10: /* cmpz */
3104 gen_vfp_cmp(dp);
3105 break;
3106 case 11: /* cmpez */
3107 gen_vfp_F1_ld0(dp);
3108 gen_vfp_cmpe(dp);
3109 break;
3110 case 15: /* single<->double conversion */
3111 if (dp)
4373f3ce 3112 gen_helper_vfp_fcvtsd(cpu_F0s, cpu_F0d, cpu_env);
b7bcbe95 3113 else
4373f3ce 3114 gen_helper_vfp_fcvtds(cpu_F0d, cpu_F0s, cpu_env);
b7bcbe95
FB		 3115 break;
3116 case 16: /* fuito */
3117 gen_vfp_uito(dp);
3118 break;
3119 case 17: /* fsito */
3120 gen_vfp_sito(dp);
3121 break;
9ee6e8bb
PB		 3122 case 20: /* fshto */
3123 if (!arm_feature(env, ARM_FEATURE_VFP3))
3124 return 1;
644ad806 3125 gen_vfp_shto(dp, 16 - rm);
9ee6e8bb
PB		 3126 break;
3127 case 21: /* fslto */
3128 if (!arm_feature(env, ARM_FEATURE_VFP3))
3129 return 1;
644ad806 3130 gen_vfp_slto(dp, 32 - rm);
9ee6e8bb
PB		 3131 break;
3132 case 22: /* fuhto */
3133 if (!arm_feature(env, ARM_FEATURE_VFP3))
3134 return 1;
644ad806 3135 gen_vfp_uhto(dp, 16 - rm);
9ee6e8bb
PB		 3136 break;
3137 case 23: /* fulto */
3138 if (!arm_feature(env, ARM_FEATURE_VFP3))
3139 return 1;
644ad806 3140 gen_vfp_ulto(dp, 32 - rm);
9ee6e8bb 3141 break;
b7bcbe95
FB		 3142 case 24: /* ftoui */
3143 gen_vfp_toui(dp);
3144 break;
3145 case 25: /* ftouiz */
3146 gen_vfp_touiz(dp);
3147 break;
3148 case 26: /* ftosi */
3149 gen_vfp_tosi(dp);
3150 break;
3151 case 27: /* ftosiz */
3152 gen_vfp_tosiz(dp);
3153 break;
9ee6e8bb
PB		 3154 case 28: /* ftosh */
3155 if (!arm_feature(env, ARM_FEATURE_VFP3))
3156 return 1;
644ad806 3157 gen_vfp_tosh(dp, 16 - rm);
9ee6e8bb
PB		 3158 break;
3159 case 29: /* ftosl */
3160 if (!arm_feature(env, ARM_FEATURE_VFP3))
3161 return 1;
644ad806 3162 gen_vfp_tosl(dp, 32 - rm);
9ee6e8bb
PB		 3163 break;
3164 case 30: /* ftouh */
3165 if (!arm_feature(env, ARM_FEATURE_VFP3))
3166 return 1;
644ad806 3167 gen_vfp_touh(dp, 16 - rm);
9ee6e8bb
PB		 3168 break;
3169 case 31: /* ftoul */
3170 if (!arm_feature(env, ARM_FEATURE_VFP3))
3171 return 1;
644ad806 3172 gen_vfp_toul(dp, 32 - rm);
9ee6e8bb 3173 break;
b7bcbe95
FB		 3174 default: /* undefined */
3175 printf ("rn:%d\n", rn);
3176 return 1;
3177 }
3178 break;
3179 default: /* undefined */
3180 printf ("op:%d\n", op);
3181 return 1;
3182 }
3183
3184 /* Write back the result. */
3185 if (op == 15 && (rn >= 8 && rn <= 11))
3186 ; /* Comparison, do nothing. */
04595bf6
PM		 3187 else if (op == 15 && dp && ((rn & 0x1c) == 0x18))
3188 /* VCVT double to int: always integer result. */
b7bcbe95
FB		 3189 gen_mov_vreg_F0(0, rd);
3190 else if (op == 15 && rn == 15)
3191 /* conversion */
3192 gen_mov_vreg_F0(!dp, rd);
3193 else
3194 gen_mov_vreg_F0(dp, rd);
3195
3196 /* break out of the loop if we have finished */
3197 if (veclen == 0)
3198 break;
3199
3200 if (op == 15 && delta_m == 0) {
3201 /* single source one-many */
3202 while (veclen--) {
3203 rd = ((rd + delta_d) & (bank_mask - 1))
3204 | (rd & bank_mask);
3205 gen_mov_vreg_F0(dp, rd);
3206 }
3207 break;
3208 }
3209 /* Setup the next operands. */
3210 veclen--;
3211 rd = ((rd + delta_d) & (bank_mask - 1))
3212 | (rd & bank_mask);
3213
3214 if (op == 15) {
3215 /* One source operand. */
3216 rm = ((rm + delta_m) & (bank_mask - 1))
3217 | (rm & bank_mask);
3218 gen_mov_F0_vreg(dp, rm);
3219 } else {
3220 /* Two source operands. */
3221 rn = ((rn + delta_d) & (bank_mask - 1))
3222 | (rn & bank_mask);
3223 gen_mov_F0_vreg(dp, rn);
3224 if (delta_m) {
3225 rm = ((rm + delta_m) & (bank_mask - 1))
3226 | (rm & bank_mask);
3227 gen_mov_F1_vreg(dp, rm);
3228 }
3229 }
3230 }
3231 }
3232 break;
3233 case 0xc:
3234 case 0xd:
9ee6e8bb 3235 if (dp && (insn & 0x03e00000) == 0x00400000) {
b7bcbe95
FB		 3236 /* two-register transfer */
3237 rn = (insn >> 16) & 0xf;
3238 rd = (insn >> 12) & 0xf;
3239 if (dp) {
9ee6e8bb
PB		 3240 VFP_DREG_M(rm, insn);
3241 } else {
3242 rm = VFP_SREG_M(insn);
3243 }
b7bcbe95 3244
18c9b560 3245 if (insn & ARM_CP_RW_BIT) {
b7bcbe95
FB		 3246 /* vfp->arm */
3247 if (dp) {
4373f3ce
PB		 3248 gen_mov_F0_vreg(0, rm * 2);
3249 tmp = gen_vfp_mrs();
3250 store_reg(s, rd, tmp);
3251 gen_mov_F0_vreg(0, rm * 2 + 1);
3252 tmp = gen_vfp_mrs();
3253 store_reg(s, rn, tmp);
b7bcbe95
FB		 3254 } else {
3255 gen_mov_F0_vreg(0, rm);
4373f3ce
PB		 3256 tmp = gen_vfp_mrs();
3257 store_reg(s, rn, tmp);
b7bcbe95 3258 gen_mov_F0_vreg(0, rm + 1);
4373f3ce
PB		 3259 tmp = gen_vfp_mrs();
3260 store_reg(s, rd, tmp);
b7bcbe95
FB		 3261 }
3262 } else {
3263 /* arm->vfp */
3264 if (dp) {
4373f3ce
PB		 3265 tmp = load_reg(s, rd);
3266 gen_vfp_msr(tmp);
3267 gen_mov_vreg_F0(0, rm * 2);
3268 tmp = load_reg(s, rn);
3269 gen_vfp_msr(tmp);
3270 gen_mov_vreg_F0(0, rm * 2 + 1);
b7bcbe95 3271 } else {
4373f3ce
PB		 3272 tmp = load_reg(s, rn);
3273 gen_vfp_msr(tmp);
b7bcbe95 3274 gen_mov_vreg_F0(0, rm);
4373f3ce
PB		 3275 tmp = load_reg(s, rd);
3276 gen_vfp_msr(tmp);
b7bcbe95
FB		 3277 gen_mov_vreg_F0(0, rm + 1);
3278 }
3279 }
3280 } else {
3281 /* Load/store */
3282 rn = (insn >> 16) & 0xf;
3283 if (dp)
9ee6e8bb 3284 VFP_DREG_D(rd, insn);
b7bcbe95 3285 else
9ee6e8bb
PB		 3286 rd = VFP_SREG_D(insn);
3287 if (s->thumb && rn == 15) {
312eea9f
FN		 3288 addr = new_tmp();
3289 tcg_gen_movi_i32(addr, s->pc & ~2);
9ee6e8bb 3290 } else {
312eea9f 3291 addr = load_reg(s, rn);
9ee6e8bb 3292 }
b7bcbe95
FB		 3293 if ((insn & 0x01200000) == 0x01000000) {
3294 /* Single load/store */
3295 offset = (insn & 0xff) << 2;
3296 if ((insn & (1 << 23)) == 0)
3297 offset = -offset;
312eea9f 3298 tcg_gen_addi_i32(addr, addr, offset);
b7bcbe95 3299 if (insn & (1 << 20)) {
312eea9f 3300 gen_vfp_ld(s, dp, addr);
b7bcbe95
FB		 3301 gen_mov_vreg_F0(dp, rd);
3302 } else {
3303 gen_mov_F0_vreg(dp, rd);
312eea9f 3304 gen_vfp_st(s, dp, addr);
b7bcbe95 3305 }
312eea9f 3306 dead_tmp(addr);
b7bcbe95
FB		 3307 } else {
3308 /* load/store multiple */
3309 if (dp)
3310 n = (insn >> 1) & 0x7f;
3311 else
3312 n = insn & 0xff;
3313
3314 if (insn & (1 << 24)) /* pre-decrement */
312eea9f 3315 tcg_gen_addi_i32(addr, addr, -((insn & 0xff) << 2));
b7bcbe95
FB		 3316
3317 if (dp)
3318 offset = 8;
3319 else
3320 offset = 4;
3321 for (i = 0; i < n; i++) {
18c9b560 3322 if (insn & ARM_CP_RW_BIT) {
b7bcbe95 3323 /* load */
312eea9f 3324 gen_vfp_ld(s, dp, addr);
b7bcbe95
FB		 3325 gen_mov_vreg_F0(dp, rd + i);
3326 } else {
3327 /* store */
3328 gen_mov_F0_vreg(dp, rd + i);
312eea9f 3329 gen_vfp_st(s, dp, addr);
b7bcbe95 3330 }
312eea9f 3331 tcg_gen_addi_i32(addr, addr, offset);
b7bcbe95
FB		 3332 }
3333 if (insn & (1 << 21)) {
3334 /* writeback */
3335 if (insn & (1 << 24))
3336 offset = -offset * n;
3337 else if (dp && (insn & 1))
3338 offset = 4;
3339 else
3340 offset = 0;
3341
3342 if (offset != 0)
312eea9f
FN		 3343 tcg_gen_addi_i32(addr, addr, offset);
3344 store_reg(s, rn, addr);
3345 } else {
3346 dead_tmp(addr);
b7bcbe95
FB		 3347 }
3348 }
3349 }
3350 break;
3351 default:
3352 /* Should never happen. */
3353 return 1;
3354 }
3355 return 0;
3356}
3357
6e256c93 3358static inline void gen_goto_tb(DisasContext *s, int n, uint32_t dest)
c53be334 3359{
6e256c93
FB		 3360 TranslationBlock *tb;
3361
3362 tb = s->tb;
3363 if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK)) {
57fec1fe 3364 tcg_gen_goto_tb(n);
8984bd2e 3365 gen_set_pc_im(dest);
57fec1fe 3366 tcg_gen_exit_tb((long)tb + n);
6e256c93 3367 } else {
8984bd2e 3368 gen_set_pc_im(dest);
57fec1fe 3369 tcg_gen_exit_tb(0);
6e256c93 3370 }
c53be334
FB		 3371}
3372
8aaca4c0
FB		 3373static inline void gen_jmp (DisasContext *s, uint32_t dest)
3374{
551bd27f 3375 if (unlikely(s->singlestep_enabled)) {
8aaca4c0 3376 /* An indirect jump so that we still trigger the debug exception. */
5899f386 3377 if (s->thumb)
d9ba4830
PB		 3378 dest |= 1;
3379 gen_bx_im(s, dest);
8aaca4c0 3380 } else {
6e256c93 3381 gen_goto_tb(s, 0, dest);
8aaca4c0
FB		 3382 s->is_jmp = DISAS_TB_JUMP;
3383 }
3384}
3385
d9ba4830 3386static inline void gen_mulxy(TCGv t0, TCGv t1, int x, int y)
b5ff1b31 3387{
ee097184 3388 if (x)
d9ba4830 3389 tcg_gen_sari_i32(t0, t0, 16);
b5ff1b31 3390 else
d9ba4830 3391 gen_sxth(t0);
ee097184 3392 if (y)
d9ba4830 3393 tcg_gen_sari_i32(t1, t1, 16);
b5ff1b31 3394 else
d9ba4830
PB		 3395 gen_sxth(t1);
3396 tcg_gen_mul_i32(t0, t0, t1);
b5ff1b31
FB		 3397}
3398
3399/* Return the mask of PSR bits set by a MSR instruction. */
9ee6e8bb 3400static uint32_t msr_mask(CPUState *env, DisasContext *s, int flags, int spsr) {
b5ff1b31
FB		 3401 uint32_t mask;
3402
3403 mask = 0;
3404 if (flags & (1 << 0))
3405 mask |= 0xff;
3406 if (flags & (1 << 1))
3407 mask |= 0xff00;
3408 if (flags & (1 << 2))
3409 mask |= 0xff0000;
3410 if (flags & (1 << 3))
3411 mask |= 0xff000000;
9ee6e8bb 3412
2ae23e75 3413 /* Mask out undefined bits. */
9ee6e8bb
PB		 3414 mask &= ~CPSR_RESERVED;
3415 if (!arm_feature(env, ARM_FEATURE_V6))
e160c51c 3416 mask &= ~(CPSR_E | CPSR_GE);
9ee6e8bb 3417 if (!arm_feature(env, ARM_FEATURE_THUMB2))
e160c51c 3418 mask &= ~CPSR_IT;
9ee6e8bb 3419 /* Mask out execution state bits. */
2ae23e75 3420 if (!spsr)
e160c51c 3421 mask &= ~CPSR_EXEC;
b5ff1b31
FB		 3422 /* Mask out privileged bits. */
3423 if (IS_USER(s))
9ee6e8bb 3424 mask &= CPSR_USER;
b5ff1b31
FB		 3425 return mask;
3426}
3427
2fbac54b
FN		 3428/* Returns nonzero if access to the PSR is not permitted. Marks t0 as dead. */
3429static int gen_set_psr(DisasContext *s, uint32_t mask, int spsr, TCGv t0)
b5ff1b31 3430{
d9ba4830 3431 TCGv tmp;
b5ff1b31
FB		 3432 if (spsr) {
3433 /* ??? This is also undefined in system mode. */
3434 if (IS_USER(s))
3435 return 1;
d9ba4830
PB		 3436
3437 tmp = load_cpu_field(spsr);
3438 tcg_gen_andi_i32(tmp, tmp, ~mask);
2fbac54b
FN		 3439 tcg_gen_andi_i32(t0, t0, mask);
3440 tcg_gen_or_i32(tmp, tmp, t0);
d9ba4830 3441 store_cpu_field(tmp, spsr);
b5ff1b31 3442 } else {
2fbac54b 3443 gen_set_cpsr(t0, mask);
b5ff1b31 3444 }
2fbac54b 3445 dead_tmp(t0);
b5ff1b31
FB		 3446 gen_lookup_tb(s);
3447 return 0;
3448}
3449
2fbac54b
FN		 3450/* Returns nonzero if access to the PSR is not permitted. */
3451static int gen_set_psr_im(DisasContext *s, uint32_t mask, int spsr, uint32_t val)
3452{
3453 TCGv tmp;
3454 tmp = new_tmp();
3455 tcg_gen_movi_i32(tmp, val);
3456 return gen_set_psr(s, mask, spsr, tmp);
3457}
3458
e9bb4aa9
JR		 3459/* Generate an old-style exception return. Marks pc as dead. */
3460static void gen_exception_return(DisasContext *s, TCGv pc)
b5ff1b31 3461{
d9ba4830 3462 TCGv tmp;
e9bb4aa9 3463 store_reg(s, 15, pc);
d9ba4830
PB		 3464 tmp = load_cpu_field(spsr);
3465 gen_set_cpsr(tmp, 0xffffffff);
3466 dead_tmp(tmp);
b5ff1b31
FB		 3467 s->is_jmp = DISAS_UPDATE;
3468}
3469
b0109805
PB		 3470/* Generate a v6 exception return. Marks both values as dead. */
3471static void gen_rfe(DisasContext *s, TCGv pc, TCGv cpsr)
2c0262af 3472{
b0109805
PB		 3473 gen_set_cpsr(cpsr, 0xffffffff);
3474 dead_tmp(cpsr);
3475 store_reg(s, 15, pc);
9ee6e8bb
PB		 3476 s->is_jmp = DISAS_UPDATE;
3477}
3b46e624 3478
9ee6e8bb
PB		 3479static inline void
3480gen_set_condexec (DisasContext *s)
3481{
3482 if (s->condexec_mask) {
8f01245e
PB		 3483 uint32_t val = (s->condexec_cond << 4) | (s->condexec_mask >> 1);
3484 TCGv tmp = new_tmp();
3485 tcg_gen_movi_i32(tmp, val);
d9ba4830 3486 store_cpu_field(tmp, condexec_bits);
9ee6e8bb
PB		 3487 }
3488}
3b46e624 3489
9ee6e8bb
PB		 3490static void gen_nop_hint(DisasContext *s, int val)
3491{
3492 switch (val) {
3493 case 3: /* wfi */
8984bd2e 3494 gen_set_pc_im(s->pc);
9ee6e8bb
PB		 3495 s->is_jmp = DISAS_WFI;
3496 break;
3497 case 2: /* wfe */
3498 case 4: /* sev */
3499 /* TODO: Implement SEV and WFE. May help SMP performance. */
3500 default: /* nop */
3501 break;
3502 }
3503}
99c475ab 3504
ad69471c 3505#define CPU_V001 cpu_V0, cpu_V0, cpu_V1
9ee6e8bb 3506
dd8fbd78 3507static inline int gen_neon_add(int size, TCGv t0, TCGv t1)
9ee6e8bb
PB		 3508{
3509 switch (size) {
dd8fbd78
FN		 3510 case 0: gen_helper_neon_add_u8(t0, t0, t1); break;
3511 case 1: gen_helper_neon_add_u16(t0, t0, t1); break;
3512 case 2: tcg_gen_add_i32(t0, t0, t1); break;
9ee6e8bb
PB		 3513 default: return 1;
3514 }
3515 return 0;
3516}
3517
dd8fbd78 3518static inline void gen_neon_rsb(int size, TCGv t0, TCGv t1)
ad69471c
PB		 3519{
3520 switch (size) {
dd8fbd78
FN		 3521 case 0: gen_helper_neon_sub_u8(t0, t1, t0); break;
3522 case 1: gen_helper_neon_sub_u16(t0, t1, t0); break;
3523 case 2: tcg_gen_sub_i32(t0, t1, t0); break;
ad69471c
PB		 3524 default: return;
3525 }
3526}
3527
3528/* 32-bit pairwise ops end up the same as the elementwise versions. */
3529#define gen_helper_neon_pmax_s32 gen_helper_neon_max_s32
3530#define gen_helper_neon_pmax_u32 gen_helper_neon_max_u32
3531#define gen_helper_neon_pmin_s32 gen_helper_neon_min_s32
3532#define gen_helper_neon_pmin_u32 gen_helper_neon_min_u32
3533
3534/* FIXME: This is wrong. They set the wrong overflow bit. */
3535#define gen_helper_neon_qadd_s32(a, e, b, c) gen_helper_add_saturate(a, b, c)
3536#define gen_helper_neon_qadd_u32(a, e, b, c) gen_helper_add_usaturate(a, b, c)
3537#define gen_helper_neon_qsub_s32(a, e, b, c) gen_helper_sub_saturate(a, b, c)
3538#define gen_helper_neon_qsub_u32(a, e, b, c) gen_helper_sub_usaturate(a, b, c)
3539
3540#define GEN_NEON_INTEGER_OP_ENV(name) do { \
3541 switch ((size << 1) | u) { \
3542 case 0: \
dd8fbd78 3543 gen_helper_neon_##name##_s8(tmp, cpu_env, tmp, tmp2); \
ad69471c
PB		 3544 break; \
3545 case 1: \
dd8fbd78 3546 gen_helper_neon_##name##_u8(tmp, cpu_env, tmp, tmp2); \
ad69471c
PB		 3547 break; \
3548 case 2: \
dd8fbd78 3549 gen_helper_neon_##name##_s16(tmp, cpu_env, tmp, tmp2); \
ad69471c
PB		 3550 break; \
3551 case 3: \
dd8fbd78 3552 gen_helper_neon_##name##_u16(tmp, cpu_env, tmp, tmp2); \
ad69471c
PB		 3553 break; \
3554 case 4: \
dd8fbd78 3555 gen_helper_neon_##name##_s32(tmp, cpu_env, tmp, tmp2); \
ad69471c
PB		 3556 break; \
3557 case 5: \
dd8fbd78 3558 gen_helper_neon_##name##_u32(tmp, cpu_env, tmp, tmp2); \
ad69471c
PB		 3559 break; \
3560 default: return 1; \
3561 }} while (0)
9ee6e8bb
PB		 3562
3563#define GEN_NEON_INTEGER_OP(name) do { \
3564 switch ((size << 1) | u) { \
ad69471c 3565 case 0: \
dd8fbd78 3566 gen_helper_neon_##name##_s8(tmp, tmp, tmp2); \
ad69471c
PB		 3567 break; \
3568 case 1: \
dd8fbd78 3569 gen_helper_neon_##name##_u8(tmp, tmp, tmp2); \
ad69471c
PB		 3570 break; \
3571 case 2: \
dd8fbd78 3572 gen_helper_neon_##name##_s16(tmp, tmp, tmp2); \
ad69471c
PB		 3573 break; \
3574 case 3: \
dd8fbd78 3575 gen_helper_neon_##name##_u16(tmp, tmp, tmp2); \
ad69471c
PB		 3576 break; \
3577 case 4: \
dd8fbd78 3578 gen_helper_neon_##name##_s32(tmp, tmp, tmp2); \
ad69471c
PB		 3579 break; \
3580 case 5: \
dd8fbd78 3581 gen_helper_neon_##name##_u32(tmp, tmp, tmp2); \
ad69471c 3582 break; \
9ee6e8bb
PB		 3583 default: return 1; \
3584 }} while (0)
3585
dd8fbd78 3586static TCGv neon_load_scratch(int scratch)
9ee6e8bb 3587{
dd8fbd78
FN		 3588 TCGv tmp = new_tmp();
3589 tcg_gen_ld_i32(tmp, cpu_env, offsetof(CPUARMState, vfp.scratch[scratch]));
3590 return tmp;
9ee6e8bb
PB		 3591}
3592
dd8fbd78 3593static void neon_store_scratch(int scratch, TCGv var)
9ee6e8bb 3594{
dd8fbd78
FN		 3595 tcg_gen_st_i32(var, cpu_env, offsetof(CPUARMState, vfp.scratch[scratch]));
3596 dead_tmp(var);
9ee6e8bb
PB		 3597}
3598
dd8fbd78 3599static inline TCGv neon_get_scalar(int size, int reg)
9ee6e8bb 3600{
dd8fbd78 3601 TCGv tmp;
9ee6e8bb 3602 if (size == 1) {
dd8fbd78 3603 tmp = neon_load_reg(reg >> 1, reg & 1);
9ee6e8bb 3604 } else {
dd8fbd78
FN		 3605 tmp = neon_load_reg(reg >> 2, (reg >> 1) & 1);
3606 if (reg & 1) {
3607 gen_neon_dup_low16(tmp);
3608 } else {
3609 gen_neon_dup_high16(tmp);
3610 }
9ee6e8bb 3611 }
dd8fbd78 3612 return tmp;
9ee6e8bb
PB		 3613}
3614
19457615
FN		 3615static void gen_neon_unzip_u8(TCGv t0, TCGv t1)
3616{
3617 TCGv rd, rm, tmp;
3618
3619 rd = new_tmp();
3620 rm = new_tmp();
3621 tmp = new_tmp();
3622
3623 tcg_gen_andi_i32(rd, t0, 0xff);
3624 tcg_gen_shri_i32(tmp, t0, 8);
3625 tcg_gen_andi_i32(tmp, tmp, 0xff00);
3626 tcg_gen_or_i32(rd, rd, tmp);
3627 tcg_gen_shli_i32(tmp, t1, 16);
3628 tcg_gen_andi_i32(tmp, tmp, 0xff0000);
3629 tcg_gen_or_i32(rd, rd, tmp);
3630 tcg_gen_shli_i32(tmp, t1, 8);
3631 tcg_gen_andi_i32(tmp, tmp, 0xff000000);
3632 tcg_gen_or_i32(rd, rd, tmp);
3633
3634 tcg_gen_shri_i32(rm, t0, 8);
3635 tcg_gen_andi_i32(rm, rm, 0xff);
3636 tcg_gen_shri_i32(tmp, t0, 16);
3637 tcg_gen_andi_i32(tmp, tmp, 0xff00);
3638 tcg_gen_or_i32(rm, rm, tmp);
3639 tcg_gen_shli_i32(tmp, t1, 8);
3640 tcg_gen_andi_i32(tmp, tmp, 0xff0000);
3641 tcg_gen_or_i32(rm, rm, tmp);
3642 tcg_gen_andi_i32(tmp, t1, 0xff000000);
3643 tcg_gen_or_i32(t1, rm, tmp);
3644 tcg_gen_mov_i32(t0, rd);
3645
3646 dead_tmp(tmp);
3647 dead_tmp(rm);
3648 dead_tmp(rd);
3649}
3650
3651static void gen_neon_zip_u8(TCGv t0, TCGv t1)
3652{
3653 TCGv rd, rm, tmp;
3654
3655 rd = new_tmp();
3656 rm = new_tmp();
3657 tmp = new_tmp();
3658
3659 tcg_gen_andi_i32(rd, t0, 0xff);
3660 tcg_gen_shli_i32(tmp, t1, 8);
3661 tcg_gen_andi_i32(tmp, tmp, 0xff00);
3662 tcg_gen_or_i32(rd, rd, tmp);
3663 tcg_gen_shli_i32(tmp, t0, 16);
3664 tcg_gen_andi_i32(tmp, tmp, 0xff0000);
3665 tcg_gen_or_i32(rd, rd, tmp);
3666 tcg_gen_shli_i32(tmp, t1, 24);
3667 tcg_gen_andi_i32(tmp, tmp, 0xff000000);
3668 tcg_gen_or_i32(rd, rd, tmp);
3669
3670 tcg_gen_andi_i32(rm, t1, 0xff000000);
3671 tcg_gen_shri_i32(tmp, t0, 8);
3672 tcg_gen_andi_i32(tmp, tmp, 0xff0000);
3673 tcg_gen_or_i32(rm, rm, tmp);
3674 tcg_gen_shri_i32(tmp, t1, 8);
3675 tcg_gen_andi_i32(tmp, tmp, 0xff00);
3676 tcg_gen_or_i32(rm, rm, tmp);
3677 tcg_gen_shri_i32(tmp, t0, 16);
3678 tcg_gen_andi_i32(tmp, tmp, 0xff);
3679 tcg_gen_or_i32(t1, rm, tmp);
3680 tcg_gen_mov_i32(t0, rd);
3681
3682 dead_tmp(tmp);
3683 dead_tmp(rm);
3684 dead_tmp(rd);
3685}
3686
3687static void gen_neon_zip_u16(TCGv t0, TCGv t1)
3688{
3689 TCGv tmp, tmp2;
3690
3691 tmp = new_tmp();
3692 tmp2 = new_tmp();
3693
3694 tcg_gen_andi_i32(tmp, t0, 0xffff);
3695 tcg_gen_shli_i32(tmp2, t1, 16);
3696 tcg_gen_or_i32(tmp, tmp, tmp2);
3697 tcg_gen_andi_i32(t1, t1, 0xffff0000);
3698 tcg_gen_shri_i32(tmp2, t0, 16);
3699 tcg_gen_or_i32(t1, t1, tmp2);
3700 tcg_gen_mov_i32(t0, tmp);
3701
3702 dead_tmp(tmp2);
3703 dead_tmp(tmp);
3704}
3705
9ee6e8bb
PB		 3706static void gen_neon_unzip(int reg, int q, int tmp, int size)
3707{
3708 int n;
dd8fbd78 3709 TCGv t0, t1;
9ee6e8bb
PB		 3710
3711 for (n = 0; n < q + 1; n += 2) {
dd8fbd78
FN		 3712 t0 = neon_load_reg(reg, n);
3713 t1 = neon_load_reg(reg, n + 1);
9ee6e8bb 3714 switch (size) {
dd8fbd78
FN		 3715 case 0: gen_neon_unzip_u8(t0, t1); break;
3716 case 1: gen_neon_zip_u16(t0, t1); break; /* zip and unzip are the same. */
9ee6e8bb
PB		 3717 case 2: /* no-op */; break;
3718 default: abort();
3719 }
dd8fbd78
FN		 3720 neon_store_scratch(tmp + n, t0);
3721 neon_store_scratch(tmp + n + 1, t1);
9ee6e8bb
PB		 3722 }
3723}
3724
19457615
FN		 3725static void gen_neon_trn_u8(TCGv t0, TCGv t1)
3726{
3727 TCGv rd, tmp;
3728
3729 rd = new_tmp();
3730 tmp = new_tmp();
3731
3732 tcg_gen_shli_i32(rd, t0, 8);
3733 tcg_gen_andi_i32(rd, rd, 0xff00ff00);
3734 tcg_gen_andi_i32(tmp, t1, 0x00ff00ff);
3735 tcg_gen_or_i32(rd, rd, tmp);
3736
3737 tcg_gen_shri_i32(t1, t1, 8);
3738 tcg_gen_andi_i32(t1, t1, 0x00ff00ff);
3739 tcg_gen_andi_i32(tmp, t0, 0xff00ff00);
3740 tcg_gen_or_i32(t1, t1, tmp);
3741 tcg_gen_mov_i32(t0, rd);
3742
3743 dead_tmp(tmp);
3744 dead_tmp(rd);
3745}
3746
3747static void gen_neon_trn_u16(TCGv t0, TCGv t1)
3748{
3749 TCGv rd, tmp;
3750
3751 rd = new_tmp();
3752 tmp = new_tmp();
3753
3754 tcg_gen_shli_i32(rd, t0, 16);
3755 tcg_gen_andi_i32(tmp, t1, 0xffff);
3756 tcg_gen_or_i32(rd, rd, tmp);
3757 tcg_gen_shri_i32(t1, t1, 16);
3758 tcg_gen_andi_i32(tmp, t0, 0xffff0000);
3759 tcg_gen_or_i32(t1, t1, tmp);
3760 tcg_gen_mov_i32(t0, rd);
3761
3762 dead_tmp(tmp);
3763 dead_tmp(rd);
3764}
3765
3766
9ee6e8bb
PB		 3767static struct {
3768 int nregs;
3769 int interleave;
3770 int spacing;
3771} neon_ls_element_type[11] = {
3772 {4, 4, 1},
3773 {4, 4, 2},
3774 {4, 1, 1},
3775 {4, 2, 1},
3776 {3, 3, 1},
3777 {3, 3, 2},
3778 {3, 1, 1},
3779 {1, 1, 1},
3780 {2, 2, 1},
3781 {2, 2, 2},
3782 {2, 1, 1}
3783};
3784
3785/* Translate a NEON load/store element instruction. Return nonzero if the
3786 instruction is invalid. */
3787static int disas_neon_ls_insn(CPUState * env, DisasContext *s, uint32_t insn)
3788{
3789 int rd, rn, rm;
3790 int op;
3791 int nregs;
3792 int interleave;
84496233 3793 int spacing;
9ee6e8bb
PB		 3794 int stride;
3795 int size;
3796 int reg;
3797 int pass;
3798 int load;
3799 int shift;
9ee6e8bb 3800 int n;
1b2b1e54 3801 TCGv addr;
b0109805 3802 TCGv tmp;
8f8e3aa4 3803 TCGv tmp2;
84496233 3804 TCGv_i64 tmp64;
9ee6e8bb
PB		 3805
3806 if (!vfp_enabled(env))
3807 return 1;
3808 VFP_DREG_D(rd, insn);
3809 rn = (insn >> 16) & 0xf;
3810 rm = insn & 0xf;
3811 load = (insn & (1 << 21)) != 0;
1b2b1e54 3812 addr = new_tmp();
9ee6e8bb
PB		 3813 if ((insn & (1 << 23)) == 0) {
3814 /* Load store all elements. */
3815 op = (insn >> 8) & 0xf;
3816 size = (insn >> 6) & 3;
84496233 3817 if (op > 10)
9ee6e8bb
PB		 3818 return 1;
3819 nregs = neon_ls_element_type[op].nregs;
3820 interleave = neon_ls_element_type[op].interleave;
84496233
JR		 3821 spacing = neon_ls_element_type[op].spacing;
3822 if (size == 3 && (interleave | spacing) != 1)
3823 return 1;
dcc65026 3824 load_reg_var(s, addr, rn);
9ee6e8bb
PB		 3825 stride = (1 << size) * interleave;
3826 for (reg = 0; reg < nregs; reg++) {
3827 if (interleave > 2 || (interleave == 2 && nregs == 2)) {
dcc65026
AJ		 3828 load_reg_var(s, addr, rn);
3829 tcg_gen_addi_i32(addr, addr, (1 << size) * reg);
9ee6e8bb 3830 } else if (interleave == 2 && nregs == 4 && reg == 2) {
dcc65026
AJ		 3831 load_reg_var(s, addr, rn);
3832 tcg_gen_addi_i32(addr, addr, 1 << size);
9ee6e8bb 3833 }
84496233
JR		 3834 if (size == 3) {
3835 if (load) {
3836 tmp64 = gen_ld64(addr, IS_USER(s));
3837 neon_store_reg64(tmp64, rd);
3838 tcg_temp_free_i64(tmp64);
3839 } else {
3840 tmp64 = tcg_temp_new_i64();
3841 neon_load_reg64(tmp64, rd);
3842 gen_st64(tmp64, addr, IS_USER(s));
3843 }
3844 tcg_gen_addi_i32(addr, addr, stride);
3845 } else {
3846 for (pass = 0; pass < 2; pass++) {
3847 if (size == 2) {
3848 if (load) {
3849 tmp = gen_ld32(addr, IS_USER(s));
3850 neon_store_reg(rd, pass, tmp);
3851 } else {
3852 tmp = neon_load_reg(rd, pass);
3853 gen_st32(tmp, addr, IS_USER(s));
3854 }
1b2b1e54 3855 tcg_gen_addi_i32(addr, addr, stride);
84496233
JR		 3856 } else if (size == 1) {
3857 if (load) {
3858 tmp = gen_ld16u(addr, IS_USER(s));
3859 tcg_gen_addi_i32(addr, addr, stride);
3860 tmp2 = gen_ld16u(addr, IS_USER(s));
3861 tcg_gen_addi_i32(addr, addr, stride);
41ba8341
PB		 3862 tcg_gen_shli_i32(tmp2, tmp2, 16);
3863 tcg_gen_or_i32(tmp, tmp, tmp2);
84496233
JR		 3864 dead_tmp(tmp2);
3865 neon_store_reg(rd, pass, tmp);
3866 } else {
3867 tmp = neon_load_reg(rd, pass);
3868 tmp2 = new_tmp();
3869 tcg_gen_shri_i32(tmp2, tmp, 16);
3870 gen_st16(tmp, addr, IS_USER(s));
3871 tcg_gen_addi_i32(addr, addr, stride);
3872 gen_st16(tmp2, addr, IS_USER(s));
1b2b1e54 3873 tcg_gen_addi_i32(addr, addr, stride);
9ee6e8bb 3874 }
84496233
JR		 3875 } else /* size == 0 */ {
3876 if (load) {
3877 TCGV_UNUSED(tmp2);
3878 for (n = 0; n < 4; n++) {
3879 tmp = gen_ld8u(addr, IS_USER(s));
3880 tcg_gen_addi_i32(addr, addr, stride);
3881 if (n == 0) {
3882 tmp2 = tmp;
3883 } else {
41ba8341
PB		 3884 tcg_gen_shli_i32(tmp, tmp, n * 8);
3885 tcg_gen_or_i32(tmp2, tmp2, tmp);
84496233
JR		 3886 dead_tmp(tmp);
3887 }
9ee6e8bb 3888 }
84496233
JR		 3889 neon_store_reg(rd, pass, tmp2);
3890 } else {
3891 tmp2 = neon_load_reg(rd, pass);
3892 for (n = 0; n < 4; n++) {
3893 tmp = new_tmp();
3894 if (n == 0) {
3895 tcg_gen_mov_i32(tmp, tmp2);
3896 } else {
3897 tcg_gen_shri_i32(tmp, tmp2, n * 8);
3898 }
3899 gen_st8(tmp, addr, IS_USER(s));
3900 tcg_gen_addi_i32(addr, addr, stride);
3901 }
3902 dead_tmp(tmp2);
9ee6e8bb
PB		 3903 }
3904 }
3905 }
3906 }
84496233 3907 rd += spacing;
9ee6e8bb
PB		 3908 }
3909 stride = nregs * 8;
3910 } else {
3911 size = (insn >> 10) & 3;
3912 if (size == 3) {
3913 /* Load single element to all lanes. */
3914 if (!load)
3915 return 1;
3916 size = (insn >> 6) & 3;
3917 nregs = ((insn >> 8) & 3) + 1;
3918 stride = (insn & (1 << 5)) ? 2 : 1;
dcc65026 3919 load_reg_var(s, addr, rn);
9ee6e8bb
PB		 3920 for (reg = 0; reg < nregs; reg++) {
3921 switch (size) {
3922 case 0:
1b2b1e54 3923 tmp = gen_ld8u(addr, IS_USER(s));
ad69471c 3924 gen_neon_dup_u8(tmp, 0);
9ee6e8bb
PB		 3925 break;
3926 case 1:
1b2b1e54 3927 tmp = gen_ld16u(addr, IS_USER(s));
ad69471c 3928 gen_neon_dup_low16(tmp);
9ee6e8bb
PB		 3929 break;
3930 case 2:
1b2b1e54 3931 tmp = gen_ld32(addr, IS_USER(s));
9ee6e8bb
PB		 3932 break;
3933 case 3:
3934 return 1;
a50f5b91
PB		 3935 default: /* Avoid compiler warnings. */
3936 abort();
99c475ab 3937 }
1b2b1e54 3938 tcg_gen_addi_i32(addr, addr, 1 << size);
ad69471c
PB		 3939 tmp2 = new_tmp();
3940 tcg_gen_mov_i32(tmp2, tmp);
3941 neon_store_reg(rd, 0, tmp2);
3018f259 3942 neon_store_reg(rd, 1, tmp);
9ee6e8bb
PB		 3943 rd += stride;
3944 }
3945 stride = (1 << size) * nregs;
3946 } else {
3947 /* Single element. */
3948 pass = (insn >> 7) & 1;
3949 switch (size) {
3950 case 0:
3951 shift = ((insn >> 5) & 3) * 8;
9ee6e8bb
PB		 3952 stride = 1;
3953 break;
3954 case 1:
3955 shift = ((insn >> 6) & 1) * 16;
9ee6e8bb
PB		 3956 stride = (insn & (1 << 5)) ? 2 : 1;
3957 break;
3958 case 2:
3959 shift = 0;
9ee6e8bb
PB		 3960 stride = (insn & (1 << 6)) ? 2 : 1;
3961 break;
3962 default:
3963 abort();
3964 }
3965 nregs = ((insn >> 8) & 3) + 1;
dcc65026 3966 load_reg_var(s, addr, rn);
9ee6e8bb
PB		 3967 for (reg = 0; reg < nregs; reg++) {
3968 if (load) {
9ee6e8bb
PB		 3969 switch (size) {
3970 case 0:
1b2b1e54 3971 tmp = gen_ld8u(addr, IS_USER(s));
9ee6e8bb
PB		 3972 break;
3973 case 1:
1b2b1e54 3974 tmp = gen_ld16u(addr, IS_USER(s));
9ee6e8bb
PB		 3975 break;
3976 case 2:
1b2b1e54 3977 tmp = gen_ld32(addr, IS_USER(s));
9ee6e8bb 3978 break;
a50f5b91
PB		 3979 default: /* Avoid compiler warnings. */
3980 abort();
9ee6e8bb
PB		 3981 }
3982 if (size != 2) {
8f8e3aa4
PB		 3983 tmp2 = neon_load_reg(rd, pass);
3984 gen_bfi(tmp, tmp2, tmp, shift, size ? 0xffff : 0xff);
3985 dead_tmp(tmp2);
9ee6e8bb 3986 }
8f8e3aa4 3987 neon_store_reg(rd, pass, tmp);
9ee6e8bb 3988 } else { /* Store */
8f8e3aa4
PB		 3989 tmp = neon_load_reg(rd, pass);
3990 if (shift)
3991 tcg_gen_shri_i32(tmp, tmp, shift);
9ee6e8bb
PB		 3992 switch (size) {
3993 case 0:
1b2b1e54 3994 gen_st8(tmp, addr, IS_USER(s));
9ee6e8bb
PB		 3995 break;
3996 case 1:
1b2b1e54 3997 gen_st16(tmp, addr, IS_USER(s));
9ee6e8bb
PB		 3998 break;
3999 case 2:
1b2b1e54 4000 gen_st32(tmp, addr, IS_USER(s));
9ee6e8bb 4001 break;
99c475ab 4002 }
99c475ab 4003 }
9ee6e8bb 4004 rd += stride;
1b2b1e54 4005 tcg_gen_addi_i32(addr, addr, 1 << size);
99c475ab 4006 }
9ee6e8bb 4007 stride = nregs * (1 << size);
99c475ab 4008 }
9ee6e8bb 4009 }
1b2b1e54 4010 dead_tmp(addr);
9ee6e8bb 4011 if (rm != 15) {
b26eefb6
PB		 4012 TCGv base;
4013
4014 base = load_reg(s, rn);
9ee6e8bb 4015 if (rm == 13) {
b26eefb6 4016 tcg_gen_addi_i32(base, base, stride);
9ee6e8bb 4017 } else {
b26eefb6
PB		 4018 TCGv index;
4019 index = load_reg(s, rm);
4020 tcg_gen_add_i32(base, base, index);
4021 dead_tmp(index);
9ee6e8bb 4022 }
b26eefb6 4023 store_reg(s, rn, base);
9ee6e8bb
PB		 4024 }
4025 return 0;
4026}
3b46e624 4027
8f8e3aa4
PB		 4028/* Bitwise select. dest = c ? t : f. Clobbers T and F. */
4029static void gen_neon_bsl(TCGv dest, TCGv t, TCGv f, TCGv c)
4030{
4031 tcg_gen_and_i32(t, t, c);
f669df27 4032 tcg_gen_andc_i32(f, f, c);
8f8e3aa4
PB		 4033 tcg_gen_or_i32(dest, t, f);
4034}
4035
a7812ae4 4036static inline void gen_neon_narrow(int size, TCGv dest, TCGv_i64 src)
ad69471c
PB		 4037{
4038 switch (size) {
4039 case 0: gen_helper_neon_narrow_u8(dest, src); break;
4040 case 1: gen_helper_neon_narrow_u16(dest, src); break;
4041 case 2: tcg_gen_trunc_i64_i32(dest, src); break;
4042 default: abort();
4043 }
4044}
4045
a7812ae4 4046static inline void gen_neon_narrow_sats(int size, TCGv dest, TCGv_i64 src)
ad69471c
PB		 4047{
4048 switch (size) {
4049 case 0: gen_helper_neon_narrow_sat_s8(dest, cpu_env, src); break;
4050 case 1: gen_helper_neon_narrow_sat_s16(dest, cpu_env, src); break;
4051 case 2: gen_helper_neon_narrow_sat_s32(dest, cpu_env, src); break;
4052 default: abort();
4053 }
4054}
4055
a7812ae4 4056static inline void gen_neon_narrow_satu(int size, TCGv dest, TCGv_i64 src)
ad69471c
PB		 4057{
4058 switch (size) {
4059 case 0: gen_helper_neon_narrow_sat_u8(dest, cpu_env, src); break;
4060 case 1: gen_helper_neon_narrow_sat_u16(dest, cpu_env, src); break;
4061 case 2: gen_helper_neon_narrow_sat_u32(dest, cpu_env, src); break;
4062 default: abort();
4063 }
4064}
4065
4066static inline void gen_neon_shift_narrow(int size, TCGv var, TCGv shift,
4067 int q, int u)
4068{
4069 if (q) {
4070 if (u) {
4071 switch (size) {
4072 case 1: gen_helper_neon_rshl_u16(var, var, shift); break;
4073 case 2: gen_helper_neon_rshl_u32(var, var, shift); break;
4074 default: abort();
4075 }
4076 } else {
4077 switch (size) {
4078 case 1: gen_helper_neon_rshl_s16(var, var, shift); break;
4079 case 2: gen_helper_neon_rshl_s32(var, var, shift); break;
4080 default: abort();
4081 }
4082 }
4083 } else {
4084 if (u) {
4085 switch (size) {
4086 case 1: gen_helper_neon_rshl_u16(var, var, shift); break;
4087 case 2: gen_helper_neon_rshl_u32(var, var, shift); break;
4088 default: abort();
4089 }
4090 } else {
4091 switch (size) {
4092 case 1: gen_helper_neon_shl_s16(var, var, shift); break;
4093 case 2: gen_helper_neon_shl_s32(var, var, shift); break;
4094 default: abort();
4095 }
4096 }
4097 }
4098}
4099
a7812ae4 4100static inline void gen_neon_widen(TCGv_i64 dest, TCGv src, int size, int u)
ad69471c
PB		 4101{
4102 if (u) {
4103 switch (size) {
4104 case 0: gen_helper_neon_widen_u8(dest, src); break;
4105 case 1: gen_helper_neon_widen_u16(dest, src); break;
4106 case 2: tcg_gen_extu_i32_i64(dest, src); break;
4107 default: abort();
4108 }
4109 } else {
4110 switch (size) {
4111 case 0: gen_helper_neon_widen_s8(dest, src); break;
4112 case 1: gen_helper_neon_widen_s16(dest, src); break;
4113 case 2: tcg_gen_ext_i32_i64(dest, src); break;
4114 default: abort();
4115 }
4116 }
4117 dead_tmp(src);
4118}
4119
4120static inline void gen_neon_addl(int size)
4121{
4122 switch (size) {
4123 case 0: gen_helper_neon_addl_u16(CPU_V001); break;
4124 case 1: gen_helper_neon_addl_u32(CPU_V001); break;
4125 case 2: tcg_gen_add_i64(CPU_V001); break;
4126 default: abort();
4127 }
4128}
4129
4130static inline void gen_neon_subl(int size)
4131{
4132 switch (size) {
4133 case 0: gen_helper_neon_subl_u16(CPU_V001); break;
4134 case 1: gen_helper_neon_subl_u32(CPU_V001); break;
4135 case 2: tcg_gen_sub_i64(CPU_V001); break;
4136 default: abort();
4137 }
4138}
4139
a7812ae4 4140static inline void gen_neon_negl(TCGv_i64 var, int size)
ad69471c
PB		 4141{
4142 switch (size) {
4143 case 0: gen_helper_neon_negl_u16(var, var); break;
4144 case 1: gen_helper_neon_negl_u32(var, var); break;
4145 case 2: gen_helper_neon_negl_u64(var, var); break;
4146 default: abort();
4147 }
4148}
4149
a7812ae4 4150static inline void gen_neon_addl_saturate(TCGv_i64 op0, TCGv_i64 op1, int size)
ad69471c
PB		 4151{
4152 switch (size) {
4153 case 1: gen_helper_neon_addl_saturate_s32(op0, cpu_env, op0, op1); break;
4154 case 2: gen_helper_neon_addl_saturate_s64(op0, cpu_env, op0, op1); break;
4155 default: abort();
4156 }
4157}
4158
a7812ae4 4159static inline void gen_neon_mull(TCGv_i64 dest, TCGv a, TCGv b, int size, int u)
ad69471c 4160{
a7812ae4 4161 TCGv_i64 tmp;
ad69471c
PB		 4162
4163 switch ((size << 1) | u) {
4164 case 0: gen_helper_neon_mull_s8(dest, a, b); break;
4165 case 1: gen_helper_neon_mull_u8(dest, a, b); break;
4166 case 2: gen_helper_neon_mull_s16(dest, a, b); break;
4167 case 3: gen_helper_neon_mull_u16(dest, a, b); break;
4168 case 4:
4169 tmp = gen_muls_i64_i32(a, b);
4170 tcg_gen_mov_i64(dest, tmp);
4171 break;
4172 case 5:
4173 tmp = gen_mulu_i64_i32(a, b);
4174 tcg_gen_mov_i64(dest, tmp);
4175 break;
4176 default: abort();
4177 }
ad69471c
PB		 4178}
4179
9ee6e8bb
PB		 4180/* Translate a NEON data processing instruction. Return nonzero if the
4181 instruction is invalid.
ad69471c
PB		 4182 We process data in a mixture of 32-bit and 64-bit chunks.
4183 Mostly we use 32-bit chunks so we can use normal scalar instructions. */
2c0262af 4184
9ee6e8bb
PB		 4185static int disas_neon_data_insn(CPUState * env, DisasContext *s, uint32_t insn)
4186{
4187 int op;
4188 int q;
4189 int rd, rn, rm;
4190 int size;
4191 int shift;
4192 int pass;
4193 int count;
4194 int pairwise;
4195 int u;
4196 int n;
ca9a32e4 4197 uint32_t imm, mask;
b75263d6 4198 TCGv tmp, tmp2, tmp3, tmp4, tmp5;
a7812ae4 4199 TCGv_i64 tmp64;
9ee6e8bb
PB		 4200
4201 if (!vfp_enabled(env))
4202 return 1;
4203 q = (insn & (1 << 6)) != 0;
4204 u = (insn >> 24) & 1;
4205 VFP_DREG_D(rd, insn);
4206 VFP_DREG_N(rn, insn);
4207 VFP_DREG_M(rm, insn);
4208 size = (insn >> 20) & 3;
4209 if ((insn & (1 << 23)) == 0) {
4210 /* Three register same length. */
4211 op = ((insn >> 7) & 0x1e) | ((insn >> 4) & 1);
ad69471c
PB		 4212 if (size == 3 && (op == 1 || op == 5 || op == 8 || op == 9
4213 || op == 10 || op == 11 || op == 16)) {
4214 /* 64-bit element instructions. */
9ee6e8bb 4215 for (pass = 0; pass < (q ? 2 : 1); pass++) {
ad69471c
PB		 4216 neon_load_reg64(cpu_V0, rn + pass);
4217 neon_load_reg64(cpu_V1, rm + pass);
9ee6e8bb
PB		 4218 switch (op) {
4219 case 1: /* VQADD */
4220 if (u) {
ad69471c 4221 gen_helper_neon_add_saturate_u64(CPU_V001);
2c0262af 4222 } else {
ad69471c 4223 gen_helper_neon_add_saturate_s64(CPU_V001);
2c0262af 4224 }
9ee6e8bb
PB		 4225 break;
4226 case 5: /* VQSUB */
4227 if (u) {
ad69471c
PB		 4228 gen_helper_neon_sub_saturate_u64(CPU_V001);
4229 } else {
4230 gen_helper_neon_sub_saturate_s64(CPU_V001);
4231 }
4232 break;
4233 case 8: /* VSHL */
4234 if (u) {
4235 gen_helper_neon_shl_u64(cpu_V0, cpu_V1, cpu_V0);
4236 } else {
4237 gen_helper_neon_shl_s64(cpu_V0, cpu_V1, cpu_V0);
4238 }
4239 break;
4240 case 9: /* VQSHL */
4241 if (u) {
4242 gen_helper_neon_qshl_u64(cpu_V0, cpu_env,
4243 cpu_V0, cpu_V0);
4244 } else {
4245 gen_helper_neon_qshl_s64(cpu_V1, cpu_env,
4246 cpu_V1, cpu_V0);
4247 }
4248 break;
4249 case 10: /* VRSHL */
4250 if (u) {
4251 gen_helper_neon_rshl_u64(cpu_V0, cpu_V1, cpu_V0);
1e8d4eec 4252 } else {
ad69471c
PB		 4253 gen_helper_neon_rshl_s64(cpu_V0, cpu_V1, cpu_V0);
4254 }
4255 break;
4256 case 11: /* VQRSHL */
4257 if (u) {
4258 gen_helper_neon_qrshl_u64(cpu_V0, cpu_env,
4259 cpu_V1, cpu_V0);
4260 } else {
4261 gen_helper_neon_qrshl_s64(cpu_V0, cpu_env,
4262 cpu_V1, cpu_V0);
1e8d4eec 4263 }
9ee6e8bb
PB		 4264 break;
4265 case 16:
4266 if (u) {
ad69471c 4267 tcg_gen_sub_i64(CPU_V001);
9ee6e8bb 4268 } else {
ad69471c 4269 tcg_gen_add_i64(CPU_V001);
9ee6e8bb
PB		 4270 }
4271 break;
4272 default:
4273 abort();
2c0262af 4274 }
ad69471c 4275 neon_store_reg64(cpu_V0, rd + pass);
2c0262af 4276 }
9ee6e8bb 4277 return 0;
2c0262af 4278 }
9ee6e8bb
PB		 4279 switch (op) {
4280 case 8: /* VSHL */
4281 case 9: /* VQSHL */
4282 case 10: /* VRSHL */
ad69471c 4283 case 11: /* VQRSHL */
9ee6e8bb 4284 {
ad69471c
PB		 4285 int rtmp;
4286 /* Shift instruction operands are reversed. */
4287 rtmp = rn;
9ee6e8bb 4288 rn = rm;
ad69471c 4289 rm = rtmp;
9ee6e8bb
PB		 4290 pairwise = 0;
4291 }
2c0262af 4292 break;
9ee6e8bb
PB		 4293 case 20: /* VPMAX */
4294 case 21: /* VPMIN */
4295 case 23: /* VPADD */
4296 pairwise = 1;
2c0262af 4297 break;
9ee6e8bb
PB		 4298 case 26: /* VPADD (float) */
4299 pairwise = (u && size < 2);
2c0262af 4300 break;
9ee6e8bb
PB		 4301 case 30: /* VPMIN/VPMAX (float) */
4302 pairwise = u;
2c0262af 4303 break;
9ee6e8bb
PB		 4304 default:
4305 pairwise = 0;
2c0262af 4306 break;
9ee6e8bb 4307 }
dd8fbd78 4308
9ee6e8bb
PB		 4309 for (pass = 0; pass < (q ? 4 : 2); pass++) {
4310
4311 if (pairwise) {
4312 /* Pairwise. */
4313 if (q)
4314 n = (pass & 1) * 2;
2c0262af 4315 else
9ee6e8bb
PB		 4316 n = 0;
4317 if (pass < q + 1) {
dd8fbd78
FN		 4318 tmp = neon_load_reg(rn, n);
4319 tmp2 = neon_load_reg(rn, n + 1);
9ee6e8bb 4320 } else {
dd8fbd78
FN		 4321 tmp = neon_load_reg(rm, n);
4322 tmp2 = neon_load_reg(rm, n + 1);
9ee6e8bb
PB		 4323 }
4324 } else {
4325 /* Elementwise. */
dd8fbd78
FN		 4326 tmp = neon_load_reg(rn, pass);
4327 tmp2 = neon_load_reg(rm, pass);
9ee6e8bb
PB		 4328 }
4329 switch (op) {
4330 case 0: /* VHADD */
4331 GEN_NEON_INTEGER_OP(hadd);
4332 break;
4333 case 1: /* VQADD */
ad69471c 4334 GEN_NEON_INTEGER_OP_ENV(qadd);
2c0262af 4335 break;
9ee6e8bb
PB		 4336 case 2: /* VRHADD */
4337 GEN_NEON_INTEGER_OP(rhadd);
2c0262af 4338 break;
9ee6e8bb
PB		 4339 case 3: /* Logic ops. */
4340 switch ((u << 2) | size) {
4341 case 0: /* VAND */
dd8fbd78 4342 tcg_gen_and_i32(tmp, tmp, tmp2);
9ee6e8bb
PB		 4343 break;
4344 case 1: /* BIC */
f669df27 4345 tcg_gen_andc_i32(tmp, tmp, tmp2);
9ee6e8bb
PB		 4346 break;
4347 case 2: /* VORR */
dd8fbd78 4348 tcg_gen_or_i32(tmp, tmp, tmp2);
9ee6e8bb
PB		 4349 break;
4350 case 3: /* VORN */
f669df27 4351 tcg_gen_orc_i32(tmp, tmp, tmp2);
9ee6e8bb
PB		 4352 break;
4353 case 4: /* VEOR */
dd8fbd78 4354 tcg_gen_xor_i32(tmp, tmp, tmp2);
9ee6e8bb
PB		 4355 break;
4356 case 5: /* VBSL */
dd8fbd78
FN		 4357 tmp3 = neon_load_reg(rd, pass);
4358 gen_neon_bsl(tmp, tmp, tmp2, tmp3);
4359 dead_tmp(tmp3);
9ee6e8bb
PB		 4360 break;
4361 case 6: /* VBIT */
dd8fbd78
FN		 4362 tmp3 = neon_load_reg(rd, pass);
4363 gen_neon_bsl(tmp, tmp, tmp3, tmp2);
4364 dead_tmp(tmp3);
9ee6e8bb
PB		 4365 break;
4366 case 7: /* VBIF */
dd8fbd78
FN		 4367 tmp3 = neon_load_reg(rd, pass);
4368 gen_neon_bsl(tmp, tmp3, tmp, tmp2);
4369 dead_tmp(tmp3);
9ee6e8bb 4370 break;
2c0262af
FB		 4371 }
4372 break;
9ee6e8bb
PB		 4373 case 4: /* VHSUB */
4374 GEN_NEON_INTEGER_OP(hsub);
4375 break;
4376 case 5: /* VQSUB */
ad69471c 4377 GEN_NEON_INTEGER_OP_ENV(qsub);
2c0262af 4378 break;
9ee6e8bb
PB		 4379 case 6: /* VCGT */
4380 GEN_NEON_INTEGER_OP(cgt);
4381 break;
4382 case 7: /* VCGE */
4383 GEN_NEON_INTEGER_OP(cge);
4384 break;
4385 case 8: /* VSHL */
ad69471c 4386 GEN_NEON_INTEGER_OP(shl);
2c0262af 4387 break;
9ee6e8bb 4388 case 9: /* VQSHL */
ad69471c 4389 GEN_NEON_INTEGER_OP_ENV(qshl);
2c0262af 4390 break;
9ee6e8bb 4391 case 10: /* VRSHL */
ad69471c 4392 GEN_NEON_INTEGER_OP(rshl);
2c0262af 4393 break;
9ee6e8bb 4394 case 11: /* VQRSHL */
ad69471c 4395 GEN_NEON_INTEGER_OP_ENV(qrshl);
9ee6e8bb
PB		 4396 break;
4397 case 12: /* VMAX */
4398 GEN_NEON_INTEGER_OP(max);
4399 break;
4400 case 13: /* VMIN */
4401 GEN_NEON_INTEGER_OP(min);
4402 break;
4403 case 14: /* VABD */
4404 GEN_NEON_INTEGER_OP(abd);
4405 break;
4406 case 15: /* VABA */
4407 GEN_NEON_INTEGER_OP(abd);
dd8fbd78
FN		 4408 dead_tmp(tmp2);
4409 tmp2 = neon_load_reg(rd, pass);
4410 gen_neon_add(size, tmp, tmp2);
9ee6e8bb
PB		 4411 break;
4412 case 16:
4413 if (!u) { /* VADD */
dd8fbd78 4414 if (gen_neon_add(size, tmp, tmp2))
9ee6e8bb
PB		 4415 return 1;
4416 } else { /* VSUB */
4417 switch (size) {
dd8fbd78
FN		 4418 case 0: gen_helper_neon_sub_u8(tmp, tmp, tmp2); break;
4419 case 1: gen_helper_neon_sub_u16(tmp, tmp, tmp2); break;
4420 case 2: tcg_gen_sub_i32(tmp, tmp, tmp2); break;
9ee6e8bb
PB		 4421 default: return 1;
4422 }
4423 }
4424 break;
4425 case 17:
4426 if (!u) { /* VTST */
4427 switch (size) {
dd8fbd78
FN		 4428 case 0: gen_helper_neon_tst_u8(tmp, tmp, tmp2); break;
4429 case 1: gen_helper_neon_tst_u16(tmp, tmp, tmp2); break;
4430 case 2: gen_helper_neon_tst_u32(tmp, tmp, tmp2); break;
9ee6e8bb
PB		 4431 default: return 1;
4432 }
4433 } else { /* VCEQ */
4434 switch (size) {
dd8fbd78
FN		 4435 case 0: gen_helper_neon_ceq_u8(tmp, tmp, tmp2); break;
4436 case 1: gen_helper_neon_ceq_u16(tmp, tmp, tmp2); break;
4437 case 2: gen_helper_neon_ceq_u32(tmp, tmp, tmp2); break;
9ee6e8bb
PB		 4438 default: return 1;
4439 }
4440 }
4441 break;
4442 case 18: /* Multiply. */
4443 switch (size) {
dd8fbd78
FN		 4444 case 0: gen_helper_neon_mul_u8(tmp, tmp, tmp2); break;
4445 case 1: gen_helper_neon_mul_u16(tmp, tmp, tmp2); break;
4446 case 2: tcg_gen_mul_i32(tmp, tmp, tmp2); break;
9ee6e8bb
PB		 4447 default: return 1;
4448 }
dd8fbd78
FN		 4449 dead_tmp(tmp2);
4450 tmp2 = neon_load_reg(rd, pass);
9ee6e8bb 4451 if (u) { /* VMLS */
dd8fbd78 4452 gen_neon_rsb(size, tmp, tmp2);
9ee6e8bb 4453 } else { /* VMLA */
dd8fbd78 4454 gen_neon_add(size, tmp, tmp2);
9ee6e8bb
PB		 4455 }
4456 break;
4457 case 19: /* VMUL */
4458 if (u) { /* polynomial */
dd8fbd78 4459 gen_helper_neon_mul_p8(tmp, tmp, tmp2);
9ee6e8bb
PB		 4460 } else { /* Integer */
4461 switch (size) {
dd8fbd78
FN		 4462 case 0: gen_helper_neon_mul_u8(tmp, tmp, tmp2); break;
4463 case 1: gen_helper_neon_mul_u16(tmp, tmp, tmp2); break;
4464 case 2: tcg_gen_mul_i32(tmp, tmp, tmp2); break;
9ee6e8bb
PB		 4465 default: return 1;
4466 }
4467 }
4468 break;
4469 case 20: /* VPMAX */
4470 GEN_NEON_INTEGER_OP(pmax);
4471 break;
4472 case 21: /* VPMIN */
4473 GEN_NEON_INTEGER_OP(pmin);
4474 break;
4475 case 22: /* Hultiply high. */
4476 if (!u) { /* VQDMULH */
4477 switch (size) {
dd8fbd78
FN		 4478 case 1: gen_helper_neon_qdmulh_s16(tmp, cpu_env, tmp, tmp2); break;
4479 case 2: gen_helper_neon_qdmulh_s32(tmp, cpu_env, tmp, tmp2); break;
9ee6e8bb
PB		 4480 default: return 1;
4481 }
4482 } else { /* VQRDHMUL */
4483 switch (size) {
dd8fbd78
FN		 4484 case 1: gen_helper_neon_qrdmulh_s16(tmp, cpu_env, tmp, tmp2); break;
4485 case 2: gen_helper_neon_qrdmulh_s32(tmp, cpu_env, tmp, tmp2); break;
9ee6e8bb
PB		 4486 default: return 1;
4487 }
4488 }
4489 break;
4490 case 23: /* VPADD */
4491 if (u)
4492 return 1;
4493 switch (size) {
dd8fbd78
FN		 4494 case 0: gen_helper_neon_padd_u8(tmp, tmp, tmp2); break;
4495 case 1: gen_helper_neon_padd_u16(tmp, tmp, tmp2); break;
4496 case 2: tcg_gen_add_i32(tmp, tmp, tmp2); break;
9ee6e8bb
PB		 4497 default: return 1;
4498 }
4499 break;
4500 case 26: /* Floating point arithnetic. */
4501 switch ((u << 2) | size) {
4502 case 0: /* VADD */
dd8fbd78 4503 gen_helper_neon_add_f32(tmp, tmp, tmp2);
9ee6e8bb
PB		 4504 break;
4505 case 2: /* VSUB */
dd8fbd78 4506 gen_helper_neon_sub_f32(tmp, tmp, tmp2);
9ee6e8bb
PB		 4507 break;
4508 case 4: /* VPADD */
dd8fbd78 4509 gen_helper_neon_add_f32(tmp, tmp, tmp2);
9ee6e8bb
PB		 4510 break;
4511 case 6: /* VABD */
dd8fbd78 4512 gen_helper_neon_abd_f32(tmp, tmp, tmp2);
9ee6e8bb
PB		 4513 break;
4514 default:
4515 return 1;
4516 }
4517 break;
4518 case 27: /* Float multiply. */
dd8fbd78 4519 gen_helper_neon_mul_f32(tmp, tmp, tmp2);
9ee6e8bb 4520 if (!u) {
dd8fbd78
FN		 4521 dead_tmp(tmp2);
4522 tmp2 = neon_load_reg(rd, pass);
9ee6e8bb 4523 if (size == 0) {
dd8fbd78 4524 gen_helper_neon_add_f32(tmp, tmp, tmp2);
9ee6e8bb 4525 } else {
dd8fbd78 4526 gen_helper_neon_sub_f32(tmp, tmp2, tmp);
9ee6e8bb
PB		 4527 }
4528 }
4529 break;
4530 case 28: /* Float compare. */
4531 if (!u) {
dd8fbd78 4532 gen_helper_neon_ceq_f32(tmp, tmp, tmp2);
b5ff1b31 4533 } else {
9ee6e8bb 4534 if (size == 0)
dd8fbd78 4535 gen_helper_neon_cge_f32(tmp, tmp, tmp2);
9ee6e8bb 4536 else
dd8fbd78 4537 gen_helper_neon_cgt_f32(tmp, tmp, tmp2);
b5ff1b31 4538 }
2c0262af 4539 break;
9ee6e8bb
PB		 4540 case 29: /* Float compare absolute. */
4541 if (!u)
4542 return 1;
4543 if (size == 0)
dd8fbd78 4544 gen_helper_neon_acge_f32(tmp, tmp, tmp2);
9ee6e8bb 4545 else
dd8fbd78 4546 gen_helper_neon_acgt_f32(tmp, tmp, tmp2);
2c0262af 4547 break;
9ee6e8bb
PB		 4548 case 30: /* Float min/max. */
4549 if (size == 0)
dd8fbd78 4550 gen_helper_neon_max_f32(tmp, tmp, tmp2);
9ee6e8bb 4551 else
dd8fbd78 4552 gen_helper_neon_min_f32(tmp, tmp, tmp2);
9ee6e8bb
PB		 4553 break;
4554 case 31:
4555 if (size == 0)
dd8fbd78 4556 gen_helper_recps_f32(tmp, tmp, tmp2, cpu_env);
9ee6e8bb 4557 else
dd8fbd78 4558 gen_helper_rsqrts_f32(tmp, tmp, tmp2, cpu_env);
2c0262af 4559 break;
9ee6e8bb
PB		 4560 default:
4561 abort();
2c0262af 4562 }
dd8fbd78
FN		 4563 dead_tmp(tmp2);
4564
9ee6e8bb
PB		 4565 /* Save the result. For elementwise operations we can put it
4566 straight into the destination register. For pairwise operations
4567 we have to be careful to avoid clobbering the source operands. */
4568 if (pairwise && rd == rm) {
dd8fbd78 4569 neon_store_scratch(pass, tmp);
9ee6e8bb 4570 } else {
dd8fbd78 4571 neon_store_reg(rd, pass, tmp);
9ee6e8bb
PB		 4572 }
4573
4574 } /* for pass */
4575 if (pairwise && rd == rm) {
4576 for (pass = 0; pass < (q ? 4 : 2); pass++) {
dd8fbd78
FN		 4577 tmp = neon_load_scratch(pass);
4578 neon_store_reg(rd, pass, tmp);
9ee6e8bb
PB		 4579 }
4580 }
ad69471c 4581 /* End of 3 register same size operations. */
9ee6e8bb
PB		 4582 } else if (insn & (1 << 4)) {
4583 if ((insn & 0x00380080) != 0) {
4584 /* Two registers and shift. */
4585 op = (insn >> 8) & 0xf;
4586 if (insn & (1 << 7)) {
4587 /* 64-bit shift. */
4588 size = 3;
4589 } else {
4590 size = 2;
4591 while ((insn & (1 << (size + 19))) == 0)
4592 size--;
4593 }
4594 shift = (insn >> 16) & ((1 << (3 + size)) - 1);
4595 /* To avoid excessive dumplication of ops we implement shift
4596 by immediate using the variable shift operations. */
4597 if (op < 8) {
4598 /* Shift by immediate:
4599 VSHR, VSRA, VRSHR, VRSRA, VSRI, VSHL, VQSHL, VQSHLU. */
4600 /* Right shifts are encoded as N - shift, where N is the
4601 element size in bits. */
4602 if (op <= 4)
4603 shift = shift - (1 << (size + 3));
9ee6e8bb
PB		 4604 if (size == 3) {
4605 count = q + 1;
4606 } else {
4607 count = q ? 4: 2;
4608 }
4609 switch (size) {
4610 case 0:
4611 imm = (uint8_t) shift;
4612 imm |= imm << 8;
4613 imm |= imm << 16;
4614 break;
4615 case 1:
4616 imm = (uint16_t) shift;
4617 imm |= imm << 16;
4618 break;
4619 case 2:
4620 case 3:
4621 imm = shift;
4622 break;
4623 default:
4624 abort();
4625 }
4626
4627 for (pass = 0; pass < count; pass++) {
ad69471c
PB		 4628 if (size == 3) {
4629 neon_load_reg64(cpu_V0, rm + pass);
4630 tcg_gen_movi_i64(cpu_V1, imm);
4631 switch (op) {
4632 case 0: /* VSHR */
4633 case 1: /* VSRA */
4634 if (u)
4635 gen_helper_neon_shl_u64(cpu_V0, cpu_V0, cpu_V1);
9ee6e8bb 4636 else
ad69471c 4637 gen_helper_neon_shl_s64(cpu_V0, cpu_V0, cpu_V1);
9ee6e8bb 4638 break;
ad69471c
PB		 4639 case 2: /* VRSHR */
4640 case 3: /* VRSRA */
4641 if (u)
4642 gen_helper_neon_rshl_u64(cpu_V0, cpu_V0, cpu_V1);
9ee6e8bb 4643 else
ad69471c 4644 gen_helper_neon_rshl_s64(cpu_V0, cpu_V0, cpu_V1);
9ee6e8bb 4645 break;
ad69471c
PB		 4646 case 4: /* VSRI */
4647 if (!u)
4648 return 1;
4649 gen_helper_neon_shl_u64(cpu_V0, cpu_V0, cpu_V1);
4650 break;
4651 case 5: /* VSHL, VSLI */
4652 gen_helper_neon_shl_u64(cpu_V0, cpu_V0, cpu_V1);
4653 break;
4654 case 6: /* VQSHL */
4655 if (u)
4656 gen_helper_neon_qshl_u64(cpu_V0, cpu_env, cpu_V0, cpu_V1);
9ee6e8bb 4657 else
ad69471c
PB		 4658 gen_helper_neon_qshl_s64(cpu_V0, cpu_env, cpu_V0, cpu_V1);
4659 break;
4660 case 7: /* VQSHLU */
4661 gen_helper_neon_qshl_u64(cpu_V0, cpu_env, cpu_V0, cpu_V1);
9ee6e8bb 4662 break;
9ee6e8bb 4663 }
ad69471c
PB		 4664 if (op == 1 || op == 3) {
4665 /* Accumulate. */
4666 neon_load_reg64(cpu_V0, rd + pass);
4667 tcg_gen_add_i64(cpu_V0, cpu_V0, cpu_V1);
4668 } else if (op == 4 || (op == 5 && u)) {
4669 /* Insert */
4670 cpu_abort(env, "VS[LR]I.64 not implemented");
4671 }
4672 neon_store_reg64(cpu_V0, rd + pass);
4673 } else { /* size < 3 */
4674 /* Operands in T0 and T1. */
dd8fbd78
FN		 4675 tmp = neon_load_reg(rm, pass);
4676 tmp2 = new_tmp();
4677 tcg_gen_movi_i32(tmp2, imm);
ad69471c
PB		 4678 switch (op) {
4679 case 0: /* VSHR */
4680 case 1: /* VSRA */
4681 GEN_NEON_INTEGER_OP(shl);
4682 break;
4683 case 2: /* VRSHR */
4684 case 3: /* VRSRA */
4685 GEN_NEON_INTEGER_OP(rshl);
4686 break;
4687 case 4: /* VSRI */
4688 if (!u)
4689 return 1;
4690 GEN_NEON_INTEGER_OP(shl);
4691 break;
4692 case 5: /* VSHL, VSLI */
4693 switch (size) {
dd8fbd78
FN		 4694 case 0: gen_helper_neon_shl_u8(tmp, tmp, tmp2); break;
4695 case 1: gen_helper_neon_shl_u16(tmp, tmp, tmp2); break;
4696 case 2: gen_helper_neon_shl_u32(tmp, tmp, tmp2); break;
ad69471c
PB		 4697 default: return 1;
4698 }
4699 break;
4700 case 6: /* VQSHL */
4701 GEN_NEON_INTEGER_OP_ENV(qshl);
4702 break;
4703 case 7: /* VQSHLU */
4704 switch (size) {
dd8fbd78
FN		 4705 case 0: gen_helper_neon_qshl_u8(tmp, cpu_env, tmp, tmp2); break;
4706 case 1: gen_helper_neon_qshl_u16(tmp, cpu_env, tmp, tmp2); break;
4707 case 2: gen_helper_neon_qshl_u32(tmp, cpu_env, tmp, tmp2); break;
ad69471c
PB		 4708 default: return 1;
4709 }
4710 break;
4711 }
dd8fbd78 4712 dead_tmp(tmp2);
ad69471c
PB		 4713
4714 if (op == 1 || op == 3) {
4715 /* Accumulate. */
dd8fbd78
FN		 4716 tmp2 = neon_load_reg(rd, pass);
4717 gen_neon_add(size, tmp2, tmp);
4718 dead_tmp(tmp2);
ad69471c
PB		 4719 } else if (op == 4 || (op == 5 && u)) {
4720 /* Insert */
4721 switch (size) {
4722 case 0:
4723 if (op == 4)
ca9a32e4 4724 mask = 0xff >> -shift;
ad69471c 4725 else
ca9a32e4
JR		 4726 mask = (uint8_t)(0xff << shift);
4727 mask |= mask << 8;
4728 mask |= mask << 16;
ad69471c
PB		 4729 break;
4730 case 1:
4731 if (op == 4)
ca9a32e4 4732 mask = 0xffff >> -shift;
ad69471c 4733 else
ca9a32e4
JR		 4734 mask = (uint16_t)(0xffff << shift);
4735 mask |= mask << 16;
ad69471c
PB		 4736 break;
4737 case 2:
ca9a32e4
JR		 4738 if (shift < -31 || shift > 31) {
4739 mask = 0;
4740 } else {
4741 if (op == 4)
4742 mask = 0xffffffffu >> -shift;
4743 else
4744 mask = 0xffffffffu << shift;
4745 }
ad69471c
PB		 4746 break;
4747 default:
4748 abort();
4749 }
dd8fbd78 4750 tmp2 = neon_load_reg(rd, pass);
ca9a32e4
JR		 4751 tcg_gen_andi_i32(tmp, tmp, mask);
4752 tcg_gen_andi_i32(tmp2, tmp2, ~mask);
dd8fbd78
FN		 4753 tcg_gen_or_i32(tmp, tmp, tmp2);
4754 dead_tmp(tmp2);
ad69471c 4755 }
dd8fbd78 4756 neon_store_reg(rd, pass, tmp);
9ee6e8bb
PB		 4757 }
4758 } /* for pass */
4759 } else if (op < 10) {
ad69471c 4760 /* Shift by immediate and narrow:
9ee6e8bb
PB		 4761 VSHRN, VRSHRN, VQSHRN, VQRSHRN. */
4762 shift = shift - (1 << (size + 3));
4763 size++;
9ee6e8bb
PB		 4764 switch (size) {
4765 case 1:
ad69471c 4766 imm = (uint16_t)shift;
9ee6e8bb 4767 imm |= imm << 16;
ad69471c 4768 tmp2 = tcg_const_i32(imm);
a7812ae4 4769 TCGV_UNUSED_I64(tmp64);
9ee6e8bb
PB		 4770 break;
4771 case 2:
ad69471c
PB		 4772 imm = (uint32_t)shift;
4773 tmp2 = tcg_const_i32(imm);
a7812ae4 4774 TCGV_UNUSED_I64(tmp64);
4cc633c3 4775 break;
9ee6e8bb 4776 case 3:
a7812ae4
PB		 4777 tmp64 = tcg_const_i64(shift);
4778 TCGV_UNUSED(tmp2);
9ee6e8bb
PB		 4779 break;
4780 default:
4781 abort();
4782 }
4783
ad69471c
PB		 4784 for (pass = 0; pass < 2; pass++) {
4785 if (size == 3) {
4786 neon_load_reg64(cpu_V0, rm + pass);
4787 if (q) {
4788 if (u)
a7812ae4 4789 gen_helper_neon_rshl_u64(cpu_V0, cpu_V0, tmp64);
ad69471c 4790 else
a7812ae4 4791 gen_helper_neon_rshl_s64(cpu_V0, cpu_V0, tmp64);
ad69471c
PB		 4792 } else {
4793 if (u)
a7812ae4 4794 gen_helper_neon_shl_u64(cpu_V0, cpu_V0, tmp64);
ad69471c 4795 else
a7812ae4 4796 gen_helper_neon_shl_s64(cpu_V0, cpu_V0, tmp64);
ad69471c 4797 }
2c0262af 4798 } else {
ad69471c
PB		 4799 tmp = neon_load_reg(rm + pass, 0);
4800 gen_neon_shift_narrow(size, tmp, tmp2, q, u);
36aa55dc
PB		 4801 tmp3 = neon_load_reg(rm + pass, 1);
4802 gen_neon_shift_narrow(size, tmp3, tmp2, q, u);
4803 tcg_gen_concat_i32_i64(cpu_V0, tmp, tmp3);
ad69471c 4804 dead_tmp(tmp);
36aa55dc 4805 dead_tmp(tmp3);
9ee6e8bb 4806 }
ad69471c
PB		 4807 tmp = new_tmp();
4808 if (op == 8 && !u) {
4809 gen_neon_narrow(size - 1, tmp, cpu_V0);
9ee6e8bb 4810 } else {
ad69471c
PB		 4811 if (op == 8)
4812 gen_neon_narrow_sats(size - 1, tmp, cpu_V0);
9ee6e8bb 4813 else
ad69471c
PB		 4814 gen_neon_narrow_satu(size - 1, tmp, cpu_V0);
4815 }
2301db49 4816 neon_store_reg(rd, pass, tmp);
9ee6e8bb 4817 } /* for pass */
b75263d6
JR		 4818 if (size == 3) {
4819 tcg_temp_free_i64(tmp64);
2301db49
JR		 4820 } else {
4821 dead_tmp(tmp2);
b75263d6 4822 }
9ee6e8bb
PB		 4823 } else if (op == 10) {
4824 /* VSHLL */
ad69471c 4825 if (q || size == 3)
9ee6e8bb 4826 return 1;
ad69471c
PB		 4827 tmp = neon_load_reg(rm, 0);
4828 tmp2 = neon_load_reg(rm, 1);
9ee6e8bb 4829 for (pass = 0; pass < 2; pass++) {
ad69471c
PB		 4830 if (pass == 1)
4831 tmp = tmp2;
4832
4833 gen_neon_widen(cpu_V0, tmp, size, u);
9ee6e8bb 4834
9ee6e8bb
PB		 4835 if (shift != 0) {
4836 /* The shift is less than the width of the source
ad69471c
PB		 4837 type, so we can just shift the whole register. */
4838 tcg_gen_shli_i64(cpu_V0, cpu_V0, shift);
4839 if (size < 2 || !u) {
4840 uint64_t imm64;
4841 if (size == 0) {
4842 imm = (0xffu >> (8 - shift));
4843 imm |= imm << 16;
4844 } else {
4845 imm = 0xffff >> (16 - shift);
9ee6e8bb 4846 }
ad69471c
PB		 4847 imm64 = imm | (((uint64_t)imm) << 32);
4848 tcg_gen_andi_i64(cpu_V0, cpu_V0, imm64);
9ee6e8bb
PB		 4849 }
4850 }
ad69471c 4851 neon_store_reg64(cpu_V0, rd + pass);
9ee6e8bb
PB		 4852 }
4853 } else if (op == 15 || op == 16) {
4854 /* VCVT fixed-point. */
4855 for (pass = 0; pass < (q ? 4 : 2); pass++) {
4373f3ce 4856 tcg_gen_ld_f32(cpu_F0s, cpu_env, neon_reg_offset(rm, pass));
9ee6e8bb
PB		 4857 if (op & 1) {
4858 if (u)
4373f3ce 4859 gen_vfp_ulto(0, shift);
9ee6e8bb 4860 else
4373f3ce 4861 gen_vfp_slto(0, shift);
9ee6e8bb
PB		 4862 } else {
4863 if (u)
4373f3ce 4864 gen_vfp_toul(0, shift);
9ee6e8bb 4865 else
4373f3ce 4866 gen_vfp_tosl(0, shift);
2c0262af 4867 }
4373f3ce 4868 tcg_gen_st_f32(cpu_F0s, cpu_env, neon_reg_offset(rd, pass));
2c0262af
FB		 4869 }
4870 } else {
9ee6e8bb
PB		 4871 return 1;
4872 }
4873 } else { /* (insn & 0x00380080) == 0 */
4874 int invert;
4875
4876 op = (insn >> 8) & 0xf;
4877 /* One register and immediate. */
4878 imm = (u << 7) | ((insn >> 12) & 0x70) | (insn & 0xf);
4879 invert = (insn & (1 << 5)) != 0;
4880 switch (op) {
4881 case 0: case 1:
4882 /* no-op */
4883 break;
4884 case 2: case 3:
4885 imm <<= 8;
4886 break;
4887 case 4: case 5:
4888 imm <<= 16;
4889 break;
4890 case 6: case 7:
4891 imm <<= 24;
4892 break;
4893 case 8: case 9:
4894 imm |= imm << 16;
4895 break;
4896 case 10: case 11:
4897 imm = (imm << 8) | (imm << 24);
4898 break;
4899 case 12:
8e31209e 4900 imm = (imm << 8) | 0xff;
9ee6e8bb
PB		 4901 break;
4902 case 13:
4903 imm = (imm << 16) | 0xffff;
4904 break;
4905 case 14:
4906 imm |= (imm << 8) | (imm << 16) | (imm << 24);
4907 if (invert)
4908 imm = ~imm;
4909 break;
4910 case 15:
4911 imm = ((imm & 0x80) << 24) | ((imm & 0x3f) << 19)
4912 | ((imm & 0x40) ? (0x1f << 25) : (1 << 30));
4913 break;
4914 }
4915 if (invert)
4916 imm = ~imm;
4917
9ee6e8bb
PB		 4918 for (pass = 0; pass < (q ? 4 : 2); pass++) {
4919 if (op & 1 && op < 12) {
ad69471c 4920 tmp = neon_load_reg(rd, pass);
9ee6e8bb
PB		 4921 if (invert) {
4922 /* The immediate value has already been inverted, so
4923 BIC becomes AND. */
ad69471c 4924 tcg_gen_andi_i32(tmp, tmp, imm);
9ee6e8bb 4925 } else {
ad69471c 4926 tcg_gen_ori_i32(tmp, tmp, imm);
9ee6e8bb 4927 }
9ee6e8bb 4928 } else {
ad69471c
PB		 4929 /* VMOV, VMVN. */
4930 tmp = new_tmp();
9ee6e8bb 4931 if (op == 14 && invert) {
ad69471c
PB		 4932 uint32_t val;
4933 val = 0;
9ee6e8bb
PB		 4934 for (n = 0; n < 4; n++) {
4935 if (imm & (1 << (n + (pass & 1) * 4)))
ad69471c 4936 val |= 0xff << (n * 8);
9ee6e8bb 4937 }
ad69471c
PB		 4938 tcg_gen_movi_i32(tmp, val);
4939 } else {
4940 tcg_gen_movi_i32(tmp, imm);
9ee6e8bb 4941 }
9ee6e8bb 4942 }
ad69471c 4943 neon_store_reg(rd, pass, tmp);
9ee6e8bb
PB		 4944 }
4945 }
e4b3861d 4946 } else { /* (insn & 0x00800010 == 0x00800000) */
9ee6e8bb
PB		 4947 if (size != 3) {
4948 op = (insn >> 8) & 0xf;
4949 if ((insn & (1 << 6)) == 0) {
4950 /* Three registers of different lengths. */
4951 int src1_wide;
4952 int src2_wide;
4953 int prewiden;
4954 /* prewiden, src1_wide, src2_wide */
4955 static const int neon_3reg_wide[16][3] = {
4956 {1, 0, 0}, /* VADDL */
4957 {1, 1, 0}, /* VADDW */
4958 {1, 0, 0}, /* VSUBL */
4959 {1, 1, 0}, /* VSUBW */
4960 {0, 1, 1}, /* VADDHN */
4961 {0, 0, 0}, /* VABAL */
4962 {0, 1, 1}, /* VSUBHN */
4963 {0, 0, 0}, /* VABDL */
4964 {0, 0, 0}, /* VMLAL */
4965 {0, 0, 0}, /* VQDMLAL */
4966 {0, 0, 0}, /* VMLSL */
4967 {0, 0, 0}, /* VQDMLSL */
4968 {0, 0, 0}, /* Integer VMULL */
4969 {0, 0, 0}, /* VQDMULL */
4970 {0, 0, 0} /* Polynomial VMULL */
4971 };
4972
4973 prewiden = neon_3reg_wide[op][0];
4974 src1_wide = neon_3reg_wide[op][1];
4975 src2_wide = neon_3reg_wide[op][2];
4976
ad69471c
PB		 4977 if (size == 0 && (op == 9 || op == 11 || op == 13))
4978 return 1;
4979
9ee6e8bb
PB		 4980 /* Avoid overlapping operands. Wide source operands are
4981 always aligned so will never overlap with wide
4982 destinations in problematic ways. */
8f8e3aa4 4983 if (rd == rm && !src2_wide) {
dd8fbd78
FN		 4984 tmp = neon_load_reg(rm, 1);
4985 neon_store_scratch(2, tmp);
8f8e3aa4 4986 } else if (rd == rn && !src1_wide) {
dd8fbd78
FN		 4987 tmp = neon_load_reg(rn, 1);
4988 neon_store_scratch(2, tmp);
9ee6e8bb 4989 }
a50f5b91 4990 TCGV_UNUSED(tmp3);
9ee6e8bb 4991 for (pass = 0; pass < 2; pass++) {
ad69471c
PB		 4992 if (src1_wide) {
4993 neon_load_reg64(cpu_V0, rn + pass);
a50f5b91 4994 TCGV_UNUSED(tmp);
9ee6e8bb 4995 } else {
ad69471c 4996 if (pass == 1 && rd == rn) {
dd8fbd78 4997 tmp = neon_load_scratch(2);
9ee6e8bb 4998 } else {
ad69471c
PB		 4999 tmp = neon_load_reg(rn, pass);
5000 }
5001 if (prewiden) {
5002 gen_neon_widen(cpu_V0, tmp, size, u);
9ee6e8bb
PB		 5003 }
5004 }
ad69471c
PB		 5005 if (src2_wide) {
5006 neon_load_reg64(cpu_V1, rm + pass);
a50f5b91 5007 TCGV_UNUSED(tmp2);
9ee6e8bb 5008 } else {
ad69471c 5009 if (pass == 1 && rd == rm) {
dd8fbd78 5010 tmp2 = neon_load_scratch(2);
9ee6e8bb 5011 } else {
ad69471c
PB		 5012 tmp2 = neon_load_reg(rm, pass);
5013 }
5014 if (prewiden) {
5015 gen_neon_widen(cpu_V1, tmp2, size, u);
9ee6e8bb 5016 }
9ee6e8bb
PB		 5017 }
5018 switch (op) {
5019 case 0: case 1: case 4: /* VADDL, VADDW, VADDHN, VRADDHN */
ad69471c 5020 gen_neon_addl(size);
9ee6e8bb 5021 break;
79b0e534 5022 case 2: case 3: case 6: /* VSUBL, VSUBW, VSUBHN, VRSUBHN */
ad69471c 5023 gen_neon_subl(size);
9ee6e8bb
PB		 5024 break;
5025 case 5: case 7: /* VABAL, VABDL */
5026 switch ((size << 1) | u) {
ad69471c
PB		 5027 case 0:
5028 gen_helper_neon_abdl_s16(cpu_V0, tmp, tmp2);
5029 break;
5030 case 1:
5031 gen_helper_neon_abdl_u16(cpu_V0, tmp, tmp2);
5032 break;
5033 case 2:
5034 gen_helper_neon_abdl_s32(cpu_V0, tmp, tmp2);
5035 break;
5036 case 3:
5037 gen_helper_neon_abdl_u32(cpu_V0, tmp, tmp2);
5038 break;
5039 case 4:
5040 gen_helper_neon_abdl_s64(cpu_V0, tmp, tmp2);
5041 break;
5042 case 5:
5043 gen_helper_neon_abdl_u64(cpu_V0, tmp, tmp2);
5044 break;
9ee6e8bb
PB		 5045 default: abort();
5046 }
ad69471c
PB		 5047 dead_tmp(tmp2);
5048 dead_tmp(tmp);
9ee6e8bb
PB		 5049 break;
5050 case 8: case 9: case 10: case 11: case 12: case 13:
5051 /* VMLAL, VQDMLAL, VMLSL, VQDMLSL, VMULL, VQDMULL */
ad69471c 5052 gen_neon_mull(cpu_V0, tmp, tmp2, size, u);
dd8fbd78
FN		 5053 dead_tmp(tmp2);
5054 dead_tmp(tmp);
9ee6e8bb
PB		 5055 break;
5056 case 14: /* Polynomial VMULL */
5057 cpu_abort(env, "Polynomial VMULL not implemented");
5058
5059 default: /* 15 is RESERVED. */
5060 return 1;
5061 }
5062 if (op == 5 || op == 13 || (op >= 8 && op <= 11)) {
5063 /* Accumulate. */
5064 if (op == 10 || op == 11) {
ad69471c 5065 gen_neon_negl(cpu_V0, size);
9ee6e8bb
PB		 5066 }
5067
9ee6e8bb 5068 if (op != 13) {
ad69471c 5069 neon_load_reg64(cpu_V1, rd + pass);
9ee6e8bb
PB		 5070 }
5071
5072 switch (op) {
5073 case 5: case 8: case 10: /* VABAL, VMLAL, VMLSL */
ad69471c 5074 gen_neon_addl(size);
9ee6e8bb
PB		 5075 break;
5076 case 9: case 11: /* VQDMLAL, VQDMLSL */
ad69471c
PB		 5077 gen_neon_addl_saturate(cpu_V0, cpu_V0, size);
5078 gen_neon_addl_saturate(cpu_V0, cpu_V1, size);
5079 break;
9ee6e8bb
PB		 5080 /* Fall through. */
5081 case 13: /* VQDMULL */
ad69471c 5082 gen_neon_addl_saturate(cpu_V0, cpu_V0, size);
9ee6e8bb
PB		 5083 break;
5084 default:
5085 abort();
5086 }
ad69471c 5087 neon_store_reg64(cpu_V0, rd + pass);
9ee6e8bb
PB		 5088 } else if (op == 4 || op == 6) {
5089 /* Narrowing operation. */
ad69471c 5090 tmp = new_tmp();
79b0e534 5091 if (!u) {
9ee6e8bb 5092 switch (size) {
ad69471c
PB		 5093 case 0:
5094 gen_helper_neon_narrow_high_u8(tmp, cpu_V0);
5095 break;
5096 case 1:
5097 gen_helper_neon_narrow_high_u16(tmp, cpu_V0);
5098 break;
5099 case 2:
5100 tcg_gen_shri_i64(cpu_V0, cpu_V0, 32);
5101 tcg_gen_trunc_i64_i32(tmp, cpu_V0);
5102 break;
9ee6e8bb
PB		 5103 default: abort();
5104 }
5105 } else {
5106 switch (size) {
ad69471c
PB		 5107 case 0:
5108 gen_helper_neon_narrow_round_high_u8(tmp, cpu_V0);
5109 break;
5110 case 1:
5111 gen_helper_neon_narrow_round_high_u16(tmp, cpu_V0);
5112 break;
5113 case 2:
5114 tcg_gen_addi_i64(cpu_V0, cpu_V0, 1u << 31);
5115 tcg_gen_shri_i64(cpu_V0, cpu_V0, 32);
5116 tcg_gen_trunc_i64_i32(tmp, cpu_V0);
5117 break;
9ee6e8bb
PB		 5118 default: abort();
5119 }
5120 }
ad69471c
PB		 5121 if (pass == 0) {
5122 tmp3 = tmp;
5123 } else {
5124 neon_store_reg(rd, 0, tmp3);
5125 neon_store_reg(rd, 1, tmp);
5126 }
9ee6e8bb
PB		 5127 } else {
5128 /* Write back the result. */
ad69471c 5129 neon_store_reg64(cpu_V0, rd + pass);
9ee6e8bb
PB		 5130 }
5131 }
5132 } else {
5133 /* Two registers and a scalar. */
5134 switch (op) {
5135 case 0: /* Integer VMLA scalar */
5136 case 1: /* Float VMLA scalar */
5137 case 4: /* Integer VMLS scalar */
5138 case 5: /* Floating point VMLS scalar */
5139 case 8: /* Integer VMUL scalar */
5140 case 9: /* Floating point VMUL scalar */
5141 case 12: /* VQDMULH scalar */
5142 case 13: /* VQRDMULH scalar */
dd8fbd78
FN		 5143 tmp = neon_get_scalar(size, rm);
5144 neon_store_scratch(0, tmp);
9ee6e8bb 5145 for (pass = 0; pass < (u ? 4 : 2); pass++) {
dd8fbd78
FN		 5146 tmp = neon_load_scratch(0);
5147 tmp2 = neon_load_reg(rn, pass);
9ee6e8bb
PB		 5148 if (op == 12) {
5149 if (size == 1) {
dd8fbd78 5150 gen_helper_neon_qdmulh_s16(tmp, cpu_env, tmp, tmp2);
9ee6e8bb 5151 } else {
dd8fbd78 5152 gen_helper_neon_qdmulh_s32(tmp, cpu_env, tmp, tmp2);
9ee6e8bb
PB		 5153 }
5154 } else if (op == 13) {
5155 if (size == 1) {
dd8fbd78 5156 gen_helper_neon_qrdmulh_s16(tmp, cpu_env, tmp, tmp2);
9ee6e8bb 5157 } else {
dd8fbd78 5158 gen_helper_neon_qrdmulh_s32(tmp, cpu_env, tmp, tmp2);
9ee6e8bb
PB		 5159 }
5160 } else if (op & 1) {
dd8fbd78 5161 gen_helper_neon_mul_f32(tmp, tmp, tmp2);
9ee6e8bb
PB		 5162 } else {
5163 switch (size) {
dd8fbd78
FN		 5164 case 0: gen_helper_neon_mul_u8(tmp, tmp, tmp2); break;
5165 case 1: gen_helper_neon_mul_u16(tmp, tmp, tmp2); break;
5166 case 2: tcg_gen_mul_i32(tmp, tmp, tmp2); break;
9ee6e8bb
PB		 5167 default: return 1;
5168 }
5169 }
dd8fbd78 5170 dead_tmp(tmp2);
9ee6e8bb
PB		 5171 if (op < 8) {
5172 /* Accumulate. */
dd8fbd78 5173 tmp2 = neon_load_reg(rd, pass);
9ee6e8bb
PB		 5174 switch (op) {
5175 case 0:
dd8fbd78 5176 gen_neon_add(size, tmp, tmp2);
9ee6e8bb
PB		 5177 break;
5178 case 1:
dd8fbd78 5179 gen_helper_neon_add_f32(tmp, tmp, tmp2);
9ee6e8bb
PB		 5180 break;
5181 case 4:
dd8fbd78 5182 gen_neon_rsb(size, tmp, tmp2);
9ee6e8bb
PB		 5183 break;
5184 case 5:
dd8fbd78 5185 gen_helper_neon_sub_f32(tmp, tmp2, tmp);
9ee6e8bb
PB		 5186 break;
5187 default:
5188 abort();
5189 }
dd8fbd78 5190 dead_tmp(tmp2);
9ee6e8bb 5191 }
dd8fbd78 5192 neon_store_reg(rd, pass, tmp);
9ee6e8bb
PB		 5193 }
5194 break;
5195 case 2: /* VMLAL sclar */
5196 case 3: /* VQDMLAL scalar */
5197 case 6: /* VMLSL scalar */
5198 case 7: /* VQDMLSL scalar */
5199 case 10: /* VMULL scalar */
5200 case 11: /* VQDMULL scalar */
ad69471c
PB		 5201 if (size == 0 && (op == 3 || op == 7 || op == 11))
5202 return 1;
5203
dd8fbd78
FN		 5204 tmp2 = neon_get_scalar(size, rm);
5205 tmp3 = neon_load_reg(rn, 1);
ad69471c 5206
9ee6e8bb 5207 for (pass = 0; pass < 2; pass++) {
ad69471c
PB		 5208 if (pass == 0) {
5209 tmp = neon_load_reg(rn, 0);
9ee6e8bb 5210 } else {
dd8fbd78 5211 tmp = tmp3;
9ee6e8bb 5212 }
ad69471c 5213 gen_neon_mull(cpu_V0, tmp, tmp2, size, u);
dd8fbd78 5214 dead_tmp(tmp);
9ee6e8bb 5215 if (op == 6 || op == 7) {
ad69471c
PB		 5216 gen_neon_negl(cpu_V0, size);
5217 }
5218 if (op != 11) {
5219 neon_load_reg64(cpu_V1, rd + pass);
9ee6e8bb 5220 }
9ee6e8bb
PB		 5221 switch (op) {
5222 case 2: case 6:
ad69471c 5223 gen_neon_addl(size);
9ee6e8bb
PB		 5224 break;
5225 case 3: case 7:
ad69471c
PB		 5226 gen_neon_addl_saturate(cpu_V0, cpu_V0, size);
5227 gen_neon_addl_saturate(cpu_V0, cpu_V1, size);
9ee6e8bb
PB		 5228 break;
5229 case 10:
5230 /* no-op */
5231 break;
5232 case 11:
ad69471c 5233 gen_neon_addl_saturate(cpu_V0, cpu_V0, size);
9ee6e8bb
PB		 5234 break;
5235 default:
5236 abort();
5237 }
ad69471c 5238 neon_store_reg64(cpu_V0, rd + pass);
9ee6e8bb 5239 }
dd8fbd78
FN		 5240
5241 dead_tmp(tmp2);
5242
9ee6e8bb
PB		 5243 break;
5244 default: /* 14 and 15 are RESERVED */
5245 return 1;
5246 }
5247 }
5248 } else { /* size == 3 */
5249 if (!u) {
5250 /* Extract. */
9ee6e8bb 5251 imm = (insn >> 8) & 0xf;
ad69471c
PB		 5252
5253 if (imm > 7 && !q)
5254 return 1;
5255
5256 if (imm == 0) {
5257 neon_load_reg64(cpu_V0, rn);
5258 if (q) {
5259 neon_load_reg64(cpu_V1, rn + 1);
9ee6e8bb 5260 }
ad69471c
PB		 5261 } else if (imm == 8) {
5262 neon_load_reg64(cpu_V0, rn + 1);
5263 if (q) {
5264 neon_load_reg64(cpu_V1, rm);
9ee6e8bb 5265 }
ad69471c 5266 } else if (q) {
a7812ae4 5267 tmp64 = tcg_temp_new_i64();
ad69471c
PB		 5268 if (imm < 8) {
5269 neon_load_reg64(cpu_V0, rn);
a7812ae4 5270 neon_load_reg64(tmp64, rn + 1);
ad69471c
PB		 5271 } else {
5272 neon_load_reg64(cpu_V0, rn + 1);
a7812ae4 5273 neon_load_reg64(tmp64, rm);
ad69471c
PB		 5274 }
5275 tcg_gen_shri_i64(cpu_V0, cpu_V0, (imm & 7) * 8);
a7812ae4 5276 tcg_gen_shli_i64(cpu_V1, tmp64, 64 - ((imm & 7) * 8));
ad69471c
PB		 5277 tcg_gen_or_i64(cpu_V0, cpu_V0, cpu_V1);
5278 if (imm < 8) {
5279 neon_load_reg64(cpu_V1, rm);
9ee6e8bb 5280 } else {
ad69471c
PB		 5281 neon_load_reg64(cpu_V1, rm + 1);
5282 imm -= 8;
9ee6e8bb 5283 }
ad69471c 5284 tcg_gen_shli_i64(cpu_V1, cpu_V1, 64 - (imm * 8));
a7812ae4
PB		 5285 tcg_gen_shri_i64(tmp64, tmp64, imm * 8);
5286 tcg_gen_or_i64(cpu_V1, cpu_V1, tmp64);
b75263d6 5287 tcg_temp_free_i64(tmp64);
ad69471c 5288 } else {
a7812ae4 5289 /* BUGFIX */
ad69471c 5290 neon_load_reg64(cpu_V0, rn);
a7812ae4 5291 tcg_gen_shri_i64(cpu_V0, cpu_V0, imm * 8);
ad69471c 5292 neon_load_reg64(cpu_V1, rm);
a7812ae4 5293 tcg_gen_shli_i64(cpu_V1, cpu_V1, 64 - (imm * 8));
ad69471c
PB		 5294 tcg_gen_or_i64(cpu_V0, cpu_V0, cpu_V1);
5295 }
5296 neon_store_reg64(cpu_V0, rd);
5297 if (q) {
5298 neon_store_reg64(cpu_V1, rd + 1);
9ee6e8bb
PB		 5299 }
5300 } else if ((insn & (1 << 11)) == 0) {
5301 /* Two register misc. */
5302 op = ((insn >> 12) & 0x30) | ((insn >> 7) & 0xf);
5303 size = (insn >> 18) & 3;
5304 switch (op) {
5305 case 0: /* VREV64 */
5306 if (size == 3)
5307 return 1;
5308 for (pass = 0; pass < (q ? 2 : 1); pass++) {
dd8fbd78
FN		 5309 tmp = neon_load_reg(rm, pass * 2);
5310 tmp2 = neon_load_reg(rm, pass * 2 + 1);
9ee6e8bb 5311 switch (size) {
dd8fbd78
FN		 5312 case 0: tcg_gen_bswap32_i32(tmp, tmp); break;
5313 case 1: gen_swap_half(tmp); break;
9ee6e8bb
PB		 5314 case 2: /* no-op */ break;
5315 default: abort();
5316 }
dd8fbd78 5317 neon_store_reg(rd, pass * 2 + 1, tmp);
9ee6e8bb 5318 if (size == 2) {
dd8fbd78 5319 neon_store_reg(rd, pass * 2, tmp2);
9ee6e8bb 5320 } else {
9ee6e8bb 5321 switch (size) {
dd8fbd78
FN		 5322 case 0: tcg_gen_bswap32_i32(tmp2, tmp2); break;
5323 case 1: gen_swap_half(tmp2); break;
9ee6e8bb
PB		 5324 default: abort();
5325 }
dd8fbd78 5326 neon_store_reg(rd, pass * 2, tmp2);
9ee6e8bb
PB		 5327 }
5328 }
5329 break;
5330 case 4: case 5: /* VPADDL */
5331 case 12: case 13: /* VPADAL */
9ee6e8bb
PB		 5332 if (size == 3)
5333 return 1;
ad69471c
PB		 5334 for (pass = 0; pass < q + 1; pass++) {
5335 tmp = neon_load_reg(rm, pass * 2);
5336 gen_neon_widen(cpu_V0, tmp, size, op & 1);
5337 tmp = neon_load_reg(rm, pass * 2 + 1);
5338 gen_neon_widen(cpu_V1, tmp, size, op & 1);
5339 switch (size) {
5340 case 0: gen_helper_neon_paddl_u16(CPU_V001); break;
5341 case 1: gen_helper_neon_paddl_u32(CPU_V001); break;
5342 case 2: tcg_gen_add_i64(CPU_V001); break;
5343 default: abort();
5344 }
9ee6e8bb
PB		 5345 if (op >= 12) {
5346 /* Accumulate. */
ad69471c
PB		 5347 neon_load_reg64(cpu_V1, rd + pass);
5348 gen_neon_addl(size);
9ee6e8bb 5349 }
ad69471c 5350 neon_store_reg64(cpu_V0, rd + pass);
9ee6e8bb
PB		 5351 }
5352 break;
5353 case 33: /* VTRN */
5354 if (size == 2) {
5355 for (n = 0; n < (q ? 4 : 2); n += 2) {
dd8fbd78
FN		 5356 tmp = neon_load_reg(rm, n);
5357 tmp2 = neon_load_reg(rd, n + 1);
5358 neon_store_reg(rm, n, tmp2);
5359 neon_store_reg(rd, n + 1, tmp);
9ee6e8bb
PB		 5360 }
5361 } else {
5362 goto elementwise;
5363 }
5364 break;
5365 case 34: /* VUZP */
5366 /* Reg Before After
5367 Rd A3 A2 A1 A0 B2 B0 A2 A0
5368 Rm B3 B2 B1 B0 B3 B1 A3 A1
5369 */
5370 if (size == 3)
5371 return 1;
5372 gen_neon_unzip(rd, q, 0, size);
5373 gen_neon_unzip(rm, q, 4, size);
5374 if (q) {
5375 static int unzip_order_q[8] =
5376 {0, 2, 4, 6, 1, 3, 5, 7};
5377 for (n = 0; n < 8; n++) {
5378 int reg = (n < 4) ? rd : rm;
dd8fbd78
FN		 5379 tmp = neon_load_scratch(unzip_order_q[n]);
5380 neon_store_reg(reg, n % 4, tmp);
9ee6e8bb
PB		 5381 }
5382 } else {
5383 static int unzip_order[4] =
5384 {0, 4, 1, 5};
5385 for (n = 0; n < 4; n++) {
5386 int reg = (n < 2) ? rd : rm;
dd8fbd78
FN		 5387 tmp = neon_load_scratch(unzip_order[n]);
5388 neon_store_reg(reg, n % 2, tmp);
9ee6e8bb
PB		 5389 }
5390 }
5391 break;
5392 case 35: /* VZIP */
5393 /* Reg Before After
5394 Rd A3 A2 A1 A0 B1 A1 B0 A0
5395 Rm B3 B2 B1 B0 B3 A3 B2 A2
5396 */
5397 if (size == 3)
5398 return 1;
5399 count = (q ? 4 : 2);
5400 for (n = 0; n < count; n++) {
dd8fbd78
FN		 5401 tmp = neon_load_reg(rd, n);
5402 tmp2 = neon_load_reg(rd, n);
9ee6e8bb 5403 switch (size) {
dd8fbd78
FN		 5404 case 0: gen_neon_zip_u8(tmp, tmp2); break;
5405 case 1: gen_neon_zip_u16(tmp, tmp2); break;
9ee6e8bb
PB		 5406 case 2: /* no-op */; break;
5407 default: abort();
5408 }
dd8fbd78
FN		 5409 neon_store_scratch(n * 2, tmp);
5410 neon_store_scratch(n * 2 + 1, tmp2);
9ee6e8bb
PB		 5411 }
5412 for (n = 0; n < count * 2; n++) {
5413 int reg = (n < count) ? rd : rm;
dd8fbd78
FN		 5414 tmp = neon_load_scratch(n);
5415 neon_store_reg(reg, n % count, tmp);
9ee6e8bb
PB		 5416 }
5417 break;
5418 case 36: case 37: /* VMOVN, VQMOVUN, VQMOVN */
ad69471c
PB		 5419 if (size == 3)
5420 return 1;
a50f5b91 5421 TCGV_UNUSED(tmp2);
9ee6e8bb 5422 for (pass = 0; pass < 2; pass++) {
ad69471c
PB		 5423 neon_load_reg64(cpu_V0, rm + pass);
5424 tmp = new_tmp();
9ee6e8bb 5425 if (op == 36 && q == 0) {
ad69471c 5426 gen_neon_narrow(size, tmp, cpu_V0);
9ee6e8bb 5427 } else if (q) {
ad69471c 5428 gen_neon_narrow_satu(size, tmp, cpu_V0);
9ee6e8bb 5429 } else {
ad69471c
PB		 5430 gen_neon_narrow_sats(size, tmp, cpu_V0);
5431 }
5432 if (pass == 0) {
5433 tmp2 = tmp;
5434 } else {
5435 neon_store_reg(rd, 0, tmp2);
5436 neon_store_reg(rd, 1, tmp);
9ee6e8bb 5437 }
9ee6e8bb
PB		 5438 }
5439 break;
5440 case 38: /* VSHLL */
ad69471c 5441 if (q || size == 3)
9ee6e8bb 5442 return 1;
ad69471c
PB		 5443 tmp = neon_load_reg(rm, 0);
5444 tmp2 = neon_load_reg(rm, 1);
9ee6e8bb 5445 for (pass = 0; pass < 2; pass++) {
ad69471c
PB		 5446 if (pass == 1)
5447 tmp = tmp2;
5448 gen_neon_widen(cpu_V0, tmp, size, 1);
30d11a2a 5449 tcg_gen_shli_i64(cpu_V0, cpu_V0, 8 << size);
ad69471c 5450 neon_store_reg64(cpu_V0, rd + pass);
9ee6e8bb
PB		 5451 }
5452 break;
60011498
PB		 5453 case 44: /* VCVT.F16.F32 */
5454 if (!arm_feature(env, ARM_FEATURE_VFP_FP16))
5455 return 1;
5456 tmp = new_tmp();
5457 tmp2 = new_tmp();
5458 tcg_gen_ld_f32(cpu_F0s, cpu_env, neon_reg_offset(rm, 0));
5459 gen_helper_vfp_fcvt_f32_to_f16(tmp, cpu_F0s, cpu_env);
5460 tcg_gen_ld_f32(cpu_F0s, cpu_env, neon_reg_offset(rm, 1));
5461 gen_helper_vfp_fcvt_f32_to_f16(tmp2, cpu_F0s, cpu_env);
5462 tcg_gen_shli_i32(tmp2, tmp2, 16);
5463 tcg_gen_or_i32(tmp2, tmp2, tmp);
5464 tcg_gen_ld_f32(cpu_F0s, cpu_env, neon_reg_offset(rm, 2));
5465 gen_helper_vfp_fcvt_f32_to_f16(tmp, cpu_F0s, cpu_env);
5466 tcg_gen_ld_f32(cpu_F0s, cpu_env, neon_reg_offset(rm, 3));
5467 neon_store_reg(rd, 0, tmp2);
5468 tmp2 = new_tmp();
5469 gen_helper_vfp_fcvt_f32_to_f16(tmp2, cpu_F0s, cpu_env);
5470 tcg_gen_shli_i32(tmp2, tmp2, 16);
5471 tcg_gen_or_i32(tmp2, tmp2, tmp);
5472 neon_store_reg(rd, 1, tmp2);
5473 dead_tmp(tmp);
5474 break;
5475 case 46: /* VCVT.F32.F16 */
5476 if (!arm_feature(env, ARM_FEATURE_VFP_FP16))
5477 return 1;
5478 tmp3 = new_tmp();
5479 tmp = neon_load_reg(rm, 0);
5480 tmp2 = neon_load_reg(rm, 1);
5481 tcg_gen_ext16u_i32(tmp3, tmp);
5482 gen_helper_vfp_fcvt_f16_to_f32(cpu_F0s, tmp3, cpu_env);
5483 tcg_gen_st_f32(cpu_F0s, cpu_env, neon_reg_offset(rd, 0));
5484 tcg_gen_shri_i32(tmp3, tmp, 16);
5485 gen_helper_vfp_fcvt_f16_to_f32(cpu_F0s, tmp3, cpu_env);
5486 tcg_gen_st_f32(cpu_F0s, cpu_env, neon_reg_offset(rd, 1));
5487 dead_tmp(tmp);
5488 tcg_gen_ext16u_i32(tmp3, tmp2);
5489 gen_helper_vfp_fcvt_f16_to_f32(cpu_F0s, tmp3, cpu_env);
5490 tcg_gen_st_f32(cpu_F0s, cpu_env, neon_reg_offset(rd, 2));
5491 tcg_gen_shri_i32(tmp3, tmp2, 16);
5492 gen_helper_vfp_fcvt_f16_to_f32(cpu_F0s, tmp3, cpu_env);
5493 tcg_gen_st_f32(cpu_F0s, cpu_env, neon_reg_offset(rd, 3));
5494 dead_tmp(tmp2);
5495 dead_tmp(tmp3);
5496 break;
9ee6e8bb
PB		 5497 default:
5498 elementwise:
5499 for (pass = 0; pass < (q ? 4 : 2); pass++) {
5500 if (op == 30 || op == 31 || op >= 58) {
4373f3ce
PB		 5501 tcg_gen_ld_f32(cpu_F0s, cpu_env,
5502 neon_reg_offset(rm, pass));
dd8fbd78 5503 TCGV_UNUSED(tmp);
9ee6e8bb 5504 } else {
dd8fbd78 5505 tmp = neon_load_reg(rm, pass);
9ee6e8bb
PB		 5506 }
5507 switch (op) {
5508 case 1: /* VREV32 */
5509 switch (size) {
dd8fbd78
FN		 5510 case 0: tcg_gen_bswap32_i32(tmp, tmp); break;
5511 case 1: gen_swap_half(tmp); break;
9ee6e8bb
PB		 5512 default: return 1;
5513 }
5514 break;
5515 case 2: /* VREV16 */
5516 if (size != 0)
5517 return 1;
dd8fbd78 5518 gen_rev16(tmp);
9ee6e8bb 5519 break;
9ee6e8bb
PB		 5520 case 8: /* CLS */
5521 switch (size) {
dd8fbd78
FN		 5522 case 0: gen_helper_neon_cls_s8(tmp, tmp); break;
5523 case 1: gen_helper_neon_cls_s16(tmp, tmp); break;
5524 case 2: gen_helper_neon_cls_s32(tmp, tmp); break;
9ee6e8bb
PB		 5525 default: return 1;
5526 }
5527 break;
5528 case 9: /* CLZ */
5529 switch (size) {
dd8fbd78
FN		 5530 case 0: gen_helper_neon_clz_u8(tmp, tmp); break;
5531 case 1: gen_helper_neon_clz_u16(tmp, tmp); break;
5532 case 2: gen_helper_clz(tmp, tmp); break;
9ee6e8bb
PB		 5533 default: return 1;
5534 }
5535 break;
5536 case 10: /* CNT */
5537 if (size != 0)
5538 return 1;
dd8fbd78 5539 gen_helper_neon_cnt_u8(tmp, tmp);
9ee6e8bb
PB		 5540 break;
5541 case 11: /* VNOT */
5542 if (size != 0)
5543 return 1;
dd8fbd78 5544 tcg_gen_not_i32(tmp, tmp);
9ee6e8bb
PB		 5545 break;
5546 case 14: /* VQABS */
5547 switch (size) {
dd8fbd78
FN		 5548 case 0: gen_helper_neon_qabs_s8(tmp, cpu_env, tmp); break;
5549 case 1: gen_helper_neon_qabs_s16(tmp, cpu_env, tmp); break;
5550 case 2: gen_helper_neon_qabs_s32(tmp, cpu_env, tmp); break;
9ee6e8bb
PB		 5551 default: return 1;
5552 }
5553 break;
5554 case 15: /* VQNEG */
5555 switch (size) {
dd8fbd78
FN		 5556 case 0: gen_helper_neon_qneg_s8(tmp, cpu_env, tmp); break;
5557 case 1: gen_helper_neon_qneg_s16(tmp, cpu_env, tmp); break;
5558 case 2: gen_helper_neon_qneg_s32(tmp, cpu_env, tmp); break;
9ee6e8bb
PB		 5559 default: return 1;
5560 }
5561 break;
5562 case 16: case 19: /* VCGT #0, VCLE #0 */
dd8fbd78 5563 tmp2 = tcg_const_i32(0);
9ee6e8bb 5564 switch(size) {
dd8fbd78
FN		 5565 case 0: gen_helper_neon_cgt_s8(tmp, tmp, tmp2); break;
5566 case 1: gen_helper_neon_cgt_s16(tmp, tmp, tmp2); break;
5567 case 2: gen_helper_neon_cgt_s32(tmp, tmp, tmp2); break;
9ee6e8bb
PB		 5568 default: return 1;
5569 }
dd8fbd78 5570 tcg_temp_free(tmp2);
9ee6e8bb 5571 if (op == 19)
dd8fbd78 5572 tcg_gen_not_i32(tmp, tmp);
9ee6e8bb
PB		 5573 break;
5574 case 17: case 20: /* VCGE #0, VCLT #0 */
dd8fbd78 5575 tmp2 = tcg_const_i32(0);
9ee6e8bb 5576 switch(size) {
dd8fbd78
FN		 5577 case 0: gen_helper_neon_cge_s8(tmp, tmp, tmp2); break;
5578 case 1: gen_helper_neon_cge_s16(tmp, tmp, tmp2); break;
5579 case 2: gen_helper_neon_cge_s32(tmp, tmp, tmp2); break;
9ee6e8bb
PB		 5580 default: return 1;
5581 }
dd8fbd78 5582 tcg_temp_free(tmp2);
9ee6e8bb 5583 if (op == 20)
dd8fbd78 5584 tcg_gen_not_i32(tmp, tmp);
9ee6e8bb
PB		 5585 break;
5586 case 18: /* VCEQ #0 */
dd8fbd78 5587 tmp2 = tcg_const_i32(0);
9ee6e8bb 5588 switch(size) {
dd8fbd78
FN		 5589 case 0: gen_helper_neon_ceq_u8(tmp, tmp, tmp2); break;
5590 case 1: gen_helper_neon_ceq_u16(tmp, tmp, tmp2); break;
5591 case 2: gen_helper_neon_ceq_u32(tmp, tmp, tmp2); break;
9ee6e8bb
PB		 5592 default: return 1;
5593 }
dd8fbd78 5594 tcg_temp_free(tmp2);
9ee6e8bb
PB		 5595 break;
5596 case 22: /* VABS */
5597 switch(size) {
dd8fbd78
FN		 5598 case 0: gen_helper_neon_abs_s8(tmp, tmp); break;
5599 case 1: gen_helper_neon_abs_s16(tmp, tmp); break;
5600 case 2: tcg_gen_abs_i32(tmp, tmp); break;
9ee6e8bb
PB		 5601 default: return 1;
5602 }
5603 break;
5604 case 23: /* VNEG */
ad69471c
PB		 5605 if (size == 3)
5606 return 1;
dd8fbd78
FN		 5607 tmp2 = tcg_const_i32(0);
5608 gen_neon_rsb(size, tmp, tmp2);
5609 tcg_temp_free(tmp2);
9ee6e8bb
PB		 5610 break;
5611 case 24: case 27: /* Float VCGT #0, Float VCLE #0 */
dd8fbd78
FN		 5612 tmp2 = tcg_const_i32(0);
5613 gen_helper_neon_cgt_f32(tmp, tmp, tmp2);
5614 tcg_temp_free(tmp2);
9ee6e8bb 5615 if (op == 27)
dd8fbd78 5616 tcg_gen_not_i32(tmp, tmp);
9ee6e8bb
PB		 5617 break;
5618 case 25: case 28: /* Float VCGE #0, Float VCLT #0 */
dd8fbd78
FN		 5619 tmp2 = tcg_const_i32(0);
5620 gen_helper_neon_cge_f32(tmp, tmp, tmp2);
5621 tcg_temp_free(tmp2);
9ee6e8bb 5622 if (op == 28)
dd8fbd78 5623 tcg_gen_not_i32(tmp, tmp);
9ee6e8bb
PB		 5624 break;
5625 case 26: /* Float VCEQ #0 */
dd8fbd78
FN		 5626 tmp2 = tcg_const_i32(0);
5627 gen_helper_neon_ceq_f32(tmp, tmp, tmp2);
5628 tcg_temp_free(tmp2);
9ee6e8bb
PB		 5629 break;
5630 case 30: /* Float VABS */
4373f3ce 5631 gen_vfp_abs(0);
9ee6e8bb
PB		 5632 break;
5633 case 31: /* Float VNEG */
4373f3ce 5634 gen_vfp_neg(0);
9ee6e8bb
PB		 5635 break;
5636 case 32: /* VSWP */
dd8fbd78
FN		 5637 tmp2 = neon_load_reg(rd, pass);
5638 neon_store_reg(rm, pass, tmp2);
9ee6e8bb
PB		 5639 break;
5640 case 33: /* VTRN */
dd8fbd78 5641 tmp2 = neon_load_reg(rd, pass);
9ee6e8bb 5642 switch (size) {
dd8fbd78
FN		 5643 case 0: gen_neon_trn_u8(tmp, tmp2); break;
5644 case 1: gen_neon_trn_u16(tmp, tmp2); break;
9ee6e8bb
PB		 5645 case 2: abort();
5646 default: return 1;
5647 }
dd8fbd78 5648 neon_store_reg(rm, pass, tmp2);
9ee6e8bb
PB		 5649 break;
5650 case 56: /* Integer VRECPE */
dd8fbd78 5651 gen_helper_recpe_u32(tmp, tmp, cpu_env);
9ee6e8bb
PB		 5652 break;
5653 case 57: /* Integer VRSQRTE */
dd8fbd78 5654 gen_helper_rsqrte_u32(tmp, tmp, cpu_env);
9ee6e8bb
PB		 5655 break;
5656 case 58: /* Float VRECPE */
4373f3ce 5657 gen_helper_recpe_f32(cpu_F0s, cpu_F0s, cpu_env);
9ee6e8bb
PB		 5658 break;
5659 case 59: /* Float VRSQRTE */
4373f3ce 5660 gen_helper_rsqrte_f32(cpu_F0s, cpu_F0s, cpu_env);
9ee6e8bb
PB		 5661 break;
5662 case 60: /* VCVT.F32.S32 */
4373f3ce 5663 gen_vfp_tosiz(0);
9ee6e8bb
PB		 5664 break;
5665 case 61: /* VCVT.F32.U32 */
4373f3ce 5666 gen_vfp_touiz(0);
9ee6e8bb
PB		 5667 break;
5668 case 62: /* VCVT.S32.F32 */
4373f3ce 5669 gen_vfp_sito(0);
9ee6e8bb
PB		 5670 break;
5671 case 63: /* VCVT.U32.F32 */
4373f3ce 5672 gen_vfp_uito(0);
9ee6e8bb
PB		 5673 break;
5674 default:
5675 /* Reserved: 21, 29, 39-56 */
5676 return 1;
5677 }
5678 if (op == 30 || op == 31 || op >= 58) {
4373f3ce
PB		 5679 tcg_gen_st_f32(cpu_F0s, cpu_env,
5680 neon_reg_offset(rd, pass));
9ee6e8bb 5681 } else {
dd8fbd78 5682 neon_store_reg(rd, pass, tmp);
9ee6e8bb
PB		 5683 }
5684 }
5685 break;
5686 }
5687 } else if ((insn & (1 << 10)) == 0) {
5688 /* VTBL, VTBX. */
3018f259 5689 n = ((insn >> 5) & 0x18) + 8;
9ee6e8bb 5690 if (insn & (1 << 6)) {
8f8e3aa4 5691 tmp = neon_load_reg(rd, 0);
9ee6e8bb 5692 } else {
8f8e3aa4
PB		 5693 tmp = new_tmp();
5694 tcg_gen_movi_i32(tmp, 0);
9ee6e8bb 5695 }
8f8e3aa4 5696 tmp2 = neon_load_reg(rm, 0);
b75263d6
JR		 5697 tmp4 = tcg_const_i32(rn);
5698 tmp5 = tcg_const_i32(n);
5699 gen_helper_neon_tbl(tmp2, tmp2, tmp, tmp4, tmp5);
3018f259 5700 dead_tmp(tmp);
9ee6e8bb 5701 if (insn & (1 << 6)) {
8f8e3aa4 5702 tmp = neon_load_reg(rd, 1);
9ee6e8bb 5703 } else {
8f8e3aa4
PB		 5704 tmp = new_tmp();
5705 tcg_gen_movi_i32(tmp, 0);
9ee6e8bb 5706 }
8f8e3aa4 5707 tmp3 = neon_load_reg(rm, 1);
b75263d6 5708 gen_helper_neon_tbl(tmp3, tmp3, tmp, tmp4, tmp5);
25aeb69b
JR		 5709 tcg_temp_free_i32(tmp5);
5710 tcg_temp_free_i32(tmp4);
8f8e3aa4 5711 neon_store_reg(rd, 0, tmp2);
3018f259
PB		 5712 neon_store_reg(rd, 1, tmp3);
5713 dead_tmp(tmp);
9ee6e8bb
PB		 5714 } else if ((insn & 0x380) == 0) {
5715 /* VDUP */
5716 if (insn & (1 << 19)) {
dd8fbd78 5717 tmp = neon_load_reg(rm, 1);
9ee6e8bb 5718 } else {
dd8fbd78 5719 tmp = neon_load_reg(rm, 0);
9ee6e8bb
PB		 5720 }
5721 if (insn & (1 << 16)) {
dd8fbd78 5722 gen_neon_dup_u8(tmp, ((insn >> 17) & 3) * 8);
9ee6e8bb
PB		 5723 } else if (insn & (1 << 17)) {
5724 if ((insn >> 18) & 1)
dd8fbd78 5725 gen_neon_dup_high16(tmp);
9ee6e8bb 5726 else
dd8fbd78 5727 gen_neon_dup_low16(tmp);
9ee6e8bb
PB		 5728 }
5729 for (pass = 0; pass < (q ? 4 : 2); pass++) {
dd8fbd78
FN		 5730 tmp2 = new_tmp();
5731 tcg_gen_mov_i32(tmp2, tmp);
5732 neon_store_reg(rd, pass, tmp2);
9ee6e8bb 5733 }
dd8fbd78 5734 dead_tmp(tmp);
9ee6e8bb
PB		 5735 } else {
5736 return 1;
5737 }
5738 }
5739 }
5740 return 0;
5741}
5742
fe1479c3
PB		 5743static int disas_cp14_read(CPUState * env, DisasContext *s, uint32_t insn)
5744{
5745 int crn = (insn >> 16) & 0xf;
5746 int crm = insn & 0xf;
5747 int op1 = (insn >> 21) & 7;
5748 int op2 = (insn >> 5) & 7;
5749 int rt = (insn >> 12) & 0xf;
5750 TCGv tmp;
5751
5752 if (arm_feature(env, ARM_FEATURE_THUMB2EE)) {
5753 if (op1 == 6 && crn == 0 && crm == 0 && op2 == 0) {
5754 /* TEECR */
5755 if (IS_USER(s))
5756 return 1;
5757 tmp = load_cpu_field(teecr);
5758 store_reg(s, rt, tmp);
5759 return 0;
5760 }
5761 if (op1 == 6 && crn == 1 && crm == 0 && op2 == 0) {
5762 /* TEEHBR */
5763 if (IS_USER(s) && (env->teecr & 1))
5764 return 1;
5765 tmp = load_cpu_field(teehbr);
5766 store_reg(s, rt, tmp);
5767 return 0;
5768 }
5769 }
5770 fprintf(stderr, "Unknown cp14 read op1:%d crn:%d crm:%d op2:%d\n",
5771 op1, crn, crm, op2);
5772 return 1;
5773}
5774
5775static int disas_cp14_write(CPUState * env, DisasContext *s, uint32_t insn)
5776{
5777 int crn = (insn >> 16) & 0xf;
5778 int crm = insn & 0xf;
5779 int op1 = (insn >> 21) & 7;
5780 int op2 = (insn >> 5) & 7;
5781 int rt = (insn >> 12) & 0xf;
5782 TCGv tmp;
5783
5784 if (arm_feature(env, ARM_FEATURE_THUMB2EE)) {
5785 if (op1 == 6 && crn == 0 && crm == 0 && op2 == 0) {
5786 /* TEECR */
5787 if (IS_USER(s))
5788 return 1;
5789 tmp = load_reg(s, rt);
5790 gen_helper_set_teecr(cpu_env, tmp);
5791 dead_tmp(tmp);
5792 return 0;
5793 }
5794 if (op1 == 6 && crn == 1 && crm == 0 && op2 == 0) {
5795 /* TEEHBR */
5796 if (IS_USER(s) && (env->teecr & 1))
5797 return 1;
5798 tmp = load_reg(s, rt);
5799 store_cpu_field(tmp, teehbr);
5800 return 0;
5801 }
5802 }
5803 fprintf(stderr, "Unknown cp14 write op1:%d crn:%d crm:%d op2:%d\n",
5804 op1, crn, crm, op2);
5805 return 1;
5806}
5807
9ee6e8bb
PB		 5808static int disas_coproc_insn(CPUState * env, DisasContext *s, uint32_t insn)
5809{
5810 int cpnum;
5811
5812 cpnum = (insn >> 8) & 0xf;
5813 if (arm_feature(env, ARM_FEATURE_XSCALE)
5814 && ((env->cp15.c15_cpar ^ 0x3fff) & (1 << cpnum)))
5815 return 1;
5816
5817 switch (cpnum) {
5818 case 0:
5819 case 1:
5820 if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
5821 return disas_iwmmxt_insn(env, s, insn);
5822 } else if (arm_feature(env, ARM_FEATURE_XSCALE)) {
5823 return disas_dsp_insn(env, s, insn);
5824 }
5825 return 1;
5826 case 10:
5827 case 11:
5828 return disas_vfp_insn (env, s, insn);
fe1479c3
PB		 5829 case 14:
5830 /* Coprocessors 7-15 are architecturally reserved by ARM.
5831 Unfortunately Intel decided to ignore this. */
5832 if (arm_feature(env, ARM_FEATURE_XSCALE))
5833 goto board;
5834 if (insn & (1 << 20))
5835 return disas_cp14_read(env, s, insn);
5836 else
5837 return disas_cp14_write(env, s, insn);
9ee6e8bb
PB		 5838 case 15:
5839 return disas_cp15_insn (env, s, insn);
5840 default:
fe1479c3 5841 board:
9ee6e8bb
PB		 5842 /* Unknown coprocessor. See if the board has hooked it. */
5843 return disas_cp_insn (env, s, insn);
5844 }
5845}
5846
5e3f878a
PB		 5847
5848/* Store a 64-bit value to a register pair. Clobbers val. */
a7812ae4 5849static void gen_storeq_reg(DisasContext *s, int rlow, int rhigh, TCGv_i64 val)
5e3f878a
PB		 5850{
5851 TCGv tmp;
5852 tmp = new_tmp();
5853 tcg_gen_trunc_i64_i32(tmp, val);
5854 store_reg(s, rlow, tmp);
5855 tmp = new_tmp();
5856 tcg_gen_shri_i64(val, val, 32);
5857 tcg_gen_trunc_i64_i32(tmp, val);
5858 store_reg(s, rhigh, tmp);
5859}
5860
5861/* load a 32-bit value from a register and perform a 64-bit accumulate. */
a7812ae4 5862static void gen_addq_lo(DisasContext *s, TCGv_i64 val, int rlow)
5e3f878a 5863{
a7812ae4 5864 TCGv_i64 tmp;
5e3f878a
PB		 5865 TCGv tmp2;
5866
36aa55dc 5867 /* Load value and extend to 64 bits. */
a7812ae4 5868 tmp = tcg_temp_new_i64();
5e3f878a
PB		 5869 tmp2 = load_reg(s, rlow);
5870 tcg_gen_extu_i32_i64(tmp, tmp2);
5871 dead_tmp(tmp2);
5872 tcg_gen_add_i64(val, val, tmp);
b75263d6 5873 tcg_temp_free_i64(tmp);
5e3f878a
PB		 5874}
5875
5876/* load and add a 64-bit value from a register pair. */
a7812ae4 5877static void gen_addq(DisasContext *s, TCGv_i64 val, int rlow, int rhigh)
5e3f878a 5878{
a7812ae4 5879 TCGv_i64 tmp;
36aa55dc
PB		 5880 TCGv tmpl;
5881 TCGv tmph;
5e3f878a
PB		 5882
5883 /* Load 64-bit value rd:rn. */
36aa55dc
PB		 5884 tmpl = load_reg(s, rlow);
5885 tmph = load_reg(s, rhigh);
a7812ae4 5886 tmp = tcg_temp_new_i64();
36aa55dc
PB		 5887 tcg_gen_concat_i32_i64(tmp, tmpl, tmph);
5888 dead_tmp(tmpl);
5889 dead_tmp(tmph);
5e3f878a 5890 tcg_gen_add_i64(val, val, tmp);
b75263d6 5891 tcg_temp_free_i64(tmp);
5e3f878a
PB		 5892}
5893
5894/* Set N and Z flags from a 64-bit value. */
a7812ae4 5895static void gen_logicq_cc(TCGv_i64 val)
5e3f878a
PB		 5896{
5897 TCGv tmp = new_tmp();
5898 gen_helper_logicq_cc(tmp, val);
6fbe23d5
PB		 5899 gen_logic_CC(tmp);
5900 dead_tmp(tmp);
5e3f878a
PB		 5901}
5902
426f5abc
PB		 5903/* Load/Store exclusive instructions are implemented by remembering
5904 the value/address loaded, and seeing if these are the same
5905 when the store is performed. This should be is sufficient to implement
5906 the architecturally mandated semantics, and avoids having to monitor
5907 regular stores.
5908
5909 In system emulation mode only one CPU will be running at once, so
5910 this sequence is effectively atomic. In user emulation mode we
5911 throw an exception and handle the atomic operation elsewhere. */
5912static void gen_load_exclusive(DisasContext *s, int rt, int rt2,
5913 TCGv addr, int size)
5914{
5915 TCGv tmp;
5916
5917 switch (size) {
5918 case 0:
5919 tmp = gen_ld8u(addr, IS_USER(s));
5920 break;
5921 case 1:
5922 tmp = gen_ld16u(addr, IS_USER(s));
5923 break;
5924 case 2:
5925 case 3:
5926 tmp = gen_ld32(addr, IS_USER(s));
5927 break;
5928 default:
5929 abort();
5930 }
5931 tcg_gen_mov_i32(cpu_exclusive_val, tmp);
5932 store_reg(s, rt, tmp);
5933 if (size == 3) {
2c9adbda
PM		 5934 TCGv tmp2 = new_tmp();
5935 tcg_gen_addi_i32(tmp2, addr, 4);
5936 tmp = gen_ld32(tmp2, IS_USER(s));
5937 dead_tmp(tmp2);
426f5abc
PB		 5938 tcg_gen_mov_i32(cpu_exclusive_high, tmp);
5939 store_reg(s, rt2, tmp);
5940 }
5941 tcg_gen_mov_i32(cpu_exclusive_addr, addr);
5942}
5943
5944static void gen_clrex(DisasContext *s)
5945{
5946 tcg_gen_movi_i32(cpu_exclusive_addr, -1);
5947}
5948
5949#ifdef CONFIG_USER_ONLY
5950static void gen_store_exclusive(DisasContext *s, int rd, int rt, int rt2,
5951 TCGv addr, int size)
5952{
5953 tcg_gen_mov_i32(cpu_exclusive_test, addr);
5954 tcg_gen_movi_i32(cpu_exclusive_info,
5955 size | (rd << 4) | (rt << 8) | (rt2 << 12));
5956 gen_set_condexec(s);
5957 gen_set_pc_im(s->pc - 4);
5958 gen_exception(EXCP_STREX);
5959 s->is_jmp = DISAS_JUMP;
5960}
5961#else
5962static void gen_store_exclusive(DisasContext *s, int rd, int rt, int rt2,
5963 TCGv addr, int size)
5964{
5965 TCGv tmp;
5966 int done_label;
5967 int fail_label;
5968
5969 /* if (env->exclusive_addr == addr && env->exclusive_val == [addr]) {
5970 [addr] = {Rt};
5971 {Rd} = 0;
5972 } else {
5973 {Rd} = 1;
5974 } */
5975 fail_label = gen_new_label();
5976 done_label = gen_new_label();
5977 tcg_gen_brcond_i32(TCG_COND_NE, addr, cpu_exclusive_addr, fail_label);
5978 switch (size) {
5979 case 0:
5980 tmp = gen_ld8u(addr, IS_USER(s));
5981 break;
5982 case 1:
5983 tmp = gen_ld16u(addr, IS_USER(s));
5984 break;
5985 case 2:
5986 case 3:
5987 tmp = gen_ld32(addr, IS_USER(s));
5988 break;
5989 default:
5990 abort();
5991 }
5992 tcg_gen_brcond_i32(TCG_COND_NE, tmp, cpu_exclusive_val, fail_label);
5993 dead_tmp(tmp);
5994 if (size == 3) {
5995 TCGv tmp2 = new_tmp();
5996 tcg_gen_addi_i32(tmp2, addr, 4);
2c9adbda 5997 tmp = gen_ld32(tmp2, IS_USER(s));
426f5abc
PB		 5998 dead_tmp(tmp2);
5999 tcg_gen_brcond_i32(TCG_COND_NE, tmp, cpu_exclusive_high, fail_label);
6000 dead_tmp(tmp);
6001 }
6002 tmp = load_reg(s, rt);
6003 switch (size) {
6004 case 0:
6005 gen_st8(tmp, addr, IS_USER(s));
6006 break;
6007 case 1:
6008 gen_st16(tmp, addr, IS_USER(s));
6009 break;
6010 case 2:
6011 case 3:
6012 gen_st32(tmp, addr, IS_USER(s));
6013 break;
6014 default:
6015 abort();
6016 }
6017 if (size == 3) {
6018 tcg_gen_addi_i32(addr, addr, 4);
6019 tmp = load_reg(s, rt2);
6020 gen_st32(tmp, addr, IS_USER(s));
6021 }
6022 tcg_gen_movi_i32(cpu_R[rd], 0);
6023 tcg_gen_br(done_label);
6024 gen_set_label(fail_label);
6025 tcg_gen_movi_i32(cpu_R[rd], 1);
6026 gen_set_label(done_label);
6027 tcg_gen_movi_i32(cpu_exclusive_addr, -1);
6028}
6029#endif
6030
9ee6e8bb
PB		 6031static void disas_arm_insn(CPUState * env, DisasContext *s)
6032{
6033 unsigned int cond, insn, val, op1, i, shift, rm, rs, rn, rd, sh;
b26eefb6 6034 TCGv tmp;
3670669c 6035 TCGv tmp2;
6ddbc6e4 6036 TCGv tmp3;
b0109805 6037 TCGv addr;
a7812ae4 6038 TCGv_i64 tmp64;
9ee6e8bb
PB		 6039
6040 insn = ldl_code(s->pc);
6041 s->pc += 4;
6042
6043 /* M variants do not implement ARM mode. */
6044 if (IS_M(env))
6045 goto illegal_op;
6046 cond = insn >> 28;
6047 if (cond == 0xf){
6048 /* Unconditional instructions. */
6049 if (((insn >> 25) & 7) == 1) {
6050 /* NEON Data processing. */
6051 if (!arm_feature(env, ARM_FEATURE_NEON))
6052 goto illegal_op;
6053
6054 if (disas_neon_data_insn(env, s, insn))
6055 goto illegal_op;
6056 return;
6057 }
6058 if ((insn & 0x0f100000) == 0x04000000) {
6059 /* NEON load/store. */
6060 if (!arm_feature(env, ARM_FEATURE_NEON))
6061 goto illegal_op;
6062
6063 if (disas_neon_ls_insn(env, s, insn))
6064 goto illegal_op;
6065 return;
6066 }
6067 if ((insn & 0x0d70f000) == 0x0550f000)
6068 return; /* PLD */
6069 else if ((insn & 0x0ffffdff) == 0x01010000) {
6070 ARCH(6);
6071 /* setend */
6072 if (insn & (1 << 9)) {
6073 /* BE8 mode not implemented. */
6074 goto illegal_op;
6075 }
6076 return;
6077 } else if ((insn & 0x0fffff00) == 0x057ff000) {
6078 switch ((insn >> 4) & 0xf) {
6079 case 1: /* clrex */
6080 ARCH(6K);
426f5abc 6081 gen_clrex(s);
9ee6e8bb
PB		 6082 return;
6083 case 4: /* dsb */
6084 case 5: /* dmb */
6085 case 6: /* isb */
6086 ARCH(7);
6087 /* We don't emulate caches so these are a no-op. */
6088 return;
6089 default:
6090 goto illegal_op;
6091 }
6092 } else if ((insn & 0x0e5fffe0) == 0x084d0500) {
6093 /* srs */
c67b6b71 6094 int32_t offset;
9ee6e8bb
PB		 6095 if (IS_USER(s))
6096 goto illegal_op;
6097 ARCH(6);
6098 op1 = (insn & 0x1f);
6099 if (op1 == (env->uncached_cpsr & CPSR_M)) {
b0109805 6100 addr = load_reg(s, 13);
9ee6e8bb 6101 } else {
b0109805 6102 addr = new_tmp();
b75263d6
JR		 6103 tmp = tcg_const_i32(op1);
6104 gen_helper_get_r13_banked(addr, cpu_env, tmp);
6105 tcg_temp_free_i32(tmp);
9ee6e8bb
PB		 6106 }
6107 i = (insn >> 23) & 3;
6108 switch (i) {
6109 case 0: offset = -4; break; /* DA */
c67b6b71
FN		 6110 case 1: offset = 0; break; /* IA */
6111 case 2: offset = -8; break; /* DB */
9ee6e8bb
PB		 6112 case 3: offset = 4; break; /* IB */
6113 default: abort();
6114 }
6115 if (offset)
b0109805
PB		 6116 tcg_gen_addi_i32(addr, addr, offset);
6117 tmp = load_reg(s, 14);
6118 gen_st32(tmp, addr, 0);
c67b6b71 6119 tmp = load_cpu_field(spsr);
b0109805
PB		 6120 tcg_gen_addi_i32(addr, addr, 4);
6121 gen_st32(tmp, addr, 0);
9ee6e8bb
PB		 6122 if (insn & (1 << 21)) {
6123 /* Base writeback. */
6124 switch (i) {
6125 case 0: offset = -8; break;
c67b6b71
FN		 6126 case 1: offset = 4; break;
6127 case 2: offset = -4; break;
9ee6e8bb
PB		 6128 case 3: offset = 0; break;
6129 default: abort();
6130 }
6131 if (offset)
c67b6b71 6132 tcg_gen_addi_i32(addr, addr, offset);
9ee6e8bb 6133 if (op1 == (env->uncached_cpsr & CPSR_M)) {
c67b6b71 6134 store_reg(s, 13, addr);
9ee6e8bb 6135 } else {
b75263d6
JR		 6136 tmp = tcg_const_i32(op1);
6137 gen_helper_set_r13_banked(cpu_env, tmp, addr);
6138 tcg_temp_free_i32(tmp);
c67b6b71 6139 dead_tmp(addr);
9ee6e8bb 6140 }
b0109805
PB		 6141 } else {
6142 dead_tmp(addr);
9ee6e8bb 6143 }
a990f58f 6144 return;
ea825eee 6145 } else if ((insn & 0x0e50ffe0) == 0x08100a00) {
9ee6e8bb 6146 /* rfe */
c67b6b71 6147 int32_t offset;
9ee6e8bb
PB		 6148 if (IS_USER(s))
6149 goto illegal_op;
6150 ARCH(6);
6151 rn = (insn >> 16) & 0xf;
b0109805 6152 addr = load_reg(s, rn);
9ee6e8bb
PB		 6153 i = (insn >> 23) & 3;
6154 switch (i) {
b0109805 6155 case 0: offset = -4; break; /* DA */
c67b6b71
FN		 6156 case 1: offset = 0; break; /* IA */
6157 case 2: offset = -8; break; /* DB */
b0109805 6158 case 3: offset = 4; break; /* IB */
9ee6e8bb
PB		 6159 default: abort();
6160 }
6161 if (offset)
b0109805
PB		 6162 tcg_gen_addi_i32(addr, addr, offset);
6163 /* Load PC into tmp and CPSR into tmp2. */
6164 tmp = gen_ld32(addr, 0);
6165 tcg_gen_addi_i32(addr, addr, 4);
6166 tmp2 = gen_ld32(addr, 0);
9ee6e8bb
PB		 6167 if (insn & (1 << 21)) {
6168 /* Base writeback. */
6169 switch (i) {
b0109805 6170 case 0: offset = -8; break;
c67b6b71
FN		 6171 case 1: offset = 4; break;
6172 case 2: offset = -4; break;
b0109805 6173 case 3: offset = 0; break;
9ee6e8bb
PB		 6174 default: abort();
6175 }
6176 if (offset)
b0109805
PB		 6177 tcg_gen_addi_i32(addr, addr, offset);
6178 store_reg(s, rn, addr);
6179 } else {
6180 dead_tmp(addr);
9ee6e8bb 6181 }
b0109805 6182 gen_rfe(s, tmp, tmp2);
c67b6b71 6183 return;
9ee6e8bb
PB		 6184 } else if ((insn & 0x0e000000) == 0x0a000000) {
6185 /* branch link and change to thumb (blx <offset>) */
6186 int32_t offset;
6187
6188 val = (uint32_t)s->pc;
d9ba4830
PB		 6189 tmp = new_tmp();
6190 tcg_gen_movi_i32(tmp, val);
6191 store_reg(s, 14, tmp);
9ee6e8bb
PB		 6192 /* Sign-extend the 24-bit offset */
6193 offset = (((int32_t)insn) << 8) >> 8;
6194 /* offset * 4 + bit24 * 2 + (thumb bit) */
6195 val += (offset << 2) | ((insn >> 23) & 2) | 1;
6196 /* pipeline offset */
6197 val += 4;
d9ba4830 6198 gen_bx_im(s, val);
9ee6e8bb
PB		 6199 return;
6200 } else if ((insn & 0x0e000f00) == 0x0c000100) {
6201 if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
6202 /* iWMMXt register transfer. */
6203 if (env->cp15.c15_cpar & (1 << 1))
6204 if (!disas_iwmmxt_insn(env, s, insn))
6205 return;
6206 }
6207 } else if ((insn & 0x0fe00000) == 0x0c400000) {
6208 /* Coprocessor double register transfer. */
6209 } else if ((insn & 0x0f000010) == 0x0e000010) {
6210 /* Additional coprocessor register transfer. */
7997d92f 6211 } else if ((insn & 0x0ff10020) == 0x01000000) {
9ee6e8bb
PB		 6212 uint32_t mask;
6213 uint32_t val;
6214 /* cps (privileged) */
6215 if (IS_USER(s))
6216 return;
6217 mask = val = 0;
6218 if (insn & (1 << 19)) {
6219 if (insn & (1 << 8))
6220 mask |= CPSR_A;
6221 if (insn & (1 << 7))
6222 mask |= CPSR_I;
6223 if (insn & (1 << 6))
6224 mask |= CPSR_F;
6225 if (insn & (1 << 18))
6226 val |= mask;
6227 }
7997d92f 6228 if (insn & (1 << 17)) {
9ee6e8bb
PB		 6229 mask |= CPSR_M;
6230 val |= (insn & 0x1f);
6231 }
6232 if (mask) {
2fbac54b 6233 gen_set_psr_im(s, mask, 0, val);
9ee6e8bb
PB		 6234 }
6235 return;
6236 }
6237 goto illegal_op;
6238 }
6239 if (cond != 0xe) {
6240 /* if not always execute, we generate a conditional jump to
6241 next instruction */
6242 s->condlabel = gen_new_label();
d9ba4830 6243 gen_test_cc(cond ^ 1, s->condlabel);
9ee6e8bb
PB		 6244 s->condjmp = 1;
6245 }
6246 if ((insn & 0x0f900000) == 0x03000000) {
6247 if ((insn & (1 << 21)) == 0) {
6248 ARCH(6T2);
6249 rd = (insn >> 12) & 0xf;
6250 val = ((insn >> 4) & 0xf000) | (insn & 0xfff);
6251 if ((insn & (1 << 22)) == 0) {
6252 /* MOVW */
5e3f878a
PB		 6253 tmp = new_tmp();
6254 tcg_gen_movi_i32(tmp, val);
9ee6e8bb
PB		 6255 } else {
6256 /* MOVT */
5e3f878a 6257 tmp = load_reg(s, rd);
86831435 6258 tcg_gen_ext16u_i32(tmp, tmp);
5e3f878a 6259 tcg_gen_ori_i32(tmp, tmp, val << 16);
9ee6e8bb 6260 }
5e3f878a 6261 store_reg(s, rd, tmp);
9ee6e8bb
PB		 6262 } else {
6263 if (((insn >> 12) & 0xf) != 0xf)
6264 goto illegal_op;
6265 if (((insn >> 16) & 0xf) == 0) {
6266 gen_nop_hint(s, insn & 0xff);
6267 } else {
6268 /* CPSR = immediate */
6269 val = insn & 0xff;
6270 shift = ((insn >> 8) & 0xf) * 2;
6271 if (shift)
6272 val = (val >> shift) | (val << (32 - shift));
9ee6e8bb 6273 i = ((insn & (1 << 22)) != 0);
2fbac54b 6274 if (gen_set_psr_im(s, msr_mask(env, s, (insn >> 16) & 0xf, i), i, val))
9ee6e8bb
PB		 6275 goto illegal_op;
6276 }
6277 }
6278 } else if ((insn & 0x0f900000) == 0x01000000
6279 && (insn & 0x00000090) != 0x00000090) {
6280 /* miscellaneous instructions */
6281 op1 = (insn >> 21) & 3;
6282 sh = (insn >> 4) & 0xf;
6283 rm = insn & 0xf;
6284 switch (sh) {
6285 case 0x0: /* move program status register */
6286 if (op1 & 1) {
6287 /* PSR = reg */
2fbac54b 6288 tmp = load_reg(s, rm);
9ee6e8bb 6289 i = ((op1 & 2) != 0);
2fbac54b 6290 if (gen_set_psr(s, msr_mask(env, s, (insn >> 16) & 0xf, i), i, tmp))
9ee6e8bb
PB		 6291 goto illegal_op;
6292 } else {
6293 /* reg = PSR */
6294 rd = (insn >> 12) & 0xf;
6295 if (op1 & 2) {
6296 if (IS_USER(s))
6297 goto illegal_op;
d9ba4830 6298 tmp = load_cpu_field(spsr);
9ee6e8bb 6299 } else {
d9ba4830
PB		 6300 tmp = new_tmp();
6301 gen_helper_cpsr_read(tmp);
9ee6e8bb 6302 }
d9ba4830 6303 store_reg(s, rd, tmp);
9ee6e8bb
PB		 6304 }
6305 break;
6306 case 0x1:
6307 if (op1 == 1) {
6308 /* branch/exchange thumb (bx). */
d9ba4830
PB		 6309 tmp = load_reg(s, rm);
6310 gen_bx(s, tmp);
9ee6e8bb
PB		 6311 } else if (op1 == 3) {
6312 /* clz */
6313 rd = (insn >> 12) & 0xf;
1497c961
PB		 6314 tmp = load_reg(s, rm);
6315 gen_helper_clz(tmp, tmp);
6316 store_reg(s, rd, tmp);
9ee6e8bb
PB		 6317 } else {
6318 goto illegal_op;
6319 }
6320 break;
6321 case 0x2:
6322 if (op1 == 1) {
6323 ARCH(5J); /* bxj */
6324 /* Trivial implementation equivalent to bx. */
d9ba4830
PB		 6325 tmp = load_reg(s, rm);
6326 gen_bx(s, tmp);
9ee6e8bb
PB		 6327 } else {
6328 goto illegal_op;
6329 }
6330 break;
6331 case 0x3:
6332 if (op1 != 1)
6333 goto illegal_op;
6334
6335 /* branch link/exchange thumb (blx) */
d9ba4830
PB		 6336 tmp = load_reg(s, rm);
6337 tmp2 = new_tmp();
6338 tcg_gen_movi_i32(tmp2, s->pc);
6339 store_reg(s, 14, tmp2);
6340 gen_bx(s, tmp);
9ee6e8bb
PB		 6341 break;
6342 case 0x5: /* saturating add/subtract */
6343 rd = (insn >> 12) & 0xf;
6344 rn = (insn >> 16) & 0xf;
b40d0353 6345 tmp = load_reg(s, rm);
5e3f878a 6346 tmp2 = load_reg(s, rn);
9ee6e8bb 6347 if (op1 & 2)
5e3f878a 6348 gen_helper_double_saturate(tmp2, tmp2);
9ee6e8bb 6349 if (op1 & 1)
5e3f878a 6350 gen_helper_sub_saturate(tmp, tmp, tmp2);
9ee6e8bb 6351 else
5e3f878a
PB		 6352 gen_helper_add_saturate(tmp, tmp, tmp2);
6353 dead_tmp(tmp2);
6354 store_reg(s, rd, tmp);
9ee6e8bb 6355 break;
49e14940
AL		 6356 case 7:
6357 /* SMC instruction (op1 == 3)
6358 and undefined instructions (op1 == 0 || op1 == 2)
6359 will trap */
6360 if (op1 != 1) {
6361 goto illegal_op;
6362 }
6363 /* bkpt */
9ee6e8bb 6364 gen_set_condexec(s);
5e3f878a 6365 gen_set_pc_im(s->pc - 4);
d9ba4830 6366 gen_exception(EXCP_BKPT);
9ee6e8bb
PB		 6367 s->is_jmp = DISAS_JUMP;
6368 break;
6369 case 0x8: /* signed multiply */
6370 case 0xa:
6371 case 0xc:
6372 case 0xe:
6373 rs = (insn >> 8) & 0xf;
6374 rn = (insn >> 12) & 0xf;
6375 rd = (insn >> 16) & 0xf;
6376 if (op1 == 1) {
6377 /* (32 * 16) >> 16 */
5e3f878a
PB		 6378 tmp = load_reg(s, rm);
6379 tmp2 = load_reg(s, rs);
9ee6e8bb 6380 if (sh & 4)
5e3f878a 6381 tcg_gen_sari_i32(tmp2, tmp2, 16);
9ee6e8bb 6382 else
5e3f878a 6383 gen_sxth(tmp2);
a7812ae4
PB		 6384 tmp64 = gen_muls_i64_i32(tmp, tmp2);
6385 tcg_gen_shri_i64(tmp64, tmp64, 16);
5e3f878a 6386 tmp = new_tmp();
a7812ae4 6387 tcg_gen_trunc_i64_i32(tmp, tmp64);
b75263d6 6388 tcg_temp_free_i64(tmp64);
9ee6e8bb 6389 if ((sh & 2) == 0) {
5e3f878a
PB		 6390 tmp2 = load_reg(s, rn);
6391 gen_helper_add_setq(tmp, tmp, tmp2);
6392 dead_tmp(tmp2);
9ee6e8bb 6393 }
5e3f878a 6394 store_reg(s, rd, tmp);
9ee6e8bb
PB		 6395 } else {
6396 /* 16 * 16 */
5e3f878a
PB		 6397 tmp = load_reg(s, rm);
6398 tmp2 = load_reg(s, rs);
6399 gen_mulxy(tmp, tmp2, sh & 2, sh & 4);
6400 dead_tmp(tmp2);
9ee6e8bb 6401 if (op1 == 2) {
a7812ae4
PB		 6402 tmp64 = tcg_temp_new_i64();
6403 tcg_gen_ext_i32_i64(tmp64, tmp);
22478e79 6404 dead_tmp(tmp);
a7812ae4
PB		 6405 gen_addq(s, tmp64, rn, rd);
6406 gen_storeq_reg(s, rn, rd, tmp64);
b75263d6 6407 tcg_temp_free_i64(tmp64);
9ee6e8bb
PB		 6408 } else {
6409 if (op1 == 0) {
5e3f878a
PB		 6410 tmp2 = load_reg(s, rn);
6411 gen_helper_add_setq(tmp, tmp, tmp2);
6412 dead_tmp(tmp2);
9ee6e8bb 6413 }
5e3f878a 6414 store_reg(s, rd, tmp);
9ee6e8bb
PB		 6415 }
6416 }
6417 break;
6418 default:
6419 goto illegal_op;
6420 }
6421 } else if (((insn & 0x0e000000) == 0 &&
6422 (insn & 0x00000090) != 0x90) ||
6423 ((insn & 0x0e000000) == (1 << 25))) {
6424 int set_cc, logic_cc, shiftop;
6425
6426 op1 = (insn >> 21) & 0xf;
6427 set_cc = (insn >> 20) & 1;
6428 logic_cc = table_logic_cc[op1] & set_cc;
6429
6430 /* data processing instruction */
6431 if (insn & (1 << 25)) {
6432 /* immediate operand */
6433 val = insn & 0xff;
6434 shift = ((insn >> 8) & 0xf) * 2;
e9bb4aa9 6435 if (shift) {
9ee6e8bb 6436 val = (val >> shift) | (val << (32 - shift));
e9bb4aa9
JR		 6437 }
6438 tmp2 = new_tmp();
6439 tcg_gen_movi_i32(tmp2, val);
6440 if (logic_cc && shift) {
6441 gen_set_CF_bit31(tmp2);
6442 }
9ee6e8bb
PB		 6443 } else {
6444 /* register */
6445 rm = (insn) & 0xf;
e9bb4aa9 6446 tmp2 = load_reg(s, rm);
9ee6e8bb
PB		 6447 shiftop = (insn >> 5) & 3;
6448 if (!(insn & (1 << 4))) {
6449 shift = (insn >> 7) & 0x1f;
e9bb4aa9 6450 gen_arm_shift_im(tmp2, shiftop, shift, logic_cc);
9ee6e8bb
PB		 6451 } else {
6452 rs = (insn >> 8) & 0xf;
8984bd2e 6453 tmp = load_reg(s, rs);
e9bb4aa9 6454 gen_arm_shift_reg(tmp2, shiftop, tmp, logic_cc);
9ee6e8bb
PB		 6455 }
6456 }
6457 if (op1 != 0x0f && op1 != 0x0d) {
6458 rn = (insn >> 16) & 0xf;
e9bb4aa9
JR		 6459 tmp = load_reg(s, rn);
6460 } else {
6461 TCGV_UNUSED(tmp);
9ee6e8bb
PB		 6462 }
6463 rd = (insn >> 12) & 0xf;
6464 switch(op1) {
6465 case 0x00:
e9bb4aa9
JR		 6466 tcg_gen_and_i32(tmp, tmp, tmp2);
6467 if (logic_cc) {
6468 gen_logic_CC(tmp);
6469 }
21aeb343 6470 store_reg_bx(env, s, rd, tmp);
9ee6e8bb
PB		 6471 break;
6472 case 0x01:
e9bb4aa9
JR		 6473 tcg_gen_xor_i32(tmp, tmp, tmp2);
6474 if (logic_cc) {
6475 gen_logic_CC(tmp);
6476 }
21aeb343 6477 store_reg_bx(env, s, rd, tmp);
9ee6e8bb
PB		 6478 break;
6479 case 0x02:
6480 if (set_cc && rd == 15) {
6481 /* SUBS r15, ... is used for exception return. */
e9bb4aa9 6482 if (IS_USER(s)) {
9ee6e8bb 6483 goto illegal_op;
e9bb4aa9
JR		 6484 }
6485 gen_helper_sub_cc(tmp, tmp, tmp2);
6486 gen_exception_return(s, tmp);
9ee6e8bb 6487 } else {
e9bb4aa9
JR		 6488 if (set_cc) {
6489 gen_helper_sub_cc(tmp, tmp, tmp2);
6490 } else {
6491 tcg_gen_sub_i32(tmp, tmp, tmp2);
6492 }
21aeb343 6493 store_reg_bx(env, s, rd, tmp);
9ee6e8bb
PB		 6494 }
6495 break;
6496 case 0x03:
e9bb4aa9
JR		 6497 if (set_cc) {
6498 gen_helper_sub_cc(tmp, tmp2, tmp);
6499 } else {
6500 tcg_gen_sub_i32(tmp, tmp2, tmp);
6501 }
21aeb343 6502 store_reg_bx(env, s, rd, tmp);
9ee6e8bb
PB		 6503 break;
6504 case 0x04:
e9bb4aa9
JR		 6505 if (set_cc) {
6506 gen_helper_add_cc(tmp, tmp, tmp2);
6507 } else {
6508 tcg_gen_add_i32(tmp, tmp, tmp2);
6509 }
21aeb343 6510 store_reg_bx(env, s, rd, tmp);
9ee6e8bb
PB		 6511 break;
6512 case 0x05:
e9bb4aa9
JR		 6513 if (set_cc) {
6514 gen_helper_adc_cc(tmp, tmp, tmp2);
6515 } else {
6516 gen_add_carry(tmp, tmp, tmp2);
6517 }
21aeb343 6518 store_reg_bx(env, s, rd, tmp);
9ee6e8bb
PB		 6519 break;
6520 case 0x06:
e9bb4aa9
JR		 6521 if (set_cc) {
6522 gen_helper_sbc_cc(tmp, tmp, tmp2);
6523 } else {
6524 gen_sub_carry(tmp, tmp, tmp2);
6525 }
21aeb343 6526 store_reg_bx(env, s, rd, tmp);
9ee6e8bb
PB		 6527 break;
6528 case 0x07:
e9bb4aa9
JR		 6529 if (set_cc) {
6530 gen_helper_sbc_cc(tmp, tmp2, tmp);
6531 } else {
6532 gen_sub_carry(tmp, tmp2, tmp);
6533 }
21aeb343 6534 store_reg_bx(env, s, rd, tmp);
9ee6e8bb
PB		 6535 break;
6536 case 0x08:
6537 if (set_cc) {
e9bb4aa9
JR		 6538 tcg_gen_and_i32(tmp, tmp, tmp2);
6539 gen_logic_CC(tmp);
9ee6e8bb 6540 }
e9bb4aa9 6541 dead_tmp(tmp);
9ee6e8bb
PB		 6542 break;
6543 case 0x09:
6544 if (set_cc) {
e9bb4aa9
JR		 6545 tcg_gen_xor_i32(tmp, tmp, tmp2);
6546 gen_logic_CC(tmp);
9ee6e8bb 6547 }
e9bb4aa9 6548 dead_tmp(tmp);
9ee6e8bb
PB		 6549 break;
6550 case 0x0a:
6551 if (set_cc) {
e9bb4aa9 6552 gen_helper_sub_cc(tmp, tmp, tmp2);
9ee6e8bb 6553 }
e9bb4aa9 6554 dead_tmp(tmp);
9ee6e8bb
PB		 6555 break;
6556 case 0x0b:
6557 if (set_cc) {
e9bb4aa9 6558 gen_helper_add_cc(tmp, tmp, tmp2);
9ee6e8bb 6559 }
e9bb4aa9 6560 dead_tmp(tmp);
9ee6e8bb
PB		 6561 break;
6562 case 0x0c:
e9bb4aa9
JR		 6563 tcg_gen_or_i32(tmp, tmp, tmp2);
6564 if (logic_cc) {
6565 gen_logic_CC(tmp);
6566 }
21aeb343 6567 store_reg_bx(env, s, rd, tmp);
9ee6e8bb
PB		 6568 break;
6569 case 0x0d:
6570 if (logic_cc && rd == 15) {
6571 /* MOVS r15, ... is used for exception return. */
e9bb4aa9 6572 if (IS_USER(s)) {
9ee6e8bb 6573 goto illegal_op;
e9bb4aa9
JR		 6574 }
6575 gen_exception_return(s, tmp2);
9ee6e8bb 6576 } else {
e9bb4aa9
JR		 6577 if (logic_cc) {
6578 gen_logic_CC(tmp2);
6579 }
21aeb343 6580 store_reg_bx(env, s, rd, tmp2);
9ee6e8bb
PB		 6581 }
6582 break;
6583 case 0x0e:
f669df27 6584 tcg_gen_andc_i32(tmp, tmp, tmp2);
e9bb4aa9
JR		 6585 if (logic_cc) {
6586 gen_logic_CC(tmp);
6587 }
21aeb343 6588 store_reg_bx(env, s, rd, tmp);
9ee6e8bb
PB		 6589 break;
6590 default:
6591 case 0x0f:
e9bb4aa9
JR		 6592 tcg_gen_not_i32(tmp2, tmp2);
6593 if (logic_cc) {
6594 gen_logic_CC(tmp2);
6595 }
21aeb343 6596 store_reg_bx(env, s, rd, tmp2);
9ee6e8bb
PB		 6597 break;
6598 }
e9bb4aa9
JR		 6599 if (op1 != 0x0f && op1 != 0x0d) {
6600 dead_tmp(tmp2);
6601 }
9ee6e8bb
PB		 6602 } else {
6603 /* other instructions */
6604 op1 = (insn >> 24) & 0xf;
6605 switch(op1) {
6606 case 0x0:
6607 case 0x1:
6608 /* multiplies, extra load/stores */
6609 sh = (insn >> 5) & 3;
6610 if (sh == 0) {
6611 if (op1 == 0x0) {
6612 rd = (insn >> 16) & 0xf;
6613 rn = (insn >> 12) & 0xf;
6614 rs = (insn >> 8) & 0xf;
6615 rm = (insn) & 0xf;
6616 op1 = (insn >> 20) & 0xf;
6617 switch (op1) {
6618 case 0: case 1: case 2: case 3: case 6:
6619 /* 32 bit mul */
5e3f878a
PB		 6620 tmp = load_reg(s, rs);
6621 tmp2 = load_reg(s, rm);
6622 tcg_gen_mul_i32(tmp, tmp, tmp2);
6623 dead_tmp(tmp2);
9ee6e8bb
PB		 6624 if (insn & (1 << 22)) {
6625 /* Subtract (mls) */
6626 ARCH(6T2);
5e3f878a
PB		 6627 tmp2 = load_reg(s, rn);
6628 tcg_gen_sub_i32(tmp, tmp2, tmp);
6629 dead_tmp(tmp2);
9ee6e8bb
PB		 6630 } else if (insn & (1 << 21)) {
6631 /* Add */
5e3f878a
PB		 6632 tmp2 = load_reg(s, rn);
6633 tcg_gen_add_i32(tmp, tmp, tmp2);
6634 dead_tmp(tmp2);
9ee6e8bb
PB		 6635 }
6636 if (insn & (1 << 20))
5e3f878a
PB		 6637 gen_logic_CC(tmp);
6638 store_reg(s, rd, tmp);
9ee6e8bb
PB		 6639 break;
6640 default:
6641 /* 64 bit mul */
5e3f878a
PB		 6642 tmp = load_reg(s, rs);
6643 tmp2 = load_reg(s, rm);
9ee6e8bb 6644 if (insn & (1 << 22))
a7812ae4 6645 tmp64 = gen_muls_i64_i32(tmp, tmp2);
9ee6e8bb 6646 else
a7812ae4 6647 tmp64 = gen_mulu_i64_i32(tmp, tmp2);
9ee6e8bb 6648 if (insn & (1 << 21)) /* mult accumulate */
a7812ae4 6649 gen_addq(s, tmp64, rn, rd);
9ee6e8bb
PB		 6650 if (!(insn & (1 << 23))) { /* double accumulate */
6651 ARCH(6);
a7812ae4
PB		 6652 gen_addq_lo(s, tmp64, rn);
6653 gen_addq_lo(s, tmp64, rd);
9ee6e8bb
PB		 6654 }
6655 if (insn & (1 << 20))
a7812ae4
PB		 6656 gen_logicq_cc(tmp64);
6657 gen_storeq_reg(s, rn, rd, tmp64);
b75263d6 6658 tcg_temp_free_i64(tmp64);
9ee6e8bb
PB		 6659 break;
6660 }
6661 } else {
6662 rn = (insn >> 16) & 0xf;
6663 rd = (insn >> 12) & 0xf;
6664 if (insn & (1 << 23)) {
6665 /* load/store exclusive */
86753403
PB		 6666 op1 = (insn >> 21) & 0x3;
6667 if (op1)
a47f43d2 6668 ARCH(6K);
86753403
PB		 6669 else
6670 ARCH(6);
3174f8e9 6671 addr = tcg_temp_local_new_i32();
98a46317 6672 load_reg_var(s, addr, rn);
9ee6e8bb 6673 if (insn & (1 << 20)) {
86753403
PB		 6674 switch (op1) {
6675 case 0: /* ldrex */
426f5abc 6676 gen_load_exclusive(s, rd, 15, addr, 2);
86753403
PB		 6677 break;
6678 case 1: /* ldrexd */
426f5abc 6679 gen_load_exclusive(s, rd, rd + 1, addr, 3);
86753403
PB		 6680 break;
6681 case 2: /* ldrexb */
426f5abc 6682 gen_load_exclusive(s, rd, 15, addr, 0);
86753403
PB		 6683 break;
6684 case 3: /* ldrexh */
426f5abc 6685 gen_load_exclusive(s, rd, 15, addr, 1);
86753403
PB		 6686 break;
6687 default:
6688 abort();
6689 }
9ee6e8bb
PB		 6690 } else {
6691 rm = insn & 0xf;
86753403
PB		 6692 switch (op1) {
6693 case 0: /* strex */
426f5abc 6694 gen_store_exclusive(s, rd, rm, 15, addr, 2);
86753403
PB		 6695 break;
6696 case 1: /* strexd */
502e64fe 6697 gen_store_exclusive(s, rd, rm, rm + 1, addr, 3);
86753403
PB		 6698 break;
6699 case 2: /* strexb */
426f5abc 6700 gen_store_exclusive(s, rd, rm, 15, addr, 0);
86753403
PB		 6701 break;
6702 case 3: /* strexh */
426f5abc 6703 gen_store_exclusive(s, rd, rm, 15, addr, 1);
86753403
PB		 6704 break;
6705 default:
6706 abort();
6707 }
9ee6e8bb 6708 }
3174f8e9 6709 tcg_temp_free(addr);
9ee6e8bb
PB		 6710 } else {
6711 /* SWP instruction */
6712 rm = (insn) & 0xf;
6713
8984bd2e
PB		 6714 /* ??? This is not really atomic. However we know
6715 we never have multiple CPUs running in parallel,
6716 so it is good enough. */
6717 addr = load_reg(s, rn);
6718 tmp = load_reg(s, rm);
9ee6e8bb 6719 if (insn & (1 << 22)) {
8984bd2e
PB		 6720 tmp2 = gen_ld8u(addr, IS_USER(s));
6721 gen_st8(tmp, addr, IS_USER(s));
9ee6e8bb 6722 } else {
8984bd2e
PB		 6723 tmp2 = gen_ld32(addr, IS_USER(s));
6724 gen_st32(tmp, addr, IS_USER(s));
9ee6e8bb 6725 }
8984bd2e
PB		 6726 dead_tmp(addr);
6727 store_reg(s, rd, tmp2);
9ee6e8bb
PB		 6728 }
6729 }
6730 } else {
6731 int address_offset;
6732 int load;
6733 /* Misc load/store */
6734 rn = (insn >> 16) & 0xf;
6735 rd = (insn >> 12) & 0xf;
b0109805 6736 addr = load_reg(s, rn);
9ee6e8bb 6737 if (insn & (1 << 24))
b0109805 6738 gen_add_datah_offset(s, insn, 0, addr);
9ee6e8bb
PB		 6739 address_offset = 0;
6740 if (insn & (1 << 20)) {
6741 /* load */
6742 switch(sh) {
6743 case 1:
b0109805 6744 tmp = gen_ld16u(addr, IS_USER(s));
9ee6e8bb
PB		 6745 break;
6746 case 2:
b0109805 6747 tmp = gen_ld8s(addr, IS_USER(s));
9ee6e8bb
PB		 6748 break;
6749 default:
6750 case 3:
b0109805 6751 tmp = gen_ld16s(addr, IS_USER(s));
9ee6e8bb
PB		 6752 break;
6753 }
6754 load = 1;
6755 } else if (sh & 2) {
6756 /* doubleword */
6757 if (sh & 1) {
6758 /* store */
b0109805
PB		 6759 tmp = load_reg(s, rd);
6760 gen_st32(tmp, addr, IS_USER(s));
6761 tcg_gen_addi_i32(addr, addr, 4);
6762 tmp = load_reg(s, rd + 1);
6763 gen_st32(tmp, addr, IS_USER(s));
9ee6e8bb
PB		 6764 load = 0;
6765 } else {
6766 /* load */
b0109805
PB		 6767 tmp = gen_ld32(addr, IS_USER(s));
6768 store_reg(s, rd, tmp);
6769 tcg_gen_addi_i32(addr, addr, 4);
6770 tmp = gen_ld32(addr, IS_USER(s));
9ee6e8bb
PB		 6771 rd++;
6772 load = 1;
6773 }
6774 address_offset = -4;
6775 } else {
6776 /* store */
b0109805
PB		 6777 tmp = load_reg(s, rd);
6778 gen_st16(tmp, addr, IS_USER(s));
9ee6e8bb
PB		 6779 load = 0;
6780 }
6781 /* Perform base writeback before the loaded value to
6782 ensure correct behavior with overlapping index registers.
6783 ldrd with base writeback is is undefined if the
6784 destination and index registers overlap. */
6785 if (!(insn & (1 << 24))) {
b0109805
PB		 6786 gen_add_datah_offset(s, insn, address_offset, addr);
6787 store_reg(s, rn, addr);
9ee6e8bb
PB		 6788 } else if (insn & (1 << 21)) {
6789 if (address_offset)
b0109805
PB		 6790 tcg_gen_addi_i32(addr, addr, address_offset);
6791 store_reg(s, rn, addr);
6792 } else {
6793 dead_tmp(addr);
9ee6e8bb
PB		 6794 }
6795 if (load) {
6796 /* Complete the load. */
b0109805 6797 store_reg(s, rd, tmp);
9ee6e8bb
PB		 6798 }
6799 }
6800 break;
6801 case 0x4:
6802 case 0x5:
6803 goto do_ldst;
6804 case 0x6:
6805 case 0x7:
6806 if (insn & (1 << 4)) {
6807 ARCH(6);
6808 /* Armv6 Media instructions. */
6809 rm = insn & 0xf;
6810 rn = (insn >> 16) & 0xf;
2c0262af 6811 rd = (insn >> 12) & 0xf;
9ee6e8bb
PB		 6812 rs = (insn >> 8) & 0xf;
6813 switch ((insn >> 23) & 3) {
6814 case 0: /* Parallel add/subtract. */
6815 op1 = (insn >> 20) & 7;
6ddbc6e4
PB		 6816 tmp = load_reg(s, rn);
6817 tmp2 = load_reg(s, rm);
9ee6e8bb
PB		 6818 sh = (insn >> 5) & 7;
6819 if ((op1 & 3) == 0 || sh == 5 || sh == 6)
6820 goto illegal_op;
6ddbc6e4
PB		 6821 gen_arm_parallel_addsub(op1, sh, tmp, tmp2);
6822 dead_tmp(tmp2);
6823 store_reg(s, rd, tmp);
9ee6e8bb
PB		 6824 break;
6825 case 1:
6826 if ((insn & 0x00700020) == 0) {
6c95676b 6827 /* Halfword pack. */
3670669c
PB		 6828 tmp = load_reg(s, rn);
6829 tmp2 = load_reg(s, rm);
9ee6e8bb 6830 shift = (insn >> 7) & 0x1f;
3670669c
PB		 6831 if (insn & (1 << 6)) {
6832 /* pkhtb */
22478e79
AZ		 6833 if (shift == 0)
6834 shift = 31;
6835 tcg_gen_sari_i32(tmp2, tmp2, shift);
3670669c 6836 tcg_gen_andi_i32(tmp, tmp, 0xffff0000);
86831435 6837 tcg_gen_ext16u_i32(tmp2, tmp2);
3670669c
PB		 6838 } else {
6839 /* pkhbt */
22478e79
AZ		 6840 if (shift)
6841 tcg_gen_shli_i32(tmp2, tmp2, shift);
86831435 6842 tcg_gen_ext16u_i32(tmp, tmp);
3670669c
PB		 6843 tcg_gen_andi_i32(tmp2, tmp2, 0xffff0000);
6844 }
6845 tcg_gen_or_i32(tmp, tmp, tmp2);
22478e79 6846 dead_tmp(tmp2);
3670669c 6847 store_reg(s, rd, tmp);
9ee6e8bb
PB		 6848 } else if ((insn & 0x00200020) == 0x00200000) {
6849 /* [us]sat */
6ddbc6e4 6850 tmp = load_reg(s, rm);
9ee6e8bb
PB		 6851 shift = (insn >> 7) & 0x1f;
6852 if (insn & (1 << 6)) {
6853 if (shift == 0)
6854 shift = 31;
6ddbc6e4 6855 tcg_gen_sari_i32(tmp, tmp, shift);
9ee6e8bb 6856 } else {
6ddbc6e4 6857 tcg_gen_shli_i32(tmp, tmp, shift);
9ee6e8bb
PB		 6858 }
6859 sh = (insn >> 16) & 0x1f;
6860 if (sh != 0) {
b75263d6 6861 tmp2 = tcg_const_i32(sh);
9ee6e8bb 6862 if (insn & (1 << 22))
b75263d6 6863 gen_helper_usat(tmp, tmp, tmp2);
9ee6e8bb 6864 else
b75263d6
JR		 6865 gen_helper_ssat(tmp, tmp, tmp2);
6866 tcg_temp_free_i32(tmp2);
9ee6e8bb 6867 }
6ddbc6e4 6868 store_reg(s, rd, tmp);
9ee6e8bb
PB		 6869 } else if ((insn & 0x00300fe0) == 0x00200f20) {
6870 /* [us]sat16 */
6ddbc6e4 6871 tmp = load_reg(s, rm);
9ee6e8bb
PB		 6872 sh = (insn >> 16) & 0x1f;
6873 if (sh != 0) {
b75263d6 6874 tmp2 = tcg_const_i32(sh);
9ee6e8bb 6875 if (insn & (1 << 22))
b75263d6 6876 gen_helper_usat16(tmp, tmp, tmp2);
9ee6e8bb 6877 else
b75263d6
JR		 6878 gen_helper_ssat16(tmp, tmp, tmp2);
6879 tcg_temp_free_i32(tmp2);
9ee6e8bb 6880 }
6ddbc6e4 6881 store_reg(s, rd, tmp);
9ee6e8bb
PB		 6882 } else if ((insn & 0x00700fe0) == 0x00000fa0) {
6883 /* Select bytes. */
6ddbc6e4
PB		 6884 tmp = load_reg(s, rn);
6885 tmp2 = load_reg(s, rm);
6886 tmp3 = new_tmp();
6887 tcg_gen_ld_i32(tmp3, cpu_env, offsetof(CPUState, GE));
6888 gen_helper_sel_flags(tmp, tmp3, tmp, tmp2);
6889 dead_tmp(tmp3);
6890 dead_tmp(tmp2);
6891 store_reg(s, rd, tmp);
9ee6e8bb 6892 } else if ((insn & 0x000003e0) == 0x00000060) {
5e3f878a 6893 tmp = load_reg(s, rm);
9ee6e8bb
PB		 6894 shift = (insn >> 10) & 3;
6895 /* ??? In many cases it's not neccessary to do a
6896 rotate, a shift is sufficient. */
6897 if (shift != 0)
f669df27 6898 tcg_gen_rotri_i32(tmp, tmp, shift * 8);
9ee6e8bb
PB		 6899 op1 = (insn >> 20) & 7;
6900 switch (op1) {
5e3f878a
PB		 6901 case 0: gen_sxtb16(tmp); break;
6902 case 2: gen_sxtb(tmp); break;
6903 case 3: gen_sxth(tmp); break;
6904 case 4: gen_uxtb16(tmp); break;
6905 case 6: gen_uxtb(tmp); break;
6906 case 7: gen_uxth(tmp); break;
9ee6e8bb
PB		 6907 default: goto illegal_op;
6908 }
6909 if (rn != 15) {
5e3f878a 6910 tmp2 = load_reg(s, rn);
9ee6e8bb 6911 if ((op1 & 3) == 0) {
5e3f878a 6912 gen_add16(tmp, tmp2);
9ee6e8bb 6913 } else {
5e3f878a
PB		 6914 tcg_gen_add_i32(tmp, tmp, tmp2);
6915 dead_tmp(tmp2);
9ee6e8bb
PB		 6916 }
6917 }
6c95676b 6918 store_reg(s, rd, tmp);
9ee6e8bb
PB		 6919 } else if ((insn & 0x003f0f60) == 0x003f0f20) {
6920 /* rev */
b0109805 6921 tmp = load_reg(s, rm);
9ee6e8bb
PB		 6922 if (insn & (1 << 22)) {
6923 if (insn & (1 << 7)) {
b0109805 6924 gen_revsh(tmp);
9ee6e8bb
PB		 6925 } else {
6926 ARCH(6T2);
b0109805 6927 gen_helper_rbit(tmp, tmp);
9ee6e8bb
PB		 6928 }
6929 } else {
6930 if (insn & (1 << 7))
b0109805 6931 gen_rev16(tmp);
9ee6e8bb 6932 else
66896cb8 6933 tcg_gen_bswap32_i32(tmp, tmp);
9ee6e8bb 6934 }
b0109805 6935 store_reg(s, rd, tmp);
9ee6e8bb
PB		 6936 } else {
6937 goto illegal_op;
6938 }
6939 break;
6940 case 2: /* Multiplies (Type 3). */
5e3f878a
PB		 6941 tmp = load_reg(s, rm);
6942 tmp2 = load_reg(s, rs);
9ee6e8bb
PB		 6943 if (insn & (1 << 20)) {
6944 /* Signed multiply most significant [accumulate]. */
a7812ae4 6945 tmp64 = gen_muls_i64_i32(tmp, tmp2);
9ee6e8bb 6946 if (insn & (1 << 5))
a7812ae4
PB		 6947 tcg_gen_addi_i64(tmp64, tmp64, 0x80000000u);
6948 tcg_gen_shri_i64(tmp64, tmp64, 32);
5e3f878a 6949 tmp = new_tmp();
a7812ae4 6950 tcg_gen_trunc_i64_i32(tmp, tmp64);
b75263d6 6951 tcg_temp_free_i64(tmp64);
955a7dd5
AZ		 6952 if (rd != 15) {
6953 tmp2 = load_reg(s, rd);
9ee6e8bb 6954 if (insn & (1 << 6)) {
5e3f878a 6955 tcg_gen_sub_i32(tmp, tmp, tmp2);
9ee6e8bb 6956 } else {
5e3f878a 6957 tcg_gen_add_i32(tmp, tmp, tmp2);
9ee6e8bb 6958 }
5e3f878a 6959 dead_tmp(tmp2);
9ee6e8bb 6960 }
955a7dd5 6961 store_reg(s, rn, tmp);
9ee6e8bb
PB		 6962 } else {
6963 if (insn & (1 << 5))
5e3f878a
PB		 6964 gen_swap_half(tmp2);
6965 gen_smul_dual(tmp, tmp2);
6966 /* This addition cannot overflow. */
6967 if (insn & (1 << 6)) {
6968 tcg_gen_sub_i32(tmp, tmp, tmp2);
6969 } else {
6970 tcg_gen_add_i32(tmp, tmp, tmp2);
6971 }
6972 dead_tmp(tmp2);
9ee6e8bb 6973 if (insn & (1 << 22)) {
5e3f878a 6974 /* smlald, smlsld */
a7812ae4
PB		 6975 tmp64 = tcg_temp_new_i64();
6976 tcg_gen_ext_i32_i64(tmp64, tmp);
5e3f878a 6977 dead_tmp(tmp);
a7812ae4
PB		 6978 gen_addq(s, tmp64, rd, rn);
6979 gen_storeq_reg(s, rd, rn, tmp64);
b75263d6 6980 tcg_temp_free_i64(tmp64);
9ee6e8bb 6981 } else {
5e3f878a 6982 /* smuad, smusd, smlad, smlsd */
22478e79 6983 if (rd != 15)
9ee6e8bb 6984 {
22478e79 6985 tmp2 = load_reg(s, rd);
5e3f878a
PB		 6986 gen_helper_add_setq(tmp, tmp, tmp2);
6987 dead_tmp(tmp2);
9ee6e8bb 6988 }
22478e79 6989 store_reg(s, rn, tmp);
9ee6e8bb
PB		 6990 }
6991 }
6992 break;
6993 case 3:
6994 op1 = ((insn >> 17) & 0x38) | ((insn >> 5) & 7);
6995 switch (op1) {
6996 case 0: /* Unsigned sum of absolute differences. */
6ddbc6e4
PB		 6997 ARCH(6);
6998 tmp = load_reg(s, rm);
6999 tmp2 = load_reg(s, rs);
7000 gen_helper_usad8(tmp, tmp, tmp2);
7001 dead_tmp(tmp2);
ded9d295
AZ		 7002 if (rd != 15) {
7003 tmp2 = load_reg(s, rd);
6ddbc6e4
PB		 7004 tcg_gen_add_i32(tmp, tmp, tmp2);
7005 dead_tmp(tmp2);
9ee6e8bb 7006 }
ded9d295 7007 store_reg(s, rn, tmp);
9ee6e8bb
PB		 7008 break;
7009 case 0x20: case 0x24: case 0x28: case 0x2c:
7010 /* Bitfield insert/clear. */
7011 ARCH(6T2);
7012 shift = (insn >> 7) & 0x1f;
7013 i = (insn >> 16) & 0x1f;
7014 i = i + 1 - shift;
7015 if (rm == 15) {
5e3f878a
PB		 7016 tmp = new_tmp();
7017 tcg_gen_movi_i32(tmp, 0);
9ee6e8bb 7018 } else {
5e3f878a 7019 tmp = load_reg(s, rm);
9ee6e8bb
PB		 7020 }
7021 if (i != 32) {
5e3f878a 7022 tmp2 = load_reg(s, rd);
8f8e3aa4 7023 gen_bfi(tmp, tmp2, tmp, shift, (1u << i) - 1);
5e3f878a 7024 dead_tmp(tmp2);
9ee6e8bb 7025 }
5e3f878a 7026 store_reg(s, rd, tmp);
9ee6e8bb
PB		 7027 break;
7028 case 0x12: case 0x16: case 0x1a: case 0x1e: /* sbfx */
7029 case 0x32: case 0x36: case 0x3a: case 0x3e: /* ubfx */
4cc633c3 7030 ARCH(6T2);
5e3f878a 7031 tmp = load_reg(s, rm);
9ee6e8bb
PB		 7032 shift = (insn >> 7) & 0x1f;
7033 i = ((insn >> 16) & 0x1f) + 1;
7034 if (shift + i > 32)
7035 goto illegal_op;
7036 if (i < 32) {
7037 if (op1 & 0x20) {
5e3f878a 7038 gen_ubfx(tmp, shift, (1u << i) - 1);
9ee6e8bb 7039 } else {
5e3f878a 7040 gen_sbfx(tmp, shift, i);
9ee6e8bb
PB		 7041 }
7042 }
5e3f878a 7043 store_reg(s, rd, tmp);
9ee6e8bb
PB		 7044 break;
7045 default:
7046 goto illegal_op;
7047 }
7048 break;
7049 }
7050 break;
7051 }
7052 do_ldst:
7053 /* Check for undefined extension instructions
7054 * per the ARM Bible IE:
7055 * xxxx 0111 1111 xxxx xxxx xxxx 1111 xxxx
7056 */
7057 sh = (0xf << 20) | (0xf << 4);
7058 if (op1 == 0x7 && ((insn & sh) == sh))
7059 {
7060 goto illegal_op;
7061 }
7062 /* load/store byte/word */
7063 rn = (insn >> 16) & 0xf;
7064 rd = (insn >> 12) & 0xf;
b0109805 7065 tmp2 = load_reg(s, rn);
9ee6e8bb
PB		 7066 i = (IS_USER(s) || (insn & 0x01200000) == 0x00200000);
7067 if (insn & (1 << 24))
b0109805 7068 gen_add_data_offset(s, insn, tmp2);
9ee6e8bb
PB		 7069 if (insn & (1 << 20)) {
7070 /* load */
9ee6e8bb 7071 if (insn & (1 << 22)) {
b0109805 7072 tmp = gen_ld8u(tmp2, i);
9ee6e8bb 7073 } else {
b0109805 7074 tmp = gen_ld32(tmp2, i);
9ee6e8bb 7075 }
9ee6e8bb
PB		 7076 } else {
7077 /* store */
b0109805 7078 tmp = load_reg(s, rd);
9ee6e8bb 7079 if (insn & (1 << 22))
b0109805 7080 gen_st8(tmp, tmp2, i);
9ee6e8bb 7081 else
b0109805 7082 gen_st32(tmp, tmp2, i);
9ee6e8bb
PB		 7083 }
7084 if (!(insn & (1 << 24))) {
b0109805
PB		 7085 gen_add_data_offset(s, insn, tmp2);
7086 store_reg(s, rn, tmp2);
7087 } else if (insn & (1 << 21)) {
7088 store_reg(s, rn, tmp2);
7089 } else {
7090 dead_tmp(tmp2);
9ee6e8bb
PB		 7091 }
7092 if (insn & (1 << 20)) {
7093 /* Complete the load. */
7094 if (rd == 15)
b0109805 7095 gen_bx(s, tmp);
9ee6e8bb 7096 else
b0109805 7097 store_reg(s, rd, tmp);
9ee6e8bb
PB		 7098 }
7099 break;
7100 case 0x08:
7101 case 0x09:
7102 {
7103 int j, n, user, loaded_base;
b0109805 7104 TCGv loaded_var;
9ee6e8bb
PB		 7105 /* load/store multiple words */
7106 /* XXX: store correct base if write back */
7107 user = 0;
7108 if (insn & (1 << 22)) {
7109 if (IS_USER(s))
7110 goto illegal_op; /* only usable in supervisor mode */
7111
7112 if ((insn & (1 << 15)) == 0)
7113 user = 1;
7114 }
7115 rn = (insn >> 16) & 0xf;
b0109805 7116 addr = load_reg(s, rn);
9ee6e8bb
PB		 7117
7118 /* compute total size */
7119 loaded_base = 0;
a50f5b91 7120 TCGV_UNUSED(loaded_var);
9ee6e8bb
PB		 7121 n = 0;
7122 for(i=0;i<16;i++) {
7123 if (insn & (1 << i))
7124 n++;
7125 }
7126 /* XXX: test invalid n == 0 case ? */
7127 if (insn & (1 << 23)) {
7128 if (insn & (1 << 24)) {
7129 /* pre increment */
b0109805 7130 tcg_gen_addi_i32(addr, addr, 4);
9ee6e8bb
PB		 7131 } else {
7132 /* post increment */
7133 }
7134 } else {
7135 if (insn & (1 << 24)) {
7136 /* pre decrement */
b0109805 7137 tcg_gen_addi_i32(addr, addr, -(n * 4));
9ee6e8bb
PB		 7138 } else {
7139 /* post decrement */
7140 if (n != 1)
b0109805 7141 tcg_gen_addi_i32(addr, addr, -((n - 1) * 4));
9ee6e8bb
PB		 7142 }
7143 }
7144 j = 0;
7145 for(i=0;i<16;i++) {
7146 if (insn & (1 << i)) {
7147 if (insn & (1 << 20)) {
7148 /* load */
b0109805 7149 tmp = gen_ld32(addr, IS_USER(s));
9ee6e8bb 7150 if (i == 15) {
b0109805 7151 gen_bx(s, tmp);
9ee6e8bb 7152 } else if (user) {
b75263d6
JR		 7153 tmp2 = tcg_const_i32(i);
7154 gen_helper_set_user_reg(tmp2, tmp);
7155 tcg_temp_free_i32(tmp2);
b0109805 7156 dead_tmp(tmp);
9ee6e8bb 7157 } else if (i == rn) {
b0109805 7158 loaded_var = tmp;
9ee6e8bb
PB		 7159 loaded_base = 1;
7160 } else {
b0109805 7161 store_reg(s, i, tmp);
9ee6e8bb
PB		 7162 }
7163 } else {
7164 /* store */
7165 if (i == 15) {
7166 /* special case: r15 = PC + 8 */
7167 val = (long)s->pc + 4;
b0109805
PB		 7168 tmp = new_tmp();
7169 tcg_gen_movi_i32(tmp, val);
9ee6e8bb 7170 } else if (user) {
b0109805 7171 tmp = new_tmp();
b75263d6
JR		 7172 tmp2 = tcg_const_i32(i);
7173 gen_helper_get_user_reg(tmp, tmp2);
7174 tcg_temp_free_i32(tmp2);
9ee6e8bb 7175 } else {
b0109805 7176 tmp = load_reg(s, i);
9ee6e8bb 7177 }
b0109805 7178 gen_st32(tmp, addr, IS_USER(s));
9ee6e8bb
PB		 7179 }
7180 j++;
7181 /* no need to add after the last transfer */
7182 if (j != n)
b0109805 7183 tcg_gen_addi_i32(addr, addr, 4);
9ee6e8bb
PB		 7184 }
7185 }
7186 if (insn & (1 << 21)) {
7187 /* write back */
7188 if (insn & (1 << 23)) {
7189 if (insn & (1 << 24)) {
7190 /* pre increment */
7191 } else {
7192 /* post increment */
b0109805 7193 tcg_gen_addi_i32(addr, addr, 4);
9ee6e8bb
PB		 7194 }
7195 } else {
7196 if (insn & (1 << 24)) {
7197 /* pre decrement */
7198 if (n != 1)
b0109805 7199 tcg_gen_addi_i32(addr, addr, -((n - 1) * 4));
9ee6e8bb
PB		 7200 } else {
7201 /* post decrement */
b0109805 7202 tcg_gen_addi_i32(addr, addr, -(n * 4));
9ee6e8bb
PB		 7203 }
7204 }
b0109805
PB		 7205 store_reg(s, rn, addr);
7206 } else {
7207 dead_tmp(addr);
9ee6e8bb
PB		 7208 }
7209 if (loaded_base) {
b0109805 7210 store_reg(s, rn, loaded_var);
9ee6e8bb
PB		 7211 }
7212 if ((insn & (1 << 22)) && !user) {
7213 /* Restore CPSR from SPSR. */
d9ba4830
PB		 7214 tmp = load_cpu_field(spsr);
7215 gen_set_cpsr(tmp, 0xffffffff);
7216 dead_tmp(tmp);
9ee6e8bb
PB		 7217 s->is_jmp = DISAS_UPDATE;
7218 }
7219 }
7220 break;
7221 case 0xa:
7222 case 0xb:
7223 {
7224 int32_t offset;
7225
7226 /* branch (and link) */
7227 val = (int32_t)s->pc;
7228 if (insn & (1 << 24)) {
5e3f878a
PB		 7229 tmp = new_tmp();
7230 tcg_gen_movi_i32(tmp, val);
7231 store_reg(s, 14, tmp);
9ee6e8bb
PB		 7232 }
7233 offset = (((int32_t)insn << 8) >> 8);
7234 val += (offset << 2) + 4;
7235 gen_jmp(s, val);
7236 }
7237 break;
7238 case 0xc:
7239 case 0xd:
7240 case 0xe:
7241 /* Coprocessor. */
7242 if (disas_coproc_insn(env, s, insn))
7243 goto illegal_op;
7244 break;
7245 case 0xf:
7246 /* swi */
5e3f878a 7247 gen_set_pc_im(s->pc);
9ee6e8bb
PB		 7248 s->is_jmp = DISAS_SWI;
7249 break;
7250 default:
7251 illegal_op:
7252 gen_set_condexec(s);
5e3f878a 7253 gen_set_pc_im(s->pc - 4);
d9ba4830 7254 gen_exception(EXCP_UDEF);
9ee6e8bb
PB		 7255 s->is_jmp = DISAS_JUMP;
7256 break;
7257 }
7258 }
7259}
7260
7261/* Return true if this is a Thumb-2 logical op. */
7262static int
7263thumb2_logic_op(int op)
7264{
7265 return (op < 8);
7266}
7267
7268/* Generate code for a Thumb-2 data processing operation. If CONDS is nonzero
7269 then set condition code flags based on the result of the operation.
7270 If SHIFTER_OUT is nonzero then set the carry flag for logical operations
7271 to the high bit of T1.
7272 Returns zero if the opcode is valid. */
7273
7274static int
396e467c 7275gen_thumb2_data_op(DisasContext *s, int op, int conds, uint32_t shifter_out, TCGv t0, TCGv t1)
9ee6e8bb
PB		 7276{
7277 int logic_cc;
7278
7279 logic_cc = 0;
7280 switch (op) {
7281 case 0: /* and */
396e467c 7282 tcg_gen_and_i32(t0, t0, t1);
9ee6e8bb
PB		 7283 logic_cc = conds;
7284 break;
7285 case 1: /* bic */
f669df27 7286 tcg_gen_andc_i32(t0, t0, t1);
9ee6e8bb
PB		 7287 logic_cc = conds;
7288 break;
7289 case 2: /* orr */
396e467c 7290 tcg_gen_or_i32(t0, t0, t1);
9ee6e8bb
PB		 7291 logic_cc = conds;
7292 break;
7293 case 3: /* orn */
396e467c
FN		 7294 tcg_gen_not_i32(t1, t1);
7295 tcg_gen_or_i32(t0, t0, t1);
9ee6e8bb
PB		 7296 logic_cc = conds;
7297 break;
7298 case 4: /* eor */
396e467c 7299 tcg_gen_xor_i32(t0, t0, t1);
9ee6e8bb
PB		 7300 logic_cc = conds;
7301 break;
7302 case 8: /* add */
7303 if (conds)
396e467c 7304 gen_helper_add_cc(t0, t0, t1);
9ee6e8bb 7305 else
396e467c 7306 tcg_gen_add_i32(t0, t0, t1);
9ee6e8bb
PB		 7307 break;
7308 case 10: /* adc */
7309 if (conds)
396e467c 7310 gen_helper_adc_cc(t0, t0, t1);
9ee6e8bb 7311 else
396e467c 7312 gen_adc(t0, t1);
9ee6e8bb
PB		 7313 break;
7314 case 11: /* sbc */
7315 if (conds)
396e467c 7316 gen_helper_sbc_cc(t0, t0, t1);
9ee6e8bb 7317 else
396e467c 7318 gen_sub_carry(t0, t0, t1);
9ee6e8bb
PB		 7319 break;
7320 case 13: /* sub */
7321 if (conds)
396e467c 7322 gen_helper_sub_cc(t0, t0, t1);
9ee6e8bb 7323 else
396e467c 7324 tcg_gen_sub_i32(t0, t0, t1);
9ee6e8bb
PB		 7325 break;
7326 case 14: /* rsb */
7327 if (conds)
396e467c 7328 gen_helper_sub_cc(t0, t1, t0);
9ee6e8bb 7329 else
396e467c 7330 tcg_gen_sub_i32(t0, t1, t0);
9ee6e8bb
PB		 7331 break;
7332 default: /* 5, 6, 7, 9, 12, 15. */
7333 return 1;
7334 }
7335 if (logic_cc) {
396e467c 7336 gen_logic_CC(t0);
9ee6e8bb 7337 if (shifter_out)
396e467c 7338 gen_set_CF_bit31(t1);
9ee6e8bb
PB		 7339 }
7340 return 0;
7341}
7342
7343/* Translate a 32-bit thumb instruction. Returns nonzero if the instruction
7344 is not legal. */
7345static int disas_thumb2_insn(CPUState *env, DisasContext *s, uint16_t insn_hw1)
7346{
b0109805 7347 uint32_t insn, imm, shift, offset;
9ee6e8bb 7348 uint32_t rd, rn, rm, rs;
b26eefb6 7349 TCGv tmp;
6ddbc6e4
PB		 7350 TCGv tmp2;
7351 TCGv tmp3;
b0109805 7352 TCGv addr;
a7812ae4 7353 TCGv_i64 tmp64;
9ee6e8bb
PB		 7354 int op;
7355 int shiftop;
7356 int conds;
7357 int logic_cc;
7358
7359 if (!(arm_feature(env, ARM_FEATURE_THUMB2)
7360 || arm_feature (env, ARM_FEATURE_M))) {
601d70b9 7361 /* Thumb-1 cores may need to treat bl and blx as a pair of
9ee6e8bb
PB		 7362 16-bit instructions to get correct prefetch abort behavior. */
7363 insn = insn_hw1;
7364 if ((insn & (1 << 12)) == 0) {
7365 /* Second half of blx. */
7366 offset = ((insn & 0x7ff) << 1);
d9ba4830
PB		 7367 tmp = load_reg(s, 14);
7368 tcg_gen_addi_i32(tmp, tmp, offset);
7369 tcg_gen_andi_i32(tmp, tmp, 0xfffffffc);
9ee6e8bb 7370
d9ba4830 7371 tmp2 = new_tmp();
b0109805 7372 tcg_gen_movi_i32(tmp2, s->pc | 1);
d9ba4830
PB		 7373 store_reg(s, 14, tmp2);
7374 gen_bx(s, tmp);
9ee6e8bb
PB		 7375 return 0;
7376 }
7377 if (insn & (1 << 11)) {
7378 /* Second half of bl. */
7379 offset = ((insn & 0x7ff) << 1) | 1;
d9ba4830 7380 tmp = load_reg(s, 14);
6a0d8a1d 7381 tcg_gen_addi_i32(tmp, tmp, offset);
9ee6e8bb 7382
d9ba4830 7383 tmp2 = new_tmp();
b0109805 7384 tcg_gen_movi_i32(tmp2, s->pc | 1);
d9ba4830
PB		 7385 store_reg(s, 14, tmp2);
7386 gen_bx(s, tmp);
9ee6e8bb
PB		 7387 return 0;
7388 }
7389 if ((s->pc & ~TARGET_PAGE_MASK) == 0) {
7390 /* Instruction spans a page boundary. Implement it as two
7391 16-bit instructions in case the second half causes an
7392 prefetch abort. */
7393 offset = ((int32_t)insn << 21) >> 9;
396e467c 7394 tcg_gen_movi_i32(cpu_R[14], s->pc + 2 + offset);
9ee6e8bb
PB		 7395 return 0;
7396 }
7397 /* Fall through to 32-bit decode. */
7398 }
7399
7400 insn = lduw_code(s->pc);
7401 s->pc += 2;
7402 insn |= (uint32_t)insn_hw1 << 16;
7403
7404 if ((insn & 0xf800e800) != 0xf000e800) {
7405 ARCH(6T2);
7406 }
7407
7408 rn = (insn >> 16) & 0xf;
7409 rs = (insn >> 12) & 0xf;
7410 rd = (insn >> 8) & 0xf;
7411 rm = insn & 0xf;
7412 switch ((insn >> 25) & 0xf) {
7413 case 0: case 1: case 2: case 3:
7414 /* 16-bit instructions. Should never happen. */
7415 abort();
7416 case 4:
7417 if (insn & (1 << 22)) {
7418 /* Other load/store, table branch. */
7419 if (insn & 0x01200000) {
7420 /* Load/store doubleword. */
7421 if (rn == 15) {
b0109805
PB		 7422 addr = new_tmp();
7423 tcg_gen_movi_i32(addr, s->pc & ~3);
9ee6e8bb 7424 } else {
b0109805 7425 addr = load_reg(s, rn);
9ee6e8bb
PB		 7426 }
7427 offset = (insn & 0xff) * 4;
7428 if ((insn & (1 << 23)) == 0)
7429 offset = -offset;
7430 if (insn & (1 << 24)) {
b0109805 7431 tcg_gen_addi_i32(addr, addr, offset);
9ee6e8bb
PB		 7432 offset = 0;
7433 }
7434 if (insn & (1 << 20)) {
7435 /* ldrd */
b0109805
PB		 7436 tmp = gen_ld32(addr, IS_USER(s));
7437 store_reg(s, rs, tmp);
7438 tcg_gen_addi_i32(addr, addr, 4);
7439 tmp = gen_ld32(addr, IS_USER(s));
7440 store_reg(s, rd, tmp);
9ee6e8bb
PB		 7441 } else {
7442 /* strd */
b0109805
PB		 7443 tmp = load_reg(s, rs);
7444 gen_st32(tmp, addr, IS_USER(s));
7445 tcg_gen_addi_i32(addr, addr, 4);
7446 tmp = load_reg(s, rd);
7447 gen_st32(tmp, addr, IS_USER(s));
9ee6e8bb
PB		 7448 }
7449 if (insn & (1 << 21)) {
7450 /* Base writeback. */
7451 if (rn == 15)
7452 goto illegal_op;
b0109805
PB		 7453 tcg_gen_addi_i32(addr, addr, offset - 4);
7454 store_reg(s, rn, addr);
7455 } else {
7456 dead_tmp(addr);
9ee6e8bb
PB		 7457 }
7458 } else if ((insn & (1 << 23)) == 0) {
7459 /* Load/store exclusive word. */
3174f8e9 7460 addr = tcg_temp_local_new();
98a46317 7461 load_reg_var(s, addr, rn);
426f5abc 7462 tcg_gen_addi_i32(addr, addr, (insn & 0xff) << 2);
2c0262af 7463 if (insn & (1 << 20)) {
426f5abc 7464 gen_load_exclusive(s, rs, 15, addr, 2);
9ee6e8bb 7465 } else {
426f5abc 7466 gen_store_exclusive(s, rd, rs, 15, addr, 2);
9ee6e8bb 7467 }
3174f8e9 7468 tcg_temp_free(addr);
9ee6e8bb
PB		 7469 } else if ((insn & (1 << 6)) == 0) {
7470 /* Table Branch. */
7471 if (rn == 15) {
b0109805
PB		 7472 addr = new_tmp();
7473 tcg_gen_movi_i32(addr, s->pc);
9ee6e8bb 7474 } else {
b0109805 7475 addr = load_reg(s, rn);
9ee6e8bb 7476 }
b26eefb6 7477 tmp = load_reg(s, rm);
b0109805 7478 tcg_gen_add_i32(addr, addr, tmp);
9ee6e8bb
PB		 7479 if (insn & (1 << 4)) {
7480 /* tbh */
b0109805 7481 tcg_gen_add_i32(addr, addr, tmp);
b26eefb6 7482 dead_tmp(tmp);
b0109805 7483 tmp = gen_ld16u(addr, IS_USER(s));
9ee6e8bb 7484 } else { /* tbb */
b26eefb6 7485 dead_tmp(tmp);
b0109805 7486 tmp = gen_ld8u(addr, IS_USER(s));
9ee6e8bb 7487 }
b0109805
PB		 7488 dead_tmp(addr);
7489 tcg_gen_shli_i32(tmp, tmp, 1);
7490 tcg_gen_addi_i32(tmp, tmp, s->pc);
7491 store_reg(s, 15, tmp);
9ee6e8bb
PB		 7492 } else {
7493 /* Load/store exclusive byte/halfword/doubleword. */
426f5abc 7494 ARCH(7);
9ee6e8bb 7495 op = (insn >> 4) & 0x3;
426f5abc
PB		 7496 if (op == 2) {
7497 goto illegal_op;
7498 }
3174f8e9 7499 addr = tcg_temp_local_new();
98a46317 7500 load_reg_var(s, addr, rn);
9ee6e8bb 7501 if (insn & (1 << 20)) {
426f5abc 7502 gen_load_exclusive(s, rs, rd, addr, op);
9ee6e8bb 7503 } else {
426f5abc 7504 gen_store_exclusive(s, rm, rs, rd, addr, op);
9ee6e8bb 7505 }
3174f8e9 7506 tcg_temp_free(addr);
9ee6e8bb
PB		 7507 }
7508 } else {
7509 /* Load/store multiple, RFE, SRS. */
7510 if (((insn >> 23) & 1) == ((insn >> 24) & 1)) {
7511 /* Not available in user mode. */
b0109805 7512 if (IS_USER(s))
9ee6e8bb
PB		 7513 goto illegal_op;
7514 if (insn & (1 << 20)) {
7515 /* rfe */
b0109805
PB		 7516 addr = load_reg(s, rn);
7517 if ((insn & (1 << 24)) == 0)
7518 tcg_gen_addi_i32(addr, addr, -8);
7519 /* Load PC into tmp and CPSR into tmp2. */
7520 tmp = gen_ld32(addr, 0);
7521 tcg_gen_addi_i32(addr, addr, 4);
7522 tmp2 = gen_ld32(addr, 0);
9ee6e8bb
PB		 7523 if (insn & (1 << 21)) {
7524 /* Base writeback. */
b0109805
PB		 7525 if (insn & (1 << 24)) {
7526 tcg_gen_addi_i32(addr, addr, 4);
7527 } else {
7528 tcg_gen_addi_i32(addr, addr, -4);
7529 }
7530 store_reg(s, rn, addr);
7531 } else {
7532 dead_tmp(addr);
9ee6e8bb 7533 }
b0109805 7534 gen_rfe(s, tmp, tmp2);
9ee6e8bb
PB		 7535 } else {
7536 /* srs */
7537 op = (insn & 0x1f);
7538 if (op == (env->uncached_cpsr & CPSR_M)) {
b0109805 7539 addr = load_reg(s, 13);
9ee6e8bb 7540 } else {
b0109805 7541 addr = new_tmp();
b75263d6
JR		 7542 tmp = tcg_const_i32(op);
7543 gen_helper_get_r13_banked(addr, cpu_env, tmp);
7544 tcg_temp_free_i32(tmp);
9ee6e8bb
PB		 7545 }
7546 if ((insn & (1 << 24)) == 0) {
b0109805 7547 tcg_gen_addi_i32(addr, addr, -8);
9ee6e8bb 7548 }
b0109805
PB		 7549 tmp = load_reg(s, 14);
7550 gen_st32(tmp, addr, 0);
7551 tcg_gen_addi_i32(addr, addr, 4);
7552 tmp = new_tmp();
7553 gen_helper_cpsr_read(tmp);
7554 gen_st32(tmp, addr, 0);
9ee6e8bb
PB		 7555 if (insn & (1 << 21)) {
7556 if ((insn & (1 << 24)) == 0) {
b0109805 7557 tcg_gen_addi_i32(addr, addr, -4);
9ee6e8bb 7558 } else {
b0109805 7559 tcg_gen_addi_i32(addr, addr, 4);
9ee6e8bb
PB		 7560 }
7561 if (op == (env->uncached_cpsr & CPSR_M)) {
b0109805 7562 store_reg(s, 13, addr);
9ee6e8bb 7563 } else {
b75263d6
JR		 7564 tmp = tcg_const_i32(op);
7565 gen_helper_set_r13_banked(cpu_env, tmp, addr);
7566 tcg_temp_free_i32(tmp);
9ee6e8bb 7567 }
b0109805
PB		 7568 } else {
7569 dead_tmp(addr);
9ee6e8bb
PB		 7570 }
7571 }
7572 } else {
7573 int i;
7574 /* Load/store multiple. */
b0109805 7575 addr = load_reg(s, rn);
9ee6e8bb
PB		 7576 offset = 0;
7577 for (i = 0; i < 16; i++) {
7578 if (insn & (1 << i))
7579 offset += 4;
7580 }
7581 if (insn & (1 << 24)) {
b0109805 7582 tcg_gen_addi_i32(addr, addr, -offset);
9ee6e8bb
PB		 7583 }
7584
7585 for (i = 0; i < 16; i++) {
7586 if ((insn & (1 << i)) == 0)
7587 continue;
7588 if (insn & (1 << 20)) {
7589 /* Load. */
b0109805 7590 tmp = gen_ld32(addr, IS_USER(s));
9ee6e8bb 7591 if (i == 15) {
b0109805 7592 gen_bx(s, tmp);
9ee6e8bb 7593 } else {
b0109805 7594 store_reg(s, i, tmp);
9ee6e8bb
PB		 7595 }
7596 } else {
7597 /* Store. */
b0109805
PB		 7598 tmp = load_reg(s, i);
7599 gen_st32(tmp, addr, IS_USER(s));
9ee6e8bb 7600 }
b0109805 7601 tcg_gen_addi_i32(addr, addr, 4);
9ee6e8bb
PB		 7602 }
7603 if (insn & (1 << 21)) {
7604 /* Base register writeback. */
7605 if (insn & (1 << 24)) {
b0109805 7606 tcg_gen_addi_i32(addr, addr, -offset);
9ee6e8bb
PB		 7607 }
7608 /* Fault if writeback register is in register list. */
7609 if (insn & (1 << rn))
7610 goto illegal_op;
b0109805
PB		 7611 store_reg(s, rn, addr);
7612 } else {
7613 dead_tmp(addr);
9ee6e8bb
PB		 7614 }
7615 }
7616 }
7617 break;
2af9ab77
JB		 7618 case 5:
7619
9ee6e8bb 7620 op = (insn >> 21) & 0xf;
2af9ab77
JB		 7621 if (op == 6) {
7622 /* Halfword pack. */
7623 tmp = load_reg(s, rn);
7624 tmp2 = load_reg(s, rm);
7625 shift = ((insn >> 10) & 0x1c) | ((insn >> 6) & 0x3);
7626 if (insn & (1 << 5)) {
7627 /* pkhtb */
7628 if (shift == 0)
7629 shift = 31;
7630 tcg_gen_sari_i32(tmp2, tmp2, shift);
7631 tcg_gen_andi_i32(tmp, tmp, 0xffff0000);
7632 tcg_gen_ext16u_i32(tmp2, tmp2);
7633 } else {
7634 /* pkhbt */
7635 if (shift)
7636 tcg_gen_shli_i32(tmp2, tmp2, shift);
7637 tcg_gen_ext16u_i32(tmp, tmp);
7638 tcg_gen_andi_i32(tmp2, tmp2, 0xffff0000);
7639 }
7640 tcg_gen_or_i32(tmp, tmp, tmp2);
7641 dead_tmp(tmp2);
3174f8e9
FN		 7642 store_reg(s, rd, tmp);
7643 } else {
2af9ab77
JB		 7644 /* Data processing register constant shift. */
7645 if (rn == 15) {
7646 tmp = new_tmp();
7647 tcg_gen_movi_i32(tmp, 0);
7648 } else {
7649 tmp = load_reg(s, rn);
7650 }
7651 tmp2 = load_reg(s, rm);
7652
7653 shiftop = (insn >> 4) & 3;
7654 shift = ((insn >> 6) & 3) | ((insn >> 10) & 0x1c);
7655 conds = (insn & (1 << 20)) != 0;
7656 logic_cc = (conds && thumb2_logic_op(op));
7657 gen_arm_shift_im(tmp2, shiftop, shift, logic_cc);
7658 if (gen_thumb2_data_op(s, op, conds, 0, tmp, tmp2))
7659 goto illegal_op;
7660 dead_tmp(tmp2);
7661 if (rd != 15) {
7662 store_reg(s, rd, tmp);
7663 } else {
7664 dead_tmp(tmp);
7665 }
3174f8e9 7666 }
9ee6e8bb
PB		 7667 break;
7668 case 13: /* Misc data processing. */
7669 op = ((insn >> 22) & 6) | ((insn >> 7) & 1);
7670 if (op < 4 && (insn & 0xf000) != 0xf000)
7671 goto illegal_op;
7672 switch (op) {
7673 case 0: /* Register controlled shift. */
8984bd2e
PB		 7674 tmp = load_reg(s, rn);
7675 tmp2 = load_reg(s, rm);
9ee6e8bb
PB		 7676 if ((insn & 0x70) != 0)
7677 goto illegal_op;
7678 op = (insn >> 21) & 3;
8984bd2e
PB		 7679 logic_cc = (insn & (1 << 20)) != 0;
7680 gen_arm_shift_reg(tmp, op, tmp2, logic_cc);
7681 if (logic_cc)
7682 gen_logic_CC(tmp);
21aeb343 7683 store_reg_bx(env, s, rd, tmp);
9ee6e8bb
PB		 7684 break;
7685 case 1: /* Sign/zero extend. */
5e3f878a 7686 tmp = load_reg(s, rm);
9ee6e8bb
PB		 7687 shift = (insn >> 4) & 3;
7688 /* ??? In many cases it's not neccessary to do a
7689 rotate, a shift is sufficient. */
7690 if (shift != 0)
f669df27 7691 tcg_gen_rotri_i32(tmp, tmp, shift * 8);
9ee6e8bb
PB		 7692 op = (insn >> 20) & 7;
7693 switch (op) {
5e3f878a
PB		 7694 case 0: gen_sxth(tmp); break;
7695 case 1: gen_uxth(tmp); break;
7696 case 2: gen_sxtb16(tmp); break;
7697 case 3: gen_uxtb16(tmp); break;
7698 case 4: gen_sxtb(tmp); break;
7699 case 5: gen_uxtb(tmp); break;
9ee6e8bb
PB		 7700 default: goto illegal_op;
7701 }
7702 if (rn != 15) {
5e3f878a 7703 tmp2 = load_reg(s, rn);
9ee6e8bb 7704 if ((op >> 1) == 1) {
5e3f878a 7705 gen_add16(tmp, tmp2);
9ee6e8bb 7706 } else {
5e3f878a
PB		 7707 tcg_gen_add_i32(tmp, tmp, tmp2);
7708 dead_tmp(tmp2);
9ee6e8bb
PB		 7709 }
7710 }
5e3f878a 7711 store_reg(s, rd, tmp);
9ee6e8bb
PB		 7712 break;
7713 case 2: /* SIMD add/subtract. */
7714 op = (insn >> 20) & 7;
7715 shift = (insn >> 4) & 7;
7716 if ((op & 3) == 3 || (shift & 3) == 3)
7717 goto illegal_op;
6ddbc6e4
PB		 7718 tmp = load_reg(s, rn);
7719 tmp2 = load_reg(s, rm);
7720 gen_thumb2_parallel_addsub(op, shift, tmp, tmp2);
7721 dead_tmp(tmp2);
7722 store_reg(s, rd, tmp);
9ee6e8bb
PB		 7723 break;
7724 case 3: /* Other data processing. */
7725 op = ((insn >> 17) & 0x38) | ((insn >> 4) & 7);
7726 if (op < 4) {
7727 /* Saturating add/subtract. */
d9ba4830
PB		 7728 tmp = load_reg(s, rn);
7729 tmp2 = load_reg(s, rm);
9ee6e8bb 7730 if (op & 1)
4809c612
JB		 7731 gen_helper_double_saturate(tmp, tmp);
7732 if (op & 2)
d9ba4830 7733 gen_helper_sub_saturate(tmp, tmp2, tmp);
9ee6e8bb 7734 else
d9ba4830
PB		 7735 gen_helper_add_saturate(tmp, tmp, tmp2);
7736 dead_tmp(tmp2);
9ee6e8bb 7737 } else {
d9ba4830 7738 tmp = load_reg(s, rn);
9ee6e8bb
PB		 7739 switch (op) {
7740 case 0x0a: /* rbit */
d9ba4830 7741 gen_helper_rbit(tmp, tmp);
9ee6e8bb
PB		 7742 break;
7743 case 0x08: /* rev */
66896cb8 7744 tcg_gen_bswap32_i32(tmp, tmp);
9ee6e8bb
PB		 7745 break;
7746 case 0x09: /* rev16 */
d9ba4830 7747 gen_rev16(tmp);
9ee6e8bb
PB		 7748 break;
7749 case 0x0b: /* revsh */
d9ba4830 7750 gen_revsh(tmp);
9ee6e8bb
PB		 7751 break;
7752 case 0x10: /* sel */
d9ba4830 7753 tmp2 = load_reg(s, rm);
6ddbc6e4
PB		 7754 tmp3 = new_tmp();
7755 tcg_gen_ld_i32(tmp3, cpu_env, offsetof(CPUState, GE));
d9ba4830 7756 gen_helper_sel_flags(tmp, tmp3, tmp, tmp2);
6ddbc6e4 7757 dead_tmp(tmp3);
d9ba4830 7758 dead_tmp(tmp2);
9ee6e8bb
PB		 7759 break;
7760 case 0x18: /* clz */
d9ba4830 7761 gen_helper_clz(tmp, tmp);
9ee6e8bb
PB		 7762 break;
7763 default:
7764 goto illegal_op;
7765 }
7766 }
d9ba4830 7767 store_reg(s, rd, tmp);
9ee6e8bb
PB		 7768 break;
7769 case 4: case 5: /* 32-bit multiply. Sum of absolute differences. */
7770 op = (insn >> 4) & 0xf;
d9ba4830
PB		 7771 tmp = load_reg(s, rn);
7772 tmp2 = load_reg(s, rm);
9ee6e8bb
PB		 7773 switch ((insn >> 20) & 7) {
7774 case 0: /* 32 x 32 -> 32 */
d9ba4830
PB		 7775 tcg_gen_mul_i32(tmp, tmp, tmp2);
7776 dead_tmp(tmp2);
9ee6e8bb 7777 if (rs != 15) {
d9ba4830 7778 tmp2 = load_reg(s, rs);
9ee6e8bb 7779 if (op)
d9ba4830 7780 tcg_gen_sub_i32(tmp, tmp2, tmp);
9ee6e8bb 7781 else
d9ba4830
PB		 7782 tcg_gen_add_i32(tmp, tmp, tmp2);
7783 dead_tmp(tmp2);
9ee6e8bb 7784 }
9ee6e8bb
PB		 7785 break;
7786 case 1: /* 16 x 16 -> 32 */
d9ba4830
PB		 7787 gen_mulxy(tmp, tmp2, op & 2, op & 1);
7788 dead_tmp(tmp2);
9ee6e8bb 7789 if (rs != 15) {
d9ba4830
PB		 7790 tmp2 = load_reg(s, rs);
7791 gen_helper_add_setq(tmp, tmp, tmp2);
7792 dead_tmp(tmp2);
9ee6e8bb 7793 }
9ee6e8bb
PB		 7794 break;
7795 case 2: /* Dual multiply add. */
7796 case 4: /* Dual multiply subtract. */
7797 if (op)
d9ba4830
PB		 7798 gen_swap_half(tmp2);
7799 gen_smul_dual(tmp, tmp2);
9ee6e8bb
PB		 7800 /* This addition cannot overflow. */
7801 if (insn & (1 << 22)) {
d9ba4830 7802 tcg_gen_sub_i32(tmp, tmp, tmp2);
9ee6e8bb 7803 } else {
d9ba4830 7804 tcg_gen_add_i32(tmp, tmp, tmp2);
9ee6e8bb 7805 }
d9ba4830 7806 dead_tmp(tmp2);
9ee6e8bb
PB		 7807 if (rs != 15)
7808 {
d9ba4830
PB		 7809 tmp2 = load_reg(s, rs);
7810 gen_helper_add_setq(tmp, tmp, tmp2);
7811 dead_tmp(tmp2);
9ee6e8bb 7812 }
9ee6e8bb
PB		 7813 break;
7814 case 3: /* 32 * 16 -> 32msb */
7815 if (op)
d9ba4830 7816 tcg_gen_sari_i32(tmp2, tmp2, 16);
9ee6e8bb 7817 else
d9ba4830 7818 gen_sxth(tmp2);
a7812ae4
PB		 7819 tmp64 = gen_muls_i64_i32(tmp, tmp2);
7820 tcg_gen_shri_i64(tmp64, tmp64, 16);
5e3f878a 7821 tmp = new_tmp();
a7812ae4 7822 tcg_gen_trunc_i64_i32(tmp, tmp64);
b75263d6 7823 tcg_temp_free_i64(tmp64);
9ee6e8bb
PB		 7824 if (rs != 15)
7825 {
d9ba4830
PB		 7826 tmp2 = load_reg(s, rs);
7827 gen_helper_add_setq(tmp, tmp, tmp2);
7828 dead_tmp(tmp2);
9ee6e8bb 7829 }
9ee6e8bb
PB		 7830 break;
7831 case 5: case 6: /* 32 * 32 -> 32msb */
d9ba4830
PB		 7832 gen_imull(tmp, tmp2);
7833 if (insn & (1 << 5)) {
7834 gen_roundqd(tmp, tmp2);
7835 dead_tmp(tmp2);
7836 } else {
7837 dead_tmp(tmp);
7838 tmp = tmp2;
7839 }
9ee6e8bb 7840 if (rs != 15) {
d9ba4830 7841 tmp2 = load_reg(s, rs);
9ee6e8bb 7842 if (insn & (1 << 21)) {
d9ba4830 7843 tcg_gen_add_i32(tmp, tmp, tmp2);
99c475ab 7844 } else {
d9ba4830 7845 tcg_gen_sub_i32(tmp, tmp2, tmp);
99c475ab 7846 }
d9ba4830 7847 dead_tmp(tmp2);
2c0262af 7848 }
9ee6e8bb
PB		 7849 break;
7850 case 7: /* Unsigned sum of absolute differences. */
d9ba4830
PB		 7851 gen_helper_usad8(tmp, tmp, tmp2);
7852 dead_tmp(tmp2);
9ee6e8bb 7853 if (rs != 15) {
d9ba4830
PB		 7854 tmp2 = load_reg(s, rs);
7855 tcg_gen_add_i32(tmp, tmp, tmp2);
7856 dead_tmp(tmp2);
5fd46862 7857 }
9ee6e8bb 7858 break;
2c0262af 7859 }
d9ba4830 7860 store_reg(s, rd, tmp);
2c0262af 7861 break;
9ee6e8bb
PB		 7862 case 6: case 7: /* 64-bit multiply, Divide. */
7863 op = ((insn >> 4) & 0xf) | ((insn >> 16) & 0x70);
5e3f878a
PB		 7864 tmp = load_reg(s, rn);
7865 tmp2 = load_reg(s, rm);
9ee6e8bb
PB		 7866 if ((op & 0x50) == 0x10) {
7867 /* sdiv, udiv */
7868 if (!arm_feature(env, ARM_FEATURE_DIV))
7869 goto illegal_op;
7870 if (op & 0x20)
5e3f878a 7871 gen_helper_udiv(tmp, tmp, tmp2);
2c0262af 7872 else
5e3f878a
PB		 7873 gen_helper_sdiv(tmp, tmp, tmp2);
7874 dead_tmp(tmp2);
7875 store_reg(s, rd, tmp);
9ee6e8bb
PB		 7876 } else if ((op & 0xe) == 0xc) {
7877 /* Dual multiply accumulate long. */
7878 if (op & 1)
5e3f878a
PB		 7879 gen_swap_half(tmp2);
7880 gen_smul_dual(tmp, tmp2);
9ee6e8bb 7881 if (op & 0x10) {
5e3f878a 7882 tcg_gen_sub_i32(tmp, tmp, tmp2);
b5ff1b31 7883 } else {
5e3f878a 7884 tcg_gen_add_i32(tmp, tmp, tmp2);
b5ff1b31 7885 }
5e3f878a 7886 dead_tmp(tmp2);
a7812ae4
PB		 7887 /* BUGFIX */
7888 tmp64 = tcg_temp_new_i64();
7889 tcg_gen_ext_i32_i64(tmp64, tmp);
7890 dead_tmp(tmp);
7891 gen_addq(s, tmp64, rs, rd);
7892 gen_storeq_reg(s, rs, rd, tmp64);
b75263d6 7893 tcg_temp_free_i64(tmp64);
2c0262af 7894 } else {
9ee6e8bb
PB		 7895 if (op & 0x20) {
7896 /* Unsigned 64-bit multiply */
a7812ae4 7897 tmp64 = gen_mulu_i64_i32(tmp, tmp2);
b5ff1b31 7898 } else {
9ee6e8bb
PB		 7899 if (op & 8) {
7900 /* smlalxy */
5e3f878a
PB		 7901 gen_mulxy(tmp, tmp2, op & 2, op & 1);
7902 dead_tmp(tmp2);
a7812ae4
PB		 7903 tmp64 = tcg_temp_new_i64();
7904 tcg_gen_ext_i32_i64(tmp64, tmp);
5e3f878a 7905 dead_tmp(tmp);
9ee6e8bb
PB		 7906 } else {
7907 /* Signed 64-bit multiply */
a7812ae4 7908 tmp64 = gen_muls_i64_i32(tmp, tmp2);
9ee6e8bb 7909 }
b5ff1b31 7910 }
9ee6e8bb
PB		 7911 if (op & 4) {
7912 /* umaal */
a7812ae4
PB		 7913 gen_addq_lo(s, tmp64, rs);
7914 gen_addq_lo(s, tmp64, rd);
9ee6e8bb
PB		 7915 } else if (op & 0x40) {
7916 /* 64-bit accumulate. */
a7812ae4 7917 gen_addq(s, tmp64, rs, rd);
9ee6e8bb 7918 }
a7812ae4 7919 gen_storeq_reg(s, rs, rd, tmp64);
b75263d6 7920 tcg_temp_free_i64(tmp64);
5fd46862 7921 }
2c0262af 7922 break;
9ee6e8bb
PB		 7923 }
7924 break;
7925 case 6: case 7: case 14: case 15:
7926 /* Coprocessor. */
7927 if (((insn >> 24) & 3) == 3) {
7928 /* Translate into the equivalent ARM encoding. */
7929 insn = (insn & 0xe2ffffff) | ((insn & (1 << 28)) >> 4);
7930 if (disas_neon_data_insn(env, s, insn))
7931 goto illegal_op;
7932 } else {
7933 if (insn & (1 << 28))
7934 goto illegal_op;
7935 if (disas_coproc_insn (env, s, insn))
7936 goto illegal_op;
7937 }
7938 break;
7939 case 8: case 9: case 10: case 11:
7940 if (insn & (1 << 15)) {
7941 /* Branches, misc control. */
7942 if (insn & 0x5000) {
7943 /* Unconditional branch. */
7944 /* signextend(hw1[10:0]) -> offset[:12]. */
7945 offset = ((int32_t)insn << 5) >> 9 & ~(int32_t)0xfff;
7946 /* hw1[10:0] -> offset[11:1]. */
7947 offset |= (insn & 0x7ff) << 1;
7948 /* (~hw2[13, 11] ^ offset[24]) -> offset[23,22]
7949 offset[24:22] already have the same value because of the
7950 sign extension above. */
7951 offset ^= ((~insn) & (1 << 13)) << 10;
7952 offset ^= ((~insn) & (1 << 11)) << 11;
7953
9ee6e8bb
PB		 7954 if (insn & (1 << 14)) {
7955 /* Branch and link. */
3174f8e9 7956 tcg_gen_movi_i32(cpu_R[14], s->pc | 1);
b5ff1b31 7957 }
3b46e624 7958
b0109805 7959 offset += s->pc;
9ee6e8bb
PB		 7960 if (insn & (1 << 12)) {
7961 /* b/bl */
b0109805 7962 gen_jmp(s, offset);
9ee6e8bb
PB		 7963 } else {
7964 /* blx */
b0109805
PB		 7965 offset &= ~(uint32_t)2;
7966 gen_bx_im(s, offset);
2c0262af 7967 }
9ee6e8bb
PB		 7968 } else if (((insn >> 23) & 7) == 7) {
7969 /* Misc control */
7970 if (insn & (1 << 13))
7971 goto illegal_op;
7972
7973 if (insn & (1 << 26)) {
7974 /* Secure monitor call (v6Z) */
7975 goto illegal_op; /* not implemented. */
2c0262af 7976 } else {
9ee6e8bb
PB		 7977 op = (insn >> 20) & 7;
7978 switch (op) {
7979 case 0: /* msr cpsr. */
7980 if (IS_M(env)) {
8984bd2e
PB		 7981 tmp = load_reg(s, rn);
7982 addr = tcg_const_i32(insn & 0xff);
7983 gen_helper_v7m_msr(cpu_env, addr, tmp);
b75263d6
JR		 7984 tcg_temp_free_i32(addr);
7985 dead_tmp(tmp);
9ee6e8bb
PB		 7986 gen_lookup_tb(s);
7987 break;
7988 }
7989 /* fall through */
7990 case 1: /* msr spsr. */
7991 if (IS_M(env))
7992 goto illegal_op;
2fbac54b
FN		 7993 tmp = load_reg(s, rn);
7994 if (gen_set_psr(s,
9ee6e8bb 7995 msr_mask(env, s, (insn >> 8) & 0xf, op == 1),
2fbac54b 7996 op == 1, tmp))
9ee6e8bb
PB		 7997 goto illegal_op;
7998 break;
7999 case 2: /* cps, nop-hint. */
8000 if (((insn >> 8) & 7) == 0) {
8001 gen_nop_hint(s, insn & 0xff);
8002 }
8003 /* Implemented as NOP in user mode. */
8004 if (IS_USER(s))
8005 break;
8006 offset = 0;
8007 imm = 0;
8008 if (insn & (1 << 10)) {
8009 if (insn & (1 << 7))
8010 offset |= CPSR_A;
8011 if (insn & (1 << 6))
8012 offset |= CPSR_I;
8013 if (insn & (1 << 5))
8014 offset |= CPSR_F;
8015 if (insn & (1 << 9))
8016 imm = CPSR_A | CPSR_I | CPSR_F;
8017 }
8018 if (insn & (1 << 8)) {
8019 offset |= 0x1f;
8020 imm |= (insn & 0x1f);
8021 }
8022 if (offset) {
2fbac54b 8023 gen_set_psr_im(s, offset, 0, imm);
9ee6e8bb
PB		 8024 }
8025 break;
8026 case 3: /* Special control operations. */
426f5abc 8027 ARCH(7);
9ee6e8bb
PB		 8028 op = (insn >> 4) & 0xf;
8029 switch (op) {
8030 case 2: /* clrex */
426f5abc 8031 gen_clrex(s);
9ee6e8bb
PB		 8032 break;
8033 case 4: /* dsb */
8034 case 5: /* dmb */
8035 case 6: /* isb */
8036 /* These execute as NOPs. */
9ee6e8bb
PB		 8037 break;
8038 default:
8039 goto illegal_op;
8040 }
8041 break;
8042 case 4: /* bxj */
8043 /* Trivial implementation equivalent to bx. */
d9ba4830
PB		 8044 tmp = load_reg(s, rn);
8045 gen_bx(s, tmp);
9ee6e8bb
PB		 8046 break;
8047 case 5: /* Exception return. */
b8b45b68
RV		 8048 if (IS_USER(s)) {
8049 goto illegal_op;
8050 }
8051 if (rn != 14 || rd != 15) {
8052 goto illegal_op;
8053 }
8054 tmp = load_reg(s, rn);
8055 tcg_gen_subi_i32(tmp, tmp, insn & 0xff);
8056 gen_exception_return(s, tmp);
8057 break;
9ee6e8bb 8058 case 6: /* mrs cpsr. */
8984bd2e 8059 tmp = new_tmp();
9ee6e8bb 8060 if (IS_M(env)) {
8984bd2e
PB		 8061 addr = tcg_const_i32(insn & 0xff);
8062 gen_helper_v7m_mrs(tmp, cpu_env, addr);
b75263d6 8063 tcg_temp_free_i32(addr);
9ee6e8bb 8064 } else {
8984bd2e 8065 gen_helper_cpsr_read(tmp);
9ee6e8bb 8066 }
8984bd2e 8067 store_reg(s, rd, tmp);
9ee6e8bb
PB		 8068 break;
8069 case 7: /* mrs spsr. */
8070 /* Not accessible in user mode. */
8071 if (IS_USER(s) || IS_M(env))
8072 goto illegal_op;
d9ba4830
PB		 8073 tmp = load_cpu_field(spsr);
8074 store_reg(s, rd, tmp);
9ee6e8bb 8075 break;
2c0262af
FB		 8076 }
8077 }
9ee6e8bb
PB		 8078 } else {
8079 /* Conditional branch. */
8080 op = (insn >> 22) & 0xf;
8081 /* Generate a conditional jump to next instruction. */
8082 s->condlabel = gen_new_label();
d9ba4830 8083 gen_test_cc(op ^ 1, s->condlabel);
9ee6e8bb
PB		 8084 s->condjmp = 1;
8085
8086 /* offset[11:1] = insn[10:0] */
8087 offset = (insn & 0x7ff) << 1;
8088 /* offset[17:12] = insn[21:16]. */
8089 offset |= (insn & 0x003f0000) >> 4;
8090 /* offset[31:20] = insn[26]. */
8091 offset |= ((int32_t)((insn << 5) & 0x80000000)) >> 11;
8092 /* offset[18] = insn[13]. */
8093 offset |= (insn & (1 << 13)) << 5;
8094 /* offset[19] = insn[11]. */
8095 offset |= (insn & (1 << 11)) << 8;
8096
8097 /* jump to the offset */
b0109805 8098 gen_jmp(s, s->pc + offset);
9ee6e8bb
PB		 8099 }
8100 } else {
8101 /* Data processing immediate. */
8102 if (insn & (1 << 25)) {
8103 if (insn & (1 << 24)) {
8104 if (insn & (1 << 20))
8105 goto illegal_op;
8106 /* Bitfield/Saturate. */
8107 op = (insn >> 21) & 7;
8108 imm = insn & 0x1f;
8109 shift = ((insn >> 6) & 3) | ((insn >> 10) & 0x1c);
6ddbc6e4
PB		 8110 if (rn == 15) {
8111 tmp = new_tmp();
8112 tcg_gen_movi_i32(tmp, 0);
8113 } else {
8114 tmp = load_reg(s, rn);
8115 }
9ee6e8bb
PB		 8116 switch (op) {
8117 case 2: /* Signed bitfield extract. */
8118 imm++;
8119 if (shift + imm > 32)
8120 goto illegal_op;
8121 if (imm < 32)
6ddbc6e4 8122 gen_sbfx(tmp, shift, imm);
9ee6e8bb
PB		 8123 break;
8124 case 6: /* Unsigned bitfield extract. */
8125 imm++;
8126 if (shift + imm > 32)
8127 goto illegal_op;
8128 if (imm < 32)
6ddbc6e4 8129 gen_ubfx(tmp, shift, (1u << imm) - 1);
9ee6e8bb
PB		 8130 break;
8131 case 3: /* Bitfield insert/clear. */
8132 if (imm < shift)
8133 goto illegal_op;
8134 imm = imm + 1 - shift;
8135 if (imm != 32) {
6ddbc6e4 8136 tmp2 = load_reg(s, rd);
8f8e3aa4 8137 gen_bfi(tmp, tmp2, tmp, shift, (1u << imm) - 1);
6ddbc6e4 8138 dead_tmp(tmp2);
9ee6e8bb
PB		 8139 }
8140 break;
8141 case 7:
8142 goto illegal_op;
8143 default: /* Saturate. */
9ee6e8bb
PB		 8144 if (shift) {
8145 if (op & 1)
6ddbc6e4 8146 tcg_gen_sari_i32(tmp, tmp, shift);
9ee6e8bb 8147 else
6ddbc6e4 8148 tcg_gen_shli_i32(tmp, tmp, shift);
9ee6e8bb 8149 }
6ddbc6e4 8150 tmp2 = tcg_const_i32(imm);
9ee6e8bb
PB		 8151 if (op & 4) {
8152 /* Unsigned. */
9ee6e8bb 8153 if ((op & 1) && shift == 0)
6ddbc6e4 8154 gen_helper_usat16(tmp, tmp, tmp2);
9ee6e8bb 8155 else
6ddbc6e4 8156 gen_helper_usat(tmp, tmp, tmp2);
2c0262af 8157 } else {
9ee6e8bb 8158 /* Signed. */
9ee6e8bb 8159 if ((op & 1) && shift == 0)
6ddbc6e4 8160 gen_helper_ssat16(tmp, tmp, tmp2);
9ee6e8bb 8161 else
6ddbc6e4 8162 gen_helper_ssat(tmp, tmp, tmp2);
2c0262af 8163 }
b75263d6 8164 tcg_temp_free_i32(tmp2);
9ee6e8bb 8165 break;
2c0262af 8166 }
6ddbc6e4 8167 store_reg(s, rd, tmp);
9ee6e8bb
PB		 8168 } else {
8169 imm = ((insn & 0x04000000) >> 15)
8170 | ((insn & 0x7000) >> 4) | (insn & 0xff);
8171 if (insn & (1 << 22)) {
8172 /* 16-bit immediate. */
8173 imm |= (insn >> 4) & 0xf000;
8174 if (insn & (1 << 23)) {
8175 /* movt */
5e3f878a 8176 tmp = load_reg(s, rd);
86831435 8177 tcg_gen_ext16u_i32(tmp, tmp);
5e3f878a 8178 tcg_gen_ori_i32(tmp, tmp, imm << 16);
2c0262af 8179 } else {
9ee6e8bb 8180 /* movw */
5e3f878a
PB		 8181 tmp = new_tmp();
8182 tcg_gen_movi_i32(tmp, imm);
2c0262af
FB		 8183 }
8184 } else {
9ee6e8bb
PB		 8185 /* Add/sub 12-bit immediate. */
8186 if (rn == 15) {
b0109805 8187 offset = s->pc & ~(uint32_t)3;
9ee6e8bb 8188 if (insn & (1 << 23))
b0109805 8189 offset -= imm;
9ee6e8bb 8190 else
b0109805 8191 offset += imm;
5e3f878a
PB		 8192 tmp = new_tmp();
8193 tcg_gen_movi_i32(tmp, offset);
2c0262af 8194 } else {
5e3f878a 8195 tmp = load_reg(s, rn);
9ee6e8bb 8196 if (insn & (1 << 23))
5e3f878a 8197 tcg_gen_subi_i32(tmp, tmp, imm);
9ee6e8bb 8198 else
5e3f878a 8199 tcg_gen_addi_i32(tmp, tmp, imm);
2c0262af 8200 }
9ee6e8bb 8201 }
5e3f878a 8202 store_reg(s, rd, tmp);
191abaa2 8203 }
9ee6e8bb
PB		 8204 } else {
8205 int shifter_out = 0;
8206 /* modified 12-bit immediate. */
8207 shift = ((insn & 0x04000000) >> 23) | ((insn & 0x7000) >> 12);
8208 imm = (insn & 0xff);
8209 switch (shift) {
8210 case 0: /* XY */
8211 /* Nothing to do. */
8212 break;
8213 case 1: /* 00XY00XY */
8214 imm |= imm << 16;
8215 break;
8216 case 2: /* XY00XY00 */
8217 imm |= imm << 16;
8218 imm <<= 8;
8219 break;
8220 case 3: /* XYXYXYXY */
8221 imm |= imm << 16;
8222 imm |= imm << 8;
8223 break;
8224 default: /* Rotated constant. */
8225 shift = (shift << 1) | (imm >> 7);
8226 imm |= 0x80;
8227 imm = imm << (32 - shift);
8228 shifter_out = 1;
8229 break;
b5ff1b31 8230 }
3174f8e9
FN		 8231 tmp2 = new_tmp();
8232 tcg_gen_movi_i32(tmp2, imm);
9ee6e8bb 8233 rn = (insn >> 16) & 0xf;
3174f8e9
FN		 8234 if (rn == 15) {
8235 tmp = new_tmp();
8236 tcg_gen_movi_i32(tmp, 0);
8237 } else {
8238 tmp = load_reg(s, rn);
8239 }
9ee6e8bb
PB		 8240 op = (insn >> 21) & 0xf;
8241 if (gen_thumb2_data_op(s, op, (insn & (1 << 20)) != 0,
3174f8e9 8242 shifter_out, tmp, tmp2))
9ee6e8bb 8243 goto illegal_op;
3174f8e9 8244 dead_tmp(tmp2);
9ee6e8bb
PB		 8245 rd = (insn >> 8) & 0xf;
8246 if (rd != 15) {
3174f8e9
FN		 8247 store_reg(s, rd, tmp);
8248 } else {
8249 dead_tmp(tmp);
2c0262af 8250 }
2c0262af 8251 }
9ee6e8bb
PB		 8252 }
8253 break;
8254 case 12: /* Load/store single data item. */
8255 {
8256 int postinc = 0;
8257 int writeback = 0;
b0109805 8258 int user;
9ee6e8bb
PB		 8259 if ((insn & 0x01100000) == 0x01000000) {
8260 if (disas_neon_ls_insn(env, s, insn))
c1713132 8261 goto illegal_op;
9ee6e8bb
PB		 8262 break;
8263 }
b0109805 8264 user = IS_USER(s);
9ee6e8bb 8265 if (rn == 15) {
b0109805 8266 addr = new_tmp();
9ee6e8bb
PB		 8267 /* PC relative. */
8268 /* s->pc has already been incremented by 4. */
8269 imm = s->pc & 0xfffffffc;
8270 if (insn & (1 << 23))
8271 imm += insn & 0xfff;
8272 else
8273 imm -= insn & 0xfff;
b0109805 8274 tcg_gen_movi_i32(addr, imm);
9ee6e8bb 8275 } else {
b0109805 8276 addr = load_reg(s, rn);
9ee6e8bb
PB		 8277 if (insn & (1 << 23)) {
8278 /* Positive offset. */
8279 imm = insn & 0xfff;
b0109805 8280 tcg_gen_addi_i32(addr, addr, imm);
9ee6e8bb
PB		 8281 } else {
8282 op = (insn >> 8) & 7;
8283 imm = insn & 0xff;
8284 switch (op) {
8285 case 0: case 8: /* Shifted Register. */
8286 shift = (insn >> 4) & 0xf;
8287 if (shift > 3)
18c9b560 8288 goto illegal_op;
b26eefb6 8289 tmp = load_reg(s, rm);
9ee6e8bb 8290 if (shift)
b26eefb6 8291 tcg_gen_shli_i32(tmp, tmp, shift);
b0109805 8292 tcg_gen_add_i32(addr, addr, tmp);
b26eefb6 8293 dead_tmp(tmp);
9ee6e8bb
PB		 8294 break;
8295 case 4: /* Negative offset. */
b0109805 8296 tcg_gen_addi_i32(addr, addr, -imm);
9ee6e8bb
PB		 8297 break;
8298 case 6: /* User privilege. */
b0109805
PB		 8299 tcg_gen_addi_i32(addr, addr, imm);
8300 user = 1;
9ee6e8bb
PB		 8301 break;
8302 case 1: /* Post-decrement. */
8303 imm = -imm;
8304 /* Fall through. */
8305 case 3: /* Post-increment. */
9ee6e8bb
PB		 8306 postinc = 1;
8307 writeback = 1;
8308 break;
8309 case 5: /* Pre-decrement. */
8310 imm = -imm;
8311 /* Fall through. */
8312 case 7: /* Pre-increment. */
b0109805 8313 tcg_gen_addi_i32(addr, addr, imm);
9ee6e8bb
PB		 8314 writeback = 1;
8315 break;
8316 default:
b7bcbe95 8317 goto illegal_op;
9ee6e8bb
PB		 8318 }
8319 }
8320 }
8321 op = ((insn >> 21) & 3) | ((insn >> 22) & 4);
8322 if (insn & (1 << 20)) {
8323 /* Load. */
8324 if (rs == 15 && op != 2) {
8325 if (op & 2)
b5ff1b31 8326 goto illegal_op;
9ee6e8bb
PB		 8327 /* Memory hint. Implemented as NOP. */
8328 } else {
8329 switch (op) {
b0109805
PB		 8330 case 0: tmp = gen_ld8u(addr, user); break;
8331 case 4: tmp = gen_ld8s(addr, user); break;
8332 case 1: tmp = gen_ld16u(addr, user); break;
8333 case 5: tmp = gen_ld16s(addr, user); break;
8334 case 2: tmp = gen_ld32(addr, user); break;
9ee6e8bb
PB		 8335 default: goto illegal_op;
8336 }
8337 if (rs == 15) {
b0109805 8338 gen_bx(s, tmp);
9ee6e8bb 8339 } else {
b0109805 8340 store_reg(s, rs, tmp);
9ee6e8bb
PB		 8341 }
8342 }
8343 } else {
8344 /* Store. */
8345 if (rs == 15)
b7bcbe95 8346 goto illegal_op;
b0109805 8347 tmp = load_reg(s, rs);
9ee6e8bb 8348 switch (op) {
b0109805
PB		 8349 case 0: gen_st8(tmp, addr, user); break;
8350 case 1: gen_st16(tmp, addr, user); break;
8351 case 2: gen_st32(tmp, addr, user); break;
9ee6e8bb 8352 default: goto illegal_op;
b7bcbe95 8353 }
2c0262af 8354 }
9ee6e8bb 8355 if (postinc)
b0109805
PB		 8356 tcg_gen_addi_i32(addr, addr, imm);
8357 if (writeback) {
8358 store_reg(s, rn, addr);
8359 } else {
8360 dead_tmp(addr);
8361 }
9ee6e8bb
PB		 8362 }
8363 break;
8364 default:
8365 goto illegal_op;
2c0262af 8366 }
9ee6e8bb
PB		 8367 return 0;
8368illegal_op:
8369 return 1;
2c0262af
FB		 8370}
8371
9ee6e8bb 8372static void disas_thumb_insn(CPUState *env, DisasContext *s)
99c475ab
FB		 8373{
8374 uint32_t val, insn, op, rm, rn, rd, shift, cond;
8375 int32_t offset;
8376 int i;
b26eefb6 8377 TCGv tmp;
d9ba4830 8378 TCGv tmp2;
b0109805 8379 TCGv addr;
99c475ab 8380
9ee6e8bb
PB		 8381 if (s->condexec_mask) {
8382 cond = s->condexec_cond;
bedd2912
JB		 8383 if (cond != 0x0e) { /* Skip conditional when condition is AL. */
8384 s->condlabel = gen_new_label();
8385 gen_test_cc(cond ^ 1, s->condlabel);
8386 s->condjmp = 1;
8387 }
9ee6e8bb
PB		 8388 }
8389
b5ff1b31 8390 insn = lduw_code(s->pc);
99c475ab 8391 s->pc += 2;
b5ff1b31 8392
99c475ab
FB		 8393 switch (insn >> 12) {
8394 case 0: case 1:
396e467c 8395
99c475ab
FB		 8396 rd = insn & 7;
8397 op = (insn >> 11) & 3;
8398 if (op == 3) {
8399 /* add/subtract */
8400 rn = (insn >> 3) & 7;
396e467c 8401 tmp = load_reg(s, rn);
99c475ab
FB		 8402 if (insn & (1 << 10)) {
8403 /* immediate */
396e467c
FN		 8404 tmp2 = new_tmp();
8405 tcg_gen_movi_i32(tmp2, (insn >> 6) & 7);
99c475ab
FB		 8406 } else {
8407 /* reg */
8408 rm = (insn >> 6) & 7;
396e467c 8409 tmp2 = load_reg(s, rm);
99c475ab 8410 }
9ee6e8bb
PB		 8411 if (insn & (1 << 9)) {
8412 if (s->condexec_mask)
396e467c 8413 tcg_gen_sub_i32(tmp, tmp, tmp2);
9ee6e8bb 8414 else
396e467c 8415 gen_helper_sub_cc(tmp, tmp, tmp2);
9ee6e8bb
PB		 8416 } else {
8417 if (s->condexec_mask)
396e467c 8418 tcg_gen_add_i32(tmp, tmp, tmp2);
9ee6e8bb 8419 else
396e467c 8420 gen_helper_add_cc(tmp, tmp, tmp2);
9ee6e8bb 8421 }
396e467c
FN		 8422 dead_tmp(tmp2);
8423 store_reg(s, rd, tmp);
99c475ab
FB		 8424 } else {
8425 /* shift immediate */
8426 rm = (insn >> 3) & 7;
8427 shift = (insn >> 6) & 0x1f;
9a119ff6
PB		 8428 tmp = load_reg(s, rm);
8429 gen_arm_shift_im(tmp, op, shift, s->condexec_mask == 0);
8430 if (!s->condexec_mask)
8431 gen_logic_CC(tmp);
8432 store_reg(s, rd, tmp);
99c475ab
FB		 8433 }
8434 break;
8435 case 2: case 3:
8436 /* arithmetic large immediate */
8437 op = (insn >> 11) & 3;
8438 rd = (insn >> 8) & 0x7;
396e467c
FN		 8439 if (op == 0) { /* mov */
8440 tmp = new_tmp();
8441 tcg_gen_movi_i32(tmp, insn & 0xff);
9ee6e8bb 8442 if (!s->condexec_mask)
396e467c
FN		 8443 gen_logic_CC(tmp);
8444 store_reg(s, rd, tmp);
8445 } else {
8446 tmp = load_reg(s, rd);
8447 tmp2 = new_tmp();
8448 tcg_gen_movi_i32(tmp2, insn & 0xff);
8449 switch (op) {
8450 case 1: /* cmp */
8451 gen_helper_sub_cc(tmp, tmp, tmp2);
8452 dead_tmp(tmp);
8453 dead_tmp(tmp2);
8454 break;
8455 case 2: /* add */
8456 if (s->condexec_mask)
8457 tcg_gen_add_i32(tmp, tmp, tmp2);
8458 else
8459 gen_helper_add_cc(tmp, tmp, tmp2);
8460 dead_tmp(tmp2);
8461 store_reg(s, rd, tmp);
8462 break;
8463 case 3: /* sub */
8464 if (s->condexec_mask)
8465 tcg_gen_sub_i32(tmp, tmp, tmp2);
8466 else
8467 gen_helper_sub_cc(tmp, tmp, tmp2);
8468 dead_tmp(tmp2);
8469 store_reg(s, rd, tmp);
8470 break;
8471 }
99c475ab 8472 }
99c475ab
FB		 8473 break;
8474 case 4:
8475 if (insn & (1 << 11)) {
8476 rd = (insn >> 8) & 7;
5899f386
FB		 8477 /* load pc-relative. Bit 1 of PC is ignored. */
8478 val = s->pc + 2 + ((insn & 0xff) * 4);
8479 val &= ~(uint32_t)2;
b0109805
PB		 8480 addr = new_tmp();
8481 tcg_gen_movi_i32(addr, val);
8482 tmp = gen_ld32(addr, IS_USER(s));
8483 dead_tmp(addr);
8484 store_reg(s, rd, tmp);
99c475ab
FB		 8485 break;
8486 }
8487 if (insn & (1 << 10)) {
8488 /* data processing extended or blx */
8489 rd = (insn & 7) | ((insn >> 4) & 8);
8490 rm = (insn >> 3) & 0xf;
8491 op = (insn >> 8) & 3;
8492 switch (op) {
8493 case 0: /* add */
396e467c
FN		 8494 tmp = load_reg(s, rd);
8495 tmp2 = load_reg(s, rm);
8496 tcg_gen_add_i32(tmp, tmp, tmp2);
8497 dead_tmp(tmp2);
8498 store_reg(s, rd, tmp);
99c475ab
FB		 8499 break;
8500 case 1: /* cmp */
396e467c
FN		 8501 tmp = load_reg(s, rd);
8502 tmp2 = load_reg(s, rm);
8503 gen_helper_sub_cc(tmp, tmp, tmp2);
8504 dead_tmp(tmp2);
8505 dead_tmp(tmp);
99c475ab
FB		 8506 break;
8507 case 2: /* mov/cpy */
396e467c
FN		 8508 tmp = load_reg(s, rm);
8509 store_reg(s, rd, tmp);
99c475ab
FB		 8510 break;
8511 case 3:/* branch [and link] exchange thumb register */
b0109805 8512 tmp = load_reg(s, rm);
99c475ab
FB		 8513 if (insn & (1 << 7)) {
8514 val = (uint32_t)s->pc | 1;
b0109805
PB		 8515 tmp2 = new_tmp();
8516 tcg_gen_movi_i32(tmp2, val);
8517 store_reg(s, 14, tmp2);
99c475ab 8518 }
d9ba4830 8519 gen_bx(s, tmp);
99c475ab
FB		 8520 break;
8521 }
8522 break;
8523 }
8524
8525 /* data processing register */
8526 rd = insn & 7;
8527 rm = (insn >> 3) & 7;
8528 op = (insn >> 6) & 0xf;
8529 if (op == 2 || op == 3 || op == 4 || op == 7) {
8530 /* the shift/rotate ops want the operands backwards */
8531 val = rm;
8532 rm = rd;
8533 rd = val;
8534 val = 1;
8535 } else {
8536 val = 0;
8537 }
8538
396e467c
FN		 8539 if (op == 9) { /* neg */
8540 tmp = new_tmp();
8541 tcg_gen_movi_i32(tmp, 0);
8542 } else if (op != 0xf) { /* mvn doesn't read its first operand */
8543 tmp = load_reg(s, rd);
8544 } else {
8545 TCGV_UNUSED(tmp);
8546 }
99c475ab 8547
396e467c 8548 tmp2 = load_reg(s, rm);
5899f386 8549 switch (op) {
99c475ab 8550 case 0x0: /* and */
396e467c 8551 tcg_gen_and_i32(tmp, tmp, tmp2);
9ee6e8bb 8552 if (!s->condexec_mask)
396e467c 8553 gen_logic_CC(tmp);
99c475ab
FB		 8554 break;
8555 case 0x1: /* eor */
396e467c 8556 tcg_gen_xor_i32(tmp, tmp, tmp2);
9ee6e8bb 8557 if (!s->condexec_mask)
396e467c 8558 gen_logic_CC(tmp);
99c475ab
FB		 8559 break;
8560 case 0x2: /* lsl */
9ee6e8bb 8561 if (s->condexec_mask) {
396e467c 8562 gen_helper_shl(tmp2, tmp2, tmp);
9ee6e8bb 8563 } else {
396e467c
FN		 8564 gen_helper_shl_cc(tmp2, tmp2, tmp);
8565 gen_logic_CC(tmp2);
9ee6e8bb 8566 }
99c475ab
FB		 8567 break;
8568 case 0x3: /* lsr */
9ee6e8bb 8569 if (s->condexec_mask) {
396e467c 8570 gen_helper_shr(tmp2, tmp2, tmp);
9ee6e8bb 8571 } else {
396e467c
FN		 8572 gen_helper_shr_cc(tmp2, tmp2, tmp);
8573 gen_logic_CC(tmp2);
9ee6e8bb 8574 }
99c475ab
FB		 8575 break;
8576 case 0x4: /* asr */
9ee6e8bb 8577 if (s->condexec_mask) {
396e467c 8578 gen_helper_sar(tmp2, tmp2, tmp);
9ee6e8bb 8579 } else {
396e467c
FN		 8580 gen_helper_sar_cc(tmp2, tmp2, tmp);
8581 gen_logic_CC(tmp2);
9ee6e8bb 8582 }
99c475ab
FB		 8583 break;
8584 case 0x5: /* adc */
9ee6e8bb 8585 if (s->condexec_mask)
396e467c 8586 gen_adc(tmp, tmp2);
9ee6e8bb 8587 else
396e467c 8588 gen_helper_adc_cc(tmp, tmp, tmp2);
99c475ab
FB		 8589 break;
8590 case 0x6: /* sbc */
9ee6e8bb 8591 if (s->condexec_mask)
396e467c 8592 gen_sub_carry(tmp, tmp, tmp2);
9ee6e8bb 8593 else
396e467c 8594 gen_helper_sbc_cc(tmp, tmp, tmp2);
99c475ab
FB		 8595 break;
8596 case 0x7: /* ror */
9ee6e8bb 8597 if (s->condexec_mask) {
f669df27
AJ		 8598 tcg_gen_andi_i32(tmp, tmp, 0x1f);
8599 tcg_gen_rotr_i32(tmp2, tmp2, tmp);
9ee6e8bb 8600 } else {
396e467c
FN		 8601 gen_helper_ror_cc(tmp2, tmp2, tmp);
8602 gen_logic_CC(tmp2);
9ee6e8bb 8603 }
99c475ab
FB		 8604 break;
8605 case 0x8: /* tst */
396e467c
FN		 8606 tcg_gen_and_i32(tmp, tmp, tmp2);
8607 gen_logic_CC(tmp);
99c475ab 8608 rd = 16;
5899f386 8609 break;
99c475ab 8610 case 0x9: /* neg */
9ee6e8bb 8611 if (s->condexec_mask)
396e467c 8612 tcg_gen_neg_i32(tmp, tmp2);
9ee6e8bb 8613 else
396e467c 8614 gen_helper_sub_cc(tmp, tmp, tmp2);
99c475ab
FB		 8615 break;
8616 case 0xa: /* cmp */
396e467c 8617 gen_helper_sub_cc(tmp, tmp, tmp2);
99c475ab
FB		 8618 rd = 16;
8619 break;
8620 case 0xb: /* cmn */
396e467c 8621 gen_helper_add_cc(tmp, tmp, tmp2);
99c475ab
FB		 8622 rd = 16;
8623 break;
8624 case 0xc: /* orr */
396e467c 8625 tcg_gen_or_i32(tmp, tmp, tmp2);
9ee6e8bb 8626 if (!s->condexec_mask)
396e467c 8627 gen_logic_CC(tmp);
99c475ab
FB		 8628 break;
8629 case 0xd: /* mul */
7b2919a0 8630 tcg_gen_mul_i32(tmp, tmp, tmp2);
9ee6e8bb 8631 if (!s->condexec_mask)
396e467c 8632 gen_logic_CC(tmp);
99c475ab
FB		 8633 break;
8634 case 0xe: /* bic */
f669df27 8635 tcg_gen_andc_i32(tmp, tmp, tmp2);
9ee6e8bb 8636 if (!s->condexec_mask)
396e467c 8637 gen_logic_CC(tmp);
99c475ab
FB		 8638 break;
8639 case 0xf: /* mvn */
396e467c 8640 tcg_gen_not_i32(tmp2, tmp2);
9ee6e8bb 8641 if (!s->condexec_mask)
396e467c 8642 gen_logic_CC(tmp2);
99c475ab 8643 val = 1;
5899f386 8644 rm = rd;
99c475ab
FB		 8645 break;
8646 }
8647 if (rd != 16) {
396e467c
FN		 8648 if (val) {
8649 store_reg(s, rm, tmp2);
8650 if (op != 0xf)
8651 dead_tmp(tmp);
8652 } else {
8653 store_reg(s, rd, tmp);
8654 dead_tmp(tmp2);
8655 }
8656 } else {
8657 dead_tmp(tmp);
8658 dead_tmp(tmp2);
99c475ab
FB		 8659 }
8660 break;
8661
8662 case 5:
8663 /* load/store register offset. */
8664 rd = insn & 7;
8665 rn = (insn >> 3) & 7;
8666 rm = (insn >> 6) & 7;
8667 op = (insn >> 9) & 7;
b0109805 8668 addr = load_reg(s, rn);
b26eefb6 8669 tmp = load_reg(s, rm);
b0109805 8670 tcg_gen_add_i32(addr, addr, tmp);
b26eefb6 8671 dead_tmp(tmp);
99c475ab
FB		 8672
8673 if (op < 3) /* store */
b0109805 8674 tmp = load_reg(s, rd);
99c475ab
FB		 8675
8676 switch (op) {
8677 case 0: /* str */
b0109805 8678 gen_st32(tmp, addr, IS_USER(s));
99c475ab
FB		 8679 break;
8680 case 1: /* strh */
b0109805 8681 gen_st16(tmp, addr, IS_USER(s));
99c475ab
FB		 8682 break;
8683 case 2: /* strb */
b0109805 8684 gen_st8(tmp, addr, IS_USER(s));
99c475ab
FB		 8685 break;
8686 case 3: /* ldrsb */
b0109805 8687 tmp = gen_ld8s(addr, IS_USER(s));
99c475ab
FB		 8688 break;
8689 case 4: /* ldr */
b0109805 8690 tmp = gen_ld32(addr, IS_USER(s));
99c475ab
FB		 8691 break;
8692 case 5: /* ldrh */
b0109805 8693 tmp = gen_ld16u(addr, IS_USER(s));
99c475ab
FB		 8694 break;
8695 case 6: /* ldrb */
b0109805 8696 tmp = gen_ld8u(addr, IS_USER(s));
99c475ab
FB		 8697 break;
8698 case 7: /* ldrsh */
b0109805 8699 tmp = gen_ld16s(addr, IS_USER(s));
99c475ab
FB		 8700 break;
8701 }
8702 if (op >= 3) /* load */
b0109805
PB		 8703 store_reg(s, rd, tmp);
8704 dead_tmp(addr);
99c475ab
FB		 8705 break;
8706
8707 case 6:
8708 /* load/store word immediate offset */
8709 rd = insn & 7;
8710 rn = (insn >> 3) & 7;
b0109805 8711 addr = load_reg(s, rn);
99c475ab 8712 val = (insn >> 4) & 0x7c;
b0109805 8713 tcg_gen_addi_i32(addr, addr, val);
99c475ab
FB		 8714
8715 if (insn & (1 << 11)) {
8716 /* load */
b0109805
PB		 8717 tmp = gen_ld32(addr, IS_USER(s));
8718 store_reg(s, rd, tmp);
99c475ab
FB		 8719 } else {
8720 /* store */
b0109805
PB		 8721 tmp = load_reg(s, rd);
8722 gen_st32(tmp, addr, IS_USER(s));
99c475ab 8723 }
b0109805 8724 dead_tmp(addr);
99c475ab
FB		 8725 break;
8726
8727 case 7:
8728 /* load/store byte immediate offset */
8729 rd = insn & 7;
8730 rn = (insn >> 3) & 7;
b0109805 8731 addr = load_reg(s, rn);
99c475ab 8732 val = (insn >> 6) & 0x1f;
b0109805 8733 tcg_gen_addi_i32(addr, addr, val);
99c475ab
FB		 8734
8735 if (insn & (1 << 11)) {
8736 /* load */
b0109805
PB		 8737 tmp = gen_ld8u(addr, IS_USER(s));
8738 store_reg(s, rd, tmp);
99c475ab
FB		 8739 } else {
8740 /* store */
b0109805
PB		 8741 tmp = load_reg(s, rd);
8742 gen_st8(tmp, addr, IS_USER(s));
99c475ab 8743 }
b0109805 8744 dead_tmp(addr);
99c475ab
FB		 8745 break;
8746
8747 case 8:
8748 /* load/store halfword immediate offset */
8749 rd = insn & 7;
8750 rn = (insn >> 3) & 7;
b0109805 8751 addr = load_reg(s, rn);
99c475ab 8752 val = (insn >> 5) & 0x3e;
b0109805 8753 tcg_gen_addi_i32(addr, addr, val);
99c475ab
FB		 8754
8755 if (insn & (1 << 11)) {
8756 /* load */
b0109805
PB		 8757 tmp = gen_ld16u(addr, IS_USER(s));
8758 store_reg(s, rd, tmp);
99c475ab
FB		 8759 } else {
8760 /* store */
b0109805
PB		 8761 tmp = load_reg(s, rd);
8762 gen_st16(tmp, addr, IS_USER(s));
99c475ab 8763 }
b0109805 8764 dead_tmp(addr);
99c475ab
FB		 8765 break;
8766
8767 case 9:
8768 /* load/store from stack */
8769 rd = (insn >> 8) & 7;
b0109805 8770 addr = load_reg(s, 13);
99c475ab 8771 val = (insn & 0xff) * 4;
b0109805 8772 tcg_gen_addi_i32(addr, addr, val);
99c475ab
FB		 8773
8774 if (insn & (1 << 11)) {
8775 /* load */
b0109805
PB		 8776 tmp = gen_ld32(addr, IS_USER(s));
8777 store_reg(s, rd, tmp);
99c475ab
FB		 8778 } else {
8779 /* store */
b0109805
PB		 8780 tmp = load_reg(s, rd);
8781 gen_st32(tmp, addr, IS_USER(s));
99c475ab 8782 }
b0109805 8783 dead_tmp(addr);
99c475ab
FB		 8784 break;
8785
8786 case 10:
8787 /* add to high reg */
8788 rd = (insn >> 8) & 7;
5899f386
FB		 8789 if (insn & (1 << 11)) {
8790 /* SP */
5e3f878a 8791 tmp = load_reg(s, 13);
5899f386
FB		 8792 } else {
8793 /* PC. bit 1 is ignored. */
5e3f878a
PB		 8794 tmp = new_tmp();
8795 tcg_gen_movi_i32(tmp, (s->pc + 2) & ~(uint32_t)2);
5899f386 8796 }
99c475ab 8797 val = (insn & 0xff) * 4;
5e3f878a
PB		 8798 tcg_gen_addi_i32(tmp, tmp, val);
8799 store_reg(s, rd, tmp);
99c475ab
FB		 8800 break;
8801
8802 case 11:
8803 /* misc */
8804 op = (insn >> 8) & 0xf;
8805 switch (op) {
8806 case 0:
8807 /* adjust stack pointer */
b26eefb6 8808 tmp = load_reg(s, 13);
99c475ab
FB		 8809 val = (insn & 0x7f) * 4;
8810 if (insn & (1 << 7))
6a0d8a1d 8811 val = -(int32_t)val;
b26eefb6
PB		 8812 tcg_gen_addi_i32(tmp, tmp, val);
8813 store_reg(s, 13, tmp);
99c475ab
FB		 8814 break;
8815
9ee6e8bb
PB		 8816 case 2: /* sign/zero extend. */
8817 ARCH(6);
8818 rd = insn & 7;
8819 rm = (insn >> 3) & 7;
b0109805 8820 tmp = load_reg(s, rm);
9ee6e8bb 8821 switch ((insn >> 6) & 3) {
b0109805
PB		 8822 case 0: gen_sxth(tmp); break;
8823 case 1: gen_sxtb(tmp); break;
8824 case 2: gen_uxth(tmp); break;
8825 case 3: gen_uxtb(tmp); break;
9ee6e8bb 8826 }
b0109805 8827 store_reg(s, rd, tmp);
9ee6e8bb 8828 break;
99c475ab
FB		 8829 case 4: case 5: case 0xc: case 0xd:
8830 /* push/pop */
b0109805 8831 addr = load_reg(s, 13);
5899f386
FB		 8832 if (insn & (1 << 8))
8833 offset = 4;
99c475ab 8834 else
5899f386
FB		 8835 offset = 0;
8836 for (i = 0; i < 8; i++) {
8837 if (insn & (1 << i))
8838 offset += 4;
8839 }
8840 if ((insn & (1 << 11)) == 0) {
b0109805 8841 tcg_gen_addi_i32(addr, addr, -offset);
5899f386 8842 }
99c475ab
FB		 8843 for (i = 0; i < 8; i++) {
8844 if (insn & (1 << i)) {
8845 if (insn & (1 << 11)) {
8846 /* pop */
b0109805
PB		 8847 tmp = gen_ld32(addr, IS_USER(s));
8848 store_reg(s, i, tmp);
99c475ab
FB		 8849 } else {
8850 /* push */
b0109805
PB		 8851 tmp = load_reg(s, i);
8852 gen_st32(tmp, addr, IS_USER(s));
99c475ab 8853 }
5899f386 8854 /* advance to the next address. */
b0109805 8855 tcg_gen_addi_i32(addr, addr, 4);
99c475ab
FB		 8856 }
8857 }
a50f5b91 8858 TCGV_UNUSED(tmp);
99c475ab
FB		 8859 if (insn & (1 << 8)) {
8860 if (insn & (1 << 11)) {
8861 /* pop pc */
b0109805 8862 tmp = gen_ld32(addr, IS_USER(s));
99c475ab
FB		 8863 /* don't set the pc until the rest of the instruction
8864 has completed */
8865 } else {
8866 /* push lr */
b0109805
PB		 8867 tmp = load_reg(s, 14);
8868 gen_st32(tmp, addr, IS_USER(s));
99c475ab 8869 }
b0109805 8870 tcg_gen_addi_i32(addr, addr, 4);
99c475ab 8871 }
5899f386 8872 if ((insn & (1 << 11)) == 0) {
b0109805 8873 tcg_gen_addi_i32(addr, addr, -offset);
5899f386 8874 }
99c475ab 8875 /* write back the new stack pointer */
b0109805 8876 store_reg(s, 13, addr);
99c475ab
FB		 8877 /* set the new PC value */
8878 if ((insn & 0x0900) == 0x0900)
b0109805 8879 gen_bx(s, tmp);
99c475ab
FB		 8880 break;
8881
9ee6e8bb
PB		 8882 case 1: case 3: case 9: case 11: /* czb */
8883 rm = insn & 7;
d9ba4830 8884 tmp = load_reg(s, rm);
9ee6e8bb
PB		 8885 s->condlabel = gen_new_label();
8886 s->condjmp = 1;
8887 if (insn & (1 << 11))
cb63669a 8888 tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, s->condlabel);
9ee6e8bb 8889 else
cb63669a 8890 tcg_gen_brcondi_i32(TCG_COND_NE, tmp, 0, s->condlabel);
d9ba4830 8891 dead_tmp(tmp);
9ee6e8bb
PB		 8892 offset = ((insn & 0xf8) >> 2) | (insn & 0x200) >> 3;
8893 val = (uint32_t)s->pc + 2;
8894 val += offset;
8895 gen_jmp(s, val);
8896 break;
8897
8898 case 15: /* IT, nop-hint. */
8899 if ((insn & 0xf) == 0) {
8900 gen_nop_hint(s, (insn >> 4) & 0xf);
8901 break;
8902 }
8903 /* If Then. */
8904 s->condexec_cond = (insn >> 4) & 0xe;
8905 s->condexec_mask = insn & 0x1f;
8906 /* No actual code generated for this insn, just setup state. */
8907 break;
8908
06c949e6 8909 case 0xe: /* bkpt */
9ee6e8bb 8910 gen_set_condexec(s);
5e3f878a 8911 gen_set_pc_im(s->pc - 2);
d9ba4830 8912 gen_exception(EXCP_BKPT);
06c949e6
PB		 8913 s->is_jmp = DISAS_JUMP;
8914 break;
8915
9ee6e8bb
PB		 8916 case 0xa: /* rev */
8917 ARCH(6);
8918 rn = (insn >> 3) & 0x7;
8919 rd = insn & 0x7;
b0109805 8920 tmp = load_reg(s, rn);
9ee6e8bb 8921 switch ((insn >> 6) & 3) {
66896cb8 8922 case 0: tcg_gen_bswap32_i32(tmp, tmp); break;
b0109805
PB		 8923 case 1: gen_rev16(tmp); break;
8924 case 3: gen_revsh(tmp); break;
9ee6e8bb
PB		 8925 default: goto illegal_op;
8926 }
b0109805 8927 store_reg(s, rd, tmp);
9ee6e8bb
PB		 8928 break;
8929
8930 case 6: /* cps */
8931 ARCH(6);
8932 if (IS_USER(s))
8933 break;
8934 if (IS_M(env)) {
8984bd2e 8935 tmp = tcg_const_i32((insn & (1 << 4)) != 0);
9ee6e8bb 8936 /* PRIMASK */
8984bd2e
PB		 8937 if (insn & 1) {
8938 addr = tcg_const_i32(16);
8939 gen_helper_v7m_msr(cpu_env, addr, tmp);
b75263d6 8940 tcg_temp_free_i32(addr);
8984bd2e 8941 }
9ee6e8bb 8942 /* FAULTMASK */
8984bd2e
PB		 8943 if (insn & 2) {
8944 addr = tcg_const_i32(17);
8945 gen_helper_v7m_msr(cpu_env, addr, tmp);
b75263d6 8946 tcg_temp_free_i32(addr);
8984bd2e 8947 }
b75263d6 8948 tcg_temp_free_i32(tmp);
9ee6e8bb
PB		 8949 gen_lookup_tb(s);
8950 } else {
8951 if (insn & (1 << 4))
8952 shift = CPSR_A | CPSR_I | CPSR_F;
8953 else
8954 shift = 0;
fa26df03 8955 gen_set_psr_im(s, ((insn & 7) << 6), 0, shift);
9ee6e8bb
PB		 8956 }
8957 break;
8958
99c475ab
FB		 8959 default:
8960 goto undef;
8961 }
8962 break;
8963
8964 case 12:
8965 /* load/store multiple */
8966 rn = (insn >> 8) & 0x7;
b0109805 8967 addr = load_reg(s, rn);
99c475ab
FB		 8968 for (i = 0; i < 8; i++) {
8969 if (insn & (1 << i)) {
99c475ab
FB		 8970 if (insn & (1 << 11)) {
8971 /* load */
b0109805
PB		 8972 tmp = gen_ld32(addr, IS_USER(s));
8973 store_reg(s, i, tmp);
99c475ab
FB		 8974 } else {
8975 /* store */
b0109805
PB		 8976 tmp = load_reg(s, i);
8977 gen_st32(tmp, addr, IS_USER(s));
99c475ab 8978 }
5899f386 8979 /* advance to the next address */
b0109805 8980 tcg_gen_addi_i32(addr, addr, 4);
99c475ab
FB		 8981 }
8982 }
5899f386 8983 /* Base register writeback. */
b0109805
PB		 8984 if ((insn & (1 << rn)) == 0) {
8985 store_reg(s, rn, addr);
8986 } else {
8987 dead_tmp(addr);
8988 }
99c475ab
FB		 8989 break;
8990
8991 case 13:
8992 /* conditional branch or swi */
8993 cond = (insn >> 8) & 0xf;
8994 if (cond == 0xe)
8995 goto undef;
8996
8997 if (cond == 0xf) {
8998 /* swi */
9ee6e8bb 8999 gen_set_condexec(s);
422ebf69 9000 gen_set_pc_im(s->pc);
9ee6e8bb 9001 s->is_jmp = DISAS_SWI;
99c475ab
FB		 9002 break;
9003 }
9004 /* generate a conditional jump to next instruction */
e50e6a20 9005 s->condlabel = gen_new_label();
d9ba4830 9006 gen_test_cc(cond ^ 1, s->condlabel);
e50e6a20 9007 s->condjmp = 1;
99c475ab
FB		 9008
9009 /* jump to the offset */
5899f386 9010 val = (uint32_t)s->pc + 2;
99c475ab 9011 offset = ((int32_t)insn << 24) >> 24;
5899f386 9012 val += offset << 1;
8aaca4c0 9013 gen_jmp(s, val);
99c475ab
FB		 9014 break;
9015
9016 case 14:
358bf29e 9017 if (insn & (1 << 11)) {
9ee6e8bb
PB		 9018 if (disas_thumb2_insn(env, s, insn))
9019 goto undef32;
358bf29e
PB		 9020 break;
9021 }
9ee6e8bb 9022 /* unconditional branch */
99c475ab
FB		 9023 val = (uint32_t)s->pc;
9024 offset = ((int32_t)insn << 21) >> 21;
9025 val += (offset << 1) + 2;
8aaca4c0 9026 gen_jmp(s, val);
99c475ab
FB		 9027 break;
9028
9029 case 15:
9ee6e8bb 9030 if (disas_thumb2_insn(env, s, insn))
6a0d8a1d 9031 goto undef32;
9ee6e8bb 9032 break;
99c475ab
FB		 9033 }
9034 return;
9ee6e8bb
PB		 9035undef32:
9036 gen_set_condexec(s);
5e3f878a 9037 gen_set_pc_im(s->pc - 4);
d9ba4830 9038 gen_exception(EXCP_UDEF);
9ee6e8bb
PB		 9039 s->is_jmp = DISAS_JUMP;
9040 return;
9041illegal_op:
99c475ab 9042undef:
9ee6e8bb 9043 gen_set_condexec(s);
5e3f878a 9044 gen_set_pc_im(s->pc - 2);
d9ba4830 9045 gen_exception(EXCP_UDEF);
99c475ab
FB		 9046 s->is_jmp = DISAS_JUMP;
9047}
9048
2c0262af
FB		 9049/* generate intermediate code in gen_opc_buf and gen_opparam_buf for
9050 basic block 'tb'. If search_pc is TRUE, also generate PC
9051 information for each intermediate instruction. */
2cfc5f17
TS		 9052static inline void gen_intermediate_code_internal(CPUState *env,
9053 TranslationBlock *tb,
9054 int search_pc)
2c0262af
FB		 9055{
9056 DisasContext dc1, *dc = &dc1;
a1d1bb31 9057 CPUBreakpoint *bp;
2c0262af
FB		 9058 uint16_t *gen_opc_end;
9059 int j, lj;
0fa85d43 9060 target_ulong pc_start;
b5ff1b31 9061 uint32_t next_page_start;
2e70f6ef
PB		 9062 int num_insns;
9063 int max_insns;
3b46e624 9064
2c0262af 9065 /* generate intermediate code */
b26eefb6 9066 num_temps = 0;
b26eefb6 9067
0fa85d43 9068 pc_start = tb->pc;
3b46e624 9069
2c0262af
FB		 9070 dc->tb = tb;
9071
2c0262af 9072 gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
2c0262af
FB		 9073
9074 dc->is_jmp = DISAS_NEXT;
9075 dc->pc = pc_start;
8aaca4c0 9076 dc->singlestep_enabled = env->singlestep_enabled;
e50e6a20 9077 dc->condjmp = 0;
5899f386 9078 dc->thumb = env->thumb;
9ee6e8bb
PB		 9079 dc->condexec_mask = (env->condexec_bits & 0xf) << 1;
9080 dc->condexec_cond = env->condexec_bits >> 4;
b5ff1b31 9081#if !defined(CONFIG_USER_ONLY)
9ee6e8bb
PB		 9082 if (IS_M(env)) {
9083 dc->user = ((env->v7m.exception == 0) && (env->v7m.control & 1));
9084 } else {
9085 dc->user = (env->uncached_cpsr & 0x1f) == ARM_CPU_MODE_USR;
9086 }
b5ff1b31 9087#endif
a7812ae4
PB		 9088 cpu_F0s = tcg_temp_new_i32();
9089 cpu_F1s = tcg_temp_new_i32();
9090 cpu_F0d = tcg_temp_new_i64();
9091 cpu_F1d = tcg_temp_new_i64();
ad69471c
PB		 9092 cpu_V0 = cpu_F0d;
9093 cpu_V1 = cpu_F1d;
e677137d 9094 /* FIXME: cpu_M0 can probably be the same as cpu_V0. */
a7812ae4 9095 cpu_M0 = tcg_temp_new_i64();
b5ff1b31 9096 next_page_start = (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
2c0262af 9097 lj = -1;
2e70f6ef
PB		 9098 num_insns = 0;
9099 max_insns = tb->cflags & CF_COUNT_MASK;
9100 if (max_insns == 0)
9101 max_insns = CF_COUNT_MASK;
9102
9103 gen_icount_start();
9ee6e8bb
PB		 9104 /* Reset the conditional execution bits immediately. This avoids
9105 complications trying to do it at the end of the block. */
9106 if (env->condexec_bits)
8f01245e
PB		 9107 {
9108 TCGv tmp = new_tmp();
9109 tcg_gen_movi_i32(tmp, 0);
d9ba4830 9110 store_cpu_field(tmp, condexec_bits);
8f01245e 9111 }
2c0262af 9112 do {
fbb4a2e3
PB		 9113#ifdef CONFIG_USER_ONLY
9114 /* Intercept jump to the magic kernel page. */
9115 if (dc->pc >= 0xffff0000) {
9116 /* We always get here via a jump, so know we are not in a
9117 conditional execution block. */
9118 gen_exception(EXCP_KERNEL_TRAP);
9119 dc->is_jmp = DISAS_UPDATE;
9120 break;
9121 }
9122#else
9ee6e8bb
PB		 9123 if (dc->pc >= 0xfffffff0 && IS_M(env)) {
9124 /* We always get here via a jump, so know we are not in a
9125 conditional execution block. */
d9ba4830 9126 gen_exception(EXCP_EXCEPTION_EXIT);
d60bb01c
PB		 9127 dc->is_jmp = DISAS_UPDATE;
9128 break;
9ee6e8bb
PB		 9129 }
9130#endif
9131
72cf2d4f
BS		 9132 if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) {
9133 QTAILQ_FOREACH(bp, &env->breakpoints, entry) {
a1d1bb31 9134 if (bp->pc == dc->pc) {
9ee6e8bb 9135 gen_set_condexec(dc);
5e3f878a 9136 gen_set_pc_im(dc->pc);
d9ba4830 9137 gen_exception(EXCP_DEBUG);
1fddef4b 9138 dc->is_jmp = DISAS_JUMP;
9ee6e8bb
PB		 9139 /* Advance PC so that clearing the breakpoint will
9140 invalidate this TB. */
9141 dc->pc += 2;
9142 goto done_generating;
1fddef4b
FB		 9143 break;
9144 }
9145 }
9146 }
2c0262af
FB		 9147 if (search_pc) {
9148 j = gen_opc_ptr - gen_opc_buf;
9149 if (lj < j) {
9150 lj++;
9151 while (lj < j)
9152 gen_opc_instr_start[lj++] = 0;
9153 }
0fa85d43 9154 gen_opc_pc[lj] = dc->pc;
2c0262af 9155 gen_opc_instr_start[lj] = 1;
2e70f6ef 9156 gen_opc_icount[lj] = num_insns;
2c0262af 9157 }
e50e6a20 9158
2e70f6ef
PB		 9159 if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO))
9160 gen_io_start();
9161
9ee6e8bb
PB		 9162 if (env->thumb) {
9163 disas_thumb_insn(env, dc);
9164 if (dc->condexec_mask) {
9165 dc->condexec_cond = (dc->condexec_cond & 0xe)
9166 | ((dc->condexec_mask >> 4) & 1);
9167 dc->condexec_mask = (dc->condexec_mask << 1) & 0x1f;
9168 if (dc->condexec_mask == 0) {
9169 dc->condexec_cond = 0;
9170 }
9171 }
9172 } else {
9173 disas_arm_insn(env, dc);
9174 }
b26eefb6
PB		 9175 if (num_temps) {
9176 fprintf(stderr, "Internal resource leak before %08x\n", dc->pc);
9177 num_temps = 0;
9178 }
e50e6a20
FB		 9179
9180 if (dc->condjmp && !dc->is_jmp) {
9181 gen_set_label(dc->condlabel);
9182 dc->condjmp = 0;
9183 }
aaf2d97d 9184 /* Translation stops when a conditional branch is encountered.
e50e6a20 9185 * Otherwise the subsequent code could get translated several times.
b5ff1b31 9186 * Also stop translation when a page boundary is reached. This
bf20dc07 9187 * ensures prefetch aborts occur at the right place. */
2e70f6ef 9188 num_insns ++;
1fddef4b
FB		 9189 } while (!dc->is_jmp && gen_opc_ptr < gen_opc_end &&
9190 !env->singlestep_enabled &&
1b530a6d 9191 !singlestep &&
2e70f6ef
PB		 9192 dc->pc < next_page_start &&
9193 num_insns < max_insns);
9194
9195 if (tb->cflags & CF_LAST_IO) {
9196 if (dc->condjmp) {
9197 /* FIXME: This can theoretically happen with self-modifying
9198 code. */
9199 cpu_abort(env, "IO on conditional branch instruction");
9200 }
9201 gen_io_end();
9202 }
9ee6e8bb 9203
b5ff1b31 9204 /* At this stage dc->condjmp will only be set when the skipped
9ee6e8bb
PB		 9205 instruction was a conditional branch or trap, and the PC has
9206 already been written. */
551bd27f 9207 if (unlikely(env->singlestep_enabled)) {
8aaca4c0 9208 /* Make sure the pc is updated, and raise a debug exception. */
e50e6a20 9209 if (dc->condjmp) {
9ee6e8bb
PB		 9210 gen_set_condexec(dc);
9211 if (dc->is_jmp == DISAS_SWI) {
d9ba4830 9212 gen_exception(EXCP_SWI);
9ee6e8bb 9213 } else {
d9ba4830 9214 gen_exception(EXCP_DEBUG);
9ee6e8bb 9215 }
e50e6a20
FB		 9216 gen_set_label(dc->condlabel);
9217 }
9218 if (dc->condjmp || !dc->is_jmp) {
5e3f878a 9219 gen_set_pc_im(dc->pc);
e50e6a20 9220 dc->condjmp = 0;
8aaca4c0 9221 }
9ee6e8bb
PB		 9222 gen_set_condexec(dc);
9223 if (dc->is_jmp == DISAS_SWI && !dc->condjmp) {
d9ba4830 9224 gen_exception(EXCP_SWI);
9ee6e8bb
PB		 9225 } else {
9226 /* FIXME: Single stepping a WFI insn will not halt
9227 the CPU. */
d9ba4830 9228 gen_exception(EXCP_DEBUG);
9ee6e8bb 9229 }
8aaca4c0 9230 } else {
9ee6e8bb
PB		 9231 /* While branches must always occur at the end of an IT block,
9232 there are a few other things that can cause us to terminate
9233 the TB in the middel of an IT block:
9234 - Exception generating instructions (bkpt, swi, undefined).
9235 - Page boundaries.
9236 - Hardware watchpoints.
9237 Hardware breakpoints have already been handled and skip this code.
9238 */
9239 gen_set_condexec(dc);
8aaca4c0 9240 switch(dc->is_jmp) {
8aaca4c0 9241 case DISAS_NEXT:
6e256c93 9242 gen_goto_tb(dc, 1, dc->pc);
8aaca4c0
FB		 9243 break;
9244 default:
9245 case DISAS_JUMP:
9246 case DISAS_UPDATE:
9247 /* indicate that the hash table must be used to find the next TB */
57fec1fe 9248 tcg_gen_exit_tb(0);
8aaca4c0
FB		 9249 break;
9250 case DISAS_TB_JUMP:
9251 /* nothing more to generate */
9252 break;
9ee6e8bb 9253 case DISAS_WFI:
d9ba4830 9254 gen_helper_wfi();
9ee6e8bb
PB		 9255 break;
9256 case DISAS_SWI:
d9ba4830 9257 gen_exception(EXCP_SWI);
9ee6e8bb 9258 break;
8aaca4c0 9259 }
e50e6a20
FB		 9260 if (dc->condjmp) {
9261 gen_set_label(dc->condlabel);
9ee6e8bb 9262 gen_set_condexec(dc);
6e256c93 9263 gen_goto_tb(dc, 1, dc->pc);
e50e6a20
FB		 9264 dc->condjmp = 0;
9265 }
2c0262af 9266 }
2e70f6ef 9267
9ee6e8bb 9268done_generating:
2e70f6ef 9269 gen_icount_end(tb, num_insns);
2c0262af
FB		 9270 *gen_opc_ptr = INDEX_op_end;
9271
9272#ifdef DEBUG_DISAS
8fec2b8c 9273 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
93fcfe39
AL		 9274 qemu_log("----------------\n");
9275 qemu_log("IN: %s\n", lookup_symbol(pc_start));
9276 log_target_disas(pc_start, dc->pc - pc_start, env->thumb);
9277 qemu_log("\n");
2c0262af
FB		 9278 }
9279#endif
b5ff1b31
FB		 9280 if (search_pc) {
9281 j = gen_opc_ptr - gen_opc_buf;
9282 lj++;
9283 while (lj <= j)
9284 gen_opc_instr_start[lj++] = 0;
b5ff1b31 9285 } else {
2c0262af 9286 tb->size = dc->pc - pc_start;
2e70f6ef 9287 tb->icount = num_insns;
b5ff1b31 9288 }
2c0262af
FB		 9289}
9290
2cfc5f17 9291void gen_intermediate_code(CPUState *env, TranslationBlock *tb)
2c0262af 9292{
2cfc5f17 9293 gen_intermediate_code_internal(env, tb, 0);
2c0262af
FB		 9294}
9295
2cfc5f17 9296void gen_intermediate_code_pc(CPUState *env, TranslationBlock *tb)
2c0262af 9297{
2cfc5f17 9298 gen_intermediate_code_internal(env, tb, 1);
2c0262af
FB		 9299}
9300
b5ff1b31
FB		 9301static const char *cpu_mode_names[16] = {
9302 "usr", "fiq", "irq", "svc", "???", "???", "???", "abt",
9303 "???", "???", "???", "und", "???", "???", "???", "sys"
9304};
9ee6e8bb 9305
9a78eead 9306void cpu_dump_state(CPUState *env, FILE *f, fprintf_function cpu_fprintf,
7fe48483 9307 int flags)
2c0262af
FB		 9308{
9309 int i;
06e80fc9 9310#if 0
bc380d17 9311 union {
b7bcbe95
FB		 9312 uint32_t i;
9313 float s;
9314 } s0, s1;
9315 CPU_DoubleU d;
a94a6abf
PB		 9316 /* ??? This assumes float64 and double have the same layout.
9317 Oh well, it's only debug dumps. */
9318 union {
9319 float64 f64;
9320 double d;
9321 } d0;
06e80fc9 9322#endif
b5ff1b31 9323 uint32_t psr;
2c0262af
FB		 9324
9325 for(i=0;i<16;i++) {
7fe48483 9326 cpu_fprintf(f, "R%02d=%08x", i, env->regs[i]);
2c0262af 9327 if ((i % 4) == 3)
7fe48483 9328 cpu_fprintf(f, "\n");
2c0262af 9329 else
7fe48483 9330 cpu_fprintf(f, " ");
2c0262af 9331 }
b5ff1b31 9332 psr = cpsr_read(env);
687fa640
TS		 9333 cpu_fprintf(f, "PSR=%08x %c%c%c%c %c %s%d\n",
9334 psr,
b5ff1b31
FB		 9335 psr & (1 << 31) ? 'N' : '-',
9336 psr & (1 << 30) ? 'Z' : '-',
9337 psr & (1 << 29) ? 'C' : '-',
9338 psr & (1 << 28) ? 'V' : '-',
5fafdf24 9339 psr & CPSR_T ? 'T' : 'A',
b5ff1b31 9340 cpu_mode_names[psr & 0xf], (psr & 0x10) ? 32 : 26);
b7bcbe95 9341
5e3f878a 9342#if 0
b7bcbe95 9343 for (i = 0; i < 16; i++) {
8e96005d
FB		 9344 d.d = env->vfp.regs[i];
9345 s0.i = d.l.lower;
9346 s1.i = d.l.upper;
a94a6abf
PB		 9347 d0.f64 = d.d;
9348 cpu_fprintf(f, "s%02d=%08x(%8g) s%02d=%08x(%8g) d%02d=%08x%08x(%8g)\n",
b7bcbe95 9349 i * 2, (int)s0.i, s0.s,
a94a6abf 9350 i * 2 + 1, (int)s1.i, s1.s,
b7bcbe95 9351 i, (int)(uint32_t)d.l.upper, (int)(uint32_t)d.l.lower,
a94a6abf 9352 d0.d);
b7bcbe95 9353 }
40f137e1 9354 cpu_fprintf(f, "FPSCR: %08x\n", (int)env->vfp.xregs[ARM_VFP_FPSCR]);
5e3f878a 9355#endif
2c0262af 9356}
a6b025d3 9357
d2856f1a
AJ		 9358void gen_pc_load(CPUState *env, TranslationBlock *tb,
9359 unsigned long searched_pc, int pc_pos, void *puc)
9360{
9361 env->regs[15] = gen_opc_pc[pc_pos];
9362}
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