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Commit | Line | Data |
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2c0262af FB |
1 | /* |
2 | * ARM translation | |
5fafdf24 | 3 | * |
2c0262af | 4 | * Copyright (c) 2003 Fabrice Bellard |
9ee6e8bb | 5 | * Copyright (c) 2005-2007 CodeSourcery |
18c9b560 | 6 | * Copyright (c) 2007 OpenedHand, Ltd. |
2c0262af FB |
7 | * |
8 | * This library is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU Lesser General Public | |
10 | * License as published by the Free Software Foundation; either | |
11 | * version 2 of the License, or (at your option) any later version. | |
12 | * | |
13 | * This library is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
16 | * Lesser General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU Lesser General Public | |
8167ee88 | 19 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. |
2c0262af FB |
20 | */ |
21 | #include <stdarg.h> | |
22 | #include <stdlib.h> | |
23 | #include <stdio.h> | |
24 | #include <string.h> | |
25 | #include <inttypes.h> | |
26 | ||
27 | #include "cpu.h" | |
28 | #include "exec-all.h" | |
29 | #include "disas.h" | |
57fec1fe | 30 | #include "tcg-op.h" |
79383c9c | 31 | #include "qemu-log.h" |
1497c961 | 32 | |
a7812ae4 | 33 | #include "helpers.h" |
1497c961 | 34 | #define GEN_HELPER 1 |
b26eefb6 | 35 | #include "helpers.h" |
2c0262af | 36 | |
be5e7a76 DES |
37 | #define ENABLE_ARCH_4T arm_feature(env, ARM_FEATURE_V4T) |
38 | #define ENABLE_ARCH_5 arm_feature(env, ARM_FEATURE_V5) | |
39 | /* currently all emulated v5 cores are also v5TE, so don't bother */ | |
40 | #define ENABLE_ARCH_5TE arm_feature(env, ARM_FEATURE_V5) | |
9ee6e8bb PB |
41 | #define ENABLE_ARCH_5J 0 |
42 | #define ENABLE_ARCH_6 arm_feature(env, ARM_FEATURE_V6) | |
43 | #define ENABLE_ARCH_6K arm_feature(env, ARM_FEATURE_V6K) | |
44 | #define ENABLE_ARCH_6T2 arm_feature(env, ARM_FEATURE_THUMB2) | |
45 | #define ENABLE_ARCH_7 arm_feature(env, ARM_FEATURE_V7) | |
b5ff1b31 | 46 | |
86753403 | 47 | #define ARCH(x) do { if (!ENABLE_ARCH_##x) goto illegal_op; } while(0) |
b5ff1b31 | 48 | |
2c0262af FB |
49 | /* internal defines */ |
50 | typedef struct DisasContext { | |
0fa85d43 | 51 | target_ulong pc; |
2c0262af | 52 | int is_jmp; |
e50e6a20 FB |
53 | /* Nonzero if this instruction has been conditionally skipped. */ |
54 | int condjmp; | |
55 | /* The label that will be jumped to when the instruction is skipped. */ | |
56 | int condlabel; | |
9ee6e8bb PB |
57 | /* Thumb-2 condtional execution bits. */ |
58 | int condexec_mask; | |
59 | int condexec_cond; | |
2c0262af | 60 | struct TranslationBlock *tb; |
8aaca4c0 | 61 | int singlestep_enabled; |
5899f386 | 62 | int thumb; |
b5ff1b31 FB |
63 | #if !defined(CONFIG_USER_ONLY) |
64 | int user; | |
65 | #endif | |
5df8bac1 | 66 | int vfp_enabled; |
69d1fc22 PM |
67 | int vec_len; |
68 | int vec_stride; | |
2c0262af FB |
69 | } DisasContext; |
70 | ||
e12ce78d PM |
71 | static uint32_t gen_opc_condexec_bits[OPC_BUF_SIZE]; |
72 | ||
b5ff1b31 FB |
73 | #if defined(CONFIG_USER_ONLY) |
74 | #define IS_USER(s) 1 | |
75 | #else | |
76 | #define IS_USER(s) (s->user) | |
77 | #endif | |
78 | ||
9ee6e8bb PB |
79 | /* These instructions trap after executing, so defer them until after the |
80 | conditional executions state has been updated. */ | |
81 | #define DISAS_WFI 4 | |
82 | #define DISAS_SWI 5 | |
2c0262af | 83 | |
a7812ae4 | 84 | static TCGv_ptr cpu_env; |
ad69471c | 85 | /* We reuse the same 64-bit temporaries for efficiency. */ |
a7812ae4 | 86 | static TCGv_i64 cpu_V0, cpu_V1, cpu_M0; |
155c3eac | 87 | static TCGv_i32 cpu_R[16]; |
426f5abc PB |
88 | static TCGv_i32 cpu_exclusive_addr; |
89 | static TCGv_i32 cpu_exclusive_val; | |
90 | static TCGv_i32 cpu_exclusive_high; | |
91 | #ifdef CONFIG_USER_ONLY | |
92 | static TCGv_i32 cpu_exclusive_test; | |
93 | static TCGv_i32 cpu_exclusive_info; | |
94 | #endif | |
ad69471c | 95 | |
b26eefb6 | 96 | /* FIXME: These should be removed. */ |
a7812ae4 PB |
97 | static TCGv cpu_F0s, cpu_F1s; |
98 | static TCGv_i64 cpu_F0d, cpu_F1d; | |
b26eefb6 | 99 | |
2e70f6ef PB |
100 | #include "gen-icount.h" |
101 | ||
155c3eac FN |
102 | static const char *regnames[] = |
103 | { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", | |
104 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "pc" }; | |
105 | ||
b26eefb6 PB |
106 | /* initialize TCG globals. */ |
107 | void arm_translate_init(void) | |
108 | { | |
155c3eac FN |
109 | int i; |
110 | ||
a7812ae4 PB |
111 | cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env"); |
112 | ||
155c3eac FN |
113 | for (i = 0; i < 16; i++) { |
114 | cpu_R[i] = tcg_global_mem_new_i32(TCG_AREG0, | |
115 | offsetof(CPUState, regs[i]), | |
116 | regnames[i]); | |
117 | } | |
426f5abc PB |
118 | cpu_exclusive_addr = tcg_global_mem_new_i32(TCG_AREG0, |
119 | offsetof(CPUState, exclusive_addr), "exclusive_addr"); | |
120 | cpu_exclusive_val = tcg_global_mem_new_i32(TCG_AREG0, | |
121 | offsetof(CPUState, exclusive_val), "exclusive_val"); | |
122 | cpu_exclusive_high = tcg_global_mem_new_i32(TCG_AREG0, | |
123 | offsetof(CPUState, exclusive_high), "exclusive_high"); | |
124 | #ifdef CONFIG_USER_ONLY | |
125 | cpu_exclusive_test = tcg_global_mem_new_i32(TCG_AREG0, | |
126 | offsetof(CPUState, exclusive_test), "exclusive_test"); | |
127 | cpu_exclusive_info = tcg_global_mem_new_i32(TCG_AREG0, | |
128 | offsetof(CPUState, exclusive_info), "exclusive_info"); | |
129 | #endif | |
155c3eac | 130 | |
a7812ae4 PB |
131 | #define GEN_HELPER 2 |
132 | #include "helpers.h" | |
b26eefb6 PB |
133 | } |
134 | ||
d9ba4830 PB |
135 | static inline TCGv load_cpu_offset(int offset) |
136 | { | |
7d1b0095 | 137 | TCGv tmp = tcg_temp_new_i32(); |
d9ba4830 PB |
138 | tcg_gen_ld_i32(tmp, cpu_env, offset); |
139 | return tmp; | |
140 | } | |
141 | ||
142 | #define load_cpu_field(name) load_cpu_offset(offsetof(CPUState, name)) | |
143 | ||
144 | static inline void store_cpu_offset(TCGv var, int offset) | |
145 | { | |
146 | tcg_gen_st_i32(var, cpu_env, offset); | |
7d1b0095 | 147 | tcg_temp_free_i32(var); |
d9ba4830 PB |
148 | } |
149 | ||
150 | #define store_cpu_field(var, name) \ | |
151 | store_cpu_offset(var, offsetof(CPUState, name)) | |
152 | ||
b26eefb6 PB |
153 | /* Set a variable to the value of a CPU register. */ |
154 | static void load_reg_var(DisasContext *s, TCGv var, int reg) | |
155 | { | |
156 | if (reg == 15) { | |
157 | uint32_t addr; | |
158 | /* normaly, since we updated PC, we need only to add one insn */ | |
159 | if (s->thumb) | |
160 | addr = (long)s->pc + 2; | |
161 | else | |
162 | addr = (long)s->pc + 4; | |
163 | tcg_gen_movi_i32(var, addr); | |
164 | } else { | |
155c3eac | 165 | tcg_gen_mov_i32(var, cpu_R[reg]); |
b26eefb6 PB |
166 | } |
167 | } | |
168 | ||
169 | /* Create a new temporary and set it to the value of a CPU register. */ | |
170 | static inline TCGv load_reg(DisasContext *s, int reg) | |
171 | { | |
7d1b0095 | 172 | TCGv tmp = tcg_temp_new_i32(); |
b26eefb6 PB |
173 | load_reg_var(s, tmp, reg); |
174 | return tmp; | |
175 | } | |
176 | ||
177 | /* Set a CPU register. The source must be a temporary and will be | |
178 | marked as dead. */ | |
179 | static void store_reg(DisasContext *s, int reg, TCGv var) | |
180 | { | |
181 | if (reg == 15) { | |
182 | tcg_gen_andi_i32(var, var, ~1); | |
183 | s->is_jmp = DISAS_JUMP; | |
184 | } | |
155c3eac | 185 | tcg_gen_mov_i32(cpu_R[reg], var); |
7d1b0095 | 186 | tcg_temp_free_i32(var); |
b26eefb6 PB |
187 | } |
188 | ||
b26eefb6 | 189 | /* Value extensions. */ |
86831435 PB |
190 | #define gen_uxtb(var) tcg_gen_ext8u_i32(var, var) |
191 | #define gen_uxth(var) tcg_gen_ext16u_i32(var, var) | |
b26eefb6 PB |
192 | #define gen_sxtb(var) tcg_gen_ext8s_i32(var, var) |
193 | #define gen_sxth(var) tcg_gen_ext16s_i32(var, var) | |
194 | ||
1497c961 PB |
195 | #define gen_sxtb16(var) gen_helper_sxtb16(var, var) |
196 | #define gen_uxtb16(var) gen_helper_uxtb16(var, var) | |
8f01245e | 197 | |
b26eefb6 | 198 | |
b75263d6 JR |
199 | static inline void gen_set_cpsr(TCGv var, uint32_t mask) |
200 | { | |
201 | TCGv tmp_mask = tcg_const_i32(mask); | |
202 | gen_helper_cpsr_write(var, tmp_mask); | |
203 | tcg_temp_free_i32(tmp_mask); | |
204 | } | |
d9ba4830 PB |
205 | /* Set NZCV flags from the high 4 bits of var. */ |
206 | #define gen_set_nzcv(var) gen_set_cpsr(var, CPSR_NZCV) | |
207 | ||
208 | static void gen_exception(int excp) | |
209 | { | |
7d1b0095 | 210 | TCGv tmp = tcg_temp_new_i32(); |
d9ba4830 PB |
211 | tcg_gen_movi_i32(tmp, excp); |
212 | gen_helper_exception(tmp); | |
7d1b0095 | 213 | tcg_temp_free_i32(tmp); |
d9ba4830 PB |
214 | } |
215 | ||
3670669c PB |
216 | static void gen_smul_dual(TCGv a, TCGv b) |
217 | { | |
7d1b0095 PM |
218 | TCGv tmp1 = tcg_temp_new_i32(); |
219 | TCGv tmp2 = tcg_temp_new_i32(); | |
22478e79 AZ |
220 | tcg_gen_ext16s_i32(tmp1, a); |
221 | tcg_gen_ext16s_i32(tmp2, b); | |
3670669c | 222 | tcg_gen_mul_i32(tmp1, tmp1, tmp2); |
7d1b0095 | 223 | tcg_temp_free_i32(tmp2); |
3670669c PB |
224 | tcg_gen_sari_i32(a, a, 16); |
225 | tcg_gen_sari_i32(b, b, 16); | |
226 | tcg_gen_mul_i32(b, b, a); | |
227 | tcg_gen_mov_i32(a, tmp1); | |
7d1b0095 | 228 | tcg_temp_free_i32(tmp1); |
3670669c PB |
229 | } |
230 | ||
231 | /* Byteswap each halfword. */ | |
232 | static void gen_rev16(TCGv var) | |
233 | { | |
7d1b0095 | 234 | TCGv tmp = tcg_temp_new_i32(); |
3670669c PB |
235 | tcg_gen_shri_i32(tmp, var, 8); |
236 | tcg_gen_andi_i32(tmp, tmp, 0x00ff00ff); | |
237 | tcg_gen_shli_i32(var, var, 8); | |
238 | tcg_gen_andi_i32(var, var, 0xff00ff00); | |
239 | tcg_gen_or_i32(var, var, tmp); | |
7d1b0095 | 240 | tcg_temp_free_i32(tmp); |
3670669c PB |
241 | } |
242 | ||
243 | /* Byteswap low halfword and sign extend. */ | |
244 | static void gen_revsh(TCGv var) | |
245 | { | |
1a855029 AJ |
246 | tcg_gen_ext16u_i32(var, var); |
247 | tcg_gen_bswap16_i32(var, var); | |
248 | tcg_gen_ext16s_i32(var, var); | |
3670669c PB |
249 | } |
250 | ||
251 | /* Unsigned bitfield extract. */ | |
252 | static void gen_ubfx(TCGv var, int shift, uint32_t mask) | |
253 | { | |
254 | if (shift) | |
255 | tcg_gen_shri_i32(var, var, shift); | |
256 | tcg_gen_andi_i32(var, var, mask); | |
257 | } | |
258 | ||
259 | /* Signed bitfield extract. */ | |
260 | static void gen_sbfx(TCGv var, int shift, int width) | |
261 | { | |
262 | uint32_t signbit; | |
263 | ||
264 | if (shift) | |
265 | tcg_gen_sari_i32(var, var, shift); | |
266 | if (shift + width < 32) { | |
267 | signbit = 1u << (width - 1); | |
268 | tcg_gen_andi_i32(var, var, (1u << width) - 1); | |
269 | tcg_gen_xori_i32(var, var, signbit); | |
270 | tcg_gen_subi_i32(var, var, signbit); | |
271 | } | |
272 | } | |
273 | ||
274 | /* Bitfield insertion. Insert val into base. Clobbers base and val. */ | |
275 | static void gen_bfi(TCGv dest, TCGv base, TCGv val, int shift, uint32_t mask) | |
276 | { | |
3670669c | 277 | tcg_gen_andi_i32(val, val, mask); |
8f8e3aa4 PB |
278 | tcg_gen_shli_i32(val, val, shift); |
279 | tcg_gen_andi_i32(base, base, ~(mask << shift)); | |
3670669c PB |
280 | tcg_gen_or_i32(dest, base, val); |
281 | } | |
282 | ||
838fa72d AJ |
283 | /* Return (b << 32) + a. Mark inputs as dead */ |
284 | static TCGv_i64 gen_addq_msw(TCGv_i64 a, TCGv b) | |
3670669c | 285 | { |
838fa72d AJ |
286 | TCGv_i64 tmp64 = tcg_temp_new_i64(); |
287 | ||
288 | tcg_gen_extu_i32_i64(tmp64, b); | |
7d1b0095 | 289 | tcg_temp_free_i32(b); |
838fa72d AJ |
290 | tcg_gen_shli_i64(tmp64, tmp64, 32); |
291 | tcg_gen_add_i64(a, tmp64, a); | |
292 | ||
293 | tcg_temp_free_i64(tmp64); | |
294 | return a; | |
295 | } | |
296 | ||
297 | /* Return (b << 32) - a. Mark inputs as dead. */ | |
298 | static TCGv_i64 gen_subq_msw(TCGv_i64 a, TCGv b) | |
299 | { | |
300 | TCGv_i64 tmp64 = tcg_temp_new_i64(); | |
301 | ||
302 | tcg_gen_extu_i32_i64(tmp64, b); | |
7d1b0095 | 303 | tcg_temp_free_i32(b); |
838fa72d AJ |
304 | tcg_gen_shli_i64(tmp64, tmp64, 32); |
305 | tcg_gen_sub_i64(a, tmp64, a); | |
306 | ||
307 | tcg_temp_free_i64(tmp64); | |
308 | return a; | |
3670669c PB |
309 | } |
310 | ||
8f01245e PB |
311 | /* FIXME: Most targets have native widening multiplication. |
312 | It would be good to use that instead of a full wide multiply. */ | |
5e3f878a | 313 | /* 32x32->64 multiply. Marks inputs as dead. */ |
a7812ae4 | 314 | static TCGv_i64 gen_mulu_i64_i32(TCGv a, TCGv b) |
5e3f878a | 315 | { |
a7812ae4 PB |
316 | TCGv_i64 tmp1 = tcg_temp_new_i64(); |
317 | TCGv_i64 tmp2 = tcg_temp_new_i64(); | |
5e3f878a PB |
318 | |
319 | tcg_gen_extu_i32_i64(tmp1, a); | |
7d1b0095 | 320 | tcg_temp_free_i32(a); |
5e3f878a | 321 | tcg_gen_extu_i32_i64(tmp2, b); |
7d1b0095 | 322 | tcg_temp_free_i32(b); |
5e3f878a | 323 | tcg_gen_mul_i64(tmp1, tmp1, tmp2); |
b75263d6 | 324 | tcg_temp_free_i64(tmp2); |
5e3f878a PB |
325 | return tmp1; |
326 | } | |
327 | ||
a7812ae4 | 328 | static TCGv_i64 gen_muls_i64_i32(TCGv a, TCGv b) |
5e3f878a | 329 | { |
a7812ae4 PB |
330 | TCGv_i64 tmp1 = tcg_temp_new_i64(); |
331 | TCGv_i64 tmp2 = tcg_temp_new_i64(); | |
5e3f878a PB |
332 | |
333 | tcg_gen_ext_i32_i64(tmp1, a); | |
7d1b0095 | 334 | tcg_temp_free_i32(a); |
5e3f878a | 335 | tcg_gen_ext_i32_i64(tmp2, b); |
7d1b0095 | 336 | tcg_temp_free_i32(b); |
5e3f878a | 337 | tcg_gen_mul_i64(tmp1, tmp1, tmp2); |
b75263d6 | 338 | tcg_temp_free_i64(tmp2); |
5e3f878a PB |
339 | return tmp1; |
340 | } | |
341 | ||
8f01245e PB |
342 | /* Swap low and high halfwords. */ |
343 | static void gen_swap_half(TCGv var) | |
344 | { | |
7d1b0095 | 345 | TCGv tmp = tcg_temp_new_i32(); |
8f01245e PB |
346 | tcg_gen_shri_i32(tmp, var, 16); |
347 | tcg_gen_shli_i32(var, var, 16); | |
348 | tcg_gen_or_i32(var, var, tmp); | |
7d1b0095 | 349 | tcg_temp_free_i32(tmp); |
8f01245e PB |
350 | } |
351 | ||
b26eefb6 PB |
352 | /* Dual 16-bit add. Result placed in t0 and t1 is marked as dead. |
353 | tmp = (t0 ^ t1) & 0x8000; | |
354 | t0 &= ~0x8000; | |
355 | t1 &= ~0x8000; | |
356 | t0 = (t0 + t1) ^ tmp; | |
357 | */ | |
358 | ||
359 | static void gen_add16(TCGv t0, TCGv t1) | |
360 | { | |
7d1b0095 | 361 | TCGv tmp = tcg_temp_new_i32(); |
b26eefb6 PB |
362 | tcg_gen_xor_i32(tmp, t0, t1); |
363 | tcg_gen_andi_i32(tmp, tmp, 0x8000); | |
364 | tcg_gen_andi_i32(t0, t0, ~0x8000); | |
365 | tcg_gen_andi_i32(t1, t1, ~0x8000); | |
366 | tcg_gen_add_i32(t0, t0, t1); | |
367 | tcg_gen_xor_i32(t0, t0, tmp); | |
7d1b0095 PM |
368 | tcg_temp_free_i32(tmp); |
369 | tcg_temp_free_i32(t1); | |
b26eefb6 PB |
370 | } |
371 | ||
9a119ff6 PB |
372 | #define gen_set_CF(var) tcg_gen_st_i32(var, cpu_env, offsetof(CPUState, CF)) |
373 | ||
b26eefb6 PB |
374 | /* Set CF to the top bit of var. */ |
375 | static void gen_set_CF_bit31(TCGv var) | |
376 | { | |
7d1b0095 | 377 | TCGv tmp = tcg_temp_new_i32(); |
b26eefb6 | 378 | tcg_gen_shri_i32(tmp, var, 31); |
4cc633c3 | 379 | gen_set_CF(tmp); |
7d1b0095 | 380 | tcg_temp_free_i32(tmp); |
b26eefb6 PB |
381 | } |
382 | ||
383 | /* Set N and Z flags from var. */ | |
384 | static inline void gen_logic_CC(TCGv var) | |
385 | { | |
6fbe23d5 PB |
386 | tcg_gen_st_i32(var, cpu_env, offsetof(CPUState, NF)); |
387 | tcg_gen_st_i32(var, cpu_env, offsetof(CPUState, ZF)); | |
b26eefb6 PB |
388 | } |
389 | ||
390 | /* T0 += T1 + CF. */ | |
396e467c | 391 | static void gen_adc(TCGv t0, TCGv t1) |
b26eefb6 | 392 | { |
d9ba4830 | 393 | TCGv tmp; |
396e467c | 394 | tcg_gen_add_i32(t0, t0, t1); |
d9ba4830 | 395 | tmp = load_cpu_field(CF); |
396e467c | 396 | tcg_gen_add_i32(t0, t0, tmp); |
7d1b0095 | 397 | tcg_temp_free_i32(tmp); |
b26eefb6 PB |
398 | } |
399 | ||
e9bb4aa9 JR |
400 | /* dest = T0 + T1 + CF. */ |
401 | static void gen_add_carry(TCGv dest, TCGv t0, TCGv t1) | |
402 | { | |
403 | TCGv tmp; | |
404 | tcg_gen_add_i32(dest, t0, t1); | |
405 | tmp = load_cpu_field(CF); | |
406 | tcg_gen_add_i32(dest, dest, tmp); | |
7d1b0095 | 407 | tcg_temp_free_i32(tmp); |
e9bb4aa9 JR |
408 | } |
409 | ||
3670669c PB |
410 | /* dest = T0 - T1 + CF - 1. */ |
411 | static void gen_sub_carry(TCGv dest, TCGv t0, TCGv t1) | |
412 | { | |
d9ba4830 | 413 | TCGv tmp; |
3670669c | 414 | tcg_gen_sub_i32(dest, t0, t1); |
d9ba4830 | 415 | tmp = load_cpu_field(CF); |
3670669c PB |
416 | tcg_gen_add_i32(dest, dest, tmp); |
417 | tcg_gen_subi_i32(dest, dest, 1); | |
7d1b0095 | 418 | tcg_temp_free_i32(tmp); |
3670669c PB |
419 | } |
420 | ||
ad69471c PB |
421 | /* FIXME: Implement this natively. */ |
422 | #define tcg_gen_abs_i32(t0, t1) gen_helper_abs(t0, t1) | |
423 | ||
9a119ff6 | 424 | static void shifter_out_im(TCGv var, int shift) |
b26eefb6 | 425 | { |
7d1b0095 | 426 | TCGv tmp = tcg_temp_new_i32(); |
9a119ff6 PB |
427 | if (shift == 0) { |
428 | tcg_gen_andi_i32(tmp, var, 1); | |
b26eefb6 | 429 | } else { |
9a119ff6 | 430 | tcg_gen_shri_i32(tmp, var, shift); |
4cc633c3 | 431 | if (shift != 31) |
9a119ff6 PB |
432 | tcg_gen_andi_i32(tmp, tmp, 1); |
433 | } | |
434 | gen_set_CF(tmp); | |
7d1b0095 | 435 | tcg_temp_free_i32(tmp); |
9a119ff6 | 436 | } |
b26eefb6 | 437 | |
9a119ff6 PB |
438 | /* Shift by immediate. Includes special handling for shift == 0. */ |
439 | static inline void gen_arm_shift_im(TCGv var, int shiftop, int shift, int flags) | |
440 | { | |
441 | switch (shiftop) { | |
442 | case 0: /* LSL */ | |
443 | if (shift != 0) { | |
444 | if (flags) | |
445 | shifter_out_im(var, 32 - shift); | |
446 | tcg_gen_shli_i32(var, var, shift); | |
447 | } | |
448 | break; | |
449 | case 1: /* LSR */ | |
450 | if (shift == 0) { | |
451 | if (flags) { | |
452 | tcg_gen_shri_i32(var, var, 31); | |
453 | gen_set_CF(var); | |
454 | } | |
455 | tcg_gen_movi_i32(var, 0); | |
456 | } else { | |
457 | if (flags) | |
458 | shifter_out_im(var, shift - 1); | |
459 | tcg_gen_shri_i32(var, var, shift); | |
460 | } | |
461 | break; | |
462 | case 2: /* ASR */ | |
463 | if (shift == 0) | |
464 | shift = 32; | |
465 | if (flags) | |
466 | shifter_out_im(var, shift - 1); | |
467 | if (shift == 32) | |
468 | shift = 31; | |
469 | tcg_gen_sari_i32(var, var, shift); | |
470 | break; | |
471 | case 3: /* ROR/RRX */ | |
472 | if (shift != 0) { | |
473 | if (flags) | |
474 | shifter_out_im(var, shift - 1); | |
f669df27 | 475 | tcg_gen_rotri_i32(var, var, shift); break; |
9a119ff6 | 476 | } else { |
d9ba4830 | 477 | TCGv tmp = load_cpu_field(CF); |
9a119ff6 PB |
478 | if (flags) |
479 | shifter_out_im(var, 0); | |
480 | tcg_gen_shri_i32(var, var, 1); | |
b26eefb6 PB |
481 | tcg_gen_shli_i32(tmp, tmp, 31); |
482 | tcg_gen_or_i32(var, var, tmp); | |
7d1b0095 | 483 | tcg_temp_free_i32(tmp); |
b26eefb6 PB |
484 | } |
485 | } | |
486 | }; | |
487 | ||
8984bd2e PB |
488 | static inline void gen_arm_shift_reg(TCGv var, int shiftop, |
489 | TCGv shift, int flags) | |
490 | { | |
491 | if (flags) { | |
492 | switch (shiftop) { | |
493 | case 0: gen_helper_shl_cc(var, var, shift); break; | |
494 | case 1: gen_helper_shr_cc(var, var, shift); break; | |
495 | case 2: gen_helper_sar_cc(var, var, shift); break; | |
496 | case 3: gen_helper_ror_cc(var, var, shift); break; | |
497 | } | |
498 | } else { | |
499 | switch (shiftop) { | |
500 | case 0: gen_helper_shl(var, var, shift); break; | |
501 | case 1: gen_helper_shr(var, var, shift); break; | |
502 | case 2: gen_helper_sar(var, var, shift); break; | |
f669df27 AJ |
503 | case 3: tcg_gen_andi_i32(shift, shift, 0x1f); |
504 | tcg_gen_rotr_i32(var, var, shift); break; | |
8984bd2e PB |
505 | } |
506 | } | |
7d1b0095 | 507 | tcg_temp_free_i32(shift); |
8984bd2e PB |
508 | } |
509 | ||
6ddbc6e4 PB |
510 | #define PAS_OP(pfx) \ |
511 | switch (op2) { \ | |
512 | case 0: gen_pas_helper(glue(pfx,add16)); break; \ | |
513 | case 1: gen_pas_helper(glue(pfx,addsubx)); break; \ | |
514 | case 2: gen_pas_helper(glue(pfx,subaddx)); break; \ | |
515 | case 3: gen_pas_helper(glue(pfx,sub16)); break; \ | |
516 | case 4: gen_pas_helper(glue(pfx,add8)); break; \ | |
517 | case 7: gen_pas_helper(glue(pfx,sub8)); break; \ | |
518 | } | |
d9ba4830 | 519 | static void gen_arm_parallel_addsub(int op1, int op2, TCGv a, TCGv b) |
6ddbc6e4 | 520 | { |
a7812ae4 | 521 | TCGv_ptr tmp; |
6ddbc6e4 PB |
522 | |
523 | switch (op1) { | |
524 | #define gen_pas_helper(name) glue(gen_helper_,name)(a, a, b, tmp) | |
525 | case 1: | |
a7812ae4 | 526 | tmp = tcg_temp_new_ptr(); |
6ddbc6e4 PB |
527 | tcg_gen_addi_ptr(tmp, cpu_env, offsetof(CPUState, GE)); |
528 | PAS_OP(s) | |
b75263d6 | 529 | tcg_temp_free_ptr(tmp); |
6ddbc6e4 PB |
530 | break; |
531 | case 5: | |
a7812ae4 | 532 | tmp = tcg_temp_new_ptr(); |
6ddbc6e4 PB |
533 | tcg_gen_addi_ptr(tmp, cpu_env, offsetof(CPUState, GE)); |
534 | PAS_OP(u) | |
b75263d6 | 535 | tcg_temp_free_ptr(tmp); |
6ddbc6e4 PB |
536 | break; |
537 | #undef gen_pas_helper | |
538 | #define gen_pas_helper(name) glue(gen_helper_,name)(a, a, b) | |
539 | case 2: | |
540 | PAS_OP(q); | |
541 | break; | |
542 | case 3: | |
543 | PAS_OP(sh); | |
544 | break; | |
545 | case 6: | |
546 | PAS_OP(uq); | |
547 | break; | |
548 | case 7: | |
549 | PAS_OP(uh); | |
550 | break; | |
551 | #undef gen_pas_helper | |
552 | } | |
553 | } | |
9ee6e8bb PB |
554 | #undef PAS_OP |
555 | ||
6ddbc6e4 PB |
556 | /* For unknown reasons Arm and Thumb-2 use arbitrarily different encodings. */ |
557 | #define PAS_OP(pfx) \ | |
ed89a2f1 | 558 | switch (op1) { \ |
6ddbc6e4 PB |
559 | case 0: gen_pas_helper(glue(pfx,add8)); break; \ |
560 | case 1: gen_pas_helper(glue(pfx,add16)); break; \ | |
561 | case 2: gen_pas_helper(glue(pfx,addsubx)); break; \ | |
562 | case 4: gen_pas_helper(glue(pfx,sub8)); break; \ | |
563 | case 5: gen_pas_helper(glue(pfx,sub16)); break; \ | |
564 | case 6: gen_pas_helper(glue(pfx,subaddx)); break; \ | |
565 | } | |
d9ba4830 | 566 | static void gen_thumb2_parallel_addsub(int op1, int op2, TCGv a, TCGv b) |
6ddbc6e4 | 567 | { |
a7812ae4 | 568 | TCGv_ptr tmp; |
6ddbc6e4 | 569 | |
ed89a2f1 | 570 | switch (op2) { |
6ddbc6e4 PB |
571 | #define gen_pas_helper(name) glue(gen_helper_,name)(a, a, b, tmp) |
572 | case 0: | |
a7812ae4 | 573 | tmp = tcg_temp_new_ptr(); |
6ddbc6e4 PB |
574 | tcg_gen_addi_ptr(tmp, cpu_env, offsetof(CPUState, GE)); |
575 | PAS_OP(s) | |
b75263d6 | 576 | tcg_temp_free_ptr(tmp); |
6ddbc6e4 PB |
577 | break; |
578 | case 4: | |
a7812ae4 | 579 | tmp = tcg_temp_new_ptr(); |
6ddbc6e4 PB |
580 | tcg_gen_addi_ptr(tmp, cpu_env, offsetof(CPUState, GE)); |
581 | PAS_OP(u) | |
b75263d6 | 582 | tcg_temp_free_ptr(tmp); |
6ddbc6e4 PB |
583 | break; |
584 | #undef gen_pas_helper | |
585 | #define gen_pas_helper(name) glue(gen_helper_,name)(a, a, b) | |
586 | case 1: | |
587 | PAS_OP(q); | |
588 | break; | |
589 | case 2: | |
590 | PAS_OP(sh); | |
591 | break; | |
592 | case 5: | |
593 | PAS_OP(uq); | |
594 | break; | |
595 | case 6: | |
596 | PAS_OP(uh); | |
597 | break; | |
598 | #undef gen_pas_helper | |
599 | } | |
600 | } | |
9ee6e8bb PB |
601 | #undef PAS_OP |
602 | ||
d9ba4830 PB |
603 | static void gen_test_cc(int cc, int label) |
604 | { | |
605 | TCGv tmp; | |
606 | TCGv tmp2; | |
d9ba4830 PB |
607 | int inv; |
608 | ||
d9ba4830 PB |
609 | switch (cc) { |
610 | case 0: /* eq: Z */ | |
6fbe23d5 | 611 | tmp = load_cpu_field(ZF); |
cb63669a | 612 | tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, label); |
d9ba4830 PB |
613 | break; |
614 | case 1: /* ne: !Z */ | |
6fbe23d5 | 615 | tmp = load_cpu_field(ZF); |
cb63669a | 616 | tcg_gen_brcondi_i32(TCG_COND_NE, tmp, 0, label); |
d9ba4830 PB |
617 | break; |
618 | case 2: /* cs: C */ | |
619 | tmp = load_cpu_field(CF); | |
cb63669a | 620 | tcg_gen_brcondi_i32(TCG_COND_NE, tmp, 0, label); |
d9ba4830 PB |
621 | break; |
622 | case 3: /* cc: !C */ | |
623 | tmp = load_cpu_field(CF); | |
cb63669a | 624 | tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, label); |
d9ba4830 PB |
625 | break; |
626 | case 4: /* mi: N */ | |
6fbe23d5 | 627 | tmp = load_cpu_field(NF); |
cb63669a | 628 | tcg_gen_brcondi_i32(TCG_COND_LT, tmp, 0, label); |
d9ba4830 PB |
629 | break; |
630 | case 5: /* pl: !N */ | |
6fbe23d5 | 631 | tmp = load_cpu_field(NF); |
cb63669a | 632 | tcg_gen_brcondi_i32(TCG_COND_GE, tmp, 0, label); |
d9ba4830 PB |
633 | break; |
634 | case 6: /* vs: V */ | |
635 | tmp = load_cpu_field(VF); | |
cb63669a | 636 | tcg_gen_brcondi_i32(TCG_COND_LT, tmp, 0, label); |
d9ba4830 PB |
637 | break; |
638 | case 7: /* vc: !V */ | |
639 | tmp = load_cpu_field(VF); | |
cb63669a | 640 | tcg_gen_brcondi_i32(TCG_COND_GE, tmp, 0, label); |
d9ba4830 PB |
641 | break; |
642 | case 8: /* hi: C && !Z */ | |
643 | inv = gen_new_label(); | |
644 | tmp = load_cpu_field(CF); | |
cb63669a | 645 | tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, inv); |
7d1b0095 | 646 | tcg_temp_free_i32(tmp); |
6fbe23d5 | 647 | tmp = load_cpu_field(ZF); |
cb63669a | 648 | tcg_gen_brcondi_i32(TCG_COND_NE, tmp, 0, label); |
d9ba4830 PB |
649 | gen_set_label(inv); |
650 | break; | |
651 | case 9: /* ls: !C || Z */ | |
652 | tmp = load_cpu_field(CF); | |
cb63669a | 653 | tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, label); |
7d1b0095 | 654 | tcg_temp_free_i32(tmp); |
6fbe23d5 | 655 | tmp = load_cpu_field(ZF); |
cb63669a | 656 | tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, label); |
d9ba4830 PB |
657 | break; |
658 | case 10: /* ge: N == V -> N ^ V == 0 */ | |
659 | tmp = load_cpu_field(VF); | |
6fbe23d5 | 660 | tmp2 = load_cpu_field(NF); |
d9ba4830 | 661 | tcg_gen_xor_i32(tmp, tmp, tmp2); |
7d1b0095 | 662 | tcg_temp_free_i32(tmp2); |
cb63669a | 663 | tcg_gen_brcondi_i32(TCG_COND_GE, tmp, 0, label); |
d9ba4830 PB |
664 | break; |
665 | case 11: /* lt: N != V -> N ^ V != 0 */ | |
666 | tmp = load_cpu_field(VF); | |
6fbe23d5 | 667 | tmp2 = load_cpu_field(NF); |
d9ba4830 | 668 | tcg_gen_xor_i32(tmp, tmp, tmp2); |
7d1b0095 | 669 | tcg_temp_free_i32(tmp2); |
cb63669a | 670 | tcg_gen_brcondi_i32(TCG_COND_LT, tmp, 0, label); |
d9ba4830 PB |
671 | break; |
672 | case 12: /* gt: !Z && N == V */ | |
673 | inv = gen_new_label(); | |
6fbe23d5 | 674 | tmp = load_cpu_field(ZF); |
cb63669a | 675 | tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, inv); |
7d1b0095 | 676 | tcg_temp_free_i32(tmp); |
d9ba4830 | 677 | tmp = load_cpu_field(VF); |
6fbe23d5 | 678 | tmp2 = load_cpu_field(NF); |
d9ba4830 | 679 | tcg_gen_xor_i32(tmp, tmp, tmp2); |
7d1b0095 | 680 | tcg_temp_free_i32(tmp2); |
cb63669a | 681 | tcg_gen_brcondi_i32(TCG_COND_GE, tmp, 0, label); |
d9ba4830 PB |
682 | gen_set_label(inv); |
683 | break; | |
684 | case 13: /* le: Z || N != V */ | |
6fbe23d5 | 685 | tmp = load_cpu_field(ZF); |
cb63669a | 686 | tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, label); |
7d1b0095 | 687 | tcg_temp_free_i32(tmp); |
d9ba4830 | 688 | tmp = load_cpu_field(VF); |
6fbe23d5 | 689 | tmp2 = load_cpu_field(NF); |
d9ba4830 | 690 | tcg_gen_xor_i32(tmp, tmp, tmp2); |
7d1b0095 | 691 | tcg_temp_free_i32(tmp2); |
cb63669a | 692 | tcg_gen_brcondi_i32(TCG_COND_LT, tmp, 0, label); |
d9ba4830 PB |
693 | break; |
694 | default: | |
695 | fprintf(stderr, "Bad condition code 0x%x\n", cc); | |
696 | abort(); | |
697 | } | |
7d1b0095 | 698 | tcg_temp_free_i32(tmp); |
d9ba4830 | 699 | } |
2c0262af | 700 | |
b1d8e52e | 701 | static const uint8_t table_logic_cc[16] = { |
2c0262af FB |
702 | 1, /* and */ |
703 | 1, /* xor */ | |
704 | 0, /* sub */ | |
705 | 0, /* rsb */ | |
706 | 0, /* add */ | |
707 | 0, /* adc */ | |
708 | 0, /* sbc */ | |
709 | 0, /* rsc */ | |
710 | 1, /* andl */ | |
711 | 1, /* xorl */ | |
712 | 0, /* cmp */ | |
713 | 0, /* cmn */ | |
714 | 1, /* orr */ | |
715 | 1, /* mov */ | |
716 | 1, /* bic */ | |
717 | 1, /* mvn */ | |
718 | }; | |
3b46e624 | 719 | |
d9ba4830 PB |
720 | /* Set PC and Thumb state from an immediate address. */ |
721 | static inline void gen_bx_im(DisasContext *s, uint32_t addr) | |
99c475ab | 722 | { |
b26eefb6 | 723 | TCGv tmp; |
99c475ab | 724 | |
b26eefb6 | 725 | s->is_jmp = DISAS_UPDATE; |
d9ba4830 | 726 | if (s->thumb != (addr & 1)) { |
7d1b0095 | 727 | tmp = tcg_temp_new_i32(); |
d9ba4830 PB |
728 | tcg_gen_movi_i32(tmp, addr & 1); |
729 | tcg_gen_st_i32(tmp, cpu_env, offsetof(CPUState, thumb)); | |
7d1b0095 | 730 | tcg_temp_free_i32(tmp); |
d9ba4830 | 731 | } |
155c3eac | 732 | tcg_gen_movi_i32(cpu_R[15], addr & ~1); |
d9ba4830 PB |
733 | } |
734 | ||
735 | /* Set PC and Thumb state from var. var is marked as dead. */ | |
736 | static inline void gen_bx(DisasContext *s, TCGv var) | |
737 | { | |
d9ba4830 | 738 | s->is_jmp = DISAS_UPDATE; |
155c3eac FN |
739 | tcg_gen_andi_i32(cpu_R[15], var, ~1); |
740 | tcg_gen_andi_i32(var, var, 1); | |
741 | store_cpu_field(var, thumb); | |
d9ba4830 PB |
742 | } |
743 | ||
21aeb343 JR |
744 | /* Variant of store_reg which uses branch&exchange logic when storing |
745 | to r15 in ARM architecture v7 and above. The source must be a temporary | |
746 | and will be marked as dead. */ | |
747 | static inline void store_reg_bx(CPUState *env, DisasContext *s, | |
748 | int reg, TCGv var) | |
749 | { | |
750 | if (reg == 15 && ENABLE_ARCH_7) { | |
751 | gen_bx(s, var); | |
752 | } else { | |
753 | store_reg(s, reg, var); | |
754 | } | |
755 | } | |
756 | ||
be5e7a76 DES |
757 | /* Variant of store_reg which uses branch&exchange logic when storing |
758 | * to r15 in ARM architecture v5T and above. This is used for storing | |
759 | * the results of a LDR/LDM/POP into r15, and corresponds to the cases | |
760 | * in the ARM ARM which use the LoadWritePC() pseudocode function. */ | |
761 | static inline void store_reg_from_load(CPUState *env, DisasContext *s, | |
762 | int reg, TCGv var) | |
763 | { | |
764 | if (reg == 15 && ENABLE_ARCH_5) { | |
765 | gen_bx(s, var); | |
766 | } else { | |
767 | store_reg(s, reg, var); | |
768 | } | |
769 | } | |
770 | ||
b0109805 PB |
771 | static inline TCGv gen_ld8s(TCGv addr, int index) |
772 | { | |
7d1b0095 | 773 | TCGv tmp = tcg_temp_new_i32(); |
b0109805 PB |
774 | tcg_gen_qemu_ld8s(tmp, addr, index); |
775 | return tmp; | |
776 | } | |
777 | static inline TCGv gen_ld8u(TCGv addr, int index) | |
778 | { | |
7d1b0095 | 779 | TCGv tmp = tcg_temp_new_i32(); |
b0109805 PB |
780 | tcg_gen_qemu_ld8u(tmp, addr, index); |
781 | return tmp; | |
782 | } | |
783 | static inline TCGv gen_ld16s(TCGv addr, int index) | |
784 | { | |
7d1b0095 | 785 | TCGv tmp = tcg_temp_new_i32(); |
b0109805 PB |
786 | tcg_gen_qemu_ld16s(tmp, addr, index); |
787 | return tmp; | |
788 | } | |
789 | static inline TCGv gen_ld16u(TCGv addr, int index) | |
790 | { | |
7d1b0095 | 791 | TCGv tmp = tcg_temp_new_i32(); |
b0109805 PB |
792 | tcg_gen_qemu_ld16u(tmp, addr, index); |
793 | return tmp; | |
794 | } | |
795 | static inline TCGv gen_ld32(TCGv addr, int index) | |
796 | { | |
7d1b0095 | 797 | TCGv tmp = tcg_temp_new_i32(); |
b0109805 PB |
798 | tcg_gen_qemu_ld32u(tmp, addr, index); |
799 | return tmp; | |
800 | } | |
84496233 JR |
801 | static inline TCGv_i64 gen_ld64(TCGv addr, int index) |
802 | { | |
803 | TCGv_i64 tmp = tcg_temp_new_i64(); | |
804 | tcg_gen_qemu_ld64(tmp, addr, index); | |
805 | return tmp; | |
806 | } | |
b0109805 PB |
807 | static inline void gen_st8(TCGv val, TCGv addr, int index) |
808 | { | |
809 | tcg_gen_qemu_st8(val, addr, index); | |
7d1b0095 | 810 | tcg_temp_free_i32(val); |
b0109805 PB |
811 | } |
812 | static inline void gen_st16(TCGv val, TCGv addr, int index) | |
813 | { | |
814 | tcg_gen_qemu_st16(val, addr, index); | |
7d1b0095 | 815 | tcg_temp_free_i32(val); |
b0109805 PB |
816 | } |
817 | static inline void gen_st32(TCGv val, TCGv addr, int index) | |
818 | { | |
819 | tcg_gen_qemu_st32(val, addr, index); | |
7d1b0095 | 820 | tcg_temp_free_i32(val); |
b0109805 | 821 | } |
84496233 JR |
822 | static inline void gen_st64(TCGv_i64 val, TCGv addr, int index) |
823 | { | |
824 | tcg_gen_qemu_st64(val, addr, index); | |
825 | tcg_temp_free_i64(val); | |
826 | } | |
b5ff1b31 | 827 | |
5e3f878a PB |
828 | static inline void gen_set_pc_im(uint32_t val) |
829 | { | |
155c3eac | 830 | tcg_gen_movi_i32(cpu_R[15], val); |
5e3f878a PB |
831 | } |
832 | ||
b5ff1b31 FB |
833 | /* Force a TB lookup after an instruction that changes the CPU state. */ |
834 | static inline void gen_lookup_tb(DisasContext *s) | |
835 | { | |
a6445c52 | 836 | tcg_gen_movi_i32(cpu_R[15], s->pc & ~1); |
b5ff1b31 FB |
837 | s->is_jmp = DISAS_UPDATE; |
838 | } | |
839 | ||
b0109805 PB |
840 | static inline void gen_add_data_offset(DisasContext *s, unsigned int insn, |
841 | TCGv var) | |
2c0262af | 842 | { |
1e8d4eec | 843 | int val, rm, shift, shiftop; |
b26eefb6 | 844 | TCGv offset; |
2c0262af FB |
845 | |
846 | if (!(insn & (1 << 25))) { | |
847 | /* immediate */ | |
848 | val = insn & 0xfff; | |
849 | if (!(insn & (1 << 23))) | |
850 | val = -val; | |
537730b9 | 851 | if (val != 0) |
b0109805 | 852 | tcg_gen_addi_i32(var, var, val); |
2c0262af FB |
853 | } else { |
854 | /* shift/register */ | |
855 | rm = (insn) & 0xf; | |
856 | shift = (insn >> 7) & 0x1f; | |
1e8d4eec | 857 | shiftop = (insn >> 5) & 3; |
b26eefb6 | 858 | offset = load_reg(s, rm); |
9a119ff6 | 859 | gen_arm_shift_im(offset, shiftop, shift, 0); |
2c0262af | 860 | if (!(insn & (1 << 23))) |
b0109805 | 861 | tcg_gen_sub_i32(var, var, offset); |
2c0262af | 862 | else |
b0109805 | 863 | tcg_gen_add_i32(var, var, offset); |
7d1b0095 | 864 | tcg_temp_free_i32(offset); |
2c0262af FB |
865 | } |
866 | } | |
867 | ||
191f9a93 | 868 | static inline void gen_add_datah_offset(DisasContext *s, unsigned int insn, |
b0109805 | 869 | int extra, TCGv var) |
2c0262af FB |
870 | { |
871 | int val, rm; | |
b26eefb6 | 872 | TCGv offset; |
3b46e624 | 873 | |
2c0262af FB |
874 | if (insn & (1 << 22)) { |
875 | /* immediate */ | |
876 | val = (insn & 0xf) | ((insn >> 4) & 0xf0); | |
877 | if (!(insn & (1 << 23))) | |
878 | val = -val; | |
18acad92 | 879 | val += extra; |
537730b9 | 880 | if (val != 0) |
b0109805 | 881 | tcg_gen_addi_i32(var, var, val); |
2c0262af FB |
882 | } else { |
883 | /* register */ | |
191f9a93 | 884 | if (extra) |
b0109805 | 885 | tcg_gen_addi_i32(var, var, extra); |
2c0262af | 886 | rm = (insn) & 0xf; |
b26eefb6 | 887 | offset = load_reg(s, rm); |
2c0262af | 888 | if (!(insn & (1 << 23))) |
b0109805 | 889 | tcg_gen_sub_i32(var, var, offset); |
2c0262af | 890 | else |
b0109805 | 891 | tcg_gen_add_i32(var, var, offset); |
7d1b0095 | 892 | tcg_temp_free_i32(offset); |
2c0262af FB |
893 | } |
894 | } | |
895 | ||
4373f3ce PB |
896 | #define VFP_OP2(name) \ |
897 | static inline void gen_vfp_##name(int dp) \ | |
898 | { \ | |
899 | if (dp) \ | |
900 | gen_helper_vfp_##name##d(cpu_F0d, cpu_F0d, cpu_F1d, cpu_env); \ | |
901 | else \ | |
902 | gen_helper_vfp_##name##s(cpu_F0s, cpu_F0s, cpu_F1s, cpu_env); \ | |
b7bcbe95 FB |
903 | } |
904 | ||
4373f3ce PB |
905 | VFP_OP2(add) |
906 | VFP_OP2(sub) | |
907 | VFP_OP2(mul) | |
908 | VFP_OP2(div) | |
909 | ||
910 | #undef VFP_OP2 | |
911 | ||
912 | static inline void gen_vfp_abs(int dp) | |
913 | { | |
914 | if (dp) | |
915 | gen_helper_vfp_absd(cpu_F0d, cpu_F0d); | |
916 | else | |
917 | gen_helper_vfp_abss(cpu_F0s, cpu_F0s); | |
918 | } | |
919 | ||
920 | static inline void gen_vfp_neg(int dp) | |
921 | { | |
922 | if (dp) | |
923 | gen_helper_vfp_negd(cpu_F0d, cpu_F0d); | |
924 | else | |
925 | gen_helper_vfp_negs(cpu_F0s, cpu_F0s); | |
926 | } | |
927 | ||
928 | static inline void gen_vfp_sqrt(int dp) | |
929 | { | |
930 | if (dp) | |
931 | gen_helper_vfp_sqrtd(cpu_F0d, cpu_F0d, cpu_env); | |
932 | else | |
933 | gen_helper_vfp_sqrts(cpu_F0s, cpu_F0s, cpu_env); | |
934 | } | |
935 | ||
936 | static inline void gen_vfp_cmp(int dp) | |
937 | { | |
938 | if (dp) | |
939 | gen_helper_vfp_cmpd(cpu_F0d, cpu_F1d, cpu_env); | |
940 | else | |
941 | gen_helper_vfp_cmps(cpu_F0s, cpu_F1s, cpu_env); | |
942 | } | |
943 | ||
944 | static inline void gen_vfp_cmpe(int dp) | |
945 | { | |
946 | if (dp) | |
947 | gen_helper_vfp_cmped(cpu_F0d, cpu_F1d, cpu_env); | |
948 | else | |
949 | gen_helper_vfp_cmpes(cpu_F0s, cpu_F1s, cpu_env); | |
950 | } | |
951 | ||
952 | static inline void gen_vfp_F1_ld0(int dp) | |
953 | { | |
954 | if (dp) | |
5b340b51 | 955 | tcg_gen_movi_i64(cpu_F1d, 0); |
4373f3ce | 956 | else |
5b340b51 | 957 | tcg_gen_movi_i32(cpu_F1s, 0); |
4373f3ce PB |
958 | } |
959 | ||
960 | static inline void gen_vfp_uito(int dp) | |
961 | { | |
962 | if (dp) | |
963 | gen_helper_vfp_uitod(cpu_F0d, cpu_F0s, cpu_env); | |
964 | else | |
965 | gen_helper_vfp_uitos(cpu_F0s, cpu_F0s, cpu_env); | |
966 | } | |
967 | ||
968 | static inline void gen_vfp_sito(int dp) | |
969 | { | |
970 | if (dp) | |
66230e0d | 971 | gen_helper_vfp_sitod(cpu_F0d, cpu_F0s, cpu_env); |
4373f3ce | 972 | else |
66230e0d | 973 | gen_helper_vfp_sitos(cpu_F0s, cpu_F0s, cpu_env); |
4373f3ce PB |
974 | } |
975 | ||
976 | static inline void gen_vfp_toui(int dp) | |
977 | { | |
978 | if (dp) | |
979 | gen_helper_vfp_touid(cpu_F0s, cpu_F0d, cpu_env); | |
980 | else | |
981 | gen_helper_vfp_touis(cpu_F0s, cpu_F0s, cpu_env); | |
982 | } | |
983 | ||
984 | static inline void gen_vfp_touiz(int dp) | |
985 | { | |
986 | if (dp) | |
987 | gen_helper_vfp_touizd(cpu_F0s, cpu_F0d, cpu_env); | |
988 | else | |
989 | gen_helper_vfp_touizs(cpu_F0s, cpu_F0s, cpu_env); | |
990 | } | |
991 | ||
992 | static inline void gen_vfp_tosi(int dp) | |
993 | { | |
994 | if (dp) | |
995 | gen_helper_vfp_tosid(cpu_F0s, cpu_F0d, cpu_env); | |
996 | else | |
997 | gen_helper_vfp_tosis(cpu_F0s, cpu_F0s, cpu_env); | |
998 | } | |
999 | ||
1000 | static inline void gen_vfp_tosiz(int dp) | |
9ee6e8bb PB |
1001 | { |
1002 | if (dp) | |
4373f3ce | 1003 | gen_helper_vfp_tosizd(cpu_F0s, cpu_F0d, cpu_env); |
9ee6e8bb | 1004 | else |
4373f3ce PB |
1005 | gen_helper_vfp_tosizs(cpu_F0s, cpu_F0s, cpu_env); |
1006 | } | |
1007 | ||
1008 | #define VFP_GEN_FIX(name) \ | |
1009 | static inline void gen_vfp_##name(int dp, int shift) \ | |
1010 | { \ | |
b75263d6 | 1011 | TCGv tmp_shift = tcg_const_i32(shift); \ |
4373f3ce | 1012 | if (dp) \ |
b75263d6 | 1013 | gen_helper_vfp_##name##d(cpu_F0d, cpu_F0d, tmp_shift, cpu_env);\ |
4373f3ce | 1014 | else \ |
b75263d6 JR |
1015 | gen_helper_vfp_##name##s(cpu_F0s, cpu_F0s, tmp_shift, cpu_env);\ |
1016 | tcg_temp_free_i32(tmp_shift); \ | |
9ee6e8bb | 1017 | } |
4373f3ce PB |
1018 | VFP_GEN_FIX(tosh) |
1019 | VFP_GEN_FIX(tosl) | |
1020 | VFP_GEN_FIX(touh) | |
1021 | VFP_GEN_FIX(toul) | |
1022 | VFP_GEN_FIX(shto) | |
1023 | VFP_GEN_FIX(slto) | |
1024 | VFP_GEN_FIX(uhto) | |
1025 | VFP_GEN_FIX(ulto) | |
1026 | #undef VFP_GEN_FIX | |
9ee6e8bb | 1027 | |
312eea9f | 1028 | static inline void gen_vfp_ld(DisasContext *s, int dp, TCGv addr) |
b5ff1b31 FB |
1029 | { |
1030 | if (dp) | |
312eea9f | 1031 | tcg_gen_qemu_ld64(cpu_F0d, addr, IS_USER(s)); |
b5ff1b31 | 1032 | else |
312eea9f | 1033 | tcg_gen_qemu_ld32u(cpu_F0s, addr, IS_USER(s)); |
b5ff1b31 FB |
1034 | } |
1035 | ||
312eea9f | 1036 | static inline void gen_vfp_st(DisasContext *s, int dp, TCGv addr) |
b5ff1b31 FB |
1037 | { |
1038 | if (dp) | |
312eea9f | 1039 | tcg_gen_qemu_st64(cpu_F0d, addr, IS_USER(s)); |
b5ff1b31 | 1040 | else |
312eea9f | 1041 | tcg_gen_qemu_st32(cpu_F0s, addr, IS_USER(s)); |
b5ff1b31 FB |
1042 | } |
1043 | ||
8e96005d FB |
1044 | static inline long |
1045 | vfp_reg_offset (int dp, int reg) | |
1046 | { | |
1047 | if (dp) | |
1048 | return offsetof(CPUARMState, vfp.regs[reg]); | |
1049 | else if (reg & 1) { | |
1050 | return offsetof(CPUARMState, vfp.regs[reg >> 1]) | |
1051 | + offsetof(CPU_DoubleU, l.upper); | |
1052 | } else { | |
1053 | return offsetof(CPUARMState, vfp.regs[reg >> 1]) | |
1054 | + offsetof(CPU_DoubleU, l.lower); | |
1055 | } | |
1056 | } | |
9ee6e8bb PB |
1057 | |
1058 | /* Return the offset of a 32-bit piece of a NEON register. | |
1059 | zero is the least significant end of the register. */ | |
1060 | static inline long | |
1061 | neon_reg_offset (int reg, int n) | |
1062 | { | |
1063 | int sreg; | |
1064 | sreg = reg * 2 + n; | |
1065 | return vfp_reg_offset(0, sreg); | |
1066 | } | |
1067 | ||
8f8e3aa4 PB |
1068 | static TCGv neon_load_reg(int reg, int pass) |
1069 | { | |
7d1b0095 | 1070 | TCGv tmp = tcg_temp_new_i32(); |
8f8e3aa4 PB |
1071 | tcg_gen_ld_i32(tmp, cpu_env, neon_reg_offset(reg, pass)); |
1072 | return tmp; | |
1073 | } | |
1074 | ||
1075 | static void neon_store_reg(int reg, int pass, TCGv var) | |
1076 | { | |
1077 | tcg_gen_st_i32(var, cpu_env, neon_reg_offset(reg, pass)); | |
7d1b0095 | 1078 | tcg_temp_free_i32(var); |
8f8e3aa4 PB |
1079 | } |
1080 | ||
a7812ae4 | 1081 | static inline void neon_load_reg64(TCGv_i64 var, int reg) |
ad69471c PB |
1082 | { |
1083 | tcg_gen_ld_i64(var, cpu_env, vfp_reg_offset(1, reg)); | |
1084 | } | |
1085 | ||
a7812ae4 | 1086 | static inline void neon_store_reg64(TCGv_i64 var, int reg) |
ad69471c PB |
1087 | { |
1088 | tcg_gen_st_i64(var, cpu_env, vfp_reg_offset(1, reg)); | |
1089 | } | |
1090 | ||
4373f3ce PB |
1091 | #define tcg_gen_ld_f32 tcg_gen_ld_i32 |
1092 | #define tcg_gen_ld_f64 tcg_gen_ld_i64 | |
1093 | #define tcg_gen_st_f32 tcg_gen_st_i32 | |
1094 | #define tcg_gen_st_f64 tcg_gen_st_i64 | |
1095 | ||
b7bcbe95 FB |
1096 | static inline void gen_mov_F0_vreg(int dp, int reg) |
1097 | { | |
1098 | if (dp) | |
4373f3ce | 1099 | tcg_gen_ld_f64(cpu_F0d, cpu_env, vfp_reg_offset(dp, reg)); |
b7bcbe95 | 1100 | else |
4373f3ce | 1101 | tcg_gen_ld_f32(cpu_F0s, cpu_env, vfp_reg_offset(dp, reg)); |
b7bcbe95 FB |
1102 | } |
1103 | ||
1104 | static inline void gen_mov_F1_vreg(int dp, int reg) | |
1105 | { | |
1106 | if (dp) | |
4373f3ce | 1107 | tcg_gen_ld_f64(cpu_F1d, cpu_env, vfp_reg_offset(dp, reg)); |
b7bcbe95 | 1108 | else |
4373f3ce | 1109 | tcg_gen_ld_f32(cpu_F1s, cpu_env, vfp_reg_offset(dp, reg)); |
b7bcbe95 FB |
1110 | } |
1111 | ||
1112 | static inline void gen_mov_vreg_F0(int dp, int reg) | |
1113 | { | |
1114 | if (dp) | |
4373f3ce | 1115 | tcg_gen_st_f64(cpu_F0d, cpu_env, vfp_reg_offset(dp, reg)); |
b7bcbe95 | 1116 | else |
4373f3ce | 1117 | tcg_gen_st_f32(cpu_F0s, cpu_env, vfp_reg_offset(dp, reg)); |
b7bcbe95 FB |
1118 | } |
1119 | ||
18c9b560 AZ |
1120 | #define ARM_CP_RW_BIT (1 << 20) |
1121 | ||
a7812ae4 | 1122 | static inline void iwmmxt_load_reg(TCGv_i64 var, int reg) |
e677137d PB |
1123 | { |
1124 | tcg_gen_ld_i64(var, cpu_env, offsetof(CPUState, iwmmxt.regs[reg])); | |
1125 | } | |
1126 | ||
a7812ae4 | 1127 | static inline void iwmmxt_store_reg(TCGv_i64 var, int reg) |
e677137d PB |
1128 | { |
1129 | tcg_gen_st_i64(var, cpu_env, offsetof(CPUState, iwmmxt.regs[reg])); | |
1130 | } | |
1131 | ||
da6b5335 | 1132 | static inline TCGv iwmmxt_load_creg(int reg) |
e677137d | 1133 | { |
7d1b0095 | 1134 | TCGv var = tcg_temp_new_i32(); |
da6b5335 FN |
1135 | tcg_gen_ld_i32(var, cpu_env, offsetof(CPUState, iwmmxt.cregs[reg])); |
1136 | return var; | |
e677137d PB |
1137 | } |
1138 | ||
da6b5335 | 1139 | static inline void iwmmxt_store_creg(int reg, TCGv var) |
e677137d | 1140 | { |
da6b5335 | 1141 | tcg_gen_st_i32(var, cpu_env, offsetof(CPUState, iwmmxt.cregs[reg])); |
7d1b0095 | 1142 | tcg_temp_free_i32(var); |
e677137d PB |
1143 | } |
1144 | ||
1145 | static inline void gen_op_iwmmxt_movq_wRn_M0(int rn) | |
1146 | { | |
1147 | iwmmxt_store_reg(cpu_M0, rn); | |
1148 | } | |
1149 | ||
1150 | static inline void gen_op_iwmmxt_movq_M0_wRn(int rn) | |
1151 | { | |
1152 | iwmmxt_load_reg(cpu_M0, rn); | |
1153 | } | |
1154 | ||
1155 | static inline void gen_op_iwmmxt_orq_M0_wRn(int rn) | |
1156 | { | |
1157 | iwmmxt_load_reg(cpu_V1, rn); | |
1158 | tcg_gen_or_i64(cpu_M0, cpu_M0, cpu_V1); | |
1159 | } | |
1160 | ||
1161 | static inline void gen_op_iwmmxt_andq_M0_wRn(int rn) | |
1162 | { | |
1163 | iwmmxt_load_reg(cpu_V1, rn); | |
1164 | tcg_gen_and_i64(cpu_M0, cpu_M0, cpu_V1); | |
1165 | } | |
1166 | ||
1167 | static inline void gen_op_iwmmxt_xorq_M0_wRn(int rn) | |
1168 | { | |
1169 | iwmmxt_load_reg(cpu_V1, rn); | |
1170 | tcg_gen_xor_i64(cpu_M0, cpu_M0, cpu_V1); | |
1171 | } | |
1172 | ||
1173 | #define IWMMXT_OP(name) \ | |
1174 | static inline void gen_op_iwmmxt_##name##_M0_wRn(int rn) \ | |
1175 | { \ | |
1176 | iwmmxt_load_reg(cpu_V1, rn); \ | |
1177 | gen_helper_iwmmxt_##name(cpu_M0, cpu_M0, cpu_V1); \ | |
1178 | } | |
1179 | ||
947a2fa2 PM |
1180 | #define IWMMXT_OP_SIZE(name) \ |
1181 | IWMMXT_OP(name##b) \ | |
1182 | IWMMXT_OP(name##w) \ | |
1183 | IWMMXT_OP(name##l) | |
e677137d | 1184 | |
947a2fa2 | 1185 | #define IWMMXT_OP_1(name) \ |
e677137d PB |
1186 | static inline void gen_op_iwmmxt_##name##_M0(void) \ |
1187 | { \ | |
947a2fa2 | 1188 | gen_helper_iwmmxt_##name(cpu_M0, cpu_M0); \ |
e677137d PB |
1189 | } |
1190 | ||
1191 | IWMMXT_OP(maddsq) | |
1192 | IWMMXT_OP(madduq) | |
1193 | IWMMXT_OP(sadb) | |
1194 | IWMMXT_OP(sadw) | |
1195 | IWMMXT_OP(mulslw) | |
1196 | IWMMXT_OP(mulshw) | |
1197 | IWMMXT_OP(mululw) | |
1198 | IWMMXT_OP(muluhw) | |
1199 | IWMMXT_OP(macsw) | |
1200 | IWMMXT_OP(macuw) | |
1201 | ||
947a2fa2 PM |
1202 | IWMMXT_OP_SIZE(unpackl) |
1203 | IWMMXT_OP_SIZE(unpackh) | |
1204 | ||
1205 | IWMMXT_OP_1(unpacklub) | |
1206 | IWMMXT_OP_1(unpackluw) | |
1207 | IWMMXT_OP_1(unpacklul) | |
1208 | IWMMXT_OP_1(unpackhub) | |
1209 | IWMMXT_OP_1(unpackhuw) | |
1210 | IWMMXT_OP_1(unpackhul) | |
1211 | IWMMXT_OP_1(unpacklsb) | |
1212 | IWMMXT_OP_1(unpacklsw) | |
1213 | IWMMXT_OP_1(unpacklsl) | |
1214 | IWMMXT_OP_1(unpackhsb) | |
1215 | IWMMXT_OP_1(unpackhsw) | |
1216 | IWMMXT_OP_1(unpackhsl) | |
1217 | ||
1218 | IWMMXT_OP_SIZE(cmpeq) | |
1219 | IWMMXT_OP_SIZE(cmpgtu) | |
1220 | IWMMXT_OP_SIZE(cmpgts) | |
1221 | ||
1222 | IWMMXT_OP_SIZE(mins) | |
1223 | IWMMXT_OP_SIZE(minu) | |
1224 | IWMMXT_OP_SIZE(maxs) | |
1225 | IWMMXT_OP_SIZE(maxu) | |
1226 | ||
1227 | IWMMXT_OP_SIZE(subn) | |
1228 | IWMMXT_OP_SIZE(addn) | |
1229 | IWMMXT_OP_SIZE(subu) | |
1230 | IWMMXT_OP_SIZE(addu) | |
1231 | IWMMXT_OP_SIZE(subs) | |
1232 | IWMMXT_OP_SIZE(adds) | |
1233 | ||
1234 | IWMMXT_OP(avgb0) | |
1235 | IWMMXT_OP(avgb1) | |
1236 | IWMMXT_OP(avgw0) | |
1237 | IWMMXT_OP(avgw1) | |
e677137d PB |
1238 | |
1239 | IWMMXT_OP(msadb) | |
1240 | ||
947a2fa2 PM |
1241 | IWMMXT_OP(packuw) |
1242 | IWMMXT_OP(packul) | |
1243 | IWMMXT_OP(packuq) | |
1244 | IWMMXT_OP(packsw) | |
1245 | IWMMXT_OP(packsl) | |
1246 | IWMMXT_OP(packsq) | |
e677137d | 1247 | |
e677137d PB |
1248 | static void gen_op_iwmmxt_set_mup(void) |
1249 | { | |
1250 | TCGv tmp; | |
1251 | tmp = load_cpu_field(iwmmxt.cregs[ARM_IWMMXT_wCon]); | |
1252 | tcg_gen_ori_i32(tmp, tmp, 2); | |
1253 | store_cpu_field(tmp, iwmmxt.cregs[ARM_IWMMXT_wCon]); | |
1254 | } | |
1255 | ||
1256 | static void gen_op_iwmmxt_set_cup(void) | |
1257 | { | |
1258 | TCGv tmp; | |
1259 | tmp = load_cpu_field(iwmmxt.cregs[ARM_IWMMXT_wCon]); | |
1260 | tcg_gen_ori_i32(tmp, tmp, 1); | |
1261 | store_cpu_field(tmp, iwmmxt.cregs[ARM_IWMMXT_wCon]); | |
1262 | } | |
1263 | ||
1264 | static void gen_op_iwmmxt_setpsr_nz(void) | |
1265 | { | |
7d1b0095 | 1266 | TCGv tmp = tcg_temp_new_i32(); |
e677137d PB |
1267 | gen_helper_iwmmxt_setpsr_nz(tmp, cpu_M0); |
1268 | store_cpu_field(tmp, iwmmxt.cregs[ARM_IWMMXT_wCASF]); | |
1269 | } | |
1270 | ||
1271 | static inline void gen_op_iwmmxt_addl_M0_wRn(int rn) | |
1272 | { | |
1273 | iwmmxt_load_reg(cpu_V1, rn); | |
86831435 | 1274 | tcg_gen_ext32u_i64(cpu_V1, cpu_V1); |
e677137d PB |
1275 | tcg_gen_add_i64(cpu_M0, cpu_M0, cpu_V1); |
1276 | } | |
1277 | ||
da6b5335 | 1278 | static inline int gen_iwmmxt_address(DisasContext *s, uint32_t insn, TCGv dest) |
18c9b560 AZ |
1279 | { |
1280 | int rd; | |
1281 | uint32_t offset; | |
da6b5335 | 1282 | TCGv tmp; |
18c9b560 AZ |
1283 | |
1284 | rd = (insn >> 16) & 0xf; | |
da6b5335 | 1285 | tmp = load_reg(s, rd); |
18c9b560 AZ |
1286 | |
1287 | offset = (insn & 0xff) << ((insn >> 7) & 2); | |
1288 | if (insn & (1 << 24)) { | |
1289 | /* Pre indexed */ | |
1290 | if (insn & (1 << 23)) | |
da6b5335 | 1291 | tcg_gen_addi_i32(tmp, tmp, offset); |
18c9b560 | 1292 | else |
da6b5335 FN |
1293 | tcg_gen_addi_i32(tmp, tmp, -offset); |
1294 | tcg_gen_mov_i32(dest, tmp); | |
18c9b560 | 1295 | if (insn & (1 << 21)) |
da6b5335 FN |
1296 | store_reg(s, rd, tmp); |
1297 | else | |
7d1b0095 | 1298 | tcg_temp_free_i32(tmp); |
18c9b560 AZ |
1299 | } else if (insn & (1 << 21)) { |
1300 | /* Post indexed */ | |
da6b5335 | 1301 | tcg_gen_mov_i32(dest, tmp); |
18c9b560 | 1302 | if (insn & (1 << 23)) |
da6b5335 | 1303 | tcg_gen_addi_i32(tmp, tmp, offset); |
18c9b560 | 1304 | else |
da6b5335 FN |
1305 | tcg_gen_addi_i32(tmp, tmp, -offset); |
1306 | store_reg(s, rd, tmp); | |
18c9b560 AZ |
1307 | } else if (!(insn & (1 << 23))) |
1308 | return 1; | |
1309 | return 0; | |
1310 | } | |
1311 | ||
da6b5335 | 1312 | static inline int gen_iwmmxt_shift(uint32_t insn, uint32_t mask, TCGv dest) |
18c9b560 AZ |
1313 | { |
1314 | int rd = (insn >> 0) & 0xf; | |
da6b5335 | 1315 | TCGv tmp; |
18c9b560 | 1316 | |
da6b5335 FN |
1317 | if (insn & (1 << 8)) { |
1318 | if (rd < ARM_IWMMXT_wCGR0 || rd > ARM_IWMMXT_wCGR3) { | |
18c9b560 | 1319 | return 1; |
da6b5335 FN |
1320 | } else { |
1321 | tmp = iwmmxt_load_creg(rd); | |
1322 | } | |
1323 | } else { | |
7d1b0095 | 1324 | tmp = tcg_temp_new_i32(); |
da6b5335 FN |
1325 | iwmmxt_load_reg(cpu_V0, rd); |
1326 | tcg_gen_trunc_i64_i32(tmp, cpu_V0); | |
1327 | } | |
1328 | tcg_gen_andi_i32(tmp, tmp, mask); | |
1329 | tcg_gen_mov_i32(dest, tmp); | |
7d1b0095 | 1330 | tcg_temp_free_i32(tmp); |
18c9b560 AZ |
1331 | return 0; |
1332 | } | |
1333 | ||
1334 | /* Disassemble an iwMMXt instruction. Returns nonzero if an error occured | |
1335 | (ie. an undefined instruction). */ | |
1336 | static int disas_iwmmxt_insn(CPUState *env, DisasContext *s, uint32_t insn) | |
1337 | { | |
1338 | int rd, wrd; | |
1339 | int rdhi, rdlo, rd0, rd1, i; | |
da6b5335 FN |
1340 | TCGv addr; |
1341 | TCGv tmp, tmp2, tmp3; | |
18c9b560 AZ |
1342 | |
1343 | if ((insn & 0x0e000e00) == 0x0c000000) { | |
1344 | if ((insn & 0x0fe00ff0) == 0x0c400000) { | |
1345 | wrd = insn & 0xf; | |
1346 | rdlo = (insn >> 12) & 0xf; | |
1347 | rdhi = (insn >> 16) & 0xf; | |
1348 | if (insn & ARM_CP_RW_BIT) { /* TMRRC */ | |
da6b5335 FN |
1349 | iwmmxt_load_reg(cpu_V0, wrd); |
1350 | tcg_gen_trunc_i64_i32(cpu_R[rdlo], cpu_V0); | |
1351 | tcg_gen_shri_i64(cpu_V0, cpu_V0, 32); | |
1352 | tcg_gen_trunc_i64_i32(cpu_R[rdhi], cpu_V0); | |
18c9b560 | 1353 | } else { /* TMCRR */ |
da6b5335 FN |
1354 | tcg_gen_concat_i32_i64(cpu_V0, cpu_R[rdlo], cpu_R[rdhi]); |
1355 | iwmmxt_store_reg(cpu_V0, wrd); | |
18c9b560 AZ |
1356 | gen_op_iwmmxt_set_mup(); |
1357 | } | |
1358 | return 0; | |
1359 | } | |
1360 | ||
1361 | wrd = (insn >> 12) & 0xf; | |
7d1b0095 | 1362 | addr = tcg_temp_new_i32(); |
da6b5335 | 1363 | if (gen_iwmmxt_address(s, insn, addr)) { |
7d1b0095 | 1364 | tcg_temp_free_i32(addr); |
18c9b560 | 1365 | return 1; |
da6b5335 | 1366 | } |
18c9b560 AZ |
1367 | if (insn & ARM_CP_RW_BIT) { |
1368 | if ((insn >> 28) == 0xf) { /* WLDRW wCx */ | |
7d1b0095 | 1369 | tmp = tcg_temp_new_i32(); |
da6b5335 FN |
1370 | tcg_gen_qemu_ld32u(tmp, addr, IS_USER(s)); |
1371 | iwmmxt_store_creg(wrd, tmp); | |
18c9b560 | 1372 | } else { |
e677137d PB |
1373 | i = 1; |
1374 | if (insn & (1 << 8)) { | |
1375 | if (insn & (1 << 22)) { /* WLDRD */ | |
da6b5335 | 1376 | tcg_gen_qemu_ld64(cpu_M0, addr, IS_USER(s)); |
e677137d PB |
1377 | i = 0; |
1378 | } else { /* WLDRW wRd */ | |
da6b5335 | 1379 | tmp = gen_ld32(addr, IS_USER(s)); |
e677137d PB |
1380 | } |
1381 | } else { | |
1382 | if (insn & (1 << 22)) { /* WLDRH */ | |
da6b5335 | 1383 | tmp = gen_ld16u(addr, IS_USER(s)); |
e677137d | 1384 | } else { /* WLDRB */ |
da6b5335 | 1385 | tmp = gen_ld8u(addr, IS_USER(s)); |
e677137d PB |
1386 | } |
1387 | } | |
1388 | if (i) { | |
1389 | tcg_gen_extu_i32_i64(cpu_M0, tmp); | |
7d1b0095 | 1390 | tcg_temp_free_i32(tmp); |
e677137d | 1391 | } |
18c9b560 AZ |
1392 | gen_op_iwmmxt_movq_wRn_M0(wrd); |
1393 | } | |
1394 | } else { | |
1395 | if ((insn >> 28) == 0xf) { /* WSTRW wCx */ | |
da6b5335 FN |
1396 | tmp = iwmmxt_load_creg(wrd); |
1397 | gen_st32(tmp, addr, IS_USER(s)); | |
18c9b560 AZ |
1398 | } else { |
1399 | gen_op_iwmmxt_movq_M0_wRn(wrd); | |
7d1b0095 | 1400 | tmp = tcg_temp_new_i32(); |
e677137d PB |
1401 | if (insn & (1 << 8)) { |
1402 | if (insn & (1 << 22)) { /* WSTRD */ | |
7d1b0095 | 1403 | tcg_temp_free_i32(tmp); |
da6b5335 | 1404 | tcg_gen_qemu_st64(cpu_M0, addr, IS_USER(s)); |
e677137d PB |
1405 | } else { /* WSTRW wRd */ |
1406 | tcg_gen_trunc_i64_i32(tmp, cpu_M0); | |
da6b5335 | 1407 | gen_st32(tmp, addr, IS_USER(s)); |
e677137d PB |
1408 | } |
1409 | } else { | |
1410 | if (insn & (1 << 22)) { /* WSTRH */ | |
1411 | tcg_gen_trunc_i64_i32(tmp, cpu_M0); | |
da6b5335 | 1412 | gen_st16(tmp, addr, IS_USER(s)); |
e677137d PB |
1413 | } else { /* WSTRB */ |
1414 | tcg_gen_trunc_i64_i32(tmp, cpu_M0); | |
da6b5335 | 1415 | gen_st8(tmp, addr, IS_USER(s)); |
e677137d PB |
1416 | } |
1417 | } | |
18c9b560 AZ |
1418 | } |
1419 | } | |
7d1b0095 | 1420 | tcg_temp_free_i32(addr); |
18c9b560 AZ |
1421 | return 0; |
1422 | } | |
1423 | ||
1424 | if ((insn & 0x0f000000) != 0x0e000000) | |
1425 | return 1; | |
1426 | ||
1427 | switch (((insn >> 12) & 0xf00) | ((insn >> 4) & 0xff)) { | |
1428 | case 0x000: /* WOR */ | |
1429 | wrd = (insn >> 12) & 0xf; | |
1430 | rd0 = (insn >> 0) & 0xf; | |
1431 | rd1 = (insn >> 16) & 0xf; | |
1432 | gen_op_iwmmxt_movq_M0_wRn(rd0); | |
1433 | gen_op_iwmmxt_orq_M0_wRn(rd1); | |
1434 | gen_op_iwmmxt_setpsr_nz(); | |
1435 | gen_op_iwmmxt_movq_wRn_M0(wrd); | |
1436 | gen_op_iwmmxt_set_mup(); | |
1437 | gen_op_iwmmxt_set_cup(); | |
1438 | break; | |
1439 | case 0x011: /* TMCR */ | |
1440 | if (insn & 0xf) | |
1441 | return 1; | |
1442 | rd = (insn >> 12) & 0xf; | |
1443 | wrd = (insn >> 16) & 0xf; | |
1444 | switch (wrd) { | |
1445 | case ARM_IWMMXT_wCID: | |
1446 | case ARM_IWMMXT_wCASF: | |
1447 | break; | |
1448 | case ARM_IWMMXT_wCon: | |
1449 | gen_op_iwmmxt_set_cup(); | |
1450 | /* Fall through. */ | |
1451 | case ARM_IWMMXT_wCSSF: | |
da6b5335 FN |
1452 | tmp = iwmmxt_load_creg(wrd); |
1453 | tmp2 = load_reg(s, rd); | |
f669df27 | 1454 | tcg_gen_andc_i32(tmp, tmp, tmp2); |
7d1b0095 | 1455 | tcg_temp_free_i32(tmp2); |
da6b5335 | 1456 | iwmmxt_store_creg(wrd, tmp); |
18c9b560 AZ |
1457 | break; |
1458 | case ARM_IWMMXT_wCGR0: | |
1459 | case ARM_IWMMXT_wCGR1: | |
1460 | case ARM_IWMMXT_wCGR2: | |
1461 | case ARM_IWMMXT_wCGR3: | |
1462 | gen_op_iwmmxt_set_cup(); | |
da6b5335 FN |
1463 | tmp = load_reg(s, rd); |
1464 | iwmmxt_store_creg(wrd, tmp); | |
18c9b560 AZ |
1465 | break; |
1466 | default: | |
1467 | return 1; | |
1468 | } | |
1469 | break; | |
1470 | case 0x100: /* WXOR */ | |
1471 | wrd = (insn >> 12) & 0xf; | |
1472 | rd0 = (insn >> 0) & 0xf; | |
1473 | rd1 = (insn >> 16) & 0xf; | |
1474 | gen_op_iwmmxt_movq_M0_wRn(rd0); | |
1475 | gen_op_iwmmxt_xorq_M0_wRn(rd1); | |
1476 | gen_op_iwmmxt_setpsr_nz(); | |
1477 | gen_op_iwmmxt_movq_wRn_M0(wrd); | |
1478 | gen_op_iwmmxt_set_mup(); | |
1479 | gen_op_iwmmxt_set_cup(); | |
1480 | break; | |
1481 | case 0x111: /* TMRC */ | |
1482 | if (insn & 0xf) | |
1483 | return 1; | |
1484 | rd = (insn >> 12) & 0xf; | |
1485 | wrd = (insn >> 16) & 0xf; | |
da6b5335 FN |
1486 | tmp = iwmmxt_load_creg(wrd); |
1487 | store_reg(s, rd, tmp); | |
18c9b560 AZ |
1488 | break; |
1489 | case 0x300: /* WANDN */ | |
1490 | wrd = (insn >> 12) & 0xf; | |
1491 | rd0 = (insn >> 0) & 0xf; | |
1492 | rd1 = (insn >> 16) & 0xf; | |
1493 | gen_op_iwmmxt_movq_M0_wRn(rd0); | |
e677137d | 1494 | tcg_gen_neg_i64(cpu_M0, cpu_M0); |
18c9b560 AZ |
1495 | gen_op_iwmmxt_andq_M0_wRn(rd1); |
1496 | gen_op_iwmmxt_setpsr_nz(); | |
1497 | gen_op_iwmmxt_movq_wRn_M0(wrd); | |
1498 | gen_op_iwmmxt_set_mup(); | |
1499 | gen_op_iwmmxt_set_cup(); | |
1500 | break; | |
1501 | case 0x200: /* WAND */ | |
1502 | wrd = (insn >> 12) & 0xf; | |
1503 | rd0 = (insn >> 0) & 0xf; | |
1504 | rd1 = (insn >> 16) & 0xf; | |
1505 | gen_op_iwmmxt_movq_M0_wRn(rd0); | |
1506 | gen_op_iwmmxt_andq_M0_wRn(rd1); | |
1507 | gen_op_iwmmxt_setpsr_nz(); | |
1508 | gen_op_iwmmxt_movq_wRn_M0(wrd); | |
1509 | gen_op_iwmmxt_set_mup(); | |
1510 | gen_op_iwmmxt_set_cup(); | |
1511 | break; | |
1512 | case 0x810: case 0xa10: /* WMADD */ | |
1513 | wrd = (insn >> 12) & 0xf; | |
1514 | rd0 = (insn >> 0) & 0xf; | |
1515 | rd1 = (insn >> 16) & 0xf; | |
1516 | gen_op_iwmmxt_movq_M0_wRn(rd0); | |
1517 | if (insn & (1 << 21)) | |
1518 | gen_op_iwmmxt_maddsq_M0_wRn(rd1); | |
1519 | else | |
1520 | gen_op_iwmmxt_madduq_M0_wRn(rd1); | |
1521 | gen_op_iwmmxt_movq_wRn_M0(wrd); | |
1522 | gen_op_iwmmxt_set_mup(); | |
1523 | break; | |
1524 | case 0x10e: case 0x50e: case 0x90e: case 0xd0e: /* WUNPCKIL */ | |
1525 | wrd = (insn >> 12) & 0xf; | |
1526 | rd0 = (insn >> 16) & 0xf; | |
1527 | rd1 = (insn >> 0) & 0xf; | |
1528 | gen_op_iwmmxt_movq_M0_wRn(rd0); | |
1529 | switch ((insn >> 22) & 3) { | |
1530 | case 0: | |
1531 | gen_op_iwmmxt_unpacklb_M0_wRn(rd1); | |
1532 | break; | |
1533 | case 1: | |
1534 | gen_op_iwmmxt_unpacklw_M0_wRn(rd1); | |
1535 | break; | |
1536 | case 2: | |
1537 | gen_op_iwmmxt_unpackll_M0_wRn(rd1); | |
1538 | break; | |
1539 | case 3: | |
1540 | return 1; | |
1541 | } | |
1542 | gen_op_iwmmxt_movq_wRn_M0(wrd); | |
1543 | gen_op_iwmmxt_set_mup(); | |
1544 | gen_op_iwmmxt_set_cup(); | |
1545 | break; | |
1546 | case 0x10c: case 0x50c: case 0x90c: case 0xd0c: /* WUNPCKIH */ | |
1547 | wrd = (insn >> 12) & 0xf; | |
1548 | rd0 = (insn >> 16) & 0xf; | |
1549 | rd1 = (insn >> 0) & 0xf; | |
1550 | gen_op_iwmmxt_movq_M0_wRn(rd0); | |
1551 | switch ((insn >> 22) & 3) { | |
1552 | case 0: | |
1553 | gen_op_iwmmxt_unpackhb_M0_wRn(rd1); | |
1554 | break; | |
1555 | case 1: | |
1556 | gen_op_iwmmxt_unpackhw_M0_wRn(rd1); | |
1557 | break; | |
1558 | case 2: | |
1559 | gen_op_iwmmxt_unpackhl_M0_wRn(rd1); | |
1560 | break; | |
1561 | case 3: | |
1562 | return 1; | |
1563 | } | |
1564 | gen_op_iwmmxt_movq_wRn_M0(wrd); | |
1565 | gen_op_iwmmxt_set_mup(); | |
1566 | gen_op_iwmmxt_set_cup(); | |
1567 | break; | |
1568 | case 0x012: case 0x112: case 0x412: case 0x512: /* WSAD */ | |
1569 | wrd = (insn >> 12) & 0xf; | |
1570 | rd0 = (insn >> 16) & 0xf; | |
1571 | rd1 = (insn >> 0) & 0xf; | |
1572 | gen_op_iwmmxt_movq_M0_wRn(rd0); | |
1573 | if (insn & (1 << 22)) | |
1574 | gen_op_iwmmxt_sadw_M0_wRn(rd1); | |
1575 | else | |
1576 | gen_op_iwmmxt_sadb_M0_wRn(rd1); | |
1577 | if (!(insn & (1 << 20))) | |
1578 | gen_op_iwmmxt_addl_M0_wRn(wrd); | |
1579 | gen_op_iwmmxt_movq_wRn_M0(wrd); | |
1580 | gen_op_iwmmxt_set_mup(); | |
1581 | break; | |
1582 | case 0x010: case 0x110: case 0x210: case 0x310: /* WMUL */ | |
1583 | wrd = (insn >> 12) & 0xf; | |
1584 | rd0 = (insn >> 16) & 0xf; | |
1585 | rd1 = (insn >> 0) & 0xf; | |
1586 | gen_op_iwmmxt_movq_M0_wRn(rd0); | |
e677137d PB |
1587 | if (insn & (1 << 21)) { |
1588 | if (insn & (1 << 20)) | |
1589 | gen_op_iwmmxt_mulshw_M0_wRn(rd1); | |
1590 | else | |
1591 | gen_op_iwmmxt_mulslw_M0_wRn(rd1); | |
1592 | } else { | |
1593 | if (insn & (1 << 20)) | |
1594 | gen_op_iwmmxt_muluhw_M0_wRn(rd1); | |
1595 | else | |
1596 | gen_op_iwmmxt_mululw_M0_wRn(rd1); | |
1597 | } | |
18c9b560 AZ |
1598 | gen_op_iwmmxt_movq_wRn_M0(wrd); |
1599 | gen_op_iwmmxt_set_mup(); | |
1600 | break; | |
1601 | case 0x410: case 0x510: case 0x610: case 0x710: /* WMAC */ | |
1602 | wrd = (insn >> 12) & 0xf; | |
1603 | rd0 = (insn >> 16) & 0xf; | |
1604 | rd1 = (insn >> 0) & 0xf; | |
1605 | gen_op_iwmmxt_movq_M0_wRn(rd0); | |
1606 | if (insn & (1 << 21)) | |
1607 | gen_op_iwmmxt_macsw_M0_wRn(rd1); | |
1608 | else | |
1609 | gen_op_iwmmxt_macuw_M0_wRn(rd1); | |
1610 | if (!(insn & (1 << 20))) { | |
e677137d PB |
1611 | iwmmxt_load_reg(cpu_V1, wrd); |
1612 | tcg_gen_add_i64(cpu_M0, cpu_M0, cpu_V1); | |
18c9b560 AZ |
1613 | } |
1614 | gen_op_iwmmxt_movq_wRn_M0(wrd); | |
1615 | gen_op_iwmmxt_set_mup(); | |
1616 | break; | |
1617 | case 0x006: case 0x406: case 0x806: case 0xc06: /* WCMPEQ */ | |
1618 | wrd = (insn >> 12) & 0xf; | |
1619 | rd0 = (insn >> 16) & 0xf; | |
1620 | rd1 = (insn >> 0) & 0xf; | |
1621 | gen_op_iwmmxt_movq_M0_wRn(rd0); | |
1622 | switch ((insn >> 22) & 3) { | |
1623 | case 0: | |
1624 | gen_op_iwmmxt_cmpeqb_M0_wRn(rd1); | |
1625 | break; | |
1626 | case 1: | |
1627 | gen_op_iwmmxt_cmpeqw_M0_wRn(rd1); | |
1628 | break; | |
1629 | case 2: | |
1630 | gen_op_iwmmxt_cmpeql_M0_wRn(rd1); | |
1631 | break; | |
1632 | case 3: | |
1633 | return 1; | |
1634 | } | |
1635 | gen_op_iwmmxt_movq_wRn_M0(wrd); | |
1636 | gen_op_iwmmxt_set_mup(); | |
1637 | gen_op_iwmmxt_set_cup(); | |
1638 | break; | |
1639 | case 0x800: case 0x900: case 0xc00: case 0xd00: /* WAVG2 */ | |
1640 | wrd = (insn >> 12) & 0xf; | |
1641 | rd0 = (insn >> 16) & 0xf; | |
1642 | rd1 = (insn >> 0) & 0xf; | |
1643 | gen_op_iwmmxt_movq_M0_wRn(rd0); | |
e677137d PB |
1644 | if (insn & (1 << 22)) { |
1645 | if (insn & (1 << 20)) | |
1646 | gen_op_iwmmxt_avgw1_M0_wRn(rd1); | |
1647 | else | |
1648 | gen_op_iwmmxt_avgw0_M0_wRn(rd1); | |
1649 | } else { | |
1650 | if (insn & (1 << 20)) | |
1651 | gen_op_iwmmxt_avgb1_M0_wRn(rd1); | |
1652 | else | |
1653 | gen_op_iwmmxt_avgb0_M0_wRn(rd1); | |
1654 | } | |
18c9b560 AZ |
1655 | gen_op_iwmmxt_movq_wRn_M0(wrd); |
1656 | gen_op_iwmmxt_set_mup(); | |
1657 | gen_op_iwmmxt_set_cup(); | |
1658 | break; | |
1659 | case 0x802: case 0x902: case 0xa02: case 0xb02: /* WALIGNR */ | |
1660 | wrd = (insn >> 12) & 0xf; | |
1661 | rd0 = (insn >> 16) & 0xf; | |
1662 | rd1 = (insn >> 0) & 0xf; | |
1663 | gen_op_iwmmxt_movq_M0_wRn(rd0); | |
da6b5335 FN |
1664 | tmp = iwmmxt_load_creg(ARM_IWMMXT_wCGR0 + ((insn >> 20) & 3)); |
1665 | tcg_gen_andi_i32(tmp, tmp, 7); | |
1666 | iwmmxt_load_reg(cpu_V1, rd1); | |
1667 | gen_helper_iwmmxt_align(cpu_M0, cpu_M0, cpu_V1, tmp); | |
7d1b0095 | 1668 | tcg_temp_free_i32(tmp); |
18c9b560 AZ |
1669 | gen_op_iwmmxt_movq_wRn_M0(wrd); |
1670 | gen_op_iwmmxt_set_mup(); | |
1671 | break; | |
1672 | case 0x601: case 0x605: case 0x609: case 0x60d: /* TINSR */ | |
da6b5335 FN |
1673 | if (((insn >> 6) & 3) == 3) |
1674 | return 1; | |
18c9b560 AZ |
1675 | rd = (insn >> 12) & 0xf; |
1676 | wrd = (insn >> 16) & 0xf; | |
da6b5335 | 1677 | tmp = load_reg(s, rd); |
18c9b560 AZ |
1678 | gen_op_iwmmxt_movq_M0_wRn(wrd); |
1679 | switch ((insn >> 6) & 3) { | |
1680 | case 0: | |
da6b5335 FN |
1681 | tmp2 = tcg_const_i32(0xff); |
1682 | tmp3 = tcg_const_i32((insn & 7) << 3); | |
18c9b560 AZ |
1683 | break; |
1684 | case 1: | |
da6b5335 FN |
1685 | tmp2 = tcg_const_i32(0xffff); |
1686 | tmp3 = tcg_const_i32((insn & 3) << 4); | |
18c9b560 AZ |
1687 | break; |
1688 | case 2: | |
da6b5335 FN |
1689 | tmp2 = tcg_const_i32(0xffffffff); |
1690 | tmp3 = tcg_const_i32((insn & 1) << 5); | |
18c9b560 | 1691 | break; |
da6b5335 FN |
1692 | default: |
1693 | TCGV_UNUSED(tmp2); | |
1694 | TCGV_UNUSED(tmp3); | |
18c9b560 | 1695 | } |
da6b5335 FN |
1696 | gen_helper_iwmmxt_insr(cpu_M0, cpu_M0, tmp, tmp2, tmp3); |
1697 | tcg_temp_free(tmp3); | |
1698 | tcg_temp_free(tmp2); | |
7d1b0095 | 1699 | tcg_temp_free_i32(tmp); |
18c9b560 AZ |
1700 | gen_op_iwmmxt_movq_wRn_M0(wrd); |
1701 | gen_op_iwmmxt_set_mup(); | |
1702 | break; | |
1703 | case 0x107: case 0x507: case 0x907: case 0xd07: /* TEXTRM */ | |
1704 | rd = (insn >> 12) & 0xf; | |
1705 | wrd = (insn >> 16) & 0xf; | |
da6b5335 | 1706 | if (rd == 15 || ((insn >> 22) & 3) == 3) |
18c9b560 AZ |
1707 | return 1; |
1708 | gen_op_iwmmxt_movq_M0_wRn(wrd); | |
7d1b0095 | 1709 | tmp = tcg_temp_new_i32(); |
18c9b560 AZ |
1710 | switch ((insn >> 22) & 3) { |
1711 | case 0: | |
da6b5335 FN |
1712 | tcg_gen_shri_i64(cpu_M0, cpu_M0, (insn & 7) << 3); |
1713 | tcg_gen_trunc_i64_i32(tmp, cpu_M0); | |
1714 | if (insn & 8) { | |
1715 | tcg_gen_ext8s_i32(tmp, tmp); | |
1716 | } else { | |
1717 | tcg_gen_andi_i32(tmp, tmp, 0xff); | |
18c9b560 AZ |
1718 | } |
1719 | break; | |
1720 | case 1: | |
da6b5335 FN |
1721 | tcg_gen_shri_i64(cpu_M0, cpu_M0, (insn & 3) << 4); |
1722 | tcg_gen_trunc_i64_i32(tmp, cpu_M0); | |
1723 | if (insn & 8) { | |
1724 | tcg_gen_ext16s_i32(tmp, tmp); | |
1725 | } else { | |
1726 | tcg_gen_andi_i32(tmp, tmp, 0xffff); | |
18c9b560 AZ |
1727 | } |
1728 | break; | |
1729 | case 2: | |
da6b5335 FN |
1730 | tcg_gen_shri_i64(cpu_M0, cpu_M0, (insn & 1) << 5); |
1731 | tcg_gen_trunc_i64_i32(tmp, cpu_M0); | |
18c9b560 | 1732 | break; |
18c9b560 | 1733 | } |
da6b5335 | 1734 | store_reg(s, rd, tmp); |
18c9b560 AZ |
1735 | break; |
1736 | case 0x117: case 0x517: case 0x917: case 0xd17: /* TEXTRC */ | |
da6b5335 | 1737 | if ((insn & 0x000ff008) != 0x0003f000 || ((insn >> 22) & 3) == 3) |
18c9b560 | 1738 | return 1; |
da6b5335 | 1739 | tmp = iwmmxt_load_creg(ARM_IWMMXT_wCASF); |
18c9b560 AZ |
1740 | switch ((insn >> 22) & 3) { |
1741 | case 0: | |
da6b5335 | 1742 | tcg_gen_shri_i32(tmp, tmp, ((insn & 7) << 2) + 0); |
18c9b560 AZ |
1743 | break; |
1744 | case 1: | |
da6b5335 | 1745 | tcg_gen_shri_i32(tmp, tmp, ((insn & 3) << 3) + 4); |
18c9b560 AZ |
1746 | break; |
1747 | case 2: | |
da6b5335 | 1748 | tcg_gen_shri_i32(tmp, tmp, ((insn & 1) << 4) + 12); |
18c9b560 | 1749 | break; |
18c9b560 | 1750 | } |
da6b5335 FN |
1751 | tcg_gen_shli_i32(tmp, tmp, 28); |
1752 | gen_set_nzcv(tmp); | |
7d1b0095 | 1753 | tcg_temp_free_i32(tmp); |
18c9b560 AZ |
1754 | break; |
1755 | case 0x401: case 0x405: case 0x409: case 0x40d: /* TBCST */ | |
da6b5335 FN |
1756 | if (((insn >> 6) & 3) == 3) |
1757 | return 1; | |
18c9b560 AZ |
1758 | rd = (insn >> 12) & 0xf; |
1759 | wrd = (insn >> 16) & 0xf; | |
da6b5335 | 1760 | tmp = load_reg(s, rd); |
18c9b560 AZ |
1761 | switch ((insn >> 6) & 3) { |
1762 | case 0: | |
da6b5335 | 1763 | gen_helper_iwmmxt_bcstb(cpu_M0, tmp); |
18c9b560 AZ |
1764 | break; |
1765 | case 1: | |
da6b5335 | 1766 | gen_helper_iwmmxt_bcstw(cpu_M0, tmp); |
18c9b560 AZ |
1767 | break; |
1768 | case 2: | |
da6b5335 | 1769 | gen_helper_iwmmxt_bcstl(cpu_M0, tmp); |
18c9b560 | 1770 | break; |
18c9b560 | 1771 | } |
7d1b0095 | 1772 | tcg_temp_free_i32(tmp); |
18c9b560 AZ |
1773 | gen_op_iwmmxt_movq_wRn_M0(wrd); |
1774 | gen_op_iwmmxt_set_mup(); | |
1775 | break; | |
1776 | case 0x113: case 0x513: case 0x913: case 0xd13: /* TANDC */ | |
da6b5335 | 1777 | if ((insn & 0x000ff00f) != 0x0003f000 || ((insn >> 22) & 3) == 3) |
18c9b560 | 1778 | return 1; |
da6b5335 | 1779 | tmp = iwmmxt_load_creg(ARM_IWMMXT_wCASF); |
7d1b0095 | 1780 | tmp2 = tcg_temp_new_i32(); |
da6b5335 | 1781 | tcg_gen_mov_i32(tmp2, tmp); |
18c9b560 AZ |
1782 | switch ((insn >> 22) & 3) { |
1783 | case 0: | |
1784 | for (i = 0; i < 7; i ++) { | |
da6b5335 FN |
1785 | tcg_gen_shli_i32(tmp2, tmp2, 4); |
1786 | tcg_gen_and_i32(tmp, tmp, tmp2); | |
18c9b560 AZ |
1787 | } |
1788 | break; | |
1789 | case 1: | |
1790 | for (i = 0; i < 3; i ++) { | |
da6b5335 FN |
1791 | tcg_gen_shli_i32(tmp2, tmp2, 8); |
1792 | tcg_gen_and_i32(tmp, tmp, tmp2); | |
18c9b560 AZ |
1793 | } |
1794 | break; | |
1795 | case 2: | |
da6b5335 FN |
1796 | tcg_gen_shli_i32(tmp2, tmp2, 16); |
1797 | tcg_gen_and_i32(tmp, tmp, tmp2); | |
18c9b560 | 1798 | break; |
18c9b560 | 1799 | } |
da6b5335 | 1800 | gen_set_nzcv(tmp); |
7d1b0095 PM |
1801 | tcg_temp_free_i32(tmp2); |
1802 | tcg_temp_free_i32(tmp); | |
18c9b560 AZ |
1803 | break; |
1804 | case 0x01c: case 0x41c: case 0x81c: case 0xc1c: /* WACC */ | |
1805 | wrd = (insn >> 12) & 0xf; | |
1806 | rd0 = (insn >> 16) & 0xf; | |
1807 | gen_op_iwmmxt_movq_M0_wRn(rd0); | |
1808 | switch ((insn >> 22) & 3) { | |
1809 | case 0: | |
e677137d | 1810 | gen_helper_iwmmxt_addcb(cpu_M0, cpu_M0); |
18c9b560 AZ |
1811 | break; |
1812 | case 1: | |
e677137d | 1813 | gen_helper_iwmmxt_addcw(cpu_M0, cpu_M0); |
18c9b560 AZ |
1814 | break; |
1815 | case 2: | |
e677137d | 1816 | gen_helper_iwmmxt_addcl(cpu_M0, cpu_M0); |
18c9b560 AZ |
1817 | break; |
1818 | case 3: | |
1819 | return 1; | |
1820 | } | |
1821 | gen_op_iwmmxt_movq_wRn_M0(wrd); | |
1822 | gen_op_iwmmxt_set_mup(); | |
1823 | break; | |
1824 | case 0x115: case 0x515: case 0x915: case 0xd15: /* TORC */ | |
da6b5335 | 1825 | if ((insn & 0x000ff00f) != 0x0003f000 || ((insn >> 22) & 3) == 3) |
18c9b560 | 1826 | return 1; |
da6b5335 | 1827 | tmp = iwmmxt_load_creg(ARM_IWMMXT_wCASF); |
7d1b0095 | 1828 | tmp2 = tcg_temp_new_i32(); |
da6b5335 | 1829 | tcg_gen_mov_i32(tmp2, tmp); |
18c9b560 AZ |
1830 | switch ((insn >> 22) & 3) { |
1831 | case 0: | |
1832 | for (i = 0; i < 7; i ++) { | |
da6b5335 FN |
1833 | tcg_gen_shli_i32(tmp2, tmp2, 4); |
1834 | tcg_gen_or_i32(tmp, tmp, tmp2); | |
18c9b560 AZ |
1835 | } |
1836 | break; | |
1837 | case 1: | |
1838 | for (i = 0; i < 3; i ++) { | |
da6b5335 FN |
1839 | tcg_gen_shli_i32(tmp2, tmp2, 8); |
1840 | tcg_gen_or_i32(tmp, tmp, tmp2); | |
18c9b560 AZ |
1841 | } |
1842 | break; | |
1843 | case 2: | |
da6b5335 FN |
1844 | tcg_gen_shli_i32(tmp2, tmp2, 16); |
1845 | tcg_gen_or_i32(tmp, tmp, tmp2); | |
18c9b560 | 1846 | break; |
18c9b560 | 1847 | } |
da6b5335 | 1848 | gen_set_nzcv(tmp); |
7d1b0095 PM |
1849 | tcg_temp_free_i32(tmp2); |
1850 | tcg_temp_free_i32(tmp); | |
18c9b560 AZ |
1851 | break; |
1852 | case 0x103: case 0x503: case 0x903: case 0xd03: /* TMOVMSK */ | |
1853 | rd = (insn >> 12) & 0xf; | |
1854 | rd0 = (insn >> 16) & 0xf; | |
da6b5335 | 1855 | if ((insn & 0xf) != 0 || ((insn >> 22) & 3) == 3) |
18c9b560 AZ |
1856 | return 1; |
1857 | gen_op_iwmmxt_movq_M0_wRn(rd0); | |
7d1b0095 | 1858 | tmp = tcg_temp_new_i32(); |
18c9b560 AZ |
1859 | switch ((insn >> 22) & 3) { |
1860 | case 0: | |
da6b5335 | 1861 | gen_helper_iwmmxt_msbb(tmp, cpu_M0); |
18c9b560 AZ |
1862 | break; |
1863 | case 1: | |
da6b5335 | 1864 | gen_helper_iwmmxt_msbw(tmp, cpu_M0); |
18c9b560 AZ |
1865 | break; |
1866 | case 2: | |
da6b5335 | 1867 | gen_helper_iwmmxt_msbl(tmp, cpu_M0); |
18c9b560 | 1868 | break; |
18c9b560 | 1869 | } |
da6b5335 | 1870 | store_reg(s, rd, tmp); |
18c9b560 AZ |
1871 | break; |
1872 | case 0x106: case 0x306: case 0x506: case 0x706: /* WCMPGT */ | |
1873 | case 0x906: case 0xb06: case 0xd06: case 0xf06: | |
1874 | wrd = (insn >> 12) & 0xf; | |
1875 | rd0 = (insn >> 16) & 0xf; | |
1876 | rd1 = (insn >> 0) & 0xf; | |
1877 | gen_op_iwmmxt_movq_M0_wRn(rd0); | |
1878 | switch ((insn >> 22) & 3) { | |
1879 | case 0: | |
1880 | if (insn & (1 << 21)) | |
1881 | gen_op_iwmmxt_cmpgtsb_M0_wRn(rd1); | |
1882 | else | |
1883 | gen_op_iwmmxt_cmpgtub_M0_wRn(rd1); | |
1884 | break; | |
1885 | case 1: | |
1886 | if (insn & (1 << 21)) | |
1887 | gen_op_iwmmxt_cmpgtsw_M0_wRn(rd1); | |
1888 | else | |
1889 | gen_op_iwmmxt_cmpgtuw_M0_wRn(rd1); | |
1890 | break; | |
1891 | case 2: | |
1892 | if (insn & (1 << 21)) | |
1893 | gen_op_iwmmxt_cmpgtsl_M0_wRn(rd1); | |
1894 | else | |
1895 | gen_op_iwmmxt_cmpgtul_M0_wRn(rd1); | |
1896 | break; | |
1897 | case 3: | |
1898 | return 1; | |
1899 | } | |
1900 | gen_op_iwmmxt_movq_wRn_M0(wrd); | |
1901 | gen_op_iwmmxt_set_mup(); | |
1902 | gen_op_iwmmxt_set_cup(); | |
1903 | break; | |
1904 | case 0x00e: case 0x20e: case 0x40e: case 0x60e: /* WUNPCKEL */ | |
1905 | case 0x80e: case 0xa0e: case 0xc0e: case 0xe0e: | |
1906 | wrd = (insn >> 12) & 0xf; | |
1907 | rd0 = (insn >> 16) & 0xf; | |
1908 | gen_op_iwmmxt_movq_M0_wRn(rd0); | |
1909 | switch ((insn >> 22) & 3) { | |
1910 | case 0: | |
1911 | if (insn & (1 << 21)) | |
1912 | gen_op_iwmmxt_unpacklsb_M0(); | |
1913 | else | |
1914 | gen_op_iwmmxt_unpacklub_M0(); | |
1915 | break; | |
1916 | case 1: | |
1917 | if (insn & (1 << 21)) | |
1918 | gen_op_iwmmxt_unpacklsw_M0(); | |
1919 | else | |
1920 | gen_op_iwmmxt_unpackluw_M0(); | |
1921 | break; | |
1922 | case 2: | |
1923 | if (insn & (1 << 21)) | |
1924 | gen_op_iwmmxt_unpacklsl_M0(); | |
1925 | else | |
1926 | gen_op_iwmmxt_unpacklul_M0(); | |
1927 | break; | |
1928 | case 3: | |
1929 | return 1; | |
1930 | } | |
1931 | gen_op_iwmmxt_movq_wRn_M0(wrd); | |
1932 | gen_op_iwmmxt_set_mup(); | |
1933 | gen_op_iwmmxt_set_cup(); | |
1934 | break; | |
1935 | case 0x00c: case 0x20c: case 0x40c: case 0x60c: /* WUNPCKEH */ | |
1936 | case 0x80c: case 0xa0c: case 0xc0c: case 0xe0c: | |
1937 | wrd = (insn >> 12) & 0xf; | |
1938 | rd0 = (insn >> 16) & 0xf; | |
1939 | gen_op_iwmmxt_movq_M0_wRn(rd0); | |
1940 | switch ((insn >> 22) & 3) { | |
1941 | case 0: | |
1942 | if (insn & (1 << 21)) | |
1943 | gen_op_iwmmxt_unpackhsb_M0(); | |
1944 | else | |
1945 | gen_op_iwmmxt_unpackhub_M0(); | |
1946 | break; | |
1947 | case 1: | |
1948 | if (insn & (1 << 21)) | |
1949 | gen_op_iwmmxt_unpackhsw_M0(); | |
1950 | else | |
1951 | gen_op_iwmmxt_unpackhuw_M0(); | |
1952 | break; | |
1953 | case 2: | |
1954 | if (insn & (1 << 21)) | |
1955 | gen_op_iwmmxt_unpackhsl_M0(); | |
1956 | else | |
1957 | gen_op_iwmmxt_unpackhul_M0(); | |
1958 | break; | |
1959 | case 3: | |
1960 | return 1; | |
1961 | } | |
1962 | gen_op_iwmmxt_movq_wRn_M0(wrd); | |
1963 | gen_op_iwmmxt_set_mup(); | |
1964 | gen_op_iwmmxt_set_cup(); | |
1965 | break; | |
1966 | case 0x204: case 0x604: case 0xa04: case 0xe04: /* WSRL */ | |
1967 | case 0x214: case 0x614: case 0xa14: case 0xe14: | |
da6b5335 FN |
1968 | if (((insn >> 22) & 3) == 0) |
1969 | return 1; | |
18c9b560 AZ |
1970 | wrd = (insn >> 12) & 0xf; |
1971 | rd0 = (insn >> 16) & 0xf; | |
1972 | gen_op_iwmmxt_movq_M0_wRn(rd0); | |
7d1b0095 | 1973 | tmp = tcg_temp_new_i32(); |
da6b5335 | 1974 | if (gen_iwmmxt_shift(insn, 0xff, tmp)) { |
7d1b0095 | 1975 | tcg_temp_free_i32(tmp); |
18c9b560 | 1976 | return 1; |
da6b5335 | 1977 | } |
18c9b560 | 1978 | switch ((insn >> 22) & 3) { |
18c9b560 | 1979 | case 1: |
947a2fa2 | 1980 | gen_helper_iwmmxt_srlw(cpu_M0, cpu_M0, tmp); |
18c9b560 AZ |
1981 | break; |
1982 | case 2: | |
947a2fa2 | 1983 | gen_helper_iwmmxt_srll(cpu_M0, cpu_M0, tmp); |
18c9b560 AZ |
1984 | break; |
1985 | case 3: | |
947a2fa2 | 1986 | gen_helper_iwmmxt_srlq(cpu_M0, cpu_M0, tmp); |
18c9b560 AZ |
1987 | break; |
1988 | } | |
7d1b0095 | 1989 | tcg_temp_free_i32(tmp); |
18c9b560 AZ |
1990 | gen_op_iwmmxt_movq_wRn_M0(wrd); |
1991 | gen_op_iwmmxt_set_mup(); | |
1992 | gen_op_iwmmxt_set_cup(); | |
1993 | break; | |
1994 | case 0x004: case 0x404: case 0x804: case 0xc04: /* WSRA */ | |
1995 | case 0x014: case 0x414: case 0x814: case 0xc14: | |
da6b5335 FN |
1996 | if (((insn >> 22) & 3) == 0) |
1997 | return 1; | |
18c9b560 AZ |
1998 | wrd = (insn >> 12) & 0xf; |
1999 | rd0 = (insn >> 16) & 0xf; | |
2000 | gen_op_iwmmxt_movq_M0_wRn(rd0); | |
7d1b0095 | 2001 | tmp = tcg_temp_new_i32(); |
da6b5335 | 2002 | if (gen_iwmmxt_shift(insn, 0xff, tmp)) { |
7d1b0095 | 2003 | tcg_temp_free_i32(tmp); |
18c9b560 | 2004 | return 1; |
da6b5335 | 2005 | } |
18c9b560 | 2006 | switch ((insn >> 22) & 3) { |
18c9b560 | 2007 | case 1: |
947a2fa2 | 2008 | gen_helper_iwmmxt_sraw(cpu_M0, cpu_M0, tmp); |
18c9b560 AZ |
2009 | break; |
2010 | case 2: | |
947a2fa2 | 2011 | gen_helper_iwmmxt_sral(cpu_M0, cpu_M0, tmp); |
18c9b560 AZ |
2012 | break; |
2013 | case 3: | |
947a2fa2 | 2014 | gen_helper_iwmmxt_sraq(cpu_M0, cpu_M0, tmp); |
18c9b560 AZ |
2015 | break; |
2016 | } | |
7d1b0095 | 2017 | tcg_temp_free_i32(tmp); |
18c9b560 AZ |
2018 | gen_op_iwmmxt_movq_wRn_M0(wrd); |
2019 | gen_op_iwmmxt_set_mup(); | |
2020 | gen_op_iwmmxt_set_cup(); | |
2021 | break; | |
2022 | case 0x104: case 0x504: case 0x904: case 0xd04: /* WSLL */ | |
2023 | case 0x114: case 0x514: case 0x914: case 0xd14: | |
da6b5335 FN |
2024 | if (((insn >> 22) & 3) == 0) |
2025 | return 1; | |
18c9b560 AZ |
2026 | wrd = (insn >> 12) & 0xf; |
2027 | rd0 = (insn >> 16) & 0xf; | |
2028 | gen_op_iwmmxt_movq_M0_wRn(rd0); | |
7d1b0095 | 2029 | tmp = tcg_temp_new_i32(); |
da6b5335 | 2030 | if (gen_iwmmxt_shift(insn, 0xff, tmp)) { |
7d1b0095 | 2031 | tcg_temp_free_i32(tmp); |
18c9b560 | 2032 | return 1; |
da6b5335 | 2033 | } |
18c9b560 | 2034 | switch ((insn >> 22) & 3) { |
18c9b560 | 2035 | case 1: |
947a2fa2 | 2036 | gen_helper_iwmmxt_sllw(cpu_M0, cpu_M0, tmp); |
18c9b560 AZ |
2037 | break; |
2038 | case 2: | |
947a2fa2 | 2039 | gen_helper_iwmmxt_slll(cpu_M0, cpu_M0, tmp); |
18c9b560 AZ |
2040 | break; |
2041 | case 3: | |
947a2fa2 | 2042 | gen_helper_iwmmxt_sllq(cpu_M0, cpu_M0, tmp); |
18c9b560 AZ |
2043 | break; |
2044 | } | |
7d1b0095 | 2045 | tcg_temp_free_i32(tmp); |
18c9b560 AZ |
2046 | gen_op_iwmmxt_movq_wRn_M0(wrd); |
2047 | gen_op_iwmmxt_set_mup(); | |
2048 | gen_op_iwmmxt_set_cup(); | |
2049 | break; | |
2050 | case 0x304: case 0x704: case 0xb04: case 0xf04: /* WROR */ | |
2051 | case 0x314: case 0x714: case 0xb14: case 0xf14: | |
da6b5335 FN |
2052 | if (((insn >> 22) & 3) == 0) |
2053 | return 1; | |
18c9b560 AZ |
2054 | wrd = (insn >> 12) & 0xf; |
2055 | rd0 = (insn >> 16) & 0xf; | |
2056 | gen_op_iwmmxt_movq_M0_wRn(rd0); | |
7d1b0095 | 2057 | tmp = tcg_temp_new_i32(); |
18c9b560 | 2058 | switch ((insn >> 22) & 3) { |
18c9b560 | 2059 | case 1: |
da6b5335 | 2060 | if (gen_iwmmxt_shift(insn, 0xf, tmp)) { |
7d1b0095 | 2061 | tcg_temp_free_i32(tmp); |
18c9b560 | 2062 | return 1; |
da6b5335 | 2063 | } |
947a2fa2 | 2064 | gen_helper_iwmmxt_rorw(cpu_M0, cpu_M0, tmp); |
18c9b560 AZ |
2065 | break; |
2066 | case 2: | |
da6b5335 | 2067 | if (gen_iwmmxt_shift(insn, 0x1f, tmp)) { |
7d1b0095 | 2068 | tcg_temp_free_i32(tmp); |
18c9b560 | 2069 | return 1; |
da6b5335 | 2070 | } |
947a2fa2 | 2071 | gen_helper_iwmmxt_rorl(cpu_M0, cpu_M0, tmp); |
18c9b560 AZ |
2072 | break; |
2073 | case 3: | |
da6b5335 | 2074 | if (gen_iwmmxt_shift(insn, 0x3f, tmp)) { |
7d1b0095 | 2075 | tcg_temp_free_i32(tmp); |
18c9b560 | 2076 | return 1; |
da6b5335 | 2077 | } |
947a2fa2 | 2078 | gen_helper_iwmmxt_rorq(cpu_M0, cpu_M0, tmp); |
18c9b560 AZ |
2079 | break; |
2080 | } | |
7d1b0095 | 2081 | tcg_temp_free_i32(tmp); |
18c9b560 AZ |
2082 | gen_op_iwmmxt_movq_wRn_M0(wrd); |
2083 | gen_op_iwmmxt_set_mup(); | |
2084 | gen_op_iwmmxt_set_cup(); | |
2085 | break; | |
2086 | case 0x116: case 0x316: case 0x516: case 0x716: /* WMIN */ | |
2087 | case 0x916: case 0xb16: case 0xd16: case 0xf16: | |
2088 | wrd = (insn >> 12) & 0xf; | |
2089 | rd0 = (insn >> 16) & 0xf; | |
2090 | rd1 = (insn >> 0) & 0xf; | |
2091 | gen_op_iwmmxt_movq_M0_wRn(rd0); | |
2092 | switch ((insn >> 22) & 3) { | |
2093 | case 0: | |
2094 | if (insn & (1 << 21)) | |
2095 | gen_op_iwmmxt_minsb_M0_wRn(rd1); | |
2096 | else | |
2097 | gen_op_iwmmxt_minub_M0_wRn(rd1); | |
2098 | break; | |
2099 | case 1: | |
2100 | if (insn & (1 << 21)) | |
2101 | gen_op_iwmmxt_minsw_M0_wRn(rd1); | |
2102 | else | |
2103 | gen_op_iwmmxt_minuw_M0_wRn(rd1); | |
2104 | break; | |
2105 | case 2: | |
2106 | if (insn & (1 << 21)) | |
2107 | gen_op_iwmmxt_minsl_M0_wRn(rd1); | |
2108 | else | |
2109 | gen_op_iwmmxt_minul_M0_wRn(rd1); | |
2110 | break; | |
2111 | case 3: | |
2112 | return 1; | |
2113 | } | |
2114 | gen_op_iwmmxt_movq_wRn_M0(wrd); | |
2115 | gen_op_iwmmxt_set_mup(); | |
2116 | break; | |
2117 | case 0x016: case 0x216: case 0x416: case 0x616: /* WMAX */ | |
2118 | case 0x816: case 0xa16: case 0xc16: case 0xe16: | |
2119 | wrd = (insn >> 12) & 0xf; | |
2120 | rd0 = (insn >> 16) & 0xf; | |
2121 | rd1 = (insn >> 0) & 0xf; | |
2122 | gen_op_iwmmxt_movq_M0_wRn(rd0); | |
2123 | switch ((insn >> 22) & 3) { | |
2124 | case 0: | |
2125 | if (insn & (1 << 21)) | |
2126 | gen_op_iwmmxt_maxsb_M0_wRn(rd1); | |
2127 | else | |
2128 | gen_op_iwmmxt_maxub_M0_wRn(rd1); | |
2129 | break; | |
2130 | case 1: | |
2131 | if (insn & (1 << 21)) | |
2132 | gen_op_iwmmxt_maxsw_M0_wRn(rd1); | |
2133 | else | |
2134 | gen_op_iwmmxt_maxuw_M0_wRn(rd1); | |
2135 | break; | |
2136 | case 2: | |
2137 | if (insn & (1 << 21)) | |
2138 | gen_op_iwmmxt_maxsl_M0_wRn(rd1); | |
2139 | else | |
2140 | gen_op_iwmmxt_maxul_M0_wRn(rd1); | |
2141 | break; | |
2142 | case 3: | |
2143 | return 1; | |
2144 | } | |
2145 | gen_op_iwmmxt_movq_wRn_M0(wrd); | |
2146 | gen_op_iwmmxt_set_mup(); | |
2147 | break; | |
2148 | case 0x002: case 0x102: case 0x202: case 0x302: /* WALIGNI */ | |
2149 | case 0x402: case 0x502: case 0x602: case 0x702: | |
2150 | wrd = (insn >> 12) & 0xf; | |
2151 | rd0 = (insn >> 16) & 0xf; | |
2152 | rd1 = (insn >> 0) & 0xf; | |
2153 | gen_op_iwmmxt_movq_M0_wRn(rd0); | |
da6b5335 FN |
2154 | tmp = tcg_const_i32((insn >> 20) & 3); |
2155 | iwmmxt_load_reg(cpu_V1, rd1); | |
2156 | gen_helper_iwmmxt_align(cpu_M0, cpu_M0, cpu_V1, tmp); | |
2157 | tcg_temp_free(tmp); | |
18c9b560 AZ |
2158 | gen_op_iwmmxt_movq_wRn_M0(wrd); |
2159 | gen_op_iwmmxt_set_mup(); | |
2160 | break; | |
2161 | case 0x01a: case 0x11a: case 0x21a: case 0x31a: /* WSUB */ | |
2162 | case 0x41a: case 0x51a: case 0x61a: case 0x71a: | |
2163 | case 0x81a: case 0x91a: case 0xa1a: case 0xb1a: | |
2164 | case 0xc1a: case 0xd1a: case 0xe1a: case 0xf1a: | |
2165 | wrd = (insn >> 12) & 0xf; | |
2166 | rd0 = (insn >> 16) & 0xf; | |
2167 | rd1 = (insn >> 0) & 0xf; | |
2168 | gen_op_iwmmxt_movq_M0_wRn(rd0); | |
2169 | switch ((insn >> 20) & 0xf) { | |
2170 | case 0x0: | |
2171 | gen_op_iwmmxt_subnb_M0_wRn(rd1); | |
2172 | break; | |
2173 | case 0x1: | |
2174 | gen_op_iwmmxt_subub_M0_wRn(rd1); | |
2175 | break; | |
2176 | case 0x3: | |
2177 | gen_op_iwmmxt_subsb_M0_wRn(rd1); | |
2178 | break; | |
2179 | case 0x4: | |
2180 | gen_op_iwmmxt_subnw_M0_wRn(rd1); | |
2181 | break; | |
2182 | case 0x5: | |
2183 | gen_op_iwmmxt_subuw_M0_wRn(rd1); | |
2184 | break; | |
2185 | case 0x7: | |
2186 | gen_op_iwmmxt_subsw_M0_wRn(rd1); | |
2187 | break; | |
2188 | case 0x8: | |
2189 | gen_op_iwmmxt_subnl_M0_wRn(rd1); | |
2190 | break; | |
2191 | case 0x9: | |
2192 | gen_op_iwmmxt_subul_M0_wRn(rd1); | |
2193 | break; | |
2194 | case 0xb: | |
2195 | gen_op_iwmmxt_subsl_M0_wRn(rd1); | |
2196 | break; | |
2197 | default: | |
2198 | return 1; | |
2199 | } | |
2200 | gen_op_iwmmxt_movq_wRn_M0(wrd); | |
2201 | gen_op_iwmmxt_set_mup(); | |
2202 | gen_op_iwmmxt_set_cup(); | |
2203 | break; | |
2204 | case 0x01e: case 0x11e: case 0x21e: case 0x31e: /* WSHUFH */ | |
2205 | case 0x41e: case 0x51e: case 0x61e: case 0x71e: | |
2206 | case 0x81e: case 0x91e: case 0xa1e: case 0xb1e: | |
2207 | case 0xc1e: case 0xd1e: case 0xe1e: case 0xf1e: | |
2208 | wrd = (insn >> 12) & 0xf; | |
2209 | rd0 = (insn >> 16) & 0xf; | |
2210 | gen_op_iwmmxt_movq_M0_wRn(rd0); | |
da6b5335 | 2211 | tmp = tcg_const_i32(((insn >> 16) & 0xf0) | (insn & 0x0f)); |
947a2fa2 | 2212 | gen_helper_iwmmxt_shufh(cpu_M0, cpu_M0, tmp); |
da6b5335 | 2213 | tcg_temp_free(tmp); |
18c9b560 AZ |
2214 | gen_op_iwmmxt_movq_wRn_M0(wrd); |
2215 | gen_op_iwmmxt_set_mup(); | |
2216 | gen_op_iwmmxt_set_cup(); | |
2217 | break; | |
2218 | case 0x018: case 0x118: case 0x218: case 0x318: /* WADD */ | |
2219 | case 0x418: case 0x518: case 0x618: case 0x718: | |
2220 | case 0x818: case 0x918: case 0xa18: case 0xb18: | |
2221 | case 0xc18: case 0xd18: case 0xe18: case 0xf18: | |
2222 | wrd = (insn >> 12) & 0xf; | |
2223 | rd0 = (insn >> 16) & 0xf; | |
2224 | rd1 = (insn >> 0) & 0xf; | |
2225 | gen_op_iwmmxt_movq_M0_wRn(rd0); | |
2226 | switch ((insn >> 20) & 0xf) { | |
2227 | case 0x0: | |
2228 | gen_op_iwmmxt_addnb_M0_wRn(rd1); | |
2229 | break; | |
2230 | case 0x1: | |
2231 | gen_op_iwmmxt_addub_M0_wRn(rd1); | |
2232 | break; | |
2233 | case 0x3: | |
2234 | gen_op_iwmmxt_addsb_M0_wRn(rd1); | |
2235 | break; | |
2236 | case 0x4: | |
2237 | gen_op_iwmmxt_addnw_M0_wRn(rd1); | |
2238 | break; | |
2239 | case 0x5: | |
2240 | gen_op_iwmmxt_adduw_M0_wRn(rd1); | |
2241 | break; | |
2242 | case 0x7: | |
2243 | gen_op_iwmmxt_addsw_M0_wRn(rd1); | |
2244 | break; | |
2245 | case 0x8: | |
2246 | gen_op_iwmmxt_addnl_M0_wRn(rd1); | |
2247 | break; | |
2248 | case 0x9: | |
2249 | gen_op_iwmmxt_addul_M0_wRn(rd1); | |
2250 | break; | |
2251 | case 0xb: | |
2252 | gen_op_iwmmxt_addsl_M0_wRn(rd1); | |
2253 | break; | |
2254 | default: | |
2255 | return 1; | |
2256 | } | |
2257 | gen_op_iwmmxt_movq_wRn_M0(wrd); | |
2258 | gen_op_iwmmxt_set_mup(); | |
2259 | gen_op_iwmmxt_set_cup(); | |
2260 | break; | |
2261 | case 0x008: case 0x108: case 0x208: case 0x308: /* WPACK */ | |
2262 | case 0x408: case 0x508: case 0x608: case 0x708: | |
2263 | case 0x808: case 0x908: case 0xa08: case 0xb08: | |
2264 | case 0xc08: case 0xd08: case 0xe08: case 0xf08: | |
da6b5335 FN |
2265 | if (!(insn & (1 << 20)) || ((insn >> 22) & 3) == 0) |
2266 | return 1; | |
18c9b560 AZ |
2267 | wrd = (insn >> 12) & 0xf; |
2268 | rd0 = (insn >> 16) & 0xf; | |
2269 | rd1 = (insn >> 0) & 0xf; | |
2270 | gen_op_iwmmxt_movq_M0_wRn(rd0); | |
18c9b560 | 2271 | switch ((insn >> 22) & 3) { |
18c9b560 AZ |
2272 | case 1: |
2273 | if (insn & (1 << 21)) | |
2274 | gen_op_iwmmxt_packsw_M0_wRn(rd1); | |
2275 | else | |
2276 | gen_op_iwmmxt_packuw_M0_wRn(rd1); | |
2277 | break; | |
2278 | case 2: | |
2279 | if (insn & (1 << 21)) | |
2280 | gen_op_iwmmxt_packsl_M0_wRn(rd1); | |
2281 | else | |
2282 | gen_op_iwmmxt_packul_M0_wRn(rd1); | |
2283 | break; | |
2284 | case 3: | |
2285 | if (insn & (1 << 21)) | |
2286 | gen_op_iwmmxt_packsq_M0_wRn(rd1); | |
2287 | else | |
2288 | gen_op_iwmmxt_packuq_M0_wRn(rd1); | |
2289 | break; | |
2290 | } | |
2291 | gen_op_iwmmxt_movq_wRn_M0(wrd); | |
2292 | gen_op_iwmmxt_set_mup(); | |
2293 | gen_op_iwmmxt_set_cup(); | |
2294 | break; | |
2295 | case 0x201: case 0x203: case 0x205: case 0x207: | |
2296 | case 0x209: case 0x20b: case 0x20d: case 0x20f: | |
2297 | case 0x211: case 0x213: case 0x215: case 0x217: | |
2298 | case 0x219: case 0x21b: case 0x21d: case 0x21f: | |
2299 | wrd = (insn >> 5) & 0xf; | |
2300 | rd0 = (insn >> 12) & 0xf; | |
2301 | rd1 = (insn >> 0) & 0xf; | |
2302 | if (rd0 == 0xf || rd1 == 0xf) | |
2303 | return 1; | |
2304 | gen_op_iwmmxt_movq_M0_wRn(wrd); | |
da6b5335 FN |
2305 | tmp = load_reg(s, rd0); |
2306 | tmp2 = load_reg(s, rd1); | |
18c9b560 AZ |
2307 | switch ((insn >> 16) & 0xf) { |
2308 | case 0x0: /* TMIA */ | |
da6b5335 | 2309 | gen_helper_iwmmxt_muladdsl(cpu_M0, cpu_M0, tmp, tmp2); |
18c9b560 AZ |
2310 | break; |
2311 | case 0x8: /* TMIAPH */ | |
da6b5335 | 2312 | gen_helper_iwmmxt_muladdsw(cpu_M0, cpu_M0, tmp, tmp2); |
18c9b560 AZ |
2313 | break; |
2314 | case 0xc: case 0xd: case 0xe: case 0xf: /* TMIAxy */ | |
18c9b560 | 2315 | if (insn & (1 << 16)) |
da6b5335 | 2316 | tcg_gen_shri_i32(tmp, tmp, 16); |
18c9b560 | 2317 | if (insn & (1 << 17)) |
da6b5335 FN |
2318 | tcg_gen_shri_i32(tmp2, tmp2, 16); |
2319 | gen_helper_iwmmxt_muladdswl(cpu_M0, cpu_M0, tmp, tmp2); | |
18c9b560 AZ |
2320 | break; |
2321 | default: | |
7d1b0095 PM |
2322 | tcg_temp_free_i32(tmp2); |
2323 | tcg_temp_free_i32(tmp); | |
18c9b560 AZ |
2324 | return 1; |
2325 | } | |
7d1b0095 PM |
2326 | tcg_temp_free_i32(tmp2); |
2327 | tcg_temp_free_i32(tmp); | |
18c9b560 AZ |
2328 | gen_op_iwmmxt_movq_wRn_M0(wrd); |
2329 | gen_op_iwmmxt_set_mup(); | |
2330 | break; | |
2331 | default: | |
2332 | return 1; | |
2333 | } | |
2334 | ||
2335 | return 0; | |
2336 | } | |
2337 | ||
2338 | /* Disassemble an XScale DSP instruction. Returns nonzero if an error occured | |
2339 | (ie. an undefined instruction). */ | |
2340 | static int disas_dsp_insn(CPUState *env, DisasContext *s, uint32_t insn) | |
2341 | { | |
2342 | int acc, rd0, rd1, rdhi, rdlo; | |
3a554c0f | 2343 | TCGv tmp, tmp2; |
18c9b560 AZ |
2344 | |
2345 | if ((insn & 0x0ff00f10) == 0x0e200010) { | |
2346 | /* Multiply with Internal Accumulate Format */ | |
2347 | rd0 = (insn >> 12) & 0xf; | |
2348 | rd1 = insn & 0xf; | |
2349 | acc = (insn >> 5) & 7; | |
2350 | ||
2351 | if (acc != 0) | |
2352 | return 1; | |
2353 | ||
3a554c0f FN |
2354 | tmp = load_reg(s, rd0); |
2355 | tmp2 = load_reg(s, rd1); | |
18c9b560 AZ |
2356 | switch ((insn >> 16) & 0xf) { |
2357 | case 0x0: /* MIA */ | |
3a554c0f | 2358 | gen_helper_iwmmxt_muladdsl(cpu_M0, cpu_M0, tmp, tmp2); |
18c9b560 AZ |
2359 | break; |
2360 | case 0x8: /* MIAPH */ | |
3a554c0f | 2361 | gen_helper_iwmmxt_muladdsw(cpu_M0, cpu_M0, tmp, tmp2); |
18c9b560 AZ |
2362 | break; |
2363 | case 0xc: /* MIABB */ | |
2364 | case 0xd: /* MIABT */ | |
2365 | case 0xe: /* MIATB */ | |
2366 | case 0xf: /* MIATT */ | |
18c9b560 | 2367 | if (insn & (1 << 16)) |
3a554c0f | 2368 | tcg_gen_shri_i32(tmp, tmp, 16); |
18c9b560 | 2369 | if (insn & (1 << 17)) |
3a554c0f FN |
2370 | tcg_gen_shri_i32(tmp2, tmp2, 16); |
2371 | gen_helper_iwmmxt_muladdswl(cpu_M0, cpu_M0, tmp, tmp2); | |
18c9b560 AZ |
2372 | break; |
2373 | default: | |
2374 | return 1; | |
2375 | } | |
7d1b0095 PM |
2376 | tcg_temp_free_i32(tmp2); |
2377 | tcg_temp_free_i32(tmp); | |
18c9b560 AZ |
2378 | |
2379 | gen_op_iwmmxt_movq_wRn_M0(acc); | |
2380 | return 0; | |
2381 | } | |
2382 | ||
2383 | if ((insn & 0x0fe00ff8) == 0x0c400000) { | |
2384 | /* Internal Accumulator Access Format */ | |
2385 | rdhi = (insn >> 16) & 0xf; | |
2386 | rdlo = (insn >> 12) & 0xf; | |
2387 | acc = insn & 7; | |
2388 | ||
2389 | if (acc != 0) | |
2390 | return 1; | |
2391 | ||
2392 | if (insn & ARM_CP_RW_BIT) { /* MRA */ | |
3a554c0f FN |
2393 | iwmmxt_load_reg(cpu_V0, acc); |
2394 | tcg_gen_trunc_i64_i32(cpu_R[rdlo], cpu_V0); | |
2395 | tcg_gen_shri_i64(cpu_V0, cpu_V0, 32); | |
2396 | tcg_gen_trunc_i64_i32(cpu_R[rdhi], cpu_V0); | |
2397 | tcg_gen_andi_i32(cpu_R[rdhi], cpu_R[rdhi], (1 << (40 - 32)) - 1); | |
18c9b560 | 2398 | } else { /* MAR */ |
3a554c0f FN |
2399 | tcg_gen_concat_i32_i64(cpu_V0, cpu_R[rdlo], cpu_R[rdhi]); |
2400 | iwmmxt_store_reg(cpu_V0, acc); | |
18c9b560 AZ |
2401 | } |
2402 | return 0; | |
2403 | } | |
2404 | ||
2405 | return 1; | |
2406 | } | |
2407 | ||
c1713132 AZ |
2408 | /* Disassemble system coprocessor instruction. Return nonzero if |
2409 | instruction is not defined. */ | |
2410 | static int disas_cp_insn(CPUState *env, DisasContext *s, uint32_t insn) | |
2411 | { | |
b75263d6 | 2412 | TCGv tmp, tmp2; |
c1713132 AZ |
2413 | uint32_t rd = (insn >> 12) & 0xf; |
2414 | uint32_t cp = (insn >> 8) & 0xf; | |
2415 | if (IS_USER(s)) { | |
2416 | return 1; | |
2417 | } | |
2418 | ||
18c9b560 | 2419 | if (insn & ARM_CP_RW_BIT) { |
c1713132 AZ |
2420 | if (!env->cp[cp].cp_read) |
2421 | return 1; | |
8984bd2e | 2422 | gen_set_pc_im(s->pc); |
7d1b0095 | 2423 | tmp = tcg_temp_new_i32(); |
b75263d6 JR |
2424 | tmp2 = tcg_const_i32(insn); |
2425 | gen_helper_get_cp(tmp, cpu_env, tmp2); | |
2426 | tcg_temp_free(tmp2); | |
8984bd2e | 2427 | store_reg(s, rd, tmp); |
c1713132 AZ |
2428 | } else { |
2429 | if (!env->cp[cp].cp_write) | |
2430 | return 1; | |
8984bd2e PB |
2431 | gen_set_pc_im(s->pc); |
2432 | tmp = load_reg(s, rd); | |
b75263d6 JR |
2433 | tmp2 = tcg_const_i32(insn); |
2434 | gen_helper_set_cp(cpu_env, tmp2, tmp); | |
2435 | tcg_temp_free(tmp2); | |
7d1b0095 | 2436 | tcg_temp_free_i32(tmp); |
c1713132 AZ |
2437 | } |
2438 | return 0; | |
2439 | } | |
2440 | ||
9ee6e8bb PB |
2441 | static int cp15_user_ok(uint32_t insn) |
2442 | { | |
2443 | int cpn = (insn >> 16) & 0xf; | |
2444 | int cpm = insn & 0xf; | |
2445 | int op = ((insn >> 5) & 7) | ((insn >> 18) & 0x38); | |
2446 | ||
2447 | if (cpn == 13 && cpm == 0) { | |
2448 | /* TLS register. */ | |
2449 | if (op == 2 || (op == 3 && (insn & ARM_CP_RW_BIT))) | |
2450 | return 1; | |
2451 | } | |
2452 | if (cpn == 7) { | |
2453 | /* ISB, DSB, DMB. */ | |
2454 | if ((cpm == 5 && op == 4) | |
2455 | || (cpm == 10 && (op == 4 || op == 5))) | |
2456 | return 1; | |
2457 | } | |
2458 | return 0; | |
2459 | } | |
2460 | ||
3f26c122 RV |
2461 | static int cp15_tls_load_store(CPUState *env, DisasContext *s, uint32_t insn, uint32_t rd) |
2462 | { | |
2463 | TCGv tmp; | |
2464 | int cpn = (insn >> 16) & 0xf; | |
2465 | int cpm = insn & 0xf; | |
2466 | int op = ((insn >> 5) & 7) | ((insn >> 18) & 0x38); | |
2467 | ||
2468 | if (!arm_feature(env, ARM_FEATURE_V6K)) | |
2469 | return 0; | |
2470 | ||
2471 | if (!(cpn == 13 && cpm == 0)) | |
2472 | return 0; | |
2473 | ||
2474 | if (insn & ARM_CP_RW_BIT) { | |
3f26c122 RV |
2475 | switch (op) { |
2476 | case 2: | |
c5883be2 | 2477 | tmp = load_cpu_field(cp15.c13_tls1); |
3f26c122 RV |
2478 | break; |
2479 | case 3: | |
c5883be2 | 2480 | tmp = load_cpu_field(cp15.c13_tls2); |
3f26c122 RV |
2481 | break; |
2482 | case 4: | |
c5883be2 | 2483 | tmp = load_cpu_field(cp15.c13_tls3); |
3f26c122 RV |
2484 | break; |
2485 | default: | |
3f26c122 RV |
2486 | return 0; |
2487 | } | |
2488 | store_reg(s, rd, tmp); | |
2489 | ||
2490 | } else { | |
2491 | tmp = load_reg(s, rd); | |
2492 | switch (op) { | |
2493 | case 2: | |
c5883be2 | 2494 | store_cpu_field(tmp, cp15.c13_tls1); |
3f26c122 RV |
2495 | break; |
2496 | case 3: | |
c5883be2 | 2497 | store_cpu_field(tmp, cp15.c13_tls2); |
3f26c122 RV |
2498 | break; |
2499 | case 4: | |
c5883be2 | 2500 | store_cpu_field(tmp, cp15.c13_tls3); |
3f26c122 RV |
2501 | break; |
2502 | default: | |
7d1b0095 | 2503 | tcg_temp_free_i32(tmp); |
3f26c122 RV |
2504 | return 0; |
2505 | } | |
3f26c122 RV |
2506 | } |
2507 | return 1; | |
2508 | } | |
2509 | ||
b5ff1b31 FB |
2510 | /* Disassemble system coprocessor (cp15) instruction. Return nonzero if |
2511 | instruction is not defined. */ | |
a90b7318 | 2512 | static int disas_cp15_insn(CPUState *env, DisasContext *s, uint32_t insn) |
b5ff1b31 FB |
2513 | { |
2514 | uint32_t rd; | |
b75263d6 | 2515 | TCGv tmp, tmp2; |
b5ff1b31 | 2516 | |
9ee6e8bb PB |
2517 | /* M profile cores use memory mapped registers instead of cp15. */ |
2518 | if (arm_feature(env, ARM_FEATURE_M)) | |
2519 | return 1; | |
2520 | ||
2521 | if ((insn & (1 << 25)) == 0) { | |
2522 | if (insn & (1 << 20)) { | |
2523 | /* mrrc */ | |
2524 | return 1; | |
2525 | } | |
2526 | /* mcrr. Used for block cache operations, so implement as no-op. */ | |
2527 | return 0; | |
2528 | } | |
2529 | if ((insn & (1 << 4)) == 0) { | |
2530 | /* cdp */ | |
2531 | return 1; | |
2532 | } | |
2533 | if (IS_USER(s) && !cp15_user_ok(insn)) { | |
b5ff1b31 FB |
2534 | return 1; |
2535 | } | |
cc688901 PM |
2536 | |
2537 | /* Pre-v7 versions of the architecture implemented WFI via coprocessor | |
2538 | * instructions rather than a separate instruction. | |
2539 | */ | |
2540 | if ((insn & 0x0fff0fff) == 0x0e070f90) { | |
2541 | /* 0,c7,c0,4: Standard v6 WFI (also used in some pre-v6 cores). | |
2542 | * In v7, this must NOP. | |
2543 | */ | |
2544 | if (!arm_feature(env, ARM_FEATURE_V7)) { | |
2545 | /* Wait for interrupt. */ | |
2546 | gen_set_pc_im(s->pc); | |
2547 | s->is_jmp = DISAS_WFI; | |
2548 | } | |
9332f9da FB |
2549 | return 0; |
2550 | } | |
cc688901 PM |
2551 | |
2552 | if ((insn & 0x0fff0fff) == 0x0e070f58) { | |
2553 | /* 0,c7,c8,2: Not all pre-v6 cores implemented this WFI, | |
2554 | * so this is slightly over-broad. | |
2555 | */ | |
2556 | if (!arm_feature(env, ARM_FEATURE_V6)) { | |
2557 | /* Wait for interrupt. */ | |
2558 | gen_set_pc_im(s->pc); | |
2559 | s->is_jmp = DISAS_WFI; | |
2560 | return 0; | |
2561 | } | |
2562 | /* Otherwise fall through to handle via helper function. | |
2563 | * In particular, on v7 and some v6 cores this is one of | |
2564 | * the VA-PA registers. | |
2565 | */ | |
2566 | } | |
2567 | ||
b5ff1b31 | 2568 | rd = (insn >> 12) & 0xf; |
3f26c122 RV |
2569 | |
2570 | if (cp15_tls_load_store(env, s, insn, rd)) | |
2571 | return 0; | |
2572 | ||
b75263d6 | 2573 | tmp2 = tcg_const_i32(insn); |
18c9b560 | 2574 | if (insn & ARM_CP_RW_BIT) { |
7d1b0095 | 2575 | tmp = tcg_temp_new_i32(); |
b75263d6 | 2576 | gen_helper_get_cp15(tmp, cpu_env, tmp2); |
b5ff1b31 FB |
2577 | /* If the destination register is r15 then sets condition codes. */ |
2578 | if (rd != 15) | |
8984bd2e PB |
2579 | store_reg(s, rd, tmp); |
2580 | else | |
7d1b0095 | 2581 | tcg_temp_free_i32(tmp); |
b5ff1b31 | 2582 | } else { |
8984bd2e | 2583 | tmp = load_reg(s, rd); |
b75263d6 | 2584 | gen_helper_set_cp15(cpu_env, tmp2, tmp); |
7d1b0095 | 2585 | tcg_temp_free_i32(tmp); |
a90b7318 AZ |
2586 | /* Normally we would always end the TB here, but Linux |
2587 | * arch/arm/mach-pxa/sleep.S expects two instructions following | |
2588 | * an MMU enable to execute from cache. Imitate this behaviour. */ | |
2589 | if (!arm_feature(env, ARM_FEATURE_XSCALE) || | |
2590 | (insn & 0x0fff0fff) != 0x0e010f10) | |
2591 | gen_lookup_tb(s); | |
b5ff1b31 | 2592 | } |
b75263d6 | 2593 | tcg_temp_free_i32(tmp2); |
b5ff1b31 FB |
2594 | return 0; |
2595 | } | |
2596 | ||
9ee6e8bb PB |
2597 | #define VFP_REG_SHR(x, n) (((n) > 0) ? (x) >> (n) : (x) << -(n)) |
2598 | #define VFP_SREG(insn, bigbit, smallbit) \ | |
2599 | ((VFP_REG_SHR(insn, bigbit - 1) & 0x1e) | (((insn) >> (smallbit)) & 1)) | |
2600 | #define VFP_DREG(reg, insn, bigbit, smallbit) do { \ | |
2601 | if (arm_feature(env, ARM_FEATURE_VFP3)) { \ | |
2602 | reg = (((insn) >> (bigbit)) & 0x0f) \ | |
2603 | | (((insn) >> ((smallbit) - 4)) & 0x10); \ | |
2604 | } else { \ | |
2605 | if (insn & (1 << (smallbit))) \ | |
2606 | return 1; \ | |
2607 | reg = ((insn) >> (bigbit)) & 0x0f; \ | |
2608 | }} while (0) | |
2609 | ||
2610 | #define VFP_SREG_D(insn) VFP_SREG(insn, 12, 22) | |
2611 | #define VFP_DREG_D(reg, insn) VFP_DREG(reg, insn, 12, 22) | |
2612 | #define VFP_SREG_N(insn) VFP_SREG(insn, 16, 7) | |
2613 | #define VFP_DREG_N(reg, insn) VFP_DREG(reg, insn, 16, 7) | |
2614 | #define VFP_SREG_M(insn) VFP_SREG(insn, 0, 5) | |
2615 | #define VFP_DREG_M(reg, insn) VFP_DREG(reg, insn, 0, 5) | |
2616 | ||
4373f3ce PB |
2617 | /* Move between integer and VFP cores. */ |
2618 | static TCGv gen_vfp_mrs(void) | |
2619 | { | |
7d1b0095 | 2620 | TCGv tmp = tcg_temp_new_i32(); |
4373f3ce PB |
2621 | tcg_gen_mov_i32(tmp, cpu_F0s); |
2622 | return tmp; | |
2623 | } | |
2624 | ||
2625 | static void gen_vfp_msr(TCGv tmp) | |
2626 | { | |
2627 | tcg_gen_mov_i32(cpu_F0s, tmp); | |
7d1b0095 | 2628 | tcg_temp_free_i32(tmp); |
4373f3ce PB |
2629 | } |
2630 | ||
ad69471c PB |
2631 | static void gen_neon_dup_u8(TCGv var, int shift) |
2632 | { | |
7d1b0095 | 2633 | TCGv tmp = tcg_temp_new_i32(); |
ad69471c PB |
2634 | if (shift) |
2635 | tcg_gen_shri_i32(var, var, shift); | |
86831435 | 2636 | tcg_gen_ext8u_i32(var, var); |
ad69471c PB |
2637 | tcg_gen_shli_i32(tmp, var, 8); |
2638 | tcg_gen_or_i32(var, var, tmp); | |
2639 | tcg_gen_shli_i32(tmp, var, 16); | |
2640 | tcg_gen_or_i32(var, var, tmp); | |
7d1b0095 | 2641 | tcg_temp_free_i32(tmp); |
ad69471c PB |
2642 | } |
2643 | ||
2644 | static void gen_neon_dup_low16(TCGv var) | |
2645 | { | |
7d1b0095 | 2646 | TCGv tmp = tcg_temp_new_i32(); |
86831435 | 2647 | tcg_gen_ext16u_i32(var, var); |
ad69471c PB |
2648 | tcg_gen_shli_i32(tmp, var, 16); |
2649 | tcg_gen_or_i32(var, var, tmp); | |
7d1b0095 | 2650 | tcg_temp_free_i32(tmp); |
ad69471c PB |
2651 | } |
2652 | ||
2653 | static void gen_neon_dup_high16(TCGv var) | |
2654 | { | |
7d1b0095 | 2655 | TCGv tmp = tcg_temp_new_i32(); |
ad69471c PB |
2656 | tcg_gen_andi_i32(var, var, 0xffff0000); |
2657 | tcg_gen_shri_i32(tmp, var, 16); | |
2658 | tcg_gen_or_i32(var, var, tmp); | |
7d1b0095 | 2659 | tcg_temp_free_i32(tmp); |
ad69471c PB |
2660 | } |
2661 | ||
8e18cde3 PM |
2662 | static TCGv gen_load_and_replicate(DisasContext *s, TCGv addr, int size) |
2663 | { | |
2664 | /* Load a single Neon element and replicate into a 32 bit TCG reg */ | |
2665 | TCGv tmp; | |
2666 | switch (size) { | |
2667 | case 0: | |
2668 | tmp = gen_ld8u(addr, IS_USER(s)); | |
2669 | gen_neon_dup_u8(tmp, 0); | |
2670 | break; | |
2671 | case 1: | |
2672 | tmp = gen_ld16u(addr, IS_USER(s)); | |
2673 | gen_neon_dup_low16(tmp); | |
2674 | break; | |
2675 | case 2: | |
2676 | tmp = gen_ld32(addr, IS_USER(s)); | |
2677 | break; | |
2678 | default: /* Avoid compiler warnings. */ | |
2679 | abort(); | |
2680 | } | |
2681 | return tmp; | |
2682 | } | |
2683 | ||
b7bcbe95 FB |
2684 | /* Disassemble a VFP instruction. Returns nonzero if an error occured |
2685 | (ie. an undefined instruction). */ | |
2686 | static int disas_vfp_insn(CPUState * env, DisasContext *s, uint32_t insn) | |
2687 | { | |
2688 | uint32_t rd, rn, rm, op, i, n, offset, delta_d, delta_m, bank_mask; | |
2689 | int dp, veclen; | |
312eea9f | 2690 | TCGv addr; |
4373f3ce | 2691 | TCGv tmp; |
ad69471c | 2692 | TCGv tmp2; |
b7bcbe95 | 2693 | |
40f137e1 PB |
2694 | if (!arm_feature(env, ARM_FEATURE_VFP)) |
2695 | return 1; | |
2696 | ||
5df8bac1 | 2697 | if (!s->vfp_enabled) { |
9ee6e8bb | 2698 | /* VFP disabled. Only allow fmxr/fmrx to/from some control regs. */ |
40f137e1 PB |
2699 | if ((insn & 0x0fe00fff) != 0x0ee00a10) |
2700 | return 1; | |
2701 | rn = (insn >> 16) & 0xf; | |
9ee6e8bb PB |
2702 | if (rn != ARM_VFP_FPSID && rn != ARM_VFP_FPEXC |
2703 | && rn != ARM_VFP_MVFR1 && rn != ARM_VFP_MVFR0) | |
40f137e1 PB |
2704 | return 1; |
2705 | } | |
b7bcbe95 FB |
2706 | dp = ((insn & 0xf00) == 0xb00); |
2707 | switch ((insn >> 24) & 0xf) { | |
2708 | case 0xe: | |
2709 | if (insn & (1 << 4)) { | |
2710 | /* single register transfer */ | |
b7bcbe95 FB |
2711 | rd = (insn >> 12) & 0xf; |
2712 | if (dp) { | |
9ee6e8bb PB |
2713 | int size; |
2714 | int pass; | |
2715 | ||
2716 | VFP_DREG_N(rn, insn); | |
2717 | if (insn & 0xf) | |
b7bcbe95 | 2718 | return 1; |
9ee6e8bb PB |
2719 | if (insn & 0x00c00060 |
2720 | && !arm_feature(env, ARM_FEATURE_NEON)) | |
2721 | return 1; | |
2722 | ||
2723 | pass = (insn >> 21) & 1; | |
2724 | if (insn & (1 << 22)) { | |
2725 | size = 0; | |
2726 | offset = ((insn >> 5) & 3) * 8; | |
2727 | } else if (insn & (1 << 5)) { | |
2728 | size = 1; | |
2729 | offset = (insn & (1 << 6)) ? 16 : 0; | |
2730 | } else { | |
2731 | size = 2; | |
2732 | offset = 0; | |
2733 | } | |
18c9b560 | 2734 | if (insn & ARM_CP_RW_BIT) { |
b7bcbe95 | 2735 | /* vfp->arm */ |
ad69471c | 2736 | tmp = neon_load_reg(rn, pass); |
9ee6e8bb PB |
2737 | switch (size) { |
2738 | case 0: | |
9ee6e8bb | 2739 | if (offset) |
ad69471c | 2740 | tcg_gen_shri_i32(tmp, tmp, offset); |
9ee6e8bb | 2741 | if (insn & (1 << 23)) |
ad69471c | 2742 | gen_uxtb(tmp); |
9ee6e8bb | 2743 | else |
ad69471c | 2744 | gen_sxtb(tmp); |
9ee6e8bb PB |
2745 | break; |
2746 | case 1: | |
9ee6e8bb PB |
2747 | if (insn & (1 << 23)) { |
2748 | if (offset) { | |
ad69471c | 2749 | tcg_gen_shri_i32(tmp, tmp, 16); |
9ee6e8bb | 2750 | } else { |
ad69471c | 2751 | gen_uxth(tmp); |
9ee6e8bb PB |
2752 | } |
2753 | } else { | |
2754 | if (offset) { | |
ad69471c | 2755 | tcg_gen_sari_i32(tmp, tmp, 16); |
9ee6e8bb | 2756 | } else { |
ad69471c | 2757 | gen_sxth(tmp); |
9ee6e8bb PB |
2758 | } |
2759 | } | |
2760 | break; | |
2761 | case 2: | |
9ee6e8bb PB |
2762 | break; |
2763 | } | |
ad69471c | 2764 | store_reg(s, rd, tmp); |
b7bcbe95 FB |
2765 | } else { |
2766 | /* arm->vfp */ | |
ad69471c | 2767 | tmp = load_reg(s, rd); |
9ee6e8bb PB |
2768 | if (insn & (1 << 23)) { |
2769 | /* VDUP */ | |
2770 | if (size == 0) { | |
ad69471c | 2771 | gen_neon_dup_u8(tmp, 0); |
9ee6e8bb | 2772 | } else if (size == 1) { |
ad69471c | 2773 | gen_neon_dup_low16(tmp); |
9ee6e8bb | 2774 | } |
cbbccffc | 2775 | for (n = 0; n <= pass * 2; n++) { |
7d1b0095 | 2776 | tmp2 = tcg_temp_new_i32(); |
cbbccffc PB |
2777 | tcg_gen_mov_i32(tmp2, tmp); |
2778 | neon_store_reg(rn, n, tmp2); | |
2779 | } | |
2780 | neon_store_reg(rn, n, tmp); | |
9ee6e8bb PB |
2781 | } else { |
2782 | /* VMOV */ | |
2783 | switch (size) { | |
2784 | case 0: | |
ad69471c PB |
2785 | tmp2 = neon_load_reg(rn, pass); |
2786 | gen_bfi(tmp, tmp2, tmp, offset, 0xff); | |
7d1b0095 | 2787 | tcg_temp_free_i32(tmp2); |
9ee6e8bb PB |
2788 | break; |
2789 | case 1: | |
ad69471c PB |
2790 | tmp2 = neon_load_reg(rn, pass); |
2791 | gen_bfi(tmp, tmp2, tmp, offset, 0xffff); | |
7d1b0095 | 2792 | tcg_temp_free_i32(tmp2); |
9ee6e8bb PB |
2793 | break; |
2794 | case 2: | |
9ee6e8bb PB |
2795 | break; |
2796 | } | |
ad69471c | 2797 | neon_store_reg(rn, pass, tmp); |
9ee6e8bb | 2798 | } |
b7bcbe95 | 2799 | } |
9ee6e8bb PB |
2800 | } else { /* !dp */ |
2801 | if ((insn & 0x6f) != 0x00) | |
2802 | return 1; | |
2803 | rn = VFP_SREG_N(insn); | |
18c9b560 | 2804 | if (insn & ARM_CP_RW_BIT) { |
b7bcbe95 FB |
2805 | /* vfp->arm */ |
2806 | if (insn & (1 << 21)) { | |
2807 | /* system register */ | |
40f137e1 | 2808 | rn >>= 1; |
9ee6e8bb | 2809 | |
b7bcbe95 | 2810 | switch (rn) { |
40f137e1 | 2811 | case ARM_VFP_FPSID: |
4373f3ce | 2812 | /* VFP2 allows access to FSID from userspace. |
9ee6e8bb PB |
2813 | VFP3 restricts all id registers to privileged |
2814 | accesses. */ | |
2815 | if (IS_USER(s) | |
2816 | && arm_feature(env, ARM_FEATURE_VFP3)) | |
2817 | return 1; | |
4373f3ce | 2818 | tmp = load_cpu_field(vfp.xregs[rn]); |
9ee6e8bb | 2819 | break; |
40f137e1 | 2820 | case ARM_VFP_FPEXC: |
9ee6e8bb PB |
2821 | if (IS_USER(s)) |
2822 | return 1; | |
4373f3ce | 2823 | tmp = load_cpu_field(vfp.xregs[rn]); |
9ee6e8bb | 2824 | break; |
40f137e1 PB |
2825 | case ARM_VFP_FPINST: |
2826 | case ARM_VFP_FPINST2: | |
9ee6e8bb PB |
2827 | /* Not present in VFP3. */ |
2828 | if (IS_USER(s) | |
2829 | || arm_feature(env, ARM_FEATURE_VFP3)) | |
2830 | return 1; | |
4373f3ce | 2831 | tmp = load_cpu_field(vfp.xregs[rn]); |
b7bcbe95 | 2832 | break; |
40f137e1 | 2833 | case ARM_VFP_FPSCR: |
601d70b9 | 2834 | if (rd == 15) { |
4373f3ce PB |
2835 | tmp = load_cpu_field(vfp.xregs[ARM_VFP_FPSCR]); |
2836 | tcg_gen_andi_i32(tmp, tmp, 0xf0000000); | |
2837 | } else { | |
7d1b0095 | 2838 | tmp = tcg_temp_new_i32(); |
4373f3ce PB |
2839 | gen_helper_vfp_get_fpscr(tmp, cpu_env); |
2840 | } | |
b7bcbe95 | 2841 | break; |
9ee6e8bb PB |
2842 | case ARM_VFP_MVFR0: |
2843 | case ARM_VFP_MVFR1: | |
2844 | if (IS_USER(s) | |
2845 | || !arm_feature(env, ARM_FEATURE_VFP3)) | |
2846 | return 1; | |
4373f3ce | 2847 | tmp = load_cpu_field(vfp.xregs[rn]); |
9ee6e8bb | 2848 | break; |
b7bcbe95 FB |
2849 | default: |
2850 | return 1; | |
2851 | } | |
2852 | } else { | |
2853 | gen_mov_F0_vreg(0, rn); | |
4373f3ce | 2854 | tmp = gen_vfp_mrs(); |
b7bcbe95 FB |
2855 | } |
2856 | if (rd == 15) { | |
b5ff1b31 | 2857 | /* Set the 4 flag bits in the CPSR. */ |
4373f3ce | 2858 | gen_set_nzcv(tmp); |
7d1b0095 | 2859 | tcg_temp_free_i32(tmp); |
4373f3ce PB |
2860 | } else { |
2861 | store_reg(s, rd, tmp); | |
2862 | } | |
b7bcbe95 FB |
2863 | } else { |
2864 | /* arm->vfp */ | |
4373f3ce | 2865 | tmp = load_reg(s, rd); |
b7bcbe95 | 2866 | if (insn & (1 << 21)) { |
40f137e1 | 2867 | rn >>= 1; |
b7bcbe95 FB |
2868 | /* system register */ |
2869 | switch (rn) { | |
40f137e1 | 2870 | case ARM_VFP_FPSID: |
9ee6e8bb PB |
2871 | case ARM_VFP_MVFR0: |
2872 | case ARM_VFP_MVFR1: | |
b7bcbe95 FB |
2873 | /* Writes are ignored. */ |
2874 | break; | |
40f137e1 | 2875 | case ARM_VFP_FPSCR: |
4373f3ce | 2876 | gen_helper_vfp_set_fpscr(cpu_env, tmp); |
7d1b0095 | 2877 | tcg_temp_free_i32(tmp); |
b5ff1b31 | 2878 | gen_lookup_tb(s); |
b7bcbe95 | 2879 | break; |
40f137e1 | 2880 | case ARM_VFP_FPEXC: |
9ee6e8bb PB |
2881 | if (IS_USER(s)) |
2882 | return 1; | |
71b3c3de JR |
2883 | /* TODO: VFP subarchitecture support. |
2884 | * For now, keep the EN bit only */ | |
2885 | tcg_gen_andi_i32(tmp, tmp, 1 << 30); | |
4373f3ce | 2886 | store_cpu_field(tmp, vfp.xregs[rn]); |
40f137e1 PB |
2887 | gen_lookup_tb(s); |
2888 | break; | |
2889 | case ARM_VFP_FPINST: | |
2890 | case ARM_VFP_FPINST2: | |
4373f3ce | 2891 | store_cpu_field(tmp, vfp.xregs[rn]); |
40f137e1 | 2892 | break; |
b7bcbe95 FB |
2893 | default: |
2894 | return 1; | |
2895 | } | |
2896 | } else { | |
4373f3ce | 2897 | gen_vfp_msr(tmp); |
b7bcbe95 FB |
2898 | gen_mov_vreg_F0(0, rn); |
2899 | } | |
2900 | } | |
2901 | } | |
2902 | } else { | |
2903 | /* data processing */ | |
2904 | /* The opcode is in bits 23, 21, 20 and 6. */ | |
2905 | op = ((insn >> 20) & 8) | ((insn >> 19) & 6) | ((insn >> 6) & 1); | |
2906 | if (dp) { | |
2907 | if (op == 15) { | |
2908 | /* rn is opcode */ | |
2909 | rn = ((insn >> 15) & 0x1e) | ((insn >> 7) & 1); | |
2910 | } else { | |
2911 | /* rn is register number */ | |
9ee6e8bb | 2912 | VFP_DREG_N(rn, insn); |
b7bcbe95 FB |
2913 | } |
2914 | ||
04595bf6 | 2915 | if (op == 15 && (rn == 15 || ((rn & 0x1c) == 0x18))) { |
b7bcbe95 | 2916 | /* Integer or single precision destination. */ |
9ee6e8bb | 2917 | rd = VFP_SREG_D(insn); |
b7bcbe95 | 2918 | } else { |
9ee6e8bb | 2919 | VFP_DREG_D(rd, insn); |
b7bcbe95 | 2920 | } |
04595bf6 PM |
2921 | if (op == 15 && |
2922 | (((rn & 0x1c) == 0x10) || ((rn & 0x14) == 0x14))) { | |
2923 | /* VCVT from int is always from S reg regardless of dp bit. | |
2924 | * VCVT with immediate frac_bits has same format as SREG_M | |
2925 | */ | |
2926 | rm = VFP_SREG_M(insn); | |
b7bcbe95 | 2927 | } else { |
9ee6e8bb | 2928 | VFP_DREG_M(rm, insn); |
b7bcbe95 FB |
2929 | } |
2930 | } else { | |
9ee6e8bb | 2931 | rn = VFP_SREG_N(insn); |
b7bcbe95 FB |
2932 | if (op == 15 && rn == 15) { |
2933 | /* Double precision destination. */ | |
9ee6e8bb PB |
2934 | VFP_DREG_D(rd, insn); |
2935 | } else { | |
2936 | rd = VFP_SREG_D(insn); | |
2937 | } | |
04595bf6 PM |
2938 | /* NB that we implicitly rely on the encoding for the frac_bits |
2939 | * in VCVT of fixed to float being the same as that of an SREG_M | |
2940 | */ | |
9ee6e8bb | 2941 | rm = VFP_SREG_M(insn); |
b7bcbe95 FB |
2942 | } |
2943 | ||
69d1fc22 | 2944 | veclen = s->vec_len; |
b7bcbe95 FB |
2945 | if (op == 15 && rn > 3) |
2946 | veclen = 0; | |
2947 | ||
2948 | /* Shut up compiler warnings. */ | |
2949 | delta_m = 0; | |
2950 | delta_d = 0; | |
2951 | bank_mask = 0; | |
3b46e624 | 2952 | |
b7bcbe95 FB |
2953 | if (veclen > 0) { |
2954 | if (dp) | |
2955 | bank_mask = 0xc; | |
2956 | else | |
2957 | bank_mask = 0x18; | |
2958 | ||
2959 | /* Figure out what type of vector operation this is. */ | |
2960 | if ((rd & bank_mask) == 0) { | |
2961 | /* scalar */ | |
2962 | veclen = 0; | |
2963 | } else { | |
2964 | if (dp) | |
69d1fc22 | 2965 | delta_d = (s->vec_stride >> 1) + 1; |
b7bcbe95 | 2966 | else |
69d1fc22 | 2967 | delta_d = s->vec_stride + 1; |
b7bcbe95 FB |
2968 | |
2969 | if ((rm & bank_mask) == 0) { | |
2970 | /* mixed scalar/vector */ | |
2971 | delta_m = 0; | |
2972 | } else { | |
2973 | /* vector */ | |
2974 | delta_m = delta_d; | |
2975 | } | |
2976 | } | |
2977 | } | |
2978 | ||
2979 | /* Load the initial operands. */ | |
2980 | if (op == 15) { | |
2981 | switch (rn) { | |
2982 | case 16: | |
2983 | case 17: | |
2984 | /* Integer source */ | |
2985 | gen_mov_F0_vreg(0, rm); | |
2986 | break; | |
2987 | case 8: | |
2988 | case 9: | |
2989 | /* Compare */ | |
2990 | gen_mov_F0_vreg(dp, rd); | |
2991 | gen_mov_F1_vreg(dp, rm); | |
2992 | break; | |
2993 | case 10: | |
2994 | case 11: | |
2995 | /* Compare with zero */ | |
2996 | gen_mov_F0_vreg(dp, rd); | |
2997 | gen_vfp_F1_ld0(dp); | |
2998 | break; | |
9ee6e8bb PB |
2999 | case 20: |
3000 | case 21: | |
3001 | case 22: | |
3002 | case 23: | |
644ad806 PB |
3003 | case 28: |
3004 | case 29: | |
3005 | case 30: | |
3006 | case 31: | |
9ee6e8bb PB |
3007 | /* Source and destination the same. */ |
3008 | gen_mov_F0_vreg(dp, rd); | |
3009 | break; | |
b7bcbe95 FB |
3010 | default: |
3011 | /* One source operand. */ | |
3012 | gen_mov_F0_vreg(dp, rm); | |
9ee6e8bb | 3013 | break; |
b7bcbe95 FB |
3014 | } |
3015 | } else { | |
3016 | /* Two source operands. */ | |
3017 | gen_mov_F0_vreg(dp, rn); | |
3018 | gen_mov_F1_vreg(dp, rm); | |
3019 | } | |
3020 | ||
3021 | for (;;) { | |
3022 | /* Perform the calculation. */ | |
3023 | switch (op) { | |
3024 | case 0: /* mac: fd + (fn * fm) */ | |
3025 | gen_vfp_mul(dp); | |
3026 | gen_mov_F1_vreg(dp, rd); | |
3027 | gen_vfp_add(dp); | |
3028 | break; | |
3029 | case 1: /* nmac: fd - (fn * fm) */ | |
3030 | gen_vfp_mul(dp); | |
3031 | gen_vfp_neg(dp); | |
3032 | gen_mov_F1_vreg(dp, rd); | |
3033 | gen_vfp_add(dp); | |
3034 | break; | |
3035 | case 2: /* msc: -fd + (fn * fm) */ | |
3036 | gen_vfp_mul(dp); | |
3037 | gen_mov_F1_vreg(dp, rd); | |
3038 | gen_vfp_sub(dp); | |
3039 | break; | |
3040 | case 3: /* nmsc: -fd - (fn * fm) */ | |
3041 | gen_vfp_mul(dp); | |
b7bcbe95 | 3042 | gen_vfp_neg(dp); |
c9fb531a PB |
3043 | gen_mov_F1_vreg(dp, rd); |
3044 | gen_vfp_sub(dp); | |
b7bcbe95 FB |
3045 | break; |
3046 | case 4: /* mul: fn * fm */ | |
3047 | gen_vfp_mul(dp); | |
3048 | break; | |
3049 | case 5: /* nmul: -(fn * fm) */ | |
3050 | gen_vfp_mul(dp); | |
3051 | gen_vfp_neg(dp); | |
3052 | break; | |
3053 | case 6: /* add: fn + fm */ | |
3054 | gen_vfp_add(dp); | |
3055 | break; | |
3056 | case 7: /* sub: fn - fm */ | |
3057 | gen_vfp_sub(dp); | |
3058 | break; | |
3059 | case 8: /* div: fn / fm */ | |
3060 | gen_vfp_div(dp); | |
3061 | break; | |
9ee6e8bb PB |
3062 | case 14: /* fconst */ |
3063 | if (!arm_feature(env, ARM_FEATURE_VFP3)) | |
3064 | return 1; | |
3065 | ||
3066 | n = (insn << 12) & 0x80000000; | |
3067 | i = ((insn >> 12) & 0x70) | (insn & 0xf); | |
3068 | if (dp) { | |
3069 | if (i & 0x40) | |
3070 | i |= 0x3f80; | |
3071 | else | |
3072 | i |= 0x4000; | |
3073 | n |= i << 16; | |
4373f3ce | 3074 | tcg_gen_movi_i64(cpu_F0d, ((uint64_t)n) << 32); |
9ee6e8bb PB |
3075 | } else { |
3076 | if (i & 0x40) | |
3077 | i |= 0x780; | |
3078 | else | |
3079 | i |= 0x800; | |
3080 | n |= i << 19; | |
5b340b51 | 3081 | tcg_gen_movi_i32(cpu_F0s, n); |
9ee6e8bb | 3082 | } |
9ee6e8bb | 3083 | break; |
b7bcbe95 FB |
3084 | case 15: /* extension space */ |
3085 | switch (rn) { | |
3086 | case 0: /* cpy */ | |
3087 | /* no-op */ | |
3088 | break; | |
3089 | case 1: /* abs */ | |
3090 | gen_vfp_abs(dp); | |
3091 | break; | |
3092 | case 2: /* neg */ | |
3093 | gen_vfp_neg(dp); | |
3094 | break; | |
3095 | case 3: /* sqrt */ | |
3096 | gen_vfp_sqrt(dp); | |
3097 | break; | |
60011498 PB |
3098 | case 4: /* vcvtb.f32.f16 */ |
3099 | if (!arm_feature(env, ARM_FEATURE_VFP_FP16)) | |
3100 | return 1; | |
3101 | tmp = gen_vfp_mrs(); | |
3102 | tcg_gen_ext16u_i32(tmp, tmp); | |
3103 | gen_helper_vfp_fcvt_f16_to_f32(cpu_F0s, tmp, cpu_env); | |
7d1b0095 | 3104 | tcg_temp_free_i32(tmp); |
60011498 PB |
3105 | break; |
3106 | case 5: /* vcvtt.f32.f16 */ | |
3107 | if (!arm_feature(env, ARM_FEATURE_VFP_FP16)) | |
3108 | return 1; | |
3109 | tmp = gen_vfp_mrs(); | |
3110 | tcg_gen_shri_i32(tmp, tmp, 16); | |
3111 | gen_helper_vfp_fcvt_f16_to_f32(cpu_F0s, tmp, cpu_env); | |
7d1b0095 | 3112 | tcg_temp_free_i32(tmp); |
60011498 PB |
3113 | break; |
3114 | case 6: /* vcvtb.f16.f32 */ | |
3115 | if (!arm_feature(env, ARM_FEATURE_VFP_FP16)) | |
3116 | return 1; | |
7d1b0095 | 3117 | tmp = tcg_temp_new_i32(); |
60011498 PB |
3118 | gen_helper_vfp_fcvt_f32_to_f16(tmp, cpu_F0s, cpu_env); |
3119 | gen_mov_F0_vreg(0, rd); | |
3120 | tmp2 = gen_vfp_mrs(); | |
3121 | tcg_gen_andi_i32(tmp2, tmp2, 0xffff0000); | |
3122 | tcg_gen_or_i32(tmp, tmp, tmp2); | |
7d1b0095 | 3123 | tcg_temp_free_i32(tmp2); |
60011498 PB |
3124 | gen_vfp_msr(tmp); |
3125 | break; | |
3126 | case 7: /* vcvtt.f16.f32 */ | |
3127 | if (!arm_feature(env, ARM_FEATURE_VFP_FP16)) | |
3128 | return 1; | |
7d1b0095 | 3129 | tmp = tcg_temp_new_i32(); |
60011498 PB |
3130 | gen_helper_vfp_fcvt_f32_to_f16(tmp, cpu_F0s, cpu_env); |
3131 | tcg_gen_shli_i32(tmp, tmp, 16); | |
3132 | gen_mov_F0_vreg(0, rd); | |
3133 | tmp2 = gen_vfp_mrs(); | |
3134 | tcg_gen_ext16u_i32(tmp2, tmp2); | |
3135 | tcg_gen_or_i32(tmp, tmp, tmp2); | |
7d1b0095 | 3136 | tcg_temp_free_i32(tmp2); |
60011498 PB |
3137 | gen_vfp_msr(tmp); |
3138 | break; | |
b7bcbe95 FB |
3139 | case 8: /* cmp */ |
3140 | gen_vfp_cmp(dp); | |
3141 | break; | |
3142 | case 9: /* cmpe */ | |
3143 | gen_vfp_cmpe(dp); | |
3144 | break; | |
3145 | case 10: /* cmpz */ | |
3146 | gen_vfp_cmp(dp); | |
3147 | break; | |
3148 | case 11: /* cmpez */ | |
3149 | gen_vfp_F1_ld0(dp); | |
3150 | gen_vfp_cmpe(dp); | |
3151 | break; | |
3152 | case 15: /* single<->double conversion */ | |
3153 | if (dp) | |
4373f3ce | 3154 | gen_helper_vfp_fcvtsd(cpu_F0s, cpu_F0d, cpu_env); |
b7bcbe95 | 3155 | else |
4373f3ce | 3156 | gen_helper_vfp_fcvtds(cpu_F0d, cpu_F0s, cpu_env); |
b7bcbe95 FB |
3157 | break; |
3158 | case 16: /* fuito */ | |
3159 | gen_vfp_uito(dp); | |
3160 | break; | |
3161 | case 17: /* fsito */ | |
3162 | gen_vfp_sito(dp); | |
3163 | break; | |
9ee6e8bb PB |
3164 | case 20: /* fshto */ |
3165 | if (!arm_feature(env, ARM_FEATURE_VFP3)) | |
3166 | return 1; | |
644ad806 | 3167 | gen_vfp_shto(dp, 16 - rm); |
9ee6e8bb PB |
3168 | break; |
3169 | case 21: /* fslto */ | |
3170 | if (!arm_feature(env, ARM_FEATURE_VFP3)) | |
3171 | return 1; | |
644ad806 | 3172 | gen_vfp_slto(dp, 32 - rm); |
9ee6e8bb PB |
3173 | break; |
3174 | case 22: /* fuhto */ | |
3175 | if (!arm_feature(env, ARM_FEATURE_VFP3)) | |
3176 | return 1; | |
644ad806 | 3177 | gen_vfp_uhto(dp, 16 - rm); |
9ee6e8bb PB |
3178 | break; |
3179 | case 23: /* fulto */ | |
3180 | if (!arm_feature(env, ARM_FEATURE_VFP3)) | |
3181 | return 1; | |
644ad806 | 3182 | gen_vfp_ulto(dp, 32 - rm); |
9ee6e8bb | 3183 | break; |
b7bcbe95 FB |
3184 | case 24: /* ftoui */ |
3185 | gen_vfp_toui(dp); | |
3186 | break; | |
3187 | case 25: /* ftouiz */ | |
3188 | gen_vfp_touiz(dp); | |
3189 | break; | |
3190 | case 26: /* ftosi */ | |
3191 | gen_vfp_tosi(dp); | |
3192 | break; | |
3193 | case 27: /* ftosiz */ | |
3194 | gen_vfp_tosiz(dp); | |
3195 | break; | |
9ee6e8bb PB |
3196 | case 28: /* ftosh */ |
3197 | if (!arm_feature(env, ARM_FEATURE_VFP3)) | |
3198 | return 1; | |
644ad806 | 3199 | gen_vfp_tosh(dp, 16 - rm); |
9ee6e8bb PB |
3200 | break; |
3201 | case 29: /* ftosl */ | |
3202 | if (!arm_feature(env, ARM_FEATURE_VFP3)) | |
3203 | return 1; | |
644ad806 | 3204 | gen_vfp_tosl(dp, 32 - rm); |
9ee6e8bb PB |
3205 | break; |
3206 | case 30: /* ftouh */ | |
3207 | if (!arm_feature(env, ARM_FEATURE_VFP3)) | |
3208 | return 1; | |
644ad806 | 3209 | gen_vfp_touh(dp, 16 - rm); |
9ee6e8bb PB |
3210 | break; |
3211 | case 31: /* ftoul */ | |
3212 | if (!arm_feature(env, ARM_FEATURE_VFP3)) | |
3213 | return 1; | |
644ad806 | 3214 | gen_vfp_toul(dp, 32 - rm); |
9ee6e8bb | 3215 | break; |
b7bcbe95 FB |
3216 | default: /* undefined */ |
3217 | printf ("rn:%d\n", rn); | |
3218 | return 1; | |
3219 | } | |
3220 | break; | |
3221 | default: /* undefined */ | |
3222 | printf ("op:%d\n", op); | |
3223 | return 1; | |
3224 | } | |
3225 | ||
3226 | /* Write back the result. */ | |
3227 | if (op == 15 && (rn >= 8 && rn <= 11)) | |
3228 | ; /* Comparison, do nothing. */ | |
04595bf6 PM |
3229 | else if (op == 15 && dp && ((rn & 0x1c) == 0x18)) |
3230 | /* VCVT double to int: always integer result. */ | |
b7bcbe95 FB |
3231 | gen_mov_vreg_F0(0, rd); |
3232 | else if (op == 15 && rn == 15) | |
3233 | /* conversion */ | |
3234 | gen_mov_vreg_F0(!dp, rd); | |
3235 | else | |
3236 | gen_mov_vreg_F0(dp, rd); | |
3237 | ||
3238 | /* break out of the loop if we have finished */ | |
3239 | if (veclen == 0) | |
3240 | break; | |
3241 | ||
3242 | if (op == 15 && delta_m == 0) { | |
3243 | /* single source one-many */ | |
3244 | while (veclen--) { | |
3245 | rd = ((rd + delta_d) & (bank_mask - 1)) | |
3246 | | (rd & bank_mask); | |
3247 | gen_mov_vreg_F0(dp, rd); | |
3248 | } | |
3249 | break; | |
3250 | } | |
3251 | /* Setup the next operands. */ | |
3252 | veclen--; | |
3253 | rd = ((rd + delta_d) & (bank_mask - 1)) | |
3254 | | (rd & bank_mask); | |
3255 | ||
3256 | if (op == 15) { | |
3257 | /* One source operand. */ | |
3258 | rm = ((rm + delta_m) & (bank_mask - 1)) | |
3259 | | (rm & bank_mask); | |
3260 | gen_mov_F0_vreg(dp, rm); | |
3261 | } else { | |
3262 | /* Two source operands. */ | |
3263 | rn = ((rn + delta_d) & (bank_mask - 1)) | |
3264 | | (rn & bank_mask); | |
3265 | gen_mov_F0_vreg(dp, rn); | |
3266 | if (delta_m) { | |
3267 | rm = ((rm + delta_m) & (bank_mask - 1)) | |
3268 | | (rm & bank_mask); | |
3269 | gen_mov_F1_vreg(dp, rm); | |
3270 | } | |
3271 | } | |
3272 | } | |
3273 | } | |
3274 | break; | |
3275 | case 0xc: | |
3276 | case 0xd: | |
8387da81 | 3277 | if ((insn & 0x03e00000) == 0x00400000) { |
b7bcbe95 FB |
3278 | /* two-register transfer */ |
3279 | rn = (insn >> 16) & 0xf; | |
3280 | rd = (insn >> 12) & 0xf; | |
3281 | if (dp) { | |
9ee6e8bb PB |
3282 | VFP_DREG_M(rm, insn); |
3283 | } else { | |
3284 | rm = VFP_SREG_M(insn); | |
3285 | } | |
b7bcbe95 | 3286 | |
18c9b560 | 3287 | if (insn & ARM_CP_RW_BIT) { |
b7bcbe95 FB |
3288 | /* vfp->arm */ |
3289 | if (dp) { | |
4373f3ce PB |
3290 | gen_mov_F0_vreg(0, rm * 2); |
3291 | tmp = gen_vfp_mrs(); | |
3292 | store_reg(s, rd, tmp); | |
3293 | gen_mov_F0_vreg(0, rm * 2 + 1); | |
3294 | tmp = gen_vfp_mrs(); | |
3295 | store_reg(s, rn, tmp); | |
b7bcbe95 FB |
3296 | } else { |
3297 | gen_mov_F0_vreg(0, rm); | |
4373f3ce | 3298 | tmp = gen_vfp_mrs(); |
8387da81 | 3299 | store_reg(s, rd, tmp); |
b7bcbe95 | 3300 | gen_mov_F0_vreg(0, rm + 1); |
4373f3ce | 3301 | tmp = gen_vfp_mrs(); |
8387da81 | 3302 | store_reg(s, rn, tmp); |
b7bcbe95 FB |
3303 | } |
3304 | } else { | |
3305 | /* arm->vfp */ | |
3306 | if (dp) { | |
4373f3ce PB |
3307 | tmp = load_reg(s, rd); |
3308 | gen_vfp_msr(tmp); | |
3309 | gen_mov_vreg_F0(0, rm * 2); | |
3310 | tmp = load_reg(s, rn); | |
3311 | gen_vfp_msr(tmp); | |
3312 | gen_mov_vreg_F0(0, rm * 2 + 1); | |
b7bcbe95 | 3313 | } else { |
8387da81 | 3314 | tmp = load_reg(s, rd); |
4373f3ce | 3315 | gen_vfp_msr(tmp); |
b7bcbe95 | 3316 | gen_mov_vreg_F0(0, rm); |
8387da81 | 3317 | tmp = load_reg(s, rn); |
4373f3ce | 3318 | gen_vfp_msr(tmp); |
b7bcbe95 FB |
3319 | gen_mov_vreg_F0(0, rm + 1); |
3320 | } | |
3321 | } | |
3322 | } else { | |
3323 | /* Load/store */ | |
3324 | rn = (insn >> 16) & 0xf; | |
3325 | if (dp) | |
9ee6e8bb | 3326 | VFP_DREG_D(rd, insn); |
b7bcbe95 | 3327 | else |
9ee6e8bb PB |
3328 | rd = VFP_SREG_D(insn); |
3329 | if (s->thumb && rn == 15) { | |
7d1b0095 | 3330 | addr = tcg_temp_new_i32(); |
312eea9f | 3331 | tcg_gen_movi_i32(addr, s->pc & ~2); |
9ee6e8bb | 3332 | } else { |
312eea9f | 3333 | addr = load_reg(s, rn); |
9ee6e8bb | 3334 | } |
b7bcbe95 FB |
3335 | if ((insn & 0x01200000) == 0x01000000) { |
3336 | /* Single load/store */ | |
3337 | offset = (insn & 0xff) << 2; | |
3338 | if ((insn & (1 << 23)) == 0) | |
3339 | offset = -offset; | |
312eea9f | 3340 | tcg_gen_addi_i32(addr, addr, offset); |
b7bcbe95 | 3341 | if (insn & (1 << 20)) { |
312eea9f | 3342 | gen_vfp_ld(s, dp, addr); |
b7bcbe95 FB |
3343 | gen_mov_vreg_F0(dp, rd); |
3344 | } else { | |
3345 | gen_mov_F0_vreg(dp, rd); | |
312eea9f | 3346 | gen_vfp_st(s, dp, addr); |
b7bcbe95 | 3347 | } |
7d1b0095 | 3348 | tcg_temp_free_i32(addr); |
b7bcbe95 FB |
3349 | } else { |
3350 | /* load/store multiple */ | |
3351 | if (dp) | |
3352 | n = (insn >> 1) & 0x7f; | |
3353 | else | |
3354 | n = insn & 0xff; | |
3355 | ||
3356 | if (insn & (1 << 24)) /* pre-decrement */ | |
312eea9f | 3357 | tcg_gen_addi_i32(addr, addr, -((insn & 0xff) << 2)); |
b7bcbe95 FB |
3358 | |
3359 | if (dp) | |
3360 | offset = 8; | |
3361 | else | |
3362 | offset = 4; | |
3363 | for (i = 0; i < n; i++) { | |
18c9b560 | 3364 | if (insn & ARM_CP_RW_BIT) { |
b7bcbe95 | 3365 | /* load */ |
312eea9f | 3366 | gen_vfp_ld(s, dp, addr); |
b7bcbe95 FB |
3367 | gen_mov_vreg_F0(dp, rd + i); |
3368 | } else { | |
3369 | /* store */ | |
3370 | gen_mov_F0_vreg(dp, rd + i); | |
312eea9f | 3371 | gen_vfp_st(s, dp, addr); |
b7bcbe95 | 3372 | } |
312eea9f | 3373 | tcg_gen_addi_i32(addr, addr, offset); |
b7bcbe95 FB |
3374 | } |
3375 | if (insn & (1 << 21)) { | |
3376 | /* writeback */ | |
3377 | if (insn & (1 << 24)) | |
3378 | offset = -offset * n; | |
3379 | else if (dp && (insn & 1)) | |
3380 | offset = 4; | |
3381 | else | |
3382 | offset = 0; | |
3383 | ||
3384 | if (offset != 0) | |
312eea9f FN |
3385 | tcg_gen_addi_i32(addr, addr, offset); |
3386 | store_reg(s, rn, addr); | |
3387 | } else { | |
7d1b0095 | 3388 | tcg_temp_free_i32(addr); |
b7bcbe95 FB |
3389 | } |
3390 | } | |
3391 | } | |
3392 | break; | |
3393 | default: | |
3394 | /* Should never happen. */ | |
3395 | return 1; | |
3396 | } | |
3397 | return 0; | |
3398 | } | |
3399 | ||
6e256c93 | 3400 | static inline void gen_goto_tb(DisasContext *s, int n, uint32_t dest) |
c53be334 | 3401 | { |
6e256c93 FB |
3402 | TranslationBlock *tb; |
3403 | ||
3404 | tb = s->tb; | |
3405 | if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK)) { | |
57fec1fe | 3406 | tcg_gen_goto_tb(n); |
8984bd2e | 3407 | gen_set_pc_im(dest); |
4b4a72e5 | 3408 | tcg_gen_exit_tb((tcg_target_long)tb + n); |
6e256c93 | 3409 | } else { |
8984bd2e | 3410 | gen_set_pc_im(dest); |
57fec1fe | 3411 | tcg_gen_exit_tb(0); |
6e256c93 | 3412 | } |
c53be334 FB |
3413 | } |
3414 | ||
8aaca4c0 FB |
3415 | static inline void gen_jmp (DisasContext *s, uint32_t dest) |
3416 | { | |
551bd27f | 3417 | if (unlikely(s->singlestep_enabled)) { |
8aaca4c0 | 3418 | /* An indirect jump so that we still trigger the debug exception. */ |
5899f386 | 3419 | if (s->thumb) |
d9ba4830 PB |
3420 | dest |= 1; |
3421 | gen_bx_im(s, dest); | |
8aaca4c0 | 3422 | } else { |
6e256c93 | 3423 | gen_goto_tb(s, 0, dest); |
8aaca4c0 FB |
3424 | s->is_jmp = DISAS_TB_JUMP; |
3425 | } | |
3426 | } | |
3427 | ||
d9ba4830 | 3428 | static inline void gen_mulxy(TCGv t0, TCGv t1, int x, int y) |
b5ff1b31 | 3429 | { |
ee097184 | 3430 | if (x) |
d9ba4830 | 3431 | tcg_gen_sari_i32(t0, t0, 16); |
b5ff1b31 | 3432 | else |
d9ba4830 | 3433 | gen_sxth(t0); |
ee097184 | 3434 | if (y) |
d9ba4830 | 3435 | tcg_gen_sari_i32(t1, t1, 16); |
b5ff1b31 | 3436 | else |
d9ba4830 PB |
3437 | gen_sxth(t1); |
3438 | tcg_gen_mul_i32(t0, t0, t1); | |
b5ff1b31 FB |
3439 | } |
3440 | ||
3441 | /* Return the mask of PSR bits set by a MSR instruction. */ | |
9ee6e8bb | 3442 | static uint32_t msr_mask(CPUState *env, DisasContext *s, int flags, int spsr) { |
b5ff1b31 FB |
3443 | uint32_t mask; |
3444 | ||
3445 | mask = 0; | |
3446 | if (flags & (1 << 0)) | |
3447 | mask |= 0xff; | |
3448 | if (flags & (1 << 1)) | |
3449 | mask |= 0xff00; | |
3450 | if (flags & (1 << 2)) | |
3451 | mask |= 0xff0000; | |
3452 | if (flags & (1 << 3)) | |
3453 | mask |= 0xff000000; | |
9ee6e8bb | 3454 | |
2ae23e75 | 3455 | /* Mask out undefined bits. */ |
9ee6e8bb | 3456 | mask &= ~CPSR_RESERVED; |
be5e7a76 DES |
3457 | if (!arm_feature(env, ARM_FEATURE_V4T)) |
3458 | mask &= ~CPSR_T; | |
3459 | if (!arm_feature(env, ARM_FEATURE_V5)) | |
3460 | mask &= ~CPSR_Q; /* V5TE in reality*/ | |
9ee6e8bb | 3461 | if (!arm_feature(env, ARM_FEATURE_V6)) |
e160c51c | 3462 | mask &= ~(CPSR_E | CPSR_GE); |
9ee6e8bb | 3463 | if (!arm_feature(env, ARM_FEATURE_THUMB2)) |
e160c51c | 3464 | mask &= ~CPSR_IT; |
9ee6e8bb | 3465 | /* Mask out execution state bits. */ |
2ae23e75 | 3466 | if (!spsr) |
e160c51c | 3467 | mask &= ~CPSR_EXEC; |
b5ff1b31 FB |
3468 | /* Mask out privileged bits. */ |
3469 | if (IS_USER(s)) | |
9ee6e8bb | 3470 | mask &= CPSR_USER; |
b5ff1b31 FB |
3471 | return mask; |
3472 | } | |
3473 | ||
2fbac54b FN |
3474 | /* Returns nonzero if access to the PSR is not permitted. Marks t0 as dead. */ |
3475 | static int gen_set_psr(DisasContext *s, uint32_t mask, int spsr, TCGv t0) | |
b5ff1b31 | 3476 | { |
d9ba4830 | 3477 | TCGv tmp; |
b5ff1b31 FB |
3478 | if (spsr) { |
3479 | /* ??? This is also undefined in system mode. */ | |
3480 | if (IS_USER(s)) | |
3481 | return 1; | |
d9ba4830 PB |
3482 | |
3483 | tmp = load_cpu_field(spsr); | |
3484 | tcg_gen_andi_i32(tmp, tmp, ~mask); | |
2fbac54b FN |
3485 | tcg_gen_andi_i32(t0, t0, mask); |
3486 | tcg_gen_or_i32(tmp, tmp, t0); | |
d9ba4830 | 3487 | store_cpu_field(tmp, spsr); |
b5ff1b31 | 3488 | } else { |
2fbac54b | 3489 | gen_set_cpsr(t0, mask); |
b5ff1b31 | 3490 | } |
7d1b0095 | 3491 | tcg_temp_free_i32(t0); |
b5ff1b31 FB |
3492 | gen_lookup_tb(s); |
3493 | return 0; | |
3494 | } | |
3495 | ||
2fbac54b FN |
3496 | /* Returns nonzero if access to the PSR is not permitted. */ |
3497 | static int gen_set_psr_im(DisasContext *s, uint32_t mask, int spsr, uint32_t val) | |
3498 | { | |
3499 | TCGv tmp; | |
7d1b0095 | 3500 | tmp = tcg_temp_new_i32(); |
2fbac54b FN |
3501 | tcg_gen_movi_i32(tmp, val); |
3502 | return gen_set_psr(s, mask, spsr, tmp); | |
3503 | } | |
3504 | ||
e9bb4aa9 JR |
3505 | /* Generate an old-style exception return. Marks pc as dead. */ |
3506 | static void gen_exception_return(DisasContext *s, TCGv pc) | |
b5ff1b31 | 3507 | { |
d9ba4830 | 3508 | TCGv tmp; |
e9bb4aa9 | 3509 | store_reg(s, 15, pc); |
d9ba4830 PB |
3510 | tmp = load_cpu_field(spsr); |
3511 | gen_set_cpsr(tmp, 0xffffffff); | |
7d1b0095 | 3512 | tcg_temp_free_i32(tmp); |
b5ff1b31 FB |
3513 | s->is_jmp = DISAS_UPDATE; |
3514 | } | |
3515 | ||
b0109805 PB |
3516 | /* Generate a v6 exception return. Marks both values as dead. */ |
3517 | static void gen_rfe(DisasContext *s, TCGv pc, TCGv cpsr) | |
2c0262af | 3518 | { |
b0109805 | 3519 | gen_set_cpsr(cpsr, 0xffffffff); |
7d1b0095 | 3520 | tcg_temp_free_i32(cpsr); |
b0109805 | 3521 | store_reg(s, 15, pc); |
9ee6e8bb PB |
3522 | s->is_jmp = DISAS_UPDATE; |
3523 | } | |
3b46e624 | 3524 | |
9ee6e8bb PB |
3525 | static inline void |
3526 | gen_set_condexec (DisasContext *s) | |
3527 | { | |
3528 | if (s->condexec_mask) { | |
8f01245e | 3529 | uint32_t val = (s->condexec_cond << 4) | (s->condexec_mask >> 1); |
7d1b0095 | 3530 | TCGv tmp = tcg_temp_new_i32(); |
8f01245e | 3531 | tcg_gen_movi_i32(tmp, val); |
d9ba4830 | 3532 | store_cpu_field(tmp, condexec_bits); |
9ee6e8bb PB |
3533 | } |
3534 | } | |
3b46e624 | 3535 | |
bc4a0de0 PM |
3536 | static void gen_exception_insn(DisasContext *s, int offset, int excp) |
3537 | { | |
3538 | gen_set_condexec(s); | |
3539 | gen_set_pc_im(s->pc - offset); | |
3540 | gen_exception(excp); | |
3541 | s->is_jmp = DISAS_JUMP; | |
3542 | } | |
3543 | ||
9ee6e8bb PB |
3544 | static void gen_nop_hint(DisasContext *s, int val) |
3545 | { | |
3546 | switch (val) { | |
3547 | case 3: /* wfi */ | |
8984bd2e | 3548 | gen_set_pc_im(s->pc); |
9ee6e8bb PB |
3549 | s->is_jmp = DISAS_WFI; |
3550 | break; | |
3551 | case 2: /* wfe */ | |
3552 | case 4: /* sev */ | |
3553 | /* TODO: Implement SEV and WFE. May help SMP performance. */ | |
3554 | default: /* nop */ | |
3555 | break; | |
3556 | } | |
3557 | } | |
99c475ab | 3558 | |
ad69471c | 3559 | #define CPU_V001 cpu_V0, cpu_V0, cpu_V1 |
9ee6e8bb | 3560 | |
62698be3 | 3561 | static inline void gen_neon_add(int size, TCGv t0, TCGv t1) |
9ee6e8bb PB |
3562 | { |
3563 | switch (size) { | |
dd8fbd78 FN |
3564 | case 0: gen_helper_neon_add_u8(t0, t0, t1); break; |
3565 | case 1: gen_helper_neon_add_u16(t0, t0, t1); break; | |
3566 | case 2: tcg_gen_add_i32(t0, t0, t1); break; | |
62698be3 | 3567 | default: abort(); |
9ee6e8bb | 3568 | } |
9ee6e8bb PB |
3569 | } |
3570 | ||
dd8fbd78 | 3571 | static inline void gen_neon_rsb(int size, TCGv t0, TCGv t1) |
ad69471c PB |
3572 | { |
3573 | switch (size) { | |
dd8fbd78 FN |
3574 | case 0: gen_helper_neon_sub_u8(t0, t1, t0); break; |
3575 | case 1: gen_helper_neon_sub_u16(t0, t1, t0); break; | |
3576 | case 2: tcg_gen_sub_i32(t0, t1, t0); break; | |
ad69471c PB |
3577 | default: return; |
3578 | } | |
3579 | } | |
3580 | ||
3581 | /* 32-bit pairwise ops end up the same as the elementwise versions. */ | |
3582 | #define gen_helper_neon_pmax_s32 gen_helper_neon_max_s32 | |
3583 | #define gen_helper_neon_pmax_u32 gen_helper_neon_max_u32 | |
3584 | #define gen_helper_neon_pmin_s32 gen_helper_neon_min_s32 | |
3585 | #define gen_helper_neon_pmin_u32 gen_helper_neon_min_u32 | |
3586 | ||
ad69471c PB |
3587 | #define GEN_NEON_INTEGER_OP_ENV(name) do { \ |
3588 | switch ((size << 1) | u) { \ | |
3589 | case 0: \ | |
dd8fbd78 | 3590 | gen_helper_neon_##name##_s8(tmp, cpu_env, tmp, tmp2); \ |
ad69471c PB |
3591 | break; \ |
3592 | case 1: \ | |
dd8fbd78 | 3593 | gen_helper_neon_##name##_u8(tmp, cpu_env, tmp, tmp2); \ |
ad69471c PB |
3594 | break; \ |
3595 | case 2: \ | |
dd8fbd78 | 3596 | gen_helper_neon_##name##_s16(tmp, cpu_env, tmp, tmp2); \ |
ad69471c PB |
3597 | break; \ |
3598 | case 3: \ | |
dd8fbd78 | 3599 | gen_helper_neon_##name##_u16(tmp, cpu_env, tmp, tmp2); \ |
ad69471c PB |
3600 | break; \ |
3601 | case 4: \ | |
dd8fbd78 | 3602 | gen_helper_neon_##name##_s32(tmp, cpu_env, tmp, tmp2); \ |
ad69471c PB |
3603 | break; \ |
3604 | case 5: \ | |
dd8fbd78 | 3605 | gen_helper_neon_##name##_u32(tmp, cpu_env, tmp, tmp2); \ |
ad69471c PB |
3606 | break; \ |
3607 | default: return 1; \ | |
3608 | }} while (0) | |
9ee6e8bb PB |
3609 | |
3610 | #define GEN_NEON_INTEGER_OP(name) do { \ | |
3611 | switch ((size << 1) | u) { \ | |
ad69471c | 3612 | case 0: \ |
dd8fbd78 | 3613 | gen_helper_neon_##name##_s8(tmp, tmp, tmp2); \ |
ad69471c PB |
3614 | break; \ |
3615 | case 1: \ | |
dd8fbd78 | 3616 | gen_helper_neon_##name##_u8(tmp, tmp, tmp2); \ |
ad69471c PB |
3617 | break; \ |
3618 | case 2: \ | |
dd8fbd78 | 3619 | gen_helper_neon_##name##_s16(tmp, tmp, tmp2); \ |
ad69471c PB |
3620 | break; \ |
3621 | case 3: \ | |
dd8fbd78 | 3622 | gen_helper_neon_##name##_u16(tmp, tmp, tmp2); \ |
ad69471c PB |
3623 | break; \ |
3624 | case 4: \ | |
dd8fbd78 | 3625 | gen_helper_neon_##name##_s32(tmp, tmp, tmp2); \ |
ad69471c PB |
3626 | break; \ |
3627 | case 5: \ | |
dd8fbd78 | 3628 | gen_helper_neon_##name##_u32(tmp, tmp, tmp2); \ |
ad69471c | 3629 | break; \ |
9ee6e8bb PB |
3630 | default: return 1; \ |
3631 | }} while (0) | |
3632 | ||
dd8fbd78 | 3633 | static TCGv neon_load_scratch(int scratch) |
9ee6e8bb | 3634 | { |
7d1b0095 | 3635 | TCGv tmp = tcg_temp_new_i32(); |
dd8fbd78 FN |
3636 | tcg_gen_ld_i32(tmp, cpu_env, offsetof(CPUARMState, vfp.scratch[scratch])); |
3637 | return tmp; | |
9ee6e8bb PB |
3638 | } |
3639 | ||
dd8fbd78 | 3640 | static void neon_store_scratch(int scratch, TCGv var) |
9ee6e8bb | 3641 | { |
dd8fbd78 | 3642 | tcg_gen_st_i32(var, cpu_env, offsetof(CPUARMState, vfp.scratch[scratch])); |
7d1b0095 | 3643 | tcg_temp_free_i32(var); |
9ee6e8bb PB |
3644 | } |
3645 | ||
dd8fbd78 | 3646 | static inline TCGv neon_get_scalar(int size, int reg) |
9ee6e8bb | 3647 | { |
dd8fbd78 | 3648 | TCGv tmp; |
9ee6e8bb | 3649 | if (size == 1) { |
0fad6efc PM |
3650 | tmp = neon_load_reg(reg & 7, reg >> 4); |
3651 | if (reg & 8) { | |
dd8fbd78 | 3652 | gen_neon_dup_high16(tmp); |
0fad6efc PM |
3653 | } else { |
3654 | gen_neon_dup_low16(tmp); | |
dd8fbd78 | 3655 | } |
0fad6efc PM |
3656 | } else { |
3657 | tmp = neon_load_reg(reg & 15, reg >> 4); | |
9ee6e8bb | 3658 | } |
dd8fbd78 | 3659 | return tmp; |
9ee6e8bb PB |
3660 | } |
3661 | ||
02acedf9 | 3662 | static int gen_neon_unzip(int rd, int rm, int size, int q) |
19457615 | 3663 | { |
02acedf9 | 3664 | TCGv tmp, tmp2; |
600b828c | 3665 | if (!q && size == 2) { |
02acedf9 PM |
3666 | return 1; |
3667 | } | |
3668 | tmp = tcg_const_i32(rd); | |
3669 | tmp2 = tcg_const_i32(rm); | |
3670 | if (q) { | |
3671 | switch (size) { | |
3672 | case 0: | |
2a3f75b4 | 3673 | gen_helper_neon_qunzip8(tmp, tmp2); |
02acedf9 PM |
3674 | break; |
3675 | case 1: | |
2a3f75b4 | 3676 | gen_helper_neon_qunzip16(tmp, tmp2); |
02acedf9 PM |
3677 | break; |
3678 | case 2: | |
2a3f75b4 | 3679 | gen_helper_neon_qunzip32(tmp, tmp2); |
02acedf9 PM |
3680 | break; |
3681 | default: | |
3682 | abort(); | |
3683 | } | |
3684 | } else { | |
3685 | switch (size) { | |
3686 | case 0: | |
2a3f75b4 | 3687 | gen_helper_neon_unzip8(tmp, tmp2); |
02acedf9 PM |
3688 | break; |
3689 | case 1: | |
2a3f75b4 | 3690 | gen_helper_neon_unzip16(tmp, tmp2); |
02acedf9 PM |
3691 | break; |
3692 | default: | |
3693 | abort(); | |
3694 | } | |
3695 | } | |
3696 | tcg_temp_free_i32(tmp); | |
3697 | tcg_temp_free_i32(tmp2); | |
3698 | return 0; | |
19457615 FN |
3699 | } |
3700 | ||
d68a6f3a | 3701 | static int gen_neon_zip(int rd, int rm, int size, int q) |
19457615 FN |
3702 | { |
3703 | TCGv tmp, tmp2; | |
600b828c | 3704 | if (!q && size == 2) { |
d68a6f3a PM |
3705 | return 1; |
3706 | } | |
3707 | tmp = tcg_const_i32(rd); | |
3708 | tmp2 = tcg_const_i32(rm); | |
3709 | if (q) { | |
3710 | switch (size) { | |
3711 | case 0: | |
2a3f75b4 | 3712 | gen_helper_neon_qzip8(tmp, tmp2); |
d68a6f3a PM |
3713 | break; |
3714 | case 1: | |
2a3f75b4 | 3715 | gen_helper_neon_qzip16(tmp, tmp2); |
d68a6f3a PM |
3716 | break; |
3717 | case 2: | |
2a3f75b4 | 3718 | gen_helper_neon_qzip32(tmp, tmp2); |
d68a6f3a PM |
3719 | break; |
3720 | default: | |
3721 | abort(); | |
3722 | } | |
3723 | } else { | |
3724 | switch (size) { | |
3725 | case 0: | |
2a3f75b4 | 3726 | gen_helper_neon_zip8(tmp, tmp2); |
d68a6f3a PM |
3727 | break; |
3728 | case 1: | |
2a3f75b4 | 3729 | gen_helper_neon_zip16(tmp, tmp2); |
d68a6f3a PM |
3730 | break; |
3731 | default: | |
3732 | abort(); | |
3733 | } | |
3734 | } | |
3735 | tcg_temp_free_i32(tmp); | |
3736 | tcg_temp_free_i32(tmp2); | |
3737 | return 0; | |
19457615 FN |
3738 | } |
3739 | ||
19457615 FN |
3740 | static void gen_neon_trn_u8(TCGv t0, TCGv t1) |
3741 | { | |
3742 | TCGv rd, tmp; | |
3743 | ||
7d1b0095 PM |
3744 | rd = tcg_temp_new_i32(); |
3745 | tmp = tcg_temp_new_i32(); | |
19457615 FN |
3746 | |
3747 | tcg_gen_shli_i32(rd, t0, 8); | |
3748 | tcg_gen_andi_i32(rd, rd, 0xff00ff00); | |
3749 | tcg_gen_andi_i32(tmp, t1, 0x00ff00ff); | |
3750 | tcg_gen_or_i32(rd, rd, tmp); | |
3751 | ||
3752 | tcg_gen_shri_i32(t1, t1, 8); | |
3753 | tcg_gen_andi_i32(t1, t1, 0x00ff00ff); | |
3754 | tcg_gen_andi_i32(tmp, t0, 0xff00ff00); | |
3755 | tcg_gen_or_i32(t1, t1, tmp); | |
3756 | tcg_gen_mov_i32(t0, rd); | |
3757 | ||
7d1b0095 PM |
3758 | tcg_temp_free_i32(tmp); |
3759 | tcg_temp_free_i32(rd); | |
19457615 FN |
3760 | } |
3761 | ||
3762 | static void gen_neon_trn_u16(TCGv t0, TCGv t1) | |
3763 | { | |
3764 | TCGv rd, tmp; | |
3765 | ||
7d1b0095 PM |
3766 | rd = tcg_temp_new_i32(); |
3767 | tmp = tcg_temp_new_i32(); | |
19457615 FN |
3768 | |
3769 | tcg_gen_shli_i32(rd, t0, 16); | |
3770 | tcg_gen_andi_i32(tmp, t1, 0xffff); | |
3771 | tcg_gen_or_i32(rd, rd, tmp); | |
3772 | tcg_gen_shri_i32(t1, t1, 16); | |
3773 | tcg_gen_andi_i32(tmp, t0, 0xffff0000); | |
3774 | tcg_gen_or_i32(t1, t1, tmp); | |
3775 | tcg_gen_mov_i32(t0, rd); | |
3776 | ||
7d1b0095 PM |
3777 | tcg_temp_free_i32(tmp); |
3778 | tcg_temp_free_i32(rd); | |
19457615 FN |
3779 | } |
3780 | ||
3781 | ||
9ee6e8bb PB |
3782 | static struct { |
3783 | int nregs; | |
3784 | int interleave; | |
3785 | int spacing; | |
3786 | } neon_ls_element_type[11] = { | |
3787 | {4, 4, 1}, | |
3788 | {4, 4, 2}, | |
3789 | {4, 1, 1}, | |
3790 | {4, 2, 1}, | |
3791 | {3, 3, 1}, | |
3792 | {3, 3, 2}, | |
3793 | {3, 1, 1}, | |
3794 | {1, 1, 1}, | |
3795 | {2, 2, 1}, | |
3796 | {2, 2, 2}, | |
3797 | {2, 1, 1} | |
3798 | }; | |
3799 | ||
3800 | /* Translate a NEON load/store element instruction. Return nonzero if the | |
3801 | instruction is invalid. */ | |
3802 | static int disas_neon_ls_insn(CPUState * env, DisasContext *s, uint32_t insn) | |
3803 | { | |
3804 | int rd, rn, rm; | |
3805 | int op; | |
3806 | int nregs; | |
3807 | int interleave; | |
84496233 | 3808 | int spacing; |
9ee6e8bb PB |
3809 | int stride; |
3810 | int size; | |
3811 | int reg; | |
3812 | int pass; | |
3813 | int load; | |
3814 | int shift; | |
9ee6e8bb | 3815 | int n; |
1b2b1e54 | 3816 | TCGv addr; |
b0109805 | 3817 | TCGv tmp; |
8f8e3aa4 | 3818 | TCGv tmp2; |
84496233 | 3819 | TCGv_i64 tmp64; |
9ee6e8bb | 3820 | |
5df8bac1 | 3821 | if (!s->vfp_enabled) |
9ee6e8bb PB |
3822 | return 1; |
3823 | VFP_DREG_D(rd, insn); | |
3824 | rn = (insn >> 16) & 0xf; | |
3825 | rm = insn & 0xf; | |
3826 | load = (insn & (1 << 21)) != 0; | |
3827 | if ((insn & (1 << 23)) == 0) { | |
3828 | /* Load store all elements. */ | |
3829 | op = (insn >> 8) & 0xf; | |
3830 | size = (insn >> 6) & 3; | |
84496233 | 3831 | if (op > 10) |
9ee6e8bb PB |
3832 | return 1; |
3833 | nregs = neon_ls_element_type[op].nregs; | |
3834 | interleave = neon_ls_element_type[op].interleave; | |
84496233 JR |
3835 | spacing = neon_ls_element_type[op].spacing; |
3836 | if (size == 3 && (interleave | spacing) != 1) | |
3837 | return 1; | |
e318a60b | 3838 | addr = tcg_temp_new_i32(); |
dcc65026 | 3839 | load_reg_var(s, addr, rn); |
9ee6e8bb PB |
3840 | stride = (1 << size) * interleave; |
3841 | for (reg = 0; reg < nregs; reg++) { | |
3842 | if (interleave > 2 || (interleave == 2 && nregs == 2)) { | |
dcc65026 AJ |
3843 | load_reg_var(s, addr, rn); |
3844 | tcg_gen_addi_i32(addr, addr, (1 << size) * reg); | |
9ee6e8bb | 3845 | } else if (interleave == 2 && nregs == 4 && reg == 2) { |
dcc65026 AJ |
3846 | load_reg_var(s, addr, rn); |
3847 | tcg_gen_addi_i32(addr, addr, 1 << size); | |
9ee6e8bb | 3848 | } |
84496233 JR |
3849 | if (size == 3) { |
3850 | if (load) { | |
3851 | tmp64 = gen_ld64(addr, IS_USER(s)); | |
3852 | neon_store_reg64(tmp64, rd); | |
3853 | tcg_temp_free_i64(tmp64); | |
3854 | } else { | |
3855 | tmp64 = tcg_temp_new_i64(); | |
3856 | neon_load_reg64(tmp64, rd); | |
3857 | gen_st64(tmp64, addr, IS_USER(s)); | |
3858 | } | |
3859 | tcg_gen_addi_i32(addr, addr, stride); | |
3860 | } else { | |
3861 | for (pass = 0; pass < 2; pass++) { | |
3862 | if (size == 2) { | |
3863 | if (load) { | |
3864 | tmp = gen_ld32(addr, IS_USER(s)); | |
3865 | neon_store_reg(rd, pass, tmp); | |
3866 | } else { | |
3867 | tmp = neon_load_reg(rd, pass); | |
3868 | gen_st32(tmp, addr, IS_USER(s)); | |
3869 | } | |
1b2b1e54 | 3870 | tcg_gen_addi_i32(addr, addr, stride); |
84496233 JR |
3871 | } else if (size == 1) { |
3872 | if (load) { | |
3873 | tmp = gen_ld16u(addr, IS_USER(s)); | |
3874 | tcg_gen_addi_i32(addr, addr, stride); | |
3875 | tmp2 = gen_ld16u(addr, IS_USER(s)); | |
3876 | tcg_gen_addi_i32(addr, addr, stride); | |
41ba8341 PB |
3877 | tcg_gen_shli_i32(tmp2, tmp2, 16); |
3878 | tcg_gen_or_i32(tmp, tmp, tmp2); | |
7d1b0095 | 3879 | tcg_temp_free_i32(tmp2); |
84496233 JR |
3880 | neon_store_reg(rd, pass, tmp); |
3881 | } else { | |
3882 | tmp = neon_load_reg(rd, pass); | |
7d1b0095 | 3883 | tmp2 = tcg_temp_new_i32(); |
84496233 JR |
3884 | tcg_gen_shri_i32(tmp2, tmp, 16); |
3885 | gen_st16(tmp, addr, IS_USER(s)); | |
3886 | tcg_gen_addi_i32(addr, addr, stride); | |
3887 | gen_st16(tmp2, addr, IS_USER(s)); | |
1b2b1e54 | 3888 | tcg_gen_addi_i32(addr, addr, stride); |
9ee6e8bb | 3889 | } |
84496233 JR |
3890 | } else /* size == 0 */ { |
3891 | if (load) { | |
3892 | TCGV_UNUSED(tmp2); | |
3893 | for (n = 0; n < 4; n++) { | |
3894 | tmp = gen_ld8u(addr, IS_USER(s)); | |
3895 | tcg_gen_addi_i32(addr, addr, stride); | |
3896 | if (n == 0) { | |
3897 | tmp2 = tmp; | |
3898 | } else { | |
41ba8341 PB |
3899 | tcg_gen_shli_i32(tmp, tmp, n * 8); |
3900 | tcg_gen_or_i32(tmp2, tmp2, tmp); | |
7d1b0095 | 3901 | tcg_temp_free_i32(tmp); |
84496233 | 3902 | } |
9ee6e8bb | 3903 | } |
84496233 JR |
3904 | neon_store_reg(rd, pass, tmp2); |
3905 | } else { | |
3906 | tmp2 = neon_load_reg(rd, pass); | |
3907 | for (n = 0; n < 4; n++) { | |
7d1b0095 | 3908 | tmp = tcg_temp_new_i32(); |
84496233 JR |
3909 | if (n == 0) { |
3910 | tcg_gen_mov_i32(tmp, tmp2); | |
3911 | } else { | |
3912 | tcg_gen_shri_i32(tmp, tmp2, n * 8); | |
3913 | } | |
3914 | gen_st8(tmp, addr, IS_USER(s)); | |
3915 | tcg_gen_addi_i32(addr, addr, stride); | |
3916 | } | |
7d1b0095 | 3917 | tcg_temp_free_i32(tmp2); |
9ee6e8bb PB |
3918 | } |
3919 | } | |
3920 | } | |
3921 | } | |
84496233 | 3922 | rd += spacing; |
9ee6e8bb | 3923 | } |
e318a60b | 3924 | tcg_temp_free_i32(addr); |
9ee6e8bb PB |
3925 | stride = nregs * 8; |
3926 | } else { | |
3927 | size = (insn >> 10) & 3; | |
3928 | if (size == 3) { | |
3929 | /* Load single element to all lanes. */ | |
8e18cde3 PM |
3930 | int a = (insn >> 4) & 1; |
3931 | if (!load) { | |
9ee6e8bb | 3932 | return 1; |
8e18cde3 | 3933 | } |
9ee6e8bb PB |
3934 | size = (insn >> 6) & 3; |
3935 | nregs = ((insn >> 8) & 3) + 1; | |
8e18cde3 PM |
3936 | |
3937 | if (size == 3) { | |
3938 | if (nregs != 4 || a == 0) { | |
9ee6e8bb | 3939 | return 1; |
99c475ab | 3940 | } |
8e18cde3 PM |
3941 | /* For VLD4 size==3 a == 1 means 32 bits at 16 byte alignment */ |
3942 | size = 2; | |
3943 | } | |
3944 | if (nregs == 1 && a == 1 && size == 0) { | |
3945 | return 1; | |
3946 | } | |
3947 | if (nregs == 3 && a == 1) { | |
3948 | return 1; | |
3949 | } | |
e318a60b | 3950 | addr = tcg_temp_new_i32(); |
8e18cde3 PM |
3951 | load_reg_var(s, addr, rn); |
3952 | if (nregs == 1) { | |
3953 | /* VLD1 to all lanes: bit 5 indicates how many Dregs to write */ | |
3954 | tmp = gen_load_and_replicate(s, addr, size); | |
3955 | tcg_gen_st_i32(tmp, cpu_env, neon_reg_offset(rd, 0)); | |
3956 | tcg_gen_st_i32(tmp, cpu_env, neon_reg_offset(rd, 1)); | |
3957 | if (insn & (1 << 5)) { | |
3958 | tcg_gen_st_i32(tmp, cpu_env, neon_reg_offset(rd + 1, 0)); | |
3959 | tcg_gen_st_i32(tmp, cpu_env, neon_reg_offset(rd + 1, 1)); | |
3960 | } | |
3961 | tcg_temp_free_i32(tmp); | |
3962 | } else { | |
3963 | /* VLD2/3/4 to all lanes: bit 5 indicates register stride */ | |
3964 | stride = (insn & (1 << 5)) ? 2 : 1; | |
3965 | for (reg = 0; reg < nregs; reg++) { | |
3966 | tmp = gen_load_and_replicate(s, addr, size); | |
3967 | tcg_gen_st_i32(tmp, cpu_env, neon_reg_offset(rd, 0)); | |
3968 | tcg_gen_st_i32(tmp, cpu_env, neon_reg_offset(rd, 1)); | |
3969 | tcg_temp_free_i32(tmp); | |
3970 | tcg_gen_addi_i32(addr, addr, 1 << size); | |
3971 | rd += stride; | |
3972 | } | |
9ee6e8bb | 3973 | } |
e318a60b | 3974 | tcg_temp_free_i32(addr); |
9ee6e8bb PB |
3975 | stride = (1 << size) * nregs; |
3976 | } else { | |
3977 | /* Single element. */ | |
3978 | pass = (insn >> 7) & 1; | |
3979 | switch (size) { | |
3980 | case 0: | |
3981 | shift = ((insn >> 5) & 3) * 8; | |
9ee6e8bb PB |
3982 | stride = 1; |
3983 | break; | |
3984 | case 1: | |
3985 | shift = ((insn >> 6) & 1) * 16; | |
9ee6e8bb PB |
3986 | stride = (insn & (1 << 5)) ? 2 : 1; |
3987 | break; | |
3988 | case 2: | |
3989 | shift = 0; | |
9ee6e8bb PB |
3990 | stride = (insn & (1 << 6)) ? 2 : 1; |
3991 | break; | |
3992 | default: | |
3993 | abort(); | |
3994 | } | |
3995 | nregs = ((insn >> 8) & 3) + 1; | |
e318a60b | 3996 | addr = tcg_temp_new_i32(); |
dcc65026 | 3997 | load_reg_var(s, addr, rn); |
9ee6e8bb PB |
3998 | for (reg = 0; reg < nregs; reg++) { |
3999 | if (load) { | |
9ee6e8bb PB |
4000 | switch (size) { |
4001 | case 0: | |
1b2b1e54 | 4002 | tmp = gen_ld8u(addr, IS_USER(s)); |
9ee6e8bb PB |
4003 | break; |
4004 | case 1: | |
1b2b1e54 | 4005 | tmp = gen_ld16u(addr, IS_USER(s)); |
9ee6e8bb PB |
4006 | break; |
4007 | case 2: | |
1b2b1e54 | 4008 | tmp = gen_ld32(addr, IS_USER(s)); |
9ee6e8bb | 4009 | break; |
a50f5b91 PB |
4010 | default: /* Avoid compiler warnings. */ |
4011 | abort(); | |
9ee6e8bb PB |
4012 | } |
4013 | if (size != 2) { | |
8f8e3aa4 PB |
4014 | tmp2 = neon_load_reg(rd, pass); |
4015 | gen_bfi(tmp, tmp2, tmp, shift, size ? 0xffff : 0xff); | |
7d1b0095 | 4016 | tcg_temp_free_i32(tmp2); |
9ee6e8bb | 4017 | } |
8f8e3aa4 | 4018 | neon_store_reg(rd, pass, tmp); |
9ee6e8bb | 4019 | } else { /* Store */ |
8f8e3aa4 PB |
4020 | tmp = neon_load_reg(rd, pass); |
4021 | if (shift) | |
4022 | tcg_gen_shri_i32(tmp, tmp, shift); | |
9ee6e8bb PB |
4023 | switch (size) { |
4024 | case 0: | |
1b2b1e54 | 4025 | gen_st8(tmp, addr, IS_USER(s)); |
9ee6e8bb PB |
4026 | break; |
4027 | case 1: | |
1b2b1e54 | 4028 | gen_st16(tmp, addr, IS_USER(s)); |
9ee6e8bb PB |
4029 | break; |
4030 | case 2: | |
1b2b1e54 | 4031 | gen_st32(tmp, addr, IS_USER(s)); |
9ee6e8bb | 4032 | break; |
99c475ab | 4033 | } |
99c475ab | 4034 | } |
9ee6e8bb | 4035 | rd += stride; |
1b2b1e54 | 4036 | tcg_gen_addi_i32(addr, addr, 1 << size); |
99c475ab | 4037 | } |
e318a60b | 4038 | tcg_temp_free_i32(addr); |
9ee6e8bb | 4039 | stride = nregs * (1 << size); |
99c475ab | 4040 | } |
9ee6e8bb PB |
4041 | } |
4042 | if (rm != 15) { | |
b26eefb6 PB |
4043 | TCGv base; |
4044 | ||
4045 | base = load_reg(s, rn); | |
9ee6e8bb | 4046 | if (rm == 13) { |
b26eefb6 | 4047 | tcg_gen_addi_i32(base, base, stride); |
9ee6e8bb | 4048 | } else { |
b26eefb6 PB |
4049 | TCGv index; |
4050 | index = load_reg(s, rm); | |
4051 | tcg_gen_add_i32(base, base, index); | |
7d1b0095 | 4052 | tcg_temp_free_i32(index); |
9ee6e8bb | 4053 | } |
b26eefb6 | 4054 | store_reg(s, rn, base); |
9ee6e8bb PB |
4055 | } |
4056 | return 0; | |
4057 | } | |
3b46e624 | 4058 | |
8f8e3aa4 PB |
4059 | /* Bitwise select. dest = c ? t : f. Clobbers T and F. */ |
4060 | static void gen_neon_bsl(TCGv dest, TCGv t, TCGv f, TCGv c) | |
4061 | { | |
4062 | tcg_gen_and_i32(t, t, c); | |
f669df27 | 4063 | tcg_gen_andc_i32(f, f, c); |
8f8e3aa4 PB |
4064 | tcg_gen_or_i32(dest, t, f); |
4065 | } | |
4066 | ||
a7812ae4 | 4067 | static inline void gen_neon_narrow(int size, TCGv dest, TCGv_i64 src) |
ad69471c PB |
4068 | { |
4069 | switch (size) { | |
4070 | case 0: gen_helper_neon_narrow_u8(dest, src); break; | |
4071 | case 1: gen_helper_neon_narrow_u16(dest, src); break; | |
4072 | case 2: tcg_gen_trunc_i64_i32(dest, src); break; | |
4073 | default: abort(); | |
4074 | } | |
4075 | } | |
4076 | ||
a7812ae4 | 4077 | static inline void gen_neon_narrow_sats(int size, TCGv dest, TCGv_i64 src) |
ad69471c PB |
4078 | { |
4079 | switch (size) { | |
2a3f75b4 PM |
4080 | case 0: gen_helper_neon_narrow_sat_s8(dest, src); break; |
4081 | case 1: gen_helper_neon_narrow_sat_s16(dest, src); break; | |
4082 | case 2: gen_helper_neon_narrow_sat_s32(dest, src); break; | |
ad69471c PB |
4083 | default: abort(); |
4084 | } | |
4085 | } | |
4086 | ||
a7812ae4 | 4087 | static inline void gen_neon_narrow_satu(int size, TCGv dest, TCGv_i64 src) |
ad69471c PB |
4088 | { |
4089 | switch (size) { | |
2a3f75b4 PM |
4090 | case 0: gen_helper_neon_narrow_sat_u8(dest, src); break; |
4091 | case 1: gen_helper_neon_narrow_sat_u16(dest, src); break; | |
4092 | case 2: gen_helper_neon_narrow_sat_u32(dest, src); break; | |
ad69471c PB |
4093 | default: abort(); |
4094 | } | |
4095 | } | |
4096 | ||
af1bbf30 JR |
4097 | static inline void gen_neon_unarrow_sats(int size, TCGv dest, TCGv_i64 src) |
4098 | { | |
4099 | switch (size) { | |
2a3f75b4 PM |
4100 | case 0: gen_helper_neon_unarrow_sat8(dest, src); break; |
4101 | case 1: gen_helper_neon_unarrow_sat16(dest, src); break; | |
4102 | case 2: gen_helper_neon_unarrow_sat32(dest, src); break; | |
af1bbf30 JR |
4103 | default: abort(); |
4104 | } | |
4105 | } | |
4106 | ||
ad69471c PB |
4107 | static inline void gen_neon_shift_narrow(int size, TCGv var, TCGv shift, |
4108 | int q, int u) | |
4109 | { | |
4110 | if (q) { | |
4111 | if (u) { | |
4112 | switch (size) { | |
4113 | case 1: gen_helper_neon_rshl_u16(var, var, shift); break; | |
4114 | case 2: gen_helper_neon_rshl_u32(var, var, shift); break; | |
4115 | default: abort(); | |
4116 | } | |
4117 | } else { | |
4118 | switch (size) { | |
4119 | case 1: gen_helper_neon_rshl_s16(var, var, shift); break; | |
4120 | case 2: gen_helper_neon_rshl_s32(var, var, shift); break; | |
4121 | default: abort(); | |
4122 | } | |
4123 | } | |
4124 | } else { | |
4125 | if (u) { | |
4126 | switch (size) { | |
b408a9b0 CL |
4127 | case 1: gen_helper_neon_shl_u16(var, var, shift); break; |
4128 | case 2: gen_helper_neon_shl_u32(var, var, shift); break; | |
ad69471c PB |
4129 | default: abort(); |
4130 | } | |
4131 | } else { | |
4132 | switch (size) { | |
4133 | case 1: gen_helper_neon_shl_s16(var, var, shift); break; | |
4134 | case 2: gen_helper_neon_shl_s32(var, var, shift); break; | |
4135 | default: abort(); | |
4136 | } | |
4137 | } | |
4138 | } | |
4139 | } | |
4140 | ||
a7812ae4 | 4141 | static inline void gen_neon_widen(TCGv_i64 dest, TCGv src, int size, int u) |
ad69471c PB |
4142 | { |
4143 | if (u) { | |
4144 | switch (size) { | |
4145 | case 0: gen_helper_neon_widen_u8(dest, src); break; | |
4146 | case 1: gen_helper_neon_widen_u16(dest, src); break; | |
4147 | case 2: tcg_gen_extu_i32_i64(dest, src); break; | |
4148 | default: abort(); | |
4149 | } | |
4150 | } else { | |
4151 | switch (size) { | |
4152 | case 0: gen_helper_neon_widen_s8(dest, src); break; | |
4153 | case 1: gen_helper_neon_widen_s16(dest, src); break; | |
4154 | case 2: tcg_gen_ext_i32_i64(dest, src); break; | |
4155 | default: abort(); | |
4156 | } | |
4157 | } | |
7d1b0095 | 4158 | tcg_temp_free_i32(src); |
ad69471c PB |
4159 | } |
4160 | ||
4161 | static inline void gen_neon_addl(int size) | |
4162 | { | |
4163 | switch (size) { | |
4164 | case 0: gen_helper_neon_addl_u16(CPU_V001); break; | |
4165 | case 1: gen_helper_neon_addl_u32(CPU_V001); break; | |
4166 | case 2: tcg_gen_add_i64(CPU_V001); break; | |
4167 | default: abort(); | |
4168 | } | |
4169 | } | |
4170 | ||
4171 | static inline void gen_neon_subl(int size) | |
4172 | { | |
4173 | switch (size) { | |
4174 | case 0: gen_helper_neon_subl_u16(CPU_V001); break; | |
4175 | case 1: gen_helper_neon_subl_u32(CPU_V001); break; | |
4176 | case 2: tcg_gen_sub_i64(CPU_V001); break; | |
4177 | default: abort(); | |
4178 | } | |
4179 | } | |
4180 | ||
a7812ae4 | 4181 | static inline void gen_neon_negl(TCGv_i64 var, int size) |
ad69471c PB |
4182 | { |
4183 | switch (size) { | |
4184 | case 0: gen_helper_neon_negl_u16(var, var); break; | |
4185 | case 1: gen_helper_neon_negl_u32(var, var); break; | |
4186 | case 2: gen_helper_neon_negl_u64(var, var); break; | |
4187 | default: abort(); | |
4188 | } | |
4189 | } | |
4190 | ||
a7812ae4 | 4191 | static inline void gen_neon_addl_saturate(TCGv_i64 op0, TCGv_i64 op1, int size) |
ad69471c PB |
4192 | { |
4193 | switch (size) { | |
2a3f75b4 PM |
4194 | case 1: gen_helper_neon_addl_saturate_s32(op0, op0, op1); break; |
4195 | case 2: gen_helper_neon_addl_saturate_s64(op0, op0, op1); break; | |
ad69471c PB |
4196 | default: abort(); |
4197 | } | |
4198 | } | |
4199 | ||
a7812ae4 | 4200 | static inline void gen_neon_mull(TCGv_i64 dest, TCGv a, TCGv b, int size, int u) |
ad69471c | 4201 | { |
a7812ae4 | 4202 | TCGv_i64 tmp; |
ad69471c PB |
4203 | |
4204 | switch ((size << 1) | u) { | |
4205 | case 0: gen_helper_neon_mull_s8(dest, a, b); break; | |
4206 | case 1: gen_helper_neon_mull_u8(dest, a, b); break; | |
4207 | case 2: gen_helper_neon_mull_s16(dest, a, b); break; | |
4208 | case 3: gen_helper_neon_mull_u16(dest, a, b); break; | |
4209 | case 4: | |
4210 | tmp = gen_muls_i64_i32(a, b); | |
4211 | tcg_gen_mov_i64(dest, tmp); | |
7d2aabe2 | 4212 | tcg_temp_free_i64(tmp); |
ad69471c PB |
4213 | break; |
4214 | case 5: | |
4215 | tmp = gen_mulu_i64_i32(a, b); | |
4216 | tcg_gen_mov_i64(dest, tmp); | |
7d2aabe2 | 4217 | tcg_temp_free_i64(tmp); |
ad69471c PB |
4218 | break; |
4219 | default: abort(); | |
4220 | } | |
c6067f04 CL |
4221 | |
4222 | /* gen_helper_neon_mull_[su]{8|16} do not free their parameters. | |
4223 | Don't forget to clean them now. */ | |
4224 | if (size < 2) { | |
7d1b0095 PM |
4225 | tcg_temp_free_i32(a); |
4226 | tcg_temp_free_i32(b); | |
c6067f04 | 4227 | } |
ad69471c PB |
4228 | } |
4229 | ||
c33171c7 PM |
4230 | static void gen_neon_narrow_op(int op, int u, int size, TCGv dest, TCGv_i64 src) |
4231 | { | |
4232 | if (op) { | |
4233 | if (u) { | |
4234 | gen_neon_unarrow_sats(size, dest, src); | |
4235 | } else { | |
4236 | gen_neon_narrow(size, dest, src); | |
4237 | } | |
4238 | } else { | |
4239 | if (u) { | |
4240 | gen_neon_narrow_satu(size, dest, src); | |
4241 | } else { | |
4242 | gen_neon_narrow_sats(size, dest, src); | |
4243 | } | |
4244 | } | |
4245 | } | |
4246 | ||
62698be3 PM |
4247 | /* Symbolic constants for op fields for Neon 3-register same-length. |
4248 | * The values correspond to bits [11:8,4]; see the ARM ARM DDI0406B | |
4249 | * table A7-9. | |
4250 | */ | |
4251 | #define NEON_3R_VHADD 0 | |
4252 | #define NEON_3R_VQADD 1 | |
4253 | #define NEON_3R_VRHADD 2 | |
4254 | #define NEON_3R_LOGIC 3 /* VAND,VBIC,VORR,VMOV,VORN,VEOR,VBIF,VBIT,VBSL */ | |
4255 | #define NEON_3R_VHSUB 4 | |
4256 | #define NEON_3R_VQSUB 5 | |
4257 | #define NEON_3R_VCGT 6 | |
4258 | #define NEON_3R_VCGE 7 | |
4259 | #define NEON_3R_VSHL 8 | |
4260 | #define NEON_3R_VQSHL 9 | |
4261 | #define NEON_3R_VRSHL 10 | |
4262 | #define NEON_3R_VQRSHL 11 | |
4263 | #define NEON_3R_VMAX 12 | |
4264 | #define NEON_3R_VMIN 13 | |
4265 | #define NEON_3R_VABD 14 | |
4266 | #define NEON_3R_VABA 15 | |
4267 | #define NEON_3R_VADD_VSUB 16 | |
4268 | #define NEON_3R_VTST_VCEQ 17 | |
4269 | #define NEON_3R_VML 18 /* VMLA, VMLAL, VMLS, VMLSL */ | |
4270 | #define NEON_3R_VMUL 19 | |
4271 | #define NEON_3R_VPMAX 20 | |
4272 | #define NEON_3R_VPMIN 21 | |
4273 | #define NEON_3R_VQDMULH_VQRDMULH 22 | |
4274 | #define NEON_3R_VPADD 23 | |
4275 | #define NEON_3R_FLOAT_ARITH 26 /* float VADD, VSUB, VPADD, VABD */ | |
4276 | #define NEON_3R_FLOAT_MULTIPLY 27 /* float VMLA, VMLS, VMUL */ | |
4277 | #define NEON_3R_FLOAT_CMP 28 /* float VCEQ, VCGE, VCGT */ | |
4278 | #define NEON_3R_FLOAT_ACMP 29 /* float VACGE, VACGT, VACLE, VACLT */ | |
4279 | #define NEON_3R_FLOAT_MINMAX 30 /* float VMIN, VMAX */ | |
4280 | #define NEON_3R_VRECPS_VRSQRTS 31 /* float VRECPS, VRSQRTS */ | |
4281 | ||
4282 | static const uint8_t neon_3r_sizes[] = { | |
4283 | [NEON_3R_VHADD] = 0x7, | |
4284 | [NEON_3R_VQADD] = 0xf, | |
4285 | [NEON_3R_VRHADD] = 0x7, | |
4286 | [NEON_3R_LOGIC] = 0xf, /* size field encodes op type */ | |
4287 | [NEON_3R_VHSUB] = 0x7, | |
4288 | [NEON_3R_VQSUB] = 0xf, | |
4289 | [NEON_3R_VCGT] = 0x7, | |
4290 | [NEON_3R_VCGE] = 0x7, | |
4291 | [NEON_3R_VSHL] = 0xf, | |
4292 | [NEON_3R_VQSHL] = 0xf, | |
4293 | [NEON_3R_VRSHL] = 0xf, | |
4294 | [NEON_3R_VQRSHL] = 0xf, | |
4295 | [NEON_3R_VMAX] = 0x7, | |
4296 | [NEON_3R_VMIN] = 0x7, | |
4297 | [NEON_3R_VABD] = 0x7, | |
4298 | [NEON_3R_VABA] = 0x7, | |
4299 | [NEON_3R_VADD_VSUB] = 0xf, | |
4300 | [NEON_3R_VTST_VCEQ] = 0x7, | |
4301 | [NEON_3R_VML] = 0x7, | |
4302 | [NEON_3R_VMUL] = 0x7, | |
4303 | [NEON_3R_VPMAX] = 0x7, | |
4304 | [NEON_3R_VPMIN] = 0x7, | |
4305 | [NEON_3R_VQDMULH_VQRDMULH] = 0x6, | |
4306 | [NEON_3R_VPADD] = 0x7, | |
4307 | [NEON_3R_FLOAT_ARITH] = 0x5, /* size bit 1 encodes op */ | |
4308 | [NEON_3R_FLOAT_MULTIPLY] = 0x5, /* size bit 1 encodes op */ | |
4309 | [NEON_3R_FLOAT_CMP] = 0x5, /* size bit 1 encodes op */ | |
4310 | [NEON_3R_FLOAT_ACMP] = 0x5, /* size bit 1 encodes op */ | |
4311 | [NEON_3R_FLOAT_MINMAX] = 0x5, /* size bit 1 encodes op */ | |
4312 | [NEON_3R_VRECPS_VRSQRTS] = 0x5, /* size bit 1 encodes op */ | |
4313 | }; | |
4314 | ||
600b828c PM |
4315 | /* Symbolic constants for op fields for Neon 2-register miscellaneous. |
4316 | * The values correspond to bits [17:16,10:7]; see the ARM ARM DDI0406B | |
4317 | * table A7-13. | |
4318 | */ | |
4319 | #define NEON_2RM_VREV64 0 | |
4320 | #define NEON_2RM_VREV32 1 | |
4321 | #define NEON_2RM_VREV16 2 | |
4322 | #define NEON_2RM_VPADDL 4 | |
4323 | #define NEON_2RM_VPADDL_U 5 | |
4324 | #define NEON_2RM_VCLS 8 | |
4325 | #define NEON_2RM_VCLZ 9 | |
4326 | #define NEON_2RM_VCNT 10 | |
4327 | #define NEON_2RM_VMVN 11 | |
4328 | #define NEON_2RM_VPADAL 12 | |
4329 | #define NEON_2RM_VPADAL_U 13 | |
4330 | #define NEON_2RM_VQABS 14 | |
4331 | #define NEON_2RM_VQNEG 15 | |
4332 | #define NEON_2RM_VCGT0 16 | |
4333 | #define NEON_2RM_VCGE0 17 | |
4334 | #define NEON_2RM_VCEQ0 18 | |
4335 | #define NEON_2RM_VCLE0 19 | |
4336 | #define NEON_2RM_VCLT0 20 | |
4337 | #define NEON_2RM_VABS 22 | |
4338 | #define NEON_2RM_VNEG 23 | |
4339 | #define NEON_2RM_VCGT0_F 24 | |
4340 | #define NEON_2RM_VCGE0_F 25 | |
4341 | #define NEON_2RM_VCEQ0_F 26 | |
4342 | #define NEON_2RM_VCLE0_F 27 | |
4343 | #define NEON_2RM_VCLT0_F 28 | |
4344 | #define NEON_2RM_VABS_F 30 | |
4345 | #define NEON_2RM_VNEG_F 31 | |
4346 | #define NEON_2RM_VSWP 32 | |
4347 | #define NEON_2RM_VTRN 33 | |
4348 | #define NEON_2RM_VUZP 34 | |
4349 | #define NEON_2RM_VZIP 35 | |
4350 | #define NEON_2RM_VMOVN 36 /* Includes VQMOVN, VQMOVUN */ | |
4351 | #define NEON_2RM_VQMOVN 37 /* Includes VQMOVUN */ | |
4352 | #define NEON_2RM_VSHLL 38 | |
4353 | #define NEON_2RM_VCVT_F16_F32 44 | |
4354 | #define NEON_2RM_VCVT_F32_F16 46 | |
4355 | #define NEON_2RM_VRECPE 56 | |
4356 | #define NEON_2RM_VRSQRTE 57 | |
4357 | #define NEON_2RM_VRECPE_F 58 | |
4358 | #define NEON_2RM_VRSQRTE_F 59 | |
4359 | #define NEON_2RM_VCVT_FS 60 | |
4360 | #define NEON_2RM_VCVT_FU 61 | |
4361 | #define NEON_2RM_VCVT_SF 62 | |
4362 | #define NEON_2RM_VCVT_UF 63 | |
4363 | ||
4364 | static int neon_2rm_is_float_op(int op) | |
4365 | { | |
4366 | /* Return true if this neon 2reg-misc op is float-to-float */ | |
4367 | return (op == NEON_2RM_VABS_F || op == NEON_2RM_VNEG_F || | |
4368 | op >= NEON_2RM_VRECPE_F); | |
4369 | } | |
4370 | ||
4371 | /* Each entry in this array has bit n set if the insn allows | |
4372 | * size value n (otherwise it will UNDEF). Since unallocated | |
4373 | * op values will have no bits set they always UNDEF. | |
4374 | */ | |
4375 | static const uint8_t neon_2rm_sizes[] = { | |
4376 | [NEON_2RM_VREV64] = 0x7, | |
4377 | [NEON_2RM_VREV32] = 0x3, | |
4378 | [NEON_2RM_VREV16] = 0x1, | |
4379 | [NEON_2RM_VPADDL] = 0x7, | |
4380 | [NEON_2RM_VPADDL_U] = 0x7, | |
4381 | [NEON_2RM_VCLS] = 0x7, | |
4382 | [NEON_2RM_VCLZ] = 0x7, | |
4383 | [NEON_2RM_VCNT] = 0x1, | |
4384 | [NEON_2RM_VMVN] = 0x1, | |
4385 | [NEON_2RM_VPADAL] = 0x7, | |
4386 | [NEON_2RM_VPADAL_U] = 0x7, | |
4387 | [NEON_2RM_VQABS] = 0x7, | |
4388 | [NEON_2RM_VQNEG] = 0x7, | |
4389 | [NEON_2RM_VCGT0] = 0x7, | |
4390 | [NEON_2RM_VCGE0] = 0x7, | |
4391 | [NEON_2RM_VCEQ0] = 0x7, | |
4392 | [NEON_2RM_VCLE0] = 0x7, | |
4393 | [NEON_2RM_VCLT0] = 0x7, | |
4394 | [NEON_2RM_VABS] = 0x7, | |
4395 | [NEON_2RM_VNEG] = 0x7, | |
4396 | [NEON_2RM_VCGT0_F] = 0x4, | |
4397 | [NEON_2RM_VCGE0_F] = 0x4, | |
4398 | [NEON_2RM_VCEQ0_F] = 0x4, | |
4399 | [NEON_2RM_VCLE0_F] = 0x4, | |
4400 | [NEON_2RM_VCLT0_F] = 0x4, | |
4401 | [NEON_2RM_VABS_F] = 0x4, | |
4402 | [NEON_2RM_VNEG_F] = 0x4, | |
4403 | [NEON_2RM_VSWP] = 0x1, | |
4404 | [NEON_2RM_VTRN] = 0x7, | |
4405 | [NEON_2RM_VUZP] = 0x7, | |
4406 | [NEON_2RM_VZIP] = 0x7, | |
4407 | [NEON_2RM_VMOVN] = 0x7, | |
4408 | [NEON_2RM_VQMOVN] = 0x7, | |
4409 | [NEON_2RM_VSHLL] = 0x7, | |
4410 | [NEON_2RM_VCVT_F16_F32] = 0x2, | |
4411 | [NEON_2RM_VCVT_F32_F16] = 0x2, | |
4412 | [NEON_2RM_VRECPE] = 0x4, | |
4413 | [NEON_2RM_VRSQRTE] = 0x4, | |
4414 | [NEON_2RM_VRECPE_F] = 0x4, | |
4415 | [NEON_2RM_VRSQRTE_F] = 0x4, | |
4416 | [NEON_2RM_VCVT_FS] = 0x4, | |
4417 | [NEON_2RM_VCVT_FU] = 0x4, | |
4418 | [NEON_2RM_VCVT_SF] = 0x4, | |
4419 | [NEON_2RM_VCVT_UF] = 0x4, | |
4420 | }; | |
4421 | ||
9ee6e8bb PB |
4422 | /* Translate a NEON data processing instruction. Return nonzero if the |
4423 | instruction is invalid. | |
ad69471c PB |
4424 | We process data in a mixture of 32-bit and 64-bit chunks. |
4425 | Mostly we use 32-bit chunks so we can use normal scalar instructions. */ | |
2c0262af | 4426 | |
9ee6e8bb PB |
4427 | static int disas_neon_data_insn(CPUState * env, DisasContext *s, uint32_t insn) |
4428 | { | |
4429 | int op; | |
4430 | int q; | |
4431 | int rd, rn, rm; | |
4432 | int size; | |
4433 | int shift; | |
4434 | int pass; | |
4435 | int count; | |
4436 | int pairwise; | |
4437 | int u; | |
ca9a32e4 | 4438 | uint32_t imm, mask; |
b75263d6 | 4439 | TCGv tmp, tmp2, tmp3, tmp4, tmp5; |
a7812ae4 | 4440 | TCGv_i64 tmp64; |
9ee6e8bb | 4441 | |
5df8bac1 | 4442 | if (!s->vfp_enabled) |
9ee6e8bb PB |
4443 | return 1; |
4444 | q = (insn & (1 << 6)) != 0; | |
4445 | u = (insn >> 24) & 1; | |
4446 | VFP_DREG_D(rd, insn); | |
4447 | VFP_DREG_N(rn, insn); | |
4448 | VFP_DREG_M(rm, insn); | |
4449 | size = (insn >> 20) & 3; | |
4450 | if ((insn & (1 << 23)) == 0) { | |
4451 | /* Three register same length. */ | |
4452 | op = ((insn >> 7) & 0x1e) | ((insn >> 4) & 1); | |
62698be3 PM |
4453 | /* Catch invalid op and bad size combinations: UNDEF */ |
4454 | if ((neon_3r_sizes[op] & (1 << size)) == 0) { | |
4455 | return 1; | |
4456 | } | |
25f84f79 PM |
4457 | /* All insns of this form UNDEF for either this condition or the |
4458 | * superset of cases "Q==1"; we catch the latter later. | |
4459 | */ | |
4460 | if (q && ((rd | rn | rm) & 1)) { | |
4461 | return 1; | |
4462 | } | |
62698be3 PM |
4463 | if (size == 3 && op != NEON_3R_LOGIC) { |
4464 | /* 64-bit element instructions. */ | |
9ee6e8bb | 4465 | for (pass = 0; pass < (q ? 2 : 1); pass++) { |
ad69471c PB |
4466 | neon_load_reg64(cpu_V0, rn + pass); |
4467 | neon_load_reg64(cpu_V1, rm + pass); | |
9ee6e8bb | 4468 | switch (op) { |
62698be3 | 4469 | case NEON_3R_VQADD: |
9ee6e8bb | 4470 | if (u) { |
2a3f75b4 | 4471 | gen_helper_neon_qadd_u64(cpu_V0, cpu_V0, cpu_V1); |
2c0262af | 4472 | } else { |
2a3f75b4 | 4473 | gen_helper_neon_qadd_s64(cpu_V0, cpu_V0, cpu_V1); |
2c0262af | 4474 | } |
9ee6e8bb | 4475 | break; |
62698be3 | 4476 | case NEON_3R_VQSUB: |
9ee6e8bb | 4477 | if (u) { |
2a3f75b4 | 4478 | gen_helper_neon_qsub_u64(cpu_V0, cpu_V0, cpu_V1); |
ad69471c | 4479 | } else { |
2a3f75b4 | 4480 | gen_helper_neon_qsub_s64(cpu_V0, cpu_V0, cpu_V1); |
ad69471c PB |
4481 | } |
4482 | break; | |
62698be3 | 4483 | case NEON_3R_VSHL: |
ad69471c PB |
4484 | if (u) { |
4485 | gen_helper_neon_shl_u64(cpu_V0, cpu_V1, cpu_V0); | |
4486 | } else { | |
4487 | gen_helper_neon_shl_s64(cpu_V0, cpu_V1, cpu_V0); | |
4488 | } | |
4489 | break; | |
62698be3 | 4490 | case NEON_3R_VQSHL: |
ad69471c | 4491 | if (u) { |
2a3f75b4 | 4492 | gen_helper_neon_qshl_u64(cpu_V0, cpu_V1, cpu_V0); |
ad69471c | 4493 | } else { |
2a3f75b4 | 4494 | gen_helper_neon_qshl_s64(cpu_V0, cpu_V1, cpu_V0); |
ad69471c PB |
4495 | } |
4496 | break; | |
62698be3 | 4497 | case NEON_3R_VRSHL: |
ad69471c PB |
4498 | if (u) { |
4499 | gen_helper_neon_rshl_u64(cpu_V0, cpu_V1, cpu_V0); | |
1e8d4eec | 4500 | } else { |
ad69471c PB |
4501 | gen_helper_neon_rshl_s64(cpu_V0, cpu_V1, cpu_V0); |
4502 | } | |
4503 | break; | |
62698be3 | 4504 | case NEON_3R_VQRSHL: |
ad69471c | 4505 | if (u) { |
2a3f75b4 | 4506 | gen_helper_neon_qrshl_u64(cpu_V0, cpu_V1, cpu_V0); |
ad69471c | 4507 | } else { |
2a3f75b4 | 4508 | gen_helper_neon_qrshl_s64(cpu_V0, cpu_V1, cpu_V0); |
1e8d4eec | 4509 | } |
9ee6e8bb | 4510 | break; |
62698be3 | 4511 | case NEON_3R_VADD_VSUB: |
9ee6e8bb | 4512 | if (u) { |
ad69471c | 4513 | tcg_gen_sub_i64(CPU_V001); |
9ee6e8bb | 4514 | } else { |
ad69471c | 4515 | tcg_gen_add_i64(CPU_V001); |
9ee6e8bb PB |
4516 | } |
4517 | break; | |
4518 | default: | |
4519 | abort(); | |
2c0262af | 4520 | } |
ad69471c | 4521 | neon_store_reg64(cpu_V0, rd + pass); |
2c0262af | 4522 | } |
9ee6e8bb | 4523 | return 0; |
2c0262af | 4524 | } |
25f84f79 | 4525 | pairwise = 0; |
9ee6e8bb | 4526 | switch (op) { |
62698be3 PM |
4527 | case NEON_3R_VSHL: |
4528 | case NEON_3R_VQSHL: | |
4529 | case NEON_3R_VRSHL: | |
4530 | case NEON_3R_VQRSHL: | |
9ee6e8bb | 4531 | { |
ad69471c PB |
4532 | int rtmp; |
4533 | /* Shift instruction operands are reversed. */ | |
4534 | rtmp = rn; | |
9ee6e8bb | 4535 | rn = rm; |
ad69471c | 4536 | rm = rtmp; |
9ee6e8bb | 4537 | } |
2c0262af | 4538 | break; |
25f84f79 PM |
4539 | case NEON_3R_VPADD: |
4540 | if (u) { | |
4541 | return 1; | |
4542 | } | |
4543 | /* Fall through */ | |
62698be3 PM |
4544 | case NEON_3R_VPMAX: |
4545 | case NEON_3R_VPMIN: | |
9ee6e8bb | 4546 | pairwise = 1; |
2c0262af | 4547 | break; |
25f84f79 PM |
4548 | case NEON_3R_FLOAT_ARITH: |
4549 | pairwise = (u && size < 2); /* if VPADD (float) */ | |
4550 | break; | |
4551 | case NEON_3R_FLOAT_MINMAX: | |
4552 | pairwise = u; /* if VPMIN/VPMAX (float) */ | |
4553 | break; | |
4554 | case NEON_3R_FLOAT_CMP: | |
4555 | if (!u && size) { | |
4556 | /* no encoding for U=0 C=1x */ | |
4557 | return 1; | |
4558 | } | |
4559 | break; | |
4560 | case NEON_3R_FLOAT_ACMP: | |
4561 | if (!u) { | |
4562 | return 1; | |
4563 | } | |
4564 | break; | |
4565 | case NEON_3R_VRECPS_VRSQRTS: | |
4566 | if (u) { | |
4567 | return 1; | |
4568 | } | |
2c0262af | 4569 | break; |
25f84f79 PM |
4570 | case NEON_3R_VMUL: |
4571 | if (u && (size != 0)) { | |
4572 | /* UNDEF on invalid size for polynomial subcase */ | |
4573 | return 1; | |
4574 | } | |
2c0262af | 4575 | break; |
9ee6e8bb | 4576 | default: |
2c0262af | 4577 | break; |
9ee6e8bb | 4578 | } |
dd8fbd78 | 4579 | |
25f84f79 PM |
4580 | if (pairwise && q) { |
4581 | /* All the pairwise insns UNDEF if Q is set */ | |
4582 | return 1; | |
4583 | } | |
4584 | ||
9ee6e8bb PB |
4585 | for (pass = 0; pass < (q ? 4 : 2); pass++) { |
4586 | ||
4587 | if (pairwise) { | |
4588 | /* Pairwise. */ | |
a5a14945 JR |
4589 | if (pass < 1) { |
4590 | tmp = neon_load_reg(rn, 0); | |
4591 | tmp2 = neon_load_reg(rn, 1); | |
9ee6e8bb | 4592 | } else { |
a5a14945 JR |
4593 | tmp = neon_load_reg(rm, 0); |
4594 | tmp2 = neon_load_reg(rm, 1); | |
9ee6e8bb PB |
4595 | } |
4596 | } else { | |
4597 | /* Elementwise. */ | |
dd8fbd78 FN |
4598 | tmp = neon_load_reg(rn, pass); |
4599 | tmp2 = neon_load_reg(rm, pass); | |
9ee6e8bb PB |
4600 | } |
4601 | switch (op) { | |
62698be3 | 4602 | case NEON_3R_VHADD: |
9ee6e8bb PB |
4603 | GEN_NEON_INTEGER_OP(hadd); |
4604 | break; | |
62698be3 | 4605 | case NEON_3R_VQADD: |
2a3f75b4 | 4606 | GEN_NEON_INTEGER_OP(qadd); |
2c0262af | 4607 | break; |
62698be3 | 4608 | case NEON_3R_VRHADD: |
9ee6e8bb | 4609 | GEN_NEON_INTEGER_OP(rhadd); |
2c0262af | 4610 | break; |
62698be3 | 4611 | case NEON_3R_LOGIC: /* Logic ops. */ |
9ee6e8bb PB |
4612 | switch ((u << 2) | size) { |
4613 | case 0: /* VAND */ | |
dd8fbd78 | 4614 | tcg_gen_and_i32(tmp, tmp, tmp2); |
9ee6e8bb PB |
4615 | break; |
4616 | case 1: /* BIC */ | |
f669df27 | 4617 | tcg_gen_andc_i32(tmp, tmp, tmp2); |
9ee6e8bb PB |
4618 | break; |
4619 | case 2: /* VORR */ | |
dd8fbd78 | 4620 | tcg_gen_or_i32(tmp, tmp, tmp2); |
9ee6e8bb PB |
4621 | break; |
4622 | case 3: /* VORN */ | |
f669df27 | 4623 | tcg_gen_orc_i32(tmp, tmp, tmp2); |
9ee6e8bb PB |
4624 | break; |
4625 | case 4: /* VEOR */ | |
dd8fbd78 | 4626 | tcg_gen_xor_i32(tmp, tmp, tmp2); |
9ee6e8bb PB |
4627 | break; |
4628 | case 5: /* VBSL */ | |
dd8fbd78 FN |
4629 | tmp3 = neon_load_reg(rd, pass); |
4630 | gen_neon_bsl(tmp, tmp, tmp2, tmp3); | |
7d1b0095 | 4631 | tcg_temp_free_i32(tmp3); |
9ee6e8bb PB |
4632 | break; |
4633 | case 6: /* VBIT */ | |
dd8fbd78 FN |
4634 | tmp3 = neon_load_reg(rd, pass); |
4635 | gen_neon_bsl(tmp, tmp, tmp3, tmp2); | |
7d1b0095 | 4636 | tcg_temp_free_i32(tmp3); |
9ee6e8bb PB |
4637 | break; |
4638 | case 7: /* VBIF */ | |
dd8fbd78 FN |
4639 | tmp3 = neon_load_reg(rd, pass); |
4640 | gen_neon_bsl(tmp, tmp3, tmp, tmp2); | |
7d1b0095 | 4641 | tcg_temp_free_i32(tmp3); |
9ee6e8bb | 4642 | break; |
2c0262af FB |
4643 | } |
4644 | break; | |
62698be3 | 4645 | case NEON_3R_VHSUB: |
9ee6e8bb PB |
4646 | GEN_NEON_INTEGER_OP(hsub); |
4647 | break; | |
62698be3 | 4648 | case NEON_3R_VQSUB: |
2a3f75b4 | 4649 | GEN_NEON_INTEGER_OP(qsub); |
2c0262af | 4650 | break; |
62698be3 | 4651 | case NEON_3R_VCGT: |
9ee6e8bb PB |
4652 | GEN_NEON_INTEGER_OP(cgt); |
4653 | break; | |
62698be3 | 4654 | case NEON_3R_VCGE: |
9ee6e8bb PB |
4655 | GEN_NEON_INTEGER_OP(cge); |
4656 | break; | |
62698be3 | 4657 | case NEON_3R_VSHL: |
ad69471c | 4658 | GEN_NEON_INTEGER_OP(shl); |
2c0262af | 4659 | break; |
62698be3 | 4660 | case NEON_3R_VQSHL: |
2a3f75b4 | 4661 | GEN_NEON_INTEGER_OP(qshl); |
2c0262af | 4662 | break; |
62698be3 | 4663 | case NEON_3R_VRSHL: |
ad69471c | 4664 | GEN_NEON_INTEGER_OP(rshl); |
2c0262af | 4665 | break; |
62698be3 | 4666 | case NEON_3R_VQRSHL: |
2a3f75b4 | 4667 | GEN_NEON_INTEGER_OP(qrshl); |
9ee6e8bb | 4668 | break; |
62698be3 | 4669 | case NEON_3R_VMAX: |
9ee6e8bb PB |
4670 | GEN_NEON_INTEGER_OP(max); |
4671 | break; | |
62698be3 | 4672 | case NEON_3R_VMIN: |
9ee6e8bb PB |
4673 | GEN_NEON_INTEGER_OP(min); |
4674 | break; | |
62698be3 | 4675 | case NEON_3R_VABD: |
9ee6e8bb PB |
4676 | GEN_NEON_INTEGER_OP(abd); |
4677 | break; | |
62698be3 | 4678 | case NEON_3R_VABA: |
9ee6e8bb | 4679 | GEN_NEON_INTEGER_OP(abd); |
7d1b0095 | 4680 | tcg_temp_free_i32(tmp2); |
dd8fbd78 FN |
4681 | tmp2 = neon_load_reg(rd, pass); |
4682 | gen_neon_add(size, tmp, tmp2); | |
9ee6e8bb | 4683 | break; |
62698be3 | 4684 | case NEON_3R_VADD_VSUB: |
9ee6e8bb | 4685 | if (!u) { /* VADD */ |
62698be3 | 4686 | gen_neon_add(size, tmp, tmp2); |
9ee6e8bb PB |
4687 | } else { /* VSUB */ |
4688 | switch (size) { | |
dd8fbd78 FN |
4689 | case 0: gen_helper_neon_sub_u8(tmp, tmp, tmp2); break; |
4690 | case 1: gen_helper_neon_sub_u16(tmp, tmp, tmp2); break; | |
4691 | case 2: tcg_gen_sub_i32(tmp, tmp, tmp2); break; | |
62698be3 | 4692 | default: abort(); |
9ee6e8bb PB |
4693 | } |
4694 | } | |
4695 | break; | |
62698be3 | 4696 | case NEON_3R_VTST_VCEQ: |
9ee6e8bb PB |
4697 | if (!u) { /* VTST */ |
4698 | switch (size) { | |
dd8fbd78 FN |
4699 | case 0: gen_helper_neon_tst_u8(tmp, tmp, tmp2); break; |
4700 | case 1: gen_helper_neon_tst_u16(tmp, tmp, tmp2); break; | |
4701 | case 2: gen_helper_neon_tst_u32(tmp, tmp, tmp2); break; | |
62698be3 | 4702 | default: abort(); |
9ee6e8bb PB |
4703 | } |
4704 | } else { /* VCEQ */ | |
4705 | switch (size) { | |
dd8fbd78 FN |
4706 | case 0: gen_helper_neon_ceq_u8(tmp, tmp, tmp2); break; |
4707 | case 1: gen_helper_neon_ceq_u16(tmp, tmp, tmp2); break; | |
4708 | case 2: gen_helper_neon_ceq_u32(tmp, tmp, tmp2); break; | |
62698be3 | 4709 | default: abort(); |
9ee6e8bb PB |
4710 | } |
4711 | } | |
4712 | break; | |
62698be3 | 4713 | case NEON_3R_VML: /* VMLA, VMLAL, VMLS,VMLSL */ |
9ee6e8bb | 4714 | switch (size) { |
dd8fbd78 FN |
4715 | case 0: gen_helper_neon_mul_u8(tmp, tmp, tmp2); break; |
4716 | case 1: gen_helper_neon_mul_u16(tmp, tmp, tmp2); break; | |
4717 | case 2: tcg_gen_mul_i32(tmp, tmp, tmp2); break; | |
62698be3 | 4718 | default: abort(); |
9ee6e8bb | 4719 | } |
7d1b0095 | 4720 | tcg_temp_free_i32(tmp2); |
dd8fbd78 | 4721 | tmp2 = neon_load_reg(rd, pass); |
9ee6e8bb | 4722 | if (u) { /* VMLS */ |
dd8fbd78 | 4723 | gen_neon_rsb(size, tmp, tmp2); |
9ee6e8bb | 4724 | } else { /* VMLA */ |
dd8fbd78 | 4725 | gen_neon_add(size, tmp, tmp2); |
9ee6e8bb PB |
4726 | } |
4727 | break; | |
62698be3 | 4728 | case NEON_3R_VMUL: |
9ee6e8bb | 4729 | if (u) { /* polynomial */ |
dd8fbd78 | 4730 | gen_helper_neon_mul_p8(tmp, tmp, tmp2); |
9ee6e8bb PB |
4731 | } else { /* Integer */ |
4732 | switch (size) { | |
dd8fbd78 FN |
4733 | case 0: gen_helper_neon_mul_u8(tmp, tmp, tmp2); break; |
4734 | case 1: gen_helper_neon_mul_u16(tmp, tmp, tmp2); break; | |
4735 | case 2: tcg_gen_mul_i32(tmp, tmp, tmp2); break; | |
62698be3 | 4736 | default: abort(); |
9ee6e8bb PB |
4737 | } |
4738 | } | |
4739 | break; | |
62698be3 | 4740 | case NEON_3R_VPMAX: |
9ee6e8bb PB |
4741 | GEN_NEON_INTEGER_OP(pmax); |
4742 | break; | |
62698be3 | 4743 | case NEON_3R_VPMIN: |
9ee6e8bb PB |
4744 | GEN_NEON_INTEGER_OP(pmin); |
4745 | break; | |
62698be3 | 4746 | case NEON_3R_VQDMULH_VQRDMULH: /* Multiply high. */ |
9ee6e8bb PB |
4747 | if (!u) { /* VQDMULH */ |
4748 | switch (size) { | |
2a3f75b4 PM |
4749 | case 1: gen_helper_neon_qdmulh_s16(tmp, tmp, tmp2); break; |
4750 | case 2: gen_helper_neon_qdmulh_s32(tmp, tmp, tmp2); break; | |
62698be3 | 4751 | default: abort(); |
9ee6e8bb | 4752 | } |
62698be3 | 4753 | } else { /* VQRDMULH */ |
9ee6e8bb | 4754 | switch (size) { |
2a3f75b4 PM |
4755 | case 1: gen_helper_neon_qrdmulh_s16(tmp, tmp, tmp2); break; |
4756 | case 2: gen_helper_neon_qrdmulh_s32(tmp, tmp, tmp2); break; | |
62698be3 | 4757 | default: abort(); |
9ee6e8bb PB |
4758 | } |
4759 | } | |
4760 | break; | |
62698be3 | 4761 | case NEON_3R_VPADD: |
9ee6e8bb | 4762 | switch (size) { |
dd8fbd78 FN |
4763 | case 0: gen_helper_neon_padd_u8(tmp, tmp, tmp2); break; |
4764 | case 1: gen_helper_neon_padd_u16(tmp, tmp, tmp2); break; | |
4765 | case 2: tcg_gen_add_i32(tmp, tmp, tmp2); break; | |
62698be3 | 4766 | default: abort(); |
9ee6e8bb PB |
4767 | } |
4768 | break; | |
62698be3 | 4769 | case NEON_3R_FLOAT_ARITH: /* Floating point arithmetic. */ |
9ee6e8bb PB |
4770 | switch ((u << 2) | size) { |
4771 | case 0: /* VADD */ | |
dd8fbd78 | 4772 | gen_helper_neon_add_f32(tmp, tmp, tmp2); |
9ee6e8bb PB |
4773 | break; |
4774 | case 2: /* VSUB */ | |
dd8fbd78 | 4775 | gen_helper_neon_sub_f32(tmp, tmp, tmp2); |
9ee6e8bb PB |
4776 | break; |
4777 | case 4: /* VPADD */ | |
dd8fbd78 | 4778 | gen_helper_neon_add_f32(tmp, tmp, tmp2); |
9ee6e8bb PB |
4779 | break; |
4780 | case 6: /* VABD */ | |
dd8fbd78 | 4781 | gen_helper_neon_abd_f32(tmp, tmp, tmp2); |
9ee6e8bb PB |
4782 | break; |
4783 | default: | |
62698be3 | 4784 | abort(); |
9ee6e8bb PB |
4785 | } |
4786 | break; | |
62698be3 | 4787 | case NEON_3R_FLOAT_MULTIPLY: |
dd8fbd78 | 4788 | gen_helper_neon_mul_f32(tmp, tmp, tmp2); |
9ee6e8bb | 4789 | if (!u) { |
7d1b0095 | 4790 | tcg_temp_free_i32(tmp2); |
dd8fbd78 | 4791 | tmp2 = neon_load_reg(rd, pass); |
9ee6e8bb | 4792 | if (size == 0) { |
dd8fbd78 | 4793 | gen_helper_neon_add_f32(tmp, tmp, tmp2); |
9ee6e8bb | 4794 | } else { |
dd8fbd78 | 4795 | gen_helper_neon_sub_f32(tmp, tmp2, tmp); |
9ee6e8bb PB |
4796 | } |
4797 | } | |
4798 | break; | |
62698be3 | 4799 | case NEON_3R_FLOAT_CMP: |
9ee6e8bb | 4800 | if (!u) { |
dd8fbd78 | 4801 | gen_helper_neon_ceq_f32(tmp, tmp, tmp2); |
b5ff1b31 | 4802 | } else { |
9ee6e8bb | 4803 | if (size == 0) |
dd8fbd78 | 4804 | gen_helper_neon_cge_f32(tmp, tmp, tmp2); |
9ee6e8bb | 4805 | else |
dd8fbd78 | 4806 | gen_helper_neon_cgt_f32(tmp, tmp, tmp2); |
b5ff1b31 | 4807 | } |
2c0262af | 4808 | break; |
62698be3 | 4809 | case NEON_3R_FLOAT_ACMP: |
9ee6e8bb | 4810 | if (size == 0) |
dd8fbd78 | 4811 | gen_helper_neon_acge_f32(tmp, tmp, tmp2); |
9ee6e8bb | 4812 | else |
dd8fbd78 | 4813 | gen_helper_neon_acgt_f32(tmp, tmp, tmp2); |
2c0262af | 4814 | break; |
62698be3 | 4815 | case NEON_3R_FLOAT_MINMAX: |
9ee6e8bb | 4816 | if (size == 0) |
dd8fbd78 | 4817 | gen_helper_neon_max_f32(tmp, tmp, tmp2); |
9ee6e8bb | 4818 | else |
dd8fbd78 | 4819 | gen_helper_neon_min_f32(tmp, tmp, tmp2); |
9ee6e8bb | 4820 | break; |
62698be3 | 4821 | case NEON_3R_VRECPS_VRSQRTS: |
9ee6e8bb | 4822 | if (size == 0) |
dd8fbd78 | 4823 | gen_helper_recps_f32(tmp, tmp, tmp2, cpu_env); |
9ee6e8bb | 4824 | else |
dd8fbd78 | 4825 | gen_helper_rsqrts_f32(tmp, tmp, tmp2, cpu_env); |
2c0262af | 4826 | break; |
9ee6e8bb PB |
4827 | default: |
4828 | abort(); | |
2c0262af | 4829 | } |
7d1b0095 | 4830 | tcg_temp_free_i32(tmp2); |
dd8fbd78 | 4831 | |
9ee6e8bb PB |
4832 | /* Save the result. For elementwise operations we can put it |
4833 | straight into the destination register. For pairwise operations | |
4834 | we have to be careful to avoid clobbering the source operands. */ | |
4835 | if (pairwise && rd == rm) { | |
dd8fbd78 | 4836 | neon_store_scratch(pass, tmp); |
9ee6e8bb | 4837 | } else { |
dd8fbd78 | 4838 | neon_store_reg(rd, pass, tmp); |
9ee6e8bb PB |
4839 | } |
4840 | ||
4841 | } /* for pass */ | |
4842 | if (pairwise && rd == rm) { | |
4843 | for (pass = 0; pass < (q ? 4 : 2); pass++) { | |
dd8fbd78 FN |
4844 | tmp = neon_load_scratch(pass); |
4845 | neon_store_reg(rd, pass, tmp); | |
9ee6e8bb PB |
4846 | } |
4847 | } | |
ad69471c | 4848 | /* End of 3 register same size operations. */ |
9ee6e8bb PB |
4849 | } else if (insn & (1 << 4)) { |
4850 | if ((insn & 0x00380080) != 0) { | |
4851 | /* Two registers and shift. */ | |
4852 | op = (insn >> 8) & 0xf; | |
4853 | if (insn & (1 << 7)) { | |
cc13115b PM |
4854 | /* 64-bit shift. */ |
4855 | if (op > 7) { | |
4856 | return 1; | |
4857 | } | |
9ee6e8bb PB |
4858 | size = 3; |
4859 | } else { | |
4860 | size = 2; | |
4861 | while ((insn & (1 << (size + 19))) == 0) | |
4862 | size--; | |
4863 | } | |
4864 | shift = (insn >> 16) & ((1 << (3 + size)) - 1); | |
4865 | /* To avoid excessive dumplication of ops we implement shift | |
4866 | by immediate using the variable shift operations. */ | |
4867 | if (op < 8) { | |
4868 | /* Shift by immediate: | |
4869 | VSHR, VSRA, VRSHR, VRSRA, VSRI, VSHL, VQSHL, VQSHLU. */ | |
cc13115b PM |
4870 | if (q && ((rd | rm) & 1)) { |
4871 | return 1; | |
4872 | } | |
4873 | if (!u && (op == 4 || op == 6)) { | |
4874 | return 1; | |
4875 | } | |
9ee6e8bb PB |
4876 | /* Right shifts are encoded as N - shift, where N is the |
4877 | element size in bits. */ | |
4878 | if (op <= 4) | |
4879 | shift = shift - (1 << (size + 3)); | |
9ee6e8bb PB |
4880 | if (size == 3) { |
4881 | count = q + 1; | |
4882 | } else { | |
4883 | count = q ? 4: 2; | |
4884 | } | |
4885 | switch (size) { | |
4886 | case 0: | |
4887 | imm = (uint8_t) shift; | |
4888 | imm |= imm << 8; | |
4889 | imm |= imm << 16; | |
4890 | break; | |
4891 | case 1: | |
4892 | imm = (uint16_t) shift; | |
4893 | imm |= imm << 16; | |
4894 | break; | |
4895 | case 2: | |
4896 | case 3: | |
4897 | imm = shift; | |
4898 | break; | |
4899 | default: | |
4900 | abort(); | |
4901 | } | |
4902 | ||
4903 | for (pass = 0; pass < count; pass++) { | |
ad69471c PB |
4904 | if (size == 3) { |
4905 | neon_load_reg64(cpu_V0, rm + pass); | |
4906 | tcg_gen_movi_i64(cpu_V1, imm); | |
4907 | switch (op) { | |
4908 | case 0: /* VSHR */ | |
4909 | case 1: /* VSRA */ | |
4910 | if (u) | |
4911 | gen_helper_neon_shl_u64(cpu_V0, cpu_V0, cpu_V1); | |
9ee6e8bb | 4912 | else |
ad69471c | 4913 | gen_helper_neon_shl_s64(cpu_V0, cpu_V0, cpu_V1); |
9ee6e8bb | 4914 | break; |
ad69471c PB |
4915 | case 2: /* VRSHR */ |
4916 | case 3: /* VRSRA */ | |
4917 | if (u) | |
4918 | gen_helper_neon_rshl_u64(cpu_V0, cpu_V0, cpu_V1); | |
9ee6e8bb | 4919 | else |
ad69471c | 4920 | gen_helper_neon_rshl_s64(cpu_V0, cpu_V0, cpu_V1); |
9ee6e8bb | 4921 | break; |
ad69471c | 4922 | case 4: /* VSRI */ |
ad69471c PB |
4923 | case 5: /* VSHL, VSLI */ |
4924 | gen_helper_neon_shl_u64(cpu_V0, cpu_V0, cpu_V1); | |
4925 | break; | |
0322b26e | 4926 | case 6: /* VQSHLU */ |
cc13115b | 4927 | gen_helper_neon_qshlu_s64(cpu_V0, cpu_V0, cpu_V1); |
ad69471c | 4928 | break; |
0322b26e PM |
4929 | case 7: /* VQSHL */ |
4930 | if (u) { | |
2a3f75b4 | 4931 | gen_helper_neon_qshl_u64(cpu_V0, |
0322b26e PM |
4932 | cpu_V0, cpu_V1); |
4933 | } else { | |
2a3f75b4 | 4934 | gen_helper_neon_qshl_s64(cpu_V0, |
0322b26e PM |
4935 | cpu_V0, cpu_V1); |
4936 | } | |
9ee6e8bb | 4937 | break; |
9ee6e8bb | 4938 | } |
ad69471c PB |
4939 | if (op == 1 || op == 3) { |
4940 | /* Accumulate. */ | |
5371cb81 | 4941 | neon_load_reg64(cpu_V1, rd + pass); |
ad69471c PB |
4942 | tcg_gen_add_i64(cpu_V0, cpu_V0, cpu_V1); |
4943 | } else if (op == 4 || (op == 5 && u)) { | |
4944 | /* Insert */ | |
923e6509 CL |
4945 | neon_load_reg64(cpu_V1, rd + pass); |
4946 | uint64_t mask; | |
4947 | if (shift < -63 || shift > 63) { | |
4948 | mask = 0; | |
4949 | } else { | |
4950 | if (op == 4) { | |
4951 | mask = 0xffffffffffffffffull >> -shift; | |
4952 | } else { | |
4953 | mask = 0xffffffffffffffffull << shift; | |
4954 | } | |
4955 | } | |
4956 | tcg_gen_andi_i64(cpu_V1, cpu_V1, ~mask); | |
4957 | tcg_gen_or_i64(cpu_V0, cpu_V0, cpu_V1); | |
ad69471c PB |
4958 | } |
4959 | neon_store_reg64(cpu_V0, rd + pass); | |
4960 | } else { /* size < 3 */ | |
4961 | /* Operands in T0 and T1. */ | |
dd8fbd78 | 4962 | tmp = neon_load_reg(rm, pass); |
7d1b0095 | 4963 | tmp2 = tcg_temp_new_i32(); |
dd8fbd78 | 4964 | tcg_gen_movi_i32(tmp2, imm); |
ad69471c PB |
4965 | switch (op) { |
4966 | case 0: /* VSHR */ | |
4967 | case 1: /* VSRA */ | |
4968 | GEN_NEON_INTEGER_OP(shl); | |
4969 | break; | |
4970 | case 2: /* VRSHR */ | |
4971 | case 3: /* VRSRA */ | |
4972 | GEN_NEON_INTEGER_OP(rshl); | |
4973 | break; | |
4974 | case 4: /* VSRI */ | |
ad69471c PB |
4975 | case 5: /* VSHL, VSLI */ |
4976 | switch (size) { | |
dd8fbd78 FN |
4977 | case 0: gen_helper_neon_shl_u8(tmp, tmp, tmp2); break; |
4978 | case 1: gen_helper_neon_shl_u16(tmp, tmp, tmp2); break; | |
4979 | case 2: gen_helper_neon_shl_u32(tmp, tmp, tmp2); break; | |
cc13115b | 4980 | default: abort(); |
ad69471c PB |
4981 | } |
4982 | break; | |
0322b26e | 4983 | case 6: /* VQSHLU */ |
ad69471c | 4984 | switch (size) { |
0322b26e | 4985 | case 0: |
2a3f75b4 | 4986 | gen_helper_neon_qshlu_s8(tmp, tmp, tmp2); |
0322b26e PM |
4987 | break; |
4988 | case 1: | |
2a3f75b4 | 4989 | gen_helper_neon_qshlu_s16(tmp, tmp, tmp2); |
0322b26e PM |
4990 | break; |
4991 | case 2: | |
2a3f75b4 | 4992 | gen_helper_neon_qshlu_s32(tmp, tmp, tmp2); |
0322b26e PM |
4993 | break; |
4994 | default: | |
cc13115b | 4995 | abort(); |
ad69471c PB |
4996 | } |
4997 | break; | |
0322b26e | 4998 | case 7: /* VQSHL */ |
2a3f75b4 | 4999 | GEN_NEON_INTEGER_OP(qshl); |
0322b26e | 5000 | break; |
ad69471c | 5001 | } |
7d1b0095 | 5002 | tcg_temp_free_i32(tmp2); |
ad69471c PB |
5003 | |
5004 | if (op == 1 || op == 3) { | |
5005 | /* Accumulate. */ | |
dd8fbd78 | 5006 | tmp2 = neon_load_reg(rd, pass); |
5371cb81 | 5007 | gen_neon_add(size, tmp, tmp2); |
7d1b0095 | 5008 | tcg_temp_free_i32(tmp2); |
ad69471c PB |
5009 | } else if (op == 4 || (op == 5 && u)) { |
5010 | /* Insert */ | |
5011 | switch (size) { | |
5012 | case 0: | |
5013 | if (op == 4) | |
ca9a32e4 | 5014 | mask = 0xff >> -shift; |
ad69471c | 5015 | else |
ca9a32e4 JR |
5016 | mask = (uint8_t)(0xff << shift); |
5017 | mask |= mask << 8; | |
5018 | mask |= mask << 16; | |
ad69471c PB |
5019 | break; |
5020 | case 1: | |
5021 | if (op == 4) | |
ca9a32e4 | 5022 | mask = 0xffff >> -shift; |
ad69471c | 5023 | else |
ca9a32e4 JR |
5024 | mask = (uint16_t)(0xffff << shift); |
5025 | mask |= mask << 16; | |
ad69471c PB |
5026 | break; |
5027 | case 2: | |
ca9a32e4 JR |
5028 | if (shift < -31 || shift > 31) { |
5029 | mask = 0; | |
5030 | } else { | |
5031 | if (op == 4) | |
5032 | mask = 0xffffffffu >> -shift; | |
5033 | else | |
5034 | mask = 0xffffffffu << shift; | |
5035 | } | |
ad69471c PB |
5036 | break; |
5037 | default: | |
5038 | abort(); | |
5039 | } | |
dd8fbd78 | 5040 | tmp2 = neon_load_reg(rd, pass); |
ca9a32e4 JR |
5041 | tcg_gen_andi_i32(tmp, tmp, mask); |
5042 | tcg_gen_andi_i32(tmp2, tmp2, ~mask); | |
dd8fbd78 | 5043 | tcg_gen_or_i32(tmp, tmp, tmp2); |
7d1b0095 | 5044 | tcg_temp_free_i32(tmp2); |
ad69471c | 5045 | } |
dd8fbd78 | 5046 | neon_store_reg(rd, pass, tmp); |
9ee6e8bb PB |
5047 | } |
5048 | } /* for pass */ | |
5049 | } else if (op < 10) { | |
ad69471c | 5050 | /* Shift by immediate and narrow: |
9ee6e8bb | 5051 | VSHRN, VRSHRN, VQSHRN, VQRSHRN. */ |
0b36f4cd | 5052 | int input_unsigned = (op == 8) ? !u : u; |
cc13115b PM |
5053 | if (rm & 1) { |
5054 | return 1; | |
5055 | } | |
9ee6e8bb PB |
5056 | shift = shift - (1 << (size + 3)); |
5057 | size++; | |
92cdfaeb | 5058 | if (size == 3) { |
a7812ae4 | 5059 | tmp64 = tcg_const_i64(shift); |
92cdfaeb PM |
5060 | neon_load_reg64(cpu_V0, rm); |
5061 | neon_load_reg64(cpu_V1, rm + 1); | |
5062 | for (pass = 0; pass < 2; pass++) { | |
5063 | TCGv_i64 in; | |
5064 | if (pass == 0) { | |
5065 | in = cpu_V0; | |
5066 | } else { | |
5067 | in = cpu_V1; | |
5068 | } | |
ad69471c | 5069 | if (q) { |
0b36f4cd | 5070 | if (input_unsigned) { |
92cdfaeb | 5071 | gen_helper_neon_rshl_u64(cpu_V0, in, tmp64); |
0b36f4cd | 5072 | } else { |
92cdfaeb | 5073 | gen_helper_neon_rshl_s64(cpu_V0, in, tmp64); |
0b36f4cd | 5074 | } |
ad69471c | 5075 | } else { |
0b36f4cd | 5076 | if (input_unsigned) { |
92cdfaeb | 5077 | gen_helper_neon_shl_u64(cpu_V0, in, tmp64); |
0b36f4cd | 5078 | } else { |
92cdfaeb | 5079 | gen_helper_neon_shl_s64(cpu_V0, in, tmp64); |
0b36f4cd | 5080 | } |
ad69471c | 5081 | } |
7d1b0095 | 5082 | tmp = tcg_temp_new_i32(); |
92cdfaeb PM |
5083 | gen_neon_narrow_op(op == 8, u, size - 1, tmp, cpu_V0); |
5084 | neon_store_reg(rd, pass, tmp); | |
5085 | } /* for pass */ | |
5086 | tcg_temp_free_i64(tmp64); | |
5087 | } else { | |
5088 | if (size == 1) { | |
5089 | imm = (uint16_t)shift; | |
5090 | imm |= imm << 16; | |
2c0262af | 5091 | } else { |
92cdfaeb PM |
5092 | /* size == 2 */ |
5093 | imm = (uint32_t)shift; | |
5094 | } | |
5095 | tmp2 = tcg_const_i32(imm); | |
5096 | tmp4 = neon_load_reg(rm + 1, 0); | |
5097 | tmp5 = neon_load_reg(rm + 1, 1); | |
5098 | for (pass = 0; pass < 2; pass++) { | |
5099 | if (pass == 0) { | |
5100 | tmp = neon_load_reg(rm, 0); | |
5101 | } else { | |
5102 | tmp = tmp4; | |
5103 | } | |
0b36f4cd CL |
5104 | gen_neon_shift_narrow(size, tmp, tmp2, q, |
5105 | input_unsigned); | |
92cdfaeb PM |
5106 | if (pass == 0) { |
5107 | tmp3 = neon_load_reg(rm, 1); | |
5108 | } else { | |
5109 | tmp3 = tmp5; | |
5110 | } | |
0b36f4cd CL |
5111 | gen_neon_shift_narrow(size, tmp3, tmp2, q, |
5112 | input_unsigned); | |
36aa55dc | 5113 | tcg_gen_concat_i32_i64(cpu_V0, tmp, tmp3); |
7d1b0095 PM |
5114 | tcg_temp_free_i32(tmp); |
5115 | tcg_temp_free_i32(tmp3); | |
5116 | tmp = tcg_temp_new_i32(); | |
92cdfaeb PM |
5117 | gen_neon_narrow_op(op == 8, u, size - 1, tmp, cpu_V0); |
5118 | neon_store_reg(rd, pass, tmp); | |
5119 | } /* for pass */ | |
c6067f04 | 5120 | tcg_temp_free_i32(tmp2); |
b75263d6 | 5121 | } |
9ee6e8bb | 5122 | } else if (op == 10) { |
cc13115b PM |
5123 | /* VSHLL, VMOVL */ |
5124 | if (q || (rd & 1)) { | |
9ee6e8bb | 5125 | return 1; |
cc13115b | 5126 | } |
ad69471c PB |
5127 | tmp = neon_load_reg(rm, 0); |
5128 | tmp2 = neon_load_reg(rm, 1); | |
9ee6e8bb | 5129 | for (pass = 0; pass < 2; pass++) { |
ad69471c PB |
5130 | if (pass == 1) |
5131 | tmp = tmp2; | |
5132 | ||
5133 | gen_neon_widen(cpu_V0, tmp, size, u); | |
9ee6e8bb | 5134 | |
9ee6e8bb PB |
5135 | if (shift != 0) { |
5136 | /* The shift is less than the width of the source | |
ad69471c PB |
5137 | type, so we can just shift the whole register. */ |
5138 | tcg_gen_shli_i64(cpu_V0, cpu_V0, shift); | |
acdf01ef CL |
5139 | /* Widen the result of shift: we need to clear |
5140 | * the potential overflow bits resulting from | |
5141 | * left bits of the narrow input appearing as | |
5142 | * right bits of left the neighbour narrow | |
5143 | * input. */ | |
ad69471c PB |
5144 | if (size < 2 || !u) { |
5145 | uint64_t imm64; | |
5146 | if (size == 0) { | |
5147 | imm = (0xffu >> (8 - shift)); | |
5148 | imm |= imm << 16; | |
acdf01ef | 5149 | } else if (size == 1) { |
ad69471c | 5150 | imm = 0xffff >> (16 - shift); |
acdf01ef CL |
5151 | } else { |
5152 | /* size == 2 */ | |
5153 | imm = 0xffffffff >> (32 - shift); | |
5154 | } | |
5155 | if (size < 2) { | |
5156 | imm64 = imm | (((uint64_t)imm) << 32); | |
5157 | } else { | |
5158 | imm64 = imm; | |
9ee6e8bb | 5159 | } |
acdf01ef | 5160 | tcg_gen_andi_i64(cpu_V0, cpu_V0, ~imm64); |
9ee6e8bb PB |
5161 | } |
5162 | } | |
ad69471c | 5163 | neon_store_reg64(cpu_V0, rd + pass); |
9ee6e8bb | 5164 | } |
f73534a5 | 5165 | } else if (op >= 14) { |
9ee6e8bb | 5166 | /* VCVT fixed-point. */ |
cc13115b PM |
5167 | if (!(insn & (1 << 21)) || (q && ((rd | rm) & 1))) { |
5168 | return 1; | |
5169 | } | |
f73534a5 PM |
5170 | /* We have already masked out the must-be-1 top bit of imm6, |
5171 | * hence this 32-shift where the ARM ARM has 64-imm6. | |
5172 | */ | |
5173 | shift = 32 - shift; | |
9ee6e8bb | 5174 | for (pass = 0; pass < (q ? 4 : 2); pass++) { |
4373f3ce | 5175 | tcg_gen_ld_f32(cpu_F0s, cpu_env, neon_reg_offset(rm, pass)); |
f73534a5 | 5176 | if (!(op & 1)) { |
9ee6e8bb | 5177 | if (u) |
4373f3ce | 5178 | gen_vfp_ulto(0, shift); |
9ee6e8bb | 5179 | else |
4373f3ce | 5180 | gen_vfp_slto(0, shift); |
9ee6e8bb PB |
5181 | } else { |
5182 | if (u) | |
4373f3ce | 5183 | gen_vfp_toul(0, shift); |
9ee6e8bb | 5184 | else |
4373f3ce | 5185 | gen_vfp_tosl(0, shift); |
2c0262af | 5186 | } |
4373f3ce | 5187 | tcg_gen_st_f32(cpu_F0s, cpu_env, neon_reg_offset(rd, pass)); |
2c0262af FB |
5188 | } |
5189 | } else { | |
9ee6e8bb PB |
5190 | return 1; |
5191 | } | |
5192 | } else { /* (insn & 0x00380080) == 0 */ | |
5193 | int invert; | |
7d80fee5 PM |
5194 | if (q && (rd & 1)) { |
5195 | return 1; | |
5196 | } | |
9ee6e8bb PB |
5197 | |
5198 | op = (insn >> 8) & 0xf; | |
5199 | /* One register and immediate. */ | |
5200 | imm = (u << 7) | ((insn >> 12) & 0x70) | (insn & 0xf); | |
5201 | invert = (insn & (1 << 5)) != 0; | |
7d80fee5 PM |
5202 | /* Note that op = 2,3,4,5,6,7,10,11,12,13 imm=0 is UNPREDICTABLE. |
5203 | * We choose to not special-case this and will behave as if a | |
5204 | * valid constant encoding of 0 had been given. | |
5205 | */ | |
9ee6e8bb PB |
5206 | switch (op) { |
5207 | case 0: case 1: | |
5208 | /* no-op */ | |
5209 | break; | |
5210 | case 2: case 3: | |
5211 | imm <<= 8; | |
5212 | break; | |
5213 | case 4: case 5: | |
5214 | imm <<= 16; | |
5215 | break; | |
5216 | case 6: case 7: | |
5217 | imm <<= 24; | |
5218 | break; | |
5219 | case 8: case 9: | |
5220 | imm |= imm << 16; | |
5221 | break; | |
5222 | case 10: case 11: | |
5223 | imm = (imm << 8) | (imm << 24); | |
5224 | break; | |
5225 | case 12: | |
8e31209e | 5226 | imm = (imm << 8) | 0xff; |
9ee6e8bb PB |
5227 | break; |
5228 | case 13: | |
5229 | imm = (imm << 16) | 0xffff; | |
5230 | break; | |
5231 | case 14: | |
5232 | imm |= (imm << 8) | (imm << 16) | (imm << 24); | |
5233 | if (invert) | |
5234 | imm = ~imm; | |
5235 | break; | |
5236 | case 15: | |
7d80fee5 PM |
5237 | if (invert) { |
5238 | return 1; | |
5239 | } | |
9ee6e8bb PB |
5240 | imm = ((imm & 0x80) << 24) | ((imm & 0x3f) << 19) |
5241 | | ((imm & 0x40) ? (0x1f << 25) : (1 << 30)); | |
5242 | break; | |
5243 | } | |
5244 | if (invert) | |
5245 | imm = ~imm; | |
5246 | ||
9ee6e8bb PB |
5247 | for (pass = 0; pass < (q ? 4 : 2); pass++) { |
5248 | if (op & 1 && op < 12) { | |
ad69471c | 5249 | tmp = neon_load_reg(rd, pass); |
9ee6e8bb PB |
5250 | if (invert) { |
5251 | /* The immediate value has already been inverted, so | |
5252 | BIC becomes AND. */ | |
ad69471c | 5253 | tcg_gen_andi_i32(tmp, tmp, imm); |
9ee6e8bb | 5254 | } else { |
ad69471c | 5255 | tcg_gen_ori_i32(tmp, tmp, imm); |
9ee6e8bb | 5256 | } |
9ee6e8bb | 5257 | } else { |
ad69471c | 5258 | /* VMOV, VMVN. */ |
7d1b0095 | 5259 | tmp = tcg_temp_new_i32(); |
9ee6e8bb | 5260 | if (op == 14 && invert) { |
a5a14945 | 5261 | int n; |
ad69471c PB |
5262 | uint32_t val; |
5263 | val = 0; | |
9ee6e8bb PB |
5264 | for (n = 0; n < 4; n++) { |
5265 | if (imm & (1 << (n + (pass & 1) * 4))) | |
ad69471c | 5266 | val |= 0xff << (n * 8); |
9ee6e8bb | 5267 | } |
ad69471c PB |
5268 | tcg_gen_movi_i32(tmp, val); |
5269 | } else { | |
5270 | tcg_gen_movi_i32(tmp, imm); | |
9ee6e8bb | 5271 | } |
9ee6e8bb | 5272 | } |
ad69471c | 5273 | neon_store_reg(rd, pass, tmp); |
9ee6e8bb PB |
5274 | } |
5275 | } | |
e4b3861d | 5276 | } else { /* (insn & 0x00800010 == 0x00800000) */ |
9ee6e8bb PB |
5277 | if (size != 3) { |
5278 | op = (insn >> 8) & 0xf; | |
5279 | if ((insn & (1 << 6)) == 0) { | |
5280 | /* Three registers of different lengths. */ | |
5281 | int src1_wide; | |
5282 | int src2_wide; | |
5283 | int prewiden; | |
695272dc PM |
5284 | /* undefreq: bit 0 : UNDEF if size != 0 |
5285 | * bit 1 : UNDEF if size == 0 | |
5286 | * bit 2 : UNDEF if U == 1 | |
5287 | * Note that [1:0] set implies 'always UNDEF' | |
5288 | */ | |
5289 | int undefreq; | |
5290 | /* prewiden, src1_wide, src2_wide, undefreq */ | |
5291 | static const int neon_3reg_wide[16][4] = { | |
5292 | {1, 0, 0, 0}, /* VADDL */ | |
5293 | {1, 1, 0, 0}, /* VADDW */ | |
5294 | {1, 0, 0, 0}, /* VSUBL */ | |
5295 | {1, 1, 0, 0}, /* VSUBW */ | |
5296 | {0, 1, 1, 0}, /* VADDHN */ | |
5297 | {0, 0, 0, 0}, /* VABAL */ | |
5298 | {0, 1, 1, 0}, /* VSUBHN */ | |
5299 | {0, 0, 0, 0}, /* VABDL */ | |
5300 | {0, 0, 0, 0}, /* VMLAL */ | |
5301 | {0, 0, 0, 6}, /* VQDMLAL */ | |
5302 | {0, 0, 0, 0}, /* VMLSL */ | |
5303 | {0, 0, 0, 6}, /* VQDMLSL */ | |
5304 | {0, 0, 0, 0}, /* Integer VMULL */ | |
5305 | {0, 0, 0, 2}, /* VQDMULL */ | |
5306 | {0, 0, 0, 5}, /* Polynomial VMULL */ | |
5307 | {0, 0, 0, 3}, /* Reserved: always UNDEF */ | |
9ee6e8bb PB |
5308 | }; |
5309 | ||
5310 | prewiden = neon_3reg_wide[op][0]; | |
5311 | src1_wide = neon_3reg_wide[op][1]; | |
5312 | src2_wide = neon_3reg_wide[op][2]; | |
695272dc | 5313 | undefreq = neon_3reg_wide[op][3]; |
9ee6e8bb | 5314 | |
695272dc PM |
5315 | if (((undefreq & 1) && (size != 0)) || |
5316 | ((undefreq & 2) && (size == 0)) || | |
5317 | ((undefreq & 4) && u)) { | |
5318 | return 1; | |
5319 | } | |
5320 | if ((src1_wide && (rn & 1)) || | |
5321 | (src2_wide && (rm & 1)) || | |
5322 | (!src2_wide && (rd & 1))) { | |
ad69471c | 5323 | return 1; |
695272dc | 5324 | } |
ad69471c | 5325 | |
9ee6e8bb PB |
5326 | /* Avoid overlapping operands. Wide source operands are |
5327 | always aligned so will never overlap with wide | |
5328 | destinations in problematic ways. */ | |
8f8e3aa4 | 5329 | if (rd == rm && !src2_wide) { |
dd8fbd78 FN |
5330 | tmp = neon_load_reg(rm, 1); |
5331 | neon_store_scratch(2, tmp); | |
8f8e3aa4 | 5332 | } else if (rd == rn && !src1_wide) { |
dd8fbd78 FN |
5333 | tmp = neon_load_reg(rn, 1); |
5334 | neon_store_scratch(2, tmp); | |
9ee6e8bb | 5335 | } |
a50f5b91 | 5336 | TCGV_UNUSED(tmp3); |
9ee6e8bb | 5337 | for (pass = 0; pass < 2; pass++) { |
ad69471c PB |
5338 | if (src1_wide) { |
5339 | neon_load_reg64(cpu_V0, rn + pass); | |
a50f5b91 | 5340 | TCGV_UNUSED(tmp); |
9ee6e8bb | 5341 | } else { |
ad69471c | 5342 | if (pass == 1 && rd == rn) { |
dd8fbd78 | 5343 | tmp = neon_load_scratch(2); |
9ee6e8bb | 5344 | } else { |
ad69471c PB |
5345 | tmp = neon_load_reg(rn, pass); |
5346 | } | |
5347 | if (prewiden) { | |
5348 | gen_neon_widen(cpu_V0, tmp, size, u); | |
9ee6e8bb PB |
5349 | } |
5350 | } | |
ad69471c PB |
5351 | if (src2_wide) { |
5352 | neon_load_reg64(cpu_V1, rm + pass); | |
a50f5b91 | 5353 | TCGV_UNUSED(tmp2); |
9ee6e8bb | 5354 | } else { |
ad69471c | 5355 | if (pass == 1 && rd == rm) { |
dd8fbd78 | 5356 | tmp2 = neon_load_scratch(2); |
9ee6e8bb | 5357 | } else { |
ad69471c PB |
5358 | tmp2 = neon_load_reg(rm, pass); |
5359 | } | |
5360 | if (prewiden) { | |
5361 | gen_neon_widen(cpu_V1, tmp2, size, u); | |
9ee6e8bb | 5362 | } |
9ee6e8bb PB |
5363 | } |
5364 | switch (op) { | |
5365 | case 0: case 1: case 4: /* VADDL, VADDW, VADDHN, VRADDHN */ | |
ad69471c | 5366 | gen_neon_addl(size); |
9ee6e8bb | 5367 | break; |
79b0e534 | 5368 | case 2: case 3: case 6: /* VSUBL, VSUBW, VSUBHN, VRSUBHN */ |
ad69471c | 5369 | gen_neon_subl(size); |
9ee6e8bb PB |
5370 | break; |
5371 | case 5: case 7: /* VABAL, VABDL */ | |
5372 | switch ((size << 1) | u) { | |
ad69471c PB |
5373 | case 0: |
5374 | gen_helper_neon_abdl_s16(cpu_V0, tmp, tmp2); | |
5375 | break; | |
5376 | case 1: | |
5377 | gen_helper_neon_abdl_u16(cpu_V0, tmp, tmp2); | |
5378 | break; | |
5379 | case 2: | |
5380 | gen_helper_neon_abdl_s32(cpu_V0, tmp, tmp2); | |
5381 | break; | |
5382 | case 3: | |
5383 | gen_helper_neon_abdl_u32(cpu_V0, tmp, tmp2); | |
5384 | break; | |
5385 | case 4: | |
5386 | gen_helper_neon_abdl_s64(cpu_V0, tmp, tmp2); | |
5387 | break; | |
5388 | case 5: | |
5389 | gen_helper_neon_abdl_u64(cpu_V0, tmp, tmp2); | |
5390 | break; | |
9ee6e8bb PB |
5391 | default: abort(); |
5392 | } | |
7d1b0095 PM |
5393 | tcg_temp_free_i32(tmp2); |
5394 | tcg_temp_free_i32(tmp); | |
9ee6e8bb PB |
5395 | break; |
5396 | case 8: case 9: case 10: case 11: case 12: case 13: | |
5397 | /* VMLAL, VQDMLAL, VMLSL, VQDMLSL, VMULL, VQDMULL */ | |
ad69471c | 5398 | gen_neon_mull(cpu_V0, tmp, tmp2, size, u); |
9ee6e8bb PB |
5399 | break; |
5400 | case 14: /* Polynomial VMULL */ | |
e5ca24cb | 5401 | gen_helper_neon_mull_p8(cpu_V0, tmp, tmp2); |
7d1b0095 PM |
5402 | tcg_temp_free_i32(tmp2); |
5403 | tcg_temp_free_i32(tmp); | |
e5ca24cb | 5404 | break; |
695272dc PM |
5405 | default: /* 15 is RESERVED: caught earlier */ |
5406 | abort(); | |
9ee6e8bb | 5407 | } |
ebcd88ce PM |
5408 | if (op == 13) { |
5409 | /* VQDMULL */ | |
5410 | gen_neon_addl_saturate(cpu_V0, cpu_V0, size); | |
5411 | neon_store_reg64(cpu_V0, rd + pass); | |
5412 | } else if (op == 5 || (op >= 8 && op <= 11)) { | |
9ee6e8bb | 5413 | /* Accumulate. */ |
ebcd88ce | 5414 | neon_load_reg64(cpu_V1, rd + pass); |
9ee6e8bb | 5415 | switch (op) { |
4dc064e6 PM |
5416 | case 10: /* VMLSL */ |
5417 | gen_neon_negl(cpu_V0, size); | |
5418 | /* Fall through */ | |
5419 | case 5: case 8: /* VABAL, VMLAL */ | |
ad69471c | 5420 | gen_neon_addl(size); |
9ee6e8bb PB |
5421 | break; |
5422 | case 9: case 11: /* VQDMLAL, VQDMLSL */ | |
ad69471c | 5423 | gen_neon_addl_saturate(cpu_V0, cpu_V0, size); |
4dc064e6 PM |
5424 | if (op == 11) { |
5425 | gen_neon_negl(cpu_V0, size); | |
5426 | } | |
ad69471c PB |
5427 | gen_neon_addl_saturate(cpu_V0, cpu_V1, size); |
5428 | break; | |
9ee6e8bb PB |
5429 | default: |
5430 | abort(); | |
5431 | } | |
ad69471c | 5432 | neon_store_reg64(cpu_V0, rd + pass); |
9ee6e8bb PB |
5433 | } else if (op == 4 || op == 6) { |
5434 | /* Narrowing operation. */ | |
7d1b0095 | 5435 | tmp = tcg_temp_new_i32(); |
79b0e534 | 5436 | if (!u) { |
9ee6e8bb | 5437 | switch (size) { |
ad69471c PB |
5438 | case 0: |
5439 | gen_helper_neon_narrow_high_u8(tmp, cpu_V0); | |
5440 | break; | |
5441 | case 1: | |
5442 | gen_helper_neon_narrow_high_u16(tmp, cpu_V0); | |
5443 | break; | |
5444 | case 2: | |
5445 | tcg_gen_shri_i64(cpu_V0, cpu_V0, 32); | |
5446 | tcg_gen_trunc_i64_i32(tmp, cpu_V0); | |
5447 | break; | |
9ee6e8bb PB |
5448 | default: abort(); |
5449 | } | |
5450 | } else { | |
5451 | switch (size) { | |
ad69471c PB |
5452 | case 0: |
5453 | gen_helper_neon_narrow_round_high_u8(tmp, cpu_V0); | |
5454 | break; | |
5455 | case 1: | |
5456 | gen_helper_neon_narrow_round_high_u16(tmp, cpu_V0); | |
5457 | break; | |
5458 | case 2: | |
5459 | tcg_gen_addi_i64(cpu_V0, cpu_V0, 1u << 31); | |
5460 | tcg_gen_shri_i64(cpu_V0, cpu_V0, 32); | |
5461 | tcg_gen_trunc_i64_i32(tmp, cpu_V0); | |
5462 | break; | |
9ee6e8bb PB |
5463 | default: abort(); |
5464 | } | |
5465 | } | |
ad69471c PB |
5466 | if (pass == 0) { |
5467 | tmp3 = tmp; | |
5468 | } else { | |
5469 | neon_store_reg(rd, 0, tmp3); | |
5470 | neon_store_reg(rd, 1, tmp); | |
5471 | } | |
9ee6e8bb PB |
5472 | } else { |
5473 | /* Write back the result. */ | |
ad69471c | 5474 | neon_store_reg64(cpu_V0, rd + pass); |
9ee6e8bb PB |
5475 | } |
5476 | } | |
5477 | } else { | |
3e3326df PM |
5478 | /* Two registers and a scalar. NB that for ops of this form |
5479 | * the ARM ARM labels bit 24 as Q, but it is in our variable | |
5480 | * 'u', not 'q'. | |
5481 | */ | |
5482 | if (size == 0) { | |
5483 | return 1; | |
5484 | } | |
9ee6e8bb | 5485 | switch (op) { |
9ee6e8bb | 5486 | case 1: /* Float VMLA scalar */ |
9ee6e8bb | 5487 | case 5: /* Floating point VMLS scalar */ |
9ee6e8bb | 5488 | case 9: /* Floating point VMUL scalar */ |
3e3326df PM |
5489 | if (size == 1) { |
5490 | return 1; | |
5491 | } | |
5492 | /* fall through */ | |
5493 | case 0: /* Integer VMLA scalar */ | |
5494 | case 4: /* Integer VMLS scalar */ | |
5495 | case 8: /* Integer VMUL scalar */ | |
9ee6e8bb PB |
5496 | case 12: /* VQDMULH scalar */ |
5497 | case 13: /* VQRDMULH scalar */ | |
3e3326df PM |
5498 | if (u && ((rd | rn) & 1)) { |
5499 | return 1; | |
5500 | } | |
dd8fbd78 FN |
5501 | tmp = neon_get_scalar(size, rm); |
5502 | neon_store_scratch(0, tmp); | |
9ee6e8bb | 5503 | for (pass = 0; pass < (u ? 4 : 2); pass++) { |
dd8fbd78 FN |
5504 | tmp = neon_load_scratch(0); |
5505 | tmp2 = neon_load_reg(rn, pass); | |
9ee6e8bb PB |
5506 | if (op == 12) { |
5507 | if (size == 1) { | |
2a3f75b4 | 5508 | gen_helper_neon_qdmulh_s16(tmp, tmp, tmp2); |
9ee6e8bb | 5509 | } else { |
2a3f75b4 | 5510 | gen_helper_neon_qdmulh_s32(tmp, tmp, tmp2); |
9ee6e8bb PB |
5511 | } |
5512 | } else if (op == 13) { | |
5513 | if (size == 1) { | |
2a3f75b4 | 5514 | gen_helper_neon_qrdmulh_s16(tmp, tmp, tmp2); |
9ee6e8bb | 5515 | } else { |
2a3f75b4 | 5516 | gen_helper_neon_qrdmulh_s32(tmp, tmp, tmp2); |
9ee6e8bb PB |
5517 | } |
5518 | } else if (op & 1) { | |
dd8fbd78 | 5519 | gen_helper_neon_mul_f32(tmp, tmp, tmp2); |
9ee6e8bb PB |
5520 | } else { |
5521 | switch (size) { | |
dd8fbd78 FN |
5522 | case 0: gen_helper_neon_mul_u8(tmp, tmp, tmp2); break; |
5523 | case 1: gen_helper_neon_mul_u16(tmp, tmp, tmp2); break; | |
5524 | case 2: tcg_gen_mul_i32(tmp, tmp, tmp2); break; | |
3e3326df | 5525 | default: abort(); |
9ee6e8bb PB |
5526 | } |
5527 | } | |
7d1b0095 | 5528 | tcg_temp_free_i32(tmp2); |
9ee6e8bb PB |
5529 | if (op < 8) { |
5530 | /* Accumulate. */ | |
dd8fbd78 | 5531 | tmp2 = neon_load_reg(rd, pass); |
9ee6e8bb PB |
5532 | switch (op) { |
5533 | case 0: | |
dd8fbd78 | 5534 | gen_neon_add(size, tmp, tmp2); |
9ee6e8bb PB |
5535 | break; |
5536 | case 1: | |
dd8fbd78 | 5537 | gen_helper_neon_add_f32(tmp, tmp, tmp2); |
9ee6e8bb PB |
5538 | break; |
5539 | case 4: | |
dd8fbd78 | 5540 | gen_neon_rsb(size, tmp, tmp2); |
9ee6e8bb PB |
5541 | break; |
5542 | case 5: | |
dd8fbd78 | 5543 | gen_helper_neon_sub_f32(tmp, tmp2, tmp); |
9ee6e8bb PB |
5544 | break; |
5545 | default: | |
5546 | abort(); | |
5547 | } | |
7d1b0095 | 5548 | tcg_temp_free_i32(tmp2); |
9ee6e8bb | 5549 | } |
dd8fbd78 | 5550 | neon_store_reg(rd, pass, tmp); |
9ee6e8bb PB |
5551 | } |
5552 | break; | |
9ee6e8bb | 5553 | case 3: /* VQDMLAL scalar */ |
9ee6e8bb | 5554 | case 7: /* VQDMLSL scalar */ |
9ee6e8bb | 5555 | case 11: /* VQDMULL scalar */ |
3e3326df | 5556 | if (u == 1) { |
ad69471c | 5557 | return 1; |
3e3326df PM |
5558 | } |
5559 | /* fall through */ | |
5560 | case 2: /* VMLAL sclar */ | |
5561 | case 6: /* VMLSL scalar */ | |
5562 | case 10: /* VMULL scalar */ | |
5563 | if (rd & 1) { | |
5564 | return 1; | |
5565 | } | |
dd8fbd78 | 5566 | tmp2 = neon_get_scalar(size, rm); |
c6067f04 CL |
5567 | /* We need a copy of tmp2 because gen_neon_mull |
5568 | * deletes it during pass 0. */ | |
7d1b0095 | 5569 | tmp4 = tcg_temp_new_i32(); |
c6067f04 | 5570 | tcg_gen_mov_i32(tmp4, tmp2); |
dd8fbd78 | 5571 | tmp3 = neon_load_reg(rn, 1); |
ad69471c | 5572 | |
9ee6e8bb | 5573 | for (pass = 0; pass < 2; pass++) { |
ad69471c PB |
5574 | if (pass == 0) { |
5575 | tmp = neon_load_reg(rn, 0); | |
9ee6e8bb | 5576 | } else { |
dd8fbd78 | 5577 | tmp = tmp3; |
c6067f04 | 5578 | tmp2 = tmp4; |
9ee6e8bb | 5579 | } |
ad69471c | 5580 | gen_neon_mull(cpu_V0, tmp, tmp2, size, u); |
ad69471c PB |
5581 | if (op != 11) { |
5582 | neon_load_reg64(cpu_V1, rd + pass); | |
9ee6e8bb | 5583 | } |
9ee6e8bb | 5584 | switch (op) { |
4dc064e6 PM |
5585 | case 6: |
5586 | gen_neon_negl(cpu_V0, size); | |
5587 | /* Fall through */ | |
5588 | case 2: | |
ad69471c | 5589 | gen_neon_addl(size); |
9ee6e8bb PB |
5590 | break; |
5591 | case 3: case 7: | |
ad69471c | 5592 | gen_neon_addl_saturate(cpu_V0, cpu_V0, size); |
4dc064e6 PM |
5593 | if (op == 7) { |
5594 | gen_neon_negl(cpu_V0, size); | |
5595 | } | |
ad69471c | 5596 | gen_neon_addl_saturate(cpu_V0, cpu_V1, size); |
9ee6e8bb PB |
5597 | break; |
5598 | case 10: | |
5599 | /* no-op */ | |
5600 | break; | |
5601 | case 11: | |
ad69471c | 5602 | gen_neon_addl_saturate(cpu_V0, cpu_V0, size); |
9ee6e8bb PB |
5603 | break; |
5604 | default: | |
5605 | abort(); | |
5606 | } | |
ad69471c | 5607 | neon_store_reg64(cpu_V0, rd + pass); |
9ee6e8bb | 5608 | } |
dd8fbd78 | 5609 | |
dd8fbd78 | 5610 | |
9ee6e8bb PB |
5611 | break; |
5612 | default: /* 14 and 15 are RESERVED */ | |
5613 | return 1; | |
5614 | } | |
5615 | } | |
5616 | } else { /* size == 3 */ | |
5617 | if (!u) { | |
5618 | /* Extract. */ | |
9ee6e8bb | 5619 | imm = (insn >> 8) & 0xf; |
ad69471c PB |
5620 | |
5621 | if (imm > 7 && !q) | |
5622 | return 1; | |
5623 | ||
52579ea1 PM |
5624 | if (q && ((rd | rn | rm) & 1)) { |
5625 | return 1; | |
5626 | } | |
5627 | ||
ad69471c PB |
5628 | if (imm == 0) { |
5629 | neon_load_reg64(cpu_V0, rn); | |
5630 | if (q) { | |
5631 | neon_load_reg64(cpu_V1, rn + 1); | |
9ee6e8bb | 5632 | } |
ad69471c PB |
5633 | } else if (imm == 8) { |
5634 | neon_load_reg64(cpu_V0, rn + 1); | |
5635 | if (q) { | |
5636 | neon_load_reg64(cpu_V1, rm); | |
9ee6e8bb | 5637 | } |
ad69471c | 5638 | } else if (q) { |
a7812ae4 | 5639 | tmp64 = tcg_temp_new_i64(); |
ad69471c PB |
5640 | if (imm < 8) { |
5641 | neon_load_reg64(cpu_V0, rn); | |
a7812ae4 | 5642 | neon_load_reg64(tmp64, rn + 1); |
ad69471c PB |
5643 | } else { |
5644 | neon_load_reg64(cpu_V0, rn + 1); | |
a7812ae4 | 5645 | neon_load_reg64(tmp64, rm); |
ad69471c PB |
5646 | } |
5647 | tcg_gen_shri_i64(cpu_V0, cpu_V0, (imm & 7) * 8); | |
a7812ae4 | 5648 | tcg_gen_shli_i64(cpu_V1, tmp64, 64 - ((imm & 7) * 8)); |
ad69471c PB |
5649 | tcg_gen_or_i64(cpu_V0, cpu_V0, cpu_V1); |
5650 | if (imm < 8) { | |
5651 | neon_load_reg64(cpu_V1, rm); | |
9ee6e8bb | 5652 | } else { |
ad69471c PB |
5653 | neon_load_reg64(cpu_V1, rm + 1); |
5654 | imm -= 8; | |
9ee6e8bb | 5655 | } |
ad69471c | 5656 | tcg_gen_shli_i64(cpu_V1, cpu_V1, 64 - (imm * 8)); |
a7812ae4 PB |
5657 | tcg_gen_shri_i64(tmp64, tmp64, imm * 8); |
5658 | tcg_gen_or_i64(cpu_V1, cpu_V1, tmp64); | |
b75263d6 | 5659 | tcg_temp_free_i64(tmp64); |
ad69471c | 5660 | } else { |
a7812ae4 | 5661 | /* BUGFIX */ |
ad69471c | 5662 | neon_load_reg64(cpu_V0, rn); |
a7812ae4 | 5663 | tcg_gen_shri_i64(cpu_V0, cpu_V0, imm * 8); |
ad69471c | 5664 | neon_load_reg64(cpu_V1, rm); |
a7812ae4 | 5665 | tcg_gen_shli_i64(cpu_V1, cpu_V1, 64 - (imm * 8)); |
ad69471c PB |
5666 | tcg_gen_or_i64(cpu_V0, cpu_V0, cpu_V1); |
5667 | } | |
5668 | neon_store_reg64(cpu_V0, rd); | |
5669 | if (q) { | |
5670 | neon_store_reg64(cpu_V1, rd + 1); | |
9ee6e8bb PB |
5671 | } |
5672 | } else if ((insn & (1 << 11)) == 0) { | |
5673 | /* Two register misc. */ | |
5674 | op = ((insn >> 12) & 0x30) | ((insn >> 7) & 0xf); | |
5675 | size = (insn >> 18) & 3; | |
600b828c PM |
5676 | /* UNDEF for unknown op values and bad op-size combinations */ |
5677 | if ((neon_2rm_sizes[op] & (1 << size)) == 0) { | |
5678 | return 1; | |
5679 | } | |
fc2a9b37 PM |
5680 | if ((op != NEON_2RM_VMOVN && op != NEON_2RM_VQMOVN) && |
5681 | q && ((rm | rd) & 1)) { | |
5682 | return 1; | |
5683 | } | |
9ee6e8bb | 5684 | switch (op) { |
600b828c | 5685 | case NEON_2RM_VREV64: |
9ee6e8bb | 5686 | for (pass = 0; pass < (q ? 2 : 1); pass++) { |
dd8fbd78 FN |
5687 | tmp = neon_load_reg(rm, pass * 2); |
5688 | tmp2 = neon_load_reg(rm, pass * 2 + 1); | |
9ee6e8bb | 5689 | switch (size) { |
dd8fbd78 FN |
5690 | case 0: tcg_gen_bswap32_i32(tmp, tmp); break; |
5691 | case 1: gen_swap_half(tmp); break; | |
9ee6e8bb PB |
5692 | case 2: /* no-op */ break; |
5693 | default: abort(); | |
5694 | } | |
dd8fbd78 | 5695 | neon_store_reg(rd, pass * 2 + 1, tmp); |
9ee6e8bb | 5696 | if (size == 2) { |
dd8fbd78 | 5697 | neon_store_reg(rd, pass * 2, tmp2); |
9ee6e8bb | 5698 | } else { |
9ee6e8bb | 5699 | switch (size) { |
dd8fbd78 FN |
5700 | case 0: tcg_gen_bswap32_i32(tmp2, tmp2); break; |
5701 | case 1: gen_swap_half(tmp2); break; | |
9ee6e8bb PB |
5702 | default: abort(); |
5703 | } | |
dd8fbd78 | 5704 | neon_store_reg(rd, pass * 2, tmp2); |
9ee6e8bb PB |
5705 | } |
5706 | } | |
5707 | break; | |
600b828c PM |
5708 | case NEON_2RM_VPADDL: case NEON_2RM_VPADDL_U: |
5709 | case NEON_2RM_VPADAL: case NEON_2RM_VPADAL_U: | |
ad69471c PB |
5710 | for (pass = 0; pass < q + 1; pass++) { |
5711 | tmp = neon_load_reg(rm, pass * 2); | |
5712 | gen_neon_widen(cpu_V0, tmp, size, op & 1); | |
5713 | tmp = neon_load_reg(rm, pass * 2 + 1); | |
5714 | gen_neon_widen(cpu_V1, tmp, size, op & 1); | |
5715 | switch (size) { | |
5716 | case 0: gen_helper_neon_paddl_u16(CPU_V001); break; | |
5717 | case 1: gen_helper_neon_paddl_u32(CPU_V001); break; | |
5718 | case 2: tcg_gen_add_i64(CPU_V001); break; | |
5719 | default: abort(); | |
5720 | } | |
600b828c | 5721 | if (op >= NEON_2RM_VPADAL) { |
9ee6e8bb | 5722 | /* Accumulate. */ |
ad69471c PB |
5723 | neon_load_reg64(cpu_V1, rd + pass); |
5724 | gen_neon_addl(size); | |
9ee6e8bb | 5725 | } |
ad69471c | 5726 | neon_store_reg64(cpu_V0, rd + pass); |
9ee6e8bb PB |
5727 | } |
5728 | break; | |
600b828c | 5729 | case NEON_2RM_VTRN: |
9ee6e8bb | 5730 | if (size == 2) { |
a5a14945 | 5731 | int n; |
9ee6e8bb | 5732 | for (n = 0; n < (q ? 4 : 2); n += 2) { |
dd8fbd78 FN |
5733 | tmp = neon_load_reg(rm, n); |
5734 | tmp2 = neon_load_reg(rd, n + 1); | |
5735 | neon_store_reg(rm, n, tmp2); | |
5736 | neon_store_reg(rd, n + 1, tmp); | |
9ee6e8bb PB |
5737 | } |
5738 | } else { | |
5739 | goto elementwise; | |
5740 | } | |
5741 | break; | |
600b828c | 5742 | case NEON_2RM_VUZP: |
02acedf9 | 5743 | if (gen_neon_unzip(rd, rm, size, q)) { |
9ee6e8bb | 5744 | return 1; |
9ee6e8bb PB |
5745 | } |
5746 | break; | |
600b828c | 5747 | case NEON_2RM_VZIP: |
d68a6f3a | 5748 | if (gen_neon_zip(rd, rm, size, q)) { |
9ee6e8bb | 5749 | return 1; |
9ee6e8bb PB |
5750 | } |
5751 | break; | |
600b828c PM |
5752 | case NEON_2RM_VMOVN: case NEON_2RM_VQMOVN: |
5753 | /* also VQMOVUN; op field and mnemonics don't line up */ | |
fc2a9b37 PM |
5754 | if (rm & 1) { |
5755 | return 1; | |
5756 | } | |
a50f5b91 | 5757 | TCGV_UNUSED(tmp2); |
9ee6e8bb | 5758 | for (pass = 0; pass < 2; pass++) { |
ad69471c | 5759 | neon_load_reg64(cpu_V0, rm + pass); |
7d1b0095 | 5760 | tmp = tcg_temp_new_i32(); |
600b828c PM |
5761 | gen_neon_narrow_op(op == NEON_2RM_VMOVN, q, size, |
5762 | tmp, cpu_V0); | |
ad69471c PB |
5763 | if (pass == 0) { |
5764 | tmp2 = tmp; | |
5765 | } else { | |
5766 | neon_store_reg(rd, 0, tmp2); | |
5767 | neon_store_reg(rd, 1, tmp); | |
9ee6e8bb | 5768 | } |
9ee6e8bb PB |
5769 | } |
5770 | break; | |
600b828c | 5771 | case NEON_2RM_VSHLL: |
fc2a9b37 | 5772 | if (q || (rd & 1)) { |
9ee6e8bb | 5773 | return 1; |
600b828c | 5774 | } |
ad69471c PB |
5775 | tmp = neon_load_reg(rm, 0); |
5776 | tmp2 = neon_load_reg(rm, 1); | |
9ee6e8bb | 5777 | for (pass = 0; pass < 2; pass++) { |
ad69471c PB |
5778 | if (pass == 1) |
5779 | tmp = tmp2; | |
5780 | gen_neon_widen(cpu_V0, tmp, size, 1); | |
30d11a2a | 5781 | tcg_gen_shli_i64(cpu_V0, cpu_V0, 8 << size); |
ad69471c | 5782 | neon_store_reg64(cpu_V0, rd + pass); |
9ee6e8bb PB |
5783 | } |
5784 | break; | |
600b828c | 5785 | case NEON_2RM_VCVT_F16_F32: |
fc2a9b37 PM |
5786 | if (!arm_feature(env, ARM_FEATURE_VFP_FP16) || |
5787 | q || (rm & 1)) { | |
5788 | return 1; | |
5789 | } | |
7d1b0095 PM |
5790 | tmp = tcg_temp_new_i32(); |
5791 | tmp2 = tcg_temp_new_i32(); | |
60011498 | 5792 | tcg_gen_ld_f32(cpu_F0s, cpu_env, neon_reg_offset(rm, 0)); |
2d981da7 | 5793 | gen_helper_neon_fcvt_f32_to_f16(tmp, cpu_F0s, cpu_env); |
60011498 | 5794 | tcg_gen_ld_f32(cpu_F0s, cpu_env, neon_reg_offset(rm, 1)); |
2d981da7 | 5795 | gen_helper_neon_fcvt_f32_to_f16(tmp2, cpu_F0s, cpu_env); |
60011498 PB |
5796 | tcg_gen_shli_i32(tmp2, tmp2, 16); |
5797 | tcg_gen_or_i32(tmp2, tmp2, tmp); | |
5798 | tcg_gen_ld_f32(cpu_F0s, cpu_env, neon_reg_offset(rm, 2)); | |
2d981da7 | 5799 | gen_helper_neon_fcvt_f32_to_f16(tmp, cpu_F0s, cpu_env); |
60011498 PB |
5800 | tcg_gen_ld_f32(cpu_F0s, cpu_env, neon_reg_offset(rm, 3)); |
5801 | neon_store_reg(rd, 0, tmp2); | |
7d1b0095 | 5802 | tmp2 = tcg_temp_new_i32(); |
2d981da7 | 5803 | gen_helper_neon_fcvt_f32_to_f16(tmp2, cpu_F0s, cpu_env); |
60011498 PB |
5804 | tcg_gen_shli_i32(tmp2, tmp2, 16); |
5805 | tcg_gen_or_i32(tmp2, tmp2, tmp); | |
5806 | neon_store_reg(rd, 1, tmp2); | |
7d1b0095 | 5807 | tcg_temp_free_i32(tmp); |
60011498 | 5808 | break; |
600b828c | 5809 | case NEON_2RM_VCVT_F32_F16: |
fc2a9b37 PM |
5810 | if (!arm_feature(env, ARM_FEATURE_VFP_FP16) || |
5811 | q || (rd & 1)) { | |
5812 | return 1; | |
5813 | } | |
7d1b0095 | 5814 | tmp3 = tcg_temp_new_i32(); |
60011498 PB |
5815 | tmp = neon_load_reg(rm, 0); |
5816 | tmp2 = neon_load_reg(rm, 1); | |
5817 | tcg_gen_ext16u_i32(tmp3, tmp); | |
2d981da7 | 5818 | gen_helper_neon_fcvt_f16_to_f32(cpu_F0s, tmp3, cpu_env); |
60011498 PB |
5819 | tcg_gen_st_f32(cpu_F0s, cpu_env, neon_reg_offset(rd, 0)); |
5820 | tcg_gen_shri_i32(tmp3, tmp, 16); | |
2d981da7 | 5821 | gen_helper_neon_fcvt_f16_to_f32(cpu_F0s, tmp3, cpu_env); |
60011498 | 5822 | tcg_gen_st_f32(cpu_F0s, cpu_env, neon_reg_offset(rd, 1)); |
7d1b0095 | 5823 | tcg_temp_free_i32(tmp); |
60011498 | 5824 | tcg_gen_ext16u_i32(tmp3, tmp2); |
2d981da7 | 5825 | gen_helper_neon_fcvt_f16_to_f32(cpu_F0s, tmp3, cpu_env); |
60011498 PB |
5826 | tcg_gen_st_f32(cpu_F0s, cpu_env, neon_reg_offset(rd, 2)); |
5827 | tcg_gen_shri_i32(tmp3, tmp2, 16); | |
2d981da7 | 5828 | gen_helper_neon_fcvt_f16_to_f32(cpu_F0s, tmp3, cpu_env); |
60011498 | 5829 | tcg_gen_st_f32(cpu_F0s, cpu_env, neon_reg_offset(rd, 3)); |
7d1b0095 PM |
5830 | tcg_temp_free_i32(tmp2); |
5831 | tcg_temp_free_i32(tmp3); | |
60011498 | 5832 | break; |
9ee6e8bb PB |
5833 | default: |
5834 | elementwise: | |
5835 | for (pass = 0; pass < (q ? 4 : 2); pass++) { | |
600b828c | 5836 | if (neon_2rm_is_float_op(op)) { |
4373f3ce PB |
5837 | tcg_gen_ld_f32(cpu_F0s, cpu_env, |
5838 | neon_reg_offset(rm, pass)); | |
dd8fbd78 | 5839 | TCGV_UNUSED(tmp); |
9ee6e8bb | 5840 | } else { |
dd8fbd78 | 5841 | tmp = neon_load_reg(rm, pass); |
9ee6e8bb PB |
5842 | } |
5843 | switch (op) { | |
600b828c | 5844 | case NEON_2RM_VREV32: |
9ee6e8bb | 5845 | switch (size) { |
dd8fbd78 FN |
5846 | case 0: tcg_gen_bswap32_i32(tmp, tmp); break; |
5847 | case 1: gen_swap_half(tmp); break; | |
600b828c | 5848 | default: abort(); |
9ee6e8bb PB |
5849 | } |
5850 | break; | |
600b828c | 5851 | case NEON_2RM_VREV16: |
dd8fbd78 | 5852 | gen_rev16(tmp); |
9ee6e8bb | 5853 | break; |
600b828c | 5854 | case NEON_2RM_VCLS: |
9ee6e8bb | 5855 | switch (size) { |
dd8fbd78 FN |
5856 | case 0: gen_helper_neon_cls_s8(tmp, tmp); break; |
5857 | case 1: gen_helper_neon_cls_s16(tmp, tmp); break; | |
5858 | case 2: gen_helper_neon_cls_s32(tmp, tmp); break; | |
600b828c | 5859 | default: abort(); |
9ee6e8bb PB |
5860 | } |
5861 | break; | |
600b828c | 5862 | case NEON_2RM_VCLZ: |
9ee6e8bb | 5863 | switch (size) { |
dd8fbd78 FN |
5864 | case 0: gen_helper_neon_clz_u8(tmp, tmp); break; |
5865 | case 1: gen_helper_neon_clz_u16(tmp, tmp); break; | |
5866 | case 2: gen_helper_clz(tmp, tmp); break; | |
600b828c | 5867 | default: abort(); |
9ee6e8bb PB |
5868 | } |
5869 | break; | |
600b828c | 5870 | case NEON_2RM_VCNT: |
dd8fbd78 | 5871 | gen_helper_neon_cnt_u8(tmp, tmp); |
9ee6e8bb | 5872 | break; |
600b828c | 5873 | case NEON_2RM_VMVN: |
dd8fbd78 | 5874 | tcg_gen_not_i32(tmp, tmp); |
9ee6e8bb | 5875 | break; |
600b828c | 5876 | case NEON_2RM_VQABS: |
9ee6e8bb | 5877 | switch (size) { |
2a3f75b4 PM |
5878 | case 0: gen_helper_neon_qabs_s8(tmp, tmp); break; |
5879 | case 1: gen_helper_neon_qabs_s16(tmp, tmp); break; | |
5880 | case 2: gen_helper_neon_qabs_s32(tmp, tmp); break; | |
600b828c | 5881 | default: abort(); |
9ee6e8bb PB |
5882 | } |
5883 | break; | |
600b828c | 5884 | case NEON_2RM_VQNEG: |
9ee6e8bb | 5885 | switch (size) { |
2a3f75b4 PM |
5886 | case 0: gen_helper_neon_qneg_s8(tmp, tmp); break; |
5887 | case 1: gen_helper_neon_qneg_s16(tmp, tmp); break; | |
5888 | case 2: gen_helper_neon_qneg_s32(tmp, tmp); break; | |
600b828c | 5889 | default: abort(); |
9ee6e8bb PB |
5890 | } |
5891 | break; | |
600b828c | 5892 | case NEON_2RM_VCGT0: case NEON_2RM_VCLE0: |
dd8fbd78 | 5893 | tmp2 = tcg_const_i32(0); |
9ee6e8bb | 5894 | switch(size) { |
dd8fbd78 FN |
5895 | case 0: gen_helper_neon_cgt_s8(tmp, tmp, tmp2); break; |
5896 | case 1: gen_helper_neon_cgt_s16(tmp, tmp, tmp2); break; | |
5897 | case 2: gen_helper_neon_cgt_s32(tmp, tmp, tmp2); break; | |
600b828c | 5898 | default: abort(); |
9ee6e8bb | 5899 | } |
dd8fbd78 | 5900 | tcg_temp_free(tmp2); |
600b828c | 5901 | if (op == NEON_2RM_VCLE0) { |
dd8fbd78 | 5902 | tcg_gen_not_i32(tmp, tmp); |
600b828c | 5903 | } |
9ee6e8bb | 5904 | break; |
600b828c | 5905 | case NEON_2RM_VCGE0: case NEON_2RM_VCLT0: |
dd8fbd78 | 5906 | tmp2 = tcg_const_i32(0); |
9ee6e8bb | 5907 | switch(size) { |
dd8fbd78 FN |
5908 | case 0: gen_helper_neon_cge_s8(tmp, tmp, tmp2); break; |
5909 | case 1: gen_helper_neon_cge_s16(tmp, tmp, tmp2); break; | |
5910 | case 2: gen_helper_neon_cge_s32(tmp, tmp, tmp2); break; | |
600b828c | 5911 | default: abort(); |
9ee6e8bb | 5912 | } |
dd8fbd78 | 5913 | tcg_temp_free(tmp2); |
600b828c | 5914 | if (op == NEON_2RM_VCLT0) { |
dd8fbd78 | 5915 | tcg_gen_not_i32(tmp, tmp); |
600b828c | 5916 | } |
9ee6e8bb | 5917 | break; |
600b828c | 5918 | case NEON_2RM_VCEQ0: |
dd8fbd78 | 5919 | tmp2 = tcg_const_i32(0); |
9ee6e8bb | 5920 | switch(size) { |
dd8fbd78 FN |
5921 | case 0: gen_helper_neon_ceq_u8(tmp, tmp, tmp2); break; |
5922 | case 1: gen_helper_neon_ceq_u16(tmp, tmp, tmp2); break; | |
5923 | case 2: gen_helper_neon_ceq_u32(tmp, tmp, tmp2); break; | |
600b828c | 5924 | default: abort(); |
9ee6e8bb | 5925 | } |
dd8fbd78 | 5926 | tcg_temp_free(tmp2); |
9ee6e8bb | 5927 | break; |
600b828c | 5928 | case NEON_2RM_VABS: |
9ee6e8bb | 5929 | switch(size) { |
dd8fbd78 FN |
5930 | case 0: gen_helper_neon_abs_s8(tmp, tmp); break; |
5931 | case 1: gen_helper_neon_abs_s16(tmp, tmp); break; | |
5932 | case 2: tcg_gen_abs_i32(tmp, tmp); break; | |
600b828c | 5933 | default: abort(); |
9ee6e8bb PB |
5934 | } |
5935 | break; | |
600b828c | 5936 | case NEON_2RM_VNEG: |
dd8fbd78 FN |
5937 | tmp2 = tcg_const_i32(0); |
5938 | gen_neon_rsb(size, tmp, tmp2); | |
5939 | tcg_temp_free(tmp2); | |
9ee6e8bb | 5940 | break; |
600b828c | 5941 | case NEON_2RM_VCGT0_F: |
dd8fbd78 FN |
5942 | tmp2 = tcg_const_i32(0); |
5943 | gen_helper_neon_cgt_f32(tmp, tmp, tmp2); | |
5944 | tcg_temp_free(tmp2); | |
9ee6e8bb | 5945 | break; |
600b828c | 5946 | case NEON_2RM_VCGE0_F: |
dd8fbd78 FN |
5947 | tmp2 = tcg_const_i32(0); |
5948 | gen_helper_neon_cge_f32(tmp, tmp, tmp2); | |
5949 | tcg_temp_free(tmp2); | |
9ee6e8bb | 5950 | break; |
600b828c | 5951 | case NEON_2RM_VCEQ0_F: |
dd8fbd78 FN |
5952 | tmp2 = tcg_const_i32(0); |
5953 | gen_helper_neon_ceq_f32(tmp, tmp, tmp2); | |
5954 | tcg_temp_free(tmp2); | |
9ee6e8bb | 5955 | break; |
600b828c | 5956 | case NEON_2RM_VCLE0_F: |
0e326109 PM |
5957 | tmp2 = tcg_const_i32(0); |
5958 | gen_helper_neon_cge_f32(tmp, tmp2, tmp); | |
5959 | tcg_temp_free(tmp2); | |
5960 | break; | |
600b828c | 5961 | case NEON_2RM_VCLT0_F: |
0e326109 PM |
5962 | tmp2 = tcg_const_i32(0); |
5963 | gen_helper_neon_cgt_f32(tmp, tmp2, tmp); | |
5964 | tcg_temp_free(tmp2); | |
5965 | break; | |
600b828c | 5966 | case NEON_2RM_VABS_F: |
4373f3ce | 5967 | gen_vfp_abs(0); |
9ee6e8bb | 5968 | break; |
600b828c | 5969 | case NEON_2RM_VNEG_F: |
4373f3ce | 5970 | gen_vfp_neg(0); |
9ee6e8bb | 5971 | break; |
600b828c | 5972 | case NEON_2RM_VSWP: |
dd8fbd78 FN |
5973 | tmp2 = neon_load_reg(rd, pass); |
5974 | neon_store_reg(rm, pass, tmp2); | |
9ee6e8bb | 5975 | break; |
600b828c | 5976 | case NEON_2RM_VTRN: |
dd8fbd78 | 5977 | tmp2 = neon_load_reg(rd, pass); |
9ee6e8bb | 5978 | switch (size) { |
dd8fbd78 FN |
5979 | case 0: gen_neon_trn_u8(tmp, tmp2); break; |
5980 | case 1: gen_neon_trn_u16(tmp, tmp2); break; | |
600b828c | 5981 | default: abort(); |
9ee6e8bb | 5982 | } |
dd8fbd78 | 5983 | neon_store_reg(rm, pass, tmp2); |
9ee6e8bb | 5984 | break; |
600b828c | 5985 | case NEON_2RM_VRECPE: |
dd8fbd78 | 5986 | gen_helper_recpe_u32(tmp, tmp, cpu_env); |
9ee6e8bb | 5987 | break; |
600b828c | 5988 | case NEON_2RM_VRSQRTE: |
dd8fbd78 | 5989 | gen_helper_rsqrte_u32(tmp, tmp, cpu_env); |
9ee6e8bb | 5990 | break; |
600b828c | 5991 | case NEON_2RM_VRECPE_F: |
4373f3ce | 5992 | gen_helper_recpe_f32(cpu_F0s, cpu_F0s, cpu_env); |
9ee6e8bb | 5993 | break; |
600b828c | 5994 | case NEON_2RM_VRSQRTE_F: |
4373f3ce | 5995 | gen_helper_rsqrte_f32(cpu_F0s, cpu_F0s, cpu_env); |
9ee6e8bb | 5996 | break; |
600b828c | 5997 | case NEON_2RM_VCVT_FS: /* VCVT.F32.S32 */ |
d3587ef8 | 5998 | gen_vfp_sito(0); |
9ee6e8bb | 5999 | break; |
600b828c | 6000 | case NEON_2RM_VCVT_FU: /* VCVT.F32.U32 */ |
d3587ef8 | 6001 | gen_vfp_uito(0); |
9ee6e8bb | 6002 | break; |
600b828c | 6003 | case NEON_2RM_VCVT_SF: /* VCVT.S32.F32 */ |
d3587ef8 | 6004 | gen_vfp_tosiz(0); |
9ee6e8bb | 6005 | break; |
600b828c | 6006 | case NEON_2RM_VCVT_UF: /* VCVT.U32.F32 */ |
d3587ef8 | 6007 | gen_vfp_touiz(0); |
9ee6e8bb PB |
6008 | break; |
6009 | default: | |
600b828c PM |
6010 | /* Reserved op values were caught by the |
6011 | * neon_2rm_sizes[] check earlier. | |
6012 | */ | |
6013 | abort(); | |
9ee6e8bb | 6014 | } |
600b828c | 6015 | if (neon_2rm_is_float_op(op)) { |
4373f3ce PB |
6016 | tcg_gen_st_f32(cpu_F0s, cpu_env, |
6017 | neon_reg_offset(rd, pass)); | |
9ee6e8bb | 6018 | } else { |
dd8fbd78 | 6019 | neon_store_reg(rd, pass, tmp); |
9ee6e8bb PB |
6020 | } |
6021 | } | |
6022 | break; | |
6023 | } | |
6024 | } else if ((insn & (1 << 10)) == 0) { | |
6025 | /* VTBL, VTBX. */ | |
56907d77 PM |
6026 | int n = ((insn >> 8) & 3) + 1; |
6027 | if ((rn + n) > 32) { | |
6028 | /* This is UNPREDICTABLE; we choose to UNDEF to avoid the | |
6029 | * helper function running off the end of the register file. | |
6030 | */ | |
6031 | return 1; | |
6032 | } | |
6033 | n <<= 3; | |
9ee6e8bb | 6034 | if (insn & (1 << 6)) { |
8f8e3aa4 | 6035 | tmp = neon_load_reg(rd, 0); |
9ee6e8bb | 6036 | } else { |
7d1b0095 | 6037 | tmp = tcg_temp_new_i32(); |
8f8e3aa4 | 6038 | tcg_gen_movi_i32(tmp, 0); |
9ee6e8bb | 6039 | } |
8f8e3aa4 | 6040 | tmp2 = neon_load_reg(rm, 0); |
b75263d6 JR |
6041 | tmp4 = tcg_const_i32(rn); |
6042 | tmp5 = tcg_const_i32(n); | |
6043 | gen_helper_neon_tbl(tmp2, tmp2, tmp, tmp4, tmp5); | |
7d1b0095 | 6044 | tcg_temp_free_i32(tmp); |
9ee6e8bb | 6045 | if (insn & (1 << 6)) { |
8f8e3aa4 | 6046 | tmp = neon_load_reg(rd, 1); |
9ee6e8bb | 6047 | } else { |
7d1b0095 | 6048 | tmp = tcg_temp_new_i32(); |
8f8e3aa4 | 6049 | tcg_gen_movi_i32(tmp, 0); |
9ee6e8bb | 6050 | } |
8f8e3aa4 | 6051 | tmp3 = neon_load_reg(rm, 1); |
b75263d6 | 6052 | gen_helper_neon_tbl(tmp3, tmp3, tmp, tmp4, tmp5); |
25aeb69b JR |
6053 | tcg_temp_free_i32(tmp5); |
6054 | tcg_temp_free_i32(tmp4); | |
8f8e3aa4 | 6055 | neon_store_reg(rd, 0, tmp2); |
3018f259 | 6056 | neon_store_reg(rd, 1, tmp3); |
7d1b0095 | 6057 | tcg_temp_free_i32(tmp); |
9ee6e8bb PB |
6058 | } else if ((insn & 0x380) == 0) { |
6059 | /* VDUP */ | |
133da6aa JR |
6060 | if ((insn & (7 << 16)) == 0 || (q && (rd & 1))) { |
6061 | return 1; | |
6062 | } | |
9ee6e8bb | 6063 | if (insn & (1 << 19)) { |
dd8fbd78 | 6064 | tmp = neon_load_reg(rm, 1); |
9ee6e8bb | 6065 | } else { |
dd8fbd78 | 6066 | tmp = neon_load_reg(rm, 0); |
9ee6e8bb PB |
6067 | } |
6068 | if (insn & (1 << 16)) { | |
dd8fbd78 | 6069 | gen_neon_dup_u8(tmp, ((insn >> 17) & 3) * 8); |
9ee6e8bb PB |
6070 | } else if (insn & (1 << 17)) { |
6071 | if ((insn >> 18) & 1) | |
dd8fbd78 | 6072 | gen_neon_dup_high16(tmp); |
9ee6e8bb | 6073 | else |
dd8fbd78 | 6074 | gen_neon_dup_low16(tmp); |
9ee6e8bb PB |
6075 | } |
6076 | for (pass = 0; pass < (q ? 4 : 2); pass++) { | |
7d1b0095 | 6077 | tmp2 = tcg_temp_new_i32(); |
dd8fbd78 FN |
6078 | tcg_gen_mov_i32(tmp2, tmp); |
6079 | neon_store_reg(rd, pass, tmp2); | |
9ee6e8bb | 6080 | } |
7d1b0095 | 6081 | tcg_temp_free_i32(tmp); |
9ee6e8bb PB |
6082 | } else { |
6083 | return 1; | |
6084 | } | |
6085 | } | |
6086 | } | |
6087 | return 0; | |
6088 | } | |
6089 | ||
fe1479c3 PB |
6090 | static int disas_cp14_read(CPUState * env, DisasContext *s, uint32_t insn) |
6091 | { | |
6092 | int crn = (insn >> 16) & 0xf; | |
6093 | int crm = insn & 0xf; | |
6094 | int op1 = (insn >> 21) & 7; | |
6095 | int op2 = (insn >> 5) & 7; | |
6096 | int rt = (insn >> 12) & 0xf; | |
6097 | TCGv tmp; | |
6098 | ||
ca27c052 PM |
6099 | /* Minimal set of debug registers, since we don't support debug */ |
6100 | if (op1 == 0 && crn == 0 && op2 == 0) { | |
6101 | switch (crm) { | |
6102 | case 0: | |
6103 | /* DBGDIDR: just RAZ. In particular this means the | |
6104 | * "debug architecture version" bits will read as | |
6105 | * a reserved value, which should cause Linux to | |
6106 | * not try to use the debug hardware. | |
6107 | */ | |
6108 | tmp = tcg_const_i32(0); | |
6109 | store_reg(s, rt, tmp); | |
6110 | return 0; | |
6111 | case 1: | |
6112 | case 2: | |
6113 | /* DBGDRAR and DBGDSAR: v7 only. Always RAZ since we | |
6114 | * don't implement memory mapped debug components | |
6115 | */ | |
6116 | if (ENABLE_ARCH_7) { | |
6117 | tmp = tcg_const_i32(0); | |
6118 | store_reg(s, rt, tmp); | |
6119 | return 0; | |
6120 | } | |
6121 | break; | |
6122 | default: | |
6123 | break; | |
6124 | } | |
6125 | } | |
6126 | ||
fe1479c3 PB |
6127 | if (arm_feature(env, ARM_FEATURE_THUMB2EE)) { |
6128 | if (op1 == 6 && crn == 0 && crm == 0 && op2 == 0) { | |
6129 | /* TEECR */ | |
6130 | if (IS_USER(s)) | |
6131 | return 1; | |
6132 | tmp = load_cpu_field(teecr); | |
6133 | store_reg(s, rt, tmp); | |
6134 | return 0; | |
6135 | } | |
6136 | if (op1 == 6 && crn == 1 && crm == 0 && op2 == 0) { | |
6137 | /* TEEHBR */ | |
6138 | if (IS_USER(s) && (env->teecr & 1)) | |
6139 | return 1; | |
6140 | tmp = load_cpu_field(teehbr); | |
6141 | store_reg(s, rt, tmp); | |
6142 | return 0; | |
6143 | } | |
6144 | } | |
6145 | fprintf(stderr, "Unknown cp14 read op1:%d crn:%d crm:%d op2:%d\n", | |
6146 | op1, crn, crm, op2); | |
6147 | return 1; | |
6148 | } | |
6149 | ||
6150 | static int disas_cp14_write(CPUState * env, DisasContext *s, uint32_t insn) | |
6151 | { | |
6152 | int crn = (insn >> 16) & 0xf; | |
6153 | int crm = insn & 0xf; | |
6154 | int op1 = (insn >> 21) & 7; | |
6155 | int op2 = (insn >> 5) & 7; | |
6156 | int rt = (insn >> 12) & 0xf; | |
6157 | TCGv tmp; | |
6158 | ||
6159 | if (arm_feature(env, ARM_FEATURE_THUMB2EE)) { | |
6160 | if (op1 == 6 && crn == 0 && crm == 0 && op2 == 0) { | |
6161 | /* TEECR */ | |
6162 | if (IS_USER(s)) | |
6163 | return 1; | |
6164 | tmp = load_reg(s, rt); | |
6165 | gen_helper_set_teecr(cpu_env, tmp); | |
7d1b0095 | 6166 | tcg_temp_free_i32(tmp); |
fe1479c3 PB |
6167 | return 0; |
6168 | } | |
6169 | if (op1 == 6 && crn == 1 && crm == 0 && op2 == 0) { | |
6170 | /* TEEHBR */ | |
6171 | if (IS_USER(s) && (env->teecr & 1)) | |
6172 | return 1; | |
6173 | tmp = load_reg(s, rt); | |
6174 | store_cpu_field(tmp, teehbr); | |
6175 | return 0; | |
6176 | } | |
6177 | } | |
6178 | fprintf(stderr, "Unknown cp14 write op1:%d crn:%d crm:%d op2:%d\n", | |
6179 | op1, crn, crm, op2); | |
6180 | return 1; | |
6181 | } | |
6182 | ||
9ee6e8bb PB |
6183 | static int disas_coproc_insn(CPUState * env, DisasContext *s, uint32_t insn) |
6184 | { | |
6185 | int cpnum; | |
6186 | ||
6187 | cpnum = (insn >> 8) & 0xf; | |
6188 | if (arm_feature(env, ARM_FEATURE_XSCALE) | |
6189 | && ((env->cp15.c15_cpar ^ 0x3fff) & (1 << cpnum))) | |
6190 | return 1; | |
6191 | ||
6192 | switch (cpnum) { | |
6193 | case 0: | |
6194 | case 1: | |
6195 | if (arm_feature(env, ARM_FEATURE_IWMMXT)) { | |
6196 | return disas_iwmmxt_insn(env, s, insn); | |
6197 | } else if (arm_feature(env, ARM_FEATURE_XSCALE)) { | |
6198 | return disas_dsp_insn(env, s, insn); | |
6199 | } | |
6200 | return 1; | |
6201 | case 10: | |
6202 | case 11: | |
6203 | return disas_vfp_insn (env, s, insn); | |
fe1479c3 PB |
6204 | case 14: |
6205 | /* Coprocessors 7-15 are architecturally reserved by ARM. | |
6206 | Unfortunately Intel decided to ignore this. */ | |
6207 | if (arm_feature(env, ARM_FEATURE_XSCALE)) | |
6208 | goto board; | |
6209 | if (insn & (1 << 20)) | |
6210 | return disas_cp14_read(env, s, insn); | |
6211 | else | |
6212 | return disas_cp14_write(env, s, insn); | |
9ee6e8bb PB |
6213 | case 15: |
6214 | return disas_cp15_insn (env, s, insn); | |
6215 | default: | |
fe1479c3 | 6216 | board: |
9ee6e8bb PB |
6217 | /* Unknown coprocessor. See if the board has hooked it. */ |
6218 | return disas_cp_insn (env, s, insn); | |
6219 | } | |
6220 | } | |
6221 | ||
5e3f878a PB |
6222 | |
6223 | /* Store a 64-bit value to a register pair. Clobbers val. */ | |
a7812ae4 | 6224 | static void gen_storeq_reg(DisasContext *s, int rlow, int rhigh, TCGv_i64 val) |
5e3f878a PB |
6225 | { |
6226 | TCGv tmp; | |
7d1b0095 | 6227 | tmp = tcg_temp_new_i32(); |
5e3f878a PB |
6228 | tcg_gen_trunc_i64_i32(tmp, val); |
6229 | store_reg(s, rlow, tmp); | |
7d1b0095 | 6230 | tmp = tcg_temp_new_i32(); |
5e3f878a PB |
6231 | tcg_gen_shri_i64(val, val, 32); |
6232 | tcg_gen_trunc_i64_i32(tmp, val); | |
6233 | store_reg(s, rhigh, tmp); | |
6234 | } | |
6235 | ||
6236 | /* load a 32-bit value from a register and perform a 64-bit accumulate. */ | |
a7812ae4 | 6237 | static void gen_addq_lo(DisasContext *s, TCGv_i64 val, int rlow) |
5e3f878a | 6238 | { |
a7812ae4 | 6239 | TCGv_i64 tmp; |
5e3f878a PB |
6240 | TCGv tmp2; |
6241 | ||
36aa55dc | 6242 | /* Load value and extend to 64 bits. */ |
a7812ae4 | 6243 | tmp = tcg_temp_new_i64(); |
5e3f878a PB |
6244 | tmp2 = load_reg(s, rlow); |
6245 | tcg_gen_extu_i32_i64(tmp, tmp2); | |
7d1b0095 | 6246 | tcg_temp_free_i32(tmp2); |
5e3f878a | 6247 | tcg_gen_add_i64(val, val, tmp); |
b75263d6 | 6248 | tcg_temp_free_i64(tmp); |
5e3f878a PB |
6249 | } |
6250 | ||
6251 | /* load and add a 64-bit value from a register pair. */ | |
a7812ae4 | 6252 | static void gen_addq(DisasContext *s, TCGv_i64 val, int rlow, int rhigh) |
5e3f878a | 6253 | { |
a7812ae4 | 6254 | TCGv_i64 tmp; |
36aa55dc PB |
6255 | TCGv tmpl; |
6256 | TCGv tmph; | |
5e3f878a PB |
6257 | |
6258 | /* Load 64-bit value rd:rn. */ | |
36aa55dc PB |
6259 | tmpl = load_reg(s, rlow); |
6260 | tmph = load_reg(s, rhigh); | |
a7812ae4 | 6261 | tmp = tcg_temp_new_i64(); |
36aa55dc | 6262 | tcg_gen_concat_i32_i64(tmp, tmpl, tmph); |
7d1b0095 PM |
6263 | tcg_temp_free_i32(tmpl); |
6264 | tcg_temp_free_i32(tmph); | |
5e3f878a | 6265 | tcg_gen_add_i64(val, val, tmp); |
b75263d6 | 6266 | tcg_temp_free_i64(tmp); |
5e3f878a PB |
6267 | } |
6268 | ||
6269 | /* Set N and Z flags from a 64-bit value. */ | |
a7812ae4 | 6270 | static void gen_logicq_cc(TCGv_i64 val) |
5e3f878a | 6271 | { |
7d1b0095 | 6272 | TCGv tmp = tcg_temp_new_i32(); |
5e3f878a | 6273 | gen_helper_logicq_cc(tmp, val); |
6fbe23d5 | 6274 | gen_logic_CC(tmp); |
7d1b0095 | 6275 | tcg_temp_free_i32(tmp); |
5e3f878a PB |
6276 | } |
6277 | ||
426f5abc PB |
6278 | /* Load/Store exclusive instructions are implemented by remembering |
6279 | the value/address loaded, and seeing if these are the same | |
6280 | when the store is performed. This should be is sufficient to implement | |
6281 | the architecturally mandated semantics, and avoids having to monitor | |
6282 | regular stores. | |
6283 | ||
6284 | In system emulation mode only one CPU will be running at once, so | |
6285 | this sequence is effectively atomic. In user emulation mode we | |
6286 | throw an exception and handle the atomic operation elsewhere. */ | |
6287 | static void gen_load_exclusive(DisasContext *s, int rt, int rt2, | |
6288 | TCGv addr, int size) | |
6289 | { | |
6290 | TCGv tmp; | |
6291 | ||
6292 | switch (size) { | |
6293 | case 0: | |
6294 | tmp = gen_ld8u(addr, IS_USER(s)); | |
6295 | break; | |
6296 | case 1: | |
6297 | tmp = gen_ld16u(addr, IS_USER(s)); | |
6298 | break; | |
6299 | case 2: | |
6300 | case 3: | |
6301 | tmp = gen_ld32(addr, IS_USER(s)); | |
6302 | break; | |
6303 | default: | |
6304 | abort(); | |
6305 | } | |
6306 | tcg_gen_mov_i32(cpu_exclusive_val, tmp); | |
6307 | store_reg(s, rt, tmp); | |
6308 | if (size == 3) { | |
7d1b0095 | 6309 | TCGv tmp2 = tcg_temp_new_i32(); |
2c9adbda PM |
6310 | tcg_gen_addi_i32(tmp2, addr, 4); |
6311 | tmp = gen_ld32(tmp2, IS_USER(s)); | |
7d1b0095 | 6312 | tcg_temp_free_i32(tmp2); |
426f5abc PB |
6313 | tcg_gen_mov_i32(cpu_exclusive_high, tmp); |
6314 | store_reg(s, rt2, tmp); | |
6315 | } | |
6316 | tcg_gen_mov_i32(cpu_exclusive_addr, addr); | |
6317 | } | |
6318 | ||
6319 | static void gen_clrex(DisasContext *s) | |
6320 | { | |
6321 | tcg_gen_movi_i32(cpu_exclusive_addr, -1); | |
6322 | } | |
6323 | ||
6324 | #ifdef CONFIG_USER_ONLY | |
6325 | static void gen_store_exclusive(DisasContext *s, int rd, int rt, int rt2, | |
6326 | TCGv addr, int size) | |
6327 | { | |
6328 | tcg_gen_mov_i32(cpu_exclusive_test, addr); | |
6329 | tcg_gen_movi_i32(cpu_exclusive_info, | |
6330 | size | (rd << 4) | (rt << 8) | (rt2 << 12)); | |
bc4a0de0 | 6331 | gen_exception_insn(s, 4, EXCP_STREX); |
426f5abc PB |
6332 | } |
6333 | #else | |
6334 | static void gen_store_exclusive(DisasContext *s, int rd, int rt, int rt2, | |
6335 | TCGv addr, int size) | |
6336 | { | |
6337 | TCGv tmp; | |
6338 | int done_label; | |
6339 | int fail_label; | |
6340 | ||
6341 | /* if (env->exclusive_addr == addr && env->exclusive_val == [addr]) { | |
6342 | [addr] = {Rt}; | |
6343 | {Rd} = 0; | |
6344 | } else { | |
6345 | {Rd} = 1; | |
6346 | } */ | |
6347 | fail_label = gen_new_label(); | |
6348 | done_label = gen_new_label(); | |
6349 | tcg_gen_brcond_i32(TCG_COND_NE, addr, cpu_exclusive_addr, fail_label); | |
6350 | switch (size) { | |
6351 | case 0: | |
6352 | tmp = gen_ld8u(addr, IS_USER(s)); | |
6353 | break; | |
6354 | case 1: | |
6355 | tmp = gen_ld16u(addr, IS_USER(s)); | |
6356 | break; | |
6357 | case 2: | |
6358 | case 3: | |
6359 | tmp = gen_ld32(addr, IS_USER(s)); | |
6360 | break; | |
6361 | default: | |
6362 | abort(); | |
6363 | } | |
6364 | tcg_gen_brcond_i32(TCG_COND_NE, tmp, cpu_exclusive_val, fail_label); | |
7d1b0095 | 6365 | tcg_temp_free_i32(tmp); |
426f5abc | 6366 | if (size == 3) { |
7d1b0095 | 6367 | TCGv tmp2 = tcg_temp_new_i32(); |
426f5abc | 6368 | tcg_gen_addi_i32(tmp2, addr, 4); |
2c9adbda | 6369 | tmp = gen_ld32(tmp2, IS_USER(s)); |
7d1b0095 | 6370 | tcg_temp_free_i32(tmp2); |
426f5abc | 6371 | tcg_gen_brcond_i32(TCG_COND_NE, tmp, cpu_exclusive_high, fail_label); |
7d1b0095 | 6372 | tcg_temp_free_i32(tmp); |
426f5abc PB |
6373 | } |
6374 | tmp = load_reg(s, rt); | |
6375 | switch (size) { | |
6376 | case 0: | |
6377 | gen_st8(tmp, addr, IS_USER(s)); | |
6378 | break; | |
6379 | case 1: | |
6380 | gen_st16(tmp, addr, IS_USER(s)); | |
6381 | break; | |
6382 | case 2: | |
6383 | case 3: | |
6384 | gen_st32(tmp, addr, IS_USER(s)); | |
6385 | break; | |
6386 | default: | |
6387 | abort(); | |
6388 | } | |
6389 | if (size == 3) { | |
6390 | tcg_gen_addi_i32(addr, addr, 4); | |
6391 | tmp = load_reg(s, rt2); | |
6392 | gen_st32(tmp, addr, IS_USER(s)); | |
6393 | } | |
6394 | tcg_gen_movi_i32(cpu_R[rd], 0); | |
6395 | tcg_gen_br(done_label); | |
6396 | gen_set_label(fail_label); | |
6397 | tcg_gen_movi_i32(cpu_R[rd], 1); | |
6398 | gen_set_label(done_label); | |
6399 | tcg_gen_movi_i32(cpu_exclusive_addr, -1); | |
6400 | } | |
6401 | #endif | |
6402 | ||
9ee6e8bb PB |
6403 | static void disas_arm_insn(CPUState * env, DisasContext *s) |
6404 | { | |
6405 | unsigned int cond, insn, val, op1, i, shift, rm, rs, rn, rd, sh; | |
b26eefb6 | 6406 | TCGv tmp; |
3670669c | 6407 | TCGv tmp2; |
6ddbc6e4 | 6408 | TCGv tmp3; |
b0109805 | 6409 | TCGv addr; |
a7812ae4 | 6410 | TCGv_i64 tmp64; |
9ee6e8bb PB |
6411 | |
6412 | insn = ldl_code(s->pc); | |
6413 | s->pc += 4; | |
6414 | ||
6415 | /* M variants do not implement ARM mode. */ | |
6416 | if (IS_M(env)) | |
6417 | goto illegal_op; | |
6418 | cond = insn >> 28; | |
6419 | if (cond == 0xf){ | |
be5e7a76 DES |
6420 | /* In ARMv3 and v4 the NV condition is UNPREDICTABLE; we |
6421 | * choose to UNDEF. In ARMv5 and above the space is used | |
6422 | * for miscellaneous unconditional instructions. | |
6423 | */ | |
6424 | ARCH(5); | |
6425 | ||
9ee6e8bb PB |
6426 | /* Unconditional instructions. */ |
6427 | if (((insn >> 25) & 7) == 1) { | |
6428 | /* NEON Data processing. */ | |
6429 | if (!arm_feature(env, ARM_FEATURE_NEON)) | |
6430 | goto illegal_op; | |
6431 | ||
6432 | if (disas_neon_data_insn(env, s, insn)) | |
6433 | goto illegal_op; | |
6434 | return; | |
6435 | } | |
6436 | if ((insn & 0x0f100000) == 0x04000000) { | |
6437 | /* NEON load/store. */ | |
6438 | if (!arm_feature(env, ARM_FEATURE_NEON)) | |
6439 | goto illegal_op; | |
6440 | ||
6441 | if (disas_neon_ls_insn(env, s, insn)) | |
6442 | goto illegal_op; | |
6443 | return; | |
6444 | } | |
3d185e5d PM |
6445 | if (((insn & 0x0f30f000) == 0x0510f000) || |
6446 | ((insn & 0x0f30f010) == 0x0710f000)) { | |
6447 | if ((insn & (1 << 22)) == 0) { | |
6448 | /* PLDW; v7MP */ | |
6449 | if (!arm_feature(env, ARM_FEATURE_V7MP)) { | |
6450 | goto illegal_op; | |
6451 | } | |
6452 | } | |
6453 | /* Otherwise PLD; v5TE+ */ | |
be5e7a76 | 6454 | ARCH(5TE); |
3d185e5d PM |
6455 | return; |
6456 | } | |
6457 | if (((insn & 0x0f70f000) == 0x0450f000) || | |
6458 | ((insn & 0x0f70f010) == 0x0650f000)) { | |
6459 | ARCH(7); | |
6460 | return; /* PLI; V7 */ | |
6461 | } | |
6462 | if (((insn & 0x0f700000) == 0x04100000) || | |
6463 | ((insn & 0x0f700010) == 0x06100000)) { | |
6464 | if (!arm_feature(env, ARM_FEATURE_V7MP)) { | |
6465 | goto illegal_op; | |
6466 | } | |
6467 | return; /* v7MP: Unallocated memory hint: must NOP */ | |
6468 | } | |
6469 | ||
6470 | if ((insn & 0x0ffffdff) == 0x01010000) { | |
9ee6e8bb PB |
6471 | ARCH(6); |
6472 | /* setend */ | |
6473 | if (insn & (1 << 9)) { | |
6474 | /* BE8 mode not implemented. */ | |
6475 | goto illegal_op; | |
6476 | } | |
6477 | return; | |
6478 | } else if ((insn & 0x0fffff00) == 0x057ff000) { | |
6479 | switch ((insn >> 4) & 0xf) { | |
6480 | case 1: /* clrex */ | |
6481 | ARCH(6K); | |
426f5abc | 6482 | gen_clrex(s); |
9ee6e8bb PB |
6483 | return; |
6484 | case 4: /* dsb */ | |
6485 | case 5: /* dmb */ | |
6486 | case 6: /* isb */ | |
6487 | ARCH(7); | |
6488 | /* We don't emulate caches so these are a no-op. */ | |
6489 | return; | |
6490 | default: | |
6491 | goto illegal_op; | |
6492 | } | |
6493 | } else if ((insn & 0x0e5fffe0) == 0x084d0500) { | |
6494 | /* srs */ | |
c67b6b71 | 6495 | int32_t offset; |
9ee6e8bb PB |
6496 | if (IS_USER(s)) |
6497 | goto illegal_op; | |
6498 | ARCH(6); | |
6499 | op1 = (insn & 0x1f); | |
7d1b0095 | 6500 | addr = tcg_temp_new_i32(); |
39ea3d4e PM |
6501 | tmp = tcg_const_i32(op1); |
6502 | gen_helper_get_r13_banked(addr, cpu_env, tmp); | |
6503 | tcg_temp_free_i32(tmp); | |
9ee6e8bb PB |
6504 | i = (insn >> 23) & 3; |
6505 | switch (i) { | |
6506 | case 0: offset = -4; break; /* DA */ | |
c67b6b71 FN |
6507 | case 1: offset = 0; break; /* IA */ |
6508 | case 2: offset = -8; break; /* DB */ | |
9ee6e8bb PB |
6509 | case 3: offset = 4; break; /* IB */ |
6510 | default: abort(); | |
6511 | } | |
6512 | if (offset) | |
b0109805 PB |
6513 | tcg_gen_addi_i32(addr, addr, offset); |
6514 | tmp = load_reg(s, 14); | |
6515 | gen_st32(tmp, addr, 0); | |
c67b6b71 | 6516 | tmp = load_cpu_field(spsr); |
b0109805 PB |
6517 | tcg_gen_addi_i32(addr, addr, 4); |
6518 | gen_st32(tmp, addr, 0); | |
9ee6e8bb PB |
6519 | if (insn & (1 << 21)) { |
6520 | /* Base writeback. */ | |
6521 | switch (i) { | |
6522 | case 0: offset = -8; break; | |
c67b6b71 FN |
6523 | case 1: offset = 4; break; |
6524 | case 2: offset = -4; break; | |
9ee6e8bb PB |
6525 | case 3: offset = 0; break; |
6526 | default: abort(); | |
6527 | } | |
6528 | if (offset) | |
c67b6b71 | 6529 | tcg_gen_addi_i32(addr, addr, offset); |
39ea3d4e PM |
6530 | tmp = tcg_const_i32(op1); |
6531 | gen_helper_set_r13_banked(cpu_env, tmp, addr); | |
6532 | tcg_temp_free_i32(tmp); | |
7d1b0095 | 6533 | tcg_temp_free_i32(addr); |
b0109805 | 6534 | } else { |
7d1b0095 | 6535 | tcg_temp_free_i32(addr); |
9ee6e8bb | 6536 | } |
a990f58f | 6537 | return; |
ea825eee | 6538 | } else if ((insn & 0x0e50ffe0) == 0x08100a00) { |
9ee6e8bb | 6539 | /* rfe */ |
c67b6b71 | 6540 | int32_t offset; |
9ee6e8bb PB |
6541 | if (IS_USER(s)) |
6542 | goto illegal_op; | |
6543 | ARCH(6); | |
6544 | rn = (insn >> 16) & 0xf; | |
b0109805 | 6545 | addr = load_reg(s, rn); |
9ee6e8bb PB |
6546 | i = (insn >> 23) & 3; |
6547 | switch (i) { | |
b0109805 | 6548 | case 0: offset = -4; break; /* DA */ |
c67b6b71 FN |
6549 | case 1: offset = 0; break; /* IA */ |
6550 | case 2: offset = -8; break; /* DB */ | |
b0109805 | 6551 | case 3: offset = 4; break; /* IB */ |
9ee6e8bb PB |
6552 | default: abort(); |
6553 | } | |
6554 | if (offset) | |
b0109805 PB |
6555 | tcg_gen_addi_i32(addr, addr, offset); |
6556 | /* Load PC into tmp and CPSR into tmp2. */ | |
6557 | tmp = gen_ld32(addr, 0); | |
6558 | tcg_gen_addi_i32(addr, addr, 4); | |
6559 | tmp2 = gen_ld32(addr, 0); | |
9ee6e8bb PB |
6560 | if (insn & (1 << 21)) { |
6561 | /* Base writeback. */ | |
6562 | switch (i) { | |
b0109805 | 6563 | case 0: offset = -8; break; |
c67b6b71 FN |
6564 | case 1: offset = 4; break; |
6565 | case 2: offset = -4; break; | |
b0109805 | 6566 | case 3: offset = 0; break; |
9ee6e8bb PB |
6567 | default: abort(); |
6568 | } | |
6569 | if (offset) | |
b0109805 PB |
6570 | tcg_gen_addi_i32(addr, addr, offset); |
6571 | store_reg(s, rn, addr); | |
6572 | } else { | |
7d1b0095 | 6573 | tcg_temp_free_i32(addr); |
9ee6e8bb | 6574 | } |
b0109805 | 6575 | gen_rfe(s, tmp, tmp2); |
c67b6b71 | 6576 | return; |
9ee6e8bb PB |
6577 | } else if ((insn & 0x0e000000) == 0x0a000000) { |
6578 | /* branch link and change to thumb (blx <offset>) */ | |
6579 | int32_t offset; | |
6580 | ||
6581 | val = (uint32_t)s->pc; | |
7d1b0095 | 6582 | tmp = tcg_temp_new_i32(); |
d9ba4830 PB |
6583 | tcg_gen_movi_i32(tmp, val); |
6584 | store_reg(s, 14, tmp); | |
9ee6e8bb PB |
6585 | /* Sign-extend the 24-bit offset */ |
6586 | offset = (((int32_t)insn) << 8) >> 8; | |
6587 | /* offset * 4 + bit24 * 2 + (thumb bit) */ | |
6588 | val += (offset << 2) | ((insn >> 23) & 2) | 1; | |
6589 | /* pipeline offset */ | |
6590 | val += 4; | |
be5e7a76 | 6591 | /* protected by ARCH(5); above, near the start of uncond block */ |
d9ba4830 | 6592 | gen_bx_im(s, val); |
9ee6e8bb PB |
6593 | return; |
6594 | } else if ((insn & 0x0e000f00) == 0x0c000100) { | |
6595 | if (arm_feature(env, ARM_FEATURE_IWMMXT)) { | |
6596 | /* iWMMXt register transfer. */ | |
6597 | if (env->cp15.c15_cpar & (1 << 1)) | |
6598 | if (!disas_iwmmxt_insn(env, s, insn)) | |
6599 | return; | |
6600 | } | |
6601 | } else if ((insn & 0x0fe00000) == 0x0c400000) { | |
6602 | /* Coprocessor double register transfer. */ | |
be5e7a76 | 6603 | ARCH(5TE); |
9ee6e8bb PB |
6604 | } else if ((insn & 0x0f000010) == 0x0e000010) { |
6605 | /* Additional coprocessor register transfer. */ | |
7997d92f | 6606 | } else if ((insn & 0x0ff10020) == 0x01000000) { |
9ee6e8bb PB |
6607 | uint32_t mask; |
6608 | uint32_t val; | |
6609 | /* cps (privileged) */ | |
6610 | if (IS_USER(s)) | |
6611 | return; | |
6612 | mask = val = 0; | |
6613 | if (insn & (1 << 19)) { | |
6614 | if (insn & (1 << 8)) | |
6615 | mask |= CPSR_A; | |
6616 | if (insn & (1 << 7)) | |
6617 | mask |= CPSR_I; | |
6618 | if (insn & (1 << 6)) | |
6619 | mask |= CPSR_F; | |
6620 | if (insn & (1 << 18)) | |
6621 | val |= mask; | |
6622 | } | |
7997d92f | 6623 | if (insn & (1 << 17)) { |
9ee6e8bb PB |
6624 | mask |= CPSR_M; |
6625 | val |= (insn & 0x1f); | |
6626 | } | |
6627 | if (mask) { | |
2fbac54b | 6628 | gen_set_psr_im(s, mask, 0, val); |
9ee6e8bb PB |
6629 | } |
6630 | return; | |
6631 | } | |
6632 | goto illegal_op; | |
6633 | } | |
6634 | if (cond != 0xe) { | |
6635 | /* if not always execute, we generate a conditional jump to | |
6636 | next instruction */ | |
6637 | s->condlabel = gen_new_label(); | |
d9ba4830 | 6638 | gen_test_cc(cond ^ 1, s->condlabel); |
9ee6e8bb PB |
6639 | s->condjmp = 1; |
6640 | } | |
6641 | if ((insn & 0x0f900000) == 0x03000000) { | |
6642 | if ((insn & (1 << 21)) == 0) { | |
6643 | ARCH(6T2); | |
6644 | rd = (insn >> 12) & 0xf; | |
6645 | val = ((insn >> 4) & 0xf000) | (insn & 0xfff); | |
6646 | if ((insn & (1 << 22)) == 0) { | |
6647 | /* MOVW */ | |
7d1b0095 | 6648 | tmp = tcg_temp_new_i32(); |
5e3f878a | 6649 | tcg_gen_movi_i32(tmp, val); |
9ee6e8bb PB |
6650 | } else { |
6651 | /* MOVT */ | |
5e3f878a | 6652 | tmp = load_reg(s, rd); |
86831435 | 6653 | tcg_gen_ext16u_i32(tmp, tmp); |
5e3f878a | 6654 | tcg_gen_ori_i32(tmp, tmp, val << 16); |
9ee6e8bb | 6655 | } |
5e3f878a | 6656 | store_reg(s, rd, tmp); |
9ee6e8bb PB |
6657 | } else { |
6658 | if (((insn >> 12) & 0xf) != 0xf) | |
6659 | goto illegal_op; | |
6660 | if (((insn >> 16) & 0xf) == 0) { | |
6661 | gen_nop_hint(s, insn & 0xff); | |
6662 | } else { | |
6663 | /* CPSR = immediate */ | |
6664 | val = insn & 0xff; | |
6665 | shift = ((insn >> 8) & 0xf) * 2; | |
6666 | if (shift) | |
6667 | val = (val >> shift) | (val << (32 - shift)); | |
9ee6e8bb | 6668 | i = ((insn & (1 << 22)) != 0); |
2fbac54b | 6669 | if (gen_set_psr_im(s, msr_mask(env, s, (insn >> 16) & 0xf, i), i, val)) |
9ee6e8bb PB |
6670 | goto illegal_op; |
6671 | } | |
6672 | } | |
6673 | } else if ((insn & 0x0f900000) == 0x01000000 | |
6674 | && (insn & 0x00000090) != 0x00000090) { | |
6675 | /* miscellaneous instructions */ | |
6676 | op1 = (insn >> 21) & 3; | |
6677 | sh = (insn >> 4) & 0xf; | |
6678 | rm = insn & 0xf; | |
6679 | switch (sh) { | |
6680 | case 0x0: /* move program status register */ | |
6681 | if (op1 & 1) { | |
6682 | /* PSR = reg */ | |
2fbac54b | 6683 | tmp = load_reg(s, rm); |
9ee6e8bb | 6684 | i = ((op1 & 2) != 0); |
2fbac54b | 6685 | if (gen_set_psr(s, msr_mask(env, s, (insn >> 16) & 0xf, i), i, tmp)) |
9ee6e8bb PB |
6686 | goto illegal_op; |
6687 | } else { | |
6688 | /* reg = PSR */ | |
6689 | rd = (insn >> 12) & 0xf; | |
6690 | if (op1 & 2) { | |
6691 | if (IS_USER(s)) | |
6692 | goto illegal_op; | |
d9ba4830 | 6693 | tmp = load_cpu_field(spsr); |
9ee6e8bb | 6694 | } else { |
7d1b0095 | 6695 | tmp = tcg_temp_new_i32(); |
d9ba4830 | 6696 | gen_helper_cpsr_read(tmp); |
9ee6e8bb | 6697 | } |
d9ba4830 | 6698 | store_reg(s, rd, tmp); |
9ee6e8bb PB |
6699 | } |
6700 | break; | |
6701 | case 0x1: | |
6702 | if (op1 == 1) { | |
6703 | /* branch/exchange thumb (bx). */ | |
be5e7a76 | 6704 | ARCH(4T); |
d9ba4830 PB |
6705 | tmp = load_reg(s, rm); |
6706 | gen_bx(s, tmp); | |
9ee6e8bb PB |
6707 | } else if (op1 == 3) { |
6708 | /* clz */ | |
be5e7a76 | 6709 | ARCH(5); |
9ee6e8bb | 6710 | rd = (insn >> 12) & 0xf; |
1497c961 PB |
6711 | tmp = load_reg(s, rm); |
6712 | gen_helper_clz(tmp, tmp); | |
6713 | store_reg(s, rd, tmp); | |
9ee6e8bb PB |
6714 | } else { |
6715 | goto illegal_op; | |
6716 | } | |
6717 | break; | |
6718 | case 0x2: | |
6719 | if (op1 == 1) { | |
6720 | ARCH(5J); /* bxj */ | |
6721 | /* Trivial implementation equivalent to bx. */ | |
d9ba4830 PB |
6722 | tmp = load_reg(s, rm); |
6723 | gen_bx(s, tmp); | |
9ee6e8bb PB |
6724 | } else { |
6725 | goto illegal_op; | |
6726 | } | |
6727 | break; | |
6728 | case 0x3: | |
6729 | if (op1 != 1) | |
6730 | goto illegal_op; | |
6731 | ||
be5e7a76 | 6732 | ARCH(5); |
9ee6e8bb | 6733 | /* branch link/exchange thumb (blx) */ |
d9ba4830 | 6734 | tmp = load_reg(s, rm); |
7d1b0095 | 6735 | tmp2 = tcg_temp_new_i32(); |
d9ba4830 PB |
6736 | tcg_gen_movi_i32(tmp2, s->pc); |
6737 | store_reg(s, 14, tmp2); | |
6738 | gen_bx(s, tmp); | |
9ee6e8bb PB |
6739 | break; |
6740 | case 0x5: /* saturating add/subtract */ | |
be5e7a76 | 6741 | ARCH(5TE); |
9ee6e8bb PB |
6742 | rd = (insn >> 12) & 0xf; |
6743 | rn = (insn >> 16) & 0xf; | |
b40d0353 | 6744 | tmp = load_reg(s, rm); |
5e3f878a | 6745 | tmp2 = load_reg(s, rn); |
9ee6e8bb | 6746 | if (op1 & 2) |
5e3f878a | 6747 | gen_helper_double_saturate(tmp2, tmp2); |
9ee6e8bb | 6748 | if (op1 & 1) |
5e3f878a | 6749 | gen_helper_sub_saturate(tmp, tmp, tmp2); |
9ee6e8bb | 6750 | else |
5e3f878a | 6751 | gen_helper_add_saturate(tmp, tmp, tmp2); |
7d1b0095 | 6752 | tcg_temp_free_i32(tmp2); |
5e3f878a | 6753 | store_reg(s, rd, tmp); |
9ee6e8bb | 6754 | break; |
49e14940 AL |
6755 | case 7: |
6756 | /* SMC instruction (op1 == 3) | |
6757 | and undefined instructions (op1 == 0 || op1 == 2) | |
6758 | will trap */ | |
6759 | if (op1 != 1) { | |
6760 | goto illegal_op; | |
6761 | } | |
6762 | /* bkpt */ | |
be5e7a76 | 6763 | ARCH(5); |
bc4a0de0 | 6764 | gen_exception_insn(s, 4, EXCP_BKPT); |
9ee6e8bb PB |
6765 | break; |
6766 | case 0x8: /* signed multiply */ | |
6767 | case 0xa: | |
6768 | case 0xc: | |
6769 | case 0xe: | |
be5e7a76 | 6770 | ARCH(5TE); |
9ee6e8bb PB |
6771 | rs = (insn >> 8) & 0xf; |
6772 | rn = (insn >> 12) & 0xf; | |
6773 | rd = (insn >> 16) & 0xf; | |
6774 | if (op1 == 1) { | |
6775 | /* (32 * 16) >> 16 */ | |
5e3f878a PB |
6776 | tmp = load_reg(s, rm); |
6777 | tmp2 = load_reg(s, rs); | |
9ee6e8bb | 6778 | if (sh & 4) |
5e3f878a | 6779 | tcg_gen_sari_i32(tmp2, tmp2, 16); |
9ee6e8bb | 6780 | else |
5e3f878a | 6781 | gen_sxth(tmp2); |
a7812ae4 PB |
6782 | tmp64 = gen_muls_i64_i32(tmp, tmp2); |
6783 | tcg_gen_shri_i64(tmp64, tmp64, 16); | |
7d1b0095 | 6784 | tmp = tcg_temp_new_i32(); |
a7812ae4 | 6785 | tcg_gen_trunc_i64_i32(tmp, tmp64); |
b75263d6 | 6786 | tcg_temp_free_i64(tmp64); |
9ee6e8bb | 6787 | if ((sh & 2) == 0) { |
5e3f878a PB |
6788 | tmp2 = load_reg(s, rn); |
6789 | gen_helper_add_setq(tmp, tmp, tmp2); | |
7d1b0095 | 6790 | tcg_temp_free_i32(tmp2); |
9ee6e8bb | 6791 | } |
5e3f878a | 6792 | store_reg(s, rd, tmp); |
9ee6e8bb PB |
6793 | } else { |
6794 | /* 16 * 16 */ | |
5e3f878a PB |
6795 | tmp = load_reg(s, rm); |
6796 | tmp2 = load_reg(s, rs); | |
6797 | gen_mulxy(tmp, tmp2, sh & 2, sh & 4); | |
7d1b0095 | 6798 | tcg_temp_free_i32(tmp2); |
9ee6e8bb | 6799 | if (op1 == 2) { |
a7812ae4 PB |
6800 | tmp64 = tcg_temp_new_i64(); |
6801 | tcg_gen_ext_i32_i64(tmp64, tmp); | |
7d1b0095 | 6802 | tcg_temp_free_i32(tmp); |
a7812ae4 PB |
6803 | gen_addq(s, tmp64, rn, rd); |
6804 | gen_storeq_reg(s, rn, rd, tmp64); | |
b75263d6 | 6805 | tcg_temp_free_i64(tmp64); |
9ee6e8bb PB |
6806 | } else { |
6807 | if (op1 == 0) { | |
5e3f878a PB |
6808 | tmp2 = load_reg(s, rn); |
6809 | gen_helper_add_setq(tmp, tmp, tmp2); | |
7d1b0095 | 6810 | tcg_temp_free_i32(tmp2); |
9ee6e8bb | 6811 | } |
5e3f878a | 6812 | store_reg(s, rd, tmp); |
9ee6e8bb PB |
6813 | } |
6814 | } | |
6815 | break; | |
6816 | default: | |
6817 | goto illegal_op; | |
6818 | } | |
6819 | } else if (((insn & 0x0e000000) == 0 && | |
6820 | (insn & 0x00000090) != 0x90) || | |
6821 | ((insn & 0x0e000000) == (1 << 25))) { | |
6822 | int set_cc, logic_cc, shiftop; | |
6823 | ||
6824 | op1 = (insn >> 21) & 0xf; | |
6825 | set_cc = (insn >> 20) & 1; | |
6826 | logic_cc = table_logic_cc[op1] & set_cc; | |
6827 | ||
6828 | /* data processing instruction */ | |
6829 | if (insn & (1 << 25)) { | |
6830 | /* immediate operand */ | |
6831 | val = insn & 0xff; | |
6832 | shift = ((insn >> 8) & 0xf) * 2; | |
e9bb4aa9 | 6833 | if (shift) { |
9ee6e8bb | 6834 | val = (val >> shift) | (val << (32 - shift)); |
e9bb4aa9 | 6835 | } |
7d1b0095 | 6836 | tmp2 = tcg_temp_new_i32(); |
e9bb4aa9 JR |
6837 | tcg_gen_movi_i32(tmp2, val); |
6838 | if (logic_cc && shift) { | |
6839 | gen_set_CF_bit31(tmp2); | |
6840 | } | |
9ee6e8bb PB |
6841 | } else { |
6842 | /* register */ | |
6843 | rm = (insn) & 0xf; | |
e9bb4aa9 | 6844 | tmp2 = load_reg(s, rm); |
9ee6e8bb PB |
6845 | shiftop = (insn >> 5) & 3; |
6846 | if (!(insn & (1 << 4))) { | |
6847 | shift = (insn >> 7) & 0x1f; | |
e9bb4aa9 | 6848 | gen_arm_shift_im(tmp2, shiftop, shift, logic_cc); |
9ee6e8bb PB |
6849 | } else { |
6850 | rs = (insn >> 8) & 0xf; | |
8984bd2e | 6851 | tmp = load_reg(s, rs); |
e9bb4aa9 | 6852 | gen_arm_shift_reg(tmp2, shiftop, tmp, logic_cc); |
9ee6e8bb PB |
6853 | } |
6854 | } | |
6855 | if (op1 != 0x0f && op1 != 0x0d) { | |
6856 | rn = (insn >> 16) & 0xf; | |
e9bb4aa9 JR |
6857 | tmp = load_reg(s, rn); |
6858 | } else { | |
6859 | TCGV_UNUSED(tmp); | |
9ee6e8bb PB |
6860 | } |
6861 | rd = (insn >> 12) & 0xf; | |
6862 | switch(op1) { | |
6863 | case 0x00: | |
e9bb4aa9 JR |
6864 | tcg_gen_and_i32(tmp, tmp, tmp2); |
6865 | if (logic_cc) { | |
6866 | gen_logic_CC(tmp); | |
6867 | } | |
21aeb343 | 6868 | store_reg_bx(env, s, rd, tmp); |
9ee6e8bb PB |
6869 | break; |
6870 | case 0x01: | |
e9bb4aa9 JR |
6871 | tcg_gen_xor_i32(tmp, tmp, tmp2); |
6872 | if (logic_cc) { | |
6873 | gen_logic_CC(tmp); | |
6874 | } | |
21aeb343 | 6875 | store_reg_bx(env, s, rd, tmp); |
9ee6e8bb PB |
6876 | break; |
6877 | case 0x02: | |
6878 | if (set_cc && rd == 15) { | |
6879 | /* SUBS r15, ... is used for exception return. */ | |
e9bb4aa9 | 6880 | if (IS_USER(s)) { |
9ee6e8bb | 6881 | goto illegal_op; |
e9bb4aa9 JR |
6882 | } |
6883 | gen_helper_sub_cc(tmp, tmp, tmp2); | |
6884 | gen_exception_return(s, tmp); | |
9ee6e8bb | 6885 | } else { |
e9bb4aa9 JR |
6886 | if (set_cc) { |
6887 | gen_helper_sub_cc(tmp, tmp, tmp2); | |
6888 | } else { | |
6889 | tcg_gen_sub_i32(tmp, tmp, tmp2); | |
6890 | } | |
21aeb343 | 6891 | store_reg_bx(env, s, rd, tmp); |
9ee6e8bb PB |
6892 | } |
6893 | break; | |
6894 | case 0x03: | |
e9bb4aa9 JR |
6895 | if (set_cc) { |
6896 | gen_helper_sub_cc(tmp, tmp2, tmp); | |
6897 | } else { | |
6898 | tcg_gen_sub_i32(tmp, tmp2, tmp); | |
6899 | } | |
21aeb343 | 6900 | store_reg_bx(env, s, rd, tmp); |
9ee6e8bb PB |
6901 | break; |
6902 | case 0x04: | |
e9bb4aa9 JR |
6903 | if (set_cc) { |
6904 | gen_helper_add_cc(tmp, tmp, tmp2); | |
6905 | } else { | |
6906 | tcg_gen_add_i32(tmp, tmp, tmp2); | |
6907 | } | |
21aeb343 | 6908 | store_reg_bx(env, s, rd, tmp); |
9ee6e8bb PB |
6909 | break; |
6910 | case 0x05: | |
e9bb4aa9 JR |
6911 | if (set_cc) { |
6912 | gen_helper_adc_cc(tmp, tmp, tmp2); | |
6913 | } else { | |
6914 | gen_add_carry(tmp, tmp, tmp2); | |
6915 | } | |
21aeb343 | 6916 | store_reg_bx(env, s, rd, tmp); |
9ee6e8bb PB |
6917 | break; |
6918 | case 0x06: | |
e9bb4aa9 JR |
6919 | if (set_cc) { |
6920 | gen_helper_sbc_cc(tmp, tmp, tmp2); | |
6921 | } else { | |
6922 | gen_sub_carry(tmp, tmp, tmp2); | |
6923 | } | |
21aeb343 | 6924 | store_reg_bx(env, s, rd, tmp); |
9ee6e8bb PB |
6925 | break; |
6926 | case 0x07: | |
e9bb4aa9 JR |
6927 | if (set_cc) { |
6928 | gen_helper_sbc_cc(tmp, tmp2, tmp); | |
6929 | } else { | |
6930 | gen_sub_carry(tmp, tmp2, tmp); | |
6931 | } | |
21aeb343 | 6932 | store_reg_bx(env, s, rd, tmp); |
9ee6e8bb PB |
6933 | break; |
6934 | case 0x08: | |
6935 | if (set_cc) { | |
e9bb4aa9 JR |
6936 | tcg_gen_and_i32(tmp, tmp, tmp2); |
6937 | gen_logic_CC(tmp); | |
9ee6e8bb | 6938 | } |
7d1b0095 | 6939 | tcg_temp_free_i32(tmp); |
9ee6e8bb PB |
6940 | break; |
6941 | case 0x09: | |
6942 | if (set_cc) { | |
e9bb4aa9 JR |
6943 | tcg_gen_xor_i32(tmp, tmp, tmp2); |
6944 | gen_logic_CC(tmp); | |
9ee6e8bb | 6945 | } |
7d1b0095 | 6946 | tcg_temp_free_i32(tmp); |
9ee6e8bb PB |
6947 | break; |
6948 | case 0x0a: | |
6949 | if (set_cc) { | |
e9bb4aa9 | 6950 | gen_helper_sub_cc(tmp, tmp, tmp2); |
9ee6e8bb | 6951 | } |
7d1b0095 | 6952 | tcg_temp_free_i32(tmp); |
9ee6e8bb PB |
6953 | break; |
6954 | case 0x0b: | |
6955 | if (set_cc) { | |
e9bb4aa9 | 6956 | gen_helper_add_cc(tmp, tmp, tmp2); |
9ee6e8bb | 6957 | } |
7d1b0095 | 6958 | tcg_temp_free_i32(tmp); |
9ee6e8bb PB |
6959 | break; |
6960 | case 0x0c: | |
e9bb4aa9 JR |
6961 | tcg_gen_or_i32(tmp, tmp, tmp2); |
6962 | if (logic_cc) { | |
6963 | gen_logic_CC(tmp); | |
6964 | } | |
21aeb343 | 6965 | store_reg_bx(env, s, rd, tmp); |
9ee6e8bb PB |
6966 | break; |
6967 | case 0x0d: | |
6968 | if (logic_cc && rd == 15) { | |
6969 | /* MOVS r15, ... is used for exception return. */ | |
e9bb4aa9 | 6970 | if (IS_USER(s)) { |
9ee6e8bb | 6971 | goto illegal_op; |
e9bb4aa9 JR |
6972 | } |
6973 | gen_exception_return(s, tmp2); | |
9ee6e8bb | 6974 | } else { |
e9bb4aa9 JR |
6975 | if (logic_cc) { |
6976 | gen_logic_CC(tmp2); | |
6977 | } | |
21aeb343 | 6978 | store_reg_bx(env, s, rd, tmp2); |
9ee6e8bb PB |
6979 | } |
6980 | break; | |
6981 | case 0x0e: | |
f669df27 | 6982 | tcg_gen_andc_i32(tmp, tmp, tmp2); |
e9bb4aa9 JR |
6983 | if (logic_cc) { |
6984 | gen_logic_CC(tmp); | |
6985 | } | |
21aeb343 | 6986 | store_reg_bx(env, s, rd, tmp); |
9ee6e8bb PB |
6987 | break; |
6988 | default: | |
6989 | case 0x0f: | |
e9bb4aa9 JR |
6990 | tcg_gen_not_i32(tmp2, tmp2); |
6991 | if (logic_cc) { | |
6992 | gen_logic_CC(tmp2); | |
6993 | } | |
21aeb343 | 6994 | store_reg_bx(env, s, rd, tmp2); |
9ee6e8bb PB |
6995 | break; |
6996 | } | |
e9bb4aa9 | 6997 | if (op1 != 0x0f && op1 != 0x0d) { |
7d1b0095 | 6998 | tcg_temp_free_i32(tmp2); |
e9bb4aa9 | 6999 | } |
9ee6e8bb PB |
7000 | } else { |
7001 | /* other instructions */ | |
7002 | op1 = (insn >> 24) & 0xf; | |
7003 | switch(op1) { | |
7004 | case 0x0: | |
7005 | case 0x1: | |
7006 | /* multiplies, extra load/stores */ | |
7007 | sh = (insn >> 5) & 3; | |
7008 | if (sh == 0) { | |
7009 | if (op1 == 0x0) { | |
7010 | rd = (insn >> 16) & 0xf; | |
7011 | rn = (insn >> 12) & 0xf; | |
7012 | rs = (insn >> 8) & 0xf; | |
7013 | rm = (insn) & 0xf; | |
7014 | op1 = (insn >> 20) & 0xf; | |
7015 | switch (op1) { | |
7016 | case 0: case 1: case 2: case 3: case 6: | |
7017 | /* 32 bit mul */ | |
5e3f878a PB |
7018 | tmp = load_reg(s, rs); |
7019 | tmp2 = load_reg(s, rm); | |
7020 | tcg_gen_mul_i32(tmp, tmp, tmp2); | |
7d1b0095 | 7021 | tcg_temp_free_i32(tmp2); |
9ee6e8bb PB |
7022 | if (insn & (1 << 22)) { |
7023 | /* Subtract (mls) */ | |
7024 | ARCH(6T2); | |
5e3f878a PB |
7025 | tmp2 = load_reg(s, rn); |
7026 | tcg_gen_sub_i32(tmp, tmp2, tmp); | |
7d1b0095 | 7027 | tcg_temp_free_i32(tmp2); |
9ee6e8bb PB |
7028 | } else if (insn & (1 << 21)) { |
7029 | /* Add */ | |
5e3f878a PB |
7030 | tmp2 = load_reg(s, rn); |
7031 | tcg_gen_add_i32(tmp, tmp, tmp2); | |
7d1b0095 | 7032 | tcg_temp_free_i32(tmp2); |
9ee6e8bb PB |
7033 | } |
7034 | if (insn & (1 << 20)) | |
5e3f878a PB |
7035 | gen_logic_CC(tmp); |
7036 | store_reg(s, rd, tmp); | |
9ee6e8bb | 7037 | break; |
8aac08b1 AJ |
7038 | case 4: |
7039 | /* 64 bit mul double accumulate (UMAAL) */ | |
7040 | ARCH(6); | |
7041 | tmp = load_reg(s, rs); | |
7042 | tmp2 = load_reg(s, rm); | |
7043 | tmp64 = gen_mulu_i64_i32(tmp, tmp2); | |
7044 | gen_addq_lo(s, tmp64, rn); | |
7045 | gen_addq_lo(s, tmp64, rd); | |
7046 | gen_storeq_reg(s, rn, rd, tmp64); | |
7047 | tcg_temp_free_i64(tmp64); | |
7048 | break; | |
7049 | case 8: case 9: case 10: case 11: | |
7050 | case 12: case 13: case 14: case 15: | |
7051 | /* 64 bit mul: UMULL, UMLAL, SMULL, SMLAL. */ | |
5e3f878a PB |
7052 | tmp = load_reg(s, rs); |
7053 | tmp2 = load_reg(s, rm); | |
8aac08b1 | 7054 | if (insn & (1 << 22)) { |
a7812ae4 | 7055 | tmp64 = gen_muls_i64_i32(tmp, tmp2); |
8aac08b1 | 7056 | } else { |
a7812ae4 | 7057 | tmp64 = gen_mulu_i64_i32(tmp, tmp2); |
8aac08b1 AJ |
7058 | } |
7059 | if (insn & (1 << 21)) { /* mult accumulate */ | |
a7812ae4 | 7060 | gen_addq(s, tmp64, rn, rd); |
9ee6e8bb | 7061 | } |
8aac08b1 | 7062 | if (insn & (1 << 20)) { |
a7812ae4 | 7063 | gen_logicq_cc(tmp64); |
8aac08b1 | 7064 | } |
a7812ae4 | 7065 | gen_storeq_reg(s, rn, rd, tmp64); |
b75263d6 | 7066 | tcg_temp_free_i64(tmp64); |
9ee6e8bb | 7067 | break; |
8aac08b1 AJ |
7068 | default: |
7069 | goto illegal_op; | |
9ee6e8bb PB |
7070 | } |
7071 | } else { | |
7072 | rn = (insn >> 16) & 0xf; | |
7073 | rd = (insn >> 12) & 0xf; | |
7074 | if (insn & (1 << 23)) { | |
7075 | /* load/store exclusive */ | |
86753403 PB |
7076 | op1 = (insn >> 21) & 0x3; |
7077 | if (op1) | |
a47f43d2 | 7078 | ARCH(6K); |
86753403 PB |
7079 | else |
7080 | ARCH(6); | |
3174f8e9 | 7081 | addr = tcg_temp_local_new_i32(); |
98a46317 | 7082 | load_reg_var(s, addr, rn); |
9ee6e8bb | 7083 | if (insn & (1 << 20)) { |
86753403 PB |
7084 | switch (op1) { |
7085 | case 0: /* ldrex */ | |
426f5abc | 7086 | gen_load_exclusive(s, rd, 15, addr, 2); |
86753403 PB |
7087 | break; |
7088 | case 1: /* ldrexd */ | |
426f5abc | 7089 | gen_load_exclusive(s, rd, rd + 1, addr, 3); |
86753403 PB |
7090 | break; |
7091 | case 2: /* ldrexb */ | |
426f5abc | 7092 | gen_load_exclusive(s, rd, 15, addr, 0); |
86753403 PB |
7093 | break; |
7094 | case 3: /* ldrexh */ | |
426f5abc | 7095 | gen_load_exclusive(s, rd, 15, addr, 1); |
86753403 PB |
7096 | break; |
7097 | default: | |
7098 | abort(); | |
7099 | } | |
9ee6e8bb PB |
7100 | } else { |
7101 | rm = insn & 0xf; | |
86753403 PB |
7102 | switch (op1) { |
7103 | case 0: /* strex */ | |
426f5abc | 7104 | gen_store_exclusive(s, rd, rm, 15, addr, 2); |
86753403 PB |
7105 | break; |
7106 | case 1: /* strexd */ | |
502e64fe | 7107 | gen_store_exclusive(s, rd, rm, rm + 1, addr, 3); |
86753403 PB |
7108 | break; |
7109 | case 2: /* strexb */ | |
426f5abc | 7110 | gen_store_exclusive(s, rd, rm, 15, addr, 0); |
86753403 PB |
7111 | break; |
7112 | case 3: /* strexh */ | |
426f5abc | 7113 | gen_store_exclusive(s, rd, rm, 15, addr, 1); |
86753403 PB |
7114 | break; |
7115 | default: | |
7116 | abort(); | |
7117 | } | |
9ee6e8bb | 7118 | } |
3174f8e9 | 7119 | tcg_temp_free(addr); |
9ee6e8bb PB |
7120 | } else { |
7121 | /* SWP instruction */ | |
7122 | rm = (insn) & 0xf; | |
7123 | ||
8984bd2e PB |
7124 | /* ??? This is not really atomic. However we know |
7125 | we never have multiple CPUs running in parallel, | |
7126 | so it is good enough. */ | |
7127 | addr = load_reg(s, rn); | |
7128 | tmp = load_reg(s, rm); | |
9ee6e8bb | 7129 | if (insn & (1 << 22)) { |
8984bd2e PB |
7130 | tmp2 = gen_ld8u(addr, IS_USER(s)); |
7131 | gen_st8(tmp, addr, IS_USER(s)); | |
9ee6e8bb | 7132 | } else { |
8984bd2e PB |
7133 | tmp2 = gen_ld32(addr, IS_USER(s)); |
7134 | gen_st32(tmp, addr, IS_USER(s)); | |
9ee6e8bb | 7135 | } |
7d1b0095 | 7136 | tcg_temp_free_i32(addr); |
8984bd2e | 7137 | store_reg(s, rd, tmp2); |
9ee6e8bb PB |
7138 | } |
7139 | } | |
7140 | } else { | |
7141 | int address_offset; | |
7142 | int load; | |
7143 | /* Misc load/store */ | |
7144 | rn = (insn >> 16) & 0xf; | |
7145 | rd = (insn >> 12) & 0xf; | |
b0109805 | 7146 | addr = load_reg(s, rn); |
9ee6e8bb | 7147 | if (insn & (1 << 24)) |
b0109805 | 7148 | gen_add_datah_offset(s, insn, 0, addr); |
9ee6e8bb PB |
7149 | address_offset = 0; |
7150 | if (insn & (1 << 20)) { | |
7151 | /* load */ | |
7152 | switch(sh) { | |
7153 | case 1: | |
b0109805 | 7154 | tmp = gen_ld16u(addr, IS_USER(s)); |
9ee6e8bb PB |
7155 | break; |
7156 | case 2: | |
b0109805 | 7157 | tmp = gen_ld8s(addr, IS_USER(s)); |
9ee6e8bb PB |
7158 | break; |
7159 | default: | |
7160 | case 3: | |
b0109805 | 7161 | tmp = gen_ld16s(addr, IS_USER(s)); |
9ee6e8bb PB |
7162 | break; |
7163 | } | |
7164 | load = 1; | |
7165 | } else if (sh & 2) { | |
be5e7a76 | 7166 | ARCH(5TE); |
9ee6e8bb PB |
7167 | /* doubleword */ |
7168 | if (sh & 1) { | |
7169 | /* store */ | |
b0109805 PB |
7170 | tmp = load_reg(s, rd); |
7171 | gen_st32(tmp, addr, IS_USER(s)); | |
7172 | tcg_gen_addi_i32(addr, addr, 4); | |
7173 | tmp = load_reg(s, rd + 1); | |
7174 | gen_st32(tmp, addr, IS_USER(s)); | |
9ee6e8bb PB |
7175 | load = 0; |
7176 | } else { | |
7177 | /* load */ | |
b0109805 PB |
7178 | tmp = gen_ld32(addr, IS_USER(s)); |
7179 | store_reg(s, rd, tmp); | |
7180 | tcg_gen_addi_i32(addr, addr, 4); | |
7181 | tmp = gen_ld32(addr, IS_USER(s)); | |
9ee6e8bb PB |
7182 | rd++; |
7183 | load = 1; | |
7184 | } | |
7185 | address_offset = -4; | |
7186 | } else { | |
7187 | /* store */ | |
b0109805 PB |
7188 | tmp = load_reg(s, rd); |
7189 | gen_st16(tmp, addr, IS_USER(s)); | |
9ee6e8bb PB |
7190 | load = 0; |
7191 | } | |
7192 | /* Perform base writeback before the loaded value to | |
7193 | ensure correct behavior with overlapping index registers. | |
7194 | ldrd with base writeback is is undefined if the | |
7195 | destination and index registers overlap. */ | |
7196 | if (!(insn & (1 << 24))) { | |
b0109805 PB |
7197 | gen_add_datah_offset(s, insn, address_offset, addr); |
7198 | store_reg(s, rn, addr); | |
9ee6e8bb PB |
7199 | } else if (insn & (1 << 21)) { |
7200 | if (address_offset) | |
b0109805 PB |
7201 | tcg_gen_addi_i32(addr, addr, address_offset); |
7202 | store_reg(s, rn, addr); | |
7203 | } else { | |
7d1b0095 | 7204 | tcg_temp_free_i32(addr); |
9ee6e8bb PB |
7205 | } |
7206 | if (load) { | |
7207 | /* Complete the load. */ | |
b0109805 | 7208 | store_reg(s, rd, tmp); |
9ee6e8bb PB |
7209 | } |
7210 | } | |
7211 | break; | |
7212 | case 0x4: | |
7213 | case 0x5: | |
7214 | goto do_ldst; | |
7215 | case 0x6: | |
7216 | case 0x7: | |
7217 | if (insn & (1 << 4)) { | |
7218 | ARCH(6); | |
7219 | /* Armv6 Media instructions. */ | |
7220 | rm = insn & 0xf; | |
7221 | rn = (insn >> 16) & 0xf; | |
2c0262af | 7222 | rd = (insn >> 12) & 0xf; |
9ee6e8bb PB |
7223 | rs = (insn >> 8) & 0xf; |
7224 | switch ((insn >> 23) & 3) { | |
7225 | case 0: /* Parallel add/subtract. */ | |
7226 | op1 = (insn >> 20) & 7; | |
6ddbc6e4 PB |
7227 | tmp = load_reg(s, rn); |
7228 | tmp2 = load_reg(s, rm); | |
9ee6e8bb PB |
7229 | sh = (insn >> 5) & 7; |
7230 | if ((op1 & 3) == 0 || sh == 5 || sh == 6) | |
7231 | goto illegal_op; | |
6ddbc6e4 | 7232 | gen_arm_parallel_addsub(op1, sh, tmp, tmp2); |
7d1b0095 | 7233 | tcg_temp_free_i32(tmp2); |
6ddbc6e4 | 7234 | store_reg(s, rd, tmp); |
9ee6e8bb PB |
7235 | break; |
7236 | case 1: | |
7237 | if ((insn & 0x00700020) == 0) { | |
6c95676b | 7238 | /* Halfword pack. */ |
3670669c PB |
7239 | tmp = load_reg(s, rn); |
7240 | tmp2 = load_reg(s, rm); | |
9ee6e8bb | 7241 | shift = (insn >> 7) & 0x1f; |
3670669c PB |
7242 | if (insn & (1 << 6)) { |
7243 | /* pkhtb */ | |
22478e79 AZ |
7244 | if (shift == 0) |
7245 | shift = 31; | |
7246 | tcg_gen_sari_i32(tmp2, tmp2, shift); | |
3670669c | 7247 | tcg_gen_andi_i32(tmp, tmp, 0xffff0000); |
86831435 | 7248 | tcg_gen_ext16u_i32(tmp2, tmp2); |
3670669c PB |
7249 | } else { |
7250 | /* pkhbt */ | |
22478e79 AZ |
7251 | if (shift) |
7252 | tcg_gen_shli_i32(tmp2, tmp2, shift); | |
86831435 | 7253 | tcg_gen_ext16u_i32(tmp, tmp); |
3670669c PB |
7254 | tcg_gen_andi_i32(tmp2, tmp2, 0xffff0000); |
7255 | } | |
7256 | tcg_gen_or_i32(tmp, tmp, tmp2); | |
7d1b0095 | 7257 | tcg_temp_free_i32(tmp2); |
3670669c | 7258 | store_reg(s, rd, tmp); |
9ee6e8bb PB |
7259 | } else if ((insn & 0x00200020) == 0x00200000) { |
7260 | /* [us]sat */ | |
6ddbc6e4 | 7261 | tmp = load_reg(s, rm); |
9ee6e8bb PB |
7262 | shift = (insn >> 7) & 0x1f; |
7263 | if (insn & (1 << 6)) { | |
7264 | if (shift == 0) | |
7265 | shift = 31; | |
6ddbc6e4 | 7266 | tcg_gen_sari_i32(tmp, tmp, shift); |
9ee6e8bb | 7267 | } else { |
6ddbc6e4 | 7268 | tcg_gen_shli_i32(tmp, tmp, shift); |
9ee6e8bb PB |
7269 | } |
7270 | sh = (insn >> 16) & 0x1f; | |
40d3c433 CL |
7271 | tmp2 = tcg_const_i32(sh); |
7272 | if (insn & (1 << 22)) | |
7273 | gen_helper_usat(tmp, tmp, tmp2); | |
7274 | else | |
7275 | gen_helper_ssat(tmp, tmp, tmp2); | |
7276 | tcg_temp_free_i32(tmp2); | |
6ddbc6e4 | 7277 | store_reg(s, rd, tmp); |
9ee6e8bb PB |
7278 | } else if ((insn & 0x00300fe0) == 0x00200f20) { |
7279 | /* [us]sat16 */ | |
6ddbc6e4 | 7280 | tmp = load_reg(s, rm); |
9ee6e8bb | 7281 | sh = (insn >> 16) & 0x1f; |
40d3c433 CL |
7282 | tmp2 = tcg_const_i32(sh); |
7283 | if (insn & (1 << 22)) | |
7284 | gen_helper_usat16(tmp, tmp, tmp2); | |
7285 | else | |
7286 | gen_helper_ssat16(tmp, tmp, tmp2); | |
7287 | tcg_temp_free_i32(tmp2); | |
6ddbc6e4 | 7288 | store_reg(s, rd, tmp); |
9ee6e8bb PB |
7289 | } else if ((insn & 0x00700fe0) == 0x00000fa0) { |
7290 | /* Select bytes. */ | |
6ddbc6e4 PB |
7291 | tmp = load_reg(s, rn); |
7292 | tmp2 = load_reg(s, rm); | |
7d1b0095 | 7293 | tmp3 = tcg_temp_new_i32(); |
6ddbc6e4 PB |
7294 | tcg_gen_ld_i32(tmp3, cpu_env, offsetof(CPUState, GE)); |
7295 | gen_helper_sel_flags(tmp, tmp3, tmp, tmp2); | |
7d1b0095 PM |
7296 | tcg_temp_free_i32(tmp3); |
7297 | tcg_temp_free_i32(tmp2); | |
6ddbc6e4 | 7298 | store_reg(s, rd, tmp); |
9ee6e8bb | 7299 | } else if ((insn & 0x000003e0) == 0x00000060) { |
5e3f878a | 7300 | tmp = load_reg(s, rm); |
9ee6e8bb PB |
7301 | shift = (insn >> 10) & 3; |
7302 | /* ??? In many cases it's not neccessary to do a | |
7303 | rotate, a shift is sufficient. */ | |
7304 | if (shift != 0) | |
f669df27 | 7305 | tcg_gen_rotri_i32(tmp, tmp, shift * 8); |
9ee6e8bb PB |
7306 | op1 = (insn >> 20) & 7; |
7307 | switch (op1) { | |
5e3f878a PB |
7308 | case 0: gen_sxtb16(tmp); break; |
7309 | case 2: gen_sxtb(tmp); break; | |
7310 | case 3: gen_sxth(tmp); break; | |
7311 | case 4: gen_uxtb16(tmp); break; | |
7312 | case 6: gen_uxtb(tmp); break; | |
7313 | case 7: gen_uxth(tmp); break; | |
9ee6e8bb PB |
7314 | default: goto illegal_op; |
7315 | } | |
7316 | if (rn != 15) { | |
5e3f878a | 7317 | tmp2 = load_reg(s, rn); |
9ee6e8bb | 7318 | if ((op1 & 3) == 0) { |
5e3f878a | 7319 | gen_add16(tmp, tmp2); |
9ee6e8bb | 7320 | } else { |
5e3f878a | 7321 | tcg_gen_add_i32(tmp, tmp, tmp2); |
7d1b0095 | 7322 | tcg_temp_free_i32(tmp2); |
9ee6e8bb PB |
7323 | } |
7324 | } | |
6c95676b | 7325 | store_reg(s, rd, tmp); |
9ee6e8bb PB |
7326 | } else if ((insn & 0x003f0f60) == 0x003f0f20) { |
7327 | /* rev */ | |
b0109805 | 7328 | tmp = load_reg(s, rm); |
9ee6e8bb PB |
7329 | if (insn & (1 << 22)) { |
7330 | if (insn & (1 << 7)) { | |
b0109805 | 7331 | gen_revsh(tmp); |
9ee6e8bb PB |
7332 | } else { |
7333 | ARCH(6T2); | |
b0109805 | 7334 | gen_helper_rbit(tmp, tmp); |
9ee6e8bb PB |
7335 | } |
7336 | } else { | |
7337 | if (insn & (1 << 7)) | |
b0109805 | 7338 | gen_rev16(tmp); |
9ee6e8bb | 7339 | else |
66896cb8 | 7340 | tcg_gen_bswap32_i32(tmp, tmp); |
9ee6e8bb | 7341 | } |
b0109805 | 7342 | store_reg(s, rd, tmp); |
9ee6e8bb PB |
7343 | } else { |
7344 | goto illegal_op; | |
7345 | } | |
7346 | break; | |
7347 | case 2: /* Multiplies (Type 3). */ | |
5e3f878a PB |
7348 | tmp = load_reg(s, rm); |
7349 | tmp2 = load_reg(s, rs); | |
9ee6e8bb | 7350 | if (insn & (1 << 20)) { |
838fa72d AJ |
7351 | /* Signed multiply most significant [accumulate]. |
7352 | (SMMUL, SMMLA, SMMLS) */ | |
a7812ae4 | 7353 | tmp64 = gen_muls_i64_i32(tmp, tmp2); |
838fa72d | 7354 | |
955a7dd5 | 7355 | if (rd != 15) { |
838fa72d | 7356 | tmp = load_reg(s, rd); |
9ee6e8bb | 7357 | if (insn & (1 << 6)) { |
838fa72d | 7358 | tmp64 = gen_subq_msw(tmp64, tmp); |
9ee6e8bb | 7359 | } else { |
838fa72d | 7360 | tmp64 = gen_addq_msw(tmp64, tmp); |
9ee6e8bb PB |
7361 | } |
7362 | } | |
838fa72d AJ |
7363 | if (insn & (1 << 5)) { |
7364 | tcg_gen_addi_i64(tmp64, tmp64, 0x80000000u); | |
7365 | } | |
7366 | tcg_gen_shri_i64(tmp64, tmp64, 32); | |
7d1b0095 | 7367 | tmp = tcg_temp_new_i32(); |
838fa72d AJ |
7368 | tcg_gen_trunc_i64_i32(tmp, tmp64); |
7369 | tcg_temp_free_i64(tmp64); | |
955a7dd5 | 7370 | store_reg(s, rn, tmp); |
9ee6e8bb PB |
7371 | } else { |
7372 | if (insn & (1 << 5)) | |
5e3f878a PB |
7373 | gen_swap_half(tmp2); |
7374 | gen_smul_dual(tmp, tmp2); | |
5e3f878a | 7375 | if (insn & (1 << 6)) { |
e1d177b9 | 7376 | /* This subtraction cannot overflow. */ |
5e3f878a PB |
7377 | tcg_gen_sub_i32(tmp, tmp, tmp2); |
7378 | } else { | |
e1d177b9 PM |
7379 | /* This addition cannot overflow 32 bits; |
7380 | * however it may overflow considered as a signed | |
7381 | * operation, in which case we must set the Q flag. | |
7382 | */ | |
7383 | gen_helper_add_setq(tmp, tmp, tmp2); | |
5e3f878a | 7384 | } |
7d1b0095 | 7385 | tcg_temp_free_i32(tmp2); |
9ee6e8bb | 7386 | if (insn & (1 << 22)) { |
5e3f878a | 7387 | /* smlald, smlsld */ |
a7812ae4 PB |
7388 | tmp64 = tcg_temp_new_i64(); |
7389 | tcg_gen_ext_i32_i64(tmp64, tmp); | |
7d1b0095 | 7390 | tcg_temp_free_i32(tmp); |
a7812ae4 PB |
7391 | gen_addq(s, tmp64, rd, rn); |
7392 | gen_storeq_reg(s, rd, rn, tmp64); | |
b75263d6 | 7393 | tcg_temp_free_i64(tmp64); |
9ee6e8bb | 7394 | } else { |
5e3f878a | 7395 | /* smuad, smusd, smlad, smlsd */ |
22478e79 | 7396 | if (rd != 15) |
9ee6e8bb | 7397 | { |
22478e79 | 7398 | tmp2 = load_reg(s, rd); |
5e3f878a | 7399 | gen_helper_add_setq(tmp, tmp, tmp2); |
7d1b0095 | 7400 | tcg_temp_free_i32(tmp2); |
9ee6e8bb | 7401 | } |
22478e79 | 7402 | store_reg(s, rn, tmp); |
9ee6e8bb PB |
7403 | } |
7404 | } | |
7405 | break; | |
7406 | case 3: | |
7407 | op1 = ((insn >> 17) & 0x38) | ((insn >> 5) & 7); | |
7408 | switch (op1) { | |
7409 | case 0: /* Unsigned sum of absolute differences. */ | |
6ddbc6e4 PB |
7410 | ARCH(6); |
7411 | tmp = load_reg(s, rm); | |
7412 | tmp2 = load_reg(s, rs); | |
7413 | gen_helper_usad8(tmp, tmp, tmp2); | |
7d1b0095 | 7414 | tcg_temp_free_i32(tmp2); |
ded9d295 AZ |
7415 | if (rd != 15) { |
7416 | tmp2 = load_reg(s, rd); | |
6ddbc6e4 | 7417 | tcg_gen_add_i32(tmp, tmp, tmp2); |
7d1b0095 | 7418 | tcg_temp_free_i32(tmp2); |
9ee6e8bb | 7419 | } |
ded9d295 | 7420 | store_reg(s, rn, tmp); |
9ee6e8bb PB |
7421 | break; |
7422 | case 0x20: case 0x24: case 0x28: case 0x2c: | |
7423 | /* Bitfield insert/clear. */ | |
7424 | ARCH(6T2); | |
7425 | shift = (insn >> 7) & 0x1f; | |
7426 | i = (insn >> 16) & 0x1f; | |
7427 | i = i + 1 - shift; | |
7428 | if (rm == 15) { | |
7d1b0095 | 7429 | tmp = tcg_temp_new_i32(); |
5e3f878a | 7430 | tcg_gen_movi_i32(tmp, 0); |
9ee6e8bb | 7431 | } else { |
5e3f878a | 7432 | tmp = load_reg(s, rm); |
9ee6e8bb PB |
7433 | } |
7434 | if (i != 32) { | |
5e3f878a | 7435 | tmp2 = load_reg(s, rd); |
8f8e3aa4 | 7436 | gen_bfi(tmp, tmp2, tmp, shift, (1u << i) - 1); |
7d1b0095 | 7437 | tcg_temp_free_i32(tmp2); |
9ee6e8bb | 7438 | } |
5e3f878a | 7439 | store_reg(s, rd, tmp); |
9ee6e8bb PB |
7440 | break; |
7441 | case 0x12: case 0x16: case 0x1a: case 0x1e: /* sbfx */ | |
7442 | case 0x32: case 0x36: case 0x3a: case 0x3e: /* ubfx */ | |
4cc633c3 | 7443 | ARCH(6T2); |
5e3f878a | 7444 | tmp = load_reg(s, rm); |
9ee6e8bb PB |
7445 | shift = (insn >> 7) & 0x1f; |
7446 | i = ((insn >> 16) & 0x1f) + 1; | |
7447 | if (shift + i > 32) | |
7448 | goto illegal_op; | |
7449 | if (i < 32) { | |
7450 | if (op1 & 0x20) { | |
5e3f878a | 7451 | gen_ubfx(tmp, shift, (1u << i) - 1); |
9ee6e8bb | 7452 | } else { |
5e3f878a | 7453 | gen_sbfx(tmp, shift, i); |
9ee6e8bb PB |
7454 | } |
7455 | } | |
5e3f878a | 7456 | store_reg(s, rd, tmp); |
9ee6e8bb PB |
7457 | break; |
7458 | default: | |
7459 | goto illegal_op; | |
7460 | } | |
7461 | break; | |
7462 | } | |
7463 | break; | |
7464 | } | |
7465 | do_ldst: | |
7466 | /* Check for undefined extension instructions | |
7467 | * per the ARM Bible IE: | |
7468 | * xxxx 0111 1111 xxxx xxxx xxxx 1111 xxxx | |
7469 | */ | |
7470 | sh = (0xf << 20) | (0xf << 4); | |
7471 | if (op1 == 0x7 && ((insn & sh) == sh)) | |
7472 | { | |
7473 | goto illegal_op; | |
7474 | } | |
7475 | /* load/store byte/word */ | |
7476 | rn = (insn >> 16) & 0xf; | |
7477 | rd = (insn >> 12) & 0xf; | |
b0109805 | 7478 | tmp2 = load_reg(s, rn); |
9ee6e8bb PB |
7479 | i = (IS_USER(s) || (insn & 0x01200000) == 0x00200000); |
7480 | if (insn & (1 << 24)) | |
b0109805 | 7481 | gen_add_data_offset(s, insn, tmp2); |
9ee6e8bb PB |
7482 | if (insn & (1 << 20)) { |
7483 | /* load */ | |
9ee6e8bb | 7484 | if (insn & (1 << 22)) { |
b0109805 | 7485 | tmp = gen_ld8u(tmp2, i); |
9ee6e8bb | 7486 | } else { |
b0109805 | 7487 | tmp = gen_ld32(tmp2, i); |
9ee6e8bb | 7488 | } |
9ee6e8bb PB |
7489 | } else { |
7490 | /* store */ | |
b0109805 | 7491 | tmp = load_reg(s, rd); |
9ee6e8bb | 7492 | if (insn & (1 << 22)) |
b0109805 | 7493 | gen_st8(tmp, tmp2, i); |
9ee6e8bb | 7494 | else |
b0109805 | 7495 | gen_st32(tmp, tmp2, i); |
9ee6e8bb PB |
7496 | } |
7497 | if (!(insn & (1 << 24))) { | |
b0109805 PB |
7498 | gen_add_data_offset(s, insn, tmp2); |
7499 | store_reg(s, rn, tmp2); | |
7500 | } else if (insn & (1 << 21)) { | |
7501 | store_reg(s, rn, tmp2); | |
7502 | } else { | |
7d1b0095 | 7503 | tcg_temp_free_i32(tmp2); |
9ee6e8bb PB |
7504 | } |
7505 | if (insn & (1 << 20)) { | |
7506 | /* Complete the load. */ | |
be5e7a76 | 7507 | store_reg_from_load(env, s, rd, tmp); |
9ee6e8bb PB |
7508 | } |
7509 | break; | |
7510 | case 0x08: | |
7511 | case 0x09: | |
7512 | { | |
7513 | int j, n, user, loaded_base; | |
b0109805 | 7514 | TCGv loaded_var; |
9ee6e8bb PB |
7515 | /* load/store multiple words */ |
7516 | /* XXX: store correct base if write back */ | |
7517 | user = 0; | |
7518 | if (insn & (1 << 22)) { | |
7519 | if (IS_USER(s)) | |
7520 | goto illegal_op; /* only usable in supervisor mode */ | |
7521 | ||
7522 | if ((insn & (1 << 15)) == 0) | |
7523 | user = 1; | |
7524 | } | |
7525 | rn = (insn >> 16) & 0xf; | |
b0109805 | 7526 | addr = load_reg(s, rn); |
9ee6e8bb PB |
7527 | |
7528 | /* compute total size */ | |
7529 | loaded_base = 0; | |
a50f5b91 | 7530 | TCGV_UNUSED(loaded_var); |
9ee6e8bb PB |
7531 | n = 0; |
7532 | for(i=0;i<16;i++) { | |
7533 | if (insn & (1 << i)) | |
7534 | n++; | |
7535 | } | |
7536 | /* XXX: test invalid n == 0 case ? */ | |
7537 | if (insn & (1 << 23)) { | |
7538 | if (insn & (1 << 24)) { | |
7539 | /* pre increment */ | |
b0109805 | 7540 | tcg_gen_addi_i32(addr, addr, 4); |
9ee6e8bb PB |
7541 | } else { |
7542 | /* post increment */ | |
7543 | } | |
7544 | } else { | |
7545 | if (insn & (1 << 24)) { | |
7546 | /* pre decrement */ | |
b0109805 | 7547 | tcg_gen_addi_i32(addr, addr, -(n * 4)); |
9ee6e8bb PB |
7548 | } else { |
7549 | /* post decrement */ | |
7550 | if (n != 1) | |
b0109805 | 7551 | tcg_gen_addi_i32(addr, addr, -((n - 1) * 4)); |
9ee6e8bb PB |
7552 | } |
7553 | } | |
7554 | j = 0; | |
7555 | for(i=0;i<16;i++) { | |
7556 | if (insn & (1 << i)) { | |
7557 | if (insn & (1 << 20)) { | |
7558 | /* load */ | |
b0109805 | 7559 | tmp = gen_ld32(addr, IS_USER(s)); |
be5e7a76 | 7560 | if (user) { |
b75263d6 JR |
7561 | tmp2 = tcg_const_i32(i); |
7562 | gen_helper_set_user_reg(tmp2, tmp); | |
7563 | tcg_temp_free_i32(tmp2); | |
7d1b0095 | 7564 | tcg_temp_free_i32(tmp); |
9ee6e8bb | 7565 | } else if (i == rn) { |
b0109805 | 7566 | loaded_var = tmp; |
9ee6e8bb PB |
7567 | loaded_base = 1; |
7568 | } else { | |
be5e7a76 | 7569 | store_reg_from_load(env, s, i, tmp); |
9ee6e8bb PB |
7570 | } |
7571 | } else { | |
7572 | /* store */ | |
7573 | if (i == 15) { | |
7574 | /* special case: r15 = PC + 8 */ | |
7575 | val = (long)s->pc + 4; | |
7d1b0095 | 7576 | tmp = tcg_temp_new_i32(); |
b0109805 | 7577 | tcg_gen_movi_i32(tmp, val); |
9ee6e8bb | 7578 | } else if (user) { |
7d1b0095 | 7579 | tmp = tcg_temp_new_i32(); |
b75263d6 JR |
7580 | tmp2 = tcg_const_i32(i); |
7581 | gen_helper_get_user_reg(tmp, tmp2); | |
7582 | tcg_temp_free_i32(tmp2); | |
9ee6e8bb | 7583 | } else { |
b0109805 | 7584 | tmp = load_reg(s, i); |
9ee6e8bb | 7585 | } |
b0109805 | 7586 | gen_st32(tmp, addr, IS_USER(s)); |
9ee6e8bb PB |
7587 | } |
7588 | j++; | |
7589 | /* no need to add after the last transfer */ | |
7590 | if (j != n) | |
b0109805 | 7591 | tcg_gen_addi_i32(addr, addr, 4); |
9ee6e8bb PB |
7592 | } |
7593 | } | |
7594 | if (insn & (1 << 21)) { | |
7595 | /* write back */ | |
7596 | if (insn & (1 << 23)) { | |
7597 | if (insn & (1 << 24)) { | |
7598 | /* pre increment */ | |
7599 | } else { | |
7600 | /* post increment */ | |
b0109805 | 7601 | tcg_gen_addi_i32(addr, addr, 4); |
9ee6e8bb PB |
7602 | } |
7603 | } else { | |
7604 | if (insn & (1 << 24)) { | |
7605 | /* pre decrement */ | |
7606 | if (n != 1) | |
b0109805 | 7607 | tcg_gen_addi_i32(addr, addr, -((n - 1) * 4)); |
9ee6e8bb PB |
7608 | } else { |
7609 | /* post decrement */ | |
b0109805 | 7610 | tcg_gen_addi_i32(addr, addr, -(n * 4)); |
9ee6e8bb PB |
7611 | } |
7612 | } | |
b0109805 PB |
7613 | store_reg(s, rn, addr); |
7614 | } else { | |
7d1b0095 | 7615 | tcg_temp_free_i32(addr); |
9ee6e8bb PB |
7616 | } |
7617 | if (loaded_base) { | |
b0109805 | 7618 | store_reg(s, rn, loaded_var); |
9ee6e8bb PB |
7619 | } |
7620 | if ((insn & (1 << 22)) && !user) { | |
7621 | /* Restore CPSR from SPSR. */ | |
d9ba4830 PB |
7622 | tmp = load_cpu_field(spsr); |
7623 | gen_set_cpsr(tmp, 0xffffffff); | |
7d1b0095 | 7624 | tcg_temp_free_i32(tmp); |
9ee6e8bb PB |
7625 | s->is_jmp = DISAS_UPDATE; |
7626 | } | |
7627 | } | |
7628 | break; | |
7629 | case 0xa: | |
7630 | case 0xb: | |
7631 | { | |
7632 | int32_t offset; | |
7633 | ||
7634 | /* branch (and link) */ | |
7635 | val = (int32_t)s->pc; | |
7636 | if (insn & (1 << 24)) { | |
7d1b0095 | 7637 | tmp = tcg_temp_new_i32(); |
5e3f878a PB |
7638 | tcg_gen_movi_i32(tmp, val); |
7639 | store_reg(s, 14, tmp); | |
9ee6e8bb PB |
7640 | } |
7641 | offset = (((int32_t)insn << 8) >> 8); | |
7642 | val += (offset << 2) + 4; | |
7643 | gen_jmp(s, val); | |
7644 | } | |
7645 | break; | |
7646 | case 0xc: | |
7647 | case 0xd: | |
7648 | case 0xe: | |
7649 | /* Coprocessor. */ | |
7650 | if (disas_coproc_insn(env, s, insn)) | |
7651 | goto illegal_op; | |
7652 | break; | |
7653 | case 0xf: | |
7654 | /* swi */ | |
5e3f878a | 7655 | gen_set_pc_im(s->pc); |
9ee6e8bb PB |
7656 | s->is_jmp = DISAS_SWI; |
7657 | break; | |
7658 | default: | |
7659 | illegal_op: | |
bc4a0de0 | 7660 | gen_exception_insn(s, 4, EXCP_UDEF); |
9ee6e8bb PB |
7661 | break; |
7662 | } | |
7663 | } | |
7664 | } | |
7665 | ||
7666 | /* Return true if this is a Thumb-2 logical op. */ | |
7667 | static int | |
7668 | thumb2_logic_op(int op) | |
7669 | { | |
7670 | return (op < 8); | |
7671 | } | |
7672 | ||
7673 | /* Generate code for a Thumb-2 data processing operation. If CONDS is nonzero | |
7674 | then set condition code flags based on the result of the operation. | |
7675 | If SHIFTER_OUT is nonzero then set the carry flag for logical operations | |
7676 | to the high bit of T1. | |
7677 | Returns zero if the opcode is valid. */ | |
7678 | ||
7679 | static int | |
396e467c | 7680 | gen_thumb2_data_op(DisasContext *s, int op, int conds, uint32_t shifter_out, TCGv t0, TCGv t1) |
9ee6e8bb PB |
7681 | { |
7682 | int logic_cc; | |
7683 | ||
7684 | logic_cc = 0; | |
7685 | switch (op) { | |
7686 | case 0: /* and */ | |
396e467c | 7687 | tcg_gen_and_i32(t0, t0, t1); |
9ee6e8bb PB |
7688 | logic_cc = conds; |
7689 | break; | |
7690 | case 1: /* bic */ | |
f669df27 | 7691 | tcg_gen_andc_i32(t0, t0, t1); |
9ee6e8bb PB |
7692 | logic_cc = conds; |
7693 | break; | |
7694 | case 2: /* orr */ | |
396e467c | 7695 | tcg_gen_or_i32(t0, t0, t1); |
9ee6e8bb PB |
7696 | logic_cc = conds; |
7697 | break; | |
7698 | case 3: /* orn */ | |
29501f1b | 7699 | tcg_gen_orc_i32(t0, t0, t1); |
9ee6e8bb PB |
7700 | logic_cc = conds; |
7701 | break; | |
7702 | case 4: /* eor */ | |
396e467c | 7703 | tcg_gen_xor_i32(t0, t0, t1); |
9ee6e8bb PB |
7704 | logic_cc = conds; |
7705 | break; | |
7706 | case 8: /* add */ | |
7707 | if (conds) | |
396e467c | 7708 | gen_helper_add_cc(t0, t0, t1); |
9ee6e8bb | 7709 | else |
396e467c | 7710 | tcg_gen_add_i32(t0, t0, t1); |
9ee6e8bb PB |
7711 | break; |
7712 | case 10: /* adc */ | |
7713 | if (conds) | |
396e467c | 7714 | gen_helper_adc_cc(t0, t0, t1); |
9ee6e8bb | 7715 | else |
396e467c | 7716 | gen_adc(t0, t1); |
9ee6e8bb PB |
7717 | break; |
7718 | case 11: /* sbc */ | |
7719 | if (conds) | |
396e467c | 7720 | gen_helper_sbc_cc(t0, t0, t1); |
9ee6e8bb | 7721 | else |
396e467c | 7722 | gen_sub_carry(t0, t0, t1); |
9ee6e8bb PB |
7723 | break; |
7724 | case 13: /* sub */ | |
7725 | if (conds) | |
396e467c | 7726 | gen_helper_sub_cc(t0, t0, t1); |
9ee6e8bb | 7727 | else |
396e467c | 7728 | tcg_gen_sub_i32(t0, t0, t1); |
9ee6e8bb PB |
7729 | break; |
7730 | case 14: /* rsb */ | |
7731 | if (conds) | |
396e467c | 7732 | gen_helper_sub_cc(t0, t1, t0); |
9ee6e8bb | 7733 | else |
396e467c | 7734 | tcg_gen_sub_i32(t0, t1, t0); |
9ee6e8bb PB |
7735 | break; |
7736 | default: /* 5, 6, 7, 9, 12, 15. */ | |
7737 | return 1; | |
7738 | } | |
7739 | if (logic_cc) { | |
396e467c | 7740 | gen_logic_CC(t0); |
9ee6e8bb | 7741 | if (shifter_out) |
396e467c | 7742 | gen_set_CF_bit31(t1); |
9ee6e8bb PB |
7743 | } |
7744 | return 0; | |
7745 | } | |
7746 | ||
7747 | /* Translate a 32-bit thumb instruction. Returns nonzero if the instruction | |
7748 | is not legal. */ | |
7749 | static int disas_thumb2_insn(CPUState *env, DisasContext *s, uint16_t insn_hw1) | |
7750 | { | |
b0109805 | 7751 | uint32_t insn, imm, shift, offset; |
9ee6e8bb | 7752 | uint32_t rd, rn, rm, rs; |
b26eefb6 | 7753 | TCGv tmp; |
6ddbc6e4 PB |
7754 | TCGv tmp2; |
7755 | TCGv tmp3; | |
b0109805 | 7756 | TCGv addr; |
a7812ae4 | 7757 | TCGv_i64 tmp64; |
9ee6e8bb PB |
7758 | int op; |
7759 | int shiftop; | |
7760 | int conds; | |
7761 | int logic_cc; | |
7762 | ||
7763 | if (!(arm_feature(env, ARM_FEATURE_THUMB2) | |
7764 | || arm_feature (env, ARM_FEATURE_M))) { | |
601d70b9 | 7765 | /* Thumb-1 cores may need to treat bl and blx as a pair of |
9ee6e8bb PB |
7766 | 16-bit instructions to get correct prefetch abort behavior. */ |
7767 | insn = insn_hw1; | |
7768 | if ((insn & (1 << 12)) == 0) { | |
be5e7a76 | 7769 | ARCH(5); |
9ee6e8bb PB |
7770 | /* Second half of blx. */ |
7771 | offset = ((insn & 0x7ff) << 1); | |
d9ba4830 PB |
7772 | tmp = load_reg(s, 14); |
7773 | tcg_gen_addi_i32(tmp, tmp, offset); | |
7774 | tcg_gen_andi_i32(tmp, tmp, 0xfffffffc); | |
9ee6e8bb | 7775 | |
7d1b0095 | 7776 | tmp2 = tcg_temp_new_i32(); |
b0109805 | 7777 | tcg_gen_movi_i32(tmp2, s->pc | 1); |
d9ba4830 PB |
7778 | store_reg(s, 14, tmp2); |
7779 | gen_bx(s, tmp); | |
9ee6e8bb PB |
7780 | return 0; |
7781 | } | |
7782 | if (insn & (1 << 11)) { | |
7783 | /* Second half of bl. */ | |
7784 | offset = ((insn & 0x7ff) << 1) | 1; | |
d9ba4830 | 7785 | tmp = load_reg(s, 14); |
6a0d8a1d | 7786 | tcg_gen_addi_i32(tmp, tmp, offset); |
9ee6e8bb | 7787 | |
7d1b0095 | 7788 | tmp2 = tcg_temp_new_i32(); |
b0109805 | 7789 | tcg_gen_movi_i32(tmp2, s->pc | 1); |
d9ba4830 PB |
7790 | store_reg(s, 14, tmp2); |
7791 | gen_bx(s, tmp); | |
9ee6e8bb PB |
7792 | return 0; |
7793 | } | |
7794 | if ((s->pc & ~TARGET_PAGE_MASK) == 0) { | |
7795 | /* Instruction spans a page boundary. Implement it as two | |
7796 | 16-bit instructions in case the second half causes an | |
7797 | prefetch abort. */ | |
7798 | offset = ((int32_t)insn << 21) >> 9; | |
396e467c | 7799 | tcg_gen_movi_i32(cpu_R[14], s->pc + 2 + offset); |
9ee6e8bb PB |
7800 | return 0; |
7801 | } | |
7802 | /* Fall through to 32-bit decode. */ | |
7803 | } | |
7804 | ||
7805 | insn = lduw_code(s->pc); | |
7806 | s->pc += 2; | |
7807 | insn |= (uint32_t)insn_hw1 << 16; | |
7808 | ||
7809 | if ((insn & 0xf800e800) != 0xf000e800) { | |
7810 | ARCH(6T2); | |
7811 | } | |
7812 | ||
7813 | rn = (insn >> 16) & 0xf; | |
7814 | rs = (insn >> 12) & 0xf; | |
7815 | rd = (insn >> 8) & 0xf; | |
7816 | rm = insn & 0xf; | |
7817 | switch ((insn >> 25) & 0xf) { | |
7818 | case 0: case 1: case 2: case 3: | |
7819 | /* 16-bit instructions. Should never happen. */ | |
7820 | abort(); | |
7821 | case 4: | |
7822 | if (insn & (1 << 22)) { | |
7823 | /* Other load/store, table branch. */ | |
7824 | if (insn & 0x01200000) { | |
7825 | /* Load/store doubleword. */ | |
7826 | if (rn == 15) { | |
7d1b0095 | 7827 | addr = tcg_temp_new_i32(); |
b0109805 | 7828 | tcg_gen_movi_i32(addr, s->pc & ~3); |
9ee6e8bb | 7829 | } else { |
b0109805 | 7830 | addr = load_reg(s, rn); |
9ee6e8bb PB |
7831 | } |
7832 | offset = (insn & 0xff) * 4; | |
7833 | if ((insn & (1 << 23)) == 0) | |
7834 | offset = -offset; | |
7835 | if (insn & (1 << 24)) { | |
b0109805 | 7836 | tcg_gen_addi_i32(addr, addr, offset); |
9ee6e8bb PB |
7837 | offset = 0; |
7838 | } | |
7839 | if (insn & (1 << 20)) { | |
7840 | /* ldrd */ | |
b0109805 PB |
7841 | tmp = gen_ld32(addr, IS_USER(s)); |
7842 | store_reg(s, rs, tmp); | |
7843 | tcg_gen_addi_i32(addr, addr, 4); | |
7844 | tmp = gen_ld32(addr, IS_USER(s)); | |
7845 | store_reg(s, rd, tmp); | |
9ee6e8bb PB |
7846 | } else { |
7847 | /* strd */ | |
b0109805 PB |
7848 | tmp = load_reg(s, rs); |
7849 | gen_st32(tmp, addr, IS_USER(s)); | |
7850 | tcg_gen_addi_i32(addr, addr, 4); | |
7851 | tmp = load_reg(s, rd); | |
7852 | gen_st32(tmp, addr, IS_USER(s)); | |
9ee6e8bb PB |
7853 | } |
7854 | if (insn & (1 << 21)) { | |
7855 | /* Base writeback. */ | |
7856 | if (rn == 15) | |
7857 | goto illegal_op; | |
b0109805 PB |
7858 | tcg_gen_addi_i32(addr, addr, offset - 4); |
7859 | store_reg(s, rn, addr); | |
7860 | } else { | |
7d1b0095 | 7861 | tcg_temp_free_i32(addr); |
9ee6e8bb PB |
7862 | } |
7863 | } else if ((insn & (1 << 23)) == 0) { | |
7864 | /* Load/store exclusive word. */ | |
3174f8e9 | 7865 | addr = tcg_temp_local_new(); |
98a46317 | 7866 | load_reg_var(s, addr, rn); |
426f5abc | 7867 | tcg_gen_addi_i32(addr, addr, (insn & 0xff) << 2); |
2c0262af | 7868 | if (insn & (1 << 20)) { |
426f5abc | 7869 | gen_load_exclusive(s, rs, 15, addr, 2); |
9ee6e8bb | 7870 | } else { |
426f5abc | 7871 | gen_store_exclusive(s, rd, rs, 15, addr, 2); |
9ee6e8bb | 7872 | } |
3174f8e9 | 7873 | tcg_temp_free(addr); |
9ee6e8bb PB |
7874 | } else if ((insn & (1 << 6)) == 0) { |
7875 | /* Table Branch. */ | |
7876 | if (rn == 15) { | |
7d1b0095 | 7877 | addr = tcg_temp_new_i32(); |
b0109805 | 7878 | tcg_gen_movi_i32(addr, s->pc); |
9ee6e8bb | 7879 | } else { |
b0109805 | 7880 | addr = load_reg(s, rn); |
9ee6e8bb | 7881 | } |
b26eefb6 | 7882 | tmp = load_reg(s, rm); |
b0109805 | 7883 | tcg_gen_add_i32(addr, addr, tmp); |
9ee6e8bb PB |
7884 | if (insn & (1 << 4)) { |
7885 | /* tbh */ | |
b0109805 | 7886 | tcg_gen_add_i32(addr, addr, tmp); |
7d1b0095 | 7887 | tcg_temp_free_i32(tmp); |
b0109805 | 7888 | tmp = gen_ld16u(addr, IS_USER(s)); |
9ee6e8bb | 7889 | } else { /* tbb */ |
7d1b0095 | 7890 | tcg_temp_free_i32(tmp); |
b0109805 | 7891 | tmp = gen_ld8u(addr, IS_USER(s)); |
9ee6e8bb | 7892 | } |
7d1b0095 | 7893 | tcg_temp_free_i32(addr); |
b0109805 PB |
7894 | tcg_gen_shli_i32(tmp, tmp, 1); |
7895 | tcg_gen_addi_i32(tmp, tmp, s->pc); | |
7896 | store_reg(s, 15, tmp); | |
9ee6e8bb PB |
7897 | } else { |
7898 | /* Load/store exclusive byte/halfword/doubleword. */ | |
426f5abc | 7899 | ARCH(7); |
9ee6e8bb | 7900 | op = (insn >> 4) & 0x3; |
426f5abc PB |
7901 | if (op == 2) { |
7902 | goto illegal_op; | |
7903 | } | |
3174f8e9 | 7904 | addr = tcg_temp_local_new(); |
98a46317 | 7905 | load_reg_var(s, addr, rn); |
9ee6e8bb | 7906 | if (insn & (1 << 20)) { |
426f5abc | 7907 | gen_load_exclusive(s, rs, rd, addr, op); |
9ee6e8bb | 7908 | } else { |
426f5abc | 7909 | gen_store_exclusive(s, rm, rs, rd, addr, op); |
9ee6e8bb | 7910 | } |
3174f8e9 | 7911 | tcg_temp_free(addr); |
9ee6e8bb PB |
7912 | } |
7913 | } else { | |
7914 | /* Load/store multiple, RFE, SRS. */ | |
7915 | if (((insn >> 23) & 1) == ((insn >> 24) & 1)) { | |
7916 | /* Not available in user mode. */ | |
b0109805 | 7917 | if (IS_USER(s)) |
9ee6e8bb PB |
7918 | goto illegal_op; |
7919 | if (insn & (1 << 20)) { | |
7920 | /* rfe */ | |
b0109805 PB |
7921 | addr = load_reg(s, rn); |
7922 | if ((insn & (1 << 24)) == 0) | |
7923 | tcg_gen_addi_i32(addr, addr, -8); | |
7924 | /* Load PC into tmp and CPSR into tmp2. */ | |
7925 | tmp = gen_ld32(addr, 0); | |
7926 | tcg_gen_addi_i32(addr, addr, 4); | |
7927 | tmp2 = gen_ld32(addr, 0); | |
9ee6e8bb PB |
7928 | if (insn & (1 << 21)) { |
7929 | /* Base writeback. */ | |
b0109805 PB |
7930 | if (insn & (1 << 24)) { |
7931 | tcg_gen_addi_i32(addr, addr, 4); | |
7932 | } else { | |
7933 | tcg_gen_addi_i32(addr, addr, -4); | |
7934 | } | |
7935 | store_reg(s, rn, addr); | |
7936 | } else { | |
7d1b0095 | 7937 | tcg_temp_free_i32(addr); |
9ee6e8bb | 7938 | } |
b0109805 | 7939 | gen_rfe(s, tmp, tmp2); |
9ee6e8bb PB |
7940 | } else { |
7941 | /* srs */ | |
7942 | op = (insn & 0x1f); | |
7d1b0095 | 7943 | addr = tcg_temp_new_i32(); |
39ea3d4e PM |
7944 | tmp = tcg_const_i32(op); |
7945 | gen_helper_get_r13_banked(addr, cpu_env, tmp); | |
7946 | tcg_temp_free_i32(tmp); | |
9ee6e8bb | 7947 | if ((insn & (1 << 24)) == 0) { |
b0109805 | 7948 | tcg_gen_addi_i32(addr, addr, -8); |
9ee6e8bb | 7949 | } |
b0109805 PB |
7950 | tmp = load_reg(s, 14); |
7951 | gen_st32(tmp, addr, 0); | |
7952 | tcg_gen_addi_i32(addr, addr, 4); | |
7d1b0095 | 7953 | tmp = tcg_temp_new_i32(); |
b0109805 PB |
7954 | gen_helper_cpsr_read(tmp); |
7955 | gen_st32(tmp, addr, 0); | |
9ee6e8bb PB |
7956 | if (insn & (1 << 21)) { |
7957 | if ((insn & (1 << 24)) == 0) { | |
b0109805 | 7958 | tcg_gen_addi_i32(addr, addr, -4); |
9ee6e8bb | 7959 | } else { |
b0109805 | 7960 | tcg_gen_addi_i32(addr, addr, 4); |
9ee6e8bb | 7961 | } |
39ea3d4e PM |
7962 | tmp = tcg_const_i32(op); |
7963 | gen_helper_set_r13_banked(cpu_env, tmp, addr); | |
7964 | tcg_temp_free_i32(tmp); | |
b0109805 | 7965 | } else { |
7d1b0095 | 7966 | tcg_temp_free_i32(addr); |
9ee6e8bb PB |
7967 | } |
7968 | } | |
7969 | } else { | |
7970 | int i; | |
7971 | /* Load/store multiple. */ | |
b0109805 | 7972 | addr = load_reg(s, rn); |
9ee6e8bb PB |
7973 | offset = 0; |
7974 | for (i = 0; i < 16; i++) { | |
7975 | if (insn & (1 << i)) | |
7976 | offset += 4; | |
7977 | } | |
7978 | if (insn & (1 << 24)) { | |
b0109805 | 7979 | tcg_gen_addi_i32(addr, addr, -offset); |
9ee6e8bb PB |
7980 | } |
7981 | ||
7982 | for (i = 0; i < 16; i++) { | |
7983 | if ((insn & (1 << i)) == 0) | |
7984 | continue; | |
7985 | if (insn & (1 << 20)) { | |
7986 | /* Load. */ | |
b0109805 | 7987 | tmp = gen_ld32(addr, IS_USER(s)); |
9ee6e8bb | 7988 | if (i == 15) { |
b0109805 | 7989 | gen_bx(s, tmp); |
9ee6e8bb | 7990 | } else { |
b0109805 | 7991 | store_reg(s, i, tmp); |
9ee6e8bb PB |
7992 | } |
7993 | } else { | |
7994 | /* Store. */ | |
b0109805 PB |
7995 | tmp = load_reg(s, i); |
7996 | gen_st32(tmp, addr, IS_USER(s)); | |
9ee6e8bb | 7997 | } |
b0109805 | 7998 | tcg_gen_addi_i32(addr, addr, 4); |
9ee6e8bb PB |
7999 | } |
8000 | if (insn & (1 << 21)) { | |
8001 | /* Base register writeback. */ | |
8002 | if (insn & (1 << 24)) { | |
b0109805 | 8003 | tcg_gen_addi_i32(addr, addr, -offset); |
9ee6e8bb PB |
8004 | } |
8005 | /* Fault if writeback register is in register list. */ | |
8006 | if (insn & (1 << rn)) | |
8007 | goto illegal_op; | |
b0109805 PB |
8008 | store_reg(s, rn, addr); |
8009 | } else { | |
7d1b0095 | 8010 | tcg_temp_free_i32(addr); |
9ee6e8bb PB |
8011 | } |
8012 | } | |
8013 | } | |
8014 | break; | |
2af9ab77 JB |
8015 | case 5: |
8016 | ||
9ee6e8bb | 8017 | op = (insn >> 21) & 0xf; |
2af9ab77 JB |
8018 | if (op == 6) { |
8019 | /* Halfword pack. */ | |
8020 | tmp = load_reg(s, rn); | |
8021 | tmp2 = load_reg(s, rm); | |
8022 | shift = ((insn >> 10) & 0x1c) | ((insn >> 6) & 0x3); | |
8023 | if (insn & (1 << 5)) { | |
8024 | /* pkhtb */ | |
8025 | if (shift == 0) | |
8026 | shift = 31; | |
8027 | tcg_gen_sari_i32(tmp2, tmp2, shift); | |
8028 | tcg_gen_andi_i32(tmp, tmp, 0xffff0000); | |
8029 | tcg_gen_ext16u_i32(tmp2, tmp2); | |
8030 | } else { | |
8031 | /* pkhbt */ | |
8032 | if (shift) | |
8033 | tcg_gen_shli_i32(tmp2, tmp2, shift); | |
8034 | tcg_gen_ext16u_i32(tmp, tmp); | |
8035 | tcg_gen_andi_i32(tmp2, tmp2, 0xffff0000); | |
8036 | } | |
8037 | tcg_gen_or_i32(tmp, tmp, tmp2); | |
7d1b0095 | 8038 | tcg_temp_free_i32(tmp2); |
3174f8e9 FN |
8039 | store_reg(s, rd, tmp); |
8040 | } else { | |
2af9ab77 JB |
8041 | /* Data processing register constant shift. */ |
8042 | if (rn == 15) { | |
7d1b0095 | 8043 | tmp = tcg_temp_new_i32(); |
2af9ab77 JB |
8044 | tcg_gen_movi_i32(tmp, 0); |
8045 | } else { | |
8046 | tmp = load_reg(s, rn); | |
8047 | } | |
8048 | tmp2 = load_reg(s, rm); | |
8049 | ||
8050 | shiftop = (insn >> 4) & 3; | |
8051 | shift = ((insn >> 6) & 3) | ((insn >> 10) & 0x1c); | |
8052 | conds = (insn & (1 << 20)) != 0; | |
8053 | logic_cc = (conds && thumb2_logic_op(op)); | |
8054 | gen_arm_shift_im(tmp2, shiftop, shift, logic_cc); | |
8055 | if (gen_thumb2_data_op(s, op, conds, 0, tmp, tmp2)) | |
8056 | goto illegal_op; | |
7d1b0095 | 8057 | tcg_temp_free_i32(tmp2); |
2af9ab77 JB |
8058 | if (rd != 15) { |
8059 | store_reg(s, rd, tmp); | |
8060 | } else { | |
7d1b0095 | 8061 | tcg_temp_free_i32(tmp); |
2af9ab77 | 8062 | } |
3174f8e9 | 8063 | } |
9ee6e8bb PB |
8064 | break; |
8065 | case 13: /* Misc data processing. */ | |
8066 | op = ((insn >> 22) & 6) | ((insn >> 7) & 1); | |
8067 | if (op < 4 && (insn & 0xf000) != 0xf000) | |
8068 | goto illegal_op; | |
8069 | switch (op) { | |
8070 | case 0: /* Register controlled shift. */ | |
8984bd2e PB |
8071 | tmp = load_reg(s, rn); |
8072 | tmp2 = load_reg(s, rm); | |
9ee6e8bb PB |
8073 | if ((insn & 0x70) != 0) |
8074 | goto illegal_op; | |
8075 | op = (insn >> 21) & 3; | |
8984bd2e PB |
8076 | logic_cc = (insn & (1 << 20)) != 0; |
8077 | gen_arm_shift_reg(tmp, op, tmp2, logic_cc); | |
8078 | if (logic_cc) | |
8079 | gen_logic_CC(tmp); | |
21aeb343 | 8080 | store_reg_bx(env, s, rd, tmp); |
9ee6e8bb PB |
8081 | break; |
8082 | case 1: /* Sign/zero extend. */ | |
5e3f878a | 8083 | tmp = load_reg(s, rm); |
9ee6e8bb PB |
8084 | shift = (insn >> 4) & 3; |
8085 | /* ??? In many cases it's not neccessary to do a | |
8086 | rotate, a shift is sufficient. */ | |
8087 | if (shift != 0) | |
f669df27 | 8088 | tcg_gen_rotri_i32(tmp, tmp, shift * 8); |
9ee6e8bb PB |
8089 | op = (insn >> 20) & 7; |
8090 | switch (op) { | |
5e3f878a PB |
8091 | case 0: gen_sxth(tmp); break; |
8092 | case 1: gen_uxth(tmp); break; | |
8093 | case 2: gen_sxtb16(tmp); break; | |
8094 | case 3: gen_uxtb16(tmp); break; | |
8095 | case 4: gen_sxtb(tmp); break; | |
8096 | case 5: gen_uxtb(tmp); break; | |
9ee6e8bb PB |
8097 | default: goto illegal_op; |
8098 | } | |
8099 | if (rn != 15) { | |
5e3f878a | 8100 | tmp2 = load_reg(s, rn); |
9ee6e8bb | 8101 | if ((op >> 1) == 1) { |
5e3f878a | 8102 | gen_add16(tmp, tmp2); |
9ee6e8bb | 8103 | } else { |
5e3f878a | 8104 | tcg_gen_add_i32(tmp, tmp, tmp2); |
7d1b0095 | 8105 | tcg_temp_free_i32(tmp2); |
9ee6e8bb PB |
8106 | } |
8107 | } | |
5e3f878a | 8108 | store_reg(s, rd, tmp); |
9ee6e8bb PB |
8109 | break; |
8110 | case 2: /* SIMD add/subtract. */ | |
8111 | op = (insn >> 20) & 7; | |
8112 | shift = (insn >> 4) & 7; | |
8113 | if ((op & 3) == 3 || (shift & 3) == 3) | |
8114 | goto illegal_op; | |
6ddbc6e4 PB |
8115 | tmp = load_reg(s, rn); |
8116 | tmp2 = load_reg(s, rm); | |
8117 | gen_thumb2_parallel_addsub(op, shift, tmp, tmp2); | |
7d1b0095 | 8118 | tcg_temp_free_i32(tmp2); |
6ddbc6e4 | 8119 | store_reg(s, rd, tmp); |
9ee6e8bb PB |
8120 | break; |
8121 | case 3: /* Other data processing. */ | |
8122 | op = ((insn >> 17) & 0x38) | ((insn >> 4) & 7); | |
8123 | if (op < 4) { | |
8124 | /* Saturating add/subtract. */ | |
d9ba4830 PB |
8125 | tmp = load_reg(s, rn); |
8126 | tmp2 = load_reg(s, rm); | |
9ee6e8bb | 8127 | if (op & 1) |
4809c612 JB |
8128 | gen_helper_double_saturate(tmp, tmp); |
8129 | if (op & 2) | |
d9ba4830 | 8130 | gen_helper_sub_saturate(tmp, tmp2, tmp); |
9ee6e8bb | 8131 | else |
d9ba4830 | 8132 | gen_helper_add_saturate(tmp, tmp, tmp2); |
7d1b0095 | 8133 | tcg_temp_free_i32(tmp2); |
9ee6e8bb | 8134 | } else { |
d9ba4830 | 8135 | tmp = load_reg(s, rn); |
9ee6e8bb PB |
8136 | switch (op) { |
8137 | case 0x0a: /* rbit */ | |
d9ba4830 | 8138 | gen_helper_rbit(tmp, tmp); |
9ee6e8bb PB |
8139 | break; |
8140 | case 0x08: /* rev */ | |
66896cb8 | 8141 | tcg_gen_bswap32_i32(tmp, tmp); |
9ee6e8bb PB |
8142 | break; |
8143 | case 0x09: /* rev16 */ | |
d9ba4830 | 8144 | gen_rev16(tmp); |
9ee6e8bb PB |
8145 | break; |
8146 | case 0x0b: /* revsh */ | |
d9ba4830 | 8147 | gen_revsh(tmp); |
9ee6e8bb PB |
8148 | break; |
8149 | case 0x10: /* sel */ | |
d9ba4830 | 8150 | tmp2 = load_reg(s, rm); |
7d1b0095 | 8151 | tmp3 = tcg_temp_new_i32(); |
6ddbc6e4 | 8152 | tcg_gen_ld_i32(tmp3, cpu_env, offsetof(CPUState, GE)); |
d9ba4830 | 8153 | gen_helper_sel_flags(tmp, tmp3, tmp, tmp2); |
7d1b0095 PM |
8154 | tcg_temp_free_i32(tmp3); |
8155 | tcg_temp_free_i32(tmp2); | |
9ee6e8bb PB |
8156 | break; |
8157 | case 0x18: /* clz */ | |
d9ba4830 | 8158 | gen_helper_clz(tmp, tmp); |
9ee6e8bb PB |
8159 | break; |
8160 | default: | |
8161 | goto illegal_op; | |
8162 | } | |
8163 | } | |
d9ba4830 | 8164 | store_reg(s, rd, tmp); |
9ee6e8bb PB |
8165 | break; |
8166 | case 4: case 5: /* 32-bit multiply. Sum of absolute differences. */ | |
8167 | op = (insn >> 4) & 0xf; | |
d9ba4830 PB |
8168 | tmp = load_reg(s, rn); |
8169 | tmp2 = load_reg(s, rm); | |
9ee6e8bb PB |
8170 | switch ((insn >> 20) & 7) { |
8171 | case 0: /* 32 x 32 -> 32 */ | |
d9ba4830 | 8172 | tcg_gen_mul_i32(tmp, tmp, tmp2); |
7d1b0095 | 8173 | tcg_temp_free_i32(tmp2); |
9ee6e8bb | 8174 | if (rs != 15) { |
d9ba4830 | 8175 | tmp2 = load_reg(s, rs); |
9ee6e8bb | 8176 | if (op) |
d9ba4830 | 8177 | tcg_gen_sub_i32(tmp, tmp2, tmp); |
9ee6e8bb | 8178 | else |
d9ba4830 | 8179 | tcg_gen_add_i32(tmp, tmp, tmp2); |
7d1b0095 | 8180 | tcg_temp_free_i32(tmp2); |
9ee6e8bb | 8181 | } |
9ee6e8bb PB |
8182 | break; |
8183 | case 1: /* 16 x 16 -> 32 */ | |
d9ba4830 | 8184 | gen_mulxy(tmp, tmp2, op & 2, op & 1); |
7d1b0095 | 8185 | tcg_temp_free_i32(tmp2); |
9ee6e8bb | 8186 | if (rs != 15) { |
d9ba4830 PB |
8187 | tmp2 = load_reg(s, rs); |
8188 | gen_helper_add_setq(tmp, tmp, tmp2); | |
7d1b0095 | 8189 | tcg_temp_free_i32(tmp2); |
9ee6e8bb | 8190 | } |
9ee6e8bb PB |
8191 | break; |
8192 | case 2: /* Dual multiply add. */ | |
8193 | case 4: /* Dual multiply subtract. */ | |
8194 | if (op) | |
d9ba4830 PB |
8195 | gen_swap_half(tmp2); |
8196 | gen_smul_dual(tmp, tmp2); | |
9ee6e8bb | 8197 | if (insn & (1 << 22)) { |
e1d177b9 | 8198 | /* This subtraction cannot overflow. */ |
d9ba4830 | 8199 | tcg_gen_sub_i32(tmp, tmp, tmp2); |
9ee6e8bb | 8200 | } else { |
e1d177b9 PM |
8201 | /* This addition cannot overflow 32 bits; |
8202 | * however it may overflow considered as a signed | |
8203 | * operation, in which case we must set the Q flag. | |
8204 | */ | |
8205 | gen_helper_add_setq(tmp, tmp, tmp2); | |
9ee6e8bb | 8206 | } |
7d1b0095 | 8207 | tcg_temp_free_i32(tmp2); |
9ee6e8bb PB |
8208 | if (rs != 15) |
8209 | { | |
d9ba4830 PB |
8210 | tmp2 = load_reg(s, rs); |
8211 | gen_helper_add_setq(tmp, tmp, tmp2); | |
7d1b0095 | 8212 | tcg_temp_free_i32(tmp2); |
9ee6e8bb | 8213 | } |
9ee6e8bb PB |
8214 | break; |
8215 | case 3: /* 32 * 16 -> 32msb */ | |
8216 | if (op) | |
d9ba4830 | 8217 | tcg_gen_sari_i32(tmp2, tmp2, 16); |
9ee6e8bb | 8218 | else |
d9ba4830 | 8219 | gen_sxth(tmp2); |
a7812ae4 PB |
8220 | tmp64 = gen_muls_i64_i32(tmp, tmp2); |
8221 | tcg_gen_shri_i64(tmp64, tmp64, 16); | |
7d1b0095 | 8222 | tmp = tcg_temp_new_i32(); |
a7812ae4 | 8223 | tcg_gen_trunc_i64_i32(tmp, tmp64); |
b75263d6 | 8224 | tcg_temp_free_i64(tmp64); |
9ee6e8bb PB |
8225 | if (rs != 15) |
8226 | { | |
d9ba4830 PB |
8227 | tmp2 = load_reg(s, rs); |
8228 | gen_helper_add_setq(tmp, tmp, tmp2); | |
7d1b0095 | 8229 | tcg_temp_free_i32(tmp2); |
9ee6e8bb | 8230 | } |
9ee6e8bb | 8231 | break; |
838fa72d AJ |
8232 | case 5: case 6: /* 32 * 32 -> 32msb (SMMUL, SMMLA, SMMLS) */ |
8233 | tmp64 = gen_muls_i64_i32(tmp, tmp2); | |
9ee6e8bb | 8234 | if (rs != 15) { |
838fa72d AJ |
8235 | tmp = load_reg(s, rs); |
8236 | if (insn & (1 << 20)) { | |
8237 | tmp64 = gen_addq_msw(tmp64, tmp); | |
99c475ab | 8238 | } else { |
838fa72d | 8239 | tmp64 = gen_subq_msw(tmp64, tmp); |
99c475ab | 8240 | } |
2c0262af | 8241 | } |
838fa72d AJ |
8242 | if (insn & (1 << 4)) { |
8243 | tcg_gen_addi_i64(tmp64, tmp64, 0x80000000u); | |
8244 | } | |
8245 | tcg_gen_shri_i64(tmp64, tmp64, 32); | |
7d1b0095 | 8246 | tmp = tcg_temp_new_i32(); |
838fa72d AJ |
8247 | tcg_gen_trunc_i64_i32(tmp, tmp64); |
8248 | tcg_temp_free_i64(tmp64); | |
9ee6e8bb PB |
8249 | break; |
8250 | case 7: /* Unsigned sum of absolute differences. */ | |
d9ba4830 | 8251 | gen_helper_usad8(tmp, tmp, tmp2); |
7d1b0095 | 8252 | tcg_temp_free_i32(tmp2); |
9ee6e8bb | 8253 | if (rs != 15) { |
d9ba4830 PB |
8254 | tmp2 = load_reg(s, rs); |
8255 | tcg_gen_add_i32(tmp, tmp, tmp2); | |
7d1b0095 | 8256 | tcg_temp_free_i32(tmp2); |
5fd46862 | 8257 | } |
9ee6e8bb | 8258 | break; |
2c0262af | 8259 | } |
d9ba4830 | 8260 | store_reg(s, rd, tmp); |
2c0262af | 8261 | break; |
9ee6e8bb PB |
8262 | case 6: case 7: /* 64-bit multiply, Divide. */ |
8263 | op = ((insn >> 4) & 0xf) | ((insn >> 16) & 0x70); | |
5e3f878a PB |
8264 | tmp = load_reg(s, rn); |
8265 | tmp2 = load_reg(s, rm); | |
9ee6e8bb PB |
8266 | if ((op & 0x50) == 0x10) { |
8267 | /* sdiv, udiv */ | |
8268 | if (!arm_feature(env, ARM_FEATURE_DIV)) | |
8269 | goto illegal_op; | |
8270 | if (op & 0x20) | |
5e3f878a | 8271 | gen_helper_udiv(tmp, tmp, tmp2); |
2c0262af | 8272 | else |
5e3f878a | 8273 | gen_helper_sdiv(tmp, tmp, tmp2); |
7d1b0095 | 8274 | tcg_temp_free_i32(tmp2); |
5e3f878a | 8275 | store_reg(s, rd, tmp); |
9ee6e8bb PB |
8276 | } else if ((op & 0xe) == 0xc) { |
8277 | /* Dual multiply accumulate long. */ | |
8278 | if (op & 1) | |
5e3f878a PB |
8279 | gen_swap_half(tmp2); |
8280 | gen_smul_dual(tmp, tmp2); | |
9ee6e8bb | 8281 | if (op & 0x10) { |
5e3f878a | 8282 | tcg_gen_sub_i32(tmp, tmp, tmp2); |
b5ff1b31 | 8283 | } else { |
5e3f878a | 8284 | tcg_gen_add_i32(tmp, tmp, tmp2); |
b5ff1b31 | 8285 | } |
7d1b0095 | 8286 | tcg_temp_free_i32(tmp2); |
a7812ae4 PB |
8287 | /* BUGFIX */ |
8288 | tmp64 = tcg_temp_new_i64(); | |
8289 | tcg_gen_ext_i32_i64(tmp64, tmp); | |
7d1b0095 | 8290 | tcg_temp_free_i32(tmp); |
a7812ae4 PB |
8291 | gen_addq(s, tmp64, rs, rd); |
8292 | gen_storeq_reg(s, rs, rd, tmp64); | |
b75263d6 | 8293 | tcg_temp_free_i64(tmp64); |
2c0262af | 8294 | } else { |
9ee6e8bb PB |
8295 | if (op & 0x20) { |
8296 | /* Unsigned 64-bit multiply */ | |
a7812ae4 | 8297 | tmp64 = gen_mulu_i64_i32(tmp, tmp2); |
b5ff1b31 | 8298 | } else { |
9ee6e8bb PB |
8299 | if (op & 8) { |
8300 | /* smlalxy */ | |
5e3f878a | 8301 | gen_mulxy(tmp, tmp2, op & 2, op & 1); |
7d1b0095 | 8302 | tcg_temp_free_i32(tmp2); |
a7812ae4 PB |
8303 | tmp64 = tcg_temp_new_i64(); |
8304 | tcg_gen_ext_i32_i64(tmp64, tmp); | |
7d1b0095 | 8305 | tcg_temp_free_i32(tmp); |
9ee6e8bb PB |
8306 | } else { |
8307 | /* Signed 64-bit multiply */ | |
a7812ae4 | 8308 | tmp64 = gen_muls_i64_i32(tmp, tmp2); |
9ee6e8bb | 8309 | } |
b5ff1b31 | 8310 | } |
9ee6e8bb PB |
8311 | if (op & 4) { |
8312 | /* umaal */ | |
a7812ae4 PB |
8313 | gen_addq_lo(s, tmp64, rs); |
8314 | gen_addq_lo(s, tmp64, rd); | |
9ee6e8bb PB |
8315 | } else if (op & 0x40) { |
8316 | /* 64-bit accumulate. */ | |
a7812ae4 | 8317 | gen_addq(s, tmp64, rs, rd); |
9ee6e8bb | 8318 | } |
a7812ae4 | 8319 | gen_storeq_reg(s, rs, rd, tmp64); |
b75263d6 | 8320 | tcg_temp_free_i64(tmp64); |
5fd46862 | 8321 | } |
2c0262af | 8322 | break; |
9ee6e8bb PB |
8323 | } |
8324 | break; | |
8325 | case 6: case 7: case 14: case 15: | |
8326 | /* Coprocessor. */ | |
8327 | if (((insn >> 24) & 3) == 3) { | |
8328 | /* Translate into the equivalent ARM encoding. */ | |
f06053e3 | 8329 | insn = (insn & 0xe2ffffff) | ((insn & (1 << 28)) >> 4) | (1 << 28); |
9ee6e8bb PB |
8330 | if (disas_neon_data_insn(env, s, insn)) |
8331 | goto illegal_op; | |
8332 | } else { | |
8333 | if (insn & (1 << 28)) | |
8334 | goto illegal_op; | |
8335 | if (disas_coproc_insn (env, s, insn)) | |
8336 | goto illegal_op; | |
8337 | } | |
8338 | break; | |
8339 | case 8: case 9: case 10: case 11: | |
8340 | if (insn & (1 << 15)) { | |
8341 | /* Branches, misc control. */ | |
8342 | if (insn & 0x5000) { | |
8343 | /* Unconditional branch. */ | |
8344 | /* signextend(hw1[10:0]) -> offset[:12]. */ | |
8345 | offset = ((int32_t)insn << 5) >> 9 & ~(int32_t)0xfff; | |
8346 | /* hw1[10:0] -> offset[11:1]. */ | |
8347 | offset |= (insn & 0x7ff) << 1; | |
8348 | /* (~hw2[13, 11] ^ offset[24]) -> offset[23,22] | |
8349 | offset[24:22] already have the same value because of the | |
8350 | sign extension above. */ | |
8351 | offset ^= ((~insn) & (1 << 13)) << 10; | |
8352 | offset ^= ((~insn) & (1 << 11)) << 11; | |
8353 | ||
9ee6e8bb PB |
8354 | if (insn & (1 << 14)) { |
8355 | /* Branch and link. */ | |
3174f8e9 | 8356 | tcg_gen_movi_i32(cpu_R[14], s->pc | 1); |
b5ff1b31 | 8357 | } |
3b46e624 | 8358 | |
b0109805 | 8359 | offset += s->pc; |
9ee6e8bb PB |
8360 | if (insn & (1 << 12)) { |
8361 | /* b/bl */ | |
b0109805 | 8362 | gen_jmp(s, offset); |
9ee6e8bb PB |
8363 | } else { |
8364 | /* blx */ | |
b0109805 | 8365 | offset &= ~(uint32_t)2; |
be5e7a76 | 8366 | /* thumb2 bx, no need to check */ |
b0109805 | 8367 | gen_bx_im(s, offset); |
2c0262af | 8368 | } |
9ee6e8bb PB |
8369 | } else if (((insn >> 23) & 7) == 7) { |
8370 | /* Misc control */ | |
8371 | if (insn & (1 << 13)) | |
8372 | goto illegal_op; | |
8373 | ||
8374 | if (insn & (1 << 26)) { | |
8375 | /* Secure monitor call (v6Z) */ | |
8376 | goto illegal_op; /* not implemented. */ | |
2c0262af | 8377 | } else { |
9ee6e8bb PB |
8378 | op = (insn >> 20) & 7; |
8379 | switch (op) { | |
8380 | case 0: /* msr cpsr. */ | |
8381 | if (IS_M(env)) { | |
8984bd2e PB |
8382 | tmp = load_reg(s, rn); |
8383 | addr = tcg_const_i32(insn & 0xff); | |
8384 | gen_helper_v7m_msr(cpu_env, addr, tmp); | |
b75263d6 | 8385 | tcg_temp_free_i32(addr); |
7d1b0095 | 8386 | tcg_temp_free_i32(tmp); |
9ee6e8bb PB |
8387 | gen_lookup_tb(s); |
8388 | break; | |
8389 | } | |
8390 | /* fall through */ | |
8391 | case 1: /* msr spsr. */ | |
8392 | if (IS_M(env)) | |
8393 | goto illegal_op; | |
2fbac54b FN |
8394 | tmp = load_reg(s, rn); |
8395 | if (gen_set_psr(s, | |
9ee6e8bb | 8396 | msr_mask(env, s, (insn >> 8) & 0xf, op == 1), |
2fbac54b | 8397 | op == 1, tmp)) |
9ee6e8bb PB |
8398 | goto illegal_op; |
8399 | break; | |
8400 | case 2: /* cps, nop-hint. */ | |
8401 | if (((insn >> 8) & 7) == 0) { | |
8402 | gen_nop_hint(s, insn & 0xff); | |
8403 | } | |
8404 | /* Implemented as NOP in user mode. */ | |
8405 | if (IS_USER(s)) | |
8406 | break; | |
8407 | offset = 0; | |
8408 | imm = 0; | |
8409 | if (insn & (1 << 10)) { | |
8410 | if (insn & (1 << 7)) | |
8411 | offset |= CPSR_A; | |
8412 | if (insn & (1 << 6)) | |
8413 | offset |= CPSR_I; | |
8414 | if (insn & (1 << 5)) | |
8415 | offset |= CPSR_F; | |
8416 | if (insn & (1 << 9)) | |
8417 | imm = CPSR_A | CPSR_I | CPSR_F; | |
8418 | } | |
8419 | if (insn & (1 << 8)) { | |
8420 | offset |= 0x1f; | |
8421 | imm |= (insn & 0x1f); | |
8422 | } | |
8423 | if (offset) { | |
2fbac54b | 8424 | gen_set_psr_im(s, offset, 0, imm); |
9ee6e8bb PB |
8425 | } |
8426 | break; | |
8427 | case 3: /* Special control operations. */ | |
426f5abc | 8428 | ARCH(7); |
9ee6e8bb PB |
8429 | op = (insn >> 4) & 0xf; |
8430 | switch (op) { | |
8431 | case 2: /* clrex */ | |
426f5abc | 8432 | gen_clrex(s); |
9ee6e8bb PB |
8433 | break; |
8434 | case 4: /* dsb */ | |
8435 | case 5: /* dmb */ | |
8436 | case 6: /* isb */ | |
8437 | /* These execute as NOPs. */ | |
9ee6e8bb PB |
8438 | break; |
8439 | default: | |
8440 | goto illegal_op; | |
8441 | } | |
8442 | break; | |
8443 | case 4: /* bxj */ | |
8444 | /* Trivial implementation equivalent to bx. */ | |
d9ba4830 PB |
8445 | tmp = load_reg(s, rn); |
8446 | gen_bx(s, tmp); | |
9ee6e8bb PB |
8447 | break; |
8448 | case 5: /* Exception return. */ | |
b8b45b68 RV |
8449 | if (IS_USER(s)) { |
8450 | goto illegal_op; | |
8451 | } | |
8452 | if (rn != 14 || rd != 15) { | |
8453 | goto illegal_op; | |
8454 | } | |
8455 | tmp = load_reg(s, rn); | |
8456 | tcg_gen_subi_i32(tmp, tmp, insn & 0xff); | |
8457 | gen_exception_return(s, tmp); | |
8458 | break; | |
9ee6e8bb | 8459 | case 6: /* mrs cpsr. */ |
7d1b0095 | 8460 | tmp = tcg_temp_new_i32(); |
9ee6e8bb | 8461 | if (IS_M(env)) { |
8984bd2e PB |
8462 | addr = tcg_const_i32(insn & 0xff); |
8463 | gen_helper_v7m_mrs(tmp, cpu_env, addr); | |
b75263d6 | 8464 | tcg_temp_free_i32(addr); |
9ee6e8bb | 8465 | } else { |
8984bd2e | 8466 | gen_helper_cpsr_read(tmp); |
9ee6e8bb | 8467 | } |
8984bd2e | 8468 | store_reg(s, rd, tmp); |
9ee6e8bb PB |
8469 | break; |
8470 | case 7: /* mrs spsr. */ | |
8471 | /* Not accessible in user mode. */ | |
8472 | if (IS_USER(s) || IS_M(env)) | |
8473 | goto illegal_op; | |
d9ba4830 PB |
8474 | tmp = load_cpu_field(spsr); |
8475 | store_reg(s, rd, tmp); | |
9ee6e8bb | 8476 | break; |
2c0262af FB |
8477 | } |
8478 | } | |
9ee6e8bb PB |
8479 | } else { |
8480 | /* Conditional branch. */ | |
8481 | op = (insn >> 22) & 0xf; | |
8482 | /* Generate a conditional jump to next instruction. */ | |
8483 | s->condlabel = gen_new_label(); | |
d9ba4830 | 8484 | gen_test_cc(op ^ 1, s->condlabel); |
9ee6e8bb PB |
8485 | s->condjmp = 1; |
8486 | ||
8487 | /* offset[11:1] = insn[10:0] */ | |
8488 | offset = (insn & 0x7ff) << 1; | |
8489 | /* offset[17:12] = insn[21:16]. */ | |
8490 | offset |= (insn & 0x003f0000) >> 4; | |
8491 | /* offset[31:20] = insn[26]. */ | |
8492 | offset |= ((int32_t)((insn << 5) & 0x80000000)) >> 11; | |
8493 | /* offset[18] = insn[13]. */ | |
8494 | offset |= (insn & (1 << 13)) << 5; | |
8495 | /* offset[19] = insn[11]. */ | |
8496 | offset |= (insn & (1 << 11)) << 8; | |
8497 | ||
8498 | /* jump to the offset */ | |
b0109805 | 8499 | gen_jmp(s, s->pc + offset); |
9ee6e8bb PB |
8500 | } |
8501 | } else { | |
8502 | /* Data processing immediate. */ | |
8503 | if (insn & (1 << 25)) { | |
8504 | if (insn & (1 << 24)) { | |
8505 | if (insn & (1 << 20)) | |
8506 | goto illegal_op; | |
8507 | /* Bitfield/Saturate. */ | |
8508 | op = (insn >> 21) & 7; | |
8509 | imm = insn & 0x1f; | |
8510 | shift = ((insn >> 6) & 3) | ((insn >> 10) & 0x1c); | |
6ddbc6e4 | 8511 | if (rn == 15) { |
7d1b0095 | 8512 | tmp = tcg_temp_new_i32(); |
6ddbc6e4 PB |
8513 | tcg_gen_movi_i32(tmp, 0); |
8514 | } else { | |
8515 | tmp = load_reg(s, rn); | |
8516 | } | |
9ee6e8bb PB |
8517 | switch (op) { |
8518 | case 2: /* Signed bitfield extract. */ | |
8519 | imm++; | |
8520 | if (shift + imm > 32) | |
8521 | goto illegal_op; | |
8522 | if (imm < 32) | |
6ddbc6e4 | 8523 | gen_sbfx(tmp, shift, imm); |
9ee6e8bb PB |
8524 | break; |
8525 | case 6: /* Unsigned bitfield extract. */ | |
8526 | imm++; | |
8527 | if (shift + imm > 32) | |
8528 | goto illegal_op; | |
8529 | if (imm < 32) | |
6ddbc6e4 | 8530 | gen_ubfx(tmp, shift, (1u << imm) - 1); |
9ee6e8bb PB |
8531 | break; |
8532 | case 3: /* Bitfield insert/clear. */ | |
8533 | if (imm < shift) | |
8534 | goto illegal_op; | |
8535 | imm = imm + 1 - shift; | |
8536 | if (imm != 32) { | |
6ddbc6e4 | 8537 | tmp2 = load_reg(s, rd); |
8f8e3aa4 | 8538 | gen_bfi(tmp, tmp2, tmp, shift, (1u << imm) - 1); |
7d1b0095 | 8539 | tcg_temp_free_i32(tmp2); |
9ee6e8bb PB |
8540 | } |
8541 | break; | |
8542 | case 7: | |
8543 | goto illegal_op; | |
8544 | default: /* Saturate. */ | |
9ee6e8bb PB |
8545 | if (shift) { |
8546 | if (op & 1) | |
6ddbc6e4 | 8547 | tcg_gen_sari_i32(tmp, tmp, shift); |
9ee6e8bb | 8548 | else |
6ddbc6e4 | 8549 | tcg_gen_shli_i32(tmp, tmp, shift); |
9ee6e8bb | 8550 | } |
6ddbc6e4 | 8551 | tmp2 = tcg_const_i32(imm); |
9ee6e8bb PB |
8552 | if (op & 4) { |
8553 | /* Unsigned. */ | |
9ee6e8bb | 8554 | if ((op & 1) && shift == 0) |
6ddbc6e4 | 8555 | gen_helper_usat16(tmp, tmp, tmp2); |
9ee6e8bb | 8556 | else |
6ddbc6e4 | 8557 | gen_helper_usat(tmp, tmp, tmp2); |
2c0262af | 8558 | } else { |
9ee6e8bb | 8559 | /* Signed. */ |
9ee6e8bb | 8560 | if ((op & 1) && shift == 0) |
6ddbc6e4 | 8561 | gen_helper_ssat16(tmp, tmp, tmp2); |
9ee6e8bb | 8562 | else |
6ddbc6e4 | 8563 | gen_helper_ssat(tmp, tmp, tmp2); |
2c0262af | 8564 | } |
b75263d6 | 8565 | tcg_temp_free_i32(tmp2); |
9ee6e8bb | 8566 | break; |
2c0262af | 8567 | } |
6ddbc6e4 | 8568 | store_reg(s, rd, tmp); |
9ee6e8bb PB |
8569 | } else { |
8570 | imm = ((insn & 0x04000000) >> 15) | |
8571 | | ((insn & 0x7000) >> 4) | (insn & 0xff); | |
8572 | if (insn & (1 << 22)) { | |
8573 | /* 16-bit immediate. */ | |
8574 | imm |= (insn >> 4) & 0xf000; | |
8575 | if (insn & (1 << 23)) { | |
8576 | /* movt */ | |
5e3f878a | 8577 | tmp = load_reg(s, rd); |
86831435 | 8578 | tcg_gen_ext16u_i32(tmp, tmp); |
5e3f878a | 8579 | tcg_gen_ori_i32(tmp, tmp, imm << 16); |
2c0262af | 8580 | } else { |
9ee6e8bb | 8581 | /* movw */ |
7d1b0095 | 8582 | tmp = tcg_temp_new_i32(); |
5e3f878a | 8583 | tcg_gen_movi_i32(tmp, imm); |
2c0262af FB |
8584 | } |
8585 | } else { | |
9ee6e8bb PB |
8586 | /* Add/sub 12-bit immediate. */ |
8587 | if (rn == 15) { | |
b0109805 | 8588 | offset = s->pc & ~(uint32_t)3; |
9ee6e8bb | 8589 | if (insn & (1 << 23)) |
b0109805 | 8590 | offset -= imm; |
9ee6e8bb | 8591 | else |
b0109805 | 8592 | offset += imm; |
7d1b0095 | 8593 | tmp = tcg_temp_new_i32(); |
5e3f878a | 8594 | tcg_gen_movi_i32(tmp, offset); |
2c0262af | 8595 | } else { |
5e3f878a | 8596 | tmp = load_reg(s, rn); |
9ee6e8bb | 8597 | if (insn & (1 << 23)) |
5e3f878a | 8598 | tcg_gen_subi_i32(tmp, tmp, imm); |
9ee6e8bb | 8599 | else |
5e3f878a | 8600 | tcg_gen_addi_i32(tmp, tmp, imm); |
2c0262af | 8601 | } |
9ee6e8bb | 8602 | } |
5e3f878a | 8603 | store_reg(s, rd, tmp); |
191abaa2 | 8604 | } |
9ee6e8bb PB |
8605 | } else { |
8606 | int shifter_out = 0; | |
8607 | /* modified 12-bit immediate. */ | |
8608 | shift = ((insn & 0x04000000) >> 23) | ((insn & 0x7000) >> 12); | |
8609 | imm = (insn & 0xff); | |
8610 | switch (shift) { | |
8611 | case 0: /* XY */ | |
8612 | /* Nothing to do. */ | |
8613 | break; | |
8614 | case 1: /* 00XY00XY */ | |
8615 | imm |= imm << 16; | |
8616 | break; | |
8617 | case 2: /* XY00XY00 */ | |
8618 | imm |= imm << 16; | |
8619 | imm <<= 8; | |
8620 | break; | |
8621 | case 3: /* XYXYXYXY */ | |
8622 | imm |= imm << 16; | |
8623 | imm |= imm << 8; | |
8624 | break; | |
8625 | default: /* Rotated constant. */ | |
8626 | shift = (shift << 1) | (imm >> 7); | |
8627 | imm |= 0x80; | |
8628 | imm = imm << (32 - shift); | |
8629 | shifter_out = 1; | |
8630 | break; | |
b5ff1b31 | 8631 | } |
7d1b0095 | 8632 | tmp2 = tcg_temp_new_i32(); |
3174f8e9 | 8633 | tcg_gen_movi_i32(tmp2, imm); |
9ee6e8bb | 8634 | rn = (insn >> 16) & 0xf; |
3174f8e9 | 8635 | if (rn == 15) { |
7d1b0095 | 8636 | tmp = tcg_temp_new_i32(); |
3174f8e9 FN |
8637 | tcg_gen_movi_i32(tmp, 0); |
8638 | } else { | |
8639 | tmp = load_reg(s, rn); | |
8640 | } | |
9ee6e8bb PB |
8641 | op = (insn >> 21) & 0xf; |
8642 | if (gen_thumb2_data_op(s, op, (insn & (1 << 20)) != 0, | |
3174f8e9 | 8643 | shifter_out, tmp, tmp2)) |
9ee6e8bb | 8644 | goto illegal_op; |
7d1b0095 | 8645 | tcg_temp_free_i32(tmp2); |
9ee6e8bb PB |
8646 | rd = (insn >> 8) & 0xf; |
8647 | if (rd != 15) { | |
3174f8e9 FN |
8648 | store_reg(s, rd, tmp); |
8649 | } else { | |
7d1b0095 | 8650 | tcg_temp_free_i32(tmp); |
2c0262af | 8651 | } |
2c0262af | 8652 | } |
9ee6e8bb PB |
8653 | } |
8654 | break; | |
8655 | case 12: /* Load/store single data item. */ | |
8656 | { | |
8657 | int postinc = 0; | |
8658 | int writeback = 0; | |
b0109805 | 8659 | int user; |
9ee6e8bb PB |
8660 | if ((insn & 0x01100000) == 0x01000000) { |
8661 | if (disas_neon_ls_insn(env, s, insn)) | |
c1713132 | 8662 | goto illegal_op; |
9ee6e8bb PB |
8663 | break; |
8664 | } | |
a2fdc890 PM |
8665 | op = ((insn >> 21) & 3) | ((insn >> 22) & 4); |
8666 | if (rs == 15) { | |
8667 | if (!(insn & (1 << 20))) { | |
8668 | goto illegal_op; | |
8669 | } | |
8670 | if (op != 2) { | |
8671 | /* Byte or halfword load space with dest == r15 : memory hints. | |
8672 | * Catch them early so we don't emit pointless addressing code. | |
8673 | * This space is a mix of: | |
8674 | * PLD/PLDW/PLI, which we implement as NOPs (note that unlike | |
8675 | * the ARM encodings, PLDW space doesn't UNDEF for non-v7MP | |
8676 | * cores) | |
8677 | * unallocated hints, which must be treated as NOPs | |
8678 | * UNPREDICTABLE space, which we NOP or UNDEF depending on | |
8679 | * which is easiest for the decoding logic | |
8680 | * Some space which must UNDEF | |
8681 | */ | |
8682 | int op1 = (insn >> 23) & 3; | |
8683 | int op2 = (insn >> 6) & 0x3f; | |
8684 | if (op & 2) { | |
8685 | goto illegal_op; | |
8686 | } | |
8687 | if (rn == 15) { | |
8688 | /* UNPREDICTABLE or unallocated hint */ | |
8689 | return 0; | |
8690 | } | |
8691 | if (op1 & 1) { | |
8692 | return 0; /* PLD* or unallocated hint */ | |
8693 | } | |
8694 | if ((op2 == 0) || ((op2 & 0x3c) == 0x30)) { | |
8695 | return 0; /* PLD* or unallocated hint */ | |
8696 | } | |
8697 | /* UNDEF space, or an UNPREDICTABLE */ | |
8698 | return 1; | |
8699 | } | |
8700 | } | |
b0109805 | 8701 | user = IS_USER(s); |
9ee6e8bb | 8702 | if (rn == 15) { |
7d1b0095 | 8703 | addr = tcg_temp_new_i32(); |
9ee6e8bb PB |
8704 | /* PC relative. */ |
8705 | /* s->pc has already been incremented by 4. */ | |
8706 | imm = s->pc & 0xfffffffc; | |
8707 | if (insn & (1 << 23)) | |
8708 | imm += insn & 0xfff; | |
8709 | else | |
8710 | imm -= insn & 0xfff; | |
b0109805 | 8711 | tcg_gen_movi_i32(addr, imm); |
9ee6e8bb | 8712 | } else { |
b0109805 | 8713 | addr = load_reg(s, rn); |
9ee6e8bb PB |
8714 | if (insn & (1 << 23)) { |
8715 | /* Positive offset. */ | |
8716 | imm = insn & 0xfff; | |
b0109805 | 8717 | tcg_gen_addi_i32(addr, addr, imm); |
9ee6e8bb | 8718 | } else { |
9ee6e8bb | 8719 | imm = insn & 0xff; |
2a0308c5 PM |
8720 | switch ((insn >> 8) & 0xf) { |
8721 | case 0x0: /* Shifted Register. */ | |
9ee6e8bb | 8722 | shift = (insn >> 4) & 0xf; |
2a0308c5 PM |
8723 | if (shift > 3) { |
8724 | tcg_temp_free_i32(addr); | |
18c9b560 | 8725 | goto illegal_op; |
2a0308c5 | 8726 | } |
b26eefb6 | 8727 | tmp = load_reg(s, rm); |
9ee6e8bb | 8728 | if (shift) |
b26eefb6 | 8729 | tcg_gen_shli_i32(tmp, tmp, shift); |
b0109805 | 8730 | tcg_gen_add_i32(addr, addr, tmp); |
7d1b0095 | 8731 | tcg_temp_free_i32(tmp); |
9ee6e8bb | 8732 | break; |
2a0308c5 | 8733 | case 0xc: /* Negative offset. */ |
b0109805 | 8734 | tcg_gen_addi_i32(addr, addr, -imm); |
9ee6e8bb | 8735 | break; |
2a0308c5 | 8736 | case 0xe: /* User privilege. */ |
b0109805 PB |
8737 | tcg_gen_addi_i32(addr, addr, imm); |
8738 | user = 1; | |
9ee6e8bb | 8739 | break; |
2a0308c5 | 8740 | case 0x9: /* Post-decrement. */ |
9ee6e8bb PB |
8741 | imm = -imm; |
8742 | /* Fall through. */ | |
2a0308c5 | 8743 | case 0xb: /* Post-increment. */ |
9ee6e8bb PB |
8744 | postinc = 1; |
8745 | writeback = 1; | |
8746 | break; | |
2a0308c5 | 8747 | case 0xd: /* Pre-decrement. */ |
9ee6e8bb PB |
8748 | imm = -imm; |
8749 | /* Fall through. */ | |
2a0308c5 | 8750 | case 0xf: /* Pre-increment. */ |
b0109805 | 8751 | tcg_gen_addi_i32(addr, addr, imm); |
9ee6e8bb PB |
8752 | writeback = 1; |
8753 | break; | |
8754 | default: | |
2a0308c5 | 8755 | tcg_temp_free_i32(addr); |
b7bcbe95 | 8756 | goto illegal_op; |
9ee6e8bb PB |
8757 | } |
8758 | } | |
8759 | } | |
9ee6e8bb PB |
8760 | if (insn & (1 << 20)) { |
8761 | /* Load. */ | |
a2fdc890 PM |
8762 | switch (op) { |
8763 | case 0: tmp = gen_ld8u(addr, user); break; | |
8764 | case 4: tmp = gen_ld8s(addr, user); break; | |
8765 | case 1: tmp = gen_ld16u(addr, user); break; | |
8766 | case 5: tmp = gen_ld16s(addr, user); break; | |
8767 | case 2: tmp = gen_ld32(addr, user); break; | |
2a0308c5 PM |
8768 | default: |
8769 | tcg_temp_free_i32(addr); | |
8770 | goto illegal_op; | |
a2fdc890 PM |
8771 | } |
8772 | if (rs == 15) { | |
8773 | gen_bx(s, tmp); | |
9ee6e8bb | 8774 | } else { |
a2fdc890 | 8775 | store_reg(s, rs, tmp); |
9ee6e8bb PB |
8776 | } |
8777 | } else { | |
8778 | /* Store. */ | |
b0109805 | 8779 | tmp = load_reg(s, rs); |
9ee6e8bb | 8780 | switch (op) { |
b0109805 PB |
8781 | case 0: gen_st8(tmp, addr, user); break; |
8782 | case 1: gen_st16(tmp, addr, user); break; | |
8783 | case 2: gen_st32(tmp, addr, user); break; | |
2a0308c5 PM |
8784 | default: |
8785 | tcg_temp_free_i32(addr); | |
8786 | goto illegal_op; | |
b7bcbe95 | 8787 | } |
2c0262af | 8788 | } |
9ee6e8bb | 8789 | if (postinc) |
b0109805 PB |
8790 | tcg_gen_addi_i32(addr, addr, imm); |
8791 | if (writeback) { | |
8792 | store_reg(s, rn, addr); | |
8793 | } else { | |
7d1b0095 | 8794 | tcg_temp_free_i32(addr); |
b0109805 | 8795 | } |
9ee6e8bb PB |
8796 | } |
8797 | break; | |
8798 | default: | |
8799 | goto illegal_op; | |
2c0262af | 8800 | } |
9ee6e8bb PB |
8801 | return 0; |
8802 | illegal_op: | |
8803 | return 1; | |
2c0262af FB |
8804 | } |
8805 | ||
9ee6e8bb | 8806 | static void disas_thumb_insn(CPUState *env, DisasContext *s) |
99c475ab FB |
8807 | { |
8808 | uint32_t val, insn, op, rm, rn, rd, shift, cond; | |
8809 | int32_t offset; | |
8810 | int i; | |
b26eefb6 | 8811 | TCGv tmp; |
d9ba4830 | 8812 | TCGv tmp2; |
b0109805 | 8813 | TCGv addr; |
99c475ab | 8814 | |
9ee6e8bb PB |
8815 | if (s->condexec_mask) { |
8816 | cond = s->condexec_cond; | |
bedd2912 JB |
8817 | if (cond != 0x0e) { /* Skip conditional when condition is AL. */ |
8818 | s->condlabel = gen_new_label(); | |
8819 | gen_test_cc(cond ^ 1, s->condlabel); | |
8820 | s->condjmp = 1; | |
8821 | } | |
9ee6e8bb PB |
8822 | } |
8823 | ||
b5ff1b31 | 8824 | insn = lduw_code(s->pc); |
99c475ab | 8825 | s->pc += 2; |
b5ff1b31 | 8826 | |
99c475ab FB |
8827 | switch (insn >> 12) { |
8828 | case 0: case 1: | |
396e467c | 8829 | |
99c475ab FB |
8830 | rd = insn & 7; |
8831 | op = (insn >> 11) & 3; | |
8832 | if (op == 3) { | |
8833 | /* add/subtract */ | |
8834 | rn = (insn >> 3) & 7; | |
396e467c | 8835 | tmp = load_reg(s, rn); |
99c475ab FB |
8836 | if (insn & (1 << 10)) { |
8837 | /* immediate */ | |
7d1b0095 | 8838 | tmp2 = tcg_temp_new_i32(); |
396e467c | 8839 | tcg_gen_movi_i32(tmp2, (insn >> 6) & 7); |
99c475ab FB |
8840 | } else { |
8841 | /* reg */ | |
8842 | rm = (insn >> 6) & 7; | |
396e467c | 8843 | tmp2 = load_reg(s, rm); |
99c475ab | 8844 | } |
9ee6e8bb PB |
8845 | if (insn & (1 << 9)) { |
8846 | if (s->condexec_mask) | |
396e467c | 8847 | tcg_gen_sub_i32(tmp, tmp, tmp2); |
9ee6e8bb | 8848 | else |
396e467c | 8849 | gen_helper_sub_cc(tmp, tmp, tmp2); |
9ee6e8bb PB |
8850 | } else { |
8851 | if (s->condexec_mask) | |
396e467c | 8852 | tcg_gen_add_i32(tmp, tmp, tmp2); |
9ee6e8bb | 8853 | else |
396e467c | 8854 | gen_helper_add_cc(tmp, tmp, tmp2); |
9ee6e8bb | 8855 | } |
7d1b0095 | 8856 | tcg_temp_free_i32(tmp2); |
396e467c | 8857 | store_reg(s, rd, tmp); |
99c475ab FB |
8858 | } else { |
8859 | /* shift immediate */ | |
8860 | rm = (insn >> 3) & 7; | |
8861 | shift = (insn >> 6) & 0x1f; | |
9a119ff6 PB |
8862 | tmp = load_reg(s, rm); |
8863 | gen_arm_shift_im(tmp, op, shift, s->condexec_mask == 0); | |
8864 | if (!s->condexec_mask) | |
8865 | gen_logic_CC(tmp); | |
8866 | store_reg(s, rd, tmp); | |
99c475ab FB |
8867 | } |
8868 | break; | |
8869 | case 2: case 3: | |
8870 | /* arithmetic large immediate */ | |
8871 | op = (insn >> 11) & 3; | |
8872 | rd = (insn >> 8) & 0x7; | |
396e467c | 8873 | if (op == 0) { /* mov */ |
7d1b0095 | 8874 | tmp = tcg_temp_new_i32(); |
396e467c | 8875 | tcg_gen_movi_i32(tmp, insn & 0xff); |
9ee6e8bb | 8876 | if (!s->condexec_mask) |
396e467c FN |
8877 | gen_logic_CC(tmp); |
8878 | store_reg(s, rd, tmp); | |
8879 | } else { | |
8880 | tmp = load_reg(s, rd); | |
7d1b0095 | 8881 | tmp2 = tcg_temp_new_i32(); |
396e467c FN |
8882 | tcg_gen_movi_i32(tmp2, insn & 0xff); |
8883 | switch (op) { | |
8884 | case 1: /* cmp */ | |
8885 | gen_helper_sub_cc(tmp, tmp, tmp2); | |
7d1b0095 PM |
8886 | tcg_temp_free_i32(tmp); |
8887 | tcg_temp_free_i32(tmp2); | |
396e467c FN |
8888 | break; |
8889 | case 2: /* add */ | |
8890 | if (s->condexec_mask) | |
8891 | tcg_gen_add_i32(tmp, tmp, tmp2); | |
8892 | else | |
8893 | gen_helper_add_cc(tmp, tmp, tmp2); | |
7d1b0095 | 8894 | tcg_temp_free_i32(tmp2); |
396e467c FN |
8895 | store_reg(s, rd, tmp); |
8896 | break; | |
8897 | case 3: /* sub */ | |
8898 | if (s->condexec_mask) | |
8899 | tcg_gen_sub_i32(tmp, tmp, tmp2); | |
8900 | else | |
8901 | gen_helper_sub_cc(tmp, tmp, tmp2); | |
7d1b0095 | 8902 | tcg_temp_free_i32(tmp2); |
396e467c FN |
8903 | store_reg(s, rd, tmp); |
8904 | break; | |
8905 | } | |
99c475ab | 8906 | } |
99c475ab FB |
8907 | break; |
8908 | case 4: | |
8909 | if (insn & (1 << 11)) { | |
8910 | rd = (insn >> 8) & 7; | |
5899f386 FB |
8911 | /* load pc-relative. Bit 1 of PC is ignored. */ |
8912 | val = s->pc + 2 + ((insn & 0xff) * 4); | |
8913 | val &= ~(uint32_t)2; | |
7d1b0095 | 8914 | addr = tcg_temp_new_i32(); |
b0109805 PB |
8915 | tcg_gen_movi_i32(addr, val); |
8916 | tmp = gen_ld32(addr, IS_USER(s)); | |
7d1b0095 | 8917 | tcg_temp_free_i32(addr); |
b0109805 | 8918 | store_reg(s, rd, tmp); |
99c475ab FB |
8919 | break; |
8920 | } | |
8921 | if (insn & (1 << 10)) { | |
8922 | /* data processing extended or blx */ | |
8923 | rd = (insn & 7) | ((insn >> 4) & 8); | |
8924 | rm = (insn >> 3) & 0xf; | |
8925 | op = (insn >> 8) & 3; | |
8926 | switch (op) { | |
8927 | case 0: /* add */ | |
396e467c FN |
8928 | tmp = load_reg(s, rd); |
8929 | tmp2 = load_reg(s, rm); | |
8930 | tcg_gen_add_i32(tmp, tmp, tmp2); | |
7d1b0095 | 8931 | tcg_temp_free_i32(tmp2); |
396e467c | 8932 | store_reg(s, rd, tmp); |
99c475ab FB |
8933 | break; |
8934 | case 1: /* cmp */ | |
396e467c FN |
8935 | tmp = load_reg(s, rd); |
8936 | tmp2 = load_reg(s, rm); | |
8937 | gen_helper_sub_cc(tmp, tmp, tmp2); | |
7d1b0095 PM |
8938 | tcg_temp_free_i32(tmp2); |
8939 | tcg_temp_free_i32(tmp); | |
99c475ab FB |
8940 | break; |
8941 | case 2: /* mov/cpy */ | |
396e467c FN |
8942 | tmp = load_reg(s, rm); |
8943 | store_reg(s, rd, tmp); | |
99c475ab FB |
8944 | break; |
8945 | case 3:/* branch [and link] exchange thumb register */ | |
b0109805 | 8946 | tmp = load_reg(s, rm); |
99c475ab | 8947 | if (insn & (1 << 7)) { |
be5e7a76 | 8948 | ARCH(5); |
99c475ab | 8949 | val = (uint32_t)s->pc | 1; |
7d1b0095 | 8950 | tmp2 = tcg_temp_new_i32(); |
b0109805 PB |
8951 | tcg_gen_movi_i32(tmp2, val); |
8952 | store_reg(s, 14, tmp2); | |
99c475ab | 8953 | } |
be5e7a76 | 8954 | /* already thumb, no need to check */ |
d9ba4830 | 8955 | gen_bx(s, tmp); |
99c475ab FB |
8956 | break; |
8957 | } | |
8958 | break; | |
8959 | } | |
8960 | ||
8961 | /* data processing register */ | |
8962 | rd = insn & 7; | |
8963 | rm = (insn >> 3) & 7; | |
8964 | op = (insn >> 6) & 0xf; | |
8965 | if (op == 2 || op == 3 || op == 4 || op == 7) { | |
8966 | /* the shift/rotate ops want the operands backwards */ | |
8967 | val = rm; | |
8968 | rm = rd; | |
8969 | rd = val; | |
8970 | val = 1; | |
8971 | } else { | |
8972 | val = 0; | |
8973 | } | |
8974 | ||
396e467c | 8975 | if (op == 9) { /* neg */ |
7d1b0095 | 8976 | tmp = tcg_temp_new_i32(); |
396e467c FN |
8977 | tcg_gen_movi_i32(tmp, 0); |
8978 | } else if (op != 0xf) { /* mvn doesn't read its first operand */ | |
8979 | tmp = load_reg(s, rd); | |
8980 | } else { | |
8981 | TCGV_UNUSED(tmp); | |
8982 | } | |
99c475ab | 8983 | |
396e467c | 8984 | tmp2 = load_reg(s, rm); |
5899f386 | 8985 | switch (op) { |
99c475ab | 8986 | case 0x0: /* and */ |
396e467c | 8987 | tcg_gen_and_i32(tmp, tmp, tmp2); |
9ee6e8bb | 8988 | if (!s->condexec_mask) |
396e467c | 8989 | gen_logic_CC(tmp); |
99c475ab FB |
8990 | break; |
8991 | case 0x1: /* eor */ | |
396e467c | 8992 | tcg_gen_xor_i32(tmp, tmp, tmp2); |
9ee6e8bb | 8993 | if (!s->condexec_mask) |
396e467c | 8994 | gen_logic_CC(tmp); |
99c475ab FB |
8995 | break; |
8996 | case 0x2: /* lsl */ | |
9ee6e8bb | 8997 | if (s->condexec_mask) { |
396e467c | 8998 | gen_helper_shl(tmp2, tmp2, tmp); |
9ee6e8bb | 8999 | } else { |
396e467c FN |
9000 | gen_helper_shl_cc(tmp2, tmp2, tmp); |
9001 | gen_logic_CC(tmp2); | |
9ee6e8bb | 9002 | } |
99c475ab FB |
9003 | break; |
9004 | case 0x3: /* lsr */ | |
9ee6e8bb | 9005 | if (s->condexec_mask) { |
396e467c | 9006 | gen_helper_shr(tmp2, tmp2, tmp); |
9ee6e8bb | 9007 | } else { |
396e467c FN |
9008 | gen_helper_shr_cc(tmp2, tmp2, tmp); |
9009 | gen_logic_CC(tmp2); | |
9ee6e8bb | 9010 | } |
99c475ab FB |
9011 | break; |
9012 | case 0x4: /* asr */ | |
9ee6e8bb | 9013 | if (s->condexec_mask) { |
396e467c | 9014 | gen_helper_sar(tmp2, tmp2, tmp); |
9ee6e8bb | 9015 | } else { |
396e467c FN |
9016 | gen_helper_sar_cc(tmp2, tmp2, tmp); |
9017 | gen_logic_CC(tmp2); | |
9ee6e8bb | 9018 | } |
99c475ab FB |
9019 | break; |
9020 | case 0x5: /* adc */ | |
9ee6e8bb | 9021 | if (s->condexec_mask) |
396e467c | 9022 | gen_adc(tmp, tmp2); |
9ee6e8bb | 9023 | else |
396e467c | 9024 | gen_helper_adc_cc(tmp, tmp, tmp2); |
99c475ab FB |
9025 | break; |
9026 | case 0x6: /* sbc */ | |
9ee6e8bb | 9027 | if (s->condexec_mask) |
396e467c | 9028 | gen_sub_carry(tmp, tmp, tmp2); |
9ee6e8bb | 9029 | else |
396e467c | 9030 | gen_helper_sbc_cc(tmp, tmp, tmp2); |
99c475ab FB |
9031 | break; |
9032 | case 0x7: /* ror */ | |
9ee6e8bb | 9033 | if (s->condexec_mask) { |
f669df27 AJ |
9034 | tcg_gen_andi_i32(tmp, tmp, 0x1f); |
9035 | tcg_gen_rotr_i32(tmp2, tmp2, tmp); | |
9ee6e8bb | 9036 | } else { |
396e467c FN |
9037 | gen_helper_ror_cc(tmp2, tmp2, tmp); |
9038 | gen_logic_CC(tmp2); | |
9ee6e8bb | 9039 | } |
99c475ab FB |
9040 | break; |
9041 | case 0x8: /* tst */ | |
396e467c FN |
9042 | tcg_gen_and_i32(tmp, tmp, tmp2); |
9043 | gen_logic_CC(tmp); | |
99c475ab | 9044 | rd = 16; |
5899f386 | 9045 | break; |
99c475ab | 9046 | case 0x9: /* neg */ |
9ee6e8bb | 9047 | if (s->condexec_mask) |
396e467c | 9048 | tcg_gen_neg_i32(tmp, tmp2); |
9ee6e8bb | 9049 | else |
396e467c | 9050 | gen_helper_sub_cc(tmp, tmp, tmp2); |
99c475ab FB |
9051 | break; |
9052 | case 0xa: /* cmp */ | |
396e467c | 9053 | gen_helper_sub_cc(tmp, tmp, tmp2); |
99c475ab FB |
9054 | rd = 16; |
9055 | break; | |
9056 | case 0xb: /* cmn */ | |
396e467c | 9057 | gen_helper_add_cc(tmp, tmp, tmp2); |
99c475ab FB |
9058 | rd = 16; |
9059 | break; | |
9060 | case 0xc: /* orr */ | |
396e467c | 9061 | tcg_gen_or_i32(tmp, tmp, tmp2); |
9ee6e8bb | 9062 | if (!s->condexec_mask) |
396e467c | 9063 | gen_logic_CC(tmp); |
99c475ab FB |
9064 | break; |
9065 | case 0xd: /* mul */ | |
7b2919a0 | 9066 | tcg_gen_mul_i32(tmp, tmp, tmp2); |
9ee6e8bb | 9067 | if (!s->condexec_mask) |
396e467c | 9068 | gen_logic_CC(tmp); |
99c475ab FB |
9069 | break; |
9070 | case 0xe: /* bic */ | |
f669df27 | 9071 | tcg_gen_andc_i32(tmp, tmp, tmp2); |
9ee6e8bb | 9072 | if (!s->condexec_mask) |
396e467c | 9073 | gen_logic_CC(tmp); |
99c475ab FB |
9074 | break; |
9075 | case 0xf: /* mvn */ | |
396e467c | 9076 | tcg_gen_not_i32(tmp2, tmp2); |
9ee6e8bb | 9077 | if (!s->condexec_mask) |
396e467c | 9078 | gen_logic_CC(tmp2); |
99c475ab | 9079 | val = 1; |
5899f386 | 9080 | rm = rd; |
99c475ab FB |
9081 | break; |
9082 | } | |
9083 | if (rd != 16) { | |
396e467c FN |
9084 | if (val) { |
9085 | store_reg(s, rm, tmp2); | |
9086 | if (op != 0xf) | |
7d1b0095 | 9087 | tcg_temp_free_i32(tmp); |
396e467c FN |
9088 | } else { |
9089 | store_reg(s, rd, tmp); | |
7d1b0095 | 9090 | tcg_temp_free_i32(tmp2); |
396e467c FN |
9091 | } |
9092 | } else { | |
7d1b0095 PM |
9093 | tcg_temp_free_i32(tmp); |
9094 | tcg_temp_free_i32(tmp2); | |
99c475ab FB |
9095 | } |
9096 | break; | |
9097 | ||
9098 | case 5: | |
9099 | /* load/store register offset. */ | |
9100 | rd = insn & 7; | |
9101 | rn = (insn >> 3) & 7; | |
9102 | rm = (insn >> 6) & 7; | |
9103 | op = (insn >> 9) & 7; | |
b0109805 | 9104 | addr = load_reg(s, rn); |
b26eefb6 | 9105 | tmp = load_reg(s, rm); |
b0109805 | 9106 | tcg_gen_add_i32(addr, addr, tmp); |
7d1b0095 | 9107 | tcg_temp_free_i32(tmp); |
99c475ab FB |
9108 | |
9109 | if (op < 3) /* store */ | |
b0109805 | 9110 | tmp = load_reg(s, rd); |
99c475ab FB |
9111 | |
9112 | switch (op) { | |
9113 | case 0: /* str */ | |
b0109805 | 9114 | gen_st32(tmp, addr, IS_USER(s)); |
99c475ab FB |
9115 | break; |
9116 | case 1: /* strh */ | |
b0109805 | 9117 | gen_st16(tmp, addr, IS_USER(s)); |
99c475ab FB |
9118 | break; |
9119 | case 2: /* strb */ | |
b0109805 | 9120 | gen_st8(tmp, addr, IS_USER(s)); |
99c475ab FB |
9121 | break; |
9122 | case 3: /* ldrsb */ | |
b0109805 | 9123 | tmp = gen_ld8s(addr, IS_USER(s)); |
99c475ab FB |
9124 | break; |
9125 | case 4: /* ldr */ | |
b0109805 | 9126 | tmp = gen_ld32(addr, IS_USER(s)); |
99c475ab FB |
9127 | break; |
9128 | case 5: /* ldrh */ | |
b0109805 | 9129 | tmp = gen_ld16u(addr, IS_USER(s)); |
99c475ab FB |
9130 | break; |
9131 | case 6: /* ldrb */ | |
b0109805 | 9132 | tmp = gen_ld8u(addr, IS_USER(s)); |
99c475ab FB |
9133 | break; |
9134 | case 7: /* ldrsh */ | |
b0109805 | 9135 | tmp = gen_ld16s(addr, IS_USER(s)); |
99c475ab FB |
9136 | break; |
9137 | } | |
9138 | if (op >= 3) /* load */ | |
b0109805 | 9139 | store_reg(s, rd, tmp); |
7d1b0095 | 9140 | tcg_temp_free_i32(addr); |
99c475ab FB |
9141 | break; |
9142 | ||
9143 | case 6: | |
9144 | /* load/store word immediate offset */ | |
9145 | rd = insn & 7; | |
9146 | rn = (insn >> 3) & 7; | |
b0109805 | 9147 | addr = load_reg(s, rn); |
99c475ab | 9148 | val = (insn >> 4) & 0x7c; |
b0109805 | 9149 | tcg_gen_addi_i32(addr, addr, val); |
99c475ab FB |
9150 | |
9151 | if (insn & (1 << 11)) { | |
9152 | /* load */ | |
b0109805 PB |
9153 | tmp = gen_ld32(addr, IS_USER(s)); |
9154 | store_reg(s, rd, tmp); | |
99c475ab FB |
9155 | } else { |
9156 | /* store */ | |
b0109805 PB |
9157 | tmp = load_reg(s, rd); |
9158 | gen_st32(tmp, addr, IS_USER(s)); | |
99c475ab | 9159 | } |
7d1b0095 | 9160 | tcg_temp_free_i32(addr); |
99c475ab FB |
9161 | break; |
9162 | ||
9163 | case 7: | |
9164 | /* load/store byte immediate offset */ | |
9165 | rd = insn & 7; | |
9166 | rn = (insn >> 3) & 7; | |
b0109805 | 9167 | addr = load_reg(s, rn); |
99c475ab | 9168 | val = (insn >> 6) & 0x1f; |
b0109805 | 9169 | tcg_gen_addi_i32(addr, addr, val); |
99c475ab FB |
9170 | |
9171 | if (insn & (1 << 11)) { | |
9172 | /* load */ | |
b0109805 PB |
9173 | tmp = gen_ld8u(addr, IS_USER(s)); |
9174 | store_reg(s, rd, tmp); | |
99c475ab FB |
9175 | } else { |
9176 | /* store */ | |
b0109805 PB |
9177 | tmp = load_reg(s, rd); |
9178 | gen_st8(tmp, addr, IS_USER(s)); | |
99c475ab | 9179 | } |
7d1b0095 | 9180 | tcg_temp_free_i32(addr); |
99c475ab FB |
9181 | break; |
9182 | ||
9183 | case 8: | |
9184 | /* load/store halfword immediate offset */ | |
9185 | rd = insn & 7; | |
9186 | rn = (insn >> 3) & 7; | |
b0109805 | 9187 | addr = load_reg(s, rn); |
99c475ab | 9188 | val = (insn >> 5) & 0x3e; |
b0109805 | 9189 | tcg_gen_addi_i32(addr, addr, val); |
99c475ab FB |
9190 | |
9191 | if (insn & (1 << 11)) { | |
9192 | /* load */ | |
b0109805 PB |
9193 | tmp = gen_ld16u(addr, IS_USER(s)); |
9194 | store_reg(s, rd, tmp); | |
99c475ab FB |
9195 | } else { |
9196 | /* store */ | |
b0109805 PB |
9197 | tmp = load_reg(s, rd); |
9198 | gen_st16(tmp, addr, IS_USER(s)); | |
99c475ab | 9199 | } |
7d1b0095 | 9200 | tcg_temp_free_i32(addr); |
99c475ab FB |
9201 | break; |
9202 | ||
9203 | case 9: | |
9204 | /* load/store from stack */ | |
9205 | rd = (insn >> 8) & 7; | |
b0109805 | 9206 | addr = load_reg(s, 13); |
99c475ab | 9207 | val = (insn & 0xff) * 4; |
b0109805 | 9208 | tcg_gen_addi_i32(addr, addr, val); |
99c475ab FB |
9209 | |
9210 | if (insn & (1 << 11)) { | |
9211 | /* load */ | |
b0109805 PB |
9212 | tmp = gen_ld32(addr, IS_USER(s)); |
9213 | store_reg(s, rd, tmp); | |
99c475ab FB |
9214 | } else { |
9215 | /* store */ | |
b0109805 PB |
9216 | tmp = load_reg(s, rd); |
9217 | gen_st32(tmp, addr, IS_USER(s)); | |
99c475ab | 9218 | } |
7d1b0095 | 9219 | tcg_temp_free_i32(addr); |
99c475ab FB |
9220 | break; |
9221 | ||
9222 | case 10: | |
9223 | /* add to high reg */ | |
9224 | rd = (insn >> 8) & 7; | |
5899f386 FB |
9225 | if (insn & (1 << 11)) { |
9226 | /* SP */ | |
5e3f878a | 9227 | tmp = load_reg(s, 13); |
5899f386 FB |
9228 | } else { |
9229 | /* PC. bit 1 is ignored. */ | |
7d1b0095 | 9230 | tmp = tcg_temp_new_i32(); |
5e3f878a | 9231 | tcg_gen_movi_i32(tmp, (s->pc + 2) & ~(uint32_t)2); |
5899f386 | 9232 | } |
99c475ab | 9233 | val = (insn & 0xff) * 4; |
5e3f878a PB |
9234 | tcg_gen_addi_i32(tmp, tmp, val); |
9235 | store_reg(s, rd, tmp); | |
99c475ab FB |
9236 | break; |
9237 | ||
9238 | case 11: | |
9239 | /* misc */ | |
9240 | op = (insn >> 8) & 0xf; | |
9241 | switch (op) { | |
9242 | case 0: | |
9243 | /* adjust stack pointer */ | |
b26eefb6 | 9244 | tmp = load_reg(s, 13); |
99c475ab FB |
9245 | val = (insn & 0x7f) * 4; |
9246 | if (insn & (1 << 7)) | |
6a0d8a1d | 9247 | val = -(int32_t)val; |
b26eefb6 PB |
9248 | tcg_gen_addi_i32(tmp, tmp, val); |
9249 | store_reg(s, 13, tmp); | |
99c475ab FB |
9250 | break; |
9251 | ||
9ee6e8bb PB |
9252 | case 2: /* sign/zero extend. */ |
9253 | ARCH(6); | |
9254 | rd = insn & 7; | |
9255 | rm = (insn >> 3) & 7; | |
b0109805 | 9256 | tmp = load_reg(s, rm); |
9ee6e8bb | 9257 | switch ((insn >> 6) & 3) { |
b0109805 PB |
9258 | case 0: gen_sxth(tmp); break; |
9259 | case 1: gen_sxtb(tmp); break; | |
9260 | case 2: gen_uxth(tmp); break; | |
9261 | case 3: gen_uxtb(tmp); break; | |
9ee6e8bb | 9262 | } |
b0109805 | 9263 | store_reg(s, rd, tmp); |
9ee6e8bb | 9264 | break; |
99c475ab FB |
9265 | case 4: case 5: case 0xc: case 0xd: |
9266 | /* push/pop */ | |
b0109805 | 9267 | addr = load_reg(s, 13); |
5899f386 FB |
9268 | if (insn & (1 << 8)) |
9269 | offset = 4; | |
99c475ab | 9270 | else |
5899f386 FB |
9271 | offset = 0; |
9272 | for (i = 0; i < 8; i++) { | |
9273 | if (insn & (1 << i)) | |
9274 | offset += 4; | |
9275 | } | |
9276 | if ((insn & (1 << 11)) == 0) { | |
b0109805 | 9277 | tcg_gen_addi_i32(addr, addr, -offset); |
5899f386 | 9278 | } |
99c475ab FB |
9279 | for (i = 0; i < 8; i++) { |
9280 | if (insn & (1 << i)) { | |
9281 | if (insn & (1 << 11)) { | |
9282 | /* pop */ | |
b0109805 PB |
9283 | tmp = gen_ld32(addr, IS_USER(s)); |
9284 | store_reg(s, i, tmp); | |
99c475ab FB |
9285 | } else { |
9286 | /* push */ | |
b0109805 PB |
9287 | tmp = load_reg(s, i); |
9288 | gen_st32(tmp, addr, IS_USER(s)); | |
99c475ab | 9289 | } |
5899f386 | 9290 | /* advance to the next address. */ |
b0109805 | 9291 | tcg_gen_addi_i32(addr, addr, 4); |
99c475ab FB |
9292 | } |
9293 | } | |
a50f5b91 | 9294 | TCGV_UNUSED(tmp); |
99c475ab FB |
9295 | if (insn & (1 << 8)) { |
9296 | if (insn & (1 << 11)) { | |
9297 | /* pop pc */ | |
b0109805 | 9298 | tmp = gen_ld32(addr, IS_USER(s)); |
99c475ab FB |
9299 | /* don't set the pc until the rest of the instruction |
9300 | has completed */ | |
9301 | } else { | |
9302 | /* push lr */ | |
b0109805 PB |
9303 | tmp = load_reg(s, 14); |
9304 | gen_st32(tmp, addr, IS_USER(s)); | |
99c475ab | 9305 | } |
b0109805 | 9306 | tcg_gen_addi_i32(addr, addr, 4); |
99c475ab | 9307 | } |
5899f386 | 9308 | if ((insn & (1 << 11)) == 0) { |
b0109805 | 9309 | tcg_gen_addi_i32(addr, addr, -offset); |
5899f386 | 9310 | } |
99c475ab | 9311 | /* write back the new stack pointer */ |
b0109805 | 9312 | store_reg(s, 13, addr); |
99c475ab | 9313 | /* set the new PC value */ |
be5e7a76 DES |
9314 | if ((insn & 0x0900) == 0x0900) { |
9315 | store_reg_from_load(env, s, 15, tmp); | |
9316 | } | |
99c475ab FB |
9317 | break; |
9318 | ||
9ee6e8bb PB |
9319 | case 1: case 3: case 9: case 11: /* czb */ |
9320 | rm = insn & 7; | |
d9ba4830 | 9321 | tmp = load_reg(s, rm); |
9ee6e8bb PB |
9322 | s->condlabel = gen_new_label(); |
9323 | s->condjmp = 1; | |
9324 | if (insn & (1 << 11)) | |
cb63669a | 9325 | tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, s->condlabel); |
9ee6e8bb | 9326 | else |
cb63669a | 9327 | tcg_gen_brcondi_i32(TCG_COND_NE, tmp, 0, s->condlabel); |
7d1b0095 | 9328 | tcg_temp_free_i32(tmp); |
9ee6e8bb PB |
9329 | offset = ((insn & 0xf8) >> 2) | (insn & 0x200) >> 3; |
9330 | val = (uint32_t)s->pc + 2; | |
9331 | val += offset; | |
9332 | gen_jmp(s, val); | |
9333 | break; | |
9334 | ||
9335 | case 15: /* IT, nop-hint. */ | |
9336 | if ((insn & 0xf) == 0) { | |
9337 | gen_nop_hint(s, (insn >> 4) & 0xf); | |
9338 | break; | |
9339 | } | |
9340 | /* If Then. */ | |
9341 | s->condexec_cond = (insn >> 4) & 0xe; | |
9342 | s->condexec_mask = insn & 0x1f; | |
9343 | /* No actual code generated for this insn, just setup state. */ | |
9344 | break; | |
9345 | ||
06c949e6 | 9346 | case 0xe: /* bkpt */ |
be5e7a76 | 9347 | ARCH(5); |
bc4a0de0 | 9348 | gen_exception_insn(s, 2, EXCP_BKPT); |
06c949e6 PB |
9349 | break; |
9350 | ||
9ee6e8bb PB |
9351 | case 0xa: /* rev */ |
9352 | ARCH(6); | |
9353 | rn = (insn >> 3) & 0x7; | |
9354 | rd = insn & 0x7; | |
b0109805 | 9355 | tmp = load_reg(s, rn); |
9ee6e8bb | 9356 | switch ((insn >> 6) & 3) { |
66896cb8 | 9357 | case 0: tcg_gen_bswap32_i32(tmp, tmp); break; |
b0109805 PB |
9358 | case 1: gen_rev16(tmp); break; |
9359 | case 3: gen_revsh(tmp); break; | |
9ee6e8bb PB |
9360 | default: goto illegal_op; |
9361 | } | |
b0109805 | 9362 | store_reg(s, rd, tmp); |
9ee6e8bb PB |
9363 | break; |
9364 | ||
9365 | case 6: /* cps */ | |
9366 | ARCH(6); | |
9367 | if (IS_USER(s)) | |
9368 | break; | |
9369 | if (IS_M(env)) { | |
8984bd2e | 9370 | tmp = tcg_const_i32((insn & (1 << 4)) != 0); |
9ee6e8bb | 9371 | /* PRIMASK */ |
8984bd2e PB |
9372 | if (insn & 1) { |
9373 | addr = tcg_const_i32(16); | |
9374 | gen_helper_v7m_msr(cpu_env, addr, tmp); | |
b75263d6 | 9375 | tcg_temp_free_i32(addr); |
8984bd2e | 9376 | } |
9ee6e8bb | 9377 | /* FAULTMASK */ |
8984bd2e PB |
9378 | if (insn & 2) { |
9379 | addr = tcg_const_i32(17); | |
9380 | gen_helper_v7m_msr(cpu_env, addr, tmp); | |
b75263d6 | 9381 | tcg_temp_free_i32(addr); |
8984bd2e | 9382 | } |
b75263d6 | 9383 | tcg_temp_free_i32(tmp); |
9ee6e8bb PB |
9384 | gen_lookup_tb(s); |
9385 | } else { | |
9386 | if (insn & (1 << 4)) | |
9387 | shift = CPSR_A | CPSR_I | CPSR_F; | |
9388 | else | |
9389 | shift = 0; | |
fa26df03 | 9390 | gen_set_psr_im(s, ((insn & 7) << 6), 0, shift); |
9ee6e8bb PB |
9391 | } |
9392 | break; | |
9393 | ||
99c475ab FB |
9394 | default: |
9395 | goto undef; | |
9396 | } | |
9397 | break; | |
9398 | ||
9399 | case 12: | |
9400 | /* load/store multiple */ | |
9401 | rn = (insn >> 8) & 0x7; | |
b0109805 | 9402 | addr = load_reg(s, rn); |
99c475ab FB |
9403 | for (i = 0; i < 8; i++) { |
9404 | if (insn & (1 << i)) { | |
99c475ab FB |
9405 | if (insn & (1 << 11)) { |
9406 | /* load */ | |
b0109805 PB |
9407 | tmp = gen_ld32(addr, IS_USER(s)); |
9408 | store_reg(s, i, tmp); | |
99c475ab FB |
9409 | } else { |
9410 | /* store */ | |
b0109805 PB |
9411 | tmp = load_reg(s, i); |
9412 | gen_st32(tmp, addr, IS_USER(s)); | |
99c475ab | 9413 | } |
5899f386 | 9414 | /* advance to the next address */ |
b0109805 | 9415 | tcg_gen_addi_i32(addr, addr, 4); |
99c475ab FB |
9416 | } |
9417 | } | |
5899f386 | 9418 | /* Base register writeback. */ |
b0109805 PB |
9419 | if ((insn & (1 << rn)) == 0) { |
9420 | store_reg(s, rn, addr); | |
9421 | } else { | |
7d1b0095 | 9422 | tcg_temp_free_i32(addr); |
b0109805 | 9423 | } |
99c475ab FB |
9424 | break; |
9425 | ||
9426 | case 13: | |
9427 | /* conditional branch or swi */ | |
9428 | cond = (insn >> 8) & 0xf; | |
9429 | if (cond == 0xe) | |
9430 | goto undef; | |
9431 | ||
9432 | if (cond == 0xf) { | |
9433 | /* swi */ | |
422ebf69 | 9434 | gen_set_pc_im(s->pc); |
9ee6e8bb | 9435 | s->is_jmp = DISAS_SWI; |
99c475ab FB |
9436 | break; |
9437 | } | |
9438 | /* generate a conditional jump to next instruction */ | |
e50e6a20 | 9439 | s->condlabel = gen_new_label(); |
d9ba4830 | 9440 | gen_test_cc(cond ^ 1, s->condlabel); |
e50e6a20 | 9441 | s->condjmp = 1; |
99c475ab FB |
9442 | |
9443 | /* jump to the offset */ | |
5899f386 | 9444 | val = (uint32_t)s->pc + 2; |
99c475ab | 9445 | offset = ((int32_t)insn << 24) >> 24; |
5899f386 | 9446 | val += offset << 1; |
8aaca4c0 | 9447 | gen_jmp(s, val); |
99c475ab FB |
9448 | break; |
9449 | ||
9450 | case 14: | |
358bf29e | 9451 | if (insn & (1 << 11)) { |
9ee6e8bb PB |
9452 | if (disas_thumb2_insn(env, s, insn)) |
9453 | goto undef32; | |
358bf29e PB |
9454 | break; |
9455 | } | |
9ee6e8bb | 9456 | /* unconditional branch */ |
99c475ab FB |
9457 | val = (uint32_t)s->pc; |
9458 | offset = ((int32_t)insn << 21) >> 21; | |
9459 | val += (offset << 1) + 2; | |
8aaca4c0 | 9460 | gen_jmp(s, val); |
99c475ab FB |
9461 | break; |
9462 | ||
9463 | case 15: | |
9ee6e8bb | 9464 | if (disas_thumb2_insn(env, s, insn)) |
6a0d8a1d | 9465 | goto undef32; |
9ee6e8bb | 9466 | break; |
99c475ab FB |
9467 | } |
9468 | return; | |
9ee6e8bb | 9469 | undef32: |
bc4a0de0 | 9470 | gen_exception_insn(s, 4, EXCP_UDEF); |
9ee6e8bb PB |
9471 | return; |
9472 | illegal_op: | |
99c475ab | 9473 | undef: |
bc4a0de0 | 9474 | gen_exception_insn(s, 2, EXCP_UDEF); |
99c475ab FB |
9475 | } |
9476 | ||
2c0262af FB |
9477 | /* generate intermediate code in gen_opc_buf and gen_opparam_buf for |
9478 | basic block 'tb'. If search_pc is TRUE, also generate PC | |
9479 | information for each intermediate instruction. */ | |
2cfc5f17 TS |
9480 | static inline void gen_intermediate_code_internal(CPUState *env, |
9481 | TranslationBlock *tb, | |
9482 | int search_pc) | |
2c0262af FB |
9483 | { |
9484 | DisasContext dc1, *dc = &dc1; | |
a1d1bb31 | 9485 | CPUBreakpoint *bp; |
2c0262af FB |
9486 | uint16_t *gen_opc_end; |
9487 | int j, lj; | |
0fa85d43 | 9488 | target_ulong pc_start; |
b5ff1b31 | 9489 | uint32_t next_page_start; |
2e70f6ef PB |
9490 | int num_insns; |
9491 | int max_insns; | |
3b46e624 | 9492 | |
2c0262af | 9493 | /* generate intermediate code */ |
0fa85d43 | 9494 | pc_start = tb->pc; |
3b46e624 | 9495 | |
2c0262af FB |
9496 | dc->tb = tb; |
9497 | ||
2c0262af | 9498 | gen_opc_end = gen_opc_buf + OPC_MAX_SIZE; |
2c0262af FB |
9499 | |
9500 | dc->is_jmp = DISAS_NEXT; | |
9501 | dc->pc = pc_start; | |
8aaca4c0 | 9502 | dc->singlestep_enabled = env->singlestep_enabled; |
e50e6a20 | 9503 | dc->condjmp = 0; |
7204ab88 | 9504 | dc->thumb = ARM_TBFLAG_THUMB(tb->flags); |
98eac7ca PM |
9505 | dc->condexec_mask = (ARM_TBFLAG_CONDEXEC(tb->flags) & 0xf) << 1; |
9506 | dc->condexec_cond = ARM_TBFLAG_CONDEXEC(tb->flags) >> 4; | |
b5ff1b31 | 9507 | #if !defined(CONFIG_USER_ONLY) |
61f74d6a | 9508 | dc->user = (ARM_TBFLAG_PRIV(tb->flags) == 0); |
b5ff1b31 | 9509 | #endif |
5df8bac1 | 9510 | dc->vfp_enabled = ARM_TBFLAG_VFPEN(tb->flags); |
69d1fc22 PM |
9511 | dc->vec_len = ARM_TBFLAG_VECLEN(tb->flags); |
9512 | dc->vec_stride = ARM_TBFLAG_VECSTRIDE(tb->flags); | |
a7812ae4 PB |
9513 | cpu_F0s = tcg_temp_new_i32(); |
9514 | cpu_F1s = tcg_temp_new_i32(); | |
9515 | cpu_F0d = tcg_temp_new_i64(); | |
9516 | cpu_F1d = tcg_temp_new_i64(); | |
ad69471c PB |
9517 | cpu_V0 = cpu_F0d; |
9518 | cpu_V1 = cpu_F1d; | |
e677137d | 9519 | /* FIXME: cpu_M0 can probably be the same as cpu_V0. */ |
a7812ae4 | 9520 | cpu_M0 = tcg_temp_new_i64(); |
b5ff1b31 | 9521 | next_page_start = (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE; |
2c0262af | 9522 | lj = -1; |
2e70f6ef PB |
9523 | num_insns = 0; |
9524 | max_insns = tb->cflags & CF_COUNT_MASK; | |
9525 | if (max_insns == 0) | |
9526 | max_insns = CF_COUNT_MASK; | |
9527 | ||
9528 | gen_icount_start(); | |
e12ce78d | 9529 | |
3849902c PM |
9530 | tcg_clear_temp_count(); |
9531 | ||
e12ce78d PM |
9532 | /* A note on handling of the condexec (IT) bits: |
9533 | * | |
9534 | * We want to avoid the overhead of having to write the updated condexec | |
9535 | * bits back to the CPUState for every instruction in an IT block. So: | |
9536 | * (1) if the condexec bits are not already zero then we write | |
9537 | * zero back into the CPUState now. This avoids complications trying | |
9538 | * to do it at the end of the block. (For example if we don't do this | |
9539 | * it's hard to identify whether we can safely skip writing condexec | |
9540 | * at the end of the TB, which we definitely want to do for the case | |
9541 | * where a TB doesn't do anything with the IT state at all.) | |
9542 | * (2) if we are going to leave the TB then we call gen_set_condexec() | |
9543 | * which will write the correct value into CPUState if zero is wrong. | |
9544 | * This is done both for leaving the TB at the end, and for leaving | |
9545 | * it because of an exception we know will happen, which is done in | |
9546 | * gen_exception_insn(). The latter is necessary because we need to | |
9547 | * leave the TB with the PC/IT state just prior to execution of the | |
9548 | * instruction which caused the exception. | |
9549 | * (3) if we leave the TB unexpectedly (eg a data abort on a load) | |
9550 | * then the CPUState will be wrong and we need to reset it. | |
9551 | * This is handled in the same way as restoration of the | |
9552 | * PC in these situations: we will be called again with search_pc=1 | |
9553 | * and generate a mapping of the condexec bits for each PC in | |
9554 | * gen_opc_condexec_bits[]. gen_pc_load[] then uses this to restore | |
9555 | * the condexec bits. | |
9556 | * | |
9557 | * Note that there are no instructions which can read the condexec | |
9558 | * bits, and none which can write non-static values to them, so | |
9559 | * we don't need to care about whether CPUState is correct in the | |
9560 | * middle of a TB. | |
9561 | */ | |
9562 | ||
9ee6e8bb PB |
9563 | /* Reset the conditional execution bits immediately. This avoids |
9564 | complications trying to do it at the end of the block. */ | |
98eac7ca | 9565 | if (dc->condexec_mask || dc->condexec_cond) |
8f01245e | 9566 | { |
7d1b0095 | 9567 | TCGv tmp = tcg_temp_new_i32(); |
8f01245e | 9568 | tcg_gen_movi_i32(tmp, 0); |
d9ba4830 | 9569 | store_cpu_field(tmp, condexec_bits); |
8f01245e | 9570 | } |
2c0262af | 9571 | do { |
fbb4a2e3 PB |
9572 | #ifdef CONFIG_USER_ONLY |
9573 | /* Intercept jump to the magic kernel page. */ | |
9574 | if (dc->pc >= 0xffff0000) { | |
9575 | /* We always get here via a jump, so know we are not in a | |
9576 | conditional execution block. */ | |
9577 | gen_exception(EXCP_KERNEL_TRAP); | |
9578 | dc->is_jmp = DISAS_UPDATE; | |
9579 | break; | |
9580 | } | |
9581 | #else | |
9ee6e8bb PB |
9582 | if (dc->pc >= 0xfffffff0 && IS_M(env)) { |
9583 | /* We always get here via a jump, so know we are not in a | |
9584 | conditional execution block. */ | |
d9ba4830 | 9585 | gen_exception(EXCP_EXCEPTION_EXIT); |
d60bb01c PB |
9586 | dc->is_jmp = DISAS_UPDATE; |
9587 | break; | |
9ee6e8bb PB |
9588 | } |
9589 | #endif | |
9590 | ||
72cf2d4f BS |
9591 | if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) { |
9592 | QTAILQ_FOREACH(bp, &env->breakpoints, entry) { | |
a1d1bb31 | 9593 | if (bp->pc == dc->pc) { |
bc4a0de0 | 9594 | gen_exception_insn(dc, 0, EXCP_DEBUG); |
9ee6e8bb PB |
9595 | /* Advance PC so that clearing the breakpoint will |
9596 | invalidate this TB. */ | |
9597 | dc->pc += 2; | |
9598 | goto done_generating; | |
1fddef4b FB |
9599 | break; |
9600 | } | |
9601 | } | |
9602 | } | |
2c0262af FB |
9603 | if (search_pc) { |
9604 | j = gen_opc_ptr - gen_opc_buf; | |
9605 | if (lj < j) { | |
9606 | lj++; | |
9607 | while (lj < j) | |
9608 | gen_opc_instr_start[lj++] = 0; | |
9609 | } | |
0fa85d43 | 9610 | gen_opc_pc[lj] = dc->pc; |
e12ce78d | 9611 | gen_opc_condexec_bits[lj] = (dc->condexec_cond << 4) | (dc->condexec_mask >> 1); |
2c0262af | 9612 | gen_opc_instr_start[lj] = 1; |
2e70f6ef | 9613 | gen_opc_icount[lj] = num_insns; |
2c0262af | 9614 | } |
e50e6a20 | 9615 | |
2e70f6ef PB |
9616 | if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO)) |
9617 | gen_io_start(); | |
9618 | ||
5642463a PM |
9619 | if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP))) { |
9620 | tcg_gen_debug_insn_start(dc->pc); | |
9621 | } | |
9622 | ||
7204ab88 | 9623 | if (dc->thumb) { |
9ee6e8bb PB |
9624 | disas_thumb_insn(env, dc); |
9625 | if (dc->condexec_mask) { | |
9626 | dc->condexec_cond = (dc->condexec_cond & 0xe) | |
9627 | | ((dc->condexec_mask >> 4) & 1); | |
9628 | dc->condexec_mask = (dc->condexec_mask << 1) & 0x1f; | |
9629 | if (dc->condexec_mask == 0) { | |
9630 | dc->condexec_cond = 0; | |
9631 | } | |
9632 | } | |
9633 | } else { | |
9634 | disas_arm_insn(env, dc); | |
9635 | } | |
e50e6a20 FB |
9636 | |
9637 | if (dc->condjmp && !dc->is_jmp) { | |
9638 | gen_set_label(dc->condlabel); | |
9639 | dc->condjmp = 0; | |
9640 | } | |
3849902c PM |
9641 | |
9642 | if (tcg_check_temp_count()) { | |
9643 | fprintf(stderr, "TCG temporary leak before %08x\n", dc->pc); | |
9644 | } | |
9645 | ||
aaf2d97d | 9646 | /* Translation stops when a conditional branch is encountered. |
e50e6a20 | 9647 | * Otherwise the subsequent code could get translated several times. |
b5ff1b31 | 9648 | * Also stop translation when a page boundary is reached. This |
bf20dc07 | 9649 | * ensures prefetch aborts occur at the right place. */ |
2e70f6ef | 9650 | num_insns ++; |
1fddef4b FB |
9651 | } while (!dc->is_jmp && gen_opc_ptr < gen_opc_end && |
9652 | !env->singlestep_enabled && | |
1b530a6d | 9653 | !singlestep && |
2e70f6ef PB |
9654 | dc->pc < next_page_start && |
9655 | num_insns < max_insns); | |
9656 | ||
9657 | if (tb->cflags & CF_LAST_IO) { | |
9658 | if (dc->condjmp) { | |
9659 | /* FIXME: This can theoretically happen with self-modifying | |
9660 | code. */ | |
9661 | cpu_abort(env, "IO on conditional branch instruction"); | |
9662 | } | |
9663 | gen_io_end(); | |
9664 | } | |
9ee6e8bb | 9665 | |
b5ff1b31 | 9666 | /* At this stage dc->condjmp will only be set when the skipped |
9ee6e8bb PB |
9667 | instruction was a conditional branch or trap, and the PC has |
9668 | already been written. */ | |
551bd27f | 9669 | if (unlikely(env->singlestep_enabled)) { |
8aaca4c0 | 9670 | /* Make sure the pc is updated, and raise a debug exception. */ |
e50e6a20 | 9671 | if (dc->condjmp) { |
9ee6e8bb PB |
9672 | gen_set_condexec(dc); |
9673 | if (dc->is_jmp == DISAS_SWI) { | |
d9ba4830 | 9674 | gen_exception(EXCP_SWI); |
9ee6e8bb | 9675 | } else { |
d9ba4830 | 9676 | gen_exception(EXCP_DEBUG); |
9ee6e8bb | 9677 | } |
e50e6a20 FB |
9678 | gen_set_label(dc->condlabel); |
9679 | } | |
9680 | if (dc->condjmp || !dc->is_jmp) { | |
5e3f878a | 9681 | gen_set_pc_im(dc->pc); |
e50e6a20 | 9682 | dc->condjmp = 0; |
8aaca4c0 | 9683 | } |
9ee6e8bb PB |
9684 | gen_set_condexec(dc); |
9685 | if (dc->is_jmp == DISAS_SWI && !dc->condjmp) { | |
d9ba4830 | 9686 | gen_exception(EXCP_SWI); |
9ee6e8bb PB |
9687 | } else { |
9688 | /* FIXME: Single stepping a WFI insn will not halt | |
9689 | the CPU. */ | |
d9ba4830 | 9690 | gen_exception(EXCP_DEBUG); |
9ee6e8bb | 9691 | } |
8aaca4c0 | 9692 | } else { |
9ee6e8bb PB |
9693 | /* While branches must always occur at the end of an IT block, |
9694 | there are a few other things that can cause us to terminate | |
9695 | the TB in the middel of an IT block: | |
9696 | - Exception generating instructions (bkpt, swi, undefined). | |
9697 | - Page boundaries. | |
9698 | - Hardware watchpoints. | |
9699 | Hardware breakpoints have already been handled and skip this code. | |
9700 | */ | |
9701 | gen_set_condexec(dc); | |
8aaca4c0 | 9702 | switch(dc->is_jmp) { |
8aaca4c0 | 9703 | case DISAS_NEXT: |
6e256c93 | 9704 | gen_goto_tb(dc, 1, dc->pc); |
8aaca4c0 FB |
9705 | break; |
9706 | default: | |
9707 | case DISAS_JUMP: | |
9708 | case DISAS_UPDATE: | |
9709 | /* indicate that the hash table must be used to find the next TB */ | |
57fec1fe | 9710 | tcg_gen_exit_tb(0); |
8aaca4c0 FB |
9711 | break; |
9712 | case DISAS_TB_JUMP: | |
9713 | /* nothing more to generate */ | |
9714 | break; | |
9ee6e8bb | 9715 | case DISAS_WFI: |
d9ba4830 | 9716 | gen_helper_wfi(); |
9ee6e8bb PB |
9717 | break; |
9718 | case DISAS_SWI: | |
d9ba4830 | 9719 | gen_exception(EXCP_SWI); |
9ee6e8bb | 9720 | break; |
8aaca4c0 | 9721 | } |
e50e6a20 FB |
9722 | if (dc->condjmp) { |
9723 | gen_set_label(dc->condlabel); | |
9ee6e8bb | 9724 | gen_set_condexec(dc); |
6e256c93 | 9725 | gen_goto_tb(dc, 1, dc->pc); |
e50e6a20 FB |
9726 | dc->condjmp = 0; |
9727 | } | |
2c0262af | 9728 | } |
2e70f6ef | 9729 | |
9ee6e8bb | 9730 | done_generating: |
2e70f6ef | 9731 | gen_icount_end(tb, num_insns); |
2c0262af FB |
9732 | *gen_opc_ptr = INDEX_op_end; |
9733 | ||
9734 | #ifdef DEBUG_DISAS | |
8fec2b8c | 9735 | if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) { |
93fcfe39 AL |
9736 | qemu_log("----------------\n"); |
9737 | qemu_log("IN: %s\n", lookup_symbol(pc_start)); | |
7204ab88 | 9738 | log_target_disas(pc_start, dc->pc - pc_start, dc->thumb); |
93fcfe39 | 9739 | qemu_log("\n"); |
2c0262af FB |
9740 | } |
9741 | #endif | |
b5ff1b31 FB |
9742 | if (search_pc) { |
9743 | j = gen_opc_ptr - gen_opc_buf; | |
9744 | lj++; | |
9745 | while (lj <= j) | |
9746 | gen_opc_instr_start[lj++] = 0; | |
b5ff1b31 | 9747 | } else { |
2c0262af | 9748 | tb->size = dc->pc - pc_start; |
2e70f6ef | 9749 | tb->icount = num_insns; |
b5ff1b31 | 9750 | } |
2c0262af FB |
9751 | } |
9752 | ||
2cfc5f17 | 9753 | void gen_intermediate_code(CPUState *env, TranslationBlock *tb) |
2c0262af | 9754 | { |
2cfc5f17 | 9755 | gen_intermediate_code_internal(env, tb, 0); |
2c0262af FB |
9756 | } |
9757 | ||
2cfc5f17 | 9758 | void gen_intermediate_code_pc(CPUState *env, TranslationBlock *tb) |
2c0262af | 9759 | { |
2cfc5f17 | 9760 | gen_intermediate_code_internal(env, tb, 1); |
2c0262af FB |
9761 | } |
9762 | ||
b5ff1b31 FB |
9763 | static const char *cpu_mode_names[16] = { |
9764 | "usr", "fiq", "irq", "svc", "???", "???", "???", "abt", | |
9765 | "???", "???", "???", "und", "???", "???", "???", "sys" | |
9766 | }; | |
9ee6e8bb | 9767 | |
9a78eead | 9768 | void cpu_dump_state(CPUState *env, FILE *f, fprintf_function cpu_fprintf, |
7fe48483 | 9769 | int flags) |
2c0262af FB |
9770 | { |
9771 | int i; | |
06e80fc9 | 9772 | #if 0 |
bc380d17 | 9773 | union { |
b7bcbe95 FB |
9774 | uint32_t i; |
9775 | float s; | |
9776 | } s0, s1; | |
9777 | CPU_DoubleU d; | |
a94a6abf PB |
9778 | /* ??? This assumes float64 and double have the same layout. |
9779 | Oh well, it's only debug dumps. */ | |
9780 | union { | |
9781 | float64 f64; | |
9782 | double d; | |
9783 | } d0; | |
06e80fc9 | 9784 | #endif |
b5ff1b31 | 9785 | uint32_t psr; |
2c0262af FB |
9786 | |
9787 | for(i=0;i<16;i++) { | |
7fe48483 | 9788 | cpu_fprintf(f, "R%02d=%08x", i, env->regs[i]); |
2c0262af | 9789 | if ((i % 4) == 3) |
7fe48483 | 9790 | cpu_fprintf(f, "\n"); |
2c0262af | 9791 | else |
7fe48483 | 9792 | cpu_fprintf(f, " "); |
2c0262af | 9793 | } |
b5ff1b31 | 9794 | psr = cpsr_read(env); |
687fa640 TS |
9795 | cpu_fprintf(f, "PSR=%08x %c%c%c%c %c %s%d\n", |
9796 | psr, | |
b5ff1b31 FB |
9797 | psr & (1 << 31) ? 'N' : '-', |
9798 | psr & (1 << 30) ? 'Z' : '-', | |
9799 | psr & (1 << 29) ? 'C' : '-', | |
9800 | psr & (1 << 28) ? 'V' : '-', | |
5fafdf24 | 9801 | psr & CPSR_T ? 'T' : 'A', |
b5ff1b31 | 9802 | cpu_mode_names[psr & 0xf], (psr & 0x10) ? 32 : 26); |
b7bcbe95 | 9803 | |
5e3f878a | 9804 | #if 0 |
b7bcbe95 | 9805 | for (i = 0; i < 16; i++) { |
8e96005d FB |
9806 | d.d = env->vfp.regs[i]; |
9807 | s0.i = d.l.lower; | |
9808 | s1.i = d.l.upper; | |
a94a6abf PB |
9809 | d0.f64 = d.d; |
9810 | cpu_fprintf(f, "s%02d=%08x(%8g) s%02d=%08x(%8g) d%02d=%08x%08x(%8g)\n", | |
b7bcbe95 | 9811 | i * 2, (int)s0.i, s0.s, |
a94a6abf | 9812 | i * 2 + 1, (int)s1.i, s1.s, |
b7bcbe95 | 9813 | i, (int)(uint32_t)d.l.upper, (int)(uint32_t)d.l.lower, |
a94a6abf | 9814 | d0.d); |
b7bcbe95 | 9815 | } |
40f137e1 | 9816 | cpu_fprintf(f, "FPSCR: %08x\n", (int)env->vfp.xregs[ARM_VFP_FPSCR]); |
5e3f878a | 9817 | #endif |
2c0262af | 9818 | } |
a6b025d3 | 9819 | |
d2856f1a AJ |
9820 | void gen_pc_load(CPUState *env, TranslationBlock *tb, |
9821 | unsigned long searched_pc, int pc_pos, void *puc) | |
9822 | { | |
9823 | env->regs[15] = gen_opc_pc[pc_pos]; | |
e12ce78d | 9824 | env->condexec_bits = gen_opc_condexec_bits[pc_pos]; |
d2856f1a | 9825 | } |