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target-arm: Handle UNDEF cases for Neon 3-regs-same insns
[mirror_qemu.git] / target-arm / translate.c
CommitLineData
2c0262af
FB		 1/*
2 * ARM translation
5fafdf24 3 *
2c0262af 4 * Copyright (c) 2003 Fabrice Bellard
9ee6e8bb 5 * Copyright (c) 2005-2007 CodeSourcery
18c9b560 6 * Copyright (c) 2007 OpenedHand, Ltd.
2c0262af
FB		 7 *
8 * This library is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU Lesser General Public
10 * License as published by the Free Software Foundation; either
11 * version 2 of the License, or (at your option) any later version.
12 *
13 * This library is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * Lesser General Public License for more details.
17 *
18 * You should have received a copy of the GNU Lesser General Public
8167ee88 19 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
2c0262af
FB		 20 */
21#include <stdarg.h>
22#include <stdlib.h>
23#include <stdio.h>
24#include <string.h>
25#include <inttypes.h>
26
27#include "cpu.h"
28#include "exec-all.h"
29#include "disas.h"
57fec1fe 30#include "tcg-op.h"
79383c9c 31#include "qemu-log.h"
1497c961 32
a7812ae4 33#include "helpers.h"
1497c961 34#define GEN_HELPER 1
b26eefb6 35#include "helpers.h"
2c0262af 36
be5e7a76
DES		 37#define ENABLE_ARCH_4T arm_feature(env, ARM_FEATURE_V4T)
38#define ENABLE_ARCH_5 arm_feature(env, ARM_FEATURE_V5)
39/* currently all emulated v5 cores are also v5TE, so don't bother */
40#define ENABLE_ARCH_5TE arm_feature(env, ARM_FEATURE_V5)
9ee6e8bb
PB		 41#define ENABLE_ARCH_5J 0
42#define ENABLE_ARCH_6 arm_feature(env, ARM_FEATURE_V6)
43#define ENABLE_ARCH_6K arm_feature(env, ARM_FEATURE_V6K)
44#define ENABLE_ARCH_6T2 arm_feature(env, ARM_FEATURE_THUMB2)
45#define ENABLE_ARCH_7 arm_feature(env, ARM_FEATURE_V7)
b5ff1b31 46
86753403 47#define ARCH(x) do { if (!ENABLE_ARCH_##x) goto illegal_op; } while(0)
b5ff1b31 48
2c0262af
FB		 49/* internal defines */
50typedef struct DisasContext {
0fa85d43 51 target_ulong pc;
2c0262af 52 int is_jmp;
e50e6a20
FB		 53 /* Nonzero if this instruction has been conditionally skipped. */
54 int condjmp;
55 /* The label that will be jumped to when the instruction is skipped. */
56 int condlabel;
9ee6e8bb
PB		 57 /* Thumb-2 condtional execution bits. */
58 int condexec_mask;
59 int condexec_cond;
2c0262af 60 struct TranslationBlock *tb;
8aaca4c0 61 int singlestep_enabled;
5899f386 62 int thumb;
b5ff1b31
FB		 63#if !defined(CONFIG_USER_ONLY)
64 int user;
65#endif
5df8bac1 66 int vfp_enabled;
69d1fc22
PM		 67 int vec_len;
68 int vec_stride;
2c0262af
FB		 69} DisasContext;
70
e12ce78d
PM		 71static uint32_t gen_opc_condexec_bits[OPC_BUF_SIZE];
72
b5ff1b31
FB		 73#if defined(CONFIG_USER_ONLY)
74#define IS_USER(s) 1
75#else
76#define IS_USER(s) (s->user)
77#endif
78
9ee6e8bb
PB		 79/* These instructions trap after executing, so defer them until after the
80 conditional executions state has been updated. */
81#define DISAS_WFI 4
82#define DISAS_SWI 5
2c0262af 83
a7812ae4 84static TCGv_ptr cpu_env;
ad69471c 85/* We reuse the same 64-bit temporaries for efficiency. */
a7812ae4 86static TCGv_i64 cpu_V0, cpu_V1, cpu_M0;
155c3eac 87static TCGv_i32 cpu_R[16];
426f5abc
PB		 88static TCGv_i32 cpu_exclusive_addr;
89static TCGv_i32 cpu_exclusive_val;
90static TCGv_i32 cpu_exclusive_high;
91#ifdef CONFIG_USER_ONLY
92static TCGv_i32 cpu_exclusive_test;
93static TCGv_i32 cpu_exclusive_info;
94#endif
ad69471c 95
b26eefb6 96/* FIXME: These should be removed. */
a7812ae4
PB		 97static TCGv cpu_F0s, cpu_F1s;
98static TCGv_i64 cpu_F0d, cpu_F1d;
b26eefb6 99
2e70f6ef
PB		 100#include "gen-icount.h"
101
155c3eac
FN		 102static const char *regnames[] =
103 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
104 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "pc" };
105
b26eefb6
PB		 106/* initialize TCG globals. */
107void arm_translate_init(void)
108{
155c3eac
FN		 109 int i;
110
a7812ae4
PB		 111 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
112
155c3eac
FN		 113 for (i = 0; i < 16; i++) {
114 cpu_R[i] = tcg_global_mem_new_i32(TCG_AREG0,
115 offsetof(CPUState, regs[i]),
116 regnames[i]);
117 }
426f5abc
PB		 118 cpu_exclusive_addr = tcg_global_mem_new_i32(TCG_AREG0,
119 offsetof(CPUState, exclusive_addr), "exclusive_addr");
120 cpu_exclusive_val = tcg_global_mem_new_i32(TCG_AREG0,
121 offsetof(CPUState, exclusive_val), "exclusive_val");
122 cpu_exclusive_high = tcg_global_mem_new_i32(TCG_AREG0,
123 offsetof(CPUState, exclusive_high), "exclusive_high");
124#ifdef CONFIG_USER_ONLY
125 cpu_exclusive_test = tcg_global_mem_new_i32(TCG_AREG0,
126 offsetof(CPUState, exclusive_test), "exclusive_test");
127 cpu_exclusive_info = tcg_global_mem_new_i32(TCG_AREG0,
128 offsetof(CPUState, exclusive_info), "exclusive_info");
129#endif
155c3eac 130
a7812ae4
PB		 131#define GEN_HELPER 2
132#include "helpers.h"
b26eefb6
PB		 133}
134
d9ba4830
PB		 135static inline TCGv load_cpu_offset(int offset)
136{
7d1b0095 137 TCGv tmp = tcg_temp_new_i32();
d9ba4830
PB		 138 tcg_gen_ld_i32(tmp, cpu_env, offset);
139 return tmp;
140}
141
142#define load_cpu_field(name) load_cpu_offset(offsetof(CPUState, name))
143
144static inline void store_cpu_offset(TCGv var, int offset)
145{
146 tcg_gen_st_i32(var, cpu_env, offset);
7d1b0095 147 tcg_temp_free_i32(var);
d9ba4830
PB		 148}
149
150#define store_cpu_field(var, name) \
151 store_cpu_offset(var, offsetof(CPUState, name))
152
b26eefb6
PB		 153/* Set a variable to the value of a CPU register. */
154static void load_reg_var(DisasContext *s, TCGv var, int reg)
155{
156 if (reg == 15) {
157 uint32_t addr;
158 /* normaly, since we updated PC, we need only to add one insn */
159 if (s->thumb)
160 addr = (long)s->pc + 2;
161 else
162 addr = (long)s->pc + 4;
163 tcg_gen_movi_i32(var, addr);
164 } else {
155c3eac 165 tcg_gen_mov_i32(var, cpu_R[reg]);
b26eefb6
PB		 166 }
167}
168
169/* Create a new temporary and set it to the value of a CPU register. */
170static inline TCGv load_reg(DisasContext *s, int reg)
171{
7d1b0095 172 TCGv tmp = tcg_temp_new_i32();
b26eefb6
PB		 173 load_reg_var(s, tmp, reg);
174 return tmp;
175}
176
177/* Set a CPU register. The source must be a temporary and will be
178 marked as dead. */
179static void store_reg(DisasContext *s, int reg, TCGv var)
180{
181 if (reg == 15) {
182 tcg_gen_andi_i32(var, var, ~1);
183 s->is_jmp = DISAS_JUMP;
184 }
155c3eac 185 tcg_gen_mov_i32(cpu_R[reg], var);
7d1b0095 186 tcg_temp_free_i32(var);
b26eefb6
PB		 187}
188
b26eefb6 189/* Value extensions. */
86831435
PB		 190#define gen_uxtb(var) tcg_gen_ext8u_i32(var, var)
191#define gen_uxth(var) tcg_gen_ext16u_i32(var, var)
b26eefb6
PB		 192#define gen_sxtb(var) tcg_gen_ext8s_i32(var, var)
193#define gen_sxth(var) tcg_gen_ext16s_i32(var, var)
194
1497c961
PB		 195#define gen_sxtb16(var) gen_helper_sxtb16(var, var)
196#define gen_uxtb16(var) gen_helper_uxtb16(var, var)
8f01245e 197
b26eefb6 198
b75263d6
JR		 199static inline void gen_set_cpsr(TCGv var, uint32_t mask)
200{
201 TCGv tmp_mask = tcg_const_i32(mask);
202 gen_helper_cpsr_write(var, tmp_mask);
203 tcg_temp_free_i32(tmp_mask);
204}
d9ba4830
PB		 205/* Set NZCV flags from the high 4 bits of var. */
206#define gen_set_nzcv(var) gen_set_cpsr(var, CPSR_NZCV)
207
208static void gen_exception(int excp)
209{
7d1b0095 210 TCGv tmp = tcg_temp_new_i32();
d9ba4830
PB		 211 tcg_gen_movi_i32(tmp, excp);
212 gen_helper_exception(tmp);
7d1b0095 213 tcg_temp_free_i32(tmp);
d9ba4830
PB		 214}
215
3670669c
PB		 216static void gen_smul_dual(TCGv a, TCGv b)
217{
7d1b0095
PM		 218 TCGv tmp1 = tcg_temp_new_i32();
219 TCGv tmp2 = tcg_temp_new_i32();
22478e79
AZ		 220 tcg_gen_ext16s_i32(tmp1, a);
221 tcg_gen_ext16s_i32(tmp2, b);
3670669c 222 tcg_gen_mul_i32(tmp1, tmp1, tmp2);
7d1b0095 223 tcg_temp_free_i32(tmp2);
3670669c
PB		 224 tcg_gen_sari_i32(a, a, 16);
225 tcg_gen_sari_i32(b, b, 16);
226 tcg_gen_mul_i32(b, b, a);
227 tcg_gen_mov_i32(a, tmp1);
7d1b0095 228 tcg_temp_free_i32(tmp1);
3670669c
PB		 229}
230
231/* Byteswap each halfword. */
232static void gen_rev16(TCGv var)
233{
7d1b0095 234 TCGv tmp = tcg_temp_new_i32();
3670669c
PB		 235 tcg_gen_shri_i32(tmp, var, 8);
236 tcg_gen_andi_i32(tmp, tmp, 0x00ff00ff);
237 tcg_gen_shli_i32(var, var, 8);
238 tcg_gen_andi_i32(var, var, 0xff00ff00);
239 tcg_gen_or_i32(var, var, tmp);
7d1b0095 240 tcg_temp_free_i32(tmp);
3670669c
PB		 241}
242
243/* Byteswap low halfword and sign extend. */
244static void gen_revsh(TCGv var)
245{
1a855029
AJ		 246 tcg_gen_ext16u_i32(var, var);
247 tcg_gen_bswap16_i32(var, var);
248 tcg_gen_ext16s_i32(var, var);
3670669c
PB		 249}
250
251/* Unsigned bitfield extract. */
252static void gen_ubfx(TCGv var, int shift, uint32_t mask)
253{
254 if (shift)
255 tcg_gen_shri_i32(var, var, shift);
256 tcg_gen_andi_i32(var, var, mask);
257}
258
259/* Signed bitfield extract. */
260static void gen_sbfx(TCGv var, int shift, int width)
261{
262 uint32_t signbit;
263
264 if (shift)
265 tcg_gen_sari_i32(var, var, shift);
266 if (shift + width < 32) {
267 signbit = 1u << (width - 1);
268 tcg_gen_andi_i32(var, var, (1u << width) - 1);
269 tcg_gen_xori_i32(var, var, signbit);
270 tcg_gen_subi_i32(var, var, signbit);
271 }
272}
273
274/* Bitfield insertion. Insert val into base. Clobbers base and val. */
275static void gen_bfi(TCGv dest, TCGv base, TCGv val, int shift, uint32_t mask)
276{
3670669c 277 tcg_gen_andi_i32(val, val, mask);
8f8e3aa4
PB		 278 tcg_gen_shli_i32(val, val, shift);
279 tcg_gen_andi_i32(base, base, ~(mask << shift));
3670669c
PB		 280 tcg_gen_or_i32(dest, base, val);
281}
282
838fa72d
AJ		 283/* Return (b << 32) + a. Mark inputs as dead */
284static TCGv_i64 gen_addq_msw(TCGv_i64 a, TCGv b)
3670669c 285{
838fa72d
AJ		 286 TCGv_i64 tmp64 = tcg_temp_new_i64();
287
288 tcg_gen_extu_i32_i64(tmp64, b);
7d1b0095 289 tcg_temp_free_i32(b);
838fa72d
AJ		 290 tcg_gen_shli_i64(tmp64, tmp64, 32);
291 tcg_gen_add_i64(a, tmp64, a);
292
293 tcg_temp_free_i64(tmp64);
294 return a;
295}
296
297/* Return (b << 32) - a. Mark inputs as dead. */
298static TCGv_i64 gen_subq_msw(TCGv_i64 a, TCGv b)
299{
300 TCGv_i64 tmp64 = tcg_temp_new_i64();
301
302 tcg_gen_extu_i32_i64(tmp64, b);
7d1b0095 303 tcg_temp_free_i32(b);
838fa72d
AJ		 304 tcg_gen_shli_i64(tmp64, tmp64, 32);
305 tcg_gen_sub_i64(a, tmp64, a);
306
307 tcg_temp_free_i64(tmp64);
308 return a;
3670669c
PB		 309}
310
8f01245e
PB		 311/* FIXME: Most targets have native widening multiplication.
312 It would be good to use that instead of a full wide multiply. */
5e3f878a 313/* 32x32->64 multiply. Marks inputs as dead. */
a7812ae4 314static TCGv_i64 gen_mulu_i64_i32(TCGv a, TCGv b)
5e3f878a 315{
a7812ae4
PB		 316 TCGv_i64 tmp1 = tcg_temp_new_i64();
317 TCGv_i64 tmp2 = tcg_temp_new_i64();
5e3f878a
PB		 318
319 tcg_gen_extu_i32_i64(tmp1, a);
7d1b0095 320 tcg_temp_free_i32(a);
5e3f878a 321 tcg_gen_extu_i32_i64(tmp2, b);
7d1b0095 322 tcg_temp_free_i32(b);
5e3f878a 323 tcg_gen_mul_i64(tmp1, tmp1, tmp2);
b75263d6 324 tcg_temp_free_i64(tmp2);
5e3f878a
PB		 325 return tmp1;
326}
327
a7812ae4 328static TCGv_i64 gen_muls_i64_i32(TCGv a, TCGv b)
5e3f878a 329{
a7812ae4
PB		 330 TCGv_i64 tmp1 = tcg_temp_new_i64();
331 TCGv_i64 tmp2 = tcg_temp_new_i64();
5e3f878a
PB		 332
333 tcg_gen_ext_i32_i64(tmp1, a);
7d1b0095 334 tcg_temp_free_i32(a);
5e3f878a 335 tcg_gen_ext_i32_i64(tmp2, b);
7d1b0095 336 tcg_temp_free_i32(b);
5e3f878a 337 tcg_gen_mul_i64(tmp1, tmp1, tmp2);
b75263d6 338 tcg_temp_free_i64(tmp2);
5e3f878a
PB		 339 return tmp1;
340}
341
8f01245e
PB		 342/* Swap low and high halfwords. */
343static void gen_swap_half(TCGv var)
344{
7d1b0095 345 TCGv tmp = tcg_temp_new_i32();
8f01245e
PB		 346 tcg_gen_shri_i32(tmp, var, 16);
347 tcg_gen_shli_i32(var, var, 16);
348 tcg_gen_or_i32(var, var, tmp);
7d1b0095 349 tcg_temp_free_i32(tmp);
8f01245e
PB		 350}
351
b26eefb6
PB		 352/* Dual 16-bit add. Result placed in t0 and t1 is marked as dead.
353 tmp = (t0 ^ t1) & 0x8000;
354 t0 &= ~0x8000;
355 t1 &= ~0x8000;
356 t0 = (t0 + t1) ^ tmp;
357 */
358
359static void gen_add16(TCGv t0, TCGv t1)
360{
7d1b0095 361 TCGv tmp = tcg_temp_new_i32();
b26eefb6
PB		 362 tcg_gen_xor_i32(tmp, t0, t1);
363 tcg_gen_andi_i32(tmp, tmp, 0x8000);
364 tcg_gen_andi_i32(t0, t0, ~0x8000);
365 tcg_gen_andi_i32(t1, t1, ~0x8000);
366 tcg_gen_add_i32(t0, t0, t1);
367 tcg_gen_xor_i32(t0, t0, tmp);
7d1b0095
PM		 368 tcg_temp_free_i32(tmp);
369 tcg_temp_free_i32(t1);
b26eefb6
PB		 370}
371
9a119ff6
PB		 372#define gen_set_CF(var) tcg_gen_st_i32(var, cpu_env, offsetof(CPUState, CF))
373
b26eefb6
PB		 374/* Set CF to the top bit of var. */
375static void gen_set_CF_bit31(TCGv var)
376{
7d1b0095 377 TCGv tmp = tcg_temp_new_i32();
b26eefb6 378 tcg_gen_shri_i32(tmp, var, 31);
4cc633c3 379 gen_set_CF(tmp);
7d1b0095 380 tcg_temp_free_i32(tmp);
b26eefb6
PB		 381}
382
383/* Set N and Z flags from var. */
384static inline void gen_logic_CC(TCGv var)
385{
6fbe23d5
PB		 386 tcg_gen_st_i32(var, cpu_env, offsetof(CPUState, NF));
387 tcg_gen_st_i32(var, cpu_env, offsetof(CPUState, ZF));
b26eefb6
PB		 388}
389
390/* T0 += T1 + CF. */
396e467c 391static void gen_adc(TCGv t0, TCGv t1)
b26eefb6 392{
d9ba4830 393 TCGv tmp;
396e467c 394 tcg_gen_add_i32(t0, t0, t1);
d9ba4830 395 tmp = load_cpu_field(CF);
396e467c 396 tcg_gen_add_i32(t0, t0, tmp);
7d1b0095 397 tcg_temp_free_i32(tmp);
b26eefb6
PB		 398}
399
e9bb4aa9
JR		 400/* dest = T0 + T1 + CF. */
401static void gen_add_carry(TCGv dest, TCGv t0, TCGv t1)
402{
403 TCGv tmp;
404 tcg_gen_add_i32(dest, t0, t1);
405 tmp = load_cpu_field(CF);
406 tcg_gen_add_i32(dest, dest, tmp);
7d1b0095 407 tcg_temp_free_i32(tmp);
e9bb4aa9
JR		 408}
409
3670669c
PB		 410/* dest = T0 - T1 + CF - 1. */
411static void gen_sub_carry(TCGv dest, TCGv t0, TCGv t1)
412{
d9ba4830 413 TCGv tmp;
3670669c 414 tcg_gen_sub_i32(dest, t0, t1);
d9ba4830 415 tmp = load_cpu_field(CF);
3670669c
PB		 416 tcg_gen_add_i32(dest, dest, tmp);
417 tcg_gen_subi_i32(dest, dest, 1);
7d1b0095 418 tcg_temp_free_i32(tmp);
3670669c
PB		 419}
420
ad69471c
PB		 421/* FIXME: Implement this natively. */
422#define tcg_gen_abs_i32(t0, t1) gen_helper_abs(t0, t1)
423
9a119ff6 424static void shifter_out_im(TCGv var, int shift)
b26eefb6 425{
7d1b0095 426 TCGv tmp = tcg_temp_new_i32();
9a119ff6
PB		 427 if (shift == 0) {
428 tcg_gen_andi_i32(tmp, var, 1);
b26eefb6 429 } else {
9a119ff6 430 tcg_gen_shri_i32(tmp, var, shift);
4cc633c3 431 if (shift != 31)
9a119ff6
PB		 432 tcg_gen_andi_i32(tmp, tmp, 1);
433 }
434 gen_set_CF(tmp);
7d1b0095 435 tcg_temp_free_i32(tmp);
9a119ff6 436}
b26eefb6 437
9a119ff6
PB		 438/* Shift by immediate. Includes special handling for shift == 0. */
439static inline void gen_arm_shift_im(TCGv var, int shiftop, int shift, int flags)
440{
441 switch (shiftop) {
442 case 0: /* LSL */
443 if (shift != 0) {
444 if (flags)
445 shifter_out_im(var, 32 - shift);
446 tcg_gen_shli_i32(var, var, shift);
447 }
448 break;
449 case 1: /* LSR */
450 if (shift == 0) {
451 if (flags) {
452 tcg_gen_shri_i32(var, var, 31);
453 gen_set_CF(var);
454 }
455 tcg_gen_movi_i32(var, 0);
456 } else {
457 if (flags)
458 shifter_out_im(var, shift - 1);
459 tcg_gen_shri_i32(var, var, shift);
460 }
461 break;
462 case 2: /* ASR */
463 if (shift == 0)
464 shift = 32;
465 if (flags)
466 shifter_out_im(var, shift - 1);
467 if (shift == 32)
468 shift = 31;
469 tcg_gen_sari_i32(var, var, shift);
470 break;
471 case 3: /* ROR/RRX */
472 if (shift != 0) {
473 if (flags)
474 shifter_out_im(var, shift - 1);
f669df27 475 tcg_gen_rotri_i32(var, var, shift); break;
9a119ff6 476 } else {
d9ba4830 477 TCGv tmp = load_cpu_field(CF);
9a119ff6
PB		 478 if (flags)
479 shifter_out_im(var, 0);
480 tcg_gen_shri_i32(var, var, 1);
b26eefb6
PB		 481 tcg_gen_shli_i32(tmp, tmp, 31);
482 tcg_gen_or_i32(var, var, tmp);
7d1b0095 483 tcg_temp_free_i32(tmp);
b26eefb6
PB		 484 }
485 }
486};
487
8984bd2e
PB		 488static inline void gen_arm_shift_reg(TCGv var, int shiftop,
489 TCGv shift, int flags)
490{
491 if (flags) {
492 switch (shiftop) {
493 case 0: gen_helper_shl_cc(var, var, shift); break;
494 case 1: gen_helper_shr_cc(var, var, shift); break;
495 case 2: gen_helper_sar_cc(var, var, shift); break;
496 case 3: gen_helper_ror_cc(var, var, shift); break;
497 }
498 } else {
499 switch (shiftop) {
500 case 0: gen_helper_shl(var, var, shift); break;
501 case 1: gen_helper_shr(var, var, shift); break;
502 case 2: gen_helper_sar(var, var, shift); break;
f669df27
AJ		 503 case 3: tcg_gen_andi_i32(shift, shift, 0x1f);
504 tcg_gen_rotr_i32(var, var, shift); break;
8984bd2e
PB		 505 }
506 }
7d1b0095 507 tcg_temp_free_i32(shift);
8984bd2e
PB		 508}
509
6ddbc6e4
PB		 510#define PAS_OP(pfx) \
511 switch (op2) { \
512 case 0: gen_pas_helper(glue(pfx,add16)); break; \
513 case 1: gen_pas_helper(glue(pfx,addsubx)); break; \
514 case 2: gen_pas_helper(glue(pfx,subaddx)); break; \
515 case 3: gen_pas_helper(glue(pfx,sub16)); break; \
516 case 4: gen_pas_helper(glue(pfx,add8)); break; \
517 case 7: gen_pas_helper(glue(pfx,sub8)); break; \
518 }
d9ba4830 519static void gen_arm_parallel_addsub(int op1, int op2, TCGv a, TCGv b)
6ddbc6e4 520{
a7812ae4 521 TCGv_ptr tmp;
6ddbc6e4
PB		 522
523 switch (op1) {
524#define gen_pas_helper(name) glue(gen_helper_,name)(a, a, b, tmp)
525 case 1:
a7812ae4 526 tmp = tcg_temp_new_ptr();
6ddbc6e4
PB		 527 tcg_gen_addi_ptr(tmp, cpu_env, offsetof(CPUState, GE));
528 PAS_OP(s)
b75263d6 529 tcg_temp_free_ptr(tmp);
6ddbc6e4
PB		 530 break;
531 case 5:
a7812ae4 532 tmp = tcg_temp_new_ptr();
6ddbc6e4
PB		 533 tcg_gen_addi_ptr(tmp, cpu_env, offsetof(CPUState, GE));
534 PAS_OP(u)
b75263d6 535 tcg_temp_free_ptr(tmp);
6ddbc6e4
PB		 536 break;
537#undef gen_pas_helper
538#define gen_pas_helper(name) glue(gen_helper_,name)(a, a, b)
539 case 2:
540 PAS_OP(q);
541 break;
542 case 3:
543 PAS_OP(sh);
544 break;
545 case 6:
546 PAS_OP(uq);
547 break;
548 case 7:
549 PAS_OP(uh);
550 break;
551#undef gen_pas_helper
552 }
553}
9ee6e8bb
PB		 554#undef PAS_OP
555
6ddbc6e4
PB		 556/* For unknown reasons Arm and Thumb-2 use arbitrarily different encodings. */
557#define PAS_OP(pfx) \
ed89a2f1 558 switch (op1) { \
6ddbc6e4
PB		 559 case 0: gen_pas_helper(glue(pfx,add8)); break; \
560 case 1: gen_pas_helper(glue(pfx,add16)); break; \
561 case 2: gen_pas_helper(glue(pfx,addsubx)); break; \
562 case 4: gen_pas_helper(glue(pfx,sub8)); break; \
563 case 5: gen_pas_helper(glue(pfx,sub16)); break; \
564 case 6: gen_pas_helper(glue(pfx,subaddx)); break; \
565 }
d9ba4830 566static void gen_thumb2_parallel_addsub(int op1, int op2, TCGv a, TCGv b)
6ddbc6e4 567{
a7812ae4 568 TCGv_ptr tmp;
6ddbc6e4 569
ed89a2f1 570 switch (op2) {
6ddbc6e4
PB		 571#define gen_pas_helper(name) glue(gen_helper_,name)(a, a, b, tmp)
572 case 0:
a7812ae4 573 tmp = tcg_temp_new_ptr();
6ddbc6e4
PB		 574 tcg_gen_addi_ptr(tmp, cpu_env, offsetof(CPUState, GE));
575 PAS_OP(s)
b75263d6 576 tcg_temp_free_ptr(tmp);
6ddbc6e4
PB		 577 break;
578 case 4:
a7812ae4 579 tmp = tcg_temp_new_ptr();
6ddbc6e4
PB		 580 tcg_gen_addi_ptr(tmp, cpu_env, offsetof(CPUState, GE));
581 PAS_OP(u)
b75263d6 582 tcg_temp_free_ptr(tmp);
6ddbc6e4
PB		 583 break;
584#undef gen_pas_helper
585#define gen_pas_helper(name) glue(gen_helper_,name)(a, a, b)
586 case 1:
587 PAS_OP(q);
588 break;
589 case 2:
590 PAS_OP(sh);
591 break;
592 case 5:
593 PAS_OP(uq);
594 break;
595 case 6:
596 PAS_OP(uh);
597 break;
598#undef gen_pas_helper
599 }
600}
9ee6e8bb
PB		 601#undef PAS_OP
602
d9ba4830
PB		 603static void gen_test_cc(int cc, int label)
604{
605 TCGv tmp;
606 TCGv tmp2;
d9ba4830
PB		 607 int inv;
608
d9ba4830
PB		 609 switch (cc) {
610 case 0: /* eq: Z */
6fbe23d5 611 tmp = load_cpu_field(ZF);
cb63669a 612 tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, label);
d9ba4830
PB		 613 break;
614 case 1: /* ne: !Z */
6fbe23d5 615 tmp = load_cpu_field(ZF);
cb63669a 616 tcg_gen_brcondi_i32(TCG_COND_NE, tmp, 0, label);
d9ba4830
PB		 617 break;
618 case 2: /* cs: C */
619 tmp = load_cpu_field(CF);
cb63669a 620 tcg_gen_brcondi_i32(TCG_COND_NE, tmp, 0, label);
d9ba4830
PB		 621 break;
622 case 3: /* cc: !C */
623 tmp = load_cpu_field(CF);
cb63669a 624 tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, label);
d9ba4830
PB		 625 break;
626 case 4: /* mi: N */
6fbe23d5 627 tmp = load_cpu_field(NF);
cb63669a 628 tcg_gen_brcondi_i32(TCG_COND_LT, tmp, 0, label);
d9ba4830
PB		 629 break;
630 case 5: /* pl: !N */
6fbe23d5 631 tmp = load_cpu_field(NF);
cb63669a 632 tcg_gen_brcondi_i32(TCG_COND_GE, tmp, 0, label);
d9ba4830
PB		 633 break;
634 case 6: /* vs: V */
635 tmp = load_cpu_field(VF);
cb63669a 636 tcg_gen_brcondi_i32(TCG_COND_LT, tmp, 0, label);
d9ba4830
PB		 637 break;
638 case 7: /* vc: !V */
639 tmp = load_cpu_field(VF);
cb63669a 640 tcg_gen_brcondi_i32(TCG_COND_GE, tmp, 0, label);
d9ba4830
PB		 641 break;
642 case 8: /* hi: C && !Z */
643 inv = gen_new_label();
644 tmp = load_cpu_field(CF);
cb63669a 645 tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, inv);
7d1b0095 646 tcg_temp_free_i32(tmp);
6fbe23d5 647 tmp = load_cpu_field(ZF);
cb63669a 648 tcg_gen_brcondi_i32(TCG_COND_NE, tmp, 0, label);
d9ba4830
PB		 649 gen_set_label(inv);
650 break;
651 case 9: /* ls: !C || Z */
652 tmp = load_cpu_field(CF);
cb63669a 653 tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, label);
7d1b0095 654 tcg_temp_free_i32(tmp);
6fbe23d5 655 tmp = load_cpu_field(ZF);
cb63669a 656 tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, label);
d9ba4830
PB		 657 break;
658 case 10: /* ge: N == V -> N ^ V == 0 */
659 tmp = load_cpu_field(VF);
6fbe23d5 660 tmp2 = load_cpu_field(NF);
d9ba4830 661 tcg_gen_xor_i32(tmp, tmp, tmp2);
7d1b0095 662 tcg_temp_free_i32(tmp2);
cb63669a 663 tcg_gen_brcondi_i32(TCG_COND_GE, tmp, 0, label);
d9ba4830
PB		 664 break;
665 case 11: /* lt: N != V -> N ^ V != 0 */
666 tmp = load_cpu_field(VF);
6fbe23d5 667 tmp2 = load_cpu_field(NF);
d9ba4830 668 tcg_gen_xor_i32(tmp, tmp, tmp2);
7d1b0095 669 tcg_temp_free_i32(tmp2);
cb63669a 670 tcg_gen_brcondi_i32(TCG_COND_LT, tmp, 0, label);
d9ba4830
PB		 671 break;
672 case 12: /* gt: !Z && N == V */
673 inv = gen_new_label();
6fbe23d5 674 tmp = load_cpu_field(ZF);
cb63669a 675 tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, inv);
7d1b0095 676 tcg_temp_free_i32(tmp);
d9ba4830 677 tmp = load_cpu_field(VF);
6fbe23d5 678 tmp2 = load_cpu_field(NF);
d9ba4830 679 tcg_gen_xor_i32(tmp, tmp, tmp2);
7d1b0095 680 tcg_temp_free_i32(tmp2);
cb63669a 681 tcg_gen_brcondi_i32(TCG_COND_GE, tmp, 0, label);
d9ba4830
PB		 682 gen_set_label(inv);
683 break;
684 case 13: /* le: Z || N != V */
6fbe23d5 685 tmp = load_cpu_field(ZF);
cb63669a 686 tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, label);
7d1b0095 687 tcg_temp_free_i32(tmp);
d9ba4830 688 tmp = load_cpu_field(VF);
6fbe23d5 689 tmp2 = load_cpu_field(NF);
d9ba4830 690 tcg_gen_xor_i32(tmp, tmp, tmp2);
7d1b0095 691 tcg_temp_free_i32(tmp2);
cb63669a 692 tcg_gen_brcondi_i32(TCG_COND_LT, tmp, 0, label);
d9ba4830
PB		 693 break;
694 default:
695 fprintf(stderr, "Bad condition code 0x%x\n", cc);
696 abort();
697 }
7d1b0095 698 tcg_temp_free_i32(tmp);
d9ba4830 699}
2c0262af 700
b1d8e52e 701static const uint8_t table_logic_cc[16] = {
2c0262af
FB		 702 1, /* and */
703 1, /* xor */
704 0, /* sub */
705 0, /* rsb */
706 0, /* add */
707 0, /* adc */
708 0, /* sbc */
709 0, /* rsc */
710 1, /* andl */
711 1, /* xorl */
712 0, /* cmp */
713 0, /* cmn */
714 1, /* orr */
715 1, /* mov */
716 1, /* bic */
717 1, /* mvn */
718};
3b46e624 719
d9ba4830
PB		 720/* Set PC and Thumb state from an immediate address. */
721static inline void gen_bx_im(DisasContext *s, uint32_t addr)
99c475ab 722{
b26eefb6 723 TCGv tmp;
99c475ab 724
b26eefb6 725 s->is_jmp = DISAS_UPDATE;
d9ba4830 726 if (s->thumb != (addr & 1)) {
7d1b0095 727 tmp = tcg_temp_new_i32();
d9ba4830
PB		 728 tcg_gen_movi_i32(tmp, addr & 1);
729 tcg_gen_st_i32(tmp, cpu_env, offsetof(CPUState, thumb));
7d1b0095 730 tcg_temp_free_i32(tmp);
d9ba4830 731 }
155c3eac 732 tcg_gen_movi_i32(cpu_R[15], addr & ~1);
d9ba4830
PB		 733}
734
735/* Set PC and Thumb state from var. var is marked as dead. */
736static inline void gen_bx(DisasContext *s, TCGv var)
737{
d9ba4830 738 s->is_jmp = DISAS_UPDATE;
155c3eac
FN		 739 tcg_gen_andi_i32(cpu_R[15], var, ~1);
740 tcg_gen_andi_i32(var, var, 1);
741 store_cpu_field(var, thumb);
d9ba4830
PB		 742}
743
21aeb343
JR		 744/* Variant of store_reg which uses branch&exchange logic when storing
745 to r15 in ARM architecture v7 and above. The source must be a temporary
746 and will be marked as dead. */
747static inline void store_reg_bx(CPUState *env, DisasContext *s,
748 int reg, TCGv var)
749{
750 if (reg == 15 && ENABLE_ARCH_7) {
751 gen_bx(s, var);
752 } else {
753 store_reg(s, reg, var);
754 }
755}
756
be5e7a76
DES		 757/* Variant of store_reg which uses branch&exchange logic when storing
758 * to r15 in ARM architecture v5T and above. This is used for storing
759 * the results of a LDR/LDM/POP into r15, and corresponds to the cases
760 * in the ARM ARM which use the LoadWritePC() pseudocode function. */
761static inline void store_reg_from_load(CPUState *env, DisasContext *s,
762 int reg, TCGv var)
763{
764 if (reg == 15 && ENABLE_ARCH_5) {
765 gen_bx(s, var);
766 } else {
767 store_reg(s, reg, var);
768 }
769}
770
b0109805
PB		 771static inline TCGv gen_ld8s(TCGv addr, int index)
772{
7d1b0095 773 TCGv tmp = tcg_temp_new_i32();
b0109805
PB		 774 tcg_gen_qemu_ld8s(tmp, addr, index);
775 return tmp;
776}
777static inline TCGv gen_ld8u(TCGv addr, int index)
778{
7d1b0095 779 TCGv tmp = tcg_temp_new_i32();
b0109805
PB		 780 tcg_gen_qemu_ld8u(tmp, addr, index);
781 return tmp;
782}
783static inline TCGv gen_ld16s(TCGv addr, int index)
784{
7d1b0095 785 TCGv tmp = tcg_temp_new_i32();
b0109805
PB		 786 tcg_gen_qemu_ld16s(tmp, addr, index);
787 return tmp;
788}
789static inline TCGv gen_ld16u(TCGv addr, int index)
790{
7d1b0095 791 TCGv tmp = tcg_temp_new_i32();
b0109805
PB		 792 tcg_gen_qemu_ld16u(tmp, addr, index);
793 return tmp;
794}
795static inline TCGv gen_ld32(TCGv addr, int index)
796{
7d1b0095 797 TCGv tmp = tcg_temp_new_i32();
b0109805
PB		 798 tcg_gen_qemu_ld32u(tmp, addr, index);
799 return tmp;
800}
84496233
JR		 801static inline TCGv_i64 gen_ld64(TCGv addr, int index)
802{
803 TCGv_i64 tmp = tcg_temp_new_i64();
804 tcg_gen_qemu_ld64(tmp, addr, index);
805 return tmp;
806}
b0109805
PB		 807static inline void gen_st8(TCGv val, TCGv addr, int index)
808{
809 tcg_gen_qemu_st8(val, addr, index);
7d1b0095 810 tcg_temp_free_i32(val);
b0109805
PB		 811}
812static inline void gen_st16(TCGv val, TCGv addr, int index)
813{
814 tcg_gen_qemu_st16(val, addr, index);
7d1b0095 815 tcg_temp_free_i32(val);
b0109805
PB		 816}
817static inline void gen_st32(TCGv val, TCGv addr, int index)
818{
819 tcg_gen_qemu_st32(val, addr, index);
7d1b0095 820 tcg_temp_free_i32(val);
b0109805 821}
84496233
JR		 822static inline void gen_st64(TCGv_i64 val, TCGv addr, int index)
823{
824 tcg_gen_qemu_st64(val, addr, index);
825 tcg_temp_free_i64(val);
826}
b5ff1b31 827
5e3f878a
PB		 828static inline void gen_set_pc_im(uint32_t val)
829{
155c3eac 830 tcg_gen_movi_i32(cpu_R[15], val);
5e3f878a
PB		 831}
832
b5ff1b31
FB		 833/* Force a TB lookup after an instruction that changes the CPU state. */
834static inline void gen_lookup_tb(DisasContext *s)
835{
a6445c52 836 tcg_gen_movi_i32(cpu_R[15], s->pc & ~1);
b5ff1b31
FB		 837 s->is_jmp = DISAS_UPDATE;
838}
839
b0109805
PB		 840static inline void gen_add_data_offset(DisasContext *s, unsigned int insn,
841 TCGv var)
2c0262af 842{
1e8d4eec 843 int val, rm, shift, shiftop;
b26eefb6 844 TCGv offset;
2c0262af
FB		 845
846 if (!(insn & (1 << 25))) {
847 /* immediate */
848 val = insn & 0xfff;
849 if (!(insn & (1 << 23)))
850 val = -val;
537730b9 851 if (val != 0)
b0109805 852 tcg_gen_addi_i32(var, var, val);
2c0262af
FB		 853 } else {
854 /* shift/register */
855 rm = (insn) & 0xf;
856 shift = (insn >> 7) & 0x1f;
1e8d4eec 857 shiftop = (insn >> 5) & 3;
b26eefb6 858 offset = load_reg(s, rm);
9a119ff6 859 gen_arm_shift_im(offset, shiftop, shift, 0);
2c0262af 860 if (!(insn & (1 << 23)))
b0109805 861 tcg_gen_sub_i32(var, var, offset);
2c0262af 862 else
b0109805 863 tcg_gen_add_i32(var, var, offset);
7d1b0095 864 tcg_temp_free_i32(offset);
2c0262af
FB		 865 }
866}
867
191f9a93 868static inline void gen_add_datah_offset(DisasContext *s, unsigned int insn,
b0109805 869 int extra, TCGv var)
2c0262af
FB		 870{
871 int val, rm;
b26eefb6 872 TCGv offset;
3b46e624 873
2c0262af
FB		 874 if (insn & (1 << 22)) {
875 /* immediate */
876 val = (insn & 0xf) | ((insn >> 4) & 0xf0);
877 if (!(insn & (1 << 23)))
878 val = -val;
18acad92 879 val += extra;
537730b9 880 if (val != 0)
b0109805 881 tcg_gen_addi_i32(var, var, val);
2c0262af
FB		 882 } else {
883 /* register */
191f9a93 884 if (extra)
b0109805 885 tcg_gen_addi_i32(var, var, extra);
2c0262af 886 rm = (insn) & 0xf;
b26eefb6 887 offset = load_reg(s, rm);
2c0262af 888 if (!(insn & (1 << 23)))
b0109805 889 tcg_gen_sub_i32(var, var, offset);
2c0262af 890 else
b0109805 891 tcg_gen_add_i32(var, var, offset);
7d1b0095 892 tcg_temp_free_i32(offset);
2c0262af
FB		 893 }
894}
895
4373f3ce
PB		 896#define VFP_OP2(name) \
897static inline void gen_vfp_##name(int dp) \
898{ \
899 if (dp) \
900 gen_helper_vfp_##name##d(cpu_F0d, cpu_F0d, cpu_F1d, cpu_env); \
901 else \
902 gen_helper_vfp_##name##s(cpu_F0s, cpu_F0s, cpu_F1s, cpu_env); \
b7bcbe95
FB		 903}
904
4373f3ce
PB		 905VFP_OP2(add)
906VFP_OP2(sub)
907VFP_OP2(mul)
908VFP_OP2(div)
909
910#undef VFP_OP2
911
912static inline void gen_vfp_abs(int dp)
913{
914 if (dp)
915 gen_helper_vfp_absd(cpu_F0d, cpu_F0d);
916 else
917 gen_helper_vfp_abss(cpu_F0s, cpu_F0s);
918}
919
920static inline void gen_vfp_neg(int dp)
921{
922 if (dp)
923 gen_helper_vfp_negd(cpu_F0d, cpu_F0d);
924 else
925 gen_helper_vfp_negs(cpu_F0s, cpu_F0s);
926}
927
928static inline void gen_vfp_sqrt(int dp)
929{
930 if (dp)
931 gen_helper_vfp_sqrtd(cpu_F0d, cpu_F0d, cpu_env);
932 else
933 gen_helper_vfp_sqrts(cpu_F0s, cpu_F0s, cpu_env);
934}
935
936static inline void gen_vfp_cmp(int dp)
937{
938 if (dp)
939 gen_helper_vfp_cmpd(cpu_F0d, cpu_F1d, cpu_env);
940 else
941 gen_helper_vfp_cmps(cpu_F0s, cpu_F1s, cpu_env);
942}
943
944static inline void gen_vfp_cmpe(int dp)
945{
946 if (dp)
947 gen_helper_vfp_cmped(cpu_F0d, cpu_F1d, cpu_env);
948 else
949 gen_helper_vfp_cmpes(cpu_F0s, cpu_F1s, cpu_env);
950}
951
952static inline void gen_vfp_F1_ld0(int dp)
953{
954 if (dp)
5b340b51 955 tcg_gen_movi_i64(cpu_F1d, 0);
4373f3ce 956 else
5b340b51 957 tcg_gen_movi_i32(cpu_F1s, 0);
4373f3ce
PB		 958}
959
960static inline void gen_vfp_uito(int dp)
961{
962 if (dp)
963 gen_helper_vfp_uitod(cpu_F0d, cpu_F0s, cpu_env);
964 else
965 gen_helper_vfp_uitos(cpu_F0s, cpu_F0s, cpu_env);
966}
967
968static inline void gen_vfp_sito(int dp)
969{
970 if (dp)
66230e0d 971 gen_helper_vfp_sitod(cpu_F0d, cpu_F0s, cpu_env);
4373f3ce 972 else
66230e0d 973 gen_helper_vfp_sitos(cpu_F0s, cpu_F0s, cpu_env);
4373f3ce
PB		 974}
975
976static inline void gen_vfp_toui(int dp)
977{
978 if (dp)
979 gen_helper_vfp_touid(cpu_F0s, cpu_F0d, cpu_env);
980 else
981 gen_helper_vfp_touis(cpu_F0s, cpu_F0s, cpu_env);
982}
983
984static inline void gen_vfp_touiz(int dp)
985{
986 if (dp)
987 gen_helper_vfp_touizd(cpu_F0s, cpu_F0d, cpu_env);
988 else
989 gen_helper_vfp_touizs(cpu_F0s, cpu_F0s, cpu_env);
990}
991
992static inline void gen_vfp_tosi(int dp)
993{
994 if (dp)
995 gen_helper_vfp_tosid(cpu_F0s, cpu_F0d, cpu_env);
996 else
997 gen_helper_vfp_tosis(cpu_F0s, cpu_F0s, cpu_env);
998}
999
1000static inline void gen_vfp_tosiz(int dp)
9ee6e8bb
PB		 1001{
1002 if (dp)
4373f3ce 1003 gen_helper_vfp_tosizd(cpu_F0s, cpu_F0d, cpu_env);
9ee6e8bb 1004 else
4373f3ce
PB		 1005 gen_helper_vfp_tosizs(cpu_F0s, cpu_F0s, cpu_env);
1006}
1007
1008#define VFP_GEN_FIX(name) \
1009static inline void gen_vfp_##name(int dp, int shift) \
1010{ \
b75263d6 1011 TCGv tmp_shift = tcg_const_i32(shift); \
4373f3ce 1012 if (dp) \
b75263d6 1013 gen_helper_vfp_##name##d(cpu_F0d, cpu_F0d, tmp_shift, cpu_env);\
4373f3ce 1014 else \
b75263d6
JR		 1015 gen_helper_vfp_##name##s(cpu_F0s, cpu_F0s, tmp_shift, cpu_env);\
1016 tcg_temp_free_i32(tmp_shift); \
9ee6e8bb 1017}
4373f3ce
PB		 1018VFP_GEN_FIX(tosh)
1019VFP_GEN_FIX(tosl)
1020VFP_GEN_FIX(touh)
1021VFP_GEN_FIX(toul)
1022VFP_GEN_FIX(shto)
1023VFP_GEN_FIX(slto)
1024VFP_GEN_FIX(uhto)
1025VFP_GEN_FIX(ulto)
1026#undef VFP_GEN_FIX
9ee6e8bb 1027
312eea9f 1028static inline void gen_vfp_ld(DisasContext *s, int dp, TCGv addr)
b5ff1b31
FB		 1029{
1030 if (dp)
312eea9f 1031 tcg_gen_qemu_ld64(cpu_F0d, addr, IS_USER(s));
b5ff1b31 1032 else
312eea9f 1033 tcg_gen_qemu_ld32u(cpu_F0s, addr, IS_USER(s));
b5ff1b31
FB		 1034}
1035
312eea9f 1036static inline void gen_vfp_st(DisasContext *s, int dp, TCGv addr)
b5ff1b31
FB		 1037{
1038 if (dp)
312eea9f 1039 tcg_gen_qemu_st64(cpu_F0d, addr, IS_USER(s));
b5ff1b31 1040 else
312eea9f 1041 tcg_gen_qemu_st32(cpu_F0s, addr, IS_USER(s));
b5ff1b31
FB		 1042}
1043
8e96005d
FB		 1044static inline long
1045vfp_reg_offset (int dp, int reg)
1046{
1047 if (dp)
1048 return offsetof(CPUARMState, vfp.regs[reg]);
1049 else if (reg & 1) {
1050 return offsetof(CPUARMState, vfp.regs[reg >> 1])
1051 + offsetof(CPU_DoubleU, l.upper);
1052 } else {
1053 return offsetof(CPUARMState, vfp.regs[reg >> 1])
1054 + offsetof(CPU_DoubleU, l.lower);
1055 }
1056}
9ee6e8bb
PB		 1057
1058/* Return the offset of a 32-bit piece of a NEON register.
1059 zero is the least significant end of the register. */
1060static inline long
1061neon_reg_offset (int reg, int n)
1062{
1063 int sreg;
1064 sreg = reg * 2 + n;
1065 return vfp_reg_offset(0, sreg);
1066}
1067
8f8e3aa4
PB		 1068static TCGv neon_load_reg(int reg, int pass)
1069{
7d1b0095 1070 TCGv tmp = tcg_temp_new_i32();
8f8e3aa4
PB		 1071 tcg_gen_ld_i32(tmp, cpu_env, neon_reg_offset(reg, pass));
1072 return tmp;
1073}
1074
1075static void neon_store_reg(int reg, int pass, TCGv var)
1076{
1077 tcg_gen_st_i32(var, cpu_env, neon_reg_offset(reg, pass));
7d1b0095 1078 tcg_temp_free_i32(var);
8f8e3aa4
PB		 1079}
1080
a7812ae4 1081static inline void neon_load_reg64(TCGv_i64 var, int reg)
ad69471c
PB		 1082{
1083 tcg_gen_ld_i64(var, cpu_env, vfp_reg_offset(1, reg));
1084}
1085
a7812ae4 1086static inline void neon_store_reg64(TCGv_i64 var, int reg)
ad69471c
PB		 1087{
1088 tcg_gen_st_i64(var, cpu_env, vfp_reg_offset(1, reg));
1089}
1090
4373f3ce
PB		 1091#define tcg_gen_ld_f32 tcg_gen_ld_i32
1092#define tcg_gen_ld_f64 tcg_gen_ld_i64
1093#define tcg_gen_st_f32 tcg_gen_st_i32
1094#define tcg_gen_st_f64 tcg_gen_st_i64
1095
b7bcbe95
FB		 1096static inline void gen_mov_F0_vreg(int dp, int reg)
1097{
1098 if (dp)
4373f3ce 1099 tcg_gen_ld_f64(cpu_F0d, cpu_env, vfp_reg_offset(dp, reg));
b7bcbe95 1100 else
4373f3ce 1101 tcg_gen_ld_f32(cpu_F0s, cpu_env, vfp_reg_offset(dp, reg));
b7bcbe95
FB		 1102}
1103
1104static inline void gen_mov_F1_vreg(int dp, int reg)
1105{
1106 if (dp)
4373f3ce 1107 tcg_gen_ld_f64(cpu_F1d, cpu_env, vfp_reg_offset(dp, reg));
b7bcbe95 1108 else
4373f3ce 1109 tcg_gen_ld_f32(cpu_F1s, cpu_env, vfp_reg_offset(dp, reg));
b7bcbe95
FB		 1110}
1111
1112static inline void gen_mov_vreg_F0(int dp, int reg)
1113{
1114 if (dp)
4373f3ce 1115 tcg_gen_st_f64(cpu_F0d, cpu_env, vfp_reg_offset(dp, reg));
b7bcbe95 1116 else
4373f3ce 1117 tcg_gen_st_f32(cpu_F0s, cpu_env, vfp_reg_offset(dp, reg));
b7bcbe95
FB		 1118}
1119
18c9b560
AZ		 1120#define ARM_CP_RW_BIT (1 << 20)
1121
a7812ae4 1122static inline void iwmmxt_load_reg(TCGv_i64 var, int reg)
e677137d
PB		 1123{
1124 tcg_gen_ld_i64(var, cpu_env, offsetof(CPUState, iwmmxt.regs[reg]));
1125}
1126
a7812ae4 1127static inline void iwmmxt_store_reg(TCGv_i64 var, int reg)
e677137d
PB		 1128{
1129 tcg_gen_st_i64(var, cpu_env, offsetof(CPUState, iwmmxt.regs[reg]));
1130}
1131
da6b5335 1132static inline TCGv iwmmxt_load_creg(int reg)
e677137d 1133{
7d1b0095 1134 TCGv var = tcg_temp_new_i32();
da6b5335
FN		 1135 tcg_gen_ld_i32(var, cpu_env, offsetof(CPUState, iwmmxt.cregs[reg]));
1136 return var;
e677137d
PB		 1137}
1138
da6b5335 1139static inline void iwmmxt_store_creg(int reg, TCGv var)
e677137d 1140{
da6b5335 1141 tcg_gen_st_i32(var, cpu_env, offsetof(CPUState, iwmmxt.cregs[reg]));
7d1b0095 1142 tcg_temp_free_i32(var);
e677137d
PB		 1143}
1144
1145static inline void gen_op_iwmmxt_movq_wRn_M0(int rn)
1146{
1147 iwmmxt_store_reg(cpu_M0, rn);
1148}
1149
1150static inline void gen_op_iwmmxt_movq_M0_wRn(int rn)
1151{
1152 iwmmxt_load_reg(cpu_M0, rn);
1153}
1154
1155static inline void gen_op_iwmmxt_orq_M0_wRn(int rn)
1156{
1157 iwmmxt_load_reg(cpu_V1, rn);
1158 tcg_gen_or_i64(cpu_M0, cpu_M0, cpu_V1);
1159}
1160
1161static inline void gen_op_iwmmxt_andq_M0_wRn(int rn)
1162{
1163 iwmmxt_load_reg(cpu_V1, rn);
1164 tcg_gen_and_i64(cpu_M0, cpu_M0, cpu_V1);
1165}
1166
1167static inline void gen_op_iwmmxt_xorq_M0_wRn(int rn)
1168{
1169 iwmmxt_load_reg(cpu_V1, rn);
1170 tcg_gen_xor_i64(cpu_M0, cpu_M0, cpu_V1);
1171}
1172
1173#define IWMMXT_OP(name) \
1174static inline void gen_op_iwmmxt_##name##_M0_wRn(int rn) \
1175{ \
1176 iwmmxt_load_reg(cpu_V1, rn); \
1177 gen_helper_iwmmxt_##name(cpu_M0, cpu_M0, cpu_V1); \
1178}
1179
947a2fa2
PM		 1180#define IWMMXT_OP_SIZE(name) \
1181IWMMXT_OP(name##b) \
1182IWMMXT_OP(name##w) \
1183IWMMXT_OP(name##l)
e677137d 1184
947a2fa2 1185#define IWMMXT_OP_1(name) \
e677137d
PB		 1186static inline void gen_op_iwmmxt_##name##_M0(void) \
1187{ \
947a2fa2 1188 gen_helper_iwmmxt_##name(cpu_M0, cpu_M0); \
e677137d
PB		 1189}
1190
1191IWMMXT_OP(maddsq)
1192IWMMXT_OP(madduq)
1193IWMMXT_OP(sadb)
1194IWMMXT_OP(sadw)
1195IWMMXT_OP(mulslw)
1196IWMMXT_OP(mulshw)
1197IWMMXT_OP(mululw)
1198IWMMXT_OP(muluhw)
1199IWMMXT_OP(macsw)
1200IWMMXT_OP(macuw)
1201
947a2fa2
PM		 1202IWMMXT_OP_SIZE(unpackl)
1203IWMMXT_OP_SIZE(unpackh)
1204
1205IWMMXT_OP_1(unpacklub)
1206IWMMXT_OP_1(unpackluw)
1207IWMMXT_OP_1(unpacklul)
1208IWMMXT_OP_1(unpackhub)
1209IWMMXT_OP_1(unpackhuw)
1210IWMMXT_OP_1(unpackhul)
1211IWMMXT_OP_1(unpacklsb)
1212IWMMXT_OP_1(unpacklsw)
1213IWMMXT_OP_1(unpacklsl)
1214IWMMXT_OP_1(unpackhsb)
1215IWMMXT_OP_1(unpackhsw)
1216IWMMXT_OP_1(unpackhsl)
1217
1218IWMMXT_OP_SIZE(cmpeq)
1219IWMMXT_OP_SIZE(cmpgtu)
1220IWMMXT_OP_SIZE(cmpgts)
1221
1222IWMMXT_OP_SIZE(mins)
1223IWMMXT_OP_SIZE(minu)
1224IWMMXT_OP_SIZE(maxs)
1225IWMMXT_OP_SIZE(maxu)
1226
1227IWMMXT_OP_SIZE(subn)
1228IWMMXT_OP_SIZE(addn)
1229IWMMXT_OP_SIZE(subu)
1230IWMMXT_OP_SIZE(addu)
1231IWMMXT_OP_SIZE(subs)
1232IWMMXT_OP_SIZE(adds)
1233
1234IWMMXT_OP(avgb0)
1235IWMMXT_OP(avgb1)
1236IWMMXT_OP(avgw0)
1237IWMMXT_OP(avgw1)
e677137d
PB		 1238
1239IWMMXT_OP(msadb)
1240
947a2fa2
PM		 1241IWMMXT_OP(packuw)
1242IWMMXT_OP(packul)
1243IWMMXT_OP(packuq)
1244IWMMXT_OP(packsw)
1245IWMMXT_OP(packsl)
1246IWMMXT_OP(packsq)
e677137d 1247
e677137d
PB		 1248static void gen_op_iwmmxt_set_mup(void)
1249{
1250 TCGv tmp;
1251 tmp = load_cpu_field(iwmmxt.cregs[ARM_IWMMXT_wCon]);
1252 tcg_gen_ori_i32(tmp, tmp, 2);
1253 store_cpu_field(tmp, iwmmxt.cregs[ARM_IWMMXT_wCon]);
1254}
1255
1256static void gen_op_iwmmxt_set_cup(void)
1257{
1258 TCGv tmp;
1259 tmp = load_cpu_field(iwmmxt.cregs[ARM_IWMMXT_wCon]);
1260 tcg_gen_ori_i32(tmp, tmp, 1);
1261 store_cpu_field(tmp, iwmmxt.cregs[ARM_IWMMXT_wCon]);
1262}
1263
1264static void gen_op_iwmmxt_setpsr_nz(void)
1265{
7d1b0095 1266 TCGv tmp = tcg_temp_new_i32();
e677137d
PB		 1267 gen_helper_iwmmxt_setpsr_nz(tmp, cpu_M0);
1268 store_cpu_field(tmp, iwmmxt.cregs[ARM_IWMMXT_wCASF]);
1269}
1270
1271static inline void gen_op_iwmmxt_addl_M0_wRn(int rn)
1272{
1273 iwmmxt_load_reg(cpu_V1, rn);
86831435 1274 tcg_gen_ext32u_i64(cpu_V1, cpu_V1);
e677137d
PB		 1275 tcg_gen_add_i64(cpu_M0, cpu_M0, cpu_V1);
1276}
1277
da6b5335 1278static inline int gen_iwmmxt_address(DisasContext *s, uint32_t insn, TCGv dest)
18c9b560
AZ		 1279{
1280 int rd;
1281 uint32_t offset;
da6b5335 1282 TCGv tmp;
18c9b560
AZ		 1283
1284 rd = (insn >> 16) & 0xf;
da6b5335 1285 tmp = load_reg(s, rd);
18c9b560
AZ		 1286
1287 offset = (insn & 0xff) << ((insn >> 7) & 2);
1288 if (insn & (1 << 24)) {
1289 /* Pre indexed */
1290 if (insn & (1 << 23))
da6b5335 1291 tcg_gen_addi_i32(tmp, tmp, offset);
18c9b560 1292 else
da6b5335
FN		 1293 tcg_gen_addi_i32(tmp, tmp, -offset);
1294 tcg_gen_mov_i32(dest, tmp);
18c9b560 1295 if (insn & (1 << 21))
da6b5335
FN		 1296 store_reg(s, rd, tmp);
1297 else
7d1b0095 1298 tcg_temp_free_i32(tmp);
18c9b560
AZ		 1299 } else if (insn & (1 << 21)) {
1300 /* Post indexed */
da6b5335 1301 tcg_gen_mov_i32(dest, tmp);
18c9b560 1302 if (insn & (1 << 23))
da6b5335 1303 tcg_gen_addi_i32(tmp, tmp, offset);
18c9b560 1304 else
da6b5335
FN		 1305 tcg_gen_addi_i32(tmp, tmp, -offset);
1306 store_reg(s, rd, tmp);
18c9b560
AZ		 1307 } else if (!(insn & (1 << 23)))
1308 return 1;
1309 return 0;
1310}
1311
da6b5335 1312static inline int gen_iwmmxt_shift(uint32_t insn, uint32_t mask, TCGv dest)
18c9b560
AZ		 1313{
1314 int rd = (insn >> 0) & 0xf;
da6b5335 1315 TCGv tmp;
18c9b560 1316
da6b5335
FN		 1317 if (insn & (1 << 8)) {
1318 if (rd < ARM_IWMMXT_wCGR0 || rd > ARM_IWMMXT_wCGR3) {
18c9b560 1319 return 1;
da6b5335
FN		 1320 } else {
1321 tmp = iwmmxt_load_creg(rd);
1322 }
1323 } else {
7d1b0095 1324 tmp = tcg_temp_new_i32();
da6b5335
FN		 1325 iwmmxt_load_reg(cpu_V0, rd);
1326 tcg_gen_trunc_i64_i32(tmp, cpu_V0);
1327 }
1328 tcg_gen_andi_i32(tmp, tmp, mask);
1329 tcg_gen_mov_i32(dest, tmp);
7d1b0095 1330 tcg_temp_free_i32(tmp);
18c9b560
AZ		 1331 return 0;
1332}
1333
1334/* Disassemble an iwMMXt instruction. Returns nonzero if an error occured
1335 (ie. an undefined instruction). */
1336static int disas_iwmmxt_insn(CPUState *env, DisasContext *s, uint32_t insn)
1337{
1338 int rd, wrd;
1339 int rdhi, rdlo, rd0, rd1, i;
da6b5335
FN		 1340 TCGv addr;
1341 TCGv tmp, tmp2, tmp3;
18c9b560
AZ		 1342
1343 if ((insn & 0x0e000e00) == 0x0c000000) {
1344 if ((insn & 0x0fe00ff0) == 0x0c400000) {
1345 wrd = insn & 0xf;
1346 rdlo = (insn >> 12) & 0xf;
1347 rdhi = (insn >> 16) & 0xf;
1348 if (insn & ARM_CP_RW_BIT) { /* TMRRC */
da6b5335
FN		 1349 iwmmxt_load_reg(cpu_V0, wrd);
1350 tcg_gen_trunc_i64_i32(cpu_R[rdlo], cpu_V0);
1351 tcg_gen_shri_i64(cpu_V0, cpu_V0, 32);
1352 tcg_gen_trunc_i64_i32(cpu_R[rdhi], cpu_V0);
18c9b560 1353 } else { /* TMCRR */
da6b5335
FN		 1354 tcg_gen_concat_i32_i64(cpu_V0, cpu_R[rdlo], cpu_R[rdhi]);
1355 iwmmxt_store_reg(cpu_V0, wrd);
18c9b560
AZ		 1356 gen_op_iwmmxt_set_mup();
1357 }
1358 return 0;
1359 }
1360
1361 wrd = (insn >> 12) & 0xf;
7d1b0095 1362 addr = tcg_temp_new_i32();
da6b5335 1363 if (gen_iwmmxt_address(s, insn, addr)) {
7d1b0095 1364 tcg_temp_free_i32(addr);
18c9b560 1365 return 1;
da6b5335 1366 }
18c9b560
AZ		 1367 if (insn & ARM_CP_RW_BIT) {
1368 if ((insn >> 28) == 0xf) { /* WLDRW wCx */
7d1b0095 1369 tmp = tcg_temp_new_i32();
da6b5335
FN		 1370 tcg_gen_qemu_ld32u(tmp, addr, IS_USER(s));
1371 iwmmxt_store_creg(wrd, tmp);
18c9b560 1372 } else {
e677137d
PB		 1373 i = 1;
1374 if (insn & (1 << 8)) {
1375 if (insn & (1 << 22)) { /* WLDRD */
da6b5335 1376 tcg_gen_qemu_ld64(cpu_M0, addr, IS_USER(s));
e677137d
PB		 1377 i = 0;
1378 } else { /* WLDRW wRd */
da6b5335 1379 tmp = gen_ld32(addr, IS_USER(s));
e677137d
PB		 1380 }
1381 } else {
1382 if (insn & (1 << 22)) { /* WLDRH */
da6b5335 1383 tmp = gen_ld16u(addr, IS_USER(s));
e677137d 1384 } else { /* WLDRB */
da6b5335 1385 tmp = gen_ld8u(addr, IS_USER(s));
e677137d
PB		 1386 }
1387 }
1388 if (i) {
1389 tcg_gen_extu_i32_i64(cpu_M0, tmp);
7d1b0095 1390 tcg_temp_free_i32(tmp);
e677137d 1391 }
18c9b560
AZ		 1392 gen_op_iwmmxt_movq_wRn_M0(wrd);
1393 }
1394 } else {
1395 if ((insn >> 28) == 0xf) { /* WSTRW wCx */
da6b5335
FN		 1396 tmp = iwmmxt_load_creg(wrd);
1397 gen_st32(tmp, addr, IS_USER(s));
18c9b560
AZ		 1398 } else {
1399 gen_op_iwmmxt_movq_M0_wRn(wrd);
7d1b0095 1400 tmp = tcg_temp_new_i32();
e677137d
PB		 1401 if (insn & (1 << 8)) {
1402 if (insn & (1 << 22)) { /* WSTRD */
7d1b0095 1403 tcg_temp_free_i32(tmp);
da6b5335 1404 tcg_gen_qemu_st64(cpu_M0, addr, IS_USER(s));
e677137d
PB		 1405 } else { /* WSTRW wRd */
1406 tcg_gen_trunc_i64_i32(tmp, cpu_M0);
da6b5335 1407 gen_st32(tmp, addr, IS_USER(s));
e677137d
PB		 1408 }
1409 } else {
1410 if (insn & (1 << 22)) { /* WSTRH */
1411 tcg_gen_trunc_i64_i32(tmp, cpu_M0);
da6b5335 1412 gen_st16(tmp, addr, IS_USER(s));
e677137d
PB		 1413 } else { /* WSTRB */
1414 tcg_gen_trunc_i64_i32(tmp, cpu_M0);
da6b5335 1415 gen_st8(tmp, addr, IS_USER(s));
e677137d
PB		 1416 }
1417 }
18c9b560
AZ		 1418 }
1419 }
7d1b0095 1420 tcg_temp_free_i32(addr);
18c9b560
AZ		 1421 return 0;
1422 }
1423
1424 if ((insn & 0x0f000000) != 0x0e000000)
1425 return 1;
1426
1427 switch (((insn >> 12) & 0xf00) | ((insn >> 4) & 0xff)) {
1428 case 0x000: /* WOR */
1429 wrd = (insn >> 12) & 0xf;
1430 rd0 = (insn >> 0) & 0xf;
1431 rd1 = (insn >> 16) & 0xf;
1432 gen_op_iwmmxt_movq_M0_wRn(rd0);
1433 gen_op_iwmmxt_orq_M0_wRn(rd1);
1434 gen_op_iwmmxt_setpsr_nz();
1435 gen_op_iwmmxt_movq_wRn_M0(wrd);
1436 gen_op_iwmmxt_set_mup();
1437 gen_op_iwmmxt_set_cup();
1438 break;
1439 case 0x011: /* TMCR */
1440 if (insn & 0xf)
1441 return 1;
1442 rd = (insn >> 12) & 0xf;
1443 wrd = (insn >> 16) & 0xf;
1444 switch (wrd) {
1445 case ARM_IWMMXT_wCID:
1446 case ARM_IWMMXT_wCASF:
1447 break;
1448 case ARM_IWMMXT_wCon:
1449 gen_op_iwmmxt_set_cup();
1450 /* Fall through. */
1451 case ARM_IWMMXT_wCSSF:
da6b5335
FN		 1452 tmp = iwmmxt_load_creg(wrd);
1453 tmp2 = load_reg(s, rd);
f669df27 1454 tcg_gen_andc_i32(tmp, tmp, tmp2);
7d1b0095 1455 tcg_temp_free_i32(tmp2);
da6b5335 1456 iwmmxt_store_creg(wrd, tmp);
18c9b560
AZ		 1457 break;
1458 case ARM_IWMMXT_wCGR0:
1459 case ARM_IWMMXT_wCGR1:
1460 case ARM_IWMMXT_wCGR2:
1461 case ARM_IWMMXT_wCGR3:
1462 gen_op_iwmmxt_set_cup();
da6b5335
FN		 1463 tmp = load_reg(s, rd);
1464 iwmmxt_store_creg(wrd, tmp);
18c9b560
AZ		 1465 break;
1466 default:
1467 return 1;
1468 }
1469 break;
1470 case 0x100: /* WXOR */
1471 wrd = (insn >> 12) & 0xf;
1472 rd0 = (insn >> 0) & 0xf;
1473 rd1 = (insn >> 16) & 0xf;
1474 gen_op_iwmmxt_movq_M0_wRn(rd0);
1475 gen_op_iwmmxt_xorq_M0_wRn(rd1);
1476 gen_op_iwmmxt_setpsr_nz();
1477 gen_op_iwmmxt_movq_wRn_M0(wrd);
1478 gen_op_iwmmxt_set_mup();
1479 gen_op_iwmmxt_set_cup();
1480 break;
1481 case 0x111: /* TMRC */
1482 if (insn & 0xf)
1483 return 1;
1484 rd = (insn >> 12) & 0xf;
1485 wrd = (insn >> 16) & 0xf;
da6b5335
FN		 1486 tmp = iwmmxt_load_creg(wrd);
1487 store_reg(s, rd, tmp);
18c9b560
AZ		 1488 break;
1489 case 0x300: /* WANDN */
1490 wrd = (insn >> 12) & 0xf;
1491 rd0 = (insn >> 0) & 0xf;
1492 rd1 = (insn >> 16) & 0xf;
1493 gen_op_iwmmxt_movq_M0_wRn(rd0);
e677137d 1494 tcg_gen_neg_i64(cpu_M0, cpu_M0);
18c9b560
AZ		 1495 gen_op_iwmmxt_andq_M0_wRn(rd1);
1496 gen_op_iwmmxt_setpsr_nz();
1497 gen_op_iwmmxt_movq_wRn_M0(wrd);
1498 gen_op_iwmmxt_set_mup();
1499 gen_op_iwmmxt_set_cup();
1500 break;
1501 case 0x200: /* WAND */
1502 wrd = (insn >> 12) & 0xf;
1503 rd0 = (insn >> 0) & 0xf;
1504 rd1 = (insn >> 16) & 0xf;
1505 gen_op_iwmmxt_movq_M0_wRn(rd0);
1506 gen_op_iwmmxt_andq_M0_wRn(rd1);
1507 gen_op_iwmmxt_setpsr_nz();
1508 gen_op_iwmmxt_movq_wRn_M0(wrd);
1509 gen_op_iwmmxt_set_mup();
1510 gen_op_iwmmxt_set_cup();
1511 break;
1512 case 0x810: case 0xa10: /* WMADD */
1513 wrd = (insn >> 12) & 0xf;
1514 rd0 = (insn >> 0) & 0xf;
1515 rd1 = (insn >> 16) & 0xf;
1516 gen_op_iwmmxt_movq_M0_wRn(rd0);
1517 if (insn & (1 << 21))
1518 gen_op_iwmmxt_maddsq_M0_wRn(rd1);
1519 else
1520 gen_op_iwmmxt_madduq_M0_wRn(rd1);
1521 gen_op_iwmmxt_movq_wRn_M0(wrd);
1522 gen_op_iwmmxt_set_mup();
1523 break;
1524 case 0x10e: case 0x50e: case 0x90e: case 0xd0e: /* WUNPCKIL */
1525 wrd = (insn >> 12) & 0xf;
1526 rd0 = (insn >> 16) & 0xf;
1527 rd1 = (insn >> 0) & 0xf;
1528 gen_op_iwmmxt_movq_M0_wRn(rd0);
1529 switch ((insn >> 22) & 3) {
1530 case 0:
1531 gen_op_iwmmxt_unpacklb_M0_wRn(rd1);
1532 break;
1533 case 1:
1534 gen_op_iwmmxt_unpacklw_M0_wRn(rd1);
1535 break;
1536 case 2:
1537 gen_op_iwmmxt_unpackll_M0_wRn(rd1);
1538 break;
1539 case 3:
1540 return 1;
1541 }
1542 gen_op_iwmmxt_movq_wRn_M0(wrd);
1543 gen_op_iwmmxt_set_mup();
1544 gen_op_iwmmxt_set_cup();
1545 break;
1546 case 0x10c: case 0x50c: case 0x90c: case 0xd0c: /* WUNPCKIH */
1547 wrd = (insn >> 12) & 0xf;
1548 rd0 = (insn >> 16) & 0xf;
1549 rd1 = (insn >> 0) & 0xf;
1550 gen_op_iwmmxt_movq_M0_wRn(rd0);
1551 switch ((insn >> 22) & 3) {
1552 case 0:
1553 gen_op_iwmmxt_unpackhb_M0_wRn(rd1);
1554 break;
1555 case 1:
1556 gen_op_iwmmxt_unpackhw_M0_wRn(rd1);
1557 break;
1558 case 2:
1559 gen_op_iwmmxt_unpackhl_M0_wRn(rd1);
1560 break;
1561 case 3:
1562 return 1;
1563 }
1564 gen_op_iwmmxt_movq_wRn_M0(wrd);
1565 gen_op_iwmmxt_set_mup();
1566 gen_op_iwmmxt_set_cup();
1567 break;
1568 case 0x012: case 0x112: case 0x412: case 0x512: /* WSAD */
1569 wrd = (insn >> 12) & 0xf;
1570 rd0 = (insn >> 16) & 0xf;
1571 rd1 = (insn >> 0) & 0xf;
1572 gen_op_iwmmxt_movq_M0_wRn(rd0);
1573 if (insn & (1 << 22))
1574 gen_op_iwmmxt_sadw_M0_wRn(rd1);
1575 else
1576 gen_op_iwmmxt_sadb_M0_wRn(rd1);
1577 if (!(insn & (1 << 20)))
1578 gen_op_iwmmxt_addl_M0_wRn(wrd);
1579 gen_op_iwmmxt_movq_wRn_M0(wrd);
1580 gen_op_iwmmxt_set_mup();
1581 break;
1582 case 0x010: case 0x110: case 0x210: case 0x310: /* WMUL */
1583 wrd = (insn >> 12) & 0xf;
1584 rd0 = (insn >> 16) & 0xf;
1585 rd1 = (insn >> 0) & 0xf;
1586 gen_op_iwmmxt_movq_M0_wRn(rd0);
e677137d
PB		 1587 if (insn & (1 << 21)) {
1588 if (insn & (1 << 20))
1589 gen_op_iwmmxt_mulshw_M0_wRn(rd1);
1590 else
1591 gen_op_iwmmxt_mulslw_M0_wRn(rd1);
1592 } else {
1593 if (insn & (1 << 20))
1594 gen_op_iwmmxt_muluhw_M0_wRn(rd1);
1595 else
1596 gen_op_iwmmxt_mululw_M0_wRn(rd1);
1597 }
18c9b560
AZ		 1598 gen_op_iwmmxt_movq_wRn_M0(wrd);
1599 gen_op_iwmmxt_set_mup();
1600 break;
1601 case 0x410: case 0x510: case 0x610: case 0x710: /* WMAC */
1602 wrd = (insn >> 12) & 0xf;
1603 rd0 = (insn >> 16) & 0xf;
1604 rd1 = (insn >> 0) & 0xf;
1605 gen_op_iwmmxt_movq_M0_wRn(rd0);
1606 if (insn & (1 << 21))
1607 gen_op_iwmmxt_macsw_M0_wRn(rd1);
1608 else
1609 gen_op_iwmmxt_macuw_M0_wRn(rd1);
1610 if (!(insn & (1 << 20))) {
e677137d
PB		 1611 iwmmxt_load_reg(cpu_V1, wrd);
1612 tcg_gen_add_i64(cpu_M0, cpu_M0, cpu_V1);
18c9b560
AZ		 1613 }
1614 gen_op_iwmmxt_movq_wRn_M0(wrd);
1615 gen_op_iwmmxt_set_mup();
1616 break;
1617 case 0x006: case 0x406: case 0x806: case 0xc06: /* WCMPEQ */
1618 wrd = (insn >> 12) & 0xf;
1619 rd0 = (insn >> 16) & 0xf;
1620 rd1 = (insn >> 0) & 0xf;
1621 gen_op_iwmmxt_movq_M0_wRn(rd0);
1622 switch ((insn >> 22) & 3) {
1623 case 0:
1624 gen_op_iwmmxt_cmpeqb_M0_wRn(rd1);
1625 break;
1626 case 1:
1627 gen_op_iwmmxt_cmpeqw_M0_wRn(rd1);
1628 break;
1629 case 2:
1630 gen_op_iwmmxt_cmpeql_M0_wRn(rd1);
1631 break;
1632 case 3:
1633 return 1;
1634 }
1635 gen_op_iwmmxt_movq_wRn_M0(wrd);
1636 gen_op_iwmmxt_set_mup();
1637 gen_op_iwmmxt_set_cup();
1638 break;
1639 case 0x800: case 0x900: case 0xc00: case 0xd00: /* WAVG2 */
1640 wrd = (insn >> 12) & 0xf;
1641 rd0 = (insn >> 16) & 0xf;
1642 rd1 = (insn >> 0) & 0xf;
1643 gen_op_iwmmxt_movq_M0_wRn(rd0);
e677137d
PB		 1644 if (insn & (1 << 22)) {
1645 if (insn & (1 << 20))
1646 gen_op_iwmmxt_avgw1_M0_wRn(rd1);
1647 else
1648 gen_op_iwmmxt_avgw0_M0_wRn(rd1);
1649 } else {
1650 if (insn & (1 << 20))
1651 gen_op_iwmmxt_avgb1_M0_wRn(rd1);
1652 else
1653 gen_op_iwmmxt_avgb0_M0_wRn(rd1);
1654 }
18c9b560
AZ		 1655 gen_op_iwmmxt_movq_wRn_M0(wrd);
1656 gen_op_iwmmxt_set_mup();
1657 gen_op_iwmmxt_set_cup();
1658 break;
1659 case 0x802: case 0x902: case 0xa02: case 0xb02: /* WALIGNR */
1660 wrd = (insn >> 12) & 0xf;
1661 rd0 = (insn >> 16) & 0xf;
1662 rd1 = (insn >> 0) & 0xf;
1663 gen_op_iwmmxt_movq_M0_wRn(rd0);
da6b5335
FN		 1664 tmp = iwmmxt_load_creg(ARM_IWMMXT_wCGR0 + ((insn >> 20) & 3));
1665 tcg_gen_andi_i32(tmp, tmp, 7);
1666 iwmmxt_load_reg(cpu_V1, rd1);
1667 gen_helper_iwmmxt_align(cpu_M0, cpu_M0, cpu_V1, tmp);
7d1b0095 1668 tcg_temp_free_i32(tmp);
18c9b560
AZ		 1669 gen_op_iwmmxt_movq_wRn_M0(wrd);
1670 gen_op_iwmmxt_set_mup();
1671 break;
1672 case 0x601: case 0x605: case 0x609: case 0x60d: /* TINSR */
da6b5335
FN		 1673 if (((insn >> 6) & 3) == 3)
1674 return 1;
18c9b560
AZ		 1675 rd = (insn >> 12) & 0xf;
1676 wrd = (insn >> 16) & 0xf;
da6b5335 1677 tmp = load_reg(s, rd);
18c9b560
AZ		 1678 gen_op_iwmmxt_movq_M0_wRn(wrd);
1679 switch ((insn >> 6) & 3) {
1680 case 0:
da6b5335
FN		 1681 tmp2 = tcg_const_i32(0xff);
1682 tmp3 = tcg_const_i32((insn & 7) << 3);
18c9b560
AZ		 1683 break;
1684 case 1:
da6b5335
FN		 1685 tmp2 = tcg_const_i32(0xffff);
1686 tmp3 = tcg_const_i32((insn & 3) << 4);
18c9b560
AZ		 1687 break;
1688 case 2:
da6b5335
FN		 1689 tmp2 = tcg_const_i32(0xffffffff);
1690 tmp3 = tcg_const_i32((insn & 1) << 5);
18c9b560 1691 break;
da6b5335
FN		 1692 default:
1693 TCGV_UNUSED(tmp2);
1694 TCGV_UNUSED(tmp3);
18c9b560 1695 }
da6b5335
FN		 1696 gen_helper_iwmmxt_insr(cpu_M0, cpu_M0, tmp, tmp2, tmp3);
1697 tcg_temp_free(tmp3);
1698 tcg_temp_free(tmp2);
7d1b0095 1699 tcg_temp_free_i32(tmp);
18c9b560
AZ		 1700 gen_op_iwmmxt_movq_wRn_M0(wrd);
1701 gen_op_iwmmxt_set_mup();
1702 break;
1703 case 0x107: case 0x507: case 0x907: case 0xd07: /* TEXTRM */
1704 rd = (insn >> 12) & 0xf;
1705 wrd = (insn >> 16) & 0xf;
da6b5335 1706 if (rd == 15 || ((insn >> 22) & 3) == 3)
18c9b560
AZ		 1707 return 1;
1708 gen_op_iwmmxt_movq_M0_wRn(wrd);
7d1b0095 1709 tmp = tcg_temp_new_i32();
18c9b560
AZ		 1710 switch ((insn >> 22) & 3) {
1711 case 0:
da6b5335
FN		 1712 tcg_gen_shri_i64(cpu_M0, cpu_M0, (insn & 7) << 3);
1713 tcg_gen_trunc_i64_i32(tmp, cpu_M0);
1714 if (insn & 8) {
1715 tcg_gen_ext8s_i32(tmp, tmp);
1716 } else {
1717 tcg_gen_andi_i32(tmp, tmp, 0xff);
18c9b560
AZ		 1718 }
1719 break;
1720 case 1:
da6b5335
FN		 1721 tcg_gen_shri_i64(cpu_M0, cpu_M0, (insn & 3) << 4);
1722 tcg_gen_trunc_i64_i32(tmp, cpu_M0);
1723 if (insn & 8) {
1724 tcg_gen_ext16s_i32(tmp, tmp);
1725 } else {
1726 tcg_gen_andi_i32(tmp, tmp, 0xffff);
18c9b560
AZ		 1727 }
1728 break;
1729 case 2:
da6b5335
FN		 1730 tcg_gen_shri_i64(cpu_M0, cpu_M0, (insn & 1) << 5);
1731 tcg_gen_trunc_i64_i32(tmp, cpu_M0);
18c9b560 1732 break;
18c9b560 1733 }
da6b5335 1734 store_reg(s, rd, tmp);
18c9b560
AZ		 1735 break;
1736 case 0x117: case 0x517: case 0x917: case 0xd17: /* TEXTRC */
da6b5335 1737 if ((insn & 0x000ff008) != 0x0003f000 || ((insn >> 22) & 3) == 3)
18c9b560 1738 return 1;
da6b5335 1739 tmp = iwmmxt_load_creg(ARM_IWMMXT_wCASF);
18c9b560
AZ		 1740 switch ((insn >> 22) & 3) {
1741 case 0:
da6b5335 1742 tcg_gen_shri_i32(tmp, tmp, ((insn & 7) << 2) + 0);
18c9b560
AZ		 1743 break;
1744 case 1:
da6b5335 1745 tcg_gen_shri_i32(tmp, tmp, ((insn & 3) << 3) + 4);
18c9b560
AZ		 1746 break;
1747 case 2:
da6b5335 1748 tcg_gen_shri_i32(tmp, tmp, ((insn & 1) << 4) + 12);
18c9b560 1749 break;
18c9b560 1750 }
da6b5335
FN		 1751 tcg_gen_shli_i32(tmp, tmp, 28);
1752 gen_set_nzcv(tmp);
7d1b0095 1753 tcg_temp_free_i32(tmp);
18c9b560
AZ		 1754 break;
1755 case 0x401: case 0x405: case 0x409: case 0x40d: /* TBCST */
da6b5335
FN		 1756 if (((insn >> 6) & 3) == 3)
1757 return 1;
18c9b560
AZ		 1758 rd = (insn >> 12) & 0xf;
1759 wrd = (insn >> 16) & 0xf;
da6b5335 1760 tmp = load_reg(s, rd);
18c9b560
AZ		 1761 switch ((insn >> 6) & 3) {
1762 case 0:
da6b5335 1763 gen_helper_iwmmxt_bcstb(cpu_M0, tmp);
18c9b560
AZ		 1764 break;
1765 case 1:
da6b5335 1766 gen_helper_iwmmxt_bcstw(cpu_M0, tmp);
18c9b560
AZ		 1767 break;
1768 case 2:
da6b5335 1769 gen_helper_iwmmxt_bcstl(cpu_M0, tmp);
18c9b560 1770 break;
18c9b560 1771 }
7d1b0095 1772 tcg_temp_free_i32(tmp);
18c9b560
AZ		 1773 gen_op_iwmmxt_movq_wRn_M0(wrd);
1774 gen_op_iwmmxt_set_mup();
1775 break;
1776 case 0x113: case 0x513: case 0x913: case 0xd13: /* TANDC */
da6b5335 1777 if ((insn & 0x000ff00f) != 0x0003f000 || ((insn >> 22) & 3) == 3)
18c9b560 1778 return 1;
da6b5335 1779 tmp = iwmmxt_load_creg(ARM_IWMMXT_wCASF);
7d1b0095 1780 tmp2 = tcg_temp_new_i32();
da6b5335 1781 tcg_gen_mov_i32(tmp2, tmp);
18c9b560
AZ		 1782 switch ((insn >> 22) & 3) {
1783 case 0:
1784 for (i = 0; i < 7; i ++) {
da6b5335
FN		 1785 tcg_gen_shli_i32(tmp2, tmp2, 4);
1786 tcg_gen_and_i32(tmp, tmp, tmp2);
18c9b560
AZ		 1787 }
1788 break;
1789 case 1:
1790 for (i = 0; i < 3; i ++) {
da6b5335
FN		 1791 tcg_gen_shli_i32(tmp2, tmp2, 8);
1792 tcg_gen_and_i32(tmp, tmp, tmp2);
18c9b560
AZ		 1793 }
1794 break;
1795 case 2:
da6b5335
FN		 1796 tcg_gen_shli_i32(tmp2, tmp2, 16);
1797 tcg_gen_and_i32(tmp, tmp, tmp2);
18c9b560 1798 break;
18c9b560 1799 }
da6b5335 1800 gen_set_nzcv(tmp);
7d1b0095
PM		 1801 tcg_temp_free_i32(tmp2);
1802 tcg_temp_free_i32(tmp);
18c9b560
AZ		 1803 break;
1804 case 0x01c: case 0x41c: case 0x81c: case 0xc1c: /* WACC */
1805 wrd = (insn >> 12) & 0xf;
1806 rd0 = (insn >> 16) & 0xf;
1807 gen_op_iwmmxt_movq_M0_wRn(rd0);
1808 switch ((insn >> 22) & 3) {
1809 case 0:
e677137d 1810 gen_helper_iwmmxt_addcb(cpu_M0, cpu_M0);
18c9b560
AZ		 1811 break;
1812 case 1:
e677137d 1813 gen_helper_iwmmxt_addcw(cpu_M0, cpu_M0);
18c9b560
AZ		 1814 break;
1815 case 2:
e677137d 1816 gen_helper_iwmmxt_addcl(cpu_M0, cpu_M0);
18c9b560
AZ		 1817 break;
1818 case 3:
1819 return 1;
1820 }
1821 gen_op_iwmmxt_movq_wRn_M0(wrd);
1822 gen_op_iwmmxt_set_mup();
1823 break;
1824 case 0x115: case 0x515: case 0x915: case 0xd15: /* TORC */
da6b5335 1825 if ((insn & 0x000ff00f) != 0x0003f000 || ((insn >> 22) & 3) == 3)
18c9b560 1826 return 1;
da6b5335 1827 tmp = iwmmxt_load_creg(ARM_IWMMXT_wCASF);
7d1b0095 1828 tmp2 = tcg_temp_new_i32();
da6b5335 1829 tcg_gen_mov_i32(tmp2, tmp);
18c9b560
AZ		 1830 switch ((insn >> 22) & 3) {
1831 case 0:
1832 for (i = 0; i < 7; i ++) {
da6b5335
FN		 1833 tcg_gen_shli_i32(tmp2, tmp2, 4);
1834 tcg_gen_or_i32(tmp, tmp, tmp2);
18c9b560
AZ		 1835 }
1836 break;
1837 case 1:
1838 for (i = 0; i < 3; i ++) {
da6b5335
FN		 1839 tcg_gen_shli_i32(tmp2, tmp2, 8);
1840 tcg_gen_or_i32(tmp, tmp, tmp2);
18c9b560
AZ		 1841 }
1842 break;
1843 case 2:
da6b5335
FN		 1844 tcg_gen_shli_i32(tmp2, tmp2, 16);
1845 tcg_gen_or_i32(tmp, tmp, tmp2);
18c9b560 1846 break;
18c9b560 1847 }
da6b5335 1848 gen_set_nzcv(tmp);
7d1b0095
PM		 1849 tcg_temp_free_i32(tmp2);
1850 tcg_temp_free_i32(tmp);
18c9b560
AZ		 1851 break;
1852 case 0x103: case 0x503: case 0x903: case 0xd03: /* TMOVMSK */
1853 rd = (insn >> 12) & 0xf;
1854 rd0 = (insn >> 16) & 0xf;
da6b5335 1855 if ((insn & 0xf) != 0 || ((insn >> 22) & 3) == 3)
18c9b560
AZ		 1856 return 1;
1857 gen_op_iwmmxt_movq_M0_wRn(rd0);
7d1b0095 1858 tmp = tcg_temp_new_i32();
18c9b560
AZ		 1859 switch ((insn >> 22) & 3) {
1860 case 0:
da6b5335 1861 gen_helper_iwmmxt_msbb(tmp, cpu_M0);
18c9b560
AZ		 1862 break;
1863 case 1:
da6b5335 1864 gen_helper_iwmmxt_msbw(tmp, cpu_M0);
18c9b560
AZ		 1865 break;
1866 case 2:
da6b5335 1867 gen_helper_iwmmxt_msbl(tmp, cpu_M0);
18c9b560 1868 break;
18c9b560 1869 }
da6b5335 1870 store_reg(s, rd, tmp);
18c9b560
AZ		 1871 break;
1872 case 0x106: case 0x306: case 0x506: case 0x706: /* WCMPGT */
1873 case 0x906: case 0xb06: case 0xd06: case 0xf06:
1874 wrd = (insn >> 12) & 0xf;
1875 rd0 = (insn >> 16) & 0xf;
1876 rd1 = (insn >> 0) & 0xf;
1877 gen_op_iwmmxt_movq_M0_wRn(rd0);
1878 switch ((insn >> 22) & 3) {
1879 case 0:
1880 if (insn & (1 << 21))
1881 gen_op_iwmmxt_cmpgtsb_M0_wRn(rd1);
1882 else
1883 gen_op_iwmmxt_cmpgtub_M0_wRn(rd1);
1884 break;
1885 case 1:
1886 if (insn & (1 << 21))
1887 gen_op_iwmmxt_cmpgtsw_M0_wRn(rd1);
1888 else
1889 gen_op_iwmmxt_cmpgtuw_M0_wRn(rd1);
1890 break;
1891 case 2:
1892 if (insn & (1 << 21))
1893 gen_op_iwmmxt_cmpgtsl_M0_wRn(rd1);
1894 else
1895 gen_op_iwmmxt_cmpgtul_M0_wRn(rd1);
1896 break;
1897 case 3:
1898 return 1;
1899 }
1900 gen_op_iwmmxt_movq_wRn_M0(wrd);
1901 gen_op_iwmmxt_set_mup();
1902 gen_op_iwmmxt_set_cup();
1903 break;
1904 case 0x00e: case 0x20e: case 0x40e: case 0x60e: /* WUNPCKEL */
1905 case 0x80e: case 0xa0e: case 0xc0e: case 0xe0e:
1906 wrd = (insn >> 12) & 0xf;
1907 rd0 = (insn >> 16) & 0xf;
1908 gen_op_iwmmxt_movq_M0_wRn(rd0);
1909 switch ((insn >> 22) & 3) {
1910 case 0:
1911 if (insn & (1 << 21))
1912 gen_op_iwmmxt_unpacklsb_M0();
1913 else
1914 gen_op_iwmmxt_unpacklub_M0();
1915 break;
1916 case 1:
1917 if (insn & (1 << 21))
1918 gen_op_iwmmxt_unpacklsw_M0();
1919 else
1920 gen_op_iwmmxt_unpackluw_M0();
1921 break;
1922 case 2:
1923 if (insn & (1 << 21))
1924 gen_op_iwmmxt_unpacklsl_M0();
1925 else
1926 gen_op_iwmmxt_unpacklul_M0();
1927 break;
1928 case 3:
1929 return 1;
1930 }
1931 gen_op_iwmmxt_movq_wRn_M0(wrd);
1932 gen_op_iwmmxt_set_mup();
1933 gen_op_iwmmxt_set_cup();
1934 break;
1935 case 0x00c: case 0x20c: case 0x40c: case 0x60c: /* WUNPCKEH */
1936 case 0x80c: case 0xa0c: case 0xc0c: case 0xe0c:
1937 wrd = (insn >> 12) & 0xf;
1938 rd0 = (insn >> 16) & 0xf;
1939 gen_op_iwmmxt_movq_M0_wRn(rd0);
1940 switch ((insn >> 22) & 3) {
1941 case 0:
1942 if (insn & (1 << 21))
1943 gen_op_iwmmxt_unpackhsb_M0();
1944 else
1945 gen_op_iwmmxt_unpackhub_M0();
1946 break;
1947 case 1:
1948 if (insn & (1 << 21))
1949 gen_op_iwmmxt_unpackhsw_M0();
1950 else
1951 gen_op_iwmmxt_unpackhuw_M0();
1952 break;
1953 case 2:
1954 if (insn & (1 << 21))
1955 gen_op_iwmmxt_unpackhsl_M0();
1956 else
1957 gen_op_iwmmxt_unpackhul_M0();
1958 break;
1959 case 3:
1960 return 1;
1961 }
1962 gen_op_iwmmxt_movq_wRn_M0(wrd);
1963 gen_op_iwmmxt_set_mup();
1964 gen_op_iwmmxt_set_cup();
1965 break;
1966 case 0x204: case 0x604: case 0xa04: case 0xe04: /* WSRL */
1967 case 0x214: case 0x614: case 0xa14: case 0xe14:
da6b5335
FN		 1968 if (((insn >> 22) & 3) == 0)
1969 return 1;
18c9b560
AZ		 1970 wrd = (insn >> 12) & 0xf;
1971 rd0 = (insn >> 16) & 0xf;
1972 gen_op_iwmmxt_movq_M0_wRn(rd0);
7d1b0095 1973 tmp = tcg_temp_new_i32();
da6b5335 1974 if (gen_iwmmxt_shift(insn, 0xff, tmp)) {
7d1b0095 1975 tcg_temp_free_i32(tmp);
18c9b560 1976 return 1;
da6b5335 1977 }
18c9b560 1978 switch ((insn >> 22) & 3) {
18c9b560 1979 case 1:
947a2fa2 1980 gen_helper_iwmmxt_srlw(cpu_M0, cpu_M0, tmp);
18c9b560
AZ		 1981 break;
1982 case 2:
947a2fa2 1983 gen_helper_iwmmxt_srll(cpu_M0, cpu_M0, tmp);
18c9b560
AZ		 1984 break;
1985 case 3:
947a2fa2 1986 gen_helper_iwmmxt_srlq(cpu_M0, cpu_M0, tmp);
18c9b560
AZ		 1987 break;
1988 }
7d1b0095 1989 tcg_temp_free_i32(tmp);
18c9b560
AZ		 1990 gen_op_iwmmxt_movq_wRn_M0(wrd);
1991 gen_op_iwmmxt_set_mup();
1992 gen_op_iwmmxt_set_cup();
1993 break;
1994 case 0x004: case 0x404: case 0x804: case 0xc04: /* WSRA */
1995 case 0x014: case 0x414: case 0x814: case 0xc14:
da6b5335
FN		 1996 if (((insn >> 22) & 3) == 0)
1997 return 1;
18c9b560
AZ		 1998 wrd = (insn >> 12) & 0xf;
1999 rd0 = (insn >> 16) & 0xf;
2000 gen_op_iwmmxt_movq_M0_wRn(rd0);
7d1b0095 2001 tmp = tcg_temp_new_i32();
da6b5335 2002 if (gen_iwmmxt_shift(insn, 0xff, tmp)) {
7d1b0095 2003 tcg_temp_free_i32(tmp);
18c9b560 2004 return 1;
da6b5335 2005 }
18c9b560 2006 switch ((insn >> 22) & 3) {
18c9b560 2007 case 1:
947a2fa2 2008 gen_helper_iwmmxt_sraw(cpu_M0, cpu_M0, tmp);
18c9b560
AZ		 2009 break;
2010 case 2:
947a2fa2 2011 gen_helper_iwmmxt_sral(cpu_M0, cpu_M0, tmp);
18c9b560
AZ		 2012 break;
2013 case 3:
947a2fa2 2014 gen_helper_iwmmxt_sraq(cpu_M0, cpu_M0, tmp);
18c9b560
AZ		 2015 break;
2016 }
7d1b0095 2017 tcg_temp_free_i32(tmp);
18c9b560
AZ		 2018 gen_op_iwmmxt_movq_wRn_M0(wrd);
2019 gen_op_iwmmxt_set_mup();
2020 gen_op_iwmmxt_set_cup();
2021 break;
2022 case 0x104: case 0x504: case 0x904: case 0xd04: /* WSLL */
2023 case 0x114: case 0x514: case 0x914: case 0xd14:
da6b5335
FN		 2024 if (((insn >> 22) & 3) == 0)
2025 return 1;
18c9b560
AZ		 2026 wrd = (insn >> 12) & 0xf;
2027 rd0 = (insn >> 16) & 0xf;
2028 gen_op_iwmmxt_movq_M0_wRn(rd0);
7d1b0095 2029 tmp = tcg_temp_new_i32();
da6b5335 2030 if (gen_iwmmxt_shift(insn, 0xff, tmp)) {
7d1b0095 2031 tcg_temp_free_i32(tmp);
18c9b560 2032 return 1;
da6b5335 2033 }
18c9b560 2034 switch ((insn >> 22) & 3) {
18c9b560 2035 case 1:
947a2fa2 2036 gen_helper_iwmmxt_sllw(cpu_M0, cpu_M0, tmp);
18c9b560
AZ		 2037 break;
2038 case 2:
947a2fa2 2039 gen_helper_iwmmxt_slll(cpu_M0, cpu_M0, tmp);
18c9b560
AZ		 2040 break;
2041 case 3:
947a2fa2 2042 gen_helper_iwmmxt_sllq(cpu_M0, cpu_M0, tmp);
18c9b560
AZ		 2043 break;
2044 }
7d1b0095 2045 tcg_temp_free_i32(tmp);
18c9b560
AZ		 2046 gen_op_iwmmxt_movq_wRn_M0(wrd);
2047 gen_op_iwmmxt_set_mup();
2048 gen_op_iwmmxt_set_cup();
2049 break;
2050 case 0x304: case 0x704: case 0xb04: case 0xf04: /* WROR */
2051 case 0x314: case 0x714: case 0xb14: case 0xf14:
da6b5335
FN		 2052 if (((insn >> 22) & 3) == 0)
2053 return 1;
18c9b560
AZ		 2054 wrd = (insn >> 12) & 0xf;
2055 rd0 = (insn >> 16) & 0xf;
2056 gen_op_iwmmxt_movq_M0_wRn(rd0);
7d1b0095 2057 tmp = tcg_temp_new_i32();
18c9b560 2058 switch ((insn >> 22) & 3) {
18c9b560 2059 case 1:
da6b5335 2060 if (gen_iwmmxt_shift(insn, 0xf, tmp)) {
7d1b0095 2061 tcg_temp_free_i32(tmp);
18c9b560 2062 return 1;
da6b5335 2063 }
947a2fa2 2064 gen_helper_iwmmxt_rorw(cpu_M0, cpu_M0, tmp);
18c9b560
AZ		 2065 break;
2066 case 2:
da6b5335 2067 if (gen_iwmmxt_shift(insn, 0x1f, tmp)) {
7d1b0095 2068 tcg_temp_free_i32(tmp);
18c9b560 2069 return 1;
da6b5335 2070 }
947a2fa2 2071 gen_helper_iwmmxt_rorl(cpu_M0, cpu_M0, tmp);
18c9b560
AZ		 2072 break;
2073 case 3:
da6b5335 2074 if (gen_iwmmxt_shift(insn, 0x3f, tmp)) {
7d1b0095 2075 tcg_temp_free_i32(tmp);
18c9b560 2076 return 1;
da6b5335 2077 }
947a2fa2 2078 gen_helper_iwmmxt_rorq(cpu_M0, cpu_M0, tmp);
18c9b560
AZ		 2079 break;
2080 }
7d1b0095 2081 tcg_temp_free_i32(tmp);
18c9b560
AZ		 2082 gen_op_iwmmxt_movq_wRn_M0(wrd);
2083 gen_op_iwmmxt_set_mup();
2084 gen_op_iwmmxt_set_cup();
2085 break;
2086 case 0x116: case 0x316: case 0x516: case 0x716: /* WMIN */
2087 case 0x916: case 0xb16: case 0xd16: case 0xf16:
2088 wrd = (insn >> 12) & 0xf;
2089 rd0 = (insn >> 16) & 0xf;
2090 rd1 = (insn >> 0) & 0xf;
2091 gen_op_iwmmxt_movq_M0_wRn(rd0);
2092 switch ((insn >> 22) & 3) {
2093 case 0:
2094 if (insn & (1 << 21))
2095 gen_op_iwmmxt_minsb_M0_wRn(rd1);
2096 else
2097 gen_op_iwmmxt_minub_M0_wRn(rd1);
2098 break;
2099 case 1:
2100 if (insn & (1 << 21))
2101 gen_op_iwmmxt_minsw_M0_wRn(rd1);
2102 else
2103 gen_op_iwmmxt_minuw_M0_wRn(rd1);
2104 break;
2105 case 2:
2106 if (insn & (1 << 21))
2107 gen_op_iwmmxt_minsl_M0_wRn(rd1);
2108 else
2109 gen_op_iwmmxt_minul_M0_wRn(rd1);
2110 break;
2111 case 3:
2112 return 1;
2113 }
2114 gen_op_iwmmxt_movq_wRn_M0(wrd);
2115 gen_op_iwmmxt_set_mup();
2116 break;
2117 case 0x016: case 0x216: case 0x416: case 0x616: /* WMAX */
2118 case 0x816: case 0xa16: case 0xc16: case 0xe16:
2119 wrd = (insn >> 12) & 0xf;
2120 rd0 = (insn >> 16) & 0xf;
2121 rd1 = (insn >> 0) & 0xf;
2122 gen_op_iwmmxt_movq_M0_wRn(rd0);
2123 switch ((insn >> 22) & 3) {
2124 case 0:
2125 if (insn & (1 << 21))
2126 gen_op_iwmmxt_maxsb_M0_wRn(rd1);
2127 else
2128 gen_op_iwmmxt_maxub_M0_wRn(rd1);
2129 break;
2130 case 1:
2131 if (insn & (1 << 21))
2132 gen_op_iwmmxt_maxsw_M0_wRn(rd1);
2133 else
2134 gen_op_iwmmxt_maxuw_M0_wRn(rd1);
2135 break;
2136 case 2:
2137 if (insn & (1 << 21))
2138 gen_op_iwmmxt_maxsl_M0_wRn(rd1);
2139 else
2140 gen_op_iwmmxt_maxul_M0_wRn(rd1);
2141 break;
2142 case 3:
2143 return 1;
2144 }
2145 gen_op_iwmmxt_movq_wRn_M0(wrd);
2146 gen_op_iwmmxt_set_mup();
2147 break;
2148 case 0x002: case 0x102: case 0x202: case 0x302: /* WALIGNI */
2149 case 0x402: case 0x502: case 0x602: case 0x702:
2150 wrd = (insn >> 12) & 0xf;
2151 rd0 = (insn >> 16) & 0xf;
2152 rd1 = (insn >> 0) & 0xf;
2153 gen_op_iwmmxt_movq_M0_wRn(rd0);
da6b5335
FN		 2154 tmp = tcg_const_i32((insn >> 20) & 3);
2155 iwmmxt_load_reg(cpu_V1, rd1);
2156 gen_helper_iwmmxt_align(cpu_M0, cpu_M0, cpu_V1, tmp);
2157 tcg_temp_free(tmp);
18c9b560
AZ		 2158 gen_op_iwmmxt_movq_wRn_M0(wrd);
2159 gen_op_iwmmxt_set_mup();
2160 break;
2161 case 0x01a: case 0x11a: case 0x21a: case 0x31a: /* WSUB */
2162 case 0x41a: case 0x51a: case 0x61a: case 0x71a:
2163 case 0x81a: case 0x91a: case 0xa1a: case 0xb1a:
2164 case 0xc1a: case 0xd1a: case 0xe1a: case 0xf1a:
2165 wrd = (insn >> 12) & 0xf;
2166 rd0 = (insn >> 16) & 0xf;
2167 rd1 = (insn >> 0) & 0xf;
2168 gen_op_iwmmxt_movq_M0_wRn(rd0);
2169 switch ((insn >> 20) & 0xf) {
2170 case 0x0:
2171 gen_op_iwmmxt_subnb_M0_wRn(rd1);
2172 break;
2173 case 0x1:
2174 gen_op_iwmmxt_subub_M0_wRn(rd1);
2175 break;
2176 case 0x3:
2177 gen_op_iwmmxt_subsb_M0_wRn(rd1);
2178 break;
2179 case 0x4:
2180 gen_op_iwmmxt_subnw_M0_wRn(rd1);
2181 break;
2182 case 0x5:
2183 gen_op_iwmmxt_subuw_M0_wRn(rd1);
2184 break;
2185 case 0x7:
2186 gen_op_iwmmxt_subsw_M0_wRn(rd1);
2187 break;
2188 case 0x8:
2189 gen_op_iwmmxt_subnl_M0_wRn(rd1);
2190 break;
2191 case 0x9:
2192 gen_op_iwmmxt_subul_M0_wRn(rd1);
2193 break;
2194 case 0xb:
2195 gen_op_iwmmxt_subsl_M0_wRn(rd1);
2196 break;
2197 default:
2198 return 1;
2199 }
2200 gen_op_iwmmxt_movq_wRn_M0(wrd);
2201 gen_op_iwmmxt_set_mup();
2202 gen_op_iwmmxt_set_cup();
2203 break;
2204 case 0x01e: case 0x11e: case 0x21e: case 0x31e: /* WSHUFH */
2205 case 0x41e: case 0x51e: case 0x61e: case 0x71e:
2206 case 0x81e: case 0x91e: case 0xa1e: case 0xb1e:
2207 case 0xc1e: case 0xd1e: case 0xe1e: case 0xf1e:
2208 wrd = (insn >> 12) & 0xf;
2209 rd0 = (insn >> 16) & 0xf;
2210 gen_op_iwmmxt_movq_M0_wRn(rd0);
da6b5335 2211 tmp = tcg_const_i32(((insn >> 16) & 0xf0) | (insn & 0x0f));
947a2fa2 2212 gen_helper_iwmmxt_shufh(cpu_M0, cpu_M0, tmp);
da6b5335 2213 tcg_temp_free(tmp);
18c9b560
AZ		 2214 gen_op_iwmmxt_movq_wRn_M0(wrd);
2215 gen_op_iwmmxt_set_mup();
2216 gen_op_iwmmxt_set_cup();
2217 break;
2218 case 0x018: case 0x118: case 0x218: case 0x318: /* WADD */
2219 case 0x418: case 0x518: case 0x618: case 0x718:
2220 case 0x818: case 0x918: case 0xa18: case 0xb18:
2221 case 0xc18: case 0xd18: case 0xe18: case 0xf18:
2222 wrd = (insn >> 12) & 0xf;
2223 rd0 = (insn >> 16) & 0xf;
2224 rd1 = (insn >> 0) & 0xf;
2225 gen_op_iwmmxt_movq_M0_wRn(rd0);
2226 switch ((insn >> 20) & 0xf) {
2227 case 0x0:
2228 gen_op_iwmmxt_addnb_M0_wRn(rd1);
2229 break;
2230 case 0x1:
2231 gen_op_iwmmxt_addub_M0_wRn(rd1);
2232 break;
2233 case 0x3:
2234 gen_op_iwmmxt_addsb_M0_wRn(rd1);
2235 break;
2236 case 0x4:
2237 gen_op_iwmmxt_addnw_M0_wRn(rd1);
2238 break;
2239 case 0x5:
2240 gen_op_iwmmxt_adduw_M0_wRn(rd1);
2241 break;
2242 case 0x7:
2243 gen_op_iwmmxt_addsw_M0_wRn(rd1);
2244 break;
2245 case 0x8:
2246 gen_op_iwmmxt_addnl_M0_wRn(rd1);
2247 break;
2248 case 0x9:
2249 gen_op_iwmmxt_addul_M0_wRn(rd1);
2250 break;
2251 case 0xb:
2252 gen_op_iwmmxt_addsl_M0_wRn(rd1);
2253 break;
2254 default:
2255 return 1;
2256 }
2257 gen_op_iwmmxt_movq_wRn_M0(wrd);
2258 gen_op_iwmmxt_set_mup();
2259 gen_op_iwmmxt_set_cup();
2260 break;
2261 case 0x008: case 0x108: case 0x208: case 0x308: /* WPACK */
2262 case 0x408: case 0x508: case 0x608: case 0x708:
2263 case 0x808: case 0x908: case 0xa08: case 0xb08:
2264 case 0xc08: case 0xd08: case 0xe08: case 0xf08:
da6b5335
FN		 2265 if (!(insn & (1 << 20)) || ((insn >> 22) & 3) == 0)
2266 return 1;
18c9b560
AZ		 2267 wrd = (insn >> 12) & 0xf;
2268 rd0 = (insn >> 16) & 0xf;
2269 rd1 = (insn >> 0) & 0xf;
2270 gen_op_iwmmxt_movq_M0_wRn(rd0);
18c9b560 2271 switch ((insn >> 22) & 3) {
18c9b560
AZ		 2272 case 1:
2273 if (insn & (1 << 21))
2274 gen_op_iwmmxt_packsw_M0_wRn(rd1);
2275 else
2276 gen_op_iwmmxt_packuw_M0_wRn(rd1);
2277 break;
2278 case 2:
2279 if (insn & (1 << 21))
2280 gen_op_iwmmxt_packsl_M0_wRn(rd1);
2281 else
2282 gen_op_iwmmxt_packul_M0_wRn(rd1);
2283 break;
2284 case 3:
2285 if (insn & (1 << 21))
2286 gen_op_iwmmxt_packsq_M0_wRn(rd1);
2287 else
2288 gen_op_iwmmxt_packuq_M0_wRn(rd1);
2289 break;
2290 }
2291 gen_op_iwmmxt_movq_wRn_M0(wrd);
2292 gen_op_iwmmxt_set_mup();
2293 gen_op_iwmmxt_set_cup();
2294 break;
2295 case 0x201: case 0x203: case 0x205: case 0x207:
2296 case 0x209: case 0x20b: case 0x20d: case 0x20f:
2297 case 0x211: case 0x213: case 0x215: case 0x217:
2298 case 0x219: case 0x21b: case 0x21d: case 0x21f:
2299 wrd = (insn >> 5) & 0xf;
2300 rd0 = (insn >> 12) & 0xf;
2301 rd1 = (insn >> 0) & 0xf;
2302 if (rd0 == 0xf || rd1 == 0xf)
2303 return 1;
2304 gen_op_iwmmxt_movq_M0_wRn(wrd);
da6b5335
FN		 2305 tmp = load_reg(s, rd0);
2306 tmp2 = load_reg(s, rd1);
18c9b560
AZ		 2307 switch ((insn >> 16) & 0xf) {
2308 case 0x0: /* TMIA */
da6b5335 2309 gen_helper_iwmmxt_muladdsl(cpu_M0, cpu_M0, tmp, tmp2);
18c9b560
AZ		 2310 break;
2311 case 0x8: /* TMIAPH */
da6b5335 2312 gen_helper_iwmmxt_muladdsw(cpu_M0, cpu_M0, tmp, tmp2);
18c9b560
AZ		 2313 break;
2314 case 0xc: case 0xd: case 0xe: case 0xf: /* TMIAxy */
18c9b560 2315 if (insn & (1 << 16))
da6b5335 2316 tcg_gen_shri_i32(tmp, tmp, 16);
18c9b560 2317 if (insn & (1 << 17))
da6b5335
FN		 2318 tcg_gen_shri_i32(tmp2, tmp2, 16);
2319 gen_helper_iwmmxt_muladdswl(cpu_M0, cpu_M0, tmp, tmp2);
18c9b560
AZ		 2320 break;
2321 default:
7d1b0095
PM		 2322 tcg_temp_free_i32(tmp2);
2323 tcg_temp_free_i32(tmp);
18c9b560
AZ		 2324 return 1;
2325 }
7d1b0095
PM		 2326 tcg_temp_free_i32(tmp2);
2327 tcg_temp_free_i32(tmp);
18c9b560
AZ		 2328 gen_op_iwmmxt_movq_wRn_M0(wrd);
2329 gen_op_iwmmxt_set_mup();
2330 break;
2331 default:
2332 return 1;
2333 }
2334
2335 return 0;
2336}
2337
2338/* Disassemble an XScale DSP instruction. Returns nonzero if an error occured
2339 (ie. an undefined instruction). */
2340static int disas_dsp_insn(CPUState *env, DisasContext *s, uint32_t insn)
2341{
2342 int acc, rd0, rd1, rdhi, rdlo;
3a554c0f 2343 TCGv tmp, tmp2;
18c9b560
AZ		 2344
2345 if ((insn & 0x0ff00f10) == 0x0e200010) {
2346 /* Multiply with Internal Accumulate Format */
2347 rd0 = (insn >> 12) & 0xf;
2348 rd1 = insn & 0xf;
2349 acc = (insn >> 5) & 7;
2350
2351 if (acc != 0)
2352 return 1;
2353
3a554c0f
FN		 2354 tmp = load_reg(s, rd0);
2355 tmp2 = load_reg(s, rd1);
18c9b560
AZ		 2356 switch ((insn >> 16) & 0xf) {
2357 case 0x0: /* MIA */
3a554c0f 2358 gen_helper_iwmmxt_muladdsl(cpu_M0, cpu_M0, tmp, tmp2);
18c9b560
AZ		 2359 break;
2360 case 0x8: /* MIAPH */
3a554c0f 2361 gen_helper_iwmmxt_muladdsw(cpu_M0, cpu_M0, tmp, tmp2);
18c9b560
AZ		 2362 break;
2363 case 0xc: /* MIABB */
2364 case 0xd: /* MIABT */
2365 case 0xe: /* MIATB */
2366 case 0xf: /* MIATT */
18c9b560 2367 if (insn & (1 << 16))
3a554c0f 2368 tcg_gen_shri_i32(tmp, tmp, 16);
18c9b560 2369 if (insn & (1 << 17))
3a554c0f
FN		 2370 tcg_gen_shri_i32(tmp2, tmp2, 16);
2371 gen_helper_iwmmxt_muladdswl(cpu_M0, cpu_M0, tmp, tmp2);
18c9b560
AZ		 2372 break;
2373 default:
2374 return 1;
2375 }
7d1b0095
PM		 2376 tcg_temp_free_i32(tmp2);
2377 tcg_temp_free_i32(tmp);
18c9b560
AZ		 2378
2379 gen_op_iwmmxt_movq_wRn_M0(acc);
2380 return 0;
2381 }
2382
2383 if ((insn & 0x0fe00ff8) == 0x0c400000) {
2384 /* Internal Accumulator Access Format */
2385 rdhi = (insn >> 16) & 0xf;
2386 rdlo = (insn >> 12) & 0xf;
2387 acc = insn & 7;
2388
2389 if (acc != 0)
2390 return 1;
2391
2392 if (insn & ARM_CP_RW_BIT) { /* MRA */
3a554c0f
FN		 2393 iwmmxt_load_reg(cpu_V0, acc);
2394 tcg_gen_trunc_i64_i32(cpu_R[rdlo], cpu_V0);
2395 tcg_gen_shri_i64(cpu_V0, cpu_V0, 32);
2396 tcg_gen_trunc_i64_i32(cpu_R[rdhi], cpu_V0);
2397 tcg_gen_andi_i32(cpu_R[rdhi], cpu_R[rdhi], (1 << (40 - 32)) - 1);
18c9b560 2398 } else { /* MAR */
3a554c0f
FN		 2399 tcg_gen_concat_i32_i64(cpu_V0, cpu_R[rdlo], cpu_R[rdhi]);
2400 iwmmxt_store_reg(cpu_V0, acc);
18c9b560
AZ		 2401 }
2402 return 0;
2403 }
2404
2405 return 1;
2406}
2407
c1713132
AZ		 2408/* Disassemble system coprocessor instruction. Return nonzero if
2409 instruction is not defined. */
2410static int disas_cp_insn(CPUState *env, DisasContext *s, uint32_t insn)
2411{
b75263d6 2412 TCGv tmp, tmp2;
c1713132
AZ		 2413 uint32_t rd = (insn >> 12) & 0xf;
2414 uint32_t cp = (insn >> 8) & 0xf;
2415 if (IS_USER(s)) {
2416 return 1;
2417 }
2418
18c9b560 2419 if (insn & ARM_CP_RW_BIT) {
c1713132
AZ		 2420 if (!env->cp[cp].cp_read)
2421 return 1;
8984bd2e 2422 gen_set_pc_im(s->pc);
7d1b0095 2423 tmp = tcg_temp_new_i32();
b75263d6
JR		 2424 tmp2 = tcg_const_i32(insn);
2425 gen_helper_get_cp(tmp, cpu_env, tmp2);
2426 tcg_temp_free(tmp2);
8984bd2e 2427 store_reg(s, rd, tmp);
c1713132
AZ		 2428 } else {
2429 if (!env->cp[cp].cp_write)
2430 return 1;
8984bd2e
PB		 2431 gen_set_pc_im(s->pc);
2432 tmp = load_reg(s, rd);
b75263d6
JR		 2433 tmp2 = tcg_const_i32(insn);
2434 gen_helper_set_cp(cpu_env, tmp2, tmp);
2435 tcg_temp_free(tmp2);
7d1b0095 2436 tcg_temp_free_i32(tmp);
c1713132
AZ		 2437 }
2438 return 0;
2439}
2440
9ee6e8bb
PB		 2441static int cp15_user_ok(uint32_t insn)
2442{
2443 int cpn = (insn >> 16) & 0xf;
2444 int cpm = insn & 0xf;
2445 int op = ((insn >> 5) & 7) | ((insn >> 18) & 0x38);
2446
2447 if (cpn == 13 && cpm == 0) {
2448 /* TLS register. */
2449 if (op == 2 || (op == 3 && (insn & ARM_CP_RW_BIT)))
2450 return 1;
2451 }
2452 if (cpn == 7) {
2453 /* ISB, DSB, DMB. */
2454 if ((cpm == 5 && op == 4)
2455 || (cpm == 10 && (op == 4 || op == 5)))
2456 return 1;
2457 }
2458 return 0;
2459}
2460
3f26c122
RV		 2461static int cp15_tls_load_store(CPUState *env, DisasContext *s, uint32_t insn, uint32_t rd)
2462{
2463 TCGv tmp;
2464 int cpn = (insn >> 16) & 0xf;
2465 int cpm = insn & 0xf;
2466 int op = ((insn >> 5) & 7) | ((insn >> 18) & 0x38);
2467
2468 if (!arm_feature(env, ARM_FEATURE_V6K))
2469 return 0;
2470
2471 if (!(cpn == 13 && cpm == 0))
2472 return 0;
2473
2474 if (insn & ARM_CP_RW_BIT) {
3f26c122
RV		 2475 switch (op) {
2476 case 2:
c5883be2 2477 tmp = load_cpu_field(cp15.c13_tls1);
3f26c122
RV		 2478 break;
2479 case 3:
c5883be2 2480 tmp = load_cpu_field(cp15.c13_tls2);
3f26c122
RV		 2481 break;
2482 case 4:
c5883be2 2483 tmp = load_cpu_field(cp15.c13_tls3);
3f26c122
RV		 2484 break;
2485 default:
3f26c122
RV		 2486 return 0;
2487 }
2488 store_reg(s, rd, tmp);
2489
2490 } else {
2491 tmp = load_reg(s, rd);
2492 switch (op) {
2493 case 2:
c5883be2 2494 store_cpu_field(tmp, cp15.c13_tls1);
3f26c122
RV		 2495 break;
2496 case 3:
c5883be2 2497 store_cpu_field(tmp, cp15.c13_tls2);
3f26c122
RV		 2498 break;
2499 case 4:
c5883be2 2500 store_cpu_field(tmp, cp15.c13_tls3);
3f26c122
RV		 2501 break;
2502 default:
7d1b0095 2503 tcg_temp_free_i32(tmp);
3f26c122
RV		 2504 return 0;
2505 }
3f26c122
RV		 2506 }
2507 return 1;
2508}
2509
b5ff1b31
FB		 2510/* Disassemble system coprocessor (cp15) instruction. Return nonzero if
2511 instruction is not defined. */
a90b7318 2512static int disas_cp15_insn(CPUState *env, DisasContext *s, uint32_t insn)
b5ff1b31
FB		 2513{
2514 uint32_t rd;
b75263d6 2515 TCGv tmp, tmp2;
b5ff1b31 2516
9ee6e8bb
PB		 2517 /* M profile cores use memory mapped registers instead of cp15. */
2518 if (arm_feature(env, ARM_FEATURE_M))
2519 return 1;
2520
2521 if ((insn & (1 << 25)) == 0) {
2522 if (insn & (1 << 20)) {
2523 /* mrrc */
2524 return 1;
2525 }
2526 /* mcrr. Used for block cache operations, so implement as no-op. */
2527 return 0;
2528 }
2529 if ((insn & (1 << 4)) == 0) {
2530 /* cdp */
2531 return 1;
2532 }
2533 if (IS_USER(s) && !cp15_user_ok(insn)) {
b5ff1b31
FB		 2534 return 1;
2535 }
cc688901
PM		 2536
2537 /* Pre-v7 versions of the architecture implemented WFI via coprocessor
2538 * instructions rather than a separate instruction.
2539 */
2540 if ((insn & 0x0fff0fff) == 0x0e070f90) {
2541 /* 0,c7,c0,4: Standard v6 WFI (also used in some pre-v6 cores).
2542 * In v7, this must NOP.
2543 */
2544 if (!arm_feature(env, ARM_FEATURE_V7)) {
2545 /* Wait for interrupt. */
2546 gen_set_pc_im(s->pc);
2547 s->is_jmp = DISAS_WFI;
2548 }
9332f9da
FB		 2549 return 0;
2550 }
cc688901
PM		 2551
2552 if ((insn & 0x0fff0fff) == 0x0e070f58) {
2553 /* 0,c7,c8,2: Not all pre-v6 cores implemented this WFI,
2554 * so this is slightly over-broad.
2555 */
2556 if (!arm_feature(env, ARM_FEATURE_V6)) {
2557 /* Wait for interrupt. */
2558 gen_set_pc_im(s->pc);
2559 s->is_jmp = DISAS_WFI;
2560 return 0;
2561 }
2562 /* Otherwise fall through to handle via helper function.
2563 * In particular, on v7 and some v6 cores this is one of
2564 * the VA-PA registers.
2565 */
2566 }
2567
b5ff1b31 2568 rd = (insn >> 12) & 0xf;
3f26c122
RV		 2569
2570 if (cp15_tls_load_store(env, s, insn, rd))
2571 return 0;
2572
b75263d6 2573 tmp2 = tcg_const_i32(insn);
18c9b560 2574 if (insn & ARM_CP_RW_BIT) {
7d1b0095 2575 tmp = tcg_temp_new_i32();
b75263d6 2576 gen_helper_get_cp15(tmp, cpu_env, tmp2);
b5ff1b31
FB		 2577 /* If the destination register is r15 then sets condition codes. */
2578 if (rd != 15)
8984bd2e
PB		 2579 store_reg(s, rd, tmp);
2580 else
7d1b0095 2581 tcg_temp_free_i32(tmp);
b5ff1b31 2582 } else {
8984bd2e 2583 tmp = load_reg(s, rd);
b75263d6 2584 gen_helper_set_cp15(cpu_env, tmp2, tmp);
7d1b0095 2585 tcg_temp_free_i32(tmp);
a90b7318
AZ		 2586 /* Normally we would always end the TB here, but Linux
2587 * arch/arm/mach-pxa/sleep.S expects two instructions following
2588 * an MMU enable to execute from cache. Imitate this behaviour. */
2589 if (!arm_feature(env, ARM_FEATURE_XSCALE) ||
2590 (insn & 0x0fff0fff) != 0x0e010f10)
2591 gen_lookup_tb(s);
b5ff1b31 2592 }
b75263d6 2593 tcg_temp_free_i32(tmp2);
b5ff1b31
FB		 2594 return 0;
2595}
2596
9ee6e8bb
PB		 2597#define VFP_REG_SHR(x, n) (((n) > 0) ? (x) >> (n) : (x) << -(n))
2598#define VFP_SREG(insn, bigbit, smallbit) \
2599 ((VFP_REG_SHR(insn, bigbit - 1) & 0x1e) | (((insn) >> (smallbit)) & 1))
2600#define VFP_DREG(reg, insn, bigbit, smallbit) do { \
2601 if (arm_feature(env, ARM_FEATURE_VFP3)) { \
2602 reg = (((insn) >> (bigbit)) & 0x0f) \
2603 | (((insn) >> ((smallbit) - 4)) & 0x10); \
2604 } else { \
2605 if (insn & (1 << (smallbit))) \
2606 return 1; \
2607 reg = ((insn) >> (bigbit)) & 0x0f; \
2608 }} while (0)
2609
2610#define VFP_SREG_D(insn) VFP_SREG(insn, 12, 22)
2611#define VFP_DREG_D(reg, insn) VFP_DREG(reg, insn, 12, 22)
2612#define VFP_SREG_N(insn) VFP_SREG(insn, 16, 7)
2613#define VFP_DREG_N(reg, insn) VFP_DREG(reg, insn, 16, 7)
2614#define VFP_SREG_M(insn) VFP_SREG(insn, 0, 5)
2615#define VFP_DREG_M(reg, insn) VFP_DREG(reg, insn, 0, 5)
2616
4373f3ce
PB		 2617/* Move between integer and VFP cores. */
2618static TCGv gen_vfp_mrs(void)
2619{
7d1b0095 2620 TCGv tmp = tcg_temp_new_i32();
4373f3ce
PB		 2621 tcg_gen_mov_i32(tmp, cpu_F0s);
2622 return tmp;
2623}
2624
2625static void gen_vfp_msr(TCGv tmp)
2626{
2627 tcg_gen_mov_i32(cpu_F0s, tmp);
7d1b0095 2628 tcg_temp_free_i32(tmp);
4373f3ce
PB		 2629}
2630
ad69471c
PB		 2631static void gen_neon_dup_u8(TCGv var, int shift)
2632{
7d1b0095 2633 TCGv tmp = tcg_temp_new_i32();
ad69471c
PB		 2634 if (shift)
2635 tcg_gen_shri_i32(var, var, shift);
86831435 2636 tcg_gen_ext8u_i32(var, var);
ad69471c
PB		 2637 tcg_gen_shli_i32(tmp, var, 8);
2638 tcg_gen_or_i32(var, var, tmp);
2639 tcg_gen_shli_i32(tmp, var, 16);
2640 tcg_gen_or_i32(var, var, tmp);
7d1b0095 2641 tcg_temp_free_i32(tmp);
ad69471c
PB		 2642}
2643
2644static void gen_neon_dup_low16(TCGv var)
2645{
7d1b0095 2646 TCGv tmp = tcg_temp_new_i32();
86831435 2647 tcg_gen_ext16u_i32(var, var);
ad69471c
PB		 2648 tcg_gen_shli_i32(tmp, var, 16);
2649 tcg_gen_or_i32(var, var, tmp);
7d1b0095 2650 tcg_temp_free_i32(tmp);
ad69471c
PB		 2651}
2652
2653static void gen_neon_dup_high16(TCGv var)
2654{
7d1b0095 2655 TCGv tmp = tcg_temp_new_i32();
ad69471c
PB		 2656 tcg_gen_andi_i32(var, var, 0xffff0000);
2657 tcg_gen_shri_i32(tmp, var, 16);
2658 tcg_gen_or_i32(var, var, tmp);
7d1b0095 2659 tcg_temp_free_i32(tmp);
ad69471c
PB		 2660}
2661
8e18cde3
PM		 2662static TCGv gen_load_and_replicate(DisasContext *s, TCGv addr, int size)
2663{
2664 /* Load a single Neon element and replicate into a 32 bit TCG reg */
2665 TCGv tmp;
2666 switch (size) {
2667 case 0:
2668 tmp = gen_ld8u(addr, IS_USER(s));
2669 gen_neon_dup_u8(tmp, 0);
2670 break;
2671 case 1:
2672 tmp = gen_ld16u(addr, IS_USER(s));
2673 gen_neon_dup_low16(tmp);
2674 break;
2675 case 2:
2676 tmp = gen_ld32(addr, IS_USER(s));
2677 break;
2678 default: /* Avoid compiler warnings. */
2679 abort();
2680 }
2681 return tmp;
2682}
2683
b7bcbe95
FB		 2684/* Disassemble a VFP instruction. Returns nonzero if an error occured
2685 (ie. an undefined instruction). */
2686static int disas_vfp_insn(CPUState * env, DisasContext *s, uint32_t insn)
2687{
2688 uint32_t rd, rn, rm, op, i, n, offset, delta_d, delta_m, bank_mask;
2689 int dp, veclen;
312eea9f 2690 TCGv addr;
4373f3ce 2691 TCGv tmp;
ad69471c 2692 TCGv tmp2;
b7bcbe95 2693
40f137e1
PB		 2694 if (!arm_feature(env, ARM_FEATURE_VFP))
2695 return 1;
2696
5df8bac1 2697 if (!s->vfp_enabled) {
9ee6e8bb 2698 /* VFP disabled. Only allow fmxr/fmrx to/from some control regs. */
40f137e1
PB		 2699 if ((insn & 0x0fe00fff) != 0x0ee00a10)
2700 return 1;
2701 rn = (insn >> 16) & 0xf;
9ee6e8bb
PB		 2702 if (rn != ARM_VFP_FPSID && rn != ARM_VFP_FPEXC
2703 && rn != ARM_VFP_MVFR1 && rn != ARM_VFP_MVFR0)
40f137e1
PB		 2704 return 1;
2705 }
b7bcbe95
FB		 2706 dp = ((insn & 0xf00) == 0xb00);
2707 switch ((insn >> 24) & 0xf) {
2708 case 0xe:
2709 if (insn & (1 << 4)) {
2710 /* single register transfer */
b7bcbe95
FB		 2711 rd = (insn >> 12) & 0xf;
2712 if (dp) {
9ee6e8bb
PB		 2713 int size;
2714 int pass;
2715
2716 VFP_DREG_N(rn, insn);
2717 if (insn & 0xf)
b7bcbe95 2718 return 1;
9ee6e8bb
PB		 2719 if (insn & 0x00c00060
2720 && !arm_feature(env, ARM_FEATURE_NEON))
2721 return 1;
2722
2723 pass = (insn >> 21) & 1;
2724 if (insn & (1 << 22)) {
2725 size = 0;
2726 offset = ((insn >> 5) & 3) * 8;
2727 } else if (insn & (1 << 5)) {
2728 size = 1;
2729 offset = (insn & (1 << 6)) ? 16 : 0;
2730 } else {
2731 size = 2;
2732 offset = 0;
2733 }
18c9b560 2734 if (insn & ARM_CP_RW_BIT) {
b7bcbe95 2735 /* vfp->arm */
ad69471c 2736 tmp = neon_load_reg(rn, pass);
9ee6e8bb
PB		 2737 switch (size) {
2738 case 0:
9ee6e8bb 2739 if (offset)
ad69471c 2740 tcg_gen_shri_i32(tmp, tmp, offset);
9ee6e8bb 2741 if (insn & (1 << 23))
ad69471c 2742 gen_uxtb(tmp);
9ee6e8bb 2743 else
ad69471c 2744 gen_sxtb(tmp);
9ee6e8bb
PB		 2745 break;
2746 case 1:
9ee6e8bb
PB		 2747 if (insn & (1 << 23)) {
2748 if (offset) {
ad69471c 2749 tcg_gen_shri_i32(tmp, tmp, 16);
9ee6e8bb 2750 } else {
ad69471c 2751 gen_uxth(tmp);
9ee6e8bb
PB		 2752 }
2753 } else {
2754 if (offset) {
ad69471c 2755 tcg_gen_sari_i32(tmp, tmp, 16);
9ee6e8bb 2756 } else {
ad69471c 2757 gen_sxth(tmp);
9ee6e8bb
PB		 2758 }
2759 }
2760 break;
2761 case 2:
9ee6e8bb
PB		 2762 break;
2763 }
ad69471c 2764 store_reg(s, rd, tmp);
b7bcbe95
FB		 2765 } else {
2766 /* arm->vfp */
ad69471c 2767 tmp = load_reg(s, rd);
9ee6e8bb
PB		 2768 if (insn & (1 << 23)) {
2769 /* VDUP */
2770 if (size == 0) {
ad69471c 2771 gen_neon_dup_u8(tmp, 0);
9ee6e8bb 2772 } else if (size == 1) {
ad69471c 2773 gen_neon_dup_low16(tmp);
9ee6e8bb 2774 }
cbbccffc 2775 for (n = 0; n <= pass * 2; n++) {
7d1b0095 2776 tmp2 = tcg_temp_new_i32();
cbbccffc
PB		 2777 tcg_gen_mov_i32(tmp2, tmp);
2778 neon_store_reg(rn, n, tmp2);
2779 }
2780 neon_store_reg(rn, n, tmp);
9ee6e8bb
PB		 2781 } else {
2782 /* VMOV */
2783 switch (size) {
2784 case 0:
ad69471c
PB		 2785 tmp2 = neon_load_reg(rn, pass);
2786 gen_bfi(tmp, tmp2, tmp, offset, 0xff);
7d1b0095 2787 tcg_temp_free_i32(tmp2);
9ee6e8bb
PB		 2788 break;
2789 case 1:
ad69471c
PB		 2790 tmp2 = neon_load_reg(rn, pass);
2791 gen_bfi(tmp, tmp2, tmp, offset, 0xffff);
7d1b0095 2792 tcg_temp_free_i32(tmp2);
9ee6e8bb
PB		 2793 break;
2794 case 2:
9ee6e8bb
PB		 2795 break;
2796 }
ad69471c 2797 neon_store_reg(rn, pass, tmp);
9ee6e8bb 2798 }
b7bcbe95 2799 }
9ee6e8bb
PB		 2800 } else { /* !dp */
2801 if ((insn & 0x6f) != 0x00)
2802 return 1;
2803 rn = VFP_SREG_N(insn);
18c9b560 2804 if (insn & ARM_CP_RW_BIT) {
b7bcbe95
FB		 2805 /* vfp->arm */
2806 if (insn & (1 << 21)) {
2807 /* system register */
40f137e1 2808 rn >>= 1;
9ee6e8bb 2809
b7bcbe95 2810 switch (rn) {
40f137e1 2811 case ARM_VFP_FPSID:
4373f3ce 2812 /* VFP2 allows access to FSID from userspace.
9ee6e8bb
PB		 2813 VFP3 restricts all id registers to privileged
2814 accesses. */
2815 if (IS_USER(s)
2816 && arm_feature(env, ARM_FEATURE_VFP3))
2817 return 1;
4373f3ce 2818 tmp = load_cpu_field(vfp.xregs[rn]);
9ee6e8bb 2819 break;
40f137e1 2820 case ARM_VFP_FPEXC:
9ee6e8bb
PB		 2821 if (IS_USER(s))
2822 return 1;
4373f3ce 2823 tmp = load_cpu_field(vfp.xregs[rn]);
9ee6e8bb 2824 break;
40f137e1
PB		 2825 case ARM_VFP_FPINST:
2826 case ARM_VFP_FPINST2:
9ee6e8bb
PB		 2827 /* Not present in VFP3. */
2828 if (IS_USER(s)
2829 || arm_feature(env, ARM_FEATURE_VFP3))
2830 return 1;
4373f3ce 2831 tmp = load_cpu_field(vfp.xregs[rn]);
b7bcbe95 2832 break;
40f137e1 2833 case ARM_VFP_FPSCR:
601d70b9 2834 if (rd == 15) {
4373f3ce
PB		 2835 tmp = load_cpu_field(vfp.xregs[ARM_VFP_FPSCR]);
2836 tcg_gen_andi_i32(tmp, tmp, 0xf0000000);
2837 } else {
7d1b0095 2838 tmp = tcg_temp_new_i32();
4373f3ce
PB		 2839 gen_helper_vfp_get_fpscr(tmp, cpu_env);
2840 }
b7bcbe95 2841 break;
9ee6e8bb
PB		 2842 case ARM_VFP_MVFR0:
2843 case ARM_VFP_MVFR1:
2844 if (IS_USER(s)
2845 || !arm_feature(env, ARM_FEATURE_VFP3))
2846 return 1;
4373f3ce 2847 tmp = load_cpu_field(vfp.xregs[rn]);
9ee6e8bb 2848 break;
b7bcbe95
FB		 2849 default:
2850 return 1;
2851 }
2852 } else {
2853 gen_mov_F0_vreg(0, rn);
4373f3ce 2854 tmp = gen_vfp_mrs();
b7bcbe95
FB		 2855 }
2856 if (rd == 15) {
b5ff1b31 2857 /* Set the 4 flag bits in the CPSR. */
4373f3ce 2858 gen_set_nzcv(tmp);
7d1b0095 2859 tcg_temp_free_i32(tmp);
4373f3ce
PB		 2860 } else {
2861 store_reg(s, rd, tmp);
2862 }
b7bcbe95
FB		 2863 } else {
2864 /* arm->vfp */
4373f3ce 2865 tmp = load_reg(s, rd);
b7bcbe95 2866 if (insn & (1 << 21)) {
40f137e1 2867 rn >>= 1;
b7bcbe95
FB		 2868 /* system register */
2869 switch (rn) {
40f137e1 2870 case ARM_VFP_FPSID:
9ee6e8bb
PB		 2871 case ARM_VFP_MVFR0:
2872 case ARM_VFP_MVFR1:
b7bcbe95
FB		 2873 /* Writes are ignored. */
2874 break;
40f137e1 2875 case ARM_VFP_FPSCR:
4373f3ce 2876 gen_helper_vfp_set_fpscr(cpu_env, tmp);
7d1b0095 2877 tcg_temp_free_i32(tmp);
b5ff1b31 2878 gen_lookup_tb(s);
b7bcbe95 2879 break;
40f137e1 2880 case ARM_VFP_FPEXC:
9ee6e8bb
PB		 2881 if (IS_USER(s))
2882 return 1;
71b3c3de
JR		 2883 /* TODO: VFP subarchitecture support.
2884 * For now, keep the EN bit only */
2885 tcg_gen_andi_i32(tmp, tmp, 1 << 30);
4373f3ce 2886 store_cpu_field(tmp, vfp.xregs[rn]);
40f137e1
PB		 2887 gen_lookup_tb(s);
2888 break;
2889 case ARM_VFP_FPINST:
2890 case ARM_VFP_FPINST2:
4373f3ce 2891 store_cpu_field(tmp, vfp.xregs[rn]);
40f137e1 2892 break;
b7bcbe95
FB		 2893 default:
2894 return 1;
2895 }
2896 } else {
4373f3ce 2897 gen_vfp_msr(tmp);
b7bcbe95
FB		 2898 gen_mov_vreg_F0(0, rn);
2899 }
2900 }
2901 }
2902 } else {
2903 /* data processing */
2904 /* The opcode is in bits 23, 21, 20 and 6. */
2905 op = ((insn >> 20) & 8) | ((insn >> 19) & 6) | ((insn >> 6) & 1);
2906 if (dp) {
2907 if (op == 15) {
2908 /* rn is opcode */
2909 rn = ((insn >> 15) & 0x1e) | ((insn >> 7) & 1);
2910 } else {
2911 /* rn is register number */
9ee6e8bb 2912 VFP_DREG_N(rn, insn);
b7bcbe95
FB		 2913 }
2914
04595bf6 2915 if (op == 15 && (rn == 15 || ((rn & 0x1c) == 0x18))) {
b7bcbe95 2916 /* Integer or single precision destination. */
9ee6e8bb 2917 rd = VFP_SREG_D(insn);
b7bcbe95 2918 } else {
9ee6e8bb 2919 VFP_DREG_D(rd, insn);
b7bcbe95 2920 }
04595bf6
PM		 2921 if (op == 15 &&
2922 (((rn & 0x1c) == 0x10) || ((rn & 0x14) == 0x14))) {
2923 /* VCVT from int is always from S reg regardless of dp bit.
2924 * VCVT with immediate frac_bits has same format as SREG_M
2925 */
2926 rm = VFP_SREG_M(insn);
b7bcbe95 2927 } else {
9ee6e8bb 2928 VFP_DREG_M(rm, insn);
b7bcbe95
FB		 2929 }
2930 } else {
9ee6e8bb 2931 rn = VFP_SREG_N(insn);
b7bcbe95
FB		 2932 if (op == 15 && rn == 15) {
2933 /* Double precision destination. */
9ee6e8bb
PB		 2934 VFP_DREG_D(rd, insn);
2935 } else {
2936 rd = VFP_SREG_D(insn);
2937 }
04595bf6
PM		 2938 /* NB that we implicitly rely on the encoding for the frac_bits
2939 * in VCVT of fixed to float being the same as that of an SREG_M
2940 */
9ee6e8bb 2941 rm = VFP_SREG_M(insn);
b7bcbe95
FB		 2942 }
2943
69d1fc22 2944 veclen = s->vec_len;
b7bcbe95
FB		 2945 if (op == 15 && rn > 3)
2946 veclen = 0;
2947
2948 /* Shut up compiler warnings. */
2949 delta_m = 0;
2950 delta_d = 0;
2951 bank_mask = 0;
3b46e624 2952
b7bcbe95
FB		 2953 if (veclen > 0) {
2954 if (dp)
2955 bank_mask = 0xc;
2956 else
2957 bank_mask = 0x18;
2958
2959 /* Figure out what type of vector operation this is. */
2960 if ((rd & bank_mask) == 0) {
2961 /* scalar */
2962 veclen = 0;
2963 } else {
2964 if (dp)
69d1fc22 2965 delta_d = (s->vec_stride >> 1) + 1;
b7bcbe95 2966 else
69d1fc22 2967 delta_d = s->vec_stride + 1;
b7bcbe95
FB		 2968
2969 if ((rm & bank_mask) == 0) {
2970 /* mixed scalar/vector */
2971 delta_m = 0;
2972 } else {
2973 /* vector */
2974 delta_m = delta_d;
2975 }
2976 }
2977 }
2978
2979 /* Load the initial operands. */
2980 if (op == 15) {
2981 switch (rn) {
2982 case 16:
2983 case 17:
2984 /* Integer source */
2985 gen_mov_F0_vreg(0, rm);
2986 break;
2987 case 8:
2988 case 9:
2989 /* Compare */
2990 gen_mov_F0_vreg(dp, rd);
2991 gen_mov_F1_vreg(dp, rm);
2992 break;
2993 case 10:
2994 case 11:
2995 /* Compare with zero */
2996 gen_mov_F0_vreg(dp, rd);
2997 gen_vfp_F1_ld0(dp);
2998 break;
9ee6e8bb
PB		 2999 case 20:
3000 case 21:
3001 case 22:
3002 case 23:
644ad806
PB		 3003 case 28:
3004 case 29:
3005 case 30:
3006 case 31:
9ee6e8bb
PB		 3007 /* Source and destination the same. */
3008 gen_mov_F0_vreg(dp, rd);
3009 break;
b7bcbe95
FB		 3010 default:
3011 /* One source operand. */
3012 gen_mov_F0_vreg(dp, rm);
9ee6e8bb 3013 break;
b7bcbe95
FB		 3014 }
3015 } else {
3016 /* Two source operands. */
3017 gen_mov_F0_vreg(dp, rn);
3018 gen_mov_F1_vreg(dp, rm);
3019 }
3020
3021 for (;;) {
3022 /* Perform the calculation. */
3023 switch (op) {
3024 case 0: /* mac: fd + (fn * fm) */
3025 gen_vfp_mul(dp);
3026 gen_mov_F1_vreg(dp, rd);
3027 gen_vfp_add(dp);
3028 break;
3029 case 1: /* nmac: fd - (fn * fm) */
3030 gen_vfp_mul(dp);
3031 gen_vfp_neg(dp);
3032 gen_mov_F1_vreg(dp, rd);
3033 gen_vfp_add(dp);
3034 break;
3035 case 2: /* msc: -fd + (fn * fm) */
3036 gen_vfp_mul(dp);
3037 gen_mov_F1_vreg(dp, rd);
3038 gen_vfp_sub(dp);
3039 break;
3040 case 3: /* nmsc: -fd - (fn * fm) */
3041 gen_vfp_mul(dp);
b7bcbe95 3042 gen_vfp_neg(dp);
c9fb531a
PB		 3043 gen_mov_F1_vreg(dp, rd);
3044 gen_vfp_sub(dp);
b7bcbe95
FB		 3045 break;
3046 case 4: /* mul: fn * fm */
3047 gen_vfp_mul(dp);
3048 break;
3049 case 5: /* nmul: -(fn * fm) */
3050 gen_vfp_mul(dp);
3051 gen_vfp_neg(dp);
3052 break;
3053 case 6: /* add: fn + fm */
3054 gen_vfp_add(dp);
3055 break;
3056 case 7: /* sub: fn - fm */
3057 gen_vfp_sub(dp);
3058 break;
3059 case 8: /* div: fn / fm */
3060 gen_vfp_div(dp);
3061 break;
9ee6e8bb
PB		 3062 case 14: /* fconst */
3063 if (!arm_feature(env, ARM_FEATURE_VFP3))
3064 return 1;
3065
3066 n = (insn << 12) & 0x80000000;
3067 i = ((insn >> 12) & 0x70) | (insn & 0xf);
3068 if (dp) {
3069 if (i & 0x40)
3070 i |= 0x3f80;
3071 else
3072 i |= 0x4000;
3073 n |= i << 16;
4373f3ce 3074 tcg_gen_movi_i64(cpu_F0d, ((uint64_t)n) << 32);
9ee6e8bb
PB		 3075 } else {
3076 if (i & 0x40)
3077 i |= 0x780;
3078 else
3079 i |= 0x800;
3080 n |= i << 19;
5b340b51 3081 tcg_gen_movi_i32(cpu_F0s, n);
9ee6e8bb 3082 }
9ee6e8bb 3083 break;
b7bcbe95
FB		 3084 case 15: /* extension space */
3085 switch (rn) {
3086 case 0: /* cpy */
3087 /* no-op */
3088 break;
3089 case 1: /* abs */
3090 gen_vfp_abs(dp);
3091 break;
3092 case 2: /* neg */
3093 gen_vfp_neg(dp);
3094 break;
3095 case 3: /* sqrt */
3096 gen_vfp_sqrt(dp);
3097 break;
60011498
PB		 3098 case 4: /* vcvtb.f32.f16 */
3099 if (!arm_feature(env, ARM_FEATURE_VFP_FP16))
3100 return 1;
3101 tmp = gen_vfp_mrs();
3102 tcg_gen_ext16u_i32(tmp, tmp);
3103 gen_helper_vfp_fcvt_f16_to_f32(cpu_F0s, tmp, cpu_env);
7d1b0095 3104 tcg_temp_free_i32(tmp);
60011498
PB		 3105 break;
3106 case 5: /* vcvtt.f32.f16 */
3107 if (!arm_feature(env, ARM_FEATURE_VFP_FP16))
3108 return 1;
3109 tmp = gen_vfp_mrs();
3110 tcg_gen_shri_i32(tmp, tmp, 16);
3111 gen_helper_vfp_fcvt_f16_to_f32(cpu_F0s, tmp, cpu_env);
7d1b0095 3112 tcg_temp_free_i32(tmp);
60011498
PB		 3113 break;
3114 case 6: /* vcvtb.f16.f32 */
3115 if (!arm_feature(env, ARM_FEATURE_VFP_FP16))
3116 return 1;
7d1b0095 3117 tmp = tcg_temp_new_i32();
60011498
PB		 3118 gen_helper_vfp_fcvt_f32_to_f16(tmp, cpu_F0s, cpu_env);
3119 gen_mov_F0_vreg(0, rd);
3120 tmp2 = gen_vfp_mrs();
3121 tcg_gen_andi_i32(tmp2, tmp2, 0xffff0000);
3122 tcg_gen_or_i32(tmp, tmp, tmp2);
7d1b0095 3123 tcg_temp_free_i32(tmp2);
60011498
PB		 3124 gen_vfp_msr(tmp);
3125 break;
3126 case 7: /* vcvtt.f16.f32 */
3127 if (!arm_feature(env, ARM_FEATURE_VFP_FP16))
3128 return 1;
7d1b0095 3129 tmp = tcg_temp_new_i32();
60011498
PB		 3130 gen_helper_vfp_fcvt_f32_to_f16(tmp, cpu_F0s, cpu_env);
3131 tcg_gen_shli_i32(tmp, tmp, 16);
3132 gen_mov_F0_vreg(0, rd);
3133 tmp2 = gen_vfp_mrs();
3134 tcg_gen_ext16u_i32(tmp2, tmp2);
3135 tcg_gen_or_i32(tmp, tmp, tmp2);
7d1b0095 3136 tcg_temp_free_i32(tmp2);
60011498
PB		 3137 gen_vfp_msr(tmp);
3138 break;
b7bcbe95
FB		 3139 case 8: /* cmp */
3140 gen_vfp_cmp(dp);
3141 break;
3142 case 9: /* cmpe */
3143 gen_vfp_cmpe(dp);
3144 break;
3145 case 10: /* cmpz */
3146 gen_vfp_cmp(dp);
3147 break;
3148 case 11: /* cmpez */
3149 gen_vfp_F1_ld0(dp);
3150 gen_vfp_cmpe(dp);
3151 break;
3152 case 15: /* single<->double conversion */
3153 if (dp)
4373f3ce 3154 gen_helper_vfp_fcvtsd(cpu_F0s, cpu_F0d, cpu_env);
b7bcbe95 3155 else
4373f3ce 3156 gen_helper_vfp_fcvtds(cpu_F0d, cpu_F0s, cpu_env);
b7bcbe95
FB		 3157 break;
3158 case 16: /* fuito */
3159 gen_vfp_uito(dp);
3160 break;
3161 case 17: /* fsito */
3162 gen_vfp_sito(dp);
3163 break;
9ee6e8bb
PB		 3164 case 20: /* fshto */
3165 if (!arm_feature(env, ARM_FEATURE_VFP3))
3166 return 1;
644ad806 3167 gen_vfp_shto(dp, 16 - rm);
9ee6e8bb
PB		 3168 break;
3169 case 21: /* fslto */
3170 if (!arm_feature(env, ARM_FEATURE_VFP3))
3171 return 1;
644ad806 3172 gen_vfp_slto(dp, 32 - rm);
9ee6e8bb
PB		 3173 break;
3174 case 22: /* fuhto */
3175 if (!arm_feature(env, ARM_FEATURE_VFP3))
3176 return 1;
644ad806 3177 gen_vfp_uhto(dp, 16 - rm);
9ee6e8bb
PB		 3178 break;
3179 case 23: /* fulto */
3180 if (!arm_feature(env, ARM_FEATURE_VFP3))
3181 return 1;
644ad806 3182 gen_vfp_ulto(dp, 32 - rm);
9ee6e8bb 3183 break;
b7bcbe95
FB		 3184 case 24: /* ftoui */
3185 gen_vfp_toui(dp);
3186 break;
3187 case 25: /* ftouiz */
3188 gen_vfp_touiz(dp);
3189 break;
3190 case 26: /* ftosi */
3191 gen_vfp_tosi(dp);
3192 break;
3193 case 27: /* ftosiz */
3194 gen_vfp_tosiz(dp);
3195 break;
9ee6e8bb
PB		 3196 case 28: /* ftosh */
3197 if (!arm_feature(env, ARM_FEATURE_VFP3))
3198 return 1;
644ad806 3199 gen_vfp_tosh(dp, 16 - rm);
9ee6e8bb
PB		 3200 break;
3201 case 29: /* ftosl */
3202 if (!arm_feature(env, ARM_FEATURE_VFP3))
3203 return 1;
644ad806 3204 gen_vfp_tosl(dp, 32 - rm);
9ee6e8bb
PB		 3205 break;
3206 case 30: /* ftouh */
3207 if (!arm_feature(env, ARM_FEATURE_VFP3))
3208 return 1;
644ad806 3209 gen_vfp_touh(dp, 16 - rm);
9ee6e8bb
PB		 3210 break;
3211 case 31: /* ftoul */
3212 if (!arm_feature(env, ARM_FEATURE_VFP3))
3213 return 1;
644ad806 3214 gen_vfp_toul(dp, 32 - rm);
9ee6e8bb 3215 break;
b7bcbe95
FB		 3216 default: /* undefined */
3217 printf ("rn:%d\n", rn);
3218 return 1;
3219 }
3220 break;
3221 default: /* undefined */
3222 printf ("op:%d\n", op);
3223 return 1;
3224 }
3225
3226 /* Write back the result. */
3227 if (op == 15 && (rn >= 8 && rn <= 11))
3228 ; /* Comparison, do nothing. */
04595bf6
PM		 3229 else if (op == 15 && dp && ((rn & 0x1c) == 0x18))
3230 /* VCVT double to int: always integer result. */
b7bcbe95
FB		 3231 gen_mov_vreg_F0(0, rd);
3232 else if (op == 15 && rn == 15)
3233 /* conversion */
3234 gen_mov_vreg_F0(!dp, rd);
3235 else
3236 gen_mov_vreg_F0(dp, rd);
3237
3238 /* break out of the loop if we have finished */
3239 if (veclen == 0)
3240 break;
3241
3242 if (op == 15 && delta_m == 0) {
3243 /* single source one-many */
3244 while (veclen--) {
3245 rd = ((rd + delta_d) & (bank_mask - 1))
3246 | (rd & bank_mask);
3247 gen_mov_vreg_F0(dp, rd);
3248 }
3249 break;
3250 }
3251 /* Setup the next operands. */
3252 veclen--;
3253 rd = ((rd + delta_d) & (bank_mask - 1))
3254 | (rd & bank_mask);
3255
3256 if (op == 15) {
3257 /* One source operand. */
3258 rm = ((rm + delta_m) & (bank_mask - 1))
3259 | (rm & bank_mask);
3260 gen_mov_F0_vreg(dp, rm);
3261 } else {
3262 /* Two source operands. */
3263 rn = ((rn + delta_d) & (bank_mask - 1))
3264 | (rn & bank_mask);
3265 gen_mov_F0_vreg(dp, rn);
3266 if (delta_m) {
3267 rm = ((rm + delta_m) & (bank_mask - 1))
3268 | (rm & bank_mask);
3269 gen_mov_F1_vreg(dp, rm);
3270 }
3271 }
3272 }
3273 }
3274 break;
3275 case 0xc:
3276 case 0xd:
8387da81 3277 if ((insn & 0x03e00000) == 0x00400000) {
b7bcbe95
FB		 3278 /* two-register transfer */
3279 rn = (insn >> 16) & 0xf;
3280 rd = (insn >> 12) & 0xf;
3281 if (dp) {
9ee6e8bb
PB		 3282 VFP_DREG_M(rm, insn);
3283 } else {
3284 rm = VFP_SREG_M(insn);
3285 }
b7bcbe95 3286
18c9b560 3287 if (insn & ARM_CP_RW_BIT) {
b7bcbe95
FB		 3288 /* vfp->arm */
3289 if (dp) {
4373f3ce
PB		 3290 gen_mov_F0_vreg(0, rm * 2);
3291 tmp = gen_vfp_mrs();
3292 store_reg(s, rd, tmp);
3293 gen_mov_F0_vreg(0, rm * 2 + 1);
3294 tmp = gen_vfp_mrs();
3295 store_reg(s, rn, tmp);
b7bcbe95
FB		 3296 } else {
3297 gen_mov_F0_vreg(0, rm);
4373f3ce 3298 tmp = gen_vfp_mrs();
8387da81 3299 store_reg(s, rd, tmp);
b7bcbe95 3300 gen_mov_F0_vreg(0, rm + 1);
4373f3ce 3301 tmp = gen_vfp_mrs();
8387da81 3302 store_reg(s, rn, tmp);
b7bcbe95
FB		 3303 }
3304 } else {
3305 /* arm->vfp */
3306 if (dp) {
4373f3ce
PB		 3307 tmp = load_reg(s, rd);
3308 gen_vfp_msr(tmp);
3309 gen_mov_vreg_F0(0, rm * 2);
3310 tmp = load_reg(s, rn);
3311 gen_vfp_msr(tmp);
3312 gen_mov_vreg_F0(0, rm * 2 + 1);
b7bcbe95 3313 } else {
8387da81 3314 tmp = load_reg(s, rd);
4373f3ce 3315 gen_vfp_msr(tmp);
b7bcbe95 3316 gen_mov_vreg_F0(0, rm);
8387da81 3317 tmp = load_reg(s, rn);
4373f3ce 3318 gen_vfp_msr(tmp);
b7bcbe95
FB		 3319 gen_mov_vreg_F0(0, rm + 1);
3320 }
3321 }
3322 } else {
3323 /* Load/store */
3324 rn = (insn >> 16) & 0xf;
3325 if (dp)
9ee6e8bb 3326 VFP_DREG_D(rd, insn);
b7bcbe95 3327 else
9ee6e8bb
PB		 3328 rd = VFP_SREG_D(insn);
3329 if (s->thumb && rn == 15) {
7d1b0095 3330 addr = tcg_temp_new_i32();
312eea9f 3331 tcg_gen_movi_i32(addr, s->pc & ~2);
9ee6e8bb 3332 } else {
312eea9f 3333 addr = load_reg(s, rn);
9ee6e8bb 3334 }
b7bcbe95
FB		 3335 if ((insn & 0x01200000) == 0x01000000) {
3336 /* Single load/store */
3337 offset = (insn & 0xff) << 2;
3338 if ((insn & (1 << 23)) == 0)
3339 offset = -offset;
312eea9f 3340 tcg_gen_addi_i32(addr, addr, offset);
b7bcbe95 3341 if (insn & (1 << 20)) {
312eea9f 3342 gen_vfp_ld(s, dp, addr);
b7bcbe95
FB		 3343 gen_mov_vreg_F0(dp, rd);
3344 } else {
3345 gen_mov_F0_vreg(dp, rd);
312eea9f 3346 gen_vfp_st(s, dp, addr);
b7bcbe95 3347 }
7d1b0095 3348 tcg_temp_free_i32(addr);
b7bcbe95
FB		 3349 } else {
3350 /* load/store multiple */
3351 if (dp)
3352 n = (insn >> 1) & 0x7f;
3353 else
3354 n = insn & 0xff;
3355
3356 if (insn & (1 << 24)) /* pre-decrement */
312eea9f 3357 tcg_gen_addi_i32(addr, addr, -((insn & 0xff) << 2));
b7bcbe95
FB		 3358
3359 if (dp)
3360 offset = 8;
3361 else
3362 offset = 4;
3363 for (i = 0; i < n; i++) {
18c9b560 3364 if (insn & ARM_CP_RW_BIT) {
b7bcbe95 3365 /* load */
312eea9f 3366 gen_vfp_ld(s, dp, addr);
b7bcbe95
FB		 3367 gen_mov_vreg_F0(dp, rd + i);
3368 } else {
3369 /* store */
3370 gen_mov_F0_vreg(dp, rd + i);
312eea9f 3371 gen_vfp_st(s, dp, addr);
b7bcbe95 3372 }
312eea9f 3373 tcg_gen_addi_i32(addr, addr, offset);
b7bcbe95
FB		 3374 }
3375 if (insn & (1 << 21)) {
3376 /* writeback */
3377 if (insn & (1 << 24))
3378 offset = -offset * n;
3379 else if (dp && (insn & 1))
3380 offset = 4;
3381 else
3382 offset = 0;
3383
3384 if (offset != 0)
312eea9f
FN		 3385 tcg_gen_addi_i32(addr, addr, offset);
3386 store_reg(s, rn, addr);
3387 } else {
7d1b0095 3388 tcg_temp_free_i32(addr);
b7bcbe95
FB		 3389 }
3390 }
3391 }
3392 break;
3393 default:
3394 /* Should never happen. */
3395 return 1;
3396 }
3397 return 0;
3398}
3399
6e256c93 3400static inline void gen_goto_tb(DisasContext *s, int n, uint32_t dest)
c53be334 3401{
6e256c93
FB		 3402 TranslationBlock *tb;
3403
3404 tb = s->tb;
3405 if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK)) {
57fec1fe 3406 tcg_gen_goto_tb(n);
8984bd2e 3407 gen_set_pc_im(dest);
4b4a72e5 3408 tcg_gen_exit_tb((tcg_target_long)tb + n);
6e256c93 3409 } else {
8984bd2e 3410 gen_set_pc_im(dest);
57fec1fe 3411 tcg_gen_exit_tb(0);
6e256c93 3412 }
c53be334
FB		 3413}
3414
8aaca4c0
FB		 3415static inline void gen_jmp (DisasContext *s, uint32_t dest)
3416{
551bd27f 3417 if (unlikely(s->singlestep_enabled)) {
8aaca4c0 3418 /* An indirect jump so that we still trigger the debug exception. */
5899f386 3419 if (s->thumb)
d9ba4830
PB		 3420 dest |= 1;
3421 gen_bx_im(s, dest);
8aaca4c0 3422 } else {
6e256c93 3423 gen_goto_tb(s, 0, dest);
8aaca4c0
FB		 3424 s->is_jmp = DISAS_TB_JUMP;
3425 }
3426}
3427
d9ba4830 3428static inline void gen_mulxy(TCGv t0, TCGv t1, int x, int y)
b5ff1b31 3429{
ee097184 3430 if (x)
d9ba4830 3431 tcg_gen_sari_i32(t0, t0, 16);
b5ff1b31 3432 else
d9ba4830 3433 gen_sxth(t0);
ee097184 3434 if (y)
d9ba4830 3435 tcg_gen_sari_i32(t1, t1, 16);
b5ff1b31 3436 else
d9ba4830
PB		 3437 gen_sxth(t1);
3438 tcg_gen_mul_i32(t0, t0, t1);
b5ff1b31
FB		 3439}
3440
3441/* Return the mask of PSR bits set by a MSR instruction. */
9ee6e8bb 3442static uint32_t msr_mask(CPUState *env, DisasContext *s, int flags, int spsr) {
b5ff1b31
FB		 3443 uint32_t mask;
3444
3445 mask = 0;
3446 if (flags & (1 << 0))
3447 mask |= 0xff;
3448 if (flags & (1 << 1))
3449 mask |= 0xff00;
3450 if (flags & (1 << 2))
3451 mask |= 0xff0000;
3452 if (flags & (1 << 3))
3453 mask |= 0xff000000;
9ee6e8bb 3454
2ae23e75 3455 /* Mask out undefined bits. */
9ee6e8bb 3456 mask &= ~CPSR_RESERVED;
be5e7a76
DES		 3457 if (!arm_feature(env, ARM_FEATURE_V4T))
3458 mask &= ~CPSR_T;
3459 if (!arm_feature(env, ARM_FEATURE_V5))
3460 mask &= ~CPSR_Q; /* V5TE in reality*/
9ee6e8bb 3461 if (!arm_feature(env, ARM_FEATURE_V6))
e160c51c 3462 mask &= ~(CPSR_E | CPSR_GE);
9ee6e8bb 3463 if (!arm_feature(env, ARM_FEATURE_THUMB2))
e160c51c 3464 mask &= ~CPSR_IT;
9ee6e8bb 3465 /* Mask out execution state bits. */
2ae23e75 3466 if (!spsr)
e160c51c 3467 mask &= ~CPSR_EXEC;
b5ff1b31
FB		 3468 /* Mask out privileged bits. */
3469 if (IS_USER(s))
9ee6e8bb 3470 mask &= CPSR_USER;
b5ff1b31
FB		 3471 return mask;
3472}
3473
2fbac54b
FN		 3474/* Returns nonzero if access to the PSR is not permitted. Marks t0 as dead. */
3475static int gen_set_psr(DisasContext *s, uint32_t mask, int spsr, TCGv t0)
b5ff1b31 3476{
d9ba4830 3477 TCGv tmp;
b5ff1b31
FB		 3478 if (spsr) {
3479 /* ??? This is also undefined in system mode. */
3480 if (IS_USER(s))
3481 return 1;
d9ba4830
PB		 3482
3483 tmp = load_cpu_field(spsr);
3484 tcg_gen_andi_i32(tmp, tmp, ~mask);
2fbac54b
FN		 3485 tcg_gen_andi_i32(t0, t0, mask);
3486 tcg_gen_or_i32(tmp, tmp, t0);
d9ba4830 3487 store_cpu_field(tmp, spsr);
b5ff1b31 3488 } else {
2fbac54b 3489 gen_set_cpsr(t0, mask);
b5ff1b31 3490 }
7d1b0095 3491 tcg_temp_free_i32(t0);
b5ff1b31
FB		 3492 gen_lookup_tb(s);
3493 return 0;
3494}
3495
2fbac54b
FN		 3496/* Returns nonzero if access to the PSR is not permitted. */
3497static int gen_set_psr_im(DisasContext *s, uint32_t mask, int spsr, uint32_t val)
3498{
3499 TCGv tmp;
7d1b0095 3500 tmp = tcg_temp_new_i32();
2fbac54b
FN		 3501 tcg_gen_movi_i32(tmp, val);
3502 return gen_set_psr(s, mask, spsr, tmp);
3503}
3504
e9bb4aa9
JR		 3505/* Generate an old-style exception return. Marks pc as dead. */
3506static void gen_exception_return(DisasContext *s, TCGv pc)
b5ff1b31 3507{
d9ba4830 3508 TCGv tmp;
e9bb4aa9 3509 store_reg(s, 15, pc);
d9ba4830
PB		 3510 tmp = load_cpu_field(spsr);
3511 gen_set_cpsr(tmp, 0xffffffff);
7d1b0095 3512 tcg_temp_free_i32(tmp);
b5ff1b31
FB		 3513 s->is_jmp = DISAS_UPDATE;
3514}
3515
b0109805
PB		 3516/* Generate a v6 exception return. Marks both values as dead. */
3517static void gen_rfe(DisasContext *s, TCGv pc, TCGv cpsr)
2c0262af 3518{
b0109805 3519 gen_set_cpsr(cpsr, 0xffffffff);
7d1b0095 3520 tcg_temp_free_i32(cpsr);
b0109805 3521 store_reg(s, 15, pc);
9ee6e8bb
PB		 3522 s->is_jmp = DISAS_UPDATE;
3523}
3b46e624 3524
9ee6e8bb
PB		 3525static inline void
3526gen_set_condexec (DisasContext *s)
3527{
3528 if (s->condexec_mask) {
8f01245e 3529 uint32_t val = (s->condexec_cond << 4) | (s->condexec_mask >> 1);
7d1b0095 3530 TCGv tmp = tcg_temp_new_i32();
8f01245e 3531 tcg_gen_movi_i32(tmp, val);
d9ba4830 3532 store_cpu_field(tmp, condexec_bits);
9ee6e8bb
PB		 3533 }
3534}
3b46e624 3535
bc4a0de0
PM		 3536static void gen_exception_insn(DisasContext *s, int offset, int excp)
3537{
3538 gen_set_condexec(s);
3539 gen_set_pc_im(s->pc - offset);
3540 gen_exception(excp);
3541 s->is_jmp = DISAS_JUMP;
3542}
3543
9ee6e8bb
PB		 3544static void gen_nop_hint(DisasContext *s, int val)
3545{
3546 switch (val) {
3547 case 3: /* wfi */
8984bd2e 3548 gen_set_pc_im(s->pc);
9ee6e8bb
PB		 3549 s->is_jmp = DISAS_WFI;
3550 break;
3551 case 2: /* wfe */
3552 case 4: /* sev */
3553 /* TODO: Implement SEV and WFE. May help SMP performance. */
3554 default: /* nop */
3555 break;
3556 }
3557}
99c475ab 3558
ad69471c 3559#define CPU_V001 cpu_V0, cpu_V0, cpu_V1
9ee6e8bb 3560
62698be3 3561static inline void gen_neon_add(int size, TCGv t0, TCGv t1)
9ee6e8bb
PB		 3562{
3563 switch (size) {
dd8fbd78
FN		 3564 case 0: gen_helper_neon_add_u8(t0, t0, t1); break;
3565 case 1: gen_helper_neon_add_u16(t0, t0, t1); break;
3566 case 2: tcg_gen_add_i32(t0, t0, t1); break;
62698be3 3567 default: abort();
9ee6e8bb 3568 }
9ee6e8bb
PB		 3569}
3570
dd8fbd78 3571static inline void gen_neon_rsb(int size, TCGv t0, TCGv t1)
ad69471c
PB		 3572{
3573 switch (size) {
dd8fbd78
FN		 3574 case 0: gen_helper_neon_sub_u8(t0, t1, t0); break;
3575 case 1: gen_helper_neon_sub_u16(t0, t1, t0); break;
3576 case 2: tcg_gen_sub_i32(t0, t1, t0); break;
ad69471c
PB		 3577 default: return;
3578 }
3579}
3580
3581/* 32-bit pairwise ops end up the same as the elementwise versions. */
3582#define gen_helper_neon_pmax_s32 gen_helper_neon_max_s32
3583#define gen_helper_neon_pmax_u32 gen_helper_neon_max_u32
3584#define gen_helper_neon_pmin_s32 gen_helper_neon_min_s32
3585#define gen_helper_neon_pmin_u32 gen_helper_neon_min_u32
3586
ad69471c
PB		 3587#define GEN_NEON_INTEGER_OP_ENV(name) do { \
3588 switch ((size << 1) | u) { \
3589 case 0: \
dd8fbd78 3590 gen_helper_neon_##name##_s8(tmp, cpu_env, tmp, tmp2); \
ad69471c
PB		 3591 break; \
3592 case 1: \
dd8fbd78 3593 gen_helper_neon_##name##_u8(tmp, cpu_env, tmp, tmp2); \
ad69471c
PB		 3594 break; \
3595 case 2: \
dd8fbd78 3596 gen_helper_neon_##name##_s16(tmp, cpu_env, tmp, tmp2); \
ad69471c
PB		 3597 break; \
3598 case 3: \
dd8fbd78 3599 gen_helper_neon_##name##_u16(tmp, cpu_env, tmp, tmp2); \
ad69471c
PB		 3600 break; \
3601 case 4: \
dd8fbd78 3602 gen_helper_neon_##name##_s32(tmp, cpu_env, tmp, tmp2); \
ad69471c
PB		 3603 break; \
3604 case 5: \
dd8fbd78 3605 gen_helper_neon_##name##_u32(tmp, cpu_env, tmp, tmp2); \
ad69471c
PB		 3606 break; \
3607 default: return 1; \
3608 }} while (0)
9ee6e8bb
PB		 3609
3610#define GEN_NEON_INTEGER_OP(name) do { \
3611 switch ((size << 1) | u) { \
ad69471c 3612 case 0: \
dd8fbd78 3613 gen_helper_neon_##name##_s8(tmp, tmp, tmp2); \
ad69471c
PB		 3614 break; \
3615 case 1: \
dd8fbd78 3616 gen_helper_neon_##name##_u8(tmp, tmp, tmp2); \
ad69471c
PB		 3617 break; \
3618 case 2: \
dd8fbd78 3619 gen_helper_neon_##name##_s16(tmp, tmp, tmp2); \
ad69471c
PB		 3620 break; \
3621 case 3: \
dd8fbd78 3622 gen_helper_neon_##name##_u16(tmp, tmp, tmp2); \
ad69471c
PB		 3623 break; \
3624 case 4: \
dd8fbd78 3625 gen_helper_neon_##name##_s32(tmp, tmp, tmp2); \
ad69471c
PB		 3626 break; \
3627 case 5: \
dd8fbd78 3628 gen_helper_neon_##name##_u32(tmp, tmp, tmp2); \
ad69471c 3629 break; \
9ee6e8bb
PB		 3630 default: return 1; \
3631 }} while (0)
3632
dd8fbd78 3633static TCGv neon_load_scratch(int scratch)
9ee6e8bb 3634{
7d1b0095 3635 TCGv tmp = tcg_temp_new_i32();
dd8fbd78
FN		 3636 tcg_gen_ld_i32(tmp, cpu_env, offsetof(CPUARMState, vfp.scratch[scratch]));
3637 return tmp;
9ee6e8bb
PB		 3638}
3639
dd8fbd78 3640static void neon_store_scratch(int scratch, TCGv var)
9ee6e8bb 3641{
dd8fbd78 3642 tcg_gen_st_i32(var, cpu_env, offsetof(CPUARMState, vfp.scratch[scratch]));
7d1b0095 3643 tcg_temp_free_i32(var);
9ee6e8bb
PB		 3644}
3645
dd8fbd78 3646static inline TCGv neon_get_scalar(int size, int reg)
9ee6e8bb 3647{
dd8fbd78 3648 TCGv tmp;
9ee6e8bb 3649 if (size == 1) {
0fad6efc
PM		 3650 tmp = neon_load_reg(reg & 7, reg >> 4);
3651 if (reg & 8) {
dd8fbd78 3652 gen_neon_dup_high16(tmp);
0fad6efc
PM		 3653 } else {
3654 gen_neon_dup_low16(tmp);
dd8fbd78 3655 }
0fad6efc
PM		 3656 } else {
3657 tmp = neon_load_reg(reg & 15, reg >> 4);
9ee6e8bb 3658 }
dd8fbd78 3659 return tmp;
9ee6e8bb
PB		 3660}
3661
02acedf9 3662static int gen_neon_unzip(int rd, int rm, int size, int q)
19457615 3663{
02acedf9
PM		 3664 TCGv tmp, tmp2;
3665 if (size == 3 || (!q && size == 2)) {
3666 return 1;
3667 }
3668 tmp = tcg_const_i32(rd);
3669 tmp2 = tcg_const_i32(rm);
3670 if (q) {
3671 switch (size) {
3672 case 0:
2a3f75b4 3673 gen_helper_neon_qunzip8(tmp, tmp2);
02acedf9
PM		 3674 break;
3675 case 1:
2a3f75b4 3676 gen_helper_neon_qunzip16(tmp, tmp2);
02acedf9
PM		 3677 break;
3678 case 2:
2a3f75b4 3679 gen_helper_neon_qunzip32(tmp, tmp2);
02acedf9
PM		 3680 break;
3681 default:
3682 abort();
3683 }
3684 } else {
3685 switch (size) {
3686 case 0:
2a3f75b4 3687 gen_helper_neon_unzip8(tmp, tmp2);
02acedf9
PM		 3688 break;
3689 case 1:
2a3f75b4 3690 gen_helper_neon_unzip16(tmp, tmp2);
02acedf9
PM		 3691 break;
3692 default:
3693 abort();
3694 }
3695 }
3696 tcg_temp_free_i32(tmp);
3697 tcg_temp_free_i32(tmp2);
3698 return 0;
19457615
FN		 3699}
3700
d68a6f3a 3701static int gen_neon_zip(int rd, int rm, int size, int q)
19457615
FN		 3702{
3703 TCGv tmp, tmp2;
d68a6f3a
PM		 3704 if (size == 3 || (!q && size == 2)) {
3705 return 1;
3706 }
3707 tmp = tcg_const_i32(rd);
3708 tmp2 = tcg_const_i32(rm);
3709 if (q) {
3710 switch (size) {
3711 case 0:
2a3f75b4 3712 gen_helper_neon_qzip8(tmp, tmp2);
d68a6f3a
PM		 3713 break;
3714 case 1:
2a3f75b4 3715 gen_helper_neon_qzip16(tmp, tmp2);
d68a6f3a
PM		 3716 break;
3717 case 2:
2a3f75b4 3718 gen_helper_neon_qzip32(tmp, tmp2);
d68a6f3a
PM		 3719 break;
3720 default:
3721 abort();
3722 }
3723 } else {
3724 switch (size) {
3725 case 0:
2a3f75b4 3726 gen_helper_neon_zip8(tmp, tmp2);
d68a6f3a
PM		 3727 break;
3728 case 1:
2a3f75b4 3729 gen_helper_neon_zip16(tmp, tmp2);
d68a6f3a
PM		 3730 break;
3731 default:
3732 abort();
3733 }
3734 }
3735 tcg_temp_free_i32(tmp);
3736 tcg_temp_free_i32(tmp2);
3737 return 0;
19457615
FN		 3738}
3739
19457615
FN		 3740static void gen_neon_trn_u8(TCGv t0, TCGv t1)
3741{
3742 TCGv rd, tmp;
3743
7d1b0095
PM		 3744 rd = tcg_temp_new_i32();
3745 tmp = tcg_temp_new_i32();
19457615
FN		 3746
3747 tcg_gen_shli_i32(rd, t0, 8);
3748 tcg_gen_andi_i32(rd, rd, 0xff00ff00);
3749 tcg_gen_andi_i32(tmp, t1, 0x00ff00ff);
3750 tcg_gen_or_i32(rd, rd, tmp);
3751
3752 tcg_gen_shri_i32(t1, t1, 8);
3753 tcg_gen_andi_i32(t1, t1, 0x00ff00ff);
3754 tcg_gen_andi_i32(tmp, t0, 0xff00ff00);
3755 tcg_gen_or_i32(t1, t1, tmp);
3756 tcg_gen_mov_i32(t0, rd);
3757
7d1b0095
PM		 3758 tcg_temp_free_i32(tmp);
3759 tcg_temp_free_i32(rd);
19457615
FN		 3760}
3761
3762static void gen_neon_trn_u16(TCGv t0, TCGv t1)
3763{
3764 TCGv rd, tmp;
3765
7d1b0095
PM		 3766 rd = tcg_temp_new_i32();
3767 tmp = tcg_temp_new_i32();
19457615
FN		 3768
3769 tcg_gen_shli_i32(rd, t0, 16);
3770 tcg_gen_andi_i32(tmp, t1, 0xffff);
3771 tcg_gen_or_i32(rd, rd, tmp);
3772 tcg_gen_shri_i32(t1, t1, 16);
3773 tcg_gen_andi_i32(tmp, t0, 0xffff0000);
3774 tcg_gen_or_i32(t1, t1, tmp);
3775 tcg_gen_mov_i32(t0, rd);
3776
7d1b0095
PM		 3777 tcg_temp_free_i32(tmp);
3778 tcg_temp_free_i32(rd);
19457615
FN		 3779}
3780
3781
9ee6e8bb
PB		 3782static struct {
3783 int nregs;
3784 int interleave;
3785 int spacing;
3786} neon_ls_element_type[11] = {
3787 {4, 4, 1},
3788 {4, 4, 2},
3789 {4, 1, 1},
3790 {4, 2, 1},
3791 {3, 3, 1},
3792 {3, 3, 2},
3793 {3, 1, 1},
3794 {1, 1, 1},
3795 {2, 2, 1},
3796 {2, 2, 2},
3797 {2, 1, 1}
3798};
3799
3800/* Translate a NEON load/store element instruction. Return nonzero if the
3801 instruction is invalid. */
3802static int disas_neon_ls_insn(CPUState * env, DisasContext *s, uint32_t insn)
3803{
3804 int rd, rn, rm;
3805 int op;
3806 int nregs;
3807 int interleave;
84496233 3808 int spacing;
9ee6e8bb
PB		 3809 int stride;
3810 int size;
3811 int reg;
3812 int pass;
3813 int load;
3814 int shift;
9ee6e8bb 3815 int n;
1b2b1e54 3816 TCGv addr;
b0109805 3817 TCGv tmp;
8f8e3aa4 3818 TCGv tmp2;
84496233 3819 TCGv_i64 tmp64;
9ee6e8bb 3820
5df8bac1 3821 if (!s->vfp_enabled)
9ee6e8bb
PB		 3822 return 1;
3823 VFP_DREG_D(rd, insn);
3824 rn = (insn >> 16) & 0xf;
3825 rm = insn & 0xf;
3826 load = (insn & (1 << 21)) != 0;
3827 if ((insn & (1 << 23)) == 0) {
3828 /* Load store all elements. */
3829 op = (insn >> 8) & 0xf;
3830 size = (insn >> 6) & 3;
84496233 3831 if (op > 10)
9ee6e8bb
PB		 3832 return 1;
3833 nregs = neon_ls_element_type[op].nregs;
3834 interleave = neon_ls_element_type[op].interleave;
84496233
JR		 3835 spacing = neon_ls_element_type[op].spacing;
3836 if (size == 3 && (interleave | spacing) != 1)
3837 return 1;
e318a60b 3838 addr = tcg_temp_new_i32();
dcc65026 3839 load_reg_var(s, addr, rn);
9ee6e8bb
PB		 3840 stride = (1 << size) * interleave;
3841 for (reg = 0; reg < nregs; reg++) {
3842 if (interleave > 2 || (interleave == 2 && nregs == 2)) {
dcc65026
AJ		 3843 load_reg_var(s, addr, rn);
3844 tcg_gen_addi_i32(addr, addr, (1 << size) * reg);
9ee6e8bb 3845 } else if (interleave == 2 && nregs == 4 && reg == 2) {
dcc65026
AJ		 3846 load_reg_var(s, addr, rn);
3847 tcg_gen_addi_i32(addr, addr, 1 << size);
9ee6e8bb 3848 }
84496233
JR		 3849 if (size == 3) {
3850 if (load) {
3851 tmp64 = gen_ld64(addr, IS_USER(s));
3852 neon_store_reg64(tmp64, rd);
3853 tcg_temp_free_i64(tmp64);
3854 } else {
3855 tmp64 = tcg_temp_new_i64();
3856 neon_load_reg64(tmp64, rd);
3857 gen_st64(tmp64, addr, IS_USER(s));
3858 }
3859 tcg_gen_addi_i32(addr, addr, stride);
3860 } else {
3861 for (pass = 0; pass < 2; pass++) {
3862 if (size == 2) {
3863 if (load) {
3864 tmp = gen_ld32(addr, IS_USER(s));
3865 neon_store_reg(rd, pass, tmp);
3866 } else {
3867 tmp = neon_load_reg(rd, pass);
3868 gen_st32(tmp, addr, IS_USER(s));
3869 }
1b2b1e54 3870 tcg_gen_addi_i32(addr, addr, stride);
84496233
JR		 3871 } else if (size == 1) {
3872 if (load) {
3873 tmp = gen_ld16u(addr, IS_USER(s));
3874 tcg_gen_addi_i32(addr, addr, stride);
3875 tmp2 = gen_ld16u(addr, IS_USER(s));
3876 tcg_gen_addi_i32(addr, addr, stride);
41ba8341
PB		 3877 tcg_gen_shli_i32(tmp2, tmp2, 16);
3878 tcg_gen_or_i32(tmp, tmp, tmp2);
7d1b0095 3879 tcg_temp_free_i32(tmp2);
84496233
JR		 3880 neon_store_reg(rd, pass, tmp);
3881 } else {
3882 tmp = neon_load_reg(rd, pass);
7d1b0095 3883 tmp2 = tcg_temp_new_i32();
84496233
JR		 3884 tcg_gen_shri_i32(tmp2, tmp, 16);
3885 gen_st16(tmp, addr, IS_USER(s));
3886 tcg_gen_addi_i32(addr, addr, stride);
3887 gen_st16(tmp2, addr, IS_USER(s));
1b2b1e54 3888 tcg_gen_addi_i32(addr, addr, stride);
9ee6e8bb 3889 }
84496233
JR		 3890 } else /* size == 0 */ {
3891 if (load) {
3892 TCGV_UNUSED(tmp2);
3893 for (n = 0; n < 4; n++) {
3894 tmp = gen_ld8u(addr, IS_USER(s));
3895 tcg_gen_addi_i32(addr, addr, stride);
3896 if (n == 0) {
3897 tmp2 = tmp;
3898 } else {
41ba8341
PB		 3899 tcg_gen_shli_i32(tmp, tmp, n * 8);
3900 tcg_gen_or_i32(tmp2, tmp2, tmp);
7d1b0095 3901 tcg_temp_free_i32(tmp);
84496233 3902 }
9ee6e8bb 3903 }
84496233
JR		 3904 neon_store_reg(rd, pass, tmp2);
3905 } else {
3906 tmp2 = neon_load_reg(rd, pass);
3907 for (n = 0; n < 4; n++) {
7d1b0095 3908 tmp = tcg_temp_new_i32();
84496233
JR		 3909 if (n == 0) {
3910 tcg_gen_mov_i32(tmp, tmp2);
3911 } else {
3912 tcg_gen_shri_i32(tmp, tmp2, n * 8);
3913 }
3914 gen_st8(tmp, addr, IS_USER(s));
3915 tcg_gen_addi_i32(addr, addr, stride);
3916 }
7d1b0095 3917 tcg_temp_free_i32(tmp2);
9ee6e8bb
PB		 3918 }
3919 }
3920 }
3921 }
84496233 3922 rd += spacing;
9ee6e8bb 3923 }
e318a60b 3924 tcg_temp_free_i32(addr);
9ee6e8bb
PB		 3925 stride = nregs * 8;
3926 } else {
3927 size = (insn >> 10) & 3;
3928 if (size == 3) {
3929 /* Load single element to all lanes. */
8e18cde3
PM		 3930 int a = (insn >> 4) & 1;
3931 if (!load) {
9ee6e8bb 3932 return 1;
8e18cde3 3933 }
9ee6e8bb
PB		 3934 size = (insn >> 6) & 3;
3935 nregs = ((insn >> 8) & 3) + 1;
8e18cde3
PM		 3936
3937 if (size == 3) {
3938 if (nregs != 4 || a == 0) {
9ee6e8bb 3939 return 1;
99c475ab 3940 }
8e18cde3
PM		 3941 /* For VLD4 size==3 a == 1 means 32 bits at 16 byte alignment */
3942 size = 2;
3943 }
3944 if (nregs == 1 && a == 1 && size == 0) {
3945 return 1;
3946 }
3947 if (nregs == 3 && a == 1) {
3948 return 1;
3949 }
e318a60b 3950 addr = tcg_temp_new_i32();
8e18cde3
PM		 3951 load_reg_var(s, addr, rn);
3952 if (nregs == 1) {
3953 /* VLD1 to all lanes: bit 5 indicates how many Dregs to write */
3954 tmp = gen_load_and_replicate(s, addr, size);
3955 tcg_gen_st_i32(tmp, cpu_env, neon_reg_offset(rd, 0));
3956 tcg_gen_st_i32(tmp, cpu_env, neon_reg_offset(rd, 1));
3957 if (insn & (1 << 5)) {
3958 tcg_gen_st_i32(tmp, cpu_env, neon_reg_offset(rd + 1, 0));
3959 tcg_gen_st_i32(tmp, cpu_env, neon_reg_offset(rd + 1, 1));
3960 }
3961 tcg_temp_free_i32(tmp);
3962 } else {
3963 /* VLD2/3/4 to all lanes: bit 5 indicates register stride */
3964 stride = (insn & (1 << 5)) ? 2 : 1;
3965 for (reg = 0; reg < nregs; reg++) {
3966 tmp = gen_load_and_replicate(s, addr, size);
3967 tcg_gen_st_i32(tmp, cpu_env, neon_reg_offset(rd, 0));
3968 tcg_gen_st_i32(tmp, cpu_env, neon_reg_offset(rd, 1));
3969 tcg_temp_free_i32(tmp);
3970 tcg_gen_addi_i32(addr, addr, 1 << size);
3971 rd += stride;
3972 }
9ee6e8bb 3973 }
e318a60b 3974 tcg_temp_free_i32(addr);
9ee6e8bb
PB		 3975 stride = (1 << size) * nregs;
3976 } else {
3977 /* Single element. */
3978 pass = (insn >> 7) & 1;
3979 switch (size) {
3980 case 0:
3981 shift = ((insn >> 5) & 3) * 8;
9ee6e8bb
PB		 3982 stride = 1;
3983 break;
3984 case 1:
3985 shift = ((insn >> 6) & 1) * 16;
9ee6e8bb
PB		 3986 stride = (insn & (1 << 5)) ? 2 : 1;
3987 break;
3988 case 2:
3989 shift = 0;
9ee6e8bb
PB		 3990 stride = (insn & (1 << 6)) ? 2 : 1;
3991 break;
3992 default:
3993 abort();
3994 }
3995 nregs = ((insn >> 8) & 3) + 1;
e318a60b 3996 addr = tcg_temp_new_i32();
dcc65026 3997 load_reg_var(s, addr, rn);
9ee6e8bb
PB		 3998 for (reg = 0; reg < nregs; reg++) {
3999 if (load) {
9ee6e8bb
PB		 4000 switch (size) {
4001 case 0:
1b2b1e54 4002 tmp = gen_ld8u(addr, IS_USER(s));
9ee6e8bb
PB		 4003 break;
4004 case 1:
1b2b1e54 4005 tmp = gen_ld16u(addr, IS_USER(s));
9ee6e8bb
PB		 4006 break;
4007 case 2:
1b2b1e54 4008 tmp = gen_ld32(addr, IS_USER(s));
9ee6e8bb 4009 break;
a50f5b91
PB		 4010 default: /* Avoid compiler warnings. */
4011 abort();
9ee6e8bb
PB		 4012 }
4013 if (size != 2) {
8f8e3aa4
PB		 4014 tmp2 = neon_load_reg(rd, pass);
4015 gen_bfi(tmp, tmp2, tmp, shift, size ? 0xffff : 0xff);
7d1b0095 4016 tcg_temp_free_i32(tmp2);
9ee6e8bb 4017 }
8f8e3aa4 4018 neon_store_reg(rd, pass, tmp);
9ee6e8bb 4019 } else { /* Store */
8f8e3aa4
PB		 4020 tmp = neon_load_reg(rd, pass);
4021 if (shift)
4022 tcg_gen_shri_i32(tmp, tmp, shift);
9ee6e8bb
PB		 4023 switch (size) {
4024 case 0:
1b2b1e54 4025 gen_st8(tmp, addr, IS_USER(s));
9ee6e8bb
PB		 4026 break;
4027 case 1:
1b2b1e54 4028 gen_st16(tmp, addr, IS_USER(s));
9ee6e8bb
PB		 4029 break;
4030 case 2:
1b2b1e54 4031 gen_st32(tmp, addr, IS_USER(s));
9ee6e8bb 4032 break;
99c475ab 4033 }
99c475ab 4034 }
9ee6e8bb 4035 rd += stride;
1b2b1e54 4036 tcg_gen_addi_i32(addr, addr, 1 << size);
99c475ab 4037 }
e318a60b 4038 tcg_temp_free_i32(addr);
9ee6e8bb 4039 stride = nregs * (1 << size);
99c475ab 4040 }
9ee6e8bb
PB		 4041 }
4042 if (rm != 15) {
b26eefb6
PB		 4043 TCGv base;
4044
4045 base = load_reg(s, rn);
9ee6e8bb 4046 if (rm == 13) {
b26eefb6 4047 tcg_gen_addi_i32(base, base, stride);
9ee6e8bb 4048 } else {
b26eefb6
PB		 4049 TCGv index;
4050 index = load_reg(s, rm);
4051 tcg_gen_add_i32(base, base, index);
7d1b0095 4052 tcg_temp_free_i32(index);
9ee6e8bb 4053 }
b26eefb6 4054 store_reg(s, rn, base);
9ee6e8bb
PB		 4055 }
4056 return 0;
4057}
3b46e624 4058
8f8e3aa4
PB		 4059/* Bitwise select. dest = c ? t : f. Clobbers T and F. */
4060static void gen_neon_bsl(TCGv dest, TCGv t, TCGv f, TCGv c)
4061{
4062 tcg_gen_and_i32(t, t, c);
f669df27 4063 tcg_gen_andc_i32(f, f, c);
8f8e3aa4
PB		 4064 tcg_gen_or_i32(dest, t, f);
4065}
4066
a7812ae4 4067static inline void gen_neon_narrow(int size, TCGv dest, TCGv_i64 src)
ad69471c
PB		 4068{
4069 switch (size) {
4070 case 0: gen_helper_neon_narrow_u8(dest, src); break;
4071 case 1: gen_helper_neon_narrow_u16(dest, src); break;
4072 case 2: tcg_gen_trunc_i64_i32(dest, src); break;
4073 default: abort();
4074 }
4075}
4076
a7812ae4 4077static inline void gen_neon_narrow_sats(int size, TCGv dest, TCGv_i64 src)
ad69471c
PB		 4078{
4079 switch (size) {
2a3f75b4
PM		 4080 case 0: gen_helper_neon_narrow_sat_s8(dest, src); break;
4081 case 1: gen_helper_neon_narrow_sat_s16(dest, src); break;
4082 case 2: gen_helper_neon_narrow_sat_s32(dest, src); break;
ad69471c
PB		 4083 default: abort();
4084 }
4085}
4086
a7812ae4 4087static inline void gen_neon_narrow_satu(int size, TCGv dest, TCGv_i64 src)
ad69471c
PB		 4088{
4089 switch (size) {
2a3f75b4
PM		 4090 case 0: gen_helper_neon_narrow_sat_u8(dest, src); break;
4091 case 1: gen_helper_neon_narrow_sat_u16(dest, src); break;
4092 case 2: gen_helper_neon_narrow_sat_u32(dest, src); break;
ad69471c
PB		 4093 default: abort();
4094 }
4095}
4096
af1bbf30
JR		 4097static inline void gen_neon_unarrow_sats(int size, TCGv dest, TCGv_i64 src)
4098{
4099 switch (size) {
2a3f75b4
PM		 4100 case 0: gen_helper_neon_unarrow_sat8(dest, src); break;
4101 case 1: gen_helper_neon_unarrow_sat16(dest, src); break;
4102 case 2: gen_helper_neon_unarrow_sat32(dest, src); break;
af1bbf30
JR		 4103 default: abort();
4104 }
4105}
4106
ad69471c
PB		 4107static inline void gen_neon_shift_narrow(int size, TCGv var, TCGv shift,
4108 int q, int u)
4109{
4110 if (q) {
4111 if (u) {
4112 switch (size) {
4113 case 1: gen_helper_neon_rshl_u16(var, var, shift); break;
4114 case 2: gen_helper_neon_rshl_u32(var, var, shift); break;
4115 default: abort();
4116 }
4117 } else {
4118 switch (size) {
4119 case 1: gen_helper_neon_rshl_s16(var, var, shift); break;
4120 case 2: gen_helper_neon_rshl_s32(var, var, shift); break;
4121 default: abort();
4122 }
4123 }
4124 } else {
4125 if (u) {
4126 switch (size) {
b408a9b0
CL		 4127 case 1: gen_helper_neon_shl_u16(var, var, shift); break;
4128 case 2: gen_helper_neon_shl_u32(var, var, shift); break;
ad69471c
PB		 4129 default: abort();
4130 }
4131 } else {
4132 switch (size) {
4133 case 1: gen_helper_neon_shl_s16(var, var, shift); break;
4134 case 2: gen_helper_neon_shl_s32(var, var, shift); break;
4135 default: abort();
4136 }
4137 }
4138 }
4139}
4140
a7812ae4 4141static inline void gen_neon_widen(TCGv_i64 dest, TCGv src, int size, int u)
ad69471c
PB		 4142{
4143 if (u) {
4144 switch (size) {
4145 case 0: gen_helper_neon_widen_u8(dest, src); break;
4146 case 1: gen_helper_neon_widen_u16(dest, src); break;
4147 case 2: tcg_gen_extu_i32_i64(dest, src); break;
4148 default: abort();
4149 }
4150 } else {
4151 switch (size) {
4152 case 0: gen_helper_neon_widen_s8(dest, src); break;
4153 case 1: gen_helper_neon_widen_s16(dest, src); break;
4154 case 2: tcg_gen_ext_i32_i64(dest, src); break;
4155 default: abort();
4156 }
4157 }
7d1b0095 4158 tcg_temp_free_i32(src);
ad69471c
PB		 4159}
4160
4161static inline void gen_neon_addl(int size)
4162{
4163 switch (size) {
4164 case 0: gen_helper_neon_addl_u16(CPU_V001); break;
4165 case 1: gen_helper_neon_addl_u32(CPU_V001); break;
4166 case 2: tcg_gen_add_i64(CPU_V001); break;
4167 default: abort();
4168 }
4169}
4170
4171static inline void gen_neon_subl(int size)
4172{
4173 switch (size) {
4174 case 0: gen_helper_neon_subl_u16(CPU_V001); break;
4175 case 1: gen_helper_neon_subl_u32(CPU_V001); break;
4176 case 2: tcg_gen_sub_i64(CPU_V001); break;
4177 default: abort();
4178 }
4179}
4180
a7812ae4 4181static inline void gen_neon_negl(TCGv_i64 var, int size)
ad69471c
PB		 4182{
4183 switch (size) {
4184 case 0: gen_helper_neon_negl_u16(var, var); break;
4185 case 1: gen_helper_neon_negl_u32(var, var); break;
4186 case 2: gen_helper_neon_negl_u64(var, var); break;
4187 default: abort();
4188 }
4189}
4190
a7812ae4 4191static inline void gen_neon_addl_saturate(TCGv_i64 op0, TCGv_i64 op1, int size)
ad69471c
PB		 4192{
4193 switch (size) {
2a3f75b4
PM		 4194 case 1: gen_helper_neon_addl_saturate_s32(op0, op0, op1); break;
4195 case 2: gen_helper_neon_addl_saturate_s64(op0, op0, op1); break;
ad69471c
PB		 4196 default: abort();
4197 }
4198}
4199
a7812ae4 4200static inline void gen_neon_mull(TCGv_i64 dest, TCGv a, TCGv b, int size, int u)
ad69471c 4201{
a7812ae4 4202 TCGv_i64 tmp;
ad69471c
PB		 4203
4204 switch ((size << 1) | u) {
4205 case 0: gen_helper_neon_mull_s8(dest, a, b); break;
4206 case 1: gen_helper_neon_mull_u8(dest, a, b); break;
4207 case 2: gen_helper_neon_mull_s16(dest, a, b); break;
4208 case 3: gen_helper_neon_mull_u16(dest, a, b); break;
4209 case 4:
4210 tmp = gen_muls_i64_i32(a, b);
4211 tcg_gen_mov_i64(dest, tmp);
7d2aabe2 4212 tcg_temp_free_i64(tmp);
ad69471c
PB		 4213 break;
4214 case 5:
4215 tmp = gen_mulu_i64_i32(a, b);
4216 tcg_gen_mov_i64(dest, tmp);
7d2aabe2 4217 tcg_temp_free_i64(tmp);
ad69471c
PB		 4218 break;
4219 default: abort();
4220 }
c6067f04
CL		 4221
4222 /* gen_helper_neon_mull_[su]{8|16} do not free their parameters.
4223 Don't forget to clean them now. */
4224 if (size < 2) {
7d1b0095
PM		 4225 tcg_temp_free_i32(a);
4226 tcg_temp_free_i32(b);
c6067f04 4227 }
ad69471c
PB		 4228}
4229
c33171c7
PM		 4230static void gen_neon_narrow_op(int op, int u, int size, TCGv dest, TCGv_i64 src)
4231{
4232 if (op) {
4233 if (u) {
4234 gen_neon_unarrow_sats(size, dest, src);
4235 } else {
4236 gen_neon_narrow(size, dest, src);
4237 }
4238 } else {
4239 if (u) {
4240 gen_neon_narrow_satu(size, dest, src);
4241 } else {
4242 gen_neon_narrow_sats(size, dest, src);
4243 }
4244 }
4245}
4246
62698be3
PM		 4247/* Symbolic constants for op fields for Neon 3-register same-length.
4248 * The values correspond to bits [11:8,4]; see the ARM ARM DDI0406B
4249 * table A7-9.
4250 */
4251#define NEON_3R_VHADD 0
4252#define NEON_3R_VQADD 1
4253#define NEON_3R_VRHADD 2
4254#define NEON_3R_LOGIC 3 /* VAND,VBIC,VORR,VMOV,VORN,VEOR,VBIF,VBIT,VBSL */
4255#define NEON_3R_VHSUB 4
4256#define NEON_3R_VQSUB 5
4257#define NEON_3R_VCGT 6
4258#define NEON_3R_VCGE 7
4259#define NEON_3R_VSHL 8
4260#define NEON_3R_VQSHL 9
4261#define NEON_3R_VRSHL 10
4262#define NEON_3R_VQRSHL 11
4263#define NEON_3R_VMAX 12
4264#define NEON_3R_VMIN 13
4265#define NEON_3R_VABD 14
4266#define NEON_3R_VABA 15
4267#define NEON_3R_VADD_VSUB 16
4268#define NEON_3R_VTST_VCEQ 17
4269#define NEON_3R_VML 18 /* VMLA, VMLAL, VMLS, VMLSL */
4270#define NEON_3R_VMUL 19
4271#define NEON_3R_VPMAX 20
4272#define NEON_3R_VPMIN 21
4273#define NEON_3R_VQDMULH_VQRDMULH 22
4274#define NEON_3R_VPADD 23
4275#define NEON_3R_FLOAT_ARITH 26 /* float VADD, VSUB, VPADD, VABD */
4276#define NEON_3R_FLOAT_MULTIPLY 27 /* float VMLA, VMLS, VMUL */
4277#define NEON_3R_FLOAT_CMP 28 /* float VCEQ, VCGE, VCGT */
4278#define NEON_3R_FLOAT_ACMP 29 /* float VACGE, VACGT, VACLE, VACLT */
4279#define NEON_3R_FLOAT_MINMAX 30 /* float VMIN, VMAX */
4280#define NEON_3R_VRECPS_VRSQRTS 31 /* float VRECPS, VRSQRTS */
4281
4282static const uint8_t neon_3r_sizes[] = {
4283 [NEON_3R_VHADD] = 0x7,
4284 [NEON_3R_VQADD] = 0xf,
4285 [NEON_3R_VRHADD] = 0x7,
4286 [NEON_3R_LOGIC] = 0xf, /* size field encodes op type */
4287 [NEON_3R_VHSUB] = 0x7,
4288 [NEON_3R_VQSUB] = 0xf,
4289 [NEON_3R_VCGT] = 0x7,
4290 [NEON_3R_VCGE] = 0x7,
4291 [NEON_3R_VSHL] = 0xf,
4292 [NEON_3R_VQSHL] = 0xf,
4293 [NEON_3R_VRSHL] = 0xf,
4294 [NEON_3R_VQRSHL] = 0xf,
4295 [NEON_3R_VMAX] = 0x7,
4296 [NEON_3R_VMIN] = 0x7,
4297 [NEON_3R_VABD] = 0x7,
4298 [NEON_3R_VABA] = 0x7,
4299 [NEON_3R_VADD_VSUB] = 0xf,
4300 [NEON_3R_VTST_VCEQ] = 0x7,
4301 [NEON_3R_VML] = 0x7,
4302 [NEON_3R_VMUL] = 0x7,
4303 [NEON_3R_VPMAX] = 0x7,
4304 [NEON_3R_VPMIN] = 0x7,
4305 [NEON_3R_VQDMULH_VQRDMULH] = 0x6,
4306 [NEON_3R_VPADD] = 0x7,
4307 [NEON_3R_FLOAT_ARITH] = 0x5, /* size bit 1 encodes op */
4308 [NEON_3R_FLOAT_MULTIPLY] = 0x5, /* size bit 1 encodes op */
4309 [NEON_3R_FLOAT_CMP] = 0x5, /* size bit 1 encodes op */
4310 [NEON_3R_FLOAT_ACMP] = 0x5, /* size bit 1 encodes op */
4311 [NEON_3R_FLOAT_MINMAX] = 0x5, /* size bit 1 encodes op */
4312 [NEON_3R_VRECPS_VRSQRTS] = 0x5, /* size bit 1 encodes op */
4313};
4314
9ee6e8bb
PB		 4315/* Translate a NEON data processing instruction. Return nonzero if the
4316 instruction is invalid.
ad69471c
PB		 4317 We process data in a mixture of 32-bit and 64-bit chunks.
4318 Mostly we use 32-bit chunks so we can use normal scalar instructions. */
2c0262af 4319
9ee6e8bb
PB		 4320static int disas_neon_data_insn(CPUState * env, DisasContext *s, uint32_t insn)
4321{
4322 int op;
4323 int q;
4324 int rd, rn, rm;
4325 int size;
4326 int shift;
4327 int pass;
4328 int count;
4329 int pairwise;
4330 int u;
4331 int n;
ca9a32e4 4332 uint32_t imm, mask;
b75263d6 4333 TCGv tmp, tmp2, tmp3, tmp4, tmp5;
a7812ae4 4334 TCGv_i64 tmp64;
9ee6e8bb 4335
5df8bac1 4336 if (!s->vfp_enabled)
9ee6e8bb
PB		 4337 return 1;
4338 q = (insn & (1 << 6)) != 0;
4339 u = (insn >> 24) & 1;
4340 VFP_DREG_D(rd, insn);
4341 VFP_DREG_N(rn, insn);
4342 VFP_DREG_M(rm, insn);
4343 size = (insn >> 20) & 3;
4344 if ((insn & (1 << 23)) == 0) {
4345 /* Three register same length. */
4346 op = ((insn >> 7) & 0x1e) | ((insn >> 4) & 1);
62698be3
PM		 4347 /* Catch invalid op and bad size combinations: UNDEF */
4348 if ((neon_3r_sizes[op] & (1 << size)) == 0) {
4349 return 1;
4350 }
25f84f79
PM		 4351 /* All insns of this form UNDEF for either this condition or the
4352 * superset of cases "Q==1"; we catch the latter later.
4353 */
4354 if (q && ((rd | rn | rm) & 1)) {
4355 return 1;
4356 }
62698be3
PM		 4357 if (size == 3 && op != NEON_3R_LOGIC) {
4358 /* 64-bit element instructions. */
9ee6e8bb 4359 for (pass = 0; pass < (q ? 2 : 1); pass++) {
ad69471c
PB		 4360 neon_load_reg64(cpu_V0, rn + pass);
4361 neon_load_reg64(cpu_V1, rm + pass);
9ee6e8bb 4362 switch (op) {
62698be3 4363 case NEON_3R_VQADD:
9ee6e8bb 4364 if (u) {
2a3f75b4 4365 gen_helper_neon_qadd_u64(cpu_V0, cpu_V0, cpu_V1);
2c0262af 4366 } else {
2a3f75b4 4367 gen_helper_neon_qadd_s64(cpu_V0, cpu_V0, cpu_V1);
2c0262af 4368 }
9ee6e8bb 4369 break;
62698be3 4370 case NEON_3R_VQSUB:
9ee6e8bb 4371 if (u) {
2a3f75b4 4372 gen_helper_neon_qsub_u64(cpu_V0, cpu_V0, cpu_V1);
ad69471c 4373 } else {
2a3f75b4 4374 gen_helper_neon_qsub_s64(cpu_V0, cpu_V0, cpu_V1);
ad69471c
PB		 4375 }
4376 break;
62698be3 4377 case NEON_3R_VSHL:
ad69471c
PB		 4378 if (u) {
4379 gen_helper_neon_shl_u64(cpu_V0, cpu_V1, cpu_V0);
4380 } else {
4381 gen_helper_neon_shl_s64(cpu_V0, cpu_V1, cpu_V0);
4382 }
4383 break;
62698be3 4384 case NEON_3R_VQSHL:
ad69471c 4385 if (u) {
2a3f75b4 4386 gen_helper_neon_qshl_u64(cpu_V0, cpu_V1, cpu_V0);
ad69471c 4387 } else {
2a3f75b4 4388 gen_helper_neon_qshl_s64(cpu_V0, cpu_V1, cpu_V0);
ad69471c
PB		 4389 }
4390 break;
62698be3 4391 case NEON_3R_VRSHL:
ad69471c
PB		 4392 if (u) {
4393 gen_helper_neon_rshl_u64(cpu_V0, cpu_V1, cpu_V0);
1e8d4eec 4394 } else {
ad69471c
PB		 4395 gen_helper_neon_rshl_s64(cpu_V0, cpu_V1, cpu_V0);
4396 }
4397 break;
62698be3 4398 case NEON_3R_VQRSHL:
ad69471c 4399 if (u) {
2a3f75b4 4400 gen_helper_neon_qrshl_u64(cpu_V0, cpu_V1, cpu_V0);
ad69471c 4401 } else {
2a3f75b4 4402 gen_helper_neon_qrshl_s64(cpu_V0, cpu_V1, cpu_V0);
1e8d4eec 4403 }
9ee6e8bb 4404 break;
62698be3 4405 case NEON_3R_VADD_VSUB:
9ee6e8bb 4406 if (u) {
ad69471c 4407 tcg_gen_sub_i64(CPU_V001);
9ee6e8bb 4408 } else {
ad69471c 4409 tcg_gen_add_i64(CPU_V001);
9ee6e8bb
PB		 4410 }
4411 break;
4412 default:
4413 abort();
2c0262af 4414 }
ad69471c 4415 neon_store_reg64(cpu_V0, rd + pass);
2c0262af 4416 }
9ee6e8bb 4417 return 0;
2c0262af 4418 }
25f84f79 4419 pairwise = 0;
9ee6e8bb 4420 switch (op) {
62698be3
PM		 4421 case NEON_3R_VSHL:
4422 case NEON_3R_VQSHL:
4423 case NEON_3R_VRSHL:
4424 case NEON_3R_VQRSHL:
9ee6e8bb 4425 {
ad69471c
PB		 4426 int rtmp;
4427 /* Shift instruction operands are reversed. */
4428 rtmp = rn;
9ee6e8bb 4429 rn = rm;
ad69471c 4430 rm = rtmp;
9ee6e8bb 4431 }
2c0262af 4432 break;
25f84f79
PM		 4433 case NEON_3R_VPADD:
4434 if (u) {
4435 return 1;
4436 }
4437 /* Fall through */
62698be3
PM		 4438 case NEON_3R_VPMAX:
4439 case NEON_3R_VPMIN:
9ee6e8bb 4440 pairwise = 1;
2c0262af 4441 break;
25f84f79
PM		 4442 case NEON_3R_FLOAT_ARITH:
4443 pairwise = (u && size < 2); /* if VPADD (float) */
4444 break;
4445 case NEON_3R_FLOAT_MINMAX:
4446 pairwise = u; /* if VPMIN/VPMAX (float) */
4447 break;
4448 case NEON_3R_FLOAT_CMP:
4449 if (!u && size) {
4450 /* no encoding for U=0 C=1x */
4451 return 1;
4452 }
4453 break;
4454 case NEON_3R_FLOAT_ACMP:
4455 if (!u) {
4456 return 1;
4457 }
4458 break;
4459 case NEON_3R_VRECPS_VRSQRTS:
4460 if (u) {
4461 return 1;
4462 }
2c0262af 4463 break;
25f84f79
PM		 4464 case NEON_3R_VMUL:
4465 if (u && (size != 0)) {
4466 /* UNDEF on invalid size for polynomial subcase */
4467 return 1;
4468 }
2c0262af 4469 break;
9ee6e8bb 4470 default:
2c0262af 4471 break;
9ee6e8bb 4472 }
dd8fbd78 4473
25f84f79
PM		 4474 if (pairwise && q) {
4475 /* All the pairwise insns UNDEF if Q is set */
4476 return 1;
4477 }
4478
9ee6e8bb
PB		 4479 for (pass = 0; pass < (q ? 4 : 2); pass++) {
4480
4481 if (pairwise) {
4482 /* Pairwise. */
4483 if (q)
4484 n = (pass & 1) * 2;
2c0262af 4485 else
9ee6e8bb
PB		 4486 n = 0;
4487 if (pass < q + 1) {
dd8fbd78
FN		 4488 tmp = neon_load_reg(rn, n);
4489 tmp2 = neon_load_reg(rn, n + 1);
9ee6e8bb 4490 } else {
dd8fbd78
FN		 4491 tmp = neon_load_reg(rm, n);
4492 tmp2 = neon_load_reg(rm, n + 1);
9ee6e8bb
PB		 4493 }
4494 } else {
4495 /* Elementwise. */
dd8fbd78
FN		 4496 tmp = neon_load_reg(rn, pass);
4497 tmp2 = neon_load_reg(rm, pass);
9ee6e8bb
PB		 4498 }
4499 switch (op) {
62698be3 4500 case NEON_3R_VHADD:
9ee6e8bb
PB		 4501 GEN_NEON_INTEGER_OP(hadd);
4502 break;
62698be3 4503 case NEON_3R_VQADD:
2a3f75b4 4504 GEN_NEON_INTEGER_OP(qadd);
2c0262af 4505 break;
62698be3 4506 case NEON_3R_VRHADD:
9ee6e8bb 4507 GEN_NEON_INTEGER_OP(rhadd);
2c0262af 4508 break;
62698be3 4509 case NEON_3R_LOGIC: /* Logic ops. */
9ee6e8bb
PB		 4510 switch ((u << 2) | size) {
4511 case 0: /* VAND */
dd8fbd78 4512 tcg_gen_and_i32(tmp, tmp, tmp2);
9ee6e8bb
PB		 4513 break;
4514 case 1: /* BIC */
f669df27 4515 tcg_gen_andc_i32(tmp, tmp, tmp2);
9ee6e8bb
PB		 4516 break;
4517 case 2: /* VORR */
dd8fbd78 4518 tcg_gen_or_i32(tmp, tmp, tmp2);
9ee6e8bb
PB		 4519 break;
4520 case 3: /* VORN */
f669df27 4521 tcg_gen_orc_i32(tmp, tmp, tmp2);
9ee6e8bb
PB		 4522 break;
4523 case 4: /* VEOR */
dd8fbd78 4524 tcg_gen_xor_i32(tmp, tmp, tmp2);
9ee6e8bb
PB		 4525 break;
4526 case 5: /* VBSL */
dd8fbd78
FN		 4527 tmp3 = neon_load_reg(rd, pass);
4528 gen_neon_bsl(tmp, tmp, tmp2, tmp3);
7d1b0095 4529 tcg_temp_free_i32(tmp3);
9ee6e8bb
PB		 4530 break;
4531 case 6: /* VBIT */
dd8fbd78
FN		 4532 tmp3 = neon_load_reg(rd, pass);
4533 gen_neon_bsl(tmp, tmp, tmp3, tmp2);
7d1b0095 4534 tcg_temp_free_i32(tmp3);
9ee6e8bb
PB		 4535 break;
4536 case 7: /* VBIF */
dd8fbd78
FN		 4537 tmp3 = neon_load_reg(rd, pass);
4538 gen_neon_bsl(tmp, tmp3, tmp, tmp2);
7d1b0095 4539 tcg_temp_free_i32(tmp3);
9ee6e8bb 4540 break;
2c0262af
FB		 4541 }
4542 break;
62698be3 4543 case NEON_3R_VHSUB:
9ee6e8bb
PB		 4544 GEN_NEON_INTEGER_OP(hsub);
4545 break;
62698be3 4546 case NEON_3R_VQSUB:
2a3f75b4 4547 GEN_NEON_INTEGER_OP(qsub);
2c0262af 4548 break;
62698be3 4549 case NEON_3R_VCGT:
9ee6e8bb
PB		 4550 GEN_NEON_INTEGER_OP(cgt);
4551 break;
62698be3 4552 case NEON_3R_VCGE:
9ee6e8bb
PB		 4553 GEN_NEON_INTEGER_OP(cge);
4554 break;
62698be3 4555 case NEON_3R_VSHL:
ad69471c 4556 GEN_NEON_INTEGER_OP(shl);
2c0262af 4557 break;
62698be3 4558 case NEON_3R_VQSHL:
2a3f75b4 4559 GEN_NEON_INTEGER_OP(qshl);
2c0262af 4560 break;
62698be3 4561 case NEON_3R_VRSHL:
ad69471c 4562 GEN_NEON_INTEGER_OP(rshl);
2c0262af 4563 break;
62698be3 4564 case NEON_3R_VQRSHL:
2a3f75b4 4565 GEN_NEON_INTEGER_OP(qrshl);
9ee6e8bb 4566 break;
62698be3 4567 case NEON_3R_VMAX:
9ee6e8bb
PB		 4568 GEN_NEON_INTEGER_OP(max);
4569 break;
62698be3 4570 case NEON_3R_VMIN:
9ee6e8bb
PB		 4571 GEN_NEON_INTEGER_OP(min);
4572 break;
62698be3 4573 case NEON_3R_VABD:
9ee6e8bb
PB		 4574 GEN_NEON_INTEGER_OP(abd);
4575 break;
62698be3 4576 case NEON_3R_VABA:
9ee6e8bb 4577 GEN_NEON_INTEGER_OP(abd);
7d1b0095 4578 tcg_temp_free_i32(tmp2);
dd8fbd78
FN		 4579 tmp2 = neon_load_reg(rd, pass);
4580 gen_neon_add(size, tmp, tmp2);
9ee6e8bb 4581 break;
62698be3 4582 case NEON_3R_VADD_VSUB:
9ee6e8bb 4583 if (!u) { /* VADD */
62698be3 4584 gen_neon_add(size, tmp, tmp2);
9ee6e8bb
PB		 4585 } else { /* VSUB */
4586 switch (size) {
dd8fbd78
FN		 4587 case 0: gen_helper_neon_sub_u8(tmp, tmp, tmp2); break;
4588 case 1: gen_helper_neon_sub_u16(tmp, tmp, tmp2); break;
4589 case 2: tcg_gen_sub_i32(tmp, tmp, tmp2); break;
62698be3 4590 default: abort();
9ee6e8bb
PB		 4591 }
4592 }
4593 break;
62698be3 4594 case NEON_3R_VTST_VCEQ:
9ee6e8bb
PB		 4595 if (!u) { /* VTST */
4596 switch (size) {
dd8fbd78
FN		 4597 case 0: gen_helper_neon_tst_u8(tmp, tmp, tmp2); break;
4598 case 1: gen_helper_neon_tst_u16(tmp, tmp, tmp2); break;
4599 case 2: gen_helper_neon_tst_u32(tmp, tmp, tmp2); break;
62698be3 4600 default: abort();
9ee6e8bb
PB		 4601 }
4602 } else { /* VCEQ */
4603 switch (size) {
dd8fbd78
FN		 4604 case 0: gen_helper_neon_ceq_u8(tmp, tmp, tmp2); break;
4605 case 1: gen_helper_neon_ceq_u16(tmp, tmp, tmp2); break;
4606 case 2: gen_helper_neon_ceq_u32(tmp, tmp, tmp2); break;
62698be3 4607 default: abort();
9ee6e8bb
PB		 4608 }
4609 }
4610 break;
62698be3 4611 case NEON_3R_VML: /* VMLA, VMLAL, VMLS,VMLSL */
9ee6e8bb 4612 switch (size) {
dd8fbd78
FN		 4613 case 0: gen_helper_neon_mul_u8(tmp, tmp, tmp2); break;
4614 case 1: gen_helper_neon_mul_u16(tmp, tmp, tmp2); break;
4615 case 2: tcg_gen_mul_i32(tmp, tmp, tmp2); break;
62698be3 4616 default: abort();
9ee6e8bb 4617 }
7d1b0095 4618 tcg_temp_free_i32(tmp2);
dd8fbd78 4619 tmp2 = neon_load_reg(rd, pass);
9ee6e8bb 4620 if (u) { /* VMLS */
dd8fbd78 4621 gen_neon_rsb(size, tmp, tmp2);
9ee6e8bb 4622 } else { /* VMLA */
dd8fbd78 4623 gen_neon_add(size, tmp, tmp2);
9ee6e8bb
PB		 4624 }
4625 break;
62698be3 4626 case NEON_3R_VMUL:
9ee6e8bb 4627 if (u) { /* polynomial */
dd8fbd78 4628 gen_helper_neon_mul_p8(tmp, tmp, tmp2);
9ee6e8bb
PB		 4629 } else { /* Integer */
4630 switch (size) {
dd8fbd78
FN		 4631 case 0: gen_helper_neon_mul_u8(tmp, tmp, tmp2); break;
4632 case 1: gen_helper_neon_mul_u16(tmp, tmp, tmp2); break;
4633 case 2: tcg_gen_mul_i32(tmp, tmp, tmp2); break;
62698be3 4634 default: abort();
9ee6e8bb
PB		 4635 }
4636 }
4637 break;
62698be3 4638 case NEON_3R_VPMAX:
9ee6e8bb
PB		 4639 GEN_NEON_INTEGER_OP(pmax);
4640 break;
62698be3 4641 case NEON_3R_VPMIN:
9ee6e8bb
PB		 4642 GEN_NEON_INTEGER_OP(pmin);
4643 break;
62698be3 4644 case NEON_3R_VQDMULH_VQRDMULH: /* Multiply high. */
9ee6e8bb
PB		 4645 if (!u) { /* VQDMULH */
4646 switch (size) {
2a3f75b4
PM		 4647 case 1: gen_helper_neon_qdmulh_s16(tmp, tmp, tmp2); break;
4648 case 2: gen_helper_neon_qdmulh_s32(tmp, tmp, tmp2); break;
62698be3 4649 default: abort();
9ee6e8bb 4650 }
62698be3 4651 } else { /* VQRDMULH */
9ee6e8bb 4652 switch (size) {
2a3f75b4
PM		 4653 case 1: gen_helper_neon_qrdmulh_s16(tmp, tmp, tmp2); break;
4654 case 2: gen_helper_neon_qrdmulh_s32(tmp, tmp, tmp2); break;
62698be3 4655 default: abort();
9ee6e8bb
PB		 4656 }
4657 }
4658 break;
62698be3 4659 case NEON_3R_VPADD:
9ee6e8bb 4660 switch (size) {
dd8fbd78
FN		 4661 case 0: gen_helper_neon_padd_u8(tmp, tmp, tmp2); break;
4662 case 1: gen_helper_neon_padd_u16(tmp, tmp, tmp2); break;
4663 case 2: tcg_gen_add_i32(tmp, tmp, tmp2); break;
62698be3 4664 default: abort();
9ee6e8bb
PB		 4665 }
4666 break;
62698be3 4667 case NEON_3R_FLOAT_ARITH: /* Floating point arithmetic. */
9ee6e8bb
PB		 4668 switch ((u << 2) | size) {
4669 case 0: /* VADD */
dd8fbd78 4670 gen_helper_neon_add_f32(tmp, tmp, tmp2);
9ee6e8bb
PB		 4671 break;
4672 case 2: /* VSUB */
dd8fbd78 4673 gen_helper_neon_sub_f32(tmp, tmp, tmp2);
9ee6e8bb
PB		 4674 break;
4675 case 4: /* VPADD */
dd8fbd78 4676 gen_helper_neon_add_f32(tmp, tmp, tmp2);
9ee6e8bb
PB		 4677 break;
4678 case 6: /* VABD */
dd8fbd78 4679 gen_helper_neon_abd_f32(tmp, tmp, tmp2);
9ee6e8bb
PB		 4680 break;
4681 default:
62698be3 4682 abort();
9ee6e8bb
PB		 4683 }
4684 break;
62698be3 4685 case NEON_3R_FLOAT_MULTIPLY:
dd8fbd78 4686 gen_helper_neon_mul_f32(tmp, tmp, tmp2);
9ee6e8bb 4687 if (!u) {
7d1b0095 4688 tcg_temp_free_i32(tmp2);
dd8fbd78 4689 tmp2 = neon_load_reg(rd, pass);
9ee6e8bb 4690 if (size == 0) {
dd8fbd78 4691 gen_helper_neon_add_f32(tmp, tmp, tmp2);
9ee6e8bb 4692 } else {
dd8fbd78 4693 gen_helper_neon_sub_f32(tmp, tmp2, tmp);
9ee6e8bb
PB		 4694 }
4695 }
4696 break;
62698be3 4697 case NEON_3R_FLOAT_CMP:
9ee6e8bb 4698 if (!u) {
dd8fbd78 4699 gen_helper_neon_ceq_f32(tmp, tmp, tmp2);
b5ff1b31 4700 } else {
9ee6e8bb 4701 if (size == 0)
dd8fbd78 4702 gen_helper_neon_cge_f32(tmp, tmp, tmp2);
9ee6e8bb 4703 else
dd8fbd78 4704 gen_helper_neon_cgt_f32(tmp, tmp, tmp2);
b5ff1b31 4705 }
2c0262af 4706 break;
62698be3 4707 case NEON_3R_FLOAT_ACMP:
9ee6e8bb 4708 if (size == 0)
dd8fbd78 4709 gen_helper_neon_acge_f32(tmp, tmp, tmp2);
9ee6e8bb 4710 else
dd8fbd78 4711 gen_helper_neon_acgt_f32(tmp, tmp, tmp2);
2c0262af 4712 break;
62698be3 4713 case NEON_3R_FLOAT_MINMAX:
9ee6e8bb 4714 if (size == 0)
dd8fbd78 4715 gen_helper_neon_max_f32(tmp, tmp, tmp2);
9ee6e8bb 4716 else
dd8fbd78 4717 gen_helper_neon_min_f32(tmp, tmp, tmp2);
9ee6e8bb 4718 break;
62698be3 4719 case NEON_3R_VRECPS_VRSQRTS:
9ee6e8bb 4720 if (size == 0)
dd8fbd78 4721 gen_helper_recps_f32(tmp, tmp, tmp2, cpu_env);
9ee6e8bb 4722 else
dd8fbd78 4723 gen_helper_rsqrts_f32(tmp, tmp, tmp2, cpu_env);
2c0262af 4724 break;
9ee6e8bb
PB		 4725 default:
4726 abort();
2c0262af 4727 }
7d1b0095 4728 tcg_temp_free_i32(tmp2);
dd8fbd78 4729
9ee6e8bb
PB		 4730 /* Save the result. For elementwise operations we can put it
4731 straight into the destination register. For pairwise operations
4732 we have to be careful to avoid clobbering the source operands. */
4733 if (pairwise && rd == rm) {
dd8fbd78 4734 neon_store_scratch(pass, tmp);
9ee6e8bb 4735 } else {
dd8fbd78 4736 neon_store_reg(rd, pass, tmp);
9ee6e8bb
PB		 4737 }
4738
4739 } /* for pass */
4740 if (pairwise && rd == rm) {
4741 for (pass = 0; pass < (q ? 4 : 2); pass++) {
dd8fbd78
FN		 4742 tmp = neon_load_scratch(pass);
4743 neon_store_reg(rd, pass, tmp);
9ee6e8bb
PB		 4744 }
4745 }
ad69471c 4746 /* End of 3 register same size operations. */
9ee6e8bb
PB		 4747 } else if (insn & (1 << 4)) {
4748 if ((insn & 0x00380080) != 0) {
4749 /* Two registers and shift. */
4750 op = (insn >> 8) & 0xf;
4751 if (insn & (1 << 7)) {
4752 /* 64-bit shift. */
4753 size = 3;
4754 } else {
4755 size = 2;
4756 while ((insn & (1 << (size + 19))) == 0)
4757 size--;
4758 }
4759 shift = (insn >> 16) & ((1 << (3 + size)) - 1);
4760 /* To avoid excessive dumplication of ops we implement shift
4761 by immediate using the variable shift operations. */
4762 if (op < 8) {
4763 /* Shift by immediate:
4764 VSHR, VSRA, VRSHR, VRSRA, VSRI, VSHL, VQSHL, VQSHLU. */
4765 /* Right shifts are encoded as N - shift, where N is the
4766 element size in bits. */
4767 if (op <= 4)
4768 shift = shift - (1 << (size + 3));
9ee6e8bb
PB		 4769 if (size == 3) {
4770 count = q + 1;
4771 } else {
4772 count = q ? 4: 2;
4773 }
4774 switch (size) {
4775 case 0:
4776 imm = (uint8_t) shift;
4777 imm |= imm << 8;
4778 imm |= imm << 16;
4779 break;
4780 case 1:
4781 imm = (uint16_t) shift;
4782 imm |= imm << 16;
4783 break;
4784 case 2:
4785 case 3:
4786 imm = shift;
4787 break;
4788 default:
4789 abort();
4790 }
4791
4792 for (pass = 0; pass < count; pass++) {
ad69471c
PB		 4793 if (size == 3) {
4794 neon_load_reg64(cpu_V0, rm + pass);
4795 tcg_gen_movi_i64(cpu_V1, imm);
4796 switch (op) {
4797 case 0: /* VSHR */
4798 case 1: /* VSRA */
4799 if (u)
4800 gen_helper_neon_shl_u64(cpu_V0, cpu_V0, cpu_V1);
9ee6e8bb 4801 else
ad69471c 4802 gen_helper_neon_shl_s64(cpu_V0, cpu_V0, cpu_V1);
9ee6e8bb 4803 break;
ad69471c
PB		 4804 case 2: /* VRSHR */
4805 case 3: /* VRSRA */
4806 if (u)
4807 gen_helper_neon_rshl_u64(cpu_V0, cpu_V0, cpu_V1);
9ee6e8bb 4808 else
ad69471c 4809 gen_helper_neon_rshl_s64(cpu_V0, cpu_V0, cpu_V1);
9ee6e8bb 4810 break;
ad69471c
PB		 4811 case 4: /* VSRI */
4812 if (!u)
4813 return 1;
4814 gen_helper_neon_shl_u64(cpu_V0, cpu_V0, cpu_V1);
4815 break;
4816 case 5: /* VSHL, VSLI */
4817 gen_helper_neon_shl_u64(cpu_V0, cpu_V0, cpu_V1);
4818 break;
0322b26e
PM		 4819 case 6: /* VQSHLU */
4820 if (u) {
2a3f75b4 4821 gen_helper_neon_qshlu_s64(cpu_V0,
0322b26e
PM		 4822 cpu_V0, cpu_V1);
4823 } else {
4824 return 1;
4825 }
ad69471c 4826 break;
0322b26e
PM		 4827 case 7: /* VQSHL */
4828 if (u) {
2a3f75b4 4829 gen_helper_neon_qshl_u64(cpu_V0,
0322b26e
PM		 4830 cpu_V0, cpu_V1);
4831 } else {
2a3f75b4 4832 gen_helper_neon_qshl_s64(cpu_V0,
0322b26e
PM		 4833 cpu_V0, cpu_V1);
4834 }
9ee6e8bb 4835 break;
9ee6e8bb 4836 }
ad69471c
PB		 4837 if (op == 1 || op == 3) {
4838 /* Accumulate. */
5371cb81 4839 neon_load_reg64(cpu_V1, rd + pass);
ad69471c
PB		 4840 tcg_gen_add_i64(cpu_V0, cpu_V0, cpu_V1);
4841 } else if (op == 4 || (op == 5 && u)) {
4842 /* Insert */
923e6509
CL		 4843 neon_load_reg64(cpu_V1, rd + pass);
4844 uint64_t mask;
4845 if (shift < -63 || shift > 63) {
4846 mask = 0;
4847 } else {
4848 if (op == 4) {
4849 mask = 0xffffffffffffffffull >> -shift;
4850 } else {
4851 mask = 0xffffffffffffffffull << shift;
4852 }
4853 }
4854 tcg_gen_andi_i64(cpu_V1, cpu_V1, ~mask);
4855 tcg_gen_or_i64(cpu_V0, cpu_V0, cpu_V1);
ad69471c
PB		 4856 }
4857 neon_store_reg64(cpu_V0, rd + pass);
4858 } else { /* size < 3 */
4859 /* Operands in T0 and T1. */
dd8fbd78 4860 tmp = neon_load_reg(rm, pass);
7d1b0095 4861 tmp2 = tcg_temp_new_i32();
dd8fbd78 4862 tcg_gen_movi_i32(tmp2, imm);
ad69471c
PB		 4863 switch (op) {
4864 case 0: /* VSHR */
4865 case 1: /* VSRA */
4866 GEN_NEON_INTEGER_OP(shl);
4867 break;
4868 case 2: /* VRSHR */
4869 case 3: /* VRSRA */
4870 GEN_NEON_INTEGER_OP(rshl);
4871 break;
4872 case 4: /* VSRI */
4873 if (!u)
4874 return 1;
4875 GEN_NEON_INTEGER_OP(shl);
4876 break;
4877 case 5: /* VSHL, VSLI */
4878 switch (size) {
dd8fbd78
FN		 4879 case 0: gen_helper_neon_shl_u8(tmp, tmp, tmp2); break;
4880 case 1: gen_helper_neon_shl_u16(tmp, tmp, tmp2); break;
4881 case 2: gen_helper_neon_shl_u32(tmp, tmp, tmp2); break;
ad69471c
PB		 4882 default: return 1;
4883 }
4884 break;
0322b26e
PM		 4885 case 6: /* VQSHLU */
4886 if (!u) {
4887 return 1;
4888 }
ad69471c 4889 switch (size) {
0322b26e 4890 case 0:
2a3f75b4 4891 gen_helper_neon_qshlu_s8(tmp, tmp, tmp2);
0322b26e
PM		 4892 break;
4893 case 1:
2a3f75b4 4894 gen_helper_neon_qshlu_s16(tmp, tmp, tmp2);
0322b26e
PM		 4895 break;
4896 case 2:
2a3f75b4 4897 gen_helper_neon_qshlu_s32(tmp, tmp, tmp2);
0322b26e
PM		 4898 break;
4899 default:
4900 return 1;
ad69471c
PB		 4901 }
4902 break;
0322b26e 4903 case 7: /* VQSHL */
2a3f75b4 4904 GEN_NEON_INTEGER_OP(qshl);
0322b26e 4905 break;
ad69471c 4906 }
7d1b0095 4907 tcg_temp_free_i32(tmp2);
ad69471c
PB		 4908
4909 if (op == 1 || op == 3) {
4910 /* Accumulate. */
dd8fbd78 4911 tmp2 = neon_load_reg(rd, pass);
5371cb81 4912 gen_neon_add(size, tmp, tmp2);
7d1b0095 4913 tcg_temp_free_i32(tmp2);
ad69471c
PB		 4914 } else if (op == 4 || (op == 5 && u)) {
4915 /* Insert */
4916 switch (size) {
4917 case 0:
4918 if (op == 4)
ca9a32e4 4919 mask = 0xff >> -shift;
ad69471c 4920 else
ca9a32e4
JR		 4921 mask = (uint8_t)(0xff << shift);
4922 mask |= mask << 8;
4923 mask |= mask << 16;
ad69471c
PB		 4924 break;
4925 case 1:
4926 if (op == 4)
ca9a32e4 4927 mask = 0xffff >> -shift;
ad69471c 4928 else
ca9a32e4
JR		 4929 mask = (uint16_t)(0xffff << shift);
4930 mask |= mask << 16;
ad69471c
PB		 4931 break;
4932 case 2:
ca9a32e4
JR		 4933 if (shift < -31 || shift > 31) {
4934 mask = 0;
4935 } else {
4936 if (op == 4)
4937 mask = 0xffffffffu >> -shift;
4938 else
4939 mask = 0xffffffffu << shift;
4940 }
ad69471c
PB		 4941 break;
4942 default:
4943 abort();
4944 }
dd8fbd78 4945 tmp2 = neon_load_reg(rd, pass);
ca9a32e4
JR		 4946 tcg_gen_andi_i32(tmp, tmp, mask);
4947 tcg_gen_andi_i32(tmp2, tmp2, ~mask);
dd8fbd78 4948 tcg_gen_or_i32(tmp, tmp, tmp2);
7d1b0095 4949 tcg_temp_free_i32(tmp2);
ad69471c 4950 }
dd8fbd78 4951 neon_store_reg(rd, pass, tmp);
9ee6e8bb
PB		 4952 }
4953 } /* for pass */
4954 } else if (op < 10) {
ad69471c 4955 /* Shift by immediate and narrow:
9ee6e8bb 4956 VSHRN, VRSHRN, VQSHRN, VQRSHRN. */
0b36f4cd
CL		 4957 int input_unsigned = (op == 8) ? !u : u;
4958
9ee6e8bb
PB		 4959 shift = shift - (1 << (size + 3));
4960 size++;
92cdfaeb 4961 if (size == 3) {
a7812ae4 4962 tmp64 = tcg_const_i64(shift);
92cdfaeb
PM		 4963 neon_load_reg64(cpu_V0, rm);
4964 neon_load_reg64(cpu_V1, rm + 1);
4965 for (pass = 0; pass < 2; pass++) {
4966 TCGv_i64 in;
4967 if (pass == 0) {
4968 in = cpu_V0;
4969 } else {
4970 in = cpu_V1;
4971 }
ad69471c 4972 if (q) {
0b36f4cd 4973 if (input_unsigned) {
92cdfaeb 4974 gen_helper_neon_rshl_u64(cpu_V0, in, tmp64);
0b36f4cd 4975 } else {
92cdfaeb 4976 gen_helper_neon_rshl_s64(cpu_V0, in, tmp64);
0b36f4cd 4977 }
ad69471c 4978 } else {
0b36f4cd 4979 if (input_unsigned) {
92cdfaeb 4980 gen_helper_neon_shl_u64(cpu_V0, in, tmp64);
0b36f4cd 4981 } else {
92cdfaeb 4982 gen_helper_neon_shl_s64(cpu_V0, in, tmp64);
0b36f4cd 4983 }
ad69471c 4984 }
7d1b0095 4985 tmp = tcg_temp_new_i32();
92cdfaeb
PM		 4986 gen_neon_narrow_op(op == 8, u, size - 1, tmp, cpu_V0);
4987 neon_store_reg(rd, pass, tmp);
4988 } /* for pass */
4989 tcg_temp_free_i64(tmp64);
4990 } else {
4991 if (size == 1) {
4992 imm = (uint16_t)shift;
4993 imm |= imm << 16;
2c0262af 4994 } else {
92cdfaeb
PM		 4995 /* size == 2 */
4996 imm = (uint32_t)shift;
4997 }
4998 tmp2 = tcg_const_i32(imm);
4999 tmp4 = neon_load_reg(rm + 1, 0);
5000 tmp5 = neon_load_reg(rm + 1, 1);
5001 for (pass = 0; pass < 2; pass++) {
5002 if (pass == 0) {
5003 tmp = neon_load_reg(rm, 0);
5004 } else {
5005 tmp = tmp4;
5006 }
0b36f4cd
CL		 5007 gen_neon_shift_narrow(size, tmp, tmp2, q,
5008 input_unsigned);
92cdfaeb
PM		 5009 if (pass == 0) {
5010 tmp3 = neon_load_reg(rm, 1);
5011 } else {
5012 tmp3 = tmp5;
5013 }
0b36f4cd
CL		 5014 gen_neon_shift_narrow(size, tmp3, tmp2, q,
5015 input_unsigned);
36aa55dc 5016 tcg_gen_concat_i32_i64(cpu_V0, tmp, tmp3);
7d1b0095
PM		 5017 tcg_temp_free_i32(tmp);
5018 tcg_temp_free_i32(tmp3);
5019 tmp = tcg_temp_new_i32();
92cdfaeb
PM		 5020 gen_neon_narrow_op(op == 8, u, size - 1, tmp, cpu_V0);
5021 neon_store_reg(rd, pass, tmp);
5022 } /* for pass */
c6067f04 5023 tcg_temp_free_i32(tmp2);
b75263d6 5024 }
9ee6e8bb
PB		 5025 } else if (op == 10) {
5026 /* VSHLL */
ad69471c 5027 if (q || size == 3)
9ee6e8bb 5028 return 1;
ad69471c
PB		 5029 tmp = neon_load_reg(rm, 0);
5030 tmp2 = neon_load_reg(rm, 1);
9ee6e8bb 5031 for (pass = 0; pass < 2; pass++) {
ad69471c
PB		 5032 if (pass == 1)
5033 tmp = tmp2;
5034
5035 gen_neon_widen(cpu_V0, tmp, size, u);
9ee6e8bb 5036
9ee6e8bb
PB		 5037 if (shift != 0) {
5038 /* The shift is less than the width of the source
ad69471c
PB		 5039 type, so we can just shift the whole register. */
5040 tcg_gen_shli_i64(cpu_V0, cpu_V0, shift);
acdf01ef
CL		 5041 /* Widen the result of shift: we need to clear
5042 * the potential overflow bits resulting from
5043 * left bits of the narrow input appearing as
5044 * right bits of left the neighbour narrow
5045 * input. */
ad69471c
PB		 5046 if (size < 2 || !u) {
5047 uint64_t imm64;
5048 if (size == 0) {
5049 imm = (0xffu >> (8 - shift));
5050 imm |= imm << 16;
acdf01ef 5051 } else if (size == 1) {
ad69471c 5052 imm = 0xffff >> (16 - shift);
acdf01ef
CL		 5053 } else {
5054 /* size == 2 */
5055 imm = 0xffffffff >> (32 - shift);
5056 }
5057 if (size < 2) {
5058 imm64 = imm | (((uint64_t)imm) << 32);
5059 } else {
5060 imm64 = imm;
9ee6e8bb 5061 }
acdf01ef 5062 tcg_gen_andi_i64(cpu_V0, cpu_V0, ~imm64);
9ee6e8bb
PB		 5063 }
5064 }
ad69471c 5065 neon_store_reg64(cpu_V0, rd + pass);
9ee6e8bb 5066 }
f73534a5 5067 } else if (op >= 14) {
9ee6e8bb 5068 /* VCVT fixed-point. */
f73534a5
PM		 5069 /* We have already masked out the must-be-1 top bit of imm6,
5070 * hence this 32-shift where the ARM ARM has 64-imm6.
5071 */
5072 shift = 32 - shift;
9ee6e8bb 5073 for (pass = 0; pass < (q ? 4 : 2); pass++) {
4373f3ce 5074 tcg_gen_ld_f32(cpu_F0s, cpu_env, neon_reg_offset(rm, pass));
f73534a5 5075 if (!(op & 1)) {
9ee6e8bb 5076 if (u)
4373f3ce 5077 gen_vfp_ulto(0, shift);
9ee6e8bb 5078 else
4373f3ce 5079 gen_vfp_slto(0, shift);
9ee6e8bb
PB		 5080 } else {
5081 if (u)
4373f3ce 5082 gen_vfp_toul(0, shift);
9ee6e8bb 5083 else
4373f3ce 5084 gen_vfp_tosl(0, shift);
2c0262af 5085 }
4373f3ce 5086 tcg_gen_st_f32(cpu_F0s, cpu_env, neon_reg_offset(rd, pass));
2c0262af
FB		 5087 }
5088 } else {
9ee6e8bb
PB		 5089 return 1;
5090 }
5091 } else { /* (insn & 0x00380080) == 0 */
5092 int invert;
5093
5094 op = (insn >> 8) & 0xf;
5095 /* One register and immediate. */
5096 imm = (u << 7) | ((insn >> 12) & 0x70) | (insn & 0xf);
5097 invert = (insn & (1 << 5)) != 0;
5098 switch (op) {
5099 case 0: case 1:
5100 /* no-op */
5101 break;
5102 case 2: case 3:
5103 imm <<= 8;
5104 break;
5105 case 4: case 5:
5106 imm <<= 16;
5107 break;
5108 case 6: case 7:
5109 imm <<= 24;
5110 break;
5111 case 8: case 9:
5112 imm |= imm << 16;
5113 break;
5114 case 10: case 11:
5115 imm = (imm << 8) | (imm << 24);
5116 break;
5117 case 12:
8e31209e 5118 imm = (imm << 8) | 0xff;
9ee6e8bb
PB		 5119 break;
5120 case 13:
5121 imm = (imm << 16) | 0xffff;
5122 break;
5123 case 14:
5124 imm |= (imm << 8) | (imm << 16) | (imm << 24);
5125 if (invert)
5126 imm = ~imm;
5127 break;
5128 case 15:
5129 imm = ((imm & 0x80) << 24) | ((imm & 0x3f) << 19)
5130 | ((imm & 0x40) ? (0x1f << 25) : (1 << 30));
5131 break;
5132 }
5133 if (invert)
5134 imm = ~imm;
5135
9ee6e8bb
PB		 5136 for (pass = 0; pass < (q ? 4 : 2); pass++) {
5137 if (op & 1 && op < 12) {
ad69471c 5138 tmp = neon_load_reg(rd, pass);
9ee6e8bb
PB		 5139 if (invert) {
5140 /* The immediate value has already been inverted, so
5141 BIC becomes AND. */
ad69471c 5142 tcg_gen_andi_i32(tmp, tmp, imm);
9ee6e8bb 5143 } else {
ad69471c 5144 tcg_gen_ori_i32(tmp, tmp, imm);
9ee6e8bb 5145 }
9ee6e8bb 5146 } else {
ad69471c 5147 /* VMOV, VMVN. */
7d1b0095 5148 tmp = tcg_temp_new_i32();
9ee6e8bb 5149 if (op == 14 && invert) {
ad69471c
PB		 5150 uint32_t val;
5151 val = 0;
9ee6e8bb
PB		 5152 for (n = 0; n < 4; n++) {
5153 if (imm & (1 << (n + (pass & 1) * 4)))
ad69471c 5154 val |= 0xff << (n * 8);
9ee6e8bb 5155 }
ad69471c
PB		 5156 tcg_gen_movi_i32(tmp, val);
5157 } else {
5158 tcg_gen_movi_i32(tmp, imm);
9ee6e8bb 5159 }
9ee6e8bb 5160 }
ad69471c 5161 neon_store_reg(rd, pass, tmp);
9ee6e8bb
PB		 5162 }
5163 }
e4b3861d 5164 } else { /* (insn & 0x00800010 == 0x00800000) */
9ee6e8bb
PB		 5165 if (size != 3) {
5166 op = (insn >> 8) & 0xf;
5167 if ((insn & (1 << 6)) == 0) {
5168 /* Three registers of different lengths. */
5169 int src1_wide;
5170 int src2_wide;
5171 int prewiden;
5172 /* prewiden, src1_wide, src2_wide */
5173 static const int neon_3reg_wide[16][3] = {
5174 {1, 0, 0}, /* VADDL */
5175 {1, 1, 0}, /* VADDW */
5176 {1, 0, 0}, /* VSUBL */
5177 {1, 1, 0}, /* VSUBW */
5178 {0, 1, 1}, /* VADDHN */
5179 {0, 0, 0}, /* VABAL */
5180 {0, 1, 1}, /* VSUBHN */
5181 {0, 0, 0}, /* VABDL */
5182 {0, 0, 0}, /* VMLAL */
5183 {0, 0, 0}, /* VQDMLAL */
5184 {0, 0, 0}, /* VMLSL */
5185 {0, 0, 0}, /* VQDMLSL */
5186 {0, 0, 0}, /* Integer VMULL */
5187 {0, 0, 0}, /* VQDMULL */
5188 {0, 0, 0} /* Polynomial VMULL */
5189 };
5190
5191 prewiden = neon_3reg_wide[op][0];
5192 src1_wide = neon_3reg_wide[op][1];
5193 src2_wide = neon_3reg_wide[op][2];
5194
ad69471c
PB		 5195 if (size == 0 && (op == 9 || op == 11 || op == 13))
5196 return 1;
5197
9ee6e8bb
PB		 5198 /* Avoid overlapping operands. Wide source operands are
5199 always aligned so will never overlap with wide
5200 destinations in problematic ways. */
8f8e3aa4 5201 if (rd == rm && !src2_wide) {
dd8fbd78
FN		 5202 tmp = neon_load_reg(rm, 1);
5203 neon_store_scratch(2, tmp);
8f8e3aa4 5204 } else if (rd == rn && !src1_wide) {
dd8fbd78
FN		 5205 tmp = neon_load_reg(rn, 1);
5206 neon_store_scratch(2, tmp);
9ee6e8bb 5207 }
a50f5b91 5208 TCGV_UNUSED(tmp3);
9ee6e8bb 5209 for (pass = 0; pass < 2; pass++) {
ad69471c
PB		 5210 if (src1_wide) {
5211 neon_load_reg64(cpu_V0, rn + pass);
a50f5b91 5212 TCGV_UNUSED(tmp);
9ee6e8bb 5213 } else {
ad69471c 5214 if (pass == 1 && rd == rn) {
dd8fbd78 5215 tmp = neon_load_scratch(2);
9ee6e8bb 5216 } else {
ad69471c
PB		 5217 tmp = neon_load_reg(rn, pass);
5218 }
5219 if (prewiden) {
5220 gen_neon_widen(cpu_V0, tmp, size, u);
9ee6e8bb
PB		 5221 }
5222 }
ad69471c
PB		 5223 if (src2_wide) {
5224 neon_load_reg64(cpu_V1, rm + pass);
a50f5b91 5225 TCGV_UNUSED(tmp2);
9ee6e8bb 5226 } else {
ad69471c 5227 if (pass == 1 && rd == rm) {
dd8fbd78 5228 tmp2 = neon_load_scratch(2);
9ee6e8bb 5229 } else {
ad69471c
PB		 5230 tmp2 = neon_load_reg(rm, pass);
5231 }
5232 if (prewiden) {
5233 gen_neon_widen(cpu_V1, tmp2, size, u);
9ee6e8bb 5234 }
9ee6e8bb
PB		 5235 }
5236 switch (op) {
5237 case 0: case 1: case 4: /* VADDL, VADDW, VADDHN, VRADDHN */
ad69471c 5238 gen_neon_addl(size);
9ee6e8bb 5239 break;
79b0e534 5240 case 2: case 3: case 6: /* VSUBL, VSUBW, VSUBHN, VRSUBHN */
ad69471c 5241 gen_neon_subl(size);
9ee6e8bb
PB		 5242 break;
5243 case 5: case 7: /* VABAL, VABDL */
5244 switch ((size << 1) | u) {
ad69471c
PB		 5245 case 0:
5246 gen_helper_neon_abdl_s16(cpu_V0, tmp, tmp2);
5247 break;
5248 case 1:
5249 gen_helper_neon_abdl_u16(cpu_V0, tmp, tmp2);
5250 break;
5251 case 2:
5252 gen_helper_neon_abdl_s32(cpu_V0, tmp, tmp2);
5253 break;
5254 case 3:
5255 gen_helper_neon_abdl_u32(cpu_V0, tmp, tmp2);
5256 break;
5257 case 4:
5258 gen_helper_neon_abdl_s64(cpu_V0, tmp, tmp2);
5259 break;
5260 case 5:
5261 gen_helper_neon_abdl_u64(cpu_V0, tmp, tmp2);
5262 break;
9ee6e8bb
PB		 5263 default: abort();
5264 }
7d1b0095
PM		 5265 tcg_temp_free_i32(tmp2);
5266 tcg_temp_free_i32(tmp);
9ee6e8bb
PB		 5267 break;
5268 case 8: case 9: case 10: case 11: case 12: case 13:
5269 /* VMLAL, VQDMLAL, VMLSL, VQDMLSL, VMULL, VQDMULL */
ad69471c 5270 gen_neon_mull(cpu_V0, tmp, tmp2, size, u);
9ee6e8bb
PB		 5271 break;
5272 case 14: /* Polynomial VMULL */
e5ca24cb 5273 gen_helper_neon_mull_p8(cpu_V0, tmp, tmp2);
7d1b0095
PM		 5274 tcg_temp_free_i32(tmp2);
5275 tcg_temp_free_i32(tmp);
e5ca24cb 5276 break;
9ee6e8bb
PB		 5277 default: /* 15 is RESERVED. */
5278 return 1;
5279 }
ebcd88ce
PM		 5280 if (op == 13) {
5281 /* VQDMULL */
5282 gen_neon_addl_saturate(cpu_V0, cpu_V0, size);
5283 neon_store_reg64(cpu_V0, rd + pass);
5284 } else if (op == 5 || (op >= 8 && op <= 11)) {
9ee6e8bb 5285 /* Accumulate. */
ebcd88ce 5286 neon_load_reg64(cpu_V1, rd + pass);
9ee6e8bb 5287 switch (op) {
4dc064e6
PM		 5288 case 10: /* VMLSL */
5289 gen_neon_negl(cpu_V0, size);
5290 /* Fall through */
5291 case 5: case 8: /* VABAL, VMLAL */
ad69471c 5292 gen_neon_addl(size);
9ee6e8bb
PB		 5293 break;
5294 case 9: case 11: /* VQDMLAL, VQDMLSL */
ad69471c 5295 gen_neon_addl_saturate(cpu_V0, cpu_V0, size);
4dc064e6
PM		 5296 if (op == 11) {
5297 gen_neon_negl(cpu_V0, size);
5298 }
ad69471c
PB		 5299 gen_neon_addl_saturate(cpu_V0, cpu_V1, size);
5300 break;
9ee6e8bb
PB		 5301 default:
5302 abort();
5303 }
ad69471c 5304 neon_store_reg64(cpu_V0, rd + pass);
9ee6e8bb
PB		 5305 } else if (op == 4 || op == 6) {
5306 /* Narrowing operation. */
7d1b0095 5307 tmp = tcg_temp_new_i32();
79b0e534 5308 if (!u) {
9ee6e8bb 5309 switch (size) {
ad69471c
PB		 5310 case 0:
5311 gen_helper_neon_narrow_high_u8(tmp, cpu_V0);
5312 break;
5313 case 1:
5314 gen_helper_neon_narrow_high_u16(tmp, cpu_V0);
5315 break;
5316 case 2:
5317 tcg_gen_shri_i64(cpu_V0, cpu_V0, 32);
5318 tcg_gen_trunc_i64_i32(tmp, cpu_V0);
5319 break;
9ee6e8bb
PB		 5320 default: abort();
5321 }
5322 } else {
5323 switch (size) {
ad69471c
PB		 5324 case 0:
5325 gen_helper_neon_narrow_round_high_u8(tmp, cpu_V0);
5326 break;
5327 case 1:
5328 gen_helper_neon_narrow_round_high_u16(tmp, cpu_V0);
5329 break;
5330 case 2:
5331 tcg_gen_addi_i64(cpu_V0, cpu_V0, 1u << 31);
5332 tcg_gen_shri_i64(cpu_V0, cpu_V0, 32);
5333 tcg_gen_trunc_i64_i32(tmp, cpu_V0);
5334 break;
9ee6e8bb
PB		 5335 default: abort();
5336 }
5337 }
ad69471c
PB		 5338 if (pass == 0) {
5339 tmp3 = tmp;
5340 } else {
5341 neon_store_reg(rd, 0, tmp3);
5342 neon_store_reg(rd, 1, tmp);
5343 }
9ee6e8bb
PB		 5344 } else {
5345 /* Write back the result. */
ad69471c 5346 neon_store_reg64(cpu_V0, rd + pass);
9ee6e8bb
PB		 5347 }
5348 }
5349 } else {
5350 /* Two registers and a scalar. */
5351 switch (op) {
5352 case 0: /* Integer VMLA scalar */
5353 case 1: /* Float VMLA scalar */
5354 case 4: /* Integer VMLS scalar */
5355 case 5: /* Floating point VMLS scalar */
5356 case 8: /* Integer VMUL scalar */
5357 case 9: /* Floating point VMUL scalar */
5358 case 12: /* VQDMULH scalar */
5359 case 13: /* VQRDMULH scalar */
dd8fbd78
FN		 5360 tmp = neon_get_scalar(size, rm);
5361 neon_store_scratch(0, tmp);
9ee6e8bb 5362 for (pass = 0; pass < (u ? 4 : 2); pass++) {
dd8fbd78
FN		 5363 tmp = neon_load_scratch(0);
5364 tmp2 = neon_load_reg(rn, pass);
9ee6e8bb
PB		 5365 if (op == 12) {
5366 if (size == 1) {
2a3f75b4 5367 gen_helper_neon_qdmulh_s16(tmp, tmp, tmp2);
9ee6e8bb 5368 } else {
2a3f75b4 5369 gen_helper_neon_qdmulh_s32(tmp, tmp, tmp2);
9ee6e8bb
PB		 5370 }
5371 } else if (op == 13) {
5372 if (size == 1) {
2a3f75b4 5373 gen_helper_neon_qrdmulh_s16(tmp, tmp, tmp2);
9ee6e8bb 5374 } else {
2a3f75b4 5375 gen_helper_neon_qrdmulh_s32(tmp, tmp, tmp2);
9ee6e8bb
PB		 5376 }
5377 } else if (op & 1) {
dd8fbd78 5378 gen_helper_neon_mul_f32(tmp, tmp, tmp2);
9ee6e8bb
PB		 5379 } else {
5380 switch (size) {
dd8fbd78
FN		 5381 case 0: gen_helper_neon_mul_u8(tmp, tmp, tmp2); break;
5382 case 1: gen_helper_neon_mul_u16(tmp, tmp, tmp2); break;
5383 case 2: tcg_gen_mul_i32(tmp, tmp, tmp2); break;
9ee6e8bb
PB		 5384 default: return 1;
5385 }
5386 }
7d1b0095 5387 tcg_temp_free_i32(tmp2);
9ee6e8bb
PB		 5388 if (op < 8) {
5389 /* Accumulate. */
dd8fbd78 5390 tmp2 = neon_load_reg(rd, pass);
9ee6e8bb
PB		 5391 switch (op) {
5392 case 0:
dd8fbd78 5393 gen_neon_add(size, tmp, tmp2);
9ee6e8bb
PB		 5394 break;
5395 case 1:
dd8fbd78 5396 gen_helper_neon_add_f32(tmp, tmp, tmp2);
9ee6e8bb
PB		 5397 break;
5398 case 4:
dd8fbd78 5399 gen_neon_rsb(size, tmp, tmp2);
9ee6e8bb
PB		 5400 break;
5401 case 5:
dd8fbd78 5402 gen_helper_neon_sub_f32(tmp, tmp2, tmp);
9ee6e8bb
PB		 5403 break;
5404 default:
5405 abort();
5406 }
7d1b0095 5407 tcg_temp_free_i32(tmp2);
9ee6e8bb 5408 }
dd8fbd78 5409 neon_store_reg(rd, pass, tmp);
9ee6e8bb
PB		 5410 }
5411 break;
5412 case 2: /* VMLAL sclar */
5413 case 3: /* VQDMLAL scalar */
5414 case 6: /* VMLSL scalar */
5415 case 7: /* VQDMLSL scalar */
5416 case 10: /* VMULL scalar */
5417 case 11: /* VQDMULL scalar */
ad69471c
PB		 5418 if (size == 0 && (op == 3 || op == 7 || op == 11))
5419 return 1;
5420
dd8fbd78 5421 tmp2 = neon_get_scalar(size, rm);
c6067f04
CL		 5422 /* We need a copy of tmp2 because gen_neon_mull
5423 * deletes it during pass 0. */
7d1b0095 5424 tmp4 = tcg_temp_new_i32();
c6067f04 5425 tcg_gen_mov_i32(tmp4, tmp2);
dd8fbd78 5426 tmp3 = neon_load_reg(rn, 1);
ad69471c 5427
9ee6e8bb 5428 for (pass = 0; pass < 2; pass++) {
ad69471c
PB		 5429 if (pass == 0) {
5430 tmp = neon_load_reg(rn, 0);
9ee6e8bb 5431 } else {
dd8fbd78 5432 tmp = tmp3;
c6067f04 5433 tmp2 = tmp4;
9ee6e8bb 5434 }
ad69471c 5435 gen_neon_mull(cpu_V0, tmp, tmp2, size, u);
ad69471c
PB		 5436 if (op != 11) {
5437 neon_load_reg64(cpu_V1, rd + pass);
9ee6e8bb 5438 }
9ee6e8bb 5439 switch (op) {
4dc064e6
PM		 5440 case 6:
5441 gen_neon_negl(cpu_V0, size);
5442 /* Fall through */
5443 case 2:
ad69471c 5444 gen_neon_addl(size);
9ee6e8bb
PB		 5445 break;
5446 case 3: case 7:
ad69471c 5447 gen_neon_addl_saturate(cpu_V0, cpu_V0, size);
4dc064e6
PM		 5448 if (op == 7) {
5449 gen_neon_negl(cpu_V0, size);
5450 }
ad69471c 5451 gen_neon_addl_saturate(cpu_V0, cpu_V1, size);
9ee6e8bb
PB		 5452 break;
5453 case 10:
5454 /* no-op */
5455 break;
5456 case 11:
ad69471c 5457 gen_neon_addl_saturate(cpu_V0, cpu_V0, size);
9ee6e8bb
PB		 5458 break;
5459 default:
5460 abort();
5461 }
ad69471c 5462 neon_store_reg64(cpu_V0, rd + pass);
9ee6e8bb 5463 }
dd8fbd78 5464
dd8fbd78 5465
9ee6e8bb
PB		 5466 break;
5467 default: /* 14 and 15 are RESERVED */
5468 return 1;
5469 }
5470 }
5471 } else { /* size == 3 */
5472 if (!u) {
5473 /* Extract. */
9ee6e8bb 5474 imm = (insn >> 8) & 0xf;
ad69471c
PB		 5475
5476 if (imm > 7 && !q)
5477 return 1;
5478
5479 if (imm == 0) {
5480 neon_load_reg64(cpu_V0, rn);
5481 if (q) {
5482 neon_load_reg64(cpu_V1, rn + 1);
9ee6e8bb 5483 }
ad69471c
PB		 5484 } else if (imm == 8) {
5485 neon_load_reg64(cpu_V0, rn + 1);
5486 if (q) {
5487 neon_load_reg64(cpu_V1, rm);
9ee6e8bb 5488 }
ad69471c 5489 } else if (q) {
a7812ae4 5490 tmp64 = tcg_temp_new_i64();
ad69471c
PB		 5491 if (imm < 8) {
5492 neon_load_reg64(cpu_V0, rn);
a7812ae4 5493 neon_load_reg64(tmp64, rn + 1);
ad69471c
PB		 5494 } else {
5495 neon_load_reg64(cpu_V0, rn + 1);
a7812ae4 5496 neon_load_reg64(tmp64, rm);
ad69471c
PB		 5497 }
5498 tcg_gen_shri_i64(cpu_V0, cpu_V0, (imm & 7) * 8);
a7812ae4 5499 tcg_gen_shli_i64(cpu_V1, tmp64, 64 - ((imm & 7) * 8));
ad69471c
PB		 5500 tcg_gen_or_i64(cpu_V0, cpu_V0, cpu_V1);
5501 if (imm < 8) {
5502 neon_load_reg64(cpu_V1, rm);
9ee6e8bb 5503 } else {
ad69471c
PB		 5504 neon_load_reg64(cpu_V1, rm + 1);
5505 imm -= 8;
9ee6e8bb 5506 }
ad69471c 5507 tcg_gen_shli_i64(cpu_V1, cpu_V1, 64 - (imm * 8));
a7812ae4
PB		 5508 tcg_gen_shri_i64(tmp64, tmp64, imm * 8);
5509 tcg_gen_or_i64(cpu_V1, cpu_V1, tmp64);
b75263d6 5510 tcg_temp_free_i64(tmp64);
ad69471c 5511 } else {
a7812ae4 5512 /* BUGFIX */
ad69471c 5513 neon_load_reg64(cpu_V0, rn);
a7812ae4 5514 tcg_gen_shri_i64(cpu_V0, cpu_V0, imm * 8);
ad69471c 5515 neon_load_reg64(cpu_V1, rm);
a7812ae4 5516 tcg_gen_shli_i64(cpu_V1, cpu_V1, 64 - (imm * 8));
ad69471c
PB		 5517 tcg_gen_or_i64(cpu_V0, cpu_V0, cpu_V1);
5518 }
5519 neon_store_reg64(cpu_V0, rd);
5520 if (q) {
5521 neon_store_reg64(cpu_V1, rd + 1);
9ee6e8bb
PB		 5522 }
5523 } else if ((insn & (1 << 11)) == 0) {
5524 /* Two register misc. */
5525 op = ((insn >> 12) & 0x30) | ((insn >> 7) & 0xf);
5526 size = (insn >> 18) & 3;
5527 switch (op) {
5528 case 0: /* VREV64 */
5529 if (size == 3)
5530 return 1;
5531 for (pass = 0; pass < (q ? 2 : 1); pass++) {
dd8fbd78
FN		 5532 tmp = neon_load_reg(rm, pass * 2);
5533 tmp2 = neon_load_reg(rm, pass * 2 + 1);
9ee6e8bb 5534 switch (size) {
dd8fbd78
FN		 5535 case 0: tcg_gen_bswap32_i32(tmp, tmp); break;
5536 case 1: gen_swap_half(tmp); break;
9ee6e8bb
PB		 5537 case 2: /* no-op */ break;
5538 default: abort();
5539 }
dd8fbd78 5540 neon_store_reg(rd, pass * 2 + 1, tmp);
9ee6e8bb 5541 if (size == 2) {
dd8fbd78 5542 neon_store_reg(rd, pass * 2, tmp2);
9ee6e8bb 5543 } else {
9ee6e8bb 5544 switch (size) {
dd8fbd78
FN		 5545 case 0: tcg_gen_bswap32_i32(tmp2, tmp2); break;
5546 case 1: gen_swap_half(tmp2); break;
9ee6e8bb
PB		 5547 default: abort();
5548 }
dd8fbd78 5549 neon_store_reg(rd, pass * 2, tmp2);
9ee6e8bb
PB		 5550 }
5551 }
5552 break;
5553 case 4: case 5: /* VPADDL */
5554 case 12: case 13: /* VPADAL */
9ee6e8bb
PB		 5555 if (size == 3)
5556 return 1;
ad69471c
PB		 5557 for (pass = 0; pass < q + 1; pass++) {
5558 tmp = neon_load_reg(rm, pass * 2);
5559 gen_neon_widen(cpu_V0, tmp, size, op & 1);
5560 tmp = neon_load_reg(rm, pass * 2 + 1);
5561 gen_neon_widen(cpu_V1, tmp, size, op & 1);
5562 switch (size) {
5563 case 0: gen_helper_neon_paddl_u16(CPU_V001); break;
5564 case 1: gen_helper_neon_paddl_u32(CPU_V001); break;
5565 case 2: tcg_gen_add_i64(CPU_V001); break;
5566 default: abort();
5567 }
9ee6e8bb
PB		 5568 if (op >= 12) {
5569 /* Accumulate. */
ad69471c
PB		 5570 neon_load_reg64(cpu_V1, rd + pass);
5571 gen_neon_addl(size);
9ee6e8bb 5572 }
ad69471c 5573 neon_store_reg64(cpu_V0, rd + pass);
9ee6e8bb
PB		 5574 }
5575 break;
5576 case 33: /* VTRN */
5577 if (size == 2) {
5578 for (n = 0; n < (q ? 4 : 2); n += 2) {
dd8fbd78
FN		 5579 tmp = neon_load_reg(rm, n);
5580 tmp2 = neon_load_reg(rd, n + 1);
5581 neon_store_reg(rm, n, tmp2);
5582 neon_store_reg(rd, n + 1, tmp);
9ee6e8bb
PB		 5583 }
5584 } else {
5585 goto elementwise;
5586 }
5587 break;
5588 case 34: /* VUZP */
02acedf9 5589 if (gen_neon_unzip(rd, rm, size, q)) {
9ee6e8bb 5590 return 1;
9ee6e8bb
PB		 5591 }
5592 break;
5593 case 35: /* VZIP */
d68a6f3a 5594 if (gen_neon_zip(rd, rm, size, q)) {
9ee6e8bb 5595 return 1;
9ee6e8bb
PB		 5596 }
5597 break;
5598 case 36: case 37: /* VMOVN, VQMOVUN, VQMOVN */
ad69471c
PB		 5599 if (size == 3)
5600 return 1;
a50f5b91 5601 TCGV_UNUSED(tmp2);
9ee6e8bb 5602 for (pass = 0; pass < 2; pass++) {
ad69471c 5603 neon_load_reg64(cpu_V0, rm + pass);
7d1b0095 5604 tmp = tcg_temp_new_i32();
c33171c7 5605 gen_neon_narrow_op(op == 36, q, size, tmp, cpu_V0);
ad69471c
PB		 5606 if (pass == 0) {
5607 tmp2 = tmp;
5608 } else {
5609 neon_store_reg(rd, 0, tmp2);
5610 neon_store_reg(rd, 1, tmp);
9ee6e8bb 5611 }
9ee6e8bb
PB		 5612 }
5613 break;
5614 case 38: /* VSHLL */
ad69471c 5615 if (q || size == 3)
9ee6e8bb 5616 return 1;
ad69471c
PB		 5617 tmp = neon_load_reg(rm, 0);
5618 tmp2 = neon_load_reg(rm, 1);
9ee6e8bb 5619 for (pass = 0; pass < 2; pass++) {
ad69471c
PB		 5620 if (pass == 1)
5621 tmp = tmp2;
5622 gen_neon_widen(cpu_V0, tmp, size, 1);
30d11a2a 5623 tcg_gen_shli_i64(cpu_V0, cpu_V0, 8 << size);
ad69471c 5624 neon_store_reg64(cpu_V0, rd + pass);
9ee6e8bb
PB		 5625 }
5626 break;
60011498
PB		 5627 case 44: /* VCVT.F16.F32 */
5628 if (!arm_feature(env, ARM_FEATURE_VFP_FP16))
5629 return 1;
7d1b0095
PM		 5630 tmp = tcg_temp_new_i32();
5631 tmp2 = tcg_temp_new_i32();
60011498 5632 tcg_gen_ld_f32(cpu_F0s, cpu_env, neon_reg_offset(rm, 0));
2d981da7 5633 gen_helper_neon_fcvt_f32_to_f16(tmp, cpu_F0s, cpu_env);
60011498 5634 tcg_gen_ld_f32(cpu_F0s, cpu_env, neon_reg_offset(rm, 1));
2d981da7 5635 gen_helper_neon_fcvt_f32_to_f16(tmp2, cpu_F0s, cpu_env);
60011498
PB		 5636 tcg_gen_shli_i32(tmp2, tmp2, 16);
5637 tcg_gen_or_i32(tmp2, tmp2, tmp);
5638 tcg_gen_ld_f32(cpu_F0s, cpu_env, neon_reg_offset(rm, 2));
2d981da7 5639 gen_helper_neon_fcvt_f32_to_f16(tmp, cpu_F0s, cpu_env);
60011498
PB		 5640 tcg_gen_ld_f32(cpu_F0s, cpu_env, neon_reg_offset(rm, 3));
5641 neon_store_reg(rd, 0, tmp2);
7d1b0095 5642 tmp2 = tcg_temp_new_i32();
2d981da7 5643 gen_helper_neon_fcvt_f32_to_f16(tmp2, cpu_F0s, cpu_env);
60011498
PB		 5644 tcg_gen_shli_i32(tmp2, tmp2, 16);
5645 tcg_gen_or_i32(tmp2, tmp2, tmp);
5646 neon_store_reg(rd, 1, tmp2);
7d1b0095 5647 tcg_temp_free_i32(tmp);
60011498
PB		 5648 break;
5649 case 46: /* VCVT.F32.F16 */
5650 if (!arm_feature(env, ARM_FEATURE_VFP_FP16))
5651 return 1;
7d1b0095 5652 tmp3 = tcg_temp_new_i32();
60011498
PB		 5653 tmp = neon_load_reg(rm, 0);
5654 tmp2 = neon_load_reg(rm, 1);
5655 tcg_gen_ext16u_i32(tmp3, tmp);
2d981da7 5656 gen_helper_neon_fcvt_f16_to_f32(cpu_F0s, tmp3, cpu_env);
60011498
PB		 5657 tcg_gen_st_f32(cpu_F0s, cpu_env, neon_reg_offset(rd, 0));
5658 tcg_gen_shri_i32(tmp3, tmp, 16);
2d981da7 5659 gen_helper_neon_fcvt_f16_to_f32(cpu_F0s, tmp3, cpu_env);
60011498 5660 tcg_gen_st_f32(cpu_F0s, cpu_env, neon_reg_offset(rd, 1));
7d1b0095 5661 tcg_temp_free_i32(tmp);
60011498 5662 tcg_gen_ext16u_i32(tmp3, tmp2);
2d981da7 5663 gen_helper_neon_fcvt_f16_to_f32(cpu_F0s, tmp3, cpu_env);
60011498
PB		 5664 tcg_gen_st_f32(cpu_F0s, cpu_env, neon_reg_offset(rd, 2));
5665 tcg_gen_shri_i32(tmp3, tmp2, 16);
2d981da7 5666 gen_helper_neon_fcvt_f16_to_f32(cpu_F0s, tmp3, cpu_env);
60011498 5667 tcg_gen_st_f32(cpu_F0s, cpu_env, neon_reg_offset(rd, 3));
7d1b0095
PM		 5668 tcg_temp_free_i32(tmp2);
5669 tcg_temp_free_i32(tmp3);
60011498 5670 break;
9ee6e8bb
PB		 5671 default:
5672 elementwise:
5673 for (pass = 0; pass < (q ? 4 : 2); pass++) {
5674 if (op == 30 || op == 31 || op >= 58) {
4373f3ce
PB		 5675 tcg_gen_ld_f32(cpu_F0s, cpu_env,
5676 neon_reg_offset(rm, pass));
dd8fbd78 5677 TCGV_UNUSED(tmp);
9ee6e8bb 5678 } else {
dd8fbd78 5679 tmp = neon_load_reg(rm, pass);
9ee6e8bb
PB		 5680 }
5681 switch (op) {
5682 case 1: /* VREV32 */
5683 switch (size) {
dd8fbd78
FN		 5684 case 0: tcg_gen_bswap32_i32(tmp, tmp); break;
5685 case 1: gen_swap_half(tmp); break;
9ee6e8bb
PB		 5686 default: return 1;
5687 }
5688 break;
5689 case 2: /* VREV16 */
5690 if (size != 0)
5691 return 1;
dd8fbd78 5692 gen_rev16(tmp);
9ee6e8bb 5693 break;
9ee6e8bb
PB		 5694 case 8: /* CLS */
5695 switch (size) {
dd8fbd78
FN		 5696 case 0: gen_helper_neon_cls_s8(tmp, tmp); break;
5697 case 1: gen_helper_neon_cls_s16(tmp, tmp); break;
5698 case 2: gen_helper_neon_cls_s32(tmp, tmp); break;
9ee6e8bb
PB		 5699 default: return 1;
5700 }
5701 break;
5702 case 9: /* CLZ */
5703 switch (size) {
dd8fbd78
FN		 5704 case 0: gen_helper_neon_clz_u8(tmp, tmp); break;
5705 case 1: gen_helper_neon_clz_u16(tmp, tmp); break;
5706 case 2: gen_helper_clz(tmp, tmp); break;
9ee6e8bb
PB		 5707 default: return 1;
5708 }
5709 break;
5710 case 10: /* CNT */
5711 if (size != 0)
5712 return 1;
dd8fbd78 5713 gen_helper_neon_cnt_u8(tmp, tmp);
9ee6e8bb
PB		 5714 break;
5715 case 11: /* VNOT */
5716 if (size != 0)
5717 return 1;
dd8fbd78 5718 tcg_gen_not_i32(tmp, tmp);
9ee6e8bb
PB		 5719 break;
5720 case 14: /* VQABS */
5721 switch (size) {
2a3f75b4
PM		 5722 case 0: gen_helper_neon_qabs_s8(tmp, tmp); break;
5723 case 1: gen_helper_neon_qabs_s16(tmp, tmp); break;
5724 case 2: gen_helper_neon_qabs_s32(tmp, tmp); break;
9ee6e8bb
PB		 5725 default: return 1;
5726 }
5727 break;
5728 case 15: /* VQNEG */
5729 switch (size) {
2a3f75b4
PM		 5730 case 0: gen_helper_neon_qneg_s8(tmp, tmp); break;
5731 case 1: gen_helper_neon_qneg_s16(tmp, tmp); break;
5732 case 2: gen_helper_neon_qneg_s32(tmp, tmp); break;
9ee6e8bb
PB		 5733 default: return 1;
5734 }
5735 break;
5736 case 16: case 19: /* VCGT #0, VCLE #0 */
dd8fbd78 5737 tmp2 = tcg_const_i32(0);
9ee6e8bb 5738 switch(size) {
dd8fbd78
FN		 5739 case 0: gen_helper_neon_cgt_s8(tmp, tmp, tmp2); break;
5740 case 1: gen_helper_neon_cgt_s16(tmp, tmp, tmp2); break;
5741 case 2: gen_helper_neon_cgt_s32(tmp, tmp, tmp2); break;
9ee6e8bb
PB		 5742 default: return 1;
5743 }
dd8fbd78 5744 tcg_temp_free(tmp2);
9ee6e8bb 5745 if (op == 19)
dd8fbd78 5746 tcg_gen_not_i32(tmp, tmp);
9ee6e8bb
PB		 5747 break;
5748 case 17: case 20: /* VCGE #0, VCLT #0 */
dd8fbd78 5749 tmp2 = tcg_const_i32(0);
9ee6e8bb 5750 switch(size) {
dd8fbd78
FN		 5751 case 0: gen_helper_neon_cge_s8(tmp, tmp, tmp2); break;
5752 case 1: gen_helper_neon_cge_s16(tmp, tmp, tmp2); break;
5753 case 2: gen_helper_neon_cge_s32(tmp, tmp, tmp2); break;
9ee6e8bb
PB		 5754 default: return 1;
5755 }
dd8fbd78 5756 tcg_temp_free(tmp2);
9ee6e8bb 5757 if (op == 20)
dd8fbd78 5758 tcg_gen_not_i32(tmp, tmp);
9ee6e8bb
PB		 5759 break;
5760 case 18: /* VCEQ #0 */
dd8fbd78 5761 tmp2 = tcg_const_i32(0);
9ee6e8bb 5762 switch(size) {
dd8fbd78
FN		 5763 case 0: gen_helper_neon_ceq_u8(tmp, tmp, tmp2); break;
5764 case 1: gen_helper_neon_ceq_u16(tmp, tmp, tmp2); break;
5765 case 2: gen_helper_neon_ceq_u32(tmp, tmp, tmp2); break;
9ee6e8bb
PB		 5766 default: return 1;
5767 }
dd8fbd78 5768 tcg_temp_free(tmp2);
9ee6e8bb
PB		 5769 break;
5770 case 22: /* VABS */
5771 switch(size) {
dd8fbd78
FN		 5772 case 0: gen_helper_neon_abs_s8(tmp, tmp); break;
5773 case 1: gen_helper_neon_abs_s16(tmp, tmp); break;
5774 case 2: tcg_gen_abs_i32(tmp, tmp); break;
9ee6e8bb
PB		 5775 default: return 1;
5776 }
5777 break;
5778 case 23: /* VNEG */
ad69471c
PB		 5779 if (size == 3)
5780 return 1;
dd8fbd78
FN		 5781 tmp2 = tcg_const_i32(0);
5782 gen_neon_rsb(size, tmp, tmp2);
5783 tcg_temp_free(tmp2);
9ee6e8bb 5784 break;
0e326109 5785 case 24: /* Float VCGT #0 */
dd8fbd78
FN		 5786 tmp2 = tcg_const_i32(0);
5787 gen_helper_neon_cgt_f32(tmp, tmp, tmp2);
5788 tcg_temp_free(tmp2);
9ee6e8bb 5789 break;
0e326109 5790 case 25: /* Float VCGE #0 */
dd8fbd78
FN		 5791 tmp2 = tcg_const_i32(0);
5792 gen_helper_neon_cge_f32(tmp, tmp, tmp2);
5793 tcg_temp_free(tmp2);
9ee6e8bb
PB		 5794 break;
5795 case 26: /* Float VCEQ #0 */
dd8fbd78
FN		 5796 tmp2 = tcg_const_i32(0);
5797 gen_helper_neon_ceq_f32(tmp, tmp, tmp2);
5798 tcg_temp_free(tmp2);
9ee6e8bb 5799 break;
0e326109
PM		 5800 case 27: /* Float VCLE #0 */
5801 tmp2 = tcg_const_i32(0);
5802 gen_helper_neon_cge_f32(tmp, tmp2, tmp);
5803 tcg_temp_free(tmp2);
5804 break;
5805 case 28: /* Float VCLT #0 */
5806 tmp2 = tcg_const_i32(0);
5807 gen_helper_neon_cgt_f32(tmp, tmp2, tmp);
5808 tcg_temp_free(tmp2);
5809 break;
9ee6e8bb 5810 case 30: /* Float VABS */
4373f3ce 5811 gen_vfp_abs(0);
9ee6e8bb
PB		 5812 break;
5813 case 31: /* Float VNEG */
4373f3ce 5814 gen_vfp_neg(0);
9ee6e8bb
PB		 5815 break;
5816 case 32: /* VSWP */
dd8fbd78
FN		 5817 tmp2 = neon_load_reg(rd, pass);
5818 neon_store_reg(rm, pass, tmp2);
9ee6e8bb
PB		 5819 break;
5820 case 33: /* VTRN */
dd8fbd78 5821 tmp2 = neon_load_reg(rd, pass);
9ee6e8bb 5822 switch (size) {
dd8fbd78
FN		 5823 case 0: gen_neon_trn_u8(tmp, tmp2); break;
5824 case 1: gen_neon_trn_u16(tmp, tmp2); break;
9ee6e8bb
PB		 5825 case 2: abort();
5826 default: return 1;
5827 }
dd8fbd78 5828 neon_store_reg(rm, pass, tmp2);
9ee6e8bb
PB		 5829 break;
5830 case 56: /* Integer VRECPE */
dd8fbd78 5831 gen_helper_recpe_u32(tmp, tmp, cpu_env);
9ee6e8bb
PB		 5832 break;
5833 case 57: /* Integer VRSQRTE */
dd8fbd78 5834 gen_helper_rsqrte_u32(tmp, tmp, cpu_env);
9ee6e8bb
PB		 5835 break;
5836 case 58: /* Float VRECPE */
4373f3ce 5837 gen_helper_recpe_f32(cpu_F0s, cpu_F0s, cpu_env);
9ee6e8bb
PB		 5838 break;
5839 case 59: /* Float VRSQRTE */
4373f3ce 5840 gen_helper_rsqrte_f32(cpu_F0s, cpu_F0s, cpu_env);
9ee6e8bb
PB		 5841 break;
5842 case 60: /* VCVT.F32.S32 */
d3587ef8 5843 gen_vfp_sito(0);
9ee6e8bb
PB		 5844 break;
5845 case 61: /* VCVT.F32.U32 */
d3587ef8 5846 gen_vfp_uito(0);
9ee6e8bb
PB		 5847 break;
5848 case 62: /* VCVT.S32.F32 */
d3587ef8 5849 gen_vfp_tosiz(0);
9ee6e8bb
PB		 5850 break;
5851 case 63: /* VCVT.U32.F32 */
d3587ef8 5852 gen_vfp_touiz(0);
9ee6e8bb
PB		 5853 break;
5854 default:
5855 /* Reserved: 21, 29, 39-56 */
5856 return 1;
5857 }
5858 if (op == 30 || op == 31 || op >= 58) {
4373f3ce
PB		 5859 tcg_gen_st_f32(cpu_F0s, cpu_env,
5860 neon_reg_offset(rd, pass));
9ee6e8bb 5861 } else {
dd8fbd78 5862 neon_store_reg(rd, pass, tmp);
9ee6e8bb
PB		 5863 }
5864 }
5865 break;
5866 }
5867 } else if ((insn & (1 << 10)) == 0) {
5868 /* VTBL, VTBX. */
3018f259 5869 n = ((insn >> 5) & 0x18) + 8;
9ee6e8bb 5870 if (insn & (1 << 6)) {
8f8e3aa4 5871 tmp = neon_load_reg(rd, 0);
9ee6e8bb 5872 } else {
7d1b0095 5873 tmp = tcg_temp_new_i32();
8f8e3aa4 5874 tcg_gen_movi_i32(tmp, 0);
9ee6e8bb 5875 }
8f8e3aa4 5876 tmp2 = neon_load_reg(rm, 0);
b75263d6
JR		 5877 tmp4 = tcg_const_i32(rn);
5878 tmp5 = tcg_const_i32(n);
5879 gen_helper_neon_tbl(tmp2, tmp2, tmp, tmp4, tmp5);
7d1b0095 5880 tcg_temp_free_i32(tmp);
9ee6e8bb 5881 if (insn & (1 << 6)) {
8f8e3aa4 5882 tmp = neon_load_reg(rd, 1);
9ee6e8bb 5883 } else {
7d1b0095 5884 tmp = tcg_temp_new_i32();
8f8e3aa4 5885 tcg_gen_movi_i32(tmp, 0);
9ee6e8bb 5886 }
8f8e3aa4 5887 tmp3 = neon_load_reg(rm, 1);
b75263d6 5888 gen_helper_neon_tbl(tmp3, tmp3, tmp, tmp4, tmp5);
25aeb69b
JR		 5889 tcg_temp_free_i32(tmp5);
5890 tcg_temp_free_i32(tmp4);
8f8e3aa4 5891 neon_store_reg(rd, 0, tmp2);
3018f259 5892 neon_store_reg(rd, 1, tmp3);
7d1b0095 5893 tcg_temp_free_i32(tmp);
9ee6e8bb
PB		 5894 } else if ((insn & 0x380) == 0) {
5895 /* VDUP */
5896 if (insn & (1 << 19)) {
dd8fbd78 5897 tmp = neon_load_reg(rm, 1);
9ee6e8bb 5898 } else {
dd8fbd78 5899 tmp = neon_load_reg(rm, 0);
9ee6e8bb
PB		 5900 }
5901 if (insn & (1 << 16)) {
dd8fbd78 5902 gen_neon_dup_u8(tmp, ((insn >> 17) & 3) * 8);
9ee6e8bb
PB		 5903 } else if (insn & (1 << 17)) {
5904 if ((insn >> 18) & 1)
dd8fbd78 5905 gen_neon_dup_high16(tmp);
9ee6e8bb 5906 else
dd8fbd78 5907 gen_neon_dup_low16(tmp);
9ee6e8bb
PB		 5908 }
5909 for (pass = 0; pass < (q ? 4 : 2); pass++) {
7d1b0095 5910 tmp2 = tcg_temp_new_i32();
dd8fbd78
FN		 5911 tcg_gen_mov_i32(tmp2, tmp);
5912 neon_store_reg(rd, pass, tmp2);
9ee6e8bb 5913 }
7d1b0095 5914 tcg_temp_free_i32(tmp);
9ee6e8bb
PB		 5915 } else {
5916 return 1;
5917 }
5918 }
5919 }
5920 return 0;
5921}
5922
fe1479c3
PB		 5923static int disas_cp14_read(CPUState * env, DisasContext *s, uint32_t insn)
5924{
5925 int crn = (insn >> 16) & 0xf;
5926 int crm = insn & 0xf;
5927 int op1 = (insn >> 21) & 7;
5928 int op2 = (insn >> 5) & 7;
5929 int rt = (insn >> 12) & 0xf;
5930 TCGv tmp;
5931
ca27c052
PM		 5932 /* Minimal set of debug registers, since we don't support debug */
5933 if (op1 == 0 && crn == 0 && op2 == 0) {
5934 switch (crm) {
5935 case 0:
5936 /* DBGDIDR: just RAZ. In particular this means the
5937 * "debug architecture version" bits will read as
5938 * a reserved value, which should cause Linux to
5939 * not try to use the debug hardware.
5940 */
5941 tmp = tcg_const_i32(0);
5942 store_reg(s, rt, tmp);
5943 return 0;
5944 case 1:
5945 case 2:
5946 /* DBGDRAR and DBGDSAR: v7 only. Always RAZ since we
5947 * don't implement memory mapped debug components
5948 */
5949 if (ENABLE_ARCH_7) {
5950 tmp = tcg_const_i32(0);
5951 store_reg(s, rt, tmp);
5952 return 0;
5953 }
5954 break;
5955 default:
5956 break;
5957 }
5958 }
5959
fe1479c3
PB		 5960 if (arm_feature(env, ARM_FEATURE_THUMB2EE)) {
5961 if (op1 == 6 && crn == 0 && crm == 0 && op2 == 0) {
5962 /* TEECR */
5963 if (IS_USER(s))
5964 return 1;
5965 tmp = load_cpu_field(teecr);
5966 store_reg(s, rt, tmp);
5967 return 0;
5968 }
5969 if (op1 == 6 && crn == 1 && crm == 0 && op2 == 0) {
5970 /* TEEHBR */
5971 if (IS_USER(s) && (env->teecr & 1))
5972 return 1;
5973 tmp = load_cpu_field(teehbr);
5974 store_reg(s, rt, tmp);
5975 return 0;
5976 }
5977 }
5978 fprintf(stderr, "Unknown cp14 read op1:%d crn:%d crm:%d op2:%d\n",
5979 op1, crn, crm, op2);
5980 return 1;
5981}
5982
5983static int disas_cp14_write(CPUState * env, DisasContext *s, uint32_t insn)
5984{
5985 int crn = (insn >> 16) & 0xf;
5986 int crm = insn & 0xf;
5987 int op1 = (insn >> 21) & 7;
5988 int op2 = (insn >> 5) & 7;
5989 int rt = (insn >> 12) & 0xf;
5990 TCGv tmp;
5991
5992 if (arm_feature(env, ARM_FEATURE_THUMB2EE)) {
5993 if (op1 == 6 && crn == 0 && crm == 0 && op2 == 0) {
5994 /* TEECR */
5995 if (IS_USER(s))
5996 return 1;
5997 tmp = load_reg(s, rt);
5998 gen_helper_set_teecr(cpu_env, tmp);
7d1b0095 5999 tcg_temp_free_i32(tmp);
fe1479c3
PB		 6000 return 0;
6001 }
6002 if (op1 == 6 && crn == 1 && crm == 0 && op2 == 0) {
6003 /* TEEHBR */
6004 if (IS_USER(s) && (env->teecr & 1))
6005 return 1;
6006 tmp = load_reg(s, rt);
6007 store_cpu_field(tmp, teehbr);
6008 return 0;
6009 }
6010 }
6011 fprintf(stderr, "Unknown cp14 write op1:%d crn:%d crm:%d op2:%d\n",
6012 op1, crn, crm, op2);
6013 return 1;
6014}
6015
9ee6e8bb
PB		 6016static int disas_coproc_insn(CPUState * env, DisasContext *s, uint32_t insn)
6017{
6018 int cpnum;
6019
6020 cpnum = (insn >> 8) & 0xf;
6021 if (arm_feature(env, ARM_FEATURE_XSCALE)
6022 && ((env->cp15.c15_cpar ^ 0x3fff) & (1 << cpnum)))
6023 return 1;
6024
6025 switch (cpnum) {
6026 case 0:
6027 case 1:
6028 if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
6029 return disas_iwmmxt_insn(env, s, insn);
6030 } else if (arm_feature(env, ARM_FEATURE_XSCALE)) {
6031 return disas_dsp_insn(env, s, insn);
6032 }
6033 return 1;
6034 case 10:
6035 case 11:
6036 return disas_vfp_insn (env, s, insn);
fe1479c3
PB		 6037 case 14:
6038 /* Coprocessors 7-15 are architecturally reserved by ARM.
6039 Unfortunately Intel decided to ignore this. */
6040 if (arm_feature(env, ARM_FEATURE_XSCALE))
6041 goto board;
6042 if (insn & (1 << 20))
6043 return disas_cp14_read(env, s, insn);
6044 else
6045 return disas_cp14_write(env, s, insn);
9ee6e8bb
PB		 6046 case 15:
6047 return disas_cp15_insn (env, s, insn);
6048 default:
fe1479c3 6049 board:
9ee6e8bb
PB		 6050 /* Unknown coprocessor. See if the board has hooked it. */
6051 return disas_cp_insn (env, s, insn);
6052 }
6053}
6054
5e3f878a
PB		 6055
6056/* Store a 64-bit value to a register pair. Clobbers val. */
a7812ae4 6057static void gen_storeq_reg(DisasContext *s, int rlow, int rhigh, TCGv_i64 val)
5e3f878a
PB		 6058{
6059 TCGv tmp;
7d1b0095 6060 tmp = tcg_temp_new_i32();
5e3f878a
PB		 6061 tcg_gen_trunc_i64_i32(tmp, val);
6062 store_reg(s, rlow, tmp);
7d1b0095 6063 tmp = tcg_temp_new_i32();
5e3f878a
PB		 6064 tcg_gen_shri_i64(val, val, 32);
6065 tcg_gen_trunc_i64_i32(tmp, val);
6066 store_reg(s, rhigh, tmp);
6067}
6068
6069/* load a 32-bit value from a register and perform a 64-bit accumulate. */
a7812ae4 6070static void gen_addq_lo(DisasContext *s, TCGv_i64 val, int rlow)
5e3f878a 6071{
a7812ae4 6072 TCGv_i64 tmp;
5e3f878a
PB		 6073 TCGv tmp2;
6074
36aa55dc 6075 /* Load value and extend to 64 bits. */
a7812ae4 6076 tmp = tcg_temp_new_i64();
5e3f878a
PB		 6077 tmp2 = load_reg(s, rlow);
6078 tcg_gen_extu_i32_i64(tmp, tmp2);
7d1b0095 6079 tcg_temp_free_i32(tmp2);
5e3f878a 6080 tcg_gen_add_i64(val, val, tmp);
b75263d6 6081 tcg_temp_free_i64(tmp);
5e3f878a
PB		 6082}
6083
6084/* load and add a 64-bit value from a register pair. */
a7812ae4 6085static void gen_addq(DisasContext *s, TCGv_i64 val, int rlow, int rhigh)
5e3f878a 6086{
a7812ae4 6087 TCGv_i64 tmp;
36aa55dc
PB		 6088 TCGv tmpl;
6089 TCGv tmph;
5e3f878a
PB		 6090
6091 /* Load 64-bit value rd:rn. */
36aa55dc
PB		 6092 tmpl = load_reg(s, rlow);
6093 tmph = load_reg(s, rhigh);
a7812ae4 6094 tmp = tcg_temp_new_i64();
36aa55dc 6095 tcg_gen_concat_i32_i64(tmp, tmpl, tmph);
7d1b0095
PM		 6096 tcg_temp_free_i32(tmpl);
6097 tcg_temp_free_i32(tmph);
5e3f878a 6098 tcg_gen_add_i64(val, val, tmp);
b75263d6 6099 tcg_temp_free_i64(tmp);
5e3f878a
PB		 6100}
6101
6102/* Set N and Z flags from a 64-bit value. */
a7812ae4 6103static void gen_logicq_cc(TCGv_i64 val)
5e3f878a 6104{
7d1b0095 6105 TCGv tmp = tcg_temp_new_i32();
5e3f878a 6106 gen_helper_logicq_cc(tmp, val);
6fbe23d5 6107 gen_logic_CC(tmp);
7d1b0095 6108 tcg_temp_free_i32(tmp);
5e3f878a
PB		 6109}
6110
426f5abc
PB		 6111/* Load/Store exclusive instructions are implemented by remembering
6112 the value/address loaded, and seeing if these are the same
6113 when the store is performed. This should be is sufficient to implement
6114 the architecturally mandated semantics, and avoids having to monitor
6115 regular stores.
6116
6117 In system emulation mode only one CPU will be running at once, so
6118 this sequence is effectively atomic. In user emulation mode we
6119 throw an exception and handle the atomic operation elsewhere. */
6120static void gen_load_exclusive(DisasContext *s, int rt, int rt2,
6121 TCGv addr, int size)
6122{
6123 TCGv tmp;
6124
6125 switch (size) {
6126 case 0:
6127 tmp = gen_ld8u(addr, IS_USER(s));
6128 break;
6129 case 1:
6130 tmp = gen_ld16u(addr, IS_USER(s));
6131 break;
6132 case 2:
6133 case 3:
6134 tmp = gen_ld32(addr, IS_USER(s));
6135 break;
6136 default:
6137 abort();
6138 }
6139 tcg_gen_mov_i32(cpu_exclusive_val, tmp);
6140 store_reg(s, rt, tmp);
6141 if (size == 3) {
7d1b0095 6142 TCGv tmp2 = tcg_temp_new_i32();
2c9adbda
PM		 6143 tcg_gen_addi_i32(tmp2, addr, 4);
6144 tmp = gen_ld32(tmp2, IS_USER(s));
7d1b0095 6145 tcg_temp_free_i32(tmp2);
426f5abc
PB		 6146 tcg_gen_mov_i32(cpu_exclusive_high, tmp);
6147 store_reg(s, rt2, tmp);
6148 }
6149 tcg_gen_mov_i32(cpu_exclusive_addr, addr);
6150}
6151
6152static void gen_clrex(DisasContext *s)
6153{
6154 tcg_gen_movi_i32(cpu_exclusive_addr, -1);
6155}
6156
6157#ifdef CONFIG_USER_ONLY
6158static void gen_store_exclusive(DisasContext *s, int rd, int rt, int rt2,
6159 TCGv addr, int size)
6160{
6161 tcg_gen_mov_i32(cpu_exclusive_test, addr);
6162 tcg_gen_movi_i32(cpu_exclusive_info,
6163 size | (rd << 4) | (rt << 8) | (rt2 << 12));
bc4a0de0 6164 gen_exception_insn(s, 4, EXCP_STREX);
426f5abc
PB		 6165}
6166#else
6167static void gen_store_exclusive(DisasContext *s, int rd, int rt, int rt2,
6168 TCGv addr, int size)
6169{
6170 TCGv tmp;
6171 int done_label;
6172 int fail_label;
6173
6174 /* if (env->exclusive_addr == addr && env->exclusive_val == [addr]) {
6175 [addr] = {Rt};
6176 {Rd} = 0;
6177 } else {
6178 {Rd} = 1;
6179 } */
6180 fail_label = gen_new_label();
6181 done_label = gen_new_label();
6182 tcg_gen_brcond_i32(TCG_COND_NE, addr, cpu_exclusive_addr, fail_label);
6183 switch (size) {
6184 case 0:
6185 tmp = gen_ld8u(addr, IS_USER(s));
6186 break;
6187 case 1:
6188 tmp = gen_ld16u(addr, IS_USER(s));
6189 break;
6190 case 2:
6191 case 3:
6192 tmp = gen_ld32(addr, IS_USER(s));
6193 break;
6194 default:
6195 abort();
6196 }
6197 tcg_gen_brcond_i32(TCG_COND_NE, tmp, cpu_exclusive_val, fail_label);
7d1b0095 6198 tcg_temp_free_i32(tmp);
426f5abc 6199 if (size == 3) {
7d1b0095 6200 TCGv tmp2 = tcg_temp_new_i32();
426f5abc 6201 tcg_gen_addi_i32(tmp2, addr, 4);
2c9adbda 6202 tmp = gen_ld32(tmp2, IS_USER(s));
7d1b0095 6203 tcg_temp_free_i32(tmp2);
426f5abc 6204 tcg_gen_brcond_i32(TCG_COND_NE, tmp, cpu_exclusive_high, fail_label);
7d1b0095 6205 tcg_temp_free_i32(tmp);
426f5abc
PB		 6206 }
6207 tmp = load_reg(s, rt);
6208 switch (size) {
6209 case 0:
6210 gen_st8(tmp, addr, IS_USER(s));
6211 break;
6212 case 1:
6213 gen_st16(tmp, addr, IS_USER(s));
6214 break;
6215 case 2:
6216 case 3:
6217 gen_st32(tmp, addr, IS_USER(s));
6218 break;
6219 default:
6220 abort();
6221 }
6222 if (size == 3) {
6223 tcg_gen_addi_i32(addr, addr, 4);
6224 tmp = load_reg(s, rt2);
6225 gen_st32(tmp, addr, IS_USER(s));
6226 }
6227 tcg_gen_movi_i32(cpu_R[rd], 0);
6228 tcg_gen_br(done_label);
6229 gen_set_label(fail_label);
6230 tcg_gen_movi_i32(cpu_R[rd], 1);
6231 gen_set_label(done_label);
6232 tcg_gen_movi_i32(cpu_exclusive_addr, -1);
6233}
6234#endif
6235
9ee6e8bb
PB		 6236static void disas_arm_insn(CPUState * env, DisasContext *s)
6237{
6238 unsigned int cond, insn, val, op1, i, shift, rm, rs, rn, rd, sh;
b26eefb6 6239 TCGv tmp;
3670669c 6240 TCGv tmp2;
6ddbc6e4 6241 TCGv tmp3;
b0109805 6242 TCGv addr;
a7812ae4 6243 TCGv_i64 tmp64;
9ee6e8bb
PB		 6244
6245 insn = ldl_code(s->pc);
6246 s->pc += 4;
6247
6248 /* M variants do not implement ARM mode. */
6249 if (IS_M(env))
6250 goto illegal_op;
6251 cond = insn >> 28;
6252 if (cond == 0xf){
be5e7a76
DES		 6253 /* In ARMv3 and v4 the NV condition is UNPREDICTABLE; we
6254 * choose to UNDEF. In ARMv5 and above the space is used
6255 * for miscellaneous unconditional instructions.
6256 */
6257 ARCH(5);
6258
9ee6e8bb
PB		 6259 /* Unconditional instructions. */
6260 if (((insn >> 25) & 7) == 1) {
6261 /* NEON Data processing. */
6262 if (!arm_feature(env, ARM_FEATURE_NEON))
6263 goto illegal_op;
6264
6265 if (disas_neon_data_insn(env, s, insn))
6266 goto illegal_op;
6267 return;
6268 }
6269 if ((insn & 0x0f100000) == 0x04000000) {
6270 /* NEON load/store. */
6271 if (!arm_feature(env, ARM_FEATURE_NEON))
6272 goto illegal_op;
6273
6274 if (disas_neon_ls_insn(env, s, insn))
6275 goto illegal_op;
6276 return;
6277 }
3d185e5d
PM		 6278 if (((insn & 0x0f30f000) == 0x0510f000) ||
6279 ((insn & 0x0f30f010) == 0x0710f000)) {
6280 if ((insn & (1 << 22)) == 0) {
6281 /* PLDW; v7MP */
6282 if (!arm_feature(env, ARM_FEATURE_V7MP)) {
6283 goto illegal_op;
6284 }
6285 }
6286 /* Otherwise PLD; v5TE+ */
be5e7a76 6287 ARCH(5TE);
3d185e5d
PM		 6288 return;
6289 }
6290 if (((insn & 0x0f70f000) == 0x0450f000) ||
6291 ((insn & 0x0f70f010) == 0x0650f000)) {
6292 ARCH(7);
6293 return; /* PLI; V7 */
6294 }
6295 if (((insn & 0x0f700000) == 0x04100000) ||
6296 ((insn & 0x0f700010) == 0x06100000)) {
6297 if (!arm_feature(env, ARM_FEATURE_V7MP)) {
6298 goto illegal_op;
6299 }
6300 return; /* v7MP: Unallocated memory hint: must NOP */
6301 }
6302
6303 if ((insn & 0x0ffffdff) == 0x01010000) {
9ee6e8bb
PB		 6304 ARCH(6);
6305 /* setend */
6306 if (insn & (1 << 9)) {
6307 /* BE8 mode not implemented. */
6308 goto illegal_op;
6309 }
6310 return;
6311 } else if ((insn & 0x0fffff00) == 0x057ff000) {
6312 switch ((insn >> 4) & 0xf) {
6313 case 1: /* clrex */
6314 ARCH(6K);
426f5abc 6315 gen_clrex(s);
9ee6e8bb
PB		 6316 return;
6317 case 4: /* dsb */
6318 case 5: /* dmb */
6319 case 6: /* isb */
6320 ARCH(7);
6321 /* We don't emulate caches so these are a no-op. */
6322 return;
6323 default:
6324 goto illegal_op;
6325 }
6326 } else if ((insn & 0x0e5fffe0) == 0x084d0500) {
6327 /* srs */
c67b6b71 6328 int32_t offset;
9ee6e8bb
PB		 6329 if (IS_USER(s))
6330 goto illegal_op;
6331 ARCH(6);
6332 op1 = (insn & 0x1f);
7d1b0095 6333 addr = tcg_temp_new_i32();
39ea3d4e
PM		 6334 tmp = tcg_const_i32(op1);
6335 gen_helper_get_r13_banked(addr, cpu_env, tmp);
6336 tcg_temp_free_i32(tmp);
9ee6e8bb
PB		 6337 i = (insn >> 23) & 3;
6338 switch (i) {
6339 case 0: offset = -4; break; /* DA */
c67b6b71
FN		 6340 case 1: offset = 0; break; /* IA */
6341 case 2: offset = -8; break; /* DB */
9ee6e8bb
PB		 6342 case 3: offset = 4; break; /* IB */
6343 default: abort();
6344 }
6345 if (offset)
b0109805
PB		 6346 tcg_gen_addi_i32(addr, addr, offset);
6347 tmp = load_reg(s, 14);
6348 gen_st32(tmp, addr, 0);
c67b6b71 6349 tmp = load_cpu_field(spsr);
b0109805
PB		 6350 tcg_gen_addi_i32(addr, addr, 4);
6351 gen_st32(tmp, addr, 0);
9ee6e8bb
PB		 6352 if (insn & (1 << 21)) {
6353 /* Base writeback. */
6354 switch (i) {
6355 case 0: offset = -8; break;
c67b6b71
FN		 6356 case 1: offset = 4; break;
6357 case 2: offset = -4; break;
9ee6e8bb
PB		 6358 case 3: offset = 0; break;
6359 default: abort();
6360 }
6361 if (offset)
c67b6b71 6362 tcg_gen_addi_i32(addr, addr, offset);
39ea3d4e
PM		 6363 tmp = tcg_const_i32(op1);
6364 gen_helper_set_r13_banked(cpu_env, tmp, addr);
6365 tcg_temp_free_i32(tmp);
7d1b0095 6366 tcg_temp_free_i32(addr);
b0109805 6367 } else {
7d1b0095 6368 tcg_temp_free_i32(addr);
9ee6e8bb 6369 }
a990f58f 6370 return;
ea825eee 6371 } else if ((insn & 0x0e50ffe0) == 0x08100a00) {
9ee6e8bb 6372 /* rfe */
c67b6b71 6373 int32_t offset;
9ee6e8bb
PB		 6374 if (IS_USER(s))
6375 goto illegal_op;
6376 ARCH(6);
6377 rn = (insn >> 16) & 0xf;
b0109805 6378 addr = load_reg(s, rn);
9ee6e8bb
PB		 6379 i = (insn >> 23) & 3;
6380 switch (i) {
b0109805 6381 case 0: offset = -4; break; /* DA */
c67b6b71
FN		 6382 case 1: offset = 0; break; /* IA */
6383 case 2: offset = -8; break; /* DB */
b0109805 6384 case 3: offset = 4; break; /* IB */
9ee6e8bb
PB		 6385 default: abort();
6386 }
6387 if (offset)
b0109805
PB		 6388 tcg_gen_addi_i32(addr, addr, offset);
6389 /* Load PC into tmp and CPSR into tmp2. */
6390 tmp = gen_ld32(addr, 0);
6391 tcg_gen_addi_i32(addr, addr, 4);
6392 tmp2 = gen_ld32(addr, 0);
9ee6e8bb
PB		 6393 if (insn & (1 << 21)) {
6394 /* Base writeback. */
6395 switch (i) {
b0109805 6396 case 0: offset = -8; break;
c67b6b71
FN		 6397 case 1: offset = 4; break;
6398 case 2: offset = -4; break;
b0109805 6399 case 3: offset = 0; break;
9ee6e8bb
PB		 6400 default: abort();
6401 }
6402 if (offset)
b0109805
PB		 6403 tcg_gen_addi_i32(addr, addr, offset);
6404 store_reg(s, rn, addr);
6405 } else {
7d1b0095 6406 tcg_temp_free_i32(addr);
9ee6e8bb 6407 }
b0109805 6408 gen_rfe(s, tmp, tmp2);
c67b6b71 6409 return;
9ee6e8bb
PB		 6410 } else if ((insn & 0x0e000000) == 0x0a000000) {
6411 /* branch link and change to thumb (blx <offset>) */
6412 int32_t offset;
6413
6414 val = (uint32_t)s->pc;
7d1b0095 6415 tmp = tcg_temp_new_i32();
d9ba4830
PB		 6416 tcg_gen_movi_i32(tmp, val);
6417 store_reg(s, 14, tmp);
9ee6e8bb
PB		 6418 /* Sign-extend the 24-bit offset */
6419 offset = (((int32_t)insn) << 8) >> 8;
6420 /* offset * 4 + bit24 * 2 + (thumb bit) */
6421 val += (offset << 2) | ((insn >> 23) & 2) | 1;
6422 /* pipeline offset */
6423 val += 4;
be5e7a76 6424 /* protected by ARCH(5); above, near the start of uncond block */
d9ba4830 6425 gen_bx_im(s, val);
9ee6e8bb
PB		 6426 return;
6427 } else if ((insn & 0x0e000f00) == 0x0c000100) {
6428 if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
6429 /* iWMMXt register transfer. */
6430 if (env->cp15.c15_cpar & (1 << 1))
6431 if (!disas_iwmmxt_insn(env, s, insn))
6432 return;
6433 }
6434 } else if ((insn & 0x0fe00000) == 0x0c400000) {
6435 /* Coprocessor double register transfer. */
be5e7a76 6436 ARCH(5TE);
9ee6e8bb
PB		 6437 } else if ((insn & 0x0f000010) == 0x0e000010) {
6438 /* Additional coprocessor register transfer. */
7997d92f 6439 } else if ((insn & 0x0ff10020) == 0x01000000) {
9ee6e8bb
PB		 6440 uint32_t mask;
6441 uint32_t val;
6442 /* cps (privileged) */
6443 if (IS_USER(s))
6444 return;
6445 mask = val = 0;
6446 if (insn & (1 << 19)) {
6447 if (insn & (1 << 8))
6448 mask |= CPSR_A;
6449 if (insn & (1 << 7))
6450 mask |= CPSR_I;
6451 if (insn & (1 << 6))
6452 mask |= CPSR_F;
6453 if (insn & (1 << 18))
6454 val |= mask;
6455 }
7997d92f 6456 if (insn & (1 << 17)) {
9ee6e8bb
PB		 6457 mask |= CPSR_M;
6458 val |= (insn & 0x1f);
6459 }
6460 if (mask) {
2fbac54b 6461 gen_set_psr_im(s, mask, 0, val);
9ee6e8bb
PB		 6462 }
6463 return;
6464 }
6465 goto illegal_op;
6466 }
6467 if (cond != 0xe) {
6468 /* if not always execute, we generate a conditional jump to
6469 next instruction */
6470 s->condlabel = gen_new_label();
d9ba4830 6471 gen_test_cc(cond ^ 1, s->condlabel);
9ee6e8bb
PB		 6472 s->condjmp = 1;
6473 }
6474 if ((insn & 0x0f900000) == 0x03000000) {
6475 if ((insn & (1 << 21)) == 0) {
6476 ARCH(6T2);
6477 rd = (insn >> 12) & 0xf;
6478 val = ((insn >> 4) & 0xf000) | (insn & 0xfff);
6479 if ((insn & (1 << 22)) == 0) {
6480 /* MOVW */
7d1b0095 6481 tmp = tcg_temp_new_i32();
5e3f878a 6482 tcg_gen_movi_i32(tmp, val);
9ee6e8bb
PB		 6483 } else {
6484 /* MOVT */
5e3f878a 6485 tmp = load_reg(s, rd);
86831435 6486 tcg_gen_ext16u_i32(tmp, tmp);
5e3f878a 6487 tcg_gen_ori_i32(tmp, tmp, val << 16);
9ee6e8bb 6488 }
5e3f878a 6489 store_reg(s, rd, tmp);
9ee6e8bb
PB		 6490 } else {
6491 if (((insn >> 12) & 0xf) != 0xf)
6492 goto illegal_op;
6493 if (((insn >> 16) & 0xf) == 0) {
6494 gen_nop_hint(s, insn & 0xff);
6495 } else {
6496 /* CPSR = immediate */
6497 val = insn & 0xff;
6498 shift = ((insn >> 8) & 0xf) * 2;
6499 if (shift)
6500 val = (val >> shift) | (val << (32 - shift));
9ee6e8bb 6501 i = ((insn & (1 << 22)) != 0);
2fbac54b 6502 if (gen_set_psr_im(s, msr_mask(env, s, (insn >> 16) & 0xf, i), i, val))
9ee6e8bb
PB		 6503 goto illegal_op;
6504 }
6505 }
6506 } else if ((insn & 0x0f900000) == 0x01000000
6507 && (insn & 0x00000090) != 0x00000090) {
6508 /* miscellaneous instructions */
6509 op1 = (insn >> 21) & 3;
6510 sh = (insn >> 4) & 0xf;
6511 rm = insn & 0xf;
6512 switch (sh) {
6513 case 0x0: /* move program status register */
6514 if (op1 & 1) {
6515 /* PSR = reg */
2fbac54b 6516 tmp = load_reg(s, rm);
9ee6e8bb 6517 i = ((op1 & 2) != 0);
2fbac54b 6518 if (gen_set_psr(s, msr_mask(env, s, (insn >> 16) & 0xf, i), i, tmp))
9ee6e8bb
PB		 6519 goto illegal_op;
6520 } else {
6521 /* reg = PSR */
6522 rd = (insn >> 12) & 0xf;
6523 if (op1 & 2) {
6524 if (IS_USER(s))
6525 goto illegal_op;
d9ba4830 6526 tmp = load_cpu_field(spsr);
9ee6e8bb 6527 } else {
7d1b0095 6528 tmp = tcg_temp_new_i32();
d9ba4830 6529 gen_helper_cpsr_read(tmp);
9ee6e8bb 6530 }
d9ba4830 6531 store_reg(s, rd, tmp);
9ee6e8bb
PB		 6532 }
6533 break;
6534 case 0x1:
6535 if (op1 == 1) {
6536 /* branch/exchange thumb (bx). */
be5e7a76 6537 ARCH(4T);
d9ba4830
PB		 6538 tmp = load_reg(s, rm);
6539 gen_bx(s, tmp);
9ee6e8bb
PB		 6540 } else if (op1 == 3) {
6541 /* clz */
be5e7a76 6542 ARCH(5);
9ee6e8bb 6543 rd = (insn >> 12) & 0xf;
1497c961
PB		 6544 tmp = load_reg(s, rm);
6545 gen_helper_clz(tmp, tmp);
6546 store_reg(s, rd, tmp);
9ee6e8bb
PB		 6547 } else {
6548 goto illegal_op;
6549 }
6550 break;
6551 case 0x2:
6552 if (op1 == 1) {
6553 ARCH(5J); /* bxj */
6554 /* Trivial implementation equivalent to bx. */
d9ba4830
PB		 6555 tmp = load_reg(s, rm);
6556 gen_bx(s, tmp);
9ee6e8bb
PB		 6557 } else {
6558 goto illegal_op;
6559 }
6560 break;
6561 case 0x3:
6562 if (op1 != 1)
6563 goto illegal_op;
6564
be5e7a76 6565 ARCH(5);
9ee6e8bb 6566 /* branch link/exchange thumb (blx) */
d9ba4830 6567 tmp = load_reg(s, rm);
7d1b0095 6568 tmp2 = tcg_temp_new_i32();
d9ba4830
PB		 6569 tcg_gen_movi_i32(tmp2, s->pc);
6570 store_reg(s, 14, tmp2);
6571 gen_bx(s, tmp);
9ee6e8bb
PB		 6572 break;
6573 case 0x5: /* saturating add/subtract */
be5e7a76 6574 ARCH(5TE);
9ee6e8bb
PB		 6575 rd = (insn >> 12) & 0xf;
6576 rn = (insn >> 16) & 0xf;
b40d0353 6577 tmp = load_reg(s, rm);
5e3f878a 6578 tmp2 = load_reg(s, rn);
9ee6e8bb 6579 if (op1 & 2)
5e3f878a 6580 gen_helper_double_saturate(tmp2, tmp2);
9ee6e8bb 6581 if (op1 & 1)
5e3f878a 6582 gen_helper_sub_saturate(tmp, tmp, tmp2);
9ee6e8bb 6583 else
5e3f878a 6584 gen_helper_add_saturate(tmp, tmp, tmp2);
7d1b0095 6585 tcg_temp_free_i32(tmp2);
5e3f878a 6586 store_reg(s, rd, tmp);
9ee6e8bb 6587 break;
49e14940
AL		 6588 case 7:
6589 /* SMC instruction (op1 == 3)
6590 and undefined instructions (op1 == 0 || op1 == 2)
6591 will trap */
6592 if (op1 != 1) {
6593 goto illegal_op;
6594 }
6595 /* bkpt */
be5e7a76 6596 ARCH(5);
bc4a0de0 6597 gen_exception_insn(s, 4, EXCP_BKPT);
9ee6e8bb
PB		 6598 break;
6599 case 0x8: /* signed multiply */
6600 case 0xa:
6601 case 0xc:
6602 case 0xe:
be5e7a76 6603 ARCH(5TE);
9ee6e8bb
PB		 6604 rs = (insn >> 8) & 0xf;
6605 rn = (insn >> 12) & 0xf;
6606 rd = (insn >> 16) & 0xf;
6607 if (op1 == 1) {
6608 /* (32 * 16) >> 16 */
5e3f878a
PB		 6609 tmp = load_reg(s, rm);
6610 tmp2 = load_reg(s, rs);
9ee6e8bb 6611 if (sh & 4)
5e3f878a 6612 tcg_gen_sari_i32(tmp2, tmp2, 16);
9ee6e8bb 6613 else
5e3f878a 6614 gen_sxth(tmp2);
a7812ae4
PB		 6615 tmp64 = gen_muls_i64_i32(tmp, tmp2);
6616 tcg_gen_shri_i64(tmp64, tmp64, 16);
7d1b0095 6617 tmp = tcg_temp_new_i32();
a7812ae4 6618 tcg_gen_trunc_i64_i32(tmp, tmp64);
b75263d6 6619 tcg_temp_free_i64(tmp64);
9ee6e8bb 6620 if ((sh & 2) == 0) {
5e3f878a
PB		 6621 tmp2 = load_reg(s, rn);
6622 gen_helper_add_setq(tmp, tmp, tmp2);
7d1b0095 6623 tcg_temp_free_i32(tmp2);
9ee6e8bb 6624 }
5e3f878a 6625 store_reg(s, rd, tmp);
9ee6e8bb
PB		 6626 } else {
6627 /* 16 * 16 */
5e3f878a
PB		 6628 tmp = load_reg(s, rm);
6629 tmp2 = load_reg(s, rs);
6630 gen_mulxy(tmp, tmp2, sh & 2, sh & 4);
7d1b0095 6631 tcg_temp_free_i32(tmp2);
9ee6e8bb 6632 if (op1 == 2) {
a7812ae4
PB		 6633 tmp64 = tcg_temp_new_i64();
6634 tcg_gen_ext_i32_i64(tmp64, tmp);
7d1b0095 6635 tcg_temp_free_i32(tmp);
a7812ae4
PB		 6636 gen_addq(s, tmp64, rn, rd);
6637 gen_storeq_reg(s, rn, rd, tmp64);
b75263d6 6638 tcg_temp_free_i64(tmp64);
9ee6e8bb
PB		 6639 } else {
6640 if (op1 == 0) {
5e3f878a
PB		 6641 tmp2 = load_reg(s, rn);
6642 gen_helper_add_setq(tmp, tmp, tmp2);
7d1b0095 6643 tcg_temp_free_i32(tmp2);
9ee6e8bb 6644 }
5e3f878a 6645 store_reg(s, rd, tmp);
9ee6e8bb
PB		 6646 }
6647 }
6648 break;
6649 default:
6650 goto illegal_op;
6651 }
6652 } else if (((insn & 0x0e000000) == 0 &&
6653 (insn & 0x00000090) != 0x90) ||
6654 ((insn & 0x0e000000) == (1 << 25))) {
6655 int set_cc, logic_cc, shiftop;
6656
6657 op1 = (insn >> 21) & 0xf;
6658 set_cc = (insn >> 20) & 1;
6659 logic_cc = table_logic_cc[op1] & set_cc;
6660
6661 /* data processing instruction */
6662 if (insn & (1 << 25)) {
6663 /* immediate operand */
6664 val = insn & 0xff;
6665 shift = ((insn >> 8) & 0xf) * 2;
e9bb4aa9 6666 if (shift) {
9ee6e8bb 6667 val = (val >> shift) | (val << (32 - shift));
e9bb4aa9 6668 }
7d1b0095 6669 tmp2 = tcg_temp_new_i32();
e9bb4aa9
JR		 6670 tcg_gen_movi_i32(tmp2, val);
6671 if (logic_cc && shift) {
6672 gen_set_CF_bit31(tmp2);
6673 }
9ee6e8bb
PB		 6674 } else {
6675 /* register */
6676 rm = (insn) & 0xf;
e9bb4aa9 6677 tmp2 = load_reg(s, rm);
9ee6e8bb
PB		 6678 shiftop = (insn >> 5) & 3;
6679 if (!(insn & (1 << 4))) {
6680 shift = (insn >> 7) & 0x1f;
e9bb4aa9 6681 gen_arm_shift_im(tmp2, shiftop, shift, logic_cc);
9ee6e8bb
PB		 6682 } else {
6683 rs = (insn >> 8) & 0xf;
8984bd2e 6684 tmp = load_reg(s, rs);
e9bb4aa9 6685 gen_arm_shift_reg(tmp2, shiftop, tmp, logic_cc);
9ee6e8bb
PB		 6686 }
6687 }
6688 if (op1 != 0x0f && op1 != 0x0d) {
6689 rn = (insn >> 16) & 0xf;
e9bb4aa9
JR		 6690 tmp = load_reg(s, rn);
6691 } else {
6692 TCGV_UNUSED(tmp);
9ee6e8bb
PB		 6693 }
6694 rd = (insn >> 12) & 0xf;
6695 switch(op1) {
6696 case 0x00:
e9bb4aa9
JR		 6697 tcg_gen_and_i32(tmp, tmp, tmp2);
6698 if (logic_cc) {
6699 gen_logic_CC(tmp);
6700 }
21aeb343 6701 store_reg_bx(env, s, rd, tmp);
9ee6e8bb
PB		 6702 break;
6703 case 0x01:
e9bb4aa9
JR		 6704 tcg_gen_xor_i32(tmp, tmp, tmp2);
6705 if (logic_cc) {
6706 gen_logic_CC(tmp);
6707 }
21aeb343 6708 store_reg_bx(env, s, rd, tmp);
9ee6e8bb
PB		 6709 break;
6710 case 0x02:
6711 if (set_cc && rd == 15) {
6712 /* SUBS r15, ... is used for exception return. */
e9bb4aa9 6713 if (IS_USER(s)) {
9ee6e8bb 6714 goto illegal_op;
e9bb4aa9
JR		 6715 }
6716 gen_helper_sub_cc(tmp, tmp, tmp2);
6717 gen_exception_return(s, tmp);
9ee6e8bb 6718 } else {
e9bb4aa9
JR		 6719 if (set_cc) {
6720 gen_helper_sub_cc(tmp, tmp, tmp2);
6721 } else {
6722 tcg_gen_sub_i32(tmp, tmp, tmp2);
6723 }
21aeb343 6724 store_reg_bx(env, s, rd, tmp);
9ee6e8bb
PB		 6725 }
6726 break;
6727 case 0x03:
e9bb4aa9
JR		 6728 if (set_cc) {
6729 gen_helper_sub_cc(tmp, tmp2, tmp);
6730 } else {
6731 tcg_gen_sub_i32(tmp, tmp2, tmp);
6732 }
21aeb343 6733 store_reg_bx(env, s, rd, tmp);
9ee6e8bb
PB		 6734 break;
6735 case 0x04:
e9bb4aa9
JR		 6736 if (set_cc) {
6737 gen_helper_add_cc(tmp, tmp, tmp2);
6738 } else {
6739 tcg_gen_add_i32(tmp, tmp, tmp2);
6740 }
21aeb343 6741 store_reg_bx(env, s, rd, tmp);
9ee6e8bb
PB		 6742 break;
6743 case 0x05:
e9bb4aa9
JR		 6744 if (set_cc) {
6745 gen_helper_adc_cc(tmp, tmp, tmp2);
6746 } else {
6747 gen_add_carry(tmp, tmp, tmp2);
6748 }
21aeb343 6749 store_reg_bx(env, s, rd, tmp);
9ee6e8bb
PB		 6750 break;
6751 case 0x06:
e9bb4aa9
JR		 6752 if (set_cc) {
6753 gen_helper_sbc_cc(tmp, tmp, tmp2);
6754 } else {
6755 gen_sub_carry(tmp, tmp, tmp2);
6756 }
21aeb343 6757 store_reg_bx(env, s, rd, tmp);
9ee6e8bb
PB		 6758 break;
6759 case 0x07:
e9bb4aa9
JR		 6760 if (set_cc) {
6761 gen_helper_sbc_cc(tmp, tmp2, tmp);
6762 } else {
6763 gen_sub_carry(tmp, tmp2, tmp);
6764 }
21aeb343 6765 store_reg_bx(env, s, rd, tmp);
9ee6e8bb
PB		 6766 break;
6767 case 0x08:
6768 if (set_cc) {
e9bb4aa9
JR		 6769 tcg_gen_and_i32(tmp, tmp, tmp2);
6770 gen_logic_CC(tmp);
9ee6e8bb 6771 }
7d1b0095 6772 tcg_temp_free_i32(tmp);
9ee6e8bb
PB		 6773 break;
6774 case 0x09:
6775 if (set_cc) {
e9bb4aa9
JR		 6776 tcg_gen_xor_i32(tmp, tmp, tmp2);
6777 gen_logic_CC(tmp);
9ee6e8bb 6778 }
7d1b0095 6779 tcg_temp_free_i32(tmp);
9ee6e8bb
PB		 6780 break;
6781 case 0x0a:
6782 if (set_cc) {
e9bb4aa9 6783 gen_helper_sub_cc(tmp, tmp, tmp2);
9ee6e8bb 6784 }
7d1b0095 6785 tcg_temp_free_i32(tmp);
9ee6e8bb
PB		 6786 break;
6787 case 0x0b:
6788 if (set_cc) {
e9bb4aa9 6789 gen_helper_add_cc(tmp, tmp, tmp2);
9ee6e8bb 6790 }
7d1b0095 6791 tcg_temp_free_i32(tmp);
9ee6e8bb
PB		 6792 break;
6793 case 0x0c:
e9bb4aa9
JR		 6794 tcg_gen_or_i32(tmp, tmp, tmp2);
6795 if (logic_cc) {
6796 gen_logic_CC(tmp);
6797 }
21aeb343 6798 store_reg_bx(env, s, rd, tmp);
9ee6e8bb
PB		 6799 break;
6800 case 0x0d:
6801 if (logic_cc && rd == 15) {
6802 /* MOVS r15, ... is used for exception return. */
e9bb4aa9 6803 if (IS_USER(s)) {
9ee6e8bb 6804 goto illegal_op;
e9bb4aa9
JR		 6805 }
6806 gen_exception_return(s, tmp2);
9ee6e8bb 6807 } else {
e9bb4aa9
JR		 6808 if (logic_cc) {
6809 gen_logic_CC(tmp2);
6810 }
21aeb343 6811 store_reg_bx(env, s, rd, tmp2);
9ee6e8bb
PB		 6812 }
6813 break;
6814 case 0x0e:
f669df27 6815 tcg_gen_andc_i32(tmp, tmp, tmp2);
e9bb4aa9
JR		 6816 if (logic_cc) {
6817 gen_logic_CC(tmp);
6818 }
21aeb343 6819 store_reg_bx(env, s, rd, tmp);
9ee6e8bb
PB		 6820 break;
6821 default:
6822 case 0x0f:
e9bb4aa9
JR		 6823 tcg_gen_not_i32(tmp2, tmp2);
6824 if (logic_cc) {
6825 gen_logic_CC(tmp2);
6826 }
21aeb343 6827 store_reg_bx(env, s, rd, tmp2);
9ee6e8bb
PB		 6828 break;
6829 }
e9bb4aa9 6830 if (op1 != 0x0f && op1 != 0x0d) {
7d1b0095 6831 tcg_temp_free_i32(tmp2);
e9bb4aa9 6832 }
9ee6e8bb
PB		 6833 } else {
6834 /* other instructions */
6835 op1 = (insn >> 24) & 0xf;
6836 switch(op1) {
6837 case 0x0:
6838 case 0x1:
6839 /* multiplies, extra load/stores */
6840 sh = (insn >> 5) & 3;
6841 if (sh == 0) {
6842 if (op1 == 0x0) {
6843 rd = (insn >> 16) & 0xf;
6844 rn = (insn >> 12) & 0xf;
6845 rs = (insn >> 8) & 0xf;
6846 rm = (insn) & 0xf;
6847 op1 = (insn >> 20) & 0xf;
6848 switch (op1) {
6849 case 0: case 1: case 2: case 3: case 6:
6850 /* 32 bit mul */
5e3f878a
PB		 6851 tmp = load_reg(s, rs);
6852 tmp2 = load_reg(s, rm);
6853 tcg_gen_mul_i32(tmp, tmp, tmp2);
7d1b0095 6854 tcg_temp_free_i32(tmp2);
9ee6e8bb
PB		 6855 if (insn & (1 << 22)) {
6856 /* Subtract (mls) */
6857 ARCH(6T2);
5e3f878a
PB		 6858 tmp2 = load_reg(s, rn);
6859 tcg_gen_sub_i32(tmp, tmp2, tmp);
7d1b0095 6860 tcg_temp_free_i32(tmp2);
9ee6e8bb
PB		 6861 } else if (insn & (1 << 21)) {
6862 /* Add */
5e3f878a
PB		 6863 tmp2 = load_reg(s, rn);
6864 tcg_gen_add_i32(tmp, tmp, tmp2);
7d1b0095 6865 tcg_temp_free_i32(tmp2);
9ee6e8bb
PB		 6866 }
6867 if (insn & (1 << 20))
5e3f878a
PB		 6868 gen_logic_CC(tmp);
6869 store_reg(s, rd, tmp);
9ee6e8bb 6870 break;
8aac08b1
AJ		 6871 case 4:
6872 /* 64 bit mul double accumulate (UMAAL) */
6873 ARCH(6);
6874 tmp = load_reg(s, rs);
6875 tmp2 = load_reg(s, rm);
6876 tmp64 = gen_mulu_i64_i32(tmp, tmp2);
6877 gen_addq_lo(s, tmp64, rn);
6878 gen_addq_lo(s, tmp64, rd);
6879 gen_storeq_reg(s, rn, rd, tmp64);
6880 tcg_temp_free_i64(tmp64);
6881 break;
6882 case 8: case 9: case 10: case 11:
6883 case 12: case 13: case 14: case 15:
6884 /* 64 bit mul: UMULL, UMLAL, SMULL, SMLAL. */
5e3f878a
PB		 6885 tmp = load_reg(s, rs);
6886 tmp2 = load_reg(s, rm);
8aac08b1 6887 if (insn & (1 << 22)) {
a7812ae4 6888 tmp64 = gen_muls_i64_i32(tmp, tmp2);
8aac08b1 6889 } else {
a7812ae4 6890 tmp64 = gen_mulu_i64_i32(tmp, tmp2);
8aac08b1
AJ		 6891 }
6892 if (insn & (1 << 21)) { /* mult accumulate */
a7812ae4 6893 gen_addq(s, tmp64, rn, rd);
9ee6e8bb 6894 }
8aac08b1 6895 if (insn & (1 << 20)) {
a7812ae4 6896 gen_logicq_cc(tmp64);
8aac08b1 6897 }
a7812ae4 6898 gen_storeq_reg(s, rn, rd, tmp64);
b75263d6 6899 tcg_temp_free_i64(tmp64);
9ee6e8bb 6900 break;
8aac08b1
AJ		 6901 default:
6902 goto illegal_op;
9ee6e8bb
PB		 6903 }
6904 } else {
6905 rn = (insn >> 16) & 0xf;
6906 rd = (insn >> 12) & 0xf;
6907 if (insn & (1 << 23)) {
6908 /* load/store exclusive */
86753403
PB		 6909 op1 = (insn >> 21) & 0x3;
6910 if (op1)
a47f43d2 6911 ARCH(6K);
86753403
PB		 6912 else
6913 ARCH(6);
3174f8e9 6914 addr = tcg_temp_local_new_i32();
98a46317 6915 load_reg_var(s, addr, rn);
9ee6e8bb 6916 if (insn & (1 << 20)) {
86753403
PB		 6917 switch (op1) {
6918 case 0: /* ldrex */
426f5abc 6919 gen_load_exclusive(s, rd, 15, addr, 2);
86753403
PB		 6920 break;
6921 case 1: /* ldrexd */
426f5abc 6922 gen_load_exclusive(s, rd, rd + 1, addr, 3);
86753403
PB		 6923 break;
6924 case 2: /* ldrexb */
426f5abc 6925 gen_load_exclusive(s, rd, 15, addr, 0);
86753403
PB		 6926 break;
6927 case 3: /* ldrexh */
426f5abc 6928 gen_load_exclusive(s, rd, 15, addr, 1);
86753403
PB		 6929 break;
6930 default:
6931 abort();
6932 }
9ee6e8bb
PB		 6933 } else {
6934 rm = insn & 0xf;
86753403
PB		 6935 switch (op1) {
6936 case 0: /* strex */
426f5abc 6937 gen_store_exclusive(s, rd, rm, 15, addr, 2);
86753403
PB		 6938 break;
6939 case 1: /* strexd */
502e64fe 6940 gen_store_exclusive(s, rd, rm, rm + 1, addr, 3);
86753403
PB		 6941 break;
6942 case 2: /* strexb */
426f5abc 6943 gen_store_exclusive(s, rd, rm, 15, addr, 0);
86753403
PB		 6944 break;
6945 case 3: /* strexh */
426f5abc 6946 gen_store_exclusive(s, rd, rm, 15, addr, 1);
86753403
PB		 6947 break;
6948 default:
6949 abort();
6950 }
9ee6e8bb 6951 }
3174f8e9 6952 tcg_temp_free(addr);
9ee6e8bb
PB		 6953 } else {
6954 /* SWP instruction */
6955 rm = (insn) & 0xf;
6956
8984bd2e
PB		 6957 /* ??? This is not really atomic. However we know
6958 we never have multiple CPUs running in parallel,
6959 so it is good enough. */
6960 addr = load_reg(s, rn);
6961 tmp = load_reg(s, rm);
9ee6e8bb 6962 if (insn & (1 << 22)) {
8984bd2e
PB		 6963 tmp2 = gen_ld8u(addr, IS_USER(s));
6964 gen_st8(tmp, addr, IS_USER(s));
9ee6e8bb 6965 } else {
8984bd2e
PB		 6966 tmp2 = gen_ld32(addr, IS_USER(s));
6967 gen_st32(tmp, addr, IS_USER(s));
9ee6e8bb 6968 }
7d1b0095 6969 tcg_temp_free_i32(addr);
8984bd2e 6970 store_reg(s, rd, tmp2);
9ee6e8bb
PB		 6971 }
6972 }
6973 } else {
6974 int address_offset;
6975 int load;
6976 /* Misc load/store */
6977 rn = (insn >> 16) & 0xf;
6978 rd = (insn >> 12) & 0xf;
b0109805 6979 addr = load_reg(s, rn);
9ee6e8bb 6980 if (insn & (1 << 24))
b0109805 6981 gen_add_datah_offset(s, insn, 0, addr);
9ee6e8bb
PB		 6982 address_offset = 0;
6983 if (insn & (1 << 20)) {
6984 /* load */
6985 switch(sh) {
6986 case 1:
b0109805 6987 tmp = gen_ld16u(addr, IS_USER(s));
9ee6e8bb
PB		 6988 break;
6989 case 2:
b0109805 6990 tmp = gen_ld8s(addr, IS_USER(s));
9ee6e8bb
PB		 6991 break;
6992 default:
6993 case 3:
b0109805 6994 tmp = gen_ld16s(addr, IS_USER(s));
9ee6e8bb
PB		 6995 break;
6996 }
6997 load = 1;
6998 } else if (sh & 2) {
be5e7a76 6999 ARCH(5TE);
9ee6e8bb
PB		 7000 /* doubleword */
7001 if (sh & 1) {
7002 /* store */
b0109805
PB		 7003 tmp = load_reg(s, rd);
7004 gen_st32(tmp, addr, IS_USER(s));
7005 tcg_gen_addi_i32(addr, addr, 4);
7006 tmp = load_reg(s, rd + 1);
7007 gen_st32(tmp, addr, IS_USER(s));
9ee6e8bb
PB		 7008 load = 0;
7009 } else {
7010 /* load */
b0109805
PB		 7011 tmp = gen_ld32(addr, IS_USER(s));
7012 store_reg(s, rd, tmp);
7013 tcg_gen_addi_i32(addr, addr, 4);
7014 tmp = gen_ld32(addr, IS_USER(s));
9ee6e8bb
PB		 7015 rd++;
7016 load = 1;
7017 }
7018 address_offset = -4;
7019 } else {
7020 /* store */
b0109805
PB		 7021 tmp = load_reg(s, rd);
7022 gen_st16(tmp, addr, IS_USER(s));
9ee6e8bb
PB		 7023 load = 0;
7024 }
7025 /* Perform base writeback before the loaded value to
7026 ensure correct behavior with overlapping index registers.
7027 ldrd with base writeback is is undefined if the
7028 destination and index registers overlap. */
7029 if (!(insn & (1 << 24))) {
b0109805
PB		 7030 gen_add_datah_offset(s, insn, address_offset, addr);
7031 store_reg(s, rn, addr);
9ee6e8bb
PB		 7032 } else if (insn & (1 << 21)) {
7033 if (address_offset)
b0109805
PB		 7034 tcg_gen_addi_i32(addr, addr, address_offset);
7035 store_reg(s, rn, addr);
7036 } else {
7d1b0095 7037 tcg_temp_free_i32(addr);
9ee6e8bb
PB		 7038 }
7039 if (load) {
7040 /* Complete the load. */
b0109805 7041 store_reg(s, rd, tmp);
9ee6e8bb
PB		 7042 }
7043 }
7044 break;
7045 case 0x4:
7046 case 0x5:
7047 goto do_ldst;
7048 case 0x6:
7049 case 0x7:
7050 if (insn & (1 << 4)) {
7051 ARCH(6);
7052 /* Armv6 Media instructions. */
7053 rm = insn & 0xf;
7054 rn = (insn >> 16) & 0xf;
2c0262af 7055 rd = (insn >> 12) & 0xf;
9ee6e8bb
PB		 7056 rs = (insn >> 8) & 0xf;
7057 switch ((insn >> 23) & 3) {
7058 case 0: /* Parallel add/subtract. */
7059 op1 = (insn >> 20) & 7;
6ddbc6e4
PB		 7060 tmp = load_reg(s, rn);
7061 tmp2 = load_reg(s, rm);
9ee6e8bb
PB		 7062 sh = (insn >> 5) & 7;
7063 if ((op1 & 3) == 0 || sh == 5 || sh == 6)
7064 goto illegal_op;
6ddbc6e4 7065 gen_arm_parallel_addsub(op1, sh, tmp, tmp2);
7d1b0095 7066 tcg_temp_free_i32(tmp2);
6ddbc6e4 7067 store_reg(s, rd, tmp);
9ee6e8bb
PB		 7068 break;
7069 case 1:
7070 if ((insn & 0x00700020) == 0) {
6c95676b 7071 /* Halfword pack. */
3670669c
PB		 7072 tmp = load_reg(s, rn);
7073 tmp2 = load_reg(s, rm);
9ee6e8bb 7074 shift = (insn >> 7) & 0x1f;
3670669c
PB		 7075 if (insn & (1 << 6)) {
7076 /* pkhtb */
22478e79
AZ		 7077 if (shift == 0)
7078 shift = 31;
7079 tcg_gen_sari_i32(tmp2, tmp2, shift);
3670669c 7080 tcg_gen_andi_i32(tmp, tmp, 0xffff0000);
86831435 7081 tcg_gen_ext16u_i32(tmp2, tmp2);
3670669c
PB		 7082 } else {
7083 /* pkhbt */
22478e79
AZ		 7084 if (shift)
7085 tcg_gen_shli_i32(tmp2, tmp2, shift);
86831435 7086 tcg_gen_ext16u_i32(tmp, tmp);
3670669c
PB		 7087 tcg_gen_andi_i32(tmp2, tmp2, 0xffff0000);
7088 }
7089 tcg_gen_or_i32(tmp, tmp, tmp2);
7d1b0095 7090 tcg_temp_free_i32(tmp2);
3670669c 7091 store_reg(s, rd, tmp);
9ee6e8bb
PB		 7092 } else if ((insn & 0x00200020) == 0x00200000) {
7093 /* [us]sat */
6ddbc6e4 7094 tmp = load_reg(s, rm);
9ee6e8bb
PB		 7095 shift = (insn >> 7) & 0x1f;
7096 if (insn & (1 << 6)) {
7097 if (shift == 0)
7098 shift = 31;
6ddbc6e4 7099 tcg_gen_sari_i32(tmp, tmp, shift);
9ee6e8bb 7100 } else {
6ddbc6e4 7101 tcg_gen_shli_i32(tmp, tmp, shift);
9ee6e8bb
PB		 7102 }
7103 sh = (insn >> 16) & 0x1f;
40d3c433
CL		 7104 tmp2 = tcg_const_i32(sh);
7105 if (insn & (1 << 22))
7106 gen_helper_usat(tmp, tmp, tmp2);
7107 else
7108 gen_helper_ssat(tmp, tmp, tmp2);
7109 tcg_temp_free_i32(tmp2);
6ddbc6e4 7110 store_reg(s, rd, tmp);
9ee6e8bb
PB		 7111 } else if ((insn & 0x00300fe0) == 0x00200f20) {
7112 /* [us]sat16 */
6ddbc6e4 7113 tmp = load_reg(s, rm);
9ee6e8bb 7114 sh = (insn >> 16) & 0x1f;
40d3c433
CL		 7115 tmp2 = tcg_const_i32(sh);
7116 if (insn & (1 << 22))
7117 gen_helper_usat16(tmp, tmp, tmp2);
7118 else
7119 gen_helper_ssat16(tmp, tmp, tmp2);
7120 tcg_temp_free_i32(tmp2);
6ddbc6e4 7121 store_reg(s, rd, tmp);
9ee6e8bb
PB		 7122 } else if ((insn & 0x00700fe0) == 0x00000fa0) {
7123 /* Select bytes. */
6ddbc6e4
PB		 7124 tmp = load_reg(s, rn);
7125 tmp2 = load_reg(s, rm);
7d1b0095 7126 tmp3 = tcg_temp_new_i32();
6ddbc6e4
PB		 7127 tcg_gen_ld_i32(tmp3, cpu_env, offsetof(CPUState, GE));
7128 gen_helper_sel_flags(tmp, tmp3, tmp, tmp2);
7d1b0095
PM		 7129 tcg_temp_free_i32(tmp3);
7130 tcg_temp_free_i32(tmp2);
6ddbc6e4 7131 store_reg(s, rd, tmp);
9ee6e8bb 7132 } else if ((insn & 0x000003e0) == 0x00000060) {
5e3f878a 7133 tmp = load_reg(s, rm);
9ee6e8bb
PB		 7134 shift = (insn >> 10) & 3;
7135 /* ??? In many cases it's not neccessary to do a
7136 rotate, a shift is sufficient. */
7137 if (shift != 0)
f669df27 7138 tcg_gen_rotri_i32(tmp, tmp, shift * 8);
9ee6e8bb
PB		 7139 op1 = (insn >> 20) & 7;
7140 switch (op1) {
5e3f878a
PB		 7141 case 0: gen_sxtb16(tmp); break;
7142 case 2: gen_sxtb(tmp); break;
7143 case 3: gen_sxth(tmp); break;
7144 case 4: gen_uxtb16(tmp); break;
7145 case 6: gen_uxtb(tmp); break;
7146 case 7: gen_uxth(tmp); break;
9ee6e8bb
PB		 7147 default: goto illegal_op;
7148 }
7149 if (rn != 15) {
5e3f878a 7150 tmp2 = load_reg(s, rn);
9ee6e8bb 7151 if ((op1 & 3) == 0) {
5e3f878a 7152 gen_add16(tmp, tmp2);
9ee6e8bb 7153 } else {
5e3f878a 7154 tcg_gen_add_i32(tmp, tmp, tmp2);
7d1b0095 7155 tcg_temp_free_i32(tmp2);
9ee6e8bb
PB		 7156 }
7157 }
6c95676b 7158 store_reg(s, rd, tmp);
9ee6e8bb
PB		 7159 } else if ((insn & 0x003f0f60) == 0x003f0f20) {
7160 /* rev */
b0109805 7161 tmp = load_reg(s, rm);
9ee6e8bb
PB		 7162 if (insn & (1 << 22)) {
7163 if (insn & (1 << 7)) {
b0109805 7164 gen_revsh(tmp);
9ee6e8bb
PB		 7165 } else {
7166 ARCH(6T2);
b0109805 7167 gen_helper_rbit(tmp, tmp);
9ee6e8bb
PB		 7168 }
7169 } else {
7170 if (insn & (1 << 7))
b0109805 7171 gen_rev16(tmp);
9ee6e8bb 7172 else
66896cb8 7173 tcg_gen_bswap32_i32(tmp, tmp);
9ee6e8bb 7174 }
b0109805 7175 store_reg(s, rd, tmp);
9ee6e8bb
PB		 7176 } else {
7177 goto illegal_op;
7178 }
7179 break;
7180 case 2: /* Multiplies (Type 3). */
5e3f878a
PB		 7181 tmp = load_reg(s, rm);
7182 tmp2 = load_reg(s, rs);
9ee6e8bb 7183 if (insn & (1 << 20)) {
838fa72d
AJ		 7184 /* Signed multiply most significant [accumulate].
7185 (SMMUL, SMMLA, SMMLS) */
a7812ae4 7186 tmp64 = gen_muls_i64_i32(tmp, tmp2);
838fa72d 7187
955a7dd5 7188 if (rd != 15) {
838fa72d 7189 tmp = load_reg(s, rd);
9ee6e8bb 7190 if (insn & (1 << 6)) {
838fa72d 7191 tmp64 = gen_subq_msw(tmp64, tmp);
9ee6e8bb 7192 } else {
838fa72d 7193 tmp64 = gen_addq_msw(tmp64, tmp);
9ee6e8bb
PB		 7194 }
7195 }
838fa72d
AJ		 7196 if (insn & (1 << 5)) {
7197 tcg_gen_addi_i64(tmp64, tmp64, 0x80000000u);
7198 }
7199 tcg_gen_shri_i64(tmp64, tmp64, 32);
7d1b0095 7200 tmp = tcg_temp_new_i32();
838fa72d
AJ		 7201 tcg_gen_trunc_i64_i32(tmp, tmp64);
7202 tcg_temp_free_i64(tmp64);
955a7dd5 7203 store_reg(s, rn, tmp);
9ee6e8bb
PB		 7204 } else {
7205 if (insn & (1 << 5))
5e3f878a
PB		 7206 gen_swap_half(tmp2);
7207 gen_smul_dual(tmp, tmp2);
5e3f878a 7208 if (insn & (1 << 6)) {
e1d177b9 7209 /* This subtraction cannot overflow. */
5e3f878a
PB		 7210 tcg_gen_sub_i32(tmp, tmp, tmp2);
7211 } else {
e1d177b9
PM		 7212 /* This addition cannot overflow 32 bits;
7213 * however it may overflow considered as a signed
7214 * operation, in which case we must set the Q flag.
7215 */
7216 gen_helper_add_setq(tmp, tmp, tmp2);
5e3f878a 7217 }
7d1b0095 7218 tcg_temp_free_i32(tmp2);
9ee6e8bb 7219 if (insn & (1 << 22)) {
5e3f878a 7220 /* smlald, smlsld */
a7812ae4
PB		 7221 tmp64 = tcg_temp_new_i64();
7222 tcg_gen_ext_i32_i64(tmp64, tmp);
7d1b0095 7223 tcg_temp_free_i32(tmp);
a7812ae4
PB		 7224 gen_addq(s, tmp64, rd, rn);
7225 gen_storeq_reg(s, rd, rn, tmp64);
b75263d6 7226 tcg_temp_free_i64(tmp64);
9ee6e8bb 7227 } else {
5e3f878a 7228 /* smuad, smusd, smlad, smlsd */
22478e79 7229 if (rd != 15)
9ee6e8bb 7230 {
22478e79 7231 tmp2 = load_reg(s, rd);
5e3f878a 7232 gen_helper_add_setq(tmp, tmp, tmp2);
7d1b0095 7233 tcg_temp_free_i32(tmp2);
9ee6e8bb 7234 }
22478e79 7235 store_reg(s, rn, tmp);
9ee6e8bb
PB		 7236 }
7237 }
7238 break;
7239 case 3:
7240 op1 = ((insn >> 17) & 0x38) | ((insn >> 5) & 7);
7241 switch (op1) {
7242 case 0: /* Unsigned sum of absolute differences. */
6ddbc6e4
PB		 7243 ARCH(6);
7244 tmp = load_reg(s, rm);
7245 tmp2 = load_reg(s, rs);
7246 gen_helper_usad8(tmp, tmp, tmp2);
7d1b0095 7247 tcg_temp_free_i32(tmp2);
ded9d295
AZ		 7248 if (rd != 15) {
7249 tmp2 = load_reg(s, rd);
6ddbc6e4 7250 tcg_gen_add_i32(tmp, tmp, tmp2);
7d1b0095 7251 tcg_temp_free_i32(tmp2);
9ee6e8bb 7252 }
ded9d295 7253 store_reg(s, rn, tmp);
9ee6e8bb
PB		 7254 break;
7255 case 0x20: case 0x24: case 0x28: case 0x2c:
7256 /* Bitfield insert/clear. */
7257 ARCH(6T2);
7258 shift = (insn >> 7) & 0x1f;
7259 i = (insn >> 16) & 0x1f;
7260 i = i + 1 - shift;
7261 if (rm == 15) {
7d1b0095 7262 tmp = tcg_temp_new_i32();
5e3f878a 7263 tcg_gen_movi_i32(tmp, 0);
9ee6e8bb 7264 } else {
5e3f878a 7265 tmp = load_reg(s, rm);
9ee6e8bb
PB		 7266 }
7267 if (i != 32) {
5e3f878a 7268 tmp2 = load_reg(s, rd);
8f8e3aa4 7269 gen_bfi(tmp, tmp2, tmp, shift, (1u << i) - 1);
7d1b0095 7270 tcg_temp_free_i32(tmp2);
9ee6e8bb 7271 }
5e3f878a 7272 store_reg(s, rd, tmp);
9ee6e8bb
PB		 7273 break;
7274 case 0x12: case 0x16: case 0x1a: case 0x1e: /* sbfx */
7275 case 0x32: case 0x36: case 0x3a: case 0x3e: /* ubfx */
4cc633c3 7276 ARCH(6T2);
5e3f878a 7277 tmp = load_reg(s, rm);
9ee6e8bb
PB		 7278 shift = (insn >> 7) & 0x1f;
7279 i = ((insn >> 16) & 0x1f) + 1;
7280 if (shift + i > 32)
7281 goto illegal_op;
7282 if (i < 32) {
7283 if (op1 & 0x20) {
5e3f878a 7284 gen_ubfx(tmp, shift, (1u << i) - 1);
9ee6e8bb 7285 } else {
5e3f878a 7286 gen_sbfx(tmp, shift, i);
9ee6e8bb
PB		 7287 }
7288 }
5e3f878a 7289 store_reg(s, rd, tmp);
9ee6e8bb
PB		 7290 break;
7291 default:
7292 goto illegal_op;
7293 }
7294 break;
7295 }
7296 break;
7297 }
7298 do_ldst:
7299 /* Check for undefined extension instructions
7300 * per the ARM Bible IE:
7301 * xxxx 0111 1111 xxxx xxxx xxxx 1111 xxxx
7302 */
7303 sh = (0xf << 20) | (0xf << 4);
7304 if (op1 == 0x7 && ((insn & sh) == sh))
7305 {
7306 goto illegal_op;
7307 }
7308 /* load/store byte/word */
7309 rn = (insn >> 16) & 0xf;
7310 rd = (insn >> 12) & 0xf;
b0109805 7311 tmp2 = load_reg(s, rn);
9ee6e8bb
PB		 7312 i = (IS_USER(s) || (insn & 0x01200000) == 0x00200000);
7313 if (insn & (1 << 24))
b0109805 7314 gen_add_data_offset(s, insn, tmp2);
9ee6e8bb
PB		 7315 if (insn & (1 << 20)) {
7316 /* load */
9ee6e8bb 7317 if (insn & (1 << 22)) {
b0109805 7318 tmp = gen_ld8u(tmp2, i);
9ee6e8bb 7319 } else {
b0109805 7320 tmp = gen_ld32(tmp2, i);
9ee6e8bb 7321 }
9ee6e8bb
PB		 7322 } else {
7323 /* store */
b0109805 7324 tmp = load_reg(s, rd);
9ee6e8bb 7325 if (insn & (1 << 22))
b0109805 7326 gen_st8(tmp, tmp2, i);
9ee6e8bb 7327 else
b0109805 7328 gen_st32(tmp, tmp2, i);
9ee6e8bb
PB		 7329 }
7330 if (!(insn & (1 << 24))) {
b0109805
PB		 7331 gen_add_data_offset(s, insn, tmp2);
7332 store_reg(s, rn, tmp2);
7333 } else if (insn & (1 << 21)) {
7334 store_reg(s, rn, tmp2);
7335 } else {
7d1b0095 7336 tcg_temp_free_i32(tmp2);
9ee6e8bb
PB		 7337 }
7338 if (insn & (1 << 20)) {
7339 /* Complete the load. */
be5e7a76 7340 store_reg_from_load(env, s, rd, tmp);
9ee6e8bb
PB		 7341 }
7342 break;
7343 case 0x08:
7344 case 0x09:
7345 {
7346 int j, n, user, loaded_base;
b0109805 7347 TCGv loaded_var;
9ee6e8bb
PB		 7348 /* load/store multiple words */
7349 /* XXX: store correct base if write back */
7350 user = 0;
7351 if (insn & (1 << 22)) {
7352 if (IS_USER(s))
7353 goto illegal_op; /* only usable in supervisor mode */
7354
7355 if ((insn & (1 << 15)) == 0)
7356 user = 1;
7357 }
7358 rn = (insn >> 16) & 0xf;
b0109805 7359 addr = load_reg(s, rn);
9ee6e8bb
PB		 7360
7361 /* compute total size */
7362 loaded_base = 0;
a50f5b91 7363 TCGV_UNUSED(loaded_var);
9ee6e8bb
PB		 7364 n = 0;
7365 for(i=0;i<16;i++) {
7366 if (insn & (1 << i))
7367 n++;
7368 }
7369 /* XXX: test invalid n == 0 case ? */
7370 if (insn & (1 << 23)) {
7371 if (insn & (1 << 24)) {
7372 /* pre increment */
b0109805 7373 tcg_gen_addi_i32(addr, addr, 4);
9ee6e8bb
PB		 7374 } else {
7375 /* post increment */
7376 }
7377 } else {
7378 if (insn & (1 << 24)) {
7379 /* pre decrement */
b0109805 7380 tcg_gen_addi_i32(addr, addr, -(n * 4));
9ee6e8bb
PB		 7381 } else {
7382 /* post decrement */
7383 if (n != 1)
b0109805 7384 tcg_gen_addi_i32(addr, addr, -((n - 1) * 4));
9ee6e8bb
PB		 7385 }
7386 }
7387 j = 0;
7388 for(i=0;i<16;i++) {
7389 if (insn & (1 << i)) {
7390 if (insn & (1 << 20)) {
7391 /* load */
b0109805 7392 tmp = gen_ld32(addr, IS_USER(s));
be5e7a76 7393 if (user) {
b75263d6
JR		 7394 tmp2 = tcg_const_i32(i);
7395 gen_helper_set_user_reg(tmp2, tmp);
7396 tcg_temp_free_i32(tmp2);
7d1b0095 7397 tcg_temp_free_i32(tmp);
9ee6e8bb 7398 } else if (i == rn) {
b0109805 7399 loaded_var = tmp;
9ee6e8bb
PB		 7400 loaded_base = 1;
7401 } else {
be5e7a76 7402 store_reg_from_load(env, s, i, tmp);
9ee6e8bb
PB		 7403 }
7404 } else {
7405 /* store */
7406 if (i == 15) {
7407 /* special case: r15 = PC + 8 */
7408 val = (long)s->pc + 4;
7d1b0095 7409 tmp = tcg_temp_new_i32();
b0109805 7410 tcg_gen_movi_i32(tmp, val);
9ee6e8bb 7411 } else if (user) {
7d1b0095 7412 tmp = tcg_temp_new_i32();
b75263d6
JR		 7413 tmp2 = tcg_const_i32(i);
7414 gen_helper_get_user_reg(tmp, tmp2);
7415 tcg_temp_free_i32(tmp2);
9ee6e8bb 7416 } else {
b0109805 7417 tmp = load_reg(s, i);
9ee6e8bb 7418 }
b0109805 7419 gen_st32(tmp, addr, IS_USER(s));
9ee6e8bb
PB		 7420 }
7421 j++;
7422 /* no need to add after the last transfer */
7423 if (j != n)
b0109805 7424 tcg_gen_addi_i32(addr, addr, 4);
9ee6e8bb
PB		 7425 }
7426 }
7427 if (insn & (1 << 21)) {
7428 /* write back */
7429 if (insn & (1 << 23)) {
7430 if (insn & (1 << 24)) {
7431 /* pre increment */
7432 } else {
7433 /* post increment */
b0109805 7434 tcg_gen_addi_i32(addr, addr, 4);
9ee6e8bb
PB		 7435 }
7436 } else {
7437 if (insn & (1 << 24)) {
7438 /* pre decrement */
7439 if (n != 1)
b0109805 7440 tcg_gen_addi_i32(addr, addr, -((n - 1) * 4));
9ee6e8bb
PB		 7441 } else {
7442 /* post decrement */
b0109805 7443 tcg_gen_addi_i32(addr, addr, -(n * 4));
9ee6e8bb
PB		 7444 }
7445 }
b0109805
PB		 7446 store_reg(s, rn, addr);
7447 } else {
7d1b0095 7448 tcg_temp_free_i32(addr);
9ee6e8bb
PB		 7449 }
7450 if (loaded_base) {
b0109805 7451 store_reg(s, rn, loaded_var);
9ee6e8bb
PB		 7452 }
7453 if ((insn & (1 << 22)) && !user) {
7454 /* Restore CPSR from SPSR. */
d9ba4830
PB		 7455 tmp = load_cpu_field(spsr);
7456 gen_set_cpsr(tmp, 0xffffffff);
7d1b0095 7457 tcg_temp_free_i32(tmp);
9ee6e8bb
PB		 7458 s->is_jmp = DISAS_UPDATE;
7459 }
7460 }
7461 break;
7462 case 0xa:
7463 case 0xb:
7464 {
7465 int32_t offset;
7466
7467 /* branch (and link) */
7468 val = (int32_t)s->pc;
7469 if (insn & (1 << 24)) {
7d1b0095 7470 tmp = tcg_temp_new_i32();
5e3f878a
PB		 7471 tcg_gen_movi_i32(tmp, val);
7472 store_reg(s, 14, tmp);
9ee6e8bb
PB		 7473 }
7474 offset = (((int32_t)insn << 8) >> 8);
7475 val += (offset << 2) + 4;
7476 gen_jmp(s, val);
7477 }
7478 break;
7479 case 0xc:
7480 case 0xd:
7481 case 0xe:
7482 /* Coprocessor. */
7483 if (disas_coproc_insn(env, s, insn))
7484 goto illegal_op;
7485 break;
7486 case 0xf:
7487 /* swi */
5e3f878a 7488 gen_set_pc_im(s->pc);
9ee6e8bb
PB		 7489 s->is_jmp = DISAS_SWI;
7490 break;
7491 default:
7492 illegal_op:
bc4a0de0 7493 gen_exception_insn(s, 4, EXCP_UDEF);
9ee6e8bb
PB		 7494 break;
7495 }
7496 }
7497}
7498
7499/* Return true if this is a Thumb-2 logical op. */
7500static int
7501thumb2_logic_op(int op)
7502{
7503 return (op < 8);
7504}
7505
7506/* Generate code for a Thumb-2 data processing operation. If CONDS is nonzero
7507 then set condition code flags based on the result of the operation.
7508 If SHIFTER_OUT is nonzero then set the carry flag for logical operations
7509 to the high bit of T1.
7510 Returns zero if the opcode is valid. */
7511
7512static int
396e467c 7513gen_thumb2_data_op(DisasContext *s, int op, int conds, uint32_t shifter_out, TCGv t0, TCGv t1)
9ee6e8bb
PB		 7514{
7515 int logic_cc;
7516
7517 logic_cc = 0;
7518 switch (op) {
7519 case 0: /* and */
396e467c 7520 tcg_gen_and_i32(t0, t0, t1);
9ee6e8bb
PB		 7521 logic_cc = conds;
7522 break;
7523 case 1: /* bic */
f669df27 7524 tcg_gen_andc_i32(t0, t0, t1);
9ee6e8bb
PB		 7525 logic_cc = conds;
7526 break;
7527 case 2: /* orr */
396e467c 7528 tcg_gen_or_i32(t0, t0, t1);
9ee6e8bb
PB		 7529 logic_cc = conds;
7530 break;
7531 case 3: /* orn */
29501f1b 7532 tcg_gen_orc_i32(t0, t0, t1);
9ee6e8bb
PB		 7533 logic_cc = conds;
7534 break;
7535 case 4: /* eor */
396e467c 7536 tcg_gen_xor_i32(t0, t0, t1);
9ee6e8bb
PB		 7537 logic_cc = conds;
7538 break;
7539 case 8: /* add */
7540 if (conds)
396e467c 7541 gen_helper_add_cc(t0, t0, t1);
9ee6e8bb 7542 else
396e467c 7543 tcg_gen_add_i32(t0, t0, t1);
9ee6e8bb
PB		 7544 break;
7545 case 10: /* adc */
7546 if (conds)
396e467c 7547 gen_helper_adc_cc(t0, t0, t1);
9ee6e8bb 7548 else
396e467c 7549 gen_adc(t0, t1);
9ee6e8bb
PB		 7550 break;
7551 case 11: /* sbc */
7552 if (conds)
396e467c 7553 gen_helper_sbc_cc(t0, t0, t1);
9ee6e8bb 7554 else
396e467c 7555 gen_sub_carry(t0, t0, t1);
9ee6e8bb
PB		 7556 break;
7557 case 13: /* sub */
7558 if (conds)
396e467c 7559 gen_helper_sub_cc(t0, t0, t1);
9ee6e8bb 7560 else
396e467c 7561 tcg_gen_sub_i32(t0, t0, t1);
9ee6e8bb
PB		 7562 break;
7563 case 14: /* rsb */
7564 if (conds)
396e467c 7565 gen_helper_sub_cc(t0, t1, t0);
9ee6e8bb 7566 else
396e467c 7567 tcg_gen_sub_i32(t0, t1, t0);
9ee6e8bb
PB		 7568 break;
7569 default: /* 5, 6, 7, 9, 12, 15. */
7570 return 1;
7571 }
7572 if (logic_cc) {
396e467c 7573 gen_logic_CC(t0);
9ee6e8bb 7574 if (shifter_out)
396e467c 7575 gen_set_CF_bit31(t1);
9ee6e8bb
PB		 7576 }
7577 return 0;
7578}
7579
7580/* Translate a 32-bit thumb instruction. Returns nonzero if the instruction
7581 is not legal. */
7582static int disas_thumb2_insn(CPUState *env, DisasContext *s, uint16_t insn_hw1)
7583{
b0109805 7584 uint32_t insn, imm, shift, offset;
9ee6e8bb 7585 uint32_t rd, rn, rm, rs;
b26eefb6 7586 TCGv tmp;
6ddbc6e4
PB		 7587 TCGv tmp2;
7588 TCGv tmp3;
b0109805 7589 TCGv addr;
a7812ae4 7590 TCGv_i64 tmp64;
9ee6e8bb
PB		 7591 int op;
7592 int shiftop;
7593 int conds;
7594 int logic_cc;
7595
7596 if (!(arm_feature(env, ARM_FEATURE_THUMB2)
7597 || arm_feature (env, ARM_FEATURE_M))) {
601d70b9 7598 /* Thumb-1 cores may need to treat bl and blx as a pair of
9ee6e8bb
PB		 7599 16-bit instructions to get correct prefetch abort behavior. */
7600 insn = insn_hw1;
7601 if ((insn & (1 << 12)) == 0) {
be5e7a76 7602 ARCH(5);
9ee6e8bb
PB		 7603 /* Second half of blx. */
7604 offset = ((insn & 0x7ff) << 1);
d9ba4830
PB		 7605 tmp = load_reg(s, 14);
7606 tcg_gen_addi_i32(tmp, tmp, offset);
7607 tcg_gen_andi_i32(tmp, tmp, 0xfffffffc);
9ee6e8bb 7608
7d1b0095 7609 tmp2 = tcg_temp_new_i32();
b0109805 7610 tcg_gen_movi_i32(tmp2, s->pc | 1);
d9ba4830
PB		 7611 store_reg(s, 14, tmp2);
7612 gen_bx(s, tmp);
9ee6e8bb
PB		 7613 return 0;
7614 }
7615 if (insn & (1 << 11)) {
7616 /* Second half of bl. */
7617 offset = ((insn & 0x7ff) << 1) | 1;
d9ba4830 7618 tmp = load_reg(s, 14);
6a0d8a1d 7619 tcg_gen_addi_i32(tmp, tmp, offset);
9ee6e8bb 7620
7d1b0095 7621 tmp2 = tcg_temp_new_i32();
b0109805 7622 tcg_gen_movi_i32(tmp2, s->pc | 1);
d9ba4830
PB		 7623 store_reg(s, 14, tmp2);
7624 gen_bx(s, tmp);
9ee6e8bb
PB		 7625 return 0;
7626 }
7627 if ((s->pc & ~TARGET_PAGE_MASK) == 0) {
7628 /* Instruction spans a page boundary. Implement it as two
7629 16-bit instructions in case the second half causes an
7630 prefetch abort. */
7631 offset = ((int32_t)insn << 21) >> 9;
396e467c 7632 tcg_gen_movi_i32(cpu_R[14], s->pc + 2 + offset);
9ee6e8bb
PB		 7633 return 0;
7634 }
7635 /* Fall through to 32-bit decode. */
7636 }
7637
7638 insn = lduw_code(s->pc);
7639 s->pc += 2;
7640 insn |= (uint32_t)insn_hw1 << 16;
7641
7642 if ((insn & 0xf800e800) != 0xf000e800) {
7643 ARCH(6T2);
7644 }
7645
7646 rn = (insn >> 16) & 0xf;
7647 rs = (insn >> 12) & 0xf;
7648 rd = (insn >> 8) & 0xf;
7649 rm = insn & 0xf;
7650 switch ((insn >> 25) & 0xf) {
7651 case 0: case 1: case 2: case 3:
7652 /* 16-bit instructions. Should never happen. */
7653 abort();
7654 case 4:
7655 if (insn & (1 << 22)) {
7656 /* Other load/store, table branch. */
7657 if (insn & 0x01200000) {
7658 /* Load/store doubleword. */
7659 if (rn == 15) {
7d1b0095 7660 addr = tcg_temp_new_i32();
b0109805 7661 tcg_gen_movi_i32(addr, s->pc & ~3);
9ee6e8bb 7662 } else {
b0109805 7663 addr = load_reg(s, rn);
9ee6e8bb
PB		 7664 }
7665 offset = (insn & 0xff) * 4;
7666 if ((insn & (1 << 23)) == 0)
7667 offset = -offset;
7668 if (insn & (1 << 24)) {
b0109805 7669 tcg_gen_addi_i32(addr, addr, offset);
9ee6e8bb
PB		 7670 offset = 0;
7671 }
7672 if (insn & (1 << 20)) {
7673 /* ldrd */
b0109805
PB		 7674 tmp = gen_ld32(addr, IS_USER(s));
7675 store_reg(s, rs, tmp);
7676 tcg_gen_addi_i32(addr, addr, 4);
7677 tmp = gen_ld32(addr, IS_USER(s));
7678 store_reg(s, rd, tmp);
9ee6e8bb
PB		 7679 } else {
7680 /* strd */
b0109805
PB		 7681 tmp = load_reg(s, rs);
7682 gen_st32(tmp, addr, IS_USER(s));
7683 tcg_gen_addi_i32(addr, addr, 4);
7684 tmp = load_reg(s, rd);
7685 gen_st32(tmp, addr, IS_USER(s));
9ee6e8bb
PB		 7686 }
7687 if (insn & (1 << 21)) {
7688 /* Base writeback. */
7689 if (rn == 15)
7690 goto illegal_op;
b0109805
PB		 7691 tcg_gen_addi_i32(addr, addr, offset - 4);
7692 store_reg(s, rn, addr);
7693 } else {
7d1b0095 7694 tcg_temp_free_i32(addr);
9ee6e8bb
PB		 7695 }
7696 } else if ((insn & (1 << 23)) == 0) {
7697 /* Load/store exclusive word. */
3174f8e9 7698 addr = tcg_temp_local_new();
98a46317 7699 load_reg_var(s, addr, rn);
426f5abc 7700 tcg_gen_addi_i32(addr, addr, (insn & 0xff) << 2);
2c0262af 7701 if (insn & (1 << 20)) {
426f5abc 7702 gen_load_exclusive(s, rs, 15, addr, 2);
9ee6e8bb 7703 } else {
426f5abc 7704 gen_store_exclusive(s, rd, rs, 15, addr, 2);
9ee6e8bb 7705 }
3174f8e9 7706 tcg_temp_free(addr);
9ee6e8bb
PB		 7707 } else if ((insn & (1 << 6)) == 0) {
7708 /* Table Branch. */
7709 if (rn == 15) {
7d1b0095 7710 addr = tcg_temp_new_i32();
b0109805 7711 tcg_gen_movi_i32(addr, s->pc);
9ee6e8bb 7712 } else {
b0109805 7713 addr = load_reg(s, rn);
9ee6e8bb 7714 }
b26eefb6 7715 tmp = load_reg(s, rm);
b0109805 7716 tcg_gen_add_i32(addr, addr, tmp);
9ee6e8bb
PB		 7717 if (insn & (1 << 4)) {
7718 /* tbh */
b0109805 7719 tcg_gen_add_i32(addr, addr, tmp);
7d1b0095 7720 tcg_temp_free_i32(tmp);
b0109805 7721 tmp = gen_ld16u(addr, IS_USER(s));
9ee6e8bb 7722 } else { /* tbb */
7d1b0095 7723 tcg_temp_free_i32(tmp);
b0109805 7724 tmp = gen_ld8u(addr, IS_USER(s));
9ee6e8bb 7725 }
7d1b0095 7726 tcg_temp_free_i32(addr);
b0109805
PB		 7727 tcg_gen_shli_i32(tmp, tmp, 1);
7728 tcg_gen_addi_i32(tmp, tmp, s->pc);
7729 store_reg(s, 15, tmp);
9ee6e8bb
PB		 7730 } else {
7731 /* Load/store exclusive byte/halfword/doubleword. */
426f5abc 7732 ARCH(7);
9ee6e8bb 7733 op = (insn >> 4) & 0x3;
426f5abc
PB		 7734 if (op == 2) {
7735 goto illegal_op;
7736 }
3174f8e9 7737 addr = tcg_temp_local_new();
98a46317 7738 load_reg_var(s, addr, rn);
9ee6e8bb 7739 if (insn & (1 << 20)) {
426f5abc 7740 gen_load_exclusive(s, rs, rd, addr, op);
9ee6e8bb 7741 } else {
426f5abc 7742 gen_store_exclusive(s, rm, rs, rd, addr, op);
9ee6e8bb 7743 }
3174f8e9 7744 tcg_temp_free(addr);
9ee6e8bb
PB		 7745 }
7746 } else {
7747 /* Load/store multiple, RFE, SRS. */
7748 if (((insn >> 23) & 1) == ((insn >> 24) & 1)) {
7749 /* Not available in user mode. */
b0109805 7750 if (IS_USER(s))
9ee6e8bb
PB		 7751 goto illegal_op;
7752 if (insn & (1 << 20)) {
7753 /* rfe */
b0109805
PB		 7754 addr = load_reg(s, rn);
7755 if ((insn & (1 << 24)) == 0)
7756 tcg_gen_addi_i32(addr, addr, -8);
7757 /* Load PC into tmp and CPSR into tmp2. */
7758 tmp = gen_ld32(addr, 0);
7759 tcg_gen_addi_i32(addr, addr, 4);
7760 tmp2 = gen_ld32(addr, 0);
9ee6e8bb
PB		 7761 if (insn & (1 << 21)) {
7762 /* Base writeback. */
b0109805
PB		 7763 if (insn & (1 << 24)) {
7764 tcg_gen_addi_i32(addr, addr, 4);
7765 } else {
7766 tcg_gen_addi_i32(addr, addr, -4);
7767 }
7768 store_reg(s, rn, addr);
7769 } else {
7d1b0095 7770 tcg_temp_free_i32(addr);
9ee6e8bb 7771 }
b0109805 7772 gen_rfe(s, tmp, tmp2);
9ee6e8bb
PB		 7773 } else {
7774 /* srs */
7775 op = (insn & 0x1f);
7d1b0095 7776 addr = tcg_temp_new_i32();
39ea3d4e
PM		 7777 tmp = tcg_const_i32(op);
7778 gen_helper_get_r13_banked(addr, cpu_env, tmp);
7779 tcg_temp_free_i32(tmp);
9ee6e8bb 7780 if ((insn & (1 << 24)) == 0) {
b0109805 7781 tcg_gen_addi_i32(addr, addr, -8);
9ee6e8bb 7782 }
b0109805
PB		 7783 tmp = load_reg(s, 14);
7784 gen_st32(tmp, addr, 0);
7785 tcg_gen_addi_i32(addr, addr, 4);
7d1b0095 7786 tmp = tcg_temp_new_i32();
b0109805
PB		 7787 gen_helper_cpsr_read(tmp);
7788 gen_st32(tmp, addr, 0);
9ee6e8bb
PB		 7789 if (insn & (1 << 21)) {
7790 if ((insn & (1 << 24)) == 0) {
b0109805 7791 tcg_gen_addi_i32(addr, addr, -4);
9ee6e8bb 7792 } else {
b0109805 7793 tcg_gen_addi_i32(addr, addr, 4);
9ee6e8bb 7794 }
39ea3d4e
PM		 7795 tmp = tcg_const_i32(op);
7796 gen_helper_set_r13_banked(cpu_env, tmp, addr);
7797 tcg_temp_free_i32(tmp);
b0109805 7798 } else {
7d1b0095 7799 tcg_temp_free_i32(addr);
9ee6e8bb
PB		 7800 }
7801 }
7802 } else {
7803 int i;
7804 /* Load/store multiple. */
b0109805 7805 addr = load_reg(s, rn);
9ee6e8bb
PB		 7806 offset = 0;
7807 for (i = 0; i < 16; i++) {
7808 if (insn & (1 << i))
7809 offset += 4;
7810 }
7811 if (insn & (1 << 24)) {
b0109805 7812 tcg_gen_addi_i32(addr, addr, -offset);
9ee6e8bb
PB		 7813 }
7814
7815 for (i = 0; i < 16; i++) {
7816 if ((insn & (1 << i)) == 0)
7817 continue;
7818 if (insn & (1 << 20)) {
7819 /* Load. */
b0109805 7820 tmp = gen_ld32(addr, IS_USER(s));
9ee6e8bb 7821 if (i == 15) {
b0109805 7822 gen_bx(s, tmp);
9ee6e8bb 7823 } else {
b0109805 7824 store_reg(s, i, tmp);
9ee6e8bb
PB		 7825 }
7826 } else {
7827 /* Store. */
b0109805
PB		 7828 tmp = load_reg(s, i);
7829 gen_st32(tmp, addr, IS_USER(s));
9ee6e8bb 7830 }
b0109805 7831 tcg_gen_addi_i32(addr, addr, 4);
9ee6e8bb
PB		 7832 }
7833 if (insn & (1 << 21)) {
7834 /* Base register writeback. */
7835 if (insn & (1 << 24)) {
b0109805 7836 tcg_gen_addi_i32(addr, addr, -offset);
9ee6e8bb
PB		 7837 }
7838 /* Fault if writeback register is in register list. */
7839 if (insn & (1 << rn))
7840 goto illegal_op;
b0109805
PB		 7841 store_reg(s, rn, addr);
7842 } else {
7d1b0095 7843 tcg_temp_free_i32(addr);
9ee6e8bb
PB		 7844 }
7845 }
7846 }
7847 break;
2af9ab77
JB		 7848 case 5:
7849
9ee6e8bb 7850 op = (insn >> 21) & 0xf;
2af9ab77
JB		 7851 if (op == 6) {
7852 /* Halfword pack. */
7853 tmp = load_reg(s, rn);
7854 tmp2 = load_reg(s, rm);
7855 shift = ((insn >> 10) & 0x1c) | ((insn >> 6) & 0x3);
7856 if (insn & (1 << 5)) {
7857 /* pkhtb */
7858 if (shift == 0)
7859 shift = 31;
7860 tcg_gen_sari_i32(tmp2, tmp2, shift);
7861 tcg_gen_andi_i32(tmp, tmp, 0xffff0000);
7862 tcg_gen_ext16u_i32(tmp2, tmp2);
7863 } else {
7864 /* pkhbt */
7865 if (shift)
7866 tcg_gen_shli_i32(tmp2, tmp2, shift);
7867 tcg_gen_ext16u_i32(tmp, tmp);
7868 tcg_gen_andi_i32(tmp2, tmp2, 0xffff0000);
7869 }
7870 tcg_gen_or_i32(tmp, tmp, tmp2);
7d1b0095 7871 tcg_temp_free_i32(tmp2);
3174f8e9
FN		 7872 store_reg(s, rd, tmp);
7873 } else {
2af9ab77
JB		 7874 /* Data processing register constant shift. */
7875 if (rn == 15) {
7d1b0095 7876 tmp = tcg_temp_new_i32();
2af9ab77
JB		 7877 tcg_gen_movi_i32(tmp, 0);
7878 } else {
7879 tmp = load_reg(s, rn);
7880 }
7881 tmp2 = load_reg(s, rm);
7882
7883 shiftop = (insn >> 4) & 3;
7884 shift = ((insn >> 6) & 3) | ((insn >> 10) & 0x1c);
7885 conds = (insn & (1 << 20)) != 0;
7886 logic_cc = (conds && thumb2_logic_op(op));
7887 gen_arm_shift_im(tmp2, shiftop, shift, logic_cc);
7888 if (gen_thumb2_data_op(s, op, conds, 0, tmp, tmp2))
7889 goto illegal_op;
7d1b0095 7890 tcg_temp_free_i32(tmp2);
2af9ab77
JB		 7891 if (rd != 15) {
7892 store_reg(s, rd, tmp);
7893 } else {
7d1b0095 7894 tcg_temp_free_i32(tmp);
2af9ab77 7895 }
3174f8e9 7896 }
9ee6e8bb
PB		 7897 break;
7898 case 13: /* Misc data processing. */
7899 op = ((insn >> 22) & 6) | ((insn >> 7) & 1);
7900 if (op < 4 && (insn & 0xf000) != 0xf000)
7901 goto illegal_op;
7902 switch (op) {
7903 case 0: /* Register controlled shift. */
8984bd2e
PB		 7904 tmp = load_reg(s, rn);
7905 tmp2 = load_reg(s, rm);
9ee6e8bb
PB		 7906 if ((insn & 0x70) != 0)
7907 goto illegal_op;
7908 op = (insn >> 21) & 3;
8984bd2e
PB		 7909 logic_cc = (insn & (1 << 20)) != 0;
7910 gen_arm_shift_reg(tmp, op, tmp2, logic_cc);
7911 if (logic_cc)
7912 gen_logic_CC(tmp);
21aeb343 7913 store_reg_bx(env, s, rd, tmp);
9ee6e8bb
PB		 7914 break;
7915 case 1: /* Sign/zero extend. */
5e3f878a 7916 tmp = load_reg(s, rm);
9ee6e8bb
PB		 7917 shift = (insn >> 4) & 3;
7918 /* ??? In many cases it's not neccessary to do a
7919 rotate, a shift is sufficient. */
7920 if (shift != 0)
f669df27 7921 tcg_gen_rotri_i32(tmp, tmp, shift * 8);
9ee6e8bb
PB		 7922 op = (insn >> 20) & 7;
7923 switch (op) {
5e3f878a
PB		 7924 case 0: gen_sxth(tmp); break;
7925 case 1: gen_uxth(tmp); break;
7926 case 2: gen_sxtb16(tmp); break;
7927 case 3: gen_uxtb16(tmp); break;
7928 case 4: gen_sxtb(tmp); break;
7929 case 5: gen_uxtb(tmp); break;
9ee6e8bb
PB		 7930 default: goto illegal_op;
7931 }
7932 if (rn != 15) {
5e3f878a 7933 tmp2 = load_reg(s, rn);
9ee6e8bb 7934 if ((op >> 1) == 1) {
5e3f878a 7935 gen_add16(tmp, tmp2);
9ee6e8bb 7936 } else {
5e3f878a 7937 tcg_gen_add_i32(tmp, tmp, tmp2);
7d1b0095 7938 tcg_temp_free_i32(tmp2);
9ee6e8bb
PB		 7939 }
7940 }
5e3f878a 7941 store_reg(s, rd, tmp);
9ee6e8bb
PB		 7942 break;
7943 case 2: /* SIMD add/subtract. */
7944 op = (insn >> 20) & 7;
7945 shift = (insn >> 4) & 7;
7946 if ((op & 3) == 3 || (shift & 3) == 3)
7947 goto illegal_op;
6ddbc6e4
PB		 7948 tmp = load_reg(s, rn);
7949 tmp2 = load_reg(s, rm);
7950 gen_thumb2_parallel_addsub(op, shift, tmp, tmp2);
7d1b0095 7951 tcg_temp_free_i32(tmp2);
6ddbc6e4 7952 store_reg(s, rd, tmp);
9ee6e8bb
PB		 7953 break;
7954 case 3: /* Other data processing. */
7955 op = ((insn >> 17) & 0x38) | ((insn >> 4) & 7);
7956 if (op < 4) {
7957 /* Saturating add/subtract. */
d9ba4830
PB		 7958 tmp = load_reg(s, rn);
7959 tmp2 = load_reg(s, rm);
9ee6e8bb 7960 if (op & 1)
4809c612
JB		 7961 gen_helper_double_saturate(tmp, tmp);
7962 if (op & 2)
d9ba4830 7963 gen_helper_sub_saturate(tmp, tmp2, tmp);
9ee6e8bb 7964 else
d9ba4830 7965 gen_helper_add_saturate(tmp, tmp, tmp2);
7d1b0095 7966 tcg_temp_free_i32(tmp2);
9ee6e8bb 7967 } else {
d9ba4830 7968 tmp = load_reg(s, rn);
9ee6e8bb
PB		 7969 switch (op) {
7970 case 0x0a: /* rbit */
d9ba4830 7971 gen_helper_rbit(tmp, tmp);
9ee6e8bb
PB		 7972 break;
7973 case 0x08: /* rev */
66896cb8 7974 tcg_gen_bswap32_i32(tmp, tmp);
9ee6e8bb
PB		 7975 break;
7976 case 0x09: /* rev16 */
d9ba4830 7977 gen_rev16(tmp);
9ee6e8bb
PB		 7978 break;
7979 case 0x0b: /* revsh */
d9ba4830 7980 gen_revsh(tmp);
9ee6e8bb
PB		 7981 break;
7982 case 0x10: /* sel */
d9ba4830 7983 tmp2 = load_reg(s, rm);
7d1b0095 7984 tmp3 = tcg_temp_new_i32();
6ddbc6e4 7985 tcg_gen_ld_i32(tmp3, cpu_env, offsetof(CPUState, GE));
d9ba4830 7986 gen_helper_sel_flags(tmp, tmp3, tmp, tmp2);
7d1b0095
PM		 7987 tcg_temp_free_i32(tmp3);
7988 tcg_temp_free_i32(tmp2);
9ee6e8bb
PB		 7989 break;
7990 case 0x18: /* clz */
d9ba4830 7991 gen_helper_clz(tmp, tmp);
9ee6e8bb
PB		 7992 break;
7993 default:
7994 goto illegal_op;
7995 }
7996 }
d9ba4830 7997 store_reg(s, rd, tmp);
9ee6e8bb
PB		 7998 break;
7999 case 4: case 5: /* 32-bit multiply. Sum of absolute differences. */
8000 op = (insn >> 4) & 0xf;
d9ba4830
PB		 8001 tmp = load_reg(s, rn);
8002 tmp2 = load_reg(s, rm);
9ee6e8bb
PB		 8003 switch ((insn >> 20) & 7) {
8004 case 0: /* 32 x 32 -> 32 */
d9ba4830 8005 tcg_gen_mul_i32(tmp, tmp, tmp2);
7d1b0095 8006 tcg_temp_free_i32(tmp2);
9ee6e8bb 8007 if (rs != 15) {
d9ba4830 8008 tmp2 = load_reg(s, rs);
9ee6e8bb 8009 if (op)
d9ba4830 8010 tcg_gen_sub_i32(tmp, tmp2, tmp);
9ee6e8bb 8011 else
d9ba4830 8012 tcg_gen_add_i32(tmp, tmp, tmp2);
7d1b0095 8013 tcg_temp_free_i32(tmp2);
9ee6e8bb 8014 }
9ee6e8bb
PB		 8015 break;
8016 case 1: /* 16 x 16 -> 32 */
d9ba4830 8017 gen_mulxy(tmp, tmp2, op & 2, op & 1);
7d1b0095 8018 tcg_temp_free_i32(tmp2);
9ee6e8bb 8019 if (rs != 15) {
d9ba4830
PB		 8020 tmp2 = load_reg(s, rs);
8021 gen_helper_add_setq(tmp, tmp, tmp2);
7d1b0095 8022 tcg_temp_free_i32(tmp2);
9ee6e8bb 8023 }
9ee6e8bb
PB		 8024 break;
8025 case 2: /* Dual multiply add. */
8026 case 4: /* Dual multiply subtract. */
8027 if (op)
d9ba4830
PB		 8028 gen_swap_half(tmp2);
8029 gen_smul_dual(tmp, tmp2);
9ee6e8bb 8030 if (insn & (1 << 22)) {
e1d177b9 8031 /* This subtraction cannot overflow. */
d9ba4830 8032 tcg_gen_sub_i32(tmp, tmp, tmp2);
9ee6e8bb 8033 } else {
e1d177b9
PM		 8034 /* This addition cannot overflow 32 bits;
8035 * however it may overflow considered as a signed
8036 * operation, in which case we must set the Q flag.
8037 */
8038 gen_helper_add_setq(tmp, tmp, tmp2);
9ee6e8bb 8039 }
7d1b0095 8040 tcg_temp_free_i32(tmp2);
9ee6e8bb
PB		 8041 if (rs != 15)
8042 {
d9ba4830
PB		 8043 tmp2 = load_reg(s, rs);
8044 gen_helper_add_setq(tmp, tmp, tmp2);
7d1b0095 8045 tcg_temp_free_i32(tmp2);
9ee6e8bb 8046 }
9ee6e8bb
PB		 8047 break;
8048 case 3: /* 32 * 16 -> 32msb */
8049 if (op)
d9ba4830 8050 tcg_gen_sari_i32(tmp2, tmp2, 16);
9ee6e8bb 8051 else
d9ba4830 8052 gen_sxth(tmp2);
a7812ae4
PB		 8053 tmp64 = gen_muls_i64_i32(tmp, tmp2);
8054 tcg_gen_shri_i64(tmp64, tmp64, 16);
7d1b0095 8055 tmp = tcg_temp_new_i32();
a7812ae4 8056 tcg_gen_trunc_i64_i32(tmp, tmp64);
b75263d6 8057 tcg_temp_free_i64(tmp64);
9ee6e8bb
PB		 8058 if (rs != 15)
8059 {
d9ba4830
PB		 8060 tmp2 = load_reg(s, rs);
8061 gen_helper_add_setq(tmp, tmp, tmp2);
7d1b0095 8062 tcg_temp_free_i32(tmp2);
9ee6e8bb 8063 }
9ee6e8bb 8064 break;
838fa72d
AJ		 8065 case 5: case 6: /* 32 * 32 -> 32msb (SMMUL, SMMLA, SMMLS) */
8066 tmp64 = gen_muls_i64_i32(tmp, tmp2);
9ee6e8bb 8067 if (rs != 15) {
838fa72d
AJ		 8068 tmp = load_reg(s, rs);
8069 if (insn & (1 << 20)) {
8070 tmp64 = gen_addq_msw(tmp64, tmp);
99c475ab 8071 } else {
838fa72d 8072 tmp64 = gen_subq_msw(tmp64, tmp);
99c475ab 8073 }
2c0262af 8074 }
838fa72d
AJ		 8075 if (insn & (1 << 4)) {
8076 tcg_gen_addi_i64(tmp64, tmp64, 0x80000000u);
8077 }
8078 tcg_gen_shri_i64(tmp64, tmp64, 32);
7d1b0095 8079 tmp = tcg_temp_new_i32();
838fa72d
AJ		 8080 tcg_gen_trunc_i64_i32(tmp, tmp64);
8081 tcg_temp_free_i64(tmp64);
9ee6e8bb
PB		 8082 break;
8083 case 7: /* Unsigned sum of absolute differences. */
d9ba4830 8084 gen_helper_usad8(tmp, tmp, tmp2);
7d1b0095 8085 tcg_temp_free_i32(tmp2);
9ee6e8bb 8086 if (rs != 15) {
d9ba4830
PB		 8087 tmp2 = load_reg(s, rs);
8088 tcg_gen_add_i32(tmp, tmp, tmp2);
7d1b0095 8089 tcg_temp_free_i32(tmp2);
5fd46862 8090 }
9ee6e8bb 8091 break;
2c0262af 8092 }
d9ba4830 8093 store_reg(s, rd, tmp);
2c0262af 8094 break;
9ee6e8bb
PB		 8095 case 6: case 7: /* 64-bit multiply, Divide. */
8096 op = ((insn >> 4) & 0xf) | ((insn >> 16) & 0x70);
5e3f878a
PB		 8097 tmp = load_reg(s, rn);
8098 tmp2 = load_reg(s, rm);
9ee6e8bb
PB		 8099 if ((op & 0x50) == 0x10) {
8100 /* sdiv, udiv */
8101 if (!arm_feature(env, ARM_FEATURE_DIV))
8102 goto illegal_op;
8103 if (op & 0x20)
5e3f878a 8104 gen_helper_udiv(tmp, tmp, tmp2);
2c0262af 8105 else
5e3f878a 8106 gen_helper_sdiv(tmp, tmp, tmp2);
7d1b0095 8107 tcg_temp_free_i32(tmp2);
5e3f878a 8108 store_reg(s, rd, tmp);
9ee6e8bb
PB		 8109 } else if ((op & 0xe) == 0xc) {
8110 /* Dual multiply accumulate long. */
8111 if (op & 1)
5e3f878a
PB		 8112 gen_swap_half(tmp2);
8113 gen_smul_dual(tmp, tmp2);
9ee6e8bb 8114 if (op & 0x10) {
5e3f878a 8115 tcg_gen_sub_i32(tmp, tmp, tmp2);
b5ff1b31 8116 } else {
5e3f878a 8117 tcg_gen_add_i32(tmp, tmp, tmp2);
b5ff1b31 8118 }
7d1b0095 8119 tcg_temp_free_i32(tmp2);
a7812ae4
PB		 8120 /* BUGFIX */
8121 tmp64 = tcg_temp_new_i64();
8122 tcg_gen_ext_i32_i64(tmp64, tmp);
7d1b0095 8123 tcg_temp_free_i32(tmp);
a7812ae4
PB		 8124 gen_addq(s, tmp64, rs, rd);
8125 gen_storeq_reg(s, rs, rd, tmp64);
b75263d6 8126 tcg_temp_free_i64(tmp64);
2c0262af 8127 } else {
9ee6e8bb
PB		 8128 if (op & 0x20) {
8129 /* Unsigned 64-bit multiply */
a7812ae4 8130 tmp64 = gen_mulu_i64_i32(tmp, tmp2);
b5ff1b31 8131 } else {
9ee6e8bb
PB		 8132 if (op & 8) {
8133 /* smlalxy */
5e3f878a 8134 gen_mulxy(tmp, tmp2, op & 2, op & 1);
7d1b0095 8135 tcg_temp_free_i32(tmp2);
a7812ae4
PB		 8136 tmp64 = tcg_temp_new_i64();
8137 tcg_gen_ext_i32_i64(tmp64, tmp);
7d1b0095 8138 tcg_temp_free_i32(tmp);
9ee6e8bb
PB		 8139 } else {
8140 /* Signed 64-bit multiply */
a7812ae4 8141 tmp64 = gen_muls_i64_i32(tmp, tmp2);
9ee6e8bb 8142 }
b5ff1b31 8143 }
9ee6e8bb
PB		 8144 if (op & 4) {
8145 /* umaal */
a7812ae4
PB		 8146 gen_addq_lo(s, tmp64, rs);
8147 gen_addq_lo(s, tmp64, rd);
9ee6e8bb
PB		 8148 } else if (op & 0x40) {
8149 /* 64-bit accumulate. */
a7812ae4 8150 gen_addq(s, tmp64, rs, rd);
9ee6e8bb 8151 }
a7812ae4 8152 gen_storeq_reg(s, rs, rd, tmp64);
b75263d6 8153 tcg_temp_free_i64(tmp64);
5fd46862 8154 }
2c0262af 8155 break;
9ee6e8bb
PB		 8156 }
8157 break;
8158 case 6: case 7: case 14: case 15:
8159 /* Coprocessor. */
8160 if (((insn >> 24) & 3) == 3) {
8161 /* Translate into the equivalent ARM encoding. */
f06053e3 8162 insn = (insn & 0xe2ffffff) | ((insn & (1 << 28)) >> 4) | (1 << 28);
9ee6e8bb
PB		 8163 if (disas_neon_data_insn(env, s, insn))
8164 goto illegal_op;
8165 } else {
8166 if (insn & (1 << 28))
8167 goto illegal_op;
8168 if (disas_coproc_insn (env, s, insn))
8169 goto illegal_op;
8170 }
8171 break;
8172 case 8: case 9: case 10: case 11:
8173 if (insn & (1 << 15)) {
8174 /* Branches, misc control. */
8175 if (insn & 0x5000) {
8176 /* Unconditional branch. */
8177 /* signextend(hw1[10:0]) -> offset[:12]. */
8178 offset = ((int32_t)insn << 5) >> 9 & ~(int32_t)0xfff;
8179 /* hw1[10:0] -> offset[11:1]. */
8180 offset |= (insn & 0x7ff) << 1;
8181 /* (~hw2[13, 11] ^ offset[24]) -> offset[23,22]
8182 offset[24:22] already have the same value because of the
8183 sign extension above. */
8184 offset ^= ((~insn) & (1 << 13)) << 10;
8185 offset ^= ((~insn) & (1 << 11)) << 11;
8186
9ee6e8bb
PB		 8187 if (insn & (1 << 14)) {
8188 /* Branch and link. */
3174f8e9 8189 tcg_gen_movi_i32(cpu_R[14], s->pc | 1);
b5ff1b31 8190 }
3b46e624 8191
b0109805 8192 offset += s->pc;
9ee6e8bb
PB		 8193 if (insn & (1 << 12)) {
8194 /* b/bl */
b0109805 8195 gen_jmp(s, offset);
9ee6e8bb
PB		 8196 } else {
8197 /* blx */
b0109805 8198 offset &= ~(uint32_t)2;
be5e7a76 8199 /* thumb2 bx, no need to check */
b0109805 8200 gen_bx_im(s, offset);
2c0262af 8201 }
9ee6e8bb
PB		 8202 } else if (((insn >> 23) & 7) == 7) {
8203 /* Misc control */
8204 if (insn & (1 << 13))
8205 goto illegal_op;
8206
8207 if (insn & (1 << 26)) {
8208 /* Secure monitor call (v6Z) */
8209 goto illegal_op; /* not implemented. */
2c0262af 8210 } else {
9ee6e8bb
PB		 8211 op = (insn >> 20) & 7;
8212 switch (op) {
8213 case 0: /* msr cpsr. */
8214 if (IS_M(env)) {
8984bd2e
PB		 8215 tmp = load_reg(s, rn);
8216 addr = tcg_const_i32(insn & 0xff);
8217 gen_helper_v7m_msr(cpu_env, addr, tmp);
b75263d6 8218 tcg_temp_free_i32(addr);
7d1b0095 8219 tcg_temp_free_i32(tmp);
9ee6e8bb
PB		 8220 gen_lookup_tb(s);
8221 break;
8222 }
8223 /* fall through */
8224 case 1: /* msr spsr. */
8225 if (IS_M(env))
8226 goto illegal_op;
2fbac54b
FN		 8227 tmp = load_reg(s, rn);
8228 if (gen_set_psr(s,
9ee6e8bb 8229 msr_mask(env, s, (insn >> 8) & 0xf, op == 1),
2fbac54b 8230 op == 1, tmp))
9ee6e8bb
PB		 8231 goto illegal_op;
8232 break;
8233 case 2: /* cps, nop-hint. */
8234 if (((insn >> 8) & 7) == 0) {
8235 gen_nop_hint(s, insn & 0xff);
8236 }
8237 /* Implemented as NOP in user mode. */
8238 if (IS_USER(s))
8239 break;
8240 offset = 0;
8241 imm = 0;
8242 if (insn & (1 << 10)) {
8243 if (insn & (1 << 7))
8244 offset |= CPSR_A;
8245 if (insn & (1 << 6))
8246 offset |= CPSR_I;
8247 if (insn & (1 << 5))
8248 offset |= CPSR_F;
8249 if (insn & (1 << 9))
8250 imm = CPSR_A | CPSR_I | CPSR_F;
8251 }
8252 if (insn & (1 << 8)) {
8253 offset |= 0x1f;
8254 imm |= (insn & 0x1f);
8255 }
8256 if (offset) {
2fbac54b 8257 gen_set_psr_im(s, offset, 0, imm);
9ee6e8bb
PB		 8258 }
8259 break;
8260 case 3: /* Special control operations. */
426f5abc 8261 ARCH(7);
9ee6e8bb
PB		 8262 op = (insn >> 4) & 0xf;
8263 switch (op) {
8264 case 2: /* clrex */
426f5abc 8265 gen_clrex(s);
9ee6e8bb
PB		 8266 break;
8267 case 4: /* dsb */
8268 case 5: /* dmb */
8269 case 6: /* isb */
8270 /* These execute as NOPs. */
9ee6e8bb
PB		 8271 break;
8272 default:
8273 goto illegal_op;
8274 }
8275 break;
8276 case 4: /* bxj */
8277 /* Trivial implementation equivalent to bx. */
d9ba4830
PB		 8278 tmp = load_reg(s, rn);
8279 gen_bx(s, tmp);
9ee6e8bb
PB		 8280 break;
8281 case 5: /* Exception return. */
b8b45b68
RV		 8282 if (IS_USER(s)) {
8283 goto illegal_op;
8284 }
8285 if (rn != 14 || rd != 15) {
8286 goto illegal_op;
8287 }
8288 tmp = load_reg(s, rn);
8289 tcg_gen_subi_i32(tmp, tmp, insn & 0xff);
8290 gen_exception_return(s, tmp);
8291 break;
9ee6e8bb 8292 case 6: /* mrs cpsr. */
7d1b0095 8293 tmp = tcg_temp_new_i32();
9ee6e8bb 8294 if (IS_M(env)) {
8984bd2e
PB		 8295 addr = tcg_const_i32(insn & 0xff);
8296 gen_helper_v7m_mrs(tmp, cpu_env, addr);
b75263d6 8297 tcg_temp_free_i32(addr);
9ee6e8bb 8298 } else {
8984bd2e 8299 gen_helper_cpsr_read(tmp);
9ee6e8bb 8300 }
8984bd2e 8301 store_reg(s, rd, tmp);
9ee6e8bb
PB		 8302 break;
8303 case 7: /* mrs spsr. */
8304 /* Not accessible in user mode. */
8305 if (IS_USER(s) || IS_M(env))
8306 goto illegal_op;
d9ba4830
PB		 8307 tmp = load_cpu_field(spsr);
8308 store_reg(s, rd, tmp);
9ee6e8bb 8309 break;
2c0262af
FB		 8310 }
8311 }
9ee6e8bb
PB		 8312 } else {
8313 /* Conditional branch. */
8314 op = (insn >> 22) & 0xf;
8315 /* Generate a conditional jump to next instruction. */
8316 s->condlabel = gen_new_label();
d9ba4830 8317 gen_test_cc(op ^ 1, s->condlabel);
9ee6e8bb
PB		 8318 s->condjmp = 1;
8319
8320 /* offset[11:1] = insn[10:0] */
8321 offset = (insn & 0x7ff) << 1;
8322 /* offset[17:12] = insn[21:16]. */
8323 offset |= (insn & 0x003f0000) >> 4;
8324 /* offset[31:20] = insn[26]. */
8325 offset |= ((int32_t)((insn << 5) & 0x80000000)) >> 11;
8326 /* offset[18] = insn[13]. */
8327 offset |= (insn & (1 << 13)) << 5;
8328 /* offset[19] = insn[11]. */
8329 offset |= (insn & (1 << 11)) << 8;
8330
8331 /* jump to the offset */
b0109805 8332 gen_jmp(s, s->pc + offset);
9ee6e8bb
PB		 8333 }
8334 } else {
8335 /* Data processing immediate. */
8336 if (insn & (1 << 25)) {
8337 if (insn & (1 << 24)) {
8338 if (insn & (1 << 20))
8339 goto illegal_op;
8340 /* Bitfield/Saturate. */
8341 op = (insn >> 21) & 7;
8342 imm = insn & 0x1f;
8343 shift = ((insn >> 6) & 3) | ((insn >> 10) & 0x1c);
6ddbc6e4 8344 if (rn == 15) {
7d1b0095 8345 tmp = tcg_temp_new_i32();
6ddbc6e4
PB		 8346 tcg_gen_movi_i32(tmp, 0);
8347 } else {
8348 tmp = load_reg(s, rn);
8349 }
9ee6e8bb
PB		 8350 switch (op) {
8351 case 2: /* Signed bitfield extract. */
8352 imm++;
8353 if (shift + imm > 32)
8354 goto illegal_op;
8355 if (imm < 32)
6ddbc6e4 8356 gen_sbfx(tmp, shift, imm);
9ee6e8bb
PB		 8357 break;
8358 case 6: /* Unsigned bitfield extract. */
8359 imm++;
8360 if (shift + imm > 32)
8361 goto illegal_op;
8362 if (imm < 32)
6ddbc6e4 8363 gen_ubfx(tmp, shift, (1u << imm) - 1);
9ee6e8bb
PB		 8364 break;
8365 case 3: /* Bitfield insert/clear. */
8366 if (imm < shift)
8367 goto illegal_op;
8368 imm = imm + 1 - shift;
8369 if (imm != 32) {
6ddbc6e4 8370 tmp2 = load_reg(s, rd);
8f8e3aa4 8371 gen_bfi(tmp, tmp2, tmp, shift, (1u << imm) - 1);
7d1b0095 8372 tcg_temp_free_i32(tmp2);
9ee6e8bb
PB		 8373 }
8374 break;
8375 case 7:
8376 goto illegal_op;
8377 default: /* Saturate. */
9ee6e8bb
PB		 8378 if (shift) {
8379 if (op & 1)
6ddbc6e4 8380 tcg_gen_sari_i32(tmp, tmp, shift);
9ee6e8bb 8381 else
6ddbc6e4 8382 tcg_gen_shli_i32(tmp, tmp, shift);
9ee6e8bb 8383 }
6ddbc6e4 8384 tmp2 = tcg_const_i32(imm);
9ee6e8bb
PB		 8385 if (op & 4) {
8386 /* Unsigned. */
9ee6e8bb 8387 if ((op & 1) && shift == 0)
6ddbc6e4 8388 gen_helper_usat16(tmp, tmp, tmp2);
9ee6e8bb 8389 else
6ddbc6e4 8390 gen_helper_usat(tmp, tmp, tmp2);
2c0262af 8391 } else {
9ee6e8bb 8392 /* Signed. */
9ee6e8bb 8393 if ((op & 1) && shift == 0)
6ddbc6e4 8394 gen_helper_ssat16(tmp, tmp, tmp2);
9ee6e8bb 8395 else
6ddbc6e4 8396 gen_helper_ssat(tmp, tmp, tmp2);
2c0262af 8397 }
b75263d6 8398 tcg_temp_free_i32(tmp2);
9ee6e8bb 8399 break;
2c0262af 8400 }
6ddbc6e4 8401 store_reg(s, rd, tmp);
9ee6e8bb
PB		 8402 } else {
8403 imm = ((insn & 0x04000000) >> 15)
8404 | ((insn & 0x7000) >> 4) | (insn & 0xff);
8405 if (insn & (1 << 22)) {
8406 /* 16-bit immediate. */
8407 imm |= (insn >> 4) & 0xf000;
8408 if (insn & (1 << 23)) {
8409 /* movt */
5e3f878a 8410 tmp = load_reg(s, rd);
86831435 8411 tcg_gen_ext16u_i32(tmp, tmp);
5e3f878a 8412 tcg_gen_ori_i32(tmp, tmp, imm << 16);
2c0262af 8413 } else {
9ee6e8bb 8414 /* movw */
7d1b0095 8415 tmp = tcg_temp_new_i32();
5e3f878a 8416 tcg_gen_movi_i32(tmp, imm);
2c0262af
FB		 8417 }
8418 } else {
9ee6e8bb
PB		 8419 /* Add/sub 12-bit immediate. */
8420 if (rn == 15) {
b0109805 8421 offset = s->pc & ~(uint32_t)3;
9ee6e8bb 8422 if (insn & (1 << 23))
b0109805 8423 offset -= imm;
9ee6e8bb 8424 else
b0109805 8425 offset += imm;
7d1b0095 8426 tmp = tcg_temp_new_i32();
5e3f878a 8427 tcg_gen_movi_i32(tmp, offset);
2c0262af 8428 } else {
5e3f878a 8429 tmp = load_reg(s, rn);
9ee6e8bb 8430 if (insn & (1 << 23))
5e3f878a 8431 tcg_gen_subi_i32(tmp, tmp, imm);
9ee6e8bb 8432 else
5e3f878a 8433 tcg_gen_addi_i32(tmp, tmp, imm);
2c0262af 8434 }
9ee6e8bb 8435 }
5e3f878a 8436 store_reg(s, rd, tmp);
191abaa2 8437 }
9ee6e8bb
PB		 8438 } else {
8439 int shifter_out = 0;
8440 /* modified 12-bit immediate. */
8441 shift = ((insn & 0x04000000) >> 23) | ((insn & 0x7000) >> 12);
8442 imm = (insn & 0xff);
8443 switch (shift) {
8444 case 0: /* XY */
8445 /* Nothing to do. */
8446 break;
8447 case 1: /* 00XY00XY */
8448 imm |= imm << 16;
8449 break;
8450 case 2: /* XY00XY00 */
8451 imm |= imm << 16;
8452 imm <<= 8;
8453 break;
8454 case 3: /* XYXYXYXY */
8455 imm |= imm << 16;
8456 imm |= imm << 8;
8457 break;
8458 default: /* Rotated constant. */
8459 shift = (shift << 1) | (imm >> 7);
8460 imm |= 0x80;
8461 imm = imm << (32 - shift);
8462 shifter_out = 1;
8463 break;
b5ff1b31 8464 }
7d1b0095 8465 tmp2 = tcg_temp_new_i32();
3174f8e9 8466 tcg_gen_movi_i32(tmp2, imm);
9ee6e8bb 8467 rn = (insn >> 16) & 0xf;
3174f8e9 8468 if (rn == 15) {
7d1b0095 8469 tmp = tcg_temp_new_i32();
3174f8e9
FN		 8470 tcg_gen_movi_i32(tmp, 0);
8471 } else {
8472 tmp = load_reg(s, rn);
8473 }
9ee6e8bb
PB		 8474 op = (insn >> 21) & 0xf;
8475 if (gen_thumb2_data_op(s, op, (insn & (1 << 20)) != 0,
3174f8e9 8476 shifter_out, tmp, tmp2))
9ee6e8bb 8477 goto illegal_op;
7d1b0095 8478 tcg_temp_free_i32(tmp2);
9ee6e8bb
PB		 8479 rd = (insn >> 8) & 0xf;
8480 if (rd != 15) {
3174f8e9
FN		 8481 store_reg(s, rd, tmp);
8482 } else {
7d1b0095 8483 tcg_temp_free_i32(tmp);
2c0262af 8484 }
2c0262af 8485 }
9ee6e8bb
PB		 8486 }
8487 break;
8488 case 12: /* Load/store single data item. */
8489 {
8490 int postinc = 0;
8491 int writeback = 0;
b0109805 8492 int user;
9ee6e8bb
PB		 8493 if ((insn & 0x01100000) == 0x01000000) {
8494 if (disas_neon_ls_insn(env, s, insn))
c1713132 8495 goto illegal_op;
9ee6e8bb
PB		 8496 break;
8497 }
a2fdc890
PM		 8498 op = ((insn >> 21) & 3) | ((insn >> 22) & 4);
8499 if (rs == 15) {
8500 if (!(insn & (1 << 20))) {
8501 goto illegal_op;
8502 }
8503 if (op != 2) {
8504 /* Byte or halfword load space with dest == r15 : memory hints.
8505 * Catch them early so we don't emit pointless addressing code.
8506 * This space is a mix of:
8507 * PLD/PLDW/PLI, which we implement as NOPs (note that unlike
8508 * the ARM encodings, PLDW space doesn't UNDEF for non-v7MP
8509 * cores)
8510 * unallocated hints, which must be treated as NOPs
8511 * UNPREDICTABLE space, which we NOP or UNDEF depending on
8512 * which is easiest for the decoding logic
8513 * Some space which must UNDEF
8514 */
8515 int op1 = (insn >> 23) & 3;
8516 int op2 = (insn >> 6) & 0x3f;
8517 if (op & 2) {
8518 goto illegal_op;
8519 }
8520 if (rn == 15) {
8521 /* UNPREDICTABLE or unallocated hint */
8522 return 0;
8523 }
8524 if (op1 & 1) {
8525 return 0; /* PLD* or unallocated hint */
8526 }
8527 if ((op2 == 0) || ((op2 & 0x3c) == 0x30)) {
8528 return 0; /* PLD* or unallocated hint */
8529 }
8530 /* UNDEF space, or an UNPREDICTABLE */
8531 return 1;
8532 }
8533 }
b0109805 8534 user = IS_USER(s);
9ee6e8bb 8535 if (rn == 15) {
7d1b0095 8536 addr = tcg_temp_new_i32();
9ee6e8bb
PB		 8537 /* PC relative. */
8538 /* s->pc has already been incremented by 4. */
8539 imm = s->pc & 0xfffffffc;
8540 if (insn & (1 << 23))
8541 imm += insn & 0xfff;
8542 else
8543 imm -= insn & 0xfff;
b0109805 8544 tcg_gen_movi_i32(addr, imm);
9ee6e8bb 8545 } else {
b0109805 8546 addr = load_reg(s, rn);
9ee6e8bb
PB		 8547 if (insn & (1 << 23)) {
8548 /* Positive offset. */
8549 imm = insn & 0xfff;
b0109805 8550 tcg_gen_addi_i32(addr, addr, imm);
9ee6e8bb 8551 } else {
9ee6e8bb 8552 imm = insn & 0xff;
2a0308c5
PM		 8553 switch ((insn >> 8) & 0xf) {
8554 case 0x0: /* Shifted Register. */
9ee6e8bb 8555 shift = (insn >> 4) & 0xf;
2a0308c5
PM		 8556 if (shift > 3) {
8557 tcg_temp_free_i32(addr);
18c9b560 8558 goto illegal_op;
2a0308c5 8559 }
b26eefb6 8560 tmp = load_reg(s, rm);
9ee6e8bb 8561 if (shift)
b26eefb6 8562 tcg_gen_shli_i32(tmp, tmp, shift);
b0109805 8563 tcg_gen_add_i32(addr, addr, tmp);
7d1b0095 8564 tcg_temp_free_i32(tmp);
9ee6e8bb 8565 break;
2a0308c5 8566 case 0xc: /* Negative offset. */
b0109805 8567 tcg_gen_addi_i32(addr, addr, -imm);
9ee6e8bb 8568 break;
2a0308c5 8569 case 0xe: /* User privilege. */
b0109805
PB		 8570 tcg_gen_addi_i32(addr, addr, imm);
8571 user = 1;
9ee6e8bb 8572 break;
2a0308c5 8573 case 0x9: /* Post-decrement. */
9ee6e8bb
PB		 8574 imm = -imm;
8575 /* Fall through. */
2a0308c5 8576 case 0xb: /* Post-increment. */
9ee6e8bb
PB		 8577 postinc = 1;
8578 writeback = 1;
8579 break;
2a0308c5 8580 case 0xd: /* Pre-decrement. */
9ee6e8bb
PB		 8581 imm = -imm;
8582 /* Fall through. */
2a0308c5 8583 case 0xf: /* Pre-increment. */
b0109805 8584 tcg_gen_addi_i32(addr, addr, imm);
9ee6e8bb
PB		 8585 writeback = 1;
8586 break;
8587 default:
2a0308c5 8588 tcg_temp_free_i32(addr);
b7bcbe95 8589 goto illegal_op;
9ee6e8bb
PB		 8590 }
8591 }
8592 }
9ee6e8bb
PB		 8593 if (insn & (1 << 20)) {
8594 /* Load. */
a2fdc890
PM		 8595 switch (op) {
8596 case 0: tmp = gen_ld8u(addr, user); break;
8597 case 4: tmp = gen_ld8s(addr, user); break;
8598 case 1: tmp = gen_ld16u(addr, user); break;
8599 case 5: tmp = gen_ld16s(addr, user); break;
8600 case 2: tmp = gen_ld32(addr, user); break;
2a0308c5
PM		 8601 default:
8602 tcg_temp_free_i32(addr);
8603 goto illegal_op;
a2fdc890
PM		 8604 }
8605 if (rs == 15) {
8606 gen_bx(s, tmp);
9ee6e8bb 8607 } else {
a2fdc890 8608 store_reg(s, rs, tmp);
9ee6e8bb
PB		 8609 }
8610 } else {
8611 /* Store. */
b0109805 8612 tmp = load_reg(s, rs);
9ee6e8bb 8613 switch (op) {
b0109805
PB		 8614 case 0: gen_st8(tmp, addr, user); break;
8615 case 1: gen_st16(tmp, addr, user); break;
8616 case 2: gen_st32(tmp, addr, user); break;
2a0308c5
PM		 8617 default:
8618 tcg_temp_free_i32(addr);
8619 goto illegal_op;
b7bcbe95 8620 }
2c0262af 8621 }
9ee6e8bb 8622 if (postinc)
b0109805
PB		 8623 tcg_gen_addi_i32(addr, addr, imm);
8624 if (writeback) {
8625 store_reg(s, rn, addr);
8626 } else {
7d1b0095 8627 tcg_temp_free_i32(addr);
b0109805 8628 }
9ee6e8bb
PB		 8629 }
8630 break;
8631 default:
8632 goto illegal_op;
2c0262af 8633 }
9ee6e8bb
PB		 8634 return 0;
8635illegal_op:
8636 return 1;
2c0262af
FB		 8637}
8638
9ee6e8bb 8639static void disas_thumb_insn(CPUState *env, DisasContext *s)
99c475ab
FB		 8640{
8641 uint32_t val, insn, op, rm, rn, rd, shift, cond;
8642 int32_t offset;
8643 int i;
b26eefb6 8644 TCGv tmp;
d9ba4830 8645 TCGv tmp2;
b0109805 8646 TCGv addr;
99c475ab 8647
9ee6e8bb
PB		 8648 if (s->condexec_mask) {
8649 cond = s->condexec_cond;
bedd2912
JB		 8650 if (cond != 0x0e) { /* Skip conditional when condition is AL. */
8651 s->condlabel = gen_new_label();
8652 gen_test_cc(cond ^ 1, s->condlabel);
8653 s->condjmp = 1;
8654 }
9ee6e8bb
PB		 8655 }
8656
b5ff1b31 8657 insn = lduw_code(s->pc);
99c475ab 8658 s->pc += 2;
b5ff1b31 8659
99c475ab
FB		 8660 switch (insn >> 12) {
8661 case 0: case 1:
396e467c 8662
99c475ab
FB		 8663 rd = insn & 7;
8664 op = (insn >> 11) & 3;
8665 if (op == 3) {
8666 /* add/subtract */
8667 rn = (insn >> 3) & 7;
396e467c 8668 tmp = load_reg(s, rn);
99c475ab
FB		 8669 if (insn & (1 << 10)) {
8670 /* immediate */
7d1b0095 8671 tmp2 = tcg_temp_new_i32();
396e467c 8672 tcg_gen_movi_i32(tmp2, (insn >> 6) & 7);
99c475ab
FB		 8673 } else {
8674 /* reg */
8675 rm = (insn >> 6) & 7;
396e467c 8676 tmp2 = load_reg(s, rm);
99c475ab 8677 }
9ee6e8bb
PB		 8678 if (insn & (1 << 9)) {
8679 if (s->condexec_mask)
396e467c 8680 tcg_gen_sub_i32(tmp, tmp, tmp2);
9ee6e8bb 8681 else
396e467c 8682 gen_helper_sub_cc(tmp, tmp, tmp2);
9ee6e8bb
PB		 8683 } else {
8684 if (s->condexec_mask)
396e467c 8685 tcg_gen_add_i32(tmp, tmp, tmp2);
9ee6e8bb 8686 else
396e467c 8687 gen_helper_add_cc(tmp, tmp, tmp2);
9ee6e8bb 8688 }
7d1b0095 8689 tcg_temp_free_i32(tmp2);
396e467c 8690 store_reg(s, rd, tmp);
99c475ab
FB		 8691 } else {
8692 /* shift immediate */
8693 rm = (insn >> 3) & 7;
8694 shift = (insn >> 6) & 0x1f;
9a119ff6
PB		 8695 tmp = load_reg(s, rm);
8696 gen_arm_shift_im(tmp, op, shift, s->condexec_mask == 0);
8697 if (!s->condexec_mask)
8698 gen_logic_CC(tmp);
8699 store_reg(s, rd, tmp);
99c475ab
FB		 8700 }
8701 break;
8702 case 2: case 3:
8703 /* arithmetic large immediate */
8704 op = (insn >> 11) & 3;
8705 rd = (insn >> 8) & 0x7;
396e467c 8706 if (op == 0) { /* mov */
7d1b0095 8707 tmp = tcg_temp_new_i32();
396e467c 8708 tcg_gen_movi_i32(tmp, insn & 0xff);
9ee6e8bb 8709 if (!s->condexec_mask)
396e467c
FN		 8710 gen_logic_CC(tmp);
8711 store_reg(s, rd, tmp);
8712 } else {
8713 tmp = load_reg(s, rd);
7d1b0095 8714 tmp2 = tcg_temp_new_i32();
396e467c
FN		 8715 tcg_gen_movi_i32(tmp2, insn & 0xff);
8716 switch (op) {
8717 case 1: /* cmp */
8718 gen_helper_sub_cc(tmp, tmp, tmp2);
7d1b0095
PM		 8719 tcg_temp_free_i32(tmp);
8720 tcg_temp_free_i32(tmp2);
396e467c
FN		 8721 break;
8722 case 2: /* add */
8723 if (s->condexec_mask)
8724 tcg_gen_add_i32(tmp, tmp, tmp2);
8725 else
8726 gen_helper_add_cc(tmp, tmp, tmp2);
7d1b0095 8727 tcg_temp_free_i32(tmp2);
396e467c
FN		 8728 store_reg(s, rd, tmp);
8729 break;
8730 case 3: /* sub */
8731 if (s->condexec_mask)
8732 tcg_gen_sub_i32(tmp, tmp, tmp2);
8733 else
8734 gen_helper_sub_cc(tmp, tmp, tmp2);
7d1b0095 8735 tcg_temp_free_i32(tmp2);
396e467c
FN		 8736 store_reg(s, rd, tmp);
8737 break;
8738 }
99c475ab 8739 }
99c475ab
FB		 8740 break;
8741 case 4:
8742 if (insn & (1 << 11)) {
8743 rd = (insn >> 8) & 7;
5899f386
FB		 8744 /* load pc-relative. Bit 1 of PC is ignored. */
8745 val = s->pc + 2 + ((insn & 0xff) * 4);
8746 val &= ~(uint32_t)2;
7d1b0095 8747 addr = tcg_temp_new_i32();
b0109805
PB		 8748 tcg_gen_movi_i32(addr, val);
8749 tmp = gen_ld32(addr, IS_USER(s));
7d1b0095 8750 tcg_temp_free_i32(addr);
b0109805 8751 store_reg(s, rd, tmp);
99c475ab
FB		 8752 break;
8753 }
8754 if (insn & (1 << 10)) {
8755 /* data processing extended or blx */
8756 rd = (insn & 7) | ((insn >> 4) & 8);
8757 rm = (insn >> 3) & 0xf;
8758 op = (insn >> 8) & 3;
8759 switch (op) {
8760 case 0: /* add */
396e467c
FN		 8761 tmp = load_reg(s, rd);
8762 tmp2 = load_reg(s, rm);
8763 tcg_gen_add_i32(tmp, tmp, tmp2);
7d1b0095 8764 tcg_temp_free_i32(tmp2);
396e467c 8765 store_reg(s, rd, tmp);
99c475ab
FB		 8766 break;
8767 case 1: /* cmp */
396e467c
FN		 8768 tmp = load_reg(s, rd);
8769 tmp2 = load_reg(s, rm);
8770 gen_helper_sub_cc(tmp, tmp, tmp2);
7d1b0095
PM		 8771 tcg_temp_free_i32(tmp2);
8772 tcg_temp_free_i32(tmp);
99c475ab
FB		 8773 break;
8774 case 2: /* mov/cpy */
396e467c
FN		 8775 tmp = load_reg(s, rm);
8776 store_reg(s, rd, tmp);
99c475ab
FB		 8777 break;
8778 case 3:/* branch [and link] exchange thumb register */
b0109805 8779 tmp = load_reg(s, rm);
99c475ab 8780 if (insn & (1 << 7)) {
be5e7a76 8781 ARCH(5);
99c475ab 8782 val = (uint32_t)s->pc | 1;
7d1b0095 8783 tmp2 = tcg_temp_new_i32();
b0109805
PB		 8784 tcg_gen_movi_i32(tmp2, val);
8785 store_reg(s, 14, tmp2);
99c475ab 8786 }
be5e7a76 8787 /* already thumb, no need to check */
d9ba4830 8788 gen_bx(s, tmp);
99c475ab
FB		 8789 break;
8790 }
8791 break;
8792 }
8793
8794 /* data processing register */
8795 rd = insn & 7;
8796 rm = (insn >> 3) & 7;
8797 op = (insn >> 6) & 0xf;
8798 if (op == 2 || op == 3 || op == 4 || op == 7) {
8799 /* the shift/rotate ops want the operands backwards */
8800 val = rm;
8801 rm = rd;
8802 rd = val;
8803 val = 1;
8804 } else {
8805 val = 0;
8806 }
8807
396e467c 8808 if (op == 9) { /* neg */
7d1b0095 8809 tmp = tcg_temp_new_i32();
396e467c
FN		 8810 tcg_gen_movi_i32(tmp, 0);
8811 } else if (op != 0xf) { /* mvn doesn't read its first operand */
8812 tmp = load_reg(s, rd);
8813 } else {
8814 TCGV_UNUSED(tmp);
8815 }
99c475ab 8816
396e467c 8817 tmp2 = load_reg(s, rm);
5899f386 8818 switch (op) {
99c475ab 8819 case 0x0: /* and */
396e467c 8820 tcg_gen_and_i32(tmp, tmp, tmp2);
9ee6e8bb 8821 if (!s->condexec_mask)
396e467c 8822 gen_logic_CC(tmp);
99c475ab
FB		 8823 break;
8824 case 0x1: /* eor */
396e467c 8825 tcg_gen_xor_i32(tmp, tmp, tmp2);
9ee6e8bb 8826 if (!s->condexec_mask)
396e467c 8827 gen_logic_CC(tmp);
99c475ab
FB		 8828 break;
8829 case 0x2: /* lsl */
9ee6e8bb 8830 if (s->condexec_mask) {
396e467c 8831 gen_helper_shl(tmp2, tmp2, tmp);
9ee6e8bb 8832 } else {
396e467c
FN		 8833 gen_helper_shl_cc(tmp2, tmp2, tmp);
8834 gen_logic_CC(tmp2);
9ee6e8bb 8835 }
99c475ab
FB		 8836 break;
8837 case 0x3: /* lsr */
9ee6e8bb 8838 if (s->condexec_mask) {
396e467c 8839 gen_helper_shr(tmp2, tmp2, tmp);
9ee6e8bb 8840 } else {
396e467c
FN		 8841 gen_helper_shr_cc(tmp2, tmp2, tmp);
8842 gen_logic_CC(tmp2);
9ee6e8bb 8843 }
99c475ab
FB		 8844 break;
8845 case 0x4: /* asr */
9ee6e8bb 8846 if (s->condexec_mask) {
396e467c 8847 gen_helper_sar(tmp2, tmp2, tmp);
9ee6e8bb 8848 } else {
396e467c
FN		 8849 gen_helper_sar_cc(tmp2, tmp2, tmp);
8850 gen_logic_CC(tmp2);
9ee6e8bb 8851 }
99c475ab
FB		 8852 break;
8853 case 0x5: /* adc */
9ee6e8bb 8854 if (s->condexec_mask)
396e467c 8855 gen_adc(tmp, tmp2);
9ee6e8bb 8856 else
396e467c 8857 gen_helper_adc_cc(tmp, tmp, tmp2);
99c475ab
FB		 8858 break;
8859 case 0x6: /* sbc */
9ee6e8bb 8860 if (s->condexec_mask)
396e467c 8861 gen_sub_carry(tmp, tmp, tmp2);
9ee6e8bb 8862 else
396e467c 8863 gen_helper_sbc_cc(tmp, tmp, tmp2);
99c475ab
FB		 8864 break;
8865 case 0x7: /* ror */
9ee6e8bb 8866 if (s->condexec_mask) {
f669df27
AJ		 8867 tcg_gen_andi_i32(tmp, tmp, 0x1f);
8868 tcg_gen_rotr_i32(tmp2, tmp2, tmp);
9ee6e8bb 8869 } else {
396e467c
FN		 8870 gen_helper_ror_cc(tmp2, tmp2, tmp);
8871 gen_logic_CC(tmp2);
9ee6e8bb 8872 }
99c475ab
FB		 8873 break;
8874 case 0x8: /* tst */
396e467c
FN		 8875 tcg_gen_and_i32(tmp, tmp, tmp2);
8876 gen_logic_CC(tmp);
99c475ab 8877 rd = 16;
5899f386 8878 break;
99c475ab 8879 case 0x9: /* neg */
9ee6e8bb 8880 if (s->condexec_mask)
396e467c 8881 tcg_gen_neg_i32(tmp, tmp2);
9ee6e8bb 8882 else
396e467c 8883 gen_helper_sub_cc(tmp, tmp, tmp2);
99c475ab
FB		 8884 break;
8885 case 0xa: /* cmp */
396e467c 8886 gen_helper_sub_cc(tmp, tmp, tmp2);
99c475ab
FB		 8887 rd = 16;
8888 break;
8889 case 0xb: /* cmn */
396e467c 8890 gen_helper_add_cc(tmp, tmp, tmp2);
99c475ab
FB		 8891 rd = 16;
8892 break;
8893 case 0xc: /* orr */
396e467c 8894 tcg_gen_or_i32(tmp, tmp, tmp2);
9ee6e8bb 8895 if (!s->condexec_mask)
396e467c 8896 gen_logic_CC(tmp);
99c475ab
FB		 8897 break;
8898 case 0xd: /* mul */
7b2919a0 8899 tcg_gen_mul_i32(tmp, tmp, tmp2);
9ee6e8bb 8900 if (!s->condexec_mask)
396e467c 8901 gen_logic_CC(tmp);
99c475ab
FB		 8902 break;
8903 case 0xe: /* bic */
f669df27 8904 tcg_gen_andc_i32(tmp, tmp, tmp2);
9ee6e8bb 8905 if (!s->condexec_mask)
396e467c 8906 gen_logic_CC(tmp);
99c475ab
FB		 8907 break;
8908 case 0xf: /* mvn */
396e467c 8909 tcg_gen_not_i32(tmp2, tmp2);
9ee6e8bb 8910 if (!s->condexec_mask)
396e467c 8911 gen_logic_CC(tmp2);
99c475ab 8912 val = 1;
5899f386 8913 rm = rd;
99c475ab
FB		 8914 break;
8915 }
8916 if (rd != 16) {
396e467c
FN		 8917 if (val) {
8918 store_reg(s, rm, tmp2);
8919 if (op != 0xf)
7d1b0095 8920 tcg_temp_free_i32(tmp);
396e467c
FN		 8921 } else {
8922 store_reg(s, rd, tmp);
7d1b0095 8923 tcg_temp_free_i32(tmp2);
396e467c
FN		 8924 }
8925 } else {
7d1b0095
PM		 8926 tcg_temp_free_i32(tmp);
8927 tcg_temp_free_i32(tmp2);
99c475ab
FB		 8928 }
8929 break;
8930
8931 case 5:
8932 /* load/store register offset. */
8933 rd = insn & 7;
8934 rn = (insn >> 3) & 7;
8935 rm = (insn >> 6) & 7;
8936 op = (insn >> 9) & 7;
b0109805 8937 addr = load_reg(s, rn);
b26eefb6 8938 tmp = load_reg(s, rm);
b0109805 8939 tcg_gen_add_i32(addr, addr, tmp);
7d1b0095 8940 tcg_temp_free_i32(tmp);
99c475ab
FB		 8941
8942 if (op < 3) /* store */
b0109805 8943 tmp = load_reg(s, rd);
99c475ab
FB		 8944
8945 switch (op) {
8946 case 0: /* str */
b0109805 8947 gen_st32(tmp, addr, IS_USER(s));
99c475ab
FB		 8948 break;
8949 case 1: /* strh */
b0109805 8950 gen_st16(tmp, addr, IS_USER(s));
99c475ab
FB		 8951 break;
8952 case 2: /* strb */
b0109805 8953 gen_st8(tmp, addr, IS_USER(s));
99c475ab
FB		 8954 break;
8955 case 3: /* ldrsb */
b0109805 8956 tmp = gen_ld8s(addr, IS_USER(s));
99c475ab
FB		 8957 break;
8958 case 4: /* ldr */
b0109805 8959 tmp = gen_ld32(addr, IS_USER(s));
99c475ab
FB		 8960 break;
8961 case 5: /* ldrh */
b0109805 8962 tmp = gen_ld16u(addr, IS_USER(s));
99c475ab
FB		 8963 break;
8964 case 6: /* ldrb */
b0109805 8965 tmp = gen_ld8u(addr, IS_USER(s));
99c475ab
FB		 8966 break;
8967 case 7: /* ldrsh */
b0109805 8968 tmp = gen_ld16s(addr, IS_USER(s));
99c475ab
FB		 8969 break;
8970 }
8971 if (op >= 3) /* load */
b0109805 8972 store_reg(s, rd, tmp);
7d1b0095 8973 tcg_temp_free_i32(addr);
99c475ab
FB		 8974 break;
8975
8976 case 6:
8977 /* load/store word immediate offset */
8978 rd = insn & 7;
8979 rn = (insn >> 3) & 7;
b0109805 8980 addr = load_reg(s, rn);
99c475ab 8981 val = (insn >> 4) & 0x7c;
b0109805 8982 tcg_gen_addi_i32(addr, addr, val);
99c475ab
FB		 8983
8984 if (insn & (1 << 11)) {
8985 /* load */
b0109805
PB		 8986 tmp = gen_ld32(addr, IS_USER(s));
8987 store_reg(s, rd, tmp);
99c475ab
FB		 8988 } else {
8989 /* store */
b0109805
PB		 8990 tmp = load_reg(s, rd);
8991 gen_st32(tmp, addr, IS_USER(s));
99c475ab 8992 }
7d1b0095 8993 tcg_temp_free_i32(addr);
99c475ab
FB		 8994 break;
8995
8996 case 7:
8997 /* load/store byte immediate offset */
8998 rd = insn & 7;
8999 rn = (insn >> 3) & 7;
b0109805 9000 addr = load_reg(s, rn);
99c475ab 9001 val = (insn >> 6) & 0x1f;
b0109805 9002 tcg_gen_addi_i32(addr, addr, val);
99c475ab
FB		 9003
9004 if (insn & (1 << 11)) {
9005 /* load */
b0109805
PB		 9006 tmp = gen_ld8u(addr, IS_USER(s));
9007 store_reg(s, rd, tmp);
99c475ab
FB		 9008 } else {
9009 /* store */
b0109805
PB		 9010 tmp = load_reg(s, rd);
9011 gen_st8(tmp, addr, IS_USER(s));
99c475ab 9012 }
7d1b0095 9013 tcg_temp_free_i32(addr);
99c475ab
FB		 9014 break;
9015
9016 case 8:
9017 /* load/store halfword immediate offset */
9018 rd = insn & 7;
9019 rn = (insn >> 3) & 7;
b0109805 9020 addr = load_reg(s, rn);
99c475ab 9021 val = (insn >> 5) & 0x3e;
b0109805 9022 tcg_gen_addi_i32(addr, addr, val);
99c475ab
FB		 9023
9024 if (insn & (1 << 11)) {
9025 /* load */
b0109805
PB		 9026 tmp = gen_ld16u(addr, IS_USER(s));
9027 store_reg(s, rd, tmp);
99c475ab
FB		 9028 } else {
9029 /* store */
b0109805
PB		 9030 tmp = load_reg(s, rd);
9031 gen_st16(tmp, addr, IS_USER(s));
99c475ab 9032 }
7d1b0095 9033 tcg_temp_free_i32(addr);
99c475ab
FB		 9034 break;
9035
9036 case 9:
9037 /* load/store from stack */
9038 rd = (insn >> 8) & 7;
b0109805 9039 addr = load_reg(s, 13);
99c475ab 9040 val = (insn & 0xff) * 4;
b0109805 9041 tcg_gen_addi_i32(addr, addr, val);
99c475ab
FB		 9042
9043 if (insn & (1 << 11)) {
9044 /* load */
b0109805
PB		 9045 tmp = gen_ld32(addr, IS_USER(s));
9046 store_reg(s, rd, tmp);
99c475ab
FB		 9047 } else {
9048 /* store */
b0109805
PB		 9049 tmp = load_reg(s, rd);
9050 gen_st32(tmp, addr, IS_USER(s));
99c475ab 9051 }
7d1b0095 9052 tcg_temp_free_i32(addr);
99c475ab
FB		 9053 break;
9054
9055 case 10:
9056 /* add to high reg */
9057 rd = (insn >> 8) & 7;
5899f386
FB		 9058 if (insn & (1 << 11)) {
9059 /* SP */
5e3f878a 9060 tmp = load_reg(s, 13);
5899f386
FB		 9061 } else {
9062 /* PC. bit 1 is ignored. */
7d1b0095 9063 tmp = tcg_temp_new_i32();
5e3f878a 9064 tcg_gen_movi_i32(tmp, (s->pc + 2) & ~(uint32_t)2);
5899f386 9065 }
99c475ab 9066 val = (insn & 0xff) * 4;
5e3f878a
PB		 9067 tcg_gen_addi_i32(tmp, tmp, val);
9068 store_reg(s, rd, tmp);
99c475ab
FB		 9069 break;
9070
9071 case 11:
9072 /* misc */
9073 op = (insn >> 8) & 0xf;
9074 switch (op) {
9075 case 0:
9076 /* adjust stack pointer */
b26eefb6 9077 tmp = load_reg(s, 13);
99c475ab
FB		 9078 val = (insn & 0x7f) * 4;
9079 if (insn & (1 << 7))
6a0d8a1d 9080 val = -(int32_t)val;
b26eefb6
PB		 9081 tcg_gen_addi_i32(tmp, tmp, val);
9082 store_reg(s, 13, tmp);
99c475ab
FB		 9083 break;
9084
9ee6e8bb
PB		 9085 case 2: /* sign/zero extend. */
9086 ARCH(6);
9087 rd = insn & 7;
9088 rm = (insn >> 3) & 7;
b0109805 9089 tmp = load_reg(s, rm);
9ee6e8bb 9090 switch ((insn >> 6) & 3) {
b0109805
PB		 9091 case 0: gen_sxth(tmp); break;
9092 case 1: gen_sxtb(tmp); break;
9093 case 2: gen_uxth(tmp); break;
9094 case 3: gen_uxtb(tmp); break;
9ee6e8bb 9095 }
b0109805 9096 store_reg(s, rd, tmp);
9ee6e8bb 9097 break;
99c475ab
FB		 9098 case 4: case 5: case 0xc: case 0xd:
9099 /* push/pop */
b0109805 9100 addr = load_reg(s, 13);
5899f386
FB		 9101 if (insn & (1 << 8))
9102 offset = 4;
99c475ab 9103 else
5899f386
FB		 9104 offset = 0;
9105 for (i = 0; i < 8; i++) {
9106 if (insn & (1 << i))
9107 offset += 4;
9108 }
9109 if ((insn & (1 << 11)) == 0) {
b0109805 9110 tcg_gen_addi_i32(addr, addr, -offset);
5899f386 9111 }
99c475ab
FB		 9112 for (i = 0; i < 8; i++) {
9113 if (insn & (1 << i)) {
9114 if (insn & (1 << 11)) {
9115 /* pop */
b0109805
PB		 9116 tmp = gen_ld32(addr, IS_USER(s));
9117 store_reg(s, i, tmp);
99c475ab
FB		 9118 } else {
9119 /* push */
b0109805
PB		 9120 tmp = load_reg(s, i);
9121 gen_st32(tmp, addr, IS_USER(s));
99c475ab 9122 }
5899f386 9123 /* advance to the next address. */
b0109805 9124 tcg_gen_addi_i32(addr, addr, 4);
99c475ab
FB		 9125 }
9126 }
a50f5b91 9127 TCGV_UNUSED(tmp);
99c475ab
FB		 9128 if (insn & (1 << 8)) {
9129 if (insn & (1 << 11)) {
9130 /* pop pc */
b0109805 9131 tmp = gen_ld32(addr, IS_USER(s));
99c475ab
FB		 9132 /* don't set the pc until the rest of the instruction
9133 has completed */
9134 } else {
9135 /* push lr */
b0109805
PB		 9136 tmp = load_reg(s, 14);
9137 gen_st32(tmp, addr, IS_USER(s));
99c475ab 9138 }
b0109805 9139 tcg_gen_addi_i32(addr, addr, 4);
99c475ab 9140 }
5899f386 9141 if ((insn & (1 << 11)) == 0) {
b0109805 9142 tcg_gen_addi_i32(addr, addr, -offset);
5899f386 9143 }
99c475ab 9144 /* write back the new stack pointer */
b0109805 9145 store_reg(s, 13, addr);
99c475ab 9146 /* set the new PC value */
be5e7a76
DES		 9147 if ((insn & 0x0900) == 0x0900) {
9148 store_reg_from_load(env, s, 15, tmp);
9149 }
99c475ab
FB		 9150 break;
9151
9ee6e8bb
PB		 9152 case 1: case 3: case 9: case 11: /* czb */
9153 rm = insn & 7;
d9ba4830 9154 tmp = load_reg(s, rm);
9ee6e8bb
PB		 9155 s->condlabel = gen_new_label();
9156 s->condjmp = 1;
9157 if (insn & (1 << 11))
cb63669a 9158 tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, s->condlabel);
9ee6e8bb 9159 else
cb63669a 9160 tcg_gen_brcondi_i32(TCG_COND_NE, tmp, 0, s->condlabel);
7d1b0095 9161 tcg_temp_free_i32(tmp);
9ee6e8bb
PB		 9162 offset = ((insn & 0xf8) >> 2) | (insn & 0x200) >> 3;
9163 val = (uint32_t)s->pc + 2;
9164 val += offset;
9165 gen_jmp(s, val);
9166 break;
9167
9168 case 15: /* IT, nop-hint. */
9169 if ((insn & 0xf) == 0) {
9170 gen_nop_hint(s, (insn >> 4) & 0xf);
9171 break;
9172 }
9173 /* If Then. */
9174 s->condexec_cond = (insn >> 4) & 0xe;
9175 s->condexec_mask = insn & 0x1f;
9176 /* No actual code generated for this insn, just setup state. */
9177 break;
9178
06c949e6 9179 case 0xe: /* bkpt */
be5e7a76 9180 ARCH(5);
bc4a0de0 9181 gen_exception_insn(s, 2, EXCP_BKPT);
06c949e6
PB		 9182 break;
9183
9ee6e8bb
PB		 9184 case 0xa: /* rev */
9185 ARCH(6);
9186 rn = (insn >> 3) & 0x7;
9187 rd = insn & 0x7;
b0109805 9188 tmp = load_reg(s, rn);
9ee6e8bb 9189 switch ((insn >> 6) & 3) {
66896cb8 9190 case 0: tcg_gen_bswap32_i32(tmp, tmp); break;
b0109805
PB		 9191 case 1: gen_rev16(tmp); break;
9192 case 3: gen_revsh(tmp); break;
9ee6e8bb
PB		 9193 default: goto illegal_op;
9194 }
b0109805 9195 store_reg(s, rd, tmp);
9ee6e8bb
PB		 9196 break;
9197
9198 case 6: /* cps */
9199 ARCH(6);
9200 if (IS_USER(s))
9201 break;
9202 if (IS_M(env)) {
8984bd2e 9203 tmp = tcg_const_i32((insn & (1 << 4)) != 0);
9ee6e8bb 9204 /* PRIMASK */
8984bd2e
PB		 9205 if (insn & 1) {
9206 addr = tcg_const_i32(16);
9207 gen_helper_v7m_msr(cpu_env, addr, tmp);
b75263d6 9208 tcg_temp_free_i32(addr);
8984bd2e 9209 }
9ee6e8bb 9210 /* FAULTMASK */
8984bd2e
PB		 9211 if (insn & 2) {
9212 addr = tcg_const_i32(17);
9213 gen_helper_v7m_msr(cpu_env, addr, tmp);
b75263d6 9214 tcg_temp_free_i32(addr);
8984bd2e 9215 }
b75263d6 9216 tcg_temp_free_i32(tmp);
9ee6e8bb
PB		 9217 gen_lookup_tb(s);
9218 } else {
9219 if (insn & (1 << 4))
9220 shift = CPSR_A | CPSR_I | CPSR_F;
9221 else
9222 shift = 0;
fa26df03 9223 gen_set_psr_im(s, ((insn & 7) << 6), 0, shift);
9ee6e8bb
PB		 9224 }
9225 break;
9226
99c475ab
FB		 9227 default:
9228 goto undef;
9229 }
9230 break;
9231
9232 case 12:
9233 /* load/store multiple */
9234 rn = (insn >> 8) & 0x7;
b0109805 9235 addr = load_reg(s, rn);
99c475ab
FB		 9236 for (i = 0; i < 8; i++) {
9237 if (insn & (1 << i)) {
99c475ab
FB		 9238 if (insn & (1 << 11)) {
9239 /* load */
b0109805
PB		 9240 tmp = gen_ld32(addr, IS_USER(s));
9241 store_reg(s, i, tmp);
99c475ab
FB		 9242 } else {
9243 /* store */
b0109805
PB		 9244 tmp = load_reg(s, i);
9245 gen_st32(tmp, addr, IS_USER(s));
99c475ab 9246 }
5899f386 9247 /* advance to the next address */
b0109805 9248 tcg_gen_addi_i32(addr, addr, 4);
99c475ab
FB		 9249 }
9250 }
5899f386 9251 /* Base register writeback. */
b0109805
PB		 9252 if ((insn & (1 << rn)) == 0) {
9253 store_reg(s, rn, addr);
9254 } else {
7d1b0095 9255 tcg_temp_free_i32(addr);
b0109805 9256 }
99c475ab
FB		 9257 break;
9258
9259 case 13:
9260 /* conditional branch or swi */
9261 cond = (insn >> 8) & 0xf;
9262 if (cond == 0xe)
9263 goto undef;
9264
9265 if (cond == 0xf) {
9266 /* swi */
422ebf69 9267 gen_set_pc_im(s->pc);
9ee6e8bb 9268 s->is_jmp = DISAS_SWI;
99c475ab
FB		 9269 break;
9270 }
9271 /* generate a conditional jump to next instruction */
e50e6a20 9272 s->condlabel = gen_new_label();
d9ba4830 9273 gen_test_cc(cond ^ 1, s->condlabel);
e50e6a20 9274 s->condjmp = 1;
99c475ab
FB		 9275
9276 /* jump to the offset */
5899f386 9277 val = (uint32_t)s->pc + 2;
99c475ab 9278 offset = ((int32_t)insn << 24) >> 24;
5899f386 9279 val += offset << 1;
8aaca4c0 9280 gen_jmp(s, val);
99c475ab
FB		 9281 break;
9282
9283 case 14:
358bf29e 9284 if (insn & (1 << 11)) {
9ee6e8bb
PB		 9285 if (disas_thumb2_insn(env, s, insn))
9286 goto undef32;
358bf29e
PB		 9287 break;
9288 }
9ee6e8bb 9289 /* unconditional branch */
99c475ab
FB		 9290 val = (uint32_t)s->pc;
9291 offset = ((int32_t)insn << 21) >> 21;
9292 val += (offset << 1) + 2;
8aaca4c0 9293 gen_jmp(s, val);
99c475ab
FB		 9294 break;
9295
9296 case 15:
9ee6e8bb 9297 if (disas_thumb2_insn(env, s, insn))
6a0d8a1d 9298 goto undef32;
9ee6e8bb 9299 break;
99c475ab
FB		 9300 }
9301 return;
9ee6e8bb 9302undef32:
bc4a0de0 9303 gen_exception_insn(s, 4, EXCP_UDEF);
9ee6e8bb
PB		 9304 return;
9305illegal_op:
99c475ab 9306undef:
bc4a0de0 9307 gen_exception_insn(s, 2, EXCP_UDEF);
99c475ab
FB		 9308}
9309
2c0262af
FB		 9310/* generate intermediate code in gen_opc_buf and gen_opparam_buf for
9311 basic block 'tb'. If search_pc is TRUE, also generate PC
9312 information for each intermediate instruction. */
2cfc5f17
TS		 9313static inline void gen_intermediate_code_internal(CPUState *env,
9314 TranslationBlock *tb,
9315 int search_pc)
2c0262af
FB		 9316{
9317 DisasContext dc1, *dc = &dc1;
a1d1bb31 9318 CPUBreakpoint *bp;
2c0262af
FB		 9319 uint16_t *gen_opc_end;
9320 int j, lj;
0fa85d43 9321 target_ulong pc_start;
b5ff1b31 9322 uint32_t next_page_start;
2e70f6ef
PB		 9323 int num_insns;
9324 int max_insns;
3b46e624 9325
2c0262af 9326 /* generate intermediate code */
0fa85d43 9327 pc_start = tb->pc;
3b46e624 9328
2c0262af
FB		 9329 dc->tb = tb;
9330
2c0262af 9331 gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
2c0262af
FB		 9332
9333 dc->is_jmp = DISAS_NEXT;
9334 dc->pc = pc_start;
8aaca4c0 9335 dc->singlestep_enabled = env->singlestep_enabled;
e50e6a20 9336 dc->condjmp = 0;
7204ab88 9337 dc->thumb = ARM_TBFLAG_THUMB(tb->flags);
98eac7ca
PM		 9338 dc->condexec_mask = (ARM_TBFLAG_CONDEXEC(tb->flags) & 0xf) << 1;
9339 dc->condexec_cond = ARM_TBFLAG_CONDEXEC(tb->flags) >> 4;
b5ff1b31 9340#if !defined(CONFIG_USER_ONLY)
61f74d6a 9341 dc->user = (ARM_TBFLAG_PRIV(tb->flags) == 0);
b5ff1b31 9342#endif
5df8bac1 9343 dc->vfp_enabled = ARM_TBFLAG_VFPEN(tb->flags);
69d1fc22
PM		 9344 dc->vec_len = ARM_TBFLAG_VECLEN(tb->flags);
9345 dc->vec_stride = ARM_TBFLAG_VECSTRIDE(tb->flags);
a7812ae4
PB		 9346 cpu_F0s = tcg_temp_new_i32();
9347 cpu_F1s = tcg_temp_new_i32();
9348 cpu_F0d = tcg_temp_new_i64();
9349 cpu_F1d = tcg_temp_new_i64();
ad69471c
PB		 9350 cpu_V0 = cpu_F0d;
9351 cpu_V1 = cpu_F1d;
e677137d 9352 /* FIXME: cpu_M0 can probably be the same as cpu_V0. */
a7812ae4 9353 cpu_M0 = tcg_temp_new_i64();
b5ff1b31 9354 next_page_start = (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
2c0262af 9355 lj = -1;
2e70f6ef
PB		 9356 num_insns = 0;
9357 max_insns = tb->cflags & CF_COUNT_MASK;
9358 if (max_insns == 0)
9359 max_insns = CF_COUNT_MASK;
9360
9361 gen_icount_start();
e12ce78d 9362
3849902c
PM		 9363 tcg_clear_temp_count();
9364
e12ce78d
PM		 9365 /* A note on handling of the condexec (IT) bits:
9366 *
9367 * We want to avoid the overhead of having to write the updated condexec
9368 * bits back to the CPUState for every instruction in an IT block. So:
9369 * (1) if the condexec bits are not already zero then we write
9370 * zero back into the CPUState now. This avoids complications trying
9371 * to do it at the end of the block. (For example if we don't do this
9372 * it's hard to identify whether we can safely skip writing condexec
9373 * at the end of the TB, which we definitely want to do for the case
9374 * where a TB doesn't do anything with the IT state at all.)
9375 * (2) if we are going to leave the TB then we call gen_set_condexec()
9376 * which will write the correct value into CPUState if zero is wrong.
9377 * This is done both for leaving the TB at the end, and for leaving
9378 * it because of an exception we know will happen, which is done in
9379 * gen_exception_insn(). The latter is necessary because we need to
9380 * leave the TB with the PC/IT state just prior to execution of the
9381 * instruction which caused the exception.
9382 * (3) if we leave the TB unexpectedly (eg a data abort on a load)
9383 * then the CPUState will be wrong and we need to reset it.
9384 * This is handled in the same way as restoration of the
9385 * PC in these situations: we will be called again with search_pc=1
9386 * and generate a mapping of the condexec bits for each PC in
9387 * gen_opc_condexec_bits[]. gen_pc_load[] then uses this to restore
9388 * the condexec bits.
9389 *
9390 * Note that there are no instructions which can read the condexec
9391 * bits, and none which can write non-static values to them, so
9392 * we don't need to care about whether CPUState is correct in the
9393 * middle of a TB.
9394 */
9395
9ee6e8bb
PB		 9396 /* Reset the conditional execution bits immediately. This avoids
9397 complications trying to do it at the end of the block. */
98eac7ca 9398 if (dc->condexec_mask || dc->condexec_cond)
8f01245e 9399 {
7d1b0095 9400 TCGv tmp = tcg_temp_new_i32();
8f01245e 9401 tcg_gen_movi_i32(tmp, 0);
d9ba4830 9402 store_cpu_field(tmp, condexec_bits);
8f01245e 9403 }
2c0262af 9404 do {
fbb4a2e3
PB		 9405#ifdef CONFIG_USER_ONLY
9406 /* Intercept jump to the magic kernel page. */
9407 if (dc->pc >= 0xffff0000) {
9408 /* We always get here via a jump, so know we are not in a
9409 conditional execution block. */
9410 gen_exception(EXCP_KERNEL_TRAP);
9411 dc->is_jmp = DISAS_UPDATE;
9412 break;
9413 }
9414#else
9ee6e8bb
PB		 9415 if (dc->pc >= 0xfffffff0 && IS_M(env)) {
9416 /* We always get here via a jump, so know we are not in a
9417 conditional execution block. */
d9ba4830 9418 gen_exception(EXCP_EXCEPTION_EXIT);
d60bb01c
PB		 9419 dc->is_jmp = DISAS_UPDATE;
9420 break;
9ee6e8bb
PB		 9421 }
9422#endif
9423
72cf2d4f
BS		 9424 if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) {
9425 QTAILQ_FOREACH(bp, &env->breakpoints, entry) {
a1d1bb31 9426 if (bp->pc == dc->pc) {
bc4a0de0 9427 gen_exception_insn(dc, 0, EXCP_DEBUG);
9ee6e8bb
PB		 9428 /* Advance PC so that clearing the breakpoint will
9429 invalidate this TB. */
9430 dc->pc += 2;
9431 goto done_generating;
1fddef4b
FB		 9432 break;
9433 }
9434 }
9435 }
2c0262af
FB		 9436 if (search_pc) {
9437 j = gen_opc_ptr - gen_opc_buf;
9438 if (lj < j) {
9439 lj++;
9440 while (lj < j)
9441 gen_opc_instr_start[lj++] = 0;
9442 }
0fa85d43 9443 gen_opc_pc[lj] = dc->pc;
e12ce78d 9444 gen_opc_condexec_bits[lj] = (dc->condexec_cond << 4) | (dc->condexec_mask >> 1);
2c0262af 9445 gen_opc_instr_start[lj] = 1;
2e70f6ef 9446 gen_opc_icount[lj] = num_insns;
2c0262af 9447 }
e50e6a20 9448
2e70f6ef
PB		 9449 if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO))
9450 gen_io_start();
9451
5642463a
PM		 9452 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP))) {
9453 tcg_gen_debug_insn_start(dc->pc);
9454 }
9455
7204ab88 9456 if (dc->thumb) {
9ee6e8bb
PB		 9457 disas_thumb_insn(env, dc);
9458 if (dc->condexec_mask) {
9459 dc->condexec_cond = (dc->condexec_cond & 0xe)
9460 | ((dc->condexec_mask >> 4) & 1);
9461 dc->condexec_mask = (dc->condexec_mask << 1) & 0x1f;
9462 if (dc->condexec_mask == 0) {
9463 dc->condexec_cond = 0;
9464 }
9465 }
9466 } else {
9467 disas_arm_insn(env, dc);
9468 }
e50e6a20
FB		 9469
9470 if (dc->condjmp && !dc->is_jmp) {
9471 gen_set_label(dc->condlabel);
9472 dc->condjmp = 0;
9473 }
3849902c
PM		 9474
9475 if (tcg_check_temp_count()) {
9476 fprintf(stderr, "TCG temporary leak before %08x\n", dc->pc);
9477 }
9478
aaf2d97d 9479 /* Translation stops when a conditional branch is encountered.
e50e6a20 9480 * Otherwise the subsequent code could get translated several times.
b5ff1b31 9481 * Also stop translation when a page boundary is reached. This
bf20dc07 9482 * ensures prefetch aborts occur at the right place. */
2e70f6ef 9483 num_insns ++;
1fddef4b
FB		 9484 } while (!dc->is_jmp && gen_opc_ptr < gen_opc_end &&
9485 !env->singlestep_enabled &&
1b530a6d 9486 !singlestep &&
2e70f6ef
PB		 9487 dc->pc < next_page_start &&
9488 num_insns < max_insns);
9489
9490 if (tb->cflags & CF_LAST_IO) {
9491 if (dc->condjmp) {
9492 /* FIXME: This can theoretically happen with self-modifying
9493 code. */
9494 cpu_abort(env, "IO on conditional branch instruction");
9495 }
9496 gen_io_end();
9497 }
9ee6e8bb 9498
b5ff1b31 9499 /* At this stage dc->condjmp will only be set when the skipped
9ee6e8bb
PB		 9500 instruction was a conditional branch or trap, and the PC has
9501 already been written. */
551bd27f 9502 if (unlikely(env->singlestep_enabled)) {
8aaca4c0 9503 /* Make sure the pc is updated, and raise a debug exception. */
e50e6a20 9504 if (dc->condjmp) {
9ee6e8bb
PB		 9505 gen_set_condexec(dc);
9506 if (dc->is_jmp == DISAS_SWI) {
d9ba4830 9507 gen_exception(EXCP_SWI);
9ee6e8bb 9508 } else {
d9ba4830 9509 gen_exception(EXCP_DEBUG);
9ee6e8bb 9510 }
e50e6a20
FB		 9511 gen_set_label(dc->condlabel);
9512 }
9513 if (dc->condjmp || !dc->is_jmp) {
5e3f878a 9514 gen_set_pc_im(dc->pc);
e50e6a20 9515 dc->condjmp = 0;
8aaca4c0 9516 }
9ee6e8bb
PB		 9517 gen_set_condexec(dc);
9518 if (dc->is_jmp == DISAS_SWI && !dc->condjmp) {
d9ba4830 9519 gen_exception(EXCP_SWI);
9ee6e8bb
PB		 9520 } else {
9521 /* FIXME: Single stepping a WFI insn will not halt
9522 the CPU. */
d9ba4830 9523 gen_exception(EXCP_DEBUG);
9ee6e8bb 9524 }
8aaca4c0 9525 } else {
9ee6e8bb
PB		 9526 /* While branches must always occur at the end of an IT block,
9527 there are a few other things that can cause us to terminate
9528 the TB in the middel of an IT block:
9529 - Exception generating instructions (bkpt, swi, undefined).
9530 - Page boundaries.
9531 - Hardware watchpoints.
9532 Hardware breakpoints have already been handled and skip this code.
9533 */
9534 gen_set_condexec(dc);
8aaca4c0 9535 switch(dc->is_jmp) {
8aaca4c0 9536 case DISAS_NEXT:
6e256c93 9537 gen_goto_tb(dc, 1, dc->pc);
8aaca4c0
FB		 9538 break;
9539 default:
9540 case DISAS_JUMP:
9541 case DISAS_UPDATE:
9542 /* indicate that the hash table must be used to find the next TB */
57fec1fe 9543 tcg_gen_exit_tb(0);
8aaca4c0
FB		 9544 break;
9545 case DISAS_TB_JUMP:
9546 /* nothing more to generate */
9547 break;
9ee6e8bb 9548 case DISAS_WFI:
d9ba4830 9549 gen_helper_wfi();
9ee6e8bb
PB		 9550 break;
9551 case DISAS_SWI:
d9ba4830 9552 gen_exception(EXCP_SWI);
9ee6e8bb 9553 break;
8aaca4c0 9554 }
e50e6a20
FB		 9555 if (dc->condjmp) {
9556 gen_set_label(dc->condlabel);
9ee6e8bb 9557 gen_set_condexec(dc);
6e256c93 9558 gen_goto_tb(dc, 1, dc->pc);
e50e6a20
FB		 9559 dc->condjmp = 0;
9560 }
2c0262af 9561 }
2e70f6ef 9562
9ee6e8bb 9563done_generating:
2e70f6ef 9564 gen_icount_end(tb, num_insns);
2c0262af
FB		 9565 *gen_opc_ptr = INDEX_op_end;
9566
9567#ifdef DEBUG_DISAS
8fec2b8c 9568 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
93fcfe39
AL		 9569 qemu_log("----------------\n");
9570 qemu_log("IN: %s\n", lookup_symbol(pc_start));
7204ab88 9571 log_target_disas(pc_start, dc->pc - pc_start, dc->thumb);
93fcfe39 9572 qemu_log("\n");
2c0262af
FB		 9573 }
9574#endif
b5ff1b31
FB		 9575 if (search_pc) {
9576 j = gen_opc_ptr - gen_opc_buf;
9577 lj++;
9578 while (lj <= j)
9579 gen_opc_instr_start[lj++] = 0;
b5ff1b31 9580 } else {
2c0262af 9581 tb->size = dc->pc - pc_start;
2e70f6ef 9582 tb->icount = num_insns;
b5ff1b31 9583 }
2c0262af
FB		 9584}
9585
2cfc5f17 9586void gen_intermediate_code(CPUState *env, TranslationBlock *tb)
2c0262af 9587{
2cfc5f17 9588 gen_intermediate_code_internal(env, tb, 0);
2c0262af
FB		 9589}
9590
2cfc5f17 9591void gen_intermediate_code_pc(CPUState *env, TranslationBlock *tb)
2c0262af 9592{
2cfc5f17 9593 gen_intermediate_code_internal(env, tb, 1);
2c0262af
FB		 9594}
9595
b5ff1b31
FB		 9596static const char *cpu_mode_names[16] = {
9597 "usr", "fiq", "irq", "svc", "???", "???", "???", "abt",
9598 "???", "???", "???", "und", "???", "???", "???", "sys"
9599};
9ee6e8bb 9600
9a78eead 9601void cpu_dump_state(CPUState *env, FILE *f, fprintf_function cpu_fprintf,
7fe48483 9602 int flags)
2c0262af
FB		 9603{
9604 int i;
06e80fc9 9605#if 0
bc380d17 9606 union {
b7bcbe95
FB		 9607 uint32_t i;
9608 float s;
9609 } s0, s1;
9610 CPU_DoubleU d;
a94a6abf
PB		 9611 /* ??? This assumes float64 and double have the same layout.
9612 Oh well, it's only debug dumps. */
9613 union {
9614 float64 f64;
9615 double d;
9616 } d0;
06e80fc9 9617#endif
b5ff1b31 9618 uint32_t psr;
2c0262af
FB		 9619
9620 for(i=0;i<16;i++) {
7fe48483 9621 cpu_fprintf(f, "R%02d=%08x", i, env->regs[i]);
2c0262af 9622 if ((i % 4) == 3)
7fe48483 9623 cpu_fprintf(f, "\n");
2c0262af 9624 else
7fe48483 9625 cpu_fprintf(f, " ");
2c0262af 9626 }
b5ff1b31 9627 psr = cpsr_read(env);
687fa640
TS		 9628 cpu_fprintf(f, "PSR=%08x %c%c%c%c %c %s%d\n",
9629 psr,
b5ff1b31
FB		 9630 psr & (1 << 31) ? 'N' : '-',
9631 psr & (1 << 30) ? 'Z' : '-',
9632 psr & (1 << 29) ? 'C' : '-',
9633 psr & (1 << 28) ? 'V' : '-',
5fafdf24 9634 psr & CPSR_T ? 'T' : 'A',
b5ff1b31 9635 cpu_mode_names[psr & 0xf], (psr & 0x10) ? 32 : 26);
b7bcbe95 9636
5e3f878a 9637#if 0
b7bcbe95 9638 for (i = 0; i < 16; i++) {
8e96005d
FB		 9639 d.d = env->vfp.regs[i];
9640 s0.i = d.l.lower;
9641 s1.i = d.l.upper;
a94a6abf
PB		 9642 d0.f64 = d.d;
9643 cpu_fprintf(f, "s%02d=%08x(%8g) s%02d=%08x(%8g) d%02d=%08x%08x(%8g)\n",
b7bcbe95 9644 i * 2, (int)s0.i, s0.s,
a94a6abf 9645 i * 2 + 1, (int)s1.i, s1.s,
b7bcbe95 9646 i, (int)(uint32_t)d.l.upper, (int)(uint32_t)d.l.lower,
a94a6abf 9647 d0.d);
b7bcbe95 9648 }
40f137e1 9649 cpu_fprintf(f, "FPSCR: %08x\n", (int)env->vfp.xregs[ARM_VFP_FPSCR]);
5e3f878a 9650#endif
2c0262af 9651}
a6b025d3 9652
d2856f1a
AJ		 9653void gen_pc_load(CPUState *env, TranslationBlock *tb,
9654 unsigned long searched_pc, int pc_pos, void *puc)
9655{
9656 env->regs[15] = gen_opc_pc[pc_pos];
e12ce78d 9657 env->condexec_bits = gen_opc_condexec_bits[pc_pos];
d2856f1a 9658}
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