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Allocate the -vmwarevga framebuffer in the right place in RAM.
[mirror_qemu.git] / target-arm / translate.c
CommitLineData
2c0262af
FB		 1/*
2 * ARM translation
5fafdf24 3 *
2c0262af 4 * Copyright (c) 2003 Fabrice Bellard
9ee6e8bb 5 * Copyright (c) 2005-2007 CodeSourcery
18c9b560 6 * Copyright (c) 2007 OpenedHand, Ltd.
2c0262af
FB		 7 *
8 * This library is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU Lesser General Public
10 * License as published by the Free Software Foundation; either
11 * version 2 of the License, or (at your option) any later version.
12 *
13 * This library is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * Lesser General Public License for more details.
17 *
18 * You should have received a copy of the GNU Lesser General Public
19 * License along with this library; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 */
22#include <stdarg.h>
23#include <stdlib.h>
24#include <stdio.h>
25#include <string.h>
26#include <inttypes.h>
27
28#include "cpu.h"
29#include "exec-all.h"
30#include "disas.h"
57fec1fe 31#include "tcg-op.h"
1497c961
PB		 32
33#define GEN_HELPER 1
b26eefb6 34#include "helpers.h"
2c0262af 35
9ee6e8bb
PB		 36#define ENABLE_ARCH_5J 0
37#define ENABLE_ARCH_6 arm_feature(env, ARM_FEATURE_V6)
38#define ENABLE_ARCH_6K arm_feature(env, ARM_FEATURE_V6K)
39#define ENABLE_ARCH_6T2 arm_feature(env, ARM_FEATURE_THUMB2)
40#define ENABLE_ARCH_7 arm_feature(env, ARM_FEATURE_V7)
b5ff1b31
FB		 41
42#define ARCH(x) if (!ENABLE_ARCH_##x) goto illegal_op;
43
2c0262af
FB		 44/* internal defines */
45typedef struct DisasContext {
0fa85d43 46 target_ulong pc;
2c0262af 47 int is_jmp;
e50e6a20
FB		 48 /* Nonzero if this instruction has been conditionally skipped. */
49 int condjmp;
50 /* The label that will be jumped to when the instruction is skipped. */
51 int condlabel;
9ee6e8bb
PB		 52 /* Thumb-2 condtional execution bits. */
53 int condexec_mask;
54 int condexec_cond;
2c0262af 55 struct TranslationBlock *tb;
8aaca4c0 56 int singlestep_enabled;
5899f386 57 int thumb;
6658ffb8 58 int is_mem;
b5ff1b31
FB		 59#if !defined(CONFIG_USER_ONLY)
60 int user;
61#endif
2c0262af
FB		 62} DisasContext;
63
b5ff1b31
FB		 64#if defined(CONFIG_USER_ONLY)
65#define IS_USER(s) 1
66#else
67#define IS_USER(s) (s->user)
68#endif
69
9ee6e8bb
PB		 70/* These instructions trap after executing, so defer them until after the
71 conditional executions state has been updated. */
72#define DISAS_WFI 4
73#define DISAS_SWI 5
2c0262af
FB		 74
75/* XXX: move that elsewhere */
2c0262af
FB		 76extern FILE *logfile;
77extern int loglevel;
78
b26eefb6 79static TCGv cpu_env;
ad69471c 80/* We reuse the same 64-bit temporaries for efficiency. */
e677137d 81static TCGv cpu_V0, cpu_V1, cpu_M0;
ad69471c 82
b26eefb6 83/* FIXME: These should be removed. */
8f8e3aa4 84static TCGv cpu_T[2];
4373f3ce 85static TCGv cpu_F0s, cpu_F1s, cpu_F0d, cpu_F1d;
b26eefb6
PB		 86
87/* initialize TCG globals. */
88void arm_translate_init(void)
89{
90 cpu_env = tcg_global_reg_new(TCG_TYPE_PTR, TCG_AREG0, "env");
91
92 cpu_T[0] = tcg_global_reg_new(TCG_TYPE_I32, TCG_AREG1, "T0");
93 cpu_T[1] = tcg_global_reg_new(TCG_TYPE_I32, TCG_AREG2, "T1");
b26eefb6
PB		 94}
95
96/* The code generator doesn't like lots of temporaries, so maintain our own
97 cache for reuse within a function. */
98#define MAX_TEMPS 8
99static int num_temps;
100static TCGv temps[MAX_TEMPS];
101
102/* Allocate a temporary variable. */
103static TCGv new_tmp(void)
104{
105 TCGv tmp;
106 if (num_temps == MAX_TEMPS)
107 abort();
108
109 if (GET_TCGV(temps[num_temps]))
110 return temps[num_temps++];
111
112 tmp = tcg_temp_new(TCG_TYPE_I32);
113 temps[num_temps++] = tmp;
114 return tmp;
115}
116
117/* Release a temporary variable. */
118static void dead_tmp(TCGv tmp)
119{
120 int i;
121 num_temps--;
122 i = num_temps;
123 if (GET_TCGV(temps[i]) == GET_TCGV(tmp))
124 return;
125
126 /* Shuffle this temp to the last slot. */
127 while (GET_TCGV(temps[i]) != GET_TCGV(tmp))
128 i--;
129 while (i < num_temps) {
130 temps[i] = temps[i + 1];
131 i++;
132 }
133 temps[i] = tmp;
134}
135
d9ba4830
PB		 136static inline TCGv load_cpu_offset(int offset)
137{
138 TCGv tmp = new_tmp();
139 tcg_gen_ld_i32(tmp, cpu_env, offset);
140 return tmp;
141}
142
143#define load_cpu_field(name) load_cpu_offset(offsetof(CPUState, name))
144
145static inline void store_cpu_offset(TCGv var, int offset)
146{
147 tcg_gen_st_i32(var, cpu_env, offset);
148 dead_tmp(var);
149}
150
151#define store_cpu_field(var, name) \
152 store_cpu_offset(var, offsetof(CPUState, name))
153
b26eefb6
PB		 154/* Set a variable to the value of a CPU register. */
155static void load_reg_var(DisasContext *s, TCGv var, int reg)
156{
157 if (reg == 15) {
158 uint32_t addr;
159 /* normaly, since we updated PC, we need only to add one insn */
160 if (s->thumb)
161 addr = (long)s->pc + 2;
162 else
163 addr = (long)s->pc + 4;
164 tcg_gen_movi_i32(var, addr);
165 } else {
166 tcg_gen_ld_i32(var, cpu_env, offsetof(CPUState, regs[reg]));
167 }
168}
169
170/* Create a new temporary and set it to the value of a CPU register. */
171static inline TCGv load_reg(DisasContext *s, int reg)
172{
173 TCGv tmp = new_tmp();
174 load_reg_var(s, tmp, reg);
175 return tmp;
176}
177
178/* Set a CPU register. The source must be a temporary and will be
179 marked as dead. */
180static void store_reg(DisasContext *s, int reg, TCGv var)
181{
182 if (reg == 15) {
183 tcg_gen_andi_i32(var, var, ~1);
184 s->is_jmp = DISAS_JUMP;
185 }
186 tcg_gen_st_i32(var, cpu_env, offsetof(CPUState, regs[reg]));
187 dead_tmp(var);
188}
189
190
191/* Basic operations. */
192#define gen_op_movl_T0_T1() tcg_gen_mov_i32(cpu_T[0], cpu_T[1])
b26eefb6 193#define gen_op_movl_T1_T0() tcg_gen_mov_i32(cpu_T[1], cpu_T[0])
b26eefb6
PB		 194#define gen_op_movl_T0_im(im) tcg_gen_movi_i32(cpu_T[0], im)
195#define gen_op_movl_T1_im(im) tcg_gen_movi_i32(cpu_T[1], im)
b26eefb6
PB		 196
197#define gen_op_addl_T1_im(im) tcg_gen_addi_i32(cpu_T[1], cpu_T[1], im)
198#define gen_op_addl_T0_T1() tcg_gen_add_i32(cpu_T[0], cpu_T[0], cpu_T[1])
199#define gen_op_subl_T0_T1() tcg_gen_sub_i32(cpu_T[0], cpu_T[0], cpu_T[1])
200#define gen_op_rsbl_T0_T1() tcg_gen_sub_i32(cpu_T[0], cpu_T[1], cpu_T[0])
201
8984bd2e
PB		 202#define gen_op_addl_T0_T1_cc() gen_helper_add_cc(cpu_T[0], cpu_T[0], cpu_T[1])
203#define gen_op_adcl_T0_T1_cc() gen_helper_adc_cc(cpu_T[0], cpu_T[0], cpu_T[1])
204#define gen_op_subl_T0_T1_cc() gen_helper_sub_cc(cpu_T[0], cpu_T[0], cpu_T[1])
205#define gen_op_sbcl_T0_T1_cc() gen_helper_sbc_cc(cpu_T[0], cpu_T[0], cpu_T[1])
206#define gen_op_rsbl_T0_T1_cc() gen_helper_sub_cc(cpu_T[0], cpu_T[1], cpu_T[0])
207#define gen_op_rscl_T0_T1_cc() gen_helper_sbc_cc(cpu_T[0], cpu_T[1], cpu_T[0])
208
b26eefb6
PB		 209#define gen_op_andl_T0_T1() tcg_gen_and_i32(cpu_T[0], cpu_T[0], cpu_T[1])
210#define gen_op_xorl_T0_T1() tcg_gen_xor_i32(cpu_T[0], cpu_T[0], cpu_T[1])
211#define gen_op_orl_T0_T1() tcg_gen_or_i32(cpu_T[0], cpu_T[0], cpu_T[1])
212#define gen_op_notl_T0() tcg_gen_not_i32(cpu_T[0], cpu_T[0])
213#define gen_op_notl_T1() tcg_gen_not_i32(cpu_T[1], cpu_T[1])
214#define gen_op_logic_T0_cc() gen_logic_CC(cpu_T[0]);
215#define gen_op_logic_T1_cc() gen_logic_CC(cpu_T[1]);
216
217#define gen_op_shll_T0_im(im) tcg_gen_shli_i32(cpu_T[0], cpu_T[0], im)
218#define gen_op_shll_T1_im(im) tcg_gen_shli_i32(cpu_T[1], cpu_T[1], im)
219#define gen_op_shrl_T1_im(im) tcg_gen_shri_i32(cpu_T[1], cpu_T[1], im)
220#define gen_op_sarl_T1_im(im) tcg_gen_sari_i32(cpu_T[1], cpu_T[1], im)
221#define gen_op_rorl_T1_im(im) tcg_gen_rori_i32(cpu_T[1], cpu_T[1], im)
222
223/* Value extensions. */
224#define gen_uxtb(var) tcg_gen_andi_i32(var, var, 0xff)
225#define gen_uxth(var) tcg_gen_andi_i32(var, var, 0xffff)
226#define gen_sxtb(var) tcg_gen_ext8s_i32(var, var)
227#define gen_sxth(var) tcg_gen_ext16s_i32(var, var)
228
1497c961
PB		 229#define gen_sxtb16(var) gen_helper_sxtb16(var, var)
230#define gen_uxtb16(var) gen_helper_uxtb16(var, var)
8f01245e
PB		 231
232#define gen_op_mul_T0_T1() tcg_gen_mul_i32(cpu_T[0], cpu_T[0], cpu_T[1])
b26eefb6 233
d9ba4830
PB		 234#define gen_set_cpsr(var, mask) gen_helper_cpsr_write(var, tcg_const_i32(mask))
235/* Set NZCV flags from the high 4 bits of var. */
236#define gen_set_nzcv(var) gen_set_cpsr(var, CPSR_NZCV)
237
238static void gen_exception(int excp)
239{
240 TCGv tmp = new_tmp();
241 tcg_gen_movi_i32(tmp, excp);
242 gen_helper_exception(tmp);
243 dead_tmp(tmp);
244}
245
3670669c
PB		 246static void gen_smul_dual(TCGv a, TCGv b)
247{
248 TCGv tmp1 = new_tmp();
249 TCGv tmp2 = new_tmp();
3670669c
PB		 250 tcg_gen_ext8s_i32(tmp1, a);
251 tcg_gen_ext8s_i32(tmp2, b);
252 tcg_gen_mul_i32(tmp1, tmp1, tmp2);
253 dead_tmp(tmp2);
254 tcg_gen_sari_i32(a, a, 16);
255 tcg_gen_sari_i32(b, b, 16);
256 tcg_gen_mul_i32(b, b, a);
257 tcg_gen_mov_i32(a, tmp1);
258 dead_tmp(tmp1);
259}
260
261/* Byteswap each halfword. */
262static void gen_rev16(TCGv var)
263{
264 TCGv tmp = new_tmp();
265 tcg_gen_shri_i32(tmp, var, 8);
266 tcg_gen_andi_i32(tmp, tmp, 0x00ff00ff);
267 tcg_gen_shli_i32(var, var, 8);
268 tcg_gen_andi_i32(var, var, 0xff00ff00);
269 tcg_gen_or_i32(var, var, tmp);
270 dead_tmp(tmp);
271}
272
273/* Byteswap low halfword and sign extend. */
274static void gen_revsh(TCGv var)
275{
276 TCGv tmp = new_tmp();
277 tcg_gen_shri_i32(tmp, var, 8);
278 tcg_gen_andi_i32(tmp, tmp, 0x00ff);
279 tcg_gen_shli_i32(var, var, 8);
280 tcg_gen_ext8s_i32(var, var);
281 tcg_gen_or_i32(var, var, tmp);
282 dead_tmp(tmp);
283}
284
285/* Unsigned bitfield extract. */
286static void gen_ubfx(TCGv var, int shift, uint32_t mask)
287{
288 if (shift)
289 tcg_gen_shri_i32(var, var, shift);
290 tcg_gen_andi_i32(var, var, mask);
291}
292
293/* Signed bitfield extract. */
294static void gen_sbfx(TCGv var, int shift, int width)
295{
296 uint32_t signbit;
297
298 if (shift)
299 tcg_gen_sari_i32(var, var, shift);
300 if (shift + width < 32) {
301 signbit = 1u << (width - 1);
302 tcg_gen_andi_i32(var, var, (1u << width) - 1);
303 tcg_gen_xori_i32(var, var, signbit);
304 tcg_gen_subi_i32(var, var, signbit);
305 }
306}
307
308/* Bitfield insertion. Insert val into base. Clobbers base and val. */
309static void gen_bfi(TCGv dest, TCGv base, TCGv val, int shift, uint32_t mask)
310{
3670669c 311 tcg_gen_andi_i32(val, val, mask);
8f8e3aa4
PB		 312 tcg_gen_shli_i32(val, val, shift);
313 tcg_gen_andi_i32(base, base, ~(mask << shift));
3670669c
PB		 314 tcg_gen_or_i32(dest, base, val);
315}
316
d9ba4830
PB		 317/* Round the top 32 bits of a 64-bit value. */
318static void gen_roundqd(TCGv a, TCGv b)
3670669c 319{
d9ba4830
PB		 320 tcg_gen_shri_i32(a, a, 31);
321 tcg_gen_add_i32(a, a, b);
3670669c
PB		 322}
323
8f01245e
PB		 324/* FIXME: Most targets have native widening multiplication.
325 It would be good to use that instead of a full wide multiply. */
5e3f878a
PB		 326/* 32x32->64 multiply. Marks inputs as dead. */
327static TCGv gen_mulu_i64_i32(TCGv a, TCGv b)
328{
329 TCGv tmp1 = tcg_temp_new(TCG_TYPE_I64);
330 TCGv tmp2 = tcg_temp_new(TCG_TYPE_I64);
331
332 tcg_gen_extu_i32_i64(tmp1, a);
333 dead_tmp(a);
334 tcg_gen_extu_i32_i64(tmp2, b);
335 dead_tmp(b);
336 tcg_gen_mul_i64(tmp1, tmp1, tmp2);
337 return tmp1;
338}
339
340static TCGv gen_muls_i64_i32(TCGv a, TCGv b)
341{
342 TCGv tmp1 = tcg_temp_new(TCG_TYPE_I64);
343 TCGv tmp2 = tcg_temp_new(TCG_TYPE_I64);
344
345 tcg_gen_ext_i32_i64(tmp1, a);
346 dead_tmp(a);
347 tcg_gen_ext_i32_i64(tmp2, b);
348 dead_tmp(b);
349 tcg_gen_mul_i64(tmp1, tmp1, tmp2);
350 return tmp1;
351}
352
8f01245e
PB		 353/* Unsigned 32x32->64 multiply. */
354static void gen_op_mull_T0_T1(void)
355{
356 TCGv tmp1 = tcg_temp_new(TCG_TYPE_I64);
357 TCGv tmp2 = tcg_temp_new(TCG_TYPE_I64);
358
359 tcg_gen_extu_i32_i64(tmp1, cpu_T[0]);
360 tcg_gen_extu_i32_i64(tmp2, cpu_T[1]);
361 tcg_gen_mul_i64(tmp1, tmp1, tmp2);
362 tcg_gen_trunc_i64_i32(cpu_T[0], tmp1);
363 tcg_gen_shri_i64(tmp1, tmp1, 32);
364 tcg_gen_trunc_i64_i32(cpu_T[1], tmp1);
365}
366
367/* Signed 32x32->64 multiply. */
d9ba4830 368static void gen_imull(TCGv a, TCGv b)
8f01245e
PB		 369{
370 TCGv tmp1 = tcg_temp_new(TCG_TYPE_I64);
371 TCGv tmp2 = tcg_temp_new(TCG_TYPE_I64);
372
d9ba4830
PB		 373 tcg_gen_ext_i32_i64(tmp1, a);
374 tcg_gen_ext_i32_i64(tmp2, b);
8f01245e 375 tcg_gen_mul_i64(tmp1, tmp1, tmp2);
d9ba4830 376 tcg_gen_trunc_i64_i32(a, tmp1);
8f01245e 377 tcg_gen_shri_i64(tmp1, tmp1, 32);
d9ba4830
PB		 378 tcg_gen_trunc_i64_i32(b, tmp1);
379}
380#define gen_op_imull_T0_T1() gen_imull(cpu_T[0], cpu_T[1])
381
8f01245e
PB		 382/* Swap low and high halfwords. */
383static void gen_swap_half(TCGv var)
384{
385 TCGv tmp = new_tmp();
386 tcg_gen_shri_i32(tmp, var, 16);
387 tcg_gen_shli_i32(var, var, 16);
388 tcg_gen_or_i32(var, var, tmp);
3670669c 389 dead_tmp(tmp);
8f01245e
PB		 390}
391
b26eefb6
PB		 392/* Dual 16-bit add. Result placed in t0 and t1 is marked as dead.
393 tmp = (t0 ^ t1) & 0x8000;
394 t0 &= ~0x8000;
395 t1 &= ~0x8000;
396 t0 = (t0 + t1) ^ tmp;
397 */
398
399static void gen_add16(TCGv t0, TCGv t1)
400{
401 TCGv tmp = new_tmp();
402 tcg_gen_xor_i32(tmp, t0, t1);
403 tcg_gen_andi_i32(tmp, tmp, 0x8000);
404 tcg_gen_andi_i32(t0, t0, ~0x8000);
405 tcg_gen_andi_i32(t1, t1, ~0x8000);
406 tcg_gen_add_i32(t0, t0, t1);
407 tcg_gen_xor_i32(t0, t0, tmp);
408 dead_tmp(tmp);
409 dead_tmp(t1);
410}
411
9a119ff6
PB		 412#define gen_set_CF(var) tcg_gen_st_i32(var, cpu_env, offsetof(CPUState, CF))
413
b26eefb6
PB		 414/* Set CF to the top bit of var. */
415static void gen_set_CF_bit31(TCGv var)
416{
417 TCGv tmp = new_tmp();
418 tcg_gen_shri_i32(tmp, var, 31);
9a119ff6 419 gen_set_CF(var);
b26eefb6
PB		 420 dead_tmp(tmp);
421}
422
423/* Set N and Z flags from var. */
424static inline void gen_logic_CC(TCGv var)
425{
6fbe23d5
PB		 426 tcg_gen_st_i32(var, cpu_env, offsetof(CPUState, NF));
427 tcg_gen_st_i32(var, cpu_env, offsetof(CPUState, ZF));
b26eefb6
PB		 428}
429
430/* T0 += T1 + CF. */
431static void gen_adc_T0_T1(void)
432{
d9ba4830 433 TCGv tmp;
b26eefb6 434 gen_op_addl_T0_T1();
d9ba4830 435 tmp = load_cpu_field(CF);
b26eefb6
PB		 436 tcg_gen_add_i32(cpu_T[0], cpu_T[0], tmp);
437 dead_tmp(tmp);
438}
439
3670669c
PB		 440/* dest = T0 - T1 + CF - 1. */
441static void gen_sub_carry(TCGv dest, TCGv t0, TCGv t1)
442{
d9ba4830 443 TCGv tmp;
3670669c 444 tcg_gen_sub_i32(dest, t0, t1);
d9ba4830 445 tmp = load_cpu_field(CF);
3670669c
PB		 446 tcg_gen_add_i32(dest, dest, tmp);
447 tcg_gen_subi_i32(dest, dest, 1);
448 dead_tmp(tmp);
449}
450
451#define gen_sbc_T0_T1() gen_sub_carry(cpu_T[0], cpu_T[0], cpu_T[1])
452#define gen_rsc_T0_T1() gen_sub_carry(cpu_T[0], cpu_T[1], cpu_T[0])
453
b26eefb6
PB		 454/* FIXME: Implement this natively. */
455static inline void tcg_gen_not_i32(TCGv t0, TCGv t1)
456{
457 tcg_gen_xori_i32(t0, t1, ~0);
458}
459
e677137d
PB		 460/* FIXME: Implement this natively. */
461static inline void tcg_gen_neg_i64(TCGv dest, TCGv src)
462{
463 tcg_gen_sub_i64(dest, tcg_const_i64(0), src);
464}
465
b26eefb6
PB		 466/* T0 &= ~T1. Clobbers T1. */
467/* FIXME: Implement bic natively. */
8f8e3aa4
PB		 468static inline void tcg_gen_bic_i32(TCGv dest, TCGv t0, TCGv t1)
469{
470 TCGv tmp = new_tmp();
471 tcg_gen_not_i32(tmp, t1);
472 tcg_gen_and_i32(dest, t0, tmp);
473 dead_tmp(tmp);
474}
b26eefb6
PB		 475static inline void gen_op_bicl_T0_T1(void)
476{
477 gen_op_notl_T1();
478 gen_op_andl_T0_T1();
479}
480
ad69471c
PB		 481/* FIXME: Implement this natively. */
482#define tcg_gen_abs_i32(t0, t1) gen_helper_abs(t0, t1)
483
b26eefb6
PB		 484/* FIXME: Implement this natively. */
485static void tcg_gen_rori_i32(TCGv t0, TCGv t1, int i)
486{
487 TCGv tmp;
488
489 if (i == 0)
490 return;
491
492 tmp = new_tmp();
493 tcg_gen_shri_i32(tmp, t1, i);
494 tcg_gen_shli_i32(t1, t1, 32 - i);
495 tcg_gen_or_i32(t0, t1, tmp);
496 dead_tmp(tmp);
497}
498
9a119ff6 499static void shifter_out_im(TCGv var, int shift)
b26eefb6 500{
9a119ff6
PB		 501 TCGv tmp = new_tmp();
502 if (shift == 0) {
503 tcg_gen_andi_i32(tmp, var, 1);
b26eefb6 504 } else {
9a119ff6
PB		 505 tcg_gen_shri_i32(tmp, var, shift);
506 if (shift != 31);
507 tcg_gen_andi_i32(tmp, tmp, 1);
508 }
509 gen_set_CF(tmp);
510 dead_tmp(tmp);
511}
b26eefb6 512
9a119ff6
PB		 513/* Shift by immediate. Includes special handling for shift == 0. */
514static inline void gen_arm_shift_im(TCGv var, int shiftop, int shift, int flags)
515{
516 switch (shiftop) {
517 case 0: /* LSL */
518 if (shift != 0) {
519 if (flags)
520 shifter_out_im(var, 32 - shift);
521 tcg_gen_shli_i32(var, var, shift);
522 }
523 break;
524 case 1: /* LSR */
525 if (shift == 0) {
526 if (flags) {
527 tcg_gen_shri_i32(var, var, 31);
528 gen_set_CF(var);
529 }
530 tcg_gen_movi_i32(var, 0);
531 } else {
532 if (flags)
533 shifter_out_im(var, shift - 1);
534 tcg_gen_shri_i32(var, var, shift);
535 }
536 break;
537 case 2: /* ASR */
538 if (shift == 0)
539 shift = 32;
540 if (flags)
541 shifter_out_im(var, shift - 1);
542 if (shift == 32)
543 shift = 31;
544 tcg_gen_sari_i32(var, var, shift);
545 break;
546 case 3: /* ROR/RRX */
547 if (shift != 0) {
548 if (flags)
549 shifter_out_im(var, shift - 1);
550 tcg_gen_rori_i32(var, var, shift); break;
551 } else {
d9ba4830 552 TCGv tmp = load_cpu_field(CF);
9a119ff6
PB		 553 if (flags)
554 shifter_out_im(var, 0);
555 tcg_gen_shri_i32(var, var, 1);
b26eefb6
PB		 556 tcg_gen_shli_i32(tmp, tmp, 31);
557 tcg_gen_or_i32(var, var, tmp);
558 dead_tmp(tmp);
b26eefb6
PB		 559 }
560 }
561};
562
8984bd2e
PB		 563static inline void gen_arm_shift_reg(TCGv var, int shiftop,
564 TCGv shift, int flags)
565{
566 if (flags) {
567 switch (shiftop) {
568 case 0: gen_helper_shl_cc(var, var, shift); break;
569 case 1: gen_helper_shr_cc(var, var, shift); break;
570 case 2: gen_helper_sar_cc(var, var, shift); break;
571 case 3: gen_helper_ror_cc(var, var, shift); break;
572 }
573 } else {
574 switch (shiftop) {
575 case 0: gen_helper_shl(var, var, shift); break;
576 case 1: gen_helper_shr(var, var, shift); break;
577 case 2: gen_helper_sar(var, var, shift); break;
578 case 3: gen_helper_ror(var, var, shift); break;
579 }
580 }
581 dead_tmp(shift);
582}
583
6ddbc6e4
PB		 584#define PAS_OP(pfx) \
585 switch (op2) { \
586 case 0: gen_pas_helper(glue(pfx,add16)); break; \
587 case 1: gen_pas_helper(glue(pfx,addsubx)); break; \
588 case 2: gen_pas_helper(glue(pfx,subaddx)); break; \
589 case 3: gen_pas_helper(glue(pfx,sub16)); break; \
590 case 4: gen_pas_helper(glue(pfx,add8)); break; \
591 case 7: gen_pas_helper(glue(pfx,sub8)); break; \
592 }
d9ba4830 593static void gen_arm_parallel_addsub(int op1, int op2, TCGv a, TCGv b)
6ddbc6e4
PB		 594{
595 TCGv tmp;
596
597 switch (op1) {
598#define gen_pas_helper(name) glue(gen_helper_,name)(a, a, b, tmp)
599 case 1:
600 tmp = tcg_temp_new(TCG_TYPE_PTR);
601 tcg_gen_addi_ptr(tmp, cpu_env, offsetof(CPUState, GE));
602 PAS_OP(s)
603 break;
604 case 5:
605 tmp = tcg_temp_new(TCG_TYPE_PTR);
606 tcg_gen_addi_ptr(tmp, cpu_env, offsetof(CPUState, GE));
607 PAS_OP(u)
608 break;
609#undef gen_pas_helper
610#define gen_pas_helper(name) glue(gen_helper_,name)(a, a, b)
611 case 2:
612 PAS_OP(q);
613 break;
614 case 3:
615 PAS_OP(sh);
616 break;
617 case 6:
618 PAS_OP(uq);
619 break;
620 case 7:
621 PAS_OP(uh);
622 break;
623#undef gen_pas_helper
624 }
625}
9ee6e8bb
PB		 626#undef PAS_OP
627
6ddbc6e4
PB		 628/* For unknown reasons Arm and Thumb-2 use arbitrarily different encodings. */
629#define PAS_OP(pfx) \
630 switch (op2) { \
631 case 0: gen_pas_helper(glue(pfx,add8)); break; \
632 case 1: gen_pas_helper(glue(pfx,add16)); break; \
633 case 2: gen_pas_helper(glue(pfx,addsubx)); break; \
634 case 4: gen_pas_helper(glue(pfx,sub8)); break; \
635 case 5: gen_pas_helper(glue(pfx,sub16)); break; \
636 case 6: gen_pas_helper(glue(pfx,subaddx)); break; \
637 }
d9ba4830 638static void gen_thumb2_parallel_addsub(int op1, int op2, TCGv a, TCGv b)
6ddbc6e4
PB		 639{
640 TCGv tmp;
641
642 switch (op1) {
643#define gen_pas_helper(name) glue(gen_helper_,name)(a, a, b, tmp)
644 case 0:
645 tmp = tcg_temp_new(TCG_TYPE_PTR);
646 tcg_gen_addi_ptr(tmp, cpu_env, offsetof(CPUState, GE));
647 PAS_OP(s)
648 break;
649 case 4:
650 tmp = tcg_temp_new(TCG_TYPE_PTR);
651 tcg_gen_addi_ptr(tmp, cpu_env, offsetof(CPUState, GE));
652 PAS_OP(u)
653 break;
654#undef gen_pas_helper
655#define gen_pas_helper(name) glue(gen_helper_,name)(a, a, b)
656 case 1:
657 PAS_OP(q);
658 break;
659 case 2:
660 PAS_OP(sh);
661 break;
662 case 5:
663 PAS_OP(uq);
664 break;
665 case 6:
666 PAS_OP(uh);
667 break;
668#undef gen_pas_helper
669 }
670}
9ee6e8bb
PB		 671#undef PAS_OP
672
d9ba4830
PB		 673static void gen_test_cc(int cc, int label)
674{
675 TCGv tmp;
676 TCGv tmp2;
677 TCGv zero;
678 int inv;
679
680 zero = tcg_const_i32(0);
681 switch (cc) {
682 case 0: /* eq: Z */
6fbe23d5 683 tmp = load_cpu_field(ZF);
d9ba4830
PB		 684 tcg_gen_brcond_i32(TCG_COND_EQ, tmp, zero, label);
685 break;
686 case 1: /* ne: !Z */
6fbe23d5 687 tmp = load_cpu_field(ZF);
d9ba4830
PB		 688 tcg_gen_brcond_i32(TCG_COND_NE, tmp, zero, label);
689 break;
690 case 2: /* cs: C */
691 tmp = load_cpu_field(CF);
692 tcg_gen_brcond_i32(TCG_COND_NE, tmp, zero, label);
693 break;
694 case 3: /* cc: !C */
695 tmp = load_cpu_field(CF);
696 tcg_gen_brcond_i32(TCG_COND_EQ, tmp, zero, label);
697 break;
698 case 4: /* mi: N */
6fbe23d5 699 tmp = load_cpu_field(NF);
d9ba4830
PB		 700 tcg_gen_brcond_i32(TCG_COND_LT, tmp, zero, label);
701 break;
702 case 5: /* pl: !N */
6fbe23d5 703 tmp = load_cpu_field(NF);
d9ba4830
PB		 704 tcg_gen_brcond_i32(TCG_COND_GE, tmp, zero, label);
705 break;
706 case 6: /* vs: V */
707 tmp = load_cpu_field(VF);
708 tcg_gen_brcond_i32(TCG_COND_LT, tmp, zero, label);
709 break;
710 case 7: /* vc: !V */
711 tmp = load_cpu_field(VF);
712 tcg_gen_brcond_i32(TCG_COND_GE, tmp, zero, label);
713 break;
714 case 8: /* hi: C && !Z */
715 inv = gen_new_label();
716 tmp = load_cpu_field(CF);
717 tcg_gen_brcond_i32(TCG_COND_EQ, tmp, zero, inv);
718 dead_tmp(tmp);
6fbe23d5 719 tmp = load_cpu_field(ZF);
d9ba4830
PB		 720 tcg_gen_brcond_i32(TCG_COND_NE, tmp, zero, label);
721 gen_set_label(inv);
722 break;
723 case 9: /* ls: !C || Z */
724 tmp = load_cpu_field(CF);
725 tcg_gen_brcond_i32(TCG_COND_EQ, tmp, zero, label);
726 dead_tmp(tmp);
6fbe23d5 727 tmp = load_cpu_field(ZF);
d9ba4830
PB		 728 tcg_gen_brcond_i32(TCG_COND_EQ, tmp, zero, label);
729 break;
730 case 10: /* ge: N == V -> N ^ V == 0 */
731 tmp = load_cpu_field(VF);
6fbe23d5 732 tmp2 = load_cpu_field(NF);
d9ba4830
PB		 733 tcg_gen_xor_i32(tmp, tmp, tmp2);
734 dead_tmp(tmp2);
735 tcg_gen_brcond_i32(TCG_COND_GE, tmp, zero, label);
736 break;
737 case 11: /* lt: N != V -> N ^ V != 0 */
738 tmp = load_cpu_field(VF);
6fbe23d5 739 tmp2 = load_cpu_field(NF);
d9ba4830
PB		 740 tcg_gen_xor_i32(tmp, tmp, tmp2);
741 dead_tmp(tmp2);
742 tcg_gen_brcond_i32(TCG_COND_LT, tmp, zero, label);
743 break;
744 case 12: /* gt: !Z && N == V */
745 inv = gen_new_label();
6fbe23d5 746 tmp = load_cpu_field(ZF);
d9ba4830
PB		 747 tcg_gen_brcond_i32(TCG_COND_EQ, tmp, zero, inv);
748 dead_tmp(tmp);
749 tmp = load_cpu_field(VF);
6fbe23d5 750 tmp2 = load_cpu_field(NF);
d9ba4830
PB		 751 tcg_gen_xor_i32(tmp, tmp, tmp2);
752 dead_tmp(tmp2);
753 tcg_gen_brcond_i32(TCG_COND_GE, tmp, zero, label);
754 gen_set_label(inv);
755 break;
756 case 13: /* le: Z || N != V */
6fbe23d5 757 tmp = load_cpu_field(ZF);
d9ba4830
PB		 758 tcg_gen_brcond_i32(TCG_COND_EQ, tmp, zero, label);
759 dead_tmp(tmp);
760 tmp = load_cpu_field(VF);
6fbe23d5 761 tmp2 = load_cpu_field(NF);
d9ba4830
PB		 762 tcg_gen_xor_i32(tmp, tmp, tmp2);
763 dead_tmp(tmp2);
764 tcg_gen_brcond_i32(TCG_COND_LT, tmp, zero, label);
765 break;
766 default:
767 fprintf(stderr, "Bad condition code 0x%x\n", cc);
768 abort();
769 }
770 dead_tmp(tmp);
771}
2c0262af
FB		 772
773const uint8_t table_logic_cc[16] = {
774 1, /* and */
775 1, /* xor */
776 0, /* sub */
777 0, /* rsb */
778 0, /* add */
779 0, /* adc */
780 0, /* sbc */
781 0, /* rsc */
782 1, /* andl */
783 1, /* xorl */
784 0, /* cmp */
785 0, /* cmn */
786 1, /* orr */
787 1, /* mov */
788 1, /* bic */
789 1, /* mvn */
790};
3b46e624 791
d9ba4830
PB		 792/* Set PC and Thumb state from an immediate address. */
793static inline void gen_bx_im(DisasContext *s, uint32_t addr)
99c475ab 794{
b26eefb6 795 TCGv tmp;
99c475ab 796
b26eefb6
PB		 797 s->is_jmp = DISAS_UPDATE;
798 tmp = new_tmp();
d9ba4830
PB		 799 if (s->thumb != (addr & 1)) {
800 tcg_gen_movi_i32(tmp, addr & 1);
801 tcg_gen_st_i32(tmp, cpu_env, offsetof(CPUState, thumb));
802 }
803 tcg_gen_movi_i32(tmp, addr & ~1);
804 tcg_gen_st_i32(tmp, cpu_env, offsetof(CPUState, regs[15]));
b26eefb6 805 dead_tmp(tmp);
d9ba4830
PB		 806}
807
808/* Set PC and Thumb state from var. var is marked as dead. */
809static inline void gen_bx(DisasContext *s, TCGv var)
810{
811 TCGv tmp;
812
813 s->is_jmp = DISAS_UPDATE;
814 tmp = new_tmp();
815 tcg_gen_andi_i32(tmp, var, 1);
816 store_cpu_field(tmp, thumb);
817 tcg_gen_andi_i32(var, var, ~1);
818 store_cpu_field(var, regs[15]);
819}
820
821/* TODO: This should be removed. Use gen_bx instead. */
822static inline void gen_bx_T0(DisasContext *s)
823{
824 TCGv tmp = new_tmp();
825 tcg_gen_mov_i32(tmp, cpu_T[0]);
826 gen_bx(s, tmp);
b26eefb6 827}
b5ff1b31
FB		 828
829#if defined(CONFIG_USER_ONLY)
830#define gen_ldst(name, s) gen_op_##name##_raw()
831#else
832#define gen_ldst(name, s) do { \
6658ffb8 833 s->is_mem = 1; \
b5ff1b31
FB		 834 if (IS_USER(s)) \
835 gen_op_##name##_user(); \
836 else \
837 gen_op_##name##_kernel(); \
838 } while (0)
839#endif
b0109805
PB		 840static inline TCGv gen_ld8s(TCGv addr, int index)
841{
842 TCGv tmp = new_tmp();
843 tcg_gen_qemu_ld8s(tmp, addr, index);
844 return tmp;
845}
846static inline TCGv gen_ld8u(TCGv addr, int index)
847{
848 TCGv tmp = new_tmp();
849 tcg_gen_qemu_ld8u(tmp, addr, index);
850 return tmp;
851}
852static inline TCGv gen_ld16s(TCGv addr, int index)
853{
854 TCGv tmp = new_tmp();
855 tcg_gen_qemu_ld16s(tmp, addr, index);
856 return tmp;
857}
858static inline TCGv gen_ld16u(TCGv addr, int index)
859{
860 TCGv tmp = new_tmp();
861 tcg_gen_qemu_ld16u(tmp, addr, index);
862 return tmp;
863}
864static inline TCGv gen_ld32(TCGv addr, int index)
865{
866 TCGv tmp = new_tmp();
867 tcg_gen_qemu_ld32u(tmp, addr, index);
868 return tmp;
869}
870static inline void gen_st8(TCGv val, TCGv addr, int index)
871{
872 tcg_gen_qemu_st8(val, addr, index);
873 dead_tmp(val);
874}
875static inline void gen_st16(TCGv val, TCGv addr, int index)
876{
877 tcg_gen_qemu_st16(val, addr, index);
878 dead_tmp(val);
879}
880static inline void gen_st32(TCGv val, TCGv addr, int index)
881{
882 tcg_gen_qemu_st32(val, addr, index);
883 dead_tmp(val);
884}
b5ff1b31 885
2c0262af
FB		 886static inline void gen_movl_T0_reg(DisasContext *s, int reg)
887{
b26eefb6 888 load_reg_var(s, cpu_T[0], reg);
2c0262af
FB		 889}
890
891static inline void gen_movl_T1_reg(DisasContext *s, int reg)
892{
b26eefb6 893 load_reg_var(s, cpu_T[1], reg);
2c0262af
FB		 894}
895
896static inline void gen_movl_T2_reg(DisasContext *s, int reg)
897{
b26eefb6
PB		 898 load_reg_var(s, cpu_T[2], reg);
899}
900
5e3f878a
PB		 901static inline void gen_set_pc_im(uint32_t val)
902{
903 TCGv tmp = new_tmp();
904 tcg_gen_movi_i32(tmp, val);
905 store_cpu_field(tmp, regs[15]);
906}
907
b26eefb6
PB		 908static inline void gen_set_pc_T0(void)
909{
910 tcg_gen_st_i32(cpu_T[0], cpu_env, offsetof(CPUState, regs[15]));
2c0262af
FB		 911}
912
913static inline void gen_movl_reg_TN(DisasContext *s, int reg, int t)
914{
b26eefb6
PB		 915 TCGv tmp;
916 if (reg == 15) {
917 tmp = new_tmp();
918 tcg_gen_andi_i32(tmp, cpu_T[t], ~1);
919 } else {
920 tmp = cpu_T[t];
921 }
922 tcg_gen_st_i32(tmp, cpu_env, offsetof(CPUState, regs[reg]));
2c0262af 923 if (reg == 15) {
b26eefb6 924 dead_tmp(tmp);
2c0262af
FB		 925 s->is_jmp = DISAS_JUMP;
926 }
927}
928
929static inline void gen_movl_reg_T0(DisasContext *s, int reg)
930{
931 gen_movl_reg_TN(s, reg, 0);
932}
933
934static inline void gen_movl_reg_T1(DisasContext *s, int reg)
935{
936 gen_movl_reg_TN(s, reg, 1);
937}
938
b5ff1b31
FB		 939/* Force a TB lookup after an instruction that changes the CPU state. */
940static inline void gen_lookup_tb(DisasContext *s)
941{
942 gen_op_movl_T0_im(s->pc);
943 gen_movl_reg_T0(s, 15);
944 s->is_jmp = DISAS_UPDATE;
945}
946
b0109805
PB		 947static inline void gen_add_data_offset(DisasContext *s, unsigned int insn,
948 TCGv var)
2c0262af 949{
1e8d4eec 950 int val, rm, shift, shiftop;
b26eefb6 951 TCGv offset;
2c0262af
FB		 952
953 if (!(insn & (1 << 25))) {
954 /* immediate */
955 val = insn & 0xfff;
956 if (!(insn & (1 << 23)))
957 val = -val;
537730b9 958 if (val != 0)
b0109805 959 tcg_gen_addi_i32(var, var, val);
2c0262af
FB		 960 } else {
961 /* shift/register */
962 rm = (insn) & 0xf;
963 shift = (insn >> 7) & 0x1f;
1e8d4eec 964 shiftop = (insn >> 5) & 3;
b26eefb6 965 offset = load_reg(s, rm);
9a119ff6 966 gen_arm_shift_im(offset, shiftop, shift, 0);
2c0262af 967 if (!(insn & (1 << 23)))
b0109805 968 tcg_gen_sub_i32(var, var, offset);
2c0262af 969 else
b0109805 970 tcg_gen_add_i32(var, var, offset);
b26eefb6 971 dead_tmp(offset);
2c0262af
FB		 972 }
973}
974
191f9a93 975static inline void gen_add_datah_offset(DisasContext *s, unsigned int insn,
b0109805 976 int extra, TCGv var)
2c0262af
FB		 977{
978 int val, rm;
b26eefb6 979 TCGv offset;
3b46e624 980
2c0262af
FB		 981 if (insn & (1 << 22)) {
982 /* immediate */
983 val = (insn & 0xf) | ((insn >> 4) & 0xf0);
984 if (!(insn & (1 << 23)))
985 val = -val;
18acad92 986 val += extra;
537730b9 987 if (val != 0)
b0109805 988 tcg_gen_addi_i32(var, var, val);
2c0262af
FB		 989 } else {
990 /* register */
191f9a93 991 if (extra)
b0109805 992 tcg_gen_addi_i32(var, var, extra);
2c0262af 993 rm = (insn) & 0xf;
b26eefb6 994 offset = load_reg(s, rm);
2c0262af 995 if (!(insn & (1 << 23)))
b0109805 996 tcg_gen_sub_i32(var, var, offset);
2c0262af 997 else
b0109805 998 tcg_gen_add_i32(var, var, offset);
b26eefb6 999 dead_tmp(offset);
2c0262af
FB		 1000 }
1001}
1002
4373f3ce
PB		 1003#define VFP_OP2(name) \
1004static inline void gen_vfp_##name(int dp) \
1005{ \
1006 if (dp) \
1007 gen_helper_vfp_##name##d(cpu_F0d, cpu_F0d, cpu_F1d, cpu_env); \
1008 else \
1009 gen_helper_vfp_##name##s(cpu_F0s, cpu_F0s, cpu_F1s, cpu_env); \
b7bcbe95
FB		 1010}
1011
4373f3ce 1012#define VFP_OP1i(name) \
9ee6e8bb
PB		 1013static inline void gen_vfp_##name(int dp, int arg) \
1014{ \
1015 if (dp) \
1016 gen_op_vfp_##name##d(arg); \
1017 else \
1018 gen_op_vfp_##name##s(arg); \
1019}
1020
4373f3ce
PB		 1021VFP_OP2(add)
1022VFP_OP2(sub)
1023VFP_OP2(mul)
1024VFP_OP2(div)
1025
1026#undef VFP_OP2
1027
1028static inline void gen_vfp_abs(int dp)
1029{
1030 if (dp)
1031 gen_helper_vfp_absd(cpu_F0d, cpu_F0d);
1032 else
1033 gen_helper_vfp_abss(cpu_F0s, cpu_F0s);
1034}
1035
1036static inline void gen_vfp_neg(int dp)
1037{
1038 if (dp)
1039 gen_helper_vfp_negd(cpu_F0d, cpu_F0d);
1040 else
1041 gen_helper_vfp_negs(cpu_F0s, cpu_F0s);
1042}
1043
1044static inline void gen_vfp_sqrt(int dp)
1045{
1046 if (dp)
1047 gen_helper_vfp_sqrtd(cpu_F0d, cpu_F0d, cpu_env);
1048 else
1049 gen_helper_vfp_sqrts(cpu_F0s, cpu_F0s, cpu_env);
1050}
1051
1052static inline void gen_vfp_cmp(int dp)
1053{
1054 if (dp)
1055 gen_helper_vfp_cmpd(cpu_F0d, cpu_F1d, cpu_env);
1056 else
1057 gen_helper_vfp_cmps(cpu_F0s, cpu_F1s, cpu_env);
1058}
1059
1060static inline void gen_vfp_cmpe(int dp)
1061{
1062 if (dp)
1063 gen_helper_vfp_cmped(cpu_F0d, cpu_F1d, cpu_env);
1064 else
1065 gen_helper_vfp_cmpes(cpu_F0s, cpu_F1s, cpu_env);
1066}
1067
1068static inline void gen_vfp_F1_ld0(int dp)
1069{
1070 if (dp)
1071 tcg_gen_movi_i64(cpu_F0d, 0);
1072 else
1073 tcg_gen_movi_i32(cpu_F0s, 0);
1074}
1075
1076static inline void gen_vfp_uito(int dp)
1077{
1078 if (dp)
1079 gen_helper_vfp_uitod(cpu_F0d, cpu_F0s, cpu_env);
1080 else
1081 gen_helper_vfp_uitos(cpu_F0s, cpu_F0s, cpu_env);
1082}
1083
1084static inline void gen_vfp_sito(int dp)
1085{
1086 if (dp)
1087 gen_helper_vfp_uitod(cpu_F0d, cpu_F0s, cpu_env);
1088 else
1089 gen_helper_vfp_uitos(cpu_F0s, cpu_F0s, cpu_env);
1090}
1091
1092static inline void gen_vfp_toui(int dp)
1093{
1094 if (dp)
1095 gen_helper_vfp_touid(cpu_F0s, cpu_F0d, cpu_env);
1096 else
1097 gen_helper_vfp_touis(cpu_F0s, cpu_F0s, cpu_env);
1098}
1099
1100static inline void gen_vfp_touiz(int dp)
1101{
1102 if (dp)
1103 gen_helper_vfp_touizd(cpu_F0s, cpu_F0d, cpu_env);
1104 else
1105 gen_helper_vfp_touizs(cpu_F0s, cpu_F0s, cpu_env);
1106}
1107
1108static inline void gen_vfp_tosi(int dp)
1109{
1110 if (dp)
1111 gen_helper_vfp_tosid(cpu_F0s, cpu_F0d, cpu_env);
1112 else
1113 gen_helper_vfp_tosis(cpu_F0s, cpu_F0s, cpu_env);
1114}
1115
1116static inline void gen_vfp_tosiz(int dp)
9ee6e8bb
PB		 1117{
1118 if (dp)
4373f3ce 1119 gen_helper_vfp_tosizd(cpu_F0s, cpu_F0d, cpu_env);
9ee6e8bb 1120 else
4373f3ce
PB		 1121 gen_helper_vfp_tosizs(cpu_F0s, cpu_F0s, cpu_env);
1122}
1123
1124#define VFP_GEN_FIX(name) \
1125static inline void gen_vfp_##name(int dp, int shift) \
1126{ \
1127 if (dp) \
1128 gen_helper_vfp_##name##d(cpu_F0d, cpu_F0d, tcg_const_i32(shift), cpu_env);\
1129 else \
1130 gen_helper_vfp_##name##s(cpu_F0s, cpu_F0s, tcg_const_i32(shift), cpu_env);\
9ee6e8bb 1131}
4373f3ce
PB		 1132VFP_GEN_FIX(tosh)
1133VFP_GEN_FIX(tosl)
1134VFP_GEN_FIX(touh)
1135VFP_GEN_FIX(toul)
1136VFP_GEN_FIX(shto)
1137VFP_GEN_FIX(slto)
1138VFP_GEN_FIX(uhto)
1139VFP_GEN_FIX(ulto)
1140#undef VFP_GEN_FIX
9ee6e8bb 1141
b5ff1b31
FB		 1142static inline void gen_vfp_ld(DisasContext *s, int dp)
1143{
1144 if (dp)
4373f3ce 1145 tcg_gen_qemu_ld64(cpu_F0d, cpu_T[1], IS_USER(s));
b5ff1b31 1146 else
4373f3ce 1147 tcg_gen_qemu_ld32u(cpu_F0s, cpu_T[1], IS_USER(s));
b5ff1b31
FB		 1148}
1149
1150static inline void gen_vfp_st(DisasContext *s, int dp)
1151{
1152 if (dp)
4373f3ce 1153 tcg_gen_qemu_st64(cpu_F0d, cpu_T[1], IS_USER(s));
b5ff1b31 1154 else
4373f3ce 1155 tcg_gen_qemu_st32(cpu_F0s, cpu_T[1], IS_USER(s));
b5ff1b31
FB		 1156}
1157
8e96005d
FB		 1158static inline long
1159vfp_reg_offset (int dp, int reg)
1160{
1161 if (dp)
1162 return offsetof(CPUARMState, vfp.regs[reg]);
1163 else if (reg & 1) {
1164 return offsetof(CPUARMState, vfp.regs[reg >> 1])
1165 + offsetof(CPU_DoubleU, l.upper);
1166 } else {
1167 return offsetof(CPUARMState, vfp.regs[reg >> 1])
1168 + offsetof(CPU_DoubleU, l.lower);
1169 }
1170}
9ee6e8bb
PB		 1171
1172/* Return the offset of a 32-bit piece of a NEON register.
1173 zero is the least significant end of the register. */
1174static inline long
1175neon_reg_offset (int reg, int n)
1176{
1177 int sreg;
1178 sreg = reg * 2 + n;
1179 return vfp_reg_offset(0, sreg);
1180}
1181
ad69471c
PB		 1182/* FIXME: Remove these. */
1183#define neon_T0 cpu_T[0]
1184#define neon_T1 cpu_T[1]
1185#define NEON_GET_REG(T, reg, n) \
1186 tcg_gen_ld_i32(neon_##T, cpu_env, neon_reg_offset(reg, n))
1187#define NEON_SET_REG(T, reg, n) \
1188 tcg_gen_st_i32(neon_##T, cpu_env, neon_reg_offset(reg, n))
9ee6e8bb 1189
8f8e3aa4
PB		 1190static TCGv neon_load_reg(int reg, int pass)
1191{
1192 TCGv tmp = new_tmp();
1193 tcg_gen_ld_i32(tmp, cpu_env, neon_reg_offset(reg, pass));
1194 return tmp;
1195}
1196
1197static void neon_store_reg(int reg, int pass, TCGv var)
1198{
1199 tcg_gen_st_i32(var, cpu_env, neon_reg_offset(reg, pass));
1200 dead_tmp(var);
1201}
1202
ad69471c
PB		 1203static inline void neon_load_reg64(TCGv var, int reg)
1204{
1205 tcg_gen_ld_i64(var, cpu_env, vfp_reg_offset(1, reg));
1206}
1207
1208static inline void neon_store_reg64(TCGv var, int reg)
1209{
1210 tcg_gen_st_i64(var, cpu_env, vfp_reg_offset(1, reg));
1211}
1212
4373f3ce
PB		 1213#define tcg_gen_ld_f32 tcg_gen_ld_i32
1214#define tcg_gen_ld_f64 tcg_gen_ld_i64
1215#define tcg_gen_st_f32 tcg_gen_st_i32
1216#define tcg_gen_st_f64 tcg_gen_st_i64
1217
b7bcbe95
FB		 1218static inline void gen_mov_F0_vreg(int dp, int reg)
1219{
1220 if (dp)
4373f3ce 1221 tcg_gen_ld_f64(cpu_F0d, cpu_env, vfp_reg_offset(dp, reg));
b7bcbe95 1222 else
4373f3ce 1223 tcg_gen_ld_f32(cpu_F0s, cpu_env, vfp_reg_offset(dp, reg));
b7bcbe95
FB		 1224}
1225
1226static inline void gen_mov_F1_vreg(int dp, int reg)
1227{
1228 if (dp)
4373f3ce 1229 tcg_gen_ld_f64(cpu_F1d, cpu_env, vfp_reg_offset(dp, reg));
b7bcbe95 1230 else
4373f3ce 1231 tcg_gen_ld_f32(cpu_F1s, cpu_env, vfp_reg_offset(dp, reg));
b7bcbe95
FB		 1232}
1233
1234static inline void gen_mov_vreg_F0(int dp, int reg)
1235{
1236 if (dp)
4373f3ce 1237 tcg_gen_st_f64(cpu_F0d, cpu_env, vfp_reg_offset(dp, reg));
b7bcbe95 1238 else
4373f3ce 1239 tcg_gen_st_f32(cpu_F0s, cpu_env, vfp_reg_offset(dp, reg));
b7bcbe95
FB		 1240}
1241
18c9b560
AZ		 1242#define ARM_CP_RW_BIT (1 << 20)
1243
e677137d
PB		 1244static inline void iwmmxt_load_reg(TCGv var, int reg)
1245{
1246 tcg_gen_ld_i64(var, cpu_env, offsetof(CPUState, iwmmxt.regs[reg]));
1247}
1248
1249static inline void iwmmxt_store_reg(TCGv var, int reg)
1250{
1251 tcg_gen_st_i64(var, cpu_env, offsetof(CPUState, iwmmxt.regs[reg]));
1252}
1253
1254static inline void gen_op_iwmmxt_movl_wCx_T0(int reg)
1255{
1256 tcg_gen_st_i32(cpu_T[0], cpu_env, offsetof(CPUState, iwmmxt.cregs[reg]));
1257}
1258
1259static inline void gen_op_iwmmxt_movl_T0_wCx(int reg)
1260{
1261 tcg_gen_ld_i32(cpu_T[0], cpu_env, offsetof(CPUState, iwmmxt.cregs[reg]));
1262}
1263
1264static inline void gen_op_iwmmxt_movl_T1_wCx(int reg)
1265{
1266 tcg_gen_ld_i32(cpu_T[1], cpu_env, offsetof(CPUState, iwmmxt.cregs[reg]));
1267}
1268
1269static inline void gen_op_iwmmxt_movq_wRn_M0(int rn)
1270{
1271 iwmmxt_store_reg(cpu_M0, rn);
1272}
1273
1274static inline void gen_op_iwmmxt_movq_M0_wRn(int rn)
1275{
1276 iwmmxt_load_reg(cpu_M0, rn);
1277}
1278
1279static inline void gen_op_iwmmxt_orq_M0_wRn(int rn)
1280{
1281 iwmmxt_load_reg(cpu_V1, rn);
1282 tcg_gen_or_i64(cpu_M0, cpu_M0, cpu_V1);
1283}
1284
1285static inline void gen_op_iwmmxt_andq_M0_wRn(int rn)
1286{
1287 iwmmxt_load_reg(cpu_V1, rn);
1288 tcg_gen_and_i64(cpu_M0, cpu_M0, cpu_V1);
1289}
1290
1291static inline void gen_op_iwmmxt_xorq_M0_wRn(int rn)
1292{
1293 iwmmxt_load_reg(cpu_V1, rn);
1294 tcg_gen_xor_i64(cpu_M0, cpu_M0, cpu_V1);
1295}
1296
1297#define IWMMXT_OP(name) \
1298static inline void gen_op_iwmmxt_##name##_M0_wRn(int rn) \
1299{ \
1300 iwmmxt_load_reg(cpu_V1, rn); \
1301 gen_helper_iwmmxt_##name(cpu_M0, cpu_M0, cpu_V1); \
1302}
1303
1304#define IWMMXT_OP_ENV(name) \
1305static inline void gen_op_iwmmxt_##name##_M0_wRn(int rn) \
1306{ \
1307 iwmmxt_load_reg(cpu_V1, rn); \
1308 gen_helper_iwmmxt_##name(cpu_M0, cpu_env, cpu_M0, cpu_V1); \
1309}
1310
1311#define IWMMXT_OP_ENV_SIZE(name) \
1312IWMMXT_OP_ENV(name##b) \
1313IWMMXT_OP_ENV(name##w) \
1314IWMMXT_OP_ENV(name##l)
1315
1316#define IWMMXT_OP_ENV1(name) \
1317static inline void gen_op_iwmmxt_##name##_M0(void) \
1318{ \
1319 gen_helper_iwmmxt_##name(cpu_M0, cpu_env, cpu_M0); \
1320}
1321
1322IWMMXT_OP(maddsq)
1323IWMMXT_OP(madduq)
1324IWMMXT_OP(sadb)
1325IWMMXT_OP(sadw)
1326IWMMXT_OP(mulslw)
1327IWMMXT_OP(mulshw)
1328IWMMXT_OP(mululw)
1329IWMMXT_OP(muluhw)
1330IWMMXT_OP(macsw)
1331IWMMXT_OP(macuw)
1332
1333IWMMXT_OP_ENV_SIZE(unpackl)
1334IWMMXT_OP_ENV_SIZE(unpackh)
1335
1336IWMMXT_OP_ENV1(unpacklub)
1337IWMMXT_OP_ENV1(unpackluw)
1338IWMMXT_OP_ENV1(unpacklul)
1339IWMMXT_OP_ENV1(unpackhub)
1340IWMMXT_OP_ENV1(unpackhuw)
1341IWMMXT_OP_ENV1(unpackhul)
1342IWMMXT_OP_ENV1(unpacklsb)
1343IWMMXT_OP_ENV1(unpacklsw)
1344IWMMXT_OP_ENV1(unpacklsl)
1345IWMMXT_OP_ENV1(unpackhsb)
1346IWMMXT_OP_ENV1(unpackhsw)
1347IWMMXT_OP_ENV1(unpackhsl)
1348
1349IWMMXT_OP_ENV_SIZE(cmpeq)
1350IWMMXT_OP_ENV_SIZE(cmpgtu)
1351IWMMXT_OP_ENV_SIZE(cmpgts)
1352
1353IWMMXT_OP_ENV_SIZE(mins)
1354IWMMXT_OP_ENV_SIZE(minu)
1355IWMMXT_OP_ENV_SIZE(maxs)
1356IWMMXT_OP_ENV_SIZE(maxu)
1357
1358IWMMXT_OP_ENV_SIZE(subn)
1359IWMMXT_OP_ENV_SIZE(addn)
1360IWMMXT_OP_ENV_SIZE(subu)
1361IWMMXT_OP_ENV_SIZE(addu)
1362IWMMXT_OP_ENV_SIZE(subs)
1363IWMMXT_OP_ENV_SIZE(adds)
1364
1365IWMMXT_OP_ENV(avgb0)
1366IWMMXT_OP_ENV(avgb1)
1367IWMMXT_OP_ENV(avgw0)
1368IWMMXT_OP_ENV(avgw1)
1369
1370IWMMXT_OP(msadb)
1371
1372IWMMXT_OP_ENV(packuw)
1373IWMMXT_OP_ENV(packul)
1374IWMMXT_OP_ENV(packuq)
1375IWMMXT_OP_ENV(packsw)
1376IWMMXT_OP_ENV(packsl)
1377IWMMXT_OP_ENV(packsq)
1378
1379static inline void gen_op_iwmmxt_muladdsl_M0_T0_T1(void)
1380{
1381 gen_helper_iwmmxt_muladdsl(cpu_M0, cpu_M0, cpu_T[0], cpu_T[1]);
1382}
1383
1384static inline void gen_op_iwmmxt_muladdsw_M0_T0_T1(void)
1385{
1386 gen_helper_iwmmxt_muladdsw(cpu_M0, cpu_M0, cpu_T[0], cpu_T[1]);
1387}
1388
1389static inline void gen_op_iwmmxt_muladdswl_M0_T0_T1(void)
1390{
1391 gen_helper_iwmmxt_muladdswl(cpu_M0, cpu_M0, cpu_T[0], cpu_T[1]);
1392}
1393
1394static inline void gen_op_iwmmxt_align_M0_T0_wRn(int rn)
1395{
1396 iwmmxt_load_reg(cpu_V1, rn);
1397 gen_helper_iwmmxt_align(cpu_M0, cpu_M0, cpu_V1, cpu_T[0]);
1398}
1399
1400static inline void gen_op_iwmmxt_insr_M0_T0_T1(int shift)
1401{
1402 TCGv tmp = tcg_const_i32(shift);
1403 gen_helper_iwmmxt_insr(cpu_M0, cpu_M0, cpu_T[0], cpu_T[1], tmp);
1404}
1405
1406static inline void gen_op_iwmmxt_extrsb_T0_M0(int shift)
1407{
1408 tcg_gen_shri_i64(cpu_M0, cpu_M0, shift);
1409 tcg_gen_trunc_i64_i32(cpu_T[0], cpu_M0);
1410 tcg_gen_ext8s_i32(cpu_T[0], cpu_T[0]);
1411}
1412
1413static inline void gen_op_iwmmxt_extrsw_T0_M0(int shift)
1414{
1415 tcg_gen_shri_i64(cpu_M0, cpu_M0, shift);
1416 tcg_gen_trunc_i64_i32(cpu_T[0], cpu_M0);
1417 tcg_gen_ext16s_i32(cpu_T[0], cpu_T[0]);
1418}
1419
1420static inline void gen_op_iwmmxt_extru_T0_M0(int shift, uint32_t mask)
1421{
1422 tcg_gen_shri_i64(cpu_M0, cpu_M0, shift);
1423 tcg_gen_trunc_i64_i32(cpu_T[0], cpu_M0);
1424 if (mask != ~0u)
1425 tcg_gen_andi_i32(cpu_T[0], cpu_T[0], mask);
1426}
1427
1428static void gen_op_iwmmxt_set_mup(void)
1429{
1430 TCGv tmp;
1431 tmp = load_cpu_field(iwmmxt.cregs[ARM_IWMMXT_wCon]);
1432 tcg_gen_ori_i32(tmp, tmp, 2);
1433 store_cpu_field(tmp, iwmmxt.cregs[ARM_IWMMXT_wCon]);
1434}
1435
1436static void gen_op_iwmmxt_set_cup(void)
1437{
1438 TCGv tmp;
1439 tmp = load_cpu_field(iwmmxt.cregs[ARM_IWMMXT_wCon]);
1440 tcg_gen_ori_i32(tmp, tmp, 1);
1441 store_cpu_field(tmp, iwmmxt.cregs[ARM_IWMMXT_wCon]);
1442}
1443
1444static void gen_op_iwmmxt_setpsr_nz(void)
1445{
1446 TCGv tmp = new_tmp();
1447 gen_helper_iwmmxt_setpsr_nz(tmp, cpu_M0);
1448 store_cpu_field(tmp, iwmmxt.cregs[ARM_IWMMXT_wCASF]);
1449}
1450
1451static inline void gen_op_iwmmxt_addl_M0_wRn(int rn)
1452{
1453 iwmmxt_load_reg(cpu_V1, rn);
1454 tcg_gen_andi_i64(cpu_V1, cpu_V1, 0xffffffffu);
1455 tcg_gen_add_i64(cpu_M0, cpu_M0, cpu_V1);
1456}
1457
1458
1459static void gen_iwmmxt_movl_T0_T1_wRn(int rn)
1460{
1461 iwmmxt_load_reg(cpu_V0, rn);
1462 tcg_gen_trunc_i64_i32(cpu_T[0], cpu_V0);
1463 tcg_gen_shri_i64(cpu_V0, cpu_V0, 32);
1464 tcg_gen_trunc_i64_i32(cpu_T[1], cpu_V0);
1465}
1466
1467static void gen_iwmmxt_movl_wRn_T0_T1(int rn)
1468{
1469 tcg_gen_extu_i32_i64(cpu_V0, cpu_T[0]);
1470 tcg_gen_extu_i32_i64(cpu_V1, cpu_T[0]);
1471 tcg_gen_shli_i64(cpu_V1, cpu_V1, 32);
1472 tcg_gen_or_i64(cpu_V0, cpu_V0, cpu_V1);
1473 iwmmxt_store_reg(cpu_V0, rn);
1474}
1475
18c9b560
AZ		 1476static inline int gen_iwmmxt_address(DisasContext *s, uint32_t insn)
1477{
1478 int rd;
1479 uint32_t offset;
1480
1481 rd = (insn >> 16) & 0xf;
1482 gen_movl_T1_reg(s, rd);
1483
1484 offset = (insn & 0xff) << ((insn >> 7) & 2);
1485 if (insn & (1 << 24)) {
1486 /* Pre indexed */
1487 if (insn & (1 << 23))
1488 gen_op_addl_T1_im(offset);
1489 else
1490 gen_op_addl_T1_im(-offset);
1491
1492 if (insn & (1 << 21))
1493 gen_movl_reg_T1(s, rd);
1494 } else if (insn & (1 << 21)) {
1495 /* Post indexed */
1496 if (insn & (1 << 23))
1497 gen_op_movl_T0_im(offset);
1498 else
1499 gen_op_movl_T0_im(- offset);
1500 gen_op_addl_T0_T1();
1501 gen_movl_reg_T0(s, rd);
1502 } else if (!(insn & (1 << 23)))
1503 return 1;
1504 return 0;
1505}
1506
1507static inline int gen_iwmmxt_shift(uint32_t insn, uint32_t mask)
1508{
1509 int rd = (insn >> 0) & 0xf;
1510
1511 if (insn & (1 << 8))
1512 if (rd < ARM_IWMMXT_wCGR0 || rd > ARM_IWMMXT_wCGR3)
1513 return 1;
1514 else
1515 gen_op_iwmmxt_movl_T0_wCx(rd);
1516 else
e677137d 1517 gen_iwmmxt_movl_T0_T1_wRn(rd);
18c9b560
AZ		 1518
1519 gen_op_movl_T1_im(mask);
1520 gen_op_andl_T0_T1();
1521 return 0;
1522}
1523
1524/* Disassemble an iwMMXt instruction. Returns nonzero if an error occured
1525 (ie. an undefined instruction). */
1526static int disas_iwmmxt_insn(CPUState *env, DisasContext *s, uint32_t insn)
1527{
1528 int rd, wrd;
1529 int rdhi, rdlo, rd0, rd1, i;
b0109805 1530 TCGv tmp;
18c9b560
AZ		 1531
1532 if ((insn & 0x0e000e00) == 0x0c000000) {
1533 if ((insn & 0x0fe00ff0) == 0x0c400000) {
1534 wrd = insn & 0xf;
1535 rdlo = (insn >> 12) & 0xf;
1536 rdhi = (insn >> 16) & 0xf;
1537 if (insn & ARM_CP_RW_BIT) { /* TMRRC */
e677137d 1538 gen_iwmmxt_movl_T0_T1_wRn(wrd);
18c9b560
AZ		 1539 gen_movl_reg_T0(s, rdlo);
1540 gen_movl_reg_T1(s, rdhi);
1541 } else { /* TMCRR */
1542 gen_movl_T0_reg(s, rdlo);
1543 gen_movl_T1_reg(s, rdhi);
e677137d 1544 gen_iwmmxt_movl_wRn_T0_T1(wrd);
18c9b560
AZ		 1545 gen_op_iwmmxt_set_mup();
1546 }
1547 return 0;
1548 }
1549
1550 wrd = (insn >> 12) & 0xf;
1551 if (gen_iwmmxt_address(s, insn))
1552 return 1;
1553 if (insn & ARM_CP_RW_BIT) {
1554 if ((insn >> 28) == 0xf) { /* WLDRW wCx */
b0109805
PB		 1555 tmp = gen_ld32(cpu_T[1], IS_USER(s));
1556 tcg_gen_mov_i32(cpu_T[0], tmp);
1557 dead_tmp(tmp);
18c9b560
AZ		 1558 gen_op_iwmmxt_movl_wCx_T0(wrd);
1559 } else {
e677137d
PB		 1560 i = 1;
1561 if (insn & (1 << 8)) {
1562 if (insn & (1 << 22)) { /* WLDRD */
1563 tcg_gen_qemu_ld64(cpu_M0, cpu_T[1], IS_USER(s));
1564 i = 0;
1565 } else { /* WLDRW wRd */
1566 tmp = gen_ld32(cpu_T[1], IS_USER(s));
1567 }
1568 } else {
1569 if (insn & (1 << 22)) { /* WLDRH */
1570 tmp = gen_ld16u(cpu_T[1], IS_USER(s));
1571 } else { /* WLDRB */
1572 tmp = gen_ld8u(cpu_T[1], IS_USER(s));
1573 }
1574 }
1575 if (i) {
1576 tcg_gen_extu_i32_i64(cpu_M0, tmp);
1577 dead_tmp(tmp);
1578 }
18c9b560
AZ		 1579 gen_op_iwmmxt_movq_wRn_M0(wrd);
1580 }
1581 } else {
1582 if ((insn >> 28) == 0xf) { /* WSTRW wCx */
1583 gen_op_iwmmxt_movl_T0_wCx(wrd);
b0109805
PB		 1584 tmp = new_tmp();
1585 tcg_gen_mov_i32(tmp, cpu_T[0]);
1586 gen_st32(tmp, cpu_T[1], IS_USER(s));
18c9b560
AZ		 1587 } else {
1588 gen_op_iwmmxt_movq_M0_wRn(wrd);
e677137d
PB		 1589 tmp = new_tmp();
1590 if (insn & (1 << 8)) {
1591 if (insn & (1 << 22)) { /* WSTRD */
1592 dead_tmp(tmp);
1593 tcg_gen_qemu_st64(cpu_M0, cpu_T[1], IS_USER(s));
1594 } else { /* WSTRW wRd */
1595 tcg_gen_trunc_i64_i32(tmp, cpu_M0);
1596 gen_st32(tmp, cpu_T[1], IS_USER(s));
1597 }
1598 } else {
1599 if (insn & (1 << 22)) { /* WSTRH */
1600 tcg_gen_trunc_i64_i32(tmp, cpu_M0);
1601 gen_st16(tmp, cpu_T[1], IS_USER(s));
1602 } else { /* WSTRB */
1603 tcg_gen_trunc_i64_i32(tmp, cpu_M0);
1604 gen_st8(tmp, cpu_T[1], IS_USER(s));
1605 }
1606 }
18c9b560
AZ		 1607 }
1608 }
1609 return 0;
1610 }
1611
1612 if ((insn & 0x0f000000) != 0x0e000000)
1613 return 1;
1614
1615 switch (((insn >> 12) & 0xf00) | ((insn >> 4) & 0xff)) {
1616 case 0x000: /* WOR */
1617 wrd = (insn >> 12) & 0xf;
1618 rd0 = (insn >> 0) & 0xf;
1619 rd1 = (insn >> 16) & 0xf;
1620 gen_op_iwmmxt_movq_M0_wRn(rd0);
1621 gen_op_iwmmxt_orq_M0_wRn(rd1);
1622 gen_op_iwmmxt_setpsr_nz();
1623 gen_op_iwmmxt_movq_wRn_M0(wrd);
1624 gen_op_iwmmxt_set_mup();
1625 gen_op_iwmmxt_set_cup();
1626 break;
1627 case 0x011: /* TMCR */
1628 if (insn & 0xf)
1629 return 1;
1630 rd = (insn >> 12) & 0xf;
1631 wrd = (insn >> 16) & 0xf;
1632 switch (wrd) {
1633 case ARM_IWMMXT_wCID:
1634 case ARM_IWMMXT_wCASF:
1635 break;
1636 case ARM_IWMMXT_wCon:
1637 gen_op_iwmmxt_set_cup();
1638 /* Fall through. */
1639 case ARM_IWMMXT_wCSSF:
1640 gen_op_iwmmxt_movl_T0_wCx(wrd);
1641 gen_movl_T1_reg(s, rd);
1642 gen_op_bicl_T0_T1();
1643 gen_op_iwmmxt_movl_wCx_T0(wrd);
1644 break;
1645 case ARM_IWMMXT_wCGR0:
1646 case ARM_IWMMXT_wCGR1:
1647 case ARM_IWMMXT_wCGR2:
1648 case ARM_IWMMXT_wCGR3:
1649 gen_op_iwmmxt_set_cup();
1650 gen_movl_reg_T0(s, rd);
1651 gen_op_iwmmxt_movl_wCx_T0(wrd);
1652 break;
1653 default:
1654 return 1;
1655 }
1656 break;
1657 case 0x100: /* WXOR */
1658 wrd = (insn >> 12) & 0xf;
1659 rd0 = (insn >> 0) & 0xf;
1660 rd1 = (insn >> 16) & 0xf;
1661 gen_op_iwmmxt_movq_M0_wRn(rd0);
1662 gen_op_iwmmxt_xorq_M0_wRn(rd1);
1663 gen_op_iwmmxt_setpsr_nz();
1664 gen_op_iwmmxt_movq_wRn_M0(wrd);
1665 gen_op_iwmmxt_set_mup();
1666 gen_op_iwmmxt_set_cup();
1667 break;
1668 case 0x111: /* TMRC */
1669 if (insn & 0xf)
1670 return 1;
1671 rd = (insn >> 12) & 0xf;
1672 wrd = (insn >> 16) & 0xf;
1673 gen_op_iwmmxt_movl_T0_wCx(wrd);
1674 gen_movl_reg_T0(s, rd);
1675 break;
1676 case 0x300: /* WANDN */
1677 wrd = (insn >> 12) & 0xf;
1678 rd0 = (insn >> 0) & 0xf;
1679 rd1 = (insn >> 16) & 0xf;
1680 gen_op_iwmmxt_movq_M0_wRn(rd0);
e677137d 1681 tcg_gen_neg_i64(cpu_M0, cpu_M0);
18c9b560
AZ		 1682 gen_op_iwmmxt_andq_M0_wRn(rd1);
1683 gen_op_iwmmxt_setpsr_nz();
1684 gen_op_iwmmxt_movq_wRn_M0(wrd);
1685 gen_op_iwmmxt_set_mup();
1686 gen_op_iwmmxt_set_cup();
1687 break;
1688 case 0x200: /* WAND */
1689 wrd = (insn >> 12) & 0xf;
1690 rd0 = (insn >> 0) & 0xf;
1691 rd1 = (insn >> 16) & 0xf;
1692 gen_op_iwmmxt_movq_M0_wRn(rd0);
1693 gen_op_iwmmxt_andq_M0_wRn(rd1);
1694 gen_op_iwmmxt_setpsr_nz();
1695 gen_op_iwmmxt_movq_wRn_M0(wrd);
1696 gen_op_iwmmxt_set_mup();
1697 gen_op_iwmmxt_set_cup();
1698 break;
1699 case 0x810: case 0xa10: /* WMADD */
1700 wrd = (insn >> 12) & 0xf;
1701 rd0 = (insn >> 0) & 0xf;
1702 rd1 = (insn >> 16) & 0xf;
1703 gen_op_iwmmxt_movq_M0_wRn(rd0);
1704 if (insn & (1 << 21))
1705 gen_op_iwmmxt_maddsq_M0_wRn(rd1);
1706 else
1707 gen_op_iwmmxt_madduq_M0_wRn(rd1);
1708 gen_op_iwmmxt_movq_wRn_M0(wrd);
1709 gen_op_iwmmxt_set_mup();
1710 break;
1711 case 0x10e: case 0x50e: case 0x90e: case 0xd0e: /* WUNPCKIL */
1712 wrd = (insn >> 12) & 0xf;
1713 rd0 = (insn >> 16) & 0xf;
1714 rd1 = (insn >> 0) & 0xf;
1715 gen_op_iwmmxt_movq_M0_wRn(rd0);
1716 switch ((insn >> 22) & 3) {
1717 case 0:
1718 gen_op_iwmmxt_unpacklb_M0_wRn(rd1);
1719 break;
1720 case 1:
1721 gen_op_iwmmxt_unpacklw_M0_wRn(rd1);
1722 break;
1723 case 2:
1724 gen_op_iwmmxt_unpackll_M0_wRn(rd1);
1725 break;
1726 case 3:
1727 return 1;
1728 }
1729 gen_op_iwmmxt_movq_wRn_M0(wrd);
1730 gen_op_iwmmxt_set_mup();
1731 gen_op_iwmmxt_set_cup();
1732 break;
1733 case 0x10c: case 0x50c: case 0x90c: case 0xd0c: /* WUNPCKIH */
1734 wrd = (insn >> 12) & 0xf;
1735 rd0 = (insn >> 16) & 0xf;
1736 rd1 = (insn >> 0) & 0xf;
1737 gen_op_iwmmxt_movq_M0_wRn(rd0);
1738 switch ((insn >> 22) & 3) {
1739 case 0:
1740 gen_op_iwmmxt_unpackhb_M0_wRn(rd1);
1741 break;
1742 case 1:
1743 gen_op_iwmmxt_unpackhw_M0_wRn(rd1);
1744 break;
1745 case 2:
1746 gen_op_iwmmxt_unpackhl_M0_wRn(rd1);
1747 break;
1748 case 3:
1749 return 1;
1750 }
1751 gen_op_iwmmxt_movq_wRn_M0(wrd);
1752 gen_op_iwmmxt_set_mup();
1753 gen_op_iwmmxt_set_cup();
1754 break;
1755 case 0x012: case 0x112: case 0x412: case 0x512: /* WSAD */
1756 wrd = (insn >> 12) & 0xf;
1757 rd0 = (insn >> 16) & 0xf;
1758 rd1 = (insn >> 0) & 0xf;
1759 gen_op_iwmmxt_movq_M0_wRn(rd0);
1760 if (insn & (1 << 22))
1761 gen_op_iwmmxt_sadw_M0_wRn(rd1);
1762 else
1763 gen_op_iwmmxt_sadb_M0_wRn(rd1);
1764 if (!(insn & (1 << 20)))
1765 gen_op_iwmmxt_addl_M0_wRn(wrd);
1766 gen_op_iwmmxt_movq_wRn_M0(wrd);
1767 gen_op_iwmmxt_set_mup();
1768 break;
1769 case 0x010: case 0x110: case 0x210: case 0x310: /* WMUL */
1770 wrd = (insn >> 12) & 0xf;
1771 rd0 = (insn >> 16) & 0xf;
1772 rd1 = (insn >> 0) & 0xf;
1773 gen_op_iwmmxt_movq_M0_wRn(rd0);
e677137d
PB		 1774 if (insn & (1 << 21)) {
1775 if (insn & (1 << 20))
1776 gen_op_iwmmxt_mulshw_M0_wRn(rd1);
1777 else
1778 gen_op_iwmmxt_mulslw_M0_wRn(rd1);
1779 } else {
1780 if (insn & (1 << 20))
1781 gen_op_iwmmxt_muluhw_M0_wRn(rd1);
1782 else
1783 gen_op_iwmmxt_mululw_M0_wRn(rd1);
1784 }
18c9b560
AZ		 1785 gen_op_iwmmxt_movq_wRn_M0(wrd);
1786 gen_op_iwmmxt_set_mup();
1787 break;
1788 case 0x410: case 0x510: case 0x610: case 0x710: /* WMAC */
1789 wrd = (insn >> 12) & 0xf;
1790 rd0 = (insn >> 16) & 0xf;
1791 rd1 = (insn >> 0) & 0xf;
1792 gen_op_iwmmxt_movq_M0_wRn(rd0);
1793 if (insn & (1 << 21))
1794 gen_op_iwmmxt_macsw_M0_wRn(rd1);
1795 else
1796 gen_op_iwmmxt_macuw_M0_wRn(rd1);
1797 if (!(insn & (1 << 20))) {
e677137d
PB		 1798 iwmmxt_load_reg(cpu_V1, wrd);
1799 tcg_gen_add_i64(cpu_M0, cpu_M0, cpu_V1);
18c9b560
AZ		 1800 }
1801 gen_op_iwmmxt_movq_wRn_M0(wrd);
1802 gen_op_iwmmxt_set_mup();
1803 break;
1804 case 0x006: case 0x406: case 0x806: case 0xc06: /* WCMPEQ */
1805 wrd = (insn >> 12) & 0xf;
1806 rd0 = (insn >> 16) & 0xf;
1807 rd1 = (insn >> 0) & 0xf;
1808 gen_op_iwmmxt_movq_M0_wRn(rd0);
1809 switch ((insn >> 22) & 3) {
1810 case 0:
1811 gen_op_iwmmxt_cmpeqb_M0_wRn(rd1);
1812 break;
1813 case 1:
1814 gen_op_iwmmxt_cmpeqw_M0_wRn(rd1);
1815 break;
1816 case 2:
1817 gen_op_iwmmxt_cmpeql_M0_wRn(rd1);
1818 break;
1819 case 3:
1820 return 1;
1821 }
1822 gen_op_iwmmxt_movq_wRn_M0(wrd);
1823 gen_op_iwmmxt_set_mup();
1824 gen_op_iwmmxt_set_cup();
1825 break;
1826 case 0x800: case 0x900: case 0xc00: case 0xd00: /* WAVG2 */
1827 wrd = (insn >> 12) & 0xf;
1828 rd0 = (insn >> 16) & 0xf;
1829 rd1 = (insn >> 0) & 0xf;
1830 gen_op_iwmmxt_movq_M0_wRn(rd0);
e677137d
PB		 1831 if (insn & (1 << 22)) {
1832 if (insn & (1 << 20))
1833 gen_op_iwmmxt_avgw1_M0_wRn(rd1);
1834 else
1835 gen_op_iwmmxt_avgw0_M0_wRn(rd1);
1836 } else {
1837 if (insn & (1 << 20))
1838 gen_op_iwmmxt_avgb1_M0_wRn(rd1);
1839 else
1840 gen_op_iwmmxt_avgb0_M0_wRn(rd1);
1841 }
18c9b560
AZ		 1842 gen_op_iwmmxt_movq_wRn_M0(wrd);
1843 gen_op_iwmmxt_set_mup();
1844 gen_op_iwmmxt_set_cup();
1845 break;
1846 case 0x802: case 0x902: case 0xa02: case 0xb02: /* WALIGNR */
1847 wrd = (insn >> 12) & 0xf;
1848 rd0 = (insn >> 16) & 0xf;
1849 rd1 = (insn >> 0) & 0xf;
1850 gen_op_iwmmxt_movq_M0_wRn(rd0);
1851 gen_op_iwmmxt_movl_T0_wCx(ARM_IWMMXT_wCGR0 + ((insn >> 20) & 3));
1852 gen_op_movl_T1_im(7);
1853 gen_op_andl_T0_T1();
1854 gen_op_iwmmxt_align_M0_T0_wRn(rd1);
1855 gen_op_iwmmxt_movq_wRn_M0(wrd);
1856 gen_op_iwmmxt_set_mup();
1857 break;
1858 case 0x601: case 0x605: case 0x609: case 0x60d: /* TINSR */
1859 rd = (insn >> 12) & 0xf;
1860 wrd = (insn >> 16) & 0xf;
1861 gen_movl_T0_reg(s, rd);
1862 gen_op_iwmmxt_movq_M0_wRn(wrd);
1863 switch ((insn >> 6) & 3) {
1864 case 0:
1865 gen_op_movl_T1_im(0xff);
1866 gen_op_iwmmxt_insr_M0_T0_T1((insn & 7) << 3);
1867 break;
1868 case 1:
1869 gen_op_movl_T1_im(0xffff);
1870 gen_op_iwmmxt_insr_M0_T0_T1((insn & 3) << 4);
1871 break;
1872 case 2:
1873 gen_op_movl_T1_im(0xffffffff);
1874 gen_op_iwmmxt_insr_M0_T0_T1((insn & 1) << 5);
1875 break;
1876 case 3:
1877 return 1;
1878 }
1879 gen_op_iwmmxt_movq_wRn_M0(wrd);
1880 gen_op_iwmmxt_set_mup();
1881 break;
1882 case 0x107: case 0x507: case 0x907: case 0xd07: /* TEXTRM */
1883 rd = (insn >> 12) & 0xf;
1884 wrd = (insn >> 16) & 0xf;
1885 if (rd == 15)
1886 return 1;
1887 gen_op_iwmmxt_movq_M0_wRn(wrd);
1888 switch ((insn >> 22) & 3) {
1889 case 0:
1890 if (insn & 8)
1891 gen_op_iwmmxt_extrsb_T0_M0((insn & 7) << 3);
1892 else {
e677137d 1893 gen_op_iwmmxt_extru_T0_M0((insn & 7) << 3, 0xff);
18c9b560
AZ		 1894 }
1895 break;
1896 case 1:
1897 if (insn & 8)
1898 gen_op_iwmmxt_extrsw_T0_M0((insn & 3) << 4);
1899 else {
e677137d 1900 gen_op_iwmmxt_extru_T0_M0((insn & 3) << 4, 0xffff);
18c9b560
AZ		 1901 }
1902 break;
1903 case 2:
e677137d 1904 gen_op_iwmmxt_extru_T0_M0((insn & 1) << 5, ~0u);
18c9b560
AZ		 1905 break;
1906 case 3:
1907 return 1;
1908 }
b26eefb6 1909 gen_movl_reg_T0(s, rd);
18c9b560
AZ		 1910 break;
1911 case 0x117: case 0x517: case 0x917: case 0xd17: /* TEXTRC */
1912 if ((insn & 0x000ff008) != 0x0003f000)
1913 return 1;
1914 gen_op_iwmmxt_movl_T1_wCx(ARM_IWMMXT_wCASF);
1915 switch ((insn >> 22) & 3) {
1916 case 0:
1917 gen_op_shrl_T1_im(((insn & 7) << 2) + 0);
1918 break;
1919 case 1:
1920 gen_op_shrl_T1_im(((insn & 3) << 3) + 4);
1921 break;
1922 case 2:
1923 gen_op_shrl_T1_im(((insn & 1) << 4) + 12);
1924 break;
1925 case 3:
1926 return 1;
1927 }
1928 gen_op_shll_T1_im(28);
d9ba4830 1929 gen_set_nzcv(cpu_T[1]);
18c9b560
AZ		 1930 break;
1931 case 0x401: case 0x405: case 0x409: case 0x40d: /* TBCST */
1932 rd = (insn >> 12) & 0xf;
1933 wrd = (insn >> 16) & 0xf;
1934 gen_movl_T0_reg(s, rd);
1935 switch ((insn >> 6) & 3) {
1936 case 0:
e677137d 1937 gen_helper_iwmmxt_bcstb(cpu_M0, cpu_T[0]);
18c9b560
AZ		 1938 break;
1939 case 1:
e677137d 1940 gen_helper_iwmmxt_bcstw(cpu_M0, cpu_T[0]);
18c9b560
AZ		 1941 break;
1942 case 2:
e677137d 1943 gen_helper_iwmmxt_bcstl(cpu_M0, cpu_T[0]);
18c9b560
AZ		 1944 break;
1945 case 3:
1946 return 1;
1947 }
1948 gen_op_iwmmxt_movq_wRn_M0(wrd);
1949 gen_op_iwmmxt_set_mup();
1950 break;
1951 case 0x113: case 0x513: case 0x913: case 0xd13: /* TANDC */
1952 if ((insn & 0x000ff00f) != 0x0003f000)
1953 return 1;
1954 gen_op_iwmmxt_movl_T1_wCx(ARM_IWMMXT_wCASF);
1955 switch ((insn >> 22) & 3) {
1956 case 0:
1957 for (i = 0; i < 7; i ++) {
1958 gen_op_shll_T1_im(4);
1959 gen_op_andl_T0_T1();
1960 }
1961 break;
1962 case 1:
1963 for (i = 0; i < 3; i ++) {
1964 gen_op_shll_T1_im(8);
1965 gen_op_andl_T0_T1();
1966 }
1967 break;
1968 case 2:
1969 gen_op_shll_T1_im(16);
1970 gen_op_andl_T0_T1();
1971 break;
1972 case 3:
1973 return 1;
1974 }
d9ba4830 1975 gen_set_nzcv(cpu_T[0]);
18c9b560
AZ		 1976 break;
1977 case 0x01c: case 0x41c: case 0x81c: case 0xc1c: /* WACC */
1978 wrd = (insn >> 12) & 0xf;
1979 rd0 = (insn >> 16) & 0xf;
1980 gen_op_iwmmxt_movq_M0_wRn(rd0);
1981 switch ((insn >> 22) & 3) {
1982 case 0:
e677137d 1983 gen_helper_iwmmxt_addcb(cpu_M0, cpu_M0);
18c9b560
AZ		 1984 break;
1985 case 1:
e677137d 1986 gen_helper_iwmmxt_addcw(cpu_M0, cpu_M0);
18c9b560
AZ		 1987 break;
1988 case 2:
e677137d 1989 gen_helper_iwmmxt_addcl(cpu_M0, cpu_M0);
18c9b560
AZ		 1990 break;
1991 case 3:
1992 return 1;
1993 }
1994 gen_op_iwmmxt_movq_wRn_M0(wrd);
1995 gen_op_iwmmxt_set_mup();
1996 break;
1997 case 0x115: case 0x515: case 0x915: case 0xd15: /* TORC */
1998 if ((insn & 0x000ff00f) != 0x0003f000)
1999 return 1;
2000 gen_op_iwmmxt_movl_T1_wCx(ARM_IWMMXT_wCASF);
2001 switch ((insn >> 22) & 3) {
2002 case 0:
2003 for (i = 0; i < 7; i ++) {
2004 gen_op_shll_T1_im(4);
2005 gen_op_orl_T0_T1();
2006 }
2007 break;
2008 case 1:
2009 for (i = 0; i < 3; i ++) {
2010 gen_op_shll_T1_im(8);
2011 gen_op_orl_T0_T1();
2012 }
2013 break;
2014 case 2:
2015 gen_op_shll_T1_im(16);
2016 gen_op_orl_T0_T1();
2017 break;
2018 case 3:
2019 return 1;
2020 }
d9ba4830 2021 gen_set_nzcv(cpu_T[0]);
18c9b560
AZ		 2022 break;
2023 case 0x103: case 0x503: case 0x903: case 0xd03: /* TMOVMSK */
2024 rd = (insn >> 12) & 0xf;
2025 rd0 = (insn >> 16) & 0xf;
2026 if ((insn & 0xf) != 0)
2027 return 1;
2028 gen_op_iwmmxt_movq_M0_wRn(rd0);
2029 switch ((insn >> 22) & 3) {
2030 case 0:
e677137d 2031 gen_helper_iwmmxt_msbb(cpu_T[0], cpu_M0);
18c9b560
AZ		 2032 break;
2033 case 1:
e677137d 2034 gen_helper_iwmmxt_msbw(cpu_T[0], cpu_M0);
18c9b560
AZ		 2035 break;
2036 case 2:
e677137d 2037 gen_helper_iwmmxt_msbl(cpu_T[0], cpu_M0);
18c9b560
AZ		 2038 break;
2039 case 3:
2040 return 1;
2041 }
2042 gen_movl_reg_T0(s, rd);
2043 break;
2044 case 0x106: case 0x306: case 0x506: case 0x706: /* WCMPGT */
2045 case 0x906: case 0xb06: case 0xd06: case 0xf06:
2046 wrd = (insn >> 12) & 0xf;
2047 rd0 = (insn >> 16) & 0xf;
2048 rd1 = (insn >> 0) & 0xf;
2049 gen_op_iwmmxt_movq_M0_wRn(rd0);
2050 switch ((insn >> 22) & 3) {
2051 case 0:
2052 if (insn & (1 << 21))
2053 gen_op_iwmmxt_cmpgtsb_M0_wRn(rd1);
2054 else
2055 gen_op_iwmmxt_cmpgtub_M0_wRn(rd1);
2056 break;
2057 case 1:
2058 if (insn & (1 << 21))
2059 gen_op_iwmmxt_cmpgtsw_M0_wRn(rd1);
2060 else
2061 gen_op_iwmmxt_cmpgtuw_M0_wRn(rd1);
2062 break;
2063 case 2:
2064 if (insn & (1 << 21))
2065 gen_op_iwmmxt_cmpgtsl_M0_wRn(rd1);
2066 else
2067 gen_op_iwmmxt_cmpgtul_M0_wRn(rd1);
2068 break;
2069 case 3:
2070 return 1;
2071 }
2072 gen_op_iwmmxt_movq_wRn_M0(wrd);
2073 gen_op_iwmmxt_set_mup();
2074 gen_op_iwmmxt_set_cup();
2075 break;
2076 case 0x00e: case 0x20e: case 0x40e: case 0x60e: /* WUNPCKEL */
2077 case 0x80e: case 0xa0e: case 0xc0e: case 0xe0e:
2078 wrd = (insn >> 12) & 0xf;
2079 rd0 = (insn >> 16) & 0xf;
2080 gen_op_iwmmxt_movq_M0_wRn(rd0);
2081 switch ((insn >> 22) & 3) {
2082 case 0:
2083 if (insn & (1 << 21))
2084 gen_op_iwmmxt_unpacklsb_M0();
2085 else
2086 gen_op_iwmmxt_unpacklub_M0();
2087 break;
2088 case 1:
2089 if (insn & (1 << 21))
2090 gen_op_iwmmxt_unpacklsw_M0();
2091 else
2092 gen_op_iwmmxt_unpackluw_M0();
2093 break;
2094 case 2:
2095 if (insn & (1 << 21))
2096 gen_op_iwmmxt_unpacklsl_M0();
2097 else
2098 gen_op_iwmmxt_unpacklul_M0();
2099 break;
2100 case 3:
2101 return 1;
2102 }
2103 gen_op_iwmmxt_movq_wRn_M0(wrd);
2104 gen_op_iwmmxt_set_mup();
2105 gen_op_iwmmxt_set_cup();
2106 break;
2107 case 0x00c: case 0x20c: case 0x40c: case 0x60c: /* WUNPCKEH */
2108 case 0x80c: case 0xa0c: case 0xc0c: case 0xe0c:
2109 wrd = (insn >> 12) & 0xf;
2110 rd0 = (insn >> 16) & 0xf;
2111 gen_op_iwmmxt_movq_M0_wRn(rd0);
2112 switch ((insn >> 22) & 3) {
2113 case 0:
2114 if (insn & (1 << 21))
2115 gen_op_iwmmxt_unpackhsb_M0();
2116 else
2117 gen_op_iwmmxt_unpackhub_M0();
2118 break;
2119 case 1:
2120 if (insn & (1 << 21))
2121 gen_op_iwmmxt_unpackhsw_M0();
2122 else
2123 gen_op_iwmmxt_unpackhuw_M0();
2124 break;
2125 case 2:
2126 if (insn & (1 << 21))
2127 gen_op_iwmmxt_unpackhsl_M0();
2128 else
2129 gen_op_iwmmxt_unpackhul_M0();
2130 break;
2131 case 3:
2132 return 1;
2133 }
2134 gen_op_iwmmxt_movq_wRn_M0(wrd);
2135 gen_op_iwmmxt_set_mup();
2136 gen_op_iwmmxt_set_cup();
2137 break;
2138 case 0x204: case 0x604: case 0xa04: case 0xe04: /* WSRL */
2139 case 0x214: case 0x614: case 0xa14: case 0xe14:
2140 wrd = (insn >> 12) & 0xf;
2141 rd0 = (insn >> 16) & 0xf;
2142 gen_op_iwmmxt_movq_M0_wRn(rd0);
2143 if (gen_iwmmxt_shift(insn, 0xff))
2144 return 1;
2145 switch ((insn >> 22) & 3) {
2146 case 0:
2147 return 1;
2148 case 1:
e677137d 2149 gen_helper_iwmmxt_srlw(cpu_M0, cpu_env, cpu_M0, cpu_T[0]);
18c9b560
AZ		 2150 break;
2151 case 2:
e677137d 2152 gen_helper_iwmmxt_srll(cpu_M0, cpu_env, cpu_M0, cpu_T[0]);
18c9b560
AZ		 2153 break;
2154 case 3:
e677137d 2155 gen_helper_iwmmxt_srlq(cpu_M0, cpu_env, cpu_M0, cpu_T[0]);
18c9b560
AZ		 2156 break;
2157 }
2158 gen_op_iwmmxt_movq_wRn_M0(wrd);
2159 gen_op_iwmmxt_set_mup();
2160 gen_op_iwmmxt_set_cup();
2161 break;
2162 case 0x004: case 0x404: case 0x804: case 0xc04: /* WSRA */
2163 case 0x014: case 0x414: case 0x814: case 0xc14:
2164 wrd = (insn >> 12) & 0xf;
2165 rd0 = (insn >> 16) & 0xf;
2166 gen_op_iwmmxt_movq_M0_wRn(rd0);
2167 if (gen_iwmmxt_shift(insn, 0xff))
2168 return 1;
2169 switch ((insn >> 22) & 3) {
2170 case 0:
2171 return 1;
2172 case 1:
e677137d 2173 gen_helper_iwmmxt_sraw(cpu_M0, cpu_env, cpu_M0, cpu_T[0]);
18c9b560
AZ		 2174 break;
2175 case 2:
e677137d 2176 gen_helper_iwmmxt_sral(cpu_M0, cpu_env, cpu_M0, cpu_T[0]);
18c9b560
AZ		 2177 break;
2178 case 3:
e677137d 2179 gen_helper_iwmmxt_sraq(cpu_M0, cpu_env, cpu_M0, cpu_T[0]);
18c9b560
AZ		 2180 break;
2181 }
2182 gen_op_iwmmxt_movq_wRn_M0(wrd);
2183 gen_op_iwmmxt_set_mup();
2184 gen_op_iwmmxt_set_cup();
2185 break;
2186 case 0x104: case 0x504: case 0x904: case 0xd04: /* WSLL */
2187 case 0x114: case 0x514: case 0x914: case 0xd14:
2188 wrd = (insn >> 12) & 0xf;
2189 rd0 = (insn >> 16) & 0xf;
2190 gen_op_iwmmxt_movq_M0_wRn(rd0);
2191 if (gen_iwmmxt_shift(insn, 0xff))
2192 return 1;
2193 switch ((insn >> 22) & 3) {
2194 case 0:
2195 return 1;
2196 case 1:
e677137d 2197 gen_helper_iwmmxt_sllw(cpu_M0, cpu_env, cpu_M0, cpu_T[0]);
18c9b560
AZ		 2198 break;
2199 case 2:
e677137d 2200 gen_helper_iwmmxt_slll(cpu_M0, cpu_env, cpu_M0, cpu_T[0]);
18c9b560
AZ		 2201 break;
2202 case 3:
e677137d 2203 gen_helper_iwmmxt_sllq(cpu_M0, cpu_env, cpu_M0, cpu_T[0]);
18c9b560
AZ		 2204 break;
2205 }
2206 gen_op_iwmmxt_movq_wRn_M0(wrd);
2207 gen_op_iwmmxt_set_mup();
2208 gen_op_iwmmxt_set_cup();
2209 break;
2210 case 0x304: case 0x704: case 0xb04: case 0xf04: /* WROR */
2211 case 0x314: case 0x714: case 0xb14: case 0xf14:
2212 wrd = (insn >> 12) & 0xf;
2213 rd0 = (insn >> 16) & 0xf;
2214 gen_op_iwmmxt_movq_M0_wRn(rd0);
2215 switch ((insn >> 22) & 3) {
2216 case 0:
2217 return 1;
2218 case 1:
2219 if (gen_iwmmxt_shift(insn, 0xf))
2220 return 1;
e677137d 2221 gen_helper_iwmmxt_rorw(cpu_M0, cpu_env, cpu_M0, cpu_T[0]);
18c9b560
AZ		 2222 break;
2223 case 2:
2224 if (gen_iwmmxt_shift(insn, 0x1f))
2225 return 1;
e677137d 2226 gen_helper_iwmmxt_rorl(cpu_M0, cpu_env, cpu_M0, cpu_T[0]);
18c9b560
AZ		 2227 break;
2228 case 3:
2229 if (gen_iwmmxt_shift(insn, 0x3f))
2230 return 1;
e677137d 2231 gen_helper_iwmmxt_rorq(cpu_M0, cpu_env, cpu_M0, cpu_T[0]);
18c9b560
AZ		 2232 break;
2233 }
2234 gen_op_iwmmxt_movq_wRn_M0(wrd);
2235 gen_op_iwmmxt_set_mup();
2236 gen_op_iwmmxt_set_cup();
2237 break;
2238 case 0x116: case 0x316: case 0x516: case 0x716: /* WMIN */
2239 case 0x916: case 0xb16: case 0xd16: case 0xf16:
2240 wrd = (insn >> 12) & 0xf;
2241 rd0 = (insn >> 16) & 0xf;
2242 rd1 = (insn >> 0) & 0xf;
2243 gen_op_iwmmxt_movq_M0_wRn(rd0);
2244 switch ((insn >> 22) & 3) {
2245 case 0:
2246 if (insn & (1 << 21))
2247 gen_op_iwmmxt_minsb_M0_wRn(rd1);
2248 else
2249 gen_op_iwmmxt_minub_M0_wRn(rd1);
2250 break;
2251 case 1:
2252 if (insn & (1 << 21))
2253 gen_op_iwmmxt_minsw_M0_wRn(rd1);
2254 else
2255 gen_op_iwmmxt_minuw_M0_wRn(rd1);
2256 break;
2257 case 2:
2258 if (insn & (1 << 21))
2259 gen_op_iwmmxt_minsl_M0_wRn(rd1);
2260 else
2261 gen_op_iwmmxt_minul_M0_wRn(rd1);
2262 break;
2263 case 3:
2264 return 1;
2265 }
2266 gen_op_iwmmxt_movq_wRn_M0(wrd);
2267 gen_op_iwmmxt_set_mup();
2268 break;
2269 case 0x016: case 0x216: case 0x416: case 0x616: /* WMAX */
2270 case 0x816: case 0xa16: case 0xc16: case 0xe16:
2271 wrd = (insn >> 12) & 0xf;
2272 rd0 = (insn >> 16) & 0xf;
2273 rd1 = (insn >> 0) & 0xf;
2274 gen_op_iwmmxt_movq_M0_wRn(rd0);
2275 switch ((insn >> 22) & 3) {
2276 case 0:
2277 if (insn & (1 << 21))
2278 gen_op_iwmmxt_maxsb_M0_wRn(rd1);
2279 else
2280 gen_op_iwmmxt_maxub_M0_wRn(rd1);
2281 break;
2282 case 1:
2283 if (insn & (1 << 21))
2284 gen_op_iwmmxt_maxsw_M0_wRn(rd1);
2285 else
2286 gen_op_iwmmxt_maxuw_M0_wRn(rd1);
2287 break;
2288 case 2:
2289 if (insn & (1 << 21))
2290 gen_op_iwmmxt_maxsl_M0_wRn(rd1);
2291 else
2292 gen_op_iwmmxt_maxul_M0_wRn(rd1);
2293 break;
2294 case 3:
2295 return 1;
2296 }
2297 gen_op_iwmmxt_movq_wRn_M0(wrd);
2298 gen_op_iwmmxt_set_mup();
2299 break;
2300 case 0x002: case 0x102: case 0x202: case 0x302: /* WALIGNI */
2301 case 0x402: case 0x502: case 0x602: case 0x702:
2302 wrd = (insn >> 12) & 0xf;
2303 rd0 = (insn >> 16) & 0xf;
2304 rd1 = (insn >> 0) & 0xf;
2305 gen_op_iwmmxt_movq_M0_wRn(rd0);
2306 gen_op_movl_T0_im((insn >> 20) & 3);
2307 gen_op_iwmmxt_align_M0_T0_wRn(rd1);
2308 gen_op_iwmmxt_movq_wRn_M0(wrd);
2309 gen_op_iwmmxt_set_mup();
2310 break;
2311 case 0x01a: case 0x11a: case 0x21a: case 0x31a: /* WSUB */
2312 case 0x41a: case 0x51a: case 0x61a: case 0x71a:
2313 case 0x81a: case 0x91a: case 0xa1a: case 0xb1a:
2314 case 0xc1a: case 0xd1a: case 0xe1a: case 0xf1a:
2315 wrd = (insn >> 12) & 0xf;
2316 rd0 = (insn >> 16) & 0xf;
2317 rd1 = (insn >> 0) & 0xf;
2318 gen_op_iwmmxt_movq_M0_wRn(rd0);
2319 switch ((insn >> 20) & 0xf) {
2320 case 0x0:
2321 gen_op_iwmmxt_subnb_M0_wRn(rd1);
2322 break;
2323 case 0x1:
2324 gen_op_iwmmxt_subub_M0_wRn(rd1);
2325 break;
2326 case 0x3:
2327 gen_op_iwmmxt_subsb_M0_wRn(rd1);
2328 break;
2329 case 0x4:
2330 gen_op_iwmmxt_subnw_M0_wRn(rd1);
2331 break;
2332 case 0x5:
2333 gen_op_iwmmxt_subuw_M0_wRn(rd1);
2334 break;
2335 case 0x7:
2336 gen_op_iwmmxt_subsw_M0_wRn(rd1);
2337 break;
2338 case 0x8:
2339 gen_op_iwmmxt_subnl_M0_wRn(rd1);
2340 break;
2341 case 0x9:
2342 gen_op_iwmmxt_subul_M0_wRn(rd1);
2343 break;
2344 case 0xb:
2345 gen_op_iwmmxt_subsl_M0_wRn(rd1);
2346 break;
2347 default:
2348 return 1;
2349 }
2350 gen_op_iwmmxt_movq_wRn_M0(wrd);
2351 gen_op_iwmmxt_set_mup();
2352 gen_op_iwmmxt_set_cup();
2353 break;
2354 case 0x01e: case 0x11e: case 0x21e: case 0x31e: /* WSHUFH */
2355 case 0x41e: case 0x51e: case 0x61e: case 0x71e:
2356 case 0x81e: case 0x91e: case 0xa1e: case 0xb1e:
2357 case 0xc1e: case 0xd1e: case 0xe1e: case 0xf1e:
2358 wrd = (insn >> 12) & 0xf;
2359 rd0 = (insn >> 16) & 0xf;
2360 gen_op_iwmmxt_movq_M0_wRn(rd0);
2361 gen_op_movl_T0_im(((insn >> 16) & 0xf0) | (insn & 0x0f));
e677137d 2362 gen_helper_iwmmxt_shufh(cpu_M0, cpu_env, cpu_M0, cpu_T[0]);
18c9b560
AZ		 2363 gen_op_iwmmxt_movq_wRn_M0(wrd);
2364 gen_op_iwmmxt_set_mup();
2365 gen_op_iwmmxt_set_cup();
2366 break;
2367 case 0x018: case 0x118: case 0x218: case 0x318: /* WADD */
2368 case 0x418: case 0x518: case 0x618: case 0x718:
2369 case 0x818: case 0x918: case 0xa18: case 0xb18:
2370 case 0xc18: case 0xd18: case 0xe18: case 0xf18:
2371 wrd = (insn >> 12) & 0xf;
2372 rd0 = (insn >> 16) & 0xf;
2373 rd1 = (insn >> 0) & 0xf;
2374 gen_op_iwmmxt_movq_M0_wRn(rd0);
2375 switch ((insn >> 20) & 0xf) {
2376 case 0x0:
2377 gen_op_iwmmxt_addnb_M0_wRn(rd1);
2378 break;
2379 case 0x1:
2380 gen_op_iwmmxt_addub_M0_wRn(rd1);
2381 break;
2382 case 0x3:
2383 gen_op_iwmmxt_addsb_M0_wRn(rd1);
2384 break;
2385 case 0x4:
2386 gen_op_iwmmxt_addnw_M0_wRn(rd1);
2387 break;
2388 case 0x5:
2389 gen_op_iwmmxt_adduw_M0_wRn(rd1);
2390 break;
2391 case 0x7:
2392 gen_op_iwmmxt_addsw_M0_wRn(rd1);
2393 break;
2394 case 0x8:
2395 gen_op_iwmmxt_addnl_M0_wRn(rd1);
2396 break;
2397 case 0x9:
2398 gen_op_iwmmxt_addul_M0_wRn(rd1);
2399 break;
2400 case 0xb:
2401 gen_op_iwmmxt_addsl_M0_wRn(rd1);
2402 break;
2403 default:
2404 return 1;
2405 }
2406 gen_op_iwmmxt_movq_wRn_M0(wrd);
2407 gen_op_iwmmxt_set_mup();
2408 gen_op_iwmmxt_set_cup();
2409 break;
2410 case 0x008: case 0x108: case 0x208: case 0x308: /* WPACK */
2411 case 0x408: case 0x508: case 0x608: case 0x708:
2412 case 0x808: case 0x908: case 0xa08: case 0xb08:
2413 case 0xc08: case 0xd08: case 0xe08: case 0xf08:
2414 wrd = (insn >> 12) & 0xf;
2415 rd0 = (insn >> 16) & 0xf;
2416 rd1 = (insn >> 0) & 0xf;
2417 gen_op_iwmmxt_movq_M0_wRn(rd0);
2418 if (!(insn & (1 << 20)))
2419 return 1;
2420 switch ((insn >> 22) & 3) {
2421 case 0:
2422 return 1;
2423 case 1:
2424 if (insn & (1 << 21))
2425 gen_op_iwmmxt_packsw_M0_wRn(rd1);
2426 else
2427 gen_op_iwmmxt_packuw_M0_wRn(rd1);
2428 break;
2429 case 2:
2430 if (insn & (1 << 21))
2431 gen_op_iwmmxt_packsl_M0_wRn(rd1);
2432 else
2433 gen_op_iwmmxt_packul_M0_wRn(rd1);
2434 break;
2435 case 3:
2436 if (insn & (1 << 21))
2437 gen_op_iwmmxt_packsq_M0_wRn(rd1);
2438 else
2439 gen_op_iwmmxt_packuq_M0_wRn(rd1);
2440 break;
2441 }
2442 gen_op_iwmmxt_movq_wRn_M0(wrd);
2443 gen_op_iwmmxt_set_mup();
2444 gen_op_iwmmxt_set_cup();
2445 break;
2446 case 0x201: case 0x203: case 0x205: case 0x207:
2447 case 0x209: case 0x20b: case 0x20d: case 0x20f:
2448 case 0x211: case 0x213: case 0x215: case 0x217:
2449 case 0x219: case 0x21b: case 0x21d: case 0x21f:
2450 wrd = (insn >> 5) & 0xf;
2451 rd0 = (insn >> 12) & 0xf;
2452 rd1 = (insn >> 0) & 0xf;
2453 if (rd0 == 0xf || rd1 == 0xf)
2454 return 1;
2455 gen_op_iwmmxt_movq_M0_wRn(wrd);
2456 switch ((insn >> 16) & 0xf) {
2457 case 0x0: /* TMIA */
b26eefb6
PB		 2458 gen_movl_T0_reg(s, rd0);
2459 gen_movl_T1_reg(s, rd1);
18c9b560
AZ		 2460 gen_op_iwmmxt_muladdsl_M0_T0_T1();
2461 break;
2462 case 0x8: /* TMIAPH */
b26eefb6
PB		 2463 gen_movl_T0_reg(s, rd0);
2464 gen_movl_T1_reg(s, rd1);
18c9b560
AZ		 2465 gen_op_iwmmxt_muladdsw_M0_T0_T1();
2466 break;
2467 case 0xc: case 0xd: case 0xe: case 0xf: /* TMIAxy */
b26eefb6 2468 gen_movl_T1_reg(s, rd0);
18c9b560
AZ		 2469 if (insn & (1 << 16))
2470 gen_op_shrl_T1_im(16);
2471 gen_op_movl_T0_T1();
b26eefb6 2472 gen_movl_T1_reg(s, rd1);
18c9b560
AZ		 2473 if (insn & (1 << 17))
2474 gen_op_shrl_T1_im(16);
2475 gen_op_iwmmxt_muladdswl_M0_T0_T1();
2476 break;
2477 default:
2478 return 1;
2479 }
2480 gen_op_iwmmxt_movq_wRn_M0(wrd);
2481 gen_op_iwmmxt_set_mup();
2482 break;
2483 default:
2484 return 1;
2485 }
2486
2487 return 0;
2488}
2489
2490/* Disassemble an XScale DSP instruction. Returns nonzero if an error occured
2491 (ie. an undefined instruction). */
2492static int disas_dsp_insn(CPUState *env, DisasContext *s, uint32_t insn)
2493{
2494 int acc, rd0, rd1, rdhi, rdlo;
2495
2496 if ((insn & 0x0ff00f10) == 0x0e200010) {
2497 /* Multiply with Internal Accumulate Format */
2498 rd0 = (insn >> 12) & 0xf;
2499 rd1 = insn & 0xf;
2500 acc = (insn >> 5) & 7;
2501
2502 if (acc != 0)
2503 return 1;
2504
2505 switch ((insn >> 16) & 0xf) {
2506 case 0x0: /* MIA */
b26eefb6
PB		 2507 gen_movl_T0_reg(s, rd0);
2508 gen_movl_T1_reg(s, rd1);
18c9b560
AZ		 2509 gen_op_iwmmxt_muladdsl_M0_T0_T1();
2510 break;
2511 case 0x8: /* MIAPH */
b26eefb6
PB		 2512 gen_movl_T0_reg(s, rd0);
2513 gen_movl_T1_reg(s, rd1);
18c9b560
AZ		 2514 gen_op_iwmmxt_muladdsw_M0_T0_T1();
2515 break;
2516 case 0xc: /* MIABB */
2517 case 0xd: /* MIABT */
2518 case 0xe: /* MIATB */
2519 case 0xf: /* MIATT */
b26eefb6 2520 gen_movl_T1_reg(s, rd0);
18c9b560
AZ		 2521 if (insn & (1 << 16))
2522 gen_op_shrl_T1_im(16);
2523 gen_op_movl_T0_T1();
b26eefb6 2524 gen_movl_T1_reg(s, rd1);
18c9b560
AZ		 2525 if (insn & (1 << 17))
2526 gen_op_shrl_T1_im(16);
2527 gen_op_iwmmxt_muladdswl_M0_T0_T1();
2528 break;
2529 default:
2530 return 1;
2531 }
2532
2533 gen_op_iwmmxt_movq_wRn_M0(acc);
2534 return 0;
2535 }
2536
2537 if ((insn & 0x0fe00ff8) == 0x0c400000) {
2538 /* Internal Accumulator Access Format */
2539 rdhi = (insn >> 16) & 0xf;
2540 rdlo = (insn >> 12) & 0xf;
2541 acc = insn & 7;
2542
2543 if (acc != 0)
2544 return 1;
2545
2546 if (insn & ARM_CP_RW_BIT) { /* MRA */
e677137d 2547 gen_iwmmxt_movl_T0_T1_wRn(acc);
b26eefb6 2548 gen_movl_reg_T0(s, rdlo);
18c9b560
AZ		 2549 gen_op_movl_T0_im((1 << (40 - 32)) - 1);
2550 gen_op_andl_T0_T1();
b26eefb6 2551 gen_movl_reg_T0(s, rdhi);
18c9b560 2552 } else { /* MAR */
b26eefb6
PB		 2553 gen_movl_T0_reg(s, rdlo);
2554 gen_movl_T1_reg(s, rdhi);
e677137d 2555 gen_iwmmxt_movl_wRn_T0_T1(acc);
18c9b560
AZ		 2556 }
2557 return 0;
2558 }
2559
2560 return 1;
2561}
2562
c1713132
AZ		 2563/* Disassemble system coprocessor instruction. Return nonzero if
2564 instruction is not defined. */
2565static int disas_cp_insn(CPUState *env, DisasContext *s, uint32_t insn)
2566{
8984bd2e 2567 TCGv tmp;
c1713132
AZ		 2568 uint32_t rd = (insn >> 12) & 0xf;
2569 uint32_t cp = (insn >> 8) & 0xf;
2570 if (IS_USER(s)) {
2571 return 1;
2572 }
2573
18c9b560 2574 if (insn & ARM_CP_RW_BIT) {
c1713132
AZ		 2575 if (!env->cp[cp].cp_read)
2576 return 1;
8984bd2e
PB		 2577 gen_set_pc_im(s->pc);
2578 tmp = new_tmp();
2579 gen_helper_get_cp(tmp, cpu_env, tcg_const_i32(insn));
2580 store_reg(s, rd, tmp);
c1713132
AZ		 2581 } else {
2582 if (!env->cp[cp].cp_write)
2583 return 1;
8984bd2e
PB		 2584 gen_set_pc_im(s->pc);
2585 tmp = load_reg(s, rd);
2586 gen_helper_set_cp(cpu_env, tcg_const_i32(insn), tmp);
c1713132
AZ		 2587 }
2588 return 0;
2589}
2590
9ee6e8bb
PB		 2591static int cp15_user_ok(uint32_t insn)
2592{
2593 int cpn = (insn >> 16) & 0xf;
2594 int cpm = insn & 0xf;
2595 int op = ((insn >> 5) & 7) | ((insn >> 18) & 0x38);
2596
2597 if (cpn == 13 && cpm == 0) {
2598 /* TLS register. */
2599 if (op == 2 || (op == 3 && (insn & ARM_CP_RW_BIT)))
2600 return 1;
2601 }
2602 if (cpn == 7) {
2603 /* ISB, DSB, DMB. */
2604 if ((cpm == 5 && op == 4)
2605 || (cpm == 10 && (op == 4 || op == 5)))
2606 return 1;
2607 }
2608 return 0;
2609}
2610
b5ff1b31
FB		 2611/* Disassemble system coprocessor (cp15) instruction. Return nonzero if
2612 instruction is not defined. */
a90b7318 2613static int disas_cp15_insn(CPUState *env, DisasContext *s, uint32_t insn)
b5ff1b31
FB		 2614{
2615 uint32_t rd;
8984bd2e 2616 TCGv tmp;
b5ff1b31 2617
9ee6e8bb
PB		 2618 /* M profile cores use memory mapped registers instead of cp15. */
2619 if (arm_feature(env, ARM_FEATURE_M))
2620 return 1;
2621
2622 if ((insn & (1 << 25)) == 0) {
2623 if (insn & (1 << 20)) {
2624 /* mrrc */
2625 return 1;
2626 }
2627 /* mcrr. Used for block cache operations, so implement as no-op. */
2628 return 0;
2629 }
2630 if ((insn & (1 << 4)) == 0) {
2631 /* cdp */
2632 return 1;
2633 }
2634 if (IS_USER(s) && !cp15_user_ok(insn)) {
b5ff1b31
FB		 2635 return 1;
2636 }
9332f9da
FB		 2637 if ((insn & 0x0fff0fff) == 0x0e070f90
2638 || (insn & 0x0fff0fff) == 0x0e070f58) {
2639 /* Wait for interrupt. */
8984bd2e 2640 gen_set_pc_im(s->pc);
9ee6e8bb 2641 s->is_jmp = DISAS_WFI;
9332f9da
FB		 2642 return 0;
2643 }
b5ff1b31 2644 rd = (insn >> 12) & 0xf;
18c9b560 2645 if (insn & ARM_CP_RW_BIT) {
8984bd2e
PB		 2646 tmp = new_tmp();
2647 gen_helper_get_cp15(tmp, cpu_env, tcg_const_i32(insn));
b5ff1b31
FB		 2648 /* If the destination register is r15 then sets condition codes. */
2649 if (rd != 15)
8984bd2e
PB		 2650 store_reg(s, rd, tmp);
2651 else
2652 dead_tmp(tmp);
b5ff1b31 2653 } else {
8984bd2e
PB		 2654 tmp = load_reg(s, rd);
2655 gen_helper_set_cp15(cpu_env, tcg_const_i32(insn), tmp);
2656 dead_tmp(tmp);
a90b7318
AZ		 2657 /* Normally we would always end the TB here, but Linux
2658 * arch/arm/mach-pxa/sleep.S expects two instructions following
2659 * an MMU enable to execute from cache. Imitate this behaviour. */
2660 if (!arm_feature(env, ARM_FEATURE_XSCALE) ||
2661 (insn & 0x0fff0fff) != 0x0e010f10)
2662 gen_lookup_tb(s);
b5ff1b31 2663 }
b5ff1b31
FB		 2664 return 0;
2665}
2666
9ee6e8bb
PB		 2667#define VFP_REG_SHR(x, n) (((n) > 0) ? (x) >> (n) : (x) << -(n))
2668#define VFP_SREG(insn, bigbit, smallbit) \
2669 ((VFP_REG_SHR(insn, bigbit - 1) & 0x1e) | (((insn) >> (smallbit)) & 1))
2670#define VFP_DREG(reg, insn, bigbit, smallbit) do { \
2671 if (arm_feature(env, ARM_FEATURE_VFP3)) { \
2672 reg = (((insn) >> (bigbit)) & 0x0f) \
2673 | (((insn) >> ((smallbit) - 4)) & 0x10); \
2674 } else { \
2675 if (insn & (1 << (smallbit))) \
2676 return 1; \
2677 reg = ((insn) >> (bigbit)) & 0x0f; \
2678 }} while (0)
2679
2680#define VFP_SREG_D(insn) VFP_SREG(insn, 12, 22)
2681#define VFP_DREG_D(reg, insn) VFP_DREG(reg, insn, 12, 22)
2682#define VFP_SREG_N(insn) VFP_SREG(insn, 16, 7)
2683#define VFP_DREG_N(reg, insn) VFP_DREG(reg, insn, 16, 7)
2684#define VFP_SREG_M(insn) VFP_SREG(insn, 0, 5)
2685#define VFP_DREG_M(reg, insn) VFP_DREG(reg, insn, 0, 5)
2686
4373f3ce
PB		 2687/* Move between integer and VFP cores. */
2688static TCGv gen_vfp_mrs(void)
2689{
2690 TCGv tmp = new_tmp();
2691 tcg_gen_mov_i32(tmp, cpu_F0s);
2692 return tmp;
2693}
2694
2695static void gen_vfp_msr(TCGv tmp)
2696{
2697 tcg_gen_mov_i32(cpu_F0s, tmp);
2698 dead_tmp(tmp);
2699}
2700
9ee6e8bb
PB		 2701static inline int
2702vfp_enabled(CPUState * env)
2703{
2704 return ((env->vfp.xregs[ARM_VFP_FPEXC] & (1 << 30)) != 0);
2705}
2706
ad69471c
PB		 2707static void gen_neon_dup_u8(TCGv var, int shift)
2708{
2709 TCGv tmp = new_tmp();
2710 if (shift)
2711 tcg_gen_shri_i32(var, var, shift);
2712 tcg_gen_andi_i32(var, var, 0xff);
2713 tcg_gen_shli_i32(tmp, var, 8);
2714 tcg_gen_or_i32(var, var, tmp);
2715 tcg_gen_shli_i32(tmp, var, 16);
2716 tcg_gen_or_i32(var, var, tmp);
2717 dead_tmp(tmp);
2718}
2719
2720static void gen_neon_dup_low16(TCGv var)
2721{
2722 TCGv tmp = new_tmp();
2723 tcg_gen_andi_i32(var, var, 0xffff);
2724 tcg_gen_shli_i32(tmp, var, 16);
2725 tcg_gen_or_i32(var, var, tmp);
2726 dead_tmp(tmp);
2727}
2728
2729static void gen_neon_dup_high16(TCGv var)
2730{
2731 TCGv tmp = new_tmp();
2732 tcg_gen_andi_i32(var, var, 0xffff0000);
2733 tcg_gen_shri_i32(tmp, var, 16);
2734 tcg_gen_or_i32(var, var, tmp);
2735 dead_tmp(tmp);
2736}
2737
b7bcbe95
FB		 2738/* Disassemble a VFP instruction. Returns nonzero if an error occured
2739 (ie. an undefined instruction). */
2740static int disas_vfp_insn(CPUState * env, DisasContext *s, uint32_t insn)
2741{
2742 uint32_t rd, rn, rm, op, i, n, offset, delta_d, delta_m, bank_mask;
2743 int dp, veclen;
4373f3ce 2744 TCGv tmp;
ad69471c 2745 TCGv tmp2;
b7bcbe95 2746
40f137e1
PB		 2747 if (!arm_feature(env, ARM_FEATURE_VFP))
2748 return 1;
2749
9ee6e8bb
PB		 2750 if (!vfp_enabled(env)) {
2751 /* VFP disabled. Only allow fmxr/fmrx to/from some control regs. */
40f137e1
PB		 2752 if ((insn & 0x0fe00fff) != 0x0ee00a10)
2753 return 1;
2754 rn = (insn >> 16) & 0xf;
9ee6e8bb
PB		 2755 if (rn != ARM_VFP_FPSID && rn != ARM_VFP_FPEXC
2756 && rn != ARM_VFP_MVFR1 && rn != ARM_VFP_MVFR0)
40f137e1
PB		 2757 return 1;
2758 }
b7bcbe95
FB		 2759 dp = ((insn & 0xf00) == 0xb00);
2760 switch ((insn >> 24) & 0xf) {
2761 case 0xe:
2762 if (insn & (1 << 4)) {
2763 /* single register transfer */
b7bcbe95
FB		 2764 rd = (insn >> 12) & 0xf;
2765 if (dp) {
9ee6e8bb
PB		 2766 int size;
2767 int pass;
2768
2769 VFP_DREG_N(rn, insn);
2770 if (insn & 0xf)
b7bcbe95 2771 return 1;
9ee6e8bb
PB		 2772 if (insn & 0x00c00060
2773 && !arm_feature(env, ARM_FEATURE_NEON))
2774 return 1;
2775
2776 pass = (insn >> 21) & 1;
2777 if (insn & (1 << 22)) {
2778 size = 0;
2779 offset = ((insn >> 5) & 3) * 8;
2780 } else if (insn & (1 << 5)) {
2781 size = 1;
2782 offset = (insn & (1 << 6)) ? 16 : 0;
2783 } else {
2784 size = 2;
2785 offset = 0;
2786 }
18c9b560 2787 if (insn & ARM_CP_RW_BIT) {
b7bcbe95 2788 /* vfp->arm */
ad69471c 2789 tmp = neon_load_reg(rn, pass);
9ee6e8bb
PB		 2790 switch (size) {
2791 case 0:
9ee6e8bb 2792 if (offset)
ad69471c 2793 tcg_gen_shri_i32(tmp, tmp, offset);
9ee6e8bb 2794 if (insn & (1 << 23))
ad69471c 2795 gen_uxtb(tmp);
9ee6e8bb 2796 else
ad69471c 2797 gen_sxtb(tmp);
9ee6e8bb
PB		 2798 break;
2799 case 1:
9ee6e8bb
PB		 2800 if (insn & (1 << 23)) {
2801 if (offset) {
ad69471c 2802 tcg_gen_shri_i32(tmp, tmp, 16);
9ee6e8bb 2803 } else {
ad69471c 2804 gen_uxth(tmp);
9ee6e8bb
PB		 2805 }
2806 } else {
2807 if (offset) {
ad69471c 2808 tcg_gen_sari_i32(tmp, tmp, 16);
9ee6e8bb 2809 } else {
ad69471c 2810 gen_sxth(tmp);
9ee6e8bb
PB		 2811 }
2812 }
2813 break;
2814 case 2:
9ee6e8bb
PB		 2815 break;
2816 }
ad69471c 2817 store_reg(s, rd, tmp);
b7bcbe95
FB		 2818 } else {
2819 /* arm->vfp */
ad69471c 2820 tmp = load_reg(s, rd);
9ee6e8bb
PB		 2821 if (insn & (1 << 23)) {
2822 /* VDUP */
2823 if (size == 0) {
ad69471c 2824 gen_neon_dup_u8(tmp, 0);
9ee6e8bb 2825 } else if (size == 1) {
ad69471c 2826 gen_neon_dup_low16(tmp);
9ee6e8bb 2827 }
ad69471c
PB		 2828 tmp2 = new_tmp();
2829 tcg_gen_mov_i32(tmp2, tmp);
2830 neon_store_reg(rn, 0, tmp2);
2831 neon_store_reg(rn, 0, tmp);
9ee6e8bb
PB		 2832 } else {
2833 /* VMOV */
2834 switch (size) {
2835 case 0:
ad69471c
PB		 2836 tmp2 = neon_load_reg(rn, pass);
2837 gen_bfi(tmp, tmp2, tmp, offset, 0xff);
2838 dead_tmp(tmp2);
9ee6e8bb
PB		 2839 break;
2840 case 1:
ad69471c
PB		 2841 tmp2 = neon_load_reg(rn, pass);
2842 gen_bfi(tmp, tmp2, tmp, offset, 0xffff);
2843 dead_tmp(tmp2);
9ee6e8bb
PB		 2844 break;
2845 case 2:
9ee6e8bb
PB		 2846 break;
2847 }
ad69471c 2848 neon_store_reg(rn, pass, tmp);
9ee6e8bb 2849 }
b7bcbe95 2850 }
9ee6e8bb
PB		 2851 } else { /* !dp */
2852 if ((insn & 0x6f) != 0x00)
2853 return 1;
2854 rn = VFP_SREG_N(insn);
18c9b560 2855 if (insn & ARM_CP_RW_BIT) {
b7bcbe95
FB		 2856 /* vfp->arm */
2857 if (insn & (1 << 21)) {
2858 /* system register */
40f137e1 2859 rn >>= 1;
9ee6e8bb 2860
b7bcbe95 2861 switch (rn) {
40f137e1 2862 case ARM_VFP_FPSID:
4373f3ce 2863 /* VFP2 allows access to FSID from userspace.
9ee6e8bb
PB		 2864 VFP3 restricts all id registers to privileged
2865 accesses. */
2866 if (IS_USER(s)
2867 && arm_feature(env, ARM_FEATURE_VFP3))
2868 return 1;
4373f3ce 2869 tmp = load_cpu_field(vfp.xregs[rn]);
9ee6e8bb 2870 break;
40f137e1 2871 case ARM_VFP_FPEXC:
9ee6e8bb
PB		 2872 if (IS_USER(s))
2873 return 1;
4373f3ce 2874 tmp = load_cpu_field(vfp.xregs[rn]);
9ee6e8bb 2875 break;
40f137e1
PB		 2876 case ARM_VFP_FPINST:
2877 case ARM_VFP_FPINST2:
9ee6e8bb
PB		 2878 /* Not present in VFP3. */
2879 if (IS_USER(s)
2880 || arm_feature(env, ARM_FEATURE_VFP3))
2881 return 1;
4373f3ce 2882 tmp = load_cpu_field(vfp.xregs[rn]);
b7bcbe95 2883 break;
40f137e1 2884 case ARM_VFP_FPSCR:
4373f3ce
PB		 2885 if (rd == 15) {
2886 tmp = load_cpu_field(vfp.xregs[ARM_VFP_FPSCR]);
2887 tcg_gen_andi_i32(tmp, tmp, 0xf0000000);
2888 } else {
2889 tmp = new_tmp();
2890 gen_helper_vfp_get_fpscr(tmp, cpu_env);
2891 }
b7bcbe95 2892 break;
9ee6e8bb
PB		 2893 case ARM_VFP_MVFR0:
2894 case ARM_VFP_MVFR1:
2895 if (IS_USER(s)
2896 || !arm_feature(env, ARM_FEATURE_VFP3))
2897 return 1;
4373f3ce 2898 tmp = load_cpu_field(vfp.xregs[rn]);
9ee6e8bb 2899 break;
b7bcbe95
FB		 2900 default:
2901 return 1;
2902 }
2903 } else {
2904 gen_mov_F0_vreg(0, rn);
4373f3ce 2905 tmp = gen_vfp_mrs();
b7bcbe95
FB		 2906 }
2907 if (rd == 15) {
b5ff1b31 2908 /* Set the 4 flag bits in the CPSR. */
4373f3ce
PB		 2909 gen_set_nzcv(tmp);
2910 dead_tmp(tmp);
2911 } else {
2912 store_reg(s, rd, tmp);
2913 }
b7bcbe95
FB		 2914 } else {
2915 /* arm->vfp */
4373f3ce 2916 tmp = load_reg(s, rd);
b7bcbe95 2917 if (insn & (1 << 21)) {
40f137e1 2918 rn >>= 1;
b7bcbe95
FB		 2919 /* system register */
2920 switch (rn) {
40f137e1 2921 case ARM_VFP_FPSID:
9ee6e8bb
PB		 2922 case ARM_VFP_MVFR0:
2923 case ARM_VFP_MVFR1:
b7bcbe95
FB		 2924 /* Writes are ignored. */
2925 break;
40f137e1 2926 case ARM_VFP_FPSCR:
4373f3ce
PB		 2927 gen_helper_vfp_set_fpscr(cpu_env, tmp);
2928 dead_tmp(tmp);
b5ff1b31 2929 gen_lookup_tb(s);
b7bcbe95 2930 break;
40f137e1 2931 case ARM_VFP_FPEXC:
9ee6e8bb
PB		 2932 if (IS_USER(s))
2933 return 1;
4373f3ce 2934 store_cpu_field(tmp, vfp.xregs[rn]);
40f137e1
PB		 2935 gen_lookup_tb(s);
2936 break;
2937 case ARM_VFP_FPINST:
2938 case ARM_VFP_FPINST2:
4373f3ce 2939 store_cpu_field(tmp, vfp.xregs[rn]);
40f137e1 2940 break;
b7bcbe95
FB		 2941 default:
2942 return 1;
2943 }
2944 } else {
4373f3ce 2945 gen_vfp_msr(tmp);
b7bcbe95
FB		 2946 gen_mov_vreg_F0(0, rn);
2947 }
2948 }
2949 }
2950 } else {
2951 /* data processing */
2952 /* The opcode is in bits 23, 21, 20 and 6. */
2953 op = ((insn >> 20) & 8) | ((insn >> 19) & 6) | ((insn >> 6) & 1);
2954 if (dp) {
2955 if (op == 15) {
2956 /* rn is opcode */
2957 rn = ((insn >> 15) & 0x1e) | ((insn >> 7) & 1);
2958 } else {
2959 /* rn is register number */
9ee6e8bb 2960 VFP_DREG_N(rn, insn);
b7bcbe95
FB		 2961 }
2962
2963 if (op == 15 && (rn == 15 || rn > 17)) {
2964 /* Integer or single precision destination. */
9ee6e8bb 2965 rd = VFP_SREG_D(insn);
b7bcbe95 2966 } else {
9ee6e8bb 2967 VFP_DREG_D(rd, insn);
b7bcbe95
FB		 2968 }
2969
2970 if (op == 15 && (rn == 16 || rn == 17)) {
2971 /* Integer source. */
2972 rm = ((insn << 1) & 0x1e) | ((insn >> 5) & 1);
2973 } else {
9ee6e8bb 2974 VFP_DREG_M(rm, insn);
b7bcbe95
FB		 2975 }
2976 } else {
9ee6e8bb 2977 rn = VFP_SREG_N(insn);
b7bcbe95
FB		 2978 if (op == 15 && rn == 15) {
2979 /* Double precision destination. */
9ee6e8bb
PB		 2980 VFP_DREG_D(rd, insn);
2981 } else {
2982 rd = VFP_SREG_D(insn);
2983 }
2984 rm = VFP_SREG_M(insn);
b7bcbe95
FB		 2985 }
2986
2987 veclen = env->vfp.vec_len;
2988 if (op == 15 && rn > 3)
2989 veclen = 0;
2990
2991 /* Shut up compiler warnings. */
2992 delta_m = 0;
2993 delta_d = 0;
2994 bank_mask = 0;
3b46e624 2995
b7bcbe95
FB		 2996 if (veclen > 0) {
2997 if (dp)
2998 bank_mask = 0xc;
2999 else
3000 bank_mask = 0x18;
3001
3002 /* Figure out what type of vector operation this is. */
3003 if ((rd & bank_mask) == 0) {
3004 /* scalar */
3005 veclen = 0;
3006 } else {
3007 if (dp)
3008 delta_d = (env->vfp.vec_stride >> 1) + 1;
3009 else
3010 delta_d = env->vfp.vec_stride + 1;
3011
3012 if ((rm & bank_mask) == 0) {
3013 /* mixed scalar/vector */
3014 delta_m = 0;
3015 } else {
3016 /* vector */
3017 delta_m = delta_d;
3018 }
3019 }
3020 }
3021
3022 /* Load the initial operands. */
3023 if (op == 15) {
3024 switch (rn) {
3025 case 16:
3026 case 17:
3027 /* Integer source */
3028 gen_mov_F0_vreg(0, rm);
3029 break;
3030 case 8:
3031 case 9:
3032 /* Compare */
3033 gen_mov_F0_vreg(dp, rd);
3034 gen_mov_F1_vreg(dp, rm);
3035 break;
3036 case 10:
3037 case 11:
3038 /* Compare with zero */
3039 gen_mov_F0_vreg(dp, rd);
3040 gen_vfp_F1_ld0(dp);
3041 break;
9ee6e8bb
PB		 3042 case 20:
3043 case 21:
3044 case 22:
3045 case 23:
3046 /* Source and destination the same. */
3047 gen_mov_F0_vreg(dp, rd);
3048 break;
b7bcbe95
FB		 3049 default:
3050 /* One source operand. */
3051 gen_mov_F0_vreg(dp, rm);
9ee6e8bb 3052 break;
b7bcbe95
FB		 3053 }
3054 } else {
3055 /* Two source operands. */
3056 gen_mov_F0_vreg(dp, rn);
3057 gen_mov_F1_vreg(dp, rm);
3058 }
3059
3060 for (;;) {
3061 /* Perform the calculation. */
3062 switch (op) {
3063 case 0: /* mac: fd + (fn * fm) */
3064 gen_vfp_mul(dp);
3065 gen_mov_F1_vreg(dp, rd);
3066 gen_vfp_add(dp);
3067 break;
3068 case 1: /* nmac: fd - (fn * fm) */
3069 gen_vfp_mul(dp);
3070 gen_vfp_neg(dp);
3071 gen_mov_F1_vreg(dp, rd);
3072 gen_vfp_add(dp);
3073 break;
3074 case 2: /* msc: -fd + (fn * fm) */
3075 gen_vfp_mul(dp);
3076 gen_mov_F1_vreg(dp, rd);
3077 gen_vfp_sub(dp);
3078 break;
3079 case 3: /* nmsc: -fd - (fn * fm) */
3080 gen_vfp_mul(dp);
3081 gen_mov_F1_vreg(dp, rd);
3082 gen_vfp_add(dp);
3083 gen_vfp_neg(dp);
3084 break;
3085 case 4: /* mul: fn * fm */
3086 gen_vfp_mul(dp);
3087 break;
3088 case 5: /* nmul: -(fn * fm) */
3089 gen_vfp_mul(dp);
3090 gen_vfp_neg(dp);
3091 break;
3092 case 6: /* add: fn + fm */
3093 gen_vfp_add(dp);
3094 break;
3095 case 7: /* sub: fn - fm */
3096 gen_vfp_sub(dp);
3097 break;
3098 case 8: /* div: fn / fm */
3099 gen_vfp_div(dp);
3100 break;
9ee6e8bb
PB		 3101 case 14: /* fconst */
3102 if (!arm_feature(env, ARM_FEATURE_VFP3))
3103 return 1;
3104
3105 n = (insn << 12) & 0x80000000;
3106 i = ((insn >> 12) & 0x70) | (insn & 0xf);
3107 if (dp) {
3108 if (i & 0x40)
3109 i |= 0x3f80;
3110 else
3111 i |= 0x4000;
3112 n |= i << 16;
4373f3ce 3113 tcg_gen_movi_i64(cpu_F0d, ((uint64_t)n) << 32);
9ee6e8bb
PB		 3114 } else {
3115 if (i & 0x40)
3116 i |= 0x780;
3117 else
3118 i |= 0x800;
3119 n |= i << 19;
4373f3ce 3120 tcg_gen_movi_i32(cpu_F0d, ((uint64_t)n) << 32);
9ee6e8bb 3121 }
9ee6e8bb 3122 break;
b7bcbe95
FB		 3123 case 15: /* extension space */
3124 switch (rn) {
3125 case 0: /* cpy */
3126 /* no-op */
3127 break;
3128 case 1: /* abs */
3129 gen_vfp_abs(dp);
3130 break;
3131 case 2: /* neg */
3132 gen_vfp_neg(dp);
3133 break;
3134 case 3: /* sqrt */
3135 gen_vfp_sqrt(dp);
3136 break;
3137 case 8: /* cmp */
3138 gen_vfp_cmp(dp);
3139 break;
3140 case 9: /* cmpe */
3141 gen_vfp_cmpe(dp);
3142 break;
3143 case 10: /* cmpz */
3144 gen_vfp_cmp(dp);
3145 break;
3146 case 11: /* cmpez */
3147 gen_vfp_F1_ld0(dp);
3148 gen_vfp_cmpe(dp);
3149 break;
3150 case 15: /* single<->double conversion */
3151 if (dp)
4373f3ce 3152 gen_helper_vfp_fcvtsd(cpu_F0s, cpu_F0d, cpu_env);
b7bcbe95 3153 else
4373f3ce 3154 gen_helper_vfp_fcvtds(cpu_F0d, cpu_F0s, cpu_env);
b7bcbe95
FB		 3155 break;
3156 case 16: /* fuito */
3157 gen_vfp_uito(dp);
3158 break;
3159 case 17: /* fsito */
3160 gen_vfp_sito(dp);
3161 break;
9ee6e8bb
PB		 3162 case 20: /* fshto */
3163 if (!arm_feature(env, ARM_FEATURE_VFP3))
3164 return 1;
3165 gen_vfp_shto(dp, rm);
3166 break;
3167 case 21: /* fslto */
3168 if (!arm_feature(env, ARM_FEATURE_VFP3))
3169 return 1;
3170 gen_vfp_slto(dp, rm);
3171 break;
3172 case 22: /* fuhto */
3173 if (!arm_feature(env, ARM_FEATURE_VFP3))
3174 return 1;
3175 gen_vfp_uhto(dp, rm);
3176 break;
3177 case 23: /* fulto */
3178 if (!arm_feature(env, ARM_FEATURE_VFP3))
3179 return 1;
3180 gen_vfp_ulto(dp, rm);
3181 break;
b7bcbe95
FB		 3182 case 24: /* ftoui */
3183 gen_vfp_toui(dp);
3184 break;
3185 case 25: /* ftouiz */
3186 gen_vfp_touiz(dp);
3187 break;
3188 case 26: /* ftosi */
3189 gen_vfp_tosi(dp);
3190 break;
3191 case 27: /* ftosiz */
3192 gen_vfp_tosiz(dp);
3193 break;
9ee6e8bb
PB		 3194 case 28: /* ftosh */
3195 if (!arm_feature(env, ARM_FEATURE_VFP3))
3196 return 1;
3197 gen_vfp_tosh(dp, rm);
3198 break;
3199 case 29: /* ftosl */
3200 if (!arm_feature(env, ARM_FEATURE_VFP3))
3201 return 1;
3202 gen_vfp_tosl(dp, rm);
3203 break;
3204 case 30: /* ftouh */
3205 if (!arm_feature(env, ARM_FEATURE_VFP3))
3206 return 1;
3207 gen_vfp_touh(dp, rm);
3208 break;
3209 case 31: /* ftoul */
3210 if (!arm_feature(env, ARM_FEATURE_VFP3))
3211 return 1;
3212 gen_vfp_toul(dp, rm);
3213 break;
b7bcbe95
FB		 3214 default: /* undefined */
3215 printf ("rn:%d\n", rn);
3216 return 1;
3217 }
3218 break;
3219 default: /* undefined */
3220 printf ("op:%d\n", op);
3221 return 1;
3222 }
3223
3224 /* Write back the result. */
3225 if (op == 15 && (rn >= 8 && rn <= 11))
3226 ; /* Comparison, do nothing. */
3227 else if (op == 15 && rn > 17)
3228 /* Integer result. */
3229 gen_mov_vreg_F0(0, rd);
3230 else if (op == 15 && rn == 15)
3231 /* conversion */
3232 gen_mov_vreg_F0(!dp, rd);
3233 else
3234 gen_mov_vreg_F0(dp, rd);
3235
3236 /* break out of the loop if we have finished */
3237 if (veclen == 0)
3238 break;
3239
3240 if (op == 15 && delta_m == 0) {
3241 /* single source one-many */
3242 while (veclen--) {
3243 rd = ((rd + delta_d) & (bank_mask - 1))
3244 | (rd & bank_mask);
3245 gen_mov_vreg_F0(dp, rd);
3246 }
3247 break;
3248 }
3249 /* Setup the next operands. */
3250 veclen--;
3251 rd = ((rd + delta_d) & (bank_mask - 1))
3252 | (rd & bank_mask);
3253
3254 if (op == 15) {
3255 /* One source operand. */
3256 rm = ((rm + delta_m) & (bank_mask - 1))
3257 | (rm & bank_mask);
3258 gen_mov_F0_vreg(dp, rm);
3259 } else {
3260 /* Two source operands. */
3261 rn = ((rn + delta_d) & (bank_mask - 1))
3262 | (rn & bank_mask);
3263 gen_mov_F0_vreg(dp, rn);
3264 if (delta_m) {
3265 rm = ((rm + delta_m) & (bank_mask - 1))
3266 | (rm & bank_mask);
3267 gen_mov_F1_vreg(dp, rm);
3268 }
3269 }
3270 }
3271 }
3272 break;
3273 case 0xc:
3274 case 0xd:
9ee6e8bb 3275 if (dp && (insn & 0x03e00000) == 0x00400000) {
b7bcbe95
FB		 3276 /* two-register transfer */
3277 rn = (insn >> 16) & 0xf;
3278 rd = (insn >> 12) & 0xf;
3279 if (dp) {
9ee6e8bb
PB		 3280 VFP_DREG_M(rm, insn);
3281 } else {
3282 rm = VFP_SREG_M(insn);
3283 }
b7bcbe95 3284
18c9b560 3285 if (insn & ARM_CP_RW_BIT) {
b7bcbe95
FB		 3286 /* vfp->arm */
3287 if (dp) {
4373f3ce
PB		 3288 gen_mov_F0_vreg(0, rm * 2);
3289 tmp = gen_vfp_mrs();
3290 store_reg(s, rd, tmp);
3291 gen_mov_F0_vreg(0, rm * 2 + 1);
3292 tmp = gen_vfp_mrs();
3293 store_reg(s, rn, tmp);
b7bcbe95
FB		 3294 } else {
3295 gen_mov_F0_vreg(0, rm);
4373f3ce
PB		 3296 tmp = gen_vfp_mrs();
3297 store_reg(s, rn, tmp);
b7bcbe95 3298 gen_mov_F0_vreg(0, rm + 1);
4373f3ce
PB		 3299 tmp = gen_vfp_mrs();
3300 store_reg(s, rd, tmp);
b7bcbe95
FB		 3301 }
3302 } else {
3303 /* arm->vfp */
3304 if (dp) {
4373f3ce
PB		 3305 tmp = load_reg(s, rd);
3306 gen_vfp_msr(tmp);
3307 gen_mov_vreg_F0(0, rm * 2);
3308 tmp = load_reg(s, rn);
3309 gen_vfp_msr(tmp);
3310 gen_mov_vreg_F0(0, rm * 2 + 1);
b7bcbe95 3311 } else {
4373f3ce
PB		 3312 tmp = load_reg(s, rn);
3313 gen_vfp_msr(tmp);
b7bcbe95 3314 gen_mov_vreg_F0(0, rm);
4373f3ce
PB		 3315 tmp = load_reg(s, rd);
3316 gen_vfp_msr(tmp);
b7bcbe95
FB		 3317 gen_mov_vreg_F0(0, rm + 1);
3318 }
3319 }
3320 } else {
3321 /* Load/store */
3322 rn = (insn >> 16) & 0xf;
3323 if (dp)
9ee6e8bb 3324 VFP_DREG_D(rd, insn);
b7bcbe95 3325 else
9ee6e8bb
PB		 3326 rd = VFP_SREG_D(insn);
3327 if (s->thumb && rn == 15) {
3328 gen_op_movl_T1_im(s->pc & ~2);
3329 } else {
3330 gen_movl_T1_reg(s, rn);
3331 }
b7bcbe95
FB		 3332 if ((insn & 0x01200000) == 0x01000000) {
3333 /* Single load/store */
3334 offset = (insn & 0xff) << 2;
3335 if ((insn & (1 << 23)) == 0)
3336 offset = -offset;
3337 gen_op_addl_T1_im(offset);
3338 if (insn & (1 << 20)) {
b5ff1b31 3339 gen_vfp_ld(s, dp);
b7bcbe95
FB		 3340 gen_mov_vreg_F0(dp, rd);
3341 } else {
3342 gen_mov_F0_vreg(dp, rd);
b5ff1b31 3343 gen_vfp_st(s, dp);
b7bcbe95
FB		 3344 }
3345 } else {
3346 /* load/store multiple */
3347 if (dp)
3348 n = (insn >> 1) & 0x7f;
3349 else
3350 n = insn & 0xff;
3351
3352 if (insn & (1 << 24)) /* pre-decrement */
3353 gen_op_addl_T1_im(-((insn & 0xff) << 2));
3354
3355 if (dp)
3356 offset = 8;
3357 else
3358 offset = 4;
3359 for (i = 0; i < n; i++) {
18c9b560 3360 if (insn & ARM_CP_RW_BIT) {
b7bcbe95 3361 /* load */
b5ff1b31 3362 gen_vfp_ld(s, dp);
b7bcbe95
FB		 3363 gen_mov_vreg_F0(dp, rd + i);
3364 } else {
3365 /* store */
3366 gen_mov_F0_vreg(dp, rd + i);
b5ff1b31 3367 gen_vfp_st(s, dp);
b7bcbe95
FB		 3368 }
3369 gen_op_addl_T1_im(offset);
3370 }
3371 if (insn & (1 << 21)) {
3372 /* writeback */
3373 if (insn & (1 << 24))
3374 offset = -offset * n;
3375 else if (dp && (insn & 1))
3376 offset = 4;
3377 else
3378 offset = 0;
3379
3380 if (offset != 0)
3381 gen_op_addl_T1_im(offset);
3382 gen_movl_reg_T1(s, rn);
3383 }
3384 }
3385 }
3386 break;
3387 default:
3388 /* Should never happen. */
3389 return 1;
3390 }
3391 return 0;
3392}
3393
6e256c93 3394static inline void gen_goto_tb(DisasContext *s, int n, uint32_t dest)
c53be334 3395{
6e256c93
FB		 3396 TranslationBlock *tb;
3397
3398 tb = s->tb;
3399 if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK)) {
57fec1fe 3400 tcg_gen_goto_tb(n);
8984bd2e 3401 gen_set_pc_im(dest);
57fec1fe 3402 tcg_gen_exit_tb((long)tb + n);
6e256c93 3403 } else {
8984bd2e 3404 gen_set_pc_im(dest);
57fec1fe 3405 tcg_gen_exit_tb(0);
6e256c93 3406 }
c53be334
FB		 3407}
3408
8aaca4c0
FB		 3409static inline void gen_jmp (DisasContext *s, uint32_t dest)
3410{
3411 if (__builtin_expect(s->singlestep_enabled, 0)) {
3412 /* An indirect jump so that we still trigger the debug exception. */
5899f386 3413 if (s->thumb)
d9ba4830
PB		 3414 dest |= 1;
3415 gen_bx_im(s, dest);
8aaca4c0 3416 } else {
6e256c93 3417 gen_goto_tb(s, 0, dest);
8aaca4c0
FB		 3418 s->is_jmp = DISAS_TB_JUMP;
3419 }
3420}
3421
d9ba4830 3422static inline void gen_mulxy(TCGv t0, TCGv t1, int x, int y)
b5ff1b31 3423{
ee097184 3424 if (x)
d9ba4830 3425 tcg_gen_sari_i32(t0, t0, 16);
b5ff1b31 3426 else
d9ba4830 3427 gen_sxth(t0);
ee097184 3428 if (y)
d9ba4830 3429 tcg_gen_sari_i32(t1, t1, 16);
b5ff1b31 3430 else
d9ba4830
PB		 3431 gen_sxth(t1);
3432 tcg_gen_mul_i32(t0, t0, t1);
b5ff1b31
FB		 3433}
3434
3435/* Return the mask of PSR bits set by a MSR instruction. */
9ee6e8bb 3436static uint32_t msr_mask(CPUState *env, DisasContext *s, int flags, int spsr) {
b5ff1b31
FB		 3437 uint32_t mask;
3438
3439 mask = 0;
3440 if (flags & (1 << 0))
3441 mask |= 0xff;
3442 if (flags & (1 << 1))
3443 mask |= 0xff00;
3444 if (flags & (1 << 2))
3445 mask |= 0xff0000;
3446 if (flags & (1 << 3))
3447 mask |= 0xff000000;
9ee6e8bb 3448
2ae23e75 3449 /* Mask out undefined bits. */
9ee6e8bb
PB		 3450 mask &= ~CPSR_RESERVED;
3451 if (!arm_feature(env, ARM_FEATURE_V6))
e160c51c 3452 mask &= ~(CPSR_E | CPSR_GE);
9ee6e8bb 3453 if (!arm_feature(env, ARM_FEATURE_THUMB2))
e160c51c 3454 mask &= ~CPSR_IT;
9ee6e8bb 3455 /* Mask out execution state bits. */
2ae23e75 3456 if (!spsr)
e160c51c 3457 mask &= ~CPSR_EXEC;
b5ff1b31
FB		 3458 /* Mask out privileged bits. */
3459 if (IS_USER(s))
9ee6e8bb 3460 mask &= CPSR_USER;
b5ff1b31
FB		 3461 return mask;
3462}
3463
3464/* Returns nonzero if access to the PSR is not permitted. */
3465static int gen_set_psr_T0(DisasContext *s, uint32_t mask, int spsr)
3466{
d9ba4830 3467 TCGv tmp;
b5ff1b31
FB		 3468 if (spsr) {
3469 /* ??? This is also undefined in system mode. */
3470 if (IS_USER(s))
3471 return 1;
d9ba4830
PB		 3472
3473 tmp = load_cpu_field(spsr);
3474 tcg_gen_andi_i32(tmp, tmp, ~mask);
3475 tcg_gen_andi_i32(cpu_T[0], cpu_T[0], mask);
3476 tcg_gen_or_i32(tmp, tmp, cpu_T[0]);
3477 store_cpu_field(tmp, spsr);
b5ff1b31 3478 } else {
d9ba4830 3479 gen_set_cpsr(cpu_T[0], mask);
b5ff1b31
FB		 3480 }
3481 gen_lookup_tb(s);
3482 return 0;
3483}
3484
9ee6e8bb 3485/* Generate an old-style exception return. */
b5ff1b31
FB		 3486static void gen_exception_return(DisasContext *s)
3487{
d9ba4830 3488 TCGv tmp;
b26eefb6 3489 gen_set_pc_T0();
d9ba4830
PB		 3490 tmp = load_cpu_field(spsr);
3491 gen_set_cpsr(tmp, 0xffffffff);
3492 dead_tmp(tmp);
b5ff1b31
FB		 3493 s->is_jmp = DISAS_UPDATE;
3494}
3495
b0109805
PB		 3496/* Generate a v6 exception return. Marks both values as dead. */
3497static void gen_rfe(DisasContext *s, TCGv pc, TCGv cpsr)
2c0262af 3498{
b0109805
PB		 3499 gen_set_cpsr(cpsr, 0xffffffff);
3500 dead_tmp(cpsr);
3501 store_reg(s, 15, pc);
9ee6e8bb
PB		 3502 s->is_jmp = DISAS_UPDATE;
3503}
3b46e624 3504
9ee6e8bb
PB		 3505static inline void
3506gen_set_condexec (DisasContext *s)
3507{
3508 if (s->condexec_mask) {
8f01245e
PB		 3509 uint32_t val = (s->condexec_cond << 4) | (s->condexec_mask >> 1);
3510 TCGv tmp = new_tmp();
3511 tcg_gen_movi_i32(tmp, val);
d9ba4830 3512 store_cpu_field(tmp, condexec_bits);
9ee6e8bb
PB		 3513 }
3514}
3b46e624 3515
9ee6e8bb
PB		 3516static void gen_nop_hint(DisasContext *s, int val)
3517{
3518 switch (val) {
3519 case 3: /* wfi */
8984bd2e 3520 gen_set_pc_im(s->pc);
9ee6e8bb
PB		 3521 s->is_jmp = DISAS_WFI;
3522 break;
3523 case 2: /* wfe */
3524 case 4: /* sev */
3525 /* TODO: Implement SEV and WFE. May help SMP performance. */
3526 default: /* nop */
3527 break;
3528 }
3529}
99c475ab 3530
ad69471c
PB		 3531/* These macros help make the code more readable when migrating from the
3532 old dyngen helpers. They should probably be removed when
3533 T0/T1 are removed. */
3534#define CPU_T001 cpu_T[0], cpu_T[0], cpu_T[1]
3535#define CPU_T0E01 cpu_T[0], cpu_env, cpu_T[0], cpu_T[1]
9ee6e8bb 3536
ad69471c 3537#define CPU_V001 cpu_V0, cpu_V0, cpu_V1
9ee6e8bb
PB		 3538
3539static inline int gen_neon_add(int size)
3540{
3541 switch (size) {
ad69471c
PB		 3542 case 0: gen_helper_neon_add_u8(CPU_T001); break;
3543 case 1: gen_helper_neon_add_u16(CPU_T001); break;
9ee6e8bb
PB		 3544 case 2: gen_op_addl_T0_T1(); break;
3545 default: return 1;
3546 }
3547 return 0;
3548}
3549
ad69471c
PB		 3550static inline void gen_neon_rsb(int size)
3551{
3552 switch (size) {
3553 case 0: gen_helper_neon_sub_u8(cpu_T[0], cpu_T[1], cpu_T[0]); break;
3554 case 1: gen_helper_neon_sub_u16(cpu_T[0], cpu_T[1], cpu_T[0]); break;
3555 case 2: gen_op_rsbl_T0_T1(); break;
3556 default: return;
3557 }
3558}
3559
3560/* 32-bit pairwise ops end up the same as the elementwise versions. */
3561#define gen_helper_neon_pmax_s32 gen_helper_neon_max_s32
3562#define gen_helper_neon_pmax_u32 gen_helper_neon_max_u32
3563#define gen_helper_neon_pmin_s32 gen_helper_neon_min_s32
3564#define gen_helper_neon_pmin_u32 gen_helper_neon_min_u32
3565
3566/* FIXME: This is wrong. They set the wrong overflow bit. */
3567#define gen_helper_neon_qadd_s32(a, e, b, c) gen_helper_add_saturate(a, b, c)
3568#define gen_helper_neon_qadd_u32(a, e, b, c) gen_helper_add_usaturate(a, b, c)
3569#define gen_helper_neon_qsub_s32(a, e, b, c) gen_helper_sub_saturate(a, b, c)
3570#define gen_helper_neon_qsub_u32(a, e, b, c) gen_helper_sub_usaturate(a, b, c)
3571
3572#define GEN_NEON_INTEGER_OP_ENV(name) do { \
3573 switch ((size << 1) | u) { \
3574 case 0: \
3575 gen_helper_neon_##name##_s8(cpu_T[0], cpu_env, cpu_T[0], cpu_T[1]); \
3576 break; \
3577 case 1: \
3578 gen_helper_neon_##name##_u8(cpu_T[0], cpu_env, cpu_T[0], cpu_T[1]); \
3579 break; \
3580 case 2: \
3581 gen_helper_neon_##name##_s16(cpu_T[0], cpu_env, cpu_T[0], cpu_T[1]); \
3582 break; \
3583 case 3: \
3584 gen_helper_neon_##name##_u16(cpu_T[0], cpu_env, cpu_T[0], cpu_T[1]); \
3585 break; \
3586 case 4: \
3587 gen_helper_neon_##name##_s32(cpu_T[0], cpu_env, cpu_T[0], cpu_T[1]); \
3588 break; \
3589 case 5: \
3590 gen_helper_neon_##name##_u32(cpu_T[0], cpu_env, cpu_T[0], cpu_T[1]); \
3591 break; \
3592 default: return 1; \
3593 }} while (0)
9ee6e8bb
PB		 3594
3595#define GEN_NEON_INTEGER_OP(name) do { \
3596 switch ((size << 1) | u) { \
ad69471c
PB		 3597 case 0: \
3598 gen_helper_neon_##name##_s8(cpu_T[0], cpu_T[0], cpu_T[1]); \
3599 break; \
3600 case 1: \
3601 gen_helper_neon_##name##_u8(cpu_T[0], cpu_T[0], cpu_T[1]); \
3602 break; \
3603 case 2: \
3604 gen_helper_neon_##name##_s16(cpu_T[0], cpu_T[0], cpu_T[1]); \
3605 break; \
3606 case 3: \
3607 gen_helper_neon_##name##_u16(cpu_T[0], cpu_T[0], cpu_T[1]); \
3608 break; \
3609 case 4: \
3610 gen_helper_neon_##name##_s32(cpu_T[0], cpu_T[0], cpu_T[1]); \
3611 break; \
3612 case 5: \
3613 gen_helper_neon_##name##_u32(cpu_T[0], cpu_T[0], cpu_T[1]); \
3614 break; \
9ee6e8bb
PB		 3615 default: return 1; \
3616 }} while (0)
3617
3618static inline void
3619gen_neon_movl_scratch_T0(int scratch)
3620{
3621 uint32_t offset;
3622
3623 offset = offsetof(CPUARMState, vfp.scratch[scratch]);
ad69471c 3624 tcg_gen_st_i32(cpu_T[0], cpu_env, offset);
9ee6e8bb
PB		 3625}
3626
3627static inline void
3628gen_neon_movl_scratch_T1(int scratch)
3629{
3630 uint32_t offset;
3631
3632 offset = offsetof(CPUARMState, vfp.scratch[scratch]);
ad69471c 3633 tcg_gen_st_i32(cpu_T[1], cpu_env, offset);
9ee6e8bb
PB		 3634}
3635
3636static inline void
3637gen_neon_movl_T0_scratch(int scratch)
3638{
3639 uint32_t offset;
3640
3641 offset = offsetof(CPUARMState, vfp.scratch[scratch]);
ad69471c 3642 tcg_gen_ld_i32(cpu_T[0], cpu_env, offset);
9ee6e8bb
PB		 3643}
3644
3645static inline void
3646gen_neon_movl_T1_scratch(int scratch)
3647{
3648 uint32_t offset;
3649
3650 offset = offsetof(CPUARMState, vfp.scratch[scratch]);
ad69471c 3651 tcg_gen_ld_i32(cpu_T[1], cpu_env, offset);
9ee6e8bb
PB		 3652}
3653
3654static inline void gen_neon_get_scalar(int size, int reg)
3655{
3656 if (size == 1) {
3657 NEON_GET_REG(T0, reg >> 1, reg & 1);
3658 } else {
3659 NEON_GET_REG(T0, reg >> 2, (reg >> 1) & 1);
3660 if (reg & 1)
ad69471c 3661 gen_neon_dup_low16(cpu_T[0]);
9ee6e8bb 3662 else
ad69471c 3663 gen_neon_dup_high16(cpu_T[0]);
9ee6e8bb
PB		 3664 }
3665}
3666
3667static void gen_neon_unzip(int reg, int q, int tmp, int size)
3668{
3669 int n;
3670
3671 for (n = 0; n < q + 1; n += 2) {
3672 NEON_GET_REG(T0, reg, n);
3673 NEON_GET_REG(T0, reg, n + n);
3674 switch (size) {
ad69471c
PB		 3675 case 0: gen_helper_neon_unzip_u8(); break;
3676 case 1: gen_helper_neon_zip_u16(); break; /* zip and unzip are the same. */
9ee6e8bb
PB		 3677 case 2: /* no-op */; break;
3678 default: abort();
3679 }
3680 gen_neon_movl_scratch_T0(tmp + n);
3681 gen_neon_movl_scratch_T1(tmp + n + 1);
3682 }
3683}
3684
3685static struct {
3686 int nregs;
3687 int interleave;
3688 int spacing;
3689} neon_ls_element_type[11] = {
3690 {4, 4, 1},
3691 {4, 4, 2},
3692 {4, 1, 1},
3693 {4, 2, 1},
3694 {3, 3, 1},
3695 {3, 3, 2},
3696 {3, 1, 1},
3697 {1, 1, 1},
3698 {2, 2, 1},
3699 {2, 2, 2},
3700 {2, 1, 1}
3701};
3702
3703/* Translate a NEON load/store element instruction. Return nonzero if the
3704 instruction is invalid. */
3705static int disas_neon_ls_insn(CPUState * env, DisasContext *s, uint32_t insn)
3706{
3707 int rd, rn, rm;
3708 int op;
3709 int nregs;
3710 int interleave;
3711 int stride;
3712 int size;
3713 int reg;
3714 int pass;
3715 int load;
3716 int shift;
9ee6e8bb 3717 int n;
b0109805 3718 TCGv tmp;
8f8e3aa4 3719 TCGv tmp2;
9ee6e8bb
PB		 3720
3721 if (!vfp_enabled(env))
3722 return 1;
3723 VFP_DREG_D(rd, insn);
3724 rn = (insn >> 16) & 0xf;
3725 rm = insn & 0xf;
3726 load = (insn & (1 << 21)) != 0;
3727 if ((insn & (1 << 23)) == 0) {
3728 /* Load store all elements. */
3729 op = (insn >> 8) & 0xf;
3730 size = (insn >> 6) & 3;
3731 if (op > 10 || size == 3)
3732 return 1;
3733 nregs = neon_ls_element_type[op].nregs;
3734 interleave = neon_ls_element_type[op].interleave;
3735 gen_movl_T1_reg(s, rn);
3736 stride = (1 << size) * interleave;
3737 for (reg = 0; reg < nregs; reg++) {
3738 if (interleave > 2 || (interleave == 2 && nregs == 2)) {
3739 gen_movl_T1_reg(s, rn);
3740 gen_op_addl_T1_im((1 << size) * reg);
3741 } else if (interleave == 2 && nregs == 4 && reg == 2) {
3742 gen_movl_T1_reg(s, rn);
3743 gen_op_addl_T1_im(1 << size);
3744 }
3745 for (pass = 0; pass < 2; pass++) {
3746 if (size == 2) {
3747 if (load) {
b0109805 3748 tmp = gen_ld32(cpu_T[1], IS_USER(s));
ad69471c 3749 neon_store_reg(rd, pass, tmp);
9ee6e8bb 3750 } else {
ad69471c 3751 tmp = neon_load_reg(rd, pass);
b0109805 3752 gen_st32(tmp, cpu_T[1], IS_USER(s));
9ee6e8bb
PB		 3753 }
3754 gen_op_addl_T1_im(stride);
3755 } else if (size == 1) {
3756 if (load) {
b0109805 3757 tmp = gen_ld16u(cpu_T[1], IS_USER(s));
9ee6e8bb 3758 gen_op_addl_T1_im(stride);
8f8e3aa4 3759 tmp2 = gen_ld16u(cpu_T[1], IS_USER(s));
9ee6e8bb 3760 gen_op_addl_T1_im(stride);
8f8e3aa4
PB		 3761 gen_bfi(tmp, tmp, tmp2, 16, 0xffff);
3762 dead_tmp(tmp2);
3763 neon_store_reg(rd, pass, tmp);
9ee6e8bb 3764 } else {
8f8e3aa4
PB		 3765 tmp = neon_load_reg(rd, pass);
3766 tmp2 = new_tmp();
3767 tcg_gen_shri_i32(tmp2, tmp, 16);
b0109805 3768 gen_st16(tmp, cpu_T[1], IS_USER(s));
9ee6e8bb 3769 gen_op_addl_T1_im(stride);
8f8e3aa4 3770 gen_st16(tmp2, cpu_T[1], IS_USER(s));
9ee6e8bb
PB		 3771 gen_op_addl_T1_im(stride);
3772 }
3773 } else /* size == 0 */ {
3774 if (load) {
9ee6e8bb 3775 for (n = 0; n < 4; n++) {
b0109805 3776 tmp = gen_ld8u(cpu_T[1], IS_USER(s));
9ee6e8bb
PB		 3777 gen_op_addl_T1_im(stride);
3778 if (n == 0) {
8f8e3aa4 3779 tmp2 = tmp;
9ee6e8bb 3780 } else {
8f8e3aa4
PB		 3781 gen_bfi(tmp2, tmp2, tmp, n * 8, 0xff);
3782 dead_tmp(tmp);
9ee6e8bb 3783 }
9ee6e8bb 3784 }
8f8e3aa4 3785 neon_store_reg(rd, pass, tmp2);
9ee6e8bb 3786 } else {
8f8e3aa4 3787 tmp2 = neon_load_reg(rd, pass);
9ee6e8bb 3788 for (n = 0; n < 4; n++) {
8f8e3aa4 3789 tmp = new_tmp();
9ee6e8bb 3790 if (n == 0) {
8f8e3aa4 3791 tcg_gen_mov_i32(tmp, tmp2);
9ee6e8bb 3792 } else {
8f8e3aa4 3793 tcg_gen_shri_i32(tmp, tmp2, n * 8);
9ee6e8bb 3794 }
b0109805 3795 gen_st8(tmp, cpu_T[1], IS_USER(s));
9ee6e8bb 3796 gen_op_addl_T1_im(stride);
9ee6e8bb 3797 }
8f8e3aa4 3798 dead_tmp(tmp2);
9ee6e8bb
PB		 3799 }
3800 }
3801 }
3802 rd += neon_ls_element_type[op].spacing;
3803 }
3804 stride = nregs * 8;
3805 } else {
3806 size = (insn >> 10) & 3;
3807 if (size == 3) {
3808 /* Load single element to all lanes. */
3809 if (!load)
3810 return 1;
3811 size = (insn >> 6) & 3;
3812 nregs = ((insn >> 8) & 3) + 1;
3813 stride = (insn & (1 << 5)) ? 2 : 1;
ff8263a9 3814 gen_movl_T1_reg(s, rn);
9ee6e8bb
PB		 3815 for (reg = 0; reg < nregs; reg++) {
3816 switch (size) {
3817 case 0:
b0109805 3818 tmp = gen_ld8u(cpu_T[1], IS_USER(s));
ad69471c 3819 gen_neon_dup_u8(tmp, 0);
9ee6e8bb
PB		 3820 break;
3821 case 1:
b0109805 3822 tmp = gen_ld16u(cpu_T[1], IS_USER(s));
ad69471c 3823 gen_neon_dup_low16(tmp);
9ee6e8bb
PB		 3824 break;
3825 case 2:
b0109805 3826 tmp = gen_ld32(cpu_T[0], IS_USER(s));
9ee6e8bb
PB		 3827 break;
3828 case 3:
3829 return 1;
99c475ab 3830 }
9ee6e8bb 3831 gen_op_addl_T1_im(1 << size);
ad69471c
PB		 3832 tmp2 = new_tmp();
3833 tcg_gen_mov_i32(tmp2, tmp);
3834 neon_store_reg(rd, 0, tmp2);
3835 neon_store_reg(rd, 0, tmp);
9ee6e8bb
PB		 3836 rd += stride;
3837 }
3838 stride = (1 << size) * nregs;
3839 } else {
3840 /* Single element. */
3841 pass = (insn >> 7) & 1;
3842 switch (size) {
3843 case 0:
3844 shift = ((insn >> 5) & 3) * 8;
9ee6e8bb
PB		 3845 stride = 1;
3846 break;
3847 case 1:
3848 shift = ((insn >> 6) & 1) * 16;
9ee6e8bb
PB		 3849 stride = (insn & (1 << 5)) ? 2 : 1;
3850 break;
3851 case 2:
3852 shift = 0;
9ee6e8bb
PB		 3853 stride = (insn & (1 << 6)) ? 2 : 1;
3854 break;
3855 default:
3856 abort();
3857 }
3858 nregs = ((insn >> 8) & 3) + 1;
3859 gen_movl_T1_reg(s, rn);
3860 for (reg = 0; reg < nregs; reg++) {
3861 if (load) {
9ee6e8bb
PB		 3862 switch (size) {
3863 case 0:
b0109805 3864 tmp = gen_ld8u(cpu_T[1], IS_USER(s));
9ee6e8bb
PB		 3865 break;
3866 case 1:
b0109805 3867 tmp = gen_ld16u(cpu_T[1], IS_USER(s));
9ee6e8bb
PB		 3868 break;
3869 case 2:
b0109805 3870 tmp = gen_ld32(cpu_T[1], IS_USER(s));
9ee6e8bb
PB		 3871 break;
3872 }
3873 if (size != 2) {
8f8e3aa4
PB		 3874 tmp2 = neon_load_reg(rd, pass);
3875 gen_bfi(tmp, tmp2, tmp, shift, size ? 0xffff : 0xff);
3876 dead_tmp(tmp2);
9ee6e8bb 3877 }
8f8e3aa4 3878 neon_store_reg(rd, pass, tmp);
9ee6e8bb 3879 } else { /* Store */
8f8e3aa4
PB		 3880 tmp = neon_load_reg(rd, pass);
3881 if (shift)
3882 tcg_gen_shri_i32(tmp, tmp, shift);
9ee6e8bb
PB		 3883 switch (size) {
3884 case 0:
b0109805 3885 gen_st8(tmp, cpu_T[1], IS_USER(s));
9ee6e8bb
PB		 3886 break;
3887 case 1:
b0109805 3888 gen_st16(tmp, cpu_T[1], IS_USER(s));
9ee6e8bb
PB		 3889 break;
3890 case 2:
b0109805 3891 gen_st32(tmp, cpu_T[1], IS_USER(s));
9ee6e8bb 3892 break;
99c475ab 3893 }
99c475ab 3894 }
9ee6e8bb
PB		 3895 rd += stride;
3896 gen_op_addl_T1_im(1 << size);
99c475ab 3897 }
9ee6e8bb 3898 stride = nregs * (1 << size);
99c475ab 3899 }
9ee6e8bb
PB		 3900 }
3901 if (rm != 15) {
b26eefb6
PB		 3902 TCGv base;
3903
3904 base = load_reg(s, rn);
9ee6e8bb 3905 if (rm == 13) {
b26eefb6 3906 tcg_gen_addi_i32(base, base, stride);
9ee6e8bb 3907 } else {
b26eefb6
PB		 3908 TCGv index;
3909 index = load_reg(s, rm);
3910 tcg_gen_add_i32(base, base, index);
3911 dead_tmp(index);
9ee6e8bb 3912 }
b26eefb6 3913 store_reg(s, rn, base);
9ee6e8bb
PB		 3914 }
3915 return 0;
3916}
3b46e624 3917
8f8e3aa4
PB		 3918/* Bitwise select. dest = c ? t : f. Clobbers T and F. */
3919static void gen_neon_bsl(TCGv dest, TCGv t, TCGv f, TCGv c)
3920{
3921 tcg_gen_and_i32(t, t, c);
3922 tcg_gen_bic_i32(f, f, c);
3923 tcg_gen_or_i32(dest, t, f);
3924}
3925
ad69471c
PB		 3926static inline void gen_neon_narrow(int size, TCGv dest, TCGv src)
3927{
3928 switch (size) {
3929 case 0: gen_helper_neon_narrow_u8(dest, src); break;
3930 case 1: gen_helper_neon_narrow_u16(dest, src); break;
3931 case 2: tcg_gen_trunc_i64_i32(dest, src); break;
3932 default: abort();
3933 }
3934}
3935
3936static inline void gen_neon_narrow_sats(int size, TCGv dest, TCGv src)
3937{
3938 switch (size) {
3939 case 0: gen_helper_neon_narrow_sat_s8(dest, cpu_env, src); break;
3940 case 1: gen_helper_neon_narrow_sat_s16(dest, cpu_env, src); break;
3941 case 2: gen_helper_neon_narrow_sat_s32(dest, cpu_env, src); break;
3942 default: abort();
3943 }
3944}
3945
3946static inline void gen_neon_narrow_satu(int size, TCGv dest, TCGv src)
3947{
3948 switch (size) {
3949 case 0: gen_helper_neon_narrow_sat_u8(dest, cpu_env, src); break;
3950 case 1: gen_helper_neon_narrow_sat_u16(dest, cpu_env, src); break;
3951 case 2: gen_helper_neon_narrow_sat_u32(dest, cpu_env, src); break;
3952 default: abort();
3953 }
3954}
3955
3956static inline void gen_neon_shift_narrow(int size, TCGv var, TCGv shift,
3957 int q, int u)
3958{
3959 if (q) {
3960 if (u) {
3961 switch (size) {
3962 case 1: gen_helper_neon_rshl_u16(var, var, shift); break;
3963 case 2: gen_helper_neon_rshl_u32(var, var, shift); break;
3964 default: abort();
3965 }
3966 } else {
3967 switch (size) {
3968 case 1: gen_helper_neon_rshl_s16(var, var, shift); break;
3969 case 2: gen_helper_neon_rshl_s32(var, var, shift); break;
3970 default: abort();
3971 }
3972 }
3973 } else {
3974 if (u) {
3975 switch (size) {
3976 case 1: gen_helper_neon_rshl_u16(var, var, shift); break;
3977 case 2: gen_helper_neon_rshl_u32(var, var, shift); break;
3978 default: abort();
3979 }
3980 } else {
3981 switch (size) {
3982 case 1: gen_helper_neon_shl_s16(var, var, shift); break;
3983 case 2: gen_helper_neon_shl_s32(var, var, shift); break;
3984 default: abort();
3985 }
3986 }
3987 }
3988}
3989
3990static inline void gen_neon_widen(TCGv dest, TCGv src, int size, int u)
3991{
3992 if (u) {
3993 switch (size) {
3994 case 0: gen_helper_neon_widen_u8(dest, src); break;
3995 case 1: gen_helper_neon_widen_u16(dest, src); break;
3996 case 2: tcg_gen_extu_i32_i64(dest, src); break;
3997 default: abort();
3998 }
3999 } else {
4000 switch (size) {
4001 case 0: gen_helper_neon_widen_s8(dest, src); break;
4002 case 1: gen_helper_neon_widen_s16(dest, src); break;
4003 case 2: tcg_gen_ext_i32_i64(dest, src); break;
4004 default: abort();
4005 }
4006 }
4007 dead_tmp(src);
4008}
4009
4010static inline void gen_neon_addl(int size)
4011{
4012 switch (size) {
4013 case 0: gen_helper_neon_addl_u16(CPU_V001); break;
4014 case 1: gen_helper_neon_addl_u32(CPU_V001); break;
4015 case 2: tcg_gen_add_i64(CPU_V001); break;
4016 default: abort();
4017 }
4018}
4019
4020static inline void gen_neon_subl(int size)
4021{
4022 switch (size) {
4023 case 0: gen_helper_neon_subl_u16(CPU_V001); break;
4024 case 1: gen_helper_neon_subl_u32(CPU_V001); break;
4025 case 2: tcg_gen_sub_i64(CPU_V001); break;
4026 default: abort();
4027 }
4028}
4029
4030static inline void gen_neon_negl(TCGv var, int size)
4031{
4032 switch (size) {
4033 case 0: gen_helper_neon_negl_u16(var, var); break;
4034 case 1: gen_helper_neon_negl_u32(var, var); break;
4035 case 2: gen_helper_neon_negl_u64(var, var); break;
4036 default: abort();
4037 }
4038}
4039
4040static inline void gen_neon_addl_saturate(TCGv op0, TCGv op1, int size)
4041{
4042 switch (size) {
4043 case 1: gen_helper_neon_addl_saturate_s32(op0, cpu_env, op0, op1); break;
4044 case 2: gen_helper_neon_addl_saturate_s64(op0, cpu_env, op0, op1); break;
4045 default: abort();
4046 }
4047}
4048
4049static inline void gen_neon_mull(TCGv dest, TCGv a, TCGv b, int size, int u)
4050{
4051 TCGv tmp;
4052
4053 switch ((size << 1) | u) {
4054 case 0: gen_helper_neon_mull_s8(dest, a, b); break;
4055 case 1: gen_helper_neon_mull_u8(dest, a, b); break;
4056 case 2: gen_helper_neon_mull_s16(dest, a, b); break;
4057 case 3: gen_helper_neon_mull_u16(dest, a, b); break;
4058 case 4:
4059 tmp = gen_muls_i64_i32(a, b);
4060 tcg_gen_mov_i64(dest, tmp);
4061 break;
4062 case 5:
4063 tmp = gen_mulu_i64_i32(a, b);
4064 tcg_gen_mov_i64(dest, tmp);
4065 break;
4066 default: abort();
4067 }
4068 if (size < 2) {
4069 dead_tmp(b);
4070 dead_tmp(a);
4071 }
4072}
4073
9ee6e8bb
PB		 4074/* Translate a NEON data processing instruction. Return nonzero if the
4075 instruction is invalid.
ad69471c
PB		 4076 We process data in a mixture of 32-bit and 64-bit chunks.
4077 Mostly we use 32-bit chunks so we can use normal scalar instructions. */
2c0262af 4078
9ee6e8bb
PB		 4079static int disas_neon_data_insn(CPUState * env, DisasContext *s, uint32_t insn)
4080{
4081 int op;
4082 int q;
4083 int rd, rn, rm;
4084 int size;
4085 int shift;
4086 int pass;
4087 int count;
4088 int pairwise;
4089 int u;
4090 int n;
4091 uint32_t imm;
8f8e3aa4
PB		 4092 TCGv tmp;
4093 TCGv tmp2;
4094 TCGv tmp3;
9ee6e8bb
PB		 4095
4096 if (!vfp_enabled(env))
4097 return 1;
4098 q = (insn & (1 << 6)) != 0;
4099 u = (insn >> 24) & 1;
4100 VFP_DREG_D(rd, insn);
4101 VFP_DREG_N(rn, insn);
4102 VFP_DREG_M(rm, insn);
4103 size = (insn >> 20) & 3;
4104 if ((insn & (1 << 23)) == 0) {
4105 /* Three register same length. */
4106 op = ((insn >> 7) & 0x1e) | ((insn >> 4) & 1);
ad69471c
PB		 4107 if (size == 3 && (op == 1 || op == 5 || op == 8 || op == 9
4108 || op == 10 || op == 11 || op == 16)) {
4109 /* 64-bit element instructions. */
9ee6e8bb 4110 for (pass = 0; pass < (q ? 2 : 1); pass++) {
ad69471c
PB		 4111 neon_load_reg64(cpu_V0, rn + pass);
4112 neon_load_reg64(cpu_V1, rm + pass);
9ee6e8bb
PB		 4113 switch (op) {
4114 case 1: /* VQADD */
4115 if (u) {
ad69471c 4116 gen_helper_neon_add_saturate_u64(CPU_V001);
2c0262af 4117 } else {
ad69471c 4118 gen_helper_neon_add_saturate_s64(CPU_V001);
2c0262af 4119 }
9ee6e8bb
PB		 4120 break;
4121 case 5: /* VQSUB */
4122 if (u) {
ad69471c
PB		 4123 gen_helper_neon_sub_saturate_u64(CPU_V001);
4124 } else {
4125 gen_helper_neon_sub_saturate_s64(CPU_V001);
4126 }
4127 break;
4128 case 8: /* VSHL */
4129 if (u) {
4130 gen_helper_neon_shl_u64(cpu_V0, cpu_V1, cpu_V0);
4131 } else {
4132 gen_helper_neon_shl_s64(cpu_V0, cpu_V1, cpu_V0);
4133 }
4134 break;
4135 case 9: /* VQSHL */
4136 if (u) {
4137 gen_helper_neon_qshl_u64(cpu_V0, cpu_env,
4138 cpu_V0, cpu_V0);
4139 } else {
4140 gen_helper_neon_qshl_s64(cpu_V1, cpu_env,
4141 cpu_V1, cpu_V0);
4142 }
4143 break;
4144 case 10: /* VRSHL */
4145 if (u) {
4146 gen_helper_neon_rshl_u64(cpu_V0, cpu_V1, cpu_V0);
1e8d4eec 4147 } else {
ad69471c
PB		 4148 gen_helper_neon_rshl_s64(cpu_V0, cpu_V1, cpu_V0);
4149 }
4150 break;
4151 case 11: /* VQRSHL */
4152 if (u) {
4153 gen_helper_neon_qrshl_u64(cpu_V0, cpu_env,
4154 cpu_V1, cpu_V0);
4155 } else {
4156 gen_helper_neon_qrshl_s64(cpu_V0, cpu_env,
4157 cpu_V1, cpu_V0);
1e8d4eec 4158 }
9ee6e8bb
PB		 4159 break;
4160 case 16:
4161 if (u) {
ad69471c 4162 tcg_gen_sub_i64(CPU_V001);
9ee6e8bb 4163 } else {
ad69471c 4164 tcg_gen_add_i64(CPU_V001);
9ee6e8bb
PB		 4165 }
4166 break;
4167 default:
4168 abort();
2c0262af 4169 }
ad69471c 4170 neon_store_reg64(cpu_V0, rd + pass);
2c0262af 4171 }
9ee6e8bb 4172 return 0;
2c0262af 4173 }
9ee6e8bb
PB		 4174 switch (op) {
4175 case 8: /* VSHL */
4176 case 9: /* VQSHL */
4177 case 10: /* VRSHL */
ad69471c 4178 case 11: /* VQRSHL */
9ee6e8bb 4179 {
ad69471c
PB		 4180 int rtmp;
4181 /* Shift instruction operands are reversed. */
4182 rtmp = rn;
9ee6e8bb 4183 rn = rm;
ad69471c 4184 rm = rtmp;
9ee6e8bb
PB		 4185 pairwise = 0;
4186 }
2c0262af 4187 break;
9ee6e8bb
PB		 4188 case 20: /* VPMAX */
4189 case 21: /* VPMIN */
4190 case 23: /* VPADD */
4191 pairwise = 1;
2c0262af 4192 break;
9ee6e8bb
PB		 4193 case 26: /* VPADD (float) */
4194 pairwise = (u && size < 2);
2c0262af 4195 break;
9ee6e8bb
PB		 4196 case 30: /* VPMIN/VPMAX (float) */
4197 pairwise = u;
2c0262af 4198 break;
9ee6e8bb
PB		 4199 default:
4200 pairwise = 0;
2c0262af 4201 break;
9ee6e8bb
PB		 4202 }
4203 for (pass = 0; pass < (q ? 4 : 2); pass++) {
4204
4205 if (pairwise) {
4206 /* Pairwise. */
4207 if (q)
4208 n = (pass & 1) * 2;
2c0262af 4209 else
9ee6e8bb
PB		 4210 n = 0;
4211 if (pass < q + 1) {
4212 NEON_GET_REG(T0, rn, n);
4213 NEON_GET_REG(T1, rn, n + 1);
4214 } else {
4215 NEON_GET_REG(T0, rm, n);
4216 NEON_GET_REG(T1, rm, n + 1);
4217 }
4218 } else {
4219 /* Elementwise. */
4220 NEON_GET_REG(T0, rn, pass);
4221 NEON_GET_REG(T1, rm, pass);
4222 }
4223 switch (op) {
4224 case 0: /* VHADD */
4225 GEN_NEON_INTEGER_OP(hadd);
4226 break;
4227 case 1: /* VQADD */
ad69471c 4228 GEN_NEON_INTEGER_OP_ENV(qadd);
2c0262af 4229 break;
9ee6e8bb
PB		 4230 case 2: /* VRHADD */
4231 GEN_NEON_INTEGER_OP(rhadd);
2c0262af 4232 break;
9ee6e8bb
PB		 4233 case 3: /* Logic ops. */
4234 switch ((u << 2) | size) {
4235 case 0: /* VAND */
2c0262af 4236 gen_op_andl_T0_T1();
9ee6e8bb
PB		 4237 break;
4238 case 1: /* BIC */
4239 gen_op_bicl_T0_T1();
4240 break;
4241 case 2: /* VORR */
4242 gen_op_orl_T0_T1();
4243 break;
4244 case 3: /* VORN */
4245 gen_op_notl_T1();
4246 gen_op_orl_T0_T1();
4247 break;
4248 case 4: /* VEOR */
4249 gen_op_xorl_T0_T1();
4250 break;
4251 case 5: /* VBSL */
8f8e3aa4
PB		 4252 tmp = neon_load_reg(rd, pass);
4253 gen_neon_bsl(cpu_T[0], cpu_T[0], cpu_T[1], tmp);
4254 dead_tmp(tmp);
9ee6e8bb
PB		 4255 break;
4256 case 6: /* VBIT */
8f8e3aa4
PB		 4257 tmp = neon_load_reg(rd, pass);
4258 gen_neon_bsl(cpu_T[0], cpu_T[0], tmp, cpu_T[1]);
4259 dead_tmp(tmp);
9ee6e8bb
PB		 4260 break;
4261 case 7: /* VBIF */
8f8e3aa4
PB		 4262 tmp = neon_load_reg(rd, pass);
4263 gen_neon_bsl(cpu_T[0], tmp, cpu_T[0], cpu_T[1]);
4264 dead_tmp(tmp);
9ee6e8bb 4265 break;
2c0262af
FB		 4266 }
4267 break;
9ee6e8bb
PB		 4268 case 4: /* VHSUB */
4269 GEN_NEON_INTEGER_OP(hsub);
4270 break;
4271 case 5: /* VQSUB */
ad69471c 4272 GEN_NEON_INTEGER_OP_ENV(qsub);
2c0262af 4273 break;
9ee6e8bb
PB		 4274 case 6: /* VCGT */
4275 GEN_NEON_INTEGER_OP(cgt);
4276 break;
4277 case 7: /* VCGE */
4278 GEN_NEON_INTEGER_OP(cge);
4279 break;
4280 case 8: /* VSHL */
ad69471c 4281 GEN_NEON_INTEGER_OP(shl);
2c0262af 4282 break;
9ee6e8bb 4283 case 9: /* VQSHL */
ad69471c 4284 GEN_NEON_INTEGER_OP_ENV(qshl);
2c0262af 4285 break;
9ee6e8bb 4286 case 10: /* VRSHL */
ad69471c 4287 GEN_NEON_INTEGER_OP(rshl);
2c0262af 4288 break;
9ee6e8bb 4289 case 11: /* VQRSHL */
ad69471c 4290 GEN_NEON_INTEGER_OP_ENV(qrshl);
9ee6e8bb
PB		 4291 break;
4292 case 12: /* VMAX */
4293 GEN_NEON_INTEGER_OP(max);
4294 break;
4295 case 13: /* VMIN */
4296 GEN_NEON_INTEGER_OP(min);
4297 break;
4298 case 14: /* VABD */
4299 GEN_NEON_INTEGER_OP(abd);
4300 break;
4301 case 15: /* VABA */
4302 GEN_NEON_INTEGER_OP(abd);
4303 NEON_GET_REG(T1, rd, pass);
4304 gen_neon_add(size);
4305 break;
4306 case 16:
4307 if (!u) { /* VADD */
4308 if (gen_neon_add(size))
4309 return 1;
4310 } else { /* VSUB */
4311 switch (size) {
ad69471c
PB		 4312 case 0: gen_helper_neon_sub_u8(CPU_T001); break;
4313 case 1: gen_helper_neon_sub_u16(CPU_T001); break;
9ee6e8bb
PB		 4314 case 2: gen_op_subl_T0_T1(); break;
4315 default: return 1;
4316 }
4317 }
4318 break;
4319 case 17:
4320 if (!u) { /* VTST */
4321 switch (size) {
ad69471c
PB		 4322 case 0: gen_helper_neon_tst_u8(CPU_T001); break;
4323 case 1: gen_helper_neon_tst_u16(CPU_T001); break;
4324 case 2: gen_helper_neon_tst_u32(CPU_T001); break;
9ee6e8bb
PB		 4325 default: return 1;
4326 }
4327 } else { /* VCEQ */
4328 switch (size) {
ad69471c
PB		 4329 case 0: gen_helper_neon_ceq_u8(CPU_T001); break;
4330 case 1: gen_helper_neon_ceq_u16(CPU_T001); break;
4331 case 2: gen_helper_neon_ceq_u32(CPU_T001); break;
9ee6e8bb
PB		 4332 default: return 1;
4333 }
4334 }
4335 break;
4336 case 18: /* Multiply. */
4337 switch (size) {
ad69471c
PB		 4338 case 0: gen_helper_neon_mul_u8(CPU_T001); break;
4339 case 1: gen_helper_neon_mul_u16(CPU_T001); break;
9ee6e8bb
PB		 4340 case 2: gen_op_mul_T0_T1(); break;
4341 default: return 1;
4342 }
4343 NEON_GET_REG(T1, rd, pass);
4344 if (u) { /* VMLS */
ad69471c 4345 gen_neon_rsb(size);
9ee6e8bb
PB		 4346 } else { /* VMLA */
4347 gen_neon_add(size);
4348 }
4349 break;
4350 case 19: /* VMUL */
4351 if (u) { /* polynomial */
ad69471c 4352 gen_helper_neon_mul_p8(CPU_T001);
9ee6e8bb
PB		 4353 } else { /* Integer */
4354 switch (size) {
ad69471c
PB		 4355 case 0: gen_helper_neon_mul_u8(CPU_T001); break;
4356 case 1: gen_helper_neon_mul_u16(CPU_T001); break;
9ee6e8bb
PB		 4357 case 2: gen_op_mul_T0_T1(); break;
4358 default: return 1;
4359 }
4360 }
4361 break;
4362 case 20: /* VPMAX */
4363 GEN_NEON_INTEGER_OP(pmax);
4364 break;
4365 case 21: /* VPMIN */
4366 GEN_NEON_INTEGER_OP(pmin);
4367 break;
4368 case 22: /* Hultiply high. */
4369 if (!u) { /* VQDMULH */
4370 switch (size) {
ad69471c
PB		 4371 case 1: gen_helper_neon_qdmulh_s16(CPU_T0E01); break;
4372 case 2: gen_helper_neon_qdmulh_s32(CPU_T0E01); break;
9ee6e8bb
PB		 4373 default: return 1;
4374 }
4375 } else { /* VQRDHMUL */
4376 switch (size) {
ad69471c
PB		 4377 case 1: gen_helper_neon_qrdmulh_s16(CPU_T0E01); break;
4378 case 2: gen_helper_neon_qrdmulh_s32(CPU_T0E01); break;
9ee6e8bb
PB		 4379 default: return 1;
4380 }
4381 }
4382 break;
4383 case 23: /* VPADD */
4384 if (u)
4385 return 1;
4386 switch (size) {
ad69471c
PB		 4387 case 0: gen_helper_neon_padd_u8(CPU_T001); break;
4388 case 1: gen_helper_neon_padd_u16(CPU_T001); break;
9ee6e8bb
PB		 4389 case 2: gen_op_addl_T0_T1(); break;
4390 default: return 1;
4391 }
4392 break;
4393 case 26: /* Floating point arithnetic. */
4394 switch ((u << 2) | size) {
4395 case 0: /* VADD */
ad69471c 4396 gen_helper_neon_add_f32(CPU_T001);
9ee6e8bb
PB		 4397 break;
4398 case 2: /* VSUB */
ad69471c 4399 gen_helper_neon_sub_f32(CPU_T001);
9ee6e8bb
PB		 4400 break;
4401 case 4: /* VPADD */
ad69471c 4402 gen_helper_neon_add_f32(CPU_T001);
9ee6e8bb
PB		 4403 break;
4404 case 6: /* VABD */
ad69471c 4405 gen_helper_neon_abd_f32(CPU_T001);
9ee6e8bb
PB		 4406 break;
4407 default:
4408 return 1;
4409 }
4410 break;
4411 case 27: /* Float multiply. */
ad69471c 4412 gen_helper_neon_mul_f32(CPU_T001);
9ee6e8bb
PB		 4413 if (!u) {
4414 NEON_GET_REG(T1, rd, pass);
4415 if (size == 0) {
ad69471c 4416 gen_helper_neon_add_f32(CPU_T001);
9ee6e8bb 4417 } else {
ad69471c 4418 gen_helper_neon_sub_f32(cpu_T[0], cpu_T[1], cpu_T[0]);
9ee6e8bb
PB		 4419 }
4420 }
4421 break;
4422 case 28: /* Float compare. */
4423 if (!u) {
ad69471c 4424 gen_helper_neon_ceq_f32(CPU_T001);
b5ff1b31 4425 } else {
9ee6e8bb 4426 if (size == 0)
ad69471c 4427 gen_helper_neon_cge_f32(CPU_T001);
9ee6e8bb 4428 else
ad69471c 4429 gen_helper_neon_cgt_f32(CPU_T001);
b5ff1b31 4430 }
2c0262af 4431 break;
9ee6e8bb
PB		 4432 case 29: /* Float compare absolute. */
4433 if (!u)
4434 return 1;
4435 if (size == 0)
ad69471c 4436 gen_helper_neon_acge_f32(CPU_T001);
9ee6e8bb 4437 else
ad69471c 4438 gen_helper_neon_acgt_f32(CPU_T001);
2c0262af 4439 break;
9ee6e8bb
PB		 4440 case 30: /* Float min/max. */
4441 if (size == 0)
ad69471c 4442 gen_helper_neon_max_f32(CPU_T001);
9ee6e8bb 4443 else
ad69471c 4444 gen_helper_neon_min_f32(CPU_T001);
9ee6e8bb
PB		 4445 break;
4446 case 31:
4447 if (size == 0)
4373f3ce 4448 gen_helper_recps_f32(cpu_T[0], cpu_T[0], cpu_T[1], cpu_env);
9ee6e8bb 4449 else
4373f3ce 4450 gen_helper_rsqrts_f32(cpu_T[0], cpu_T[0], cpu_T[1], cpu_env);
2c0262af 4451 break;
9ee6e8bb
PB		 4452 default:
4453 abort();
2c0262af 4454 }
9ee6e8bb
PB		 4455 /* Save the result. For elementwise operations we can put it
4456 straight into the destination register. For pairwise operations
4457 we have to be careful to avoid clobbering the source operands. */
4458 if (pairwise && rd == rm) {
4459 gen_neon_movl_scratch_T0(pass);
4460 } else {
4461 NEON_SET_REG(T0, rd, pass);
4462 }
4463
4464 } /* for pass */
4465 if (pairwise && rd == rm) {
4466 for (pass = 0; pass < (q ? 4 : 2); pass++) {
4467 gen_neon_movl_T0_scratch(pass);
4468 NEON_SET_REG(T0, rd, pass);
4469 }
4470 }
ad69471c 4471 /* End of 3 register same size operations. */
9ee6e8bb
PB		 4472 } else if (insn & (1 << 4)) {
4473 if ((insn & 0x00380080) != 0) {
4474 /* Two registers and shift. */
4475 op = (insn >> 8) & 0xf;
4476 if (insn & (1 << 7)) {
4477 /* 64-bit shift. */
4478 size = 3;
4479 } else {
4480 size = 2;
4481 while ((insn & (1 << (size + 19))) == 0)
4482 size--;
4483 }
4484 shift = (insn >> 16) & ((1 << (3 + size)) - 1);
4485 /* To avoid excessive dumplication of ops we implement shift
4486 by immediate using the variable shift operations. */
4487 if (op < 8) {
4488 /* Shift by immediate:
4489 VSHR, VSRA, VRSHR, VRSRA, VSRI, VSHL, VQSHL, VQSHLU. */
4490 /* Right shifts are encoded as N - shift, where N is the
4491 element size in bits. */
4492 if (op <= 4)
4493 shift = shift - (1 << (size + 3));
9ee6e8bb
PB		 4494 if (size == 3) {
4495 count = q + 1;
4496 } else {
4497 count = q ? 4: 2;
4498 }
4499 switch (size) {
4500 case 0:
4501 imm = (uint8_t) shift;
4502 imm |= imm << 8;
4503 imm |= imm << 16;
4504 break;
4505 case 1:
4506 imm = (uint16_t) shift;
4507 imm |= imm << 16;
4508 break;
4509 case 2:
4510 case 3:
4511 imm = shift;
4512 break;
4513 default:
4514 abort();
4515 }
4516
4517 for (pass = 0; pass < count; pass++) {
ad69471c
PB		 4518 if (size == 3) {
4519 neon_load_reg64(cpu_V0, rm + pass);
4520 tcg_gen_movi_i64(cpu_V1, imm);
4521 switch (op) {
4522 case 0: /* VSHR */
4523 case 1: /* VSRA */
4524 if (u)
4525 gen_helper_neon_shl_u64(cpu_V0, cpu_V0, cpu_V1);
9ee6e8bb 4526 else
ad69471c 4527 gen_helper_neon_shl_s64(cpu_V0, cpu_V0, cpu_V1);
9ee6e8bb 4528 break;
ad69471c
PB		 4529 case 2: /* VRSHR */
4530 case 3: /* VRSRA */
4531 if (u)
4532 gen_helper_neon_rshl_u64(cpu_V0, cpu_V0, cpu_V1);
9ee6e8bb 4533 else
ad69471c 4534 gen_helper_neon_rshl_s64(cpu_V0, cpu_V0, cpu_V1);
9ee6e8bb 4535 break;
ad69471c
PB		 4536 case 4: /* VSRI */
4537 if (!u)
4538 return 1;
4539 gen_helper_neon_shl_u64(cpu_V0, cpu_V0, cpu_V1);
4540 break;
4541 case 5: /* VSHL, VSLI */
4542 gen_helper_neon_shl_u64(cpu_V0, cpu_V0, cpu_V1);
4543 break;
4544 case 6: /* VQSHL */
4545 if (u)
4546 gen_helper_neon_qshl_u64(cpu_V0, cpu_env, cpu_V0, cpu_V1);
9ee6e8bb 4547 else
ad69471c
PB		 4548 gen_helper_neon_qshl_s64(cpu_V0, cpu_env, cpu_V0, cpu_V1);
4549 break;
4550 case 7: /* VQSHLU */
4551 gen_helper_neon_qshl_u64(cpu_V0, cpu_env, cpu_V0, cpu_V1);
9ee6e8bb 4552 break;
9ee6e8bb 4553 }
ad69471c
PB		 4554 if (op == 1 || op == 3) {
4555 /* Accumulate. */
4556 neon_load_reg64(cpu_V0, rd + pass);
4557 tcg_gen_add_i64(cpu_V0, cpu_V0, cpu_V1);
4558 } else if (op == 4 || (op == 5 && u)) {
4559 /* Insert */
4560 cpu_abort(env, "VS[LR]I.64 not implemented");
4561 }
4562 neon_store_reg64(cpu_V0, rd + pass);
4563 } else { /* size < 3 */
4564 /* Operands in T0 and T1. */
4565 gen_op_movl_T1_im(imm);
4566 NEON_GET_REG(T0, rm, pass);
4567 switch (op) {
4568 case 0: /* VSHR */
4569 case 1: /* VSRA */
4570 GEN_NEON_INTEGER_OP(shl);
4571 break;
4572 case 2: /* VRSHR */
4573 case 3: /* VRSRA */
4574 GEN_NEON_INTEGER_OP(rshl);
4575 break;
4576 case 4: /* VSRI */
4577 if (!u)
4578 return 1;
4579 GEN_NEON_INTEGER_OP(shl);
4580 break;
4581 case 5: /* VSHL, VSLI */
4582 switch (size) {
4583 case 0: gen_helper_neon_shl_u8(CPU_T001); break;
4584 case 1: gen_helper_neon_shl_u16(CPU_T001); break;
4585 case 2: gen_helper_neon_shl_u32(CPU_T001); break;
4586 default: return 1;
4587 }
4588 break;
4589 case 6: /* VQSHL */
4590 GEN_NEON_INTEGER_OP_ENV(qshl);
4591 break;
4592 case 7: /* VQSHLU */
4593 switch (size) {
4594 case 0: gen_helper_neon_qshl_u8(CPU_T0E01); break;
4595 case 1: gen_helper_neon_qshl_u16(CPU_T0E01); break;
4596 case 2: gen_helper_neon_qshl_u32(CPU_T0E01); break;
4597 default: return 1;
4598 }
4599 break;
4600 }
4601
4602 if (op == 1 || op == 3) {
4603 /* Accumulate. */
4604 NEON_GET_REG(T1, rd, pass);
4605 gen_neon_add(size);
4606 } else if (op == 4 || (op == 5 && u)) {
4607 /* Insert */
4608 switch (size) {
4609 case 0:
4610 if (op == 4)
4611 imm = 0xff >> -shift;
4612 else
4613 imm = (uint8_t)(0xff << shift);
4614 imm |= imm << 8;
4615 imm |= imm << 16;
4616 break;
4617 case 1:
4618 if (op == 4)
4619 imm = 0xffff >> -shift;
4620 else
4621 imm = (uint16_t)(0xffff << shift);
4622 imm |= imm << 16;
4623 break;
4624 case 2:
4625 if (op == 4)
4626 imm = 0xffffffffu >> -shift;
4627 else
4628 imm = 0xffffffffu << shift;
4629 break;
4630 default:
4631 abort();
4632 }
4633 tmp = neon_load_reg(rd, pass);
4634 tcg_gen_andi_i32(cpu_T[0], cpu_T[0], imm);
4635 tcg_gen_andi_i32(tmp, tmp, ~imm);
4636 tcg_gen_or_i32(cpu_T[0], cpu_T[0], tmp);
4637 }
9ee6e8bb
PB		 4638 NEON_SET_REG(T0, rd, pass);
4639 }
4640 } /* for pass */
4641 } else if (op < 10) {
ad69471c 4642 /* Shift by immediate and narrow:
9ee6e8bb
PB		 4643 VSHRN, VRSHRN, VQSHRN, VQRSHRN. */
4644 shift = shift - (1 << (size + 3));
4645 size++;
9ee6e8bb
PB		 4646 switch (size) {
4647 case 1:
ad69471c 4648 imm = (uint16_t)shift;
9ee6e8bb 4649 imm |= imm << 16;
ad69471c 4650 tmp2 = tcg_const_i32(imm);
9ee6e8bb
PB		 4651 break;
4652 case 2:
ad69471c
PB		 4653 imm = (uint32_t)shift;
4654 tmp2 = tcg_const_i32(imm);
9ee6e8bb 4655 case 3:
ad69471c 4656 tmp2 = tcg_const_i64(shift);
9ee6e8bb
PB		 4657 break;
4658 default:
4659 abort();
4660 }
4661
ad69471c
PB		 4662 for (pass = 0; pass < 2; pass++) {
4663 if (size == 3) {
4664 neon_load_reg64(cpu_V0, rm + pass);
4665 if (q) {
4666 if (u)
4667 gen_helper_neon_rshl_u64(cpu_V0, cpu_V0, tmp2);
4668 else
4669 gen_helper_neon_rshl_s64(cpu_V0, cpu_V0, tmp2);
4670 } else {
4671 if (u)
4672 gen_helper_neon_shl_u64(cpu_V0, cpu_V0, tmp2);
4673 else
4674 gen_helper_neon_shl_s64(cpu_V0, cpu_V0, tmp2);
4675 }
2c0262af 4676 } else {
ad69471c
PB		 4677 tmp = neon_load_reg(rm + pass, 0);
4678 gen_neon_shift_narrow(size, tmp, tmp2, q, u);
4679 tcg_gen_extu_i32_i64(cpu_V0, tmp);
4680 dead_tmp(tmp);
4681 tmp = neon_load_reg(rm + pass, 1);
4682 gen_neon_shift_narrow(size, tmp, tmp2, q, u);
4683 tcg_gen_extu_i32_i64(cpu_V1, tmp);
4684 dead_tmp(tmp);
4685 tcg_gen_shli_i64(cpu_V1, cpu_V1, 32);
4686 tcg_gen_or_i64(cpu_V0, cpu_V0, cpu_V1);
9ee6e8bb 4687 }
ad69471c
PB		 4688 tmp = new_tmp();
4689 if (op == 8 && !u) {
4690 gen_neon_narrow(size - 1, tmp, cpu_V0);
9ee6e8bb 4691 } else {
ad69471c
PB		 4692 if (op == 8)
4693 gen_neon_narrow_sats(size - 1, tmp, cpu_V0);
9ee6e8bb 4694 else
ad69471c
PB		 4695 gen_neon_narrow_satu(size - 1, tmp, cpu_V0);
4696 }
4697 if (pass == 0) {
4698 tmp2 = tmp;
4699 } else {
4700 neon_store_reg(rd, 0, tmp2);
4701 neon_store_reg(rd, 1, tmp);
9ee6e8bb
PB		 4702 }
4703 } /* for pass */
4704 } else if (op == 10) {
4705 /* VSHLL */
ad69471c 4706 if (q || size == 3)
9ee6e8bb 4707 return 1;
ad69471c
PB		 4708 tmp = neon_load_reg(rm, 0);
4709 tmp2 = neon_load_reg(rm, 1);
9ee6e8bb 4710 for (pass = 0; pass < 2; pass++) {
ad69471c
PB		 4711 if (pass == 1)
4712 tmp = tmp2;
4713
4714 gen_neon_widen(cpu_V0, tmp, size, u);
9ee6e8bb 4715
9ee6e8bb
PB		 4716 if (shift != 0) {
4717 /* The shift is less than the width of the source
ad69471c
PB		 4718 type, so we can just shift the whole register. */
4719 tcg_gen_shli_i64(cpu_V0, cpu_V0, shift);
4720 if (size < 2 || !u) {
4721 uint64_t imm64;
4722 if (size == 0) {
4723 imm = (0xffu >> (8 - shift));
4724 imm |= imm << 16;
4725 } else {
4726 imm = 0xffff >> (16 - shift);
9ee6e8bb 4727 }
ad69471c
PB		 4728 imm64 = imm | (((uint64_t)imm) << 32);
4729 tcg_gen_andi_i64(cpu_V0, cpu_V0, imm64);
9ee6e8bb
PB		 4730 }
4731 }
ad69471c 4732 neon_store_reg64(cpu_V0, rd + pass);
9ee6e8bb
PB		 4733 }
4734 } else if (op == 15 || op == 16) {
4735 /* VCVT fixed-point. */
4736 for (pass = 0; pass < (q ? 4 : 2); pass++) {
4373f3ce 4737 tcg_gen_ld_f32(cpu_F0s, cpu_env, neon_reg_offset(rm, pass));
9ee6e8bb
PB		 4738 if (op & 1) {
4739 if (u)
4373f3ce 4740 gen_vfp_ulto(0, shift);
9ee6e8bb 4741 else
4373f3ce 4742 gen_vfp_slto(0, shift);
9ee6e8bb
PB		 4743 } else {
4744 if (u)
4373f3ce 4745 gen_vfp_toul(0, shift);
9ee6e8bb 4746 else
4373f3ce 4747 gen_vfp_tosl(0, shift);
2c0262af 4748 }
4373f3ce 4749 tcg_gen_st_f32(cpu_F0s, cpu_env, neon_reg_offset(rd, pass));
2c0262af
FB		 4750 }
4751 } else {
9ee6e8bb
PB		 4752 return 1;
4753 }
4754 } else { /* (insn & 0x00380080) == 0 */
4755 int invert;
4756
4757 op = (insn >> 8) & 0xf;
4758 /* One register and immediate. */
4759 imm = (u << 7) | ((insn >> 12) & 0x70) | (insn & 0xf);
4760 invert = (insn & (1 << 5)) != 0;
4761 switch (op) {
4762 case 0: case 1:
4763 /* no-op */
4764 break;
4765 case 2: case 3:
4766 imm <<= 8;
4767 break;
4768 case 4: case 5:
4769 imm <<= 16;
4770 break;
4771 case 6: case 7:
4772 imm <<= 24;
4773 break;
4774 case 8: case 9:
4775 imm |= imm << 16;
4776 break;
4777 case 10: case 11:
4778 imm = (imm << 8) | (imm << 24);
4779 break;
4780 case 12:
4781 imm = (imm < 8) | 0xff;
4782 break;
4783 case 13:
4784 imm = (imm << 16) | 0xffff;
4785 break;
4786 case 14:
4787 imm |= (imm << 8) | (imm << 16) | (imm << 24);
4788 if (invert)
4789 imm = ~imm;
4790 break;
4791 case 15:
4792 imm = ((imm & 0x80) << 24) | ((imm & 0x3f) << 19)
4793 | ((imm & 0x40) ? (0x1f << 25) : (1 << 30));
4794 break;
4795 }
4796 if (invert)
4797 imm = ~imm;
4798
4799 if (op != 14 || !invert)
4800 gen_op_movl_T1_im(imm);
4801
4802 for (pass = 0; pass < (q ? 4 : 2); pass++) {
4803 if (op & 1 && op < 12) {
ad69471c 4804 tmp = neon_load_reg(rd, pass);
9ee6e8bb
PB		 4805 if (invert) {
4806 /* The immediate value has already been inverted, so
4807 BIC becomes AND. */
ad69471c 4808 tcg_gen_andi_i32(tmp, tmp, imm);
9ee6e8bb 4809 } else {
ad69471c 4810 tcg_gen_ori_i32(tmp, tmp, imm);
9ee6e8bb 4811 }
9ee6e8bb 4812 } else {
ad69471c
PB		 4813 /* VMOV, VMVN. */
4814 tmp = new_tmp();
9ee6e8bb 4815 if (op == 14 && invert) {
ad69471c
PB		 4816 uint32_t val;
4817 val = 0;
9ee6e8bb
PB		 4818 for (n = 0; n < 4; n++) {
4819 if (imm & (1 << (n + (pass & 1) * 4)))
ad69471c 4820 val |= 0xff << (n * 8);
9ee6e8bb 4821 }
ad69471c
PB		 4822 tcg_gen_movi_i32(tmp, val);
4823 } else {
4824 tcg_gen_movi_i32(tmp, imm);
9ee6e8bb 4825 }
9ee6e8bb 4826 }
ad69471c 4827 neon_store_reg(rd, pass, tmp);
9ee6e8bb
PB		 4828 }
4829 }
4830 } else { /* (insn & 0x00800010 == 0x00800010) */
4831 if (size != 3) {
4832 op = (insn >> 8) & 0xf;
4833 if ((insn & (1 << 6)) == 0) {
4834 /* Three registers of different lengths. */
4835 int src1_wide;
4836 int src2_wide;
4837 int prewiden;
4838 /* prewiden, src1_wide, src2_wide */
4839 static const int neon_3reg_wide[16][3] = {
4840 {1, 0, 0}, /* VADDL */
4841 {1, 1, 0}, /* VADDW */
4842 {1, 0, 0}, /* VSUBL */
4843 {1, 1, 0}, /* VSUBW */
4844 {0, 1, 1}, /* VADDHN */
4845 {0, 0, 0}, /* VABAL */
4846 {0, 1, 1}, /* VSUBHN */
4847 {0, 0, 0}, /* VABDL */
4848 {0, 0, 0}, /* VMLAL */
4849 {0, 0, 0}, /* VQDMLAL */
4850 {0, 0, 0}, /* VMLSL */
4851 {0, 0, 0}, /* VQDMLSL */
4852 {0, 0, 0}, /* Integer VMULL */
4853 {0, 0, 0}, /* VQDMULL */
4854 {0, 0, 0} /* Polynomial VMULL */
4855 };
4856
4857 prewiden = neon_3reg_wide[op][0];
4858 src1_wide = neon_3reg_wide[op][1];
4859 src2_wide = neon_3reg_wide[op][2];
4860
ad69471c
PB		 4861 if (size == 0 && (op == 9 || op == 11 || op == 13))
4862 return 1;
4863
9ee6e8bb
PB		 4864 /* Avoid overlapping operands. Wide source operands are
4865 always aligned so will never overlap with wide
4866 destinations in problematic ways. */
8f8e3aa4
PB		 4867 if (rd == rm && !src2_wide) {
4868 NEON_GET_REG(T0, rm, 1);
4869 gen_neon_movl_scratch_T0(2);
4870 } else if (rd == rn && !src1_wide) {
4871 NEON_GET_REG(T0, rn, 1);
4872 gen_neon_movl_scratch_T0(2);
9ee6e8bb
PB		 4873 }
4874 for (pass = 0; pass < 2; pass++) {
ad69471c
PB		 4875 if (src1_wide) {
4876 neon_load_reg64(cpu_V0, rn + pass);
9ee6e8bb 4877 } else {
ad69471c
PB		 4878 if (pass == 1 && rd == rn) {
4879 gen_neon_movl_T0_scratch(2);
4880 tmp = new_tmp();
4881 tcg_gen_mov_i32(tmp, cpu_T[0]);
9ee6e8bb 4882 } else {
ad69471c
PB		 4883 tmp = neon_load_reg(rn, pass);
4884 }
4885 if (prewiden) {
4886 gen_neon_widen(cpu_V0, tmp, size, u);
9ee6e8bb
PB		 4887 }
4888 }
ad69471c
PB		 4889 if (src2_wide) {
4890 neon_load_reg64(cpu_V1, rm + pass);
9ee6e8bb 4891 } else {
ad69471c 4892 if (pass == 1 && rd == rm) {
8f8e3aa4 4893 gen_neon_movl_T0_scratch(2);
ad69471c
PB		 4894 tmp2 = new_tmp();
4895 tcg_gen_mov_i32(tmp2, cpu_T[0]);
9ee6e8bb 4896 } else {
ad69471c
PB		 4897 tmp2 = neon_load_reg(rm, pass);
4898 }
4899 if (prewiden) {
4900 gen_neon_widen(cpu_V1, tmp2, size, u);
9ee6e8bb 4901 }
9ee6e8bb
PB		 4902 }
4903 switch (op) {
4904 case 0: case 1: case 4: /* VADDL, VADDW, VADDHN, VRADDHN */
ad69471c 4905 gen_neon_addl(size);
9ee6e8bb
PB		 4906 break;
4907 case 2: case 3: case 6: /* VSUBL, VSUBW, VSUBHL, VRSUBHL */
ad69471c 4908 gen_neon_subl(size);
9ee6e8bb
PB		 4909 break;
4910 case 5: case 7: /* VABAL, VABDL */
4911 switch ((size << 1) | u) {
ad69471c
PB		 4912 case 0:
4913 gen_helper_neon_abdl_s16(cpu_V0, tmp, tmp2);
4914 break;
4915 case 1:
4916 gen_helper_neon_abdl_u16(cpu_V0, tmp, tmp2);
4917 break;
4918 case 2:
4919 gen_helper_neon_abdl_s32(cpu_V0, tmp, tmp2);
4920 break;
4921 case 3:
4922 gen_helper_neon_abdl_u32(cpu_V0, tmp, tmp2);
4923 break;
4924 case 4:
4925 gen_helper_neon_abdl_s64(cpu_V0, tmp, tmp2);
4926 break;
4927 case 5:
4928 gen_helper_neon_abdl_u64(cpu_V0, tmp, tmp2);
4929 break;
9ee6e8bb
PB		 4930 default: abort();
4931 }
ad69471c
PB		 4932 dead_tmp(tmp2);
4933 dead_tmp(tmp);
9ee6e8bb
PB		 4934 break;
4935 case 8: case 9: case 10: case 11: case 12: case 13:
4936 /* VMLAL, VQDMLAL, VMLSL, VQDMLSL, VMULL, VQDMULL */
ad69471c 4937 gen_neon_mull(cpu_V0, tmp, tmp2, size, u);
9ee6e8bb
PB		 4938 break;
4939 case 14: /* Polynomial VMULL */
4940 cpu_abort(env, "Polynomial VMULL not implemented");
4941
4942 default: /* 15 is RESERVED. */
4943 return 1;
4944 }
4945 if (op == 5 || op == 13 || (op >= 8 && op <= 11)) {
4946 /* Accumulate. */
4947 if (op == 10 || op == 11) {
ad69471c 4948 gen_neon_negl(cpu_V0, size);
9ee6e8bb
PB		 4949 }
4950
9ee6e8bb 4951 if (op != 13) {
ad69471c 4952 neon_load_reg64(cpu_V1, rd + pass);
9ee6e8bb
PB		 4953 }
4954
4955 switch (op) {
4956 case 5: case 8: case 10: /* VABAL, VMLAL, VMLSL */
ad69471c 4957 gen_neon_addl(size);
9ee6e8bb
PB		 4958 break;
4959 case 9: case 11: /* VQDMLAL, VQDMLSL */
ad69471c
PB		 4960 gen_neon_addl_saturate(cpu_V0, cpu_V0, size);
4961 gen_neon_addl_saturate(cpu_V0, cpu_V1, size);
4962 break;
9ee6e8bb
PB		 4963 /* Fall through. */
4964 case 13: /* VQDMULL */
ad69471c 4965 gen_neon_addl_saturate(cpu_V0, cpu_V0, size);
9ee6e8bb
PB		 4966 break;
4967 default:
4968 abort();
4969 }
ad69471c 4970 neon_store_reg64(cpu_V0, rd + pass);
9ee6e8bb
PB		 4971 } else if (op == 4 || op == 6) {
4972 /* Narrowing operation. */
ad69471c 4973 tmp = new_tmp();
9ee6e8bb
PB		 4974 if (u) {
4975 switch (size) {
ad69471c
PB		 4976 case 0:
4977 gen_helper_neon_narrow_high_u8(tmp, cpu_V0);
4978 break;
4979 case 1:
4980 gen_helper_neon_narrow_high_u16(tmp, cpu_V0);
4981 break;
4982 case 2:
4983 tcg_gen_shri_i64(cpu_V0, cpu_V0, 32);
4984 tcg_gen_trunc_i64_i32(tmp, cpu_V0);
4985 break;
9ee6e8bb
PB		 4986 default: abort();
4987 }
4988 } else {
4989 switch (size) {
ad69471c
PB		 4990 case 0:
4991 gen_helper_neon_narrow_round_high_u8(tmp, cpu_V0);
4992 break;
4993 case 1:
4994 gen_helper_neon_narrow_round_high_u16(tmp, cpu_V0);
4995 break;
4996 case 2:
4997 tcg_gen_addi_i64(cpu_V0, cpu_V0, 1u << 31);
4998 tcg_gen_shri_i64(cpu_V0, cpu_V0, 32);
4999 tcg_gen_trunc_i64_i32(tmp, cpu_V0);
5000 break;
9ee6e8bb
PB		 5001 default: abort();
5002 }
5003 }
ad69471c
PB		 5004 if (pass == 0) {
5005 tmp3 = tmp;
5006 } else {
5007 neon_store_reg(rd, 0, tmp3);
5008 neon_store_reg(rd, 1, tmp);
5009 }
9ee6e8bb
PB		 5010 } else {
5011 /* Write back the result. */
ad69471c 5012 neon_store_reg64(cpu_V0, rd + pass);
9ee6e8bb
PB		 5013 }
5014 }
5015 } else {
5016 /* Two registers and a scalar. */
5017 switch (op) {
5018 case 0: /* Integer VMLA scalar */
5019 case 1: /* Float VMLA scalar */
5020 case 4: /* Integer VMLS scalar */
5021 case 5: /* Floating point VMLS scalar */
5022 case 8: /* Integer VMUL scalar */
5023 case 9: /* Floating point VMUL scalar */
5024 case 12: /* VQDMULH scalar */
5025 case 13: /* VQRDMULH scalar */
5026 gen_neon_get_scalar(size, rm);
8f8e3aa4 5027 gen_neon_movl_scratch_T0(0);
9ee6e8bb
PB		 5028 for (pass = 0; pass < (u ? 4 : 2); pass++) {
5029 if (pass != 0)
8f8e3aa4 5030 gen_neon_movl_T0_scratch(0);
9ee6e8bb
PB		 5031 NEON_GET_REG(T1, rn, pass);
5032 if (op == 12) {
5033 if (size == 1) {
ad69471c 5034 gen_helper_neon_qdmulh_s16(CPU_T0E01);
9ee6e8bb 5035 } else {
ad69471c 5036 gen_helper_neon_qdmulh_s32(CPU_T0E01);
9ee6e8bb
PB		 5037 }
5038 } else if (op == 13) {
5039 if (size == 1) {
ad69471c 5040 gen_helper_neon_qrdmulh_s16(CPU_T0E01);
9ee6e8bb 5041 } else {
ad69471c 5042 gen_helper_neon_qrdmulh_s32(CPU_T0E01);
9ee6e8bb
PB		 5043 }
5044 } else if (op & 1) {
ad69471c 5045 gen_helper_neon_mul_f32(CPU_T001);
9ee6e8bb
PB		 5046 } else {
5047 switch (size) {
ad69471c
PB		 5048 case 0: gen_helper_neon_mul_u8(CPU_T001); break;
5049 case 1: gen_helper_neon_mul_u16(CPU_T001); break;
9ee6e8bb
PB		 5050 case 2: gen_op_mul_T0_T1(); break;
5051 default: return 1;
5052 }
5053 }
5054 if (op < 8) {
5055 /* Accumulate. */
5056 NEON_GET_REG(T1, rd, pass);
5057 switch (op) {
5058 case 0:
5059 gen_neon_add(size);
5060 break;
5061 case 1:
ad69471c 5062 gen_helper_neon_add_f32(CPU_T001);
9ee6e8bb
PB		 5063 break;
5064 case 4:
ad69471c 5065 gen_neon_rsb(size);
9ee6e8bb
PB		 5066 break;
5067 case 5:
ad69471c 5068 gen_helper_neon_sub_f32(cpu_T[0], cpu_T[1], cpu_T[0]);
9ee6e8bb
PB		 5069 break;
5070 default:
5071 abort();
5072 }
5073 }
5074 NEON_SET_REG(T0, rd, pass);
5075 }
5076 break;
5077 case 2: /* VMLAL sclar */
5078 case 3: /* VQDMLAL scalar */
5079 case 6: /* VMLSL scalar */
5080 case 7: /* VQDMLSL scalar */
5081 case 10: /* VMULL scalar */
5082 case 11: /* VQDMULL scalar */
ad69471c
PB		 5083 if (size == 0 && (op == 3 || op == 7 || op == 11))
5084 return 1;
5085
9ee6e8bb 5086 gen_neon_get_scalar(size, rm);
ad69471c
PB		 5087 NEON_GET_REG(T1, rn, 1);
5088
9ee6e8bb 5089 for (pass = 0; pass < 2; pass++) {
ad69471c
PB		 5090 if (pass == 0) {
5091 tmp = neon_load_reg(rn, 0);
9ee6e8bb 5092 } else {
ad69471c
PB		 5093 tmp = new_tmp();
5094 tcg_gen_mov_i32(tmp, cpu_T[1]);
9ee6e8bb 5095 }
ad69471c
PB		 5096 tmp2 = new_tmp();
5097 tcg_gen_mov_i32(tmp2, cpu_T[0]);
5098 gen_neon_mull(cpu_V0, tmp, tmp2, size, u);
9ee6e8bb 5099 if (op == 6 || op == 7) {
ad69471c
PB		 5100 gen_neon_negl(cpu_V0, size);
5101 }
5102 if (op != 11) {
5103 neon_load_reg64(cpu_V1, rd + pass);
9ee6e8bb 5104 }
9ee6e8bb
PB		 5105 switch (op) {
5106 case 2: case 6:
ad69471c 5107 gen_neon_addl(size);
9ee6e8bb
PB		 5108 break;
5109 case 3: case 7:
ad69471c
PB		 5110 gen_neon_addl_saturate(cpu_V0, cpu_V0, size);
5111 gen_neon_addl_saturate(cpu_V0, cpu_V1, size);
9ee6e8bb
PB		 5112 break;
5113 case 10:
5114 /* no-op */
5115 break;
5116 case 11:
ad69471c 5117 gen_neon_addl_saturate(cpu_V0, cpu_V0, size);
9ee6e8bb
PB		 5118 break;
5119 default:
5120 abort();
5121 }
ad69471c 5122 neon_store_reg64(cpu_V0, rd + pass);
9ee6e8bb
PB		 5123 }
5124 break;
5125 default: /* 14 and 15 are RESERVED */
5126 return 1;
5127 }
5128 }
5129 } else { /* size == 3 */
5130 if (!u) {
5131 /* Extract. */
9ee6e8bb 5132 imm = (insn >> 8) & 0xf;
ad69471c
PB		 5133 count = q + 1;
5134
5135 if (imm > 7 && !q)
5136 return 1;
5137
5138 if (imm == 0) {
5139 neon_load_reg64(cpu_V0, rn);
5140 if (q) {
5141 neon_load_reg64(cpu_V1, rn + 1);
9ee6e8bb 5142 }
ad69471c
PB		 5143 } else if (imm == 8) {
5144 neon_load_reg64(cpu_V0, rn + 1);
5145 if (q) {
5146 neon_load_reg64(cpu_V1, rm);
9ee6e8bb 5147 }
ad69471c
PB		 5148 } else if (q) {
5149 tmp = tcg_temp_new(TCG_TYPE_I64);
5150 if (imm < 8) {
5151 neon_load_reg64(cpu_V0, rn);
5152 neon_load_reg64(tmp, rn + 1);
5153 } else {
5154 neon_load_reg64(cpu_V0, rn + 1);
5155 neon_load_reg64(tmp, rm);
5156 }
5157 tcg_gen_shri_i64(cpu_V0, cpu_V0, (imm & 7) * 8);
5158 tcg_gen_shli_i64(cpu_V1, tmp, 64 - ((imm & 7) * 8));
5159 tcg_gen_or_i64(cpu_V0, cpu_V0, cpu_V1);
5160 if (imm < 8) {
5161 neon_load_reg64(cpu_V1, rm);
9ee6e8bb 5162 } else {
ad69471c
PB		 5163 neon_load_reg64(cpu_V1, rm + 1);
5164 imm -= 8;
9ee6e8bb 5165 }
ad69471c
PB		 5166 tcg_gen_shli_i64(cpu_V1, cpu_V1, 64 - (imm * 8));
5167 tcg_gen_shri_i64(tmp, tmp, imm * 8);
5168 tcg_gen_or_i64(cpu_V1, cpu_V1, tmp);
5169 } else {
5170 neon_load_reg64(cpu_V0, rn);
5171 tcg_gen_shri_i32(cpu_V0, cpu_V0, imm * 8);
5172 neon_load_reg64(cpu_V1, rm);
5173 tcg_gen_shli_i32(cpu_V1, cpu_V1, 64 - (imm * 8));
5174 tcg_gen_or_i64(cpu_V0, cpu_V0, cpu_V1);
5175 }
5176 neon_store_reg64(cpu_V0, rd);
5177 if (q) {
5178 neon_store_reg64(cpu_V1, rd + 1);
9ee6e8bb
PB		 5179 }
5180 } else if ((insn & (1 << 11)) == 0) {
5181 /* Two register misc. */
5182 op = ((insn >> 12) & 0x30) | ((insn >> 7) & 0xf);
5183 size = (insn >> 18) & 3;
5184 switch (op) {
5185 case 0: /* VREV64 */
5186 if (size == 3)
5187 return 1;
5188 for (pass = 0; pass < (q ? 2 : 1); pass++) {
5189 NEON_GET_REG(T0, rm, pass * 2);
5190 NEON_GET_REG(T1, rm, pass * 2 + 1);
5191 switch (size) {
b0109805 5192 case 0: tcg_gen_bswap_i32(cpu_T[0], cpu_T[0]); break;
8f01245e 5193 case 1: gen_swap_half(cpu_T[0]); break;
9ee6e8bb
PB		 5194 case 2: /* no-op */ break;
5195 default: abort();
5196 }
5197 NEON_SET_REG(T0, rd, pass * 2 + 1);
5198 if (size == 2) {
5199 NEON_SET_REG(T1, rd, pass * 2);
5200 } else {
5201 gen_op_movl_T0_T1();
5202 switch (size) {
b0109805 5203 case 0: tcg_gen_bswap_i32(cpu_T[0], cpu_T[0]); break;
8f01245e 5204 case 1: gen_swap_half(cpu_T[0]); break;
9ee6e8bb
PB		 5205 default: abort();
5206 }
5207 NEON_SET_REG(T0, rd, pass * 2);
5208 }
5209 }
5210 break;
5211 case 4: case 5: /* VPADDL */
5212 case 12: case 13: /* VPADAL */
9ee6e8bb
PB		 5213 if (size == 3)
5214 return 1;
ad69471c
PB		 5215 for (pass = 0; pass < q + 1; pass++) {
5216 tmp = neon_load_reg(rm, pass * 2);
5217 gen_neon_widen(cpu_V0, tmp, size, op & 1);
5218 tmp = neon_load_reg(rm, pass * 2 + 1);
5219 gen_neon_widen(cpu_V1, tmp, size, op & 1);
5220 switch (size) {
5221 case 0: gen_helper_neon_paddl_u16(CPU_V001); break;
5222 case 1: gen_helper_neon_paddl_u32(CPU_V001); break;
5223 case 2: tcg_gen_add_i64(CPU_V001); break;
5224 default: abort();
5225 }
9ee6e8bb
PB		 5226 if (op >= 12) {
5227 /* Accumulate. */
ad69471c
PB		 5228 neon_load_reg64(cpu_V1, rd + pass);
5229 gen_neon_addl(size);
9ee6e8bb 5230 }
ad69471c 5231 neon_store_reg64(cpu_V0, rd + pass);
9ee6e8bb
PB		 5232 }
5233 break;
5234 case 33: /* VTRN */
5235 if (size == 2) {
5236 for (n = 0; n < (q ? 4 : 2); n += 2) {
5237 NEON_GET_REG(T0, rm, n);
5238 NEON_GET_REG(T1, rd, n + 1);
5239 NEON_SET_REG(T1, rm, n);
5240 NEON_SET_REG(T0, rd, n + 1);
5241 }
5242 } else {
5243 goto elementwise;
5244 }
5245 break;
5246 case 34: /* VUZP */
5247 /* Reg Before After
5248 Rd A3 A2 A1 A0 B2 B0 A2 A0
5249 Rm B3 B2 B1 B0 B3 B1 A3 A1
5250 */
5251 if (size == 3)
5252 return 1;
5253 gen_neon_unzip(rd, q, 0, size);
5254 gen_neon_unzip(rm, q, 4, size);
5255 if (q) {
5256 static int unzip_order_q[8] =
5257 {0, 2, 4, 6, 1, 3, 5, 7};
5258 for (n = 0; n < 8; n++) {
5259 int reg = (n < 4) ? rd : rm;
5260 gen_neon_movl_T0_scratch(unzip_order_q[n]);
5261 NEON_SET_REG(T0, reg, n % 4);
5262 }
5263 } else {
5264 static int unzip_order[4] =
5265 {0, 4, 1, 5};
5266 for (n = 0; n < 4; n++) {
5267 int reg = (n < 2) ? rd : rm;
5268 gen_neon_movl_T0_scratch(unzip_order[n]);
5269 NEON_SET_REG(T0, reg, n % 2);
5270 }
5271 }
5272 break;
5273 case 35: /* VZIP */
5274 /* Reg Before After
5275 Rd A3 A2 A1 A0 B1 A1 B0 A0
5276 Rm B3 B2 B1 B0 B3 A3 B2 A2
5277 */
5278 if (size == 3)
5279 return 1;
5280 count = (q ? 4 : 2);
5281 for (n = 0; n < count; n++) {
5282 NEON_GET_REG(T0, rd, n);
5283 NEON_GET_REG(T1, rd, n);
5284 switch (size) {
ad69471c
PB		 5285 case 0: gen_helper_neon_zip_u8(); break;
5286 case 1: gen_helper_neon_zip_u16(); break;
9ee6e8bb
PB		 5287 case 2: /* no-op */; break;
5288 default: abort();
5289 }
5290 gen_neon_movl_scratch_T0(n * 2);
5291 gen_neon_movl_scratch_T1(n * 2 + 1);
5292 }
5293 for (n = 0; n < count * 2; n++) {
5294 int reg = (n < count) ? rd : rm;
5295 gen_neon_movl_T0_scratch(n);
5296 NEON_SET_REG(T0, reg, n % count);
5297 }
5298 break;
5299 case 36: case 37: /* VMOVN, VQMOVUN, VQMOVN */
ad69471c
PB		 5300 if (size == 3)
5301 return 1;
9ee6e8bb 5302 for (pass = 0; pass < 2; pass++) {
ad69471c
PB		 5303 neon_load_reg64(cpu_V0, rm + pass);
5304 tmp = new_tmp();
9ee6e8bb 5305 if (op == 36 && q == 0) {
ad69471c 5306 gen_neon_narrow(size, tmp, cpu_V0);
9ee6e8bb 5307 } else if (q) {
ad69471c 5308 gen_neon_narrow_satu(size, tmp, cpu_V0);
9ee6e8bb 5309 } else {
ad69471c
PB		 5310 gen_neon_narrow_sats(size, tmp, cpu_V0);
5311 }
5312 if (pass == 0) {
5313 tmp2 = tmp;
5314 } else {
5315 neon_store_reg(rd, 0, tmp2);
5316 neon_store_reg(rd, 1, tmp);
9ee6e8bb 5317 }
9ee6e8bb
PB		 5318 }
5319 break;
5320 case 38: /* VSHLL */
ad69471c 5321 if (q || size == 3)
9ee6e8bb 5322 return 1;
ad69471c
PB		 5323 tmp = neon_load_reg(rm, 0);
5324 tmp2 = neon_load_reg(rm, 1);
9ee6e8bb 5325 for (pass = 0; pass < 2; pass++) {
ad69471c
PB		 5326 if (pass == 1)
5327 tmp = tmp2;
5328 gen_neon_widen(cpu_V0, tmp, size, 1);
5329 neon_store_reg64(cpu_V0, rd + pass);
9ee6e8bb
PB		 5330 }
5331 break;
5332 default:
5333 elementwise:
5334 for (pass = 0; pass < (q ? 4 : 2); pass++) {
5335 if (op == 30 || op == 31 || op >= 58) {
4373f3ce
PB		 5336 tcg_gen_ld_f32(cpu_F0s, cpu_env,
5337 neon_reg_offset(rm, pass));
9ee6e8bb
PB		 5338 } else {
5339 NEON_GET_REG(T0, rm, pass);
5340 }
5341 switch (op) {
5342 case 1: /* VREV32 */
5343 switch (size) {
b0109805 5344 case 0: tcg_gen_bswap_i32(cpu_T[0], cpu_T[0]); break;
8f01245e 5345 case 1: gen_swap_half(cpu_T[0]); break;
9ee6e8bb
PB		 5346 default: return 1;
5347 }
5348 break;
5349 case 2: /* VREV16 */
5350 if (size != 0)
5351 return 1;
3670669c 5352 gen_rev16(cpu_T[0]);
9ee6e8bb 5353 break;
9ee6e8bb
PB		 5354 case 8: /* CLS */
5355 switch (size) {
ad69471c
PB		 5356 case 0: gen_helper_neon_cls_s8(cpu_T[0], cpu_T[0]); break;
5357 case 1: gen_helper_neon_cls_s16(cpu_T[0], cpu_T[0]); break;
5358 case 2: gen_helper_neon_cls_s32(cpu_T[0], cpu_T[0]); break;
9ee6e8bb
PB		 5359 default: return 1;
5360 }
5361 break;
5362 case 9: /* CLZ */
5363 switch (size) {
ad69471c
PB		 5364 case 0: gen_helper_neon_clz_u8(cpu_T[0], cpu_T[0]); break;
5365 case 1: gen_helper_neon_clz_u16(cpu_T[0], cpu_T[0]); break;
1497c961 5366 case 2: gen_helper_clz(cpu_T[0], cpu_T[0]); break;
9ee6e8bb
PB		 5367 default: return 1;
5368 }
5369 break;
5370 case 10: /* CNT */
5371 if (size != 0)
5372 return 1;
ad69471c 5373 gen_helper_neon_cnt_u8(cpu_T[0], cpu_T[0]);
9ee6e8bb
PB		 5374 break;
5375 case 11: /* VNOT */
5376 if (size != 0)
5377 return 1;
5378 gen_op_notl_T0();
5379 break;
5380 case 14: /* VQABS */
5381 switch (size) {
ad69471c
PB		 5382 case 0: gen_helper_neon_qabs_s8(cpu_T[0], cpu_env, cpu_T[0]); break;
5383 case 1: gen_helper_neon_qabs_s16(cpu_T[0], cpu_env, cpu_T[0]); break;
5384 case 2: gen_helper_neon_qabs_s32(cpu_T[0], cpu_env, cpu_T[0]); break;
9ee6e8bb
PB		 5385 default: return 1;
5386 }
5387 break;
5388 case 15: /* VQNEG */
5389 switch (size) {
ad69471c
PB		 5390 case 0: gen_helper_neon_qneg_s8(cpu_T[0], cpu_env, cpu_T[0]); break;
5391 case 1: gen_helper_neon_qneg_s16(cpu_T[0], cpu_env, cpu_T[0]); break;
5392 case 2: gen_helper_neon_qneg_s32(cpu_T[0], cpu_env, cpu_T[0]); break;
9ee6e8bb
PB		 5393 default: return 1;
5394 }
5395 break;
5396 case 16: case 19: /* VCGT #0, VCLE #0 */
5397 gen_op_movl_T1_im(0);
5398 switch(size) {
ad69471c
PB		 5399 case 0: gen_helper_neon_cgt_s8(CPU_T001); break;
5400 case 1: gen_helper_neon_cgt_s16(CPU_T001); break;
5401 case 2: gen_helper_neon_cgt_s32(CPU_T001); break;
9ee6e8bb
PB		 5402 default: return 1;
5403 }
5404 if (op == 19)
5405 gen_op_notl_T0();
5406 break;
5407 case 17: case 20: /* VCGE #0, VCLT #0 */
5408 gen_op_movl_T1_im(0);
5409 switch(size) {
ad69471c
PB		 5410 case 0: gen_helper_neon_cge_s8(CPU_T001); break;
5411 case 1: gen_helper_neon_cge_s16(CPU_T001); break;
5412 case 2: gen_helper_neon_cge_s32(CPU_T001); break;
9ee6e8bb
PB		 5413 default: return 1;
5414 }
5415 if (op == 20)
5416 gen_op_notl_T0();
5417 break;
5418 case 18: /* VCEQ #0 */
5419 gen_op_movl_T1_im(0);
5420 switch(size) {
ad69471c
PB		 5421 case 0: gen_helper_neon_ceq_u8(CPU_T001); break;
5422 case 1: gen_helper_neon_ceq_u16(CPU_T001); break;
5423 case 2: gen_helper_neon_ceq_u32(CPU_T001); break;
9ee6e8bb
PB		 5424 default: return 1;
5425 }
5426 break;
5427 case 22: /* VABS */
5428 switch(size) {
ad69471c
PB		 5429 case 0: gen_helper_neon_abs_s8(cpu_T[0], cpu_T[0]); break;
5430 case 1: gen_helper_neon_abs_s16(cpu_T[0], cpu_T[0]); break;
5431 case 2: tcg_gen_abs_i32(cpu_T[0], cpu_T[0]); break;
9ee6e8bb
PB		 5432 default: return 1;
5433 }
5434 break;
5435 case 23: /* VNEG */
5436 gen_op_movl_T1_im(0);
ad69471c
PB		 5437 if (size == 3)
5438 return 1;
5439 gen_neon_rsb(size);
9ee6e8bb
PB		 5440 break;
5441 case 24: case 27: /* Float VCGT #0, Float VCLE #0 */
5442 gen_op_movl_T1_im(0);
ad69471c 5443 gen_helper_neon_cgt_f32(CPU_T001);
9ee6e8bb
PB		 5444 if (op == 27)
5445 gen_op_notl_T0();
5446 break;
5447 case 25: case 28: /* Float VCGE #0, Float VCLT #0 */
5448 gen_op_movl_T1_im(0);
ad69471c 5449 gen_helper_neon_cge_f32(CPU_T001);
9ee6e8bb
PB		 5450 if (op == 28)
5451 gen_op_notl_T0();
5452 break;
5453 case 26: /* Float VCEQ #0 */
5454 gen_op_movl_T1_im(0);
ad69471c 5455 gen_helper_neon_ceq_f32(CPU_T001);
9ee6e8bb
PB		 5456 break;
5457 case 30: /* Float VABS */
4373f3ce 5458 gen_vfp_abs(0);
9ee6e8bb
PB		 5459 break;
5460 case 31: /* Float VNEG */
4373f3ce 5461 gen_vfp_neg(0);
9ee6e8bb
PB		 5462 break;
5463 case 32: /* VSWP */
5464 NEON_GET_REG(T1, rd, pass);
5465 NEON_SET_REG(T1, rm, pass);
5466 break;
5467 case 33: /* VTRN */
5468 NEON_GET_REG(T1, rd, pass);
5469 switch (size) {
ad69471c
PB		 5470 case 0: gen_helper_neon_trn_u8(); break;
5471 case 1: gen_helper_neon_trn_u16(); break;
9ee6e8bb
PB		 5472 case 2: abort();
5473 default: return 1;
5474 }
5475 NEON_SET_REG(T1, rm, pass);
5476 break;
5477 case 56: /* Integer VRECPE */
4373f3ce 5478 gen_helper_recpe_u32(cpu_T[0], cpu_T[0], cpu_env);
9ee6e8bb
PB		 5479 break;
5480 case 57: /* Integer VRSQRTE */
4373f3ce 5481 gen_helper_rsqrte_u32(cpu_T[0], cpu_T[0], cpu_env);
9ee6e8bb
PB		 5482 break;
5483 case 58: /* Float VRECPE */
4373f3ce 5484 gen_helper_recpe_f32(cpu_F0s, cpu_F0s, cpu_env);
9ee6e8bb
PB		 5485 break;
5486 case 59: /* Float VRSQRTE */
4373f3ce 5487 gen_helper_rsqrte_f32(cpu_F0s, cpu_F0s, cpu_env);
9ee6e8bb
PB		 5488 break;
5489 case 60: /* VCVT.F32.S32 */
4373f3ce 5490 gen_vfp_tosiz(0);
9ee6e8bb
PB		 5491 break;
5492 case 61: /* VCVT.F32.U32 */
4373f3ce 5493 gen_vfp_touiz(0);
9ee6e8bb
PB		 5494 break;
5495 case 62: /* VCVT.S32.F32 */
4373f3ce 5496 gen_vfp_sito(0);
9ee6e8bb
PB		 5497 break;
5498 case 63: /* VCVT.U32.F32 */
4373f3ce 5499 gen_vfp_uito(0);
9ee6e8bb
PB		 5500 break;
5501 default:
5502 /* Reserved: 21, 29, 39-56 */
5503 return 1;
5504 }
5505 if (op == 30 || op == 31 || op >= 58) {
4373f3ce
PB		 5506 tcg_gen_st_f32(cpu_F0s, cpu_env,
5507 neon_reg_offset(rd, pass));
9ee6e8bb
PB		 5508 } else {
5509 NEON_SET_REG(T0, rd, pass);
5510 }
5511 }
5512 break;
5513 }
5514 } else if ((insn & (1 << 10)) == 0) {
5515 /* VTBL, VTBX. */
5516 n = (insn >> 5) & 0x18;
9ee6e8bb 5517 if (insn & (1 << 6)) {
8f8e3aa4 5518 tmp = neon_load_reg(rd, 0);
9ee6e8bb 5519 } else {
8f8e3aa4
PB		 5520 tmp = new_tmp();
5521 tcg_gen_movi_i32(tmp, 0);
9ee6e8bb 5522 }
8f8e3aa4
PB		 5523 tmp2 = neon_load_reg(rm, 0);
5524 gen_helper_neon_tbl(tmp2, tmp2, tmp, tcg_const_i32(rn),
5525 tcg_const_i32(n));
9ee6e8bb 5526 if (insn & (1 << 6)) {
8f8e3aa4 5527 tmp = neon_load_reg(rd, 1);
9ee6e8bb 5528 } else {
8f8e3aa4
PB		 5529 tmp = new_tmp();
5530 tcg_gen_movi_i32(tmp, 0);
9ee6e8bb 5531 }
8f8e3aa4
PB		 5532 tmp3 = neon_load_reg(rm, 1);
5533 gen_helper_neon_tbl(tmp3, tmp3, tmp, tcg_const_i32(rn),
5534 tcg_const_i32(n));
5535 neon_store_reg(rd, 0, tmp2);
5536 neon_store_reg(rd, 1, tmp2);
9ee6e8bb
PB		 5537 } else if ((insn & 0x380) == 0) {
5538 /* VDUP */
5539 if (insn & (1 << 19)) {
5540 NEON_SET_REG(T0, rm, 1);
5541 } else {
5542 NEON_SET_REG(T0, rm, 0);
5543 }
5544 if (insn & (1 << 16)) {
ad69471c 5545 gen_neon_dup_u8(cpu_T[0], ((insn >> 17) & 3) * 8);
9ee6e8bb
PB		 5546 } else if (insn & (1 << 17)) {
5547 if ((insn >> 18) & 1)
ad69471c 5548 gen_neon_dup_high16(cpu_T[0]);
9ee6e8bb 5549 else
ad69471c 5550 gen_neon_dup_low16(cpu_T[0]);
9ee6e8bb
PB		 5551 }
5552 for (pass = 0; pass < (q ? 4 : 2); pass++) {
5553 NEON_SET_REG(T0, rd, pass);
5554 }
5555 } else {
5556 return 1;
5557 }
5558 }
5559 }
5560 return 0;
5561}
5562
5563static int disas_coproc_insn(CPUState * env, DisasContext *s, uint32_t insn)
5564{
5565 int cpnum;
5566
5567 cpnum = (insn >> 8) & 0xf;
5568 if (arm_feature(env, ARM_FEATURE_XSCALE)
5569 && ((env->cp15.c15_cpar ^ 0x3fff) & (1 << cpnum)))
5570 return 1;
5571
5572 switch (cpnum) {
5573 case 0:
5574 case 1:
5575 if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
5576 return disas_iwmmxt_insn(env, s, insn);
5577 } else if (arm_feature(env, ARM_FEATURE_XSCALE)) {
5578 return disas_dsp_insn(env, s, insn);
5579 }
5580 return 1;
5581 case 10:
5582 case 11:
5583 return disas_vfp_insn (env, s, insn);
5584 case 15:
5585 return disas_cp15_insn (env, s, insn);
5586 default:
5587 /* Unknown coprocessor. See if the board has hooked it. */
5588 return disas_cp_insn (env, s, insn);
5589 }
5590}
5591
5e3f878a
PB		 5592
5593/* Store a 64-bit value to a register pair. Clobbers val. */
5594static void gen_storeq_reg(DisasContext *s, int rlow, int rhigh, TCGv val)
5595{
5596 TCGv tmp;
5597 tmp = new_tmp();
5598 tcg_gen_trunc_i64_i32(tmp, val);
5599 store_reg(s, rlow, tmp);
5600 tmp = new_tmp();
5601 tcg_gen_shri_i64(val, val, 32);
5602 tcg_gen_trunc_i64_i32(tmp, val);
5603 store_reg(s, rhigh, tmp);
5604}
5605
5606/* load a 32-bit value from a register and perform a 64-bit accumulate. */
5607static void gen_addq_lo(DisasContext *s, TCGv val, int rlow)
5608{
5609 TCGv tmp;
5610 TCGv tmp2;
5611
5612 /* Load 64-bit value rd:rn. */
5613 tmp = tcg_temp_new(TCG_TYPE_I64);
5614 tmp2 = load_reg(s, rlow);
5615 tcg_gen_extu_i32_i64(tmp, tmp2);
5616 dead_tmp(tmp2);
5617 tcg_gen_add_i64(val, val, tmp);
5618}
5619
5620/* load and add a 64-bit value from a register pair. */
5621static void gen_addq(DisasContext *s, TCGv val, int rlow, int rhigh)
5622{
5623 TCGv tmp;
5624 TCGv tmp2;
5625
5626 /* Load 64-bit value rd:rn. */
5627 tmp = tcg_temp_new(TCG_TYPE_I64);
5628 tmp2 = load_reg(s, rhigh);
5629 tcg_gen_extu_i32_i64(tmp, tmp2);
5630 dead_tmp(tmp2);
5631 tcg_gen_shli_i64(tmp, tmp, 32);
5632 tcg_gen_add_i64(val, val, tmp);
5633
5634 tmp2 = load_reg(s, rlow);
5635 tcg_gen_extu_i32_i64(tmp, tmp2);
5636 dead_tmp(tmp2);
5637 tcg_gen_add_i64(val, val, tmp);
5638}
5639
5640/* Set N and Z flags from a 64-bit value. */
5641static void gen_logicq_cc(TCGv val)
5642{
5643 TCGv tmp = new_tmp();
5644 gen_helper_logicq_cc(tmp, val);
6fbe23d5
PB		 5645 gen_logic_CC(tmp);
5646 dead_tmp(tmp);
5e3f878a
PB		 5647}
5648
9ee6e8bb
PB		 5649static void disas_arm_insn(CPUState * env, DisasContext *s)
5650{
5651 unsigned int cond, insn, val, op1, i, shift, rm, rs, rn, rd, sh;
b26eefb6 5652 TCGv tmp;
3670669c 5653 TCGv tmp2;
6ddbc6e4 5654 TCGv tmp3;
b0109805 5655 TCGv addr;
9ee6e8bb
PB		 5656
5657 insn = ldl_code(s->pc);
5658 s->pc += 4;
5659
5660 /* M variants do not implement ARM mode. */
5661 if (IS_M(env))
5662 goto illegal_op;
5663 cond = insn >> 28;
5664 if (cond == 0xf){
5665 /* Unconditional instructions. */
5666 if (((insn >> 25) & 7) == 1) {
5667 /* NEON Data processing. */
5668 if (!arm_feature(env, ARM_FEATURE_NEON))
5669 goto illegal_op;
5670
5671 if (disas_neon_data_insn(env, s, insn))
5672 goto illegal_op;
5673 return;
5674 }
5675 if ((insn & 0x0f100000) == 0x04000000) {
5676 /* NEON load/store. */
5677 if (!arm_feature(env, ARM_FEATURE_NEON))
5678 goto illegal_op;
5679
5680 if (disas_neon_ls_insn(env, s, insn))
5681 goto illegal_op;
5682 return;
5683 }
5684 if ((insn & 0x0d70f000) == 0x0550f000)
5685 return; /* PLD */
5686 else if ((insn & 0x0ffffdff) == 0x01010000) {
5687 ARCH(6);
5688 /* setend */
5689 if (insn & (1 << 9)) {
5690 /* BE8 mode not implemented. */
5691 goto illegal_op;
5692 }
5693 return;
5694 } else if ((insn & 0x0fffff00) == 0x057ff000) {
5695 switch ((insn >> 4) & 0xf) {
5696 case 1: /* clrex */
5697 ARCH(6K);
8f8e3aa4 5698 gen_helper_clrex(cpu_env);
9ee6e8bb
PB		 5699 return;
5700 case 4: /* dsb */
5701 case 5: /* dmb */
5702 case 6: /* isb */
5703 ARCH(7);
5704 /* We don't emulate caches so these are a no-op. */
5705 return;
5706 default:
5707 goto illegal_op;
5708 }
5709 } else if ((insn & 0x0e5fffe0) == 0x084d0500) {
5710 /* srs */
5711 uint32_t offset;
5712 if (IS_USER(s))
5713 goto illegal_op;
5714 ARCH(6);
5715 op1 = (insn & 0x1f);
5716 if (op1 == (env->uncached_cpsr & CPSR_M)) {
b0109805 5717 addr = load_reg(s, 13);
9ee6e8bb 5718 } else {
b0109805
PB		 5719 addr = new_tmp();
5720 gen_helper_get_r13_banked(addr, cpu_env, tcg_const_i32(op1));
9ee6e8bb
PB		 5721 }
5722 i = (insn >> 23) & 3;
5723 switch (i) {
5724 case 0: offset = -4; break; /* DA */
5725 case 1: offset = -8; break; /* DB */
5726 case 2: offset = 0; break; /* IA */
5727 case 3: offset = 4; break; /* IB */
5728 default: abort();
5729 }
5730 if (offset)
b0109805
PB		 5731 tcg_gen_addi_i32(addr, addr, offset);
5732 tmp = load_reg(s, 14);
5733 gen_st32(tmp, addr, 0);
5734 tmp = new_tmp();
5735 gen_helper_cpsr_read(tmp);
5736 tcg_gen_addi_i32(addr, addr, 4);
5737 gen_st32(tmp, addr, 0);
9ee6e8bb
PB		 5738 if (insn & (1 << 21)) {
5739 /* Base writeback. */
5740 switch (i) {
5741 case 0: offset = -8; break;
5742 case 1: offset = -4; break;
5743 case 2: offset = 4; break;
5744 case 3: offset = 0; break;
5745 default: abort();
5746 }
5747 if (offset)
b0109805 5748 tcg_gen_addi_i32(addr, tmp, offset);
9ee6e8bb
PB		 5749 if (op1 == (env->uncached_cpsr & CPSR_M)) {
5750 gen_movl_reg_T1(s, 13);
5751 } else {
b0109805 5752 gen_helper_set_r13_banked(cpu_env, tcg_const_i32(op1), cpu_T[1]);
9ee6e8bb 5753 }
b0109805
PB		 5754 } else {
5755 dead_tmp(addr);
9ee6e8bb
PB		 5756 }
5757 } else if ((insn & 0x0e5fffe0) == 0x081d0a00) {
5758 /* rfe */
5759 uint32_t offset;
5760 if (IS_USER(s))
5761 goto illegal_op;
5762 ARCH(6);
5763 rn = (insn >> 16) & 0xf;
b0109805 5764 addr = load_reg(s, rn);
9ee6e8bb
PB		 5765 i = (insn >> 23) & 3;
5766 switch (i) {
b0109805
PB		 5767 case 0: offset = -4; break; /* DA */
5768 case 1: offset = -8; break; /* DB */
5769 case 2: offset = 0; break; /* IA */
5770 case 3: offset = 4; break; /* IB */
9ee6e8bb
PB		 5771 default: abort();
5772 }
5773 if (offset)
b0109805
PB		 5774 tcg_gen_addi_i32(addr, addr, offset);
5775 /* Load PC into tmp and CPSR into tmp2. */
5776 tmp = gen_ld32(addr, 0);
5777 tcg_gen_addi_i32(addr, addr, 4);
5778 tmp2 = gen_ld32(addr, 0);
9ee6e8bb
PB		 5779 if (insn & (1 << 21)) {
5780 /* Base writeback. */
5781 switch (i) {
b0109805
PB		 5782 case 0: offset = -8; break;
5783 case 1: offset = -4; break;
5784 case 2: offset = 4; break;
5785 case 3: offset = 0; break;
9ee6e8bb
PB		 5786 default: abort();
5787 }
5788 if (offset)
b0109805
PB		 5789 tcg_gen_addi_i32(addr, addr, offset);
5790 store_reg(s, rn, addr);
5791 } else {
5792 dead_tmp(addr);
9ee6e8bb 5793 }
b0109805 5794 gen_rfe(s, tmp, tmp2);
9ee6e8bb
PB		 5795 } else if ((insn & 0x0e000000) == 0x0a000000) {
5796 /* branch link and change to thumb (blx <offset>) */
5797 int32_t offset;
5798
5799 val = (uint32_t)s->pc;
d9ba4830
PB		 5800 tmp = new_tmp();
5801 tcg_gen_movi_i32(tmp, val);
5802 store_reg(s, 14, tmp);
9ee6e8bb
PB		 5803 /* Sign-extend the 24-bit offset */
5804 offset = (((int32_t)insn) << 8) >> 8;
5805 /* offset * 4 + bit24 * 2 + (thumb bit) */
5806 val += (offset << 2) | ((insn >> 23) & 2) | 1;
5807 /* pipeline offset */
5808 val += 4;
d9ba4830 5809 gen_bx_im(s, val);
9ee6e8bb
PB		 5810 return;
5811 } else if ((insn & 0x0e000f00) == 0x0c000100) {
5812 if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
5813 /* iWMMXt register transfer. */
5814 if (env->cp15.c15_cpar & (1 << 1))
5815 if (!disas_iwmmxt_insn(env, s, insn))
5816 return;
5817 }
5818 } else if ((insn & 0x0fe00000) == 0x0c400000) {
5819 /* Coprocessor double register transfer. */
5820 } else if ((insn & 0x0f000010) == 0x0e000010) {
5821 /* Additional coprocessor register transfer. */
5822 } else if ((insn & 0x0ff10010) == 0x01000000) {
5823 uint32_t mask;
5824 uint32_t val;
5825 /* cps (privileged) */
5826 if (IS_USER(s))
5827 return;
5828 mask = val = 0;
5829 if (insn & (1 << 19)) {
5830 if (insn & (1 << 8))
5831 mask |= CPSR_A;
5832 if (insn & (1 << 7))
5833 mask |= CPSR_I;
5834 if (insn & (1 << 6))
5835 mask |= CPSR_F;
5836 if (insn & (1 << 18))
5837 val |= mask;
5838 }
5839 if (insn & (1 << 14)) {
5840 mask |= CPSR_M;
5841 val |= (insn & 0x1f);
5842 }
5843 if (mask) {
5844 gen_op_movl_T0_im(val);
5845 gen_set_psr_T0(s, mask, 0);
5846 }
5847 return;
5848 }
5849 goto illegal_op;
5850 }
5851 if (cond != 0xe) {
5852 /* if not always execute, we generate a conditional jump to
5853 next instruction */
5854 s->condlabel = gen_new_label();
d9ba4830 5855 gen_test_cc(cond ^ 1, s->condlabel);
9ee6e8bb
PB		 5856 s->condjmp = 1;
5857 }
5858 if ((insn & 0x0f900000) == 0x03000000) {
5859 if ((insn & (1 << 21)) == 0) {
5860 ARCH(6T2);
5861 rd = (insn >> 12) & 0xf;
5862 val = ((insn >> 4) & 0xf000) | (insn & 0xfff);
5863 if ((insn & (1 << 22)) == 0) {
5864 /* MOVW */
5e3f878a
PB		 5865 tmp = new_tmp();
5866 tcg_gen_movi_i32(tmp, val);
9ee6e8bb
PB		 5867 } else {
5868 /* MOVT */
5e3f878a
PB		 5869 tmp = load_reg(s, rd);
5870 tcg_gen_andi_i32(tmp, tmp, 0xffff);
5871 tcg_gen_ori_i32(tmp, tmp, val << 16);
9ee6e8bb 5872 }
5e3f878a 5873 store_reg(s, rd, tmp);
9ee6e8bb
PB		 5874 } else {
5875 if (((insn >> 12) & 0xf) != 0xf)
5876 goto illegal_op;
5877 if (((insn >> 16) & 0xf) == 0) {
5878 gen_nop_hint(s, insn & 0xff);
5879 } else {
5880 /* CPSR = immediate */
5881 val = insn & 0xff;
5882 shift = ((insn >> 8) & 0xf) * 2;
5883 if (shift)
5884 val = (val >> shift) | (val << (32 - shift));
5885 gen_op_movl_T0_im(val);
5886 i = ((insn & (1 << 22)) != 0);
5887 if (gen_set_psr_T0(s, msr_mask(env, s, (insn >> 16) & 0xf, i), i))
5888 goto illegal_op;
5889 }
5890 }
5891 } else if ((insn & 0x0f900000) == 0x01000000
5892 && (insn & 0x00000090) != 0x00000090) {
5893 /* miscellaneous instructions */
5894 op1 = (insn >> 21) & 3;
5895 sh = (insn >> 4) & 0xf;
5896 rm = insn & 0xf;
5897 switch (sh) {
5898 case 0x0: /* move program status register */
5899 if (op1 & 1) {
5900 /* PSR = reg */
5901 gen_movl_T0_reg(s, rm);
5902 i = ((op1 & 2) != 0);
5903 if (gen_set_psr_T0(s, msr_mask(env, s, (insn >> 16) & 0xf, i), i))
5904 goto illegal_op;
5905 } else {
5906 /* reg = PSR */
5907 rd = (insn >> 12) & 0xf;
5908 if (op1 & 2) {
5909 if (IS_USER(s))
5910 goto illegal_op;
d9ba4830 5911 tmp = load_cpu_field(spsr);
9ee6e8bb 5912 } else {
d9ba4830
PB		 5913 tmp = new_tmp();
5914 gen_helper_cpsr_read(tmp);
9ee6e8bb 5915 }
d9ba4830 5916 store_reg(s, rd, tmp);
9ee6e8bb
PB		 5917 }
5918 break;
5919 case 0x1:
5920 if (op1 == 1) {
5921 /* branch/exchange thumb (bx). */
d9ba4830
PB		 5922 tmp = load_reg(s, rm);
5923 gen_bx(s, tmp);
9ee6e8bb
PB		 5924 } else if (op1 == 3) {
5925 /* clz */
5926 rd = (insn >> 12) & 0xf;
1497c961
PB		 5927 tmp = load_reg(s, rm);
5928 gen_helper_clz(tmp, tmp);
5929 store_reg(s, rd, tmp);
9ee6e8bb
PB		 5930 } else {
5931 goto illegal_op;
5932 }
5933 break;
5934 case 0x2:
5935 if (op1 == 1) {
5936 ARCH(5J); /* bxj */
5937 /* Trivial implementation equivalent to bx. */
d9ba4830
PB		 5938 tmp = load_reg(s, rm);
5939 gen_bx(s, tmp);
9ee6e8bb
PB		 5940 } else {
5941 goto illegal_op;
5942 }
5943 break;
5944 case 0x3:
5945 if (op1 != 1)
5946 goto illegal_op;
5947
5948 /* branch link/exchange thumb (blx) */
d9ba4830
PB		 5949 tmp = load_reg(s, rm);
5950 tmp2 = new_tmp();
5951 tcg_gen_movi_i32(tmp2, s->pc);
5952 store_reg(s, 14, tmp2);
5953 gen_bx(s, tmp);
9ee6e8bb
PB		 5954 break;
5955 case 0x5: /* saturating add/subtract */
5956 rd = (insn >> 12) & 0xf;
5957 rn = (insn >> 16) & 0xf;
5e3f878a
PB		 5958 tmp = load_reg(s, rn);
5959 tmp2 = load_reg(s, rn);
9ee6e8bb 5960 if (op1 & 2)
5e3f878a 5961 gen_helper_double_saturate(tmp2, tmp2);
9ee6e8bb 5962 if (op1 & 1)
5e3f878a 5963 gen_helper_sub_saturate(tmp, tmp, tmp2);
9ee6e8bb 5964 else
5e3f878a
PB		 5965 gen_helper_add_saturate(tmp, tmp, tmp2);
5966 dead_tmp(tmp2);
5967 store_reg(s, rd, tmp);
9ee6e8bb
PB		 5968 break;
5969 case 7: /* bkpt */
5970 gen_set_condexec(s);
5e3f878a 5971 gen_set_pc_im(s->pc - 4);
d9ba4830 5972 gen_exception(EXCP_BKPT);
9ee6e8bb
PB		 5973 s->is_jmp = DISAS_JUMP;
5974 break;
5975 case 0x8: /* signed multiply */
5976 case 0xa:
5977 case 0xc:
5978 case 0xe:
5979 rs = (insn >> 8) & 0xf;
5980 rn = (insn >> 12) & 0xf;
5981 rd = (insn >> 16) & 0xf;
5982 if (op1 == 1) {
5983 /* (32 * 16) >> 16 */
5e3f878a
PB		 5984 tmp = load_reg(s, rm);
5985 tmp2 = load_reg(s, rs);
9ee6e8bb 5986 if (sh & 4)
5e3f878a 5987 tcg_gen_sari_i32(tmp2, tmp2, 16);
9ee6e8bb 5988 else
5e3f878a
PB		 5989 gen_sxth(tmp2);
5990 tmp2 = gen_muls_i64_i32(tmp, tmp2);
5991 tcg_gen_shri_i64(tmp2, tmp2, 16);
5992 tmp = new_tmp();
5993 tcg_gen_trunc_i64_i32(tmp, tmp2);
9ee6e8bb 5994 if ((sh & 2) == 0) {
5e3f878a
PB		 5995 tmp2 = load_reg(s, rn);
5996 gen_helper_add_setq(tmp, tmp, tmp2);
5997 dead_tmp(tmp2);
9ee6e8bb 5998 }
5e3f878a 5999 store_reg(s, rd, tmp);
9ee6e8bb
PB		 6000 } else {
6001 /* 16 * 16 */
5e3f878a
PB		 6002 tmp = load_reg(s, rm);
6003 tmp2 = load_reg(s, rs);
6004 gen_mulxy(tmp, tmp2, sh & 2, sh & 4);
6005 dead_tmp(tmp2);
9ee6e8bb 6006 if (op1 == 2) {
5e3f878a
PB		 6007 tmp = tcg_temp_new(TCG_TYPE_I64);
6008 tcg_gen_ext_i32_i64(tmp, cpu_T[0]);
6009 gen_addq(s, tmp, rn, rd);
6010 gen_storeq_reg(s, rn, rd, tmp);
9ee6e8bb
PB		 6011 } else {
6012 if (op1 == 0) {
5e3f878a
PB		 6013 tmp2 = load_reg(s, rn);
6014 gen_helper_add_setq(tmp, tmp, tmp2);
6015 dead_tmp(tmp2);
9ee6e8bb 6016 }
5e3f878a 6017 store_reg(s, rd, tmp);
9ee6e8bb
PB		 6018 }
6019 }
6020 break;
6021 default:
6022 goto illegal_op;
6023 }
6024 } else if (((insn & 0x0e000000) == 0 &&
6025 (insn & 0x00000090) != 0x90) ||
6026 ((insn & 0x0e000000) == (1 << 25))) {
6027 int set_cc, logic_cc, shiftop;
6028
6029 op1 = (insn >> 21) & 0xf;
6030 set_cc = (insn >> 20) & 1;
6031 logic_cc = table_logic_cc[op1] & set_cc;
6032
6033 /* data processing instruction */
6034 if (insn & (1 << 25)) {
6035 /* immediate operand */
6036 val = insn & 0xff;
6037 shift = ((insn >> 8) & 0xf) * 2;
6038 if (shift)
6039 val = (val >> shift) | (val << (32 - shift));
6040 gen_op_movl_T1_im(val);
6041 if (logic_cc && shift)
b26eefb6 6042 gen_set_CF_bit31(cpu_T[1]);
9ee6e8bb
PB		 6043 } else {
6044 /* register */
6045 rm = (insn) & 0xf;
6046 gen_movl_T1_reg(s, rm);
6047 shiftop = (insn >> 5) & 3;
6048 if (!(insn & (1 << 4))) {
6049 shift = (insn >> 7) & 0x1f;
9a119ff6 6050 gen_arm_shift_im(cpu_T[1], shiftop, shift, logic_cc);
9ee6e8bb
PB		 6051 } else {
6052 rs = (insn >> 8) & 0xf;
8984bd2e
PB		 6053 tmp = load_reg(s, rs);
6054 gen_arm_shift_reg(cpu_T[1], shiftop, tmp, logic_cc);
9ee6e8bb
PB		 6055 }
6056 }
6057 if (op1 != 0x0f && op1 != 0x0d) {
6058 rn = (insn >> 16) & 0xf;
6059 gen_movl_T0_reg(s, rn);
6060 }
6061 rd = (insn >> 12) & 0xf;
6062 switch(op1) {
6063 case 0x00:
6064 gen_op_andl_T0_T1();
6065 gen_movl_reg_T0(s, rd);
6066 if (logic_cc)
6067 gen_op_logic_T0_cc();
6068 break;
6069 case 0x01:
6070 gen_op_xorl_T0_T1();
6071 gen_movl_reg_T0(s, rd);
6072 if (logic_cc)
6073 gen_op_logic_T0_cc();
6074 break;
6075 case 0x02:
6076 if (set_cc && rd == 15) {
6077 /* SUBS r15, ... is used for exception return. */
6078 if (IS_USER(s))
6079 goto illegal_op;
6080 gen_op_subl_T0_T1_cc();
6081 gen_exception_return(s);
6082 } else {
6083 if (set_cc)
6084 gen_op_subl_T0_T1_cc();
6085 else
6086 gen_op_subl_T0_T1();
6087 gen_movl_reg_T0(s, rd);
6088 }
6089 break;
6090 case 0x03:
6091 if (set_cc)
6092 gen_op_rsbl_T0_T1_cc();
6093 else
6094 gen_op_rsbl_T0_T1();
6095 gen_movl_reg_T0(s, rd);
6096 break;
6097 case 0x04:
6098 if (set_cc)
6099 gen_op_addl_T0_T1_cc();
6100 else
6101 gen_op_addl_T0_T1();
6102 gen_movl_reg_T0(s, rd);
6103 break;
6104 case 0x05:
6105 if (set_cc)
6106 gen_op_adcl_T0_T1_cc();
6107 else
b26eefb6 6108 gen_adc_T0_T1();
9ee6e8bb
PB		 6109 gen_movl_reg_T0(s, rd);
6110 break;
6111 case 0x06:
6112 if (set_cc)
6113 gen_op_sbcl_T0_T1_cc();
6114 else
3670669c 6115 gen_sbc_T0_T1();
9ee6e8bb
PB		 6116 gen_movl_reg_T0(s, rd);
6117 break;
6118 case 0x07:
6119 if (set_cc)
6120 gen_op_rscl_T0_T1_cc();
6121 else
3670669c 6122 gen_rsc_T0_T1();
9ee6e8bb
PB		 6123 gen_movl_reg_T0(s, rd);
6124 break;
6125 case 0x08:
6126 if (set_cc) {
6127 gen_op_andl_T0_T1();
6128 gen_op_logic_T0_cc();
6129 }
6130 break;
6131 case 0x09:
6132 if (set_cc) {
6133 gen_op_xorl_T0_T1();
6134 gen_op_logic_T0_cc();
6135 }
6136 break;
6137 case 0x0a:
6138 if (set_cc) {
6139 gen_op_subl_T0_T1_cc();
6140 }
6141 break;
6142 case 0x0b:
6143 if (set_cc) {
6144 gen_op_addl_T0_T1_cc();
6145 }
6146 break;
6147 case 0x0c:
6148 gen_op_orl_T0_T1();
6149 gen_movl_reg_T0(s, rd);
6150 if (logic_cc)
6151 gen_op_logic_T0_cc();
6152 break;
6153 case 0x0d:
6154 if (logic_cc && rd == 15) {
6155 /* MOVS r15, ... is used for exception return. */
6156 if (IS_USER(s))
6157 goto illegal_op;
6158 gen_op_movl_T0_T1();
6159 gen_exception_return(s);
6160 } else {
6161 gen_movl_reg_T1(s, rd);
6162 if (logic_cc)
6163 gen_op_logic_T1_cc();
6164 }
6165 break;
6166 case 0x0e:
6167 gen_op_bicl_T0_T1();
6168 gen_movl_reg_T0(s, rd);
6169 if (logic_cc)
6170 gen_op_logic_T0_cc();
6171 break;
6172 default:
6173 case 0x0f:
6174 gen_op_notl_T1();
6175 gen_movl_reg_T1(s, rd);
6176 if (logic_cc)
6177 gen_op_logic_T1_cc();
6178 break;
6179 }
6180 } else {
6181 /* other instructions */
6182 op1 = (insn >> 24) & 0xf;
6183 switch(op1) {
6184 case 0x0:
6185 case 0x1:
6186 /* multiplies, extra load/stores */
6187 sh = (insn >> 5) & 3;
6188 if (sh == 0) {
6189 if (op1 == 0x0) {
6190 rd = (insn >> 16) & 0xf;
6191 rn = (insn >> 12) & 0xf;
6192 rs = (insn >> 8) & 0xf;
6193 rm = (insn) & 0xf;
6194 op1 = (insn >> 20) & 0xf;
6195 switch (op1) {
6196 case 0: case 1: case 2: case 3: case 6:
6197 /* 32 bit mul */
5e3f878a
PB		 6198 tmp = load_reg(s, rs);
6199 tmp2 = load_reg(s, rm);
6200 tcg_gen_mul_i32(tmp, tmp, tmp2);
6201 dead_tmp(tmp2);
9ee6e8bb
PB		 6202 if (insn & (1 << 22)) {
6203 /* Subtract (mls) */
6204 ARCH(6T2);
5e3f878a
PB		 6205 tmp2 = load_reg(s, rn);
6206 tcg_gen_sub_i32(tmp, tmp2, tmp);
6207 dead_tmp(tmp2);
9ee6e8bb
PB		 6208 } else if (insn & (1 << 21)) {
6209 /* Add */
5e3f878a
PB		 6210 tmp2 = load_reg(s, rn);
6211 tcg_gen_add_i32(tmp, tmp, tmp2);
6212 dead_tmp(tmp2);
9ee6e8bb
PB		 6213 }
6214 if (insn & (1 << 20))
5e3f878a
PB		 6215 gen_logic_CC(tmp);
6216 store_reg(s, rd, tmp);
9ee6e8bb
PB		 6217 break;
6218 default:
6219 /* 64 bit mul */
5e3f878a
PB		 6220 tmp = load_reg(s, rs);
6221 tmp2 = load_reg(s, rm);
9ee6e8bb 6222 if (insn & (1 << 22))
5e3f878a 6223 tmp = gen_muls_i64_i32(tmp, tmp2);
9ee6e8bb 6224 else
5e3f878a 6225 tmp = gen_mulu_i64_i32(tmp, tmp2);
9ee6e8bb 6226 if (insn & (1 << 21)) /* mult accumulate */
5e3f878a 6227 gen_addq(s, tmp, rn, rd);
9ee6e8bb
PB		 6228 if (!(insn & (1 << 23))) { /* double accumulate */
6229 ARCH(6);
5e3f878a
PB		 6230 gen_addq_lo(s, tmp, rn);
6231 gen_addq_lo(s, tmp, rd);
9ee6e8bb
PB		 6232 }
6233 if (insn & (1 << 20))
5e3f878a
PB		 6234 gen_logicq_cc(tmp);
6235 gen_storeq_reg(s, rn, rd, tmp);
9ee6e8bb
PB		 6236 break;
6237 }
6238 } else {
6239 rn = (insn >> 16) & 0xf;
6240 rd = (insn >> 12) & 0xf;
6241 if (insn & (1 << 23)) {
6242 /* load/store exclusive */
6243 gen_movl_T1_reg(s, rn);
6244 if (insn & (1 << 20)) {
8f8e3aa4
PB		 6245 gen_helper_mark_exclusive(cpu_env, cpu_T[1]);
6246 tmp = gen_ld32(addr, IS_USER(s));
6247 store_reg(s, rd, tmp);
9ee6e8bb 6248 } else {
8f8e3aa4 6249 int label = gen_new_label();
9ee6e8bb 6250 rm = insn & 0xf;
8f8e3aa4
PB		 6251 gen_helper_test_exclusive(cpu_T[0], cpu_env, addr);
6252 tcg_gen_brcond_i32(TCG_COND_NE, cpu_T[0],
6253 tcg_const_i32(0), label);
6254 tmp = load_reg(s,rm);
6255 gen_st32(tmp, cpu_T[1], IS_USER(s));
6256 gen_movl_reg_T0(s, rd);
9ee6e8bb 6257 }
9ee6e8bb
PB		 6258 } else {
6259 /* SWP instruction */
6260 rm = (insn) & 0xf;
6261
8984bd2e
PB		 6262 /* ??? This is not really atomic. However we know
6263 we never have multiple CPUs running in parallel,
6264 so it is good enough. */
6265 addr = load_reg(s, rn);
6266 tmp = load_reg(s, rm);
9ee6e8bb 6267 if (insn & (1 << 22)) {
8984bd2e
PB		 6268 tmp2 = gen_ld8u(addr, IS_USER(s));
6269 gen_st8(tmp, addr, IS_USER(s));
9ee6e8bb 6270 } else {
8984bd2e
PB		 6271 tmp2 = gen_ld32(addr, IS_USER(s));
6272 gen_st32(tmp, addr, IS_USER(s));
9ee6e8bb 6273 }
8984bd2e
PB		 6274 dead_tmp(addr);
6275 store_reg(s, rd, tmp2);
9ee6e8bb
PB		 6276 }
6277 }
6278 } else {
6279 int address_offset;
6280 int load;
6281 /* Misc load/store */
6282 rn = (insn >> 16) & 0xf;
6283 rd = (insn >> 12) & 0xf;
b0109805 6284 addr = load_reg(s, rn);
9ee6e8bb 6285 if (insn & (1 << 24))
b0109805 6286 gen_add_datah_offset(s, insn, 0, addr);
9ee6e8bb
PB		 6287 address_offset = 0;
6288 if (insn & (1 << 20)) {
6289 /* load */
6290 switch(sh) {
6291 case 1:
b0109805 6292 tmp = gen_ld16u(addr, IS_USER(s));
9ee6e8bb
PB		 6293 break;
6294 case 2:
b0109805 6295 tmp = gen_ld8s(addr, IS_USER(s));
9ee6e8bb
PB		 6296 break;
6297 default:
6298 case 3:
b0109805 6299 tmp = gen_ld16s(addr, IS_USER(s));
9ee6e8bb
PB		 6300 break;
6301 }
6302 load = 1;
6303 } else if (sh & 2) {
6304 /* doubleword */
6305 if (sh & 1) {
6306 /* store */
b0109805
PB		 6307 tmp = load_reg(s, rd);
6308 gen_st32(tmp, addr, IS_USER(s));
6309 tcg_gen_addi_i32(addr, addr, 4);
6310 tmp = load_reg(s, rd + 1);
6311 gen_st32(tmp, addr, IS_USER(s));
9ee6e8bb
PB		 6312 load = 0;
6313 } else {
6314 /* load */
b0109805
PB		 6315 tmp = gen_ld32(addr, IS_USER(s));
6316 store_reg(s, rd, tmp);
6317 tcg_gen_addi_i32(addr, addr, 4);
6318 tmp = gen_ld32(addr, IS_USER(s));
9ee6e8bb
PB		 6319 rd++;
6320 load = 1;
6321 }
6322 address_offset = -4;
6323 } else {
6324 /* store */
b0109805
PB		 6325 tmp = load_reg(s, rd);
6326 gen_st16(tmp, addr, IS_USER(s));
9ee6e8bb
PB		 6327 load = 0;
6328 }
6329 /* Perform base writeback before the loaded value to
6330 ensure correct behavior with overlapping index registers.
6331 ldrd with base writeback is is undefined if the
6332 destination and index registers overlap. */
6333 if (!(insn & (1 << 24))) {
b0109805
PB		 6334 gen_add_datah_offset(s, insn, address_offset, addr);
6335 store_reg(s, rn, addr);
9ee6e8bb
PB		 6336 } else if (insn & (1 << 21)) {
6337 if (address_offset)
b0109805
PB		 6338 tcg_gen_addi_i32(addr, addr, address_offset);
6339 store_reg(s, rn, addr);
6340 } else {
6341 dead_tmp(addr);
9ee6e8bb
PB		 6342 }
6343 if (load) {
6344 /* Complete the load. */
b0109805 6345 store_reg(s, rd, tmp);
9ee6e8bb
PB		 6346 }
6347 }
6348 break;
6349 case 0x4:
6350 case 0x5:
6351 goto do_ldst;
6352 case 0x6:
6353 case 0x7:
6354 if (insn & (1 << 4)) {
6355 ARCH(6);
6356 /* Armv6 Media instructions. */
6357 rm = insn & 0xf;
6358 rn = (insn >> 16) & 0xf;
2c0262af 6359 rd = (insn >> 12) & 0xf;
9ee6e8bb
PB		 6360 rs = (insn >> 8) & 0xf;
6361 switch ((insn >> 23) & 3) {
6362 case 0: /* Parallel add/subtract. */
6363 op1 = (insn >> 20) & 7;
6ddbc6e4
PB		 6364 tmp = load_reg(s, rn);
6365 tmp2 = load_reg(s, rm);
9ee6e8bb
PB		 6366 sh = (insn >> 5) & 7;
6367 if ((op1 & 3) == 0 || sh == 5 || sh == 6)
6368 goto illegal_op;
6ddbc6e4
PB		 6369 gen_arm_parallel_addsub(op1, sh, tmp, tmp2);
6370 dead_tmp(tmp2);
6371 store_reg(s, rd, tmp);
9ee6e8bb
PB		 6372 break;
6373 case 1:
6374 if ((insn & 0x00700020) == 0) {
6375 /* Hafword pack. */
3670669c
PB		 6376 tmp = load_reg(s, rn);
6377 tmp2 = load_reg(s, rm);
9ee6e8bb
PB		 6378 shift = (insn >> 7) & 0x1f;
6379 if (shift)
3670669c
PB		 6380 tcg_gen_shli_i32(tmp2, tmp2, shift);
6381 if (insn & (1 << 6)) {
6382 /* pkhtb */
6383 tcg_gen_andi_i32(tmp, tmp, 0xffff0000);
6384 tcg_gen_andi_i32(tmp2, tmp2, 0xffff);
6385 } else {
6386 /* pkhbt */
6387 tcg_gen_andi_i32(tmp, tmp, 0xffff);
6388 tcg_gen_andi_i32(tmp2, tmp2, 0xffff0000);
6389 }
6390 tcg_gen_or_i32(tmp, tmp, tmp2);
6391 store_reg(s, rd, tmp);
9ee6e8bb
PB		 6392 } else if ((insn & 0x00200020) == 0x00200000) {
6393 /* [us]sat */
6ddbc6e4 6394 tmp = load_reg(s, rm);
9ee6e8bb
PB		 6395 shift = (insn >> 7) & 0x1f;
6396 if (insn & (1 << 6)) {
6397 if (shift == 0)
6398 shift = 31;
6ddbc6e4 6399 tcg_gen_sari_i32(tmp, tmp, shift);
9ee6e8bb 6400 } else {
6ddbc6e4 6401 tcg_gen_shli_i32(tmp, tmp, shift);
9ee6e8bb
PB		 6402 }
6403 sh = (insn >> 16) & 0x1f;
6404 if (sh != 0) {
6405 if (insn & (1 << 22))
6ddbc6e4 6406 gen_helper_usat(tmp, tmp, tcg_const_i32(sh));
9ee6e8bb 6407 else
6ddbc6e4 6408 gen_helper_ssat(tmp, tmp, tcg_const_i32(sh));
9ee6e8bb 6409 }
6ddbc6e4 6410 store_reg(s, rd, tmp);
9ee6e8bb
PB		 6411 } else if ((insn & 0x00300fe0) == 0x00200f20) {
6412 /* [us]sat16 */
6ddbc6e4 6413 tmp = load_reg(s, rm);
9ee6e8bb
PB		 6414 sh = (insn >> 16) & 0x1f;
6415 if (sh != 0) {
6416 if (insn & (1 << 22))
6ddbc6e4 6417 gen_helper_usat16(tmp, tmp, tcg_const_i32(sh));
9ee6e8bb 6418 else
6ddbc6e4 6419 gen_helper_ssat16(tmp, tmp, tcg_const_i32(sh));
9ee6e8bb 6420 }
6ddbc6e4 6421 store_reg(s, rd, tmp);
9ee6e8bb
PB		 6422 } else if ((insn & 0x00700fe0) == 0x00000fa0) {
6423 /* Select bytes. */
6ddbc6e4
PB		 6424 tmp = load_reg(s, rn);
6425 tmp2 = load_reg(s, rm);
6426 tmp3 = new_tmp();
6427 tcg_gen_ld_i32(tmp3, cpu_env, offsetof(CPUState, GE));
6428 gen_helper_sel_flags(tmp, tmp3, tmp, tmp2);
6429 dead_tmp(tmp3);
6430 dead_tmp(tmp2);
6431 store_reg(s, rd, tmp);
9ee6e8bb 6432 } else if ((insn & 0x000003e0) == 0x00000060) {
5e3f878a 6433 tmp = load_reg(s, rm);
9ee6e8bb
PB		 6434 shift = (insn >> 10) & 3;
6435 /* ??? In many cases it's not neccessary to do a
6436 rotate, a shift is sufficient. */
6437 if (shift != 0)
5e3f878a 6438 tcg_gen_rori_i32(tmp, tmp, shift * 8);
9ee6e8bb
PB		 6439 op1 = (insn >> 20) & 7;
6440 switch (op1) {
5e3f878a
PB		 6441 case 0: gen_sxtb16(tmp); break;
6442 case 2: gen_sxtb(tmp); break;
6443 case 3: gen_sxth(tmp); break;
6444 case 4: gen_uxtb16(tmp); break;
6445 case 6: gen_uxtb(tmp); break;
6446 case 7: gen_uxth(tmp); break;
9ee6e8bb
PB		 6447 default: goto illegal_op;
6448 }
6449 if (rn != 15) {
5e3f878a 6450 tmp2 = load_reg(s, rn);
9ee6e8bb 6451 if ((op1 & 3) == 0) {
5e3f878a 6452 gen_add16(tmp, tmp2);
9ee6e8bb 6453 } else {
5e3f878a
PB		 6454 tcg_gen_add_i32(tmp, tmp, tmp2);
6455 dead_tmp(tmp2);
9ee6e8bb
PB		 6456 }
6457 }
5e3f878a 6458 store_reg(s, rd, tmp2);
9ee6e8bb
PB		 6459 } else if ((insn & 0x003f0f60) == 0x003f0f20) {
6460 /* rev */
b0109805 6461 tmp = load_reg(s, rm);
9ee6e8bb
PB		 6462 if (insn & (1 << 22)) {
6463 if (insn & (1 << 7)) {
b0109805 6464 gen_revsh(tmp);
9ee6e8bb
PB		 6465 } else {
6466 ARCH(6T2);
b0109805 6467 gen_helper_rbit(tmp, tmp);
9ee6e8bb
PB		 6468 }
6469 } else {
6470 if (insn & (1 << 7))
b0109805 6471 gen_rev16(tmp);
9ee6e8bb 6472 else
b0109805 6473 tcg_gen_bswap_i32(tmp, tmp);
9ee6e8bb 6474 }
b0109805 6475 store_reg(s, rd, tmp);
9ee6e8bb
PB		 6476 } else {
6477 goto illegal_op;
6478 }
6479 break;
6480 case 2: /* Multiplies (Type 3). */
5e3f878a
PB		 6481 tmp = load_reg(s, rm);
6482 tmp2 = load_reg(s, rs);
9ee6e8bb
PB		 6483 if (insn & (1 << 20)) {
6484 /* Signed multiply most significant [accumulate]. */
5e3f878a 6485 tmp2 = gen_muls_i64_i32(tmp, tmp2);
9ee6e8bb 6486 if (insn & (1 << 5))
5e3f878a
PB		 6487 tcg_gen_addi_i64(tmp2, tmp2, 0x80000000u);
6488 tcg_gen_shri_i64(tmp2, tmp2, 32);
6489 tmp = new_tmp();
6490 tcg_gen_trunc_i64_i32(tmp, tmp2);
9ee6e8bb 6491 if (rn != 15) {
5e3f878a 6492 tmp2 = load_reg(s, rn);
9ee6e8bb 6493 if (insn & (1 << 6)) {
5e3f878a 6494 tcg_gen_sub_i32(tmp, tmp, tmp2);
9ee6e8bb 6495 } else {
5e3f878a 6496 tcg_gen_add_i32(tmp, tmp, tmp2);
9ee6e8bb 6497 }
5e3f878a 6498 dead_tmp(tmp2);
9ee6e8bb 6499 }
5e3f878a 6500 store_reg(s, rd, tmp);
9ee6e8bb
PB		 6501 } else {
6502 if (insn & (1 << 5))
5e3f878a
PB		 6503 gen_swap_half(tmp2);
6504 gen_smul_dual(tmp, tmp2);
6505 /* This addition cannot overflow. */
6506 if (insn & (1 << 6)) {
6507 tcg_gen_sub_i32(tmp, tmp, tmp2);
6508 } else {
6509 tcg_gen_add_i32(tmp, tmp, tmp2);
6510 }
6511 dead_tmp(tmp2);
9ee6e8bb 6512 if (insn & (1 << 22)) {
5e3f878a
PB		 6513 /* smlald, smlsld */
6514 tmp2 = tcg_temp_new(TCG_TYPE_I64);
6515 tcg_gen_ext_i32_i64(tmp2, tmp);
6516 dead_tmp(tmp);
6517 gen_addq(s, tmp2, rn, rd);
6518 gen_storeq_reg(s, rn, rd, tmp2);
9ee6e8bb 6519 } else {
5e3f878a 6520 /* smuad, smusd, smlad, smlsd */
9ee6e8bb
PB		 6521 if (rn != 15)
6522 {
5e3f878a
PB		 6523 tmp2 = load_reg(s, rn);
6524 gen_helper_add_setq(tmp, tmp, tmp2);
6525 dead_tmp(tmp2);
9ee6e8bb 6526 }
5e3f878a 6527 store_reg(s, rd, tmp);
9ee6e8bb
PB		 6528 }
6529 }
6530 break;
6531 case 3:
6532 op1 = ((insn >> 17) & 0x38) | ((insn >> 5) & 7);
6533 switch (op1) {
6534 case 0: /* Unsigned sum of absolute differences. */
6ddbc6e4
PB		 6535 ARCH(6);
6536 tmp = load_reg(s, rm);
6537 tmp2 = load_reg(s, rs);
6538 gen_helper_usad8(tmp, tmp, tmp2);
6539 dead_tmp(tmp2);
9ee6e8bb 6540 if (rn != 15) {
6ddbc6e4
PB		 6541 tmp2 = load_reg(s, rn);
6542 tcg_gen_add_i32(tmp, tmp, tmp2);
6543 dead_tmp(tmp2);
9ee6e8bb 6544 }
6ddbc6e4 6545 store_reg(s, rd, tmp);
9ee6e8bb
PB		 6546 break;
6547 case 0x20: case 0x24: case 0x28: case 0x2c:
6548 /* Bitfield insert/clear. */
6549 ARCH(6T2);
6550 shift = (insn >> 7) & 0x1f;
6551 i = (insn >> 16) & 0x1f;
6552 i = i + 1 - shift;
6553 if (rm == 15) {
5e3f878a
PB		 6554 tmp = new_tmp();
6555 tcg_gen_movi_i32(tmp, 0);
9ee6e8bb 6556 } else {
5e3f878a 6557 tmp = load_reg(s, rm);
9ee6e8bb
PB		 6558 }
6559 if (i != 32) {
5e3f878a 6560 tmp2 = load_reg(s, rd);
8f8e3aa4 6561 gen_bfi(tmp, tmp2, tmp, shift, (1u << i) - 1);
5e3f878a 6562 dead_tmp(tmp2);
9ee6e8bb 6563 }
5e3f878a 6564 store_reg(s, rd, tmp);
9ee6e8bb
PB		 6565 break;
6566 case 0x12: case 0x16: case 0x1a: case 0x1e: /* sbfx */
6567 case 0x32: case 0x36: case 0x3a: case 0x3e: /* ubfx */
5e3f878a 6568 tmp = load_reg(s, rm);
9ee6e8bb
PB		 6569 shift = (insn >> 7) & 0x1f;
6570 i = ((insn >> 16) & 0x1f) + 1;
6571 if (shift + i > 32)
6572 goto illegal_op;
6573 if (i < 32) {
6574 if (op1 & 0x20) {
5e3f878a 6575 gen_ubfx(tmp, shift, (1u << i) - 1);
9ee6e8bb 6576 } else {
5e3f878a 6577 gen_sbfx(tmp, shift, i);
9ee6e8bb
PB		 6578 }
6579 }
5e3f878a 6580 store_reg(s, rd, tmp);
9ee6e8bb
PB		 6581 break;
6582 default:
6583 goto illegal_op;
6584 }
6585 break;
6586 }
6587 break;
6588 }
6589 do_ldst:
6590 /* Check for undefined extension instructions
6591 * per the ARM Bible IE:
6592 * xxxx 0111 1111 xxxx xxxx xxxx 1111 xxxx
6593 */
6594 sh = (0xf << 20) | (0xf << 4);
6595 if (op1 == 0x7 && ((insn & sh) == sh))
6596 {
6597 goto illegal_op;
6598 }
6599 /* load/store byte/word */
6600 rn = (insn >> 16) & 0xf;
6601 rd = (insn >> 12) & 0xf;
b0109805 6602 tmp2 = load_reg(s, rn);
9ee6e8bb
PB		 6603 i = (IS_USER(s) || (insn & 0x01200000) == 0x00200000);
6604 if (insn & (1 << 24))
b0109805 6605 gen_add_data_offset(s, insn, tmp2);
9ee6e8bb
PB		 6606 if (insn & (1 << 20)) {
6607 /* load */
6608 s->is_mem = 1;
9ee6e8bb 6609 if (insn & (1 << 22)) {
b0109805 6610 tmp = gen_ld8u(tmp2, i);
9ee6e8bb 6611 } else {
b0109805 6612 tmp = gen_ld32(tmp2, i);
9ee6e8bb 6613 }
9ee6e8bb
PB		 6614 } else {
6615 /* store */
b0109805 6616 tmp = load_reg(s, rd);
9ee6e8bb 6617 if (insn & (1 << 22))
b0109805 6618 gen_st8(tmp, tmp2, i);
9ee6e8bb 6619 else
b0109805 6620 gen_st32(tmp, tmp2, i);
9ee6e8bb
PB		 6621 }
6622 if (!(insn & (1 << 24))) {
b0109805
PB		 6623 gen_add_data_offset(s, insn, tmp2);
6624 store_reg(s, rn, tmp2);
6625 } else if (insn & (1 << 21)) {
6626 store_reg(s, rn, tmp2);
6627 } else {
6628 dead_tmp(tmp2);
9ee6e8bb
PB		 6629 }
6630 if (insn & (1 << 20)) {
6631 /* Complete the load. */
6632 if (rd == 15)
b0109805 6633 gen_bx(s, tmp);
9ee6e8bb 6634 else
b0109805 6635 store_reg(s, rd, tmp);
9ee6e8bb
PB		 6636 }
6637 break;
6638 case 0x08:
6639 case 0x09:
6640 {
6641 int j, n, user, loaded_base;
b0109805 6642 TCGv loaded_var;
9ee6e8bb
PB		 6643 /* load/store multiple words */
6644 /* XXX: store correct base if write back */
6645 user = 0;
6646 if (insn & (1 << 22)) {
6647 if (IS_USER(s))
6648 goto illegal_op; /* only usable in supervisor mode */
6649
6650 if ((insn & (1 << 15)) == 0)
6651 user = 1;
6652 }
6653 rn = (insn >> 16) & 0xf;
b0109805 6654 addr = load_reg(s, rn);
9ee6e8bb
PB		 6655
6656 /* compute total size */
6657 loaded_base = 0;
6658 n = 0;
6659 for(i=0;i<16;i++) {
6660 if (insn & (1 << i))
6661 n++;
6662 }
6663 /* XXX: test invalid n == 0 case ? */
6664 if (insn & (1 << 23)) {
6665 if (insn & (1 << 24)) {
6666 /* pre increment */
b0109805 6667 tcg_gen_addi_i32(addr, addr, 4);
9ee6e8bb
PB		 6668 } else {
6669 /* post increment */
6670 }
6671 } else {
6672 if (insn & (1 << 24)) {
6673 /* pre decrement */
b0109805 6674 tcg_gen_addi_i32(addr, addr, -(n * 4));
9ee6e8bb
PB		 6675 } else {
6676 /* post decrement */
6677 if (n != 1)
b0109805 6678 tcg_gen_addi_i32(addr, addr, -((n - 1) * 4));
9ee6e8bb
PB		 6679 }
6680 }
6681 j = 0;
6682 for(i=0;i<16;i++) {
6683 if (insn & (1 << i)) {
6684 if (insn & (1 << 20)) {
6685 /* load */
b0109805 6686 tmp = gen_ld32(addr, IS_USER(s));
9ee6e8bb 6687 if (i == 15) {
b0109805 6688 gen_bx(s, tmp);
9ee6e8bb 6689 } else if (user) {
b0109805
PB		 6690 gen_helper_set_user_reg(tcg_const_i32(i), tmp);
6691 dead_tmp(tmp);
9ee6e8bb 6692 } else if (i == rn) {
b0109805 6693 loaded_var = tmp;
9ee6e8bb
PB		 6694 loaded_base = 1;
6695 } else {
b0109805 6696 store_reg(s, i, tmp);
9ee6e8bb
PB		 6697 }
6698 } else {
6699 /* store */
6700 if (i == 15) {
6701 /* special case: r15 = PC + 8 */
6702 val = (long)s->pc + 4;
b0109805
PB		 6703 tmp = new_tmp();
6704 tcg_gen_movi_i32(tmp, val);
9ee6e8bb 6705 } else if (user) {
b0109805
PB		 6706 tmp = new_tmp();
6707 gen_helper_get_user_reg(tmp, tcg_const_i32(i));
9ee6e8bb 6708 } else {
b0109805 6709 tmp = load_reg(s, i);
9ee6e8bb 6710 }
b0109805 6711 gen_st32(tmp, addr, IS_USER(s));
9ee6e8bb
PB		 6712 }
6713 j++;
6714 /* no need to add after the last transfer */
6715 if (j != n)
b0109805 6716 tcg_gen_addi_i32(addr, addr, 4);
9ee6e8bb
PB		 6717 }
6718 }
6719 if (insn & (1 << 21)) {
6720 /* write back */
6721 if (insn & (1 << 23)) {
6722 if (insn & (1 << 24)) {
6723 /* pre increment */
6724 } else {
6725 /* post increment */
b0109805 6726 tcg_gen_addi_i32(addr, addr, 4);
9ee6e8bb
PB		 6727 }
6728 } else {
6729 if (insn & (1 << 24)) {
6730 /* pre decrement */
6731 if (n != 1)
b0109805 6732 tcg_gen_addi_i32(addr, addr, -((n - 1) * 4));
9ee6e8bb
PB		 6733 } else {
6734 /* post decrement */
b0109805 6735 tcg_gen_addi_i32(addr, addr, -(n * 4));
9ee6e8bb
PB		 6736 }
6737 }
b0109805
PB		 6738 store_reg(s, rn, addr);
6739 } else {
6740 dead_tmp(addr);
9ee6e8bb
PB		 6741 }
6742 if (loaded_base) {
b0109805 6743 store_reg(s, rn, loaded_var);
9ee6e8bb
PB		 6744 }
6745 if ((insn & (1 << 22)) && !user) {
6746 /* Restore CPSR from SPSR. */
d9ba4830
PB		 6747 tmp = load_cpu_field(spsr);
6748 gen_set_cpsr(tmp, 0xffffffff);
6749 dead_tmp(tmp);
9ee6e8bb
PB		 6750 s->is_jmp = DISAS_UPDATE;
6751 }
6752 }
6753 break;
6754 case 0xa:
6755 case 0xb:
6756 {
6757 int32_t offset;
6758
6759 /* branch (and link) */
6760 val = (int32_t)s->pc;
6761 if (insn & (1 << 24)) {
5e3f878a
PB		 6762 tmp = new_tmp();
6763 tcg_gen_movi_i32(tmp, val);
6764 store_reg(s, 14, tmp);
9ee6e8bb
PB		 6765 }
6766 offset = (((int32_t)insn << 8) >> 8);
6767 val += (offset << 2) + 4;
6768 gen_jmp(s, val);
6769 }
6770 break;
6771 case 0xc:
6772 case 0xd:
6773 case 0xe:
6774 /* Coprocessor. */
6775 if (disas_coproc_insn(env, s, insn))
6776 goto illegal_op;
6777 break;
6778 case 0xf:
6779 /* swi */
5e3f878a 6780 gen_set_pc_im(s->pc);
9ee6e8bb
PB		 6781 s->is_jmp = DISAS_SWI;
6782 break;
6783 default:
6784 illegal_op:
6785 gen_set_condexec(s);
5e3f878a 6786 gen_set_pc_im(s->pc - 4);
d9ba4830 6787 gen_exception(EXCP_UDEF);
9ee6e8bb
PB		 6788 s->is_jmp = DISAS_JUMP;
6789 break;
6790 }
6791 }
6792}
6793
6794/* Return true if this is a Thumb-2 logical op. */
6795static int
6796thumb2_logic_op(int op)
6797{
6798 return (op < 8);
6799}
6800
6801/* Generate code for a Thumb-2 data processing operation. If CONDS is nonzero
6802 then set condition code flags based on the result of the operation.
6803 If SHIFTER_OUT is nonzero then set the carry flag for logical operations
6804 to the high bit of T1.
6805 Returns zero if the opcode is valid. */
6806
6807static int
6808gen_thumb2_data_op(DisasContext *s, int op, int conds, uint32_t shifter_out)
6809{
6810 int logic_cc;
6811
6812 logic_cc = 0;
6813 switch (op) {
6814 case 0: /* and */
6815 gen_op_andl_T0_T1();
6816 logic_cc = conds;
6817 break;
6818 case 1: /* bic */
6819 gen_op_bicl_T0_T1();
6820 logic_cc = conds;
6821 break;
6822 case 2: /* orr */
6823 gen_op_orl_T0_T1();
6824 logic_cc = conds;
6825 break;
6826 case 3: /* orn */
6827 gen_op_notl_T1();
6828 gen_op_orl_T0_T1();
6829 logic_cc = conds;
6830 break;
6831 case 4: /* eor */
6832 gen_op_xorl_T0_T1();
6833 logic_cc = conds;
6834 break;
6835 case 8: /* add */
6836 if (conds)
6837 gen_op_addl_T0_T1_cc();
6838 else
6839 gen_op_addl_T0_T1();
6840 break;
6841 case 10: /* adc */
6842 if (conds)
6843 gen_op_adcl_T0_T1_cc();
6844 else
b26eefb6 6845 gen_adc_T0_T1();
9ee6e8bb
PB		 6846 break;
6847 case 11: /* sbc */
6848 if (conds)
6849 gen_op_sbcl_T0_T1_cc();
6850 else
3670669c 6851 gen_sbc_T0_T1();
9ee6e8bb
PB		 6852 break;
6853 case 13: /* sub */
6854 if (conds)
6855 gen_op_subl_T0_T1_cc();
6856 else
6857 gen_op_subl_T0_T1();
6858 break;
6859 case 14: /* rsb */
6860 if (conds)
6861 gen_op_rsbl_T0_T1_cc();
6862 else
6863 gen_op_rsbl_T0_T1();
6864 break;
6865 default: /* 5, 6, 7, 9, 12, 15. */
6866 return 1;
6867 }
6868 if (logic_cc) {
6869 gen_op_logic_T0_cc();
6870 if (shifter_out)
b26eefb6 6871 gen_set_CF_bit31(cpu_T[1]);
9ee6e8bb
PB		 6872 }
6873 return 0;
6874}
6875
6876/* Translate a 32-bit thumb instruction. Returns nonzero if the instruction
6877 is not legal. */
6878static int disas_thumb2_insn(CPUState *env, DisasContext *s, uint16_t insn_hw1)
6879{
b0109805 6880 uint32_t insn, imm, shift, offset;
9ee6e8bb 6881 uint32_t rd, rn, rm, rs;
b26eefb6 6882 TCGv tmp;
6ddbc6e4
PB		 6883 TCGv tmp2;
6884 TCGv tmp3;
b0109805 6885 TCGv addr;
9ee6e8bb
PB		 6886 int op;
6887 int shiftop;
6888 int conds;
6889 int logic_cc;
6890
6891 if (!(arm_feature(env, ARM_FEATURE_THUMB2)
6892 || arm_feature (env, ARM_FEATURE_M))) {
6893 /* Thumb-1 cores may need to tread bl and blx as a pair of
6894 16-bit instructions to get correct prefetch abort behavior. */
6895 insn = insn_hw1;
6896 if ((insn & (1 << 12)) == 0) {
6897 /* Second half of blx. */
6898 offset = ((insn & 0x7ff) << 1);
d9ba4830
PB		 6899 tmp = load_reg(s, 14);
6900 tcg_gen_addi_i32(tmp, tmp, offset);
6901 tcg_gen_andi_i32(tmp, tmp, 0xfffffffc);
9ee6e8bb 6902
d9ba4830 6903 tmp2 = new_tmp();
b0109805 6904 tcg_gen_movi_i32(tmp2, s->pc | 1);
d9ba4830
PB		 6905 store_reg(s, 14, tmp2);
6906 gen_bx(s, tmp);
9ee6e8bb
PB		 6907 return 0;
6908 }
6909 if (insn & (1 << 11)) {
6910 /* Second half of bl. */
6911 offset = ((insn & 0x7ff) << 1) | 1;
d9ba4830
PB		 6912 tmp = load_reg(s, 14);
6913 tcg_gen_addi_i32(tmp, tmp, 14);
9ee6e8bb 6914
d9ba4830 6915 tmp2 = new_tmp();
b0109805 6916 tcg_gen_movi_i32(tmp2, s->pc | 1);
d9ba4830
PB		 6917 store_reg(s, 14, tmp2);
6918 gen_bx(s, tmp);
9ee6e8bb
PB		 6919 return 0;
6920 }
6921 if ((s->pc & ~TARGET_PAGE_MASK) == 0) {
6922 /* Instruction spans a page boundary. Implement it as two
6923 16-bit instructions in case the second half causes an
6924 prefetch abort. */
6925 offset = ((int32_t)insn << 21) >> 9;
b0109805 6926 gen_op_movl_T0_im(s->pc + 2 + offset);
9ee6e8bb
PB		 6927 gen_movl_reg_T0(s, 14);
6928 return 0;
6929 }
6930 /* Fall through to 32-bit decode. */
6931 }
6932
6933 insn = lduw_code(s->pc);
6934 s->pc += 2;
6935 insn |= (uint32_t)insn_hw1 << 16;
6936
6937 if ((insn & 0xf800e800) != 0xf000e800) {
6938 ARCH(6T2);
6939 }
6940
6941 rn = (insn >> 16) & 0xf;
6942 rs = (insn >> 12) & 0xf;
6943 rd = (insn >> 8) & 0xf;
6944 rm = insn & 0xf;
6945 switch ((insn >> 25) & 0xf) {
6946 case 0: case 1: case 2: case 3:
6947 /* 16-bit instructions. Should never happen. */
6948 abort();
6949 case 4:
6950 if (insn & (1 << 22)) {
6951 /* Other load/store, table branch. */
6952 if (insn & 0x01200000) {
6953 /* Load/store doubleword. */
6954 if (rn == 15) {
b0109805
PB		 6955 addr = new_tmp();
6956 tcg_gen_movi_i32(addr, s->pc & ~3);
9ee6e8bb 6957 } else {
b0109805 6958 addr = load_reg(s, rn);
9ee6e8bb
PB		 6959 }
6960 offset = (insn & 0xff) * 4;
6961 if ((insn & (1 << 23)) == 0)
6962 offset = -offset;
6963 if (insn & (1 << 24)) {
b0109805 6964 tcg_gen_addi_i32(addr, addr, offset);
9ee6e8bb
PB		 6965 offset = 0;
6966 }
6967 if (insn & (1 << 20)) {
6968 /* ldrd */
b0109805
PB		 6969 tmp = gen_ld32(addr, IS_USER(s));
6970 store_reg(s, rs, tmp);
6971 tcg_gen_addi_i32(addr, addr, 4);
6972 tmp = gen_ld32(addr, IS_USER(s));
6973 store_reg(s, rd, tmp);
9ee6e8bb
PB		 6974 } else {
6975 /* strd */
b0109805
PB		 6976 tmp = load_reg(s, rs);
6977 gen_st32(tmp, addr, IS_USER(s));
6978 tcg_gen_addi_i32(addr, addr, 4);
6979 tmp = load_reg(s, rd);
6980 gen_st32(tmp, addr, IS_USER(s));
9ee6e8bb
PB		 6981 }
6982 if (insn & (1 << 21)) {
6983 /* Base writeback. */
6984 if (rn == 15)
6985 goto illegal_op;
b0109805
PB		 6986 tcg_gen_addi_i32(addr, addr, offset - 4);
6987 store_reg(s, rn, addr);
6988 } else {
6989 dead_tmp(addr);
9ee6e8bb
PB		 6990 }
6991 } else if ((insn & (1 << 23)) == 0) {
6992 /* Load/store exclusive word. */
2c0262af 6993 gen_movl_T1_reg(s, rn);
2c0262af 6994 if (insn & (1 << 20)) {
8f8e3aa4
PB		 6995 gen_helper_mark_exclusive(cpu_env, cpu_T[1]);
6996 tmp = gen_ld32(addr, IS_USER(s));
6997 store_reg(s, rd, tmp);
9ee6e8bb 6998 } else {
8f8e3aa4
PB		 6999 int label = gen_new_label();
7000 gen_helper_test_exclusive(cpu_T[0], cpu_env, addr);
7001 tcg_gen_brcond_i32(TCG_COND_NE, cpu_T[0],
7002 tcg_const_i32(0), label);
7003 tmp = load_reg(s, rs);
7004 gen_st32(tmp, cpu_T[1], IS_USER(s));
7005 gen_set_label(label);
7006 gen_movl_reg_T0(s, rd);
9ee6e8bb 7007 }
9ee6e8bb
PB		 7008 } else if ((insn & (1 << 6)) == 0) {
7009 /* Table Branch. */
7010 if (rn == 15) {
b0109805
PB		 7011 addr = new_tmp();
7012 tcg_gen_movi_i32(addr, s->pc);
9ee6e8bb 7013 } else {
b0109805 7014 addr = load_reg(s, rn);
9ee6e8bb 7015 }
b26eefb6 7016 tmp = load_reg(s, rm);
b0109805 7017 tcg_gen_add_i32(addr, addr, tmp);
9ee6e8bb
PB		 7018 if (insn & (1 << 4)) {
7019 /* tbh */
b0109805 7020 tcg_gen_add_i32(addr, addr, tmp);
b26eefb6 7021 dead_tmp(tmp);
b0109805 7022 tmp = gen_ld16u(addr, IS_USER(s));
9ee6e8bb 7023 } else { /* tbb */
b26eefb6 7024 dead_tmp(tmp);
b0109805 7025 tmp = gen_ld8u(addr, IS_USER(s));
9ee6e8bb 7026 }
b0109805
PB		 7027 dead_tmp(addr);
7028 tcg_gen_shli_i32(tmp, tmp, 1);
7029 tcg_gen_addi_i32(tmp, tmp, s->pc);
7030 store_reg(s, 15, tmp);
9ee6e8bb
PB		 7031 } else {
7032 /* Load/store exclusive byte/halfword/doubleword. */
8f8e3aa4
PB		 7033 /* ??? These are not really atomic. However we know
7034 we never have multiple CPUs running in parallel,
7035 so it is good enough. */
9ee6e8bb 7036 op = (insn >> 4) & 0x3;
8f8e3aa4
PB		 7037 /* Must use a global reg for the address because we have
7038 a conditional branch in the store instruction. */
9ee6e8bb 7039 gen_movl_T1_reg(s, rn);
8f8e3aa4 7040 addr = cpu_T[1];
9ee6e8bb 7041 if (insn & (1 << 20)) {
8f8e3aa4 7042 gen_helper_mark_exclusive(cpu_env, addr);
9ee6e8bb
PB		 7043 switch (op) {
7044 case 0:
8f8e3aa4 7045 tmp = gen_ld8u(addr, IS_USER(s));
9ee6e8bb 7046 break;
2c0262af 7047 case 1:
8f8e3aa4 7048 tmp = gen_ld16u(addr, IS_USER(s));
2c0262af 7049 break;
9ee6e8bb 7050 case 3:
8f8e3aa4
PB		 7051 tmp = gen_ld32(addr, IS_USER(s));
7052 tcg_gen_addi_i32(addr, addr, 4);
7053 tmp2 = gen_ld32(addr, IS_USER(s));
7054 store_reg(s, rd, tmp2);
2c0262af
FB		 7055 break;
7056 default:
9ee6e8bb
PB		 7057 goto illegal_op;
7058 }
8f8e3aa4 7059 store_reg(s, rs, tmp);
9ee6e8bb 7060 } else {
8f8e3aa4
PB		 7061 int label = gen_new_label();
7062 /* Must use a global that is not killed by the branch. */
7063 gen_helper_test_exclusive(cpu_T[0], cpu_env, addr);
7064 tcg_gen_brcond_i32(TCG_COND_NE, cpu_T[0], tcg_const_i32(0),
7065 label);
7066 tmp = load_reg(s, rs);
9ee6e8bb
PB		 7067 switch (op) {
7068 case 0:
8f8e3aa4 7069 gen_st8(tmp, addr, IS_USER(s));
9ee6e8bb
PB		 7070 break;
7071 case 1:
8f8e3aa4 7072 gen_st16(tmp, addr, IS_USER(s));
9ee6e8bb 7073 break;
2c0262af 7074 case 3:
8f8e3aa4
PB		 7075 gen_st32(tmp, addr, IS_USER(s));
7076 tcg_gen_addi_i32(addr, addr, 4);
7077 tmp = load_reg(s, rd);
7078 gen_st32(tmp, addr, IS_USER(s));
2c0262af 7079 break;
9ee6e8bb
PB		 7080 default:
7081 goto illegal_op;
2c0262af 7082 }
8f8e3aa4 7083 gen_set_label(label);
9ee6e8bb
PB		 7084 gen_movl_reg_T0(s, rm);
7085 }
7086 }
7087 } else {
7088 /* Load/store multiple, RFE, SRS. */
7089 if (((insn >> 23) & 1) == ((insn >> 24) & 1)) {
7090 /* Not available in user mode. */
b0109805 7091 if (IS_USER(s))
9ee6e8bb
PB		 7092 goto illegal_op;
7093 if (insn & (1 << 20)) {
7094 /* rfe */
b0109805
PB		 7095 addr = load_reg(s, rn);
7096 if ((insn & (1 << 24)) == 0)
7097 tcg_gen_addi_i32(addr, addr, -8);
7098 /* Load PC into tmp and CPSR into tmp2. */
7099 tmp = gen_ld32(addr, 0);
7100 tcg_gen_addi_i32(addr, addr, 4);
7101 tmp2 = gen_ld32(addr, 0);
9ee6e8bb
PB		 7102 if (insn & (1 << 21)) {
7103 /* Base writeback. */
b0109805
PB		 7104 if (insn & (1 << 24)) {
7105 tcg_gen_addi_i32(addr, addr, 4);
7106 } else {
7107 tcg_gen_addi_i32(addr, addr, -4);
7108 }
7109 store_reg(s, rn, addr);
7110 } else {
7111 dead_tmp(addr);
9ee6e8bb 7112 }
b0109805 7113 gen_rfe(s, tmp, tmp2);
9ee6e8bb
PB		 7114 } else {
7115 /* srs */
7116 op = (insn & 0x1f);
7117 if (op == (env->uncached_cpsr & CPSR_M)) {
b0109805 7118 addr = load_reg(s, 13);
9ee6e8bb 7119 } else {
b0109805
PB		 7120 addr = new_tmp();
7121 gen_helper_get_r13_banked(addr, cpu_env, tcg_const_i32(op));
9ee6e8bb
PB		 7122 }
7123 if ((insn & (1 << 24)) == 0) {
b0109805 7124 tcg_gen_addi_i32(addr, addr, -8);
9ee6e8bb 7125 }
b0109805
PB		 7126 tmp = load_reg(s, 14);
7127 gen_st32(tmp, addr, 0);
7128 tcg_gen_addi_i32(addr, addr, 4);
7129 tmp = new_tmp();
7130 gen_helper_cpsr_read(tmp);
7131 gen_st32(tmp, addr, 0);
9ee6e8bb
PB		 7132 if (insn & (1 << 21)) {
7133 if ((insn & (1 << 24)) == 0) {
b0109805 7134 tcg_gen_addi_i32(addr, addr, -4);
9ee6e8bb 7135 } else {
b0109805 7136 tcg_gen_addi_i32(addr, addr, 4);
9ee6e8bb
PB		 7137 }
7138 if (op == (env->uncached_cpsr & CPSR_M)) {
b0109805 7139 store_reg(s, 13, addr);
9ee6e8bb 7140 } else {
b0109805
PB		 7141 gen_helper_set_r13_banked(cpu_env,
7142 tcg_const_i32(op), addr);
9ee6e8bb 7143 }
b0109805
PB		 7144 } else {
7145 dead_tmp(addr);
9ee6e8bb
PB		 7146 }
7147 }
7148 } else {
7149 int i;
7150 /* Load/store multiple. */
b0109805 7151 addr = load_reg(s, rn);
9ee6e8bb
PB		 7152 offset = 0;
7153 for (i = 0; i < 16; i++) {
7154 if (insn & (1 << i))
7155 offset += 4;
7156 }
7157 if (insn & (1 << 24)) {
b0109805 7158 tcg_gen_addi_i32(addr, addr, -offset);
9ee6e8bb
PB		 7159 }
7160
7161 for (i = 0; i < 16; i++) {
7162 if ((insn & (1 << i)) == 0)
7163 continue;
7164 if (insn & (1 << 20)) {
7165 /* Load. */
b0109805 7166 tmp = gen_ld32(addr, IS_USER(s));
9ee6e8bb 7167 if (i == 15) {
b0109805 7168 gen_bx(s, tmp);
9ee6e8bb 7169 } else {
b0109805 7170 store_reg(s, i, tmp);
9ee6e8bb
PB		 7171 }
7172 } else {
7173 /* Store. */
b0109805
PB		 7174 tmp = load_reg(s, i);
7175 gen_st32(tmp, addr, IS_USER(s));
9ee6e8bb 7176 }
b0109805 7177 tcg_gen_addi_i32(addr, addr, 4);
9ee6e8bb
PB		 7178 }
7179 if (insn & (1 << 21)) {
7180 /* Base register writeback. */
7181 if (insn & (1 << 24)) {
b0109805 7182 tcg_gen_addi_i32(addr, addr, -offset);
9ee6e8bb
PB		 7183 }
7184 /* Fault if writeback register is in register list. */
7185 if (insn & (1 << rn))
7186 goto illegal_op;
b0109805
PB		 7187 store_reg(s, rn, addr);
7188 } else {
7189 dead_tmp(addr);
9ee6e8bb
PB		 7190 }
7191 }
7192 }
7193 break;
7194 case 5: /* Data processing register constant shift. */
7195 if (rn == 15)
7196 gen_op_movl_T0_im(0);
7197 else
7198 gen_movl_T0_reg(s, rn);
7199 gen_movl_T1_reg(s, rm);
7200 op = (insn >> 21) & 0xf;
7201 shiftop = (insn >> 4) & 3;
7202 shift = ((insn >> 6) & 3) | ((insn >> 10) & 0x1c);
7203 conds = (insn & (1 << 20)) != 0;
7204 logic_cc = (conds && thumb2_logic_op(op));
9a119ff6 7205 gen_arm_shift_im(cpu_T[1], shiftop, shift, logic_cc);
9ee6e8bb
PB		 7206 if (gen_thumb2_data_op(s, op, conds, 0))
7207 goto illegal_op;
7208 if (rd != 15)
7209 gen_movl_reg_T0(s, rd);
7210 break;
7211 case 13: /* Misc data processing. */
7212 op = ((insn >> 22) & 6) | ((insn >> 7) & 1);
7213 if (op < 4 && (insn & 0xf000) != 0xf000)
7214 goto illegal_op;
7215 switch (op) {
7216 case 0: /* Register controlled shift. */
8984bd2e
PB		 7217 tmp = load_reg(s, rn);
7218 tmp2 = load_reg(s, rm);
9ee6e8bb
PB		 7219 if ((insn & 0x70) != 0)
7220 goto illegal_op;
7221 op = (insn >> 21) & 3;
8984bd2e
PB		 7222 logic_cc = (insn & (1 << 20)) != 0;
7223 gen_arm_shift_reg(tmp, op, tmp2, logic_cc);
7224 if (logic_cc)
7225 gen_logic_CC(tmp);
7226 store_reg(s, rd, tmp);
9ee6e8bb
PB		 7227 break;
7228 case 1: /* Sign/zero extend. */
5e3f878a 7229 tmp = load_reg(s, rm);
9ee6e8bb
PB		 7230 shift = (insn >> 4) & 3;
7231 /* ??? In many cases it's not neccessary to do a
7232 rotate, a shift is sufficient. */
7233 if (shift != 0)
5e3f878a 7234 tcg_gen_rori_i32(tmp, tmp, shift * 8);
9ee6e8bb
PB		 7235 op = (insn >> 20) & 7;
7236 switch (op) {
5e3f878a
PB		 7237 case 0: gen_sxth(tmp); break;
7238 case 1: gen_uxth(tmp); break;
7239 case 2: gen_sxtb16(tmp); break;
7240 case 3: gen_uxtb16(tmp); break;
7241 case 4: gen_sxtb(tmp); break;
7242 case 5: gen_uxtb(tmp); break;
9ee6e8bb
PB		 7243 default: goto illegal_op;
7244 }
7245 if (rn != 15) {
5e3f878a 7246 tmp2 = load_reg(s, rn);
9ee6e8bb 7247 if ((op >> 1) == 1) {
5e3f878a 7248 gen_add16(tmp, tmp2);
9ee6e8bb 7249 } else {
5e3f878a
PB		 7250 tcg_gen_add_i32(tmp, tmp, tmp2);
7251 dead_tmp(tmp2);
9ee6e8bb
PB		 7252 }
7253 }
5e3f878a 7254 store_reg(s, rd, tmp);
9ee6e8bb
PB		 7255 break;
7256 case 2: /* SIMD add/subtract. */
7257 op = (insn >> 20) & 7;
7258 shift = (insn >> 4) & 7;
7259 if ((op & 3) == 3 || (shift & 3) == 3)
7260 goto illegal_op;
6ddbc6e4
PB		 7261 tmp = load_reg(s, rn);
7262 tmp2 = load_reg(s, rm);
7263 gen_thumb2_parallel_addsub(op, shift, tmp, tmp2);
7264 dead_tmp(tmp2);
7265 store_reg(s, rd, tmp);
9ee6e8bb
PB		 7266 break;
7267 case 3: /* Other data processing. */
7268 op = ((insn >> 17) & 0x38) | ((insn >> 4) & 7);
7269 if (op < 4) {
7270 /* Saturating add/subtract. */
d9ba4830
PB		 7271 tmp = load_reg(s, rn);
7272 tmp2 = load_reg(s, rm);
9ee6e8bb 7273 if (op & 2)
d9ba4830 7274 gen_helper_double_saturate(tmp, tmp);
9ee6e8bb 7275 if (op & 1)
d9ba4830 7276 gen_helper_sub_saturate(tmp, tmp2, tmp);
9ee6e8bb 7277 else
d9ba4830
PB		 7278 gen_helper_add_saturate(tmp, tmp, tmp2);
7279 dead_tmp(tmp2);
9ee6e8bb 7280 } else {
d9ba4830 7281 tmp = load_reg(s, rn);
9ee6e8bb
PB		 7282 switch (op) {
7283 case 0x0a: /* rbit */
d9ba4830 7284 gen_helper_rbit(tmp, tmp);
9ee6e8bb
PB		 7285 break;
7286 case 0x08: /* rev */
d9ba4830 7287 tcg_gen_bswap_i32(tmp, tmp);
9ee6e8bb
PB		 7288 break;
7289 case 0x09: /* rev16 */
d9ba4830 7290 gen_rev16(tmp);
9ee6e8bb
PB		 7291 break;
7292 case 0x0b: /* revsh */
d9ba4830 7293 gen_revsh(tmp);
9ee6e8bb
PB		 7294 break;
7295 case 0x10: /* sel */
d9ba4830 7296 tmp2 = load_reg(s, rm);
6ddbc6e4
PB		 7297 tmp3 = new_tmp();
7298 tcg_gen_ld_i32(tmp3, cpu_env, offsetof(CPUState, GE));
d9ba4830 7299 gen_helper_sel_flags(tmp, tmp3, tmp, tmp2);
6ddbc6e4 7300 dead_tmp(tmp3);
d9ba4830 7301 dead_tmp(tmp2);
9ee6e8bb
PB		 7302 break;
7303 case 0x18: /* clz */
d9ba4830 7304 gen_helper_clz(tmp, tmp);
9ee6e8bb
PB		 7305 break;
7306 default:
7307 goto illegal_op;
7308 }
7309 }
d9ba4830 7310 store_reg(s, rd, tmp);
9ee6e8bb
PB		 7311 break;
7312 case 4: case 5: /* 32-bit multiply. Sum of absolute differences. */
7313 op = (insn >> 4) & 0xf;
d9ba4830
PB		 7314 tmp = load_reg(s, rn);
7315 tmp2 = load_reg(s, rm);
9ee6e8bb
PB		 7316 switch ((insn >> 20) & 7) {
7317 case 0: /* 32 x 32 -> 32 */
d9ba4830
PB		 7318 tcg_gen_mul_i32(tmp, tmp, tmp2);
7319 dead_tmp(tmp2);
9ee6e8bb 7320 if (rs != 15) {
d9ba4830 7321 tmp2 = load_reg(s, rs);
9ee6e8bb 7322 if (op)
d9ba4830 7323 tcg_gen_sub_i32(tmp, tmp2, tmp);
9ee6e8bb 7324 else
d9ba4830
PB		 7325 tcg_gen_add_i32(tmp, tmp, tmp2);
7326 dead_tmp(tmp2);
9ee6e8bb 7327 }
9ee6e8bb
PB		 7328 break;
7329 case 1: /* 16 x 16 -> 32 */
d9ba4830
PB		 7330 gen_mulxy(tmp, tmp2, op & 2, op & 1);
7331 dead_tmp(tmp2);
9ee6e8bb 7332 if (rs != 15) {
d9ba4830
PB		 7333 tmp2 = load_reg(s, rs);
7334 gen_helper_add_setq(tmp, tmp, tmp2);
7335 dead_tmp(tmp2);
9ee6e8bb 7336 }
9ee6e8bb
PB		 7337 break;
7338 case 2: /* Dual multiply add. */
7339 case 4: /* Dual multiply subtract. */
7340 if (op)
d9ba4830
PB		 7341 gen_swap_half(tmp2);
7342 gen_smul_dual(tmp, tmp2);
9ee6e8bb
PB		 7343 /* This addition cannot overflow. */
7344 if (insn & (1 << 22)) {
d9ba4830 7345 tcg_gen_sub_i32(tmp, tmp, tmp2);
9ee6e8bb 7346 } else {
d9ba4830 7347 tcg_gen_add_i32(tmp, tmp, tmp2);
9ee6e8bb 7348 }
d9ba4830 7349 dead_tmp(tmp2);
9ee6e8bb
PB		 7350 if (rs != 15)
7351 {
d9ba4830
PB		 7352 tmp2 = load_reg(s, rs);
7353 gen_helper_add_setq(tmp, tmp, tmp2);
7354 dead_tmp(tmp2);
9ee6e8bb 7355 }
9ee6e8bb
PB		 7356 break;
7357 case 3: /* 32 * 16 -> 32msb */
7358 if (op)
d9ba4830 7359 tcg_gen_sari_i32(tmp2, tmp2, 16);
9ee6e8bb 7360 else
d9ba4830 7361 gen_sxth(tmp2);
5e3f878a
PB		 7362 tmp2 = gen_muls_i64_i32(tmp, tmp2);
7363 tcg_gen_shri_i64(tmp2, tmp2, 16);
7364 tmp = new_tmp();
7365 tcg_gen_trunc_i64_i32(tmp, tmp2);
9ee6e8bb
PB		 7366 if (rs != 15)
7367 {
d9ba4830
PB		 7368 tmp2 = load_reg(s, rs);
7369 gen_helper_add_setq(tmp, tmp, tmp2);
7370 dead_tmp(tmp2);
9ee6e8bb 7371 }
9ee6e8bb
PB		 7372 break;
7373 case 5: case 6: /* 32 * 32 -> 32msb */
d9ba4830
PB		 7374 gen_imull(tmp, tmp2);
7375 if (insn & (1 << 5)) {
7376 gen_roundqd(tmp, tmp2);
7377 dead_tmp(tmp2);
7378 } else {
7379 dead_tmp(tmp);
7380 tmp = tmp2;
7381 }
9ee6e8bb 7382 if (rs != 15) {
d9ba4830 7383 tmp2 = load_reg(s, rs);
9ee6e8bb 7384 if (insn & (1 << 21)) {
d9ba4830 7385 tcg_gen_add_i32(tmp, tmp, tmp2);
99c475ab 7386 } else {
d9ba4830 7387 tcg_gen_sub_i32(tmp, tmp2, tmp);
99c475ab 7388 }
d9ba4830 7389 dead_tmp(tmp2);
2c0262af 7390 }
9ee6e8bb
PB		 7391 break;
7392 case 7: /* Unsigned sum of absolute differences. */
d9ba4830
PB		 7393 gen_helper_usad8(tmp, tmp, tmp2);
7394 dead_tmp(tmp2);
9ee6e8bb 7395 if (rs != 15) {
d9ba4830
PB		 7396 tmp2 = load_reg(s, rs);
7397 tcg_gen_add_i32(tmp, tmp, tmp2);
7398 dead_tmp(tmp2);
5fd46862 7399 }
9ee6e8bb 7400 break;
2c0262af 7401 }
d9ba4830 7402 store_reg(s, rd, tmp);
2c0262af 7403 break;
9ee6e8bb
PB		 7404 case 6: case 7: /* 64-bit multiply, Divide. */
7405 op = ((insn >> 4) & 0xf) | ((insn >> 16) & 0x70);
5e3f878a
PB		 7406 tmp = load_reg(s, rn);
7407 tmp2 = load_reg(s, rm);
9ee6e8bb
PB		 7408 if ((op & 0x50) == 0x10) {
7409 /* sdiv, udiv */
7410 if (!arm_feature(env, ARM_FEATURE_DIV))
7411 goto illegal_op;
7412 if (op & 0x20)
5e3f878a 7413 gen_helper_udiv(tmp, tmp, tmp2);
2c0262af 7414 else
5e3f878a
PB		 7415 gen_helper_sdiv(tmp, tmp, tmp2);
7416 dead_tmp(tmp2);
7417 store_reg(s, rd, tmp);
9ee6e8bb
PB		 7418 } else if ((op & 0xe) == 0xc) {
7419 /* Dual multiply accumulate long. */
7420 if (op & 1)
5e3f878a
PB		 7421 gen_swap_half(tmp2);
7422 gen_smul_dual(tmp, tmp2);
9ee6e8bb 7423 if (op & 0x10) {
5e3f878a 7424 tcg_gen_sub_i32(tmp, tmp, tmp2);
b5ff1b31 7425 } else {
5e3f878a 7426 tcg_gen_add_i32(tmp, tmp, tmp2);
b5ff1b31 7427 }
5e3f878a
PB		 7428 dead_tmp(tmp2);
7429 tmp2 = tcg_temp_new(TCG_TYPE_I64);
7430 gen_addq(s, tmp, rs, rd);
7431 gen_storeq_reg(s, rs, rd, tmp);
2c0262af 7432 } else {
9ee6e8bb
PB		 7433 if (op & 0x20) {
7434 /* Unsigned 64-bit multiply */
5e3f878a 7435 tmp = gen_mulu_i64_i32(tmp, tmp2);
b5ff1b31 7436 } else {
9ee6e8bb
PB		 7437 if (op & 8) {
7438 /* smlalxy */
5e3f878a
PB		 7439 gen_mulxy(tmp, tmp2, op & 2, op & 1);
7440 dead_tmp(tmp2);
7441 tmp2 = tcg_temp_new(TCG_TYPE_I64);
7442 tcg_gen_ext_i32_i64(tmp2, tmp);
7443 dead_tmp(tmp);
7444 tmp = tmp2;
9ee6e8bb
PB		 7445 } else {
7446 /* Signed 64-bit multiply */
5e3f878a 7447 tmp = gen_muls_i64_i32(tmp, tmp2);
9ee6e8bb 7448 }
b5ff1b31 7449 }
9ee6e8bb
PB		 7450 if (op & 4) {
7451 /* umaal */
5e3f878a
PB		 7452 gen_addq_lo(s, tmp, rs);
7453 gen_addq_lo(s, tmp, rd);
9ee6e8bb
PB		 7454 } else if (op & 0x40) {
7455 /* 64-bit accumulate. */
5e3f878a 7456 gen_addq(s, tmp, rs, rd);
9ee6e8bb 7457 }
5e3f878a 7458 gen_storeq_reg(s, rs, rd, tmp);
5fd46862 7459 }
2c0262af 7460 break;
9ee6e8bb
PB		 7461 }
7462 break;
7463 case 6: case 7: case 14: case 15:
7464 /* Coprocessor. */
7465 if (((insn >> 24) & 3) == 3) {
7466 /* Translate into the equivalent ARM encoding. */
7467 insn = (insn & 0xe2ffffff) | ((insn & (1 << 28)) >> 4);
7468 if (disas_neon_data_insn(env, s, insn))
7469 goto illegal_op;
7470 } else {
7471 if (insn & (1 << 28))
7472 goto illegal_op;
7473 if (disas_coproc_insn (env, s, insn))
7474 goto illegal_op;
7475 }
7476 break;
7477 case 8: case 9: case 10: case 11:
7478 if (insn & (1 << 15)) {
7479 /* Branches, misc control. */
7480 if (insn & 0x5000) {
7481 /* Unconditional branch. */
7482 /* signextend(hw1[10:0]) -> offset[:12]. */
7483 offset = ((int32_t)insn << 5) >> 9 & ~(int32_t)0xfff;
7484 /* hw1[10:0] -> offset[11:1]. */
7485 offset |= (insn & 0x7ff) << 1;
7486 /* (~hw2[13, 11] ^ offset[24]) -> offset[23,22]
7487 offset[24:22] already have the same value because of the
7488 sign extension above. */
7489 offset ^= ((~insn) & (1 << 13)) << 10;
7490 offset ^= ((~insn) & (1 << 11)) << 11;
7491
9ee6e8bb
PB		 7492 if (insn & (1 << 14)) {
7493 /* Branch and link. */
b0109805 7494 gen_op_movl_T1_im(s->pc | 1);
9ee6e8bb 7495 gen_movl_reg_T1(s, 14);
b5ff1b31 7496 }
3b46e624 7497
b0109805 7498 offset += s->pc;
9ee6e8bb
PB		 7499 if (insn & (1 << 12)) {
7500 /* b/bl */
b0109805 7501 gen_jmp(s, offset);
9ee6e8bb
PB		 7502 } else {
7503 /* blx */
b0109805
PB		 7504 offset &= ~(uint32_t)2;
7505 gen_bx_im(s, offset);
2c0262af 7506 }
9ee6e8bb
PB		 7507 } else if (((insn >> 23) & 7) == 7) {
7508 /* Misc control */
7509 if (insn & (1 << 13))
7510 goto illegal_op;
7511
7512 if (insn & (1 << 26)) {
7513 /* Secure monitor call (v6Z) */
7514 goto illegal_op; /* not implemented. */
2c0262af 7515 } else {
9ee6e8bb
PB		 7516 op = (insn >> 20) & 7;
7517 switch (op) {
7518 case 0: /* msr cpsr. */
7519 if (IS_M(env)) {
8984bd2e
PB		 7520 tmp = load_reg(s, rn);
7521 addr = tcg_const_i32(insn & 0xff);
7522 gen_helper_v7m_msr(cpu_env, addr, tmp);
9ee6e8bb
PB		 7523 gen_lookup_tb(s);
7524 break;
7525 }
7526 /* fall through */
7527 case 1: /* msr spsr. */
7528 if (IS_M(env))
7529 goto illegal_op;
7530 gen_movl_T0_reg(s, rn);
7531 if (gen_set_psr_T0(s,
7532 msr_mask(env, s, (insn >> 8) & 0xf, op == 1),
7533 op == 1))
7534 goto illegal_op;
7535 break;
7536 case 2: /* cps, nop-hint. */
7537 if (((insn >> 8) & 7) == 0) {
7538 gen_nop_hint(s, insn & 0xff);
7539 }
7540 /* Implemented as NOP in user mode. */
7541 if (IS_USER(s))
7542 break;
7543 offset = 0;
7544 imm = 0;
7545 if (insn & (1 << 10)) {
7546 if (insn & (1 << 7))
7547 offset |= CPSR_A;
7548 if (insn & (1 << 6))
7549 offset |= CPSR_I;
7550 if (insn & (1 << 5))
7551 offset |= CPSR_F;
7552 if (insn & (1 << 9))
7553 imm = CPSR_A | CPSR_I | CPSR_F;
7554 }
7555 if (insn & (1 << 8)) {
7556 offset |= 0x1f;
7557 imm |= (insn & 0x1f);
7558 }
7559 if (offset) {
7560 gen_op_movl_T0_im(imm);
7561 gen_set_psr_T0(s, offset, 0);
7562 }
7563 break;
7564 case 3: /* Special control operations. */
7565 op = (insn >> 4) & 0xf;
7566 switch (op) {
7567 case 2: /* clrex */
8f8e3aa4 7568 gen_helper_clrex(cpu_env);
9ee6e8bb
PB		 7569 break;
7570 case 4: /* dsb */
7571 case 5: /* dmb */
7572 case 6: /* isb */
7573 /* These execute as NOPs. */
7574 ARCH(7);
7575 break;
7576 default:
7577 goto illegal_op;
7578 }
7579 break;
7580 case 4: /* bxj */
7581 /* Trivial implementation equivalent to bx. */
d9ba4830
PB		 7582 tmp = load_reg(s, rn);
7583 gen_bx(s, tmp);
9ee6e8bb
PB		 7584 break;
7585 case 5: /* Exception return. */
7586 /* Unpredictable in user mode. */
7587 goto illegal_op;
7588 case 6: /* mrs cpsr. */
8984bd2e 7589 tmp = new_tmp();
9ee6e8bb 7590 if (IS_M(env)) {
8984bd2e
PB		 7591 addr = tcg_const_i32(insn & 0xff);
7592 gen_helper_v7m_mrs(tmp, cpu_env, addr);
9ee6e8bb 7593 } else {
8984bd2e 7594 gen_helper_cpsr_read(tmp);
9ee6e8bb 7595 }
8984bd2e 7596 store_reg(s, rd, tmp);
9ee6e8bb
PB		 7597 break;
7598 case 7: /* mrs spsr. */
7599 /* Not accessible in user mode. */
7600 if (IS_USER(s) || IS_M(env))
7601 goto illegal_op;
d9ba4830
PB		 7602 tmp = load_cpu_field(spsr);
7603 store_reg(s, rd, tmp);
9ee6e8bb 7604 break;
2c0262af
FB		 7605 }
7606 }
9ee6e8bb
PB		 7607 } else {
7608 /* Conditional branch. */
7609 op = (insn >> 22) & 0xf;
7610 /* Generate a conditional jump to next instruction. */
7611 s->condlabel = gen_new_label();
d9ba4830 7612 gen_test_cc(op ^ 1, s->condlabel);
9ee6e8bb
PB		 7613 s->condjmp = 1;
7614
7615 /* offset[11:1] = insn[10:0] */
7616 offset = (insn & 0x7ff) << 1;
7617 /* offset[17:12] = insn[21:16]. */
7618 offset |= (insn & 0x003f0000) >> 4;
7619 /* offset[31:20] = insn[26]. */
7620 offset |= ((int32_t)((insn << 5) & 0x80000000)) >> 11;
7621 /* offset[18] = insn[13]. */
7622 offset |= (insn & (1 << 13)) << 5;
7623 /* offset[19] = insn[11]. */
7624 offset |= (insn & (1 << 11)) << 8;
7625
7626 /* jump to the offset */
b0109805 7627 gen_jmp(s, s->pc + offset);
9ee6e8bb
PB		 7628 }
7629 } else {
7630 /* Data processing immediate. */
7631 if (insn & (1 << 25)) {
7632 if (insn & (1 << 24)) {
7633 if (insn & (1 << 20))
7634 goto illegal_op;
7635 /* Bitfield/Saturate. */
7636 op = (insn >> 21) & 7;
7637 imm = insn & 0x1f;
7638 shift = ((insn >> 6) & 3) | ((insn >> 10) & 0x1c);
6ddbc6e4
PB		 7639 if (rn == 15) {
7640 tmp = new_tmp();
7641 tcg_gen_movi_i32(tmp, 0);
7642 } else {
7643 tmp = load_reg(s, rn);
7644 }
9ee6e8bb
PB		 7645 switch (op) {
7646 case 2: /* Signed bitfield extract. */
7647 imm++;
7648 if (shift + imm > 32)
7649 goto illegal_op;
7650 if (imm < 32)
6ddbc6e4 7651 gen_sbfx(tmp, shift, imm);
9ee6e8bb
PB		 7652 break;
7653 case 6: /* Unsigned bitfield extract. */
7654 imm++;
7655 if (shift + imm > 32)
7656 goto illegal_op;
7657 if (imm < 32)
6ddbc6e4 7658 gen_ubfx(tmp, shift, (1u << imm) - 1);
9ee6e8bb
PB		 7659 break;
7660 case 3: /* Bitfield insert/clear. */
7661 if (imm < shift)
7662 goto illegal_op;
7663 imm = imm + 1 - shift;
7664 if (imm != 32) {
6ddbc6e4 7665 tmp2 = load_reg(s, rd);
8f8e3aa4 7666 gen_bfi(tmp, tmp2, tmp, shift, (1u << imm) - 1);
6ddbc6e4 7667 dead_tmp(tmp2);
9ee6e8bb
PB		 7668 }
7669 break;
7670 case 7:
7671 goto illegal_op;
7672 default: /* Saturate. */
9ee6e8bb
PB		 7673 if (shift) {
7674 if (op & 1)
6ddbc6e4 7675 tcg_gen_sari_i32(tmp, tmp, shift);
9ee6e8bb 7676 else
6ddbc6e4 7677 tcg_gen_shli_i32(tmp, tmp, shift);
9ee6e8bb 7678 }
6ddbc6e4 7679 tmp2 = tcg_const_i32(imm);
9ee6e8bb
PB		 7680 if (op & 4) {
7681 /* Unsigned. */
9ee6e8bb 7682 if ((op & 1) && shift == 0)
6ddbc6e4 7683 gen_helper_usat16(tmp, tmp, tmp2);
9ee6e8bb 7684 else
6ddbc6e4 7685 gen_helper_usat(tmp, tmp, tmp2);
2c0262af 7686 } else {
9ee6e8bb 7687 /* Signed. */
9ee6e8bb 7688 if ((op & 1) && shift == 0)
6ddbc6e4 7689 gen_helper_ssat16(tmp, tmp, tmp2);
9ee6e8bb 7690 else
6ddbc6e4 7691 gen_helper_ssat(tmp, tmp, tmp2);
2c0262af 7692 }
9ee6e8bb 7693 break;
2c0262af 7694 }
6ddbc6e4 7695 store_reg(s, rd, tmp);
9ee6e8bb
PB		 7696 } else {
7697 imm = ((insn & 0x04000000) >> 15)
7698 | ((insn & 0x7000) >> 4) | (insn & 0xff);
7699 if (insn & (1 << 22)) {
7700 /* 16-bit immediate. */
7701 imm |= (insn >> 4) & 0xf000;
7702 if (insn & (1 << 23)) {
7703 /* movt */
5e3f878a
PB		 7704 tmp = load_reg(s, rd);
7705 tcg_gen_andi_i32(tmp, tmp, 0xffff);
7706 tcg_gen_ori_i32(tmp, tmp, imm << 16);
2c0262af 7707 } else {
9ee6e8bb 7708 /* movw */
5e3f878a
PB		 7709 tmp = new_tmp();
7710 tcg_gen_movi_i32(tmp, imm);
2c0262af
FB		 7711 }
7712 } else {
9ee6e8bb
PB		 7713 /* Add/sub 12-bit immediate. */
7714 if (rn == 15) {
b0109805 7715 offset = s->pc & ~(uint32_t)3;
9ee6e8bb 7716 if (insn & (1 << 23))
b0109805 7717 offset -= imm;
9ee6e8bb 7718 else
b0109805 7719 offset += imm;
5e3f878a
PB		 7720 tmp = new_tmp();
7721 tcg_gen_movi_i32(tmp, offset);
2c0262af 7722 } else {
5e3f878a 7723 tmp = load_reg(s, rn);
9ee6e8bb 7724 if (insn & (1 << 23))
5e3f878a 7725 tcg_gen_subi_i32(tmp, tmp, imm);
9ee6e8bb 7726 else
5e3f878a 7727 tcg_gen_addi_i32(tmp, tmp, imm);
2c0262af 7728 }
9ee6e8bb 7729 }
5e3f878a 7730 store_reg(s, rd, tmp);
191abaa2 7731 }
9ee6e8bb
PB		 7732 } else {
7733 int shifter_out = 0;
7734 /* modified 12-bit immediate. */
7735 shift = ((insn & 0x04000000) >> 23) | ((insn & 0x7000) >> 12);
7736 imm = (insn & 0xff);
7737 switch (shift) {
7738 case 0: /* XY */
7739 /* Nothing to do. */
7740 break;
7741 case 1: /* 00XY00XY */
7742 imm |= imm << 16;
7743 break;
7744 case 2: /* XY00XY00 */
7745 imm |= imm << 16;
7746 imm <<= 8;
7747 break;
7748 case 3: /* XYXYXYXY */
7749 imm |= imm << 16;
7750 imm |= imm << 8;
7751 break;
7752 default: /* Rotated constant. */
7753 shift = (shift << 1) | (imm >> 7);
7754 imm |= 0x80;
7755 imm = imm << (32 - shift);
7756 shifter_out = 1;
7757 break;
b5ff1b31 7758 }
9ee6e8bb
PB		 7759 gen_op_movl_T1_im(imm);
7760 rn = (insn >> 16) & 0xf;
7761 if (rn == 15)
7762 gen_op_movl_T0_im(0);
7763 else
7764 gen_movl_T0_reg(s, rn);
7765 op = (insn >> 21) & 0xf;
7766 if (gen_thumb2_data_op(s, op, (insn & (1 << 20)) != 0,
7767 shifter_out))
7768 goto illegal_op;
7769 rd = (insn >> 8) & 0xf;
7770 if (rd != 15) {
7771 gen_movl_reg_T0(s, rd);
2c0262af 7772 }
2c0262af 7773 }
9ee6e8bb
PB		 7774 }
7775 break;
7776 case 12: /* Load/store single data item. */
7777 {
7778 int postinc = 0;
7779 int writeback = 0;
b0109805 7780 int user;
9ee6e8bb
PB		 7781 if ((insn & 0x01100000) == 0x01000000) {
7782 if (disas_neon_ls_insn(env, s, insn))
c1713132 7783 goto illegal_op;
9ee6e8bb
PB		 7784 break;
7785 }
b0109805 7786 user = IS_USER(s);
9ee6e8bb 7787 if (rn == 15) {
b0109805 7788 addr = new_tmp();
9ee6e8bb
PB		 7789 /* PC relative. */
7790 /* s->pc has already been incremented by 4. */
7791 imm = s->pc & 0xfffffffc;
7792 if (insn & (1 << 23))
7793 imm += insn & 0xfff;
7794 else
7795 imm -= insn & 0xfff;
b0109805 7796 tcg_gen_movi_i32(addr, imm);
9ee6e8bb 7797 } else {
b0109805 7798 addr = load_reg(s, rn);
9ee6e8bb
PB		 7799 if (insn & (1 << 23)) {
7800 /* Positive offset. */
7801 imm = insn & 0xfff;
b0109805 7802 tcg_gen_addi_i32(addr, addr, imm);
9ee6e8bb
PB		 7803 } else {
7804 op = (insn >> 8) & 7;
7805 imm = insn & 0xff;
7806 switch (op) {
7807 case 0: case 8: /* Shifted Register. */
7808 shift = (insn >> 4) & 0xf;
7809 if (shift > 3)
18c9b560 7810 goto illegal_op;
b26eefb6 7811 tmp = load_reg(s, rm);
9ee6e8bb 7812 if (shift)
b26eefb6 7813 tcg_gen_shli_i32(tmp, tmp, shift);
b0109805 7814 tcg_gen_add_i32(addr, addr, tmp);
b26eefb6 7815 dead_tmp(tmp);
9ee6e8bb
PB		 7816 break;
7817 case 4: /* Negative offset. */
b0109805 7818 tcg_gen_addi_i32(addr, addr, -imm);
9ee6e8bb
PB		 7819 break;
7820 case 6: /* User privilege. */
b0109805
PB		 7821 tcg_gen_addi_i32(addr, addr, imm);
7822 user = 1;
9ee6e8bb
PB		 7823 break;
7824 case 1: /* Post-decrement. */
7825 imm = -imm;
7826 /* Fall through. */
7827 case 3: /* Post-increment. */
9ee6e8bb
PB		 7828 postinc = 1;
7829 writeback = 1;
7830 break;
7831 case 5: /* Pre-decrement. */
7832 imm = -imm;
7833 /* Fall through. */
7834 case 7: /* Pre-increment. */
b0109805 7835 tcg_gen_addi_i32(addr, addr, imm);
9ee6e8bb
PB		 7836 writeback = 1;
7837 break;
7838 default:
b7bcbe95 7839 goto illegal_op;
9ee6e8bb
PB		 7840 }
7841 }
7842 }
7843 op = ((insn >> 21) & 3) | ((insn >> 22) & 4);
7844 if (insn & (1 << 20)) {
7845 /* Load. */
7846 if (rs == 15 && op != 2) {
7847 if (op & 2)
b5ff1b31 7848 goto illegal_op;
9ee6e8bb
PB		 7849 /* Memory hint. Implemented as NOP. */
7850 } else {
7851 switch (op) {
b0109805
PB		 7852 case 0: tmp = gen_ld8u(addr, user); break;
7853 case 4: tmp = gen_ld8s(addr, user); break;
7854 case 1: tmp = gen_ld16u(addr, user); break;
7855 case 5: tmp = gen_ld16s(addr, user); break;
7856 case 2: tmp = gen_ld32(addr, user); break;
9ee6e8bb
PB		 7857 default: goto illegal_op;
7858 }
7859 if (rs == 15) {
b0109805 7860 gen_bx(s, tmp);
9ee6e8bb 7861 } else {
b0109805 7862 store_reg(s, rs, tmp);
9ee6e8bb
PB		 7863 }
7864 }
7865 } else {
7866 /* Store. */
7867 if (rs == 15)
b7bcbe95 7868 goto illegal_op;
b0109805 7869 tmp = load_reg(s, rs);
9ee6e8bb 7870 switch (op) {
b0109805
PB		 7871 case 0: gen_st8(tmp, addr, user); break;
7872 case 1: gen_st16(tmp, addr, user); break;
7873 case 2: gen_st32(tmp, addr, user); break;
9ee6e8bb 7874 default: goto illegal_op;
b7bcbe95 7875 }
2c0262af 7876 }
9ee6e8bb 7877 if (postinc)
b0109805
PB		 7878 tcg_gen_addi_i32(addr, addr, imm);
7879 if (writeback) {
7880 store_reg(s, rn, addr);
7881 } else {
7882 dead_tmp(addr);
7883 }
9ee6e8bb
PB		 7884 }
7885 break;
7886 default:
7887 goto illegal_op;
2c0262af 7888 }
9ee6e8bb
PB		 7889 return 0;
7890illegal_op:
7891 return 1;
2c0262af
FB		 7892}
7893
9ee6e8bb 7894static void disas_thumb_insn(CPUState *env, DisasContext *s)
99c475ab
FB		 7895{
7896 uint32_t val, insn, op, rm, rn, rd, shift, cond;
7897 int32_t offset;
7898 int i;
b26eefb6 7899 TCGv tmp;
d9ba4830 7900 TCGv tmp2;
b0109805 7901 TCGv addr;
99c475ab 7902
9ee6e8bb
PB		 7903 if (s->condexec_mask) {
7904 cond = s->condexec_cond;
7905 s->condlabel = gen_new_label();
d9ba4830 7906 gen_test_cc(cond ^ 1, s->condlabel);
9ee6e8bb
PB		 7907 s->condjmp = 1;
7908 }
7909
b5ff1b31 7910 insn = lduw_code(s->pc);
99c475ab 7911 s->pc += 2;
b5ff1b31 7912
99c475ab
FB		 7913 switch (insn >> 12) {
7914 case 0: case 1:
7915 rd = insn & 7;
7916 op = (insn >> 11) & 3;
7917 if (op == 3) {
7918 /* add/subtract */
7919 rn = (insn >> 3) & 7;
7920 gen_movl_T0_reg(s, rn);
7921 if (insn & (1 << 10)) {
7922 /* immediate */
7923 gen_op_movl_T1_im((insn >> 6) & 7);
7924 } else {
7925 /* reg */
7926 rm = (insn >> 6) & 7;
7927 gen_movl_T1_reg(s, rm);
7928 }
9ee6e8bb
PB		 7929 if (insn & (1 << 9)) {
7930 if (s->condexec_mask)
7931 gen_op_subl_T0_T1();
7932 else
7933 gen_op_subl_T0_T1_cc();
7934 } else {
7935 if (s->condexec_mask)
7936 gen_op_addl_T0_T1();
7937 else
7938 gen_op_addl_T0_T1_cc();
7939 }
99c475ab
FB		 7940 gen_movl_reg_T0(s, rd);
7941 } else {
7942 /* shift immediate */
7943 rm = (insn >> 3) & 7;
7944 shift = (insn >> 6) & 0x1f;
9a119ff6
PB		 7945 tmp = load_reg(s, rm);
7946 gen_arm_shift_im(tmp, op, shift, s->condexec_mask == 0);
7947 if (!s->condexec_mask)
7948 gen_logic_CC(tmp);
7949 store_reg(s, rd, tmp);
99c475ab
FB		 7950 }
7951 break;
7952 case 2: case 3:
7953 /* arithmetic large immediate */
7954 op = (insn >> 11) & 3;
7955 rd = (insn >> 8) & 0x7;
7956 if (op == 0) {
7957 gen_op_movl_T0_im(insn & 0xff);
7958 } else {
7959 gen_movl_T0_reg(s, rd);
7960 gen_op_movl_T1_im(insn & 0xff);
7961 }
7962 switch (op) {
7963 case 0: /* mov */
9ee6e8bb
PB		 7964 if (!s->condexec_mask)
7965 gen_op_logic_T0_cc();
99c475ab
FB		 7966 break;
7967 case 1: /* cmp */
7968 gen_op_subl_T0_T1_cc();
7969 break;
7970 case 2: /* add */
9ee6e8bb
PB		 7971 if (s->condexec_mask)
7972 gen_op_addl_T0_T1();
7973 else
7974 gen_op_addl_T0_T1_cc();
99c475ab
FB		 7975 break;
7976 case 3: /* sub */
9ee6e8bb
PB		 7977 if (s->condexec_mask)
7978 gen_op_subl_T0_T1();
7979 else
7980 gen_op_subl_T0_T1_cc();
99c475ab
FB		 7981 break;
7982 }
7983 if (op != 1)
7984 gen_movl_reg_T0(s, rd);
7985 break;
7986 case 4:
7987 if (insn & (1 << 11)) {
7988 rd = (insn >> 8) & 7;
5899f386
FB		 7989 /* load pc-relative. Bit 1 of PC is ignored. */
7990 val = s->pc + 2 + ((insn & 0xff) * 4);
7991 val &= ~(uint32_t)2;
b0109805
PB		 7992 addr = new_tmp();
7993 tcg_gen_movi_i32(addr, val);
7994 tmp = gen_ld32(addr, IS_USER(s));
7995 dead_tmp(addr);
7996 store_reg(s, rd, tmp);
99c475ab
FB		 7997 break;
7998 }
7999 if (insn & (1 << 10)) {
8000 /* data processing extended or blx */
8001 rd = (insn & 7) | ((insn >> 4) & 8);
8002 rm = (insn >> 3) & 0xf;
8003 op = (insn >> 8) & 3;
8004 switch (op) {
8005 case 0: /* add */
8006 gen_movl_T0_reg(s, rd);
8007 gen_movl_T1_reg(s, rm);
8008 gen_op_addl_T0_T1();
8009 gen_movl_reg_T0(s, rd);
8010 break;
8011 case 1: /* cmp */
8012 gen_movl_T0_reg(s, rd);
8013 gen_movl_T1_reg(s, rm);
8014 gen_op_subl_T0_T1_cc();
8015 break;
8016 case 2: /* mov/cpy */
8017 gen_movl_T0_reg(s, rm);
8018 gen_movl_reg_T0(s, rd);
8019 break;
8020 case 3:/* branch [and link] exchange thumb register */
b0109805 8021 tmp = load_reg(s, rm);
99c475ab
FB		 8022 if (insn & (1 << 7)) {
8023 val = (uint32_t)s->pc | 1;
b0109805
PB		 8024 tmp2 = new_tmp();
8025 tcg_gen_movi_i32(tmp2, val);
8026 store_reg(s, 14, tmp2);
99c475ab 8027 }
d9ba4830 8028 gen_bx(s, tmp);
99c475ab
FB		 8029 break;
8030 }
8031 break;
8032 }
8033
8034 /* data processing register */
8035 rd = insn & 7;
8036 rm = (insn >> 3) & 7;
8037 op = (insn >> 6) & 0xf;
8038 if (op == 2 || op == 3 || op == 4 || op == 7) {
8039 /* the shift/rotate ops want the operands backwards */
8040 val = rm;
8041 rm = rd;
8042 rd = val;
8043 val = 1;
8044 } else {
8045 val = 0;
8046 }
8047
8048 if (op == 9) /* neg */
8049 gen_op_movl_T0_im(0);
8050 else if (op != 0xf) /* mvn doesn't read its first operand */
8051 gen_movl_T0_reg(s, rd);
8052
8053 gen_movl_T1_reg(s, rm);
5899f386 8054 switch (op) {
99c475ab
FB		 8055 case 0x0: /* and */
8056 gen_op_andl_T0_T1();
9ee6e8bb
PB		 8057 if (!s->condexec_mask)
8058 gen_op_logic_T0_cc();
99c475ab
FB		 8059 break;
8060 case 0x1: /* eor */
8061 gen_op_xorl_T0_T1();
9ee6e8bb
PB		 8062 if (!s->condexec_mask)
8063 gen_op_logic_T0_cc();
99c475ab
FB		 8064 break;
8065 case 0x2: /* lsl */
9ee6e8bb 8066 if (s->condexec_mask) {
8984bd2e 8067 gen_helper_shl(cpu_T[1], cpu_T[1], cpu_T[0]);
9ee6e8bb 8068 } else {
8984bd2e 8069 gen_helper_shl_cc(cpu_T[1], cpu_T[1], cpu_T[0]);
9ee6e8bb
PB		 8070 gen_op_logic_T1_cc();
8071 }
99c475ab
FB		 8072 break;
8073 case 0x3: /* lsr */
9ee6e8bb 8074 if (s->condexec_mask) {
8984bd2e 8075 gen_helper_shr(cpu_T[1], cpu_T[1], cpu_T[0]);
9ee6e8bb 8076 } else {
8984bd2e 8077 gen_helper_shr_cc(cpu_T[1], cpu_T[1], cpu_T[0]);
9ee6e8bb
PB		 8078 gen_op_logic_T1_cc();
8079 }
99c475ab
FB		 8080 break;
8081 case 0x4: /* asr */
9ee6e8bb 8082 if (s->condexec_mask) {
8984bd2e 8083 gen_helper_sar(cpu_T[1], cpu_T[1], cpu_T[0]);
9ee6e8bb 8084 } else {
8984bd2e 8085 gen_helper_sar_cc(cpu_T[1], cpu_T[1], cpu_T[0]);
9ee6e8bb
PB		 8086 gen_op_logic_T1_cc();
8087 }
99c475ab
FB		 8088 break;
8089 case 0x5: /* adc */
9ee6e8bb 8090 if (s->condexec_mask)
b26eefb6 8091 gen_adc_T0_T1();
9ee6e8bb
PB		 8092 else
8093 gen_op_adcl_T0_T1_cc();
99c475ab
FB		 8094 break;
8095 case 0x6: /* sbc */
9ee6e8bb 8096 if (s->condexec_mask)
3670669c 8097 gen_sbc_T0_T1();
9ee6e8bb
PB		 8098 else
8099 gen_op_sbcl_T0_T1_cc();
99c475ab
FB		 8100 break;
8101 case 0x7: /* ror */
9ee6e8bb 8102 if (s->condexec_mask) {
8984bd2e 8103 gen_helper_ror(cpu_T[1], cpu_T[1], cpu_T[0]);
9ee6e8bb 8104 } else {
8984bd2e 8105 gen_helper_ror_cc(cpu_T[1], cpu_T[1], cpu_T[0]);
9ee6e8bb
PB		 8106 gen_op_logic_T1_cc();
8107 }
99c475ab
FB		 8108 break;
8109 case 0x8: /* tst */
8110 gen_op_andl_T0_T1();
8111 gen_op_logic_T0_cc();
8112 rd = 16;
5899f386 8113 break;
99c475ab 8114 case 0x9: /* neg */
9ee6e8bb
PB		 8115 if (s->condexec_mask)
8116 gen_op_subl_T0_T1();
8117 else
8118 gen_op_subl_T0_T1_cc();
99c475ab
FB		 8119 break;
8120 case 0xa: /* cmp */
8121 gen_op_subl_T0_T1_cc();
8122 rd = 16;
8123 break;
8124 case 0xb: /* cmn */
8125 gen_op_addl_T0_T1_cc();
8126 rd = 16;
8127 break;
8128 case 0xc: /* orr */
8129 gen_op_orl_T0_T1();
9ee6e8bb
PB		 8130 if (!s->condexec_mask)
8131 gen_op_logic_T0_cc();
99c475ab
FB		 8132 break;
8133 case 0xd: /* mul */
8134 gen_op_mull_T0_T1();
9ee6e8bb
PB		 8135 if (!s->condexec_mask)
8136 gen_op_logic_T0_cc();
99c475ab
FB		 8137 break;
8138 case 0xe: /* bic */
8139 gen_op_bicl_T0_T1();
9ee6e8bb
PB		 8140 if (!s->condexec_mask)
8141 gen_op_logic_T0_cc();
99c475ab
FB		 8142 break;
8143 case 0xf: /* mvn */
8144 gen_op_notl_T1();
9ee6e8bb
PB		 8145 if (!s->condexec_mask)
8146 gen_op_logic_T1_cc();
99c475ab 8147 val = 1;
5899f386 8148 rm = rd;
99c475ab
FB		 8149 break;
8150 }
8151 if (rd != 16) {
8152 if (val)
5899f386 8153 gen_movl_reg_T1(s, rm);
99c475ab
FB		 8154 else
8155 gen_movl_reg_T0(s, rd);
8156 }
8157 break;
8158
8159 case 5:
8160 /* load/store register offset. */
8161 rd = insn & 7;
8162 rn = (insn >> 3) & 7;
8163 rm = (insn >> 6) & 7;
8164 op = (insn >> 9) & 7;
b0109805 8165 addr = load_reg(s, rn);
b26eefb6 8166 tmp = load_reg(s, rm);
b0109805 8167 tcg_gen_add_i32(addr, addr, tmp);
b26eefb6 8168 dead_tmp(tmp);
99c475ab
FB		 8169
8170 if (op < 3) /* store */
b0109805 8171 tmp = load_reg(s, rd);
99c475ab
FB		 8172
8173 switch (op) {
8174 case 0: /* str */
b0109805 8175 gen_st32(tmp, addr, IS_USER(s));
99c475ab
FB		 8176 break;
8177 case 1: /* strh */
b0109805 8178 gen_st16(tmp, addr, IS_USER(s));
99c475ab
FB		 8179 break;
8180 case 2: /* strb */
b0109805 8181 gen_st8(tmp, addr, IS_USER(s));
99c475ab
FB		 8182 break;
8183 case 3: /* ldrsb */
b0109805 8184 tmp = gen_ld8s(addr, IS_USER(s));
99c475ab
FB		 8185 break;
8186 case 4: /* ldr */
b0109805 8187 tmp = gen_ld32(addr, IS_USER(s));
99c475ab
FB		 8188 break;
8189 case 5: /* ldrh */
b0109805 8190 tmp = gen_ld16u(addr, IS_USER(s));
99c475ab
FB		 8191 break;
8192 case 6: /* ldrb */
b0109805 8193 tmp = gen_ld8u(addr, IS_USER(s));
99c475ab
FB		 8194 break;
8195 case 7: /* ldrsh */
b0109805 8196 tmp = gen_ld16s(addr, IS_USER(s));
99c475ab
FB		 8197 break;
8198 }
8199 if (op >= 3) /* load */
b0109805
PB		 8200 store_reg(s, rd, tmp);
8201 dead_tmp(addr);
99c475ab
FB		 8202 break;
8203
8204 case 6:
8205 /* load/store word immediate offset */
8206 rd = insn & 7;
8207 rn = (insn >> 3) & 7;
b0109805 8208 addr = load_reg(s, rn);
99c475ab 8209 val = (insn >> 4) & 0x7c;
b0109805 8210 tcg_gen_addi_i32(addr, addr, val);
99c475ab
FB		 8211
8212 if (insn & (1 << 11)) {
8213 /* load */
b0109805
PB		 8214 tmp = gen_ld32(addr, IS_USER(s));
8215 store_reg(s, rd, tmp);
99c475ab
FB		 8216 } else {
8217 /* store */
b0109805
PB		 8218 tmp = load_reg(s, rd);
8219 gen_st32(tmp, addr, IS_USER(s));
99c475ab 8220 }
b0109805 8221 dead_tmp(addr);
99c475ab
FB		 8222 break;
8223
8224 case 7:
8225 /* load/store byte immediate offset */
8226 rd = insn & 7;
8227 rn = (insn >> 3) & 7;
b0109805 8228 addr = load_reg(s, rn);
99c475ab 8229 val = (insn >> 6) & 0x1f;
b0109805 8230 tcg_gen_addi_i32(addr, addr, val);
99c475ab
FB		 8231
8232 if (insn & (1 << 11)) {
8233 /* load */
b0109805
PB		 8234 tmp = gen_ld8u(addr, IS_USER(s));
8235 store_reg(s, rd, tmp);
99c475ab
FB		 8236 } else {
8237 /* store */
b0109805
PB		 8238 tmp = load_reg(s, rd);
8239 gen_st8(tmp, addr, IS_USER(s));
99c475ab 8240 }
b0109805 8241 dead_tmp(addr);
99c475ab
FB		 8242 break;
8243
8244 case 8:
8245 /* load/store halfword immediate offset */
8246 rd = insn & 7;
8247 rn = (insn >> 3) & 7;
b0109805 8248 addr = load_reg(s, rn);
99c475ab 8249 val = (insn >> 5) & 0x3e;
b0109805 8250 tcg_gen_addi_i32(addr, addr, val);
99c475ab
FB		 8251
8252 if (insn & (1 << 11)) {
8253 /* load */
b0109805
PB		 8254 tmp = gen_ld16u(addr, IS_USER(s));
8255 store_reg(s, rd, tmp);
99c475ab
FB		 8256 } else {
8257 /* store */
b0109805
PB		 8258 tmp = load_reg(s, rd);
8259 gen_st16(tmp, addr, IS_USER(s));
99c475ab 8260 }
b0109805 8261 dead_tmp(addr);
99c475ab
FB		 8262 break;
8263
8264 case 9:
8265 /* load/store from stack */
8266 rd = (insn >> 8) & 7;
b0109805 8267 addr = load_reg(s, 13);
99c475ab 8268 val = (insn & 0xff) * 4;
b0109805 8269 tcg_gen_addi_i32(addr, addr, val);
99c475ab
FB		 8270
8271 if (insn & (1 << 11)) {
8272 /* load */
b0109805
PB		 8273 tmp = gen_ld32(addr, IS_USER(s));
8274 store_reg(s, rd, tmp);
99c475ab
FB		 8275 } else {
8276 /* store */
b0109805
PB		 8277 tmp = load_reg(s, rd);
8278 gen_st32(tmp, addr, IS_USER(s));
99c475ab 8279 }
b0109805 8280 dead_tmp(addr);
99c475ab
FB		 8281 break;
8282
8283 case 10:
8284 /* add to high reg */
8285 rd = (insn >> 8) & 7;
5899f386
FB		 8286 if (insn & (1 << 11)) {
8287 /* SP */
5e3f878a 8288 tmp = load_reg(s, 13);
5899f386
FB		 8289 } else {
8290 /* PC. bit 1 is ignored. */
5e3f878a
PB		 8291 tmp = new_tmp();
8292 tcg_gen_movi_i32(tmp, (s->pc + 2) & ~(uint32_t)2);
5899f386 8293 }
99c475ab 8294 val = (insn & 0xff) * 4;
5e3f878a
PB		 8295 tcg_gen_addi_i32(tmp, tmp, val);
8296 store_reg(s, rd, tmp);
99c475ab
FB		 8297 break;
8298
8299 case 11:
8300 /* misc */
8301 op = (insn >> 8) & 0xf;
8302 switch (op) {
8303 case 0:
8304 /* adjust stack pointer */
b26eefb6 8305 tmp = load_reg(s, 13);
99c475ab
FB		 8306 val = (insn & 0x7f) * 4;
8307 if (insn & (1 << 7))
8308 val = -(int32_t)val;
b26eefb6
PB		 8309 tcg_gen_addi_i32(tmp, tmp, val);
8310 store_reg(s, 13, tmp);
99c475ab
FB		 8311 break;
8312
9ee6e8bb
PB		 8313 case 2: /* sign/zero extend. */
8314 ARCH(6);
8315 rd = insn & 7;
8316 rm = (insn >> 3) & 7;
b0109805 8317 tmp = load_reg(s, rm);
9ee6e8bb 8318 switch ((insn >> 6) & 3) {
b0109805
PB		 8319 case 0: gen_sxth(tmp); break;
8320 case 1: gen_sxtb(tmp); break;
8321 case 2: gen_uxth(tmp); break;
8322 case 3: gen_uxtb(tmp); break;
9ee6e8bb 8323 }
b0109805 8324 store_reg(s, rd, tmp);
9ee6e8bb 8325 break;
99c475ab
FB		 8326 case 4: case 5: case 0xc: case 0xd:
8327 /* push/pop */
b0109805 8328 addr = load_reg(s, 13);
5899f386
FB		 8329 if (insn & (1 << 8))
8330 offset = 4;
99c475ab 8331 else
5899f386
FB		 8332 offset = 0;
8333 for (i = 0; i < 8; i++) {
8334 if (insn & (1 << i))
8335 offset += 4;
8336 }
8337 if ((insn & (1 << 11)) == 0) {
b0109805 8338 tcg_gen_addi_i32(addr, addr, -offset);
5899f386 8339 }
99c475ab
FB		 8340 for (i = 0; i < 8; i++) {
8341 if (insn & (1 << i)) {
8342 if (insn & (1 << 11)) {
8343 /* pop */
b0109805
PB		 8344 tmp = gen_ld32(addr, IS_USER(s));
8345 store_reg(s, i, tmp);
99c475ab
FB		 8346 } else {
8347 /* push */
b0109805
PB		 8348 tmp = load_reg(s, i);
8349 gen_st32(tmp, addr, IS_USER(s));
99c475ab 8350 }
5899f386 8351 /* advance to the next address. */
b0109805 8352 tcg_gen_addi_i32(addr, addr, 4);
99c475ab
FB		 8353 }
8354 }
8355 if (insn & (1 << 8)) {
8356 if (insn & (1 << 11)) {
8357 /* pop pc */
b0109805 8358 tmp = gen_ld32(addr, IS_USER(s));
99c475ab
FB		 8359 /* don't set the pc until the rest of the instruction
8360 has completed */
8361 } else {
8362 /* push lr */
b0109805
PB		 8363 tmp = load_reg(s, 14);
8364 gen_st32(tmp, addr, IS_USER(s));
99c475ab 8365 }
b0109805 8366 tcg_gen_addi_i32(addr, addr, 4);
99c475ab 8367 }
5899f386 8368 if ((insn & (1 << 11)) == 0) {
b0109805 8369 tcg_gen_addi_i32(addr, addr, -offset);
5899f386 8370 }
99c475ab 8371 /* write back the new stack pointer */
b0109805 8372 store_reg(s, 13, addr);
99c475ab
FB		 8373 /* set the new PC value */
8374 if ((insn & 0x0900) == 0x0900)
b0109805 8375 gen_bx(s, tmp);
99c475ab
FB		 8376 break;
8377
9ee6e8bb
PB		 8378 case 1: case 3: case 9: case 11: /* czb */
8379 rm = insn & 7;
d9ba4830
PB		 8380 tmp = load_reg(s, rm);
8381 tmp2 = tcg_const_i32(0);
9ee6e8bb
PB		 8382 s->condlabel = gen_new_label();
8383 s->condjmp = 1;
8384 if (insn & (1 << 11))
d9ba4830 8385 tcg_gen_brcond_i32(TCG_COND_EQ, tmp, tmp2, s->condlabel);
9ee6e8bb 8386 else
d9ba4830
PB		 8387 tcg_gen_brcond_i32(TCG_COND_NE, tmp, tmp2, s->condlabel);
8388 dead_tmp(tmp);
9ee6e8bb
PB		 8389 offset = ((insn & 0xf8) >> 2) | (insn & 0x200) >> 3;
8390 val = (uint32_t)s->pc + 2;
8391 val += offset;
8392 gen_jmp(s, val);
8393 break;
8394
8395 case 15: /* IT, nop-hint. */
8396 if ((insn & 0xf) == 0) {
8397 gen_nop_hint(s, (insn >> 4) & 0xf);
8398 break;
8399 }
8400 /* If Then. */
8401 s->condexec_cond = (insn >> 4) & 0xe;
8402 s->condexec_mask = insn & 0x1f;
8403 /* No actual code generated for this insn, just setup state. */
8404 break;
8405
06c949e6 8406 case 0xe: /* bkpt */
9ee6e8bb 8407 gen_set_condexec(s);
5e3f878a 8408 gen_set_pc_im(s->pc - 2);
d9ba4830 8409 gen_exception(EXCP_BKPT);
06c949e6
PB		 8410 s->is_jmp = DISAS_JUMP;
8411 break;
8412
9ee6e8bb
PB		 8413 case 0xa: /* rev */
8414 ARCH(6);
8415 rn = (insn >> 3) & 0x7;
8416 rd = insn & 0x7;
b0109805 8417 tmp = load_reg(s, rn);
9ee6e8bb 8418 switch ((insn >> 6) & 3) {
b0109805
PB		 8419 case 0: tcg_gen_bswap_i32(tmp, tmp); break;
8420 case 1: gen_rev16(tmp); break;
8421 case 3: gen_revsh(tmp); break;
9ee6e8bb
PB		 8422 default: goto illegal_op;
8423 }
b0109805 8424 store_reg(s, rd, tmp);
9ee6e8bb
PB		 8425 break;
8426
8427 case 6: /* cps */
8428 ARCH(6);
8429 if (IS_USER(s))
8430 break;
8431 if (IS_M(env)) {
8984bd2e 8432 tmp = tcg_const_i32((insn & (1 << 4)) != 0);
9ee6e8bb 8433 /* PRIMASK */
8984bd2e
PB		 8434 if (insn & 1) {
8435 addr = tcg_const_i32(16);
8436 gen_helper_v7m_msr(cpu_env, addr, tmp);
8437 }
9ee6e8bb 8438 /* FAULTMASK */
8984bd2e
PB		 8439 if (insn & 2) {
8440 addr = tcg_const_i32(17);
8441 gen_helper_v7m_msr(cpu_env, addr, tmp);
8442 }
9ee6e8bb
PB		 8443 gen_lookup_tb(s);
8444 } else {
8445 if (insn & (1 << 4))
8446 shift = CPSR_A | CPSR_I | CPSR_F;
8447 else
8448 shift = 0;
8449
8450 val = ((insn & 7) << 6) & shift;
8451 gen_op_movl_T0_im(val);
8452 gen_set_psr_T0(s, shift, 0);
8453 }
8454 break;
8455
99c475ab
FB		 8456 default:
8457 goto undef;
8458 }
8459 break;
8460
8461 case 12:
8462 /* load/store multiple */
8463 rn = (insn >> 8) & 0x7;
b0109805 8464 addr = load_reg(s, rn);
99c475ab
FB		 8465 for (i = 0; i < 8; i++) {
8466 if (insn & (1 << i)) {
99c475ab
FB		 8467 if (insn & (1 << 11)) {
8468 /* load */
b0109805
PB		 8469 tmp = gen_ld32(addr, IS_USER(s));
8470 store_reg(s, i, tmp);
99c475ab
FB		 8471 } else {
8472 /* store */
b0109805
PB		 8473 tmp = load_reg(s, i);
8474 gen_st32(tmp, addr, IS_USER(s));
99c475ab 8475 }
5899f386 8476 /* advance to the next address */
b0109805 8477 tcg_gen_addi_i32(addr, addr, 4);
99c475ab
FB		 8478 }
8479 }
5899f386 8480 /* Base register writeback. */
b0109805
PB		 8481 if ((insn & (1 << rn)) == 0) {
8482 store_reg(s, rn, addr);
8483 } else {
8484 dead_tmp(addr);
8485 }
99c475ab
FB		 8486 break;
8487
8488 case 13:
8489 /* conditional branch or swi */
8490 cond = (insn >> 8) & 0xf;
8491 if (cond == 0xe)
8492 goto undef;
8493
8494 if (cond == 0xf) {
8495 /* swi */
9ee6e8bb 8496 gen_set_condexec(s);
5e3f878a 8497 gen_set_pc_im(s->pc | 1);
9ee6e8bb 8498 s->is_jmp = DISAS_SWI;
99c475ab
FB		 8499 break;
8500 }
8501 /* generate a conditional jump to next instruction */
e50e6a20 8502 s->condlabel = gen_new_label();
d9ba4830 8503 gen_test_cc(cond ^ 1, s->condlabel);
e50e6a20 8504 s->condjmp = 1;
99c475ab
FB		 8505 gen_movl_T1_reg(s, 15);
8506
8507 /* jump to the offset */
5899f386 8508 val = (uint32_t)s->pc + 2;
99c475ab 8509 offset = ((int32_t)insn << 24) >> 24;
5899f386 8510 val += offset << 1;
8aaca4c0 8511 gen_jmp(s, val);
99c475ab
FB		 8512 break;
8513
8514 case 14:
358bf29e 8515 if (insn & (1 << 11)) {
9ee6e8bb
PB		 8516 if (disas_thumb2_insn(env, s, insn))
8517 goto undef32;
358bf29e
PB		 8518 break;
8519 }
9ee6e8bb 8520 /* unconditional branch */
99c475ab
FB		 8521 val = (uint32_t)s->pc;
8522 offset = ((int32_t)insn << 21) >> 21;
8523 val += (offset << 1) + 2;
8aaca4c0 8524 gen_jmp(s, val);
99c475ab
FB		 8525 break;
8526
8527 case 15:
9ee6e8bb
PB		 8528 if (disas_thumb2_insn(env, s, insn))
8529 goto undef32;
8530 break;
99c475ab
FB		 8531 }
8532 return;
9ee6e8bb
PB		 8533undef32:
8534 gen_set_condexec(s);
5e3f878a 8535 gen_set_pc_im(s->pc - 4);
d9ba4830 8536 gen_exception(EXCP_UDEF);
9ee6e8bb
PB		 8537 s->is_jmp = DISAS_JUMP;
8538 return;
8539illegal_op:
99c475ab 8540undef:
9ee6e8bb 8541 gen_set_condexec(s);
5e3f878a 8542 gen_set_pc_im(s->pc - 2);
d9ba4830 8543 gen_exception(EXCP_UDEF);
99c475ab
FB		 8544 s->is_jmp = DISAS_JUMP;
8545}
8546
2c0262af
FB		 8547/* generate intermediate code in gen_opc_buf and gen_opparam_buf for
8548 basic block 'tb'. If search_pc is TRUE, also generate PC
8549 information for each intermediate instruction. */
5fafdf24
TS		 8550static inline int gen_intermediate_code_internal(CPUState *env,
8551 TranslationBlock *tb,
2c0262af
FB		 8552 int search_pc)
8553{
8554 DisasContext dc1, *dc = &dc1;
8555 uint16_t *gen_opc_end;
8556 int j, lj;
0fa85d43 8557 target_ulong pc_start;
b5ff1b31 8558 uint32_t next_page_start;
3b46e624 8559
2c0262af 8560 /* generate intermediate code */
b26eefb6
PB		 8561 num_temps = 0;
8562 memset(temps, 0, sizeof(temps));
8563
0fa85d43 8564 pc_start = tb->pc;
3b46e624 8565
2c0262af
FB		 8566 dc->tb = tb;
8567
2c0262af 8568 gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
2c0262af
FB		 8569
8570 dc->is_jmp = DISAS_NEXT;
8571 dc->pc = pc_start;
8aaca4c0 8572 dc->singlestep_enabled = env->singlestep_enabled;
e50e6a20 8573 dc->condjmp = 0;
5899f386 8574 dc->thumb = env->thumb;
9ee6e8bb
PB		 8575 dc->condexec_mask = (env->condexec_bits & 0xf) << 1;
8576 dc->condexec_cond = env->condexec_bits >> 4;
6658ffb8 8577 dc->is_mem = 0;
b5ff1b31 8578#if !defined(CONFIG_USER_ONLY)
9ee6e8bb
PB		 8579 if (IS_M(env)) {
8580 dc->user = ((env->v7m.exception == 0) && (env->v7m.control & 1));
8581 } else {
8582 dc->user = (env->uncached_cpsr & 0x1f) == ARM_CPU_MODE_USR;
8583 }
b5ff1b31 8584#endif
4373f3ce
PB		 8585 cpu_F0s = tcg_temp_new(TCG_TYPE_I32);
8586 cpu_F1s = tcg_temp_new(TCG_TYPE_I32);
8587 cpu_F0d = tcg_temp_new(TCG_TYPE_I64);
8588 cpu_F1d = tcg_temp_new(TCG_TYPE_I64);
ad69471c
PB		 8589 cpu_V0 = cpu_F0d;
8590 cpu_V1 = cpu_F1d;
e677137d
PB		 8591 /* FIXME: cpu_M0 can probably be the same as cpu_V0. */
8592 cpu_M0 = tcg_temp_new(TCG_TYPE_I64);
b5ff1b31 8593 next_page_start = (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
2c0262af 8594 lj = -1;
9ee6e8bb
PB		 8595 /* Reset the conditional execution bits immediately. This avoids
8596 complications trying to do it at the end of the block. */
8597 if (env->condexec_bits)
8f01245e
PB		 8598 {
8599 TCGv tmp = new_tmp();
8600 tcg_gen_movi_i32(tmp, 0);
d9ba4830 8601 store_cpu_field(tmp, condexec_bits);
8f01245e 8602 }
2c0262af 8603 do {
9ee6e8bb
PB		 8604#ifndef CONFIG_USER_ONLY
8605 if (dc->pc >= 0xfffffff0 && IS_M(env)) {
8606 /* We always get here via a jump, so know we are not in a
8607 conditional execution block. */
d9ba4830 8608 gen_exception(EXCP_EXCEPTION_EXIT);
9ee6e8bb
PB		 8609 }
8610#endif
8611
1fddef4b
FB		 8612 if (env->nb_breakpoints > 0) {
8613 for(j = 0; j < env->nb_breakpoints; j++) {
8614 if (env->breakpoints[j] == dc->pc) {
9ee6e8bb 8615 gen_set_condexec(dc);
5e3f878a 8616 gen_set_pc_im(dc->pc);
d9ba4830 8617 gen_exception(EXCP_DEBUG);
1fddef4b 8618 dc->is_jmp = DISAS_JUMP;
9ee6e8bb
PB		 8619 /* Advance PC so that clearing the breakpoint will
8620 invalidate this TB. */
8621 dc->pc += 2;
8622 goto done_generating;
1fddef4b
FB		 8623 break;
8624 }
8625 }
8626 }
2c0262af
FB		 8627 if (search_pc) {
8628 j = gen_opc_ptr - gen_opc_buf;
8629 if (lj < j) {
8630 lj++;
8631 while (lj < j)
8632 gen_opc_instr_start[lj++] = 0;
8633 }
0fa85d43 8634 gen_opc_pc[lj] = dc->pc;
2c0262af
FB		 8635 gen_opc_instr_start[lj] = 1;
8636 }
e50e6a20 8637
9ee6e8bb
PB		 8638 if (env->thumb) {
8639 disas_thumb_insn(env, dc);
8640 if (dc->condexec_mask) {
8641 dc->condexec_cond = (dc->condexec_cond & 0xe)
8642 | ((dc->condexec_mask >> 4) & 1);
8643 dc->condexec_mask = (dc->condexec_mask << 1) & 0x1f;
8644 if (dc->condexec_mask == 0) {
8645 dc->condexec_cond = 0;
8646 }
8647 }
8648 } else {
8649 disas_arm_insn(env, dc);
8650 }
b26eefb6
PB		 8651 if (num_temps) {
8652 fprintf(stderr, "Internal resource leak before %08x\n", dc->pc);
8653 num_temps = 0;
8654 }
e50e6a20
FB		 8655
8656 if (dc->condjmp && !dc->is_jmp) {
8657 gen_set_label(dc->condlabel);
8658 dc->condjmp = 0;
8659 }
6658ffb8
PB		 8660 /* Terminate the TB on memory ops if watchpoints are present. */
8661 /* FIXME: This should be replacd by the deterministic execution
8662 * IRQ raising bits. */
8663 if (dc->is_mem && env->nb_watchpoints)
8664 break;
8665
e50e6a20
FB		 8666 /* Translation stops when a conditional branch is enoutered.
8667 * Otherwise the subsequent code could get translated several times.
b5ff1b31
FB		 8668 * Also stop translation when a page boundary is reached. This
8669 * ensures prefech aborts occur at the right place. */
1fddef4b
FB		 8670 } while (!dc->is_jmp && gen_opc_ptr < gen_opc_end &&
8671 !env->singlestep_enabled &&
b5ff1b31 8672 dc->pc < next_page_start);
9ee6e8bb 8673
b5ff1b31 8674 /* At this stage dc->condjmp will only be set when the skipped
9ee6e8bb
PB		 8675 instruction was a conditional branch or trap, and the PC has
8676 already been written. */
8aaca4c0
FB		 8677 if (__builtin_expect(env->singlestep_enabled, 0)) {
8678 /* Make sure the pc is updated, and raise a debug exception. */
e50e6a20 8679 if (dc->condjmp) {
9ee6e8bb
PB		 8680 gen_set_condexec(dc);
8681 if (dc->is_jmp == DISAS_SWI) {
d9ba4830 8682 gen_exception(EXCP_SWI);
9ee6e8bb 8683 } else {
d9ba4830 8684 gen_exception(EXCP_DEBUG);
9ee6e8bb 8685 }
e50e6a20
FB		 8686 gen_set_label(dc->condlabel);
8687 }
8688 if (dc->condjmp || !dc->is_jmp) {
5e3f878a 8689 gen_set_pc_im(dc->pc);
e50e6a20 8690 dc->condjmp = 0;
8aaca4c0 8691 }
9ee6e8bb
PB		 8692 gen_set_condexec(dc);
8693 if (dc->is_jmp == DISAS_SWI && !dc->condjmp) {
d9ba4830 8694 gen_exception(EXCP_SWI);
9ee6e8bb
PB		 8695 } else {
8696 /* FIXME: Single stepping a WFI insn will not halt
8697 the CPU. */
d9ba4830 8698 gen_exception(EXCP_DEBUG);
9ee6e8bb 8699 }
8aaca4c0 8700 } else {
9ee6e8bb
PB		 8701 /* While branches must always occur at the end of an IT block,
8702 there are a few other things that can cause us to terminate
8703 the TB in the middel of an IT block:
8704 - Exception generating instructions (bkpt, swi, undefined).
8705 - Page boundaries.
8706 - Hardware watchpoints.
8707 Hardware breakpoints have already been handled and skip this code.
8708 */
8709 gen_set_condexec(dc);
8aaca4c0 8710 switch(dc->is_jmp) {
8aaca4c0 8711 case DISAS_NEXT:
6e256c93 8712 gen_goto_tb(dc, 1, dc->pc);
8aaca4c0
FB		 8713 break;
8714 default:
8715 case DISAS_JUMP:
8716 case DISAS_UPDATE:
8717 /* indicate that the hash table must be used to find the next TB */
57fec1fe 8718 tcg_gen_exit_tb(0);
8aaca4c0
FB		 8719 break;
8720 case DISAS_TB_JUMP:
8721 /* nothing more to generate */
8722 break;
9ee6e8bb 8723 case DISAS_WFI:
d9ba4830 8724 gen_helper_wfi();
9ee6e8bb
PB		 8725 break;
8726 case DISAS_SWI:
d9ba4830 8727 gen_exception(EXCP_SWI);
9ee6e8bb 8728 break;
8aaca4c0 8729 }
e50e6a20
FB		 8730 if (dc->condjmp) {
8731 gen_set_label(dc->condlabel);
9ee6e8bb 8732 gen_set_condexec(dc);
6e256c93 8733 gen_goto_tb(dc, 1, dc->pc);
e50e6a20
FB		 8734 dc->condjmp = 0;
8735 }
2c0262af 8736 }
9ee6e8bb 8737done_generating:
2c0262af
FB		 8738 *gen_opc_ptr = INDEX_op_end;
8739
8740#ifdef DEBUG_DISAS
e19e89a5 8741 if (loglevel & CPU_LOG_TB_IN_ASM) {
2c0262af
FB		 8742 fprintf(logfile, "----------------\n");
8743 fprintf(logfile, "IN: %s\n", lookup_symbol(pc_start));
5899f386 8744 target_disas(logfile, pc_start, dc->pc - pc_start, env->thumb);
2c0262af
FB		 8745 fprintf(logfile, "\n");
8746 }
8747#endif
b5ff1b31
FB		 8748 if (search_pc) {
8749 j = gen_opc_ptr - gen_opc_buf;
8750 lj++;
8751 while (lj <= j)
8752 gen_opc_instr_start[lj++] = 0;
b5ff1b31 8753 } else {
2c0262af 8754 tb->size = dc->pc - pc_start;
b5ff1b31 8755 }
2c0262af
FB		 8756 return 0;
8757}
8758
8759int gen_intermediate_code(CPUState *env, TranslationBlock *tb)
8760{
8761 return gen_intermediate_code_internal(env, tb, 0);
8762}
8763
8764int gen_intermediate_code_pc(CPUState *env, TranslationBlock *tb)
8765{
8766 return gen_intermediate_code_internal(env, tb, 1);
8767}
8768
b5ff1b31
FB		 8769static const char *cpu_mode_names[16] = {
8770 "usr", "fiq", "irq", "svc", "???", "???", "???", "abt",
8771 "???", "???", "???", "und", "???", "???", "???", "sys"
8772};
9ee6e8bb 8773
5fafdf24 8774void cpu_dump_state(CPUState *env, FILE *f,
7fe48483
FB		 8775 int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
8776 int flags)
2c0262af
FB		 8777{
8778 int i;
bc380d17 8779 union {
b7bcbe95
FB		 8780 uint32_t i;
8781 float s;
8782 } s0, s1;
8783 CPU_DoubleU d;
a94a6abf
PB		 8784 /* ??? This assumes float64 and double have the same layout.
8785 Oh well, it's only debug dumps. */
8786 union {
8787 float64 f64;
8788 double d;
8789 } d0;
b5ff1b31 8790 uint32_t psr;
2c0262af
FB		 8791
8792 for(i=0;i<16;i++) {
7fe48483 8793 cpu_fprintf(f, "R%02d=%08x", i, env->regs[i]);
2c0262af 8794 if ((i % 4) == 3)
7fe48483 8795 cpu_fprintf(f, "\n");
2c0262af 8796 else
7fe48483 8797 cpu_fprintf(f, " ");
2c0262af 8798 }
b5ff1b31 8799 psr = cpsr_read(env);
687fa640
TS		 8800 cpu_fprintf(f, "PSR=%08x %c%c%c%c %c %s%d\n",
8801 psr,
b5ff1b31
FB		 8802 psr & (1 << 31) ? 'N' : '-',
8803 psr & (1 << 30) ? 'Z' : '-',
8804 psr & (1 << 29) ? 'C' : '-',
8805 psr & (1 << 28) ? 'V' : '-',
5fafdf24 8806 psr & CPSR_T ? 'T' : 'A',
b5ff1b31 8807 cpu_mode_names[psr & 0xf], (psr & 0x10) ? 32 : 26);
b7bcbe95 8808
5e3f878a 8809#if 0
b7bcbe95 8810 for (i = 0; i < 16; i++) {
8e96005d
FB		 8811 d.d = env->vfp.regs[i];
8812 s0.i = d.l.lower;
8813 s1.i = d.l.upper;
a94a6abf
PB		 8814 d0.f64 = d.d;
8815 cpu_fprintf(f, "s%02d=%08x(%8g) s%02d=%08x(%8g) d%02d=%08x%08x(%8g)\n",
b7bcbe95 8816 i * 2, (int)s0.i, s0.s,
a94a6abf 8817 i * 2 + 1, (int)s1.i, s1.s,
b7bcbe95 8818 i, (int)(uint32_t)d.l.upper, (int)(uint32_t)d.l.lower,
a94a6abf 8819 d0.d);
b7bcbe95 8820 }
40f137e1 8821 cpu_fprintf(f, "FPSCR: %08x\n", (int)env->vfp.xregs[ARM_VFP_FPSCR]);
5e3f878a 8822#endif
2c0262af 8823}
a6b025d3 8824
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