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Fix net_check_clients warnings: make it per vlan.
[mirror_qemu.git] / target-arm / translate.c
CommitLineData
2c0262af
FB		 1/*
2 * ARM translation
5fafdf24 3 *
2c0262af 4 * Copyright (c) 2003 Fabrice Bellard
9ee6e8bb 5 * Copyright (c) 2005-2007 CodeSourcery
18c9b560 6 * Copyright (c) 2007 OpenedHand, Ltd.
2c0262af
FB		 7 *
8 * This library is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU Lesser General Public
10 * License as published by the Free Software Foundation; either
11 * version 2 of the License, or (at your option) any later version.
12 *
13 * This library is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * Lesser General Public License for more details.
17 *
18 * You should have received a copy of the GNU Lesser General Public
8167ee88 19 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
2c0262af
FB		 20 */
21#include <stdarg.h>
22#include <stdlib.h>
23#include <stdio.h>
24#include <string.h>
25#include <inttypes.h>
26
27#include "cpu.h"
28#include "exec-all.h"
29#include "disas.h"
57fec1fe 30#include "tcg-op.h"
79383c9c 31#include "qemu-log.h"
1497c961 32
a7812ae4 33#include "helpers.h"
1497c961 34#define GEN_HELPER 1
b26eefb6 35#include "helpers.h"
2c0262af 36
9ee6e8bb
PB		 37#define ENABLE_ARCH_5J 0
38#define ENABLE_ARCH_6 arm_feature(env, ARM_FEATURE_V6)
39#define ENABLE_ARCH_6K arm_feature(env, ARM_FEATURE_V6K)
40#define ENABLE_ARCH_6T2 arm_feature(env, ARM_FEATURE_THUMB2)
41#define ENABLE_ARCH_7 arm_feature(env, ARM_FEATURE_V7)
b5ff1b31 42
86753403 43#define ARCH(x) do { if (!ENABLE_ARCH_##x) goto illegal_op; } while(0)
b5ff1b31 44
2c0262af
FB		 45/* internal defines */
46typedef struct DisasContext {
0fa85d43 47 target_ulong pc;
2c0262af 48 int is_jmp;
e50e6a20
FB		 49 /* Nonzero if this instruction has been conditionally skipped. */
50 int condjmp;
51 /* The label that will be jumped to when the instruction is skipped. */
52 int condlabel;
9ee6e8bb
PB		 53 /* Thumb-2 condtional execution bits. */
54 int condexec_mask;
55 int condexec_cond;
2c0262af 56 struct TranslationBlock *tb;
8aaca4c0 57 int singlestep_enabled;
5899f386 58 int thumb;
b5ff1b31
FB		 59#if !defined(CONFIG_USER_ONLY)
60 int user;
61#endif
5df8bac1 62 int vfp_enabled;
69d1fc22
PM		 63 int vec_len;
64 int vec_stride;
2c0262af
FB		 65} DisasContext;
66
e12ce78d
PM		 67static uint32_t gen_opc_condexec_bits[OPC_BUF_SIZE];
68
b5ff1b31
FB		 69#if defined(CONFIG_USER_ONLY)
70#define IS_USER(s) 1
71#else
72#define IS_USER(s) (s->user)
73#endif
74
9ee6e8bb
PB		 75/* These instructions trap after executing, so defer them until after the
76 conditional executions state has been updated. */
77#define DISAS_WFI 4
78#define DISAS_SWI 5
2c0262af 79
a7812ae4 80static TCGv_ptr cpu_env;
ad69471c 81/* We reuse the same 64-bit temporaries for efficiency. */
a7812ae4 82static TCGv_i64 cpu_V0, cpu_V1, cpu_M0;
155c3eac 83static TCGv_i32 cpu_R[16];
426f5abc
PB		 84static TCGv_i32 cpu_exclusive_addr;
85static TCGv_i32 cpu_exclusive_val;
86static TCGv_i32 cpu_exclusive_high;
87#ifdef CONFIG_USER_ONLY
88static TCGv_i32 cpu_exclusive_test;
89static TCGv_i32 cpu_exclusive_info;
90#endif
ad69471c 91
b26eefb6 92/* FIXME: These should be removed. */
a7812ae4
PB		 93static TCGv cpu_F0s, cpu_F1s;
94static TCGv_i64 cpu_F0d, cpu_F1d;
b26eefb6 95
2e70f6ef
PB		 96#include "gen-icount.h"
97
155c3eac
FN		 98static const char *regnames[] =
99 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
100 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "pc" };
101
b26eefb6
PB		 102/* initialize TCG globals. */
103void arm_translate_init(void)
104{
155c3eac
FN		 105 int i;
106
a7812ae4
PB		 107 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
108
155c3eac
FN		 109 for (i = 0; i < 16; i++) {
110 cpu_R[i] = tcg_global_mem_new_i32(TCG_AREG0,
111 offsetof(CPUState, regs[i]),
112 regnames[i]);
113 }
426f5abc
PB		 114 cpu_exclusive_addr = tcg_global_mem_new_i32(TCG_AREG0,
115 offsetof(CPUState, exclusive_addr), "exclusive_addr");
116 cpu_exclusive_val = tcg_global_mem_new_i32(TCG_AREG0,
117 offsetof(CPUState, exclusive_val), "exclusive_val");
118 cpu_exclusive_high = tcg_global_mem_new_i32(TCG_AREG0,
119 offsetof(CPUState, exclusive_high), "exclusive_high");
120#ifdef CONFIG_USER_ONLY
121 cpu_exclusive_test = tcg_global_mem_new_i32(TCG_AREG0,
122 offsetof(CPUState, exclusive_test), "exclusive_test");
123 cpu_exclusive_info = tcg_global_mem_new_i32(TCG_AREG0,
124 offsetof(CPUState, exclusive_info), "exclusive_info");
125#endif
155c3eac 126
a7812ae4
PB		 127#define GEN_HELPER 2
128#include "helpers.h"
b26eefb6
PB		 129}
130
d9ba4830
PB		 131static inline TCGv load_cpu_offset(int offset)
132{
7d1b0095 133 TCGv tmp = tcg_temp_new_i32();
d9ba4830
PB		 134 tcg_gen_ld_i32(tmp, cpu_env, offset);
135 return tmp;
136}
137
138#define load_cpu_field(name) load_cpu_offset(offsetof(CPUState, name))
139
140static inline void store_cpu_offset(TCGv var, int offset)
141{
142 tcg_gen_st_i32(var, cpu_env, offset);
7d1b0095 143 tcg_temp_free_i32(var);
d9ba4830
PB		 144}
145
146#define store_cpu_field(var, name) \
147 store_cpu_offset(var, offsetof(CPUState, name))
148
b26eefb6
PB		 149/* Set a variable to the value of a CPU register. */
150static void load_reg_var(DisasContext *s, TCGv var, int reg)
151{
152 if (reg == 15) {
153 uint32_t addr;
154 /* normaly, since we updated PC, we need only to add one insn */
155 if (s->thumb)
156 addr = (long)s->pc + 2;
157 else
158 addr = (long)s->pc + 4;
159 tcg_gen_movi_i32(var, addr);
160 } else {
155c3eac 161 tcg_gen_mov_i32(var, cpu_R[reg]);
b26eefb6
PB		 162 }
163}
164
165/* Create a new temporary and set it to the value of a CPU register. */
166static inline TCGv load_reg(DisasContext *s, int reg)
167{
7d1b0095 168 TCGv tmp = tcg_temp_new_i32();
b26eefb6
PB		 169 load_reg_var(s, tmp, reg);
170 return tmp;
171}
172
173/* Set a CPU register. The source must be a temporary and will be
174 marked as dead. */
175static void store_reg(DisasContext *s, int reg, TCGv var)
176{
177 if (reg == 15) {
178 tcg_gen_andi_i32(var, var, ~1);
179 s->is_jmp = DISAS_JUMP;
180 }
155c3eac 181 tcg_gen_mov_i32(cpu_R[reg], var);
7d1b0095 182 tcg_temp_free_i32(var);
b26eefb6
PB		 183}
184
b26eefb6 185/* Value extensions. */
86831435
PB		 186#define gen_uxtb(var) tcg_gen_ext8u_i32(var, var)
187#define gen_uxth(var) tcg_gen_ext16u_i32(var, var)
b26eefb6
PB		 188#define gen_sxtb(var) tcg_gen_ext8s_i32(var, var)
189#define gen_sxth(var) tcg_gen_ext16s_i32(var, var)
190
1497c961
PB		 191#define gen_sxtb16(var) gen_helper_sxtb16(var, var)
192#define gen_uxtb16(var) gen_helper_uxtb16(var, var)
8f01245e 193
b26eefb6 194
b75263d6
JR		 195static inline void gen_set_cpsr(TCGv var, uint32_t mask)
196{
197 TCGv tmp_mask = tcg_const_i32(mask);
198 gen_helper_cpsr_write(var, tmp_mask);
199 tcg_temp_free_i32(tmp_mask);
200}
d9ba4830
PB		 201/* Set NZCV flags from the high 4 bits of var. */
202#define gen_set_nzcv(var) gen_set_cpsr(var, CPSR_NZCV)
203
204static void gen_exception(int excp)
205{
7d1b0095 206 TCGv tmp = tcg_temp_new_i32();
d9ba4830
PB		 207 tcg_gen_movi_i32(tmp, excp);
208 gen_helper_exception(tmp);
7d1b0095 209 tcg_temp_free_i32(tmp);
d9ba4830
PB		 210}
211
3670669c
PB		 212static void gen_smul_dual(TCGv a, TCGv b)
213{
7d1b0095
PM		 214 TCGv tmp1 = tcg_temp_new_i32();
215 TCGv tmp2 = tcg_temp_new_i32();
22478e79
AZ		 216 tcg_gen_ext16s_i32(tmp1, a);
217 tcg_gen_ext16s_i32(tmp2, b);
3670669c 218 tcg_gen_mul_i32(tmp1, tmp1, tmp2);
7d1b0095 219 tcg_temp_free_i32(tmp2);
3670669c
PB		 220 tcg_gen_sari_i32(a, a, 16);
221 tcg_gen_sari_i32(b, b, 16);
222 tcg_gen_mul_i32(b, b, a);
223 tcg_gen_mov_i32(a, tmp1);
7d1b0095 224 tcg_temp_free_i32(tmp1);
3670669c
PB		 225}
226
227/* Byteswap each halfword. */
228static void gen_rev16(TCGv var)
229{
7d1b0095 230 TCGv tmp = tcg_temp_new_i32();
3670669c
PB		 231 tcg_gen_shri_i32(tmp, var, 8);
232 tcg_gen_andi_i32(tmp, tmp, 0x00ff00ff);
233 tcg_gen_shli_i32(var, var, 8);
234 tcg_gen_andi_i32(var, var, 0xff00ff00);
235 tcg_gen_or_i32(var, var, tmp);
7d1b0095 236 tcg_temp_free_i32(tmp);
3670669c
PB		 237}
238
239/* Byteswap low halfword and sign extend. */
240static void gen_revsh(TCGv var)
241{
1a855029
AJ		 242 tcg_gen_ext16u_i32(var, var);
243 tcg_gen_bswap16_i32(var, var);
244 tcg_gen_ext16s_i32(var, var);
3670669c
PB		 245}
246
247/* Unsigned bitfield extract. */
248static void gen_ubfx(TCGv var, int shift, uint32_t mask)
249{
250 if (shift)
251 tcg_gen_shri_i32(var, var, shift);
252 tcg_gen_andi_i32(var, var, mask);
253}
254
255/* Signed bitfield extract. */
256static void gen_sbfx(TCGv var, int shift, int width)
257{
258 uint32_t signbit;
259
260 if (shift)
261 tcg_gen_sari_i32(var, var, shift);
262 if (shift + width < 32) {
263 signbit = 1u << (width - 1);
264 tcg_gen_andi_i32(var, var, (1u << width) - 1);
265 tcg_gen_xori_i32(var, var, signbit);
266 tcg_gen_subi_i32(var, var, signbit);
267 }
268}
269
270/* Bitfield insertion. Insert val into base. Clobbers base and val. */
271static void gen_bfi(TCGv dest, TCGv base, TCGv val, int shift, uint32_t mask)
272{
3670669c 273 tcg_gen_andi_i32(val, val, mask);
8f8e3aa4
PB		 274 tcg_gen_shli_i32(val, val, shift);
275 tcg_gen_andi_i32(base, base, ~(mask << shift));
3670669c
PB		 276 tcg_gen_or_i32(dest, base, val);
277}
278
838fa72d
AJ		 279/* Return (b << 32) + a. Mark inputs as dead */
280static TCGv_i64 gen_addq_msw(TCGv_i64 a, TCGv b)
3670669c 281{
838fa72d
AJ		 282 TCGv_i64 tmp64 = tcg_temp_new_i64();
283
284 tcg_gen_extu_i32_i64(tmp64, b);
7d1b0095 285 tcg_temp_free_i32(b);
838fa72d
AJ		 286 tcg_gen_shli_i64(tmp64, tmp64, 32);
287 tcg_gen_add_i64(a, tmp64, a);
288
289 tcg_temp_free_i64(tmp64);
290 return a;
291}
292
293/* Return (b << 32) - a. Mark inputs as dead. */
294static TCGv_i64 gen_subq_msw(TCGv_i64 a, TCGv b)
295{
296 TCGv_i64 tmp64 = tcg_temp_new_i64();
297
298 tcg_gen_extu_i32_i64(tmp64, b);
7d1b0095 299 tcg_temp_free_i32(b);
838fa72d
AJ		 300 tcg_gen_shli_i64(tmp64, tmp64, 32);
301 tcg_gen_sub_i64(a, tmp64, a);
302
303 tcg_temp_free_i64(tmp64);
304 return a;
3670669c
PB		 305}
306
8f01245e
PB		 307/* FIXME: Most targets have native widening multiplication.
308 It would be good to use that instead of a full wide multiply. */
5e3f878a 309/* 32x32->64 multiply. Marks inputs as dead. */
a7812ae4 310static TCGv_i64 gen_mulu_i64_i32(TCGv a, TCGv b)
5e3f878a 311{
a7812ae4
PB		 312 TCGv_i64 tmp1 = tcg_temp_new_i64();
313 TCGv_i64 tmp2 = tcg_temp_new_i64();
5e3f878a
PB		 314
315 tcg_gen_extu_i32_i64(tmp1, a);
7d1b0095 316 tcg_temp_free_i32(a);
5e3f878a 317 tcg_gen_extu_i32_i64(tmp2, b);
7d1b0095 318 tcg_temp_free_i32(b);
5e3f878a 319 tcg_gen_mul_i64(tmp1, tmp1, tmp2);
b75263d6 320 tcg_temp_free_i64(tmp2);
5e3f878a
PB		 321 return tmp1;
322}
323
a7812ae4 324static TCGv_i64 gen_muls_i64_i32(TCGv a, TCGv b)
5e3f878a 325{
a7812ae4
PB		 326 TCGv_i64 tmp1 = tcg_temp_new_i64();
327 TCGv_i64 tmp2 = tcg_temp_new_i64();
5e3f878a
PB		 328
329 tcg_gen_ext_i32_i64(tmp1, a);
7d1b0095 330 tcg_temp_free_i32(a);
5e3f878a 331 tcg_gen_ext_i32_i64(tmp2, b);
7d1b0095 332 tcg_temp_free_i32(b);
5e3f878a 333 tcg_gen_mul_i64(tmp1, tmp1, tmp2);
b75263d6 334 tcg_temp_free_i64(tmp2);
5e3f878a
PB		 335 return tmp1;
336}
337
8f01245e
PB		 338/* Swap low and high halfwords. */
339static void gen_swap_half(TCGv var)
340{
7d1b0095 341 TCGv tmp = tcg_temp_new_i32();
8f01245e
PB		 342 tcg_gen_shri_i32(tmp, var, 16);
343 tcg_gen_shli_i32(var, var, 16);
344 tcg_gen_or_i32(var, var, tmp);
7d1b0095 345 tcg_temp_free_i32(tmp);
8f01245e
PB		 346}
347
b26eefb6
PB		 348/* Dual 16-bit add. Result placed in t0 and t1 is marked as dead.
349 tmp = (t0 ^ t1) & 0x8000;
350 t0 &= ~0x8000;
351 t1 &= ~0x8000;
352 t0 = (t0 + t1) ^ tmp;
353 */
354
355static void gen_add16(TCGv t0, TCGv t1)
356{
7d1b0095 357 TCGv tmp = tcg_temp_new_i32();
b26eefb6
PB		 358 tcg_gen_xor_i32(tmp, t0, t1);
359 tcg_gen_andi_i32(tmp, tmp, 0x8000);
360 tcg_gen_andi_i32(t0, t0, ~0x8000);
361 tcg_gen_andi_i32(t1, t1, ~0x8000);
362 tcg_gen_add_i32(t0, t0, t1);
363 tcg_gen_xor_i32(t0, t0, tmp);
7d1b0095
PM		 364 tcg_temp_free_i32(tmp);
365 tcg_temp_free_i32(t1);
b26eefb6
PB		 366}
367
9a119ff6
PB		 368#define gen_set_CF(var) tcg_gen_st_i32(var, cpu_env, offsetof(CPUState, CF))
369
b26eefb6
PB		 370/* Set CF to the top bit of var. */
371static void gen_set_CF_bit31(TCGv var)
372{
7d1b0095 373 TCGv tmp = tcg_temp_new_i32();
b26eefb6 374 tcg_gen_shri_i32(tmp, var, 31);
4cc633c3 375 gen_set_CF(tmp);
7d1b0095 376 tcg_temp_free_i32(tmp);
b26eefb6
PB		 377}
378
379/* Set N and Z flags from var. */
380static inline void gen_logic_CC(TCGv var)
381{
6fbe23d5
PB		 382 tcg_gen_st_i32(var, cpu_env, offsetof(CPUState, NF));
383 tcg_gen_st_i32(var, cpu_env, offsetof(CPUState, ZF));
b26eefb6
PB		 384}
385
386/* T0 += T1 + CF. */
396e467c 387static void gen_adc(TCGv t0, TCGv t1)
b26eefb6 388{
d9ba4830 389 TCGv tmp;
396e467c 390 tcg_gen_add_i32(t0, t0, t1);
d9ba4830 391 tmp = load_cpu_field(CF);
396e467c 392 tcg_gen_add_i32(t0, t0, tmp);
7d1b0095 393 tcg_temp_free_i32(tmp);
b26eefb6
PB		 394}
395
e9bb4aa9
JR		 396/* dest = T0 + T1 + CF. */
397static void gen_add_carry(TCGv dest, TCGv t0, TCGv t1)
398{
399 TCGv tmp;
400 tcg_gen_add_i32(dest, t0, t1);
401 tmp = load_cpu_field(CF);
402 tcg_gen_add_i32(dest, dest, tmp);
7d1b0095 403 tcg_temp_free_i32(tmp);
e9bb4aa9
JR		 404}
405
3670669c
PB		 406/* dest = T0 - T1 + CF - 1. */
407static void gen_sub_carry(TCGv dest, TCGv t0, TCGv t1)
408{
d9ba4830 409 TCGv tmp;
3670669c 410 tcg_gen_sub_i32(dest, t0, t1);
d9ba4830 411 tmp = load_cpu_field(CF);
3670669c
PB		 412 tcg_gen_add_i32(dest, dest, tmp);
413 tcg_gen_subi_i32(dest, dest, 1);
7d1b0095 414 tcg_temp_free_i32(tmp);
3670669c
PB		 415}
416
ad69471c
PB		 417/* FIXME: Implement this natively. */
418#define tcg_gen_abs_i32(t0, t1) gen_helper_abs(t0, t1)
419
9a119ff6 420static void shifter_out_im(TCGv var, int shift)
b26eefb6 421{
7d1b0095 422 TCGv tmp = tcg_temp_new_i32();
9a119ff6
PB		 423 if (shift == 0) {
424 tcg_gen_andi_i32(tmp, var, 1);
b26eefb6 425 } else {
9a119ff6 426 tcg_gen_shri_i32(tmp, var, shift);
4cc633c3 427 if (shift != 31)
9a119ff6
PB		 428 tcg_gen_andi_i32(tmp, tmp, 1);
429 }
430 gen_set_CF(tmp);
7d1b0095 431 tcg_temp_free_i32(tmp);
9a119ff6 432}
b26eefb6 433
9a119ff6
PB		 434/* Shift by immediate. Includes special handling for shift == 0. */
435static inline void gen_arm_shift_im(TCGv var, int shiftop, int shift, int flags)
436{
437 switch (shiftop) {
438 case 0: /* LSL */
439 if (shift != 0) {
440 if (flags)
441 shifter_out_im(var, 32 - shift);
442 tcg_gen_shli_i32(var, var, shift);
443 }
444 break;
445 case 1: /* LSR */
446 if (shift == 0) {
447 if (flags) {
448 tcg_gen_shri_i32(var, var, 31);
449 gen_set_CF(var);
450 }
451 tcg_gen_movi_i32(var, 0);
452 } else {
453 if (flags)
454 shifter_out_im(var, shift - 1);
455 tcg_gen_shri_i32(var, var, shift);
456 }
457 break;
458 case 2: /* ASR */
459 if (shift == 0)
460 shift = 32;
461 if (flags)
462 shifter_out_im(var, shift - 1);
463 if (shift == 32)
464 shift = 31;
465 tcg_gen_sari_i32(var, var, shift);
466 break;
467 case 3: /* ROR/RRX */
468 if (shift != 0) {
469 if (flags)
470 shifter_out_im(var, shift - 1);
f669df27 471 tcg_gen_rotri_i32(var, var, shift); break;
9a119ff6 472 } else {
d9ba4830 473 TCGv tmp = load_cpu_field(CF);
9a119ff6
PB		 474 if (flags)
475 shifter_out_im(var, 0);
476 tcg_gen_shri_i32(var, var, 1);
b26eefb6
PB		 477 tcg_gen_shli_i32(tmp, tmp, 31);
478 tcg_gen_or_i32(var, var, tmp);
7d1b0095 479 tcg_temp_free_i32(tmp);
b26eefb6
PB		 480 }
481 }
482};
483
8984bd2e
PB		 484static inline void gen_arm_shift_reg(TCGv var, int shiftop,
485 TCGv shift, int flags)
486{
487 if (flags) {
488 switch (shiftop) {
489 case 0: gen_helper_shl_cc(var, var, shift); break;
490 case 1: gen_helper_shr_cc(var, var, shift); break;
491 case 2: gen_helper_sar_cc(var, var, shift); break;
492 case 3: gen_helper_ror_cc(var, var, shift); break;
493 }
494 } else {
495 switch (shiftop) {
496 case 0: gen_helper_shl(var, var, shift); break;
497 case 1: gen_helper_shr(var, var, shift); break;
498 case 2: gen_helper_sar(var, var, shift); break;
f669df27
AJ		 499 case 3: tcg_gen_andi_i32(shift, shift, 0x1f);
500 tcg_gen_rotr_i32(var, var, shift); break;
8984bd2e
PB		 501 }
502 }
7d1b0095 503 tcg_temp_free_i32(shift);
8984bd2e
PB		 504}
505
6ddbc6e4
PB		 506#define PAS_OP(pfx) \
507 switch (op2) { \
508 case 0: gen_pas_helper(glue(pfx,add16)); break; \
509 case 1: gen_pas_helper(glue(pfx,addsubx)); break; \
510 case 2: gen_pas_helper(glue(pfx,subaddx)); break; \
511 case 3: gen_pas_helper(glue(pfx,sub16)); break; \
512 case 4: gen_pas_helper(glue(pfx,add8)); break; \
513 case 7: gen_pas_helper(glue(pfx,sub8)); break; \
514 }
d9ba4830 515static void gen_arm_parallel_addsub(int op1, int op2, TCGv a, TCGv b)
6ddbc6e4 516{
a7812ae4 517 TCGv_ptr tmp;
6ddbc6e4
PB		 518
519 switch (op1) {
520#define gen_pas_helper(name) glue(gen_helper_,name)(a, a, b, tmp)
521 case 1:
a7812ae4 522 tmp = tcg_temp_new_ptr();
6ddbc6e4
PB		 523 tcg_gen_addi_ptr(tmp, cpu_env, offsetof(CPUState, GE));
524 PAS_OP(s)
b75263d6 525 tcg_temp_free_ptr(tmp);
6ddbc6e4
PB		 526 break;
527 case 5:
a7812ae4 528 tmp = tcg_temp_new_ptr();
6ddbc6e4
PB		 529 tcg_gen_addi_ptr(tmp, cpu_env, offsetof(CPUState, GE));
530 PAS_OP(u)
b75263d6 531 tcg_temp_free_ptr(tmp);
6ddbc6e4
PB		 532 break;
533#undef gen_pas_helper
534#define gen_pas_helper(name) glue(gen_helper_,name)(a, a, b)
535 case 2:
536 PAS_OP(q);
537 break;
538 case 3:
539 PAS_OP(sh);
540 break;
541 case 6:
542 PAS_OP(uq);
543 break;
544 case 7:
545 PAS_OP(uh);
546 break;
547#undef gen_pas_helper
548 }
549}
9ee6e8bb
PB		 550#undef PAS_OP
551
6ddbc6e4
PB		 552/* For unknown reasons Arm and Thumb-2 use arbitrarily different encodings. */
553#define PAS_OP(pfx) \
ed89a2f1 554 switch (op1) { \
6ddbc6e4
PB		 555 case 0: gen_pas_helper(glue(pfx,add8)); break; \
556 case 1: gen_pas_helper(glue(pfx,add16)); break; \
557 case 2: gen_pas_helper(glue(pfx,addsubx)); break; \
558 case 4: gen_pas_helper(glue(pfx,sub8)); break; \
559 case 5: gen_pas_helper(glue(pfx,sub16)); break; \
560 case 6: gen_pas_helper(glue(pfx,subaddx)); break; \
561 }
d9ba4830 562static void gen_thumb2_parallel_addsub(int op1, int op2, TCGv a, TCGv b)
6ddbc6e4 563{
a7812ae4 564 TCGv_ptr tmp;
6ddbc6e4 565
ed89a2f1 566 switch (op2) {
6ddbc6e4
PB		 567#define gen_pas_helper(name) glue(gen_helper_,name)(a, a, b, tmp)
568 case 0:
a7812ae4 569 tmp = tcg_temp_new_ptr();
6ddbc6e4
PB		 570 tcg_gen_addi_ptr(tmp, cpu_env, offsetof(CPUState, GE));
571 PAS_OP(s)
b75263d6 572 tcg_temp_free_ptr(tmp);
6ddbc6e4
PB		 573 break;
574 case 4:
a7812ae4 575 tmp = tcg_temp_new_ptr();
6ddbc6e4
PB		 576 tcg_gen_addi_ptr(tmp, cpu_env, offsetof(CPUState, GE));
577 PAS_OP(u)
b75263d6 578 tcg_temp_free_ptr(tmp);
6ddbc6e4
PB		 579 break;
580#undef gen_pas_helper
581#define gen_pas_helper(name) glue(gen_helper_,name)(a, a, b)
582 case 1:
583 PAS_OP(q);
584 break;
585 case 2:
586 PAS_OP(sh);
587 break;
588 case 5:
589 PAS_OP(uq);
590 break;
591 case 6:
592 PAS_OP(uh);
593 break;
594#undef gen_pas_helper
595 }
596}
9ee6e8bb
PB		 597#undef PAS_OP
598
d9ba4830
PB		 599static void gen_test_cc(int cc, int label)
600{
601 TCGv tmp;
602 TCGv tmp2;
d9ba4830
PB		 603 int inv;
604
d9ba4830
PB		 605 switch (cc) {
606 case 0: /* eq: Z */
6fbe23d5 607 tmp = load_cpu_field(ZF);
cb63669a 608 tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, label);
d9ba4830
PB		 609 break;
610 case 1: /* ne: !Z */
6fbe23d5 611 tmp = load_cpu_field(ZF);
cb63669a 612 tcg_gen_brcondi_i32(TCG_COND_NE, tmp, 0, label);
d9ba4830
PB		 613 break;
614 case 2: /* cs: C */
615 tmp = load_cpu_field(CF);
cb63669a 616 tcg_gen_brcondi_i32(TCG_COND_NE, tmp, 0, label);
d9ba4830
PB		 617 break;
618 case 3: /* cc: !C */
619 tmp = load_cpu_field(CF);
cb63669a 620 tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, label);
d9ba4830
PB		 621 break;
622 case 4: /* mi: N */
6fbe23d5 623 tmp = load_cpu_field(NF);
cb63669a 624 tcg_gen_brcondi_i32(TCG_COND_LT, tmp, 0, label);
d9ba4830
PB		 625 break;
626 case 5: /* pl: !N */
6fbe23d5 627 tmp = load_cpu_field(NF);
cb63669a 628 tcg_gen_brcondi_i32(TCG_COND_GE, tmp, 0, label);
d9ba4830
PB		 629 break;
630 case 6: /* vs: V */
631 tmp = load_cpu_field(VF);
cb63669a 632 tcg_gen_brcondi_i32(TCG_COND_LT, tmp, 0, label);
d9ba4830
PB		 633 break;
634 case 7: /* vc: !V */
635 tmp = load_cpu_field(VF);
cb63669a 636 tcg_gen_brcondi_i32(TCG_COND_GE, tmp, 0, label);
d9ba4830
PB		 637 break;
638 case 8: /* hi: C && !Z */
639 inv = gen_new_label();
640 tmp = load_cpu_field(CF);
cb63669a 641 tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, inv);
7d1b0095 642 tcg_temp_free_i32(tmp);
6fbe23d5 643 tmp = load_cpu_field(ZF);
cb63669a 644 tcg_gen_brcondi_i32(TCG_COND_NE, tmp, 0, label);
d9ba4830
PB		 645 gen_set_label(inv);
646 break;
647 case 9: /* ls: !C || Z */
648 tmp = load_cpu_field(CF);
cb63669a 649 tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, label);
7d1b0095 650 tcg_temp_free_i32(tmp);
6fbe23d5 651 tmp = load_cpu_field(ZF);
cb63669a 652 tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, label);
d9ba4830
PB		 653 break;
654 case 10: /* ge: N == V -> N ^ V == 0 */
655 tmp = load_cpu_field(VF);
6fbe23d5 656 tmp2 = load_cpu_field(NF);
d9ba4830 657 tcg_gen_xor_i32(tmp, tmp, tmp2);
7d1b0095 658 tcg_temp_free_i32(tmp2);
cb63669a 659 tcg_gen_brcondi_i32(TCG_COND_GE, tmp, 0, label);
d9ba4830
PB		 660 break;
661 case 11: /* lt: N != V -> N ^ V != 0 */
662 tmp = load_cpu_field(VF);
6fbe23d5 663 tmp2 = load_cpu_field(NF);
d9ba4830 664 tcg_gen_xor_i32(tmp, tmp, tmp2);
7d1b0095 665 tcg_temp_free_i32(tmp2);
cb63669a 666 tcg_gen_brcondi_i32(TCG_COND_LT, tmp, 0, label);
d9ba4830
PB		 667 break;
668 case 12: /* gt: !Z && N == V */
669 inv = gen_new_label();
6fbe23d5 670 tmp = load_cpu_field(ZF);
cb63669a 671 tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, inv);
7d1b0095 672 tcg_temp_free_i32(tmp);
d9ba4830 673 tmp = load_cpu_field(VF);
6fbe23d5 674 tmp2 = load_cpu_field(NF);
d9ba4830 675 tcg_gen_xor_i32(tmp, tmp, tmp2);
7d1b0095 676 tcg_temp_free_i32(tmp2);
cb63669a 677 tcg_gen_brcondi_i32(TCG_COND_GE, tmp, 0, label);
d9ba4830
PB		 678 gen_set_label(inv);
679 break;
680 case 13: /* le: Z || N != V */
6fbe23d5 681 tmp = load_cpu_field(ZF);
cb63669a 682 tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, label);
7d1b0095 683 tcg_temp_free_i32(tmp);
d9ba4830 684 tmp = load_cpu_field(VF);
6fbe23d5 685 tmp2 = load_cpu_field(NF);
d9ba4830 686 tcg_gen_xor_i32(tmp, tmp, tmp2);
7d1b0095 687 tcg_temp_free_i32(tmp2);
cb63669a 688 tcg_gen_brcondi_i32(TCG_COND_LT, tmp, 0, label);
d9ba4830
PB		 689 break;
690 default:
691 fprintf(stderr, "Bad condition code 0x%x\n", cc);
692 abort();
693 }
7d1b0095 694 tcg_temp_free_i32(tmp);
d9ba4830 695}
2c0262af 696
b1d8e52e 697static const uint8_t table_logic_cc[16] = {
2c0262af
FB		 698 1, /* and */
699 1, /* xor */
700 0, /* sub */
701 0, /* rsb */
702 0, /* add */
703 0, /* adc */
704 0, /* sbc */
705 0, /* rsc */
706 1, /* andl */
707 1, /* xorl */
708 0, /* cmp */
709 0, /* cmn */
710 1, /* orr */
711 1, /* mov */
712 1, /* bic */
713 1, /* mvn */
714};
3b46e624 715
d9ba4830
PB		 716/* Set PC and Thumb state from an immediate address. */
717static inline void gen_bx_im(DisasContext *s, uint32_t addr)
99c475ab 718{
b26eefb6 719 TCGv tmp;
99c475ab 720
b26eefb6 721 s->is_jmp = DISAS_UPDATE;
d9ba4830 722 if (s->thumb != (addr & 1)) {
7d1b0095 723 tmp = tcg_temp_new_i32();
d9ba4830
PB		 724 tcg_gen_movi_i32(tmp, addr & 1);
725 tcg_gen_st_i32(tmp, cpu_env, offsetof(CPUState, thumb));
7d1b0095 726 tcg_temp_free_i32(tmp);
d9ba4830 727 }
155c3eac 728 tcg_gen_movi_i32(cpu_R[15], addr & ~1);
d9ba4830
PB		 729}
730
731/* Set PC and Thumb state from var. var is marked as dead. */
732static inline void gen_bx(DisasContext *s, TCGv var)
733{
d9ba4830 734 s->is_jmp = DISAS_UPDATE;
155c3eac
FN		 735 tcg_gen_andi_i32(cpu_R[15], var, ~1);
736 tcg_gen_andi_i32(var, var, 1);
737 store_cpu_field(var, thumb);
d9ba4830
PB		 738}
739
21aeb343
JR		 740/* Variant of store_reg which uses branch&exchange logic when storing
741 to r15 in ARM architecture v7 and above. The source must be a temporary
742 and will be marked as dead. */
743static inline void store_reg_bx(CPUState *env, DisasContext *s,
744 int reg, TCGv var)
745{
746 if (reg == 15 && ENABLE_ARCH_7) {
747 gen_bx(s, var);
748 } else {
749 store_reg(s, reg, var);
750 }
751}
752
b0109805
PB		 753static inline TCGv gen_ld8s(TCGv addr, int index)
754{
7d1b0095 755 TCGv tmp = tcg_temp_new_i32();
b0109805
PB		 756 tcg_gen_qemu_ld8s(tmp, addr, index);
757 return tmp;
758}
759static inline TCGv gen_ld8u(TCGv addr, int index)
760{
7d1b0095 761 TCGv tmp = tcg_temp_new_i32();
b0109805
PB		 762 tcg_gen_qemu_ld8u(tmp, addr, index);
763 return tmp;
764}
765static inline TCGv gen_ld16s(TCGv addr, int index)
766{
7d1b0095 767 TCGv tmp = tcg_temp_new_i32();
b0109805
PB		 768 tcg_gen_qemu_ld16s(tmp, addr, index);
769 return tmp;
770}
771static inline TCGv gen_ld16u(TCGv addr, int index)
772{
7d1b0095 773 TCGv tmp = tcg_temp_new_i32();
b0109805
PB		 774 tcg_gen_qemu_ld16u(tmp, addr, index);
775 return tmp;
776}
777static inline TCGv gen_ld32(TCGv addr, int index)
778{
7d1b0095 779 TCGv tmp = tcg_temp_new_i32();
b0109805
PB		 780 tcg_gen_qemu_ld32u(tmp, addr, index);
781 return tmp;
782}
84496233
JR		 783static inline TCGv_i64 gen_ld64(TCGv addr, int index)
784{
785 TCGv_i64 tmp = tcg_temp_new_i64();
786 tcg_gen_qemu_ld64(tmp, addr, index);
787 return tmp;
788}
b0109805
PB		 789static inline void gen_st8(TCGv val, TCGv addr, int index)
790{
791 tcg_gen_qemu_st8(val, addr, index);
7d1b0095 792 tcg_temp_free_i32(val);
b0109805
PB		 793}
794static inline void gen_st16(TCGv val, TCGv addr, int index)
795{
796 tcg_gen_qemu_st16(val, addr, index);
7d1b0095 797 tcg_temp_free_i32(val);
b0109805
PB		 798}
799static inline void gen_st32(TCGv val, TCGv addr, int index)
800{
801 tcg_gen_qemu_st32(val, addr, index);
7d1b0095 802 tcg_temp_free_i32(val);
b0109805 803}
84496233
JR		 804static inline void gen_st64(TCGv_i64 val, TCGv addr, int index)
805{
806 tcg_gen_qemu_st64(val, addr, index);
807 tcg_temp_free_i64(val);
808}
b5ff1b31 809
5e3f878a
PB		 810static inline void gen_set_pc_im(uint32_t val)
811{
155c3eac 812 tcg_gen_movi_i32(cpu_R[15], val);
5e3f878a
PB		 813}
814
b5ff1b31
FB		 815/* Force a TB lookup after an instruction that changes the CPU state. */
816static inline void gen_lookup_tb(DisasContext *s)
817{
a6445c52 818 tcg_gen_movi_i32(cpu_R[15], s->pc & ~1);
b5ff1b31
FB		 819 s->is_jmp = DISAS_UPDATE;
820}
821
b0109805
PB		 822static inline void gen_add_data_offset(DisasContext *s, unsigned int insn,
823 TCGv var)
2c0262af 824{
1e8d4eec 825 int val, rm, shift, shiftop;
b26eefb6 826 TCGv offset;
2c0262af
FB		 827
828 if (!(insn & (1 << 25))) {
829 /* immediate */
830 val = insn & 0xfff;
831 if (!(insn & (1 << 23)))
832 val = -val;
537730b9 833 if (val != 0)
b0109805 834 tcg_gen_addi_i32(var, var, val);
2c0262af
FB		 835 } else {
836 /* shift/register */
837 rm = (insn) & 0xf;
838 shift = (insn >> 7) & 0x1f;
1e8d4eec 839 shiftop = (insn >> 5) & 3;
b26eefb6 840 offset = load_reg(s, rm);
9a119ff6 841 gen_arm_shift_im(offset, shiftop, shift, 0);
2c0262af 842 if (!(insn & (1 << 23)))
b0109805 843 tcg_gen_sub_i32(var, var, offset);
2c0262af 844 else
b0109805 845 tcg_gen_add_i32(var, var, offset);
7d1b0095 846 tcg_temp_free_i32(offset);
2c0262af
FB		 847 }
848}
849
191f9a93 850static inline void gen_add_datah_offset(DisasContext *s, unsigned int insn,
b0109805 851 int extra, TCGv var)
2c0262af
FB		 852{
853 int val, rm;
b26eefb6 854 TCGv offset;
3b46e624 855
2c0262af
FB		 856 if (insn & (1 << 22)) {
857 /* immediate */
858 val = (insn & 0xf) | ((insn >> 4) & 0xf0);
859 if (!(insn & (1 << 23)))
860 val = -val;
18acad92 861 val += extra;
537730b9 862 if (val != 0)
b0109805 863 tcg_gen_addi_i32(var, var, val);
2c0262af
FB		 864 } else {
865 /* register */
191f9a93 866 if (extra)
b0109805 867 tcg_gen_addi_i32(var, var, extra);
2c0262af 868 rm = (insn) & 0xf;
b26eefb6 869 offset = load_reg(s, rm);
2c0262af 870 if (!(insn & (1 << 23)))
b0109805 871 tcg_gen_sub_i32(var, var, offset);
2c0262af 872 else
b0109805 873 tcg_gen_add_i32(var, var, offset);
7d1b0095 874 tcg_temp_free_i32(offset);
2c0262af
FB		 875 }
876}
877
4373f3ce
PB		 878#define VFP_OP2(name) \
879static inline void gen_vfp_##name(int dp) \
880{ \
881 if (dp) \
882 gen_helper_vfp_##name##d(cpu_F0d, cpu_F0d, cpu_F1d, cpu_env); \
883 else \
884 gen_helper_vfp_##name##s(cpu_F0s, cpu_F0s, cpu_F1s, cpu_env); \
b7bcbe95
FB		 885}
886
4373f3ce
PB		 887VFP_OP2(add)
888VFP_OP2(sub)
889VFP_OP2(mul)
890VFP_OP2(div)
891
892#undef VFP_OP2
893
894static inline void gen_vfp_abs(int dp)
895{
896 if (dp)
897 gen_helper_vfp_absd(cpu_F0d, cpu_F0d);
898 else
899 gen_helper_vfp_abss(cpu_F0s, cpu_F0s);
900}
901
902static inline void gen_vfp_neg(int dp)
903{
904 if (dp)
905 gen_helper_vfp_negd(cpu_F0d, cpu_F0d);
906 else
907 gen_helper_vfp_negs(cpu_F0s, cpu_F0s);
908}
909
910static inline void gen_vfp_sqrt(int dp)
911{
912 if (dp)
913 gen_helper_vfp_sqrtd(cpu_F0d, cpu_F0d, cpu_env);
914 else
915 gen_helper_vfp_sqrts(cpu_F0s, cpu_F0s, cpu_env);
916}
917
918static inline void gen_vfp_cmp(int dp)
919{
920 if (dp)
921 gen_helper_vfp_cmpd(cpu_F0d, cpu_F1d, cpu_env);
922 else
923 gen_helper_vfp_cmps(cpu_F0s, cpu_F1s, cpu_env);
924}
925
926static inline void gen_vfp_cmpe(int dp)
927{
928 if (dp)
929 gen_helper_vfp_cmped(cpu_F0d, cpu_F1d, cpu_env);
930 else
931 gen_helper_vfp_cmpes(cpu_F0s, cpu_F1s, cpu_env);
932}
933
934static inline void gen_vfp_F1_ld0(int dp)
935{
936 if (dp)
5b340b51 937 tcg_gen_movi_i64(cpu_F1d, 0);
4373f3ce 938 else
5b340b51 939 tcg_gen_movi_i32(cpu_F1s, 0);
4373f3ce
PB		 940}
941
942static inline void gen_vfp_uito(int dp)
943{
944 if (dp)
945 gen_helper_vfp_uitod(cpu_F0d, cpu_F0s, cpu_env);
946 else
947 gen_helper_vfp_uitos(cpu_F0s, cpu_F0s, cpu_env);
948}
949
950static inline void gen_vfp_sito(int dp)
951{
952 if (dp)
66230e0d 953 gen_helper_vfp_sitod(cpu_F0d, cpu_F0s, cpu_env);
4373f3ce 954 else
66230e0d 955 gen_helper_vfp_sitos(cpu_F0s, cpu_F0s, cpu_env);
4373f3ce
PB		 956}
957
958static inline void gen_vfp_toui(int dp)
959{
960 if (dp)
961 gen_helper_vfp_touid(cpu_F0s, cpu_F0d, cpu_env);
962 else
963 gen_helper_vfp_touis(cpu_F0s, cpu_F0s, cpu_env);
964}
965
966static inline void gen_vfp_touiz(int dp)
967{
968 if (dp)
969 gen_helper_vfp_touizd(cpu_F0s, cpu_F0d, cpu_env);
970 else
971 gen_helper_vfp_touizs(cpu_F0s, cpu_F0s, cpu_env);
972}
973
974static inline void gen_vfp_tosi(int dp)
975{
976 if (dp)
977 gen_helper_vfp_tosid(cpu_F0s, cpu_F0d, cpu_env);
978 else
979 gen_helper_vfp_tosis(cpu_F0s, cpu_F0s, cpu_env);
980}
981
982static inline void gen_vfp_tosiz(int dp)
9ee6e8bb
PB		 983{
984 if (dp)
4373f3ce 985 gen_helper_vfp_tosizd(cpu_F0s, cpu_F0d, cpu_env);
9ee6e8bb 986 else
4373f3ce
PB		 987 gen_helper_vfp_tosizs(cpu_F0s, cpu_F0s, cpu_env);
988}
989
990#define VFP_GEN_FIX(name) \
991static inline void gen_vfp_##name(int dp, int shift) \
992{ \
b75263d6 993 TCGv tmp_shift = tcg_const_i32(shift); \
4373f3ce 994 if (dp) \
b75263d6 995 gen_helper_vfp_##name##d(cpu_F0d, cpu_F0d, tmp_shift, cpu_env);\
4373f3ce 996 else \
b75263d6
JR		 997 gen_helper_vfp_##name##s(cpu_F0s, cpu_F0s, tmp_shift, cpu_env);\
998 tcg_temp_free_i32(tmp_shift); \
9ee6e8bb 999}
4373f3ce
PB		 1000VFP_GEN_FIX(tosh)
1001VFP_GEN_FIX(tosl)
1002VFP_GEN_FIX(touh)
1003VFP_GEN_FIX(toul)
1004VFP_GEN_FIX(shto)
1005VFP_GEN_FIX(slto)
1006VFP_GEN_FIX(uhto)
1007VFP_GEN_FIX(ulto)
1008#undef VFP_GEN_FIX
9ee6e8bb 1009
312eea9f 1010static inline void gen_vfp_ld(DisasContext *s, int dp, TCGv addr)
b5ff1b31
FB		 1011{
1012 if (dp)
312eea9f 1013 tcg_gen_qemu_ld64(cpu_F0d, addr, IS_USER(s));
b5ff1b31 1014 else
312eea9f 1015 tcg_gen_qemu_ld32u(cpu_F0s, addr, IS_USER(s));
b5ff1b31
FB		 1016}
1017
312eea9f 1018static inline void gen_vfp_st(DisasContext *s, int dp, TCGv addr)
b5ff1b31
FB		 1019{
1020 if (dp)
312eea9f 1021 tcg_gen_qemu_st64(cpu_F0d, addr, IS_USER(s));
b5ff1b31 1022 else
312eea9f 1023 tcg_gen_qemu_st32(cpu_F0s, addr, IS_USER(s));
b5ff1b31
FB		 1024}
1025
8e96005d
FB		 1026static inline long
1027vfp_reg_offset (int dp, int reg)
1028{
1029 if (dp)
1030 return offsetof(CPUARMState, vfp.regs[reg]);
1031 else if (reg & 1) {
1032 return offsetof(CPUARMState, vfp.regs[reg >> 1])
1033 + offsetof(CPU_DoubleU, l.upper);
1034 } else {
1035 return offsetof(CPUARMState, vfp.regs[reg >> 1])
1036 + offsetof(CPU_DoubleU, l.lower);
1037 }
1038}
9ee6e8bb
PB		 1039
1040/* Return the offset of a 32-bit piece of a NEON register.
1041 zero is the least significant end of the register. */
1042static inline long
1043neon_reg_offset (int reg, int n)
1044{
1045 int sreg;
1046 sreg = reg * 2 + n;
1047 return vfp_reg_offset(0, sreg);
1048}
1049
8f8e3aa4
PB		 1050static TCGv neon_load_reg(int reg, int pass)
1051{
7d1b0095 1052 TCGv tmp = tcg_temp_new_i32();
8f8e3aa4
PB		 1053 tcg_gen_ld_i32(tmp, cpu_env, neon_reg_offset(reg, pass));
1054 return tmp;
1055}
1056
1057static void neon_store_reg(int reg, int pass, TCGv var)
1058{
1059 tcg_gen_st_i32(var, cpu_env, neon_reg_offset(reg, pass));
7d1b0095 1060 tcg_temp_free_i32(var);
8f8e3aa4
PB		 1061}
1062
a7812ae4 1063static inline void neon_load_reg64(TCGv_i64 var, int reg)
ad69471c
PB		 1064{
1065 tcg_gen_ld_i64(var, cpu_env, vfp_reg_offset(1, reg));
1066}
1067
a7812ae4 1068static inline void neon_store_reg64(TCGv_i64 var, int reg)
ad69471c
PB		 1069{
1070 tcg_gen_st_i64(var, cpu_env, vfp_reg_offset(1, reg));
1071}
1072
4373f3ce
PB		 1073#define tcg_gen_ld_f32 tcg_gen_ld_i32
1074#define tcg_gen_ld_f64 tcg_gen_ld_i64
1075#define tcg_gen_st_f32 tcg_gen_st_i32
1076#define tcg_gen_st_f64 tcg_gen_st_i64
1077
b7bcbe95
FB		 1078static inline void gen_mov_F0_vreg(int dp, int reg)
1079{
1080 if (dp)
4373f3ce 1081 tcg_gen_ld_f64(cpu_F0d, cpu_env, vfp_reg_offset(dp, reg));
b7bcbe95 1082 else
4373f3ce 1083 tcg_gen_ld_f32(cpu_F0s, cpu_env, vfp_reg_offset(dp, reg));
b7bcbe95
FB		 1084}
1085
1086static inline void gen_mov_F1_vreg(int dp, int reg)
1087{
1088 if (dp)
4373f3ce 1089 tcg_gen_ld_f64(cpu_F1d, cpu_env, vfp_reg_offset(dp, reg));
b7bcbe95 1090 else
4373f3ce 1091 tcg_gen_ld_f32(cpu_F1s, cpu_env, vfp_reg_offset(dp, reg));
b7bcbe95
FB		 1092}
1093
1094static inline void gen_mov_vreg_F0(int dp, int reg)
1095{
1096 if (dp)
4373f3ce 1097 tcg_gen_st_f64(cpu_F0d, cpu_env, vfp_reg_offset(dp, reg));
b7bcbe95 1098 else
4373f3ce 1099 tcg_gen_st_f32(cpu_F0s, cpu_env, vfp_reg_offset(dp, reg));
b7bcbe95
FB		 1100}
1101
18c9b560
AZ		 1102#define ARM_CP_RW_BIT (1 << 20)
1103
a7812ae4 1104static inline void iwmmxt_load_reg(TCGv_i64 var, int reg)
e677137d
PB		 1105{
1106 tcg_gen_ld_i64(var, cpu_env, offsetof(CPUState, iwmmxt.regs[reg]));
1107}
1108
a7812ae4 1109static inline void iwmmxt_store_reg(TCGv_i64 var, int reg)
e677137d
PB		 1110{
1111 tcg_gen_st_i64(var, cpu_env, offsetof(CPUState, iwmmxt.regs[reg]));
1112}
1113
da6b5335 1114static inline TCGv iwmmxt_load_creg(int reg)
e677137d 1115{
7d1b0095 1116 TCGv var = tcg_temp_new_i32();
da6b5335
FN		 1117 tcg_gen_ld_i32(var, cpu_env, offsetof(CPUState, iwmmxt.cregs[reg]));
1118 return var;
e677137d
PB		 1119}
1120
da6b5335 1121static inline void iwmmxt_store_creg(int reg, TCGv var)
e677137d 1122{
da6b5335 1123 tcg_gen_st_i32(var, cpu_env, offsetof(CPUState, iwmmxt.cregs[reg]));
7d1b0095 1124 tcg_temp_free_i32(var);
e677137d
PB		 1125}
1126
1127static inline void gen_op_iwmmxt_movq_wRn_M0(int rn)
1128{
1129 iwmmxt_store_reg(cpu_M0, rn);
1130}
1131
1132static inline void gen_op_iwmmxt_movq_M0_wRn(int rn)
1133{
1134 iwmmxt_load_reg(cpu_M0, rn);
1135}
1136
1137static inline void gen_op_iwmmxt_orq_M0_wRn(int rn)
1138{
1139 iwmmxt_load_reg(cpu_V1, rn);
1140 tcg_gen_or_i64(cpu_M0, cpu_M0, cpu_V1);
1141}
1142
1143static inline void gen_op_iwmmxt_andq_M0_wRn(int rn)
1144{
1145 iwmmxt_load_reg(cpu_V1, rn);
1146 tcg_gen_and_i64(cpu_M0, cpu_M0, cpu_V1);
1147}
1148
1149static inline void gen_op_iwmmxt_xorq_M0_wRn(int rn)
1150{
1151 iwmmxt_load_reg(cpu_V1, rn);
1152 tcg_gen_xor_i64(cpu_M0, cpu_M0, cpu_V1);
1153}
1154
1155#define IWMMXT_OP(name) \
1156static inline void gen_op_iwmmxt_##name##_M0_wRn(int rn) \
1157{ \
1158 iwmmxt_load_reg(cpu_V1, rn); \
1159 gen_helper_iwmmxt_##name(cpu_M0, cpu_M0, cpu_V1); \
1160}
1161
1162#define IWMMXT_OP_ENV(name) \
1163static inline void gen_op_iwmmxt_##name##_M0_wRn(int rn) \
1164{ \
1165 iwmmxt_load_reg(cpu_V1, rn); \
1166 gen_helper_iwmmxt_##name(cpu_M0, cpu_env, cpu_M0, cpu_V1); \
1167}
1168
1169#define IWMMXT_OP_ENV_SIZE(name) \
1170IWMMXT_OP_ENV(name##b) \
1171IWMMXT_OP_ENV(name##w) \
1172IWMMXT_OP_ENV(name##l)
1173
1174#define IWMMXT_OP_ENV1(name) \
1175static inline void gen_op_iwmmxt_##name##_M0(void) \
1176{ \
1177 gen_helper_iwmmxt_##name(cpu_M0, cpu_env, cpu_M0); \
1178}
1179
1180IWMMXT_OP(maddsq)
1181IWMMXT_OP(madduq)
1182IWMMXT_OP(sadb)
1183IWMMXT_OP(sadw)
1184IWMMXT_OP(mulslw)
1185IWMMXT_OP(mulshw)
1186IWMMXT_OP(mululw)
1187IWMMXT_OP(muluhw)
1188IWMMXT_OP(macsw)
1189IWMMXT_OP(macuw)
1190
1191IWMMXT_OP_ENV_SIZE(unpackl)
1192IWMMXT_OP_ENV_SIZE(unpackh)
1193
1194IWMMXT_OP_ENV1(unpacklub)
1195IWMMXT_OP_ENV1(unpackluw)
1196IWMMXT_OP_ENV1(unpacklul)
1197IWMMXT_OP_ENV1(unpackhub)
1198IWMMXT_OP_ENV1(unpackhuw)
1199IWMMXT_OP_ENV1(unpackhul)
1200IWMMXT_OP_ENV1(unpacklsb)
1201IWMMXT_OP_ENV1(unpacklsw)
1202IWMMXT_OP_ENV1(unpacklsl)
1203IWMMXT_OP_ENV1(unpackhsb)
1204IWMMXT_OP_ENV1(unpackhsw)
1205IWMMXT_OP_ENV1(unpackhsl)
1206
1207IWMMXT_OP_ENV_SIZE(cmpeq)
1208IWMMXT_OP_ENV_SIZE(cmpgtu)
1209IWMMXT_OP_ENV_SIZE(cmpgts)
1210
1211IWMMXT_OP_ENV_SIZE(mins)
1212IWMMXT_OP_ENV_SIZE(minu)
1213IWMMXT_OP_ENV_SIZE(maxs)
1214IWMMXT_OP_ENV_SIZE(maxu)
1215
1216IWMMXT_OP_ENV_SIZE(subn)
1217IWMMXT_OP_ENV_SIZE(addn)
1218IWMMXT_OP_ENV_SIZE(subu)
1219IWMMXT_OP_ENV_SIZE(addu)
1220IWMMXT_OP_ENV_SIZE(subs)
1221IWMMXT_OP_ENV_SIZE(adds)
1222
1223IWMMXT_OP_ENV(avgb0)
1224IWMMXT_OP_ENV(avgb1)
1225IWMMXT_OP_ENV(avgw0)
1226IWMMXT_OP_ENV(avgw1)
1227
1228IWMMXT_OP(msadb)
1229
1230IWMMXT_OP_ENV(packuw)
1231IWMMXT_OP_ENV(packul)
1232IWMMXT_OP_ENV(packuq)
1233IWMMXT_OP_ENV(packsw)
1234IWMMXT_OP_ENV(packsl)
1235IWMMXT_OP_ENV(packsq)
1236
e677137d
PB		 1237static void gen_op_iwmmxt_set_mup(void)
1238{
1239 TCGv tmp;
1240 tmp = load_cpu_field(iwmmxt.cregs[ARM_IWMMXT_wCon]);
1241 tcg_gen_ori_i32(tmp, tmp, 2);
1242 store_cpu_field(tmp, iwmmxt.cregs[ARM_IWMMXT_wCon]);
1243}
1244
1245static void gen_op_iwmmxt_set_cup(void)
1246{
1247 TCGv tmp;
1248 tmp = load_cpu_field(iwmmxt.cregs[ARM_IWMMXT_wCon]);
1249 tcg_gen_ori_i32(tmp, tmp, 1);
1250 store_cpu_field(tmp, iwmmxt.cregs[ARM_IWMMXT_wCon]);
1251}
1252
1253static void gen_op_iwmmxt_setpsr_nz(void)
1254{
7d1b0095 1255 TCGv tmp = tcg_temp_new_i32();
e677137d
PB		 1256 gen_helper_iwmmxt_setpsr_nz(tmp, cpu_M0);
1257 store_cpu_field(tmp, iwmmxt.cregs[ARM_IWMMXT_wCASF]);
1258}
1259
1260static inline void gen_op_iwmmxt_addl_M0_wRn(int rn)
1261{
1262 iwmmxt_load_reg(cpu_V1, rn);
86831435 1263 tcg_gen_ext32u_i64(cpu_V1, cpu_V1);
e677137d
PB		 1264 tcg_gen_add_i64(cpu_M0, cpu_M0, cpu_V1);
1265}
1266
da6b5335 1267static inline int gen_iwmmxt_address(DisasContext *s, uint32_t insn, TCGv dest)
18c9b560
AZ		 1268{
1269 int rd;
1270 uint32_t offset;
da6b5335 1271 TCGv tmp;
18c9b560
AZ		 1272
1273 rd = (insn >> 16) & 0xf;
da6b5335 1274 tmp = load_reg(s, rd);
18c9b560
AZ		 1275
1276 offset = (insn & 0xff) << ((insn >> 7) & 2);
1277 if (insn & (1 << 24)) {
1278 /* Pre indexed */
1279 if (insn & (1 << 23))
da6b5335 1280 tcg_gen_addi_i32(tmp, tmp, offset);
18c9b560 1281 else
da6b5335
FN		 1282 tcg_gen_addi_i32(tmp, tmp, -offset);
1283 tcg_gen_mov_i32(dest, tmp);
18c9b560 1284 if (insn & (1 << 21))
da6b5335
FN		 1285 store_reg(s, rd, tmp);
1286 else
7d1b0095 1287 tcg_temp_free_i32(tmp);
18c9b560
AZ		 1288 } else if (insn & (1 << 21)) {
1289 /* Post indexed */
da6b5335 1290 tcg_gen_mov_i32(dest, tmp);
18c9b560 1291 if (insn & (1 << 23))
da6b5335 1292 tcg_gen_addi_i32(tmp, tmp, offset);
18c9b560 1293 else
da6b5335
FN		 1294 tcg_gen_addi_i32(tmp, tmp, -offset);
1295 store_reg(s, rd, tmp);
18c9b560
AZ		 1296 } else if (!(insn & (1 << 23)))
1297 return 1;
1298 return 0;
1299}
1300
da6b5335 1301static inline int gen_iwmmxt_shift(uint32_t insn, uint32_t mask, TCGv dest)
18c9b560
AZ		 1302{
1303 int rd = (insn >> 0) & 0xf;
da6b5335 1304 TCGv tmp;
18c9b560 1305
da6b5335
FN		 1306 if (insn & (1 << 8)) {
1307 if (rd < ARM_IWMMXT_wCGR0 || rd > ARM_IWMMXT_wCGR3) {
18c9b560 1308 return 1;
da6b5335
FN		 1309 } else {
1310 tmp = iwmmxt_load_creg(rd);
1311 }
1312 } else {
7d1b0095 1313 tmp = tcg_temp_new_i32();
da6b5335
FN		 1314 iwmmxt_load_reg(cpu_V0, rd);
1315 tcg_gen_trunc_i64_i32(tmp, cpu_V0);
1316 }
1317 tcg_gen_andi_i32(tmp, tmp, mask);
1318 tcg_gen_mov_i32(dest, tmp);
7d1b0095 1319 tcg_temp_free_i32(tmp);
18c9b560
AZ		 1320 return 0;
1321}
1322
1323/* Disassemble an iwMMXt instruction. Returns nonzero if an error occured
1324 (ie. an undefined instruction). */
1325static int disas_iwmmxt_insn(CPUState *env, DisasContext *s, uint32_t insn)
1326{
1327 int rd, wrd;
1328 int rdhi, rdlo, rd0, rd1, i;
da6b5335
FN		 1329 TCGv addr;
1330 TCGv tmp, tmp2, tmp3;
18c9b560
AZ		 1331
1332 if ((insn & 0x0e000e00) == 0x0c000000) {
1333 if ((insn & 0x0fe00ff0) == 0x0c400000) {
1334 wrd = insn & 0xf;
1335 rdlo = (insn >> 12) & 0xf;
1336 rdhi = (insn >> 16) & 0xf;
1337 if (insn & ARM_CP_RW_BIT) { /* TMRRC */
da6b5335
FN		 1338 iwmmxt_load_reg(cpu_V0, wrd);
1339 tcg_gen_trunc_i64_i32(cpu_R[rdlo], cpu_V0);
1340 tcg_gen_shri_i64(cpu_V0, cpu_V0, 32);
1341 tcg_gen_trunc_i64_i32(cpu_R[rdhi], cpu_V0);
18c9b560 1342 } else { /* TMCRR */
da6b5335
FN		 1343 tcg_gen_concat_i32_i64(cpu_V0, cpu_R[rdlo], cpu_R[rdhi]);
1344 iwmmxt_store_reg(cpu_V0, wrd);
18c9b560
AZ		 1345 gen_op_iwmmxt_set_mup();
1346 }
1347 return 0;
1348 }
1349
1350 wrd = (insn >> 12) & 0xf;
7d1b0095 1351 addr = tcg_temp_new_i32();
da6b5335 1352 if (gen_iwmmxt_address(s, insn, addr)) {
7d1b0095 1353 tcg_temp_free_i32(addr);
18c9b560 1354 return 1;
da6b5335 1355 }
18c9b560
AZ		 1356 if (insn & ARM_CP_RW_BIT) {
1357 if ((insn >> 28) == 0xf) { /* WLDRW wCx */
7d1b0095 1358 tmp = tcg_temp_new_i32();
da6b5335
FN		 1359 tcg_gen_qemu_ld32u(tmp, addr, IS_USER(s));
1360 iwmmxt_store_creg(wrd, tmp);
18c9b560 1361 } else {
e677137d
PB		 1362 i = 1;
1363 if (insn & (1 << 8)) {
1364 if (insn & (1 << 22)) { /* WLDRD */
da6b5335 1365 tcg_gen_qemu_ld64(cpu_M0, addr, IS_USER(s));
e677137d
PB		 1366 i = 0;
1367 } else { /* WLDRW wRd */
da6b5335 1368 tmp = gen_ld32(addr, IS_USER(s));
e677137d
PB		 1369 }
1370 } else {
1371 if (insn & (1 << 22)) { /* WLDRH */
da6b5335 1372 tmp = gen_ld16u(addr, IS_USER(s));
e677137d 1373 } else { /* WLDRB */
da6b5335 1374 tmp = gen_ld8u(addr, IS_USER(s));
e677137d
PB		 1375 }
1376 }
1377 if (i) {
1378 tcg_gen_extu_i32_i64(cpu_M0, tmp);
7d1b0095 1379 tcg_temp_free_i32(tmp);
e677137d 1380 }
18c9b560
AZ		 1381 gen_op_iwmmxt_movq_wRn_M0(wrd);
1382 }
1383 } else {
1384 if ((insn >> 28) == 0xf) { /* WSTRW wCx */
da6b5335
FN		 1385 tmp = iwmmxt_load_creg(wrd);
1386 gen_st32(tmp, addr, IS_USER(s));
18c9b560
AZ		 1387 } else {
1388 gen_op_iwmmxt_movq_M0_wRn(wrd);
7d1b0095 1389 tmp = tcg_temp_new_i32();
e677137d
PB		 1390 if (insn & (1 << 8)) {
1391 if (insn & (1 << 22)) { /* WSTRD */
7d1b0095 1392 tcg_temp_free_i32(tmp);
da6b5335 1393 tcg_gen_qemu_st64(cpu_M0, addr, IS_USER(s));
e677137d
PB		 1394 } else { /* WSTRW wRd */
1395 tcg_gen_trunc_i64_i32(tmp, cpu_M0);
da6b5335 1396 gen_st32(tmp, addr, IS_USER(s));
e677137d
PB		 1397 }
1398 } else {
1399 if (insn & (1 << 22)) { /* WSTRH */
1400 tcg_gen_trunc_i64_i32(tmp, cpu_M0);
da6b5335 1401 gen_st16(tmp, addr, IS_USER(s));
e677137d
PB		 1402 } else { /* WSTRB */
1403 tcg_gen_trunc_i64_i32(tmp, cpu_M0);
da6b5335 1404 gen_st8(tmp, addr, IS_USER(s));
e677137d
PB		 1405 }
1406 }
18c9b560
AZ		 1407 }
1408 }
7d1b0095 1409 tcg_temp_free_i32(addr);
18c9b560
AZ		 1410 return 0;
1411 }
1412
1413 if ((insn & 0x0f000000) != 0x0e000000)
1414 return 1;
1415
1416 switch (((insn >> 12) & 0xf00) | ((insn >> 4) & 0xff)) {
1417 case 0x000: /* WOR */
1418 wrd = (insn >> 12) & 0xf;
1419 rd0 = (insn >> 0) & 0xf;
1420 rd1 = (insn >> 16) & 0xf;
1421 gen_op_iwmmxt_movq_M0_wRn(rd0);
1422 gen_op_iwmmxt_orq_M0_wRn(rd1);
1423 gen_op_iwmmxt_setpsr_nz();
1424 gen_op_iwmmxt_movq_wRn_M0(wrd);
1425 gen_op_iwmmxt_set_mup();
1426 gen_op_iwmmxt_set_cup();
1427 break;
1428 case 0x011: /* TMCR */
1429 if (insn & 0xf)
1430 return 1;
1431 rd = (insn >> 12) & 0xf;
1432 wrd = (insn >> 16) & 0xf;
1433 switch (wrd) {
1434 case ARM_IWMMXT_wCID:
1435 case ARM_IWMMXT_wCASF:
1436 break;
1437 case ARM_IWMMXT_wCon:
1438 gen_op_iwmmxt_set_cup();
1439 /* Fall through. */
1440 case ARM_IWMMXT_wCSSF:
da6b5335
FN		 1441 tmp = iwmmxt_load_creg(wrd);
1442 tmp2 = load_reg(s, rd);
f669df27 1443 tcg_gen_andc_i32(tmp, tmp, tmp2);
7d1b0095 1444 tcg_temp_free_i32(tmp2);
da6b5335 1445 iwmmxt_store_creg(wrd, tmp);
18c9b560
AZ		 1446 break;
1447 case ARM_IWMMXT_wCGR0:
1448 case ARM_IWMMXT_wCGR1:
1449 case ARM_IWMMXT_wCGR2:
1450 case ARM_IWMMXT_wCGR3:
1451 gen_op_iwmmxt_set_cup();
da6b5335
FN		 1452 tmp = load_reg(s, rd);
1453 iwmmxt_store_creg(wrd, tmp);
18c9b560
AZ		 1454 break;
1455 default:
1456 return 1;
1457 }
1458 break;
1459 case 0x100: /* WXOR */
1460 wrd = (insn >> 12) & 0xf;
1461 rd0 = (insn >> 0) & 0xf;
1462 rd1 = (insn >> 16) & 0xf;
1463 gen_op_iwmmxt_movq_M0_wRn(rd0);
1464 gen_op_iwmmxt_xorq_M0_wRn(rd1);
1465 gen_op_iwmmxt_setpsr_nz();
1466 gen_op_iwmmxt_movq_wRn_M0(wrd);
1467 gen_op_iwmmxt_set_mup();
1468 gen_op_iwmmxt_set_cup();
1469 break;
1470 case 0x111: /* TMRC */
1471 if (insn & 0xf)
1472 return 1;
1473 rd = (insn >> 12) & 0xf;
1474 wrd = (insn >> 16) & 0xf;
da6b5335
FN		 1475 tmp = iwmmxt_load_creg(wrd);
1476 store_reg(s, rd, tmp);
18c9b560
AZ		 1477 break;
1478 case 0x300: /* WANDN */
1479 wrd = (insn >> 12) & 0xf;
1480 rd0 = (insn >> 0) & 0xf;
1481 rd1 = (insn >> 16) & 0xf;
1482 gen_op_iwmmxt_movq_M0_wRn(rd0);
e677137d 1483 tcg_gen_neg_i64(cpu_M0, cpu_M0);
18c9b560
AZ		 1484 gen_op_iwmmxt_andq_M0_wRn(rd1);
1485 gen_op_iwmmxt_setpsr_nz();
1486 gen_op_iwmmxt_movq_wRn_M0(wrd);
1487 gen_op_iwmmxt_set_mup();
1488 gen_op_iwmmxt_set_cup();
1489 break;
1490 case 0x200: /* WAND */
1491 wrd = (insn >> 12) & 0xf;
1492 rd0 = (insn >> 0) & 0xf;
1493 rd1 = (insn >> 16) & 0xf;
1494 gen_op_iwmmxt_movq_M0_wRn(rd0);
1495 gen_op_iwmmxt_andq_M0_wRn(rd1);
1496 gen_op_iwmmxt_setpsr_nz();
1497 gen_op_iwmmxt_movq_wRn_M0(wrd);
1498 gen_op_iwmmxt_set_mup();
1499 gen_op_iwmmxt_set_cup();
1500 break;
1501 case 0x810: case 0xa10: /* WMADD */
1502 wrd = (insn >> 12) & 0xf;
1503 rd0 = (insn >> 0) & 0xf;
1504 rd1 = (insn >> 16) & 0xf;
1505 gen_op_iwmmxt_movq_M0_wRn(rd0);
1506 if (insn & (1 << 21))
1507 gen_op_iwmmxt_maddsq_M0_wRn(rd1);
1508 else
1509 gen_op_iwmmxt_madduq_M0_wRn(rd1);
1510 gen_op_iwmmxt_movq_wRn_M0(wrd);
1511 gen_op_iwmmxt_set_mup();
1512 break;
1513 case 0x10e: case 0x50e: case 0x90e: case 0xd0e: /* WUNPCKIL */
1514 wrd = (insn >> 12) & 0xf;
1515 rd0 = (insn >> 16) & 0xf;
1516 rd1 = (insn >> 0) & 0xf;
1517 gen_op_iwmmxt_movq_M0_wRn(rd0);
1518 switch ((insn >> 22) & 3) {
1519 case 0:
1520 gen_op_iwmmxt_unpacklb_M0_wRn(rd1);
1521 break;
1522 case 1:
1523 gen_op_iwmmxt_unpacklw_M0_wRn(rd1);
1524 break;
1525 case 2:
1526 gen_op_iwmmxt_unpackll_M0_wRn(rd1);
1527 break;
1528 case 3:
1529 return 1;
1530 }
1531 gen_op_iwmmxt_movq_wRn_M0(wrd);
1532 gen_op_iwmmxt_set_mup();
1533 gen_op_iwmmxt_set_cup();
1534 break;
1535 case 0x10c: case 0x50c: case 0x90c: case 0xd0c: /* WUNPCKIH */
1536 wrd = (insn >> 12) & 0xf;
1537 rd0 = (insn >> 16) & 0xf;
1538 rd1 = (insn >> 0) & 0xf;
1539 gen_op_iwmmxt_movq_M0_wRn(rd0);
1540 switch ((insn >> 22) & 3) {
1541 case 0:
1542 gen_op_iwmmxt_unpackhb_M0_wRn(rd1);
1543 break;
1544 case 1:
1545 gen_op_iwmmxt_unpackhw_M0_wRn(rd1);
1546 break;
1547 case 2:
1548 gen_op_iwmmxt_unpackhl_M0_wRn(rd1);
1549 break;
1550 case 3:
1551 return 1;
1552 }
1553 gen_op_iwmmxt_movq_wRn_M0(wrd);
1554 gen_op_iwmmxt_set_mup();
1555 gen_op_iwmmxt_set_cup();
1556 break;
1557 case 0x012: case 0x112: case 0x412: case 0x512: /* WSAD */
1558 wrd = (insn >> 12) & 0xf;
1559 rd0 = (insn >> 16) & 0xf;
1560 rd1 = (insn >> 0) & 0xf;
1561 gen_op_iwmmxt_movq_M0_wRn(rd0);
1562 if (insn & (1 << 22))
1563 gen_op_iwmmxt_sadw_M0_wRn(rd1);
1564 else
1565 gen_op_iwmmxt_sadb_M0_wRn(rd1);
1566 if (!(insn & (1 << 20)))
1567 gen_op_iwmmxt_addl_M0_wRn(wrd);
1568 gen_op_iwmmxt_movq_wRn_M0(wrd);
1569 gen_op_iwmmxt_set_mup();
1570 break;
1571 case 0x010: case 0x110: case 0x210: case 0x310: /* WMUL */
1572 wrd = (insn >> 12) & 0xf;
1573 rd0 = (insn >> 16) & 0xf;
1574 rd1 = (insn >> 0) & 0xf;
1575 gen_op_iwmmxt_movq_M0_wRn(rd0);
e677137d
PB		 1576 if (insn & (1 << 21)) {
1577 if (insn & (1 << 20))
1578 gen_op_iwmmxt_mulshw_M0_wRn(rd1);
1579 else
1580 gen_op_iwmmxt_mulslw_M0_wRn(rd1);
1581 } else {
1582 if (insn & (1 << 20))
1583 gen_op_iwmmxt_muluhw_M0_wRn(rd1);
1584 else
1585 gen_op_iwmmxt_mululw_M0_wRn(rd1);
1586 }
18c9b560
AZ		 1587 gen_op_iwmmxt_movq_wRn_M0(wrd);
1588 gen_op_iwmmxt_set_mup();
1589 break;
1590 case 0x410: case 0x510: case 0x610: case 0x710: /* WMAC */
1591 wrd = (insn >> 12) & 0xf;
1592 rd0 = (insn >> 16) & 0xf;
1593 rd1 = (insn >> 0) & 0xf;
1594 gen_op_iwmmxt_movq_M0_wRn(rd0);
1595 if (insn & (1 << 21))
1596 gen_op_iwmmxt_macsw_M0_wRn(rd1);
1597 else
1598 gen_op_iwmmxt_macuw_M0_wRn(rd1);
1599 if (!(insn & (1 << 20))) {
e677137d
PB		 1600 iwmmxt_load_reg(cpu_V1, wrd);
1601 tcg_gen_add_i64(cpu_M0, cpu_M0, cpu_V1);
18c9b560
AZ		 1602 }
1603 gen_op_iwmmxt_movq_wRn_M0(wrd);
1604 gen_op_iwmmxt_set_mup();
1605 break;
1606 case 0x006: case 0x406: case 0x806: case 0xc06: /* WCMPEQ */
1607 wrd = (insn >> 12) & 0xf;
1608 rd0 = (insn >> 16) & 0xf;
1609 rd1 = (insn >> 0) & 0xf;
1610 gen_op_iwmmxt_movq_M0_wRn(rd0);
1611 switch ((insn >> 22) & 3) {
1612 case 0:
1613 gen_op_iwmmxt_cmpeqb_M0_wRn(rd1);
1614 break;
1615 case 1:
1616 gen_op_iwmmxt_cmpeqw_M0_wRn(rd1);
1617 break;
1618 case 2:
1619 gen_op_iwmmxt_cmpeql_M0_wRn(rd1);
1620 break;
1621 case 3:
1622 return 1;
1623 }
1624 gen_op_iwmmxt_movq_wRn_M0(wrd);
1625 gen_op_iwmmxt_set_mup();
1626 gen_op_iwmmxt_set_cup();
1627 break;
1628 case 0x800: case 0x900: case 0xc00: case 0xd00: /* WAVG2 */
1629 wrd = (insn >> 12) & 0xf;
1630 rd0 = (insn >> 16) & 0xf;
1631 rd1 = (insn >> 0) & 0xf;
1632 gen_op_iwmmxt_movq_M0_wRn(rd0);
e677137d
PB		 1633 if (insn & (1 << 22)) {
1634 if (insn & (1 << 20))
1635 gen_op_iwmmxt_avgw1_M0_wRn(rd1);
1636 else
1637 gen_op_iwmmxt_avgw0_M0_wRn(rd1);
1638 } else {
1639 if (insn & (1 << 20))
1640 gen_op_iwmmxt_avgb1_M0_wRn(rd1);
1641 else
1642 gen_op_iwmmxt_avgb0_M0_wRn(rd1);
1643 }
18c9b560
AZ		 1644 gen_op_iwmmxt_movq_wRn_M0(wrd);
1645 gen_op_iwmmxt_set_mup();
1646 gen_op_iwmmxt_set_cup();
1647 break;
1648 case 0x802: case 0x902: case 0xa02: case 0xb02: /* WALIGNR */
1649 wrd = (insn >> 12) & 0xf;
1650 rd0 = (insn >> 16) & 0xf;
1651 rd1 = (insn >> 0) & 0xf;
1652 gen_op_iwmmxt_movq_M0_wRn(rd0);
da6b5335
FN		 1653 tmp = iwmmxt_load_creg(ARM_IWMMXT_wCGR0 + ((insn >> 20) & 3));
1654 tcg_gen_andi_i32(tmp, tmp, 7);
1655 iwmmxt_load_reg(cpu_V1, rd1);
1656 gen_helper_iwmmxt_align(cpu_M0, cpu_M0, cpu_V1, tmp);
7d1b0095 1657 tcg_temp_free_i32(tmp);
18c9b560
AZ		 1658 gen_op_iwmmxt_movq_wRn_M0(wrd);
1659 gen_op_iwmmxt_set_mup();
1660 break;
1661 case 0x601: case 0x605: case 0x609: case 0x60d: /* TINSR */
da6b5335
FN		 1662 if (((insn >> 6) & 3) == 3)
1663 return 1;
18c9b560
AZ		 1664 rd = (insn >> 12) & 0xf;
1665 wrd = (insn >> 16) & 0xf;
da6b5335 1666 tmp = load_reg(s, rd);
18c9b560
AZ		 1667 gen_op_iwmmxt_movq_M0_wRn(wrd);
1668 switch ((insn >> 6) & 3) {
1669 case 0:
da6b5335
FN		 1670 tmp2 = tcg_const_i32(0xff);
1671 tmp3 = tcg_const_i32((insn & 7) << 3);
18c9b560
AZ		 1672 break;
1673 case 1:
da6b5335
FN		 1674 tmp2 = tcg_const_i32(0xffff);
1675 tmp3 = tcg_const_i32((insn & 3) << 4);
18c9b560
AZ		 1676 break;
1677 case 2:
da6b5335
FN		 1678 tmp2 = tcg_const_i32(0xffffffff);
1679 tmp3 = tcg_const_i32((insn & 1) << 5);
18c9b560 1680 break;
da6b5335
FN		 1681 default:
1682 TCGV_UNUSED(tmp2);
1683 TCGV_UNUSED(tmp3);
18c9b560 1684 }
da6b5335
FN		 1685 gen_helper_iwmmxt_insr(cpu_M0, cpu_M0, tmp, tmp2, tmp3);
1686 tcg_temp_free(tmp3);
1687 tcg_temp_free(tmp2);
7d1b0095 1688 tcg_temp_free_i32(tmp);
18c9b560
AZ		 1689 gen_op_iwmmxt_movq_wRn_M0(wrd);
1690 gen_op_iwmmxt_set_mup();
1691 break;
1692 case 0x107: case 0x507: case 0x907: case 0xd07: /* TEXTRM */
1693 rd = (insn >> 12) & 0xf;
1694 wrd = (insn >> 16) & 0xf;
da6b5335 1695 if (rd == 15 || ((insn >> 22) & 3) == 3)
18c9b560
AZ		 1696 return 1;
1697 gen_op_iwmmxt_movq_M0_wRn(wrd);
7d1b0095 1698 tmp = tcg_temp_new_i32();
18c9b560
AZ		 1699 switch ((insn >> 22) & 3) {
1700 case 0:
da6b5335
FN		 1701 tcg_gen_shri_i64(cpu_M0, cpu_M0, (insn & 7) << 3);
1702 tcg_gen_trunc_i64_i32(tmp, cpu_M0);
1703 if (insn & 8) {
1704 tcg_gen_ext8s_i32(tmp, tmp);
1705 } else {
1706 tcg_gen_andi_i32(tmp, tmp, 0xff);
18c9b560
AZ		 1707 }
1708 break;
1709 case 1:
da6b5335
FN		 1710 tcg_gen_shri_i64(cpu_M0, cpu_M0, (insn & 3) << 4);
1711 tcg_gen_trunc_i64_i32(tmp, cpu_M0);
1712 if (insn & 8) {
1713 tcg_gen_ext16s_i32(tmp, tmp);
1714 } else {
1715 tcg_gen_andi_i32(tmp, tmp, 0xffff);
18c9b560
AZ		 1716 }
1717 break;
1718 case 2:
da6b5335
FN		 1719 tcg_gen_shri_i64(cpu_M0, cpu_M0, (insn & 1) << 5);
1720 tcg_gen_trunc_i64_i32(tmp, cpu_M0);
18c9b560 1721 break;
18c9b560 1722 }
da6b5335 1723 store_reg(s, rd, tmp);
18c9b560
AZ		 1724 break;
1725 case 0x117: case 0x517: case 0x917: case 0xd17: /* TEXTRC */
da6b5335 1726 if ((insn & 0x000ff008) != 0x0003f000 || ((insn >> 22) & 3) == 3)
18c9b560 1727 return 1;
da6b5335 1728 tmp = iwmmxt_load_creg(ARM_IWMMXT_wCASF);
18c9b560
AZ		 1729 switch ((insn >> 22) & 3) {
1730 case 0:
da6b5335 1731 tcg_gen_shri_i32(tmp, tmp, ((insn & 7) << 2) + 0);
18c9b560
AZ		 1732 break;
1733 case 1:
da6b5335 1734 tcg_gen_shri_i32(tmp, tmp, ((insn & 3) << 3) + 4);
18c9b560
AZ		 1735 break;
1736 case 2:
da6b5335 1737 tcg_gen_shri_i32(tmp, tmp, ((insn & 1) << 4) + 12);
18c9b560 1738 break;
18c9b560 1739 }
da6b5335
FN		 1740 tcg_gen_shli_i32(tmp, tmp, 28);
1741 gen_set_nzcv(tmp);
7d1b0095 1742 tcg_temp_free_i32(tmp);
18c9b560
AZ		 1743 break;
1744 case 0x401: case 0x405: case 0x409: case 0x40d: /* TBCST */
da6b5335
FN		 1745 if (((insn >> 6) & 3) == 3)
1746 return 1;
18c9b560
AZ		 1747 rd = (insn >> 12) & 0xf;
1748 wrd = (insn >> 16) & 0xf;
da6b5335 1749 tmp = load_reg(s, rd);
18c9b560
AZ		 1750 switch ((insn >> 6) & 3) {
1751 case 0:
da6b5335 1752 gen_helper_iwmmxt_bcstb(cpu_M0, tmp);
18c9b560
AZ		 1753 break;
1754 case 1:
da6b5335 1755 gen_helper_iwmmxt_bcstw(cpu_M0, tmp);
18c9b560
AZ		 1756 break;
1757 case 2:
da6b5335 1758 gen_helper_iwmmxt_bcstl(cpu_M0, tmp);
18c9b560 1759 break;
18c9b560 1760 }
7d1b0095 1761 tcg_temp_free_i32(tmp);
18c9b560
AZ		 1762 gen_op_iwmmxt_movq_wRn_M0(wrd);
1763 gen_op_iwmmxt_set_mup();
1764 break;
1765 case 0x113: case 0x513: case 0x913: case 0xd13: /* TANDC */
da6b5335 1766 if ((insn & 0x000ff00f) != 0x0003f000 || ((insn >> 22) & 3) == 3)
18c9b560 1767 return 1;
da6b5335 1768 tmp = iwmmxt_load_creg(ARM_IWMMXT_wCASF);
7d1b0095 1769 tmp2 = tcg_temp_new_i32();
da6b5335 1770 tcg_gen_mov_i32(tmp2, tmp);
18c9b560
AZ		 1771 switch ((insn >> 22) & 3) {
1772 case 0:
1773 for (i = 0; i < 7; i ++) {
da6b5335
FN		 1774 tcg_gen_shli_i32(tmp2, tmp2, 4);
1775 tcg_gen_and_i32(tmp, tmp, tmp2);
18c9b560
AZ		 1776 }
1777 break;
1778 case 1:
1779 for (i = 0; i < 3; i ++) {
da6b5335
FN		 1780 tcg_gen_shli_i32(tmp2, tmp2, 8);
1781 tcg_gen_and_i32(tmp, tmp, tmp2);
18c9b560
AZ		 1782 }
1783 break;
1784 case 2:
da6b5335
FN		 1785 tcg_gen_shli_i32(tmp2, tmp2, 16);
1786 tcg_gen_and_i32(tmp, tmp, tmp2);
18c9b560 1787 break;
18c9b560 1788 }
da6b5335 1789 gen_set_nzcv(tmp);
7d1b0095
PM		 1790 tcg_temp_free_i32(tmp2);
1791 tcg_temp_free_i32(tmp);
18c9b560
AZ		 1792 break;
1793 case 0x01c: case 0x41c: case 0x81c: case 0xc1c: /* WACC */
1794 wrd = (insn >> 12) & 0xf;
1795 rd0 = (insn >> 16) & 0xf;
1796 gen_op_iwmmxt_movq_M0_wRn(rd0);
1797 switch ((insn >> 22) & 3) {
1798 case 0:
e677137d 1799 gen_helper_iwmmxt_addcb(cpu_M0, cpu_M0);
18c9b560
AZ		 1800 break;
1801 case 1:
e677137d 1802 gen_helper_iwmmxt_addcw(cpu_M0, cpu_M0);
18c9b560
AZ		 1803 break;
1804 case 2:
e677137d 1805 gen_helper_iwmmxt_addcl(cpu_M0, cpu_M0);
18c9b560
AZ		 1806 break;
1807 case 3:
1808 return 1;
1809 }
1810 gen_op_iwmmxt_movq_wRn_M0(wrd);
1811 gen_op_iwmmxt_set_mup();
1812 break;
1813 case 0x115: case 0x515: case 0x915: case 0xd15: /* TORC */
da6b5335 1814 if ((insn & 0x000ff00f) != 0x0003f000 || ((insn >> 22) & 3) == 3)
18c9b560 1815 return 1;
da6b5335 1816 tmp = iwmmxt_load_creg(ARM_IWMMXT_wCASF);
7d1b0095 1817 tmp2 = tcg_temp_new_i32();
da6b5335 1818 tcg_gen_mov_i32(tmp2, tmp);
18c9b560
AZ		 1819 switch ((insn >> 22) & 3) {
1820 case 0:
1821 for (i = 0; i < 7; i ++) {
da6b5335
FN		 1822 tcg_gen_shli_i32(tmp2, tmp2, 4);
1823 tcg_gen_or_i32(tmp, tmp, tmp2);
18c9b560
AZ		 1824 }
1825 break;
1826 case 1:
1827 for (i = 0; i < 3; i ++) {
da6b5335
FN		 1828 tcg_gen_shli_i32(tmp2, tmp2, 8);
1829 tcg_gen_or_i32(tmp, tmp, tmp2);
18c9b560
AZ		 1830 }
1831 break;
1832 case 2:
da6b5335
FN		 1833 tcg_gen_shli_i32(tmp2, tmp2, 16);
1834 tcg_gen_or_i32(tmp, tmp, tmp2);
18c9b560 1835 break;
18c9b560 1836 }
da6b5335 1837 gen_set_nzcv(tmp);
7d1b0095
PM		 1838 tcg_temp_free_i32(tmp2);
1839 tcg_temp_free_i32(tmp);
18c9b560
AZ		 1840 break;
1841 case 0x103: case 0x503: case 0x903: case 0xd03: /* TMOVMSK */
1842 rd = (insn >> 12) & 0xf;
1843 rd0 = (insn >> 16) & 0xf;
da6b5335 1844 if ((insn & 0xf) != 0 || ((insn >> 22) & 3) == 3)
18c9b560
AZ		 1845 return 1;
1846 gen_op_iwmmxt_movq_M0_wRn(rd0);
7d1b0095 1847 tmp = tcg_temp_new_i32();
18c9b560
AZ		 1848 switch ((insn >> 22) & 3) {
1849 case 0:
da6b5335 1850 gen_helper_iwmmxt_msbb(tmp, cpu_M0);
18c9b560
AZ		 1851 break;
1852 case 1:
da6b5335 1853 gen_helper_iwmmxt_msbw(tmp, cpu_M0);
18c9b560
AZ		 1854 break;
1855 case 2:
da6b5335 1856 gen_helper_iwmmxt_msbl(tmp, cpu_M0);
18c9b560 1857 break;
18c9b560 1858 }
da6b5335 1859 store_reg(s, rd, tmp);
18c9b560
AZ		 1860 break;
1861 case 0x106: case 0x306: case 0x506: case 0x706: /* WCMPGT */
1862 case 0x906: case 0xb06: case 0xd06: case 0xf06:
1863 wrd = (insn >> 12) & 0xf;
1864 rd0 = (insn >> 16) & 0xf;
1865 rd1 = (insn >> 0) & 0xf;
1866 gen_op_iwmmxt_movq_M0_wRn(rd0);
1867 switch ((insn >> 22) & 3) {
1868 case 0:
1869 if (insn & (1 << 21))
1870 gen_op_iwmmxt_cmpgtsb_M0_wRn(rd1);
1871 else
1872 gen_op_iwmmxt_cmpgtub_M0_wRn(rd1);
1873 break;
1874 case 1:
1875 if (insn & (1 << 21))
1876 gen_op_iwmmxt_cmpgtsw_M0_wRn(rd1);
1877 else
1878 gen_op_iwmmxt_cmpgtuw_M0_wRn(rd1);
1879 break;
1880 case 2:
1881 if (insn & (1 << 21))
1882 gen_op_iwmmxt_cmpgtsl_M0_wRn(rd1);
1883 else
1884 gen_op_iwmmxt_cmpgtul_M0_wRn(rd1);
1885 break;
1886 case 3:
1887 return 1;
1888 }
1889 gen_op_iwmmxt_movq_wRn_M0(wrd);
1890 gen_op_iwmmxt_set_mup();
1891 gen_op_iwmmxt_set_cup();
1892 break;
1893 case 0x00e: case 0x20e: case 0x40e: case 0x60e: /* WUNPCKEL */
1894 case 0x80e: case 0xa0e: case 0xc0e: case 0xe0e:
1895 wrd = (insn >> 12) & 0xf;
1896 rd0 = (insn >> 16) & 0xf;
1897 gen_op_iwmmxt_movq_M0_wRn(rd0);
1898 switch ((insn >> 22) & 3) {
1899 case 0:
1900 if (insn & (1 << 21))
1901 gen_op_iwmmxt_unpacklsb_M0();
1902 else
1903 gen_op_iwmmxt_unpacklub_M0();
1904 break;
1905 case 1:
1906 if (insn & (1 << 21))
1907 gen_op_iwmmxt_unpacklsw_M0();
1908 else
1909 gen_op_iwmmxt_unpackluw_M0();
1910 break;
1911 case 2:
1912 if (insn & (1 << 21))
1913 gen_op_iwmmxt_unpacklsl_M0();
1914 else
1915 gen_op_iwmmxt_unpacklul_M0();
1916 break;
1917 case 3:
1918 return 1;
1919 }
1920 gen_op_iwmmxt_movq_wRn_M0(wrd);
1921 gen_op_iwmmxt_set_mup();
1922 gen_op_iwmmxt_set_cup();
1923 break;
1924 case 0x00c: case 0x20c: case 0x40c: case 0x60c: /* WUNPCKEH */
1925 case 0x80c: case 0xa0c: case 0xc0c: case 0xe0c:
1926 wrd = (insn >> 12) & 0xf;
1927 rd0 = (insn >> 16) & 0xf;
1928 gen_op_iwmmxt_movq_M0_wRn(rd0);
1929 switch ((insn >> 22) & 3) {
1930 case 0:
1931 if (insn & (1 << 21))
1932 gen_op_iwmmxt_unpackhsb_M0();
1933 else
1934 gen_op_iwmmxt_unpackhub_M0();
1935 break;
1936 case 1:
1937 if (insn & (1 << 21))
1938 gen_op_iwmmxt_unpackhsw_M0();
1939 else
1940 gen_op_iwmmxt_unpackhuw_M0();
1941 break;
1942 case 2:
1943 if (insn & (1 << 21))
1944 gen_op_iwmmxt_unpackhsl_M0();
1945 else
1946 gen_op_iwmmxt_unpackhul_M0();
1947 break;
1948 case 3:
1949 return 1;
1950 }
1951 gen_op_iwmmxt_movq_wRn_M0(wrd);
1952 gen_op_iwmmxt_set_mup();
1953 gen_op_iwmmxt_set_cup();
1954 break;
1955 case 0x204: case 0x604: case 0xa04: case 0xe04: /* WSRL */
1956 case 0x214: case 0x614: case 0xa14: case 0xe14:
da6b5335
FN		 1957 if (((insn >> 22) & 3) == 0)
1958 return 1;
18c9b560
AZ		 1959 wrd = (insn >> 12) & 0xf;
1960 rd0 = (insn >> 16) & 0xf;
1961 gen_op_iwmmxt_movq_M0_wRn(rd0);
7d1b0095 1962 tmp = tcg_temp_new_i32();
da6b5335 1963 if (gen_iwmmxt_shift(insn, 0xff, tmp)) {
7d1b0095 1964 tcg_temp_free_i32(tmp);
18c9b560 1965 return 1;
da6b5335 1966 }
18c9b560 1967 switch ((insn >> 22) & 3) {
18c9b560 1968 case 1:
da6b5335 1969 gen_helper_iwmmxt_srlw(cpu_M0, cpu_env, cpu_M0, tmp);
18c9b560
AZ		 1970 break;
1971 case 2:
da6b5335 1972 gen_helper_iwmmxt_srll(cpu_M0, cpu_env, cpu_M0, tmp);
18c9b560
AZ		 1973 break;
1974 case 3:
da6b5335 1975 gen_helper_iwmmxt_srlq(cpu_M0, cpu_env, cpu_M0, tmp);
18c9b560
AZ		 1976 break;
1977 }
7d1b0095 1978 tcg_temp_free_i32(tmp);
18c9b560
AZ		 1979 gen_op_iwmmxt_movq_wRn_M0(wrd);
1980 gen_op_iwmmxt_set_mup();
1981 gen_op_iwmmxt_set_cup();
1982 break;
1983 case 0x004: case 0x404: case 0x804: case 0xc04: /* WSRA */
1984 case 0x014: case 0x414: case 0x814: case 0xc14:
da6b5335
FN		 1985 if (((insn >> 22) & 3) == 0)
1986 return 1;
18c9b560
AZ		 1987 wrd = (insn >> 12) & 0xf;
1988 rd0 = (insn >> 16) & 0xf;
1989 gen_op_iwmmxt_movq_M0_wRn(rd0);
7d1b0095 1990 tmp = tcg_temp_new_i32();
da6b5335 1991 if (gen_iwmmxt_shift(insn, 0xff, tmp)) {
7d1b0095 1992 tcg_temp_free_i32(tmp);
18c9b560 1993 return 1;
da6b5335 1994 }
18c9b560 1995 switch ((insn >> 22) & 3) {
18c9b560 1996 case 1:
da6b5335 1997 gen_helper_iwmmxt_sraw(cpu_M0, cpu_env, cpu_M0, tmp);
18c9b560
AZ		 1998 break;
1999 case 2:
da6b5335 2000 gen_helper_iwmmxt_sral(cpu_M0, cpu_env, cpu_M0, tmp);
18c9b560
AZ		 2001 break;
2002 case 3:
da6b5335 2003 gen_helper_iwmmxt_sraq(cpu_M0, cpu_env, cpu_M0, tmp);
18c9b560
AZ		 2004 break;
2005 }
7d1b0095 2006 tcg_temp_free_i32(tmp);
18c9b560
AZ		 2007 gen_op_iwmmxt_movq_wRn_M0(wrd);
2008 gen_op_iwmmxt_set_mup();
2009 gen_op_iwmmxt_set_cup();
2010 break;
2011 case 0x104: case 0x504: case 0x904: case 0xd04: /* WSLL */
2012 case 0x114: case 0x514: case 0x914: case 0xd14:
da6b5335
FN		 2013 if (((insn >> 22) & 3) == 0)
2014 return 1;
18c9b560
AZ		 2015 wrd = (insn >> 12) & 0xf;
2016 rd0 = (insn >> 16) & 0xf;
2017 gen_op_iwmmxt_movq_M0_wRn(rd0);
7d1b0095 2018 tmp = tcg_temp_new_i32();
da6b5335 2019 if (gen_iwmmxt_shift(insn, 0xff, tmp)) {
7d1b0095 2020 tcg_temp_free_i32(tmp);
18c9b560 2021 return 1;
da6b5335 2022 }
18c9b560 2023 switch ((insn >> 22) & 3) {
18c9b560 2024 case 1:
da6b5335 2025 gen_helper_iwmmxt_sllw(cpu_M0, cpu_env, cpu_M0, tmp);
18c9b560
AZ		 2026 break;
2027 case 2:
da6b5335 2028 gen_helper_iwmmxt_slll(cpu_M0, cpu_env, cpu_M0, tmp);
18c9b560
AZ		 2029 break;
2030 case 3:
da6b5335 2031 gen_helper_iwmmxt_sllq(cpu_M0, cpu_env, cpu_M0, tmp);
18c9b560
AZ		 2032 break;
2033 }
7d1b0095 2034 tcg_temp_free_i32(tmp);
18c9b560
AZ		 2035 gen_op_iwmmxt_movq_wRn_M0(wrd);
2036 gen_op_iwmmxt_set_mup();
2037 gen_op_iwmmxt_set_cup();
2038 break;
2039 case 0x304: case 0x704: case 0xb04: case 0xf04: /* WROR */
2040 case 0x314: case 0x714: case 0xb14: case 0xf14:
da6b5335
FN		 2041 if (((insn >> 22) & 3) == 0)
2042 return 1;
18c9b560
AZ		 2043 wrd = (insn >> 12) & 0xf;
2044 rd0 = (insn >> 16) & 0xf;
2045 gen_op_iwmmxt_movq_M0_wRn(rd0);
7d1b0095 2046 tmp = tcg_temp_new_i32();
18c9b560 2047 switch ((insn >> 22) & 3) {
18c9b560 2048 case 1:
da6b5335 2049 if (gen_iwmmxt_shift(insn, 0xf, tmp)) {
7d1b0095 2050 tcg_temp_free_i32(tmp);
18c9b560 2051 return 1;
da6b5335
FN		 2052 }
2053 gen_helper_iwmmxt_rorw(cpu_M0, cpu_env, cpu_M0, tmp);
18c9b560
AZ		 2054 break;
2055 case 2:
da6b5335 2056 if (gen_iwmmxt_shift(insn, 0x1f, tmp)) {
7d1b0095 2057 tcg_temp_free_i32(tmp);
18c9b560 2058 return 1;
da6b5335
FN		 2059 }
2060 gen_helper_iwmmxt_rorl(cpu_M0, cpu_env, cpu_M0, tmp);
18c9b560
AZ		 2061 break;
2062 case 3:
da6b5335 2063 if (gen_iwmmxt_shift(insn, 0x3f, tmp)) {
7d1b0095 2064 tcg_temp_free_i32(tmp);
18c9b560 2065 return 1;
da6b5335
FN		 2066 }
2067 gen_helper_iwmmxt_rorq(cpu_M0, cpu_env, cpu_M0, tmp);
18c9b560
AZ		 2068 break;
2069 }
7d1b0095 2070 tcg_temp_free_i32(tmp);
18c9b560
AZ		 2071 gen_op_iwmmxt_movq_wRn_M0(wrd);
2072 gen_op_iwmmxt_set_mup();
2073 gen_op_iwmmxt_set_cup();
2074 break;
2075 case 0x116: case 0x316: case 0x516: case 0x716: /* WMIN */
2076 case 0x916: case 0xb16: case 0xd16: case 0xf16:
2077 wrd = (insn >> 12) & 0xf;
2078 rd0 = (insn >> 16) & 0xf;
2079 rd1 = (insn >> 0) & 0xf;
2080 gen_op_iwmmxt_movq_M0_wRn(rd0);
2081 switch ((insn >> 22) & 3) {
2082 case 0:
2083 if (insn & (1 << 21))
2084 gen_op_iwmmxt_minsb_M0_wRn(rd1);
2085 else
2086 gen_op_iwmmxt_minub_M0_wRn(rd1);
2087 break;
2088 case 1:
2089 if (insn & (1 << 21))
2090 gen_op_iwmmxt_minsw_M0_wRn(rd1);
2091 else
2092 gen_op_iwmmxt_minuw_M0_wRn(rd1);
2093 break;
2094 case 2:
2095 if (insn & (1 << 21))
2096 gen_op_iwmmxt_minsl_M0_wRn(rd1);
2097 else
2098 gen_op_iwmmxt_minul_M0_wRn(rd1);
2099 break;
2100 case 3:
2101 return 1;
2102 }
2103 gen_op_iwmmxt_movq_wRn_M0(wrd);
2104 gen_op_iwmmxt_set_mup();
2105 break;
2106 case 0x016: case 0x216: case 0x416: case 0x616: /* WMAX */
2107 case 0x816: case 0xa16: case 0xc16: case 0xe16:
2108 wrd = (insn >> 12) & 0xf;
2109 rd0 = (insn >> 16) & 0xf;
2110 rd1 = (insn >> 0) & 0xf;
2111 gen_op_iwmmxt_movq_M0_wRn(rd0);
2112 switch ((insn >> 22) & 3) {
2113 case 0:
2114 if (insn & (1 << 21))
2115 gen_op_iwmmxt_maxsb_M0_wRn(rd1);
2116 else
2117 gen_op_iwmmxt_maxub_M0_wRn(rd1);
2118 break;
2119 case 1:
2120 if (insn & (1 << 21))
2121 gen_op_iwmmxt_maxsw_M0_wRn(rd1);
2122 else
2123 gen_op_iwmmxt_maxuw_M0_wRn(rd1);
2124 break;
2125 case 2:
2126 if (insn & (1 << 21))
2127 gen_op_iwmmxt_maxsl_M0_wRn(rd1);
2128 else
2129 gen_op_iwmmxt_maxul_M0_wRn(rd1);
2130 break;
2131 case 3:
2132 return 1;
2133 }
2134 gen_op_iwmmxt_movq_wRn_M0(wrd);
2135 gen_op_iwmmxt_set_mup();
2136 break;
2137 case 0x002: case 0x102: case 0x202: case 0x302: /* WALIGNI */
2138 case 0x402: case 0x502: case 0x602: case 0x702:
2139 wrd = (insn >> 12) & 0xf;
2140 rd0 = (insn >> 16) & 0xf;
2141 rd1 = (insn >> 0) & 0xf;
2142 gen_op_iwmmxt_movq_M0_wRn(rd0);
da6b5335
FN		 2143 tmp = tcg_const_i32((insn >> 20) & 3);
2144 iwmmxt_load_reg(cpu_V1, rd1);
2145 gen_helper_iwmmxt_align(cpu_M0, cpu_M0, cpu_V1, tmp);
2146 tcg_temp_free(tmp);
18c9b560
AZ		 2147 gen_op_iwmmxt_movq_wRn_M0(wrd);
2148 gen_op_iwmmxt_set_mup();
2149 break;
2150 case 0x01a: case 0x11a: case 0x21a: case 0x31a: /* WSUB */
2151 case 0x41a: case 0x51a: case 0x61a: case 0x71a:
2152 case 0x81a: case 0x91a: case 0xa1a: case 0xb1a:
2153 case 0xc1a: case 0xd1a: case 0xe1a: case 0xf1a:
2154 wrd = (insn >> 12) & 0xf;
2155 rd0 = (insn >> 16) & 0xf;
2156 rd1 = (insn >> 0) & 0xf;
2157 gen_op_iwmmxt_movq_M0_wRn(rd0);
2158 switch ((insn >> 20) & 0xf) {
2159 case 0x0:
2160 gen_op_iwmmxt_subnb_M0_wRn(rd1);
2161 break;
2162 case 0x1:
2163 gen_op_iwmmxt_subub_M0_wRn(rd1);
2164 break;
2165 case 0x3:
2166 gen_op_iwmmxt_subsb_M0_wRn(rd1);
2167 break;
2168 case 0x4:
2169 gen_op_iwmmxt_subnw_M0_wRn(rd1);
2170 break;
2171 case 0x5:
2172 gen_op_iwmmxt_subuw_M0_wRn(rd1);
2173 break;
2174 case 0x7:
2175 gen_op_iwmmxt_subsw_M0_wRn(rd1);
2176 break;
2177 case 0x8:
2178 gen_op_iwmmxt_subnl_M0_wRn(rd1);
2179 break;
2180 case 0x9:
2181 gen_op_iwmmxt_subul_M0_wRn(rd1);
2182 break;
2183 case 0xb:
2184 gen_op_iwmmxt_subsl_M0_wRn(rd1);
2185 break;
2186 default:
2187 return 1;
2188 }
2189 gen_op_iwmmxt_movq_wRn_M0(wrd);
2190 gen_op_iwmmxt_set_mup();
2191 gen_op_iwmmxt_set_cup();
2192 break;
2193 case 0x01e: case 0x11e: case 0x21e: case 0x31e: /* WSHUFH */
2194 case 0x41e: case 0x51e: case 0x61e: case 0x71e:
2195 case 0x81e: case 0x91e: case 0xa1e: case 0xb1e:
2196 case 0xc1e: case 0xd1e: case 0xe1e: case 0xf1e:
2197 wrd = (insn >> 12) & 0xf;
2198 rd0 = (insn >> 16) & 0xf;
2199 gen_op_iwmmxt_movq_M0_wRn(rd0);
da6b5335
FN		 2200 tmp = tcg_const_i32(((insn >> 16) & 0xf0) | (insn & 0x0f));
2201 gen_helper_iwmmxt_shufh(cpu_M0, cpu_env, cpu_M0, tmp);
2202 tcg_temp_free(tmp);
18c9b560
AZ		 2203 gen_op_iwmmxt_movq_wRn_M0(wrd);
2204 gen_op_iwmmxt_set_mup();
2205 gen_op_iwmmxt_set_cup();
2206 break;
2207 case 0x018: case 0x118: case 0x218: case 0x318: /* WADD */
2208 case 0x418: case 0x518: case 0x618: case 0x718:
2209 case 0x818: case 0x918: case 0xa18: case 0xb18:
2210 case 0xc18: case 0xd18: case 0xe18: case 0xf18:
2211 wrd = (insn >> 12) & 0xf;
2212 rd0 = (insn >> 16) & 0xf;
2213 rd1 = (insn >> 0) & 0xf;
2214 gen_op_iwmmxt_movq_M0_wRn(rd0);
2215 switch ((insn >> 20) & 0xf) {
2216 case 0x0:
2217 gen_op_iwmmxt_addnb_M0_wRn(rd1);
2218 break;
2219 case 0x1:
2220 gen_op_iwmmxt_addub_M0_wRn(rd1);
2221 break;
2222 case 0x3:
2223 gen_op_iwmmxt_addsb_M0_wRn(rd1);
2224 break;
2225 case 0x4:
2226 gen_op_iwmmxt_addnw_M0_wRn(rd1);
2227 break;
2228 case 0x5:
2229 gen_op_iwmmxt_adduw_M0_wRn(rd1);
2230 break;
2231 case 0x7:
2232 gen_op_iwmmxt_addsw_M0_wRn(rd1);
2233 break;
2234 case 0x8:
2235 gen_op_iwmmxt_addnl_M0_wRn(rd1);
2236 break;
2237 case 0x9:
2238 gen_op_iwmmxt_addul_M0_wRn(rd1);
2239 break;
2240 case 0xb:
2241 gen_op_iwmmxt_addsl_M0_wRn(rd1);
2242 break;
2243 default:
2244 return 1;
2245 }
2246 gen_op_iwmmxt_movq_wRn_M0(wrd);
2247 gen_op_iwmmxt_set_mup();
2248 gen_op_iwmmxt_set_cup();
2249 break;
2250 case 0x008: case 0x108: case 0x208: case 0x308: /* WPACK */
2251 case 0x408: case 0x508: case 0x608: case 0x708:
2252 case 0x808: case 0x908: case 0xa08: case 0xb08:
2253 case 0xc08: case 0xd08: case 0xe08: case 0xf08:
da6b5335
FN		 2254 if (!(insn & (1 << 20)) || ((insn >> 22) & 3) == 0)
2255 return 1;
18c9b560
AZ		 2256 wrd = (insn >> 12) & 0xf;
2257 rd0 = (insn >> 16) & 0xf;
2258 rd1 = (insn >> 0) & 0xf;
2259 gen_op_iwmmxt_movq_M0_wRn(rd0);
18c9b560 2260 switch ((insn >> 22) & 3) {
18c9b560
AZ		 2261 case 1:
2262 if (insn & (1 << 21))
2263 gen_op_iwmmxt_packsw_M0_wRn(rd1);
2264 else
2265 gen_op_iwmmxt_packuw_M0_wRn(rd1);
2266 break;
2267 case 2:
2268 if (insn & (1 << 21))
2269 gen_op_iwmmxt_packsl_M0_wRn(rd1);
2270 else
2271 gen_op_iwmmxt_packul_M0_wRn(rd1);
2272 break;
2273 case 3:
2274 if (insn & (1 << 21))
2275 gen_op_iwmmxt_packsq_M0_wRn(rd1);
2276 else
2277 gen_op_iwmmxt_packuq_M0_wRn(rd1);
2278 break;
2279 }
2280 gen_op_iwmmxt_movq_wRn_M0(wrd);
2281 gen_op_iwmmxt_set_mup();
2282 gen_op_iwmmxt_set_cup();
2283 break;
2284 case 0x201: case 0x203: case 0x205: case 0x207:
2285 case 0x209: case 0x20b: case 0x20d: case 0x20f:
2286 case 0x211: case 0x213: case 0x215: case 0x217:
2287 case 0x219: case 0x21b: case 0x21d: case 0x21f:
2288 wrd = (insn >> 5) & 0xf;
2289 rd0 = (insn >> 12) & 0xf;
2290 rd1 = (insn >> 0) & 0xf;
2291 if (rd0 == 0xf || rd1 == 0xf)
2292 return 1;
2293 gen_op_iwmmxt_movq_M0_wRn(wrd);
da6b5335
FN		 2294 tmp = load_reg(s, rd0);
2295 tmp2 = load_reg(s, rd1);
18c9b560
AZ		 2296 switch ((insn >> 16) & 0xf) {
2297 case 0x0: /* TMIA */
da6b5335 2298 gen_helper_iwmmxt_muladdsl(cpu_M0, cpu_M0, tmp, tmp2);
18c9b560
AZ		 2299 break;
2300 case 0x8: /* TMIAPH */
da6b5335 2301 gen_helper_iwmmxt_muladdsw(cpu_M0, cpu_M0, tmp, tmp2);
18c9b560
AZ		 2302 break;
2303 case 0xc: case 0xd: case 0xe: case 0xf: /* TMIAxy */
18c9b560 2304 if (insn & (1 << 16))
da6b5335 2305 tcg_gen_shri_i32(tmp, tmp, 16);
18c9b560 2306 if (insn & (1 << 17))
da6b5335
FN		 2307 tcg_gen_shri_i32(tmp2, tmp2, 16);
2308 gen_helper_iwmmxt_muladdswl(cpu_M0, cpu_M0, tmp, tmp2);
18c9b560
AZ		 2309 break;
2310 default:
7d1b0095
PM		 2311 tcg_temp_free_i32(tmp2);
2312 tcg_temp_free_i32(tmp);
18c9b560
AZ		 2313 return 1;
2314 }
7d1b0095
PM		 2315 tcg_temp_free_i32(tmp2);
2316 tcg_temp_free_i32(tmp);
18c9b560
AZ		 2317 gen_op_iwmmxt_movq_wRn_M0(wrd);
2318 gen_op_iwmmxt_set_mup();
2319 break;
2320 default:
2321 return 1;
2322 }
2323
2324 return 0;
2325}
2326
2327/* Disassemble an XScale DSP instruction. Returns nonzero if an error occured
2328 (ie. an undefined instruction). */
2329static int disas_dsp_insn(CPUState *env, DisasContext *s, uint32_t insn)
2330{
2331 int acc, rd0, rd1, rdhi, rdlo;
3a554c0f 2332 TCGv tmp, tmp2;
18c9b560
AZ		 2333
2334 if ((insn & 0x0ff00f10) == 0x0e200010) {
2335 /* Multiply with Internal Accumulate Format */
2336 rd0 = (insn >> 12) & 0xf;
2337 rd1 = insn & 0xf;
2338 acc = (insn >> 5) & 7;
2339
2340 if (acc != 0)
2341 return 1;
2342
3a554c0f
FN		 2343 tmp = load_reg(s, rd0);
2344 tmp2 = load_reg(s, rd1);
18c9b560
AZ		 2345 switch ((insn >> 16) & 0xf) {
2346 case 0x0: /* MIA */
3a554c0f 2347 gen_helper_iwmmxt_muladdsl(cpu_M0, cpu_M0, tmp, tmp2);
18c9b560
AZ		 2348 break;
2349 case 0x8: /* MIAPH */
3a554c0f 2350 gen_helper_iwmmxt_muladdsw(cpu_M0, cpu_M0, tmp, tmp2);
18c9b560
AZ		 2351 break;
2352 case 0xc: /* MIABB */
2353 case 0xd: /* MIABT */
2354 case 0xe: /* MIATB */
2355 case 0xf: /* MIATT */
18c9b560 2356 if (insn & (1 << 16))
3a554c0f 2357 tcg_gen_shri_i32(tmp, tmp, 16);
18c9b560 2358 if (insn & (1 << 17))
3a554c0f
FN		 2359 tcg_gen_shri_i32(tmp2, tmp2, 16);
2360 gen_helper_iwmmxt_muladdswl(cpu_M0, cpu_M0, tmp, tmp2);
18c9b560
AZ		 2361 break;
2362 default:
2363 return 1;
2364 }
7d1b0095
PM		 2365 tcg_temp_free_i32(tmp2);
2366 tcg_temp_free_i32(tmp);
18c9b560
AZ		 2367
2368 gen_op_iwmmxt_movq_wRn_M0(acc);
2369 return 0;
2370 }
2371
2372 if ((insn & 0x0fe00ff8) == 0x0c400000) {
2373 /* Internal Accumulator Access Format */
2374 rdhi = (insn >> 16) & 0xf;
2375 rdlo = (insn >> 12) & 0xf;
2376 acc = insn & 7;
2377
2378 if (acc != 0)
2379 return 1;
2380
2381 if (insn & ARM_CP_RW_BIT) { /* MRA */
3a554c0f
FN		 2382 iwmmxt_load_reg(cpu_V0, acc);
2383 tcg_gen_trunc_i64_i32(cpu_R[rdlo], cpu_V0);
2384 tcg_gen_shri_i64(cpu_V0, cpu_V0, 32);
2385 tcg_gen_trunc_i64_i32(cpu_R[rdhi], cpu_V0);
2386 tcg_gen_andi_i32(cpu_R[rdhi], cpu_R[rdhi], (1 << (40 - 32)) - 1);
18c9b560 2387 } else { /* MAR */
3a554c0f
FN		 2388 tcg_gen_concat_i32_i64(cpu_V0, cpu_R[rdlo], cpu_R[rdhi]);
2389 iwmmxt_store_reg(cpu_V0, acc);
18c9b560
AZ		 2390 }
2391 return 0;
2392 }
2393
2394 return 1;
2395}
2396
c1713132
AZ		 2397/* Disassemble system coprocessor instruction. Return nonzero if
2398 instruction is not defined. */
2399static int disas_cp_insn(CPUState *env, DisasContext *s, uint32_t insn)
2400{
b75263d6 2401 TCGv tmp, tmp2;
c1713132
AZ		 2402 uint32_t rd = (insn >> 12) & 0xf;
2403 uint32_t cp = (insn >> 8) & 0xf;
2404 if (IS_USER(s)) {
2405 return 1;
2406 }
2407
18c9b560 2408 if (insn & ARM_CP_RW_BIT) {
c1713132
AZ		 2409 if (!env->cp[cp].cp_read)
2410 return 1;
8984bd2e 2411 gen_set_pc_im(s->pc);
7d1b0095 2412 tmp = tcg_temp_new_i32();
b75263d6
JR		 2413 tmp2 = tcg_const_i32(insn);
2414 gen_helper_get_cp(tmp, cpu_env, tmp2);
2415 tcg_temp_free(tmp2);
8984bd2e 2416 store_reg(s, rd, tmp);
c1713132
AZ		 2417 } else {
2418 if (!env->cp[cp].cp_write)
2419 return 1;
8984bd2e
PB		 2420 gen_set_pc_im(s->pc);
2421 tmp = load_reg(s, rd);
b75263d6
JR		 2422 tmp2 = tcg_const_i32(insn);
2423 gen_helper_set_cp(cpu_env, tmp2, tmp);
2424 tcg_temp_free(tmp2);
7d1b0095 2425 tcg_temp_free_i32(tmp);
c1713132
AZ		 2426 }
2427 return 0;
2428}
2429
9ee6e8bb
PB		 2430static int cp15_user_ok(uint32_t insn)
2431{
2432 int cpn = (insn >> 16) & 0xf;
2433 int cpm = insn & 0xf;
2434 int op = ((insn >> 5) & 7) | ((insn >> 18) & 0x38);
2435
2436 if (cpn == 13 && cpm == 0) {
2437 /* TLS register. */
2438 if (op == 2 || (op == 3 && (insn & ARM_CP_RW_BIT)))
2439 return 1;
2440 }
2441 if (cpn == 7) {
2442 /* ISB, DSB, DMB. */
2443 if ((cpm == 5 && op == 4)
2444 || (cpm == 10 && (op == 4 || op == 5)))
2445 return 1;
2446 }
2447 return 0;
2448}
2449
3f26c122
RV		 2450static int cp15_tls_load_store(CPUState *env, DisasContext *s, uint32_t insn, uint32_t rd)
2451{
2452 TCGv tmp;
2453 int cpn = (insn >> 16) & 0xf;
2454 int cpm = insn & 0xf;
2455 int op = ((insn >> 5) & 7) | ((insn >> 18) & 0x38);
2456
2457 if (!arm_feature(env, ARM_FEATURE_V6K))
2458 return 0;
2459
2460 if (!(cpn == 13 && cpm == 0))
2461 return 0;
2462
2463 if (insn & ARM_CP_RW_BIT) {
3f26c122
RV		 2464 switch (op) {
2465 case 2:
c5883be2 2466 tmp = load_cpu_field(cp15.c13_tls1);
3f26c122
RV		 2467 break;
2468 case 3:
c5883be2 2469 tmp = load_cpu_field(cp15.c13_tls2);
3f26c122
RV		 2470 break;
2471 case 4:
c5883be2 2472 tmp = load_cpu_field(cp15.c13_tls3);
3f26c122
RV		 2473 break;
2474 default:
3f26c122
RV		 2475 return 0;
2476 }
2477 store_reg(s, rd, tmp);
2478
2479 } else {
2480 tmp = load_reg(s, rd);
2481 switch (op) {
2482 case 2:
c5883be2 2483 store_cpu_field(tmp, cp15.c13_tls1);
3f26c122
RV		 2484 break;
2485 case 3:
c5883be2 2486 store_cpu_field(tmp, cp15.c13_tls2);
3f26c122
RV		 2487 break;
2488 case 4:
c5883be2 2489 store_cpu_field(tmp, cp15.c13_tls3);
3f26c122
RV		 2490 break;
2491 default:
7d1b0095 2492 tcg_temp_free_i32(tmp);
3f26c122
RV		 2493 return 0;
2494 }
3f26c122
RV		 2495 }
2496 return 1;
2497}
2498
b5ff1b31
FB		 2499/* Disassemble system coprocessor (cp15) instruction. Return nonzero if
2500 instruction is not defined. */
a90b7318 2501static int disas_cp15_insn(CPUState *env, DisasContext *s, uint32_t insn)
b5ff1b31
FB		 2502{
2503 uint32_t rd;
b75263d6 2504 TCGv tmp, tmp2;
b5ff1b31 2505
9ee6e8bb
PB		 2506 /* M profile cores use memory mapped registers instead of cp15. */
2507 if (arm_feature(env, ARM_FEATURE_M))
2508 return 1;
2509
2510 if ((insn & (1 << 25)) == 0) {
2511 if (insn & (1 << 20)) {
2512 /* mrrc */
2513 return 1;
2514 }
2515 /* mcrr. Used for block cache operations, so implement as no-op. */
2516 return 0;
2517 }
2518 if ((insn & (1 << 4)) == 0) {
2519 /* cdp */
2520 return 1;
2521 }
2522 if (IS_USER(s) && !cp15_user_ok(insn)) {
b5ff1b31
FB		 2523 return 1;
2524 }
cc688901
PM		 2525
2526 /* Pre-v7 versions of the architecture implemented WFI via coprocessor
2527 * instructions rather than a separate instruction.
2528 */
2529 if ((insn & 0x0fff0fff) == 0x0e070f90) {
2530 /* 0,c7,c0,4: Standard v6 WFI (also used in some pre-v6 cores).
2531 * In v7, this must NOP.
2532 */
2533 if (!arm_feature(env, ARM_FEATURE_V7)) {
2534 /* Wait for interrupt. */
2535 gen_set_pc_im(s->pc);
2536 s->is_jmp = DISAS_WFI;
2537 }
9332f9da
FB		 2538 return 0;
2539 }
cc688901
PM		 2540
2541 if ((insn & 0x0fff0fff) == 0x0e070f58) {
2542 /* 0,c7,c8,2: Not all pre-v6 cores implemented this WFI,
2543 * so this is slightly over-broad.
2544 */
2545 if (!arm_feature(env, ARM_FEATURE_V6)) {
2546 /* Wait for interrupt. */
2547 gen_set_pc_im(s->pc);
2548 s->is_jmp = DISAS_WFI;
2549 return 0;
2550 }
2551 /* Otherwise fall through to handle via helper function.
2552 * In particular, on v7 and some v6 cores this is one of
2553 * the VA-PA registers.
2554 */
2555 }
2556
b5ff1b31 2557 rd = (insn >> 12) & 0xf;
3f26c122
RV		 2558
2559 if (cp15_tls_load_store(env, s, insn, rd))
2560 return 0;
2561
b75263d6 2562 tmp2 = tcg_const_i32(insn);
18c9b560 2563 if (insn & ARM_CP_RW_BIT) {
7d1b0095 2564 tmp = tcg_temp_new_i32();
b75263d6 2565 gen_helper_get_cp15(tmp, cpu_env, tmp2);
b5ff1b31
FB		 2566 /* If the destination register is r15 then sets condition codes. */
2567 if (rd != 15)
8984bd2e
PB		 2568 store_reg(s, rd, tmp);
2569 else
7d1b0095 2570 tcg_temp_free_i32(tmp);
b5ff1b31 2571 } else {
8984bd2e 2572 tmp = load_reg(s, rd);
b75263d6 2573 gen_helper_set_cp15(cpu_env, tmp2, tmp);
7d1b0095 2574 tcg_temp_free_i32(tmp);
a90b7318
AZ		 2575 /* Normally we would always end the TB here, but Linux
2576 * arch/arm/mach-pxa/sleep.S expects two instructions following
2577 * an MMU enable to execute from cache. Imitate this behaviour. */
2578 if (!arm_feature(env, ARM_FEATURE_XSCALE) ||
2579 (insn & 0x0fff0fff) != 0x0e010f10)
2580 gen_lookup_tb(s);
b5ff1b31 2581 }
b75263d6 2582 tcg_temp_free_i32(tmp2);
b5ff1b31
FB		 2583 return 0;
2584}
2585
9ee6e8bb
PB		 2586#define VFP_REG_SHR(x, n) (((n) > 0) ? (x) >> (n) : (x) << -(n))
2587#define VFP_SREG(insn, bigbit, smallbit) \
2588 ((VFP_REG_SHR(insn, bigbit - 1) & 0x1e) | (((insn) >> (smallbit)) & 1))
2589#define VFP_DREG(reg, insn, bigbit, smallbit) do { \
2590 if (arm_feature(env, ARM_FEATURE_VFP3)) { \
2591 reg = (((insn) >> (bigbit)) & 0x0f) \
2592 | (((insn) >> ((smallbit) - 4)) & 0x10); \
2593 } else { \
2594 if (insn & (1 << (smallbit))) \
2595 return 1; \
2596 reg = ((insn) >> (bigbit)) & 0x0f; \
2597 }} while (0)
2598
2599#define VFP_SREG_D(insn) VFP_SREG(insn, 12, 22)
2600#define VFP_DREG_D(reg, insn) VFP_DREG(reg, insn, 12, 22)
2601#define VFP_SREG_N(insn) VFP_SREG(insn, 16, 7)
2602#define VFP_DREG_N(reg, insn) VFP_DREG(reg, insn, 16, 7)
2603#define VFP_SREG_M(insn) VFP_SREG(insn, 0, 5)
2604#define VFP_DREG_M(reg, insn) VFP_DREG(reg, insn, 0, 5)
2605
4373f3ce
PB		 2606/* Move between integer and VFP cores. */
2607static TCGv gen_vfp_mrs(void)
2608{
7d1b0095 2609 TCGv tmp = tcg_temp_new_i32();
4373f3ce
PB		 2610 tcg_gen_mov_i32(tmp, cpu_F0s);
2611 return tmp;
2612}
2613
2614static void gen_vfp_msr(TCGv tmp)
2615{
2616 tcg_gen_mov_i32(cpu_F0s, tmp);
7d1b0095 2617 tcg_temp_free_i32(tmp);
4373f3ce
PB		 2618}
2619
ad69471c
PB		 2620static void gen_neon_dup_u8(TCGv var, int shift)
2621{
7d1b0095 2622 TCGv tmp = tcg_temp_new_i32();
ad69471c
PB		 2623 if (shift)
2624 tcg_gen_shri_i32(var, var, shift);
86831435 2625 tcg_gen_ext8u_i32(var, var);
ad69471c
PB		 2626 tcg_gen_shli_i32(tmp, var, 8);
2627 tcg_gen_or_i32(var, var, tmp);
2628 tcg_gen_shli_i32(tmp, var, 16);
2629 tcg_gen_or_i32(var, var, tmp);
7d1b0095 2630 tcg_temp_free_i32(tmp);
ad69471c
PB		 2631}
2632
2633static void gen_neon_dup_low16(TCGv var)
2634{
7d1b0095 2635 TCGv tmp = tcg_temp_new_i32();
86831435 2636 tcg_gen_ext16u_i32(var, var);
ad69471c
PB		 2637 tcg_gen_shli_i32(tmp, var, 16);
2638 tcg_gen_or_i32(var, var, tmp);
7d1b0095 2639 tcg_temp_free_i32(tmp);
ad69471c
PB		 2640}
2641
2642static void gen_neon_dup_high16(TCGv var)
2643{
7d1b0095 2644 TCGv tmp = tcg_temp_new_i32();
ad69471c
PB		 2645 tcg_gen_andi_i32(var, var, 0xffff0000);
2646 tcg_gen_shri_i32(tmp, var, 16);
2647 tcg_gen_or_i32(var, var, tmp);
7d1b0095 2648 tcg_temp_free_i32(tmp);
ad69471c
PB		 2649}
2650
b7bcbe95
FB		 2651/* Disassemble a VFP instruction. Returns nonzero if an error occured
2652 (ie. an undefined instruction). */
2653static int disas_vfp_insn(CPUState * env, DisasContext *s, uint32_t insn)
2654{
2655 uint32_t rd, rn, rm, op, i, n, offset, delta_d, delta_m, bank_mask;
2656 int dp, veclen;
312eea9f 2657 TCGv addr;
4373f3ce 2658 TCGv tmp;
ad69471c 2659 TCGv tmp2;
b7bcbe95 2660
40f137e1
PB		 2661 if (!arm_feature(env, ARM_FEATURE_VFP))
2662 return 1;
2663
5df8bac1 2664 if (!s->vfp_enabled) {
9ee6e8bb 2665 /* VFP disabled. Only allow fmxr/fmrx to/from some control regs. */
40f137e1
PB		 2666 if ((insn & 0x0fe00fff) != 0x0ee00a10)
2667 return 1;
2668 rn = (insn >> 16) & 0xf;
9ee6e8bb
PB		 2669 if (rn != ARM_VFP_FPSID && rn != ARM_VFP_FPEXC
2670 && rn != ARM_VFP_MVFR1 && rn != ARM_VFP_MVFR0)
40f137e1
PB		 2671 return 1;
2672 }
b7bcbe95
FB		 2673 dp = ((insn & 0xf00) == 0xb00);
2674 switch ((insn >> 24) & 0xf) {
2675 case 0xe:
2676 if (insn & (1 << 4)) {
2677 /* single register transfer */
b7bcbe95
FB		 2678 rd = (insn >> 12) & 0xf;
2679 if (dp) {
9ee6e8bb
PB		 2680 int size;
2681 int pass;
2682
2683 VFP_DREG_N(rn, insn);
2684 if (insn & 0xf)
b7bcbe95 2685 return 1;
9ee6e8bb
PB		 2686 if (insn & 0x00c00060
2687 && !arm_feature(env, ARM_FEATURE_NEON))
2688 return 1;
2689
2690 pass = (insn >> 21) & 1;
2691 if (insn & (1 << 22)) {
2692 size = 0;
2693 offset = ((insn >> 5) & 3) * 8;
2694 } else if (insn & (1 << 5)) {
2695 size = 1;
2696 offset = (insn & (1 << 6)) ? 16 : 0;
2697 } else {
2698 size = 2;
2699 offset = 0;
2700 }
18c9b560 2701 if (insn & ARM_CP_RW_BIT) {
b7bcbe95 2702 /* vfp->arm */
ad69471c 2703 tmp = neon_load_reg(rn, pass);
9ee6e8bb
PB		 2704 switch (size) {
2705 case 0:
9ee6e8bb 2706 if (offset)
ad69471c 2707 tcg_gen_shri_i32(tmp, tmp, offset);
9ee6e8bb 2708 if (insn & (1 << 23))
ad69471c 2709 gen_uxtb(tmp);
9ee6e8bb 2710 else
ad69471c 2711 gen_sxtb(tmp);
9ee6e8bb
PB		 2712 break;
2713 case 1:
9ee6e8bb
PB		 2714 if (insn & (1 << 23)) {
2715 if (offset) {
ad69471c 2716 tcg_gen_shri_i32(tmp, tmp, 16);
9ee6e8bb 2717 } else {
ad69471c 2718 gen_uxth(tmp);
9ee6e8bb
PB		 2719 }
2720 } else {
2721 if (offset) {
ad69471c 2722 tcg_gen_sari_i32(tmp, tmp, 16);
9ee6e8bb 2723 } else {
ad69471c 2724 gen_sxth(tmp);
9ee6e8bb
PB		 2725 }
2726 }
2727 break;
2728 case 2:
9ee6e8bb
PB		 2729 break;
2730 }
ad69471c 2731 store_reg(s, rd, tmp);
b7bcbe95
FB		 2732 } else {
2733 /* arm->vfp */
ad69471c 2734 tmp = load_reg(s, rd);
9ee6e8bb
PB		 2735 if (insn & (1 << 23)) {
2736 /* VDUP */
2737 if (size == 0) {
ad69471c 2738 gen_neon_dup_u8(tmp, 0);
9ee6e8bb 2739 } else if (size == 1) {
ad69471c 2740 gen_neon_dup_low16(tmp);
9ee6e8bb 2741 }
cbbccffc 2742 for (n = 0; n <= pass * 2; n++) {
7d1b0095 2743 tmp2 = tcg_temp_new_i32();
cbbccffc
PB		 2744 tcg_gen_mov_i32(tmp2, tmp);
2745 neon_store_reg(rn, n, tmp2);
2746 }
2747 neon_store_reg(rn, n, tmp);
9ee6e8bb
PB		 2748 } else {
2749 /* VMOV */
2750 switch (size) {
2751 case 0:
ad69471c
PB		 2752 tmp2 = neon_load_reg(rn, pass);
2753 gen_bfi(tmp, tmp2, tmp, offset, 0xff);
7d1b0095 2754 tcg_temp_free_i32(tmp2);
9ee6e8bb
PB		 2755 break;
2756 case 1:
ad69471c
PB		 2757 tmp2 = neon_load_reg(rn, pass);
2758 gen_bfi(tmp, tmp2, tmp, offset, 0xffff);
7d1b0095 2759 tcg_temp_free_i32(tmp2);
9ee6e8bb
PB		 2760 break;
2761 case 2:
9ee6e8bb
PB		 2762 break;
2763 }
ad69471c 2764 neon_store_reg(rn, pass, tmp);
9ee6e8bb 2765 }
b7bcbe95 2766 }
9ee6e8bb
PB		 2767 } else { /* !dp */
2768 if ((insn & 0x6f) != 0x00)
2769 return 1;
2770 rn = VFP_SREG_N(insn);
18c9b560 2771 if (insn & ARM_CP_RW_BIT) {
b7bcbe95
FB		 2772 /* vfp->arm */
2773 if (insn & (1 << 21)) {
2774 /* system register */
40f137e1 2775 rn >>= 1;
9ee6e8bb 2776
b7bcbe95 2777 switch (rn) {
40f137e1 2778 case ARM_VFP_FPSID:
4373f3ce 2779 /* VFP2 allows access to FSID from userspace.
9ee6e8bb
PB		 2780 VFP3 restricts all id registers to privileged
2781 accesses. */
2782 if (IS_USER(s)
2783 && arm_feature(env, ARM_FEATURE_VFP3))
2784 return 1;
4373f3ce 2785 tmp = load_cpu_field(vfp.xregs[rn]);
9ee6e8bb 2786 break;
40f137e1 2787 case ARM_VFP_FPEXC:
9ee6e8bb
PB		 2788 if (IS_USER(s))
2789 return 1;
4373f3ce 2790 tmp = load_cpu_field(vfp.xregs[rn]);
9ee6e8bb 2791 break;
40f137e1
PB		 2792 case ARM_VFP_FPINST:
2793 case ARM_VFP_FPINST2:
9ee6e8bb
PB		 2794 /* Not present in VFP3. */
2795 if (IS_USER(s)
2796 || arm_feature(env, ARM_FEATURE_VFP3))
2797 return 1;
4373f3ce 2798 tmp = load_cpu_field(vfp.xregs[rn]);
b7bcbe95 2799 break;
40f137e1 2800 case ARM_VFP_FPSCR:
601d70b9 2801 if (rd == 15) {
4373f3ce
PB		 2802 tmp = load_cpu_field(vfp.xregs[ARM_VFP_FPSCR]);
2803 tcg_gen_andi_i32(tmp, tmp, 0xf0000000);
2804 } else {
7d1b0095 2805 tmp = tcg_temp_new_i32();
4373f3ce
PB		 2806 gen_helper_vfp_get_fpscr(tmp, cpu_env);
2807 }
b7bcbe95 2808 break;
9ee6e8bb
PB		 2809 case ARM_VFP_MVFR0:
2810 case ARM_VFP_MVFR1:
2811 if (IS_USER(s)
2812 || !arm_feature(env, ARM_FEATURE_VFP3))
2813 return 1;
4373f3ce 2814 tmp = load_cpu_field(vfp.xregs[rn]);
9ee6e8bb 2815 break;
b7bcbe95
FB		 2816 default:
2817 return 1;
2818 }
2819 } else {
2820 gen_mov_F0_vreg(0, rn);
4373f3ce 2821 tmp = gen_vfp_mrs();
b7bcbe95
FB		 2822 }
2823 if (rd == 15) {
b5ff1b31 2824 /* Set the 4 flag bits in the CPSR. */
4373f3ce 2825 gen_set_nzcv(tmp);
7d1b0095 2826 tcg_temp_free_i32(tmp);
4373f3ce
PB		 2827 } else {
2828 store_reg(s, rd, tmp);
2829 }
b7bcbe95
FB		 2830 } else {
2831 /* arm->vfp */
4373f3ce 2832 tmp = load_reg(s, rd);
b7bcbe95 2833 if (insn & (1 << 21)) {
40f137e1 2834 rn >>= 1;
b7bcbe95
FB		 2835 /* system register */
2836 switch (rn) {
40f137e1 2837 case ARM_VFP_FPSID:
9ee6e8bb
PB		 2838 case ARM_VFP_MVFR0:
2839 case ARM_VFP_MVFR1:
b7bcbe95
FB		 2840 /* Writes are ignored. */
2841 break;
40f137e1 2842 case ARM_VFP_FPSCR:
4373f3ce 2843 gen_helper_vfp_set_fpscr(cpu_env, tmp);
7d1b0095 2844 tcg_temp_free_i32(tmp);
b5ff1b31 2845 gen_lookup_tb(s);
b7bcbe95 2846 break;
40f137e1 2847 case ARM_VFP_FPEXC:
9ee6e8bb
PB		 2848 if (IS_USER(s))
2849 return 1;
71b3c3de
JR		 2850 /* TODO: VFP subarchitecture support.
2851 * For now, keep the EN bit only */
2852 tcg_gen_andi_i32(tmp, tmp, 1 << 30);
4373f3ce 2853 store_cpu_field(tmp, vfp.xregs[rn]);
40f137e1
PB		 2854 gen_lookup_tb(s);
2855 break;
2856 case ARM_VFP_FPINST:
2857 case ARM_VFP_FPINST2:
4373f3ce 2858 store_cpu_field(tmp, vfp.xregs[rn]);
40f137e1 2859 break;
b7bcbe95
FB		 2860 default:
2861 return 1;
2862 }
2863 } else {
4373f3ce 2864 gen_vfp_msr(tmp);
b7bcbe95
FB		 2865 gen_mov_vreg_F0(0, rn);
2866 }
2867 }
2868 }
2869 } else {
2870 /* data processing */
2871 /* The opcode is in bits 23, 21, 20 and 6. */
2872 op = ((insn >> 20) & 8) | ((insn >> 19) & 6) | ((insn >> 6) & 1);
2873 if (dp) {
2874 if (op == 15) {
2875 /* rn is opcode */
2876 rn = ((insn >> 15) & 0x1e) | ((insn >> 7) & 1);
2877 } else {
2878 /* rn is register number */
9ee6e8bb 2879 VFP_DREG_N(rn, insn);
b7bcbe95
FB		 2880 }
2881
04595bf6 2882 if (op == 15 && (rn == 15 || ((rn & 0x1c) == 0x18))) {
b7bcbe95 2883 /* Integer or single precision destination. */
9ee6e8bb 2884 rd = VFP_SREG_D(insn);
b7bcbe95 2885 } else {
9ee6e8bb 2886 VFP_DREG_D(rd, insn);
b7bcbe95 2887 }
04595bf6
PM		 2888 if (op == 15 &&
2889 (((rn & 0x1c) == 0x10) || ((rn & 0x14) == 0x14))) {
2890 /* VCVT from int is always from S reg regardless of dp bit.
2891 * VCVT with immediate frac_bits has same format as SREG_M
2892 */
2893 rm = VFP_SREG_M(insn);
b7bcbe95 2894 } else {
9ee6e8bb 2895 VFP_DREG_M(rm, insn);
b7bcbe95
FB		 2896 }
2897 } else {
9ee6e8bb 2898 rn = VFP_SREG_N(insn);
b7bcbe95
FB		 2899 if (op == 15 && rn == 15) {
2900 /* Double precision destination. */
9ee6e8bb
PB		 2901 VFP_DREG_D(rd, insn);
2902 } else {
2903 rd = VFP_SREG_D(insn);
2904 }
04595bf6
PM		 2905 /* NB that we implicitly rely on the encoding for the frac_bits
2906 * in VCVT of fixed to float being the same as that of an SREG_M
2907 */
9ee6e8bb 2908 rm = VFP_SREG_M(insn);
b7bcbe95
FB		 2909 }
2910
69d1fc22 2911 veclen = s->vec_len;
b7bcbe95
FB		 2912 if (op == 15 && rn > 3)
2913 veclen = 0;
2914
2915 /* Shut up compiler warnings. */
2916 delta_m = 0;
2917 delta_d = 0;
2918 bank_mask = 0;
3b46e624 2919
b7bcbe95
FB		 2920 if (veclen > 0) {
2921 if (dp)
2922 bank_mask = 0xc;
2923 else
2924 bank_mask = 0x18;
2925
2926 /* Figure out what type of vector operation this is. */
2927 if ((rd & bank_mask) == 0) {
2928 /* scalar */
2929 veclen = 0;
2930 } else {
2931 if (dp)
69d1fc22 2932 delta_d = (s->vec_stride >> 1) + 1;
b7bcbe95 2933 else
69d1fc22 2934 delta_d = s->vec_stride + 1;
b7bcbe95
FB		 2935
2936 if ((rm & bank_mask) == 0) {
2937 /* mixed scalar/vector */
2938 delta_m = 0;
2939 } else {
2940 /* vector */
2941 delta_m = delta_d;
2942 }
2943 }
2944 }
2945
2946 /* Load the initial operands. */
2947 if (op == 15) {
2948 switch (rn) {
2949 case 16:
2950 case 17:
2951 /* Integer source */
2952 gen_mov_F0_vreg(0, rm);
2953 break;
2954 case 8:
2955 case 9:
2956 /* Compare */
2957 gen_mov_F0_vreg(dp, rd);
2958 gen_mov_F1_vreg(dp, rm);
2959 break;
2960 case 10:
2961 case 11:
2962 /* Compare with zero */
2963 gen_mov_F0_vreg(dp, rd);
2964 gen_vfp_F1_ld0(dp);
2965 break;
9ee6e8bb
PB		 2966 case 20:
2967 case 21:
2968 case 22:
2969 case 23:
644ad806
PB		 2970 case 28:
2971 case 29:
2972 case 30:
2973 case 31:
9ee6e8bb
PB		 2974 /* Source and destination the same. */
2975 gen_mov_F0_vreg(dp, rd);
2976 break;
b7bcbe95
FB		 2977 default:
2978 /* One source operand. */
2979 gen_mov_F0_vreg(dp, rm);
9ee6e8bb 2980 break;
b7bcbe95
FB		 2981 }
2982 } else {
2983 /* Two source operands. */
2984 gen_mov_F0_vreg(dp, rn);
2985 gen_mov_F1_vreg(dp, rm);
2986 }
2987
2988 for (;;) {
2989 /* Perform the calculation. */
2990 switch (op) {
2991 case 0: /* mac: fd + (fn * fm) */
2992 gen_vfp_mul(dp);
2993 gen_mov_F1_vreg(dp, rd);
2994 gen_vfp_add(dp);
2995 break;
2996 case 1: /* nmac: fd - (fn * fm) */
2997 gen_vfp_mul(dp);
2998 gen_vfp_neg(dp);
2999 gen_mov_F1_vreg(dp, rd);
3000 gen_vfp_add(dp);
3001 break;
3002 case 2: /* msc: -fd + (fn * fm) */
3003 gen_vfp_mul(dp);
3004 gen_mov_F1_vreg(dp, rd);
3005 gen_vfp_sub(dp);
3006 break;
3007 case 3: /* nmsc: -fd - (fn * fm) */
3008 gen_vfp_mul(dp);
b7bcbe95 3009 gen_vfp_neg(dp);
c9fb531a
PB		 3010 gen_mov_F1_vreg(dp, rd);
3011 gen_vfp_sub(dp);
b7bcbe95
FB		 3012 break;
3013 case 4: /* mul: fn * fm */
3014 gen_vfp_mul(dp);
3015 break;
3016 case 5: /* nmul: -(fn * fm) */
3017 gen_vfp_mul(dp);
3018 gen_vfp_neg(dp);
3019 break;
3020 case 6: /* add: fn + fm */
3021 gen_vfp_add(dp);
3022 break;
3023 case 7: /* sub: fn - fm */
3024 gen_vfp_sub(dp);
3025 break;
3026 case 8: /* div: fn / fm */
3027 gen_vfp_div(dp);
3028 break;
9ee6e8bb
PB		 3029 case 14: /* fconst */
3030 if (!arm_feature(env, ARM_FEATURE_VFP3))
3031 return 1;
3032
3033 n = (insn << 12) & 0x80000000;
3034 i = ((insn >> 12) & 0x70) | (insn & 0xf);
3035 if (dp) {
3036 if (i & 0x40)
3037 i |= 0x3f80;
3038 else
3039 i |= 0x4000;
3040 n |= i << 16;
4373f3ce 3041 tcg_gen_movi_i64(cpu_F0d, ((uint64_t)n) << 32);
9ee6e8bb
PB		 3042 } else {
3043 if (i & 0x40)
3044 i |= 0x780;
3045 else
3046 i |= 0x800;
3047 n |= i << 19;
5b340b51 3048 tcg_gen_movi_i32(cpu_F0s, n);
9ee6e8bb 3049 }
9ee6e8bb 3050 break;
b7bcbe95
FB		 3051 case 15: /* extension space */
3052 switch (rn) {
3053 case 0: /* cpy */
3054 /* no-op */
3055 break;
3056 case 1: /* abs */
3057 gen_vfp_abs(dp);
3058 break;
3059 case 2: /* neg */
3060 gen_vfp_neg(dp);
3061 break;
3062 case 3: /* sqrt */
3063 gen_vfp_sqrt(dp);
3064 break;
60011498
PB		 3065 case 4: /* vcvtb.f32.f16 */
3066 if (!arm_feature(env, ARM_FEATURE_VFP_FP16))
3067 return 1;
3068 tmp = gen_vfp_mrs();
3069 tcg_gen_ext16u_i32(tmp, tmp);
3070 gen_helper_vfp_fcvt_f16_to_f32(cpu_F0s, tmp, cpu_env);
7d1b0095 3071 tcg_temp_free_i32(tmp);
60011498
PB		 3072 break;
3073 case 5: /* vcvtt.f32.f16 */
3074 if (!arm_feature(env, ARM_FEATURE_VFP_FP16))
3075 return 1;
3076 tmp = gen_vfp_mrs();
3077 tcg_gen_shri_i32(tmp, tmp, 16);
3078 gen_helper_vfp_fcvt_f16_to_f32(cpu_F0s, tmp, cpu_env);
7d1b0095 3079 tcg_temp_free_i32(tmp);
60011498
PB		 3080 break;
3081 case 6: /* vcvtb.f16.f32 */
3082 if (!arm_feature(env, ARM_FEATURE_VFP_FP16))
3083 return 1;
7d1b0095 3084 tmp = tcg_temp_new_i32();
60011498
PB		 3085 gen_helper_vfp_fcvt_f32_to_f16(tmp, cpu_F0s, cpu_env);
3086 gen_mov_F0_vreg(0, rd);
3087 tmp2 = gen_vfp_mrs();
3088 tcg_gen_andi_i32(tmp2, tmp2, 0xffff0000);
3089 tcg_gen_or_i32(tmp, tmp, tmp2);
7d1b0095 3090 tcg_temp_free_i32(tmp2);
60011498
PB		 3091 gen_vfp_msr(tmp);
3092 break;
3093 case 7: /* vcvtt.f16.f32 */
3094 if (!arm_feature(env, ARM_FEATURE_VFP_FP16))
3095 return 1;
7d1b0095 3096 tmp = tcg_temp_new_i32();
60011498
PB		 3097 gen_helper_vfp_fcvt_f32_to_f16(tmp, cpu_F0s, cpu_env);
3098 tcg_gen_shli_i32(tmp, tmp, 16);
3099 gen_mov_F0_vreg(0, rd);
3100 tmp2 = gen_vfp_mrs();
3101 tcg_gen_ext16u_i32(tmp2, tmp2);
3102 tcg_gen_or_i32(tmp, tmp, tmp2);
7d1b0095 3103 tcg_temp_free_i32(tmp2);
60011498
PB		 3104 gen_vfp_msr(tmp);
3105 break;
b7bcbe95
FB		 3106 case 8: /* cmp */
3107 gen_vfp_cmp(dp);
3108 break;
3109 case 9: /* cmpe */
3110 gen_vfp_cmpe(dp);
3111 break;
3112 case 10: /* cmpz */
3113 gen_vfp_cmp(dp);
3114 break;
3115 case 11: /* cmpez */
3116 gen_vfp_F1_ld0(dp);
3117 gen_vfp_cmpe(dp);
3118 break;
3119 case 15: /* single<->double conversion */
3120 if (dp)
4373f3ce 3121 gen_helper_vfp_fcvtsd(cpu_F0s, cpu_F0d, cpu_env);
b7bcbe95 3122 else
4373f3ce 3123 gen_helper_vfp_fcvtds(cpu_F0d, cpu_F0s, cpu_env);
b7bcbe95
FB		 3124 break;
3125 case 16: /* fuito */
3126 gen_vfp_uito(dp);
3127 break;
3128 case 17: /* fsito */
3129 gen_vfp_sito(dp);
3130 break;
9ee6e8bb
PB		 3131 case 20: /* fshto */
3132 if (!arm_feature(env, ARM_FEATURE_VFP3))
3133 return 1;
644ad806 3134 gen_vfp_shto(dp, 16 - rm);
9ee6e8bb
PB		 3135 break;
3136 case 21: /* fslto */
3137 if (!arm_feature(env, ARM_FEATURE_VFP3))
3138 return 1;
644ad806 3139 gen_vfp_slto(dp, 32 - rm);
9ee6e8bb
PB		 3140 break;
3141 case 22: /* fuhto */
3142 if (!arm_feature(env, ARM_FEATURE_VFP3))
3143 return 1;
644ad806 3144 gen_vfp_uhto(dp, 16 - rm);
9ee6e8bb
PB		 3145 break;
3146 case 23: /* fulto */
3147 if (!arm_feature(env, ARM_FEATURE_VFP3))
3148 return 1;
644ad806 3149 gen_vfp_ulto(dp, 32 - rm);
9ee6e8bb 3150 break;
b7bcbe95
FB		 3151 case 24: /* ftoui */
3152 gen_vfp_toui(dp);
3153 break;
3154 case 25: /* ftouiz */
3155 gen_vfp_touiz(dp);
3156 break;
3157 case 26: /* ftosi */
3158 gen_vfp_tosi(dp);
3159 break;
3160 case 27: /* ftosiz */
3161 gen_vfp_tosiz(dp);
3162 break;
9ee6e8bb
PB		 3163 case 28: /* ftosh */
3164 if (!arm_feature(env, ARM_FEATURE_VFP3))
3165 return 1;
644ad806 3166 gen_vfp_tosh(dp, 16 - rm);
9ee6e8bb
PB		 3167 break;
3168 case 29: /* ftosl */
3169 if (!arm_feature(env, ARM_FEATURE_VFP3))
3170 return 1;
644ad806 3171 gen_vfp_tosl(dp, 32 - rm);
9ee6e8bb
PB		 3172 break;
3173 case 30: /* ftouh */
3174 if (!arm_feature(env, ARM_FEATURE_VFP3))
3175 return 1;
644ad806 3176 gen_vfp_touh(dp, 16 - rm);
9ee6e8bb
PB		 3177 break;
3178 case 31: /* ftoul */
3179 if (!arm_feature(env, ARM_FEATURE_VFP3))
3180 return 1;
644ad806 3181 gen_vfp_toul(dp, 32 - rm);
9ee6e8bb 3182 break;
b7bcbe95
FB		 3183 default: /* undefined */
3184 printf ("rn:%d\n", rn);
3185 return 1;
3186 }
3187 break;
3188 default: /* undefined */
3189 printf ("op:%d\n", op);
3190 return 1;
3191 }
3192
3193 /* Write back the result. */
3194 if (op == 15 && (rn >= 8 && rn <= 11))
3195 ; /* Comparison, do nothing. */
04595bf6
PM		 3196 else if (op == 15 && dp && ((rn & 0x1c) == 0x18))
3197 /* VCVT double to int: always integer result. */
b7bcbe95
FB		 3198 gen_mov_vreg_F0(0, rd);
3199 else if (op == 15 && rn == 15)
3200 /* conversion */
3201 gen_mov_vreg_F0(!dp, rd);
3202 else
3203 gen_mov_vreg_F0(dp, rd);
3204
3205 /* break out of the loop if we have finished */
3206 if (veclen == 0)
3207 break;
3208
3209 if (op == 15 && delta_m == 0) {
3210 /* single source one-many */
3211 while (veclen--) {
3212 rd = ((rd + delta_d) & (bank_mask - 1))
3213 | (rd & bank_mask);
3214 gen_mov_vreg_F0(dp, rd);
3215 }
3216 break;
3217 }
3218 /* Setup the next operands. */
3219 veclen--;
3220 rd = ((rd + delta_d) & (bank_mask - 1))
3221 | (rd & bank_mask);
3222
3223 if (op == 15) {
3224 /* One source operand. */
3225 rm = ((rm + delta_m) & (bank_mask - 1))
3226 | (rm & bank_mask);
3227 gen_mov_F0_vreg(dp, rm);
3228 } else {
3229 /* Two source operands. */
3230 rn = ((rn + delta_d) & (bank_mask - 1))
3231 | (rn & bank_mask);
3232 gen_mov_F0_vreg(dp, rn);
3233 if (delta_m) {
3234 rm = ((rm + delta_m) & (bank_mask - 1))
3235 | (rm & bank_mask);
3236 gen_mov_F1_vreg(dp, rm);
3237 }
3238 }
3239 }
3240 }
3241 break;
3242 case 0xc:
3243 case 0xd:
8387da81 3244 if ((insn & 0x03e00000) == 0x00400000) {
b7bcbe95
FB		 3245 /* two-register transfer */
3246 rn = (insn >> 16) & 0xf;
3247 rd = (insn >> 12) & 0xf;
3248 if (dp) {
9ee6e8bb
PB		 3249 VFP_DREG_M(rm, insn);
3250 } else {
3251 rm = VFP_SREG_M(insn);
3252 }
b7bcbe95 3253
18c9b560 3254 if (insn & ARM_CP_RW_BIT) {
b7bcbe95
FB		 3255 /* vfp->arm */
3256 if (dp) {
4373f3ce
PB		 3257 gen_mov_F0_vreg(0, rm * 2);
3258 tmp = gen_vfp_mrs();
3259 store_reg(s, rd, tmp);
3260 gen_mov_F0_vreg(0, rm * 2 + 1);
3261 tmp = gen_vfp_mrs();
3262 store_reg(s, rn, tmp);
b7bcbe95
FB		 3263 } else {
3264 gen_mov_F0_vreg(0, rm);
4373f3ce 3265 tmp = gen_vfp_mrs();
8387da81 3266 store_reg(s, rd, tmp);
b7bcbe95 3267 gen_mov_F0_vreg(0, rm + 1);
4373f3ce 3268 tmp = gen_vfp_mrs();
8387da81 3269 store_reg(s, rn, tmp);
b7bcbe95
FB		 3270 }
3271 } else {
3272 /* arm->vfp */
3273 if (dp) {
4373f3ce
PB		 3274 tmp = load_reg(s, rd);
3275 gen_vfp_msr(tmp);
3276 gen_mov_vreg_F0(0, rm * 2);
3277 tmp = load_reg(s, rn);
3278 gen_vfp_msr(tmp);
3279 gen_mov_vreg_F0(0, rm * 2 + 1);
b7bcbe95 3280 } else {
8387da81 3281 tmp = load_reg(s, rd);
4373f3ce 3282 gen_vfp_msr(tmp);
b7bcbe95 3283 gen_mov_vreg_F0(0, rm);
8387da81 3284 tmp = load_reg(s, rn);
4373f3ce 3285 gen_vfp_msr(tmp);
b7bcbe95
FB		 3286 gen_mov_vreg_F0(0, rm + 1);
3287 }
3288 }
3289 } else {
3290 /* Load/store */
3291 rn = (insn >> 16) & 0xf;
3292 if (dp)
9ee6e8bb 3293 VFP_DREG_D(rd, insn);
b7bcbe95 3294 else
9ee6e8bb
PB		 3295 rd = VFP_SREG_D(insn);
3296 if (s->thumb && rn == 15) {
7d1b0095 3297 addr = tcg_temp_new_i32();
312eea9f 3298 tcg_gen_movi_i32(addr, s->pc & ~2);
9ee6e8bb 3299 } else {
312eea9f 3300 addr = load_reg(s, rn);
9ee6e8bb 3301 }
b7bcbe95
FB		 3302 if ((insn & 0x01200000) == 0x01000000) {
3303 /* Single load/store */
3304 offset = (insn & 0xff) << 2;
3305 if ((insn & (1 << 23)) == 0)
3306 offset = -offset;
312eea9f 3307 tcg_gen_addi_i32(addr, addr, offset);
b7bcbe95 3308 if (insn & (1 << 20)) {
312eea9f 3309 gen_vfp_ld(s, dp, addr);
b7bcbe95
FB		 3310 gen_mov_vreg_F0(dp, rd);
3311 } else {
3312 gen_mov_F0_vreg(dp, rd);
312eea9f 3313 gen_vfp_st(s, dp, addr);
b7bcbe95 3314 }
7d1b0095 3315 tcg_temp_free_i32(addr);
b7bcbe95
FB		 3316 } else {
3317 /* load/store multiple */
3318 if (dp)
3319 n = (insn >> 1) & 0x7f;
3320 else
3321 n = insn & 0xff;
3322
3323 if (insn & (1 << 24)) /* pre-decrement */
312eea9f 3324 tcg_gen_addi_i32(addr, addr, -((insn & 0xff) << 2));
b7bcbe95
FB		 3325
3326 if (dp)
3327 offset = 8;
3328 else
3329 offset = 4;
3330 for (i = 0; i < n; i++) {
18c9b560 3331 if (insn & ARM_CP_RW_BIT) {
b7bcbe95 3332 /* load */
312eea9f 3333 gen_vfp_ld(s, dp, addr);
b7bcbe95
FB		 3334 gen_mov_vreg_F0(dp, rd + i);
3335 } else {
3336 /* store */
3337 gen_mov_F0_vreg(dp, rd + i);
312eea9f 3338 gen_vfp_st(s, dp, addr);
b7bcbe95 3339 }
312eea9f 3340 tcg_gen_addi_i32(addr, addr, offset);
b7bcbe95
FB		 3341 }
3342 if (insn & (1 << 21)) {
3343 /* writeback */
3344 if (insn & (1 << 24))
3345 offset = -offset * n;
3346 else if (dp && (insn & 1))
3347 offset = 4;
3348 else
3349 offset = 0;
3350
3351 if (offset != 0)
312eea9f
FN		 3352 tcg_gen_addi_i32(addr, addr, offset);
3353 store_reg(s, rn, addr);
3354 } else {
7d1b0095 3355 tcg_temp_free_i32(addr);
b7bcbe95
FB		 3356 }
3357 }
3358 }
3359 break;
3360 default:
3361 /* Should never happen. */
3362 return 1;
3363 }
3364 return 0;
3365}
3366
6e256c93 3367static inline void gen_goto_tb(DisasContext *s, int n, uint32_t dest)
c53be334 3368{
6e256c93
FB		 3369 TranslationBlock *tb;
3370
3371 tb = s->tb;
3372 if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK)) {
57fec1fe 3373 tcg_gen_goto_tb(n);
8984bd2e 3374 gen_set_pc_im(dest);
57fec1fe 3375 tcg_gen_exit_tb((long)tb + n);
6e256c93 3376 } else {
8984bd2e 3377 gen_set_pc_im(dest);
57fec1fe 3378 tcg_gen_exit_tb(0);
6e256c93 3379 }
c53be334
FB		 3380}
3381
8aaca4c0
FB		 3382static inline void gen_jmp (DisasContext *s, uint32_t dest)
3383{
551bd27f 3384 if (unlikely(s->singlestep_enabled)) {
8aaca4c0 3385 /* An indirect jump so that we still trigger the debug exception. */
5899f386 3386 if (s->thumb)
d9ba4830
PB		 3387 dest |= 1;
3388 gen_bx_im(s, dest);
8aaca4c0 3389 } else {
6e256c93 3390 gen_goto_tb(s, 0, dest);
8aaca4c0
FB		 3391 s->is_jmp = DISAS_TB_JUMP;
3392 }
3393}
3394
d9ba4830 3395static inline void gen_mulxy(TCGv t0, TCGv t1, int x, int y)
b5ff1b31 3396{
ee097184 3397 if (x)
d9ba4830 3398 tcg_gen_sari_i32(t0, t0, 16);
b5ff1b31 3399 else
d9ba4830 3400 gen_sxth(t0);
ee097184 3401 if (y)
d9ba4830 3402 tcg_gen_sari_i32(t1, t1, 16);
b5ff1b31 3403 else
d9ba4830
PB		 3404 gen_sxth(t1);
3405 tcg_gen_mul_i32(t0, t0, t1);
b5ff1b31
FB		 3406}
3407
3408/* Return the mask of PSR bits set by a MSR instruction. */
9ee6e8bb 3409static uint32_t msr_mask(CPUState *env, DisasContext *s, int flags, int spsr) {
b5ff1b31
FB		 3410 uint32_t mask;
3411
3412 mask = 0;
3413 if (flags & (1 << 0))
3414 mask |= 0xff;
3415 if (flags & (1 << 1))
3416 mask |= 0xff00;
3417 if (flags & (1 << 2))
3418 mask |= 0xff0000;
3419 if (flags & (1 << 3))
3420 mask |= 0xff000000;
9ee6e8bb 3421
2ae23e75 3422 /* Mask out undefined bits. */
9ee6e8bb
PB		 3423 mask &= ~CPSR_RESERVED;
3424 if (!arm_feature(env, ARM_FEATURE_V6))
e160c51c 3425 mask &= ~(CPSR_E | CPSR_GE);
9ee6e8bb 3426 if (!arm_feature(env, ARM_FEATURE_THUMB2))
e160c51c 3427 mask &= ~CPSR_IT;
9ee6e8bb 3428 /* Mask out execution state bits. */
2ae23e75 3429 if (!spsr)
e160c51c 3430 mask &= ~CPSR_EXEC;
b5ff1b31
FB		 3431 /* Mask out privileged bits. */
3432 if (IS_USER(s))
9ee6e8bb 3433 mask &= CPSR_USER;
b5ff1b31
FB		 3434 return mask;
3435}
3436
2fbac54b
FN		 3437/* Returns nonzero if access to the PSR is not permitted. Marks t0 as dead. */
3438static int gen_set_psr(DisasContext *s, uint32_t mask, int spsr, TCGv t0)
b5ff1b31 3439{
d9ba4830 3440 TCGv tmp;
b5ff1b31
FB		 3441 if (spsr) {
3442 /* ??? This is also undefined in system mode. */
3443 if (IS_USER(s))
3444 return 1;
d9ba4830
PB		 3445
3446 tmp = load_cpu_field(spsr);
3447 tcg_gen_andi_i32(tmp, tmp, ~mask);
2fbac54b
FN		 3448 tcg_gen_andi_i32(t0, t0, mask);
3449 tcg_gen_or_i32(tmp, tmp, t0);
d9ba4830 3450 store_cpu_field(tmp, spsr);
b5ff1b31 3451 } else {
2fbac54b 3452 gen_set_cpsr(t0, mask);
b5ff1b31 3453 }
7d1b0095 3454 tcg_temp_free_i32(t0);
b5ff1b31
FB		 3455 gen_lookup_tb(s);
3456 return 0;
3457}
3458
2fbac54b
FN		 3459/* Returns nonzero if access to the PSR is not permitted. */
3460static int gen_set_psr_im(DisasContext *s, uint32_t mask, int spsr, uint32_t val)
3461{
3462 TCGv tmp;
7d1b0095 3463 tmp = tcg_temp_new_i32();
2fbac54b
FN		 3464 tcg_gen_movi_i32(tmp, val);
3465 return gen_set_psr(s, mask, spsr, tmp);
3466}
3467
e9bb4aa9
JR		 3468/* Generate an old-style exception return. Marks pc as dead. */
3469static void gen_exception_return(DisasContext *s, TCGv pc)
b5ff1b31 3470{
d9ba4830 3471 TCGv tmp;
e9bb4aa9 3472 store_reg(s, 15, pc);
d9ba4830
PB		 3473 tmp = load_cpu_field(spsr);
3474 gen_set_cpsr(tmp, 0xffffffff);
7d1b0095 3475 tcg_temp_free_i32(tmp);
b5ff1b31
FB		 3476 s->is_jmp = DISAS_UPDATE;
3477}
3478
b0109805
PB		 3479/* Generate a v6 exception return. Marks both values as dead. */
3480static void gen_rfe(DisasContext *s, TCGv pc, TCGv cpsr)
2c0262af 3481{
b0109805 3482 gen_set_cpsr(cpsr, 0xffffffff);
7d1b0095 3483 tcg_temp_free_i32(cpsr);
b0109805 3484 store_reg(s, 15, pc);
9ee6e8bb
PB		 3485 s->is_jmp = DISAS_UPDATE;
3486}
3b46e624 3487
9ee6e8bb
PB		 3488static inline void
3489gen_set_condexec (DisasContext *s)
3490{
3491 if (s->condexec_mask) {
8f01245e 3492 uint32_t val = (s->condexec_cond << 4) | (s->condexec_mask >> 1);
7d1b0095 3493 TCGv tmp = tcg_temp_new_i32();
8f01245e 3494 tcg_gen_movi_i32(tmp, val);
d9ba4830 3495 store_cpu_field(tmp, condexec_bits);
9ee6e8bb
PB		 3496 }
3497}
3b46e624 3498
bc4a0de0
PM		 3499static void gen_exception_insn(DisasContext *s, int offset, int excp)
3500{
3501 gen_set_condexec(s);
3502 gen_set_pc_im(s->pc - offset);
3503 gen_exception(excp);
3504 s->is_jmp = DISAS_JUMP;
3505}
3506
9ee6e8bb
PB		 3507static void gen_nop_hint(DisasContext *s, int val)
3508{
3509 switch (val) {
3510 case 3: /* wfi */
8984bd2e 3511 gen_set_pc_im(s->pc);
9ee6e8bb
PB		 3512 s->is_jmp = DISAS_WFI;
3513 break;
3514 case 2: /* wfe */
3515 case 4: /* sev */
3516 /* TODO: Implement SEV and WFE. May help SMP performance. */
3517 default: /* nop */
3518 break;
3519 }
3520}
99c475ab 3521
ad69471c 3522#define CPU_V001 cpu_V0, cpu_V0, cpu_V1
9ee6e8bb 3523
dd8fbd78 3524static inline int gen_neon_add(int size, TCGv t0, TCGv t1)
9ee6e8bb
PB		 3525{
3526 switch (size) {
dd8fbd78
FN		 3527 case 0: gen_helper_neon_add_u8(t0, t0, t1); break;
3528 case 1: gen_helper_neon_add_u16(t0, t0, t1); break;
3529 case 2: tcg_gen_add_i32(t0, t0, t1); break;
9ee6e8bb
PB		 3530 default: return 1;
3531 }
3532 return 0;
3533}
3534
dd8fbd78 3535static inline void gen_neon_rsb(int size, TCGv t0, TCGv t1)
ad69471c
PB		 3536{
3537 switch (size) {
dd8fbd78
FN		 3538 case 0: gen_helper_neon_sub_u8(t0, t1, t0); break;
3539 case 1: gen_helper_neon_sub_u16(t0, t1, t0); break;
3540 case 2: tcg_gen_sub_i32(t0, t1, t0); break;
ad69471c
PB		 3541 default: return;
3542 }
3543}
3544
3545/* 32-bit pairwise ops end up the same as the elementwise versions. */
3546#define gen_helper_neon_pmax_s32 gen_helper_neon_max_s32
3547#define gen_helper_neon_pmax_u32 gen_helper_neon_max_u32
3548#define gen_helper_neon_pmin_s32 gen_helper_neon_min_s32
3549#define gen_helper_neon_pmin_u32 gen_helper_neon_min_u32
3550
ad69471c
PB		 3551#define GEN_NEON_INTEGER_OP_ENV(name) do { \
3552 switch ((size << 1) | u) { \
3553 case 0: \
dd8fbd78 3554 gen_helper_neon_##name##_s8(tmp, cpu_env, tmp, tmp2); \
ad69471c
PB		 3555 break; \
3556 case 1: \
dd8fbd78 3557 gen_helper_neon_##name##_u8(tmp, cpu_env, tmp, tmp2); \
ad69471c
PB		 3558 break; \
3559 case 2: \
dd8fbd78 3560 gen_helper_neon_##name##_s16(tmp, cpu_env, tmp, tmp2); \
ad69471c
PB		 3561 break; \
3562 case 3: \
dd8fbd78 3563 gen_helper_neon_##name##_u16(tmp, cpu_env, tmp, tmp2); \
ad69471c
PB		 3564 break; \
3565 case 4: \
dd8fbd78 3566 gen_helper_neon_##name##_s32(tmp, cpu_env, tmp, tmp2); \
ad69471c
PB		 3567 break; \
3568 case 5: \
dd8fbd78 3569 gen_helper_neon_##name##_u32(tmp, cpu_env, tmp, tmp2); \
ad69471c
PB		 3570 break; \
3571 default: return 1; \
3572 }} while (0)
9ee6e8bb
PB		 3573
3574#define GEN_NEON_INTEGER_OP(name) do { \
3575 switch ((size << 1) | u) { \
ad69471c 3576 case 0: \
dd8fbd78 3577 gen_helper_neon_##name##_s8(tmp, tmp, tmp2); \
ad69471c
PB		 3578 break; \
3579 case 1: \
dd8fbd78 3580 gen_helper_neon_##name##_u8(tmp, tmp, tmp2); \
ad69471c
PB		 3581 break; \
3582 case 2: \
dd8fbd78 3583 gen_helper_neon_##name##_s16(tmp, tmp, tmp2); \
ad69471c
PB		 3584 break; \
3585 case 3: \
dd8fbd78 3586 gen_helper_neon_##name##_u16(tmp, tmp, tmp2); \
ad69471c
PB		 3587 break; \
3588 case 4: \
dd8fbd78 3589 gen_helper_neon_##name##_s32(tmp, tmp, tmp2); \
ad69471c
PB		 3590 break; \
3591 case 5: \
dd8fbd78 3592 gen_helper_neon_##name##_u32(tmp, tmp, tmp2); \
ad69471c 3593 break; \
9ee6e8bb
PB		 3594 default: return 1; \
3595 }} while (0)
3596
dd8fbd78 3597static TCGv neon_load_scratch(int scratch)
9ee6e8bb 3598{
7d1b0095 3599 TCGv tmp = tcg_temp_new_i32();
dd8fbd78
FN		 3600 tcg_gen_ld_i32(tmp, cpu_env, offsetof(CPUARMState, vfp.scratch[scratch]));
3601 return tmp;
9ee6e8bb
PB		 3602}
3603
dd8fbd78 3604static void neon_store_scratch(int scratch, TCGv var)
9ee6e8bb 3605{
dd8fbd78 3606 tcg_gen_st_i32(var, cpu_env, offsetof(CPUARMState, vfp.scratch[scratch]));
7d1b0095 3607 tcg_temp_free_i32(var);
9ee6e8bb
PB		 3608}
3609
dd8fbd78 3610static inline TCGv neon_get_scalar(int size, int reg)
9ee6e8bb 3611{
dd8fbd78 3612 TCGv tmp;
9ee6e8bb 3613 if (size == 1) {
0fad6efc
PM		 3614 tmp = neon_load_reg(reg & 7, reg >> 4);
3615 if (reg & 8) {
dd8fbd78 3616 gen_neon_dup_high16(tmp);
0fad6efc
PM		 3617 } else {
3618 gen_neon_dup_low16(tmp);
dd8fbd78 3619 }
0fad6efc
PM		 3620 } else {
3621 tmp = neon_load_reg(reg & 15, reg >> 4);
9ee6e8bb 3622 }
dd8fbd78 3623 return tmp;
9ee6e8bb
PB		 3624}
3625
02acedf9 3626static int gen_neon_unzip(int rd, int rm, int size, int q)
19457615 3627{
02acedf9
PM		 3628 TCGv tmp, tmp2;
3629 if (size == 3 || (!q && size == 2)) {
3630 return 1;
3631 }
3632 tmp = tcg_const_i32(rd);
3633 tmp2 = tcg_const_i32(rm);
3634 if (q) {
3635 switch (size) {
3636 case 0:
3637 gen_helper_neon_qunzip8(cpu_env, tmp, tmp2);
3638 break;
3639 case 1:
3640 gen_helper_neon_qunzip16(cpu_env, tmp, tmp2);
3641 break;
3642 case 2:
3643 gen_helper_neon_qunzip32(cpu_env, tmp, tmp2);
3644 break;
3645 default:
3646 abort();
3647 }
3648 } else {
3649 switch (size) {
3650 case 0:
3651 gen_helper_neon_unzip8(cpu_env, tmp, tmp2);
3652 break;
3653 case 1:
3654 gen_helper_neon_unzip16(cpu_env, tmp, tmp2);
3655 break;
3656 default:
3657 abort();
3658 }
3659 }
3660 tcg_temp_free_i32(tmp);
3661 tcg_temp_free_i32(tmp2);
3662 return 0;
19457615
FN		 3663}
3664
d68a6f3a 3665static int gen_neon_zip(int rd, int rm, int size, int q)
19457615
FN		 3666{
3667 TCGv tmp, tmp2;
d68a6f3a
PM		 3668 if (size == 3 || (!q && size == 2)) {
3669 return 1;
3670 }
3671 tmp = tcg_const_i32(rd);
3672 tmp2 = tcg_const_i32(rm);
3673 if (q) {
3674 switch (size) {
3675 case 0:
3676 gen_helper_neon_qzip8(cpu_env, tmp, tmp2);
3677 break;
3678 case 1:
3679 gen_helper_neon_qzip16(cpu_env, tmp, tmp2);
3680 break;
3681 case 2:
3682 gen_helper_neon_qzip32(cpu_env, tmp, tmp2);
3683 break;
3684 default:
3685 abort();
3686 }
3687 } else {
3688 switch (size) {
3689 case 0:
3690 gen_helper_neon_zip8(cpu_env, tmp, tmp2);
3691 break;
3692 case 1:
3693 gen_helper_neon_zip16(cpu_env, tmp, tmp2);
3694 break;
3695 default:
3696 abort();
3697 }
3698 }
3699 tcg_temp_free_i32(tmp);
3700 tcg_temp_free_i32(tmp2);
3701 return 0;
19457615
FN		 3702}
3703
19457615
FN		 3704static void gen_neon_trn_u8(TCGv t0, TCGv t1)
3705{
3706 TCGv rd, tmp;
3707
7d1b0095
PM		 3708 rd = tcg_temp_new_i32();
3709 tmp = tcg_temp_new_i32();
19457615
FN		 3710
3711 tcg_gen_shli_i32(rd, t0, 8);
3712 tcg_gen_andi_i32(rd, rd, 0xff00ff00);
3713 tcg_gen_andi_i32(tmp, t1, 0x00ff00ff);
3714 tcg_gen_or_i32(rd, rd, tmp);
3715
3716 tcg_gen_shri_i32(t1, t1, 8);
3717 tcg_gen_andi_i32(t1, t1, 0x00ff00ff);
3718 tcg_gen_andi_i32(tmp, t0, 0xff00ff00);
3719 tcg_gen_or_i32(t1, t1, tmp);
3720 tcg_gen_mov_i32(t0, rd);
3721
7d1b0095
PM		 3722 tcg_temp_free_i32(tmp);
3723 tcg_temp_free_i32(rd);
19457615
FN		 3724}
3725
3726static void gen_neon_trn_u16(TCGv t0, TCGv t1)
3727{
3728 TCGv rd, tmp;
3729
7d1b0095
PM		 3730 rd = tcg_temp_new_i32();
3731 tmp = tcg_temp_new_i32();
19457615
FN		 3732
3733 tcg_gen_shli_i32(rd, t0, 16);
3734 tcg_gen_andi_i32(tmp, t1, 0xffff);
3735 tcg_gen_or_i32(rd, rd, tmp);
3736 tcg_gen_shri_i32(t1, t1, 16);
3737 tcg_gen_andi_i32(tmp, t0, 0xffff0000);
3738 tcg_gen_or_i32(t1, t1, tmp);
3739 tcg_gen_mov_i32(t0, rd);
3740
7d1b0095
PM		 3741 tcg_temp_free_i32(tmp);
3742 tcg_temp_free_i32(rd);
19457615
FN		 3743}
3744
3745
9ee6e8bb
PB		 3746static struct {
3747 int nregs;
3748 int interleave;
3749 int spacing;
3750} neon_ls_element_type[11] = {
3751 {4, 4, 1},
3752 {4, 4, 2},
3753 {4, 1, 1},
3754 {4, 2, 1},
3755 {3, 3, 1},
3756 {3, 3, 2},
3757 {3, 1, 1},
3758 {1, 1, 1},
3759 {2, 2, 1},
3760 {2, 2, 2},
3761 {2, 1, 1}
3762};
3763
3764/* Translate a NEON load/store element instruction. Return nonzero if the
3765 instruction is invalid. */
3766static int disas_neon_ls_insn(CPUState * env, DisasContext *s, uint32_t insn)
3767{
3768 int rd, rn, rm;
3769 int op;
3770 int nregs;
3771 int interleave;
84496233 3772 int spacing;
9ee6e8bb
PB		 3773 int stride;
3774 int size;
3775 int reg;
3776 int pass;
3777 int load;
3778 int shift;
9ee6e8bb 3779 int n;
1b2b1e54 3780 TCGv addr;
b0109805 3781 TCGv tmp;
8f8e3aa4 3782 TCGv tmp2;
84496233 3783 TCGv_i64 tmp64;
9ee6e8bb 3784
5df8bac1 3785 if (!s->vfp_enabled)
9ee6e8bb
PB		 3786 return 1;
3787 VFP_DREG_D(rd, insn);
3788 rn = (insn >> 16) & 0xf;
3789 rm = insn & 0xf;
3790 load = (insn & (1 << 21)) != 0;
7d1b0095 3791 addr = tcg_temp_new_i32();
9ee6e8bb
PB		 3792 if ((insn & (1 << 23)) == 0) {
3793 /* Load store all elements. */
3794 op = (insn >> 8) & 0xf;
3795 size = (insn >> 6) & 3;
84496233 3796 if (op > 10)
9ee6e8bb
PB		 3797 return 1;
3798 nregs = neon_ls_element_type[op].nregs;
3799 interleave = neon_ls_element_type[op].interleave;
84496233
JR		 3800 spacing = neon_ls_element_type[op].spacing;
3801 if (size == 3 && (interleave | spacing) != 1)
3802 return 1;
dcc65026 3803 load_reg_var(s, addr, rn);
9ee6e8bb
PB		 3804 stride = (1 << size) * interleave;
3805 for (reg = 0; reg < nregs; reg++) {
3806 if (interleave > 2 || (interleave == 2 && nregs == 2)) {
dcc65026
AJ		 3807 load_reg_var(s, addr, rn);
3808 tcg_gen_addi_i32(addr, addr, (1 << size) * reg);
9ee6e8bb 3809 } else if (interleave == 2 && nregs == 4 && reg == 2) {
dcc65026
AJ		 3810 load_reg_var(s, addr, rn);
3811 tcg_gen_addi_i32(addr, addr, 1 << size);
9ee6e8bb 3812 }
84496233
JR		 3813 if (size == 3) {
3814 if (load) {
3815 tmp64 = gen_ld64(addr, IS_USER(s));
3816 neon_store_reg64(tmp64, rd);
3817 tcg_temp_free_i64(tmp64);
3818 } else {
3819 tmp64 = tcg_temp_new_i64();
3820 neon_load_reg64(tmp64, rd);
3821 gen_st64(tmp64, addr, IS_USER(s));
3822 }
3823 tcg_gen_addi_i32(addr, addr, stride);
3824 } else {
3825 for (pass = 0; pass < 2; pass++) {
3826 if (size == 2) {
3827 if (load) {
3828 tmp = gen_ld32(addr, IS_USER(s));
3829 neon_store_reg(rd, pass, tmp);
3830 } else {
3831 tmp = neon_load_reg(rd, pass);
3832 gen_st32(tmp, addr, IS_USER(s));
3833 }
1b2b1e54 3834 tcg_gen_addi_i32(addr, addr, stride);
84496233
JR		 3835 } else if (size == 1) {
3836 if (load) {
3837 tmp = gen_ld16u(addr, IS_USER(s));
3838 tcg_gen_addi_i32(addr, addr, stride);
3839 tmp2 = gen_ld16u(addr, IS_USER(s));
3840 tcg_gen_addi_i32(addr, addr, stride);
41ba8341
PB		 3841 tcg_gen_shli_i32(tmp2, tmp2, 16);
3842 tcg_gen_or_i32(tmp, tmp, tmp2);
7d1b0095 3843 tcg_temp_free_i32(tmp2);
84496233
JR		 3844 neon_store_reg(rd, pass, tmp);
3845 } else {
3846 tmp = neon_load_reg(rd, pass);
7d1b0095 3847 tmp2 = tcg_temp_new_i32();
84496233
JR		 3848 tcg_gen_shri_i32(tmp2, tmp, 16);
3849 gen_st16(tmp, addr, IS_USER(s));
3850 tcg_gen_addi_i32(addr, addr, stride);
3851 gen_st16(tmp2, addr, IS_USER(s));
1b2b1e54 3852 tcg_gen_addi_i32(addr, addr, stride);
9ee6e8bb 3853 }
84496233
JR		 3854 } else /* size == 0 */ {
3855 if (load) {
3856 TCGV_UNUSED(tmp2);
3857 for (n = 0; n < 4; n++) {
3858 tmp = gen_ld8u(addr, IS_USER(s));
3859 tcg_gen_addi_i32(addr, addr, stride);
3860 if (n == 0) {
3861 tmp2 = tmp;
3862 } else {
41ba8341
PB		 3863 tcg_gen_shli_i32(tmp, tmp, n * 8);
3864 tcg_gen_or_i32(tmp2, tmp2, tmp);
7d1b0095 3865 tcg_temp_free_i32(tmp);
84496233 3866 }
9ee6e8bb 3867 }
84496233
JR		 3868 neon_store_reg(rd, pass, tmp2);
3869 } else {
3870 tmp2 = neon_load_reg(rd, pass);
3871 for (n = 0; n < 4; n++) {
7d1b0095 3872 tmp = tcg_temp_new_i32();
84496233
JR		 3873 if (n == 0) {
3874 tcg_gen_mov_i32(tmp, tmp2);
3875 } else {
3876 tcg_gen_shri_i32(tmp, tmp2, n * 8);
3877 }
3878 gen_st8(tmp, addr, IS_USER(s));
3879 tcg_gen_addi_i32(addr, addr, stride);
3880 }
7d1b0095 3881 tcg_temp_free_i32(tmp2);
9ee6e8bb
PB		 3882 }
3883 }
3884 }
3885 }
84496233 3886 rd += spacing;
9ee6e8bb
PB		 3887 }
3888 stride = nregs * 8;
3889 } else {
3890 size = (insn >> 10) & 3;
3891 if (size == 3) {
3892 /* Load single element to all lanes. */
3893 if (!load)
3894 return 1;
3895 size = (insn >> 6) & 3;
3896 nregs = ((insn >> 8) & 3) + 1;
3897 stride = (insn & (1 << 5)) ? 2 : 1;
dcc65026 3898 load_reg_var(s, addr, rn);
9ee6e8bb
PB		 3899 for (reg = 0; reg < nregs; reg++) {
3900 switch (size) {
3901 case 0:
1b2b1e54 3902 tmp = gen_ld8u(addr, IS_USER(s));
ad69471c 3903 gen_neon_dup_u8(tmp, 0);
9ee6e8bb
PB		 3904 break;
3905 case 1:
1b2b1e54 3906 tmp = gen_ld16u(addr, IS_USER(s));
ad69471c 3907 gen_neon_dup_low16(tmp);
9ee6e8bb
PB		 3908 break;
3909 case 2:
1b2b1e54 3910 tmp = gen_ld32(addr, IS_USER(s));
9ee6e8bb
PB		 3911 break;
3912 case 3:
3913 return 1;
a50f5b91
PB		 3914 default: /* Avoid compiler warnings. */
3915 abort();
99c475ab 3916 }
1b2b1e54 3917 tcg_gen_addi_i32(addr, addr, 1 << size);
7d1b0095 3918 tmp2 = tcg_temp_new_i32();
ad69471c
PB		 3919 tcg_gen_mov_i32(tmp2, tmp);
3920 neon_store_reg(rd, 0, tmp2);
3018f259 3921 neon_store_reg(rd, 1, tmp);
9ee6e8bb
PB		 3922 rd += stride;
3923 }
3924 stride = (1 << size) * nregs;
3925 } else {
3926 /* Single element. */
3927 pass = (insn >> 7) & 1;
3928 switch (size) {
3929 case 0:
3930 shift = ((insn >> 5) & 3) * 8;
9ee6e8bb
PB		 3931 stride = 1;
3932 break;
3933 case 1:
3934 shift = ((insn >> 6) & 1) * 16;
9ee6e8bb
PB		 3935 stride = (insn & (1 << 5)) ? 2 : 1;
3936 break;
3937 case 2:
3938 shift = 0;
9ee6e8bb
PB		 3939 stride = (insn & (1 << 6)) ? 2 : 1;
3940 break;
3941 default:
3942 abort();
3943 }
3944 nregs = ((insn >> 8) & 3) + 1;
dcc65026 3945 load_reg_var(s, addr, rn);
9ee6e8bb
PB		 3946 for (reg = 0; reg < nregs; reg++) {
3947 if (load) {
9ee6e8bb
PB		 3948 switch (size) {
3949 case 0:
1b2b1e54 3950 tmp = gen_ld8u(addr, IS_USER(s));
9ee6e8bb
PB		 3951 break;
3952 case 1:
1b2b1e54 3953 tmp = gen_ld16u(addr, IS_USER(s));
9ee6e8bb
PB		 3954 break;
3955 case 2:
1b2b1e54 3956 tmp = gen_ld32(addr, IS_USER(s));
9ee6e8bb 3957 break;
a50f5b91
PB		 3958 default: /* Avoid compiler warnings. */
3959 abort();
9ee6e8bb
PB		 3960 }
3961 if (size != 2) {
8f8e3aa4
PB		 3962 tmp2 = neon_load_reg(rd, pass);
3963 gen_bfi(tmp, tmp2, tmp, shift, size ? 0xffff : 0xff);
7d1b0095 3964 tcg_temp_free_i32(tmp2);
9ee6e8bb 3965 }
8f8e3aa4 3966 neon_store_reg(rd, pass, tmp);
9ee6e8bb 3967 } else { /* Store */
8f8e3aa4
PB		 3968 tmp = neon_load_reg(rd, pass);
3969 if (shift)
3970 tcg_gen_shri_i32(tmp, tmp, shift);
9ee6e8bb
PB		 3971 switch (size) {
3972 case 0:
1b2b1e54 3973 gen_st8(tmp, addr, IS_USER(s));
9ee6e8bb
PB		 3974 break;
3975 case 1:
1b2b1e54 3976 gen_st16(tmp, addr, IS_USER(s));
9ee6e8bb
PB		 3977 break;
3978 case 2:
1b2b1e54 3979 gen_st32(tmp, addr, IS_USER(s));
9ee6e8bb 3980 break;
99c475ab 3981 }
99c475ab 3982 }
9ee6e8bb 3983 rd += stride;
1b2b1e54 3984 tcg_gen_addi_i32(addr, addr, 1 << size);
99c475ab 3985 }
9ee6e8bb 3986 stride = nregs * (1 << size);
99c475ab 3987 }
9ee6e8bb 3988 }
7d1b0095 3989 tcg_temp_free_i32(addr);
9ee6e8bb 3990 if (rm != 15) {
b26eefb6
PB		 3991 TCGv base;
3992
3993 base = load_reg(s, rn);
9ee6e8bb 3994 if (rm == 13) {
b26eefb6 3995 tcg_gen_addi_i32(base, base, stride);
9ee6e8bb 3996 } else {
b26eefb6
PB		 3997 TCGv index;
3998 index = load_reg(s, rm);
3999 tcg_gen_add_i32(base, base, index);
7d1b0095 4000 tcg_temp_free_i32(index);
9ee6e8bb 4001 }
b26eefb6 4002 store_reg(s, rn, base);
9ee6e8bb
PB		 4003 }
4004 return 0;
4005}
3b46e624 4006
8f8e3aa4
PB		 4007/* Bitwise select. dest = c ? t : f. Clobbers T and F. */
4008static void gen_neon_bsl(TCGv dest, TCGv t, TCGv f, TCGv c)
4009{
4010 tcg_gen_and_i32(t, t, c);
f669df27 4011 tcg_gen_andc_i32(f, f, c);
8f8e3aa4
PB		 4012 tcg_gen_or_i32(dest, t, f);
4013}
4014
a7812ae4 4015static inline void gen_neon_narrow(int size, TCGv dest, TCGv_i64 src)
ad69471c
PB		 4016{
4017 switch (size) {
4018 case 0: gen_helper_neon_narrow_u8(dest, src); break;
4019 case 1: gen_helper_neon_narrow_u16(dest, src); break;
4020 case 2: tcg_gen_trunc_i64_i32(dest, src); break;
4021 default: abort();
4022 }
4023}
4024
a7812ae4 4025static inline void gen_neon_narrow_sats(int size, TCGv dest, TCGv_i64 src)
ad69471c
PB		 4026{
4027 switch (size) {
4028 case 0: gen_helper_neon_narrow_sat_s8(dest, cpu_env, src); break;
4029 case 1: gen_helper_neon_narrow_sat_s16(dest, cpu_env, src); break;
4030 case 2: gen_helper_neon_narrow_sat_s32(dest, cpu_env, src); break;
4031 default: abort();
4032 }
4033}
4034
a7812ae4 4035static inline void gen_neon_narrow_satu(int size, TCGv dest, TCGv_i64 src)
ad69471c
PB		 4036{
4037 switch (size) {
4038 case 0: gen_helper_neon_narrow_sat_u8(dest, cpu_env, src); break;
4039 case 1: gen_helper_neon_narrow_sat_u16(dest, cpu_env, src); break;
4040 case 2: gen_helper_neon_narrow_sat_u32(dest, cpu_env, src); break;
4041 default: abort();
4042 }
4043}
4044
af1bbf30
JR		 4045static inline void gen_neon_unarrow_sats(int size, TCGv dest, TCGv_i64 src)
4046{
4047 switch (size) {
4048 case 0: gen_helper_neon_unarrow_sat8(dest, cpu_env, src); break;
4049 case 1: gen_helper_neon_unarrow_sat16(dest, cpu_env, src); break;
4050 case 2: gen_helper_neon_unarrow_sat32(dest, cpu_env, src); break;
4051 default: abort();
4052 }
4053}
4054
ad69471c
PB		 4055static inline void gen_neon_shift_narrow(int size, TCGv var, TCGv shift,
4056 int q, int u)
4057{
4058 if (q) {
4059 if (u) {
4060 switch (size) {
4061 case 1: gen_helper_neon_rshl_u16(var, var, shift); break;
4062 case 2: gen_helper_neon_rshl_u32(var, var, shift); break;
4063 default: abort();
4064 }
4065 } else {
4066 switch (size) {
4067 case 1: gen_helper_neon_rshl_s16(var, var, shift); break;
4068 case 2: gen_helper_neon_rshl_s32(var, var, shift); break;
4069 default: abort();
4070 }
4071 }
4072 } else {
4073 if (u) {
4074 switch (size) {
b408a9b0
CL		 4075 case 1: gen_helper_neon_shl_u16(var, var, shift); break;
4076 case 2: gen_helper_neon_shl_u32(var, var, shift); break;
ad69471c
PB		 4077 default: abort();
4078 }
4079 } else {
4080 switch (size) {
4081 case 1: gen_helper_neon_shl_s16(var, var, shift); break;
4082 case 2: gen_helper_neon_shl_s32(var, var, shift); break;
4083 default: abort();
4084 }
4085 }
4086 }
4087}
4088
a7812ae4 4089static inline void gen_neon_widen(TCGv_i64 dest, TCGv src, int size, int u)
ad69471c
PB		 4090{
4091 if (u) {
4092 switch (size) {
4093 case 0: gen_helper_neon_widen_u8(dest, src); break;
4094 case 1: gen_helper_neon_widen_u16(dest, src); break;
4095 case 2: tcg_gen_extu_i32_i64(dest, src); break;
4096 default: abort();
4097 }
4098 } else {
4099 switch (size) {
4100 case 0: gen_helper_neon_widen_s8(dest, src); break;
4101 case 1: gen_helper_neon_widen_s16(dest, src); break;
4102 case 2: tcg_gen_ext_i32_i64(dest, src); break;
4103 default: abort();
4104 }
4105 }
7d1b0095 4106 tcg_temp_free_i32(src);
ad69471c
PB		 4107}
4108
4109static inline void gen_neon_addl(int size)
4110{
4111 switch (size) {
4112 case 0: gen_helper_neon_addl_u16(CPU_V001); break;
4113 case 1: gen_helper_neon_addl_u32(CPU_V001); break;
4114 case 2: tcg_gen_add_i64(CPU_V001); break;
4115 default: abort();
4116 }
4117}
4118
4119static inline void gen_neon_subl(int size)
4120{
4121 switch (size) {
4122 case 0: gen_helper_neon_subl_u16(CPU_V001); break;
4123 case 1: gen_helper_neon_subl_u32(CPU_V001); break;
4124 case 2: tcg_gen_sub_i64(CPU_V001); break;
4125 default: abort();
4126 }
4127}
4128
a7812ae4 4129static inline void gen_neon_negl(TCGv_i64 var, int size)
ad69471c
PB		 4130{
4131 switch (size) {
4132 case 0: gen_helper_neon_negl_u16(var, var); break;
4133 case 1: gen_helper_neon_negl_u32(var, var); break;
4134 case 2: gen_helper_neon_negl_u64(var, var); break;
4135 default: abort();
4136 }
4137}
4138
a7812ae4 4139static inline void gen_neon_addl_saturate(TCGv_i64 op0, TCGv_i64 op1, int size)
ad69471c
PB		 4140{
4141 switch (size) {
4142 case 1: gen_helper_neon_addl_saturate_s32(op0, cpu_env, op0, op1); break;
4143 case 2: gen_helper_neon_addl_saturate_s64(op0, cpu_env, op0, op1); break;
4144 default: abort();
4145 }
4146}
4147
a7812ae4 4148static inline void gen_neon_mull(TCGv_i64 dest, TCGv a, TCGv b, int size, int u)
ad69471c 4149{
a7812ae4 4150 TCGv_i64 tmp;
ad69471c
PB		 4151
4152 switch ((size << 1) | u) {
4153 case 0: gen_helper_neon_mull_s8(dest, a, b); break;
4154 case 1: gen_helper_neon_mull_u8(dest, a, b); break;
4155 case 2: gen_helper_neon_mull_s16(dest, a, b); break;
4156 case 3: gen_helper_neon_mull_u16(dest, a, b); break;
4157 case 4:
4158 tmp = gen_muls_i64_i32(a, b);
4159 tcg_gen_mov_i64(dest, tmp);
7d2aabe2 4160 tcg_temp_free_i64(tmp);
ad69471c
PB		 4161 break;
4162 case 5:
4163 tmp = gen_mulu_i64_i32(a, b);
4164 tcg_gen_mov_i64(dest, tmp);
7d2aabe2 4165 tcg_temp_free_i64(tmp);
ad69471c
PB		 4166 break;
4167 default: abort();
4168 }
c6067f04
CL		 4169
4170 /* gen_helper_neon_mull_[su]{8|16} do not free their parameters.
4171 Don't forget to clean them now. */
4172 if (size < 2) {
7d1b0095
PM		 4173 tcg_temp_free_i32(a);
4174 tcg_temp_free_i32(b);
c6067f04 4175 }
ad69471c
PB		 4176}
4177
c33171c7
PM		 4178static void gen_neon_narrow_op(int op, int u, int size, TCGv dest, TCGv_i64 src)
4179{
4180 if (op) {
4181 if (u) {
4182 gen_neon_unarrow_sats(size, dest, src);
4183 } else {
4184 gen_neon_narrow(size, dest, src);
4185 }
4186 } else {
4187 if (u) {
4188 gen_neon_narrow_satu(size, dest, src);
4189 } else {
4190 gen_neon_narrow_sats(size, dest, src);
4191 }
4192 }
4193}
4194
9ee6e8bb
PB		 4195/* Translate a NEON data processing instruction. Return nonzero if the
4196 instruction is invalid.
ad69471c
PB		 4197 We process data in a mixture of 32-bit and 64-bit chunks.
4198 Mostly we use 32-bit chunks so we can use normal scalar instructions. */
2c0262af 4199
9ee6e8bb
PB		 4200static int disas_neon_data_insn(CPUState * env, DisasContext *s, uint32_t insn)
4201{
4202 int op;
4203 int q;
4204 int rd, rn, rm;
4205 int size;
4206 int shift;
4207 int pass;
4208 int count;
4209 int pairwise;
4210 int u;
4211 int n;
ca9a32e4 4212 uint32_t imm, mask;
b75263d6 4213 TCGv tmp, tmp2, tmp3, tmp4, tmp5;
a7812ae4 4214 TCGv_i64 tmp64;
9ee6e8bb 4215
5df8bac1 4216 if (!s->vfp_enabled)
9ee6e8bb
PB		 4217 return 1;
4218 q = (insn & (1 << 6)) != 0;
4219 u = (insn >> 24) & 1;
4220 VFP_DREG_D(rd, insn);
4221 VFP_DREG_N(rn, insn);
4222 VFP_DREG_M(rm, insn);
4223 size = (insn >> 20) & 3;
4224 if ((insn & (1 << 23)) == 0) {
4225 /* Three register same length. */
4226 op = ((insn >> 7) & 0x1e) | ((insn >> 4) & 1);
ad69471c
PB		 4227 if (size == 3 && (op == 1 || op == 5 || op == 8 || op == 9
4228 || op == 10 || op == 11 || op == 16)) {
4229 /* 64-bit element instructions. */
9ee6e8bb 4230 for (pass = 0; pass < (q ? 2 : 1); pass++) {
ad69471c
PB		 4231 neon_load_reg64(cpu_V0, rn + pass);
4232 neon_load_reg64(cpu_V1, rm + pass);
9ee6e8bb
PB		 4233 switch (op) {
4234 case 1: /* VQADD */
4235 if (u) {
72902672
CL		 4236 gen_helper_neon_qadd_u64(cpu_V0, cpu_env,
4237 cpu_V0, cpu_V1);
2c0262af 4238 } else {
72902672
CL		 4239 gen_helper_neon_qadd_s64(cpu_V0, cpu_env,
4240 cpu_V0, cpu_V1);
2c0262af 4241 }
9ee6e8bb
PB		 4242 break;
4243 case 5: /* VQSUB */
4244 if (u) {
72902672
CL		 4245 gen_helper_neon_qsub_u64(cpu_V0, cpu_env,
4246 cpu_V0, cpu_V1);
ad69471c 4247 } else {
72902672
CL		 4248 gen_helper_neon_qsub_s64(cpu_V0, cpu_env,
4249 cpu_V0, cpu_V1);
ad69471c
PB		 4250 }
4251 break;
4252 case 8: /* VSHL */
4253 if (u) {
4254 gen_helper_neon_shl_u64(cpu_V0, cpu_V1, cpu_V0);
4255 } else {
4256 gen_helper_neon_shl_s64(cpu_V0, cpu_V1, cpu_V0);
4257 }
4258 break;
4259 case 9: /* VQSHL */
4260 if (u) {
4261 gen_helper_neon_qshl_u64(cpu_V0, cpu_env,
def126ce 4262 cpu_V1, cpu_V0);
ad69471c 4263 } else {
def126ce 4264 gen_helper_neon_qshl_s64(cpu_V0, cpu_env,
ad69471c
PB		 4265 cpu_V1, cpu_V0);
4266 }
4267 break;
4268 case 10: /* VRSHL */
4269 if (u) {
4270 gen_helper_neon_rshl_u64(cpu_V0, cpu_V1, cpu_V0);
1e8d4eec 4271 } else {
ad69471c
PB		 4272 gen_helper_neon_rshl_s64(cpu_V0, cpu_V1, cpu_V0);
4273 }
4274 break;
4275 case 11: /* VQRSHL */
4276 if (u) {
4277 gen_helper_neon_qrshl_u64(cpu_V0, cpu_env,
4278 cpu_V1, cpu_V0);
4279 } else {
4280 gen_helper_neon_qrshl_s64(cpu_V0, cpu_env,
4281 cpu_V1, cpu_V0);
1e8d4eec 4282 }
9ee6e8bb
PB		 4283 break;
4284 case 16:
4285 if (u) {
ad69471c 4286 tcg_gen_sub_i64(CPU_V001);
9ee6e8bb 4287 } else {
ad69471c 4288 tcg_gen_add_i64(CPU_V001);
9ee6e8bb
PB		 4289 }
4290 break;
4291 default:
4292 abort();
2c0262af 4293 }
ad69471c 4294 neon_store_reg64(cpu_V0, rd + pass);
2c0262af 4295 }
9ee6e8bb 4296 return 0;
2c0262af 4297 }
9ee6e8bb
PB		 4298 switch (op) {
4299 case 8: /* VSHL */
4300 case 9: /* VQSHL */
4301 case 10: /* VRSHL */
ad69471c 4302 case 11: /* VQRSHL */
9ee6e8bb 4303 {
ad69471c
PB		 4304 int rtmp;
4305 /* Shift instruction operands are reversed. */
4306 rtmp = rn;
9ee6e8bb 4307 rn = rm;
ad69471c 4308 rm = rtmp;
9ee6e8bb
PB		 4309 pairwise = 0;
4310 }
2c0262af 4311 break;
9ee6e8bb
PB		 4312 case 20: /* VPMAX */
4313 case 21: /* VPMIN */
4314 case 23: /* VPADD */
4315 pairwise = 1;
2c0262af 4316 break;
9ee6e8bb
PB		 4317 case 26: /* VPADD (float) */
4318 pairwise = (u && size < 2);
2c0262af 4319 break;
9ee6e8bb
PB		 4320 case 30: /* VPMIN/VPMAX (float) */
4321 pairwise = u;
2c0262af 4322 break;
9ee6e8bb
PB		 4323 default:
4324 pairwise = 0;
2c0262af 4325 break;
9ee6e8bb 4326 }
dd8fbd78 4327
9ee6e8bb
PB		 4328 for (pass = 0; pass < (q ? 4 : 2); pass++) {
4329
4330 if (pairwise) {
4331 /* Pairwise. */
4332 if (q)
4333 n = (pass & 1) * 2;
2c0262af 4334 else
9ee6e8bb
PB		 4335 n = 0;
4336 if (pass < q + 1) {
dd8fbd78
FN		 4337 tmp = neon_load_reg(rn, n);
4338 tmp2 = neon_load_reg(rn, n + 1);
9ee6e8bb 4339 } else {
dd8fbd78
FN		 4340 tmp = neon_load_reg(rm, n);
4341 tmp2 = neon_load_reg(rm, n + 1);
9ee6e8bb
PB		 4342 }
4343 } else {
4344 /* Elementwise. */
dd8fbd78
FN		 4345 tmp = neon_load_reg(rn, pass);
4346 tmp2 = neon_load_reg(rm, pass);
9ee6e8bb
PB		 4347 }
4348 switch (op) {
4349 case 0: /* VHADD */
4350 GEN_NEON_INTEGER_OP(hadd);
4351 break;
4352 case 1: /* VQADD */
ad69471c 4353 GEN_NEON_INTEGER_OP_ENV(qadd);
2c0262af 4354 break;
9ee6e8bb
PB		 4355 case 2: /* VRHADD */
4356 GEN_NEON_INTEGER_OP(rhadd);
2c0262af 4357 break;
9ee6e8bb
PB		 4358 case 3: /* Logic ops. */
4359 switch ((u << 2) | size) {
4360 case 0: /* VAND */
dd8fbd78 4361 tcg_gen_and_i32(tmp, tmp, tmp2);
9ee6e8bb
PB		 4362 break;
4363 case 1: /* BIC */
f669df27 4364 tcg_gen_andc_i32(tmp, tmp, tmp2);
9ee6e8bb
PB		 4365 break;
4366 case 2: /* VORR */
dd8fbd78 4367 tcg_gen_or_i32(tmp, tmp, tmp2);
9ee6e8bb
PB		 4368 break;
4369 case 3: /* VORN */
f669df27 4370 tcg_gen_orc_i32(tmp, tmp, tmp2);
9ee6e8bb
PB		 4371 break;
4372 case 4: /* VEOR */
dd8fbd78 4373 tcg_gen_xor_i32(tmp, tmp, tmp2);
9ee6e8bb
PB		 4374 break;
4375 case 5: /* VBSL */
dd8fbd78
FN		 4376 tmp3 = neon_load_reg(rd, pass);
4377 gen_neon_bsl(tmp, tmp, tmp2, tmp3);
7d1b0095 4378 tcg_temp_free_i32(tmp3);
9ee6e8bb
PB		 4379 break;
4380 case 6: /* VBIT */
dd8fbd78
FN		 4381 tmp3 = neon_load_reg(rd, pass);
4382 gen_neon_bsl(tmp, tmp, tmp3, tmp2);
7d1b0095 4383 tcg_temp_free_i32(tmp3);
9ee6e8bb
PB		 4384 break;
4385 case 7: /* VBIF */
dd8fbd78
FN		 4386 tmp3 = neon_load_reg(rd, pass);
4387 gen_neon_bsl(tmp, tmp3, tmp, tmp2);
7d1b0095 4388 tcg_temp_free_i32(tmp3);
9ee6e8bb 4389 break;
2c0262af
FB		 4390 }
4391 break;
9ee6e8bb
PB		 4392 case 4: /* VHSUB */
4393 GEN_NEON_INTEGER_OP(hsub);
4394 break;
4395 case 5: /* VQSUB */
ad69471c 4396 GEN_NEON_INTEGER_OP_ENV(qsub);
2c0262af 4397 break;
9ee6e8bb
PB		 4398 case 6: /* VCGT */
4399 GEN_NEON_INTEGER_OP(cgt);
4400 break;
4401 case 7: /* VCGE */
4402 GEN_NEON_INTEGER_OP(cge);
4403 break;
4404 case 8: /* VSHL */
ad69471c 4405 GEN_NEON_INTEGER_OP(shl);
2c0262af 4406 break;
9ee6e8bb 4407 case 9: /* VQSHL */
ad69471c 4408 GEN_NEON_INTEGER_OP_ENV(qshl);
2c0262af 4409 break;
9ee6e8bb 4410 case 10: /* VRSHL */
ad69471c 4411 GEN_NEON_INTEGER_OP(rshl);
2c0262af 4412 break;
9ee6e8bb 4413 case 11: /* VQRSHL */
ad69471c 4414 GEN_NEON_INTEGER_OP_ENV(qrshl);
9ee6e8bb
PB		 4415 break;
4416 case 12: /* VMAX */
4417 GEN_NEON_INTEGER_OP(max);
4418 break;
4419 case 13: /* VMIN */
4420 GEN_NEON_INTEGER_OP(min);
4421 break;
4422 case 14: /* VABD */
4423 GEN_NEON_INTEGER_OP(abd);
4424 break;
4425 case 15: /* VABA */
4426 GEN_NEON_INTEGER_OP(abd);
7d1b0095 4427 tcg_temp_free_i32(tmp2);
dd8fbd78
FN		 4428 tmp2 = neon_load_reg(rd, pass);
4429 gen_neon_add(size, tmp, tmp2);
9ee6e8bb
PB		 4430 break;
4431 case 16:
4432 if (!u) { /* VADD */
dd8fbd78 4433 if (gen_neon_add(size, tmp, tmp2))
9ee6e8bb
PB		 4434 return 1;
4435 } else { /* VSUB */
4436 switch (size) {
dd8fbd78
FN		 4437 case 0: gen_helper_neon_sub_u8(tmp, tmp, tmp2); break;
4438 case 1: gen_helper_neon_sub_u16(tmp, tmp, tmp2); break;
4439 case 2: tcg_gen_sub_i32(tmp, tmp, tmp2); break;
9ee6e8bb
PB		 4440 default: return 1;
4441 }
4442 }
4443 break;
4444 case 17:
4445 if (!u) { /* VTST */
4446 switch (size) {
dd8fbd78
FN		 4447 case 0: gen_helper_neon_tst_u8(tmp, tmp, tmp2); break;
4448 case 1: gen_helper_neon_tst_u16(tmp, tmp, tmp2); break;
4449 case 2: gen_helper_neon_tst_u32(tmp, tmp, tmp2); break;
9ee6e8bb
PB		 4450 default: return 1;
4451 }
4452 } else { /* VCEQ */
4453 switch (size) {
dd8fbd78
FN		 4454 case 0: gen_helper_neon_ceq_u8(tmp, tmp, tmp2); break;
4455 case 1: gen_helper_neon_ceq_u16(tmp, tmp, tmp2); break;
4456 case 2: gen_helper_neon_ceq_u32(tmp, tmp, tmp2); break;
9ee6e8bb
PB		 4457 default: return 1;
4458 }
4459 }
4460 break;
4461 case 18: /* Multiply. */
4462 switch (size) {
dd8fbd78
FN		 4463 case 0: gen_helper_neon_mul_u8(tmp, tmp, tmp2); break;
4464 case 1: gen_helper_neon_mul_u16(tmp, tmp, tmp2); break;
4465 case 2: tcg_gen_mul_i32(tmp, tmp, tmp2); break;
9ee6e8bb
PB		 4466 default: return 1;
4467 }
7d1b0095 4468 tcg_temp_free_i32(tmp2);
dd8fbd78 4469 tmp2 = neon_load_reg(rd, pass);
9ee6e8bb 4470 if (u) { /* VMLS */
dd8fbd78 4471 gen_neon_rsb(size, tmp, tmp2);
9ee6e8bb 4472 } else { /* VMLA */
dd8fbd78 4473 gen_neon_add(size, tmp, tmp2);
9ee6e8bb
PB		 4474 }
4475 break;
4476 case 19: /* VMUL */
4477 if (u) { /* polynomial */
dd8fbd78 4478 gen_helper_neon_mul_p8(tmp, tmp, tmp2);
9ee6e8bb
PB		 4479 } else { /* Integer */
4480 switch (size) {
dd8fbd78
FN		 4481 case 0: gen_helper_neon_mul_u8(tmp, tmp, tmp2); break;
4482 case 1: gen_helper_neon_mul_u16(tmp, tmp, tmp2); break;
4483 case 2: tcg_gen_mul_i32(tmp, tmp, tmp2); break;
9ee6e8bb
PB		 4484 default: return 1;
4485 }
4486 }
4487 break;
4488 case 20: /* VPMAX */
4489 GEN_NEON_INTEGER_OP(pmax);
4490 break;
4491 case 21: /* VPMIN */
4492 GEN_NEON_INTEGER_OP(pmin);
4493 break;
4494 case 22: /* Hultiply high. */
4495 if (!u) { /* VQDMULH */
4496 switch (size) {
dd8fbd78
FN		 4497 case 1: gen_helper_neon_qdmulh_s16(tmp, cpu_env, tmp, tmp2); break;
4498 case 2: gen_helper_neon_qdmulh_s32(tmp, cpu_env, tmp, tmp2); break;
9ee6e8bb
PB		 4499 default: return 1;
4500 }
4501 } else { /* VQRDHMUL */
4502 switch (size) {
dd8fbd78
FN		 4503 case 1: gen_helper_neon_qrdmulh_s16(tmp, cpu_env, tmp, tmp2); break;
4504 case 2: gen_helper_neon_qrdmulh_s32(tmp, cpu_env, tmp, tmp2); break;
9ee6e8bb
PB		 4505 default: return 1;
4506 }
4507 }
4508 break;
4509 case 23: /* VPADD */
4510 if (u)
4511 return 1;
4512 switch (size) {
dd8fbd78
FN		 4513 case 0: gen_helper_neon_padd_u8(tmp, tmp, tmp2); break;
4514 case 1: gen_helper_neon_padd_u16(tmp, tmp, tmp2); break;
4515 case 2: tcg_gen_add_i32(tmp, tmp, tmp2); break;
9ee6e8bb
PB		 4516 default: return 1;
4517 }
4518 break;
4519 case 26: /* Floating point arithnetic. */
4520 switch ((u << 2) | size) {
4521 case 0: /* VADD */
dd8fbd78 4522 gen_helper_neon_add_f32(tmp, tmp, tmp2);
9ee6e8bb
PB		 4523 break;
4524 case 2: /* VSUB */
dd8fbd78 4525 gen_helper_neon_sub_f32(tmp, tmp, tmp2);
9ee6e8bb
PB		 4526 break;
4527 case 4: /* VPADD */
dd8fbd78 4528 gen_helper_neon_add_f32(tmp, tmp, tmp2);
9ee6e8bb
PB		 4529 break;
4530 case 6: /* VABD */
dd8fbd78 4531 gen_helper_neon_abd_f32(tmp, tmp, tmp2);
9ee6e8bb
PB		 4532 break;
4533 default:
4534 return 1;
4535 }
4536 break;
4537 case 27: /* Float multiply. */
dd8fbd78 4538 gen_helper_neon_mul_f32(tmp, tmp, tmp2);
9ee6e8bb 4539 if (!u) {
7d1b0095 4540 tcg_temp_free_i32(tmp2);
dd8fbd78 4541 tmp2 = neon_load_reg(rd, pass);
9ee6e8bb 4542 if (size == 0) {
dd8fbd78 4543 gen_helper_neon_add_f32(tmp, tmp, tmp2);
9ee6e8bb 4544 } else {
dd8fbd78 4545 gen_helper_neon_sub_f32(tmp, tmp2, tmp);
9ee6e8bb
PB		 4546 }
4547 }
4548 break;
4549 case 28: /* Float compare. */
4550 if (!u) {
dd8fbd78 4551 gen_helper_neon_ceq_f32(tmp, tmp, tmp2);
b5ff1b31 4552 } else {
9ee6e8bb 4553 if (size == 0)
dd8fbd78 4554 gen_helper_neon_cge_f32(tmp, tmp, tmp2);
9ee6e8bb 4555 else
dd8fbd78 4556 gen_helper_neon_cgt_f32(tmp, tmp, tmp2);
b5ff1b31 4557 }
2c0262af 4558 break;
9ee6e8bb
PB		 4559 case 29: /* Float compare absolute. */
4560 if (!u)
4561 return 1;
4562 if (size == 0)
dd8fbd78 4563 gen_helper_neon_acge_f32(tmp, tmp, tmp2);
9ee6e8bb 4564 else
dd8fbd78 4565 gen_helper_neon_acgt_f32(tmp, tmp, tmp2);
2c0262af 4566 break;
9ee6e8bb
PB		 4567 case 30: /* Float min/max. */
4568 if (size == 0)
dd8fbd78 4569 gen_helper_neon_max_f32(tmp, tmp, tmp2);
9ee6e8bb 4570 else
dd8fbd78 4571 gen_helper_neon_min_f32(tmp, tmp, tmp2);
9ee6e8bb
PB		 4572 break;
4573 case 31:
4574 if (size == 0)
dd8fbd78 4575 gen_helper_recps_f32(tmp, tmp, tmp2, cpu_env);
9ee6e8bb 4576 else
dd8fbd78 4577 gen_helper_rsqrts_f32(tmp, tmp, tmp2, cpu_env);
2c0262af 4578 break;
9ee6e8bb
PB		 4579 default:
4580 abort();
2c0262af 4581 }
7d1b0095 4582 tcg_temp_free_i32(tmp2);
dd8fbd78 4583
9ee6e8bb
PB		 4584 /* Save the result. For elementwise operations we can put it
4585 straight into the destination register. For pairwise operations
4586 we have to be careful to avoid clobbering the source operands. */
4587 if (pairwise && rd == rm) {
dd8fbd78 4588 neon_store_scratch(pass, tmp);
9ee6e8bb 4589 } else {
dd8fbd78 4590 neon_store_reg(rd, pass, tmp);
9ee6e8bb
PB		 4591 }
4592
4593 } /* for pass */
4594 if (pairwise && rd == rm) {
4595 for (pass = 0; pass < (q ? 4 : 2); pass++) {
dd8fbd78
FN		 4596 tmp = neon_load_scratch(pass);
4597 neon_store_reg(rd, pass, tmp);
9ee6e8bb
PB		 4598 }
4599 }
ad69471c 4600 /* End of 3 register same size operations. */
9ee6e8bb
PB		 4601 } else if (insn & (1 << 4)) {
4602 if ((insn & 0x00380080) != 0) {
4603 /* Two registers and shift. */
4604 op = (insn >> 8) & 0xf;
4605 if (insn & (1 << 7)) {
4606 /* 64-bit shift. */
4607 size = 3;
4608 } else {
4609 size = 2;
4610 while ((insn & (1 << (size + 19))) == 0)
4611 size--;
4612 }
4613 shift = (insn >> 16) & ((1 << (3 + size)) - 1);
4614 /* To avoid excessive dumplication of ops we implement shift
4615 by immediate using the variable shift operations. */
4616 if (op < 8) {
4617 /* Shift by immediate:
4618 VSHR, VSRA, VRSHR, VRSRA, VSRI, VSHL, VQSHL, VQSHLU. */
4619 /* Right shifts are encoded as N - shift, where N is the
4620 element size in bits. */
4621 if (op <= 4)
4622 shift = shift - (1 << (size + 3));
9ee6e8bb
PB		 4623 if (size == 3) {
4624 count = q + 1;
4625 } else {
4626 count = q ? 4: 2;
4627 }
4628 switch (size) {
4629 case 0:
4630 imm = (uint8_t) shift;
4631 imm |= imm << 8;
4632 imm |= imm << 16;
4633 break;
4634 case 1:
4635 imm = (uint16_t) shift;
4636 imm |= imm << 16;
4637 break;
4638 case 2:
4639 case 3:
4640 imm = shift;
4641 break;
4642 default:
4643 abort();
4644 }
4645
4646 for (pass = 0; pass < count; pass++) {
ad69471c
PB		 4647 if (size == 3) {
4648 neon_load_reg64(cpu_V0, rm + pass);
4649 tcg_gen_movi_i64(cpu_V1, imm);
4650 switch (op) {
4651 case 0: /* VSHR */
4652 case 1: /* VSRA */
4653 if (u)
4654 gen_helper_neon_shl_u64(cpu_V0, cpu_V0, cpu_V1);
9ee6e8bb 4655 else
ad69471c 4656 gen_helper_neon_shl_s64(cpu_V0, cpu_V0, cpu_V1);
9ee6e8bb 4657 break;
ad69471c
PB		 4658 case 2: /* VRSHR */
4659 case 3: /* VRSRA */
4660 if (u)
4661 gen_helper_neon_rshl_u64(cpu_V0, cpu_V0, cpu_V1);
9ee6e8bb 4662 else
ad69471c 4663 gen_helper_neon_rshl_s64(cpu_V0, cpu_V0, cpu_V1);
9ee6e8bb 4664 break;
ad69471c
PB		 4665 case 4: /* VSRI */
4666 if (!u)
4667 return 1;
4668 gen_helper_neon_shl_u64(cpu_V0, cpu_V0, cpu_V1);
4669 break;
4670 case 5: /* VSHL, VSLI */
4671 gen_helper_neon_shl_u64(cpu_V0, cpu_V0, cpu_V1);
4672 break;
0322b26e
PM		 4673 case 6: /* VQSHLU */
4674 if (u) {
4675 gen_helper_neon_qshlu_s64(cpu_V0, cpu_env,
4676 cpu_V0, cpu_V1);
4677 } else {
4678 return 1;
4679 }
ad69471c 4680 break;
0322b26e
PM		 4681 case 7: /* VQSHL */
4682 if (u) {
4683 gen_helper_neon_qshl_u64(cpu_V0, cpu_env,
4684 cpu_V0, cpu_V1);
4685 } else {
4686 gen_helper_neon_qshl_s64(cpu_V0, cpu_env,
4687 cpu_V0, cpu_V1);
4688 }
9ee6e8bb 4689 break;
9ee6e8bb 4690 }
ad69471c
PB		 4691 if (op == 1 || op == 3) {
4692 /* Accumulate. */
5371cb81 4693 neon_load_reg64(cpu_V1, rd + pass);
ad69471c
PB		 4694 tcg_gen_add_i64(cpu_V0, cpu_V0, cpu_V1);
4695 } else if (op == 4 || (op == 5 && u)) {
4696 /* Insert */
923e6509
CL		 4697 neon_load_reg64(cpu_V1, rd + pass);
4698 uint64_t mask;
4699 if (shift < -63 || shift > 63) {
4700 mask = 0;
4701 } else {
4702 if (op == 4) {
4703 mask = 0xffffffffffffffffull >> -shift;
4704 } else {
4705 mask = 0xffffffffffffffffull << shift;
4706 }
4707 }
4708 tcg_gen_andi_i64(cpu_V1, cpu_V1, ~mask);
4709 tcg_gen_or_i64(cpu_V0, cpu_V0, cpu_V1);
ad69471c
PB		 4710 }
4711 neon_store_reg64(cpu_V0, rd + pass);
4712 } else { /* size < 3 */
4713 /* Operands in T0 and T1. */
dd8fbd78 4714 tmp = neon_load_reg(rm, pass);
7d1b0095 4715 tmp2 = tcg_temp_new_i32();
dd8fbd78 4716 tcg_gen_movi_i32(tmp2, imm);
ad69471c
PB		 4717 switch (op) {
4718 case 0: /* VSHR */
4719 case 1: /* VSRA */
4720 GEN_NEON_INTEGER_OP(shl);
4721 break;
4722 case 2: /* VRSHR */
4723 case 3: /* VRSRA */
4724 GEN_NEON_INTEGER_OP(rshl);
4725 break;
4726 case 4: /* VSRI */
4727 if (!u)
4728 return 1;
4729 GEN_NEON_INTEGER_OP(shl);
4730 break;
4731 case 5: /* VSHL, VSLI */
4732 switch (size) {
dd8fbd78
FN		 4733 case 0: gen_helper_neon_shl_u8(tmp, tmp, tmp2); break;
4734 case 1: gen_helper_neon_shl_u16(tmp, tmp, tmp2); break;
4735 case 2: gen_helper_neon_shl_u32(tmp, tmp, tmp2); break;
ad69471c
PB		 4736 default: return 1;
4737 }
4738 break;
0322b26e
PM		 4739 case 6: /* VQSHLU */
4740 if (!u) {
4741 return 1;
4742 }
ad69471c 4743 switch (size) {
0322b26e
PM		 4744 case 0:
4745 gen_helper_neon_qshlu_s8(tmp, cpu_env,
4746 tmp, tmp2);
4747 break;
4748 case 1:
4749 gen_helper_neon_qshlu_s16(tmp, cpu_env,
4750 tmp, tmp2);
4751 break;
4752 case 2:
4753 gen_helper_neon_qshlu_s32(tmp, cpu_env,
4754 tmp, tmp2);
4755 break;
4756 default:
4757 return 1;
ad69471c
PB		 4758 }
4759 break;
0322b26e
PM		 4760 case 7: /* VQSHL */
4761 GEN_NEON_INTEGER_OP_ENV(qshl);
4762 break;
ad69471c 4763 }
7d1b0095 4764 tcg_temp_free_i32(tmp2);
ad69471c
PB		 4765
4766 if (op == 1 || op == 3) {
4767 /* Accumulate. */
dd8fbd78 4768 tmp2 = neon_load_reg(rd, pass);
5371cb81 4769 gen_neon_add(size, tmp, tmp2);
7d1b0095 4770 tcg_temp_free_i32(tmp2);
ad69471c
PB		 4771 } else if (op == 4 || (op == 5 && u)) {
4772 /* Insert */
4773 switch (size) {
4774 case 0:
4775 if (op == 4)
ca9a32e4 4776 mask = 0xff >> -shift;
ad69471c 4777 else
ca9a32e4
JR		 4778 mask = (uint8_t)(0xff << shift);
4779 mask |= mask << 8;
4780 mask |= mask << 16;
ad69471c
PB		 4781 break;
4782 case 1:
4783 if (op == 4)
ca9a32e4 4784 mask = 0xffff >> -shift;
ad69471c 4785 else
ca9a32e4
JR		 4786 mask = (uint16_t)(0xffff << shift);
4787 mask |= mask << 16;
ad69471c
PB		 4788 break;
4789 case 2:
ca9a32e4
JR		 4790 if (shift < -31 || shift > 31) {
4791 mask = 0;
4792 } else {
4793 if (op == 4)
4794 mask = 0xffffffffu >> -shift;
4795 else
4796 mask = 0xffffffffu << shift;
4797 }
ad69471c
PB		 4798 break;
4799 default:
4800 abort();
4801 }
dd8fbd78 4802 tmp2 = neon_load_reg(rd, pass);
ca9a32e4
JR		 4803 tcg_gen_andi_i32(tmp, tmp, mask);
4804 tcg_gen_andi_i32(tmp2, tmp2, ~mask);
dd8fbd78 4805 tcg_gen_or_i32(tmp, tmp, tmp2);
7d1b0095 4806 tcg_temp_free_i32(tmp2);
ad69471c 4807 }
dd8fbd78 4808 neon_store_reg(rd, pass, tmp);
9ee6e8bb
PB		 4809 }
4810 } /* for pass */
4811 } else if (op < 10) {
ad69471c 4812 /* Shift by immediate and narrow:
9ee6e8bb 4813 VSHRN, VRSHRN, VQSHRN, VQRSHRN. */
0b36f4cd
CL		 4814 int input_unsigned = (op == 8) ? !u : u;
4815
9ee6e8bb
PB		 4816 shift = shift - (1 << (size + 3));
4817 size++;
92cdfaeb 4818 if (size == 3) {
a7812ae4 4819 tmp64 = tcg_const_i64(shift);
92cdfaeb
PM		 4820 neon_load_reg64(cpu_V0, rm);
4821 neon_load_reg64(cpu_V1, rm + 1);
4822 for (pass = 0; pass < 2; pass++) {
4823 TCGv_i64 in;
4824 if (pass == 0) {
4825 in = cpu_V0;
4826 } else {
4827 in = cpu_V1;
4828 }
ad69471c 4829 if (q) {
0b36f4cd 4830 if (input_unsigned) {
92cdfaeb 4831 gen_helper_neon_rshl_u64(cpu_V0, in, tmp64);
0b36f4cd 4832 } else {
92cdfaeb 4833 gen_helper_neon_rshl_s64(cpu_V0, in, tmp64);
0b36f4cd 4834 }
ad69471c 4835 } else {
0b36f4cd 4836 if (input_unsigned) {
92cdfaeb 4837 gen_helper_neon_shl_u64(cpu_V0, in, tmp64);
0b36f4cd 4838 } else {
92cdfaeb 4839 gen_helper_neon_shl_s64(cpu_V0, in, tmp64);
0b36f4cd 4840 }
ad69471c 4841 }
7d1b0095 4842 tmp = tcg_temp_new_i32();
92cdfaeb
PM		 4843 gen_neon_narrow_op(op == 8, u, size - 1, tmp, cpu_V0);
4844 neon_store_reg(rd, pass, tmp);
4845 } /* for pass */
4846 tcg_temp_free_i64(tmp64);
4847 } else {
4848 if (size == 1) {
4849 imm = (uint16_t)shift;
4850 imm |= imm << 16;
2c0262af 4851 } else {
92cdfaeb
PM		 4852 /* size == 2 */
4853 imm = (uint32_t)shift;
4854 }
4855 tmp2 = tcg_const_i32(imm);
4856 tmp4 = neon_load_reg(rm + 1, 0);
4857 tmp5 = neon_load_reg(rm + 1, 1);
4858 for (pass = 0; pass < 2; pass++) {
4859 if (pass == 0) {
4860 tmp = neon_load_reg(rm, 0);
4861 } else {
4862 tmp = tmp4;
4863 }
0b36f4cd
CL		 4864 gen_neon_shift_narrow(size, tmp, tmp2, q,
4865 input_unsigned);
92cdfaeb
PM		 4866 if (pass == 0) {
4867 tmp3 = neon_load_reg(rm, 1);
4868 } else {
4869 tmp3 = tmp5;
4870 }
0b36f4cd
CL		 4871 gen_neon_shift_narrow(size, tmp3, tmp2, q,
4872 input_unsigned);
36aa55dc 4873 tcg_gen_concat_i32_i64(cpu_V0, tmp, tmp3);
7d1b0095
PM		 4874 tcg_temp_free_i32(tmp);
4875 tcg_temp_free_i32(tmp3);
4876 tmp = tcg_temp_new_i32();
92cdfaeb
PM		 4877 gen_neon_narrow_op(op == 8, u, size - 1, tmp, cpu_V0);
4878 neon_store_reg(rd, pass, tmp);
4879 } /* for pass */
c6067f04 4880 tcg_temp_free_i32(tmp2);
b75263d6 4881 }
9ee6e8bb
PB		 4882 } else if (op == 10) {
4883 /* VSHLL */
ad69471c 4884 if (q || size == 3)
9ee6e8bb 4885 return 1;
ad69471c
PB		 4886 tmp = neon_load_reg(rm, 0);
4887 tmp2 = neon_load_reg(rm, 1);
9ee6e8bb 4888 for (pass = 0; pass < 2; pass++) {
ad69471c
PB		 4889 if (pass == 1)
4890 tmp = tmp2;
4891
4892 gen_neon_widen(cpu_V0, tmp, size, u);
9ee6e8bb 4893
9ee6e8bb
PB		 4894 if (shift != 0) {
4895 /* The shift is less than the width of the source
ad69471c
PB		 4896 type, so we can just shift the whole register. */
4897 tcg_gen_shli_i64(cpu_V0, cpu_V0, shift);
acdf01ef
CL		 4898 /* Widen the result of shift: we need to clear
4899 * the potential overflow bits resulting from
4900 * left bits of the narrow input appearing as
4901 * right bits of left the neighbour narrow
4902 * input. */
ad69471c
PB		 4903 if (size < 2 || !u) {
4904 uint64_t imm64;
4905 if (size == 0) {
4906 imm = (0xffu >> (8 - shift));
4907 imm |= imm << 16;
acdf01ef 4908 } else if (size == 1) {
ad69471c 4909 imm = 0xffff >> (16 - shift);
acdf01ef
CL		 4910 } else {
4911 /* size == 2 */
4912 imm = 0xffffffff >> (32 - shift);
4913 }
4914 if (size < 2) {
4915 imm64 = imm | (((uint64_t)imm) << 32);
4916 } else {
4917 imm64 = imm;
9ee6e8bb 4918 }
acdf01ef 4919 tcg_gen_andi_i64(cpu_V0, cpu_V0, ~imm64);
9ee6e8bb
PB		 4920 }
4921 }
ad69471c 4922 neon_store_reg64(cpu_V0, rd + pass);
9ee6e8bb 4923 }
f73534a5 4924 } else if (op >= 14) {
9ee6e8bb 4925 /* VCVT fixed-point. */
f73534a5
PM		 4926 /* We have already masked out the must-be-1 top bit of imm6,
4927 * hence this 32-shift where the ARM ARM has 64-imm6.
4928 */
4929 shift = 32 - shift;
9ee6e8bb 4930 for (pass = 0; pass < (q ? 4 : 2); pass++) {
4373f3ce 4931 tcg_gen_ld_f32(cpu_F0s, cpu_env, neon_reg_offset(rm, pass));
f73534a5 4932 if (!(op & 1)) {
9ee6e8bb 4933 if (u)
4373f3ce 4934 gen_vfp_ulto(0, shift);
9ee6e8bb 4935 else
4373f3ce 4936 gen_vfp_slto(0, shift);
9ee6e8bb
PB		 4937 } else {
4938 if (u)
4373f3ce 4939 gen_vfp_toul(0, shift);
9ee6e8bb 4940 else
4373f3ce 4941 gen_vfp_tosl(0, shift);
2c0262af 4942 }
4373f3ce 4943 tcg_gen_st_f32(cpu_F0s, cpu_env, neon_reg_offset(rd, pass));
2c0262af
FB		 4944 }
4945 } else {
9ee6e8bb
PB		 4946 return 1;
4947 }
4948 } else { /* (insn & 0x00380080) == 0 */
4949 int invert;
4950
4951 op = (insn >> 8) & 0xf;
4952 /* One register and immediate. */
4953 imm = (u << 7) | ((insn >> 12) & 0x70) | (insn & 0xf);
4954 invert = (insn & (1 << 5)) != 0;
4955 switch (op) {
4956 case 0: case 1:
4957 /* no-op */
4958 break;
4959 case 2: case 3:
4960 imm <<= 8;
4961 break;
4962 case 4: case 5:
4963 imm <<= 16;
4964 break;
4965 case 6: case 7:
4966 imm <<= 24;
4967 break;
4968 case 8: case 9:
4969 imm |= imm << 16;
4970 break;
4971 case 10: case 11:
4972 imm = (imm << 8) | (imm << 24);
4973 break;
4974 case 12:
8e31209e 4975 imm = (imm << 8) | 0xff;
9ee6e8bb
PB		 4976 break;
4977 case 13:
4978 imm = (imm << 16) | 0xffff;
4979 break;
4980 case 14:
4981 imm |= (imm << 8) | (imm << 16) | (imm << 24);
4982 if (invert)
4983 imm = ~imm;
4984 break;
4985 case 15:
4986 imm = ((imm & 0x80) << 24) | ((imm & 0x3f) << 19)
4987 | ((imm & 0x40) ? (0x1f << 25) : (1 << 30));
4988 break;
4989 }
4990 if (invert)
4991 imm = ~imm;
4992
9ee6e8bb
PB		 4993 for (pass = 0; pass < (q ? 4 : 2); pass++) {
4994 if (op & 1 && op < 12) {
ad69471c 4995 tmp = neon_load_reg(rd, pass);
9ee6e8bb
PB		 4996 if (invert) {
4997 /* The immediate value has already been inverted, so
4998 BIC becomes AND. */
ad69471c 4999 tcg_gen_andi_i32(tmp, tmp, imm);
9ee6e8bb 5000 } else {
ad69471c 5001 tcg_gen_ori_i32(tmp, tmp, imm);
9ee6e8bb 5002 }
9ee6e8bb 5003 } else {
ad69471c 5004 /* VMOV, VMVN. */
7d1b0095 5005 tmp = tcg_temp_new_i32();
9ee6e8bb 5006 if (op == 14 && invert) {
ad69471c
PB		 5007 uint32_t val;
5008 val = 0;
9ee6e8bb
PB		 5009 for (n = 0; n < 4; n++) {
5010 if (imm & (1 << (n + (pass & 1) * 4)))
ad69471c 5011 val |= 0xff << (n * 8);
9ee6e8bb 5012 }
ad69471c
PB		 5013 tcg_gen_movi_i32(tmp, val);
5014 } else {
5015 tcg_gen_movi_i32(tmp, imm);
9ee6e8bb 5016 }
9ee6e8bb 5017 }
ad69471c 5018 neon_store_reg(rd, pass, tmp);
9ee6e8bb
PB		 5019 }
5020 }
e4b3861d 5021 } else { /* (insn & 0x00800010 == 0x00800000) */
9ee6e8bb
PB		 5022 if (size != 3) {
5023 op = (insn >> 8) & 0xf;
5024 if ((insn & (1 << 6)) == 0) {
5025 /* Three registers of different lengths. */
5026 int src1_wide;
5027 int src2_wide;
5028 int prewiden;
5029 /* prewiden, src1_wide, src2_wide */
5030 static const int neon_3reg_wide[16][3] = {
5031 {1, 0, 0}, /* VADDL */
5032 {1, 1, 0}, /* VADDW */
5033 {1, 0, 0}, /* VSUBL */
5034 {1, 1, 0}, /* VSUBW */
5035 {0, 1, 1}, /* VADDHN */
5036 {0, 0, 0}, /* VABAL */
5037 {0, 1, 1}, /* VSUBHN */
5038 {0, 0, 0}, /* VABDL */
5039 {0, 0, 0}, /* VMLAL */
5040 {0, 0, 0}, /* VQDMLAL */
5041 {0, 0, 0}, /* VMLSL */
5042 {0, 0, 0}, /* VQDMLSL */
5043 {0, 0, 0}, /* Integer VMULL */
5044 {0, 0, 0}, /* VQDMULL */
5045 {0, 0, 0} /* Polynomial VMULL */
5046 };
5047
5048 prewiden = neon_3reg_wide[op][0];
5049 src1_wide = neon_3reg_wide[op][1];
5050 src2_wide = neon_3reg_wide[op][2];
5051
ad69471c
PB		 5052 if (size == 0 && (op == 9 || op == 11 || op == 13))
5053 return 1;
5054
9ee6e8bb
PB		 5055 /* Avoid overlapping operands. Wide source operands are
5056 always aligned so will never overlap with wide
5057 destinations in problematic ways. */
8f8e3aa4 5058 if (rd == rm && !src2_wide) {
dd8fbd78
FN		 5059 tmp = neon_load_reg(rm, 1);
5060 neon_store_scratch(2, tmp);
8f8e3aa4 5061 } else if (rd == rn && !src1_wide) {
dd8fbd78
FN		 5062 tmp = neon_load_reg(rn, 1);
5063 neon_store_scratch(2, tmp);
9ee6e8bb 5064 }
a50f5b91 5065 TCGV_UNUSED(tmp3);
9ee6e8bb 5066 for (pass = 0; pass < 2; pass++) {
ad69471c
PB		 5067 if (src1_wide) {
5068 neon_load_reg64(cpu_V0, rn + pass);
a50f5b91 5069 TCGV_UNUSED(tmp);
9ee6e8bb 5070 } else {
ad69471c 5071 if (pass == 1 && rd == rn) {
dd8fbd78 5072 tmp = neon_load_scratch(2);
9ee6e8bb 5073 } else {
ad69471c
PB		 5074 tmp = neon_load_reg(rn, pass);
5075 }
5076 if (prewiden) {
5077 gen_neon_widen(cpu_V0, tmp, size, u);
9ee6e8bb
PB		 5078 }
5079 }
ad69471c
PB		 5080 if (src2_wide) {
5081 neon_load_reg64(cpu_V1, rm + pass);
a50f5b91 5082 TCGV_UNUSED(tmp2);
9ee6e8bb 5083 } else {
ad69471c 5084 if (pass == 1 && rd == rm) {
dd8fbd78 5085 tmp2 = neon_load_scratch(2);
9ee6e8bb 5086 } else {
ad69471c
PB		 5087 tmp2 = neon_load_reg(rm, pass);
5088 }
5089 if (prewiden) {
5090 gen_neon_widen(cpu_V1, tmp2, size, u);
9ee6e8bb 5091 }
9ee6e8bb
PB		 5092 }
5093 switch (op) {
5094 case 0: case 1: case 4: /* VADDL, VADDW, VADDHN, VRADDHN */
ad69471c 5095 gen_neon_addl(size);
9ee6e8bb 5096 break;
79b0e534 5097 case 2: case 3: case 6: /* VSUBL, VSUBW, VSUBHN, VRSUBHN */
ad69471c 5098 gen_neon_subl(size);
9ee6e8bb
PB		 5099 break;
5100 case 5: case 7: /* VABAL, VABDL */
5101 switch ((size << 1) | u) {
ad69471c
PB		 5102 case 0:
5103 gen_helper_neon_abdl_s16(cpu_V0, tmp, tmp2);
5104 break;
5105 case 1:
5106 gen_helper_neon_abdl_u16(cpu_V0, tmp, tmp2);
5107 break;
5108 case 2:
5109 gen_helper_neon_abdl_s32(cpu_V0, tmp, tmp2);
5110 break;
5111 case 3:
5112 gen_helper_neon_abdl_u32(cpu_V0, tmp, tmp2);
5113 break;
5114 case 4:
5115 gen_helper_neon_abdl_s64(cpu_V0, tmp, tmp2);
5116 break;
5117 case 5:
5118 gen_helper_neon_abdl_u64(cpu_V0, tmp, tmp2);
5119 break;
9ee6e8bb
PB		 5120 default: abort();
5121 }
7d1b0095
PM		 5122 tcg_temp_free_i32(tmp2);
5123 tcg_temp_free_i32(tmp);
9ee6e8bb
PB		 5124 break;
5125 case 8: case 9: case 10: case 11: case 12: case 13:
5126 /* VMLAL, VQDMLAL, VMLSL, VQDMLSL, VMULL, VQDMULL */
ad69471c 5127 gen_neon_mull(cpu_V0, tmp, tmp2, size, u);
9ee6e8bb
PB		 5128 break;
5129 case 14: /* Polynomial VMULL */
e5ca24cb 5130 gen_helper_neon_mull_p8(cpu_V0, tmp, tmp2);
7d1b0095
PM		 5131 tcg_temp_free_i32(tmp2);
5132 tcg_temp_free_i32(tmp);
e5ca24cb 5133 break;
9ee6e8bb
PB		 5134 default: /* 15 is RESERVED. */
5135 return 1;
5136 }
ebcd88ce
PM		 5137 if (op == 13) {
5138 /* VQDMULL */
5139 gen_neon_addl_saturate(cpu_V0, cpu_V0, size);
5140 neon_store_reg64(cpu_V0, rd + pass);
5141 } else if (op == 5 || (op >= 8 && op <= 11)) {
9ee6e8bb 5142 /* Accumulate. */
ebcd88ce 5143 neon_load_reg64(cpu_V1, rd + pass);
9ee6e8bb 5144 switch (op) {
4dc064e6
PM		 5145 case 10: /* VMLSL */
5146 gen_neon_negl(cpu_V0, size);
5147 /* Fall through */
5148 case 5: case 8: /* VABAL, VMLAL */
ad69471c 5149 gen_neon_addl(size);
9ee6e8bb
PB		 5150 break;
5151 case 9: case 11: /* VQDMLAL, VQDMLSL */
ad69471c 5152 gen_neon_addl_saturate(cpu_V0, cpu_V0, size);
4dc064e6
PM		 5153 if (op == 11) {
5154 gen_neon_negl(cpu_V0, size);
5155 }
ad69471c
PB		 5156 gen_neon_addl_saturate(cpu_V0, cpu_V1, size);
5157 break;
9ee6e8bb
PB		 5158 default:
5159 abort();
5160 }
ad69471c 5161 neon_store_reg64(cpu_V0, rd + pass);
9ee6e8bb
PB		 5162 } else if (op == 4 || op == 6) {
5163 /* Narrowing operation. */
7d1b0095 5164 tmp = tcg_temp_new_i32();
79b0e534 5165 if (!u) {
9ee6e8bb 5166 switch (size) {
ad69471c
PB		 5167 case 0:
5168 gen_helper_neon_narrow_high_u8(tmp, cpu_V0);
5169 break;
5170 case 1:
5171 gen_helper_neon_narrow_high_u16(tmp, cpu_V0);
5172 break;
5173 case 2:
5174 tcg_gen_shri_i64(cpu_V0, cpu_V0, 32);
5175 tcg_gen_trunc_i64_i32(tmp, cpu_V0);
5176 break;
9ee6e8bb
PB		 5177 default: abort();
5178 }
5179 } else {
5180 switch (size) {
ad69471c
PB		 5181 case 0:
5182 gen_helper_neon_narrow_round_high_u8(tmp, cpu_V0);
5183 break;
5184 case 1:
5185 gen_helper_neon_narrow_round_high_u16(tmp, cpu_V0);
5186 break;
5187 case 2:
5188 tcg_gen_addi_i64(cpu_V0, cpu_V0, 1u << 31);
5189 tcg_gen_shri_i64(cpu_V0, cpu_V0, 32);
5190 tcg_gen_trunc_i64_i32(tmp, cpu_V0);
5191 break;
9ee6e8bb
PB		 5192 default: abort();
5193 }
5194 }
ad69471c
PB		 5195 if (pass == 0) {
5196 tmp3 = tmp;
5197 } else {
5198 neon_store_reg(rd, 0, tmp3);
5199 neon_store_reg(rd, 1, tmp);
5200 }
9ee6e8bb
PB		 5201 } else {
5202 /* Write back the result. */
ad69471c 5203 neon_store_reg64(cpu_V0, rd + pass);
9ee6e8bb
PB		 5204 }
5205 }
5206 } else {
5207 /* Two registers and a scalar. */
5208 switch (op) {
5209 case 0: /* Integer VMLA scalar */
5210 case 1: /* Float VMLA scalar */
5211 case 4: /* Integer VMLS scalar */
5212 case 5: /* Floating point VMLS scalar */
5213 case 8: /* Integer VMUL scalar */
5214 case 9: /* Floating point VMUL scalar */
5215 case 12: /* VQDMULH scalar */
5216 case 13: /* VQRDMULH scalar */
dd8fbd78
FN		 5217 tmp = neon_get_scalar(size, rm);
5218 neon_store_scratch(0, tmp);
9ee6e8bb 5219 for (pass = 0; pass < (u ? 4 : 2); pass++) {
dd8fbd78
FN		 5220 tmp = neon_load_scratch(0);
5221 tmp2 = neon_load_reg(rn, pass);
9ee6e8bb
PB		 5222 if (op == 12) {
5223 if (size == 1) {
dd8fbd78 5224 gen_helper_neon_qdmulh_s16(tmp, cpu_env, tmp, tmp2);
9ee6e8bb 5225 } else {
dd8fbd78 5226 gen_helper_neon_qdmulh_s32(tmp, cpu_env, tmp, tmp2);
9ee6e8bb
PB		 5227 }
5228 } else if (op == 13) {
5229 if (size == 1) {
dd8fbd78 5230 gen_helper_neon_qrdmulh_s16(tmp, cpu_env, tmp, tmp2);
9ee6e8bb 5231 } else {
dd8fbd78 5232 gen_helper_neon_qrdmulh_s32(tmp, cpu_env, tmp, tmp2);
9ee6e8bb
PB		 5233 }
5234 } else if (op & 1) {
dd8fbd78 5235 gen_helper_neon_mul_f32(tmp, tmp, tmp2);
9ee6e8bb
PB		 5236 } else {
5237 switch (size) {
dd8fbd78
FN		 5238 case 0: gen_helper_neon_mul_u8(tmp, tmp, tmp2); break;
5239 case 1: gen_helper_neon_mul_u16(tmp, tmp, tmp2); break;
5240 case 2: tcg_gen_mul_i32(tmp, tmp, tmp2); break;
9ee6e8bb
PB		 5241 default: return 1;
5242 }
5243 }
7d1b0095 5244 tcg_temp_free_i32(tmp2);
9ee6e8bb
PB		 5245 if (op < 8) {
5246 /* Accumulate. */
dd8fbd78 5247 tmp2 = neon_load_reg(rd, pass);
9ee6e8bb
PB		 5248 switch (op) {
5249 case 0:
dd8fbd78 5250 gen_neon_add(size, tmp, tmp2);
9ee6e8bb
PB		 5251 break;
5252 case 1:
dd8fbd78 5253 gen_helper_neon_add_f32(tmp, tmp, tmp2);
9ee6e8bb
PB		 5254 break;
5255 case 4:
dd8fbd78 5256 gen_neon_rsb(size, tmp, tmp2);
9ee6e8bb
PB		 5257 break;
5258 case 5:
dd8fbd78 5259 gen_helper_neon_sub_f32(tmp, tmp2, tmp);
9ee6e8bb
PB		 5260 break;
5261 default:
5262 abort();
5263 }
7d1b0095 5264 tcg_temp_free_i32(tmp2);
9ee6e8bb 5265 }
dd8fbd78 5266 neon_store_reg(rd, pass, tmp);
9ee6e8bb
PB		 5267 }
5268 break;
5269 case 2: /* VMLAL sclar */
5270 case 3: /* VQDMLAL scalar */
5271 case 6: /* VMLSL scalar */
5272 case 7: /* VQDMLSL scalar */
5273 case 10: /* VMULL scalar */
5274 case 11: /* VQDMULL scalar */
ad69471c
PB		 5275 if (size == 0 && (op == 3 || op == 7 || op == 11))
5276 return 1;
5277
dd8fbd78 5278 tmp2 = neon_get_scalar(size, rm);
c6067f04
CL		 5279 /* We need a copy of tmp2 because gen_neon_mull
5280 * deletes it during pass 0. */
7d1b0095 5281 tmp4 = tcg_temp_new_i32();
c6067f04 5282 tcg_gen_mov_i32(tmp4, tmp2);
dd8fbd78 5283 tmp3 = neon_load_reg(rn, 1);
ad69471c 5284
9ee6e8bb 5285 for (pass = 0; pass < 2; pass++) {
ad69471c
PB		 5286 if (pass == 0) {
5287 tmp = neon_load_reg(rn, 0);
9ee6e8bb 5288 } else {
dd8fbd78 5289 tmp = tmp3;
c6067f04 5290 tmp2 = tmp4;
9ee6e8bb 5291 }
ad69471c 5292 gen_neon_mull(cpu_V0, tmp, tmp2, size, u);
ad69471c
PB		 5293 if (op != 11) {
5294 neon_load_reg64(cpu_V1, rd + pass);
9ee6e8bb 5295 }
9ee6e8bb 5296 switch (op) {
4dc064e6
PM		 5297 case 6:
5298 gen_neon_negl(cpu_V0, size);
5299 /* Fall through */
5300 case 2:
ad69471c 5301 gen_neon_addl(size);
9ee6e8bb
PB		 5302 break;
5303 case 3: case 7:
ad69471c 5304 gen_neon_addl_saturate(cpu_V0, cpu_V0, size);
4dc064e6
PM		 5305 if (op == 7) {
5306 gen_neon_negl(cpu_V0, size);
5307 }
ad69471c 5308 gen_neon_addl_saturate(cpu_V0, cpu_V1, size);
9ee6e8bb
PB		 5309 break;
5310 case 10:
5311 /* no-op */
5312 break;
5313 case 11:
ad69471c 5314 gen_neon_addl_saturate(cpu_V0, cpu_V0, size);
9ee6e8bb
PB		 5315 break;
5316 default:
5317 abort();
5318 }
ad69471c 5319 neon_store_reg64(cpu_V0, rd + pass);
9ee6e8bb 5320 }
dd8fbd78 5321
dd8fbd78 5322
9ee6e8bb
PB		 5323 break;
5324 default: /* 14 and 15 are RESERVED */
5325 return 1;
5326 }
5327 }
5328 } else { /* size == 3 */
5329 if (!u) {
5330 /* Extract. */
9ee6e8bb 5331 imm = (insn >> 8) & 0xf;
ad69471c
PB		 5332
5333 if (imm > 7 && !q)
5334 return 1;
5335
5336 if (imm == 0) {
5337 neon_load_reg64(cpu_V0, rn);
5338 if (q) {
5339 neon_load_reg64(cpu_V1, rn + 1);
9ee6e8bb 5340 }
ad69471c
PB		 5341 } else if (imm == 8) {
5342 neon_load_reg64(cpu_V0, rn + 1);
5343 if (q) {
5344 neon_load_reg64(cpu_V1, rm);
9ee6e8bb 5345 }
ad69471c 5346 } else if (q) {
a7812ae4 5347 tmp64 = tcg_temp_new_i64();
ad69471c
PB		 5348 if (imm < 8) {
5349 neon_load_reg64(cpu_V0, rn);
a7812ae4 5350 neon_load_reg64(tmp64, rn + 1);
ad69471c
PB		 5351 } else {
5352 neon_load_reg64(cpu_V0, rn + 1);
a7812ae4 5353 neon_load_reg64(tmp64, rm);
ad69471c
PB		 5354 }
5355 tcg_gen_shri_i64(cpu_V0, cpu_V0, (imm & 7) * 8);
a7812ae4 5356 tcg_gen_shli_i64(cpu_V1, tmp64, 64 - ((imm & 7) * 8));
ad69471c
PB		 5357 tcg_gen_or_i64(cpu_V0, cpu_V0, cpu_V1);
5358 if (imm < 8) {
5359 neon_load_reg64(cpu_V1, rm);
9ee6e8bb 5360 } else {
ad69471c
PB		 5361 neon_load_reg64(cpu_V1, rm + 1);
5362 imm -= 8;
9ee6e8bb 5363 }
ad69471c 5364 tcg_gen_shli_i64(cpu_V1, cpu_V1, 64 - (imm * 8));
a7812ae4
PB		 5365 tcg_gen_shri_i64(tmp64, tmp64, imm * 8);
5366 tcg_gen_or_i64(cpu_V1, cpu_V1, tmp64);
b75263d6 5367 tcg_temp_free_i64(tmp64);
ad69471c 5368 } else {
a7812ae4 5369 /* BUGFIX */
ad69471c 5370 neon_load_reg64(cpu_V0, rn);
a7812ae4 5371 tcg_gen_shri_i64(cpu_V0, cpu_V0, imm * 8);
ad69471c 5372 neon_load_reg64(cpu_V1, rm);
a7812ae4 5373 tcg_gen_shli_i64(cpu_V1, cpu_V1, 64 - (imm * 8));
ad69471c
PB		 5374 tcg_gen_or_i64(cpu_V0, cpu_V0, cpu_V1);
5375 }
5376 neon_store_reg64(cpu_V0, rd);
5377 if (q) {
5378 neon_store_reg64(cpu_V1, rd + 1);
9ee6e8bb
PB		 5379 }
5380 } else if ((insn & (1 << 11)) == 0) {
5381 /* Two register misc. */
5382 op = ((insn >> 12) & 0x30) | ((insn >> 7) & 0xf);
5383 size = (insn >> 18) & 3;
5384 switch (op) {
5385 case 0: /* VREV64 */
5386 if (size == 3)
5387 return 1;
5388 for (pass = 0; pass < (q ? 2 : 1); pass++) {
dd8fbd78
FN		 5389 tmp = neon_load_reg(rm, pass * 2);
5390 tmp2 = neon_load_reg(rm, pass * 2 + 1);
9ee6e8bb 5391 switch (size) {
dd8fbd78
FN		 5392 case 0: tcg_gen_bswap32_i32(tmp, tmp); break;
5393 case 1: gen_swap_half(tmp); break;
9ee6e8bb
PB		 5394 case 2: /* no-op */ break;
5395 default: abort();
5396 }
dd8fbd78 5397 neon_store_reg(rd, pass * 2 + 1, tmp);
9ee6e8bb 5398 if (size == 2) {
dd8fbd78 5399 neon_store_reg(rd, pass * 2, tmp2);
9ee6e8bb 5400 } else {
9ee6e8bb 5401 switch (size) {
dd8fbd78
FN		 5402 case 0: tcg_gen_bswap32_i32(tmp2, tmp2); break;
5403 case 1: gen_swap_half(tmp2); break;
9ee6e8bb
PB		 5404 default: abort();
5405 }
dd8fbd78 5406 neon_store_reg(rd, pass * 2, tmp2);
9ee6e8bb
PB		 5407 }
5408 }
5409 break;
5410 case 4: case 5: /* VPADDL */
5411 case 12: case 13: /* VPADAL */
9ee6e8bb
PB		 5412 if (size == 3)
5413 return 1;
ad69471c
PB		 5414 for (pass = 0; pass < q + 1; pass++) {
5415 tmp = neon_load_reg(rm, pass * 2);
5416 gen_neon_widen(cpu_V0, tmp, size, op & 1);
5417 tmp = neon_load_reg(rm, pass * 2 + 1);
5418 gen_neon_widen(cpu_V1, tmp, size, op & 1);
5419 switch (size) {
5420 case 0: gen_helper_neon_paddl_u16(CPU_V001); break;
5421 case 1: gen_helper_neon_paddl_u32(CPU_V001); break;
5422 case 2: tcg_gen_add_i64(CPU_V001); break;
5423 default: abort();
5424 }
9ee6e8bb
PB		 5425 if (op >= 12) {
5426 /* Accumulate. */
ad69471c
PB		 5427 neon_load_reg64(cpu_V1, rd + pass);
5428 gen_neon_addl(size);
9ee6e8bb 5429 }
ad69471c 5430 neon_store_reg64(cpu_V0, rd + pass);
9ee6e8bb
PB		 5431 }
5432 break;
5433 case 33: /* VTRN */
5434 if (size == 2) {
5435 for (n = 0; n < (q ? 4 : 2); n += 2) {
dd8fbd78
FN		 5436 tmp = neon_load_reg(rm, n);
5437 tmp2 = neon_load_reg(rd, n + 1);
5438 neon_store_reg(rm, n, tmp2);
5439 neon_store_reg(rd, n + 1, tmp);
9ee6e8bb
PB		 5440 }
5441 } else {
5442 goto elementwise;
5443 }
5444 break;
5445 case 34: /* VUZP */
02acedf9 5446 if (gen_neon_unzip(rd, rm, size, q)) {
9ee6e8bb 5447 return 1;
9ee6e8bb
PB		 5448 }
5449 break;
5450 case 35: /* VZIP */
d68a6f3a 5451 if (gen_neon_zip(rd, rm, size, q)) {
9ee6e8bb 5452 return 1;
9ee6e8bb
PB		 5453 }
5454 break;
5455 case 36: case 37: /* VMOVN, VQMOVUN, VQMOVN */
ad69471c
PB		 5456 if (size == 3)
5457 return 1;
a50f5b91 5458 TCGV_UNUSED(tmp2);
9ee6e8bb 5459 for (pass = 0; pass < 2; pass++) {
ad69471c 5460 neon_load_reg64(cpu_V0, rm + pass);
7d1b0095 5461 tmp = tcg_temp_new_i32();
c33171c7 5462 gen_neon_narrow_op(op == 36, q, size, tmp, cpu_V0);
ad69471c
PB		 5463 if (pass == 0) {
5464 tmp2 = tmp;
5465 } else {
5466 neon_store_reg(rd, 0, tmp2);
5467 neon_store_reg(rd, 1, tmp);
9ee6e8bb 5468 }
9ee6e8bb
PB		 5469 }
5470 break;
5471 case 38: /* VSHLL */
ad69471c 5472 if (q || size == 3)
9ee6e8bb 5473 return 1;
ad69471c
PB		 5474 tmp = neon_load_reg(rm, 0);
5475 tmp2 = neon_load_reg(rm, 1);
9ee6e8bb 5476 for (pass = 0; pass < 2; pass++) {
ad69471c
PB		 5477 if (pass == 1)
5478 tmp = tmp2;
5479 gen_neon_widen(cpu_V0, tmp, size, 1);
30d11a2a 5480 tcg_gen_shli_i64(cpu_V0, cpu_V0, 8 << size);
ad69471c 5481 neon_store_reg64(cpu_V0, rd + pass);
9ee6e8bb
PB		 5482 }
5483 break;
60011498
PB		 5484 case 44: /* VCVT.F16.F32 */
5485 if (!arm_feature(env, ARM_FEATURE_VFP_FP16))
5486 return 1;
7d1b0095
PM		 5487 tmp = tcg_temp_new_i32();
5488 tmp2 = tcg_temp_new_i32();
60011498 5489 tcg_gen_ld_f32(cpu_F0s, cpu_env, neon_reg_offset(rm, 0));
2d981da7 5490 gen_helper_neon_fcvt_f32_to_f16(tmp, cpu_F0s, cpu_env);
60011498 5491 tcg_gen_ld_f32(cpu_F0s, cpu_env, neon_reg_offset(rm, 1));
2d981da7 5492 gen_helper_neon_fcvt_f32_to_f16(tmp2, cpu_F0s, cpu_env);
60011498
PB		 5493 tcg_gen_shli_i32(tmp2, tmp2, 16);
5494 tcg_gen_or_i32(tmp2, tmp2, tmp);
5495 tcg_gen_ld_f32(cpu_F0s, cpu_env, neon_reg_offset(rm, 2));
2d981da7 5496 gen_helper_neon_fcvt_f32_to_f16(tmp, cpu_F0s, cpu_env);
60011498
PB		 5497 tcg_gen_ld_f32(cpu_F0s, cpu_env, neon_reg_offset(rm, 3));
5498 neon_store_reg(rd, 0, tmp2);
7d1b0095 5499 tmp2 = tcg_temp_new_i32();
2d981da7 5500 gen_helper_neon_fcvt_f32_to_f16(tmp2, cpu_F0s, cpu_env);
60011498
PB		 5501 tcg_gen_shli_i32(tmp2, tmp2, 16);
5502 tcg_gen_or_i32(tmp2, tmp2, tmp);
5503 neon_store_reg(rd, 1, tmp2);
7d1b0095 5504 tcg_temp_free_i32(tmp);
60011498
PB		 5505 break;
5506 case 46: /* VCVT.F32.F16 */
5507 if (!arm_feature(env, ARM_FEATURE_VFP_FP16))
5508 return 1;
7d1b0095 5509 tmp3 = tcg_temp_new_i32();
60011498
PB		 5510 tmp = neon_load_reg(rm, 0);
5511 tmp2 = neon_load_reg(rm, 1);
5512 tcg_gen_ext16u_i32(tmp3, tmp);
2d981da7 5513 gen_helper_neon_fcvt_f16_to_f32(cpu_F0s, tmp3, cpu_env);
60011498
PB		 5514 tcg_gen_st_f32(cpu_F0s, cpu_env, neon_reg_offset(rd, 0));
5515 tcg_gen_shri_i32(tmp3, tmp, 16);
2d981da7 5516 gen_helper_neon_fcvt_f16_to_f32(cpu_F0s, tmp3, cpu_env);
60011498 5517 tcg_gen_st_f32(cpu_F0s, cpu_env, neon_reg_offset(rd, 1));
7d1b0095 5518 tcg_temp_free_i32(tmp);
60011498 5519 tcg_gen_ext16u_i32(tmp3, tmp2);
2d981da7 5520 gen_helper_neon_fcvt_f16_to_f32(cpu_F0s, tmp3, cpu_env);
60011498
PB		 5521 tcg_gen_st_f32(cpu_F0s, cpu_env, neon_reg_offset(rd, 2));
5522 tcg_gen_shri_i32(tmp3, tmp2, 16);
2d981da7 5523 gen_helper_neon_fcvt_f16_to_f32(cpu_F0s, tmp3, cpu_env);
60011498 5524 tcg_gen_st_f32(cpu_F0s, cpu_env, neon_reg_offset(rd, 3));
7d1b0095
PM		 5525 tcg_temp_free_i32(tmp2);
5526 tcg_temp_free_i32(tmp3);
60011498 5527 break;
9ee6e8bb
PB		 5528 default:
5529 elementwise:
5530 for (pass = 0; pass < (q ? 4 : 2); pass++) {
5531 if (op == 30 || op == 31 || op >= 58) {
4373f3ce
PB		 5532 tcg_gen_ld_f32(cpu_F0s, cpu_env,
5533 neon_reg_offset(rm, pass));
dd8fbd78 5534 TCGV_UNUSED(tmp);
9ee6e8bb 5535 } else {
dd8fbd78 5536 tmp = neon_load_reg(rm, pass);
9ee6e8bb
PB		 5537 }
5538 switch (op) {
5539 case 1: /* VREV32 */
5540 switch (size) {
dd8fbd78
FN		 5541 case 0: tcg_gen_bswap32_i32(tmp, tmp); break;
5542 case 1: gen_swap_half(tmp); break;
9ee6e8bb
PB		 5543 default: return 1;
5544 }
5545 break;
5546 case 2: /* VREV16 */
5547 if (size != 0)
5548 return 1;
dd8fbd78 5549 gen_rev16(tmp);
9ee6e8bb 5550 break;
9ee6e8bb
PB		 5551 case 8: /* CLS */
5552 switch (size) {
dd8fbd78
FN		 5553 case 0: gen_helper_neon_cls_s8(tmp, tmp); break;
5554 case 1: gen_helper_neon_cls_s16(tmp, tmp); break;
5555 case 2: gen_helper_neon_cls_s32(tmp, tmp); break;
9ee6e8bb
PB		 5556 default: return 1;
5557 }
5558 break;
5559 case 9: /* CLZ */
5560 switch (size) {
dd8fbd78
FN		 5561 case 0: gen_helper_neon_clz_u8(tmp, tmp); break;
5562 case 1: gen_helper_neon_clz_u16(tmp, tmp); break;
5563 case 2: gen_helper_clz(tmp, tmp); break;
9ee6e8bb
PB		 5564 default: return 1;
5565 }
5566 break;
5567 case 10: /* CNT */
5568 if (size != 0)
5569 return 1;
dd8fbd78 5570 gen_helper_neon_cnt_u8(tmp, tmp);
9ee6e8bb
PB		 5571 break;
5572 case 11: /* VNOT */
5573 if (size != 0)
5574 return 1;
dd8fbd78 5575 tcg_gen_not_i32(tmp, tmp);
9ee6e8bb
PB		 5576 break;
5577 case 14: /* VQABS */
5578 switch (size) {
dd8fbd78
FN		 5579 case 0: gen_helper_neon_qabs_s8(tmp, cpu_env, tmp); break;
5580 case 1: gen_helper_neon_qabs_s16(tmp, cpu_env, tmp); break;
5581 case 2: gen_helper_neon_qabs_s32(tmp, cpu_env, tmp); break;
9ee6e8bb
PB		 5582 default: return 1;
5583 }
5584 break;
5585 case 15: /* VQNEG */
5586 switch (size) {
dd8fbd78
FN		 5587 case 0: gen_helper_neon_qneg_s8(tmp, cpu_env, tmp); break;
5588 case 1: gen_helper_neon_qneg_s16(tmp, cpu_env, tmp); break;
5589 case 2: gen_helper_neon_qneg_s32(tmp, cpu_env, tmp); break;
9ee6e8bb
PB		 5590 default: return 1;
5591 }
5592 break;
5593 case 16: case 19: /* VCGT #0, VCLE #0 */
dd8fbd78 5594 tmp2 = tcg_const_i32(0);
9ee6e8bb 5595 switch(size) {
dd8fbd78
FN		 5596 case 0: gen_helper_neon_cgt_s8(tmp, tmp, tmp2); break;
5597 case 1: gen_helper_neon_cgt_s16(tmp, tmp, tmp2); break;
5598 case 2: gen_helper_neon_cgt_s32(tmp, tmp, tmp2); break;
9ee6e8bb
PB		 5599 default: return 1;
5600 }
dd8fbd78 5601 tcg_temp_free(tmp2);
9ee6e8bb 5602 if (op == 19)
dd8fbd78 5603 tcg_gen_not_i32(tmp, tmp);
9ee6e8bb
PB		 5604 break;
5605 case 17: case 20: /* VCGE #0, VCLT #0 */
dd8fbd78 5606 tmp2 = tcg_const_i32(0);
9ee6e8bb 5607 switch(size) {
dd8fbd78
FN		 5608 case 0: gen_helper_neon_cge_s8(tmp, tmp, tmp2); break;
5609 case 1: gen_helper_neon_cge_s16(tmp, tmp, tmp2); break;
5610 case 2: gen_helper_neon_cge_s32(tmp, tmp, tmp2); break;
9ee6e8bb
PB		 5611 default: return 1;
5612 }
dd8fbd78 5613 tcg_temp_free(tmp2);
9ee6e8bb 5614 if (op == 20)
dd8fbd78 5615 tcg_gen_not_i32(tmp, tmp);
9ee6e8bb
PB		 5616 break;
5617 case 18: /* VCEQ #0 */
dd8fbd78 5618 tmp2 = tcg_const_i32(0);
9ee6e8bb 5619 switch(size) {
dd8fbd78
FN		 5620 case 0: gen_helper_neon_ceq_u8(tmp, tmp, tmp2); break;
5621 case 1: gen_helper_neon_ceq_u16(tmp, tmp, tmp2); break;
5622 case 2: gen_helper_neon_ceq_u32(tmp, tmp, tmp2); break;
9ee6e8bb
PB		 5623 default: return 1;
5624 }
dd8fbd78 5625 tcg_temp_free(tmp2);
9ee6e8bb
PB		 5626 break;
5627 case 22: /* VABS */
5628 switch(size) {
dd8fbd78
FN		 5629 case 0: gen_helper_neon_abs_s8(tmp, tmp); break;
5630 case 1: gen_helper_neon_abs_s16(tmp, tmp); break;
5631 case 2: tcg_gen_abs_i32(tmp, tmp); break;
9ee6e8bb
PB		 5632 default: return 1;
5633 }
5634 break;
5635 case 23: /* VNEG */
ad69471c
PB		 5636 if (size == 3)
5637 return 1;
dd8fbd78
FN		 5638 tmp2 = tcg_const_i32(0);
5639 gen_neon_rsb(size, tmp, tmp2);
5640 tcg_temp_free(tmp2);
9ee6e8bb
PB		 5641 break;
5642 case 24: case 27: /* Float VCGT #0, Float VCLE #0 */
dd8fbd78
FN		 5643 tmp2 = tcg_const_i32(0);
5644 gen_helper_neon_cgt_f32(tmp, tmp, tmp2);
5645 tcg_temp_free(tmp2);
9ee6e8bb 5646 if (op == 27)
dd8fbd78 5647 tcg_gen_not_i32(tmp, tmp);
9ee6e8bb
PB		 5648 break;
5649 case 25: case 28: /* Float VCGE #0, Float VCLT #0 */
dd8fbd78
FN		 5650 tmp2 = tcg_const_i32(0);
5651 gen_helper_neon_cge_f32(tmp, tmp, tmp2);
5652 tcg_temp_free(tmp2);
9ee6e8bb 5653 if (op == 28)
dd8fbd78 5654 tcg_gen_not_i32(tmp, tmp);
9ee6e8bb
PB		 5655 break;
5656 case 26: /* Float VCEQ #0 */
dd8fbd78
FN		 5657 tmp2 = tcg_const_i32(0);
5658 gen_helper_neon_ceq_f32(tmp, tmp, tmp2);
5659 tcg_temp_free(tmp2);
9ee6e8bb
PB		 5660 break;
5661 case 30: /* Float VABS */
4373f3ce 5662 gen_vfp_abs(0);
9ee6e8bb
PB		 5663 break;
5664 case 31: /* Float VNEG */
4373f3ce 5665 gen_vfp_neg(0);
9ee6e8bb
PB		 5666 break;
5667 case 32: /* VSWP */
dd8fbd78
FN		 5668 tmp2 = neon_load_reg(rd, pass);
5669 neon_store_reg(rm, pass, tmp2);
9ee6e8bb
PB		 5670 break;
5671 case 33: /* VTRN */
dd8fbd78 5672 tmp2 = neon_load_reg(rd, pass);
9ee6e8bb 5673 switch (size) {
dd8fbd78
FN		 5674 case 0: gen_neon_trn_u8(tmp, tmp2); break;
5675 case 1: gen_neon_trn_u16(tmp, tmp2); break;
9ee6e8bb
PB		 5676 case 2: abort();
5677 default: return 1;
5678 }
dd8fbd78 5679 neon_store_reg(rm, pass, tmp2);
9ee6e8bb
PB		 5680 break;
5681 case 56: /* Integer VRECPE */
dd8fbd78 5682 gen_helper_recpe_u32(tmp, tmp, cpu_env);
9ee6e8bb
PB		 5683 break;
5684 case 57: /* Integer VRSQRTE */
dd8fbd78 5685 gen_helper_rsqrte_u32(tmp, tmp, cpu_env);
9ee6e8bb
PB		 5686 break;
5687 case 58: /* Float VRECPE */
4373f3ce 5688 gen_helper_recpe_f32(cpu_F0s, cpu_F0s, cpu_env);
9ee6e8bb
PB		 5689 break;
5690 case 59: /* Float VRSQRTE */
4373f3ce 5691 gen_helper_rsqrte_f32(cpu_F0s, cpu_F0s, cpu_env);
9ee6e8bb
PB		 5692 break;
5693 case 60: /* VCVT.F32.S32 */
d3587ef8 5694 gen_vfp_sito(0);
9ee6e8bb
PB		 5695 break;
5696 case 61: /* VCVT.F32.U32 */
d3587ef8 5697 gen_vfp_uito(0);
9ee6e8bb
PB		 5698 break;
5699 case 62: /* VCVT.S32.F32 */
d3587ef8 5700 gen_vfp_tosiz(0);
9ee6e8bb
PB		 5701 break;
5702 case 63: /* VCVT.U32.F32 */
d3587ef8 5703 gen_vfp_touiz(0);
9ee6e8bb
PB		 5704 break;
5705 default:
5706 /* Reserved: 21, 29, 39-56 */
5707 return 1;
5708 }
5709 if (op == 30 || op == 31 || op >= 58) {
4373f3ce
PB		 5710 tcg_gen_st_f32(cpu_F0s, cpu_env,
5711 neon_reg_offset(rd, pass));
9ee6e8bb 5712 } else {
dd8fbd78 5713 neon_store_reg(rd, pass, tmp);
9ee6e8bb
PB		 5714 }
5715 }
5716 break;
5717 }
5718 } else if ((insn & (1 << 10)) == 0) {
5719 /* VTBL, VTBX. */
3018f259 5720 n = ((insn >> 5) & 0x18) + 8;
9ee6e8bb 5721 if (insn & (1 << 6)) {
8f8e3aa4 5722 tmp = neon_load_reg(rd, 0);
9ee6e8bb 5723 } else {
7d1b0095 5724 tmp = tcg_temp_new_i32();
8f8e3aa4 5725 tcg_gen_movi_i32(tmp, 0);
9ee6e8bb 5726 }
8f8e3aa4 5727 tmp2 = neon_load_reg(rm, 0);
b75263d6
JR		 5728 tmp4 = tcg_const_i32(rn);
5729 tmp5 = tcg_const_i32(n);
5730 gen_helper_neon_tbl(tmp2, tmp2, tmp, tmp4, tmp5);
7d1b0095 5731 tcg_temp_free_i32(tmp);
9ee6e8bb 5732 if (insn & (1 << 6)) {
8f8e3aa4 5733 tmp = neon_load_reg(rd, 1);
9ee6e8bb 5734 } else {
7d1b0095 5735 tmp = tcg_temp_new_i32();
8f8e3aa4 5736 tcg_gen_movi_i32(tmp, 0);
9ee6e8bb 5737 }
8f8e3aa4 5738 tmp3 = neon_load_reg(rm, 1);
b75263d6 5739 gen_helper_neon_tbl(tmp3, tmp3, tmp, tmp4, tmp5);
25aeb69b
JR		 5740 tcg_temp_free_i32(tmp5);
5741 tcg_temp_free_i32(tmp4);
8f8e3aa4 5742 neon_store_reg(rd, 0, tmp2);
3018f259 5743 neon_store_reg(rd, 1, tmp3);
7d1b0095 5744 tcg_temp_free_i32(tmp);
9ee6e8bb
PB		 5745 } else if ((insn & 0x380) == 0) {
5746 /* VDUP */
5747 if (insn & (1 << 19)) {
dd8fbd78 5748 tmp = neon_load_reg(rm, 1);
9ee6e8bb 5749 } else {
dd8fbd78 5750 tmp = neon_load_reg(rm, 0);
9ee6e8bb
PB		 5751 }
5752 if (insn & (1 << 16)) {
dd8fbd78 5753 gen_neon_dup_u8(tmp, ((insn >> 17) & 3) * 8);
9ee6e8bb
PB		 5754 } else if (insn & (1 << 17)) {
5755 if ((insn >> 18) & 1)
dd8fbd78 5756 gen_neon_dup_high16(tmp);
9ee6e8bb 5757 else
dd8fbd78 5758 gen_neon_dup_low16(tmp);
9ee6e8bb
PB		 5759 }
5760 for (pass = 0; pass < (q ? 4 : 2); pass++) {
7d1b0095 5761 tmp2 = tcg_temp_new_i32();
dd8fbd78
FN		 5762 tcg_gen_mov_i32(tmp2, tmp);
5763 neon_store_reg(rd, pass, tmp2);
9ee6e8bb 5764 }
7d1b0095 5765 tcg_temp_free_i32(tmp);
9ee6e8bb
PB		 5766 } else {
5767 return 1;
5768 }
5769 }
5770 }
5771 return 0;
5772}
5773
fe1479c3
PB		 5774static int disas_cp14_read(CPUState * env, DisasContext *s, uint32_t insn)
5775{
5776 int crn = (insn >> 16) & 0xf;
5777 int crm = insn & 0xf;
5778 int op1 = (insn >> 21) & 7;
5779 int op2 = (insn >> 5) & 7;
5780 int rt = (insn >> 12) & 0xf;
5781 TCGv tmp;
5782
ca27c052
PM		 5783 /* Minimal set of debug registers, since we don't support debug */
5784 if (op1 == 0 && crn == 0 && op2 == 0) {
5785 switch (crm) {
5786 case 0:
5787 /* DBGDIDR: just RAZ. In particular this means the
5788 * "debug architecture version" bits will read as
5789 * a reserved value, which should cause Linux to
5790 * not try to use the debug hardware.
5791 */
5792 tmp = tcg_const_i32(0);
5793 store_reg(s, rt, tmp);
5794 return 0;
5795 case 1:
5796 case 2:
5797 /* DBGDRAR and DBGDSAR: v7 only. Always RAZ since we
5798 * don't implement memory mapped debug components
5799 */
5800 if (ENABLE_ARCH_7) {
5801 tmp = tcg_const_i32(0);
5802 store_reg(s, rt, tmp);
5803 return 0;
5804 }
5805 break;
5806 default:
5807 break;
5808 }
5809 }
5810
fe1479c3
PB		 5811 if (arm_feature(env, ARM_FEATURE_THUMB2EE)) {
5812 if (op1 == 6 && crn == 0 && crm == 0 && op2 == 0) {
5813 /* TEECR */
5814 if (IS_USER(s))
5815 return 1;
5816 tmp = load_cpu_field(teecr);
5817 store_reg(s, rt, tmp);
5818 return 0;
5819 }
5820 if (op1 == 6 && crn == 1 && crm == 0 && op2 == 0) {
5821 /* TEEHBR */
5822 if (IS_USER(s) && (env->teecr & 1))
5823 return 1;
5824 tmp = load_cpu_field(teehbr);
5825 store_reg(s, rt, tmp);
5826 return 0;
5827 }
5828 }
5829 fprintf(stderr, "Unknown cp14 read op1:%d crn:%d crm:%d op2:%d\n",
5830 op1, crn, crm, op2);
5831 return 1;
5832}
5833
5834static int disas_cp14_write(CPUState * env, DisasContext *s, uint32_t insn)
5835{
5836 int crn = (insn >> 16) & 0xf;
5837 int crm = insn & 0xf;
5838 int op1 = (insn >> 21) & 7;
5839 int op2 = (insn >> 5) & 7;
5840 int rt = (insn >> 12) & 0xf;
5841 TCGv tmp;
5842
5843 if (arm_feature(env, ARM_FEATURE_THUMB2EE)) {
5844 if (op1 == 6 && crn == 0 && crm == 0 && op2 == 0) {
5845 /* TEECR */
5846 if (IS_USER(s))
5847 return 1;
5848 tmp = load_reg(s, rt);
5849 gen_helper_set_teecr(cpu_env, tmp);
7d1b0095 5850 tcg_temp_free_i32(tmp);
fe1479c3
PB		 5851 return 0;
5852 }
5853 if (op1 == 6 && crn == 1 && crm == 0 && op2 == 0) {
5854 /* TEEHBR */
5855 if (IS_USER(s) && (env->teecr & 1))
5856 return 1;
5857 tmp = load_reg(s, rt);
5858 store_cpu_field(tmp, teehbr);
5859 return 0;
5860 }
5861 }
5862 fprintf(stderr, "Unknown cp14 write op1:%d crn:%d crm:%d op2:%d\n",
5863 op1, crn, crm, op2);
5864 return 1;
5865}
5866
9ee6e8bb
PB		 5867static int disas_coproc_insn(CPUState * env, DisasContext *s, uint32_t insn)
5868{
5869 int cpnum;
5870
5871 cpnum = (insn >> 8) & 0xf;
5872 if (arm_feature(env, ARM_FEATURE_XSCALE)
5873 && ((env->cp15.c15_cpar ^ 0x3fff) & (1 << cpnum)))
5874 return 1;
5875
5876 switch (cpnum) {
5877 case 0:
5878 case 1:
5879 if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
5880 return disas_iwmmxt_insn(env, s, insn);
5881 } else if (arm_feature(env, ARM_FEATURE_XSCALE)) {
5882 return disas_dsp_insn(env, s, insn);
5883 }
5884 return 1;
5885 case 10:
5886 case 11:
5887 return disas_vfp_insn (env, s, insn);
fe1479c3
PB		 5888 case 14:
5889 /* Coprocessors 7-15 are architecturally reserved by ARM.
5890 Unfortunately Intel decided to ignore this. */
5891 if (arm_feature(env, ARM_FEATURE_XSCALE))
5892 goto board;
5893 if (insn & (1 << 20))
5894 return disas_cp14_read(env, s, insn);
5895 else
5896 return disas_cp14_write(env, s, insn);
9ee6e8bb
PB		 5897 case 15:
5898 return disas_cp15_insn (env, s, insn);
5899 default:
fe1479c3 5900 board:
9ee6e8bb
PB		 5901 /* Unknown coprocessor. See if the board has hooked it. */
5902 return disas_cp_insn (env, s, insn);
5903 }
5904}
5905
5e3f878a
PB		 5906
5907/* Store a 64-bit value to a register pair. Clobbers val. */
a7812ae4 5908static void gen_storeq_reg(DisasContext *s, int rlow, int rhigh, TCGv_i64 val)
5e3f878a
PB		 5909{
5910 TCGv tmp;
7d1b0095 5911 tmp = tcg_temp_new_i32();
5e3f878a
PB		 5912 tcg_gen_trunc_i64_i32(tmp, val);
5913 store_reg(s, rlow, tmp);
7d1b0095 5914 tmp = tcg_temp_new_i32();
5e3f878a
PB		 5915 tcg_gen_shri_i64(val, val, 32);
5916 tcg_gen_trunc_i64_i32(tmp, val);
5917 store_reg(s, rhigh, tmp);
5918}
5919
5920/* load a 32-bit value from a register and perform a 64-bit accumulate. */
a7812ae4 5921static void gen_addq_lo(DisasContext *s, TCGv_i64 val, int rlow)
5e3f878a 5922{
a7812ae4 5923 TCGv_i64 tmp;
5e3f878a
PB		 5924 TCGv tmp2;
5925
36aa55dc 5926 /* Load value and extend to 64 bits. */
a7812ae4 5927 tmp = tcg_temp_new_i64();
5e3f878a
PB		 5928 tmp2 = load_reg(s, rlow);
5929 tcg_gen_extu_i32_i64(tmp, tmp2);
7d1b0095 5930 tcg_temp_free_i32(tmp2);
5e3f878a 5931 tcg_gen_add_i64(val, val, tmp);
b75263d6 5932 tcg_temp_free_i64(tmp);
5e3f878a
PB		 5933}
5934
5935/* load and add a 64-bit value from a register pair. */
a7812ae4 5936static void gen_addq(DisasContext *s, TCGv_i64 val, int rlow, int rhigh)
5e3f878a 5937{
a7812ae4 5938 TCGv_i64 tmp;
36aa55dc
PB		 5939 TCGv tmpl;
5940 TCGv tmph;
5e3f878a
PB		 5941
5942 /* Load 64-bit value rd:rn. */
36aa55dc
PB		 5943 tmpl = load_reg(s, rlow);
5944 tmph = load_reg(s, rhigh);
a7812ae4 5945 tmp = tcg_temp_new_i64();
36aa55dc 5946 tcg_gen_concat_i32_i64(tmp, tmpl, tmph);
7d1b0095
PM		 5947 tcg_temp_free_i32(tmpl);
5948 tcg_temp_free_i32(tmph);
5e3f878a 5949 tcg_gen_add_i64(val, val, tmp);
b75263d6 5950 tcg_temp_free_i64(tmp);
5e3f878a
PB		 5951}
5952
5953/* Set N and Z flags from a 64-bit value. */
a7812ae4 5954static void gen_logicq_cc(TCGv_i64 val)
5e3f878a 5955{
7d1b0095 5956 TCGv tmp = tcg_temp_new_i32();
5e3f878a 5957 gen_helper_logicq_cc(tmp, val);
6fbe23d5 5958 gen_logic_CC(tmp);
7d1b0095 5959 tcg_temp_free_i32(tmp);
5e3f878a
PB		 5960}
5961
426f5abc
PB		 5962/* Load/Store exclusive instructions are implemented by remembering
5963 the value/address loaded, and seeing if these are the same
5964 when the store is performed. This should be is sufficient to implement
5965 the architecturally mandated semantics, and avoids having to monitor
5966 regular stores.
5967
5968 In system emulation mode only one CPU will be running at once, so
5969 this sequence is effectively atomic. In user emulation mode we
5970 throw an exception and handle the atomic operation elsewhere. */
5971static void gen_load_exclusive(DisasContext *s, int rt, int rt2,
5972 TCGv addr, int size)
5973{
5974 TCGv tmp;
5975
5976 switch (size) {
5977 case 0:
5978 tmp = gen_ld8u(addr, IS_USER(s));
5979 break;
5980 case 1:
5981 tmp = gen_ld16u(addr, IS_USER(s));
5982 break;
5983 case 2:
5984 case 3:
5985 tmp = gen_ld32(addr, IS_USER(s));
5986 break;
5987 default:
5988 abort();
5989 }
5990 tcg_gen_mov_i32(cpu_exclusive_val, tmp);
5991 store_reg(s, rt, tmp);
5992 if (size == 3) {
7d1b0095 5993 TCGv tmp2 = tcg_temp_new_i32();
2c9adbda
PM		 5994 tcg_gen_addi_i32(tmp2, addr, 4);
5995 tmp = gen_ld32(tmp2, IS_USER(s));
7d1b0095 5996 tcg_temp_free_i32(tmp2);
426f5abc
PB		 5997 tcg_gen_mov_i32(cpu_exclusive_high, tmp);
5998 store_reg(s, rt2, tmp);
5999 }
6000 tcg_gen_mov_i32(cpu_exclusive_addr, addr);
6001}
6002
6003static void gen_clrex(DisasContext *s)
6004{
6005 tcg_gen_movi_i32(cpu_exclusive_addr, -1);
6006}
6007
6008#ifdef CONFIG_USER_ONLY
6009static void gen_store_exclusive(DisasContext *s, int rd, int rt, int rt2,
6010 TCGv addr, int size)
6011{
6012 tcg_gen_mov_i32(cpu_exclusive_test, addr);
6013 tcg_gen_movi_i32(cpu_exclusive_info,
6014 size | (rd << 4) | (rt << 8) | (rt2 << 12));
bc4a0de0 6015 gen_exception_insn(s, 4, EXCP_STREX);
426f5abc
PB		 6016}
6017#else
6018static void gen_store_exclusive(DisasContext *s, int rd, int rt, int rt2,
6019 TCGv addr, int size)
6020{
6021 TCGv tmp;
6022 int done_label;
6023 int fail_label;
6024
6025 /* if (env->exclusive_addr == addr && env->exclusive_val == [addr]) {
6026 [addr] = {Rt};
6027 {Rd} = 0;
6028 } else {
6029 {Rd} = 1;
6030 } */
6031 fail_label = gen_new_label();
6032 done_label = gen_new_label();
6033 tcg_gen_brcond_i32(TCG_COND_NE, addr, cpu_exclusive_addr, fail_label);
6034 switch (size) {
6035 case 0:
6036 tmp = gen_ld8u(addr, IS_USER(s));
6037 break;
6038 case 1:
6039 tmp = gen_ld16u(addr, IS_USER(s));
6040 break;
6041 case 2:
6042 case 3:
6043 tmp = gen_ld32(addr, IS_USER(s));
6044 break;
6045 default:
6046 abort();
6047 }
6048 tcg_gen_brcond_i32(TCG_COND_NE, tmp, cpu_exclusive_val, fail_label);
7d1b0095 6049 tcg_temp_free_i32(tmp);
426f5abc 6050 if (size == 3) {
7d1b0095 6051 TCGv tmp2 = tcg_temp_new_i32();
426f5abc 6052 tcg_gen_addi_i32(tmp2, addr, 4);
2c9adbda 6053 tmp = gen_ld32(tmp2, IS_USER(s));
7d1b0095 6054 tcg_temp_free_i32(tmp2);
426f5abc 6055 tcg_gen_brcond_i32(TCG_COND_NE, tmp, cpu_exclusive_high, fail_label);
7d1b0095 6056 tcg_temp_free_i32(tmp);
426f5abc
PB		 6057 }
6058 tmp = load_reg(s, rt);
6059 switch (size) {
6060 case 0:
6061 gen_st8(tmp, addr, IS_USER(s));
6062 break;
6063 case 1:
6064 gen_st16(tmp, addr, IS_USER(s));
6065 break;
6066 case 2:
6067 case 3:
6068 gen_st32(tmp, addr, IS_USER(s));
6069 break;
6070 default:
6071 abort();
6072 }
6073 if (size == 3) {
6074 tcg_gen_addi_i32(addr, addr, 4);
6075 tmp = load_reg(s, rt2);
6076 gen_st32(tmp, addr, IS_USER(s));
6077 }
6078 tcg_gen_movi_i32(cpu_R[rd], 0);
6079 tcg_gen_br(done_label);
6080 gen_set_label(fail_label);
6081 tcg_gen_movi_i32(cpu_R[rd], 1);
6082 gen_set_label(done_label);
6083 tcg_gen_movi_i32(cpu_exclusive_addr, -1);
6084}
6085#endif
6086
9ee6e8bb
PB		 6087static void disas_arm_insn(CPUState * env, DisasContext *s)
6088{
6089 unsigned int cond, insn, val, op1, i, shift, rm, rs, rn, rd, sh;
b26eefb6 6090 TCGv tmp;
3670669c 6091 TCGv tmp2;
6ddbc6e4 6092 TCGv tmp3;
b0109805 6093 TCGv addr;
a7812ae4 6094 TCGv_i64 tmp64;
9ee6e8bb
PB		 6095
6096 insn = ldl_code(s->pc);
6097 s->pc += 4;
6098
6099 /* M variants do not implement ARM mode. */
6100 if (IS_M(env))
6101 goto illegal_op;
6102 cond = insn >> 28;
6103 if (cond == 0xf){
6104 /* Unconditional instructions. */
6105 if (((insn >> 25) & 7) == 1) {
6106 /* NEON Data processing. */
6107 if (!arm_feature(env, ARM_FEATURE_NEON))
6108 goto illegal_op;
6109
6110 if (disas_neon_data_insn(env, s, insn))
6111 goto illegal_op;
6112 return;
6113 }
6114 if ((insn & 0x0f100000) == 0x04000000) {
6115 /* NEON load/store. */
6116 if (!arm_feature(env, ARM_FEATURE_NEON))
6117 goto illegal_op;
6118
6119 if (disas_neon_ls_insn(env, s, insn))
6120 goto illegal_op;
6121 return;
6122 }
3d185e5d
PM		 6123 if (((insn & 0x0f30f000) == 0x0510f000) ||
6124 ((insn & 0x0f30f010) == 0x0710f000)) {
6125 if ((insn & (1 << 22)) == 0) {
6126 /* PLDW; v7MP */
6127 if (!arm_feature(env, ARM_FEATURE_V7MP)) {
6128 goto illegal_op;
6129 }
6130 }
6131 /* Otherwise PLD; v5TE+ */
6132 return;
6133 }
6134 if (((insn & 0x0f70f000) == 0x0450f000) ||
6135 ((insn & 0x0f70f010) == 0x0650f000)) {
6136 ARCH(7);
6137 return; /* PLI; V7 */
6138 }
6139 if (((insn & 0x0f700000) == 0x04100000) ||
6140 ((insn & 0x0f700010) == 0x06100000)) {
6141 if (!arm_feature(env, ARM_FEATURE_V7MP)) {
6142 goto illegal_op;
6143 }
6144 return; /* v7MP: Unallocated memory hint: must NOP */
6145 }
6146
6147 if ((insn & 0x0ffffdff) == 0x01010000) {
9ee6e8bb
PB		 6148 ARCH(6);
6149 /* setend */
6150 if (insn & (1 << 9)) {
6151 /* BE8 mode not implemented. */
6152 goto illegal_op;
6153 }
6154 return;
6155 } else if ((insn & 0x0fffff00) == 0x057ff000) {
6156 switch ((insn >> 4) & 0xf) {
6157 case 1: /* clrex */
6158 ARCH(6K);
426f5abc 6159 gen_clrex(s);
9ee6e8bb
PB		 6160 return;
6161 case 4: /* dsb */
6162 case 5: /* dmb */
6163 case 6: /* isb */
6164 ARCH(7);
6165 /* We don't emulate caches so these are a no-op. */
6166 return;
6167 default:
6168 goto illegal_op;
6169 }
6170 } else if ((insn & 0x0e5fffe0) == 0x084d0500) {
6171 /* srs */
c67b6b71 6172 int32_t offset;
9ee6e8bb
PB		 6173 if (IS_USER(s))
6174 goto illegal_op;
6175 ARCH(6);
6176 op1 = (insn & 0x1f);
7d1b0095 6177 addr = tcg_temp_new_i32();
39ea3d4e
PM		 6178 tmp = tcg_const_i32(op1);
6179 gen_helper_get_r13_banked(addr, cpu_env, tmp);
6180 tcg_temp_free_i32(tmp);
9ee6e8bb
PB		 6181 i = (insn >> 23) & 3;
6182 switch (i) {
6183 case 0: offset = -4; break; /* DA */
c67b6b71
FN		 6184 case 1: offset = 0; break; /* IA */
6185 case 2: offset = -8; break; /* DB */
9ee6e8bb
PB		 6186 case 3: offset = 4; break; /* IB */
6187 default: abort();
6188 }
6189 if (offset)
b0109805
PB		 6190 tcg_gen_addi_i32(addr, addr, offset);
6191 tmp = load_reg(s, 14);
6192 gen_st32(tmp, addr, 0);
c67b6b71 6193 tmp = load_cpu_field(spsr);
b0109805
PB		 6194 tcg_gen_addi_i32(addr, addr, 4);
6195 gen_st32(tmp, addr, 0);
9ee6e8bb
PB		 6196 if (insn & (1 << 21)) {
6197 /* Base writeback. */
6198 switch (i) {
6199 case 0: offset = -8; break;
c67b6b71
FN		 6200 case 1: offset = 4; break;
6201 case 2: offset = -4; break;
9ee6e8bb
PB		 6202 case 3: offset = 0; break;
6203 default: abort();
6204 }
6205 if (offset)
c67b6b71 6206 tcg_gen_addi_i32(addr, addr, offset);
39ea3d4e
PM		 6207 tmp = tcg_const_i32(op1);
6208 gen_helper_set_r13_banked(cpu_env, tmp, addr);
6209 tcg_temp_free_i32(tmp);
7d1b0095 6210 tcg_temp_free_i32(addr);
b0109805 6211 } else {
7d1b0095 6212 tcg_temp_free_i32(addr);
9ee6e8bb 6213 }
a990f58f 6214 return;
ea825eee 6215 } else if ((insn & 0x0e50ffe0) == 0x08100a00) {
9ee6e8bb 6216 /* rfe */
c67b6b71 6217 int32_t offset;
9ee6e8bb
PB		 6218 if (IS_USER(s))
6219 goto illegal_op;
6220 ARCH(6);
6221 rn = (insn >> 16) & 0xf;
b0109805 6222 addr = load_reg(s, rn);
9ee6e8bb
PB		 6223 i = (insn >> 23) & 3;
6224 switch (i) {
b0109805 6225 case 0: offset = -4; break; /* DA */
c67b6b71
FN		 6226 case 1: offset = 0; break; /* IA */
6227 case 2: offset = -8; break; /* DB */
b0109805 6228 case 3: offset = 4; break; /* IB */
9ee6e8bb
PB		 6229 default: abort();
6230 }
6231 if (offset)
b0109805
PB		 6232 tcg_gen_addi_i32(addr, addr, offset);
6233 /* Load PC into tmp and CPSR into tmp2. */
6234 tmp = gen_ld32(addr, 0);
6235 tcg_gen_addi_i32(addr, addr, 4);
6236 tmp2 = gen_ld32(addr, 0);
9ee6e8bb
PB		 6237 if (insn & (1 << 21)) {
6238 /* Base writeback. */
6239 switch (i) {
b0109805 6240 case 0: offset = -8; break;
c67b6b71
FN		 6241 case 1: offset = 4; break;
6242 case 2: offset = -4; break;
b0109805 6243 case 3: offset = 0; break;
9ee6e8bb
PB		 6244 default: abort();
6245 }
6246 if (offset)
b0109805
PB		 6247 tcg_gen_addi_i32(addr, addr, offset);
6248 store_reg(s, rn, addr);
6249 } else {
7d1b0095 6250 tcg_temp_free_i32(addr);
9ee6e8bb 6251 }
b0109805 6252 gen_rfe(s, tmp, tmp2);
c67b6b71 6253 return;
9ee6e8bb
PB		 6254 } else if ((insn & 0x0e000000) == 0x0a000000) {
6255 /* branch link and change to thumb (blx <offset>) */
6256 int32_t offset;
6257
6258 val = (uint32_t)s->pc;
7d1b0095 6259 tmp = tcg_temp_new_i32();
d9ba4830
PB		 6260 tcg_gen_movi_i32(tmp, val);
6261 store_reg(s, 14, tmp);
9ee6e8bb
PB		 6262 /* Sign-extend the 24-bit offset */
6263 offset = (((int32_t)insn) << 8) >> 8;
6264 /* offset * 4 + bit24 * 2 + (thumb bit) */
6265 val += (offset << 2) | ((insn >> 23) & 2) | 1;
6266 /* pipeline offset */
6267 val += 4;
d9ba4830 6268 gen_bx_im(s, val);
9ee6e8bb
PB		 6269 return;
6270 } else if ((insn & 0x0e000f00) == 0x0c000100) {
6271 if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
6272 /* iWMMXt register transfer. */
6273 if (env->cp15.c15_cpar & (1 << 1))
6274 if (!disas_iwmmxt_insn(env, s, insn))
6275 return;
6276 }
6277 } else if ((insn & 0x0fe00000) == 0x0c400000) {
6278 /* Coprocessor double register transfer. */
6279 } else if ((insn & 0x0f000010) == 0x0e000010) {
6280 /* Additional coprocessor register transfer. */
7997d92f 6281 } else if ((insn & 0x0ff10020) == 0x01000000) {
9ee6e8bb
PB		 6282 uint32_t mask;
6283 uint32_t val;
6284 /* cps (privileged) */
6285 if (IS_USER(s))
6286 return;
6287 mask = val = 0;
6288 if (insn & (1 << 19)) {
6289 if (insn & (1 << 8))
6290 mask |= CPSR_A;
6291 if (insn & (1 << 7))
6292 mask |= CPSR_I;
6293 if (insn & (1 << 6))
6294 mask |= CPSR_F;
6295 if (insn & (1 << 18))
6296 val |= mask;
6297 }
7997d92f 6298 if (insn & (1 << 17)) {
9ee6e8bb
PB		 6299 mask |= CPSR_M;
6300 val |= (insn & 0x1f);
6301 }
6302 if (mask) {
2fbac54b 6303 gen_set_psr_im(s, mask, 0, val);
9ee6e8bb
PB		 6304 }
6305 return;
6306 }
6307 goto illegal_op;
6308 }
6309 if (cond != 0xe) {
6310 /* if not always execute, we generate a conditional jump to
6311 next instruction */
6312 s->condlabel = gen_new_label();
d9ba4830 6313 gen_test_cc(cond ^ 1, s->condlabel);
9ee6e8bb
PB		 6314 s->condjmp = 1;
6315 }
6316 if ((insn & 0x0f900000) == 0x03000000) {
6317 if ((insn & (1 << 21)) == 0) {
6318 ARCH(6T2);
6319 rd = (insn >> 12) & 0xf;
6320 val = ((insn >> 4) & 0xf000) | (insn & 0xfff);
6321 if ((insn & (1 << 22)) == 0) {
6322 /* MOVW */
7d1b0095 6323 tmp = tcg_temp_new_i32();
5e3f878a 6324 tcg_gen_movi_i32(tmp, val);
9ee6e8bb
PB		 6325 } else {
6326 /* MOVT */
5e3f878a 6327 tmp = load_reg(s, rd);
86831435 6328 tcg_gen_ext16u_i32(tmp, tmp);
5e3f878a 6329 tcg_gen_ori_i32(tmp, tmp, val << 16);
9ee6e8bb 6330 }
5e3f878a 6331 store_reg(s, rd, tmp);
9ee6e8bb
PB		 6332 } else {
6333 if (((insn >> 12) & 0xf) != 0xf)
6334 goto illegal_op;
6335 if (((insn >> 16) & 0xf) == 0) {
6336 gen_nop_hint(s, insn & 0xff);
6337 } else {
6338 /* CPSR = immediate */
6339 val = insn & 0xff;
6340 shift = ((insn >> 8) & 0xf) * 2;
6341 if (shift)
6342 val = (val >> shift) | (val << (32 - shift));
9ee6e8bb 6343 i = ((insn & (1 << 22)) != 0);
2fbac54b 6344 if (gen_set_psr_im(s, msr_mask(env, s, (insn >> 16) & 0xf, i), i, val))
9ee6e8bb
PB		 6345 goto illegal_op;
6346 }
6347 }
6348 } else if ((insn & 0x0f900000) == 0x01000000
6349 && (insn & 0x00000090) != 0x00000090) {
6350 /* miscellaneous instructions */
6351 op1 = (insn >> 21) & 3;
6352 sh = (insn >> 4) & 0xf;
6353 rm = insn & 0xf;
6354 switch (sh) {
6355 case 0x0: /* move program status register */
6356 if (op1 & 1) {
6357 /* PSR = reg */
2fbac54b 6358 tmp = load_reg(s, rm);
9ee6e8bb 6359 i = ((op1 & 2) != 0);
2fbac54b 6360 if (gen_set_psr(s, msr_mask(env, s, (insn >> 16) & 0xf, i), i, tmp))
9ee6e8bb
PB		 6361 goto illegal_op;
6362 } else {
6363 /* reg = PSR */
6364 rd = (insn >> 12) & 0xf;
6365 if (op1 & 2) {
6366 if (IS_USER(s))
6367 goto illegal_op;
d9ba4830 6368 tmp = load_cpu_field(spsr);
9ee6e8bb 6369 } else {
7d1b0095 6370 tmp = tcg_temp_new_i32();
d9ba4830 6371 gen_helper_cpsr_read(tmp);
9ee6e8bb 6372 }
d9ba4830 6373 store_reg(s, rd, tmp);
9ee6e8bb
PB		 6374 }
6375 break;
6376 case 0x1:
6377 if (op1 == 1) {
6378 /* branch/exchange thumb (bx). */
d9ba4830
PB		 6379 tmp = load_reg(s, rm);
6380 gen_bx(s, tmp);
9ee6e8bb
PB		 6381 } else if (op1 == 3) {
6382 /* clz */
6383 rd = (insn >> 12) & 0xf;
1497c961
PB		 6384 tmp = load_reg(s, rm);
6385 gen_helper_clz(tmp, tmp);
6386 store_reg(s, rd, tmp);
9ee6e8bb
PB		 6387 } else {
6388 goto illegal_op;
6389 }
6390 break;
6391 case 0x2:
6392 if (op1 == 1) {
6393 ARCH(5J); /* bxj */
6394 /* Trivial implementation equivalent to bx. */
d9ba4830
PB		 6395 tmp = load_reg(s, rm);
6396 gen_bx(s, tmp);
9ee6e8bb
PB		 6397 } else {
6398 goto illegal_op;
6399 }
6400 break;
6401 case 0x3:
6402 if (op1 != 1)
6403 goto illegal_op;
6404
6405 /* branch link/exchange thumb (blx) */
d9ba4830 6406 tmp = load_reg(s, rm);
7d1b0095 6407 tmp2 = tcg_temp_new_i32();
d9ba4830
PB		 6408 tcg_gen_movi_i32(tmp2, s->pc);
6409 store_reg(s, 14, tmp2);
6410 gen_bx(s, tmp);
9ee6e8bb
PB		 6411 break;
6412 case 0x5: /* saturating add/subtract */
6413 rd = (insn >> 12) & 0xf;
6414 rn = (insn >> 16) & 0xf;
b40d0353 6415 tmp = load_reg(s, rm);
5e3f878a 6416 tmp2 = load_reg(s, rn);
9ee6e8bb 6417 if (op1 & 2)
5e3f878a 6418 gen_helper_double_saturate(tmp2, tmp2);
9ee6e8bb 6419 if (op1 & 1)
5e3f878a 6420 gen_helper_sub_saturate(tmp, tmp, tmp2);
9ee6e8bb 6421 else
5e3f878a 6422 gen_helper_add_saturate(tmp, tmp, tmp2);
7d1b0095 6423 tcg_temp_free_i32(tmp2);
5e3f878a 6424 store_reg(s, rd, tmp);
9ee6e8bb 6425 break;
49e14940
AL		 6426 case 7:
6427 /* SMC instruction (op1 == 3)
6428 and undefined instructions (op1 == 0 || op1 == 2)
6429 will trap */
6430 if (op1 != 1) {
6431 goto illegal_op;
6432 }
6433 /* bkpt */
bc4a0de0 6434 gen_exception_insn(s, 4, EXCP_BKPT);
9ee6e8bb
PB		 6435 break;
6436 case 0x8: /* signed multiply */
6437 case 0xa:
6438 case 0xc:
6439 case 0xe:
6440 rs = (insn >> 8) & 0xf;
6441 rn = (insn >> 12) & 0xf;
6442 rd = (insn >> 16) & 0xf;
6443 if (op1 == 1) {
6444 /* (32 * 16) >> 16 */
5e3f878a
PB		 6445 tmp = load_reg(s, rm);
6446 tmp2 = load_reg(s, rs);
9ee6e8bb 6447 if (sh & 4)
5e3f878a 6448 tcg_gen_sari_i32(tmp2, tmp2, 16);
9ee6e8bb 6449 else
5e3f878a 6450 gen_sxth(tmp2);
a7812ae4
PB		 6451 tmp64 = gen_muls_i64_i32(tmp, tmp2);
6452 tcg_gen_shri_i64(tmp64, tmp64, 16);
7d1b0095 6453 tmp = tcg_temp_new_i32();
a7812ae4 6454 tcg_gen_trunc_i64_i32(tmp, tmp64);
b75263d6 6455 tcg_temp_free_i64(tmp64);
9ee6e8bb 6456 if ((sh & 2) == 0) {
5e3f878a
PB		 6457 tmp2 = load_reg(s, rn);
6458 gen_helper_add_setq(tmp, tmp, tmp2);
7d1b0095 6459 tcg_temp_free_i32(tmp2);
9ee6e8bb 6460 }
5e3f878a 6461 store_reg(s, rd, tmp);
9ee6e8bb
PB		 6462 } else {
6463 /* 16 * 16 */
5e3f878a
PB		 6464 tmp = load_reg(s, rm);
6465 tmp2 = load_reg(s, rs);
6466 gen_mulxy(tmp, tmp2, sh & 2, sh & 4);
7d1b0095 6467 tcg_temp_free_i32(tmp2);
9ee6e8bb 6468 if (op1 == 2) {
a7812ae4
PB		 6469 tmp64 = tcg_temp_new_i64();
6470 tcg_gen_ext_i32_i64(tmp64, tmp);
7d1b0095 6471 tcg_temp_free_i32(tmp);
a7812ae4
PB		 6472 gen_addq(s, tmp64, rn, rd);
6473 gen_storeq_reg(s, rn, rd, tmp64);
b75263d6 6474 tcg_temp_free_i64(tmp64);
9ee6e8bb
PB		 6475 } else {
6476 if (op1 == 0) {
5e3f878a
PB		 6477 tmp2 = load_reg(s, rn);
6478 gen_helper_add_setq(tmp, tmp, tmp2);
7d1b0095 6479 tcg_temp_free_i32(tmp2);
9ee6e8bb 6480 }
5e3f878a 6481 store_reg(s, rd, tmp);
9ee6e8bb
PB		 6482 }
6483 }
6484 break;
6485 default:
6486 goto illegal_op;
6487 }
6488 } else if (((insn & 0x0e000000) == 0 &&
6489 (insn & 0x00000090) != 0x90) ||
6490 ((insn & 0x0e000000) == (1 << 25))) {
6491 int set_cc, logic_cc, shiftop;
6492
6493 op1 = (insn >> 21) & 0xf;
6494 set_cc = (insn >> 20) & 1;
6495 logic_cc = table_logic_cc[op1] & set_cc;
6496
6497 /* data processing instruction */
6498 if (insn & (1 << 25)) {
6499 /* immediate operand */
6500 val = insn & 0xff;
6501 shift = ((insn >> 8) & 0xf) * 2;
e9bb4aa9 6502 if (shift) {
9ee6e8bb 6503 val = (val >> shift) | (val << (32 - shift));
e9bb4aa9 6504 }
7d1b0095 6505 tmp2 = tcg_temp_new_i32();
e9bb4aa9
JR		 6506 tcg_gen_movi_i32(tmp2, val);
6507 if (logic_cc && shift) {
6508 gen_set_CF_bit31(tmp2);
6509 }
9ee6e8bb
PB		 6510 } else {
6511 /* register */
6512 rm = (insn) & 0xf;
e9bb4aa9 6513 tmp2 = load_reg(s, rm);
9ee6e8bb
PB		 6514 shiftop = (insn >> 5) & 3;
6515 if (!(insn & (1 << 4))) {
6516 shift = (insn >> 7) & 0x1f;
e9bb4aa9 6517 gen_arm_shift_im(tmp2, shiftop, shift, logic_cc);
9ee6e8bb
PB		 6518 } else {
6519 rs = (insn >> 8) & 0xf;
8984bd2e 6520 tmp = load_reg(s, rs);
e9bb4aa9 6521 gen_arm_shift_reg(tmp2, shiftop, tmp, logic_cc);
9ee6e8bb
PB		 6522 }
6523 }
6524 if (op1 != 0x0f && op1 != 0x0d) {
6525 rn = (insn >> 16) & 0xf;
e9bb4aa9
JR		 6526 tmp = load_reg(s, rn);
6527 } else {
6528 TCGV_UNUSED(tmp);
9ee6e8bb
PB		 6529 }
6530 rd = (insn >> 12) & 0xf;
6531 switch(op1) {
6532 case 0x00:
e9bb4aa9
JR		 6533 tcg_gen_and_i32(tmp, tmp, tmp2);
6534 if (logic_cc) {
6535 gen_logic_CC(tmp);
6536 }
21aeb343 6537 store_reg_bx(env, s, rd, tmp);
9ee6e8bb
PB		 6538 break;
6539 case 0x01:
e9bb4aa9
JR		 6540 tcg_gen_xor_i32(tmp, tmp, tmp2);
6541 if (logic_cc) {
6542 gen_logic_CC(tmp);
6543 }
21aeb343 6544 store_reg_bx(env, s, rd, tmp);
9ee6e8bb
PB		 6545 break;
6546 case 0x02:
6547 if (set_cc && rd == 15) {
6548 /* SUBS r15, ... is used for exception return. */
e9bb4aa9 6549 if (IS_USER(s)) {
9ee6e8bb 6550 goto illegal_op;
e9bb4aa9
JR		 6551 }
6552 gen_helper_sub_cc(tmp, tmp, tmp2);
6553 gen_exception_return(s, tmp);
9ee6e8bb 6554 } else {
e9bb4aa9
JR		 6555 if (set_cc) {
6556 gen_helper_sub_cc(tmp, tmp, tmp2);
6557 } else {
6558 tcg_gen_sub_i32(tmp, tmp, tmp2);
6559 }
21aeb343 6560 store_reg_bx(env, s, rd, tmp);
9ee6e8bb
PB		 6561 }
6562 break;
6563 case 0x03:
e9bb4aa9
JR		 6564 if (set_cc) {
6565 gen_helper_sub_cc(tmp, tmp2, tmp);
6566 } else {
6567 tcg_gen_sub_i32(tmp, tmp2, tmp);
6568 }
21aeb343 6569 store_reg_bx(env, s, rd, tmp);
9ee6e8bb
PB		 6570 break;
6571 case 0x04:
e9bb4aa9
JR		 6572 if (set_cc) {
6573 gen_helper_add_cc(tmp, tmp, tmp2);
6574 } else {
6575 tcg_gen_add_i32(tmp, tmp, tmp2);
6576 }
21aeb343 6577 store_reg_bx(env, s, rd, tmp);
9ee6e8bb
PB		 6578 break;
6579 case 0x05:
e9bb4aa9
JR		 6580 if (set_cc) {
6581 gen_helper_adc_cc(tmp, tmp, tmp2);
6582 } else {
6583 gen_add_carry(tmp, tmp, tmp2);
6584 }
21aeb343 6585 store_reg_bx(env, s, rd, tmp);
9ee6e8bb
PB		 6586 break;
6587 case 0x06:
e9bb4aa9
JR		 6588 if (set_cc) {
6589 gen_helper_sbc_cc(tmp, tmp, tmp2);
6590 } else {
6591 gen_sub_carry(tmp, tmp, tmp2);
6592 }
21aeb343 6593 store_reg_bx(env, s, rd, tmp);
9ee6e8bb
PB		 6594 break;
6595 case 0x07:
e9bb4aa9
JR		 6596 if (set_cc) {
6597 gen_helper_sbc_cc(tmp, tmp2, tmp);
6598 } else {
6599 gen_sub_carry(tmp, tmp2, tmp);
6600 }
21aeb343 6601 store_reg_bx(env, s, rd, tmp);
9ee6e8bb
PB		 6602 break;
6603 case 0x08:
6604 if (set_cc) {
e9bb4aa9
JR		 6605 tcg_gen_and_i32(tmp, tmp, tmp2);
6606 gen_logic_CC(tmp);
9ee6e8bb 6607 }
7d1b0095 6608 tcg_temp_free_i32(tmp);
9ee6e8bb
PB		 6609 break;
6610 case 0x09:
6611 if (set_cc) {
e9bb4aa9
JR		 6612 tcg_gen_xor_i32(tmp, tmp, tmp2);
6613 gen_logic_CC(tmp);
9ee6e8bb 6614 }
7d1b0095 6615 tcg_temp_free_i32(tmp);
9ee6e8bb
PB		 6616 break;
6617 case 0x0a:
6618 if (set_cc) {
e9bb4aa9 6619 gen_helper_sub_cc(tmp, tmp, tmp2);
9ee6e8bb 6620 }
7d1b0095 6621 tcg_temp_free_i32(tmp);
9ee6e8bb
PB		 6622 break;
6623 case 0x0b:
6624 if (set_cc) {
e9bb4aa9 6625 gen_helper_add_cc(tmp, tmp, tmp2);
9ee6e8bb 6626 }
7d1b0095 6627 tcg_temp_free_i32(tmp);
9ee6e8bb
PB		 6628 break;
6629 case 0x0c:
e9bb4aa9
JR		 6630 tcg_gen_or_i32(tmp, tmp, tmp2);
6631 if (logic_cc) {
6632 gen_logic_CC(tmp);
6633 }
21aeb343 6634 store_reg_bx(env, s, rd, tmp);
9ee6e8bb
PB		 6635 break;
6636 case 0x0d:
6637 if (logic_cc && rd == 15) {
6638 /* MOVS r15, ... is used for exception return. */
e9bb4aa9 6639 if (IS_USER(s)) {
9ee6e8bb 6640 goto illegal_op;
e9bb4aa9
JR		 6641 }
6642 gen_exception_return(s, tmp2);
9ee6e8bb 6643 } else {
e9bb4aa9
JR		 6644 if (logic_cc) {
6645 gen_logic_CC(tmp2);
6646 }
21aeb343 6647 store_reg_bx(env, s, rd, tmp2);
9ee6e8bb
PB		 6648 }
6649 break;
6650 case 0x0e:
f669df27 6651 tcg_gen_andc_i32(tmp, tmp, tmp2);
e9bb4aa9
JR		 6652 if (logic_cc) {
6653 gen_logic_CC(tmp);
6654 }
21aeb343 6655 store_reg_bx(env, s, rd, tmp);
9ee6e8bb
PB		 6656 break;
6657 default:
6658 case 0x0f:
e9bb4aa9
JR		 6659 tcg_gen_not_i32(tmp2, tmp2);
6660 if (logic_cc) {
6661 gen_logic_CC(tmp2);
6662 }
21aeb343 6663 store_reg_bx(env, s, rd, tmp2);
9ee6e8bb
PB		 6664 break;
6665 }
e9bb4aa9 6666 if (op1 != 0x0f && op1 != 0x0d) {
7d1b0095 6667 tcg_temp_free_i32(tmp2);
e9bb4aa9 6668 }
9ee6e8bb
PB		 6669 } else {
6670 /* other instructions */
6671 op1 = (insn >> 24) & 0xf;
6672 switch(op1) {
6673 case 0x0:
6674 case 0x1:
6675 /* multiplies, extra load/stores */
6676 sh = (insn >> 5) & 3;
6677 if (sh == 0) {
6678 if (op1 == 0x0) {
6679 rd = (insn >> 16) & 0xf;
6680 rn = (insn >> 12) & 0xf;
6681 rs = (insn >> 8) & 0xf;
6682 rm = (insn) & 0xf;
6683 op1 = (insn >> 20) & 0xf;
6684 switch (op1) {
6685 case 0: case 1: case 2: case 3: case 6:
6686 /* 32 bit mul */
5e3f878a
PB		 6687 tmp = load_reg(s, rs);
6688 tmp2 = load_reg(s, rm);
6689 tcg_gen_mul_i32(tmp, tmp, tmp2);
7d1b0095 6690 tcg_temp_free_i32(tmp2);
9ee6e8bb
PB		 6691 if (insn & (1 << 22)) {
6692 /* Subtract (mls) */
6693 ARCH(6T2);
5e3f878a
PB		 6694 tmp2 = load_reg(s, rn);
6695 tcg_gen_sub_i32(tmp, tmp2, tmp);
7d1b0095 6696 tcg_temp_free_i32(tmp2);
9ee6e8bb
PB		 6697 } else if (insn & (1 << 21)) {
6698 /* Add */
5e3f878a
PB		 6699 tmp2 = load_reg(s, rn);
6700 tcg_gen_add_i32(tmp, tmp, tmp2);
7d1b0095 6701 tcg_temp_free_i32(tmp2);
9ee6e8bb
PB		 6702 }
6703 if (insn & (1 << 20))
5e3f878a
PB		 6704 gen_logic_CC(tmp);
6705 store_reg(s, rd, tmp);
9ee6e8bb 6706 break;
8aac08b1
AJ		 6707 case 4:
6708 /* 64 bit mul double accumulate (UMAAL) */
6709 ARCH(6);
6710 tmp = load_reg(s, rs);
6711 tmp2 = load_reg(s, rm);
6712 tmp64 = gen_mulu_i64_i32(tmp, tmp2);
6713 gen_addq_lo(s, tmp64, rn);
6714 gen_addq_lo(s, tmp64, rd);
6715 gen_storeq_reg(s, rn, rd, tmp64);
6716 tcg_temp_free_i64(tmp64);
6717 break;
6718 case 8: case 9: case 10: case 11:
6719 case 12: case 13: case 14: case 15:
6720 /* 64 bit mul: UMULL, UMLAL, SMULL, SMLAL. */
5e3f878a
PB		 6721 tmp = load_reg(s, rs);
6722 tmp2 = load_reg(s, rm);
8aac08b1 6723 if (insn & (1 << 22)) {
a7812ae4 6724 tmp64 = gen_muls_i64_i32(tmp, tmp2);
8aac08b1 6725 } else {
a7812ae4 6726 tmp64 = gen_mulu_i64_i32(tmp, tmp2);
8aac08b1
AJ		 6727 }
6728 if (insn & (1 << 21)) { /* mult accumulate */
a7812ae4 6729 gen_addq(s, tmp64, rn, rd);
9ee6e8bb 6730 }
8aac08b1 6731 if (insn & (1 << 20)) {
a7812ae4 6732 gen_logicq_cc(tmp64);
8aac08b1 6733 }
a7812ae4 6734 gen_storeq_reg(s, rn, rd, tmp64);
b75263d6 6735 tcg_temp_free_i64(tmp64);
9ee6e8bb 6736 break;
8aac08b1
AJ		 6737 default:
6738 goto illegal_op;
9ee6e8bb
PB		 6739 }
6740 } else {
6741 rn = (insn >> 16) & 0xf;
6742 rd = (insn >> 12) & 0xf;
6743 if (insn & (1 << 23)) {
6744 /* load/store exclusive */
86753403
PB		 6745 op1 = (insn >> 21) & 0x3;
6746 if (op1)
a47f43d2 6747 ARCH(6K);
86753403
PB		 6748 else
6749 ARCH(6);
3174f8e9 6750 addr = tcg_temp_local_new_i32();
98a46317 6751 load_reg_var(s, addr, rn);
9ee6e8bb 6752 if (insn & (1 << 20)) {
86753403
PB		 6753 switch (op1) {
6754 case 0: /* ldrex */
426f5abc 6755 gen_load_exclusive(s, rd, 15, addr, 2);
86753403
PB		 6756 break;
6757 case 1: /* ldrexd */
426f5abc 6758 gen_load_exclusive(s, rd, rd + 1, addr, 3);
86753403
PB		 6759 break;
6760 case 2: /* ldrexb */
426f5abc 6761 gen_load_exclusive(s, rd, 15, addr, 0);
86753403
PB		 6762 break;
6763 case 3: /* ldrexh */
426f5abc 6764 gen_load_exclusive(s, rd, 15, addr, 1);
86753403
PB		 6765 break;
6766 default:
6767 abort();
6768 }
9ee6e8bb
PB		 6769 } else {
6770 rm = insn & 0xf;
86753403
PB		 6771 switch (op1) {
6772 case 0: /* strex */
426f5abc 6773 gen_store_exclusive(s, rd, rm, 15, addr, 2);
86753403
PB		 6774 break;
6775 case 1: /* strexd */
502e64fe 6776 gen_store_exclusive(s, rd, rm, rm + 1, addr, 3);
86753403
PB		 6777 break;
6778 case 2: /* strexb */
426f5abc 6779 gen_store_exclusive(s, rd, rm, 15, addr, 0);
86753403
PB		 6780 break;
6781 case 3: /* strexh */
426f5abc 6782 gen_store_exclusive(s, rd, rm, 15, addr, 1);
86753403
PB		 6783 break;
6784 default:
6785 abort();
6786 }
9ee6e8bb 6787 }
3174f8e9 6788 tcg_temp_free(addr);
9ee6e8bb
PB		 6789 } else {
6790 /* SWP instruction */
6791 rm = (insn) & 0xf;
6792
8984bd2e
PB		 6793 /* ??? This is not really atomic. However we know
6794 we never have multiple CPUs running in parallel,
6795 so it is good enough. */
6796 addr = load_reg(s, rn);
6797 tmp = load_reg(s, rm);
9ee6e8bb 6798 if (insn & (1 << 22)) {
8984bd2e
PB		 6799 tmp2 = gen_ld8u(addr, IS_USER(s));
6800 gen_st8(tmp, addr, IS_USER(s));
9ee6e8bb 6801 } else {
8984bd2e
PB		 6802 tmp2 = gen_ld32(addr, IS_USER(s));
6803 gen_st32(tmp, addr, IS_USER(s));
9ee6e8bb 6804 }
7d1b0095 6805 tcg_temp_free_i32(addr);
8984bd2e 6806 store_reg(s, rd, tmp2);
9ee6e8bb
PB		 6807 }
6808 }
6809 } else {
6810 int address_offset;
6811 int load;
6812 /* Misc load/store */
6813 rn = (insn >> 16) & 0xf;
6814 rd = (insn >> 12) & 0xf;
b0109805 6815 addr = load_reg(s, rn);
9ee6e8bb 6816 if (insn & (1 << 24))
b0109805 6817 gen_add_datah_offset(s, insn, 0, addr);
9ee6e8bb
PB		 6818 address_offset = 0;
6819 if (insn & (1 << 20)) {
6820 /* load */
6821 switch(sh) {
6822 case 1:
b0109805 6823 tmp = gen_ld16u(addr, IS_USER(s));
9ee6e8bb
PB		 6824 break;
6825 case 2:
b0109805 6826 tmp = gen_ld8s(addr, IS_USER(s));
9ee6e8bb
PB		 6827 break;
6828 default:
6829 case 3:
b0109805 6830 tmp = gen_ld16s(addr, IS_USER(s));
9ee6e8bb
PB		 6831 break;
6832 }
6833 load = 1;
6834 } else if (sh & 2) {
6835 /* doubleword */
6836 if (sh & 1) {
6837 /* store */
b0109805
PB		 6838 tmp = load_reg(s, rd);
6839 gen_st32(tmp, addr, IS_USER(s));
6840 tcg_gen_addi_i32(addr, addr, 4);
6841 tmp = load_reg(s, rd + 1);
6842 gen_st32(tmp, addr, IS_USER(s));
9ee6e8bb
PB		 6843 load = 0;
6844 } else {
6845 /* load */
b0109805
PB		 6846 tmp = gen_ld32(addr, IS_USER(s));
6847 store_reg(s, rd, tmp);
6848 tcg_gen_addi_i32(addr, addr, 4);
6849 tmp = gen_ld32(addr, IS_USER(s));
9ee6e8bb
PB		 6850 rd++;
6851 load = 1;
6852 }
6853 address_offset = -4;
6854 } else {
6855 /* store */
b0109805
PB		 6856 tmp = load_reg(s, rd);
6857 gen_st16(tmp, addr, IS_USER(s));
9ee6e8bb
PB		 6858 load = 0;
6859 }
6860 /* Perform base writeback before the loaded value to
6861 ensure correct behavior with overlapping index registers.
6862 ldrd with base writeback is is undefined if the
6863 destination and index registers overlap. */
6864 if (!(insn & (1 << 24))) {
b0109805
PB		 6865 gen_add_datah_offset(s, insn, address_offset, addr);
6866 store_reg(s, rn, addr);
9ee6e8bb
PB		 6867 } else if (insn & (1 << 21)) {
6868 if (address_offset)
b0109805
PB		 6869 tcg_gen_addi_i32(addr, addr, address_offset);
6870 store_reg(s, rn, addr);
6871 } else {
7d1b0095 6872 tcg_temp_free_i32(addr);
9ee6e8bb
PB		 6873 }
6874 if (load) {
6875 /* Complete the load. */
b0109805 6876 store_reg(s, rd, tmp);
9ee6e8bb
PB		 6877 }
6878 }
6879 break;
6880 case 0x4:
6881 case 0x5:
6882 goto do_ldst;
6883 case 0x6:
6884 case 0x7:
6885 if (insn & (1 << 4)) {
6886 ARCH(6);
6887 /* Armv6 Media instructions. */
6888 rm = insn & 0xf;
6889 rn = (insn >> 16) & 0xf;
2c0262af 6890 rd = (insn >> 12) & 0xf;
9ee6e8bb
PB		 6891 rs = (insn >> 8) & 0xf;
6892 switch ((insn >> 23) & 3) {
6893 case 0: /* Parallel add/subtract. */
6894 op1 = (insn >> 20) & 7;
6ddbc6e4
PB		 6895 tmp = load_reg(s, rn);
6896 tmp2 = load_reg(s, rm);
9ee6e8bb
PB		 6897 sh = (insn >> 5) & 7;
6898 if ((op1 & 3) == 0 || sh == 5 || sh == 6)
6899 goto illegal_op;
6ddbc6e4 6900 gen_arm_parallel_addsub(op1, sh, tmp, tmp2);
7d1b0095 6901 tcg_temp_free_i32(tmp2);
6ddbc6e4 6902 store_reg(s, rd, tmp);
9ee6e8bb
PB		 6903 break;
6904 case 1:
6905 if ((insn & 0x00700020) == 0) {
6c95676b 6906 /* Halfword pack. */
3670669c
PB		 6907 tmp = load_reg(s, rn);
6908 tmp2 = load_reg(s, rm);
9ee6e8bb 6909 shift = (insn >> 7) & 0x1f;
3670669c
PB		 6910 if (insn & (1 << 6)) {
6911 /* pkhtb */
22478e79
AZ		 6912 if (shift == 0)
6913 shift = 31;
6914 tcg_gen_sari_i32(tmp2, tmp2, shift);
3670669c 6915 tcg_gen_andi_i32(tmp, tmp, 0xffff0000);
86831435 6916 tcg_gen_ext16u_i32(tmp2, tmp2);
3670669c
PB		 6917 } else {
6918 /* pkhbt */
22478e79
AZ		 6919 if (shift)
6920 tcg_gen_shli_i32(tmp2, tmp2, shift);
86831435 6921 tcg_gen_ext16u_i32(tmp, tmp);
3670669c
PB		 6922 tcg_gen_andi_i32(tmp2, tmp2, 0xffff0000);
6923 }
6924 tcg_gen_or_i32(tmp, tmp, tmp2);
7d1b0095 6925 tcg_temp_free_i32(tmp2);
3670669c 6926 store_reg(s, rd, tmp);
9ee6e8bb
PB		 6927 } else if ((insn & 0x00200020) == 0x00200000) {
6928 /* [us]sat */
6ddbc6e4 6929 tmp = load_reg(s, rm);
9ee6e8bb
PB		 6930 shift = (insn >> 7) & 0x1f;
6931 if (insn & (1 << 6)) {
6932 if (shift == 0)
6933 shift = 31;
6ddbc6e4 6934 tcg_gen_sari_i32(tmp, tmp, shift);
9ee6e8bb 6935 } else {
6ddbc6e4 6936 tcg_gen_shli_i32(tmp, tmp, shift);
9ee6e8bb
PB		 6937 }
6938 sh = (insn >> 16) & 0x1f;
40d3c433
CL		 6939 tmp2 = tcg_const_i32(sh);
6940 if (insn & (1 << 22))
6941 gen_helper_usat(tmp, tmp, tmp2);
6942 else
6943 gen_helper_ssat(tmp, tmp, tmp2);
6944 tcg_temp_free_i32(tmp2);
6ddbc6e4 6945 store_reg(s, rd, tmp);
9ee6e8bb
PB		 6946 } else if ((insn & 0x00300fe0) == 0x00200f20) {
6947 /* [us]sat16 */
6ddbc6e4 6948 tmp = load_reg(s, rm);
9ee6e8bb 6949 sh = (insn >> 16) & 0x1f;
40d3c433
CL		 6950 tmp2 = tcg_const_i32(sh);
6951 if (insn & (1 << 22))
6952 gen_helper_usat16(tmp, tmp, tmp2);
6953 else
6954 gen_helper_ssat16(tmp, tmp, tmp2);
6955 tcg_temp_free_i32(tmp2);
6ddbc6e4 6956 store_reg(s, rd, tmp);
9ee6e8bb
PB		 6957 } else if ((insn & 0x00700fe0) == 0x00000fa0) {
6958 /* Select bytes. */
6ddbc6e4
PB		 6959 tmp = load_reg(s, rn);
6960 tmp2 = load_reg(s, rm);
7d1b0095 6961 tmp3 = tcg_temp_new_i32();
6ddbc6e4
PB		 6962 tcg_gen_ld_i32(tmp3, cpu_env, offsetof(CPUState, GE));
6963 gen_helper_sel_flags(tmp, tmp3, tmp, tmp2);
7d1b0095
PM		 6964 tcg_temp_free_i32(tmp3);
6965 tcg_temp_free_i32(tmp2);
6ddbc6e4 6966 store_reg(s, rd, tmp);
9ee6e8bb 6967 } else if ((insn & 0x000003e0) == 0x00000060) {
5e3f878a 6968 tmp = load_reg(s, rm);
9ee6e8bb
PB		 6969 shift = (insn >> 10) & 3;
6970 /* ??? In many cases it's not neccessary to do a
6971 rotate, a shift is sufficient. */
6972 if (shift != 0)
f669df27 6973 tcg_gen_rotri_i32(tmp, tmp, shift * 8);
9ee6e8bb
PB		 6974 op1 = (insn >> 20) & 7;
6975 switch (op1) {
5e3f878a
PB		 6976 case 0: gen_sxtb16(tmp); break;
6977 case 2: gen_sxtb(tmp); break;
6978 case 3: gen_sxth(tmp); break;
6979 case 4: gen_uxtb16(tmp); break;
6980 case 6: gen_uxtb(tmp); break;
6981 case 7: gen_uxth(tmp); break;
9ee6e8bb
PB		 6982 default: goto illegal_op;
6983 }
6984 if (rn != 15) {
5e3f878a 6985 tmp2 = load_reg(s, rn);
9ee6e8bb 6986 if ((op1 & 3) == 0) {
5e3f878a 6987 gen_add16(tmp, tmp2);
9ee6e8bb 6988 } else {
5e3f878a 6989 tcg_gen_add_i32(tmp, tmp, tmp2);
7d1b0095 6990 tcg_temp_free_i32(tmp2);
9ee6e8bb
PB		 6991 }
6992 }
6c95676b 6993 store_reg(s, rd, tmp);
9ee6e8bb
PB		 6994 } else if ((insn & 0x003f0f60) == 0x003f0f20) {
6995 /* rev */
b0109805 6996 tmp = load_reg(s, rm);
9ee6e8bb
PB		 6997 if (insn & (1 << 22)) {
6998 if (insn & (1 << 7)) {
b0109805 6999 gen_revsh(tmp);
9ee6e8bb
PB		 7000 } else {
7001 ARCH(6T2);
b0109805 7002 gen_helper_rbit(tmp, tmp);
9ee6e8bb
PB		 7003 }
7004 } else {
7005 if (insn & (1 << 7))
b0109805 7006 gen_rev16(tmp);
9ee6e8bb 7007 else
66896cb8 7008 tcg_gen_bswap32_i32(tmp, tmp);
9ee6e8bb 7009 }
b0109805 7010 store_reg(s, rd, tmp);
9ee6e8bb
PB		 7011 } else {
7012 goto illegal_op;
7013 }
7014 break;
7015 case 2: /* Multiplies (Type 3). */
5e3f878a
PB		 7016 tmp = load_reg(s, rm);
7017 tmp2 = load_reg(s, rs);
9ee6e8bb 7018 if (insn & (1 << 20)) {
838fa72d
AJ		 7019 /* Signed multiply most significant [accumulate].
7020 (SMMUL, SMMLA, SMMLS) */
a7812ae4 7021 tmp64 = gen_muls_i64_i32(tmp, tmp2);
838fa72d 7022
955a7dd5 7023 if (rd != 15) {
838fa72d 7024 tmp = load_reg(s, rd);
9ee6e8bb 7025 if (insn & (1 << 6)) {
838fa72d 7026 tmp64 = gen_subq_msw(tmp64, tmp);
9ee6e8bb 7027 } else {
838fa72d 7028 tmp64 = gen_addq_msw(tmp64, tmp);
9ee6e8bb
PB		 7029 }
7030 }
838fa72d
AJ		 7031 if (insn & (1 << 5)) {
7032 tcg_gen_addi_i64(tmp64, tmp64, 0x80000000u);
7033 }
7034 tcg_gen_shri_i64(tmp64, tmp64, 32);
7d1b0095 7035 tmp = tcg_temp_new_i32();
838fa72d
AJ		 7036 tcg_gen_trunc_i64_i32(tmp, tmp64);
7037 tcg_temp_free_i64(tmp64);
955a7dd5 7038 store_reg(s, rn, tmp);
9ee6e8bb
PB		 7039 } else {
7040 if (insn & (1 << 5))
5e3f878a
PB		 7041 gen_swap_half(tmp2);
7042 gen_smul_dual(tmp, tmp2);
5e3f878a 7043 if (insn & (1 << 6)) {
e1d177b9 7044 /* This subtraction cannot overflow. */
5e3f878a
PB		 7045 tcg_gen_sub_i32(tmp, tmp, tmp2);
7046 } else {
e1d177b9
PM		 7047 /* This addition cannot overflow 32 bits;
7048 * however it may overflow considered as a signed
7049 * operation, in which case we must set the Q flag.
7050 */
7051 gen_helper_add_setq(tmp, tmp, tmp2);
5e3f878a 7052 }
7d1b0095 7053 tcg_temp_free_i32(tmp2);
9ee6e8bb 7054 if (insn & (1 << 22)) {
5e3f878a 7055 /* smlald, smlsld */
a7812ae4
PB		 7056 tmp64 = tcg_temp_new_i64();
7057 tcg_gen_ext_i32_i64(tmp64, tmp);
7d1b0095 7058 tcg_temp_free_i32(tmp);
a7812ae4
PB		 7059 gen_addq(s, tmp64, rd, rn);
7060 gen_storeq_reg(s, rd, rn, tmp64);
b75263d6 7061 tcg_temp_free_i64(tmp64);
9ee6e8bb 7062 } else {
5e3f878a 7063 /* smuad, smusd, smlad, smlsd */
22478e79 7064 if (rd != 15)
9ee6e8bb 7065 {
22478e79 7066 tmp2 = load_reg(s, rd);
5e3f878a 7067 gen_helper_add_setq(tmp, tmp, tmp2);
7d1b0095 7068 tcg_temp_free_i32(tmp2);
9ee6e8bb 7069 }
22478e79 7070 store_reg(s, rn, tmp);
9ee6e8bb
PB		 7071 }
7072 }
7073 break;
7074 case 3:
7075 op1 = ((insn >> 17) & 0x38) | ((insn >> 5) & 7);
7076 switch (op1) {
7077 case 0: /* Unsigned sum of absolute differences. */
6ddbc6e4
PB		 7078 ARCH(6);
7079 tmp = load_reg(s, rm);
7080 tmp2 = load_reg(s, rs);
7081 gen_helper_usad8(tmp, tmp, tmp2);
7d1b0095 7082 tcg_temp_free_i32(tmp2);
ded9d295
AZ		 7083 if (rd != 15) {
7084 tmp2 = load_reg(s, rd);
6ddbc6e4 7085 tcg_gen_add_i32(tmp, tmp, tmp2);
7d1b0095 7086 tcg_temp_free_i32(tmp2);
9ee6e8bb 7087 }
ded9d295 7088 store_reg(s, rn, tmp);
9ee6e8bb
PB		 7089 break;
7090 case 0x20: case 0x24: case 0x28: case 0x2c:
7091 /* Bitfield insert/clear. */
7092 ARCH(6T2);
7093 shift = (insn >> 7) & 0x1f;
7094 i = (insn >> 16) & 0x1f;
7095 i = i + 1 - shift;
7096 if (rm == 15) {
7d1b0095 7097 tmp = tcg_temp_new_i32();
5e3f878a 7098 tcg_gen_movi_i32(tmp, 0);
9ee6e8bb 7099 } else {
5e3f878a 7100 tmp = load_reg(s, rm);
9ee6e8bb
PB		 7101 }
7102 if (i != 32) {
5e3f878a 7103 tmp2 = load_reg(s, rd);
8f8e3aa4 7104 gen_bfi(tmp, tmp2, tmp, shift, (1u << i) - 1);
7d1b0095 7105 tcg_temp_free_i32(tmp2);
9ee6e8bb 7106 }
5e3f878a 7107 store_reg(s, rd, tmp);
9ee6e8bb
PB		 7108 break;
7109 case 0x12: case 0x16: case 0x1a: case 0x1e: /* sbfx */
7110 case 0x32: case 0x36: case 0x3a: case 0x3e: /* ubfx */
4cc633c3 7111 ARCH(6T2);
5e3f878a 7112 tmp = load_reg(s, rm);
9ee6e8bb
PB		 7113 shift = (insn >> 7) & 0x1f;
7114 i = ((insn >> 16) & 0x1f) + 1;
7115 if (shift + i > 32)
7116 goto illegal_op;
7117 if (i < 32) {
7118 if (op1 & 0x20) {
5e3f878a 7119 gen_ubfx(tmp, shift, (1u << i) - 1);
9ee6e8bb 7120 } else {
5e3f878a 7121 gen_sbfx(tmp, shift, i);
9ee6e8bb
PB		 7122 }
7123 }
5e3f878a 7124 store_reg(s, rd, tmp);
9ee6e8bb
PB		 7125 break;
7126 default:
7127 goto illegal_op;
7128 }
7129 break;
7130 }
7131 break;
7132 }
7133 do_ldst:
7134 /* Check for undefined extension instructions
7135 * per the ARM Bible IE:
7136 * xxxx 0111 1111 xxxx xxxx xxxx 1111 xxxx
7137 */
7138 sh = (0xf << 20) | (0xf << 4);
7139 if (op1 == 0x7 && ((insn & sh) == sh))
7140 {
7141 goto illegal_op;
7142 }
7143 /* load/store byte/word */
7144 rn = (insn >> 16) & 0xf;
7145 rd = (insn >> 12) & 0xf;
b0109805 7146 tmp2 = load_reg(s, rn);
9ee6e8bb
PB		 7147 i = (IS_USER(s) || (insn & 0x01200000) == 0x00200000);
7148 if (insn & (1 << 24))
b0109805 7149 gen_add_data_offset(s, insn, tmp2);
9ee6e8bb
PB		 7150 if (insn & (1 << 20)) {
7151 /* load */
9ee6e8bb 7152 if (insn & (1 << 22)) {
b0109805 7153 tmp = gen_ld8u(tmp2, i);
9ee6e8bb 7154 } else {
b0109805 7155 tmp = gen_ld32(tmp2, i);
9ee6e8bb 7156 }
9ee6e8bb
PB		 7157 } else {
7158 /* store */
b0109805 7159 tmp = load_reg(s, rd);
9ee6e8bb 7160 if (insn & (1 << 22))
b0109805 7161 gen_st8(tmp, tmp2, i);
9ee6e8bb 7162 else
b0109805 7163 gen_st32(tmp, tmp2, i);
9ee6e8bb
PB		 7164 }
7165 if (!(insn & (1 << 24))) {
b0109805
PB		 7166 gen_add_data_offset(s, insn, tmp2);
7167 store_reg(s, rn, tmp2);
7168 } else if (insn & (1 << 21)) {
7169 store_reg(s, rn, tmp2);
7170 } else {
7d1b0095 7171 tcg_temp_free_i32(tmp2);
9ee6e8bb
PB		 7172 }
7173 if (insn & (1 << 20)) {
7174 /* Complete the load. */
7175 if (rd == 15)
b0109805 7176 gen_bx(s, tmp);
9ee6e8bb 7177 else
b0109805 7178 store_reg(s, rd, tmp);
9ee6e8bb
PB		 7179 }
7180 break;
7181 case 0x08:
7182 case 0x09:
7183 {
7184 int j, n, user, loaded_base;
b0109805 7185 TCGv loaded_var;
9ee6e8bb
PB		 7186 /* load/store multiple words */
7187 /* XXX: store correct base if write back */
7188 user = 0;
7189 if (insn & (1 << 22)) {
7190 if (IS_USER(s))
7191 goto illegal_op; /* only usable in supervisor mode */
7192
7193 if ((insn & (1 << 15)) == 0)
7194 user = 1;
7195 }
7196 rn = (insn >> 16) & 0xf;
b0109805 7197 addr = load_reg(s, rn);
9ee6e8bb
PB		 7198
7199 /* compute total size */
7200 loaded_base = 0;
a50f5b91 7201 TCGV_UNUSED(loaded_var);
9ee6e8bb
PB		 7202 n = 0;
7203 for(i=0;i<16;i++) {
7204 if (insn & (1 << i))
7205 n++;
7206 }
7207 /* XXX: test invalid n == 0 case ? */
7208 if (insn & (1 << 23)) {
7209 if (insn & (1 << 24)) {
7210 /* pre increment */
b0109805 7211 tcg_gen_addi_i32(addr, addr, 4);
9ee6e8bb
PB		 7212 } else {
7213 /* post increment */
7214 }
7215 } else {
7216 if (insn & (1 << 24)) {
7217 /* pre decrement */
b0109805 7218 tcg_gen_addi_i32(addr, addr, -(n * 4));
9ee6e8bb
PB		 7219 } else {
7220 /* post decrement */
7221 if (n != 1)
b0109805 7222 tcg_gen_addi_i32(addr, addr, -((n - 1) * 4));
9ee6e8bb
PB		 7223 }
7224 }
7225 j = 0;
7226 for(i=0;i<16;i++) {
7227 if (insn & (1 << i)) {
7228 if (insn & (1 << 20)) {
7229 /* load */
b0109805 7230 tmp = gen_ld32(addr, IS_USER(s));
9ee6e8bb 7231 if (i == 15) {
b0109805 7232 gen_bx(s, tmp);
9ee6e8bb 7233 } else if (user) {
b75263d6
JR		 7234 tmp2 = tcg_const_i32(i);
7235 gen_helper_set_user_reg(tmp2, tmp);
7236 tcg_temp_free_i32(tmp2);
7d1b0095 7237 tcg_temp_free_i32(tmp);
9ee6e8bb 7238 } else if (i == rn) {
b0109805 7239 loaded_var = tmp;
9ee6e8bb
PB		 7240 loaded_base = 1;
7241 } else {
b0109805 7242 store_reg(s, i, tmp);
9ee6e8bb
PB		 7243 }
7244 } else {
7245 /* store */
7246 if (i == 15) {
7247 /* special case: r15 = PC + 8 */
7248 val = (long)s->pc + 4;
7d1b0095 7249 tmp = tcg_temp_new_i32();
b0109805 7250 tcg_gen_movi_i32(tmp, val);
9ee6e8bb 7251 } else if (user) {
7d1b0095 7252 tmp = tcg_temp_new_i32();
b75263d6
JR		 7253 tmp2 = tcg_const_i32(i);
7254 gen_helper_get_user_reg(tmp, tmp2);
7255 tcg_temp_free_i32(tmp2);
9ee6e8bb 7256 } else {
b0109805 7257 tmp = load_reg(s, i);
9ee6e8bb 7258 }
b0109805 7259 gen_st32(tmp, addr, IS_USER(s));
9ee6e8bb
PB		 7260 }
7261 j++;
7262 /* no need to add after the last transfer */
7263 if (j != n)
b0109805 7264 tcg_gen_addi_i32(addr, addr, 4);
9ee6e8bb
PB		 7265 }
7266 }
7267 if (insn & (1 << 21)) {
7268 /* write back */
7269 if (insn & (1 << 23)) {
7270 if (insn & (1 << 24)) {
7271 /* pre increment */
7272 } else {
7273 /* post increment */
b0109805 7274 tcg_gen_addi_i32(addr, addr, 4);
9ee6e8bb
PB		 7275 }
7276 } else {
7277 if (insn & (1 << 24)) {
7278 /* pre decrement */
7279 if (n != 1)
b0109805 7280 tcg_gen_addi_i32(addr, addr, -((n - 1) * 4));
9ee6e8bb
PB		 7281 } else {
7282 /* post decrement */
b0109805 7283 tcg_gen_addi_i32(addr, addr, -(n * 4));
9ee6e8bb
PB		 7284 }
7285 }
b0109805
PB		 7286 store_reg(s, rn, addr);
7287 } else {
7d1b0095 7288 tcg_temp_free_i32(addr);
9ee6e8bb
PB		 7289 }
7290 if (loaded_base) {
b0109805 7291 store_reg(s, rn, loaded_var);
9ee6e8bb
PB		 7292 }
7293 if ((insn & (1 << 22)) && !user) {
7294 /* Restore CPSR from SPSR. */
d9ba4830
PB		 7295 tmp = load_cpu_field(spsr);
7296 gen_set_cpsr(tmp, 0xffffffff);
7d1b0095 7297 tcg_temp_free_i32(tmp);
9ee6e8bb
PB		 7298 s->is_jmp = DISAS_UPDATE;
7299 }
7300 }
7301 break;
7302 case 0xa:
7303 case 0xb:
7304 {
7305 int32_t offset;
7306
7307 /* branch (and link) */
7308 val = (int32_t)s->pc;
7309 if (insn & (1 << 24)) {
7d1b0095 7310 tmp = tcg_temp_new_i32();
5e3f878a
PB		 7311 tcg_gen_movi_i32(tmp, val);
7312 store_reg(s, 14, tmp);
9ee6e8bb
PB		 7313 }
7314 offset = (((int32_t)insn << 8) >> 8);
7315 val += (offset << 2) + 4;
7316 gen_jmp(s, val);
7317 }
7318 break;
7319 case 0xc:
7320 case 0xd:
7321 case 0xe:
7322 /* Coprocessor. */
7323 if (disas_coproc_insn(env, s, insn))
7324 goto illegal_op;
7325 break;
7326 case 0xf:
7327 /* swi */
5e3f878a 7328 gen_set_pc_im(s->pc);
9ee6e8bb
PB		 7329 s->is_jmp = DISAS_SWI;
7330 break;
7331 default:
7332 illegal_op:
bc4a0de0 7333 gen_exception_insn(s, 4, EXCP_UDEF);
9ee6e8bb
PB		 7334 break;
7335 }
7336 }
7337}
7338
7339/* Return true if this is a Thumb-2 logical op. */
7340static int
7341thumb2_logic_op(int op)
7342{
7343 return (op < 8);
7344}
7345
7346/* Generate code for a Thumb-2 data processing operation. If CONDS is nonzero
7347 then set condition code flags based on the result of the operation.
7348 If SHIFTER_OUT is nonzero then set the carry flag for logical operations
7349 to the high bit of T1.
7350 Returns zero if the opcode is valid. */
7351
7352static int
396e467c 7353gen_thumb2_data_op(DisasContext *s, int op, int conds, uint32_t shifter_out, TCGv t0, TCGv t1)
9ee6e8bb
PB		 7354{
7355 int logic_cc;
7356
7357 logic_cc = 0;
7358 switch (op) {
7359 case 0: /* and */
396e467c 7360 tcg_gen_and_i32(t0, t0, t1);
9ee6e8bb
PB		 7361 logic_cc = conds;
7362 break;
7363 case 1: /* bic */
f669df27 7364 tcg_gen_andc_i32(t0, t0, t1);
9ee6e8bb
PB		 7365 logic_cc = conds;
7366 break;
7367 case 2: /* orr */
396e467c 7368 tcg_gen_or_i32(t0, t0, t1);
9ee6e8bb
PB		 7369 logic_cc = conds;
7370 break;
7371 case 3: /* orn */
29501f1b 7372 tcg_gen_orc_i32(t0, t0, t1);
9ee6e8bb
PB		 7373 logic_cc = conds;
7374 break;
7375 case 4: /* eor */
396e467c 7376 tcg_gen_xor_i32(t0, t0, t1);
9ee6e8bb
PB		 7377 logic_cc = conds;
7378 break;
7379 case 8: /* add */
7380 if (conds)
396e467c 7381 gen_helper_add_cc(t0, t0, t1);
9ee6e8bb 7382 else
396e467c 7383 tcg_gen_add_i32(t0, t0, t1);
9ee6e8bb
PB		 7384 break;
7385 case 10: /* adc */
7386 if (conds)
396e467c 7387 gen_helper_adc_cc(t0, t0, t1);
9ee6e8bb 7388 else
396e467c 7389 gen_adc(t0, t1);
9ee6e8bb
PB		 7390 break;
7391 case 11: /* sbc */
7392 if (conds)
396e467c 7393 gen_helper_sbc_cc(t0, t0, t1);
9ee6e8bb 7394 else
396e467c 7395 gen_sub_carry(t0, t0, t1);
9ee6e8bb
PB		 7396 break;
7397 case 13: /* sub */
7398 if (conds)
396e467c 7399 gen_helper_sub_cc(t0, t0, t1);
9ee6e8bb 7400 else
396e467c 7401 tcg_gen_sub_i32(t0, t0, t1);
9ee6e8bb
PB		 7402 break;
7403 case 14: /* rsb */
7404 if (conds)
396e467c 7405 gen_helper_sub_cc(t0, t1, t0);
9ee6e8bb 7406 else
396e467c 7407 tcg_gen_sub_i32(t0, t1, t0);
9ee6e8bb
PB		 7408 break;
7409 default: /* 5, 6, 7, 9, 12, 15. */
7410 return 1;
7411 }
7412 if (logic_cc) {
396e467c 7413 gen_logic_CC(t0);
9ee6e8bb 7414 if (shifter_out)
396e467c 7415 gen_set_CF_bit31(t1);
9ee6e8bb
PB		 7416 }
7417 return 0;
7418}
7419
7420/* Translate a 32-bit thumb instruction. Returns nonzero if the instruction
7421 is not legal. */
7422static int disas_thumb2_insn(CPUState *env, DisasContext *s, uint16_t insn_hw1)
7423{
b0109805 7424 uint32_t insn, imm, shift, offset;
9ee6e8bb 7425 uint32_t rd, rn, rm, rs;
b26eefb6 7426 TCGv tmp;
6ddbc6e4
PB		 7427 TCGv tmp2;
7428 TCGv tmp3;
b0109805 7429 TCGv addr;
a7812ae4 7430 TCGv_i64 tmp64;
9ee6e8bb
PB		 7431 int op;
7432 int shiftop;
7433 int conds;
7434 int logic_cc;
7435
7436 if (!(arm_feature(env, ARM_FEATURE_THUMB2)
7437 || arm_feature (env, ARM_FEATURE_M))) {
601d70b9 7438 /* Thumb-1 cores may need to treat bl and blx as a pair of
9ee6e8bb
PB		 7439 16-bit instructions to get correct prefetch abort behavior. */
7440 insn = insn_hw1;
7441 if ((insn & (1 << 12)) == 0) {
7442 /* Second half of blx. */
7443 offset = ((insn & 0x7ff) << 1);
d9ba4830
PB		 7444 tmp = load_reg(s, 14);
7445 tcg_gen_addi_i32(tmp, tmp, offset);
7446 tcg_gen_andi_i32(tmp, tmp, 0xfffffffc);
9ee6e8bb 7447
7d1b0095 7448 tmp2 = tcg_temp_new_i32();
b0109805 7449 tcg_gen_movi_i32(tmp2, s->pc | 1);
d9ba4830
PB		 7450 store_reg(s, 14, tmp2);
7451 gen_bx(s, tmp);
9ee6e8bb
PB		 7452 return 0;
7453 }
7454 if (insn & (1 << 11)) {
7455 /* Second half of bl. */
7456 offset = ((insn & 0x7ff) << 1) | 1;
d9ba4830 7457 tmp = load_reg(s, 14);
6a0d8a1d 7458 tcg_gen_addi_i32(tmp, tmp, offset);
9ee6e8bb 7459
7d1b0095 7460 tmp2 = tcg_temp_new_i32();
b0109805 7461 tcg_gen_movi_i32(tmp2, s->pc | 1);
d9ba4830
PB		 7462 store_reg(s, 14, tmp2);
7463 gen_bx(s, tmp);
9ee6e8bb
PB		 7464 return 0;
7465 }
7466 if ((s->pc & ~TARGET_PAGE_MASK) == 0) {
7467 /* Instruction spans a page boundary. Implement it as two
7468 16-bit instructions in case the second half causes an
7469 prefetch abort. */
7470 offset = ((int32_t)insn << 21) >> 9;
396e467c 7471 tcg_gen_movi_i32(cpu_R[14], s->pc + 2 + offset);
9ee6e8bb
PB		 7472 return 0;
7473 }
7474 /* Fall through to 32-bit decode. */
7475 }
7476
7477 insn = lduw_code(s->pc);
7478 s->pc += 2;
7479 insn |= (uint32_t)insn_hw1 << 16;
7480
7481 if ((insn & 0xf800e800) != 0xf000e800) {
7482 ARCH(6T2);
7483 }
7484
7485 rn = (insn >> 16) & 0xf;
7486 rs = (insn >> 12) & 0xf;
7487 rd = (insn >> 8) & 0xf;
7488 rm = insn & 0xf;
7489 switch ((insn >> 25) & 0xf) {
7490 case 0: case 1: case 2: case 3:
7491 /* 16-bit instructions. Should never happen. */
7492 abort();
7493 case 4:
7494 if (insn & (1 << 22)) {
7495 /* Other load/store, table branch. */
7496 if (insn & 0x01200000) {
7497 /* Load/store doubleword. */
7498 if (rn == 15) {
7d1b0095 7499 addr = tcg_temp_new_i32();
b0109805 7500 tcg_gen_movi_i32(addr, s->pc & ~3);
9ee6e8bb 7501 } else {
b0109805 7502 addr = load_reg(s, rn);
9ee6e8bb
PB		 7503 }
7504 offset = (insn & 0xff) * 4;
7505 if ((insn & (1 << 23)) == 0)
7506 offset = -offset;
7507 if (insn & (1 << 24)) {
b0109805 7508 tcg_gen_addi_i32(addr, addr, offset);
9ee6e8bb
PB		 7509 offset = 0;
7510 }
7511 if (insn & (1 << 20)) {
7512 /* ldrd */
b0109805
PB		 7513 tmp = gen_ld32(addr, IS_USER(s));
7514 store_reg(s, rs, tmp);
7515 tcg_gen_addi_i32(addr, addr, 4);
7516 tmp = gen_ld32(addr, IS_USER(s));
7517 store_reg(s, rd, tmp);
9ee6e8bb
PB		 7518 } else {
7519 /* strd */
b0109805
PB		 7520 tmp = load_reg(s, rs);
7521 gen_st32(tmp, addr, IS_USER(s));
7522 tcg_gen_addi_i32(addr, addr, 4);
7523 tmp = load_reg(s, rd);
7524 gen_st32(tmp, addr, IS_USER(s));
9ee6e8bb
PB		 7525 }
7526 if (insn & (1 << 21)) {
7527 /* Base writeback. */
7528 if (rn == 15)
7529 goto illegal_op;
b0109805
PB		 7530 tcg_gen_addi_i32(addr, addr, offset - 4);
7531 store_reg(s, rn, addr);
7532 } else {
7d1b0095 7533 tcg_temp_free_i32(addr);
9ee6e8bb
PB		 7534 }
7535 } else if ((insn & (1 << 23)) == 0) {
7536 /* Load/store exclusive word. */
3174f8e9 7537 addr = tcg_temp_local_new();
98a46317 7538 load_reg_var(s, addr, rn);
426f5abc 7539 tcg_gen_addi_i32(addr, addr, (insn & 0xff) << 2);
2c0262af 7540 if (insn & (1 << 20)) {
426f5abc 7541 gen_load_exclusive(s, rs, 15, addr, 2);
9ee6e8bb 7542 } else {
426f5abc 7543 gen_store_exclusive(s, rd, rs, 15, addr, 2);
9ee6e8bb 7544 }
3174f8e9 7545 tcg_temp_free(addr);
9ee6e8bb
PB		 7546 } else if ((insn & (1 << 6)) == 0) {
7547 /* Table Branch. */
7548 if (rn == 15) {
7d1b0095 7549 addr = tcg_temp_new_i32();
b0109805 7550 tcg_gen_movi_i32(addr, s->pc);
9ee6e8bb 7551 } else {
b0109805 7552 addr = load_reg(s, rn);
9ee6e8bb 7553 }
b26eefb6 7554 tmp = load_reg(s, rm);
b0109805 7555 tcg_gen_add_i32(addr, addr, tmp);
9ee6e8bb
PB		 7556 if (insn & (1 << 4)) {
7557 /* tbh */
b0109805 7558 tcg_gen_add_i32(addr, addr, tmp);
7d1b0095 7559 tcg_temp_free_i32(tmp);
b0109805 7560 tmp = gen_ld16u(addr, IS_USER(s));
9ee6e8bb 7561 } else { /* tbb */
7d1b0095 7562 tcg_temp_free_i32(tmp);
b0109805 7563 tmp = gen_ld8u(addr, IS_USER(s));
9ee6e8bb 7564 }
7d1b0095 7565 tcg_temp_free_i32(addr);
b0109805
PB		 7566 tcg_gen_shli_i32(tmp, tmp, 1);
7567 tcg_gen_addi_i32(tmp, tmp, s->pc);
7568 store_reg(s, 15, tmp);
9ee6e8bb
PB		 7569 } else {
7570 /* Load/store exclusive byte/halfword/doubleword. */
426f5abc 7571 ARCH(7);
9ee6e8bb 7572 op = (insn >> 4) & 0x3;
426f5abc
PB		 7573 if (op == 2) {
7574 goto illegal_op;
7575 }
3174f8e9 7576 addr = tcg_temp_local_new();
98a46317 7577 load_reg_var(s, addr, rn);
9ee6e8bb 7578 if (insn & (1 << 20)) {
426f5abc 7579 gen_load_exclusive(s, rs, rd, addr, op);
9ee6e8bb 7580 } else {
426f5abc 7581 gen_store_exclusive(s, rm, rs, rd, addr, op);
9ee6e8bb 7582 }
3174f8e9 7583 tcg_temp_free(addr);
9ee6e8bb
PB		 7584 }
7585 } else {
7586 /* Load/store multiple, RFE, SRS. */
7587 if (((insn >> 23) & 1) == ((insn >> 24) & 1)) {
7588 /* Not available in user mode. */
b0109805 7589 if (IS_USER(s))
9ee6e8bb
PB		 7590 goto illegal_op;
7591 if (insn & (1 << 20)) {
7592 /* rfe */
b0109805
PB		 7593 addr = load_reg(s, rn);
7594 if ((insn & (1 << 24)) == 0)
7595 tcg_gen_addi_i32(addr, addr, -8);
7596 /* Load PC into tmp and CPSR into tmp2. */
7597 tmp = gen_ld32(addr, 0);
7598 tcg_gen_addi_i32(addr, addr, 4);
7599 tmp2 = gen_ld32(addr, 0);
9ee6e8bb
PB		 7600 if (insn & (1 << 21)) {
7601 /* Base writeback. */
b0109805
PB		 7602 if (insn & (1 << 24)) {
7603 tcg_gen_addi_i32(addr, addr, 4);
7604 } else {
7605 tcg_gen_addi_i32(addr, addr, -4);
7606 }
7607 store_reg(s, rn, addr);
7608 } else {
7d1b0095 7609 tcg_temp_free_i32(addr);
9ee6e8bb 7610 }
b0109805 7611 gen_rfe(s, tmp, tmp2);
9ee6e8bb
PB		 7612 } else {
7613 /* srs */
7614 op = (insn & 0x1f);
7d1b0095 7615 addr = tcg_temp_new_i32();
39ea3d4e
PM		 7616 tmp = tcg_const_i32(op);
7617 gen_helper_get_r13_banked(addr, cpu_env, tmp);
7618 tcg_temp_free_i32(tmp);
9ee6e8bb 7619 if ((insn & (1 << 24)) == 0) {
b0109805 7620 tcg_gen_addi_i32(addr, addr, -8);
9ee6e8bb 7621 }
b0109805
PB		 7622 tmp = load_reg(s, 14);
7623 gen_st32(tmp, addr, 0);
7624 tcg_gen_addi_i32(addr, addr, 4);
7d1b0095 7625 tmp = tcg_temp_new_i32();
b0109805
PB		 7626 gen_helper_cpsr_read(tmp);
7627 gen_st32(tmp, addr, 0);
9ee6e8bb
PB		 7628 if (insn & (1 << 21)) {
7629 if ((insn & (1 << 24)) == 0) {
b0109805 7630 tcg_gen_addi_i32(addr, addr, -4);
9ee6e8bb 7631 } else {
b0109805 7632 tcg_gen_addi_i32(addr, addr, 4);
9ee6e8bb 7633 }
39ea3d4e
PM		 7634 tmp = tcg_const_i32(op);
7635 gen_helper_set_r13_banked(cpu_env, tmp, addr);
7636 tcg_temp_free_i32(tmp);
b0109805 7637 } else {
7d1b0095 7638 tcg_temp_free_i32(addr);
9ee6e8bb
PB		 7639 }
7640 }
7641 } else {
7642 int i;
7643 /* Load/store multiple. */
b0109805 7644 addr = load_reg(s, rn);
9ee6e8bb
PB		 7645 offset = 0;
7646 for (i = 0; i < 16; i++) {
7647 if (insn & (1 << i))
7648 offset += 4;
7649 }
7650 if (insn & (1 << 24)) {
b0109805 7651 tcg_gen_addi_i32(addr, addr, -offset);
9ee6e8bb
PB		 7652 }
7653
7654 for (i = 0; i < 16; i++) {
7655 if ((insn & (1 << i)) == 0)
7656 continue;
7657 if (insn & (1 << 20)) {
7658 /* Load. */
b0109805 7659 tmp = gen_ld32(addr, IS_USER(s));
9ee6e8bb 7660 if (i == 15) {
b0109805 7661 gen_bx(s, tmp);
9ee6e8bb 7662 } else {
b0109805 7663 store_reg(s, i, tmp);
9ee6e8bb
PB		 7664 }
7665 } else {
7666 /* Store. */
b0109805
PB		 7667 tmp = load_reg(s, i);
7668 gen_st32(tmp, addr, IS_USER(s));
9ee6e8bb 7669 }
b0109805 7670 tcg_gen_addi_i32(addr, addr, 4);
9ee6e8bb
PB		 7671 }
7672 if (insn & (1 << 21)) {
7673 /* Base register writeback. */
7674 if (insn & (1 << 24)) {
b0109805 7675 tcg_gen_addi_i32(addr, addr, -offset);
9ee6e8bb
PB		 7676 }
7677 /* Fault if writeback register is in register list. */
7678 if (insn & (1 << rn))
7679 goto illegal_op;
b0109805
PB		 7680 store_reg(s, rn, addr);
7681 } else {
7d1b0095 7682 tcg_temp_free_i32(addr);
9ee6e8bb
PB		 7683 }
7684 }
7685 }
7686 break;
2af9ab77
JB		 7687 case 5:
7688
9ee6e8bb 7689 op = (insn >> 21) & 0xf;
2af9ab77
JB		 7690 if (op == 6) {
7691 /* Halfword pack. */
7692 tmp = load_reg(s, rn);
7693 tmp2 = load_reg(s, rm);
7694 shift = ((insn >> 10) & 0x1c) | ((insn >> 6) & 0x3);
7695 if (insn & (1 << 5)) {
7696 /* pkhtb */
7697 if (shift == 0)
7698 shift = 31;
7699 tcg_gen_sari_i32(tmp2, tmp2, shift);
7700 tcg_gen_andi_i32(tmp, tmp, 0xffff0000);
7701 tcg_gen_ext16u_i32(tmp2, tmp2);
7702 } else {
7703 /* pkhbt */
7704 if (shift)
7705 tcg_gen_shli_i32(tmp2, tmp2, shift);
7706 tcg_gen_ext16u_i32(tmp, tmp);
7707 tcg_gen_andi_i32(tmp2, tmp2, 0xffff0000);
7708 }
7709 tcg_gen_or_i32(tmp, tmp, tmp2);
7d1b0095 7710 tcg_temp_free_i32(tmp2);
3174f8e9
FN		 7711 store_reg(s, rd, tmp);
7712 } else {
2af9ab77
JB		 7713 /* Data processing register constant shift. */
7714 if (rn == 15) {
7d1b0095 7715 tmp = tcg_temp_new_i32();
2af9ab77
JB		 7716 tcg_gen_movi_i32(tmp, 0);
7717 } else {
7718 tmp = load_reg(s, rn);
7719 }
7720 tmp2 = load_reg(s, rm);
7721
7722 shiftop = (insn >> 4) & 3;
7723 shift = ((insn >> 6) & 3) | ((insn >> 10) & 0x1c);
7724 conds = (insn & (1 << 20)) != 0;
7725 logic_cc = (conds && thumb2_logic_op(op));
7726 gen_arm_shift_im(tmp2, shiftop, shift, logic_cc);
7727 if (gen_thumb2_data_op(s, op, conds, 0, tmp, tmp2))
7728 goto illegal_op;
7d1b0095 7729 tcg_temp_free_i32(tmp2);
2af9ab77
JB		 7730 if (rd != 15) {
7731 store_reg(s, rd, tmp);
7732 } else {
7d1b0095 7733 tcg_temp_free_i32(tmp);
2af9ab77 7734 }
3174f8e9 7735 }
9ee6e8bb
PB		 7736 break;
7737 case 13: /* Misc data processing. */
7738 op = ((insn >> 22) & 6) | ((insn >> 7) & 1);
7739 if (op < 4 && (insn & 0xf000) != 0xf000)
7740 goto illegal_op;
7741 switch (op) {
7742 case 0: /* Register controlled shift. */
8984bd2e
PB		 7743 tmp = load_reg(s, rn);
7744 tmp2 = load_reg(s, rm);
9ee6e8bb
PB		 7745 if ((insn & 0x70) != 0)
7746 goto illegal_op;
7747 op = (insn >> 21) & 3;
8984bd2e
PB		 7748 logic_cc = (insn & (1 << 20)) != 0;
7749 gen_arm_shift_reg(tmp, op, tmp2, logic_cc);
7750 if (logic_cc)
7751 gen_logic_CC(tmp);
21aeb343 7752 store_reg_bx(env, s, rd, tmp);
9ee6e8bb
PB		 7753 break;
7754 case 1: /* Sign/zero extend. */
5e3f878a 7755 tmp = load_reg(s, rm);
9ee6e8bb
PB		 7756 shift = (insn >> 4) & 3;
7757 /* ??? In many cases it's not neccessary to do a
7758 rotate, a shift is sufficient. */
7759 if (shift != 0)
f669df27 7760 tcg_gen_rotri_i32(tmp, tmp, shift * 8);
9ee6e8bb
PB		 7761 op = (insn >> 20) & 7;
7762 switch (op) {
5e3f878a
PB		 7763 case 0: gen_sxth(tmp); break;
7764 case 1: gen_uxth(tmp); break;
7765 case 2: gen_sxtb16(tmp); break;
7766 case 3: gen_uxtb16(tmp); break;
7767 case 4: gen_sxtb(tmp); break;
7768 case 5: gen_uxtb(tmp); break;
9ee6e8bb
PB		 7769 default: goto illegal_op;
7770 }
7771 if (rn != 15) {
5e3f878a 7772 tmp2 = load_reg(s, rn);
9ee6e8bb 7773 if ((op >> 1) == 1) {
5e3f878a 7774 gen_add16(tmp, tmp2);
9ee6e8bb 7775 } else {
5e3f878a 7776 tcg_gen_add_i32(tmp, tmp, tmp2);
7d1b0095 7777 tcg_temp_free_i32(tmp2);
9ee6e8bb
PB		 7778 }
7779 }
5e3f878a 7780 store_reg(s, rd, tmp);
9ee6e8bb
PB		 7781 break;
7782 case 2: /* SIMD add/subtract. */
7783 op = (insn >> 20) & 7;
7784 shift = (insn >> 4) & 7;
7785 if ((op & 3) == 3 || (shift & 3) == 3)
7786 goto illegal_op;
6ddbc6e4
PB		 7787 tmp = load_reg(s, rn);
7788 tmp2 = load_reg(s, rm);
7789 gen_thumb2_parallel_addsub(op, shift, tmp, tmp2);
7d1b0095 7790 tcg_temp_free_i32(tmp2);
6ddbc6e4 7791 store_reg(s, rd, tmp);
9ee6e8bb
PB		 7792 break;
7793 case 3: /* Other data processing. */
7794 op = ((insn >> 17) & 0x38) | ((insn >> 4) & 7);
7795 if (op < 4) {
7796 /* Saturating add/subtract. */
d9ba4830
PB		 7797 tmp = load_reg(s, rn);
7798 tmp2 = load_reg(s, rm);
9ee6e8bb 7799 if (op & 1)
4809c612
JB		 7800 gen_helper_double_saturate(tmp, tmp);
7801 if (op & 2)
d9ba4830 7802 gen_helper_sub_saturate(tmp, tmp2, tmp);
9ee6e8bb 7803 else
d9ba4830 7804 gen_helper_add_saturate(tmp, tmp, tmp2);
7d1b0095 7805 tcg_temp_free_i32(tmp2);
9ee6e8bb 7806 } else {
d9ba4830 7807 tmp = load_reg(s, rn);
9ee6e8bb
PB		 7808 switch (op) {
7809 case 0x0a: /* rbit */
d9ba4830 7810 gen_helper_rbit(tmp, tmp);
9ee6e8bb
PB		 7811 break;
7812 case 0x08: /* rev */
66896cb8 7813 tcg_gen_bswap32_i32(tmp, tmp);
9ee6e8bb
PB		 7814 break;
7815 case 0x09: /* rev16 */
d9ba4830 7816 gen_rev16(tmp);
9ee6e8bb
PB		 7817 break;
7818 case 0x0b: /* revsh */
d9ba4830 7819 gen_revsh(tmp);
9ee6e8bb
PB		 7820 break;
7821 case 0x10: /* sel */
d9ba4830 7822 tmp2 = load_reg(s, rm);
7d1b0095 7823 tmp3 = tcg_temp_new_i32();
6ddbc6e4 7824 tcg_gen_ld_i32(tmp3, cpu_env, offsetof(CPUState, GE));
d9ba4830 7825 gen_helper_sel_flags(tmp, tmp3, tmp, tmp2);
7d1b0095
PM		 7826 tcg_temp_free_i32(tmp3);
7827 tcg_temp_free_i32(tmp2);
9ee6e8bb
PB		 7828 break;
7829 case 0x18: /* clz */
d9ba4830 7830 gen_helper_clz(tmp, tmp);
9ee6e8bb
PB		 7831 break;
7832 default:
7833 goto illegal_op;
7834 }
7835 }
d9ba4830 7836 store_reg(s, rd, tmp);
9ee6e8bb
PB		 7837 break;
7838 case 4: case 5: /* 32-bit multiply. Sum of absolute differences. */
7839 op = (insn >> 4) & 0xf;
d9ba4830
PB		 7840 tmp = load_reg(s, rn);
7841 tmp2 = load_reg(s, rm);
9ee6e8bb
PB		 7842 switch ((insn >> 20) & 7) {
7843 case 0: /* 32 x 32 -> 32 */
d9ba4830 7844 tcg_gen_mul_i32(tmp, tmp, tmp2);
7d1b0095 7845 tcg_temp_free_i32(tmp2);
9ee6e8bb 7846 if (rs != 15) {
d9ba4830 7847 tmp2 = load_reg(s, rs);
9ee6e8bb 7848 if (op)
d9ba4830 7849 tcg_gen_sub_i32(tmp, tmp2, tmp);
9ee6e8bb 7850 else
d9ba4830 7851 tcg_gen_add_i32(tmp, tmp, tmp2);
7d1b0095 7852 tcg_temp_free_i32(tmp2);
9ee6e8bb 7853 }
9ee6e8bb
PB		 7854 break;
7855 case 1: /* 16 x 16 -> 32 */
d9ba4830 7856 gen_mulxy(tmp, tmp2, op & 2, op & 1);
7d1b0095 7857 tcg_temp_free_i32(tmp2);
9ee6e8bb 7858 if (rs != 15) {
d9ba4830
PB		 7859 tmp2 = load_reg(s, rs);
7860 gen_helper_add_setq(tmp, tmp, tmp2);
7d1b0095 7861 tcg_temp_free_i32(tmp2);
9ee6e8bb 7862 }
9ee6e8bb
PB		 7863 break;
7864 case 2: /* Dual multiply add. */
7865 case 4: /* Dual multiply subtract. */
7866 if (op)
d9ba4830
PB		 7867 gen_swap_half(tmp2);
7868 gen_smul_dual(tmp, tmp2);
9ee6e8bb 7869 if (insn & (1 << 22)) {
e1d177b9 7870 /* This subtraction cannot overflow. */
d9ba4830 7871 tcg_gen_sub_i32(tmp, tmp, tmp2);
9ee6e8bb 7872 } else {
e1d177b9
PM		 7873 /* This addition cannot overflow 32 bits;
7874 * however it may overflow considered as a signed
7875 * operation, in which case we must set the Q flag.
7876 */
7877 gen_helper_add_setq(tmp, tmp, tmp2);
9ee6e8bb 7878 }
7d1b0095 7879 tcg_temp_free_i32(tmp2);
9ee6e8bb
PB		 7880 if (rs != 15)
7881 {
d9ba4830
PB		 7882 tmp2 = load_reg(s, rs);
7883 gen_helper_add_setq(tmp, tmp, tmp2);
7d1b0095 7884 tcg_temp_free_i32(tmp2);
9ee6e8bb 7885 }
9ee6e8bb
PB		 7886 break;
7887 case 3: /* 32 * 16 -> 32msb */
7888 if (op)
d9ba4830 7889 tcg_gen_sari_i32(tmp2, tmp2, 16);
9ee6e8bb 7890 else
d9ba4830 7891 gen_sxth(tmp2);
a7812ae4
PB		 7892 tmp64 = gen_muls_i64_i32(tmp, tmp2);
7893 tcg_gen_shri_i64(tmp64, tmp64, 16);
7d1b0095 7894 tmp = tcg_temp_new_i32();
a7812ae4 7895 tcg_gen_trunc_i64_i32(tmp, tmp64);
b75263d6 7896 tcg_temp_free_i64(tmp64);
9ee6e8bb
PB		 7897 if (rs != 15)
7898 {
d9ba4830
PB		 7899 tmp2 = load_reg(s, rs);
7900 gen_helper_add_setq(tmp, tmp, tmp2);
7d1b0095 7901 tcg_temp_free_i32(tmp2);
9ee6e8bb 7902 }
9ee6e8bb 7903 break;
838fa72d
AJ		 7904 case 5: case 6: /* 32 * 32 -> 32msb (SMMUL, SMMLA, SMMLS) */
7905 tmp64 = gen_muls_i64_i32(tmp, tmp2);
9ee6e8bb 7906 if (rs != 15) {
838fa72d
AJ		 7907 tmp = load_reg(s, rs);
7908 if (insn & (1 << 20)) {
7909 tmp64 = gen_addq_msw(tmp64, tmp);
99c475ab 7910 } else {
838fa72d 7911 tmp64 = gen_subq_msw(tmp64, tmp);
99c475ab 7912 }
2c0262af 7913 }
838fa72d
AJ		 7914 if (insn & (1 << 4)) {
7915 tcg_gen_addi_i64(tmp64, tmp64, 0x80000000u);
7916 }
7917 tcg_gen_shri_i64(tmp64, tmp64, 32);
7d1b0095 7918 tmp = tcg_temp_new_i32();
838fa72d
AJ		 7919 tcg_gen_trunc_i64_i32(tmp, tmp64);
7920 tcg_temp_free_i64(tmp64);
9ee6e8bb
PB		 7921 break;
7922 case 7: /* Unsigned sum of absolute differences. */
d9ba4830 7923 gen_helper_usad8(tmp, tmp, tmp2);
7d1b0095 7924 tcg_temp_free_i32(tmp2);
9ee6e8bb 7925 if (rs != 15) {
d9ba4830
PB		 7926 tmp2 = load_reg(s, rs);
7927 tcg_gen_add_i32(tmp, tmp, tmp2);
7d1b0095 7928 tcg_temp_free_i32(tmp2);
5fd46862 7929 }
9ee6e8bb 7930 break;
2c0262af 7931 }
d9ba4830 7932 store_reg(s, rd, tmp);
2c0262af 7933 break;
9ee6e8bb
PB		 7934 case 6: case 7: /* 64-bit multiply, Divide. */
7935 op = ((insn >> 4) & 0xf) | ((insn >> 16) & 0x70);
5e3f878a
PB		 7936 tmp = load_reg(s, rn);
7937 tmp2 = load_reg(s, rm);
9ee6e8bb
PB		 7938 if ((op & 0x50) == 0x10) {
7939 /* sdiv, udiv */
7940 if (!arm_feature(env, ARM_FEATURE_DIV))
7941 goto illegal_op;
7942 if (op & 0x20)
5e3f878a 7943 gen_helper_udiv(tmp, tmp, tmp2);
2c0262af 7944 else
5e3f878a 7945 gen_helper_sdiv(tmp, tmp, tmp2);
7d1b0095 7946 tcg_temp_free_i32(tmp2);
5e3f878a 7947 store_reg(s, rd, tmp);
9ee6e8bb
PB		 7948 } else if ((op & 0xe) == 0xc) {
7949 /* Dual multiply accumulate long. */
7950 if (op & 1)
5e3f878a
PB		 7951 gen_swap_half(tmp2);
7952 gen_smul_dual(tmp, tmp2);
9ee6e8bb 7953 if (op & 0x10) {
5e3f878a 7954 tcg_gen_sub_i32(tmp, tmp, tmp2);
b5ff1b31 7955 } else {
5e3f878a 7956 tcg_gen_add_i32(tmp, tmp, tmp2);
b5ff1b31 7957 }
7d1b0095 7958 tcg_temp_free_i32(tmp2);
a7812ae4
PB		 7959 /* BUGFIX */
7960 tmp64 = tcg_temp_new_i64();
7961 tcg_gen_ext_i32_i64(tmp64, tmp);
7d1b0095 7962 tcg_temp_free_i32(tmp);
a7812ae4
PB		 7963 gen_addq(s, tmp64, rs, rd);
7964 gen_storeq_reg(s, rs, rd, tmp64);
b75263d6 7965 tcg_temp_free_i64(tmp64);
2c0262af 7966 } else {
9ee6e8bb
PB		 7967 if (op & 0x20) {
7968 /* Unsigned 64-bit multiply */
a7812ae4 7969 tmp64 = gen_mulu_i64_i32(tmp, tmp2);
b5ff1b31 7970 } else {
9ee6e8bb
PB		 7971 if (op & 8) {
7972 /* smlalxy */
5e3f878a 7973 gen_mulxy(tmp, tmp2, op & 2, op & 1);
7d1b0095 7974 tcg_temp_free_i32(tmp2);
a7812ae4
PB		 7975 tmp64 = tcg_temp_new_i64();
7976 tcg_gen_ext_i32_i64(tmp64, tmp);
7d1b0095 7977 tcg_temp_free_i32(tmp);
9ee6e8bb
PB		 7978 } else {
7979 /* Signed 64-bit multiply */
a7812ae4 7980 tmp64 = gen_muls_i64_i32(tmp, tmp2);
9ee6e8bb 7981 }
b5ff1b31 7982 }
9ee6e8bb
PB		 7983 if (op & 4) {
7984 /* umaal */
a7812ae4
PB		 7985 gen_addq_lo(s, tmp64, rs);
7986 gen_addq_lo(s, tmp64, rd);
9ee6e8bb
PB		 7987 } else if (op & 0x40) {
7988 /* 64-bit accumulate. */
a7812ae4 7989 gen_addq(s, tmp64, rs, rd);
9ee6e8bb 7990 }
a7812ae4 7991 gen_storeq_reg(s, rs, rd, tmp64);
b75263d6 7992 tcg_temp_free_i64(tmp64);
5fd46862 7993 }
2c0262af 7994 break;
9ee6e8bb
PB		 7995 }
7996 break;
7997 case 6: case 7: case 14: case 15:
7998 /* Coprocessor. */
7999 if (((insn >> 24) & 3) == 3) {
8000 /* Translate into the equivalent ARM encoding. */
f06053e3 8001 insn = (insn & 0xe2ffffff) | ((insn & (1 << 28)) >> 4) | (1 << 28);
9ee6e8bb
PB		 8002 if (disas_neon_data_insn(env, s, insn))
8003 goto illegal_op;
8004 } else {
8005 if (insn & (1 << 28))
8006 goto illegal_op;
8007 if (disas_coproc_insn (env, s, insn))
8008 goto illegal_op;
8009 }
8010 break;
8011 case 8: case 9: case 10: case 11:
8012 if (insn & (1 << 15)) {
8013 /* Branches, misc control. */
8014 if (insn & 0x5000) {
8015 /* Unconditional branch. */
8016 /* signextend(hw1[10:0]) -> offset[:12]. */
8017 offset = ((int32_t)insn << 5) >> 9 & ~(int32_t)0xfff;
8018 /* hw1[10:0] -> offset[11:1]. */
8019 offset |= (insn & 0x7ff) << 1;
8020 /* (~hw2[13, 11] ^ offset[24]) -> offset[23,22]
8021 offset[24:22] already have the same value because of the
8022 sign extension above. */
8023 offset ^= ((~insn) & (1 << 13)) << 10;
8024 offset ^= ((~insn) & (1 << 11)) << 11;
8025
9ee6e8bb
PB		 8026 if (insn & (1 << 14)) {
8027 /* Branch and link. */
3174f8e9 8028 tcg_gen_movi_i32(cpu_R[14], s->pc | 1);
b5ff1b31 8029 }
3b46e624 8030
b0109805 8031 offset += s->pc;
9ee6e8bb
PB		 8032 if (insn & (1 << 12)) {
8033 /* b/bl */
b0109805 8034 gen_jmp(s, offset);
9ee6e8bb
PB		 8035 } else {
8036 /* blx */
b0109805
PB		 8037 offset &= ~(uint32_t)2;
8038 gen_bx_im(s, offset);
2c0262af 8039 }
9ee6e8bb
PB		 8040 } else if (((insn >> 23) & 7) == 7) {
8041 /* Misc control */
8042 if (insn & (1 << 13))
8043 goto illegal_op;
8044
8045 if (insn & (1 << 26)) {
8046 /* Secure monitor call (v6Z) */
8047 goto illegal_op; /* not implemented. */
2c0262af 8048 } else {
9ee6e8bb
PB		 8049 op = (insn >> 20) & 7;
8050 switch (op) {
8051 case 0: /* msr cpsr. */
8052 if (IS_M(env)) {
8984bd2e
PB		 8053 tmp = load_reg(s, rn);
8054 addr = tcg_const_i32(insn & 0xff);
8055 gen_helper_v7m_msr(cpu_env, addr, tmp);
b75263d6 8056 tcg_temp_free_i32(addr);
7d1b0095 8057 tcg_temp_free_i32(tmp);
9ee6e8bb
PB		 8058 gen_lookup_tb(s);
8059 break;
8060 }
8061 /* fall through */
8062 case 1: /* msr spsr. */
8063 if (IS_M(env))
8064 goto illegal_op;
2fbac54b
FN		 8065 tmp = load_reg(s, rn);
8066 if (gen_set_psr(s,
9ee6e8bb 8067 msr_mask(env, s, (insn >> 8) & 0xf, op == 1),
2fbac54b 8068 op == 1, tmp))
9ee6e8bb
PB		 8069 goto illegal_op;
8070 break;
8071 case 2: /* cps, nop-hint. */
8072 if (((insn >> 8) & 7) == 0) {
8073 gen_nop_hint(s, insn & 0xff);
8074 }
8075 /* Implemented as NOP in user mode. */
8076 if (IS_USER(s))
8077 break;
8078 offset = 0;
8079 imm = 0;
8080 if (insn & (1 << 10)) {
8081 if (insn & (1 << 7))
8082 offset |= CPSR_A;
8083 if (insn & (1 << 6))
8084 offset |= CPSR_I;
8085 if (insn & (1 << 5))
8086 offset |= CPSR_F;
8087 if (insn & (1 << 9))
8088 imm = CPSR_A | CPSR_I | CPSR_F;
8089 }
8090 if (insn & (1 << 8)) {
8091 offset |= 0x1f;
8092 imm |= (insn & 0x1f);
8093 }
8094 if (offset) {
2fbac54b 8095 gen_set_psr_im(s, offset, 0, imm);
9ee6e8bb
PB		 8096 }
8097 break;
8098 case 3: /* Special control operations. */
426f5abc 8099 ARCH(7);
9ee6e8bb
PB		 8100 op = (insn >> 4) & 0xf;
8101 switch (op) {
8102 case 2: /* clrex */
426f5abc 8103 gen_clrex(s);
9ee6e8bb
PB		 8104 break;
8105 case 4: /* dsb */
8106 case 5: /* dmb */
8107 case 6: /* isb */
8108 /* These execute as NOPs. */
9ee6e8bb
PB		 8109 break;
8110 default:
8111 goto illegal_op;
8112 }
8113 break;
8114 case 4: /* bxj */
8115 /* Trivial implementation equivalent to bx. */
d9ba4830
PB		 8116 tmp = load_reg(s, rn);
8117 gen_bx(s, tmp);
9ee6e8bb
PB		 8118 break;
8119 case 5: /* Exception return. */
b8b45b68
RV		 8120 if (IS_USER(s)) {
8121 goto illegal_op;
8122 }
8123 if (rn != 14 || rd != 15) {
8124 goto illegal_op;
8125 }
8126 tmp = load_reg(s, rn);
8127 tcg_gen_subi_i32(tmp, tmp, insn & 0xff);
8128 gen_exception_return(s, tmp);
8129 break;
9ee6e8bb 8130 case 6: /* mrs cpsr. */
7d1b0095 8131 tmp = tcg_temp_new_i32();
9ee6e8bb 8132 if (IS_M(env)) {
8984bd2e
PB		 8133 addr = tcg_const_i32(insn & 0xff);
8134 gen_helper_v7m_mrs(tmp, cpu_env, addr);
b75263d6 8135 tcg_temp_free_i32(addr);
9ee6e8bb 8136 } else {
8984bd2e 8137 gen_helper_cpsr_read(tmp);
9ee6e8bb 8138 }
8984bd2e 8139 store_reg(s, rd, tmp);
9ee6e8bb
PB		 8140 break;
8141 case 7: /* mrs spsr. */
8142 /* Not accessible in user mode. */
8143 if (IS_USER(s) || IS_M(env))
8144 goto illegal_op;
d9ba4830
PB		 8145 tmp = load_cpu_field(spsr);
8146 store_reg(s, rd, tmp);
9ee6e8bb 8147 break;
2c0262af
FB		 8148 }
8149 }
9ee6e8bb
PB		 8150 } else {
8151 /* Conditional branch. */
8152 op = (insn >> 22) & 0xf;
8153 /* Generate a conditional jump to next instruction. */
8154 s->condlabel = gen_new_label();
d9ba4830 8155 gen_test_cc(op ^ 1, s->condlabel);
9ee6e8bb
PB		 8156 s->condjmp = 1;
8157
8158 /* offset[11:1] = insn[10:0] */
8159 offset = (insn & 0x7ff) << 1;
8160 /* offset[17:12] = insn[21:16]. */
8161 offset |= (insn & 0x003f0000) >> 4;
8162 /* offset[31:20] = insn[26]. */
8163 offset |= ((int32_t)((insn << 5) & 0x80000000)) >> 11;
8164 /* offset[18] = insn[13]. */
8165 offset |= (insn & (1 << 13)) << 5;
8166 /* offset[19] = insn[11]. */
8167 offset |= (insn & (1 << 11)) << 8;
8168
8169 /* jump to the offset */
b0109805 8170 gen_jmp(s, s->pc + offset);
9ee6e8bb
PB		 8171 }
8172 } else {
8173 /* Data processing immediate. */
8174 if (insn & (1 << 25)) {
8175 if (insn & (1 << 24)) {
8176 if (insn & (1 << 20))
8177 goto illegal_op;
8178 /* Bitfield/Saturate. */
8179 op = (insn >> 21) & 7;
8180 imm = insn & 0x1f;
8181 shift = ((insn >> 6) & 3) | ((insn >> 10) & 0x1c);
6ddbc6e4 8182 if (rn == 15) {
7d1b0095 8183 tmp = tcg_temp_new_i32();
6ddbc6e4
PB		 8184 tcg_gen_movi_i32(tmp, 0);
8185 } else {
8186 tmp = load_reg(s, rn);
8187 }
9ee6e8bb
PB		 8188 switch (op) {
8189 case 2: /* Signed bitfield extract. */
8190 imm++;
8191 if (shift + imm > 32)
8192 goto illegal_op;
8193 if (imm < 32)
6ddbc6e4 8194 gen_sbfx(tmp, shift, imm);
9ee6e8bb
PB		 8195 break;
8196 case 6: /* Unsigned bitfield extract. */
8197 imm++;
8198 if (shift + imm > 32)
8199 goto illegal_op;
8200 if (imm < 32)
6ddbc6e4 8201 gen_ubfx(tmp, shift, (1u << imm) - 1);
9ee6e8bb
PB		 8202 break;
8203 case 3: /* Bitfield insert/clear. */
8204 if (imm < shift)
8205 goto illegal_op;
8206 imm = imm + 1 - shift;
8207 if (imm != 32) {
6ddbc6e4 8208 tmp2 = load_reg(s, rd);
8f8e3aa4 8209 gen_bfi(tmp, tmp2, tmp, shift, (1u << imm) - 1);
7d1b0095 8210 tcg_temp_free_i32(tmp2);
9ee6e8bb
PB		 8211 }
8212 break;
8213 case 7:
8214 goto illegal_op;
8215 default: /* Saturate. */
9ee6e8bb
PB		 8216 if (shift) {
8217 if (op & 1)
6ddbc6e4 8218 tcg_gen_sari_i32(tmp, tmp, shift);
9ee6e8bb 8219 else
6ddbc6e4 8220 tcg_gen_shli_i32(tmp, tmp, shift);
9ee6e8bb 8221 }
6ddbc6e4 8222 tmp2 = tcg_const_i32(imm);
9ee6e8bb
PB		 8223 if (op & 4) {
8224 /* Unsigned. */
9ee6e8bb 8225 if ((op & 1) && shift == 0)
6ddbc6e4 8226 gen_helper_usat16(tmp, tmp, tmp2);
9ee6e8bb 8227 else
6ddbc6e4 8228 gen_helper_usat(tmp, tmp, tmp2);
2c0262af 8229 } else {
9ee6e8bb 8230 /* Signed. */
9ee6e8bb 8231 if ((op & 1) && shift == 0)
6ddbc6e4 8232 gen_helper_ssat16(tmp, tmp, tmp2);
9ee6e8bb 8233 else
6ddbc6e4 8234 gen_helper_ssat(tmp, tmp, tmp2);
2c0262af 8235 }
b75263d6 8236 tcg_temp_free_i32(tmp2);
9ee6e8bb 8237 break;
2c0262af 8238 }
6ddbc6e4 8239 store_reg(s, rd, tmp);
9ee6e8bb
PB		 8240 } else {
8241 imm = ((insn & 0x04000000) >> 15)
8242 | ((insn & 0x7000) >> 4) | (insn & 0xff);
8243 if (insn & (1 << 22)) {
8244 /* 16-bit immediate. */
8245 imm |= (insn >> 4) & 0xf000;
8246 if (insn & (1 << 23)) {
8247 /* movt */
5e3f878a 8248 tmp = load_reg(s, rd);
86831435 8249 tcg_gen_ext16u_i32(tmp, tmp);
5e3f878a 8250 tcg_gen_ori_i32(tmp, tmp, imm << 16);
2c0262af 8251 } else {
9ee6e8bb 8252 /* movw */
7d1b0095 8253 tmp = tcg_temp_new_i32();
5e3f878a 8254 tcg_gen_movi_i32(tmp, imm);
2c0262af
FB		 8255 }
8256 } else {
9ee6e8bb
PB		 8257 /* Add/sub 12-bit immediate. */
8258 if (rn == 15) {
b0109805 8259 offset = s->pc & ~(uint32_t)3;
9ee6e8bb 8260 if (insn & (1 << 23))
b0109805 8261 offset -= imm;
9ee6e8bb 8262 else
b0109805 8263 offset += imm;
7d1b0095 8264 tmp = tcg_temp_new_i32();
5e3f878a 8265 tcg_gen_movi_i32(tmp, offset);
2c0262af 8266 } else {
5e3f878a 8267 tmp = load_reg(s, rn);
9ee6e8bb 8268 if (insn & (1 << 23))
5e3f878a 8269 tcg_gen_subi_i32(tmp, tmp, imm);
9ee6e8bb 8270 else
5e3f878a 8271 tcg_gen_addi_i32(tmp, tmp, imm);
2c0262af 8272 }
9ee6e8bb 8273 }
5e3f878a 8274 store_reg(s, rd, tmp);
191abaa2 8275 }
9ee6e8bb
PB		 8276 } else {
8277 int shifter_out = 0;
8278 /* modified 12-bit immediate. */
8279 shift = ((insn & 0x04000000) >> 23) | ((insn & 0x7000) >> 12);
8280 imm = (insn & 0xff);
8281 switch (shift) {
8282 case 0: /* XY */
8283 /* Nothing to do. */
8284 break;
8285 case 1: /* 00XY00XY */
8286 imm |= imm << 16;
8287 break;
8288 case 2: /* XY00XY00 */
8289 imm |= imm << 16;
8290 imm <<= 8;
8291 break;
8292 case 3: /* XYXYXYXY */
8293 imm |= imm << 16;
8294 imm |= imm << 8;
8295 break;
8296 default: /* Rotated constant. */
8297 shift = (shift << 1) | (imm >> 7);
8298 imm |= 0x80;
8299 imm = imm << (32 - shift);
8300 shifter_out = 1;
8301 break;
b5ff1b31 8302 }
7d1b0095 8303 tmp2 = tcg_temp_new_i32();
3174f8e9 8304 tcg_gen_movi_i32(tmp2, imm);
9ee6e8bb 8305 rn = (insn >> 16) & 0xf;
3174f8e9 8306 if (rn == 15) {
7d1b0095 8307 tmp = tcg_temp_new_i32();
3174f8e9
FN		 8308 tcg_gen_movi_i32(tmp, 0);
8309 } else {
8310 tmp = load_reg(s, rn);
8311 }
9ee6e8bb
PB		 8312 op = (insn >> 21) & 0xf;
8313 if (gen_thumb2_data_op(s, op, (insn & (1 << 20)) != 0,
3174f8e9 8314 shifter_out, tmp, tmp2))
9ee6e8bb 8315 goto illegal_op;
7d1b0095 8316 tcg_temp_free_i32(tmp2);
9ee6e8bb
PB		 8317 rd = (insn >> 8) & 0xf;
8318 if (rd != 15) {
3174f8e9
FN		 8319 store_reg(s, rd, tmp);
8320 } else {
7d1b0095 8321 tcg_temp_free_i32(tmp);
2c0262af 8322 }
2c0262af 8323 }
9ee6e8bb
PB		 8324 }
8325 break;
8326 case 12: /* Load/store single data item. */
8327 {
8328 int postinc = 0;
8329 int writeback = 0;
b0109805 8330 int user;
9ee6e8bb
PB		 8331 if ((insn & 0x01100000) == 0x01000000) {
8332 if (disas_neon_ls_insn(env, s, insn))
c1713132 8333 goto illegal_op;
9ee6e8bb
PB		 8334 break;
8335 }
a2fdc890
PM		 8336 op = ((insn >> 21) & 3) | ((insn >> 22) & 4);
8337 if (rs == 15) {
8338 if (!(insn & (1 << 20))) {
8339 goto illegal_op;
8340 }
8341 if (op != 2) {
8342 /* Byte or halfword load space with dest == r15 : memory hints.
8343 * Catch them early so we don't emit pointless addressing code.
8344 * This space is a mix of:
8345 * PLD/PLDW/PLI, which we implement as NOPs (note that unlike
8346 * the ARM encodings, PLDW space doesn't UNDEF for non-v7MP
8347 * cores)
8348 * unallocated hints, which must be treated as NOPs
8349 * UNPREDICTABLE space, which we NOP or UNDEF depending on
8350 * which is easiest for the decoding logic
8351 * Some space which must UNDEF
8352 */
8353 int op1 = (insn >> 23) & 3;
8354 int op2 = (insn >> 6) & 0x3f;
8355 if (op & 2) {
8356 goto illegal_op;
8357 }
8358 if (rn == 15) {
8359 /* UNPREDICTABLE or unallocated hint */
8360 return 0;
8361 }
8362 if (op1 & 1) {
8363 return 0; /* PLD* or unallocated hint */
8364 }
8365 if ((op2 == 0) || ((op2 & 0x3c) == 0x30)) {
8366 return 0; /* PLD* or unallocated hint */
8367 }
8368 /* UNDEF space, or an UNPREDICTABLE */
8369 return 1;
8370 }
8371 }
b0109805 8372 user = IS_USER(s);
9ee6e8bb 8373 if (rn == 15) {
7d1b0095 8374 addr = tcg_temp_new_i32();
9ee6e8bb
PB		 8375 /* PC relative. */
8376 /* s->pc has already been incremented by 4. */
8377 imm = s->pc & 0xfffffffc;
8378 if (insn & (1 << 23))
8379 imm += insn & 0xfff;
8380 else
8381 imm -= insn & 0xfff;
b0109805 8382 tcg_gen_movi_i32(addr, imm);
9ee6e8bb 8383 } else {
b0109805 8384 addr = load_reg(s, rn);
9ee6e8bb
PB		 8385 if (insn & (1 << 23)) {
8386 /* Positive offset. */
8387 imm = insn & 0xfff;
b0109805 8388 tcg_gen_addi_i32(addr, addr, imm);
9ee6e8bb 8389 } else {
9ee6e8bb 8390 imm = insn & 0xff;
2a0308c5
PM		 8391 switch ((insn >> 8) & 0xf) {
8392 case 0x0: /* Shifted Register. */
9ee6e8bb 8393 shift = (insn >> 4) & 0xf;
2a0308c5
PM		 8394 if (shift > 3) {
8395 tcg_temp_free_i32(addr);
18c9b560 8396 goto illegal_op;
2a0308c5 8397 }
b26eefb6 8398 tmp = load_reg(s, rm);
9ee6e8bb 8399 if (shift)
b26eefb6 8400 tcg_gen_shli_i32(tmp, tmp, shift);
b0109805 8401 tcg_gen_add_i32(addr, addr, tmp);
7d1b0095 8402 tcg_temp_free_i32(tmp);
9ee6e8bb 8403 break;
2a0308c5 8404 case 0xc: /* Negative offset. */
b0109805 8405 tcg_gen_addi_i32(addr, addr, -imm);
9ee6e8bb 8406 break;
2a0308c5 8407 case 0xe: /* User privilege. */
b0109805
PB		 8408 tcg_gen_addi_i32(addr, addr, imm);
8409 user = 1;
9ee6e8bb 8410 break;
2a0308c5 8411 case 0x9: /* Post-decrement. */
9ee6e8bb
PB		 8412 imm = -imm;
8413 /* Fall through. */
2a0308c5 8414 case 0xb: /* Post-increment. */
9ee6e8bb
PB		 8415 postinc = 1;
8416 writeback = 1;
8417 break;
2a0308c5 8418 case 0xd: /* Pre-decrement. */
9ee6e8bb
PB		 8419 imm = -imm;
8420 /* Fall through. */
2a0308c5 8421 case 0xf: /* Pre-increment. */
b0109805 8422 tcg_gen_addi_i32(addr, addr, imm);
9ee6e8bb
PB		 8423 writeback = 1;
8424 break;
8425 default:
2a0308c5 8426 tcg_temp_free_i32(addr);
b7bcbe95 8427 goto illegal_op;
9ee6e8bb
PB		 8428 }
8429 }
8430 }
9ee6e8bb
PB		 8431 if (insn & (1 << 20)) {
8432 /* Load. */
a2fdc890
PM		 8433 switch (op) {
8434 case 0: tmp = gen_ld8u(addr, user); break;
8435 case 4: tmp = gen_ld8s(addr, user); break;
8436 case 1: tmp = gen_ld16u(addr, user); break;
8437 case 5: tmp = gen_ld16s(addr, user); break;
8438 case 2: tmp = gen_ld32(addr, user); break;
2a0308c5
PM		 8439 default:
8440 tcg_temp_free_i32(addr);
8441 goto illegal_op;
a2fdc890
PM		 8442 }
8443 if (rs == 15) {
8444 gen_bx(s, tmp);
9ee6e8bb 8445 } else {
a2fdc890 8446 store_reg(s, rs, tmp);
9ee6e8bb
PB		 8447 }
8448 } else {
8449 /* Store. */
b0109805 8450 tmp = load_reg(s, rs);
9ee6e8bb 8451 switch (op) {
b0109805
PB		 8452 case 0: gen_st8(tmp, addr, user); break;
8453 case 1: gen_st16(tmp, addr, user); break;
8454 case 2: gen_st32(tmp, addr, user); break;
2a0308c5
PM		 8455 default:
8456 tcg_temp_free_i32(addr);
8457 goto illegal_op;
b7bcbe95 8458 }
2c0262af 8459 }
9ee6e8bb 8460 if (postinc)
b0109805
PB		 8461 tcg_gen_addi_i32(addr, addr, imm);
8462 if (writeback) {
8463 store_reg(s, rn, addr);
8464 } else {
7d1b0095 8465 tcg_temp_free_i32(addr);
b0109805 8466 }
9ee6e8bb
PB		 8467 }
8468 break;
8469 default:
8470 goto illegal_op;
2c0262af 8471 }
9ee6e8bb
PB		 8472 return 0;
8473illegal_op:
8474 return 1;
2c0262af
FB		 8475}
8476
9ee6e8bb 8477static void disas_thumb_insn(CPUState *env, DisasContext *s)
99c475ab
FB		 8478{
8479 uint32_t val, insn, op, rm, rn, rd, shift, cond;
8480 int32_t offset;
8481 int i;
b26eefb6 8482 TCGv tmp;
d9ba4830 8483 TCGv tmp2;
b0109805 8484 TCGv addr;
99c475ab 8485
9ee6e8bb
PB		 8486 if (s->condexec_mask) {
8487 cond = s->condexec_cond;
bedd2912
JB		 8488 if (cond != 0x0e) { /* Skip conditional when condition is AL. */
8489 s->condlabel = gen_new_label();
8490 gen_test_cc(cond ^ 1, s->condlabel);
8491 s->condjmp = 1;
8492 }
9ee6e8bb
PB		 8493 }
8494
b5ff1b31 8495 insn = lduw_code(s->pc);
99c475ab 8496 s->pc += 2;
b5ff1b31 8497
99c475ab
FB		 8498 switch (insn >> 12) {
8499 case 0: case 1:
396e467c 8500
99c475ab
FB		 8501 rd = insn & 7;
8502 op = (insn >> 11) & 3;
8503 if (op == 3) {
8504 /* add/subtract */
8505 rn = (insn >> 3) & 7;
396e467c 8506 tmp = load_reg(s, rn);
99c475ab
FB		 8507 if (insn & (1 << 10)) {
8508 /* immediate */
7d1b0095 8509 tmp2 = tcg_temp_new_i32();
396e467c 8510 tcg_gen_movi_i32(tmp2, (insn >> 6) & 7);
99c475ab
FB		 8511 } else {
8512 /* reg */
8513 rm = (insn >> 6) & 7;
396e467c 8514 tmp2 = load_reg(s, rm);
99c475ab 8515 }
9ee6e8bb
PB		 8516 if (insn & (1 << 9)) {
8517 if (s->condexec_mask)
396e467c 8518 tcg_gen_sub_i32(tmp, tmp, tmp2);
9ee6e8bb 8519 else
396e467c 8520 gen_helper_sub_cc(tmp, tmp, tmp2);
9ee6e8bb
PB		 8521 } else {
8522 if (s->condexec_mask)
396e467c 8523 tcg_gen_add_i32(tmp, tmp, tmp2);
9ee6e8bb 8524 else
396e467c 8525 gen_helper_add_cc(tmp, tmp, tmp2);
9ee6e8bb 8526 }
7d1b0095 8527 tcg_temp_free_i32(tmp2);
396e467c 8528 store_reg(s, rd, tmp);
99c475ab
FB		 8529 } else {
8530 /* shift immediate */
8531 rm = (insn >> 3) & 7;
8532 shift = (insn >> 6) & 0x1f;
9a119ff6
PB		 8533 tmp = load_reg(s, rm);
8534 gen_arm_shift_im(tmp, op, shift, s->condexec_mask == 0);
8535 if (!s->condexec_mask)
8536 gen_logic_CC(tmp);
8537 store_reg(s, rd, tmp);
99c475ab
FB		 8538 }
8539 break;
8540 case 2: case 3:
8541 /* arithmetic large immediate */
8542 op = (insn >> 11) & 3;
8543 rd = (insn >> 8) & 0x7;
396e467c 8544 if (op == 0) { /* mov */
7d1b0095 8545 tmp = tcg_temp_new_i32();
396e467c 8546 tcg_gen_movi_i32(tmp, insn & 0xff);
9ee6e8bb 8547 if (!s->condexec_mask)
396e467c
FN		 8548 gen_logic_CC(tmp);
8549 store_reg(s, rd, tmp);
8550 } else {
8551 tmp = load_reg(s, rd);
7d1b0095 8552 tmp2 = tcg_temp_new_i32();
396e467c
FN		 8553 tcg_gen_movi_i32(tmp2, insn & 0xff);
8554 switch (op) {
8555 case 1: /* cmp */
8556 gen_helper_sub_cc(tmp, tmp, tmp2);
7d1b0095
PM		 8557 tcg_temp_free_i32(tmp);
8558 tcg_temp_free_i32(tmp2);
396e467c
FN		 8559 break;
8560 case 2: /* add */
8561 if (s->condexec_mask)
8562 tcg_gen_add_i32(tmp, tmp, tmp2);
8563 else
8564 gen_helper_add_cc(tmp, tmp, tmp2);
7d1b0095 8565 tcg_temp_free_i32(tmp2);
396e467c
FN		 8566 store_reg(s, rd, tmp);
8567 break;
8568 case 3: /* sub */
8569 if (s->condexec_mask)
8570 tcg_gen_sub_i32(tmp, tmp, tmp2);
8571 else
8572 gen_helper_sub_cc(tmp, tmp, tmp2);
7d1b0095 8573 tcg_temp_free_i32(tmp2);
396e467c
FN		 8574 store_reg(s, rd, tmp);
8575 break;
8576 }
99c475ab 8577 }
99c475ab
FB		 8578 break;
8579 case 4:
8580 if (insn & (1 << 11)) {
8581 rd = (insn >> 8) & 7;
5899f386
FB		 8582 /* load pc-relative. Bit 1 of PC is ignored. */
8583 val = s->pc + 2 + ((insn & 0xff) * 4);
8584 val &= ~(uint32_t)2;
7d1b0095 8585 addr = tcg_temp_new_i32();
b0109805
PB		 8586 tcg_gen_movi_i32(addr, val);
8587 tmp = gen_ld32(addr, IS_USER(s));
7d1b0095 8588 tcg_temp_free_i32(addr);
b0109805 8589 store_reg(s, rd, tmp);
99c475ab
FB		 8590 break;
8591 }
8592 if (insn & (1 << 10)) {
8593 /* data processing extended or blx */
8594 rd = (insn & 7) | ((insn >> 4) & 8);
8595 rm = (insn >> 3) & 0xf;
8596 op = (insn >> 8) & 3;
8597 switch (op) {
8598 case 0: /* add */
396e467c
FN		 8599 tmp = load_reg(s, rd);
8600 tmp2 = load_reg(s, rm);
8601 tcg_gen_add_i32(tmp, tmp, tmp2);
7d1b0095 8602 tcg_temp_free_i32(tmp2);
396e467c 8603 store_reg(s, rd, tmp);
99c475ab
FB		 8604 break;
8605 case 1: /* cmp */
396e467c
FN		 8606 tmp = load_reg(s, rd);
8607 tmp2 = load_reg(s, rm);
8608 gen_helper_sub_cc(tmp, tmp, tmp2);
7d1b0095
PM		 8609 tcg_temp_free_i32(tmp2);
8610 tcg_temp_free_i32(tmp);
99c475ab
FB		 8611 break;
8612 case 2: /* mov/cpy */
396e467c
FN		 8613 tmp = load_reg(s, rm);
8614 store_reg(s, rd, tmp);
99c475ab
FB		 8615 break;
8616 case 3:/* branch [and link] exchange thumb register */
b0109805 8617 tmp = load_reg(s, rm);
99c475ab
FB		 8618 if (insn & (1 << 7)) {
8619 val = (uint32_t)s->pc | 1;
7d1b0095 8620 tmp2 = tcg_temp_new_i32();
b0109805
PB		 8621 tcg_gen_movi_i32(tmp2, val);
8622 store_reg(s, 14, tmp2);
99c475ab 8623 }
d9ba4830 8624 gen_bx(s, tmp);
99c475ab
FB		 8625 break;
8626 }
8627 break;
8628 }
8629
8630 /* data processing register */
8631 rd = insn & 7;
8632 rm = (insn >> 3) & 7;
8633 op = (insn >> 6) & 0xf;
8634 if (op == 2 || op == 3 || op == 4 || op == 7) {
8635 /* the shift/rotate ops want the operands backwards */
8636 val = rm;
8637 rm = rd;
8638 rd = val;
8639 val = 1;
8640 } else {
8641 val = 0;
8642 }
8643
396e467c 8644 if (op == 9) { /* neg */
7d1b0095 8645 tmp = tcg_temp_new_i32();
396e467c
FN		 8646 tcg_gen_movi_i32(tmp, 0);
8647 } else if (op != 0xf) { /* mvn doesn't read its first operand */
8648 tmp = load_reg(s, rd);
8649 } else {
8650 TCGV_UNUSED(tmp);
8651 }
99c475ab 8652
396e467c 8653 tmp2 = load_reg(s, rm);
5899f386 8654 switch (op) {
99c475ab 8655 case 0x0: /* and */
396e467c 8656 tcg_gen_and_i32(tmp, tmp, tmp2);
9ee6e8bb 8657 if (!s->condexec_mask)
396e467c 8658 gen_logic_CC(tmp);
99c475ab
FB		 8659 break;
8660 case 0x1: /* eor */
396e467c 8661 tcg_gen_xor_i32(tmp, tmp, tmp2);
9ee6e8bb 8662 if (!s->condexec_mask)
396e467c 8663 gen_logic_CC(tmp);
99c475ab
FB		 8664 break;
8665 case 0x2: /* lsl */
9ee6e8bb 8666 if (s->condexec_mask) {
396e467c 8667 gen_helper_shl(tmp2, tmp2, tmp);
9ee6e8bb 8668 } else {
396e467c
FN		 8669 gen_helper_shl_cc(tmp2, tmp2, tmp);
8670 gen_logic_CC(tmp2);
9ee6e8bb 8671 }
99c475ab
FB		 8672 break;
8673 case 0x3: /* lsr */
9ee6e8bb 8674 if (s->condexec_mask) {
396e467c 8675 gen_helper_shr(tmp2, tmp2, tmp);
9ee6e8bb 8676 } else {
396e467c
FN		 8677 gen_helper_shr_cc(tmp2, tmp2, tmp);
8678 gen_logic_CC(tmp2);
9ee6e8bb 8679 }
99c475ab
FB		 8680 break;
8681 case 0x4: /* asr */
9ee6e8bb 8682 if (s->condexec_mask) {
396e467c 8683 gen_helper_sar(tmp2, tmp2, tmp);
9ee6e8bb 8684 } else {
396e467c
FN		 8685 gen_helper_sar_cc(tmp2, tmp2, tmp);
8686 gen_logic_CC(tmp2);
9ee6e8bb 8687 }
99c475ab
FB		 8688 break;
8689 case 0x5: /* adc */
9ee6e8bb 8690 if (s->condexec_mask)
396e467c 8691 gen_adc(tmp, tmp2);
9ee6e8bb 8692 else
396e467c 8693 gen_helper_adc_cc(tmp, tmp, tmp2);
99c475ab
FB		 8694 break;
8695 case 0x6: /* sbc */
9ee6e8bb 8696 if (s->condexec_mask)
396e467c 8697 gen_sub_carry(tmp, tmp, tmp2);
9ee6e8bb 8698 else
396e467c 8699 gen_helper_sbc_cc(tmp, tmp, tmp2);
99c475ab
FB		 8700 break;
8701 case 0x7: /* ror */
9ee6e8bb 8702 if (s->condexec_mask) {
f669df27
AJ		 8703 tcg_gen_andi_i32(tmp, tmp, 0x1f);
8704 tcg_gen_rotr_i32(tmp2, tmp2, tmp);
9ee6e8bb 8705 } else {
396e467c
FN		 8706 gen_helper_ror_cc(tmp2, tmp2, tmp);
8707 gen_logic_CC(tmp2);
9ee6e8bb 8708 }
99c475ab
FB		 8709 break;
8710 case 0x8: /* tst */
396e467c
FN		 8711 tcg_gen_and_i32(tmp, tmp, tmp2);
8712 gen_logic_CC(tmp);
99c475ab 8713 rd = 16;
5899f386 8714 break;
99c475ab 8715 case 0x9: /* neg */
9ee6e8bb 8716 if (s->condexec_mask)
396e467c 8717 tcg_gen_neg_i32(tmp, tmp2);
9ee6e8bb 8718 else
396e467c 8719 gen_helper_sub_cc(tmp, tmp, tmp2);
99c475ab
FB		 8720 break;
8721 case 0xa: /* cmp */
396e467c 8722 gen_helper_sub_cc(tmp, tmp, tmp2);
99c475ab
FB		 8723 rd = 16;
8724 break;
8725 case 0xb: /* cmn */
396e467c 8726 gen_helper_add_cc(tmp, tmp, tmp2);
99c475ab
FB		 8727 rd = 16;
8728 break;
8729 case 0xc: /* orr */
396e467c 8730 tcg_gen_or_i32(tmp, tmp, tmp2);
9ee6e8bb 8731 if (!s->condexec_mask)
396e467c 8732 gen_logic_CC(tmp);
99c475ab
FB		 8733 break;
8734 case 0xd: /* mul */
7b2919a0 8735 tcg_gen_mul_i32(tmp, tmp, tmp2);
9ee6e8bb 8736 if (!s->condexec_mask)
396e467c 8737 gen_logic_CC(tmp);
99c475ab
FB		 8738 break;
8739 case 0xe: /* bic */
f669df27 8740 tcg_gen_andc_i32(tmp, tmp, tmp2);
9ee6e8bb 8741 if (!s->condexec_mask)
396e467c 8742 gen_logic_CC(tmp);
99c475ab
FB		 8743 break;
8744 case 0xf: /* mvn */
396e467c 8745 tcg_gen_not_i32(tmp2, tmp2);
9ee6e8bb 8746 if (!s->condexec_mask)
396e467c 8747 gen_logic_CC(tmp2);
99c475ab 8748 val = 1;
5899f386 8749 rm = rd;
99c475ab
FB		 8750 break;
8751 }
8752 if (rd != 16) {
396e467c
FN		 8753 if (val) {
8754 store_reg(s, rm, tmp2);
8755 if (op != 0xf)
7d1b0095 8756 tcg_temp_free_i32(tmp);
396e467c
FN		 8757 } else {
8758 store_reg(s, rd, tmp);
7d1b0095 8759 tcg_temp_free_i32(tmp2);
396e467c
FN		 8760 }
8761 } else {
7d1b0095
PM		 8762 tcg_temp_free_i32(tmp);
8763 tcg_temp_free_i32(tmp2);
99c475ab
FB		 8764 }
8765 break;
8766
8767 case 5:
8768 /* load/store register offset. */
8769 rd = insn & 7;
8770 rn = (insn >> 3) & 7;
8771 rm = (insn >> 6) & 7;
8772 op = (insn >> 9) & 7;
b0109805 8773 addr = load_reg(s, rn);
b26eefb6 8774 tmp = load_reg(s, rm);
b0109805 8775 tcg_gen_add_i32(addr, addr, tmp);
7d1b0095 8776 tcg_temp_free_i32(tmp);
99c475ab
FB		 8777
8778 if (op < 3) /* store */
b0109805 8779 tmp = load_reg(s, rd);
99c475ab
FB		 8780
8781 switch (op) {
8782 case 0: /* str */
b0109805 8783 gen_st32(tmp, addr, IS_USER(s));
99c475ab
FB		 8784 break;
8785 case 1: /* strh */
b0109805 8786 gen_st16(tmp, addr, IS_USER(s));
99c475ab
FB		 8787 break;
8788 case 2: /* strb */
b0109805 8789 gen_st8(tmp, addr, IS_USER(s));
99c475ab
FB		 8790 break;
8791 case 3: /* ldrsb */
b0109805 8792 tmp = gen_ld8s(addr, IS_USER(s));
99c475ab
FB		 8793 break;
8794 case 4: /* ldr */
b0109805 8795 tmp = gen_ld32(addr, IS_USER(s));
99c475ab
FB		 8796 break;
8797 case 5: /* ldrh */
b0109805 8798 tmp = gen_ld16u(addr, IS_USER(s));
99c475ab
FB		 8799 break;
8800 case 6: /* ldrb */
b0109805 8801 tmp = gen_ld8u(addr, IS_USER(s));
99c475ab
FB		 8802 break;
8803 case 7: /* ldrsh */
b0109805 8804 tmp = gen_ld16s(addr, IS_USER(s));
99c475ab
FB		 8805 break;
8806 }
8807 if (op >= 3) /* load */
b0109805 8808 store_reg(s, rd, tmp);
7d1b0095 8809 tcg_temp_free_i32(addr);
99c475ab
FB		 8810 break;
8811
8812 case 6:
8813 /* load/store word immediate offset */
8814 rd = insn & 7;
8815 rn = (insn >> 3) & 7;
b0109805 8816 addr = load_reg(s, rn);
99c475ab 8817 val = (insn >> 4) & 0x7c;
b0109805 8818 tcg_gen_addi_i32(addr, addr, val);
99c475ab
FB		 8819
8820 if (insn & (1 << 11)) {
8821 /* load */
b0109805
PB		 8822 tmp = gen_ld32(addr, IS_USER(s));
8823 store_reg(s, rd, tmp);
99c475ab
FB		 8824 } else {
8825 /* store */
b0109805
PB		 8826 tmp = load_reg(s, rd);
8827 gen_st32(tmp, addr, IS_USER(s));
99c475ab 8828 }
7d1b0095 8829 tcg_temp_free_i32(addr);
99c475ab
FB		 8830 break;
8831
8832 case 7:
8833 /* load/store byte immediate offset */
8834 rd = insn & 7;
8835 rn = (insn >> 3) & 7;
b0109805 8836 addr = load_reg(s, rn);
99c475ab 8837 val = (insn >> 6) & 0x1f;
b0109805 8838 tcg_gen_addi_i32(addr, addr, val);
99c475ab
FB		 8839
8840 if (insn & (1 << 11)) {
8841 /* load */
b0109805
PB		 8842 tmp = gen_ld8u(addr, IS_USER(s));
8843 store_reg(s, rd, tmp);
99c475ab
FB		 8844 } else {
8845 /* store */
b0109805
PB		 8846 tmp = load_reg(s, rd);
8847 gen_st8(tmp, addr, IS_USER(s));
99c475ab 8848 }
7d1b0095 8849 tcg_temp_free_i32(addr);
99c475ab
FB		 8850 break;
8851
8852 case 8:
8853 /* load/store halfword immediate offset */
8854 rd = insn & 7;
8855 rn = (insn >> 3) & 7;
b0109805 8856 addr = load_reg(s, rn);
99c475ab 8857 val = (insn >> 5) & 0x3e;
b0109805 8858 tcg_gen_addi_i32(addr, addr, val);
99c475ab
FB		 8859
8860 if (insn & (1 << 11)) {
8861 /* load */
b0109805
PB		 8862 tmp = gen_ld16u(addr, IS_USER(s));
8863 store_reg(s, rd, tmp);
99c475ab
FB		 8864 } else {
8865 /* store */
b0109805
PB		 8866 tmp = load_reg(s, rd);
8867 gen_st16(tmp, addr, IS_USER(s));
99c475ab 8868 }
7d1b0095 8869 tcg_temp_free_i32(addr);
99c475ab
FB		 8870 break;
8871
8872 case 9:
8873 /* load/store from stack */
8874 rd = (insn >> 8) & 7;
b0109805 8875 addr = load_reg(s, 13);
99c475ab 8876 val = (insn & 0xff) * 4;
b0109805 8877 tcg_gen_addi_i32(addr, addr, val);
99c475ab
FB		 8878
8879 if (insn & (1 << 11)) {
8880 /* load */
b0109805
PB		 8881 tmp = gen_ld32(addr, IS_USER(s));
8882 store_reg(s, rd, tmp);
99c475ab
FB		 8883 } else {
8884 /* store */
b0109805
PB		 8885 tmp = load_reg(s, rd);
8886 gen_st32(tmp, addr, IS_USER(s));
99c475ab 8887 }
7d1b0095 8888 tcg_temp_free_i32(addr);
99c475ab
FB		 8889 break;
8890
8891 case 10:
8892 /* add to high reg */
8893 rd = (insn >> 8) & 7;
5899f386
FB		 8894 if (insn & (1 << 11)) {
8895 /* SP */
5e3f878a 8896 tmp = load_reg(s, 13);
5899f386
FB		 8897 } else {
8898 /* PC. bit 1 is ignored. */
7d1b0095 8899 tmp = tcg_temp_new_i32();
5e3f878a 8900 tcg_gen_movi_i32(tmp, (s->pc + 2) & ~(uint32_t)2);
5899f386 8901 }
99c475ab 8902 val = (insn & 0xff) * 4;
5e3f878a
PB		 8903 tcg_gen_addi_i32(tmp, tmp, val);
8904 store_reg(s, rd, tmp);
99c475ab
FB		 8905 break;
8906
8907 case 11:
8908 /* misc */
8909 op = (insn >> 8) & 0xf;
8910 switch (op) {
8911 case 0:
8912 /* adjust stack pointer */
b26eefb6 8913 tmp = load_reg(s, 13);
99c475ab
FB		 8914 val = (insn & 0x7f) * 4;
8915 if (insn & (1 << 7))
6a0d8a1d 8916 val = -(int32_t)val;
b26eefb6
PB		 8917 tcg_gen_addi_i32(tmp, tmp, val);
8918 store_reg(s, 13, tmp);
99c475ab
FB		 8919 break;
8920
9ee6e8bb
PB		 8921 case 2: /* sign/zero extend. */
8922 ARCH(6);
8923 rd = insn & 7;
8924 rm = (insn >> 3) & 7;
b0109805 8925 tmp = load_reg(s, rm);
9ee6e8bb 8926 switch ((insn >> 6) & 3) {
b0109805
PB		 8927 case 0: gen_sxth(tmp); break;
8928 case 1: gen_sxtb(tmp); break;
8929 case 2: gen_uxth(tmp); break;
8930 case 3: gen_uxtb(tmp); break;
9ee6e8bb 8931 }
b0109805 8932 store_reg(s, rd, tmp);
9ee6e8bb 8933 break;
99c475ab
FB		 8934 case 4: case 5: case 0xc: case 0xd:
8935 /* push/pop */
b0109805 8936 addr = load_reg(s, 13);
5899f386
FB		 8937 if (insn & (1 << 8))
8938 offset = 4;
99c475ab 8939 else
5899f386
FB		 8940 offset = 0;
8941 for (i = 0; i < 8; i++) {
8942 if (insn & (1 << i))
8943 offset += 4;
8944 }
8945 if ((insn & (1 << 11)) == 0) {
b0109805 8946 tcg_gen_addi_i32(addr, addr, -offset);
5899f386 8947 }
99c475ab
FB		 8948 for (i = 0; i < 8; i++) {
8949 if (insn & (1 << i)) {
8950 if (insn & (1 << 11)) {
8951 /* pop */
b0109805
PB		 8952 tmp = gen_ld32(addr, IS_USER(s));
8953 store_reg(s, i, tmp);
99c475ab
FB		 8954 } else {
8955 /* push */
b0109805
PB		 8956 tmp = load_reg(s, i);
8957 gen_st32(tmp, addr, IS_USER(s));
99c475ab 8958 }
5899f386 8959 /* advance to the next address. */
b0109805 8960 tcg_gen_addi_i32(addr, addr, 4);
99c475ab
FB		 8961 }
8962 }
a50f5b91 8963 TCGV_UNUSED(tmp);
99c475ab
FB		 8964 if (insn & (1 << 8)) {
8965 if (insn & (1 << 11)) {
8966 /* pop pc */
b0109805 8967 tmp = gen_ld32(addr, IS_USER(s));
99c475ab
FB		 8968 /* don't set the pc until the rest of the instruction
8969 has completed */
8970 } else {
8971 /* push lr */
b0109805
PB		 8972 tmp = load_reg(s, 14);
8973 gen_st32(tmp, addr, IS_USER(s));
99c475ab 8974 }
b0109805 8975 tcg_gen_addi_i32(addr, addr, 4);
99c475ab 8976 }
5899f386 8977 if ((insn & (1 << 11)) == 0) {
b0109805 8978 tcg_gen_addi_i32(addr, addr, -offset);
5899f386 8979 }
99c475ab 8980 /* write back the new stack pointer */
b0109805 8981 store_reg(s, 13, addr);
99c475ab
FB		 8982 /* set the new PC value */
8983 if ((insn & 0x0900) == 0x0900)
b0109805 8984 gen_bx(s, tmp);
99c475ab
FB		 8985 break;
8986
9ee6e8bb
PB		 8987 case 1: case 3: case 9: case 11: /* czb */
8988 rm = insn & 7;
d9ba4830 8989 tmp = load_reg(s, rm);
9ee6e8bb
PB		 8990 s->condlabel = gen_new_label();
8991 s->condjmp = 1;
8992 if (insn & (1 << 11))
cb63669a 8993 tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, s->condlabel);
9ee6e8bb 8994 else
cb63669a 8995 tcg_gen_brcondi_i32(TCG_COND_NE, tmp, 0, s->condlabel);
7d1b0095 8996 tcg_temp_free_i32(tmp);
9ee6e8bb
PB		 8997 offset = ((insn & 0xf8) >> 2) | (insn & 0x200) >> 3;
8998 val = (uint32_t)s->pc + 2;
8999 val += offset;
9000 gen_jmp(s, val);
9001 break;
9002
9003 case 15: /* IT, nop-hint. */
9004 if ((insn & 0xf) == 0) {
9005 gen_nop_hint(s, (insn >> 4) & 0xf);
9006 break;
9007 }
9008 /* If Then. */
9009 s->condexec_cond = (insn >> 4) & 0xe;
9010 s->condexec_mask = insn & 0x1f;
9011 /* No actual code generated for this insn, just setup state. */
9012 break;
9013
06c949e6 9014 case 0xe: /* bkpt */
bc4a0de0 9015 gen_exception_insn(s, 2, EXCP_BKPT);
06c949e6
PB		 9016 break;
9017
9ee6e8bb
PB		 9018 case 0xa: /* rev */
9019 ARCH(6);
9020 rn = (insn >> 3) & 0x7;
9021 rd = insn & 0x7;
b0109805 9022 tmp = load_reg(s, rn);
9ee6e8bb 9023 switch ((insn >> 6) & 3) {
66896cb8 9024 case 0: tcg_gen_bswap32_i32(tmp, tmp); break;
b0109805
PB		 9025 case 1: gen_rev16(tmp); break;
9026 case 3: gen_revsh(tmp); break;
9ee6e8bb
PB		 9027 default: goto illegal_op;
9028 }
b0109805 9029 store_reg(s, rd, tmp);
9ee6e8bb
PB		 9030 break;
9031
9032 case 6: /* cps */
9033 ARCH(6);
9034 if (IS_USER(s))
9035 break;
9036 if (IS_M(env)) {
8984bd2e 9037 tmp = tcg_const_i32((insn & (1 << 4)) != 0);
9ee6e8bb 9038 /* PRIMASK */
8984bd2e
PB		 9039 if (insn & 1) {
9040 addr = tcg_const_i32(16);
9041 gen_helper_v7m_msr(cpu_env, addr, tmp);
b75263d6 9042 tcg_temp_free_i32(addr);
8984bd2e 9043 }
9ee6e8bb 9044 /* FAULTMASK */
8984bd2e
PB		 9045 if (insn & 2) {
9046 addr = tcg_const_i32(17);
9047 gen_helper_v7m_msr(cpu_env, addr, tmp);
b75263d6 9048 tcg_temp_free_i32(addr);
8984bd2e 9049 }
b75263d6 9050 tcg_temp_free_i32(tmp);
9ee6e8bb
PB		 9051 gen_lookup_tb(s);
9052 } else {
9053 if (insn & (1 << 4))
9054 shift = CPSR_A | CPSR_I | CPSR_F;
9055 else
9056 shift = 0;
fa26df03 9057 gen_set_psr_im(s, ((insn & 7) << 6), 0, shift);
9ee6e8bb
PB		 9058 }
9059 break;
9060
99c475ab
FB		 9061 default:
9062 goto undef;
9063 }
9064 break;
9065
9066 case 12:
9067 /* load/store multiple */
9068 rn = (insn >> 8) & 0x7;
b0109805 9069 addr = load_reg(s, rn);
99c475ab
FB		 9070 for (i = 0; i < 8; i++) {
9071 if (insn & (1 << i)) {
99c475ab
FB		 9072 if (insn & (1 << 11)) {
9073 /* load */
b0109805
PB		 9074 tmp = gen_ld32(addr, IS_USER(s));
9075 store_reg(s, i, tmp);
99c475ab
FB		 9076 } else {
9077 /* store */
b0109805
PB		 9078 tmp = load_reg(s, i);
9079 gen_st32(tmp, addr, IS_USER(s));
99c475ab 9080 }
5899f386 9081 /* advance to the next address */
b0109805 9082 tcg_gen_addi_i32(addr, addr, 4);
99c475ab
FB		 9083 }
9084 }
5899f386 9085 /* Base register writeback. */
b0109805
PB		 9086 if ((insn & (1 << rn)) == 0) {
9087 store_reg(s, rn, addr);
9088 } else {
7d1b0095 9089 tcg_temp_free_i32(addr);
b0109805 9090 }
99c475ab
FB		 9091 break;
9092
9093 case 13:
9094 /* conditional branch or swi */
9095 cond = (insn >> 8) & 0xf;
9096 if (cond == 0xe)
9097 goto undef;
9098
9099 if (cond == 0xf) {
9100 /* swi */
422ebf69 9101 gen_set_pc_im(s->pc);
9ee6e8bb 9102 s->is_jmp = DISAS_SWI;
99c475ab
FB		 9103 break;
9104 }
9105 /* generate a conditional jump to next instruction */
e50e6a20 9106 s->condlabel = gen_new_label();
d9ba4830 9107 gen_test_cc(cond ^ 1, s->condlabel);
e50e6a20 9108 s->condjmp = 1;
99c475ab
FB		 9109
9110 /* jump to the offset */
5899f386 9111 val = (uint32_t)s->pc + 2;
99c475ab 9112 offset = ((int32_t)insn << 24) >> 24;
5899f386 9113 val += offset << 1;
8aaca4c0 9114 gen_jmp(s, val);
99c475ab
FB		 9115 break;
9116
9117 case 14:
358bf29e 9118 if (insn & (1 << 11)) {
9ee6e8bb
PB		 9119 if (disas_thumb2_insn(env, s, insn))
9120 goto undef32;
358bf29e
PB		 9121 break;
9122 }
9ee6e8bb 9123 /* unconditional branch */
99c475ab
FB		 9124 val = (uint32_t)s->pc;
9125 offset = ((int32_t)insn << 21) >> 21;
9126 val += (offset << 1) + 2;
8aaca4c0 9127 gen_jmp(s, val);
99c475ab
FB		 9128 break;
9129
9130 case 15:
9ee6e8bb 9131 if (disas_thumb2_insn(env, s, insn))
6a0d8a1d 9132 goto undef32;
9ee6e8bb 9133 break;
99c475ab
FB		 9134 }
9135 return;
9ee6e8bb 9136undef32:
bc4a0de0 9137 gen_exception_insn(s, 4, EXCP_UDEF);
9ee6e8bb
PB		 9138 return;
9139illegal_op:
99c475ab 9140undef:
bc4a0de0 9141 gen_exception_insn(s, 2, EXCP_UDEF);
99c475ab
FB		 9142}
9143
2c0262af
FB		 9144/* generate intermediate code in gen_opc_buf and gen_opparam_buf for
9145 basic block 'tb'. If search_pc is TRUE, also generate PC
9146 information for each intermediate instruction. */
2cfc5f17
TS		 9147static inline void gen_intermediate_code_internal(CPUState *env,
9148 TranslationBlock *tb,
9149 int search_pc)
2c0262af
FB		 9150{
9151 DisasContext dc1, *dc = &dc1;
a1d1bb31 9152 CPUBreakpoint *bp;
2c0262af
FB		 9153 uint16_t *gen_opc_end;
9154 int j, lj;
0fa85d43 9155 target_ulong pc_start;
b5ff1b31 9156 uint32_t next_page_start;
2e70f6ef
PB		 9157 int num_insns;
9158 int max_insns;
3b46e624 9159
2c0262af 9160 /* generate intermediate code */
0fa85d43 9161 pc_start = tb->pc;
3b46e624 9162
2c0262af
FB		 9163 dc->tb = tb;
9164
2c0262af 9165 gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
2c0262af
FB		 9166
9167 dc->is_jmp = DISAS_NEXT;
9168 dc->pc = pc_start;
8aaca4c0 9169 dc->singlestep_enabled = env->singlestep_enabled;
e50e6a20 9170 dc->condjmp = 0;
7204ab88 9171 dc->thumb = ARM_TBFLAG_THUMB(tb->flags);
98eac7ca
PM		 9172 dc->condexec_mask = (ARM_TBFLAG_CONDEXEC(tb->flags) & 0xf) << 1;
9173 dc->condexec_cond = ARM_TBFLAG_CONDEXEC(tb->flags) >> 4;
b5ff1b31 9174#if !defined(CONFIG_USER_ONLY)
61f74d6a 9175 dc->user = (ARM_TBFLAG_PRIV(tb->flags) == 0);
b5ff1b31 9176#endif
5df8bac1 9177 dc->vfp_enabled = ARM_TBFLAG_VFPEN(tb->flags);
69d1fc22
PM		 9178 dc->vec_len = ARM_TBFLAG_VECLEN(tb->flags);
9179 dc->vec_stride = ARM_TBFLAG_VECSTRIDE(tb->flags);
a7812ae4
PB		 9180 cpu_F0s = tcg_temp_new_i32();
9181 cpu_F1s = tcg_temp_new_i32();
9182 cpu_F0d = tcg_temp_new_i64();
9183 cpu_F1d = tcg_temp_new_i64();
ad69471c
PB		 9184 cpu_V0 = cpu_F0d;
9185 cpu_V1 = cpu_F1d;
e677137d 9186 /* FIXME: cpu_M0 can probably be the same as cpu_V0. */
a7812ae4 9187 cpu_M0 = tcg_temp_new_i64();
b5ff1b31 9188 next_page_start = (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
2c0262af 9189 lj = -1;
2e70f6ef
PB		 9190 num_insns = 0;
9191 max_insns = tb->cflags & CF_COUNT_MASK;
9192 if (max_insns == 0)
9193 max_insns = CF_COUNT_MASK;
9194
9195 gen_icount_start();
e12ce78d 9196
3849902c
PM		 9197 tcg_clear_temp_count();
9198
e12ce78d
PM		 9199 /* A note on handling of the condexec (IT) bits:
9200 *
9201 * We want to avoid the overhead of having to write the updated condexec
9202 * bits back to the CPUState for every instruction in an IT block. So:
9203 * (1) if the condexec bits are not already zero then we write
9204 * zero back into the CPUState now. This avoids complications trying
9205 * to do it at the end of the block. (For example if we don't do this
9206 * it's hard to identify whether we can safely skip writing condexec
9207 * at the end of the TB, which we definitely want to do for the case
9208 * where a TB doesn't do anything with the IT state at all.)
9209 * (2) if we are going to leave the TB then we call gen_set_condexec()
9210 * which will write the correct value into CPUState if zero is wrong.
9211 * This is done both for leaving the TB at the end, and for leaving
9212 * it because of an exception we know will happen, which is done in
9213 * gen_exception_insn(). The latter is necessary because we need to
9214 * leave the TB with the PC/IT state just prior to execution of the
9215 * instruction which caused the exception.
9216 * (3) if we leave the TB unexpectedly (eg a data abort on a load)
9217 * then the CPUState will be wrong and we need to reset it.
9218 * This is handled in the same way as restoration of the
9219 * PC in these situations: we will be called again with search_pc=1
9220 * and generate a mapping of the condexec bits for each PC in
9221 * gen_opc_condexec_bits[]. gen_pc_load[] then uses this to restore
9222 * the condexec bits.
9223 *
9224 * Note that there are no instructions which can read the condexec
9225 * bits, and none which can write non-static values to them, so
9226 * we don't need to care about whether CPUState is correct in the
9227 * middle of a TB.
9228 */
9229
9ee6e8bb
PB		 9230 /* Reset the conditional execution bits immediately. This avoids
9231 complications trying to do it at the end of the block. */
98eac7ca 9232 if (dc->condexec_mask || dc->condexec_cond)
8f01245e 9233 {
7d1b0095 9234 TCGv tmp = tcg_temp_new_i32();
8f01245e 9235 tcg_gen_movi_i32(tmp, 0);
d9ba4830 9236 store_cpu_field(tmp, condexec_bits);
8f01245e 9237 }
2c0262af 9238 do {
fbb4a2e3
PB		 9239#ifdef CONFIG_USER_ONLY
9240 /* Intercept jump to the magic kernel page. */
9241 if (dc->pc >= 0xffff0000) {
9242 /* We always get here via a jump, so know we are not in a
9243 conditional execution block. */
9244 gen_exception(EXCP_KERNEL_TRAP);
9245 dc->is_jmp = DISAS_UPDATE;
9246 break;
9247 }
9248#else
9ee6e8bb
PB		 9249 if (dc->pc >= 0xfffffff0 && IS_M(env)) {
9250 /* We always get here via a jump, so know we are not in a
9251 conditional execution block. */
d9ba4830 9252 gen_exception(EXCP_EXCEPTION_EXIT);
d60bb01c
PB		 9253 dc->is_jmp = DISAS_UPDATE;
9254 break;
9ee6e8bb
PB		 9255 }
9256#endif
9257
72cf2d4f
BS		 9258 if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) {
9259 QTAILQ_FOREACH(bp, &env->breakpoints, entry) {
a1d1bb31 9260 if (bp->pc == dc->pc) {
bc4a0de0 9261 gen_exception_insn(dc, 0, EXCP_DEBUG);
9ee6e8bb
PB		 9262 /* Advance PC so that clearing the breakpoint will
9263 invalidate this TB. */
9264 dc->pc += 2;
9265 goto done_generating;
1fddef4b
FB		 9266 break;
9267 }
9268 }
9269 }
2c0262af
FB		 9270 if (search_pc) {
9271 j = gen_opc_ptr - gen_opc_buf;
9272 if (lj < j) {
9273 lj++;
9274 while (lj < j)
9275 gen_opc_instr_start[lj++] = 0;
9276 }
0fa85d43 9277 gen_opc_pc[lj] = dc->pc;
e12ce78d 9278 gen_opc_condexec_bits[lj] = (dc->condexec_cond << 4) | (dc->condexec_mask >> 1);
2c0262af 9279 gen_opc_instr_start[lj] = 1;
2e70f6ef 9280 gen_opc_icount[lj] = num_insns;
2c0262af 9281 }
e50e6a20 9282
2e70f6ef
PB		 9283 if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO))
9284 gen_io_start();
9285
5642463a
PM		 9286 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP))) {
9287 tcg_gen_debug_insn_start(dc->pc);
9288 }
9289
7204ab88 9290 if (dc->thumb) {
9ee6e8bb
PB		 9291 disas_thumb_insn(env, dc);
9292 if (dc->condexec_mask) {
9293 dc->condexec_cond = (dc->condexec_cond & 0xe)
9294 | ((dc->condexec_mask >> 4) & 1);
9295 dc->condexec_mask = (dc->condexec_mask << 1) & 0x1f;
9296 if (dc->condexec_mask == 0) {
9297 dc->condexec_cond = 0;
9298 }
9299 }
9300 } else {
9301 disas_arm_insn(env, dc);
9302 }
e50e6a20
FB		 9303
9304 if (dc->condjmp && !dc->is_jmp) {
9305 gen_set_label(dc->condlabel);
9306 dc->condjmp = 0;
9307 }
3849902c
PM		 9308
9309 if (tcg_check_temp_count()) {
9310 fprintf(stderr, "TCG temporary leak before %08x\n", dc->pc);
9311 }
9312
aaf2d97d 9313 /* Translation stops when a conditional branch is encountered.
e50e6a20 9314 * Otherwise the subsequent code could get translated several times.
b5ff1b31 9315 * Also stop translation when a page boundary is reached. This
bf20dc07 9316 * ensures prefetch aborts occur at the right place. */
2e70f6ef 9317 num_insns ++;
1fddef4b
FB		 9318 } while (!dc->is_jmp && gen_opc_ptr < gen_opc_end &&
9319 !env->singlestep_enabled &&
1b530a6d 9320 !singlestep &&
2e70f6ef
PB		 9321 dc->pc < next_page_start &&
9322 num_insns < max_insns);
9323
9324 if (tb->cflags & CF_LAST_IO) {
9325 if (dc->condjmp) {
9326 /* FIXME: This can theoretically happen with self-modifying
9327 code. */
9328 cpu_abort(env, "IO on conditional branch instruction");
9329 }
9330 gen_io_end();
9331 }
9ee6e8bb 9332
b5ff1b31 9333 /* At this stage dc->condjmp will only be set when the skipped
9ee6e8bb
PB		 9334 instruction was a conditional branch or trap, and the PC has
9335 already been written. */
551bd27f 9336 if (unlikely(env->singlestep_enabled)) {
8aaca4c0 9337 /* Make sure the pc is updated, and raise a debug exception. */
e50e6a20 9338 if (dc->condjmp) {
9ee6e8bb
PB		 9339 gen_set_condexec(dc);
9340 if (dc->is_jmp == DISAS_SWI) {
d9ba4830 9341 gen_exception(EXCP_SWI);
9ee6e8bb 9342 } else {
d9ba4830 9343 gen_exception(EXCP_DEBUG);
9ee6e8bb 9344 }
e50e6a20
FB		 9345 gen_set_label(dc->condlabel);
9346 }
9347 if (dc->condjmp || !dc->is_jmp) {
5e3f878a 9348 gen_set_pc_im(dc->pc);
e50e6a20 9349 dc->condjmp = 0;
8aaca4c0 9350 }
9ee6e8bb
PB		 9351 gen_set_condexec(dc);
9352 if (dc->is_jmp == DISAS_SWI && !dc->condjmp) {
d9ba4830 9353 gen_exception(EXCP_SWI);
9ee6e8bb
PB		 9354 } else {
9355 /* FIXME: Single stepping a WFI insn will not halt
9356 the CPU. */
d9ba4830 9357 gen_exception(EXCP_DEBUG);
9ee6e8bb 9358 }
8aaca4c0 9359 } else {
9ee6e8bb
PB		 9360 /* While branches must always occur at the end of an IT block,
9361 there are a few other things that can cause us to terminate
9362 the TB in the middel of an IT block:
9363 - Exception generating instructions (bkpt, swi, undefined).
9364 - Page boundaries.
9365 - Hardware watchpoints.
9366 Hardware breakpoints have already been handled and skip this code.
9367 */
9368 gen_set_condexec(dc);
8aaca4c0 9369 switch(dc->is_jmp) {
8aaca4c0 9370 case DISAS_NEXT:
6e256c93 9371 gen_goto_tb(dc, 1, dc->pc);
8aaca4c0
FB		 9372 break;
9373 default:
9374 case DISAS_JUMP:
9375 case DISAS_UPDATE:
9376 /* indicate that the hash table must be used to find the next TB */
57fec1fe 9377 tcg_gen_exit_tb(0);
8aaca4c0
FB		 9378 break;
9379 case DISAS_TB_JUMP:
9380 /* nothing more to generate */
9381 break;
9ee6e8bb 9382 case DISAS_WFI:
d9ba4830 9383 gen_helper_wfi();
9ee6e8bb
PB		 9384 break;
9385 case DISAS_SWI:
d9ba4830 9386 gen_exception(EXCP_SWI);
9ee6e8bb 9387 break;
8aaca4c0 9388 }
e50e6a20
FB		 9389 if (dc->condjmp) {
9390 gen_set_label(dc->condlabel);
9ee6e8bb 9391 gen_set_condexec(dc);
6e256c93 9392 gen_goto_tb(dc, 1, dc->pc);
e50e6a20
FB		 9393 dc->condjmp = 0;
9394 }
2c0262af 9395 }
2e70f6ef 9396
9ee6e8bb 9397done_generating:
2e70f6ef 9398 gen_icount_end(tb, num_insns);
2c0262af
FB		 9399 *gen_opc_ptr = INDEX_op_end;
9400
9401#ifdef DEBUG_DISAS
8fec2b8c 9402 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
93fcfe39
AL		 9403 qemu_log("----------------\n");
9404 qemu_log("IN: %s\n", lookup_symbol(pc_start));
7204ab88 9405 log_target_disas(pc_start, dc->pc - pc_start, dc->thumb);
93fcfe39 9406 qemu_log("\n");
2c0262af
FB		 9407 }
9408#endif
b5ff1b31
FB		 9409 if (search_pc) {
9410 j = gen_opc_ptr - gen_opc_buf;
9411 lj++;
9412 while (lj <= j)
9413 gen_opc_instr_start[lj++] = 0;
b5ff1b31 9414 } else {
2c0262af 9415 tb->size = dc->pc - pc_start;
2e70f6ef 9416 tb->icount = num_insns;
b5ff1b31 9417 }
2c0262af
FB		 9418}
9419
2cfc5f17 9420void gen_intermediate_code(CPUState *env, TranslationBlock *tb)
2c0262af 9421{
2cfc5f17 9422 gen_intermediate_code_internal(env, tb, 0);
2c0262af
FB		 9423}
9424
2cfc5f17 9425void gen_intermediate_code_pc(CPUState *env, TranslationBlock *tb)
2c0262af 9426{
2cfc5f17 9427 gen_intermediate_code_internal(env, tb, 1);
2c0262af
FB		 9428}
9429
b5ff1b31
FB		 9430static const char *cpu_mode_names[16] = {
9431 "usr", "fiq", "irq", "svc", "???", "???", "???", "abt",
9432 "???", "???", "???", "und", "???", "???", "???", "sys"
9433};
9ee6e8bb 9434
9a78eead 9435void cpu_dump_state(CPUState *env, FILE *f, fprintf_function cpu_fprintf,
7fe48483 9436 int flags)
2c0262af
FB		 9437{
9438 int i;
06e80fc9 9439#if 0
bc380d17 9440 union {
b7bcbe95
FB		 9441 uint32_t i;
9442 float s;
9443 } s0, s1;
9444 CPU_DoubleU d;
a94a6abf
PB		 9445 /* ??? This assumes float64 and double have the same layout.
9446 Oh well, it's only debug dumps. */
9447 union {
9448 float64 f64;
9449 double d;
9450 } d0;
06e80fc9 9451#endif
b5ff1b31 9452 uint32_t psr;
2c0262af
FB		 9453
9454 for(i=0;i<16;i++) {
7fe48483 9455 cpu_fprintf(f, "R%02d=%08x", i, env->regs[i]);
2c0262af 9456 if ((i % 4) == 3)
7fe48483 9457 cpu_fprintf(f, "\n");
2c0262af 9458 else
7fe48483 9459 cpu_fprintf(f, " ");
2c0262af 9460 }
b5ff1b31 9461 psr = cpsr_read(env);
687fa640
TS		 9462 cpu_fprintf(f, "PSR=%08x %c%c%c%c %c %s%d\n",
9463 psr,
b5ff1b31
FB		 9464 psr & (1 << 31) ? 'N' : '-',
9465 psr & (1 << 30) ? 'Z' : '-',
9466 psr & (1 << 29) ? 'C' : '-',
9467 psr & (1 << 28) ? 'V' : '-',
5fafdf24 9468 psr & CPSR_T ? 'T' : 'A',
b5ff1b31 9469 cpu_mode_names[psr & 0xf], (psr & 0x10) ? 32 : 26);
b7bcbe95 9470
5e3f878a 9471#if 0
b7bcbe95 9472 for (i = 0; i < 16; i++) {
8e96005d
FB		 9473 d.d = env->vfp.regs[i];
9474 s0.i = d.l.lower;
9475 s1.i = d.l.upper;
a94a6abf
PB		 9476 d0.f64 = d.d;
9477 cpu_fprintf(f, "s%02d=%08x(%8g) s%02d=%08x(%8g) d%02d=%08x%08x(%8g)\n",
b7bcbe95 9478 i * 2, (int)s0.i, s0.s,
a94a6abf 9479 i * 2 + 1, (int)s1.i, s1.s,
b7bcbe95 9480 i, (int)(uint32_t)d.l.upper, (int)(uint32_t)d.l.lower,
a94a6abf 9481 d0.d);
b7bcbe95 9482 }
40f137e1 9483 cpu_fprintf(f, "FPSCR: %08x\n", (int)env->vfp.xregs[ARM_VFP_FPSCR]);
5e3f878a 9484#endif
2c0262af 9485}
a6b025d3 9486
d2856f1a
AJ		 9487void gen_pc_load(CPUState *env, TranslationBlock *tb,
9488 unsigned long searched_pc, int pc_pos, void *puc)
9489{
9490 env->regs[15] = gen_opc_pc[pc_pos];
e12ce78d 9491 env->condexec_bits = gen_opc_condexec_bits[pc_pos];
d2856f1a 9492}
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