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Commit | Line | Data |
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2c0262af FB |
1 | /* |
2 | * ARM translation | |
5fafdf24 | 3 | * |
2c0262af | 4 | * Copyright (c) 2003 Fabrice Bellard |
9ee6e8bb | 5 | * Copyright (c) 2005-2007 CodeSourcery |
18c9b560 | 6 | * Copyright (c) 2007 OpenedHand, Ltd. |
2c0262af FB |
7 | * |
8 | * This library is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU Lesser General Public | |
10 | * License as published by the Free Software Foundation; either | |
11 | * version 2 of the License, or (at your option) any later version. | |
12 | * | |
13 | * This library is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
16 | * Lesser General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU Lesser General Public | |
8167ee88 | 19 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. |
2c0262af FB |
20 | */ |
21 | #include <stdarg.h> | |
22 | #include <stdlib.h> | |
23 | #include <stdio.h> | |
24 | #include <string.h> | |
25 | #include <inttypes.h> | |
26 | ||
27 | #include "cpu.h" | |
28 | #include "exec-all.h" | |
29 | #include "disas.h" | |
57fec1fe | 30 | #include "tcg-op.h" |
79383c9c | 31 | #include "qemu-log.h" |
1497c961 | 32 | |
a7812ae4 | 33 | #include "helpers.h" |
1497c961 | 34 | #define GEN_HELPER 1 |
b26eefb6 | 35 | #include "helpers.h" |
2c0262af | 36 | |
9ee6e8bb PB |
37 | #define ENABLE_ARCH_5J 0 |
38 | #define ENABLE_ARCH_6 arm_feature(env, ARM_FEATURE_V6) | |
39 | #define ENABLE_ARCH_6K arm_feature(env, ARM_FEATURE_V6K) | |
40 | #define ENABLE_ARCH_6T2 arm_feature(env, ARM_FEATURE_THUMB2) | |
41 | #define ENABLE_ARCH_7 arm_feature(env, ARM_FEATURE_V7) | |
b5ff1b31 | 42 | |
86753403 | 43 | #define ARCH(x) do { if (!ENABLE_ARCH_##x) goto illegal_op; } while(0) |
b5ff1b31 | 44 | |
2c0262af FB |
45 | /* internal defines */ |
46 | typedef struct DisasContext { | |
0fa85d43 | 47 | target_ulong pc; |
2c0262af | 48 | int is_jmp; |
e50e6a20 FB |
49 | /* Nonzero if this instruction has been conditionally skipped. */ |
50 | int condjmp; | |
51 | /* The label that will be jumped to when the instruction is skipped. */ | |
52 | int condlabel; | |
9ee6e8bb PB |
53 | /* Thumb-2 condtional execution bits. */ |
54 | int condexec_mask; | |
55 | int condexec_cond; | |
2c0262af | 56 | struct TranslationBlock *tb; |
8aaca4c0 | 57 | int singlestep_enabled; |
5899f386 | 58 | int thumb; |
b5ff1b31 FB |
59 | #if !defined(CONFIG_USER_ONLY) |
60 | int user; | |
61 | #endif | |
5df8bac1 | 62 | int vfp_enabled; |
69d1fc22 PM |
63 | int vec_len; |
64 | int vec_stride; | |
2c0262af FB |
65 | } DisasContext; |
66 | ||
e12ce78d PM |
67 | static uint32_t gen_opc_condexec_bits[OPC_BUF_SIZE]; |
68 | ||
b5ff1b31 FB |
69 | #if defined(CONFIG_USER_ONLY) |
70 | #define IS_USER(s) 1 | |
71 | #else | |
72 | #define IS_USER(s) (s->user) | |
73 | #endif | |
74 | ||
9ee6e8bb PB |
75 | /* These instructions trap after executing, so defer them until after the |
76 | conditional executions state has been updated. */ | |
77 | #define DISAS_WFI 4 | |
78 | #define DISAS_SWI 5 | |
2c0262af | 79 | |
a7812ae4 | 80 | static TCGv_ptr cpu_env; |
ad69471c | 81 | /* We reuse the same 64-bit temporaries for efficiency. */ |
a7812ae4 | 82 | static TCGv_i64 cpu_V0, cpu_V1, cpu_M0; |
155c3eac | 83 | static TCGv_i32 cpu_R[16]; |
426f5abc PB |
84 | static TCGv_i32 cpu_exclusive_addr; |
85 | static TCGv_i32 cpu_exclusive_val; | |
86 | static TCGv_i32 cpu_exclusive_high; | |
87 | #ifdef CONFIG_USER_ONLY | |
88 | static TCGv_i32 cpu_exclusive_test; | |
89 | static TCGv_i32 cpu_exclusive_info; | |
90 | #endif | |
ad69471c | 91 | |
b26eefb6 | 92 | /* FIXME: These should be removed. */ |
a7812ae4 PB |
93 | static TCGv cpu_F0s, cpu_F1s; |
94 | static TCGv_i64 cpu_F0d, cpu_F1d; | |
b26eefb6 | 95 | |
2e70f6ef PB |
96 | #include "gen-icount.h" |
97 | ||
155c3eac FN |
98 | static const char *regnames[] = |
99 | { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", | |
100 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "pc" }; | |
101 | ||
b26eefb6 PB |
102 | /* initialize TCG globals. */ |
103 | void arm_translate_init(void) | |
104 | { | |
155c3eac FN |
105 | int i; |
106 | ||
a7812ae4 PB |
107 | cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env"); |
108 | ||
155c3eac FN |
109 | for (i = 0; i < 16; i++) { |
110 | cpu_R[i] = tcg_global_mem_new_i32(TCG_AREG0, | |
111 | offsetof(CPUState, regs[i]), | |
112 | regnames[i]); | |
113 | } | |
426f5abc PB |
114 | cpu_exclusive_addr = tcg_global_mem_new_i32(TCG_AREG0, |
115 | offsetof(CPUState, exclusive_addr), "exclusive_addr"); | |
116 | cpu_exclusive_val = tcg_global_mem_new_i32(TCG_AREG0, | |
117 | offsetof(CPUState, exclusive_val), "exclusive_val"); | |
118 | cpu_exclusive_high = tcg_global_mem_new_i32(TCG_AREG0, | |
119 | offsetof(CPUState, exclusive_high), "exclusive_high"); | |
120 | #ifdef CONFIG_USER_ONLY | |
121 | cpu_exclusive_test = tcg_global_mem_new_i32(TCG_AREG0, | |
122 | offsetof(CPUState, exclusive_test), "exclusive_test"); | |
123 | cpu_exclusive_info = tcg_global_mem_new_i32(TCG_AREG0, | |
124 | offsetof(CPUState, exclusive_info), "exclusive_info"); | |
125 | #endif | |
155c3eac | 126 | |
a7812ae4 PB |
127 | #define GEN_HELPER 2 |
128 | #include "helpers.h" | |
b26eefb6 PB |
129 | } |
130 | ||
b26eefb6 | 131 | static int num_temps; |
b26eefb6 PB |
132 | |
133 | /* Allocate a temporary variable. */ | |
a7812ae4 | 134 | static TCGv_i32 new_tmp(void) |
b26eefb6 | 135 | { |
12edd4f2 FN |
136 | num_temps++; |
137 | return tcg_temp_new_i32(); | |
b26eefb6 PB |
138 | } |
139 | ||
140 | /* Release a temporary variable. */ | |
141 | static void dead_tmp(TCGv tmp) | |
142 | { | |
12edd4f2 | 143 | tcg_temp_free(tmp); |
b26eefb6 | 144 | num_temps--; |
b26eefb6 PB |
145 | } |
146 | ||
d9ba4830 PB |
147 | static inline TCGv load_cpu_offset(int offset) |
148 | { | |
149 | TCGv tmp = new_tmp(); | |
150 | tcg_gen_ld_i32(tmp, cpu_env, offset); | |
151 | return tmp; | |
152 | } | |
153 | ||
154 | #define load_cpu_field(name) load_cpu_offset(offsetof(CPUState, name)) | |
155 | ||
156 | static inline void store_cpu_offset(TCGv var, int offset) | |
157 | { | |
158 | tcg_gen_st_i32(var, cpu_env, offset); | |
159 | dead_tmp(var); | |
160 | } | |
161 | ||
162 | #define store_cpu_field(var, name) \ | |
163 | store_cpu_offset(var, offsetof(CPUState, name)) | |
164 | ||
b26eefb6 PB |
165 | /* Set a variable to the value of a CPU register. */ |
166 | static void load_reg_var(DisasContext *s, TCGv var, int reg) | |
167 | { | |
168 | if (reg == 15) { | |
169 | uint32_t addr; | |
170 | /* normaly, since we updated PC, we need only to add one insn */ | |
171 | if (s->thumb) | |
172 | addr = (long)s->pc + 2; | |
173 | else | |
174 | addr = (long)s->pc + 4; | |
175 | tcg_gen_movi_i32(var, addr); | |
176 | } else { | |
155c3eac | 177 | tcg_gen_mov_i32(var, cpu_R[reg]); |
b26eefb6 PB |
178 | } |
179 | } | |
180 | ||
181 | /* Create a new temporary and set it to the value of a CPU register. */ | |
182 | static inline TCGv load_reg(DisasContext *s, int reg) | |
183 | { | |
184 | TCGv tmp = new_tmp(); | |
185 | load_reg_var(s, tmp, reg); | |
186 | return tmp; | |
187 | } | |
188 | ||
189 | /* Set a CPU register. The source must be a temporary and will be | |
190 | marked as dead. */ | |
191 | static void store_reg(DisasContext *s, int reg, TCGv var) | |
192 | { | |
193 | if (reg == 15) { | |
194 | tcg_gen_andi_i32(var, var, ~1); | |
195 | s->is_jmp = DISAS_JUMP; | |
196 | } | |
155c3eac | 197 | tcg_gen_mov_i32(cpu_R[reg], var); |
b26eefb6 PB |
198 | dead_tmp(var); |
199 | } | |
200 | ||
b26eefb6 | 201 | /* Value extensions. */ |
86831435 PB |
202 | #define gen_uxtb(var) tcg_gen_ext8u_i32(var, var) |
203 | #define gen_uxth(var) tcg_gen_ext16u_i32(var, var) | |
b26eefb6 PB |
204 | #define gen_sxtb(var) tcg_gen_ext8s_i32(var, var) |
205 | #define gen_sxth(var) tcg_gen_ext16s_i32(var, var) | |
206 | ||
1497c961 PB |
207 | #define gen_sxtb16(var) gen_helper_sxtb16(var, var) |
208 | #define gen_uxtb16(var) gen_helper_uxtb16(var, var) | |
8f01245e | 209 | |
b26eefb6 | 210 | |
b75263d6 JR |
211 | static inline void gen_set_cpsr(TCGv var, uint32_t mask) |
212 | { | |
213 | TCGv tmp_mask = tcg_const_i32(mask); | |
214 | gen_helper_cpsr_write(var, tmp_mask); | |
215 | tcg_temp_free_i32(tmp_mask); | |
216 | } | |
d9ba4830 PB |
217 | /* Set NZCV flags from the high 4 bits of var. */ |
218 | #define gen_set_nzcv(var) gen_set_cpsr(var, CPSR_NZCV) | |
219 | ||
220 | static void gen_exception(int excp) | |
221 | { | |
222 | TCGv tmp = new_tmp(); | |
223 | tcg_gen_movi_i32(tmp, excp); | |
224 | gen_helper_exception(tmp); | |
225 | dead_tmp(tmp); | |
226 | } | |
227 | ||
3670669c PB |
228 | static void gen_smul_dual(TCGv a, TCGv b) |
229 | { | |
230 | TCGv tmp1 = new_tmp(); | |
231 | TCGv tmp2 = new_tmp(); | |
22478e79 AZ |
232 | tcg_gen_ext16s_i32(tmp1, a); |
233 | tcg_gen_ext16s_i32(tmp2, b); | |
3670669c PB |
234 | tcg_gen_mul_i32(tmp1, tmp1, tmp2); |
235 | dead_tmp(tmp2); | |
236 | tcg_gen_sari_i32(a, a, 16); | |
237 | tcg_gen_sari_i32(b, b, 16); | |
238 | tcg_gen_mul_i32(b, b, a); | |
239 | tcg_gen_mov_i32(a, tmp1); | |
240 | dead_tmp(tmp1); | |
241 | } | |
242 | ||
243 | /* Byteswap each halfword. */ | |
244 | static void gen_rev16(TCGv var) | |
245 | { | |
246 | TCGv tmp = new_tmp(); | |
247 | tcg_gen_shri_i32(tmp, var, 8); | |
248 | tcg_gen_andi_i32(tmp, tmp, 0x00ff00ff); | |
249 | tcg_gen_shli_i32(var, var, 8); | |
250 | tcg_gen_andi_i32(var, var, 0xff00ff00); | |
251 | tcg_gen_or_i32(var, var, tmp); | |
252 | dead_tmp(tmp); | |
253 | } | |
254 | ||
255 | /* Byteswap low halfword and sign extend. */ | |
256 | static void gen_revsh(TCGv var) | |
257 | { | |
1a855029 AJ |
258 | tcg_gen_ext16u_i32(var, var); |
259 | tcg_gen_bswap16_i32(var, var); | |
260 | tcg_gen_ext16s_i32(var, var); | |
3670669c PB |
261 | } |
262 | ||
263 | /* Unsigned bitfield extract. */ | |
264 | static void gen_ubfx(TCGv var, int shift, uint32_t mask) | |
265 | { | |
266 | if (shift) | |
267 | tcg_gen_shri_i32(var, var, shift); | |
268 | tcg_gen_andi_i32(var, var, mask); | |
269 | } | |
270 | ||
271 | /* Signed bitfield extract. */ | |
272 | static void gen_sbfx(TCGv var, int shift, int width) | |
273 | { | |
274 | uint32_t signbit; | |
275 | ||
276 | if (shift) | |
277 | tcg_gen_sari_i32(var, var, shift); | |
278 | if (shift + width < 32) { | |
279 | signbit = 1u << (width - 1); | |
280 | tcg_gen_andi_i32(var, var, (1u << width) - 1); | |
281 | tcg_gen_xori_i32(var, var, signbit); | |
282 | tcg_gen_subi_i32(var, var, signbit); | |
283 | } | |
284 | } | |
285 | ||
286 | /* Bitfield insertion. Insert val into base. Clobbers base and val. */ | |
287 | static void gen_bfi(TCGv dest, TCGv base, TCGv val, int shift, uint32_t mask) | |
288 | { | |
3670669c | 289 | tcg_gen_andi_i32(val, val, mask); |
8f8e3aa4 PB |
290 | tcg_gen_shli_i32(val, val, shift); |
291 | tcg_gen_andi_i32(base, base, ~(mask << shift)); | |
3670669c PB |
292 | tcg_gen_or_i32(dest, base, val); |
293 | } | |
294 | ||
838fa72d AJ |
295 | /* Return (b << 32) + a. Mark inputs as dead */ |
296 | static TCGv_i64 gen_addq_msw(TCGv_i64 a, TCGv b) | |
3670669c | 297 | { |
838fa72d AJ |
298 | TCGv_i64 tmp64 = tcg_temp_new_i64(); |
299 | ||
300 | tcg_gen_extu_i32_i64(tmp64, b); | |
301 | dead_tmp(b); | |
302 | tcg_gen_shli_i64(tmp64, tmp64, 32); | |
303 | tcg_gen_add_i64(a, tmp64, a); | |
304 | ||
305 | tcg_temp_free_i64(tmp64); | |
306 | return a; | |
307 | } | |
308 | ||
309 | /* Return (b << 32) - a. Mark inputs as dead. */ | |
310 | static TCGv_i64 gen_subq_msw(TCGv_i64 a, TCGv b) | |
311 | { | |
312 | TCGv_i64 tmp64 = tcg_temp_new_i64(); | |
313 | ||
314 | tcg_gen_extu_i32_i64(tmp64, b); | |
315 | dead_tmp(b); | |
316 | tcg_gen_shli_i64(tmp64, tmp64, 32); | |
317 | tcg_gen_sub_i64(a, tmp64, a); | |
318 | ||
319 | tcg_temp_free_i64(tmp64); | |
320 | return a; | |
3670669c PB |
321 | } |
322 | ||
8f01245e PB |
323 | /* FIXME: Most targets have native widening multiplication. |
324 | It would be good to use that instead of a full wide multiply. */ | |
5e3f878a | 325 | /* 32x32->64 multiply. Marks inputs as dead. */ |
a7812ae4 | 326 | static TCGv_i64 gen_mulu_i64_i32(TCGv a, TCGv b) |
5e3f878a | 327 | { |
a7812ae4 PB |
328 | TCGv_i64 tmp1 = tcg_temp_new_i64(); |
329 | TCGv_i64 tmp2 = tcg_temp_new_i64(); | |
5e3f878a PB |
330 | |
331 | tcg_gen_extu_i32_i64(tmp1, a); | |
332 | dead_tmp(a); | |
333 | tcg_gen_extu_i32_i64(tmp2, b); | |
334 | dead_tmp(b); | |
335 | tcg_gen_mul_i64(tmp1, tmp1, tmp2); | |
b75263d6 | 336 | tcg_temp_free_i64(tmp2); |
5e3f878a PB |
337 | return tmp1; |
338 | } | |
339 | ||
a7812ae4 | 340 | static TCGv_i64 gen_muls_i64_i32(TCGv a, TCGv b) |
5e3f878a | 341 | { |
a7812ae4 PB |
342 | TCGv_i64 tmp1 = tcg_temp_new_i64(); |
343 | TCGv_i64 tmp2 = tcg_temp_new_i64(); | |
5e3f878a PB |
344 | |
345 | tcg_gen_ext_i32_i64(tmp1, a); | |
346 | dead_tmp(a); | |
347 | tcg_gen_ext_i32_i64(tmp2, b); | |
348 | dead_tmp(b); | |
349 | tcg_gen_mul_i64(tmp1, tmp1, tmp2); | |
b75263d6 | 350 | tcg_temp_free_i64(tmp2); |
5e3f878a PB |
351 | return tmp1; |
352 | } | |
353 | ||
8f01245e PB |
354 | /* Swap low and high halfwords. */ |
355 | static void gen_swap_half(TCGv var) | |
356 | { | |
357 | TCGv tmp = new_tmp(); | |
358 | tcg_gen_shri_i32(tmp, var, 16); | |
359 | tcg_gen_shli_i32(var, var, 16); | |
360 | tcg_gen_or_i32(var, var, tmp); | |
3670669c | 361 | dead_tmp(tmp); |
8f01245e PB |
362 | } |
363 | ||
b26eefb6 PB |
364 | /* Dual 16-bit add. Result placed in t0 and t1 is marked as dead. |
365 | tmp = (t0 ^ t1) & 0x8000; | |
366 | t0 &= ~0x8000; | |
367 | t1 &= ~0x8000; | |
368 | t0 = (t0 + t1) ^ tmp; | |
369 | */ | |
370 | ||
371 | static void gen_add16(TCGv t0, TCGv t1) | |
372 | { | |
373 | TCGv tmp = new_tmp(); | |
374 | tcg_gen_xor_i32(tmp, t0, t1); | |
375 | tcg_gen_andi_i32(tmp, tmp, 0x8000); | |
376 | tcg_gen_andi_i32(t0, t0, ~0x8000); | |
377 | tcg_gen_andi_i32(t1, t1, ~0x8000); | |
378 | tcg_gen_add_i32(t0, t0, t1); | |
379 | tcg_gen_xor_i32(t0, t0, tmp); | |
380 | dead_tmp(tmp); | |
381 | dead_tmp(t1); | |
382 | } | |
383 | ||
9a119ff6 PB |
384 | #define gen_set_CF(var) tcg_gen_st_i32(var, cpu_env, offsetof(CPUState, CF)) |
385 | ||
b26eefb6 PB |
386 | /* Set CF to the top bit of var. */ |
387 | static void gen_set_CF_bit31(TCGv var) | |
388 | { | |
389 | TCGv tmp = new_tmp(); | |
390 | tcg_gen_shri_i32(tmp, var, 31); | |
4cc633c3 | 391 | gen_set_CF(tmp); |
b26eefb6 PB |
392 | dead_tmp(tmp); |
393 | } | |
394 | ||
395 | /* Set N and Z flags from var. */ | |
396 | static inline void gen_logic_CC(TCGv var) | |
397 | { | |
6fbe23d5 PB |
398 | tcg_gen_st_i32(var, cpu_env, offsetof(CPUState, NF)); |
399 | tcg_gen_st_i32(var, cpu_env, offsetof(CPUState, ZF)); | |
b26eefb6 PB |
400 | } |
401 | ||
402 | /* T0 += T1 + CF. */ | |
396e467c | 403 | static void gen_adc(TCGv t0, TCGv t1) |
b26eefb6 | 404 | { |
d9ba4830 | 405 | TCGv tmp; |
396e467c | 406 | tcg_gen_add_i32(t0, t0, t1); |
d9ba4830 | 407 | tmp = load_cpu_field(CF); |
396e467c | 408 | tcg_gen_add_i32(t0, t0, tmp); |
b26eefb6 PB |
409 | dead_tmp(tmp); |
410 | } | |
411 | ||
e9bb4aa9 JR |
412 | /* dest = T0 + T1 + CF. */ |
413 | static void gen_add_carry(TCGv dest, TCGv t0, TCGv t1) | |
414 | { | |
415 | TCGv tmp; | |
416 | tcg_gen_add_i32(dest, t0, t1); | |
417 | tmp = load_cpu_field(CF); | |
418 | tcg_gen_add_i32(dest, dest, tmp); | |
419 | dead_tmp(tmp); | |
420 | } | |
421 | ||
3670669c PB |
422 | /* dest = T0 - T1 + CF - 1. */ |
423 | static void gen_sub_carry(TCGv dest, TCGv t0, TCGv t1) | |
424 | { | |
d9ba4830 | 425 | TCGv tmp; |
3670669c | 426 | tcg_gen_sub_i32(dest, t0, t1); |
d9ba4830 | 427 | tmp = load_cpu_field(CF); |
3670669c PB |
428 | tcg_gen_add_i32(dest, dest, tmp); |
429 | tcg_gen_subi_i32(dest, dest, 1); | |
430 | dead_tmp(tmp); | |
431 | } | |
432 | ||
ad69471c PB |
433 | /* FIXME: Implement this natively. */ |
434 | #define tcg_gen_abs_i32(t0, t1) gen_helper_abs(t0, t1) | |
435 | ||
9a119ff6 | 436 | static void shifter_out_im(TCGv var, int shift) |
b26eefb6 | 437 | { |
9a119ff6 PB |
438 | TCGv tmp = new_tmp(); |
439 | if (shift == 0) { | |
440 | tcg_gen_andi_i32(tmp, var, 1); | |
b26eefb6 | 441 | } else { |
9a119ff6 | 442 | tcg_gen_shri_i32(tmp, var, shift); |
4cc633c3 | 443 | if (shift != 31) |
9a119ff6 PB |
444 | tcg_gen_andi_i32(tmp, tmp, 1); |
445 | } | |
446 | gen_set_CF(tmp); | |
447 | dead_tmp(tmp); | |
448 | } | |
b26eefb6 | 449 | |
9a119ff6 PB |
450 | /* Shift by immediate. Includes special handling for shift == 0. */ |
451 | static inline void gen_arm_shift_im(TCGv var, int shiftop, int shift, int flags) | |
452 | { | |
453 | switch (shiftop) { | |
454 | case 0: /* LSL */ | |
455 | if (shift != 0) { | |
456 | if (flags) | |
457 | shifter_out_im(var, 32 - shift); | |
458 | tcg_gen_shli_i32(var, var, shift); | |
459 | } | |
460 | break; | |
461 | case 1: /* LSR */ | |
462 | if (shift == 0) { | |
463 | if (flags) { | |
464 | tcg_gen_shri_i32(var, var, 31); | |
465 | gen_set_CF(var); | |
466 | } | |
467 | tcg_gen_movi_i32(var, 0); | |
468 | } else { | |
469 | if (flags) | |
470 | shifter_out_im(var, shift - 1); | |
471 | tcg_gen_shri_i32(var, var, shift); | |
472 | } | |
473 | break; | |
474 | case 2: /* ASR */ | |
475 | if (shift == 0) | |
476 | shift = 32; | |
477 | if (flags) | |
478 | shifter_out_im(var, shift - 1); | |
479 | if (shift == 32) | |
480 | shift = 31; | |
481 | tcg_gen_sari_i32(var, var, shift); | |
482 | break; | |
483 | case 3: /* ROR/RRX */ | |
484 | if (shift != 0) { | |
485 | if (flags) | |
486 | shifter_out_im(var, shift - 1); | |
f669df27 | 487 | tcg_gen_rotri_i32(var, var, shift); break; |
9a119ff6 | 488 | } else { |
d9ba4830 | 489 | TCGv tmp = load_cpu_field(CF); |
9a119ff6 PB |
490 | if (flags) |
491 | shifter_out_im(var, 0); | |
492 | tcg_gen_shri_i32(var, var, 1); | |
b26eefb6 PB |
493 | tcg_gen_shli_i32(tmp, tmp, 31); |
494 | tcg_gen_or_i32(var, var, tmp); | |
495 | dead_tmp(tmp); | |
b26eefb6 PB |
496 | } |
497 | } | |
498 | }; | |
499 | ||
8984bd2e PB |
500 | static inline void gen_arm_shift_reg(TCGv var, int shiftop, |
501 | TCGv shift, int flags) | |
502 | { | |
503 | if (flags) { | |
504 | switch (shiftop) { | |
505 | case 0: gen_helper_shl_cc(var, var, shift); break; | |
506 | case 1: gen_helper_shr_cc(var, var, shift); break; | |
507 | case 2: gen_helper_sar_cc(var, var, shift); break; | |
508 | case 3: gen_helper_ror_cc(var, var, shift); break; | |
509 | } | |
510 | } else { | |
511 | switch (shiftop) { | |
512 | case 0: gen_helper_shl(var, var, shift); break; | |
513 | case 1: gen_helper_shr(var, var, shift); break; | |
514 | case 2: gen_helper_sar(var, var, shift); break; | |
f669df27 AJ |
515 | case 3: tcg_gen_andi_i32(shift, shift, 0x1f); |
516 | tcg_gen_rotr_i32(var, var, shift); break; | |
8984bd2e PB |
517 | } |
518 | } | |
519 | dead_tmp(shift); | |
520 | } | |
521 | ||
6ddbc6e4 PB |
522 | #define PAS_OP(pfx) \ |
523 | switch (op2) { \ | |
524 | case 0: gen_pas_helper(glue(pfx,add16)); break; \ | |
525 | case 1: gen_pas_helper(glue(pfx,addsubx)); break; \ | |
526 | case 2: gen_pas_helper(glue(pfx,subaddx)); break; \ | |
527 | case 3: gen_pas_helper(glue(pfx,sub16)); break; \ | |
528 | case 4: gen_pas_helper(glue(pfx,add8)); break; \ | |
529 | case 7: gen_pas_helper(glue(pfx,sub8)); break; \ | |
530 | } | |
d9ba4830 | 531 | static void gen_arm_parallel_addsub(int op1, int op2, TCGv a, TCGv b) |
6ddbc6e4 | 532 | { |
a7812ae4 | 533 | TCGv_ptr tmp; |
6ddbc6e4 PB |
534 | |
535 | switch (op1) { | |
536 | #define gen_pas_helper(name) glue(gen_helper_,name)(a, a, b, tmp) | |
537 | case 1: | |
a7812ae4 | 538 | tmp = tcg_temp_new_ptr(); |
6ddbc6e4 PB |
539 | tcg_gen_addi_ptr(tmp, cpu_env, offsetof(CPUState, GE)); |
540 | PAS_OP(s) | |
b75263d6 | 541 | tcg_temp_free_ptr(tmp); |
6ddbc6e4 PB |
542 | break; |
543 | case 5: | |
a7812ae4 | 544 | tmp = tcg_temp_new_ptr(); |
6ddbc6e4 PB |
545 | tcg_gen_addi_ptr(tmp, cpu_env, offsetof(CPUState, GE)); |
546 | PAS_OP(u) | |
b75263d6 | 547 | tcg_temp_free_ptr(tmp); |
6ddbc6e4 PB |
548 | break; |
549 | #undef gen_pas_helper | |
550 | #define gen_pas_helper(name) glue(gen_helper_,name)(a, a, b) | |
551 | case 2: | |
552 | PAS_OP(q); | |
553 | break; | |
554 | case 3: | |
555 | PAS_OP(sh); | |
556 | break; | |
557 | case 6: | |
558 | PAS_OP(uq); | |
559 | break; | |
560 | case 7: | |
561 | PAS_OP(uh); | |
562 | break; | |
563 | #undef gen_pas_helper | |
564 | } | |
565 | } | |
9ee6e8bb PB |
566 | #undef PAS_OP |
567 | ||
6ddbc6e4 PB |
568 | /* For unknown reasons Arm and Thumb-2 use arbitrarily different encodings. */ |
569 | #define PAS_OP(pfx) \ | |
ed89a2f1 | 570 | switch (op1) { \ |
6ddbc6e4 PB |
571 | case 0: gen_pas_helper(glue(pfx,add8)); break; \ |
572 | case 1: gen_pas_helper(glue(pfx,add16)); break; \ | |
573 | case 2: gen_pas_helper(glue(pfx,addsubx)); break; \ | |
574 | case 4: gen_pas_helper(glue(pfx,sub8)); break; \ | |
575 | case 5: gen_pas_helper(glue(pfx,sub16)); break; \ | |
576 | case 6: gen_pas_helper(glue(pfx,subaddx)); break; \ | |
577 | } | |
d9ba4830 | 578 | static void gen_thumb2_parallel_addsub(int op1, int op2, TCGv a, TCGv b) |
6ddbc6e4 | 579 | { |
a7812ae4 | 580 | TCGv_ptr tmp; |
6ddbc6e4 | 581 | |
ed89a2f1 | 582 | switch (op2) { |
6ddbc6e4 PB |
583 | #define gen_pas_helper(name) glue(gen_helper_,name)(a, a, b, tmp) |
584 | case 0: | |
a7812ae4 | 585 | tmp = tcg_temp_new_ptr(); |
6ddbc6e4 PB |
586 | tcg_gen_addi_ptr(tmp, cpu_env, offsetof(CPUState, GE)); |
587 | PAS_OP(s) | |
b75263d6 | 588 | tcg_temp_free_ptr(tmp); |
6ddbc6e4 PB |
589 | break; |
590 | case 4: | |
a7812ae4 | 591 | tmp = tcg_temp_new_ptr(); |
6ddbc6e4 PB |
592 | tcg_gen_addi_ptr(tmp, cpu_env, offsetof(CPUState, GE)); |
593 | PAS_OP(u) | |
b75263d6 | 594 | tcg_temp_free_ptr(tmp); |
6ddbc6e4 PB |
595 | break; |
596 | #undef gen_pas_helper | |
597 | #define gen_pas_helper(name) glue(gen_helper_,name)(a, a, b) | |
598 | case 1: | |
599 | PAS_OP(q); | |
600 | break; | |
601 | case 2: | |
602 | PAS_OP(sh); | |
603 | break; | |
604 | case 5: | |
605 | PAS_OP(uq); | |
606 | break; | |
607 | case 6: | |
608 | PAS_OP(uh); | |
609 | break; | |
610 | #undef gen_pas_helper | |
611 | } | |
612 | } | |
9ee6e8bb PB |
613 | #undef PAS_OP |
614 | ||
d9ba4830 PB |
615 | static void gen_test_cc(int cc, int label) |
616 | { | |
617 | TCGv tmp; | |
618 | TCGv tmp2; | |
d9ba4830 PB |
619 | int inv; |
620 | ||
d9ba4830 PB |
621 | switch (cc) { |
622 | case 0: /* eq: Z */ | |
6fbe23d5 | 623 | tmp = load_cpu_field(ZF); |
cb63669a | 624 | tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, label); |
d9ba4830 PB |
625 | break; |
626 | case 1: /* ne: !Z */ | |
6fbe23d5 | 627 | tmp = load_cpu_field(ZF); |
cb63669a | 628 | tcg_gen_brcondi_i32(TCG_COND_NE, tmp, 0, label); |
d9ba4830 PB |
629 | break; |
630 | case 2: /* cs: C */ | |
631 | tmp = load_cpu_field(CF); | |
cb63669a | 632 | tcg_gen_brcondi_i32(TCG_COND_NE, tmp, 0, label); |
d9ba4830 PB |
633 | break; |
634 | case 3: /* cc: !C */ | |
635 | tmp = load_cpu_field(CF); | |
cb63669a | 636 | tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, label); |
d9ba4830 PB |
637 | break; |
638 | case 4: /* mi: N */ | |
6fbe23d5 | 639 | tmp = load_cpu_field(NF); |
cb63669a | 640 | tcg_gen_brcondi_i32(TCG_COND_LT, tmp, 0, label); |
d9ba4830 PB |
641 | break; |
642 | case 5: /* pl: !N */ | |
6fbe23d5 | 643 | tmp = load_cpu_field(NF); |
cb63669a | 644 | tcg_gen_brcondi_i32(TCG_COND_GE, tmp, 0, label); |
d9ba4830 PB |
645 | break; |
646 | case 6: /* vs: V */ | |
647 | tmp = load_cpu_field(VF); | |
cb63669a | 648 | tcg_gen_brcondi_i32(TCG_COND_LT, tmp, 0, label); |
d9ba4830 PB |
649 | break; |
650 | case 7: /* vc: !V */ | |
651 | tmp = load_cpu_field(VF); | |
cb63669a | 652 | tcg_gen_brcondi_i32(TCG_COND_GE, tmp, 0, label); |
d9ba4830 PB |
653 | break; |
654 | case 8: /* hi: C && !Z */ | |
655 | inv = gen_new_label(); | |
656 | tmp = load_cpu_field(CF); | |
cb63669a | 657 | tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, inv); |
d9ba4830 | 658 | dead_tmp(tmp); |
6fbe23d5 | 659 | tmp = load_cpu_field(ZF); |
cb63669a | 660 | tcg_gen_brcondi_i32(TCG_COND_NE, tmp, 0, label); |
d9ba4830 PB |
661 | gen_set_label(inv); |
662 | break; | |
663 | case 9: /* ls: !C || Z */ | |
664 | tmp = load_cpu_field(CF); | |
cb63669a | 665 | tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, label); |
d9ba4830 | 666 | dead_tmp(tmp); |
6fbe23d5 | 667 | tmp = load_cpu_field(ZF); |
cb63669a | 668 | tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, label); |
d9ba4830 PB |
669 | break; |
670 | case 10: /* ge: N == V -> N ^ V == 0 */ | |
671 | tmp = load_cpu_field(VF); | |
6fbe23d5 | 672 | tmp2 = load_cpu_field(NF); |
d9ba4830 PB |
673 | tcg_gen_xor_i32(tmp, tmp, tmp2); |
674 | dead_tmp(tmp2); | |
cb63669a | 675 | tcg_gen_brcondi_i32(TCG_COND_GE, tmp, 0, label); |
d9ba4830 PB |
676 | break; |
677 | case 11: /* lt: N != V -> N ^ V != 0 */ | |
678 | tmp = load_cpu_field(VF); | |
6fbe23d5 | 679 | tmp2 = load_cpu_field(NF); |
d9ba4830 PB |
680 | tcg_gen_xor_i32(tmp, tmp, tmp2); |
681 | dead_tmp(tmp2); | |
cb63669a | 682 | tcg_gen_brcondi_i32(TCG_COND_LT, tmp, 0, label); |
d9ba4830 PB |
683 | break; |
684 | case 12: /* gt: !Z && N == V */ | |
685 | inv = gen_new_label(); | |
6fbe23d5 | 686 | tmp = load_cpu_field(ZF); |
cb63669a | 687 | tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, inv); |
d9ba4830 PB |
688 | dead_tmp(tmp); |
689 | tmp = load_cpu_field(VF); | |
6fbe23d5 | 690 | tmp2 = load_cpu_field(NF); |
d9ba4830 PB |
691 | tcg_gen_xor_i32(tmp, tmp, tmp2); |
692 | dead_tmp(tmp2); | |
cb63669a | 693 | tcg_gen_brcondi_i32(TCG_COND_GE, tmp, 0, label); |
d9ba4830 PB |
694 | gen_set_label(inv); |
695 | break; | |
696 | case 13: /* le: Z || N != V */ | |
6fbe23d5 | 697 | tmp = load_cpu_field(ZF); |
cb63669a | 698 | tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, label); |
d9ba4830 PB |
699 | dead_tmp(tmp); |
700 | tmp = load_cpu_field(VF); | |
6fbe23d5 | 701 | tmp2 = load_cpu_field(NF); |
d9ba4830 PB |
702 | tcg_gen_xor_i32(tmp, tmp, tmp2); |
703 | dead_tmp(tmp2); | |
cb63669a | 704 | tcg_gen_brcondi_i32(TCG_COND_LT, tmp, 0, label); |
d9ba4830 PB |
705 | break; |
706 | default: | |
707 | fprintf(stderr, "Bad condition code 0x%x\n", cc); | |
708 | abort(); | |
709 | } | |
710 | dead_tmp(tmp); | |
711 | } | |
2c0262af | 712 | |
b1d8e52e | 713 | static const uint8_t table_logic_cc[16] = { |
2c0262af FB |
714 | 1, /* and */ |
715 | 1, /* xor */ | |
716 | 0, /* sub */ | |
717 | 0, /* rsb */ | |
718 | 0, /* add */ | |
719 | 0, /* adc */ | |
720 | 0, /* sbc */ | |
721 | 0, /* rsc */ | |
722 | 1, /* andl */ | |
723 | 1, /* xorl */ | |
724 | 0, /* cmp */ | |
725 | 0, /* cmn */ | |
726 | 1, /* orr */ | |
727 | 1, /* mov */ | |
728 | 1, /* bic */ | |
729 | 1, /* mvn */ | |
730 | }; | |
3b46e624 | 731 | |
d9ba4830 PB |
732 | /* Set PC and Thumb state from an immediate address. */ |
733 | static inline void gen_bx_im(DisasContext *s, uint32_t addr) | |
99c475ab | 734 | { |
b26eefb6 | 735 | TCGv tmp; |
99c475ab | 736 | |
b26eefb6 | 737 | s->is_jmp = DISAS_UPDATE; |
d9ba4830 | 738 | if (s->thumb != (addr & 1)) { |
155c3eac | 739 | tmp = new_tmp(); |
d9ba4830 PB |
740 | tcg_gen_movi_i32(tmp, addr & 1); |
741 | tcg_gen_st_i32(tmp, cpu_env, offsetof(CPUState, thumb)); | |
155c3eac | 742 | dead_tmp(tmp); |
d9ba4830 | 743 | } |
155c3eac | 744 | tcg_gen_movi_i32(cpu_R[15], addr & ~1); |
d9ba4830 PB |
745 | } |
746 | ||
747 | /* Set PC and Thumb state from var. var is marked as dead. */ | |
748 | static inline void gen_bx(DisasContext *s, TCGv var) | |
749 | { | |
d9ba4830 | 750 | s->is_jmp = DISAS_UPDATE; |
155c3eac FN |
751 | tcg_gen_andi_i32(cpu_R[15], var, ~1); |
752 | tcg_gen_andi_i32(var, var, 1); | |
753 | store_cpu_field(var, thumb); | |
d9ba4830 PB |
754 | } |
755 | ||
21aeb343 JR |
756 | /* Variant of store_reg which uses branch&exchange logic when storing |
757 | to r15 in ARM architecture v7 and above. The source must be a temporary | |
758 | and will be marked as dead. */ | |
759 | static inline void store_reg_bx(CPUState *env, DisasContext *s, | |
760 | int reg, TCGv var) | |
761 | { | |
762 | if (reg == 15 && ENABLE_ARCH_7) { | |
763 | gen_bx(s, var); | |
764 | } else { | |
765 | store_reg(s, reg, var); | |
766 | } | |
767 | } | |
768 | ||
b0109805 PB |
769 | static inline TCGv gen_ld8s(TCGv addr, int index) |
770 | { | |
771 | TCGv tmp = new_tmp(); | |
772 | tcg_gen_qemu_ld8s(tmp, addr, index); | |
773 | return tmp; | |
774 | } | |
775 | static inline TCGv gen_ld8u(TCGv addr, int index) | |
776 | { | |
777 | TCGv tmp = new_tmp(); | |
778 | tcg_gen_qemu_ld8u(tmp, addr, index); | |
779 | return tmp; | |
780 | } | |
781 | static inline TCGv gen_ld16s(TCGv addr, int index) | |
782 | { | |
783 | TCGv tmp = new_tmp(); | |
784 | tcg_gen_qemu_ld16s(tmp, addr, index); | |
785 | return tmp; | |
786 | } | |
787 | static inline TCGv gen_ld16u(TCGv addr, int index) | |
788 | { | |
789 | TCGv tmp = new_tmp(); | |
790 | tcg_gen_qemu_ld16u(tmp, addr, index); | |
791 | return tmp; | |
792 | } | |
793 | static inline TCGv gen_ld32(TCGv addr, int index) | |
794 | { | |
795 | TCGv tmp = new_tmp(); | |
796 | tcg_gen_qemu_ld32u(tmp, addr, index); | |
797 | return tmp; | |
798 | } | |
84496233 JR |
799 | static inline TCGv_i64 gen_ld64(TCGv addr, int index) |
800 | { | |
801 | TCGv_i64 tmp = tcg_temp_new_i64(); | |
802 | tcg_gen_qemu_ld64(tmp, addr, index); | |
803 | return tmp; | |
804 | } | |
b0109805 PB |
805 | static inline void gen_st8(TCGv val, TCGv addr, int index) |
806 | { | |
807 | tcg_gen_qemu_st8(val, addr, index); | |
808 | dead_tmp(val); | |
809 | } | |
810 | static inline void gen_st16(TCGv val, TCGv addr, int index) | |
811 | { | |
812 | tcg_gen_qemu_st16(val, addr, index); | |
813 | dead_tmp(val); | |
814 | } | |
815 | static inline void gen_st32(TCGv val, TCGv addr, int index) | |
816 | { | |
817 | tcg_gen_qemu_st32(val, addr, index); | |
818 | dead_tmp(val); | |
819 | } | |
84496233 JR |
820 | static inline void gen_st64(TCGv_i64 val, TCGv addr, int index) |
821 | { | |
822 | tcg_gen_qemu_st64(val, addr, index); | |
823 | tcg_temp_free_i64(val); | |
824 | } | |
b5ff1b31 | 825 | |
5e3f878a PB |
826 | static inline void gen_set_pc_im(uint32_t val) |
827 | { | |
155c3eac | 828 | tcg_gen_movi_i32(cpu_R[15], val); |
5e3f878a PB |
829 | } |
830 | ||
b5ff1b31 FB |
831 | /* Force a TB lookup after an instruction that changes the CPU state. */ |
832 | static inline void gen_lookup_tb(DisasContext *s) | |
833 | { | |
a6445c52 | 834 | tcg_gen_movi_i32(cpu_R[15], s->pc & ~1); |
b5ff1b31 FB |
835 | s->is_jmp = DISAS_UPDATE; |
836 | } | |
837 | ||
b0109805 PB |
838 | static inline void gen_add_data_offset(DisasContext *s, unsigned int insn, |
839 | TCGv var) | |
2c0262af | 840 | { |
1e8d4eec | 841 | int val, rm, shift, shiftop; |
b26eefb6 | 842 | TCGv offset; |
2c0262af FB |
843 | |
844 | if (!(insn & (1 << 25))) { | |
845 | /* immediate */ | |
846 | val = insn & 0xfff; | |
847 | if (!(insn & (1 << 23))) | |
848 | val = -val; | |
537730b9 | 849 | if (val != 0) |
b0109805 | 850 | tcg_gen_addi_i32(var, var, val); |
2c0262af FB |
851 | } else { |
852 | /* shift/register */ | |
853 | rm = (insn) & 0xf; | |
854 | shift = (insn >> 7) & 0x1f; | |
1e8d4eec | 855 | shiftop = (insn >> 5) & 3; |
b26eefb6 | 856 | offset = load_reg(s, rm); |
9a119ff6 | 857 | gen_arm_shift_im(offset, shiftop, shift, 0); |
2c0262af | 858 | if (!(insn & (1 << 23))) |
b0109805 | 859 | tcg_gen_sub_i32(var, var, offset); |
2c0262af | 860 | else |
b0109805 | 861 | tcg_gen_add_i32(var, var, offset); |
b26eefb6 | 862 | dead_tmp(offset); |
2c0262af FB |
863 | } |
864 | } | |
865 | ||
191f9a93 | 866 | static inline void gen_add_datah_offset(DisasContext *s, unsigned int insn, |
b0109805 | 867 | int extra, TCGv var) |
2c0262af FB |
868 | { |
869 | int val, rm; | |
b26eefb6 | 870 | TCGv offset; |
3b46e624 | 871 | |
2c0262af FB |
872 | if (insn & (1 << 22)) { |
873 | /* immediate */ | |
874 | val = (insn & 0xf) | ((insn >> 4) & 0xf0); | |
875 | if (!(insn & (1 << 23))) | |
876 | val = -val; | |
18acad92 | 877 | val += extra; |
537730b9 | 878 | if (val != 0) |
b0109805 | 879 | tcg_gen_addi_i32(var, var, val); |
2c0262af FB |
880 | } else { |
881 | /* register */ | |
191f9a93 | 882 | if (extra) |
b0109805 | 883 | tcg_gen_addi_i32(var, var, extra); |
2c0262af | 884 | rm = (insn) & 0xf; |
b26eefb6 | 885 | offset = load_reg(s, rm); |
2c0262af | 886 | if (!(insn & (1 << 23))) |
b0109805 | 887 | tcg_gen_sub_i32(var, var, offset); |
2c0262af | 888 | else |
b0109805 | 889 | tcg_gen_add_i32(var, var, offset); |
b26eefb6 | 890 | dead_tmp(offset); |
2c0262af FB |
891 | } |
892 | } | |
893 | ||
4373f3ce PB |
894 | #define VFP_OP2(name) \ |
895 | static inline void gen_vfp_##name(int dp) \ | |
896 | { \ | |
897 | if (dp) \ | |
898 | gen_helper_vfp_##name##d(cpu_F0d, cpu_F0d, cpu_F1d, cpu_env); \ | |
899 | else \ | |
900 | gen_helper_vfp_##name##s(cpu_F0s, cpu_F0s, cpu_F1s, cpu_env); \ | |
b7bcbe95 FB |
901 | } |
902 | ||
4373f3ce PB |
903 | VFP_OP2(add) |
904 | VFP_OP2(sub) | |
905 | VFP_OP2(mul) | |
906 | VFP_OP2(div) | |
907 | ||
908 | #undef VFP_OP2 | |
909 | ||
910 | static inline void gen_vfp_abs(int dp) | |
911 | { | |
912 | if (dp) | |
913 | gen_helper_vfp_absd(cpu_F0d, cpu_F0d); | |
914 | else | |
915 | gen_helper_vfp_abss(cpu_F0s, cpu_F0s); | |
916 | } | |
917 | ||
918 | static inline void gen_vfp_neg(int dp) | |
919 | { | |
920 | if (dp) | |
921 | gen_helper_vfp_negd(cpu_F0d, cpu_F0d); | |
922 | else | |
923 | gen_helper_vfp_negs(cpu_F0s, cpu_F0s); | |
924 | } | |
925 | ||
926 | static inline void gen_vfp_sqrt(int dp) | |
927 | { | |
928 | if (dp) | |
929 | gen_helper_vfp_sqrtd(cpu_F0d, cpu_F0d, cpu_env); | |
930 | else | |
931 | gen_helper_vfp_sqrts(cpu_F0s, cpu_F0s, cpu_env); | |
932 | } | |
933 | ||
934 | static inline void gen_vfp_cmp(int dp) | |
935 | { | |
936 | if (dp) | |
937 | gen_helper_vfp_cmpd(cpu_F0d, cpu_F1d, cpu_env); | |
938 | else | |
939 | gen_helper_vfp_cmps(cpu_F0s, cpu_F1s, cpu_env); | |
940 | } | |
941 | ||
942 | static inline void gen_vfp_cmpe(int dp) | |
943 | { | |
944 | if (dp) | |
945 | gen_helper_vfp_cmped(cpu_F0d, cpu_F1d, cpu_env); | |
946 | else | |
947 | gen_helper_vfp_cmpes(cpu_F0s, cpu_F1s, cpu_env); | |
948 | } | |
949 | ||
950 | static inline void gen_vfp_F1_ld0(int dp) | |
951 | { | |
952 | if (dp) | |
5b340b51 | 953 | tcg_gen_movi_i64(cpu_F1d, 0); |
4373f3ce | 954 | else |
5b340b51 | 955 | tcg_gen_movi_i32(cpu_F1s, 0); |
4373f3ce PB |
956 | } |
957 | ||
958 | static inline void gen_vfp_uito(int dp) | |
959 | { | |
960 | if (dp) | |
961 | gen_helper_vfp_uitod(cpu_F0d, cpu_F0s, cpu_env); | |
962 | else | |
963 | gen_helper_vfp_uitos(cpu_F0s, cpu_F0s, cpu_env); | |
964 | } | |
965 | ||
966 | static inline void gen_vfp_sito(int dp) | |
967 | { | |
968 | if (dp) | |
66230e0d | 969 | gen_helper_vfp_sitod(cpu_F0d, cpu_F0s, cpu_env); |
4373f3ce | 970 | else |
66230e0d | 971 | gen_helper_vfp_sitos(cpu_F0s, cpu_F0s, cpu_env); |
4373f3ce PB |
972 | } |
973 | ||
974 | static inline void gen_vfp_toui(int dp) | |
975 | { | |
976 | if (dp) | |
977 | gen_helper_vfp_touid(cpu_F0s, cpu_F0d, cpu_env); | |
978 | else | |
979 | gen_helper_vfp_touis(cpu_F0s, cpu_F0s, cpu_env); | |
980 | } | |
981 | ||
982 | static inline void gen_vfp_touiz(int dp) | |
983 | { | |
984 | if (dp) | |
985 | gen_helper_vfp_touizd(cpu_F0s, cpu_F0d, cpu_env); | |
986 | else | |
987 | gen_helper_vfp_touizs(cpu_F0s, cpu_F0s, cpu_env); | |
988 | } | |
989 | ||
990 | static inline void gen_vfp_tosi(int dp) | |
991 | { | |
992 | if (dp) | |
993 | gen_helper_vfp_tosid(cpu_F0s, cpu_F0d, cpu_env); | |
994 | else | |
995 | gen_helper_vfp_tosis(cpu_F0s, cpu_F0s, cpu_env); | |
996 | } | |
997 | ||
998 | static inline void gen_vfp_tosiz(int dp) | |
9ee6e8bb PB |
999 | { |
1000 | if (dp) | |
4373f3ce | 1001 | gen_helper_vfp_tosizd(cpu_F0s, cpu_F0d, cpu_env); |
9ee6e8bb | 1002 | else |
4373f3ce PB |
1003 | gen_helper_vfp_tosizs(cpu_F0s, cpu_F0s, cpu_env); |
1004 | } | |
1005 | ||
1006 | #define VFP_GEN_FIX(name) \ | |
1007 | static inline void gen_vfp_##name(int dp, int shift) \ | |
1008 | { \ | |
b75263d6 | 1009 | TCGv tmp_shift = tcg_const_i32(shift); \ |
4373f3ce | 1010 | if (dp) \ |
b75263d6 | 1011 | gen_helper_vfp_##name##d(cpu_F0d, cpu_F0d, tmp_shift, cpu_env);\ |
4373f3ce | 1012 | else \ |
b75263d6 JR |
1013 | gen_helper_vfp_##name##s(cpu_F0s, cpu_F0s, tmp_shift, cpu_env);\ |
1014 | tcg_temp_free_i32(tmp_shift); \ | |
9ee6e8bb | 1015 | } |
4373f3ce PB |
1016 | VFP_GEN_FIX(tosh) |
1017 | VFP_GEN_FIX(tosl) | |
1018 | VFP_GEN_FIX(touh) | |
1019 | VFP_GEN_FIX(toul) | |
1020 | VFP_GEN_FIX(shto) | |
1021 | VFP_GEN_FIX(slto) | |
1022 | VFP_GEN_FIX(uhto) | |
1023 | VFP_GEN_FIX(ulto) | |
1024 | #undef VFP_GEN_FIX | |
9ee6e8bb | 1025 | |
312eea9f | 1026 | static inline void gen_vfp_ld(DisasContext *s, int dp, TCGv addr) |
b5ff1b31 FB |
1027 | { |
1028 | if (dp) | |
312eea9f | 1029 | tcg_gen_qemu_ld64(cpu_F0d, addr, IS_USER(s)); |
b5ff1b31 | 1030 | else |
312eea9f | 1031 | tcg_gen_qemu_ld32u(cpu_F0s, addr, IS_USER(s)); |
b5ff1b31 FB |
1032 | } |
1033 | ||
312eea9f | 1034 | static inline void gen_vfp_st(DisasContext *s, int dp, TCGv addr) |
b5ff1b31 FB |
1035 | { |
1036 | if (dp) | |
312eea9f | 1037 | tcg_gen_qemu_st64(cpu_F0d, addr, IS_USER(s)); |
b5ff1b31 | 1038 | else |
312eea9f | 1039 | tcg_gen_qemu_st32(cpu_F0s, addr, IS_USER(s)); |
b5ff1b31 FB |
1040 | } |
1041 | ||
8e96005d FB |
1042 | static inline long |
1043 | vfp_reg_offset (int dp, int reg) | |
1044 | { | |
1045 | if (dp) | |
1046 | return offsetof(CPUARMState, vfp.regs[reg]); | |
1047 | else if (reg & 1) { | |
1048 | return offsetof(CPUARMState, vfp.regs[reg >> 1]) | |
1049 | + offsetof(CPU_DoubleU, l.upper); | |
1050 | } else { | |
1051 | return offsetof(CPUARMState, vfp.regs[reg >> 1]) | |
1052 | + offsetof(CPU_DoubleU, l.lower); | |
1053 | } | |
1054 | } | |
9ee6e8bb PB |
1055 | |
1056 | /* Return the offset of a 32-bit piece of a NEON register. | |
1057 | zero is the least significant end of the register. */ | |
1058 | static inline long | |
1059 | neon_reg_offset (int reg, int n) | |
1060 | { | |
1061 | int sreg; | |
1062 | sreg = reg * 2 + n; | |
1063 | return vfp_reg_offset(0, sreg); | |
1064 | } | |
1065 | ||
8f8e3aa4 PB |
1066 | static TCGv neon_load_reg(int reg, int pass) |
1067 | { | |
1068 | TCGv tmp = new_tmp(); | |
1069 | tcg_gen_ld_i32(tmp, cpu_env, neon_reg_offset(reg, pass)); | |
1070 | return tmp; | |
1071 | } | |
1072 | ||
1073 | static void neon_store_reg(int reg, int pass, TCGv var) | |
1074 | { | |
1075 | tcg_gen_st_i32(var, cpu_env, neon_reg_offset(reg, pass)); | |
1076 | dead_tmp(var); | |
1077 | } | |
1078 | ||
a7812ae4 | 1079 | static inline void neon_load_reg64(TCGv_i64 var, int reg) |
ad69471c PB |
1080 | { |
1081 | tcg_gen_ld_i64(var, cpu_env, vfp_reg_offset(1, reg)); | |
1082 | } | |
1083 | ||
a7812ae4 | 1084 | static inline void neon_store_reg64(TCGv_i64 var, int reg) |
ad69471c PB |
1085 | { |
1086 | tcg_gen_st_i64(var, cpu_env, vfp_reg_offset(1, reg)); | |
1087 | } | |
1088 | ||
4373f3ce PB |
1089 | #define tcg_gen_ld_f32 tcg_gen_ld_i32 |
1090 | #define tcg_gen_ld_f64 tcg_gen_ld_i64 | |
1091 | #define tcg_gen_st_f32 tcg_gen_st_i32 | |
1092 | #define tcg_gen_st_f64 tcg_gen_st_i64 | |
1093 | ||
b7bcbe95 FB |
1094 | static inline void gen_mov_F0_vreg(int dp, int reg) |
1095 | { | |
1096 | if (dp) | |
4373f3ce | 1097 | tcg_gen_ld_f64(cpu_F0d, cpu_env, vfp_reg_offset(dp, reg)); |
b7bcbe95 | 1098 | else |
4373f3ce | 1099 | tcg_gen_ld_f32(cpu_F0s, cpu_env, vfp_reg_offset(dp, reg)); |
b7bcbe95 FB |
1100 | } |
1101 | ||
1102 | static inline void gen_mov_F1_vreg(int dp, int reg) | |
1103 | { | |
1104 | if (dp) | |
4373f3ce | 1105 | tcg_gen_ld_f64(cpu_F1d, cpu_env, vfp_reg_offset(dp, reg)); |
b7bcbe95 | 1106 | else |
4373f3ce | 1107 | tcg_gen_ld_f32(cpu_F1s, cpu_env, vfp_reg_offset(dp, reg)); |
b7bcbe95 FB |
1108 | } |
1109 | ||
1110 | static inline void gen_mov_vreg_F0(int dp, int reg) | |
1111 | { | |
1112 | if (dp) | |
4373f3ce | 1113 | tcg_gen_st_f64(cpu_F0d, cpu_env, vfp_reg_offset(dp, reg)); |
b7bcbe95 | 1114 | else |
4373f3ce | 1115 | tcg_gen_st_f32(cpu_F0s, cpu_env, vfp_reg_offset(dp, reg)); |
b7bcbe95 FB |
1116 | } |
1117 | ||
18c9b560 AZ |
1118 | #define ARM_CP_RW_BIT (1 << 20) |
1119 | ||
a7812ae4 | 1120 | static inline void iwmmxt_load_reg(TCGv_i64 var, int reg) |
e677137d PB |
1121 | { |
1122 | tcg_gen_ld_i64(var, cpu_env, offsetof(CPUState, iwmmxt.regs[reg])); | |
1123 | } | |
1124 | ||
a7812ae4 | 1125 | static inline void iwmmxt_store_reg(TCGv_i64 var, int reg) |
e677137d PB |
1126 | { |
1127 | tcg_gen_st_i64(var, cpu_env, offsetof(CPUState, iwmmxt.regs[reg])); | |
1128 | } | |
1129 | ||
da6b5335 | 1130 | static inline TCGv iwmmxt_load_creg(int reg) |
e677137d | 1131 | { |
da6b5335 FN |
1132 | TCGv var = new_tmp(); |
1133 | tcg_gen_ld_i32(var, cpu_env, offsetof(CPUState, iwmmxt.cregs[reg])); | |
1134 | return var; | |
e677137d PB |
1135 | } |
1136 | ||
da6b5335 | 1137 | static inline void iwmmxt_store_creg(int reg, TCGv var) |
e677137d | 1138 | { |
da6b5335 | 1139 | tcg_gen_st_i32(var, cpu_env, offsetof(CPUState, iwmmxt.cregs[reg])); |
d9968827 | 1140 | dead_tmp(var); |
e677137d PB |
1141 | } |
1142 | ||
1143 | static inline void gen_op_iwmmxt_movq_wRn_M0(int rn) | |
1144 | { | |
1145 | iwmmxt_store_reg(cpu_M0, rn); | |
1146 | } | |
1147 | ||
1148 | static inline void gen_op_iwmmxt_movq_M0_wRn(int rn) | |
1149 | { | |
1150 | iwmmxt_load_reg(cpu_M0, rn); | |
1151 | } | |
1152 | ||
1153 | static inline void gen_op_iwmmxt_orq_M0_wRn(int rn) | |
1154 | { | |
1155 | iwmmxt_load_reg(cpu_V1, rn); | |
1156 | tcg_gen_or_i64(cpu_M0, cpu_M0, cpu_V1); | |
1157 | } | |
1158 | ||
1159 | static inline void gen_op_iwmmxt_andq_M0_wRn(int rn) | |
1160 | { | |
1161 | iwmmxt_load_reg(cpu_V1, rn); | |
1162 | tcg_gen_and_i64(cpu_M0, cpu_M0, cpu_V1); | |
1163 | } | |
1164 | ||
1165 | static inline void gen_op_iwmmxt_xorq_M0_wRn(int rn) | |
1166 | { | |
1167 | iwmmxt_load_reg(cpu_V1, rn); | |
1168 | tcg_gen_xor_i64(cpu_M0, cpu_M0, cpu_V1); | |
1169 | } | |
1170 | ||
1171 | #define IWMMXT_OP(name) \ | |
1172 | static inline void gen_op_iwmmxt_##name##_M0_wRn(int rn) \ | |
1173 | { \ | |
1174 | iwmmxt_load_reg(cpu_V1, rn); \ | |
1175 | gen_helper_iwmmxt_##name(cpu_M0, cpu_M0, cpu_V1); \ | |
1176 | } | |
1177 | ||
1178 | #define IWMMXT_OP_ENV(name) \ | |
1179 | static inline void gen_op_iwmmxt_##name##_M0_wRn(int rn) \ | |
1180 | { \ | |
1181 | iwmmxt_load_reg(cpu_V1, rn); \ | |
1182 | gen_helper_iwmmxt_##name(cpu_M0, cpu_env, cpu_M0, cpu_V1); \ | |
1183 | } | |
1184 | ||
1185 | #define IWMMXT_OP_ENV_SIZE(name) \ | |
1186 | IWMMXT_OP_ENV(name##b) \ | |
1187 | IWMMXT_OP_ENV(name##w) \ | |
1188 | IWMMXT_OP_ENV(name##l) | |
1189 | ||
1190 | #define IWMMXT_OP_ENV1(name) \ | |
1191 | static inline void gen_op_iwmmxt_##name##_M0(void) \ | |
1192 | { \ | |
1193 | gen_helper_iwmmxt_##name(cpu_M0, cpu_env, cpu_M0); \ | |
1194 | } | |
1195 | ||
1196 | IWMMXT_OP(maddsq) | |
1197 | IWMMXT_OP(madduq) | |
1198 | IWMMXT_OP(sadb) | |
1199 | IWMMXT_OP(sadw) | |
1200 | IWMMXT_OP(mulslw) | |
1201 | IWMMXT_OP(mulshw) | |
1202 | IWMMXT_OP(mululw) | |
1203 | IWMMXT_OP(muluhw) | |
1204 | IWMMXT_OP(macsw) | |
1205 | IWMMXT_OP(macuw) | |
1206 | ||
1207 | IWMMXT_OP_ENV_SIZE(unpackl) | |
1208 | IWMMXT_OP_ENV_SIZE(unpackh) | |
1209 | ||
1210 | IWMMXT_OP_ENV1(unpacklub) | |
1211 | IWMMXT_OP_ENV1(unpackluw) | |
1212 | IWMMXT_OP_ENV1(unpacklul) | |
1213 | IWMMXT_OP_ENV1(unpackhub) | |
1214 | IWMMXT_OP_ENV1(unpackhuw) | |
1215 | IWMMXT_OP_ENV1(unpackhul) | |
1216 | IWMMXT_OP_ENV1(unpacklsb) | |
1217 | IWMMXT_OP_ENV1(unpacklsw) | |
1218 | IWMMXT_OP_ENV1(unpacklsl) | |
1219 | IWMMXT_OP_ENV1(unpackhsb) | |
1220 | IWMMXT_OP_ENV1(unpackhsw) | |
1221 | IWMMXT_OP_ENV1(unpackhsl) | |
1222 | ||
1223 | IWMMXT_OP_ENV_SIZE(cmpeq) | |
1224 | IWMMXT_OP_ENV_SIZE(cmpgtu) | |
1225 | IWMMXT_OP_ENV_SIZE(cmpgts) | |
1226 | ||
1227 | IWMMXT_OP_ENV_SIZE(mins) | |
1228 | IWMMXT_OP_ENV_SIZE(minu) | |
1229 | IWMMXT_OP_ENV_SIZE(maxs) | |
1230 | IWMMXT_OP_ENV_SIZE(maxu) | |
1231 | ||
1232 | IWMMXT_OP_ENV_SIZE(subn) | |
1233 | IWMMXT_OP_ENV_SIZE(addn) | |
1234 | IWMMXT_OP_ENV_SIZE(subu) | |
1235 | IWMMXT_OP_ENV_SIZE(addu) | |
1236 | IWMMXT_OP_ENV_SIZE(subs) | |
1237 | IWMMXT_OP_ENV_SIZE(adds) | |
1238 | ||
1239 | IWMMXT_OP_ENV(avgb0) | |
1240 | IWMMXT_OP_ENV(avgb1) | |
1241 | IWMMXT_OP_ENV(avgw0) | |
1242 | IWMMXT_OP_ENV(avgw1) | |
1243 | ||
1244 | IWMMXT_OP(msadb) | |
1245 | ||
1246 | IWMMXT_OP_ENV(packuw) | |
1247 | IWMMXT_OP_ENV(packul) | |
1248 | IWMMXT_OP_ENV(packuq) | |
1249 | IWMMXT_OP_ENV(packsw) | |
1250 | IWMMXT_OP_ENV(packsl) | |
1251 | IWMMXT_OP_ENV(packsq) | |
1252 | ||
e677137d PB |
1253 | static void gen_op_iwmmxt_set_mup(void) |
1254 | { | |
1255 | TCGv tmp; | |
1256 | tmp = load_cpu_field(iwmmxt.cregs[ARM_IWMMXT_wCon]); | |
1257 | tcg_gen_ori_i32(tmp, tmp, 2); | |
1258 | store_cpu_field(tmp, iwmmxt.cregs[ARM_IWMMXT_wCon]); | |
1259 | } | |
1260 | ||
1261 | static void gen_op_iwmmxt_set_cup(void) | |
1262 | { | |
1263 | TCGv tmp; | |
1264 | tmp = load_cpu_field(iwmmxt.cregs[ARM_IWMMXT_wCon]); | |
1265 | tcg_gen_ori_i32(tmp, tmp, 1); | |
1266 | store_cpu_field(tmp, iwmmxt.cregs[ARM_IWMMXT_wCon]); | |
1267 | } | |
1268 | ||
1269 | static void gen_op_iwmmxt_setpsr_nz(void) | |
1270 | { | |
1271 | TCGv tmp = new_tmp(); | |
1272 | gen_helper_iwmmxt_setpsr_nz(tmp, cpu_M0); | |
1273 | store_cpu_field(tmp, iwmmxt.cregs[ARM_IWMMXT_wCASF]); | |
1274 | } | |
1275 | ||
1276 | static inline void gen_op_iwmmxt_addl_M0_wRn(int rn) | |
1277 | { | |
1278 | iwmmxt_load_reg(cpu_V1, rn); | |
86831435 | 1279 | tcg_gen_ext32u_i64(cpu_V1, cpu_V1); |
e677137d PB |
1280 | tcg_gen_add_i64(cpu_M0, cpu_M0, cpu_V1); |
1281 | } | |
1282 | ||
da6b5335 | 1283 | static inline int gen_iwmmxt_address(DisasContext *s, uint32_t insn, TCGv dest) |
18c9b560 AZ |
1284 | { |
1285 | int rd; | |
1286 | uint32_t offset; | |
da6b5335 | 1287 | TCGv tmp; |
18c9b560 AZ |
1288 | |
1289 | rd = (insn >> 16) & 0xf; | |
da6b5335 | 1290 | tmp = load_reg(s, rd); |
18c9b560 AZ |
1291 | |
1292 | offset = (insn & 0xff) << ((insn >> 7) & 2); | |
1293 | if (insn & (1 << 24)) { | |
1294 | /* Pre indexed */ | |
1295 | if (insn & (1 << 23)) | |
da6b5335 | 1296 | tcg_gen_addi_i32(tmp, tmp, offset); |
18c9b560 | 1297 | else |
da6b5335 FN |
1298 | tcg_gen_addi_i32(tmp, tmp, -offset); |
1299 | tcg_gen_mov_i32(dest, tmp); | |
18c9b560 | 1300 | if (insn & (1 << 21)) |
da6b5335 FN |
1301 | store_reg(s, rd, tmp); |
1302 | else | |
1303 | dead_tmp(tmp); | |
18c9b560 AZ |
1304 | } else if (insn & (1 << 21)) { |
1305 | /* Post indexed */ | |
da6b5335 | 1306 | tcg_gen_mov_i32(dest, tmp); |
18c9b560 | 1307 | if (insn & (1 << 23)) |
da6b5335 | 1308 | tcg_gen_addi_i32(tmp, tmp, offset); |
18c9b560 | 1309 | else |
da6b5335 FN |
1310 | tcg_gen_addi_i32(tmp, tmp, -offset); |
1311 | store_reg(s, rd, tmp); | |
18c9b560 AZ |
1312 | } else if (!(insn & (1 << 23))) |
1313 | return 1; | |
1314 | return 0; | |
1315 | } | |
1316 | ||
da6b5335 | 1317 | static inline int gen_iwmmxt_shift(uint32_t insn, uint32_t mask, TCGv dest) |
18c9b560 AZ |
1318 | { |
1319 | int rd = (insn >> 0) & 0xf; | |
da6b5335 | 1320 | TCGv tmp; |
18c9b560 | 1321 | |
da6b5335 FN |
1322 | if (insn & (1 << 8)) { |
1323 | if (rd < ARM_IWMMXT_wCGR0 || rd > ARM_IWMMXT_wCGR3) { | |
18c9b560 | 1324 | return 1; |
da6b5335 FN |
1325 | } else { |
1326 | tmp = iwmmxt_load_creg(rd); | |
1327 | } | |
1328 | } else { | |
1329 | tmp = new_tmp(); | |
1330 | iwmmxt_load_reg(cpu_V0, rd); | |
1331 | tcg_gen_trunc_i64_i32(tmp, cpu_V0); | |
1332 | } | |
1333 | tcg_gen_andi_i32(tmp, tmp, mask); | |
1334 | tcg_gen_mov_i32(dest, tmp); | |
1335 | dead_tmp(tmp); | |
18c9b560 AZ |
1336 | return 0; |
1337 | } | |
1338 | ||
1339 | /* Disassemble an iwMMXt instruction. Returns nonzero if an error occured | |
1340 | (ie. an undefined instruction). */ | |
1341 | static int disas_iwmmxt_insn(CPUState *env, DisasContext *s, uint32_t insn) | |
1342 | { | |
1343 | int rd, wrd; | |
1344 | int rdhi, rdlo, rd0, rd1, i; | |
da6b5335 FN |
1345 | TCGv addr; |
1346 | TCGv tmp, tmp2, tmp3; | |
18c9b560 AZ |
1347 | |
1348 | if ((insn & 0x0e000e00) == 0x0c000000) { | |
1349 | if ((insn & 0x0fe00ff0) == 0x0c400000) { | |
1350 | wrd = insn & 0xf; | |
1351 | rdlo = (insn >> 12) & 0xf; | |
1352 | rdhi = (insn >> 16) & 0xf; | |
1353 | if (insn & ARM_CP_RW_BIT) { /* TMRRC */ | |
da6b5335 FN |
1354 | iwmmxt_load_reg(cpu_V0, wrd); |
1355 | tcg_gen_trunc_i64_i32(cpu_R[rdlo], cpu_V0); | |
1356 | tcg_gen_shri_i64(cpu_V0, cpu_V0, 32); | |
1357 | tcg_gen_trunc_i64_i32(cpu_R[rdhi], cpu_V0); | |
18c9b560 | 1358 | } else { /* TMCRR */ |
da6b5335 FN |
1359 | tcg_gen_concat_i32_i64(cpu_V0, cpu_R[rdlo], cpu_R[rdhi]); |
1360 | iwmmxt_store_reg(cpu_V0, wrd); | |
18c9b560 AZ |
1361 | gen_op_iwmmxt_set_mup(); |
1362 | } | |
1363 | return 0; | |
1364 | } | |
1365 | ||
1366 | wrd = (insn >> 12) & 0xf; | |
da6b5335 FN |
1367 | addr = new_tmp(); |
1368 | if (gen_iwmmxt_address(s, insn, addr)) { | |
1369 | dead_tmp(addr); | |
18c9b560 | 1370 | return 1; |
da6b5335 | 1371 | } |
18c9b560 AZ |
1372 | if (insn & ARM_CP_RW_BIT) { |
1373 | if ((insn >> 28) == 0xf) { /* WLDRW wCx */ | |
da6b5335 FN |
1374 | tmp = new_tmp(); |
1375 | tcg_gen_qemu_ld32u(tmp, addr, IS_USER(s)); | |
1376 | iwmmxt_store_creg(wrd, tmp); | |
18c9b560 | 1377 | } else { |
e677137d PB |
1378 | i = 1; |
1379 | if (insn & (1 << 8)) { | |
1380 | if (insn & (1 << 22)) { /* WLDRD */ | |
da6b5335 | 1381 | tcg_gen_qemu_ld64(cpu_M0, addr, IS_USER(s)); |
e677137d PB |
1382 | i = 0; |
1383 | } else { /* WLDRW wRd */ | |
da6b5335 | 1384 | tmp = gen_ld32(addr, IS_USER(s)); |
e677137d PB |
1385 | } |
1386 | } else { | |
1387 | if (insn & (1 << 22)) { /* WLDRH */ | |
da6b5335 | 1388 | tmp = gen_ld16u(addr, IS_USER(s)); |
e677137d | 1389 | } else { /* WLDRB */ |
da6b5335 | 1390 | tmp = gen_ld8u(addr, IS_USER(s)); |
e677137d PB |
1391 | } |
1392 | } | |
1393 | if (i) { | |
1394 | tcg_gen_extu_i32_i64(cpu_M0, tmp); | |
1395 | dead_tmp(tmp); | |
1396 | } | |
18c9b560 AZ |
1397 | gen_op_iwmmxt_movq_wRn_M0(wrd); |
1398 | } | |
1399 | } else { | |
1400 | if ((insn >> 28) == 0xf) { /* WSTRW wCx */ | |
da6b5335 FN |
1401 | tmp = iwmmxt_load_creg(wrd); |
1402 | gen_st32(tmp, addr, IS_USER(s)); | |
18c9b560 AZ |
1403 | } else { |
1404 | gen_op_iwmmxt_movq_M0_wRn(wrd); | |
e677137d PB |
1405 | tmp = new_tmp(); |
1406 | if (insn & (1 << 8)) { | |
1407 | if (insn & (1 << 22)) { /* WSTRD */ | |
1408 | dead_tmp(tmp); | |
da6b5335 | 1409 | tcg_gen_qemu_st64(cpu_M0, addr, IS_USER(s)); |
e677137d PB |
1410 | } else { /* WSTRW wRd */ |
1411 | tcg_gen_trunc_i64_i32(tmp, cpu_M0); | |
da6b5335 | 1412 | gen_st32(tmp, addr, IS_USER(s)); |
e677137d PB |
1413 | } |
1414 | } else { | |
1415 | if (insn & (1 << 22)) { /* WSTRH */ | |
1416 | tcg_gen_trunc_i64_i32(tmp, cpu_M0); | |
da6b5335 | 1417 | gen_st16(tmp, addr, IS_USER(s)); |
e677137d PB |
1418 | } else { /* WSTRB */ |
1419 | tcg_gen_trunc_i64_i32(tmp, cpu_M0); | |
da6b5335 | 1420 | gen_st8(tmp, addr, IS_USER(s)); |
e677137d PB |
1421 | } |
1422 | } | |
18c9b560 AZ |
1423 | } |
1424 | } | |
d9968827 | 1425 | dead_tmp(addr); |
18c9b560 AZ |
1426 | return 0; |
1427 | } | |
1428 | ||
1429 | if ((insn & 0x0f000000) != 0x0e000000) | |
1430 | return 1; | |
1431 | ||
1432 | switch (((insn >> 12) & 0xf00) | ((insn >> 4) & 0xff)) { | |
1433 | case 0x000: /* WOR */ | |
1434 | wrd = (insn >> 12) & 0xf; | |
1435 | rd0 = (insn >> 0) & 0xf; | |
1436 | rd1 = (insn >> 16) & 0xf; | |
1437 | gen_op_iwmmxt_movq_M0_wRn(rd0); | |
1438 | gen_op_iwmmxt_orq_M0_wRn(rd1); | |
1439 | gen_op_iwmmxt_setpsr_nz(); | |
1440 | gen_op_iwmmxt_movq_wRn_M0(wrd); | |
1441 | gen_op_iwmmxt_set_mup(); | |
1442 | gen_op_iwmmxt_set_cup(); | |
1443 | break; | |
1444 | case 0x011: /* TMCR */ | |
1445 | if (insn & 0xf) | |
1446 | return 1; | |
1447 | rd = (insn >> 12) & 0xf; | |
1448 | wrd = (insn >> 16) & 0xf; | |
1449 | switch (wrd) { | |
1450 | case ARM_IWMMXT_wCID: | |
1451 | case ARM_IWMMXT_wCASF: | |
1452 | break; | |
1453 | case ARM_IWMMXT_wCon: | |
1454 | gen_op_iwmmxt_set_cup(); | |
1455 | /* Fall through. */ | |
1456 | case ARM_IWMMXT_wCSSF: | |
da6b5335 FN |
1457 | tmp = iwmmxt_load_creg(wrd); |
1458 | tmp2 = load_reg(s, rd); | |
f669df27 | 1459 | tcg_gen_andc_i32(tmp, tmp, tmp2); |
da6b5335 FN |
1460 | dead_tmp(tmp2); |
1461 | iwmmxt_store_creg(wrd, tmp); | |
18c9b560 AZ |
1462 | break; |
1463 | case ARM_IWMMXT_wCGR0: | |
1464 | case ARM_IWMMXT_wCGR1: | |
1465 | case ARM_IWMMXT_wCGR2: | |
1466 | case ARM_IWMMXT_wCGR3: | |
1467 | gen_op_iwmmxt_set_cup(); | |
da6b5335 FN |
1468 | tmp = load_reg(s, rd); |
1469 | iwmmxt_store_creg(wrd, tmp); | |
18c9b560 AZ |
1470 | break; |
1471 | default: | |
1472 | return 1; | |
1473 | } | |
1474 | break; | |
1475 | case 0x100: /* WXOR */ | |
1476 | wrd = (insn >> 12) & 0xf; | |
1477 | rd0 = (insn >> 0) & 0xf; | |
1478 | rd1 = (insn >> 16) & 0xf; | |
1479 | gen_op_iwmmxt_movq_M0_wRn(rd0); | |
1480 | gen_op_iwmmxt_xorq_M0_wRn(rd1); | |
1481 | gen_op_iwmmxt_setpsr_nz(); | |
1482 | gen_op_iwmmxt_movq_wRn_M0(wrd); | |
1483 | gen_op_iwmmxt_set_mup(); | |
1484 | gen_op_iwmmxt_set_cup(); | |
1485 | break; | |
1486 | case 0x111: /* TMRC */ | |
1487 | if (insn & 0xf) | |
1488 | return 1; | |
1489 | rd = (insn >> 12) & 0xf; | |
1490 | wrd = (insn >> 16) & 0xf; | |
da6b5335 FN |
1491 | tmp = iwmmxt_load_creg(wrd); |
1492 | store_reg(s, rd, tmp); | |
18c9b560 AZ |
1493 | break; |
1494 | case 0x300: /* WANDN */ | |
1495 | wrd = (insn >> 12) & 0xf; | |
1496 | rd0 = (insn >> 0) & 0xf; | |
1497 | rd1 = (insn >> 16) & 0xf; | |
1498 | gen_op_iwmmxt_movq_M0_wRn(rd0); | |
e677137d | 1499 | tcg_gen_neg_i64(cpu_M0, cpu_M0); |
18c9b560 AZ |
1500 | gen_op_iwmmxt_andq_M0_wRn(rd1); |
1501 | gen_op_iwmmxt_setpsr_nz(); | |
1502 | gen_op_iwmmxt_movq_wRn_M0(wrd); | |
1503 | gen_op_iwmmxt_set_mup(); | |
1504 | gen_op_iwmmxt_set_cup(); | |
1505 | break; | |
1506 | case 0x200: /* WAND */ | |
1507 | wrd = (insn >> 12) & 0xf; | |
1508 | rd0 = (insn >> 0) & 0xf; | |
1509 | rd1 = (insn >> 16) & 0xf; | |
1510 | gen_op_iwmmxt_movq_M0_wRn(rd0); | |
1511 | gen_op_iwmmxt_andq_M0_wRn(rd1); | |
1512 | gen_op_iwmmxt_setpsr_nz(); | |
1513 | gen_op_iwmmxt_movq_wRn_M0(wrd); | |
1514 | gen_op_iwmmxt_set_mup(); | |
1515 | gen_op_iwmmxt_set_cup(); | |
1516 | break; | |
1517 | case 0x810: case 0xa10: /* WMADD */ | |
1518 | wrd = (insn >> 12) & 0xf; | |
1519 | rd0 = (insn >> 0) & 0xf; | |
1520 | rd1 = (insn >> 16) & 0xf; | |
1521 | gen_op_iwmmxt_movq_M0_wRn(rd0); | |
1522 | if (insn & (1 << 21)) | |
1523 | gen_op_iwmmxt_maddsq_M0_wRn(rd1); | |
1524 | else | |
1525 | gen_op_iwmmxt_madduq_M0_wRn(rd1); | |
1526 | gen_op_iwmmxt_movq_wRn_M0(wrd); | |
1527 | gen_op_iwmmxt_set_mup(); | |
1528 | break; | |
1529 | case 0x10e: case 0x50e: case 0x90e: case 0xd0e: /* WUNPCKIL */ | |
1530 | wrd = (insn >> 12) & 0xf; | |
1531 | rd0 = (insn >> 16) & 0xf; | |
1532 | rd1 = (insn >> 0) & 0xf; | |
1533 | gen_op_iwmmxt_movq_M0_wRn(rd0); | |
1534 | switch ((insn >> 22) & 3) { | |
1535 | case 0: | |
1536 | gen_op_iwmmxt_unpacklb_M0_wRn(rd1); | |
1537 | break; | |
1538 | case 1: | |
1539 | gen_op_iwmmxt_unpacklw_M0_wRn(rd1); | |
1540 | break; | |
1541 | case 2: | |
1542 | gen_op_iwmmxt_unpackll_M0_wRn(rd1); | |
1543 | break; | |
1544 | case 3: | |
1545 | return 1; | |
1546 | } | |
1547 | gen_op_iwmmxt_movq_wRn_M0(wrd); | |
1548 | gen_op_iwmmxt_set_mup(); | |
1549 | gen_op_iwmmxt_set_cup(); | |
1550 | break; | |
1551 | case 0x10c: case 0x50c: case 0x90c: case 0xd0c: /* WUNPCKIH */ | |
1552 | wrd = (insn >> 12) & 0xf; | |
1553 | rd0 = (insn >> 16) & 0xf; | |
1554 | rd1 = (insn >> 0) & 0xf; | |
1555 | gen_op_iwmmxt_movq_M0_wRn(rd0); | |
1556 | switch ((insn >> 22) & 3) { | |
1557 | case 0: | |
1558 | gen_op_iwmmxt_unpackhb_M0_wRn(rd1); | |
1559 | break; | |
1560 | case 1: | |
1561 | gen_op_iwmmxt_unpackhw_M0_wRn(rd1); | |
1562 | break; | |
1563 | case 2: | |
1564 | gen_op_iwmmxt_unpackhl_M0_wRn(rd1); | |
1565 | break; | |
1566 | case 3: | |
1567 | return 1; | |
1568 | } | |
1569 | gen_op_iwmmxt_movq_wRn_M0(wrd); | |
1570 | gen_op_iwmmxt_set_mup(); | |
1571 | gen_op_iwmmxt_set_cup(); | |
1572 | break; | |
1573 | case 0x012: case 0x112: case 0x412: case 0x512: /* WSAD */ | |
1574 | wrd = (insn >> 12) & 0xf; | |
1575 | rd0 = (insn >> 16) & 0xf; | |
1576 | rd1 = (insn >> 0) & 0xf; | |
1577 | gen_op_iwmmxt_movq_M0_wRn(rd0); | |
1578 | if (insn & (1 << 22)) | |
1579 | gen_op_iwmmxt_sadw_M0_wRn(rd1); | |
1580 | else | |
1581 | gen_op_iwmmxt_sadb_M0_wRn(rd1); | |
1582 | if (!(insn & (1 << 20))) | |
1583 | gen_op_iwmmxt_addl_M0_wRn(wrd); | |
1584 | gen_op_iwmmxt_movq_wRn_M0(wrd); | |
1585 | gen_op_iwmmxt_set_mup(); | |
1586 | break; | |
1587 | case 0x010: case 0x110: case 0x210: case 0x310: /* WMUL */ | |
1588 | wrd = (insn >> 12) & 0xf; | |
1589 | rd0 = (insn >> 16) & 0xf; | |
1590 | rd1 = (insn >> 0) & 0xf; | |
1591 | gen_op_iwmmxt_movq_M0_wRn(rd0); | |
e677137d PB |
1592 | if (insn & (1 << 21)) { |
1593 | if (insn & (1 << 20)) | |
1594 | gen_op_iwmmxt_mulshw_M0_wRn(rd1); | |
1595 | else | |
1596 | gen_op_iwmmxt_mulslw_M0_wRn(rd1); | |
1597 | } else { | |
1598 | if (insn & (1 << 20)) | |
1599 | gen_op_iwmmxt_muluhw_M0_wRn(rd1); | |
1600 | else | |
1601 | gen_op_iwmmxt_mululw_M0_wRn(rd1); | |
1602 | } | |
18c9b560 AZ |
1603 | gen_op_iwmmxt_movq_wRn_M0(wrd); |
1604 | gen_op_iwmmxt_set_mup(); | |
1605 | break; | |
1606 | case 0x410: case 0x510: case 0x610: case 0x710: /* WMAC */ | |
1607 | wrd = (insn >> 12) & 0xf; | |
1608 | rd0 = (insn >> 16) & 0xf; | |
1609 | rd1 = (insn >> 0) & 0xf; | |
1610 | gen_op_iwmmxt_movq_M0_wRn(rd0); | |
1611 | if (insn & (1 << 21)) | |
1612 | gen_op_iwmmxt_macsw_M0_wRn(rd1); | |
1613 | else | |
1614 | gen_op_iwmmxt_macuw_M0_wRn(rd1); | |
1615 | if (!(insn & (1 << 20))) { | |
e677137d PB |
1616 | iwmmxt_load_reg(cpu_V1, wrd); |
1617 | tcg_gen_add_i64(cpu_M0, cpu_M0, cpu_V1); | |
18c9b560 AZ |
1618 | } |
1619 | gen_op_iwmmxt_movq_wRn_M0(wrd); | |
1620 | gen_op_iwmmxt_set_mup(); | |
1621 | break; | |
1622 | case 0x006: case 0x406: case 0x806: case 0xc06: /* WCMPEQ */ | |
1623 | wrd = (insn >> 12) & 0xf; | |
1624 | rd0 = (insn >> 16) & 0xf; | |
1625 | rd1 = (insn >> 0) & 0xf; | |
1626 | gen_op_iwmmxt_movq_M0_wRn(rd0); | |
1627 | switch ((insn >> 22) & 3) { | |
1628 | case 0: | |
1629 | gen_op_iwmmxt_cmpeqb_M0_wRn(rd1); | |
1630 | break; | |
1631 | case 1: | |
1632 | gen_op_iwmmxt_cmpeqw_M0_wRn(rd1); | |
1633 | break; | |
1634 | case 2: | |
1635 | gen_op_iwmmxt_cmpeql_M0_wRn(rd1); | |
1636 | break; | |
1637 | case 3: | |
1638 | return 1; | |
1639 | } | |
1640 | gen_op_iwmmxt_movq_wRn_M0(wrd); | |
1641 | gen_op_iwmmxt_set_mup(); | |
1642 | gen_op_iwmmxt_set_cup(); | |
1643 | break; | |
1644 | case 0x800: case 0x900: case 0xc00: case 0xd00: /* WAVG2 */ | |
1645 | wrd = (insn >> 12) & 0xf; | |
1646 | rd0 = (insn >> 16) & 0xf; | |
1647 | rd1 = (insn >> 0) & 0xf; | |
1648 | gen_op_iwmmxt_movq_M0_wRn(rd0); | |
e677137d PB |
1649 | if (insn & (1 << 22)) { |
1650 | if (insn & (1 << 20)) | |
1651 | gen_op_iwmmxt_avgw1_M0_wRn(rd1); | |
1652 | else | |
1653 | gen_op_iwmmxt_avgw0_M0_wRn(rd1); | |
1654 | } else { | |
1655 | if (insn & (1 << 20)) | |
1656 | gen_op_iwmmxt_avgb1_M0_wRn(rd1); | |
1657 | else | |
1658 | gen_op_iwmmxt_avgb0_M0_wRn(rd1); | |
1659 | } | |
18c9b560 AZ |
1660 | gen_op_iwmmxt_movq_wRn_M0(wrd); |
1661 | gen_op_iwmmxt_set_mup(); | |
1662 | gen_op_iwmmxt_set_cup(); | |
1663 | break; | |
1664 | case 0x802: case 0x902: case 0xa02: case 0xb02: /* WALIGNR */ | |
1665 | wrd = (insn >> 12) & 0xf; | |
1666 | rd0 = (insn >> 16) & 0xf; | |
1667 | rd1 = (insn >> 0) & 0xf; | |
1668 | gen_op_iwmmxt_movq_M0_wRn(rd0); | |
da6b5335 FN |
1669 | tmp = iwmmxt_load_creg(ARM_IWMMXT_wCGR0 + ((insn >> 20) & 3)); |
1670 | tcg_gen_andi_i32(tmp, tmp, 7); | |
1671 | iwmmxt_load_reg(cpu_V1, rd1); | |
1672 | gen_helper_iwmmxt_align(cpu_M0, cpu_M0, cpu_V1, tmp); | |
1673 | dead_tmp(tmp); | |
18c9b560 AZ |
1674 | gen_op_iwmmxt_movq_wRn_M0(wrd); |
1675 | gen_op_iwmmxt_set_mup(); | |
1676 | break; | |
1677 | case 0x601: case 0x605: case 0x609: case 0x60d: /* TINSR */ | |
da6b5335 FN |
1678 | if (((insn >> 6) & 3) == 3) |
1679 | return 1; | |
18c9b560 AZ |
1680 | rd = (insn >> 12) & 0xf; |
1681 | wrd = (insn >> 16) & 0xf; | |
da6b5335 | 1682 | tmp = load_reg(s, rd); |
18c9b560 AZ |
1683 | gen_op_iwmmxt_movq_M0_wRn(wrd); |
1684 | switch ((insn >> 6) & 3) { | |
1685 | case 0: | |
da6b5335 FN |
1686 | tmp2 = tcg_const_i32(0xff); |
1687 | tmp3 = tcg_const_i32((insn & 7) << 3); | |
18c9b560 AZ |
1688 | break; |
1689 | case 1: | |
da6b5335 FN |
1690 | tmp2 = tcg_const_i32(0xffff); |
1691 | tmp3 = tcg_const_i32((insn & 3) << 4); | |
18c9b560 AZ |
1692 | break; |
1693 | case 2: | |
da6b5335 FN |
1694 | tmp2 = tcg_const_i32(0xffffffff); |
1695 | tmp3 = tcg_const_i32((insn & 1) << 5); | |
18c9b560 | 1696 | break; |
da6b5335 FN |
1697 | default: |
1698 | TCGV_UNUSED(tmp2); | |
1699 | TCGV_UNUSED(tmp3); | |
18c9b560 | 1700 | } |
da6b5335 FN |
1701 | gen_helper_iwmmxt_insr(cpu_M0, cpu_M0, tmp, tmp2, tmp3); |
1702 | tcg_temp_free(tmp3); | |
1703 | tcg_temp_free(tmp2); | |
1704 | dead_tmp(tmp); | |
18c9b560 AZ |
1705 | gen_op_iwmmxt_movq_wRn_M0(wrd); |
1706 | gen_op_iwmmxt_set_mup(); | |
1707 | break; | |
1708 | case 0x107: case 0x507: case 0x907: case 0xd07: /* TEXTRM */ | |
1709 | rd = (insn >> 12) & 0xf; | |
1710 | wrd = (insn >> 16) & 0xf; | |
da6b5335 | 1711 | if (rd == 15 || ((insn >> 22) & 3) == 3) |
18c9b560 AZ |
1712 | return 1; |
1713 | gen_op_iwmmxt_movq_M0_wRn(wrd); | |
da6b5335 | 1714 | tmp = new_tmp(); |
18c9b560 AZ |
1715 | switch ((insn >> 22) & 3) { |
1716 | case 0: | |
da6b5335 FN |
1717 | tcg_gen_shri_i64(cpu_M0, cpu_M0, (insn & 7) << 3); |
1718 | tcg_gen_trunc_i64_i32(tmp, cpu_M0); | |
1719 | if (insn & 8) { | |
1720 | tcg_gen_ext8s_i32(tmp, tmp); | |
1721 | } else { | |
1722 | tcg_gen_andi_i32(tmp, tmp, 0xff); | |
18c9b560 AZ |
1723 | } |
1724 | break; | |
1725 | case 1: | |
da6b5335 FN |
1726 | tcg_gen_shri_i64(cpu_M0, cpu_M0, (insn & 3) << 4); |
1727 | tcg_gen_trunc_i64_i32(tmp, cpu_M0); | |
1728 | if (insn & 8) { | |
1729 | tcg_gen_ext16s_i32(tmp, tmp); | |
1730 | } else { | |
1731 | tcg_gen_andi_i32(tmp, tmp, 0xffff); | |
18c9b560 AZ |
1732 | } |
1733 | break; | |
1734 | case 2: | |
da6b5335 FN |
1735 | tcg_gen_shri_i64(cpu_M0, cpu_M0, (insn & 1) << 5); |
1736 | tcg_gen_trunc_i64_i32(tmp, cpu_M0); | |
18c9b560 | 1737 | break; |
18c9b560 | 1738 | } |
da6b5335 | 1739 | store_reg(s, rd, tmp); |
18c9b560 AZ |
1740 | break; |
1741 | case 0x117: case 0x517: case 0x917: case 0xd17: /* TEXTRC */ | |
da6b5335 | 1742 | if ((insn & 0x000ff008) != 0x0003f000 || ((insn >> 22) & 3) == 3) |
18c9b560 | 1743 | return 1; |
da6b5335 | 1744 | tmp = iwmmxt_load_creg(ARM_IWMMXT_wCASF); |
18c9b560 AZ |
1745 | switch ((insn >> 22) & 3) { |
1746 | case 0: | |
da6b5335 | 1747 | tcg_gen_shri_i32(tmp, tmp, ((insn & 7) << 2) + 0); |
18c9b560 AZ |
1748 | break; |
1749 | case 1: | |
da6b5335 | 1750 | tcg_gen_shri_i32(tmp, tmp, ((insn & 3) << 3) + 4); |
18c9b560 AZ |
1751 | break; |
1752 | case 2: | |
da6b5335 | 1753 | tcg_gen_shri_i32(tmp, tmp, ((insn & 1) << 4) + 12); |
18c9b560 | 1754 | break; |
18c9b560 | 1755 | } |
da6b5335 FN |
1756 | tcg_gen_shli_i32(tmp, tmp, 28); |
1757 | gen_set_nzcv(tmp); | |
1758 | dead_tmp(tmp); | |
18c9b560 AZ |
1759 | break; |
1760 | case 0x401: case 0x405: case 0x409: case 0x40d: /* TBCST */ | |
da6b5335 FN |
1761 | if (((insn >> 6) & 3) == 3) |
1762 | return 1; | |
18c9b560 AZ |
1763 | rd = (insn >> 12) & 0xf; |
1764 | wrd = (insn >> 16) & 0xf; | |
da6b5335 | 1765 | tmp = load_reg(s, rd); |
18c9b560 AZ |
1766 | switch ((insn >> 6) & 3) { |
1767 | case 0: | |
da6b5335 | 1768 | gen_helper_iwmmxt_bcstb(cpu_M0, tmp); |
18c9b560 AZ |
1769 | break; |
1770 | case 1: | |
da6b5335 | 1771 | gen_helper_iwmmxt_bcstw(cpu_M0, tmp); |
18c9b560 AZ |
1772 | break; |
1773 | case 2: | |
da6b5335 | 1774 | gen_helper_iwmmxt_bcstl(cpu_M0, tmp); |
18c9b560 | 1775 | break; |
18c9b560 | 1776 | } |
da6b5335 | 1777 | dead_tmp(tmp); |
18c9b560 AZ |
1778 | gen_op_iwmmxt_movq_wRn_M0(wrd); |
1779 | gen_op_iwmmxt_set_mup(); | |
1780 | break; | |
1781 | case 0x113: case 0x513: case 0x913: case 0xd13: /* TANDC */ | |
da6b5335 | 1782 | if ((insn & 0x000ff00f) != 0x0003f000 || ((insn >> 22) & 3) == 3) |
18c9b560 | 1783 | return 1; |
da6b5335 FN |
1784 | tmp = iwmmxt_load_creg(ARM_IWMMXT_wCASF); |
1785 | tmp2 = new_tmp(); | |
1786 | tcg_gen_mov_i32(tmp2, tmp); | |
18c9b560 AZ |
1787 | switch ((insn >> 22) & 3) { |
1788 | case 0: | |
1789 | for (i = 0; i < 7; i ++) { | |
da6b5335 FN |
1790 | tcg_gen_shli_i32(tmp2, tmp2, 4); |
1791 | tcg_gen_and_i32(tmp, tmp, tmp2); | |
18c9b560 AZ |
1792 | } |
1793 | break; | |
1794 | case 1: | |
1795 | for (i = 0; i < 3; i ++) { | |
da6b5335 FN |
1796 | tcg_gen_shli_i32(tmp2, tmp2, 8); |
1797 | tcg_gen_and_i32(tmp, tmp, tmp2); | |
18c9b560 AZ |
1798 | } |
1799 | break; | |
1800 | case 2: | |
da6b5335 FN |
1801 | tcg_gen_shli_i32(tmp2, tmp2, 16); |
1802 | tcg_gen_and_i32(tmp, tmp, tmp2); | |
18c9b560 | 1803 | break; |
18c9b560 | 1804 | } |
da6b5335 FN |
1805 | gen_set_nzcv(tmp); |
1806 | dead_tmp(tmp2); | |
1807 | dead_tmp(tmp); | |
18c9b560 AZ |
1808 | break; |
1809 | case 0x01c: case 0x41c: case 0x81c: case 0xc1c: /* WACC */ | |
1810 | wrd = (insn >> 12) & 0xf; | |
1811 | rd0 = (insn >> 16) & 0xf; | |
1812 | gen_op_iwmmxt_movq_M0_wRn(rd0); | |
1813 | switch ((insn >> 22) & 3) { | |
1814 | case 0: | |
e677137d | 1815 | gen_helper_iwmmxt_addcb(cpu_M0, cpu_M0); |
18c9b560 AZ |
1816 | break; |
1817 | case 1: | |
e677137d | 1818 | gen_helper_iwmmxt_addcw(cpu_M0, cpu_M0); |
18c9b560 AZ |
1819 | break; |
1820 | case 2: | |
e677137d | 1821 | gen_helper_iwmmxt_addcl(cpu_M0, cpu_M0); |
18c9b560 AZ |
1822 | break; |
1823 | case 3: | |
1824 | return 1; | |
1825 | } | |
1826 | gen_op_iwmmxt_movq_wRn_M0(wrd); | |
1827 | gen_op_iwmmxt_set_mup(); | |
1828 | break; | |
1829 | case 0x115: case 0x515: case 0x915: case 0xd15: /* TORC */ | |
da6b5335 | 1830 | if ((insn & 0x000ff00f) != 0x0003f000 || ((insn >> 22) & 3) == 3) |
18c9b560 | 1831 | return 1; |
da6b5335 FN |
1832 | tmp = iwmmxt_load_creg(ARM_IWMMXT_wCASF); |
1833 | tmp2 = new_tmp(); | |
1834 | tcg_gen_mov_i32(tmp2, tmp); | |
18c9b560 AZ |
1835 | switch ((insn >> 22) & 3) { |
1836 | case 0: | |
1837 | for (i = 0; i < 7; i ++) { | |
da6b5335 FN |
1838 | tcg_gen_shli_i32(tmp2, tmp2, 4); |
1839 | tcg_gen_or_i32(tmp, tmp, tmp2); | |
18c9b560 AZ |
1840 | } |
1841 | break; | |
1842 | case 1: | |
1843 | for (i = 0; i < 3; i ++) { | |
da6b5335 FN |
1844 | tcg_gen_shli_i32(tmp2, tmp2, 8); |
1845 | tcg_gen_or_i32(tmp, tmp, tmp2); | |
18c9b560 AZ |
1846 | } |
1847 | break; | |
1848 | case 2: | |
da6b5335 FN |
1849 | tcg_gen_shli_i32(tmp2, tmp2, 16); |
1850 | tcg_gen_or_i32(tmp, tmp, tmp2); | |
18c9b560 | 1851 | break; |
18c9b560 | 1852 | } |
da6b5335 FN |
1853 | gen_set_nzcv(tmp); |
1854 | dead_tmp(tmp2); | |
1855 | dead_tmp(tmp); | |
18c9b560 AZ |
1856 | break; |
1857 | case 0x103: case 0x503: case 0x903: case 0xd03: /* TMOVMSK */ | |
1858 | rd = (insn >> 12) & 0xf; | |
1859 | rd0 = (insn >> 16) & 0xf; | |
da6b5335 | 1860 | if ((insn & 0xf) != 0 || ((insn >> 22) & 3) == 3) |
18c9b560 AZ |
1861 | return 1; |
1862 | gen_op_iwmmxt_movq_M0_wRn(rd0); | |
da6b5335 | 1863 | tmp = new_tmp(); |
18c9b560 AZ |
1864 | switch ((insn >> 22) & 3) { |
1865 | case 0: | |
da6b5335 | 1866 | gen_helper_iwmmxt_msbb(tmp, cpu_M0); |
18c9b560 AZ |
1867 | break; |
1868 | case 1: | |
da6b5335 | 1869 | gen_helper_iwmmxt_msbw(tmp, cpu_M0); |
18c9b560 AZ |
1870 | break; |
1871 | case 2: | |
da6b5335 | 1872 | gen_helper_iwmmxt_msbl(tmp, cpu_M0); |
18c9b560 | 1873 | break; |
18c9b560 | 1874 | } |
da6b5335 | 1875 | store_reg(s, rd, tmp); |
18c9b560 AZ |
1876 | break; |
1877 | case 0x106: case 0x306: case 0x506: case 0x706: /* WCMPGT */ | |
1878 | case 0x906: case 0xb06: case 0xd06: case 0xf06: | |
1879 | wrd = (insn >> 12) & 0xf; | |
1880 | rd0 = (insn >> 16) & 0xf; | |
1881 | rd1 = (insn >> 0) & 0xf; | |
1882 | gen_op_iwmmxt_movq_M0_wRn(rd0); | |
1883 | switch ((insn >> 22) & 3) { | |
1884 | case 0: | |
1885 | if (insn & (1 << 21)) | |
1886 | gen_op_iwmmxt_cmpgtsb_M0_wRn(rd1); | |
1887 | else | |
1888 | gen_op_iwmmxt_cmpgtub_M0_wRn(rd1); | |
1889 | break; | |
1890 | case 1: | |
1891 | if (insn & (1 << 21)) | |
1892 | gen_op_iwmmxt_cmpgtsw_M0_wRn(rd1); | |
1893 | else | |
1894 | gen_op_iwmmxt_cmpgtuw_M0_wRn(rd1); | |
1895 | break; | |
1896 | case 2: | |
1897 | if (insn & (1 << 21)) | |
1898 | gen_op_iwmmxt_cmpgtsl_M0_wRn(rd1); | |
1899 | else | |
1900 | gen_op_iwmmxt_cmpgtul_M0_wRn(rd1); | |
1901 | break; | |
1902 | case 3: | |
1903 | return 1; | |
1904 | } | |
1905 | gen_op_iwmmxt_movq_wRn_M0(wrd); | |
1906 | gen_op_iwmmxt_set_mup(); | |
1907 | gen_op_iwmmxt_set_cup(); | |
1908 | break; | |
1909 | case 0x00e: case 0x20e: case 0x40e: case 0x60e: /* WUNPCKEL */ | |
1910 | case 0x80e: case 0xa0e: case 0xc0e: case 0xe0e: | |
1911 | wrd = (insn >> 12) & 0xf; | |
1912 | rd0 = (insn >> 16) & 0xf; | |
1913 | gen_op_iwmmxt_movq_M0_wRn(rd0); | |
1914 | switch ((insn >> 22) & 3) { | |
1915 | case 0: | |
1916 | if (insn & (1 << 21)) | |
1917 | gen_op_iwmmxt_unpacklsb_M0(); | |
1918 | else | |
1919 | gen_op_iwmmxt_unpacklub_M0(); | |
1920 | break; | |
1921 | case 1: | |
1922 | if (insn & (1 << 21)) | |
1923 | gen_op_iwmmxt_unpacklsw_M0(); | |
1924 | else | |
1925 | gen_op_iwmmxt_unpackluw_M0(); | |
1926 | break; | |
1927 | case 2: | |
1928 | if (insn & (1 << 21)) | |
1929 | gen_op_iwmmxt_unpacklsl_M0(); | |
1930 | else | |
1931 | gen_op_iwmmxt_unpacklul_M0(); | |
1932 | break; | |
1933 | case 3: | |
1934 | return 1; | |
1935 | } | |
1936 | gen_op_iwmmxt_movq_wRn_M0(wrd); | |
1937 | gen_op_iwmmxt_set_mup(); | |
1938 | gen_op_iwmmxt_set_cup(); | |
1939 | break; | |
1940 | case 0x00c: case 0x20c: case 0x40c: case 0x60c: /* WUNPCKEH */ | |
1941 | case 0x80c: case 0xa0c: case 0xc0c: case 0xe0c: | |
1942 | wrd = (insn >> 12) & 0xf; | |
1943 | rd0 = (insn >> 16) & 0xf; | |
1944 | gen_op_iwmmxt_movq_M0_wRn(rd0); | |
1945 | switch ((insn >> 22) & 3) { | |
1946 | case 0: | |
1947 | if (insn & (1 << 21)) | |
1948 | gen_op_iwmmxt_unpackhsb_M0(); | |
1949 | else | |
1950 | gen_op_iwmmxt_unpackhub_M0(); | |
1951 | break; | |
1952 | case 1: | |
1953 | if (insn & (1 << 21)) | |
1954 | gen_op_iwmmxt_unpackhsw_M0(); | |
1955 | else | |
1956 | gen_op_iwmmxt_unpackhuw_M0(); | |
1957 | break; | |
1958 | case 2: | |
1959 | if (insn & (1 << 21)) | |
1960 | gen_op_iwmmxt_unpackhsl_M0(); | |
1961 | else | |
1962 | gen_op_iwmmxt_unpackhul_M0(); | |
1963 | break; | |
1964 | case 3: | |
1965 | return 1; | |
1966 | } | |
1967 | gen_op_iwmmxt_movq_wRn_M0(wrd); | |
1968 | gen_op_iwmmxt_set_mup(); | |
1969 | gen_op_iwmmxt_set_cup(); | |
1970 | break; | |
1971 | case 0x204: case 0x604: case 0xa04: case 0xe04: /* WSRL */ | |
1972 | case 0x214: case 0x614: case 0xa14: case 0xe14: | |
da6b5335 FN |
1973 | if (((insn >> 22) & 3) == 0) |
1974 | return 1; | |
18c9b560 AZ |
1975 | wrd = (insn >> 12) & 0xf; |
1976 | rd0 = (insn >> 16) & 0xf; | |
1977 | gen_op_iwmmxt_movq_M0_wRn(rd0); | |
da6b5335 FN |
1978 | tmp = new_tmp(); |
1979 | if (gen_iwmmxt_shift(insn, 0xff, tmp)) { | |
1980 | dead_tmp(tmp); | |
18c9b560 | 1981 | return 1; |
da6b5335 | 1982 | } |
18c9b560 | 1983 | switch ((insn >> 22) & 3) { |
18c9b560 | 1984 | case 1: |
da6b5335 | 1985 | gen_helper_iwmmxt_srlw(cpu_M0, cpu_env, cpu_M0, tmp); |
18c9b560 AZ |
1986 | break; |
1987 | case 2: | |
da6b5335 | 1988 | gen_helper_iwmmxt_srll(cpu_M0, cpu_env, cpu_M0, tmp); |
18c9b560 AZ |
1989 | break; |
1990 | case 3: | |
da6b5335 | 1991 | gen_helper_iwmmxt_srlq(cpu_M0, cpu_env, cpu_M0, tmp); |
18c9b560 AZ |
1992 | break; |
1993 | } | |
da6b5335 | 1994 | dead_tmp(tmp); |
18c9b560 AZ |
1995 | gen_op_iwmmxt_movq_wRn_M0(wrd); |
1996 | gen_op_iwmmxt_set_mup(); | |
1997 | gen_op_iwmmxt_set_cup(); | |
1998 | break; | |
1999 | case 0x004: case 0x404: case 0x804: case 0xc04: /* WSRA */ | |
2000 | case 0x014: case 0x414: case 0x814: case 0xc14: | |
da6b5335 FN |
2001 | if (((insn >> 22) & 3) == 0) |
2002 | return 1; | |
18c9b560 AZ |
2003 | wrd = (insn >> 12) & 0xf; |
2004 | rd0 = (insn >> 16) & 0xf; | |
2005 | gen_op_iwmmxt_movq_M0_wRn(rd0); | |
da6b5335 FN |
2006 | tmp = new_tmp(); |
2007 | if (gen_iwmmxt_shift(insn, 0xff, tmp)) { | |
2008 | dead_tmp(tmp); | |
18c9b560 | 2009 | return 1; |
da6b5335 | 2010 | } |
18c9b560 | 2011 | switch ((insn >> 22) & 3) { |
18c9b560 | 2012 | case 1: |
da6b5335 | 2013 | gen_helper_iwmmxt_sraw(cpu_M0, cpu_env, cpu_M0, tmp); |
18c9b560 AZ |
2014 | break; |
2015 | case 2: | |
da6b5335 | 2016 | gen_helper_iwmmxt_sral(cpu_M0, cpu_env, cpu_M0, tmp); |
18c9b560 AZ |
2017 | break; |
2018 | case 3: | |
da6b5335 | 2019 | gen_helper_iwmmxt_sraq(cpu_M0, cpu_env, cpu_M0, tmp); |
18c9b560 AZ |
2020 | break; |
2021 | } | |
da6b5335 | 2022 | dead_tmp(tmp); |
18c9b560 AZ |
2023 | gen_op_iwmmxt_movq_wRn_M0(wrd); |
2024 | gen_op_iwmmxt_set_mup(); | |
2025 | gen_op_iwmmxt_set_cup(); | |
2026 | break; | |
2027 | case 0x104: case 0x504: case 0x904: case 0xd04: /* WSLL */ | |
2028 | case 0x114: case 0x514: case 0x914: case 0xd14: | |
da6b5335 FN |
2029 | if (((insn >> 22) & 3) == 0) |
2030 | return 1; | |
18c9b560 AZ |
2031 | wrd = (insn >> 12) & 0xf; |
2032 | rd0 = (insn >> 16) & 0xf; | |
2033 | gen_op_iwmmxt_movq_M0_wRn(rd0); | |
da6b5335 FN |
2034 | tmp = new_tmp(); |
2035 | if (gen_iwmmxt_shift(insn, 0xff, tmp)) { | |
2036 | dead_tmp(tmp); | |
18c9b560 | 2037 | return 1; |
da6b5335 | 2038 | } |
18c9b560 | 2039 | switch ((insn >> 22) & 3) { |
18c9b560 | 2040 | case 1: |
da6b5335 | 2041 | gen_helper_iwmmxt_sllw(cpu_M0, cpu_env, cpu_M0, tmp); |
18c9b560 AZ |
2042 | break; |
2043 | case 2: | |
da6b5335 | 2044 | gen_helper_iwmmxt_slll(cpu_M0, cpu_env, cpu_M0, tmp); |
18c9b560 AZ |
2045 | break; |
2046 | case 3: | |
da6b5335 | 2047 | gen_helper_iwmmxt_sllq(cpu_M0, cpu_env, cpu_M0, tmp); |
18c9b560 AZ |
2048 | break; |
2049 | } | |
da6b5335 | 2050 | dead_tmp(tmp); |
18c9b560 AZ |
2051 | gen_op_iwmmxt_movq_wRn_M0(wrd); |
2052 | gen_op_iwmmxt_set_mup(); | |
2053 | gen_op_iwmmxt_set_cup(); | |
2054 | break; | |
2055 | case 0x304: case 0x704: case 0xb04: case 0xf04: /* WROR */ | |
2056 | case 0x314: case 0x714: case 0xb14: case 0xf14: | |
da6b5335 FN |
2057 | if (((insn >> 22) & 3) == 0) |
2058 | return 1; | |
18c9b560 AZ |
2059 | wrd = (insn >> 12) & 0xf; |
2060 | rd0 = (insn >> 16) & 0xf; | |
2061 | gen_op_iwmmxt_movq_M0_wRn(rd0); | |
da6b5335 | 2062 | tmp = new_tmp(); |
18c9b560 | 2063 | switch ((insn >> 22) & 3) { |
18c9b560 | 2064 | case 1: |
da6b5335 FN |
2065 | if (gen_iwmmxt_shift(insn, 0xf, tmp)) { |
2066 | dead_tmp(tmp); | |
18c9b560 | 2067 | return 1; |
da6b5335 FN |
2068 | } |
2069 | gen_helper_iwmmxt_rorw(cpu_M0, cpu_env, cpu_M0, tmp); | |
18c9b560 AZ |
2070 | break; |
2071 | case 2: | |
da6b5335 FN |
2072 | if (gen_iwmmxt_shift(insn, 0x1f, tmp)) { |
2073 | dead_tmp(tmp); | |
18c9b560 | 2074 | return 1; |
da6b5335 FN |
2075 | } |
2076 | gen_helper_iwmmxt_rorl(cpu_M0, cpu_env, cpu_M0, tmp); | |
18c9b560 AZ |
2077 | break; |
2078 | case 3: | |
da6b5335 FN |
2079 | if (gen_iwmmxt_shift(insn, 0x3f, tmp)) { |
2080 | dead_tmp(tmp); | |
18c9b560 | 2081 | return 1; |
da6b5335 FN |
2082 | } |
2083 | gen_helper_iwmmxt_rorq(cpu_M0, cpu_env, cpu_M0, tmp); | |
18c9b560 AZ |
2084 | break; |
2085 | } | |
da6b5335 | 2086 | dead_tmp(tmp); |
18c9b560 AZ |
2087 | gen_op_iwmmxt_movq_wRn_M0(wrd); |
2088 | gen_op_iwmmxt_set_mup(); | |
2089 | gen_op_iwmmxt_set_cup(); | |
2090 | break; | |
2091 | case 0x116: case 0x316: case 0x516: case 0x716: /* WMIN */ | |
2092 | case 0x916: case 0xb16: case 0xd16: case 0xf16: | |
2093 | wrd = (insn >> 12) & 0xf; | |
2094 | rd0 = (insn >> 16) & 0xf; | |
2095 | rd1 = (insn >> 0) & 0xf; | |
2096 | gen_op_iwmmxt_movq_M0_wRn(rd0); | |
2097 | switch ((insn >> 22) & 3) { | |
2098 | case 0: | |
2099 | if (insn & (1 << 21)) | |
2100 | gen_op_iwmmxt_minsb_M0_wRn(rd1); | |
2101 | else | |
2102 | gen_op_iwmmxt_minub_M0_wRn(rd1); | |
2103 | break; | |
2104 | case 1: | |
2105 | if (insn & (1 << 21)) | |
2106 | gen_op_iwmmxt_minsw_M0_wRn(rd1); | |
2107 | else | |
2108 | gen_op_iwmmxt_minuw_M0_wRn(rd1); | |
2109 | break; | |
2110 | case 2: | |
2111 | if (insn & (1 << 21)) | |
2112 | gen_op_iwmmxt_minsl_M0_wRn(rd1); | |
2113 | else | |
2114 | gen_op_iwmmxt_minul_M0_wRn(rd1); | |
2115 | break; | |
2116 | case 3: | |
2117 | return 1; | |
2118 | } | |
2119 | gen_op_iwmmxt_movq_wRn_M0(wrd); | |
2120 | gen_op_iwmmxt_set_mup(); | |
2121 | break; | |
2122 | case 0x016: case 0x216: case 0x416: case 0x616: /* WMAX */ | |
2123 | case 0x816: case 0xa16: case 0xc16: case 0xe16: | |
2124 | wrd = (insn >> 12) & 0xf; | |
2125 | rd0 = (insn >> 16) & 0xf; | |
2126 | rd1 = (insn >> 0) & 0xf; | |
2127 | gen_op_iwmmxt_movq_M0_wRn(rd0); | |
2128 | switch ((insn >> 22) & 3) { | |
2129 | case 0: | |
2130 | if (insn & (1 << 21)) | |
2131 | gen_op_iwmmxt_maxsb_M0_wRn(rd1); | |
2132 | else | |
2133 | gen_op_iwmmxt_maxub_M0_wRn(rd1); | |
2134 | break; | |
2135 | case 1: | |
2136 | if (insn & (1 << 21)) | |
2137 | gen_op_iwmmxt_maxsw_M0_wRn(rd1); | |
2138 | else | |
2139 | gen_op_iwmmxt_maxuw_M0_wRn(rd1); | |
2140 | break; | |
2141 | case 2: | |
2142 | if (insn & (1 << 21)) | |
2143 | gen_op_iwmmxt_maxsl_M0_wRn(rd1); | |
2144 | else | |
2145 | gen_op_iwmmxt_maxul_M0_wRn(rd1); | |
2146 | break; | |
2147 | case 3: | |
2148 | return 1; | |
2149 | } | |
2150 | gen_op_iwmmxt_movq_wRn_M0(wrd); | |
2151 | gen_op_iwmmxt_set_mup(); | |
2152 | break; | |
2153 | case 0x002: case 0x102: case 0x202: case 0x302: /* WALIGNI */ | |
2154 | case 0x402: case 0x502: case 0x602: case 0x702: | |
2155 | wrd = (insn >> 12) & 0xf; | |
2156 | rd0 = (insn >> 16) & 0xf; | |
2157 | rd1 = (insn >> 0) & 0xf; | |
2158 | gen_op_iwmmxt_movq_M0_wRn(rd0); | |
da6b5335 FN |
2159 | tmp = tcg_const_i32((insn >> 20) & 3); |
2160 | iwmmxt_load_reg(cpu_V1, rd1); | |
2161 | gen_helper_iwmmxt_align(cpu_M0, cpu_M0, cpu_V1, tmp); | |
2162 | tcg_temp_free(tmp); | |
18c9b560 AZ |
2163 | gen_op_iwmmxt_movq_wRn_M0(wrd); |
2164 | gen_op_iwmmxt_set_mup(); | |
2165 | break; | |
2166 | case 0x01a: case 0x11a: case 0x21a: case 0x31a: /* WSUB */ | |
2167 | case 0x41a: case 0x51a: case 0x61a: case 0x71a: | |
2168 | case 0x81a: case 0x91a: case 0xa1a: case 0xb1a: | |
2169 | case 0xc1a: case 0xd1a: case 0xe1a: case 0xf1a: | |
2170 | wrd = (insn >> 12) & 0xf; | |
2171 | rd0 = (insn >> 16) & 0xf; | |
2172 | rd1 = (insn >> 0) & 0xf; | |
2173 | gen_op_iwmmxt_movq_M0_wRn(rd0); | |
2174 | switch ((insn >> 20) & 0xf) { | |
2175 | case 0x0: | |
2176 | gen_op_iwmmxt_subnb_M0_wRn(rd1); | |
2177 | break; | |
2178 | case 0x1: | |
2179 | gen_op_iwmmxt_subub_M0_wRn(rd1); | |
2180 | break; | |
2181 | case 0x3: | |
2182 | gen_op_iwmmxt_subsb_M0_wRn(rd1); | |
2183 | break; | |
2184 | case 0x4: | |
2185 | gen_op_iwmmxt_subnw_M0_wRn(rd1); | |
2186 | break; | |
2187 | case 0x5: | |
2188 | gen_op_iwmmxt_subuw_M0_wRn(rd1); | |
2189 | break; | |
2190 | case 0x7: | |
2191 | gen_op_iwmmxt_subsw_M0_wRn(rd1); | |
2192 | break; | |
2193 | case 0x8: | |
2194 | gen_op_iwmmxt_subnl_M0_wRn(rd1); | |
2195 | break; | |
2196 | case 0x9: | |
2197 | gen_op_iwmmxt_subul_M0_wRn(rd1); | |
2198 | break; | |
2199 | case 0xb: | |
2200 | gen_op_iwmmxt_subsl_M0_wRn(rd1); | |
2201 | break; | |
2202 | default: | |
2203 | return 1; | |
2204 | } | |
2205 | gen_op_iwmmxt_movq_wRn_M0(wrd); | |
2206 | gen_op_iwmmxt_set_mup(); | |
2207 | gen_op_iwmmxt_set_cup(); | |
2208 | break; | |
2209 | case 0x01e: case 0x11e: case 0x21e: case 0x31e: /* WSHUFH */ | |
2210 | case 0x41e: case 0x51e: case 0x61e: case 0x71e: | |
2211 | case 0x81e: case 0x91e: case 0xa1e: case 0xb1e: | |
2212 | case 0xc1e: case 0xd1e: case 0xe1e: case 0xf1e: | |
2213 | wrd = (insn >> 12) & 0xf; | |
2214 | rd0 = (insn >> 16) & 0xf; | |
2215 | gen_op_iwmmxt_movq_M0_wRn(rd0); | |
da6b5335 FN |
2216 | tmp = tcg_const_i32(((insn >> 16) & 0xf0) | (insn & 0x0f)); |
2217 | gen_helper_iwmmxt_shufh(cpu_M0, cpu_env, cpu_M0, tmp); | |
2218 | tcg_temp_free(tmp); | |
18c9b560 AZ |
2219 | gen_op_iwmmxt_movq_wRn_M0(wrd); |
2220 | gen_op_iwmmxt_set_mup(); | |
2221 | gen_op_iwmmxt_set_cup(); | |
2222 | break; | |
2223 | case 0x018: case 0x118: case 0x218: case 0x318: /* WADD */ | |
2224 | case 0x418: case 0x518: case 0x618: case 0x718: | |
2225 | case 0x818: case 0x918: case 0xa18: case 0xb18: | |
2226 | case 0xc18: case 0xd18: case 0xe18: case 0xf18: | |
2227 | wrd = (insn >> 12) & 0xf; | |
2228 | rd0 = (insn >> 16) & 0xf; | |
2229 | rd1 = (insn >> 0) & 0xf; | |
2230 | gen_op_iwmmxt_movq_M0_wRn(rd0); | |
2231 | switch ((insn >> 20) & 0xf) { | |
2232 | case 0x0: | |
2233 | gen_op_iwmmxt_addnb_M0_wRn(rd1); | |
2234 | break; | |
2235 | case 0x1: | |
2236 | gen_op_iwmmxt_addub_M0_wRn(rd1); | |
2237 | break; | |
2238 | case 0x3: | |
2239 | gen_op_iwmmxt_addsb_M0_wRn(rd1); | |
2240 | break; | |
2241 | case 0x4: | |
2242 | gen_op_iwmmxt_addnw_M0_wRn(rd1); | |
2243 | break; | |
2244 | case 0x5: | |
2245 | gen_op_iwmmxt_adduw_M0_wRn(rd1); | |
2246 | break; | |
2247 | case 0x7: | |
2248 | gen_op_iwmmxt_addsw_M0_wRn(rd1); | |
2249 | break; | |
2250 | case 0x8: | |
2251 | gen_op_iwmmxt_addnl_M0_wRn(rd1); | |
2252 | break; | |
2253 | case 0x9: | |
2254 | gen_op_iwmmxt_addul_M0_wRn(rd1); | |
2255 | break; | |
2256 | case 0xb: | |
2257 | gen_op_iwmmxt_addsl_M0_wRn(rd1); | |
2258 | break; | |
2259 | default: | |
2260 | return 1; | |
2261 | } | |
2262 | gen_op_iwmmxt_movq_wRn_M0(wrd); | |
2263 | gen_op_iwmmxt_set_mup(); | |
2264 | gen_op_iwmmxt_set_cup(); | |
2265 | break; | |
2266 | case 0x008: case 0x108: case 0x208: case 0x308: /* WPACK */ | |
2267 | case 0x408: case 0x508: case 0x608: case 0x708: | |
2268 | case 0x808: case 0x908: case 0xa08: case 0xb08: | |
2269 | case 0xc08: case 0xd08: case 0xe08: case 0xf08: | |
da6b5335 FN |
2270 | if (!(insn & (1 << 20)) || ((insn >> 22) & 3) == 0) |
2271 | return 1; | |
18c9b560 AZ |
2272 | wrd = (insn >> 12) & 0xf; |
2273 | rd0 = (insn >> 16) & 0xf; | |
2274 | rd1 = (insn >> 0) & 0xf; | |
2275 | gen_op_iwmmxt_movq_M0_wRn(rd0); | |
18c9b560 | 2276 | switch ((insn >> 22) & 3) { |
18c9b560 AZ |
2277 | case 1: |
2278 | if (insn & (1 << 21)) | |
2279 | gen_op_iwmmxt_packsw_M0_wRn(rd1); | |
2280 | else | |
2281 | gen_op_iwmmxt_packuw_M0_wRn(rd1); | |
2282 | break; | |
2283 | case 2: | |
2284 | if (insn & (1 << 21)) | |
2285 | gen_op_iwmmxt_packsl_M0_wRn(rd1); | |
2286 | else | |
2287 | gen_op_iwmmxt_packul_M0_wRn(rd1); | |
2288 | break; | |
2289 | case 3: | |
2290 | if (insn & (1 << 21)) | |
2291 | gen_op_iwmmxt_packsq_M0_wRn(rd1); | |
2292 | else | |
2293 | gen_op_iwmmxt_packuq_M0_wRn(rd1); | |
2294 | break; | |
2295 | } | |
2296 | gen_op_iwmmxt_movq_wRn_M0(wrd); | |
2297 | gen_op_iwmmxt_set_mup(); | |
2298 | gen_op_iwmmxt_set_cup(); | |
2299 | break; | |
2300 | case 0x201: case 0x203: case 0x205: case 0x207: | |
2301 | case 0x209: case 0x20b: case 0x20d: case 0x20f: | |
2302 | case 0x211: case 0x213: case 0x215: case 0x217: | |
2303 | case 0x219: case 0x21b: case 0x21d: case 0x21f: | |
2304 | wrd = (insn >> 5) & 0xf; | |
2305 | rd0 = (insn >> 12) & 0xf; | |
2306 | rd1 = (insn >> 0) & 0xf; | |
2307 | if (rd0 == 0xf || rd1 == 0xf) | |
2308 | return 1; | |
2309 | gen_op_iwmmxt_movq_M0_wRn(wrd); | |
da6b5335 FN |
2310 | tmp = load_reg(s, rd0); |
2311 | tmp2 = load_reg(s, rd1); | |
18c9b560 AZ |
2312 | switch ((insn >> 16) & 0xf) { |
2313 | case 0x0: /* TMIA */ | |
da6b5335 | 2314 | gen_helper_iwmmxt_muladdsl(cpu_M0, cpu_M0, tmp, tmp2); |
18c9b560 AZ |
2315 | break; |
2316 | case 0x8: /* TMIAPH */ | |
da6b5335 | 2317 | gen_helper_iwmmxt_muladdsw(cpu_M0, cpu_M0, tmp, tmp2); |
18c9b560 AZ |
2318 | break; |
2319 | case 0xc: case 0xd: case 0xe: case 0xf: /* TMIAxy */ | |
18c9b560 | 2320 | if (insn & (1 << 16)) |
da6b5335 | 2321 | tcg_gen_shri_i32(tmp, tmp, 16); |
18c9b560 | 2322 | if (insn & (1 << 17)) |
da6b5335 FN |
2323 | tcg_gen_shri_i32(tmp2, tmp2, 16); |
2324 | gen_helper_iwmmxt_muladdswl(cpu_M0, cpu_M0, tmp, tmp2); | |
18c9b560 AZ |
2325 | break; |
2326 | default: | |
da6b5335 FN |
2327 | dead_tmp(tmp2); |
2328 | dead_tmp(tmp); | |
18c9b560 AZ |
2329 | return 1; |
2330 | } | |
da6b5335 FN |
2331 | dead_tmp(tmp2); |
2332 | dead_tmp(tmp); | |
18c9b560 AZ |
2333 | gen_op_iwmmxt_movq_wRn_M0(wrd); |
2334 | gen_op_iwmmxt_set_mup(); | |
2335 | break; | |
2336 | default: | |
2337 | return 1; | |
2338 | } | |
2339 | ||
2340 | return 0; | |
2341 | } | |
2342 | ||
2343 | /* Disassemble an XScale DSP instruction. Returns nonzero if an error occured | |
2344 | (ie. an undefined instruction). */ | |
2345 | static int disas_dsp_insn(CPUState *env, DisasContext *s, uint32_t insn) | |
2346 | { | |
2347 | int acc, rd0, rd1, rdhi, rdlo; | |
3a554c0f | 2348 | TCGv tmp, tmp2; |
18c9b560 AZ |
2349 | |
2350 | if ((insn & 0x0ff00f10) == 0x0e200010) { | |
2351 | /* Multiply with Internal Accumulate Format */ | |
2352 | rd0 = (insn >> 12) & 0xf; | |
2353 | rd1 = insn & 0xf; | |
2354 | acc = (insn >> 5) & 7; | |
2355 | ||
2356 | if (acc != 0) | |
2357 | return 1; | |
2358 | ||
3a554c0f FN |
2359 | tmp = load_reg(s, rd0); |
2360 | tmp2 = load_reg(s, rd1); | |
18c9b560 AZ |
2361 | switch ((insn >> 16) & 0xf) { |
2362 | case 0x0: /* MIA */ | |
3a554c0f | 2363 | gen_helper_iwmmxt_muladdsl(cpu_M0, cpu_M0, tmp, tmp2); |
18c9b560 AZ |
2364 | break; |
2365 | case 0x8: /* MIAPH */ | |
3a554c0f | 2366 | gen_helper_iwmmxt_muladdsw(cpu_M0, cpu_M0, tmp, tmp2); |
18c9b560 AZ |
2367 | break; |
2368 | case 0xc: /* MIABB */ | |
2369 | case 0xd: /* MIABT */ | |
2370 | case 0xe: /* MIATB */ | |
2371 | case 0xf: /* MIATT */ | |
18c9b560 | 2372 | if (insn & (1 << 16)) |
3a554c0f | 2373 | tcg_gen_shri_i32(tmp, tmp, 16); |
18c9b560 | 2374 | if (insn & (1 << 17)) |
3a554c0f FN |
2375 | tcg_gen_shri_i32(tmp2, tmp2, 16); |
2376 | gen_helper_iwmmxt_muladdswl(cpu_M0, cpu_M0, tmp, tmp2); | |
18c9b560 AZ |
2377 | break; |
2378 | default: | |
2379 | return 1; | |
2380 | } | |
3a554c0f FN |
2381 | dead_tmp(tmp2); |
2382 | dead_tmp(tmp); | |
18c9b560 AZ |
2383 | |
2384 | gen_op_iwmmxt_movq_wRn_M0(acc); | |
2385 | return 0; | |
2386 | } | |
2387 | ||
2388 | if ((insn & 0x0fe00ff8) == 0x0c400000) { | |
2389 | /* Internal Accumulator Access Format */ | |
2390 | rdhi = (insn >> 16) & 0xf; | |
2391 | rdlo = (insn >> 12) & 0xf; | |
2392 | acc = insn & 7; | |
2393 | ||
2394 | if (acc != 0) | |
2395 | return 1; | |
2396 | ||
2397 | if (insn & ARM_CP_RW_BIT) { /* MRA */ | |
3a554c0f FN |
2398 | iwmmxt_load_reg(cpu_V0, acc); |
2399 | tcg_gen_trunc_i64_i32(cpu_R[rdlo], cpu_V0); | |
2400 | tcg_gen_shri_i64(cpu_V0, cpu_V0, 32); | |
2401 | tcg_gen_trunc_i64_i32(cpu_R[rdhi], cpu_V0); | |
2402 | tcg_gen_andi_i32(cpu_R[rdhi], cpu_R[rdhi], (1 << (40 - 32)) - 1); | |
18c9b560 | 2403 | } else { /* MAR */ |
3a554c0f FN |
2404 | tcg_gen_concat_i32_i64(cpu_V0, cpu_R[rdlo], cpu_R[rdhi]); |
2405 | iwmmxt_store_reg(cpu_V0, acc); | |
18c9b560 AZ |
2406 | } |
2407 | return 0; | |
2408 | } | |
2409 | ||
2410 | return 1; | |
2411 | } | |
2412 | ||
c1713132 AZ |
2413 | /* Disassemble system coprocessor instruction. Return nonzero if |
2414 | instruction is not defined. */ | |
2415 | static int disas_cp_insn(CPUState *env, DisasContext *s, uint32_t insn) | |
2416 | { | |
b75263d6 | 2417 | TCGv tmp, tmp2; |
c1713132 AZ |
2418 | uint32_t rd = (insn >> 12) & 0xf; |
2419 | uint32_t cp = (insn >> 8) & 0xf; | |
2420 | if (IS_USER(s)) { | |
2421 | return 1; | |
2422 | } | |
2423 | ||
18c9b560 | 2424 | if (insn & ARM_CP_RW_BIT) { |
c1713132 AZ |
2425 | if (!env->cp[cp].cp_read) |
2426 | return 1; | |
8984bd2e PB |
2427 | gen_set_pc_im(s->pc); |
2428 | tmp = new_tmp(); | |
b75263d6 JR |
2429 | tmp2 = tcg_const_i32(insn); |
2430 | gen_helper_get_cp(tmp, cpu_env, tmp2); | |
2431 | tcg_temp_free(tmp2); | |
8984bd2e | 2432 | store_reg(s, rd, tmp); |
c1713132 AZ |
2433 | } else { |
2434 | if (!env->cp[cp].cp_write) | |
2435 | return 1; | |
8984bd2e PB |
2436 | gen_set_pc_im(s->pc); |
2437 | tmp = load_reg(s, rd); | |
b75263d6 JR |
2438 | tmp2 = tcg_const_i32(insn); |
2439 | gen_helper_set_cp(cpu_env, tmp2, tmp); | |
2440 | tcg_temp_free(tmp2); | |
a60de947 | 2441 | dead_tmp(tmp); |
c1713132 AZ |
2442 | } |
2443 | return 0; | |
2444 | } | |
2445 | ||
9ee6e8bb PB |
2446 | static int cp15_user_ok(uint32_t insn) |
2447 | { | |
2448 | int cpn = (insn >> 16) & 0xf; | |
2449 | int cpm = insn & 0xf; | |
2450 | int op = ((insn >> 5) & 7) | ((insn >> 18) & 0x38); | |
2451 | ||
2452 | if (cpn == 13 && cpm == 0) { | |
2453 | /* TLS register. */ | |
2454 | if (op == 2 || (op == 3 && (insn & ARM_CP_RW_BIT))) | |
2455 | return 1; | |
2456 | } | |
2457 | if (cpn == 7) { | |
2458 | /* ISB, DSB, DMB. */ | |
2459 | if ((cpm == 5 && op == 4) | |
2460 | || (cpm == 10 && (op == 4 || op == 5))) | |
2461 | return 1; | |
2462 | } | |
2463 | return 0; | |
2464 | } | |
2465 | ||
3f26c122 RV |
2466 | static int cp15_tls_load_store(CPUState *env, DisasContext *s, uint32_t insn, uint32_t rd) |
2467 | { | |
2468 | TCGv tmp; | |
2469 | int cpn = (insn >> 16) & 0xf; | |
2470 | int cpm = insn & 0xf; | |
2471 | int op = ((insn >> 5) & 7) | ((insn >> 18) & 0x38); | |
2472 | ||
2473 | if (!arm_feature(env, ARM_FEATURE_V6K)) | |
2474 | return 0; | |
2475 | ||
2476 | if (!(cpn == 13 && cpm == 0)) | |
2477 | return 0; | |
2478 | ||
2479 | if (insn & ARM_CP_RW_BIT) { | |
3f26c122 RV |
2480 | switch (op) { |
2481 | case 2: | |
c5883be2 | 2482 | tmp = load_cpu_field(cp15.c13_tls1); |
3f26c122 RV |
2483 | break; |
2484 | case 3: | |
c5883be2 | 2485 | tmp = load_cpu_field(cp15.c13_tls2); |
3f26c122 RV |
2486 | break; |
2487 | case 4: | |
c5883be2 | 2488 | tmp = load_cpu_field(cp15.c13_tls3); |
3f26c122 RV |
2489 | break; |
2490 | default: | |
3f26c122 RV |
2491 | return 0; |
2492 | } | |
2493 | store_reg(s, rd, tmp); | |
2494 | ||
2495 | } else { | |
2496 | tmp = load_reg(s, rd); | |
2497 | switch (op) { | |
2498 | case 2: | |
c5883be2 | 2499 | store_cpu_field(tmp, cp15.c13_tls1); |
3f26c122 RV |
2500 | break; |
2501 | case 3: | |
c5883be2 | 2502 | store_cpu_field(tmp, cp15.c13_tls2); |
3f26c122 RV |
2503 | break; |
2504 | case 4: | |
c5883be2 | 2505 | store_cpu_field(tmp, cp15.c13_tls3); |
3f26c122 RV |
2506 | break; |
2507 | default: | |
c5883be2 | 2508 | dead_tmp(tmp); |
3f26c122 RV |
2509 | return 0; |
2510 | } | |
3f26c122 RV |
2511 | } |
2512 | return 1; | |
2513 | } | |
2514 | ||
b5ff1b31 FB |
2515 | /* Disassemble system coprocessor (cp15) instruction. Return nonzero if |
2516 | instruction is not defined. */ | |
a90b7318 | 2517 | static int disas_cp15_insn(CPUState *env, DisasContext *s, uint32_t insn) |
b5ff1b31 FB |
2518 | { |
2519 | uint32_t rd; | |
b75263d6 | 2520 | TCGv tmp, tmp2; |
b5ff1b31 | 2521 | |
9ee6e8bb PB |
2522 | /* M profile cores use memory mapped registers instead of cp15. */ |
2523 | if (arm_feature(env, ARM_FEATURE_M)) | |
2524 | return 1; | |
2525 | ||
2526 | if ((insn & (1 << 25)) == 0) { | |
2527 | if (insn & (1 << 20)) { | |
2528 | /* mrrc */ | |
2529 | return 1; | |
2530 | } | |
2531 | /* mcrr. Used for block cache operations, so implement as no-op. */ | |
2532 | return 0; | |
2533 | } | |
2534 | if ((insn & (1 << 4)) == 0) { | |
2535 | /* cdp */ | |
2536 | return 1; | |
2537 | } | |
2538 | if (IS_USER(s) && !cp15_user_ok(insn)) { | |
b5ff1b31 FB |
2539 | return 1; |
2540 | } | |
9332f9da FB |
2541 | if ((insn & 0x0fff0fff) == 0x0e070f90 |
2542 | || (insn & 0x0fff0fff) == 0x0e070f58) { | |
2543 | /* Wait for interrupt. */ | |
8984bd2e | 2544 | gen_set_pc_im(s->pc); |
9ee6e8bb | 2545 | s->is_jmp = DISAS_WFI; |
9332f9da FB |
2546 | return 0; |
2547 | } | |
b5ff1b31 | 2548 | rd = (insn >> 12) & 0xf; |
3f26c122 RV |
2549 | |
2550 | if (cp15_tls_load_store(env, s, insn, rd)) | |
2551 | return 0; | |
2552 | ||
b75263d6 | 2553 | tmp2 = tcg_const_i32(insn); |
18c9b560 | 2554 | if (insn & ARM_CP_RW_BIT) { |
8984bd2e | 2555 | tmp = new_tmp(); |
b75263d6 | 2556 | gen_helper_get_cp15(tmp, cpu_env, tmp2); |
b5ff1b31 FB |
2557 | /* If the destination register is r15 then sets condition codes. */ |
2558 | if (rd != 15) | |
8984bd2e PB |
2559 | store_reg(s, rd, tmp); |
2560 | else | |
2561 | dead_tmp(tmp); | |
b5ff1b31 | 2562 | } else { |
8984bd2e | 2563 | tmp = load_reg(s, rd); |
b75263d6 | 2564 | gen_helper_set_cp15(cpu_env, tmp2, tmp); |
8984bd2e | 2565 | dead_tmp(tmp); |
a90b7318 AZ |
2566 | /* Normally we would always end the TB here, but Linux |
2567 | * arch/arm/mach-pxa/sleep.S expects two instructions following | |
2568 | * an MMU enable to execute from cache. Imitate this behaviour. */ | |
2569 | if (!arm_feature(env, ARM_FEATURE_XSCALE) || | |
2570 | (insn & 0x0fff0fff) != 0x0e010f10) | |
2571 | gen_lookup_tb(s); | |
b5ff1b31 | 2572 | } |
b75263d6 | 2573 | tcg_temp_free_i32(tmp2); |
b5ff1b31 FB |
2574 | return 0; |
2575 | } | |
2576 | ||
9ee6e8bb PB |
2577 | #define VFP_REG_SHR(x, n) (((n) > 0) ? (x) >> (n) : (x) << -(n)) |
2578 | #define VFP_SREG(insn, bigbit, smallbit) \ | |
2579 | ((VFP_REG_SHR(insn, bigbit - 1) & 0x1e) | (((insn) >> (smallbit)) & 1)) | |
2580 | #define VFP_DREG(reg, insn, bigbit, smallbit) do { \ | |
2581 | if (arm_feature(env, ARM_FEATURE_VFP3)) { \ | |
2582 | reg = (((insn) >> (bigbit)) & 0x0f) \ | |
2583 | | (((insn) >> ((smallbit) - 4)) & 0x10); \ | |
2584 | } else { \ | |
2585 | if (insn & (1 << (smallbit))) \ | |
2586 | return 1; \ | |
2587 | reg = ((insn) >> (bigbit)) & 0x0f; \ | |
2588 | }} while (0) | |
2589 | ||
2590 | #define VFP_SREG_D(insn) VFP_SREG(insn, 12, 22) | |
2591 | #define VFP_DREG_D(reg, insn) VFP_DREG(reg, insn, 12, 22) | |
2592 | #define VFP_SREG_N(insn) VFP_SREG(insn, 16, 7) | |
2593 | #define VFP_DREG_N(reg, insn) VFP_DREG(reg, insn, 16, 7) | |
2594 | #define VFP_SREG_M(insn) VFP_SREG(insn, 0, 5) | |
2595 | #define VFP_DREG_M(reg, insn) VFP_DREG(reg, insn, 0, 5) | |
2596 | ||
4373f3ce PB |
2597 | /* Move between integer and VFP cores. */ |
2598 | static TCGv gen_vfp_mrs(void) | |
2599 | { | |
2600 | TCGv tmp = new_tmp(); | |
2601 | tcg_gen_mov_i32(tmp, cpu_F0s); | |
2602 | return tmp; | |
2603 | } | |
2604 | ||
2605 | static void gen_vfp_msr(TCGv tmp) | |
2606 | { | |
2607 | tcg_gen_mov_i32(cpu_F0s, tmp); | |
2608 | dead_tmp(tmp); | |
2609 | } | |
2610 | ||
ad69471c PB |
2611 | static void gen_neon_dup_u8(TCGv var, int shift) |
2612 | { | |
2613 | TCGv tmp = new_tmp(); | |
2614 | if (shift) | |
2615 | tcg_gen_shri_i32(var, var, shift); | |
86831435 | 2616 | tcg_gen_ext8u_i32(var, var); |
ad69471c PB |
2617 | tcg_gen_shli_i32(tmp, var, 8); |
2618 | tcg_gen_or_i32(var, var, tmp); | |
2619 | tcg_gen_shli_i32(tmp, var, 16); | |
2620 | tcg_gen_or_i32(var, var, tmp); | |
2621 | dead_tmp(tmp); | |
2622 | } | |
2623 | ||
2624 | static void gen_neon_dup_low16(TCGv var) | |
2625 | { | |
2626 | TCGv tmp = new_tmp(); | |
86831435 | 2627 | tcg_gen_ext16u_i32(var, var); |
ad69471c PB |
2628 | tcg_gen_shli_i32(tmp, var, 16); |
2629 | tcg_gen_or_i32(var, var, tmp); | |
2630 | dead_tmp(tmp); | |
2631 | } | |
2632 | ||
2633 | static void gen_neon_dup_high16(TCGv var) | |
2634 | { | |
2635 | TCGv tmp = new_tmp(); | |
2636 | tcg_gen_andi_i32(var, var, 0xffff0000); | |
2637 | tcg_gen_shri_i32(tmp, var, 16); | |
2638 | tcg_gen_or_i32(var, var, tmp); | |
2639 | dead_tmp(tmp); | |
2640 | } | |
2641 | ||
b7bcbe95 FB |
2642 | /* Disassemble a VFP instruction. Returns nonzero if an error occured |
2643 | (ie. an undefined instruction). */ | |
2644 | static int disas_vfp_insn(CPUState * env, DisasContext *s, uint32_t insn) | |
2645 | { | |
2646 | uint32_t rd, rn, rm, op, i, n, offset, delta_d, delta_m, bank_mask; | |
2647 | int dp, veclen; | |
312eea9f | 2648 | TCGv addr; |
4373f3ce | 2649 | TCGv tmp; |
ad69471c | 2650 | TCGv tmp2; |
b7bcbe95 | 2651 | |
40f137e1 PB |
2652 | if (!arm_feature(env, ARM_FEATURE_VFP)) |
2653 | return 1; | |
2654 | ||
5df8bac1 | 2655 | if (!s->vfp_enabled) { |
9ee6e8bb | 2656 | /* VFP disabled. Only allow fmxr/fmrx to/from some control regs. */ |
40f137e1 PB |
2657 | if ((insn & 0x0fe00fff) != 0x0ee00a10) |
2658 | return 1; | |
2659 | rn = (insn >> 16) & 0xf; | |
9ee6e8bb PB |
2660 | if (rn != ARM_VFP_FPSID && rn != ARM_VFP_FPEXC |
2661 | && rn != ARM_VFP_MVFR1 && rn != ARM_VFP_MVFR0) | |
40f137e1 PB |
2662 | return 1; |
2663 | } | |
b7bcbe95 FB |
2664 | dp = ((insn & 0xf00) == 0xb00); |
2665 | switch ((insn >> 24) & 0xf) { | |
2666 | case 0xe: | |
2667 | if (insn & (1 << 4)) { | |
2668 | /* single register transfer */ | |
b7bcbe95 FB |
2669 | rd = (insn >> 12) & 0xf; |
2670 | if (dp) { | |
9ee6e8bb PB |
2671 | int size; |
2672 | int pass; | |
2673 | ||
2674 | VFP_DREG_N(rn, insn); | |
2675 | if (insn & 0xf) | |
b7bcbe95 | 2676 | return 1; |
9ee6e8bb PB |
2677 | if (insn & 0x00c00060 |
2678 | && !arm_feature(env, ARM_FEATURE_NEON)) | |
2679 | return 1; | |
2680 | ||
2681 | pass = (insn >> 21) & 1; | |
2682 | if (insn & (1 << 22)) { | |
2683 | size = 0; | |
2684 | offset = ((insn >> 5) & 3) * 8; | |
2685 | } else if (insn & (1 << 5)) { | |
2686 | size = 1; | |
2687 | offset = (insn & (1 << 6)) ? 16 : 0; | |
2688 | } else { | |
2689 | size = 2; | |
2690 | offset = 0; | |
2691 | } | |
18c9b560 | 2692 | if (insn & ARM_CP_RW_BIT) { |
b7bcbe95 | 2693 | /* vfp->arm */ |
ad69471c | 2694 | tmp = neon_load_reg(rn, pass); |
9ee6e8bb PB |
2695 | switch (size) { |
2696 | case 0: | |
9ee6e8bb | 2697 | if (offset) |
ad69471c | 2698 | tcg_gen_shri_i32(tmp, tmp, offset); |
9ee6e8bb | 2699 | if (insn & (1 << 23)) |
ad69471c | 2700 | gen_uxtb(tmp); |
9ee6e8bb | 2701 | else |
ad69471c | 2702 | gen_sxtb(tmp); |
9ee6e8bb PB |
2703 | break; |
2704 | case 1: | |
9ee6e8bb PB |
2705 | if (insn & (1 << 23)) { |
2706 | if (offset) { | |
ad69471c | 2707 | tcg_gen_shri_i32(tmp, tmp, 16); |
9ee6e8bb | 2708 | } else { |
ad69471c | 2709 | gen_uxth(tmp); |
9ee6e8bb PB |
2710 | } |
2711 | } else { | |
2712 | if (offset) { | |
ad69471c | 2713 | tcg_gen_sari_i32(tmp, tmp, 16); |
9ee6e8bb | 2714 | } else { |
ad69471c | 2715 | gen_sxth(tmp); |
9ee6e8bb PB |
2716 | } |
2717 | } | |
2718 | break; | |
2719 | case 2: | |
9ee6e8bb PB |
2720 | break; |
2721 | } | |
ad69471c | 2722 | store_reg(s, rd, tmp); |
b7bcbe95 FB |
2723 | } else { |
2724 | /* arm->vfp */ | |
ad69471c | 2725 | tmp = load_reg(s, rd); |
9ee6e8bb PB |
2726 | if (insn & (1 << 23)) { |
2727 | /* VDUP */ | |
2728 | if (size == 0) { | |
ad69471c | 2729 | gen_neon_dup_u8(tmp, 0); |
9ee6e8bb | 2730 | } else if (size == 1) { |
ad69471c | 2731 | gen_neon_dup_low16(tmp); |
9ee6e8bb | 2732 | } |
cbbccffc PB |
2733 | for (n = 0; n <= pass * 2; n++) { |
2734 | tmp2 = new_tmp(); | |
2735 | tcg_gen_mov_i32(tmp2, tmp); | |
2736 | neon_store_reg(rn, n, tmp2); | |
2737 | } | |
2738 | neon_store_reg(rn, n, tmp); | |
9ee6e8bb PB |
2739 | } else { |
2740 | /* VMOV */ | |
2741 | switch (size) { | |
2742 | case 0: | |
ad69471c PB |
2743 | tmp2 = neon_load_reg(rn, pass); |
2744 | gen_bfi(tmp, tmp2, tmp, offset, 0xff); | |
2745 | dead_tmp(tmp2); | |
9ee6e8bb PB |
2746 | break; |
2747 | case 1: | |
ad69471c PB |
2748 | tmp2 = neon_load_reg(rn, pass); |
2749 | gen_bfi(tmp, tmp2, tmp, offset, 0xffff); | |
2750 | dead_tmp(tmp2); | |
9ee6e8bb PB |
2751 | break; |
2752 | case 2: | |
9ee6e8bb PB |
2753 | break; |
2754 | } | |
ad69471c | 2755 | neon_store_reg(rn, pass, tmp); |
9ee6e8bb | 2756 | } |
b7bcbe95 | 2757 | } |
9ee6e8bb PB |
2758 | } else { /* !dp */ |
2759 | if ((insn & 0x6f) != 0x00) | |
2760 | return 1; | |
2761 | rn = VFP_SREG_N(insn); | |
18c9b560 | 2762 | if (insn & ARM_CP_RW_BIT) { |
b7bcbe95 FB |
2763 | /* vfp->arm */ |
2764 | if (insn & (1 << 21)) { | |
2765 | /* system register */ | |
40f137e1 | 2766 | rn >>= 1; |
9ee6e8bb | 2767 | |
b7bcbe95 | 2768 | switch (rn) { |
40f137e1 | 2769 | case ARM_VFP_FPSID: |
4373f3ce | 2770 | /* VFP2 allows access to FSID from userspace. |
9ee6e8bb PB |
2771 | VFP3 restricts all id registers to privileged |
2772 | accesses. */ | |
2773 | if (IS_USER(s) | |
2774 | && arm_feature(env, ARM_FEATURE_VFP3)) | |
2775 | return 1; | |
4373f3ce | 2776 | tmp = load_cpu_field(vfp.xregs[rn]); |
9ee6e8bb | 2777 | break; |
40f137e1 | 2778 | case ARM_VFP_FPEXC: |
9ee6e8bb PB |
2779 | if (IS_USER(s)) |
2780 | return 1; | |
4373f3ce | 2781 | tmp = load_cpu_field(vfp.xregs[rn]); |
9ee6e8bb | 2782 | break; |
40f137e1 PB |
2783 | case ARM_VFP_FPINST: |
2784 | case ARM_VFP_FPINST2: | |
9ee6e8bb PB |
2785 | /* Not present in VFP3. */ |
2786 | if (IS_USER(s) | |
2787 | || arm_feature(env, ARM_FEATURE_VFP3)) | |
2788 | return 1; | |
4373f3ce | 2789 | tmp = load_cpu_field(vfp.xregs[rn]); |
b7bcbe95 | 2790 | break; |
40f137e1 | 2791 | case ARM_VFP_FPSCR: |
601d70b9 | 2792 | if (rd == 15) { |
4373f3ce PB |
2793 | tmp = load_cpu_field(vfp.xregs[ARM_VFP_FPSCR]); |
2794 | tcg_gen_andi_i32(tmp, tmp, 0xf0000000); | |
2795 | } else { | |
2796 | tmp = new_tmp(); | |
2797 | gen_helper_vfp_get_fpscr(tmp, cpu_env); | |
2798 | } | |
b7bcbe95 | 2799 | break; |
9ee6e8bb PB |
2800 | case ARM_VFP_MVFR0: |
2801 | case ARM_VFP_MVFR1: | |
2802 | if (IS_USER(s) | |
2803 | || !arm_feature(env, ARM_FEATURE_VFP3)) | |
2804 | return 1; | |
4373f3ce | 2805 | tmp = load_cpu_field(vfp.xregs[rn]); |
9ee6e8bb | 2806 | break; |
b7bcbe95 FB |
2807 | default: |
2808 | return 1; | |
2809 | } | |
2810 | } else { | |
2811 | gen_mov_F0_vreg(0, rn); | |
4373f3ce | 2812 | tmp = gen_vfp_mrs(); |
b7bcbe95 FB |
2813 | } |
2814 | if (rd == 15) { | |
b5ff1b31 | 2815 | /* Set the 4 flag bits in the CPSR. */ |
4373f3ce PB |
2816 | gen_set_nzcv(tmp); |
2817 | dead_tmp(tmp); | |
2818 | } else { | |
2819 | store_reg(s, rd, tmp); | |
2820 | } | |
b7bcbe95 FB |
2821 | } else { |
2822 | /* arm->vfp */ | |
4373f3ce | 2823 | tmp = load_reg(s, rd); |
b7bcbe95 | 2824 | if (insn & (1 << 21)) { |
40f137e1 | 2825 | rn >>= 1; |
b7bcbe95 FB |
2826 | /* system register */ |
2827 | switch (rn) { | |
40f137e1 | 2828 | case ARM_VFP_FPSID: |
9ee6e8bb PB |
2829 | case ARM_VFP_MVFR0: |
2830 | case ARM_VFP_MVFR1: | |
b7bcbe95 FB |
2831 | /* Writes are ignored. */ |
2832 | break; | |
40f137e1 | 2833 | case ARM_VFP_FPSCR: |
4373f3ce PB |
2834 | gen_helper_vfp_set_fpscr(cpu_env, tmp); |
2835 | dead_tmp(tmp); | |
b5ff1b31 | 2836 | gen_lookup_tb(s); |
b7bcbe95 | 2837 | break; |
40f137e1 | 2838 | case ARM_VFP_FPEXC: |
9ee6e8bb PB |
2839 | if (IS_USER(s)) |
2840 | return 1; | |
71b3c3de JR |
2841 | /* TODO: VFP subarchitecture support. |
2842 | * For now, keep the EN bit only */ | |
2843 | tcg_gen_andi_i32(tmp, tmp, 1 << 30); | |
4373f3ce | 2844 | store_cpu_field(tmp, vfp.xregs[rn]); |
40f137e1 PB |
2845 | gen_lookup_tb(s); |
2846 | break; | |
2847 | case ARM_VFP_FPINST: | |
2848 | case ARM_VFP_FPINST2: | |
4373f3ce | 2849 | store_cpu_field(tmp, vfp.xregs[rn]); |
40f137e1 | 2850 | break; |
b7bcbe95 FB |
2851 | default: |
2852 | return 1; | |
2853 | } | |
2854 | } else { | |
4373f3ce | 2855 | gen_vfp_msr(tmp); |
b7bcbe95 FB |
2856 | gen_mov_vreg_F0(0, rn); |
2857 | } | |
2858 | } | |
2859 | } | |
2860 | } else { | |
2861 | /* data processing */ | |
2862 | /* The opcode is in bits 23, 21, 20 and 6. */ | |
2863 | op = ((insn >> 20) & 8) | ((insn >> 19) & 6) | ((insn >> 6) & 1); | |
2864 | if (dp) { | |
2865 | if (op == 15) { | |
2866 | /* rn is opcode */ | |
2867 | rn = ((insn >> 15) & 0x1e) | ((insn >> 7) & 1); | |
2868 | } else { | |
2869 | /* rn is register number */ | |
9ee6e8bb | 2870 | VFP_DREG_N(rn, insn); |
b7bcbe95 FB |
2871 | } |
2872 | ||
04595bf6 | 2873 | if (op == 15 && (rn == 15 || ((rn & 0x1c) == 0x18))) { |
b7bcbe95 | 2874 | /* Integer or single precision destination. */ |
9ee6e8bb | 2875 | rd = VFP_SREG_D(insn); |
b7bcbe95 | 2876 | } else { |
9ee6e8bb | 2877 | VFP_DREG_D(rd, insn); |
b7bcbe95 | 2878 | } |
04595bf6 PM |
2879 | if (op == 15 && |
2880 | (((rn & 0x1c) == 0x10) || ((rn & 0x14) == 0x14))) { | |
2881 | /* VCVT from int is always from S reg regardless of dp bit. | |
2882 | * VCVT with immediate frac_bits has same format as SREG_M | |
2883 | */ | |
2884 | rm = VFP_SREG_M(insn); | |
b7bcbe95 | 2885 | } else { |
9ee6e8bb | 2886 | VFP_DREG_M(rm, insn); |
b7bcbe95 FB |
2887 | } |
2888 | } else { | |
9ee6e8bb | 2889 | rn = VFP_SREG_N(insn); |
b7bcbe95 FB |
2890 | if (op == 15 && rn == 15) { |
2891 | /* Double precision destination. */ | |
9ee6e8bb PB |
2892 | VFP_DREG_D(rd, insn); |
2893 | } else { | |
2894 | rd = VFP_SREG_D(insn); | |
2895 | } | |
04595bf6 PM |
2896 | /* NB that we implicitly rely on the encoding for the frac_bits |
2897 | * in VCVT of fixed to float being the same as that of an SREG_M | |
2898 | */ | |
9ee6e8bb | 2899 | rm = VFP_SREG_M(insn); |
b7bcbe95 FB |
2900 | } |
2901 | ||
69d1fc22 | 2902 | veclen = s->vec_len; |
b7bcbe95 FB |
2903 | if (op == 15 && rn > 3) |
2904 | veclen = 0; | |
2905 | ||
2906 | /* Shut up compiler warnings. */ | |
2907 | delta_m = 0; | |
2908 | delta_d = 0; | |
2909 | bank_mask = 0; | |
3b46e624 | 2910 | |
b7bcbe95 FB |
2911 | if (veclen > 0) { |
2912 | if (dp) | |
2913 | bank_mask = 0xc; | |
2914 | else | |
2915 | bank_mask = 0x18; | |
2916 | ||
2917 | /* Figure out what type of vector operation this is. */ | |
2918 | if ((rd & bank_mask) == 0) { | |
2919 | /* scalar */ | |
2920 | veclen = 0; | |
2921 | } else { | |
2922 | if (dp) | |
69d1fc22 | 2923 | delta_d = (s->vec_stride >> 1) + 1; |
b7bcbe95 | 2924 | else |
69d1fc22 | 2925 | delta_d = s->vec_stride + 1; |
b7bcbe95 FB |
2926 | |
2927 | if ((rm & bank_mask) == 0) { | |
2928 | /* mixed scalar/vector */ | |
2929 | delta_m = 0; | |
2930 | } else { | |
2931 | /* vector */ | |
2932 | delta_m = delta_d; | |
2933 | } | |
2934 | } | |
2935 | } | |
2936 | ||
2937 | /* Load the initial operands. */ | |
2938 | if (op == 15) { | |
2939 | switch (rn) { | |
2940 | case 16: | |
2941 | case 17: | |
2942 | /* Integer source */ | |
2943 | gen_mov_F0_vreg(0, rm); | |
2944 | break; | |
2945 | case 8: | |
2946 | case 9: | |
2947 | /* Compare */ | |
2948 | gen_mov_F0_vreg(dp, rd); | |
2949 | gen_mov_F1_vreg(dp, rm); | |
2950 | break; | |
2951 | case 10: | |
2952 | case 11: | |
2953 | /* Compare with zero */ | |
2954 | gen_mov_F0_vreg(dp, rd); | |
2955 | gen_vfp_F1_ld0(dp); | |
2956 | break; | |
9ee6e8bb PB |
2957 | case 20: |
2958 | case 21: | |
2959 | case 22: | |
2960 | case 23: | |
644ad806 PB |
2961 | case 28: |
2962 | case 29: | |
2963 | case 30: | |
2964 | case 31: | |
9ee6e8bb PB |
2965 | /* Source and destination the same. */ |
2966 | gen_mov_F0_vreg(dp, rd); | |
2967 | break; | |
b7bcbe95 FB |
2968 | default: |
2969 | /* One source operand. */ | |
2970 | gen_mov_F0_vreg(dp, rm); | |
9ee6e8bb | 2971 | break; |
b7bcbe95 FB |
2972 | } |
2973 | } else { | |
2974 | /* Two source operands. */ | |
2975 | gen_mov_F0_vreg(dp, rn); | |
2976 | gen_mov_F1_vreg(dp, rm); | |
2977 | } | |
2978 | ||
2979 | for (;;) { | |
2980 | /* Perform the calculation. */ | |
2981 | switch (op) { | |
2982 | case 0: /* mac: fd + (fn * fm) */ | |
2983 | gen_vfp_mul(dp); | |
2984 | gen_mov_F1_vreg(dp, rd); | |
2985 | gen_vfp_add(dp); | |
2986 | break; | |
2987 | case 1: /* nmac: fd - (fn * fm) */ | |
2988 | gen_vfp_mul(dp); | |
2989 | gen_vfp_neg(dp); | |
2990 | gen_mov_F1_vreg(dp, rd); | |
2991 | gen_vfp_add(dp); | |
2992 | break; | |
2993 | case 2: /* msc: -fd + (fn * fm) */ | |
2994 | gen_vfp_mul(dp); | |
2995 | gen_mov_F1_vreg(dp, rd); | |
2996 | gen_vfp_sub(dp); | |
2997 | break; | |
2998 | case 3: /* nmsc: -fd - (fn * fm) */ | |
2999 | gen_vfp_mul(dp); | |
b7bcbe95 | 3000 | gen_vfp_neg(dp); |
c9fb531a PB |
3001 | gen_mov_F1_vreg(dp, rd); |
3002 | gen_vfp_sub(dp); | |
b7bcbe95 FB |
3003 | break; |
3004 | case 4: /* mul: fn * fm */ | |
3005 | gen_vfp_mul(dp); | |
3006 | break; | |
3007 | case 5: /* nmul: -(fn * fm) */ | |
3008 | gen_vfp_mul(dp); | |
3009 | gen_vfp_neg(dp); | |
3010 | break; | |
3011 | case 6: /* add: fn + fm */ | |
3012 | gen_vfp_add(dp); | |
3013 | break; | |
3014 | case 7: /* sub: fn - fm */ | |
3015 | gen_vfp_sub(dp); | |
3016 | break; | |
3017 | case 8: /* div: fn / fm */ | |
3018 | gen_vfp_div(dp); | |
3019 | break; | |
9ee6e8bb PB |
3020 | case 14: /* fconst */ |
3021 | if (!arm_feature(env, ARM_FEATURE_VFP3)) | |
3022 | return 1; | |
3023 | ||
3024 | n = (insn << 12) & 0x80000000; | |
3025 | i = ((insn >> 12) & 0x70) | (insn & 0xf); | |
3026 | if (dp) { | |
3027 | if (i & 0x40) | |
3028 | i |= 0x3f80; | |
3029 | else | |
3030 | i |= 0x4000; | |
3031 | n |= i << 16; | |
4373f3ce | 3032 | tcg_gen_movi_i64(cpu_F0d, ((uint64_t)n) << 32); |
9ee6e8bb PB |
3033 | } else { |
3034 | if (i & 0x40) | |
3035 | i |= 0x780; | |
3036 | else | |
3037 | i |= 0x800; | |
3038 | n |= i << 19; | |
5b340b51 | 3039 | tcg_gen_movi_i32(cpu_F0s, n); |
9ee6e8bb | 3040 | } |
9ee6e8bb | 3041 | break; |
b7bcbe95 FB |
3042 | case 15: /* extension space */ |
3043 | switch (rn) { | |
3044 | case 0: /* cpy */ | |
3045 | /* no-op */ | |
3046 | break; | |
3047 | case 1: /* abs */ | |
3048 | gen_vfp_abs(dp); | |
3049 | break; | |
3050 | case 2: /* neg */ | |
3051 | gen_vfp_neg(dp); | |
3052 | break; | |
3053 | case 3: /* sqrt */ | |
3054 | gen_vfp_sqrt(dp); | |
3055 | break; | |
60011498 PB |
3056 | case 4: /* vcvtb.f32.f16 */ |
3057 | if (!arm_feature(env, ARM_FEATURE_VFP_FP16)) | |
3058 | return 1; | |
3059 | tmp = gen_vfp_mrs(); | |
3060 | tcg_gen_ext16u_i32(tmp, tmp); | |
3061 | gen_helper_vfp_fcvt_f16_to_f32(cpu_F0s, tmp, cpu_env); | |
3062 | dead_tmp(tmp); | |
3063 | break; | |
3064 | case 5: /* vcvtt.f32.f16 */ | |
3065 | if (!arm_feature(env, ARM_FEATURE_VFP_FP16)) | |
3066 | return 1; | |
3067 | tmp = gen_vfp_mrs(); | |
3068 | tcg_gen_shri_i32(tmp, tmp, 16); | |
3069 | gen_helper_vfp_fcvt_f16_to_f32(cpu_F0s, tmp, cpu_env); | |
3070 | dead_tmp(tmp); | |
3071 | break; | |
3072 | case 6: /* vcvtb.f16.f32 */ | |
3073 | if (!arm_feature(env, ARM_FEATURE_VFP_FP16)) | |
3074 | return 1; | |
3075 | tmp = new_tmp(); | |
3076 | gen_helper_vfp_fcvt_f32_to_f16(tmp, cpu_F0s, cpu_env); | |
3077 | gen_mov_F0_vreg(0, rd); | |
3078 | tmp2 = gen_vfp_mrs(); | |
3079 | tcg_gen_andi_i32(tmp2, tmp2, 0xffff0000); | |
3080 | tcg_gen_or_i32(tmp, tmp, tmp2); | |
3081 | dead_tmp(tmp2); | |
3082 | gen_vfp_msr(tmp); | |
3083 | break; | |
3084 | case 7: /* vcvtt.f16.f32 */ | |
3085 | if (!arm_feature(env, ARM_FEATURE_VFP_FP16)) | |
3086 | return 1; | |
3087 | tmp = new_tmp(); | |
3088 | gen_helper_vfp_fcvt_f32_to_f16(tmp, cpu_F0s, cpu_env); | |
3089 | tcg_gen_shli_i32(tmp, tmp, 16); | |
3090 | gen_mov_F0_vreg(0, rd); | |
3091 | tmp2 = gen_vfp_mrs(); | |
3092 | tcg_gen_ext16u_i32(tmp2, tmp2); | |
3093 | tcg_gen_or_i32(tmp, tmp, tmp2); | |
3094 | dead_tmp(tmp2); | |
3095 | gen_vfp_msr(tmp); | |
3096 | break; | |
b7bcbe95 FB |
3097 | case 8: /* cmp */ |
3098 | gen_vfp_cmp(dp); | |
3099 | break; | |
3100 | case 9: /* cmpe */ | |
3101 | gen_vfp_cmpe(dp); | |
3102 | break; | |
3103 | case 10: /* cmpz */ | |
3104 | gen_vfp_cmp(dp); | |
3105 | break; | |
3106 | case 11: /* cmpez */ | |
3107 | gen_vfp_F1_ld0(dp); | |
3108 | gen_vfp_cmpe(dp); | |
3109 | break; | |
3110 | case 15: /* single<->double conversion */ | |
3111 | if (dp) | |
4373f3ce | 3112 | gen_helper_vfp_fcvtsd(cpu_F0s, cpu_F0d, cpu_env); |
b7bcbe95 | 3113 | else |
4373f3ce | 3114 | gen_helper_vfp_fcvtds(cpu_F0d, cpu_F0s, cpu_env); |
b7bcbe95 FB |
3115 | break; |
3116 | case 16: /* fuito */ | |
3117 | gen_vfp_uito(dp); | |
3118 | break; | |
3119 | case 17: /* fsito */ | |
3120 | gen_vfp_sito(dp); | |
3121 | break; | |
9ee6e8bb PB |
3122 | case 20: /* fshto */ |
3123 | if (!arm_feature(env, ARM_FEATURE_VFP3)) | |
3124 | return 1; | |
644ad806 | 3125 | gen_vfp_shto(dp, 16 - rm); |
9ee6e8bb PB |
3126 | break; |
3127 | case 21: /* fslto */ | |
3128 | if (!arm_feature(env, ARM_FEATURE_VFP3)) | |
3129 | return 1; | |
644ad806 | 3130 | gen_vfp_slto(dp, 32 - rm); |
9ee6e8bb PB |
3131 | break; |
3132 | case 22: /* fuhto */ | |
3133 | if (!arm_feature(env, ARM_FEATURE_VFP3)) | |
3134 | return 1; | |
644ad806 | 3135 | gen_vfp_uhto(dp, 16 - rm); |
9ee6e8bb PB |
3136 | break; |
3137 | case 23: /* fulto */ | |
3138 | if (!arm_feature(env, ARM_FEATURE_VFP3)) | |
3139 | return 1; | |
644ad806 | 3140 | gen_vfp_ulto(dp, 32 - rm); |
9ee6e8bb | 3141 | break; |
b7bcbe95 FB |
3142 | case 24: /* ftoui */ |
3143 | gen_vfp_toui(dp); | |
3144 | break; | |
3145 | case 25: /* ftouiz */ | |
3146 | gen_vfp_touiz(dp); | |
3147 | break; | |
3148 | case 26: /* ftosi */ | |
3149 | gen_vfp_tosi(dp); | |
3150 | break; | |
3151 | case 27: /* ftosiz */ | |
3152 | gen_vfp_tosiz(dp); | |
3153 | break; | |
9ee6e8bb PB |
3154 | case 28: /* ftosh */ |
3155 | if (!arm_feature(env, ARM_FEATURE_VFP3)) | |
3156 | return 1; | |
644ad806 | 3157 | gen_vfp_tosh(dp, 16 - rm); |
9ee6e8bb PB |
3158 | break; |
3159 | case 29: /* ftosl */ | |
3160 | if (!arm_feature(env, ARM_FEATURE_VFP3)) | |
3161 | return 1; | |
644ad806 | 3162 | gen_vfp_tosl(dp, 32 - rm); |
9ee6e8bb PB |
3163 | break; |
3164 | case 30: /* ftouh */ | |
3165 | if (!arm_feature(env, ARM_FEATURE_VFP3)) | |
3166 | return 1; | |
644ad806 | 3167 | gen_vfp_touh(dp, 16 - rm); |
9ee6e8bb PB |
3168 | break; |
3169 | case 31: /* ftoul */ | |
3170 | if (!arm_feature(env, ARM_FEATURE_VFP3)) | |
3171 | return 1; | |
644ad806 | 3172 | gen_vfp_toul(dp, 32 - rm); |
9ee6e8bb | 3173 | break; |
b7bcbe95 FB |
3174 | default: /* undefined */ |
3175 | printf ("rn:%d\n", rn); | |
3176 | return 1; | |
3177 | } | |
3178 | break; | |
3179 | default: /* undefined */ | |
3180 | printf ("op:%d\n", op); | |
3181 | return 1; | |
3182 | } | |
3183 | ||
3184 | /* Write back the result. */ | |
3185 | if (op == 15 && (rn >= 8 && rn <= 11)) | |
3186 | ; /* Comparison, do nothing. */ | |
04595bf6 PM |
3187 | else if (op == 15 && dp && ((rn & 0x1c) == 0x18)) |
3188 | /* VCVT double to int: always integer result. */ | |
b7bcbe95 FB |
3189 | gen_mov_vreg_F0(0, rd); |
3190 | else if (op == 15 && rn == 15) | |
3191 | /* conversion */ | |
3192 | gen_mov_vreg_F0(!dp, rd); | |
3193 | else | |
3194 | gen_mov_vreg_F0(dp, rd); | |
3195 | ||
3196 | /* break out of the loop if we have finished */ | |
3197 | if (veclen == 0) | |
3198 | break; | |
3199 | ||
3200 | if (op == 15 && delta_m == 0) { | |
3201 | /* single source one-many */ | |
3202 | while (veclen--) { | |
3203 | rd = ((rd + delta_d) & (bank_mask - 1)) | |
3204 | | (rd & bank_mask); | |
3205 | gen_mov_vreg_F0(dp, rd); | |
3206 | } | |
3207 | break; | |
3208 | } | |
3209 | /* Setup the next operands. */ | |
3210 | veclen--; | |
3211 | rd = ((rd + delta_d) & (bank_mask - 1)) | |
3212 | | (rd & bank_mask); | |
3213 | ||
3214 | if (op == 15) { | |
3215 | /* One source operand. */ | |
3216 | rm = ((rm + delta_m) & (bank_mask - 1)) | |
3217 | | (rm & bank_mask); | |
3218 | gen_mov_F0_vreg(dp, rm); | |
3219 | } else { | |
3220 | /* Two source operands. */ | |
3221 | rn = ((rn + delta_d) & (bank_mask - 1)) | |
3222 | | (rn & bank_mask); | |
3223 | gen_mov_F0_vreg(dp, rn); | |
3224 | if (delta_m) { | |
3225 | rm = ((rm + delta_m) & (bank_mask - 1)) | |
3226 | | (rm & bank_mask); | |
3227 | gen_mov_F1_vreg(dp, rm); | |
3228 | } | |
3229 | } | |
3230 | } | |
3231 | } | |
3232 | break; | |
3233 | case 0xc: | |
3234 | case 0xd: | |
9ee6e8bb | 3235 | if (dp && (insn & 0x03e00000) == 0x00400000) { |
b7bcbe95 FB |
3236 | /* two-register transfer */ |
3237 | rn = (insn >> 16) & 0xf; | |
3238 | rd = (insn >> 12) & 0xf; | |
3239 | if (dp) { | |
9ee6e8bb PB |
3240 | VFP_DREG_M(rm, insn); |
3241 | } else { | |
3242 | rm = VFP_SREG_M(insn); | |
3243 | } | |
b7bcbe95 | 3244 | |
18c9b560 | 3245 | if (insn & ARM_CP_RW_BIT) { |
b7bcbe95 FB |
3246 | /* vfp->arm */ |
3247 | if (dp) { | |
4373f3ce PB |
3248 | gen_mov_F0_vreg(0, rm * 2); |
3249 | tmp = gen_vfp_mrs(); | |
3250 | store_reg(s, rd, tmp); | |
3251 | gen_mov_F0_vreg(0, rm * 2 + 1); | |
3252 | tmp = gen_vfp_mrs(); | |
3253 | store_reg(s, rn, tmp); | |
b7bcbe95 FB |
3254 | } else { |
3255 | gen_mov_F0_vreg(0, rm); | |
4373f3ce PB |
3256 | tmp = gen_vfp_mrs(); |
3257 | store_reg(s, rn, tmp); | |
b7bcbe95 | 3258 | gen_mov_F0_vreg(0, rm + 1); |
4373f3ce PB |
3259 | tmp = gen_vfp_mrs(); |
3260 | store_reg(s, rd, tmp); | |
b7bcbe95 FB |
3261 | } |
3262 | } else { | |
3263 | /* arm->vfp */ | |
3264 | if (dp) { | |
4373f3ce PB |
3265 | tmp = load_reg(s, rd); |
3266 | gen_vfp_msr(tmp); | |
3267 | gen_mov_vreg_F0(0, rm * 2); | |
3268 | tmp = load_reg(s, rn); | |
3269 | gen_vfp_msr(tmp); | |
3270 | gen_mov_vreg_F0(0, rm * 2 + 1); | |
b7bcbe95 | 3271 | } else { |
4373f3ce PB |
3272 | tmp = load_reg(s, rn); |
3273 | gen_vfp_msr(tmp); | |
b7bcbe95 | 3274 | gen_mov_vreg_F0(0, rm); |
4373f3ce PB |
3275 | tmp = load_reg(s, rd); |
3276 | gen_vfp_msr(tmp); | |
b7bcbe95 FB |
3277 | gen_mov_vreg_F0(0, rm + 1); |
3278 | } | |
3279 | } | |
3280 | } else { | |
3281 | /* Load/store */ | |
3282 | rn = (insn >> 16) & 0xf; | |
3283 | if (dp) | |
9ee6e8bb | 3284 | VFP_DREG_D(rd, insn); |
b7bcbe95 | 3285 | else |
9ee6e8bb PB |
3286 | rd = VFP_SREG_D(insn); |
3287 | if (s->thumb && rn == 15) { | |
312eea9f FN |
3288 | addr = new_tmp(); |
3289 | tcg_gen_movi_i32(addr, s->pc & ~2); | |
9ee6e8bb | 3290 | } else { |
312eea9f | 3291 | addr = load_reg(s, rn); |
9ee6e8bb | 3292 | } |
b7bcbe95 FB |
3293 | if ((insn & 0x01200000) == 0x01000000) { |
3294 | /* Single load/store */ | |
3295 | offset = (insn & 0xff) << 2; | |
3296 | if ((insn & (1 << 23)) == 0) | |
3297 | offset = -offset; | |
312eea9f | 3298 | tcg_gen_addi_i32(addr, addr, offset); |
b7bcbe95 | 3299 | if (insn & (1 << 20)) { |
312eea9f | 3300 | gen_vfp_ld(s, dp, addr); |
b7bcbe95 FB |
3301 | gen_mov_vreg_F0(dp, rd); |
3302 | } else { | |
3303 | gen_mov_F0_vreg(dp, rd); | |
312eea9f | 3304 | gen_vfp_st(s, dp, addr); |
b7bcbe95 | 3305 | } |
312eea9f | 3306 | dead_tmp(addr); |
b7bcbe95 FB |
3307 | } else { |
3308 | /* load/store multiple */ | |
3309 | if (dp) | |
3310 | n = (insn >> 1) & 0x7f; | |
3311 | else | |
3312 | n = insn & 0xff; | |
3313 | ||
3314 | if (insn & (1 << 24)) /* pre-decrement */ | |
312eea9f | 3315 | tcg_gen_addi_i32(addr, addr, -((insn & 0xff) << 2)); |
b7bcbe95 FB |
3316 | |
3317 | if (dp) | |
3318 | offset = 8; | |
3319 | else | |
3320 | offset = 4; | |
3321 | for (i = 0; i < n; i++) { | |
18c9b560 | 3322 | if (insn & ARM_CP_RW_BIT) { |
b7bcbe95 | 3323 | /* load */ |
312eea9f | 3324 | gen_vfp_ld(s, dp, addr); |
b7bcbe95 FB |
3325 | gen_mov_vreg_F0(dp, rd + i); |
3326 | } else { | |
3327 | /* store */ | |
3328 | gen_mov_F0_vreg(dp, rd + i); | |
312eea9f | 3329 | gen_vfp_st(s, dp, addr); |
b7bcbe95 | 3330 | } |
312eea9f | 3331 | tcg_gen_addi_i32(addr, addr, offset); |
b7bcbe95 FB |
3332 | } |
3333 | if (insn & (1 << 21)) { | |
3334 | /* writeback */ | |
3335 | if (insn & (1 << 24)) | |
3336 | offset = -offset * n; | |
3337 | else if (dp && (insn & 1)) | |
3338 | offset = 4; | |
3339 | else | |
3340 | offset = 0; | |
3341 | ||
3342 | if (offset != 0) | |
312eea9f FN |
3343 | tcg_gen_addi_i32(addr, addr, offset); |
3344 | store_reg(s, rn, addr); | |
3345 | } else { | |
3346 | dead_tmp(addr); | |
b7bcbe95 FB |
3347 | } |
3348 | } | |
3349 | } | |
3350 | break; | |
3351 | default: | |
3352 | /* Should never happen. */ | |
3353 | return 1; | |
3354 | } | |
3355 | return 0; | |
3356 | } | |
3357 | ||
6e256c93 | 3358 | static inline void gen_goto_tb(DisasContext *s, int n, uint32_t dest) |
c53be334 | 3359 | { |
6e256c93 FB |
3360 | TranslationBlock *tb; |
3361 | ||
3362 | tb = s->tb; | |
3363 | if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK)) { | |
57fec1fe | 3364 | tcg_gen_goto_tb(n); |
8984bd2e | 3365 | gen_set_pc_im(dest); |
57fec1fe | 3366 | tcg_gen_exit_tb((long)tb + n); |
6e256c93 | 3367 | } else { |
8984bd2e | 3368 | gen_set_pc_im(dest); |
57fec1fe | 3369 | tcg_gen_exit_tb(0); |
6e256c93 | 3370 | } |
c53be334 FB |
3371 | } |
3372 | ||
8aaca4c0 FB |
3373 | static inline void gen_jmp (DisasContext *s, uint32_t dest) |
3374 | { | |
551bd27f | 3375 | if (unlikely(s->singlestep_enabled)) { |
8aaca4c0 | 3376 | /* An indirect jump so that we still trigger the debug exception. */ |
5899f386 | 3377 | if (s->thumb) |
d9ba4830 PB |
3378 | dest |= 1; |
3379 | gen_bx_im(s, dest); | |
8aaca4c0 | 3380 | } else { |
6e256c93 | 3381 | gen_goto_tb(s, 0, dest); |
8aaca4c0 FB |
3382 | s->is_jmp = DISAS_TB_JUMP; |
3383 | } | |
3384 | } | |
3385 | ||
d9ba4830 | 3386 | static inline void gen_mulxy(TCGv t0, TCGv t1, int x, int y) |
b5ff1b31 | 3387 | { |
ee097184 | 3388 | if (x) |
d9ba4830 | 3389 | tcg_gen_sari_i32(t0, t0, 16); |
b5ff1b31 | 3390 | else |
d9ba4830 | 3391 | gen_sxth(t0); |
ee097184 | 3392 | if (y) |
d9ba4830 | 3393 | tcg_gen_sari_i32(t1, t1, 16); |
b5ff1b31 | 3394 | else |
d9ba4830 PB |
3395 | gen_sxth(t1); |
3396 | tcg_gen_mul_i32(t0, t0, t1); | |
b5ff1b31 FB |
3397 | } |
3398 | ||
3399 | /* Return the mask of PSR bits set by a MSR instruction. */ | |
9ee6e8bb | 3400 | static uint32_t msr_mask(CPUState *env, DisasContext *s, int flags, int spsr) { |
b5ff1b31 FB |
3401 | uint32_t mask; |
3402 | ||
3403 | mask = 0; | |
3404 | if (flags & (1 << 0)) | |
3405 | mask |= 0xff; | |
3406 | if (flags & (1 << 1)) | |
3407 | mask |= 0xff00; | |
3408 | if (flags & (1 << 2)) | |
3409 | mask |= 0xff0000; | |
3410 | if (flags & (1 << 3)) | |
3411 | mask |= 0xff000000; | |
9ee6e8bb | 3412 | |
2ae23e75 | 3413 | /* Mask out undefined bits. */ |
9ee6e8bb PB |
3414 | mask &= ~CPSR_RESERVED; |
3415 | if (!arm_feature(env, ARM_FEATURE_V6)) | |
e160c51c | 3416 | mask &= ~(CPSR_E | CPSR_GE); |
9ee6e8bb | 3417 | if (!arm_feature(env, ARM_FEATURE_THUMB2)) |
e160c51c | 3418 | mask &= ~CPSR_IT; |
9ee6e8bb | 3419 | /* Mask out execution state bits. */ |
2ae23e75 | 3420 | if (!spsr) |
e160c51c | 3421 | mask &= ~CPSR_EXEC; |
b5ff1b31 FB |
3422 | /* Mask out privileged bits. */ |
3423 | if (IS_USER(s)) | |
9ee6e8bb | 3424 | mask &= CPSR_USER; |
b5ff1b31 FB |
3425 | return mask; |
3426 | } | |
3427 | ||
2fbac54b FN |
3428 | /* Returns nonzero if access to the PSR is not permitted. Marks t0 as dead. */ |
3429 | static int gen_set_psr(DisasContext *s, uint32_t mask, int spsr, TCGv t0) | |
b5ff1b31 | 3430 | { |
d9ba4830 | 3431 | TCGv tmp; |
b5ff1b31 FB |
3432 | if (spsr) { |
3433 | /* ??? This is also undefined in system mode. */ | |
3434 | if (IS_USER(s)) | |
3435 | return 1; | |
d9ba4830 PB |
3436 | |
3437 | tmp = load_cpu_field(spsr); | |
3438 | tcg_gen_andi_i32(tmp, tmp, ~mask); | |
2fbac54b FN |
3439 | tcg_gen_andi_i32(t0, t0, mask); |
3440 | tcg_gen_or_i32(tmp, tmp, t0); | |
d9ba4830 | 3441 | store_cpu_field(tmp, spsr); |
b5ff1b31 | 3442 | } else { |
2fbac54b | 3443 | gen_set_cpsr(t0, mask); |
b5ff1b31 | 3444 | } |
2fbac54b | 3445 | dead_tmp(t0); |
b5ff1b31 FB |
3446 | gen_lookup_tb(s); |
3447 | return 0; | |
3448 | } | |
3449 | ||
2fbac54b FN |
3450 | /* Returns nonzero if access to the PSR is not permitted. */ |
3451 | static int gen_set_psr_im(DisasContext *s, uint32_t mask, int spsr, uint32_t val) | |
3452 | { | |
3453 | TCGv tmp; | |
3454 | tmp = new_tmp(); | |
3455 | tcg_gen_movi_i32(tmp, val); | |
3456 | return gen_set_psr(s, mask, spsr, tmp); | |
3457 | } | |
3458 | ||
e9bb4aa9 JR |
3459 | /* Generate an old-style exception return. Marks pc as dead. */ |
3460 | static void gen_exception_return(DisasContext *s, TCGv pc) | |
b5ff1b31 | 3461 | { |
d9ba4830 | 3462 | TCGv tmp; |
e9bb4aa9 | 3463 | store_reg(s, 15, pc); |
d9ba4830 PB |
3464 | tmp = load_cpu_field(spsr); |
3465 | gen_set_cpsr(tmp, 0xffffffff); | |
3466 | dead_tmp(tmp); | |
b5ff1b31 FB |
3467 | s->is_jmp = DISAS_UPDATE; |
3468 | } | |
3469 | ||
b0109805 PB |
3470 | /* Generate a v6 exception return. Marks both values as dead. */ |
3471 | static void gen_rfe(DisasContext *s, TCGv pc, TCGv cpsr) | |
2c0262af | 3472 | { |
b0109805 PB |
3473 | gen_set_cpsr(cpsr, 0xffffffff); |
3474 | dead_tmp(cpsr); | |
3475 | store_reg(s, 15, pc); | |
9ee6e8bb PB |
3476 | s->is_jmp = DISAS_UPDATE; |
3477 | } | |
3b46e624 | 3478 | |
9ee6e8bb PB |
3479 | static inline void |
3480 | gen_set_condexec (DisasContext *s) | |
3481 | { | |
3482 | if (s->condexec_mask) { | |
8f01245e PB |
3483 | uint32_t val = (s->condexec_cond << 4) | (s->condexec_mask >> 1); |
3484 | TCGv tmp = new_tmp(); | |
3485 | tcg_gen_movi_i32(tmp, val); | |
d9ba4830 | 3486 | store_cpu_field(tmp, condexec_bits); |
9ee6e8bb PB |
3487 | } |
3488 | } | |
3b46e624 | 3489 | |
bc4a0de0 PM |
3490 | static void gen_exception_insn(DisasContext *s, int offset, int excp) |
3491 | { | |
3492 | gen_set_condexec(s); | |
3493 | gen_set_pc_im(s->pc - offset); | |
3494 | gen_exception(excp); | |
3495 | s->is_jmp = DISAS_JUMP; | |
3496 | } | |
3497 | ||
9ee6e8bb PB |
3498 | static void gen_nop_hint(DisasContext *s, int val) |
3499 | { | |
3500 | switch (val) { | |
3501 | case 3: /* wfi */ | |
8984bd2e | 3502 | gen_set_pc_im(s->pc); |
9ee6e8bb PB |
3503 | s->is_jmp = DISAS_WFI; |
3504 | break; | |
3505 | case 2: /* wfe */ | |
3506 | case 4: /* sev */ | |
3507 | /* TODO: Implement SEV and WFE. May help SMP performance. */ | |
3508 | default: /* nop */ | |
3509 | break; | |
3510 | } | |
3511 | } | |
99c475ab | 3512 | |
ad69471c | 3513 | #define CPU_V001 cpu_V0, cpu_V0, cpu_V1 |
9ee6e8bb | 3514 | |
dd8fbd78 | 3515 | static inline int gen_neon_add(int size, TCGv t0, TCGv t1) |
9ee6e8bb PB |
3516 | { |
3517 | switch (size) { | |
dd8fbd78 FN |
3518 | case 0: gen_helper_neon_add_u8(t0, t0, t1); break; |
3519 | case 1: gen_helper_neon_add_u16(t0, t0, t1); break; | |
3520 | case 2: tcg_gen_add_i32(t0, t0, t1); break; | |
9ee6e8bb PB |
3521 | default: return 1; |
3522 | } | |
3523 | return 0; | |
3524 | } | |
3525 | ||
dd8fbd78 | 3526 | static inline void gen_neon_rsb(int size, TCGv t0, TCGv t1) |
ad69471c PB |
3527 | { |
3528 | switch (size) { | |
dd8fbd78 FN |
3529 | case 0: gen_helper_neon_sub_u8(t0, t1, t0); break; |
3530 | case 1: gen_helper_neon_sub_u16(t0, t1, t0); break; | |
3531 | case 2: tcg_gen_sub_i32(t0, t1, t0); break; | |
ad69471c PB |
3532 | default: return; |
3533 | } | |
3534 | } | |
3535 | ||
3536 | /* 32-bit pairwise ops end up the same as the elementwise versions. */ | |
3537 | #define gen_helper_neon_pmax_s32 gen_helper_neon_max_s32 | |
3538 | #define gen_helper_neon_pmax_u32 gen_helper_neon_max_u32 | |
3539 | #define gen_helper_neon_pmin_s32 gen_helper_neon_min_s32 | |
3540 | #define gen_helper_neon_pmin_u32 gen_helper_neon_min_u32 | |
3541 | ||
ad69471c PB |
3542 | #define GEN_NEON_INTEGER_OP_ENV(name) do { \ |
3543 | switch ((size << 1) | u) { \ | |
3544 | case 0: \ | |
dd8fbd78 | 3545 | gen_helper_neon_##name##_s8(tmp, cpu_env, tmp, tmp2); \ |
ad69471c PB |
3546 | break; \ |
3547 | case 1: \ | |
dd8fbd78 | 3548 | gen_helper_neon_##name##_u8(tmp, cpu_env, tmp, tmp2); \ |
ad69471c PB |
3549 | break; \ |
3550 | case 2: \ | |
dd8fbd78 | 3551 | gen_helper_neon_##name##_s16(tmp, cpu_env, tmp, tmp2); \ |
ad69471c PB |
3552 | break; \ |
3553 | case 3: \ | |
dd8fbd78 | 3554 | gen_helper_neon_##name##_u16(tmp, cpu_env, tmp, tmp2); \ |
ad69471c PB |
3555 | break; \ |
3556 | case 4: \ | |
dd8fbd78 | 3557 | gen_helper_neon_##name##_s32(tmp, cpu_env, tmp, tmp2); \ |
ad69471c PB |
3558 | break; \ |
3559 | case 5: \ | |
dd8fbd78 | 3560 | gen_helper_neon_##name##_u32(tmp, cpu_env, tmp, tmp2); \ |
ad69471c PB |
3561 | break; \ |
3562 | default: return 1; \ | |
3563 | }} while (0) | |
9ee6e8bb PB |
3564 | |
3565 | #define GEN_NEON_INTEGER_OP(name) do { \ | |
3566 | switch ((size << 1) | u) { \ | |
ad69471c | 3567 | case 0: \ |
dd8fbd78 | 3568 | gen_helper_neon_##name##_s8(tmp, tmp, tmp2); \ |
ad69471c PB |
3569 | break; \ |
3570 | case 1: \ | |
dd8fbd78 | 3571 | gen_helper_neon_##name##_u8(tmp, tmp, tmp2); \ |
ad69471c PB |
3572 | break; \ |
3573 | case 2: \ | |
dd8fbd78 | 3574 | gen_helper_neon_##name##_s16(tmp, tmp, tmp2); \ |
ad69471c PB |
3575 | break; \ |
3576 | case 3: \ | |
dd8fbd78 | 3577 | gen_helper_neon_##name##_u16(tmp, tmp, tmp2); \ |
ad69471c PB |
3578 | break; \ |
3579 | case 4: \ | |
dd8fbd78 | 3580 | gen_helper_neon_##name##_s32(tmp, tmp, tmp2); \ |
ad69471c PB |
3581 | break; \ |
3582 | case 5: \ | |
dd8fbd78 | 3583 | gen_helper_neon_##name##_u32(tmp, tmp, tmp2); \ |
ad69471c | 3584 | break; \ |
9ee6e8bb PB |
3585 | default: return 1; \ |
3586 | }} while (0) | |
3587 | ||
dd8fbd78 | 3588 | static TCGv neon_load_scratch(int scratch) |
9ee6e8bb | 3589 | { |
dd8fbd78 FN |
3590 | TCGv tmp = new_tmp(); |
3591 | tcg_gen_ld_i32(tmp, cpu_env, offsetof(CPUARMState, vfp.scratch[scratch])); | |
3592 | return tmp; | |
9ee6e8bb PB |
3593 | } |
3594 | ||
dd8fbd78 | 3595 | static void neon_store_scratch(int scratch, TCGv var) |
9ee6e8bb | 3596 | { |
dd8fbd78 FN |
3597 | tcg_gen_st_i32(var, cpu_env, offsetof(CPUARMState, vfp.scratch[scratch])); |
3598 | dead_tmp(var); | |
9ee6e8bb PB |
3599 | } |
3600 | ||
dd8fbd78 | 3601 | static inline TCGv neon_get_scalar(int size, int reg) |
9ee6e8bb | 3602 | { |
dd8fbd78 | 3603 | TCGv tmp; |
9ee6e8bb | 3604 | if (size == 1) { |
0fad6efc PM |
3605 | tmp = neon_load_reg(reg & 7, reg >> 4); |
3606 | if (reg & 8) { | |
dd8fbd78 | 3607 | gen_neon_dup_high16(tmp); |
0fad6efc PM |
3608 | } else { |
3609 | gen_neon_dup_low16(tmp); | |
dd8fbd78 | 3610 | } |
0fad6efc PM |
3611 | } else { |
3612 | tmp = neon_load_reg(reg & 15, reg >> 4); | |
9ee6e8bb | 3613 | } |
dd8fbd78 | 3614 | return tmp; |
9ee6e8bb PB |
3615 | } |
3616 | ||
19457615 FN |
3617 | static void gen_neon_unzip_u8(TCGv t0, TCGv t1) |
3618 | { | |
3619 | TCGv rd, rm, tmp; | |
3620 | ||
3621 | rd = new_tmp(); | |
3622 | rm = new_tmp(); | |
3623 | tmp = new_tmp(); | |
3624 | ||
3625 | tcg_gen_andi_i32(rd, t0, 0xff); | |
3626 | tcg_gen_shri_i32(tmp, t0, 8); | |
3627 | tcg_gen_andi_i32(tmp, tmp, 0xff00); | |
3628 | tcg_gen_or_i32(rd, rd, tmp); | |
3629 | tcg_gen_shli_i32(tmp, t1, 16); | |
3630 | tcg_gen_andi_i32(tmp, tmp, 0xff0000); | |
3631 | tcg_gen_or_i32(rd, rd, tmp); | |
3632 | tcg_gen_shli_i32(tmp, t1, 8); | |
3633 | tcg_gen_andi_i32(tmp, tmp, 0xff000000); | |
3634 | tcg_gen_or_i32(rd, rd, tmp); | |
3635 | ||
3636 | tcg_gen_shri_i32(rm, t0, 8); | |
3637 | tcg_gen_andi_i32(rm, rm, 0xff); | |
3638 | tcg_gen_shri_i32(tmp, t0, 16); | |
3639 | tcg_gen_andi_i32(tmp, tmp, 0xff00); | |
3640 | tcg_gen_or_i32(rm, rm, tmp); | |
3641 | tcg_gen_shli_i32(tmp, t1, 8); | |
3642 | tcg_gen_andi_i32(tmp, tmp, 0xff0000); | |
3643 | tcg_gen_or_i32(rm, rm, tmp); | |
3644 | tcg_gen_andi_i32(tmp, t1, 0xff000000); | |
3645 | tcg_gen_or_i32(t1, rm, tmp); | |
3646 | tcg_gen_mov_i32(t0, rd); | |
3647 | ||
3648 | dead_tmp(tmp); | |
3649 | dead_tmp(rm); | |
3650 | dead_tmp(rd); | |
3651 | } | |
3652 | ||
3653 | static void gen_neon_zip_u8(TCGv t0, TCGv t1) | |
3654 | { | |
3655 | TCGv rd, rm, tmp; | |
3656 | ||
3657 | rd = new_tmp(); | |
3658 | rm = new_tmp(); | |
3659 | tmp = new_tmp(); | |
3660 | ||
3661 | tcg_gen_andi_i32(rd, t0, 0xff); | |
3662 | tcg_gen_shli_i32(tmp, t1, 8); | |
3663 | tcg_gen_andi_i32(tmp, tmp, 0xff00); | |
3664 | tcg_gen_or_i32(rd, rd, tmp); | |
3665 | tcg_gen_shli_i32(tmp, t0, 16); | |
3666 | tcg_gen_andi_i32(tmp, tmp, 0xff0000); | |
3667 | tcg_gen_or_i32(rd, rd, tmp); | |
3668 | tcg_gen_shli_i32(tmp, t1, 24); | |
3669 | tcg_gen_andi_i32(tmp, tmp, 0xff000000); | |
3670 | tcg_gen_or_i32(rd, rd, tmp); | |
3671 | ||
3672 | tcg_gen_andi_i32(rm, t1, 0xff000000); | |
3673 | tcg_gen_shri_i32(tmp, t0, 8); | |
3674 | tcg_gen_andi_i32(tmp, tmp, 0xff0000); | |
3675 | tcg_gen_or_i32(rm, rm, tmp); | |
3676 | tcg_gen_shri_i32(tmp, t1, 8); | |
3677 | tcg_gen_andi_i32(tmp, tmp, 0xff00); | |
3678 | tcg_gen_or_i32(rm, rm, tmp); | |
3679 | tcg_gen_shri_i32(tmp, t0, 16); | |
3680 | tcg_gen_andi_i32(tmp, tmp, 0xff); | |
3681 | tcg_gen_or_i32(t1, rm, tmp); | |
3682 | tcg_gen_mov_i32(t0, rd); | |
3683 | ||
3684 | dead_tmp(tmp); | |
3685 | dead_tmp(rm); | |
3686 | dead_tmp(rd); | |
3687 | } | |
3688 | ||
3689 | static void gen_neon_zip_u16(TCGv t0, TCGv t1) | |
3690 | { | |
3691 | TCGv tmp, tmp2; | |
3692 | ||
3693 | tmp = new_tmp(); | |
3694 | tmp2 = new_tmp(); | |
3695 | ||
3696 | tcg_gen_andi_i32(tmp, t0, 0xffff); | |
3697 | tcg_gen_shli_i32(tmp2, t1, 16); | |
3698 | tcg_gen_or_i32(tmp, tmp, tmp2); | |
3699 | tcg_gen_andi_i32(t1, t1, 0xffff0000); | |
3700 | tcg_gen_shri_i32(tmp2, t0, 16); | |
3701 | tcg_gen_or_i32(t1, t1, tmp2); | |
3702 | tcg_gen_mov_i32(t0, tmp); | |
3703 | ||
3704 | dead_tmp(tmp2); | |
3705 | dead_tmp(tmp); | |
3706 | } | |
3707 | ||
9ee6e8bb PB |
3708 | static void gen_neon_unzip(int reg, int q, int tmp, int size) |
3709 | { | |
3710 | int n; | |
dd8fbd78 | 3711 | TCGv t0, t1; |
9ee6e8bb PB |
3712 | |
3713 | for (n = 0; n < q + 1; n += 2) { | |
dd8fbd78 FN |
3714 | t0 = neon_load_reg(reg, n); |
3715 | t1 = neon_load_reg(reg, n + 1); | |
9ee6e8bb | 3716 | switch (size) { |
dd8fbd78 FN |
3717 | case 0: gen_neon_unzip_u8(t0, t1); break; |
3718 | case 1: gen_neon_zip_u16(t0, t1); break; /* zip and unzip are the same. */ | |
9ee6e8bb PB |
3719 | case 2: /* no-op */; break; |
3720 | default: abort(); | |
3721 | } | |
dd8fbd78 FN |
3722 | neon_store_scratch(tmp + n, t0); |
3723 | neon_store_scratch(tmp + n + 1, t1); | |
9ee6e8bb PB |
3724 | } |
3725 | } | |
3726 | ||
19457615 FN |
3727 | static void gen_neon_trn_u8(TCGv t0, TCGv t1) |
3728 | { | |
3729 | TCGv rd, tmp; | |
3730 | ||
3731 | rd = new_tmp(); | |
3732 | tmp = new_tmp(); | |
3733 | ||
3734 | tcg_gen_shli_i32(rd, t0, 8); | |
3735 | tcg_gen_andi_i32(rd, rd, 0xff00ff00); | |
3736 | tcg_gen_andi_i32(tmp, t1, 0x00ff00ff); | |
3737 | tcg_gen_or_i32(rd, rd, tmp); | |
3738 | ||
3739 | tcg_gen_shri_i32(t1, t1, 8); | |
3740 | tcg_gen_andi_i32(t1, t1, 0x00ff00ff); | |
3741 | tcg_gen_andi_i32(tmp, t0, 0xff00ff00); | |
3742 | tcg_gen_or_i32(t1, t1, tmp); | |
3743 | tcg_gen_mov_i32(t0, rd); | |
3744 | ||
3745 | dead_tmp(tmp); | |
3746 | dead_tmp(rd); | |
3747 | } | |
3748 | ||
3749 | static void gen_neon_trn_u16(TCGv t0, TCGv t1) | |
3750 | { | |
3751 | TCGv rd, tmp; | |
3752 | ||
3753 | rd = new_tmp(); | |
3754 | tmp = new_tmp(); | |
3755 | ||
3756 | tcg_gen_shli_i32(rd, t0, 16); | |
3757 | tcg_gen_andi_i32(tmp, t1, 0xffff); | |
3758 | tcg_gen_or_i32(rd, rd, tmp); | |
3759 | tcg_gen_shri_i32(t1, t1, 16); | |
3760 | tcg_gen_andi_i32(tmp, t0, 0xffff0000); | |
3761 | tcg_gen_or_i32(t1, t1, tmp); | |
3762 | tcg_gen_mov_i32(t0, rd); | |
3763 | ||
3764 | dead_tmp(tmp); | |
3765 | dead_tmp(rd); | |
3766 | } | |
3767 | ||
3768 | ||
9ee6e8bb PB |
3769 | static struct { |
3770 | int nregs; | |
3771 | int interleave; | |
3772 | int spacing; | |
3773 | } neon_ls_element_type[11] = { | |
3774 | {4, 4, 1}, | |
3775 | {4, 4, 2}, | |
3776 | {4, 1, 1}, | |
3777 | {4, 2, 1}, | |
3778 | {3, 3, 1}, | |
3779 | {3, 3, 2}, | |
3780 | {3, 1, 1}, | |
3781 | {1, 1, 1}, | |
3782 | {2, 2, 1}, | |
3783 | {2, 2, 2}, | |
3784 | {2, 1, 1} | |
3785 | }; | |
3786 | ||
3787 | /* Translate a NEON load/store element instruction. Return nonzero if the | |
3788 | instruction is invalid. */ | |
3789 | static int disas_neon_ls_insn(CPUState * env, DisasContext *s, uint32_t insn) | |
3790 | { | |
3791 | int rd, rn, rm; | |
3792 | int op; | |
3793 | int nregs; | |
3794 | int interleave; | |
84496233 | 3795 | int spacing; |
9ee6e8bb PB |
3796 | int stride; |
3797 | int size; | |
3798 | int reg; | |
3799 | int pass; | |
3800 | int load; | |
3801 | int shift; | |
9ee6e8bb | 3802 | int n; |
1b2b1e54 | 3803 | TCGv addr; |
b0109805 | 3804 | TCGv tmp; |
8f8e3aa4 | 3805 | TCGv tmp2; |
84496233 | 3806 | TCGv_i64 tmp64; |
9ee6e8bb | 3807 | |
5df8bac1 | 3808 | if (!s->vfp_enabled) |
9ee6e8bb PB |
3809 | return 1; |
3810 | VFP_DREG_D(rd, insn); | |
3811 | rn = (insn >> 16) & 0xf; | |
3812 | rm = insn & 0xf; | |
3813 | load = (insn & (1 << 21)) != 0; | |
1b2b1e54 | 3814 | addr = new_tmp(); |
9ee6e8bb PB |
3815 | if ((insn & (1 << 23)) == 0) { |
3816 | /* Load store all elements. */ | |
3817 | op = (insn >> 8) & 0xf; | |
3818 | size = (insn >> 6) & 3; | |
84496233 | 3819 | if (op > 10) |
9ee6e8bb PB |
3820 | return 1; |
3821 | nregs = neon_ls_element_type[op].nregs; | |
3822 | interleave = neon_ls_element_type[op].interleave; | |
84496233 JR |
3823 | spacing = neon_ls_element_type[op].spacing; |
3824 | if (size == 3 && (interleave | spacing) != 1) | |
3825 | return 1; | |
dcc65026 | 3826 | load_reg_var(s, addr, rn); |
9ee6e8bb PB |
3827 | stride = (1 << size) * interleave; |
3828 | for (reg = 0; reg < nregs; reg++) { | |
3829 | if (interleave > 2 || (interleave == 2 && nregs == 2)) { | |
dcc65026 AJ |
3830 | load_reg_var(s, addr, rn); |
3831 | tcg_gen_addi_i32(addr, addr, (1 << size) * reg); | |
9ee6e8bb | 3832 | } else if (interleave == 2 && nregs == 4 && reg == 2) { |
dcc65026 AJ |
3833 | load_reg_var(s, addr, rn); |
3834 | tcg_gen_addi_i32(addr, addr, 1 << size); | |
9ee6e8bb | 3835 | } |
84496233 JR |
3836 | if (size == 3) { |
3837 | if (load) { | |
3838 | tmp64 = gen_ld64(addr, IS_USER(s)); | |
3839 | neon_store_reg64(tmp64, rd); | |
3840 | tcg_temp_free_i64(tmp64); | |
3841 | } else { | |
3842 | tmp64 = tcg_temp_new_i64(); | |
3843 | neon_load_reg64(tmp64, rd); | |
3844 | gen_st64(tmp64, addr, IS_USER(s)); | |
3845 | } | |
3846 | tcg_gen_addi_i32(addr, addr, stride); | |
3847 | } else { | |
3848 | for (pass = 0; pass < 2; pass++) { | |
3849 | if (size == 2) { | |
3850 | if (load) { | |
3851 | tmp = gen_ld32(addr, IS_USER(s)); | |
3852 | neon_store_reg(rd, pass, tmp); | |
3853 | } else { | |
3854 | tmp = neon_load_reg(rd, pass); | |
3855 | gen_st32(tmp, addr, IS_USER(s)); | |
3856 | } | |
1b2b1e54 | 3857 | tcg_gen_addi_i32(addr, addr, stride); |
84496233 JR |
3858 | } else if (size == 1) { |
3859 | if (load) { | |
3860 | tmp = gen_ld16u(addr, IS_USER(s)); | |
3861 | tcg_gen_addi_i32(addr, addr, stride); | |
3862 | tmp2 = gen_ld16u(addr, IS_USER(s)); | |
3863 | tcg_gen_addi_i32(addr, addr, stride); | |
41ba8341 PB |
3864 | tcg_gen_shli_i32(tmp2, tmp2, 16); |
3865 | tcg_gen_or_i32(tmp, tmp, tmp2); | |
84496233 JR |
3866 | dead_tmp(tmp2); |
3867 | neon_store_reg(rd, pass, tmp); | |
3868 | } else { | |
3869 | tmp = neon_load_reg(rd, pass); | |
3870 | tmp2 = new_tmp(); | |
3871 | tcg_gen_shri_i32(tmp2, tmp, 16); | |
3872 | gen_st16(tmp, addr, IS_USER(s)); | |
3873 | tcg_gen_addi_i32(addr, addr, stride); | |
3874 | gen_st16(tmp2, addr, IS_USER(s)); | |
1b2b1e54 | 3875 | tcg_gen_addi_i32(addr, addr, stride); |
9ee6e8bb | 3876 | } |
84496233 JR |
3877 | } else /* size == 0 */ { |
3878 | if (load) { | |
3879 | TCGV_UNUSED(tmp2); | |
3880 | for (n = 0; n < 4; n++) { | |
3881 | tmp = gen_ld8u(addr, IS_USER(s)); | |
3882 | tcg_gen_addi_i32(addr, addr, stride); | |
3883 | if (n == 0) { | |
3884 | tmp2 = tmp; | |
3885 | } else { | |
41ba8341 PB |
3886 | tcg_gen_shli_i32(tmp, tmp, n * 8); |
3887 | tcg_gen_or_i32(tmp2, tmp2, tmp); | |
84496233 JR |
3888 | dead_tmp(tmp); |
3889 | } | |
9ee6e8bb | 3890 | } |
84496233 JR |
3891 | neon_store_reg(rd, pass, tmp2); |
3892 | } else { | |
3893 | tmp2 = neon_load_reg(rd, pass); | |
3894 | for (n = 0; n < 4; n++) { | |
3895 | tmp = new_tmp(); | |
3896 | if (n == 0) { | |
3897 | tcg_gen_mov_i32(tmp, tmp2); | |
3898 | } else { | |
3899 | tcg_gen_shri_i32(tmp, tmp2, n * 8); | |
3900 | } | |
3901 | gen_st8(tmp, addr, IS_USER(s)); | |
3902 | tcg_gen_addi_i32(addr, addr, stride); | |
3903 | } | |
3904 | dead_tmp(tmp2); | |
9ee6e8bb PB |
3905 | } |
3906 | } | |
3907 | } | |
3908 | } | |
84496233 | 3909 | rd += spacing; |
9ee6e8bb PB |
3910 | } |
3911 | stride = nregs * 8; | |
3912 | } else { | |
3913 | size = (insn >> 10) & 3; | |
3914 | if (size == 3) { | |
3915 | /* Load single element to all lanes. */ | |
3916 | if (!load) | |
3917 | return 1; | |
3918 | size = (insn >> 6) & 3; | |
3919 | nregs = ((insn >> 8) & 3) + 1; | |
3920 | stride = (insn & (1 << 5)) ? 2 : 1; | |
dcc65026 | 3921 | load_reg_var(s, addr, rn); |
9ee6e8bb PB |
3922 | for (reg = 0; reg < nregs; reg++) { |
3923 | switch (size) { | |
3924 | case 0: | |
1b2b1e54 | 3925 | tmp = gen_ld8u(addr, IS_USER(s)); |
ad69471c | 3926 | gen_neon_dup_u8(tmp, 0); |
9ee6e8bb PB |
3927 | break; |
3928 | case 1: | |
1b2b1e54 | 3929 | tmp = gen_ld16u(addr, IS_USER(s)); |
ad69471c | 3930 | gen_neon_dup_low16(tmp); |
9ee6e8bb PB |
3931 | break; |
3932 | case 2: | |
1b2b1e54 | 3933 | tmp = gen_ld32(addr, IS_USER(s)); |
9ee6e8bb PB |
3934 | break; |
3935 | case 3: | |
3936 | return 1; | |
a50f5b91 PB |
3937 | default: /* Avoid compiler warnings. */ |
3938 | abort(); | |
99c475ab | 3939 | } |
1b2b1e54 | 3940 | tcg_gen_addi_i32(addr, addr, 1 << size); |
ad69471c PB |
3941 | tmp2 = new_tmp(); |
3942 | tcg_gen_mov_i32(tmp2, tmp); | |
3943 | neon_store_reg(rd, 0, tmp2); | |
3018f259 | 3944 | neon_store_reg(rd, 1, tmp); |
9ee6e8bb PB |
3945 | rd += stride; |
3946 | } | |
3947 | stride = (1 << size) * nregs; | |
3948 | } else { | |
3949 | /* Single element. */ | |
3950 | pass = (insn >> 7) & 1; | |
3951 | switch (size) { | |
3952 | case 0: | |
3953 | shift = ((insn >> 5) & 3) * 8; | |
9ee6e8bb PB |
3954 | stride = 1; |
3955 | break; | |
3956 | case 1: | |
3957 | shift = ((insn >> 6) & 1) * 16; | |
9ee6e8bb PB |
3958 | stride = (insn & (1 << 5)) ? 2 : 1; |
3959 | break; | |
3960 | case 2: | |
3961 | shift = 0; | |
9ee6e8bb PB |
3962 | stride = (insn & (1 << 6)) ? 2 : 1; |
3963 | break; | |
3964 | default: | |
3965 | abort(); | |
3966 | } | |
3967 | nregs = ((insn >> 8) & 3) + 1; | |
dcc65026 | 3968 | load_reg_var(s, addr, rn); |
9ee6e8bb PB |
3969 | for (reg = 0; reg < nregs; reg++) { |
3970 | if (load) { | |
9ee6e8bb PB |
3971 | switch (size) { |
3972 | case 0: | |
1b2b1e54 | 3973 | tmp = gen_ld8u(addr, IS_USER(s)); |
9ee6e8bb PB |
3974 | break; |
3975 | case 1: | |
1b2b1e54 | 3976 | tmp = gen_ld16u(addr, IS_USER(s)); |
9ee6e8bb PB |
3977 | break; |
3978 | case 2: | |
1b2b1e54 | 3979 | tmp = gen_ld32(addr, IS_USER(s)); |
9ee6e8bb | 3980 | break; |
a50f5b91 PB |
3981 | default: /* Avoid compiler warnings. */ |
3982 | abort(); | |
9ee6e8bb PB |
3983 | } |
3984 | if (size != 2) { | |
8f8e3aa4 PB |
3985 | tmp2 = neon_load_reg(rd, pass); |
3986 | gen_bfi(tmp, tmp2, tmp, shift, size ? 0xffff : 0xff); | |
3987 | dead_tmp(tmp2); | |
9ee6e8bb | 3988 | } |
8f8e3aa4 | 3989 | neon_store_reg(rd, pass, tmp); |
9ee6e8bb | 3990 | } else { /* Store */ |
8f8e3aa4 PB |
3991 | tmp = neon_load_reg(rd, pass); |
3992 | if (shift) | |
3993 | tcg_gen_shri_i32(tmp, tmp, shift); | |
9ee6e8bb PB |
3994 | switch (size) { |
3995 | case 0: | |
1b2b1e54 | 3996 | gen_st8(tmp, addr, IS_USER(s)); |
9ee6e8bb PB |
3997 | break; |
3998 | case 1: | |
1b2b1e54 | 3999 | gen_st16(tmp, addr, IS_USER(s)); |
9ee6e8bb PB |
4000 | break; |
4001 | case 2: | |
1b2b1e54 | 4002 | gen_st32(tmp, addr, IS_USER(s)); |
9ee6e8bb | 4003 | break; |
99c475ab | 4004 | } |
99c475ab | 4005 | } |
9ee6e8bb | 4006 | rd += stride; |
1b2b1e54 | 4007 | tcg_gen_addi_i32(addr, addr, 1 << size); |
99c475ab | 4008 | } |
9ee6e8bb | 4009 | stride = nregs * (1 << size); |
99c475ab | 4010 | } |
9ee6e8bb | 4011 | } |
1b2b1e54 | 4012 | dead_tmp(addr); |
9ee6e8bb | 4013 | if (rm != 15) { |
b26eefb6 PB |
4014 | TCGv base; |
4015 | ||
4016 | base = load_reg(s, rn); | |
9ee6e8bb | 4017 | if (rm == 13) { |
b26eefb6 | 4018 | tcg_gen_addi_i32(base, base, stride); |
9ee6e8bb | 4019 | } else { |
b26eefb6 PB |
4020 | TCGv index; |
4021 | index = load_reg(s, rm); | |
4022 | tcg_gen_add_i32(base, base, index); | |
4023 | dead_tmp(index); | |
9ee6e8bb | 4024 | } |
b26eefb6 | 4025 | store_reg(s, rn, base); |
9ee6e8bb PB |
4026 | } |
4027 | return 0; | |
4028 | } | |
3b46e624 | 4029 | |
8f8e3aa4 PB |
4030 | /* Bitwise select. dest = c ? t : f. Clobbers T and F. */ |
4031 | static void gen_neon_bsl(TCGv dest, TCGv t, TCGv f, TCGv c) | |
4032 | { | |
4033 | tcg_gen_and_i32(t, t, c); | |
f669df27 | 4034 | tcg_gen_andc_i32(f, f, c); |
8f8e3aa4 PB |
4035 | tcg_gen_or_i32(dest, t, f); |
4036 | } | |
4037 | ||
a7812ae4 | 4038 | static inline void gen_neon_narrow(int size, TCGv dest, TCGv_i64 src) |
ad69471c PB |
4039 | { |
4040 | switch (size) { | |
4041 | case 0: gen_helper_neon_narrow_u8(dest, src); break; | |
4042 | case 1: gen_helper_neon_narrow_u16(dest, src); break; | |
4043 | case 2: tcg_gen_trunc_i64_i32(dest, src); break; | |
4044 | default: abort(); | |
4045 | } | |
4046 | } | |
4047 | ||
a7812ae4 | 4048 | static inline void gen_neon_narrow_sats(int size, TCGv dest, TCGv_i64 src) |
ad69471c PB |
4049 | { |
4050 | switch (size) { | |
4051 | case 0: gen_helper_neon_narrow_sat_s8(dest, cpu_env, src); break; | |
4052 | case 1: gen_helper_neon_narrow_sat_s16(dest, cpu_env, src); break; | |
4053 | case 2: gen_helper_neon_narrow_sat_s32(dest, cpu_env, src); break; | |
4054 | default: abort(); | |
4055 | } | |
4056 | } | |
4057 | ||
a7812ae4 | 4058 | static inline void gen_neon_narrow_satu(int size, TCGv dest, TCGv_i64 src) |
ad69471c PB |
4059 | { |
4060 | switch (size) { | |
4061 | case 0: gen_helper_neon_narrow_sat_u8(dest, cpu_env, src); break; | |
4062 | case 1: gen_helper_neon_narrow_sat_u16(dest, cpu_env, src); break; | |
4063 | case 2: gen_helper_neon_narrow_sat_u32(dest, cpu_env, src); break; | |
4064 | default: abort(); | |
4065 | } | |
4066 | } | |
4067 | ||
af1bbf30 JR |
4068 | static inline void gen_neon_unarrow_sats(int size, TCGv dest, TCGv_i64 src) |
4069 | { | |
4070 | switch (size) { | |
4071 | case 0: gen_helper_neon_unarrow_sat8(dest, cpu_env, src); break; | |
4072 | case 1: gen_helper_neon_unarrow_sat16(dest, cpu_env, src); break; | |
4073 | case 2: gen_helper_neon_unarrow_sat32(dest, cpu_env, src); break; | |
4074 | default: abort(); | |
4075 | } | |
4076 | } | |
4077 | ||
ad69471c PB |
4078 | static inline void gen_neon_shift_narrow(int size, TCGv var, TCGv shift, |
4079 | int q, int u) | |
4080 | { | |
4081 | if (q) { | |
4082 | if (u) { | |
4083 | switch (size) { | |
4084 | case 1: gen_helper_neon_rshl_u16(var, var, shift); break; | |
4085 | case 2: gen_helper_neon_rshl_u32(var, var, shift); break; | |
4086 | default: abort(); | |
4087 | } | |
4088 | } else { | |
4089 | switch (size) { | |
4090 | case 1: gen_helper_neon_rshl_s16(var, var, shift); break; | |
4091 | case 2: gen_helper_neon_rshl_s32(var, var, shift); break; | |
4092 | default: abort(); | |
4093 | } | |
4094 | } | |
4095 | } else { | |
4096 | if (u) { | |
4097 | switch (size) { | |
4098 | case 1: gen_helper_neon_rshl_u16(var, var, shift); break; | |
4099 | case 2: gen_helper_neon_rshl_u32(var, var, shift); break; | |
4100 | default: abort(); | |
4101 | } | |
4102 | } else { | |
4103 | switch (size) { | |
4104 | case 1: gen_helper_neon_shl_s16(var, var, shift); break; | |
4105 | case 2: gen_helper_neon_shl_s32(var, var, shift); break; | |
4106 | default: abort(); | |
4107 | } | |
4108 | } | |
4109 | } | |
4110 | } | |
4111 | ||
a7812ae4 | 4112 | static inline void gen_neon_widen(TCGv_i64 dest, TCGv src, int size, int u) |
ad69471c PB |
4113 | { |
4114 | if (u) { | |
4115 | switch (size) { | |
4116 | case 0: gen_helper_neon_widen_u8(dest, src); break; | |
4117 | case 1: gen_helper_neon_widen_u16(dest, src); break; | |
4118 | case 2: tcg_gen_extu_i32_i64(dest, src); break; | |
4119 | default: abort(); | |
4120 | } | |
4121 | } else { | |
4122 | switch (size) { | |
4123 | case 0: gen_helper_neon_widen_s8(dest, src); break; | |
4124 | case 1: gen_helper_neon_widen_s16(dest, src); break; | |
4125 | case 2: tcg_gen_ext_i32_i64(dest, src); break; | |
4126 | default: abort(); | |
4127 | } | |
4128 | } | |
4129 | dead_tmp(src); | |
4130 | } | |
4131 | ||
4132 | static inline void gen_neon_addl(int size) | |
4133 | { | |
4134 | switch (size) { | |
4135 | case 0: gen_helper_neon_addl_u16(CPU_V001); break; | |
4136 | case 1: gen_helper_neon_addl_u32(CPU_V001); break; | |
4137 | case 2: tcg_gen_add_i64(CPU_V001); break; | |
4138 | default: abort(); | |
4139 | } | |
4140 | } | |
4141 | ||
4142 | static inline void gen_neon_subl(int size) | |
4143 | { | |
4144 | switch (size) { | |
4145 | case 0: gen_helper_neon_subl_u16(CPU_V001); break; | |
4146 | case 1: gen_helper_neon_subl_u32(CPU_V001); break; | |
4147 | case 2: tcg_gen_sub_i64(CPU_V001); break; | |
4148 | default: abort(); | |
4149 | } | |
4150 | } | |
4151 | ||
a7812ae4 | 4152 | static inline void gen_neon_negl(TCGv_i64 var, int size) |
ad69471c PB |
4153 | { |
4154 | switch (size) { | |
4155 | case 0: gen_helper_neon_negl_u16(var, var); break; | |
4156 | case 1: gen_helper_neon_negl_u32(var, var); break; | |
4157 | case 2: gen_helper_neon_negl_u64(var, var); break; | |
4158 | default: abort(); | |
4159 | } | |
4160 | } | |
4161 | ||
a7812ae4 | 4162 | static inline void gen_neon_addl_saturate(TCGv_i64 op0, TCGv_i64 op1, int size) |
ad69471c PB |
4163 | { |
4164 | switch (size) { | |
4165 | case 1: gen_helper_neon_addl_saturate_s32(op0, cpu_env, op0, op1); break; | |
4166 | case 2: gen_helper_neon_addl_saturate_s64(op0, cpu_env, op0, op1); break; | |
4167 | default: abort(); | |
4168 | } | |
4169 | } | |
4170 | ||
a7812ae4 | 4171 | static inline void gen_neon_mull(TCGv_i64 dest, TCGv a, TCGv b, int size, int u) |
ad69471c | 4172 | { |
a7812ae4 | 4173 | TCGv_i64 tmp; |
ad69471c PB |
4174 | |
4175 | switch ((size << 1) | u) { | |
4176 | case 0: gen_helper_neon_mull_s8(dest, a, b); break; | |
4177 | case 1: gen_helper_neon_mull_u8(dest, a, b); break; | |
4178 | case 2: gen_helper_neon_mull_s16(dest, a, b); break; | |
4179 | case 3: gen_helper_neon_mull_u16(dest, a, b); break; | |
4180 | case 4: | |
4181 | tmp = gen_muls_i64_i32(a, b); | |
4182 | tcg_gen_mov_i64(dest, tmp); | |
4183 | break; | |
4184 | case 5: | |
4185 | tmp = gen_mulu_i64_i32(a, b); | |
4186 | tcg_gen_mov_i64(dest, tmp); | |
4187 | break; | |
4188 | default: abort(); | |
4189 | } | |
c6067f04 CL |
4190 | |
4191 | /* gen_helper_neon_mull_[su]{8|16} do not free their parameters. | |
4192 | Don't forget to clean them now. */ | |
4193 | if (size < 2) { | |
4194 | dead_tmp(a); | |
4195 | dead_tmp(b); | |
4196 | } | |
ad69471c PB |
4197 | } |
4198 | ||
9ee6e8bb PB |
4199 | /* Translate a NEON data processing instruction. Return nonzero if the |
4200 | instruction is invalid. | |
ad69471c PB |
4201 | We process data in a mixture of 32-bit and 64-bit chunks. |
4202 | Mostly we use 32-bit chunks so we can use normal scalar instructions. */ | |
2c0262af | 4203 | |
9ee6e8bb PB |
4204 | static int disas_neon_data_insn(CPUState * env, DisasContext *s, uint32_t insn) |
4205 | { | |
4206 | int op; | |
4207 | int q; | |
4208 | int rd, rn, rm; | |
4209 | int size; | |
4210 | int shift; | |
4211 | int pass; | |
4212 | int count; | |
4213 | int pairwise; | |
4214 | int u; | |
4215 | int n; | |
ca9a32e4 | 4216 | uint32_t imm, mask; |
b75263d6 | 4217 | TCGv tmp, tmp2, tmp3, tmp4, tmp5; |
a7812ae4 | 4218 | TCGv_i64 tmp64; |
9ee6e8bb | 4219 | |
5df8bac1 | 4220 | if (!s->vfp_enabled) |
9ee6e8bb PB |
4221 | return 1; |
4222 | q = (insn & (1 << 6)) != 0; | |
4223 | u = (insn >> 24) & 1; | |
4224 | VFP_DREG_D(rd, insn); | |
4225 | VFP_DREG_N(rn, insn); | |
4226 | VFP_DREG_M(rm, insn); | |
4227 | size = (insn >> 20) & 3; | |
4228 | if ((insn & (1 << 23)) == 0) { | |
4229 | /* Three register same length. */ | |
4230 | op = ((insn >> 7) & 0x1e) | ((insn >> 4) & 1); | |
ad69471c PB |
4231 | if (size == 3 && (op == 1 || op == 5 || op == 8 || op == 9 |
4232 | || op == 10 || op == 11 || op == 16)) { | |
4233 | /* 64-bit element instructions. */ | |
9ee6e8bb | 4234 | for (pass = 0; pass < (q ? 2 : 1); pass++) { |
ad69471c PB |
4235 | neon_load_reg64(cpu_V0, rn + pass); |
4236 | neon_load_reg64(cpu_V1, rm + pass); | |
9ee6e8bb PB |
4237 | switch (op) { |
4238 | case 1: /* VQADD */ | |
4239 | if (u) { | |
72902672 CL |
4240 | gen_helper_neon_qadd_u64(cpu_V0, cpu_env, |
4241 | cpu_V0, cpu_V1); | |
2c0262af | 4242 | } else { |
72902672 CL |
4243 | gen_helper_neon_qadd_s64(cpu_V0, cpu_env, |
4244 | cpu_V0, cpu_V1); | |
2c0262af | 4245 | } |
9ee6e8bb PB |
4246 | break; |
4247 | case 5: /* VQSUB */ | |
4248 | if (u) { | |
72902672 CL |
4249 | gen_helper_neon_qsub_u64(cpu_V0, cpu_env, |
4250 | cpu_V0, cpu_V1); | |
ad69471c | 4251 | } else { |
72902672 CL |
4252 | gen_helper_neon_qsub_s64(cpu_V0, cpu_env, |
4253 | cpu_V0, cpu_V1); | |
ad69471c PB |
4254 | } |
4255 | break; | |
4256 | case 8: /* VSHL */ | |
4257 | if (u) { | |
4258 | gen_helper_neon_shl_u64(cpu_V0, cpu_V1, cpu_V0); | |
4259 | } else { | |
4260 | gen_helper_neon_shl_s64(cpu_V0, cpu_V1, cpu_V0); | |
4261 | } | |
4262 | break; | |
4263 | case 9: /* VQSHL */ | |
4264 | if (u) { | |
4265 | gen_helper_neon_qshl_u64(cpu_V0, cpu_env, | |
def126ce | 4266 | cpu_V1, cpu_V0); |
ad69471c | 4267 | } else { |
def126ce | 4268 | gen_helper_neon_qshl_s64(cpu_V0, cpu_env, |
ad69471c PB |
4269 | cpu_V1, cpu_V0); |
4270 | } | |
4271 | break; | |
4272 | case 10: /* VRSHL */ | |
4273 | if (u) { | |
4274 | gen_helper_neon_rshl_u64(cpu_V0, cpu_V1, cpu_V0); | |
1e8d4eec | 4275 | } else { |
ad69471c PB |
4276 | gen_helper_neon_rshl_s64(cpu_V0, cpu_V1, cpu_V0); |
4277 | } | |
4278 | break; | |
4279 | case 11: /* VQRSHL */ | |
4280 | if (u) { | |
4281 | gen_helper_neon_qrshl_u64(cpu_V0, cpu_env, | |
4282 | cpu_V1, cpu_V0); | |
4283 | } else { | |
4284 | gen_helper_neon_qrshl_s64(cpu_V0, cpu_env, | |
4285 | cpu_V1, cpu_V0); | |
1e8d4eec | 4286 | } |
9ee6e8bb PB |
4287 | break; |
4288 | case 16: | |
4289 | if (u) { | |
ad69471c | 4290 | tcg_gen_sub_i64(CPU_V001); |
9ee6e8bb | 4291 | } else { |
ad69471c | 4292 | tcg_gen_add_i64(CPU_V001); |
9ee6e8bb PB |
4293 | } |
4294 | break; | |
4295 | default: | |
4296 | abort(); | |
2c0262af | 4297 | } |
ad69471c | 4298 | neon_store_reg64(cpu_V0, rd + pass); |
2c0262af | 4299 | } |
9ee6e8bb | 4300 | return 0; |
2c0262af | 4301 | } |
9ee6e8bb PB |
4302 | switch (op) { |
4303 | case 8: /* VSHL */ | |
4304 | case 9: /* VQSHL */ | |
4305 | case 10: /* VRSHL */ | |
ad69471c | 4306 | case 11: /* VQRSHL */ |
9ee6e8bb | 4307 | { |
ad69471c PB |
4308 | int rtmp; |
4309 | /* Shift instruction operands are reversed. */ | |
4310 | rtmp = rn; | |
9ee6e8bb | 4311 | rn = rm; |
ad69471c | 4312 | rm = rtmp; |
9ee6e8bb PB |
4313 | pairwise = 0; |
4314 | } | |
2c0262af | 4315 | break; |
9ee6e8bb PB |
4316 | case 20: /* VPMAX */ |
4317 | case 21: /* VPMIN */ | |
4318 | case 23: /* VPADD */ | |
4319 | pairwise = 1; | |
2c0262af | 4320 | break; |
9ee6e8bb PB |
4321 | case 26: /* VPADD (float) */ |
4322 | pairwise = (u && size < 2); | |
2c0262af | 4323 | break; |
9ee6e8bb PB |
4324 | case 30: /* VPMIN/VPMAX (float) */ |
4325 | pairwise = u; | |
2c0262af | 4326 | break; |
9ee6e8bb PB |
4327 | default: |
4328 | pairwise = 0; | |
2c0262af | 4329 | break; |
9ee6e8bb | 4330 | } |
dd8fbd78 | 4331 | |
9ee6e8bb PB |
4332 | for (pass = 0; pass < (q ? 4 : 2); pass++) { |
4333 | ||
4334 | if (pairwise) { | |
4335 | /* Pairwise. */ | |
4336 | if (q) | |
4337 | n = (pass & 1) * 2; | |
2c0262af | 4338 | else |
9ee6e8bb PB |
4339 | n = 0; |
4340 | if (pass < q + 1) { | |
dd8fbd78 FN |
4341 | tmp = neon_load_reg(rn, n); |
4342 | tmp2 = neon_load_reg(rn, n + 1); | |
9ee6e8bb | 4343 | } else { |
dd8fbd78 FN |
4344 | tmp = neon_load_reg(rm, n); |
4345 | tmp2 = neon_load_reg(rm, n + 1); | |
9ee6e8bb PB |
4346 | } |
4347 | } else { | |
4348 | /* Elementwise. */ | |
dd8fbd78 FN |
4349 | tmp = neon_load_reg(rn, pass); |
4350 | tmp2 = neon_load_reg(rm, pass); | |
9ee6e8bb PB |
4351 | } |
4352 | switch (op) { | |
4353 | case 0: /* VHADD */ | |
4354 | GEN_NEON_INTEGER_OP(hadd); | |
4355 | break; | |
4356 | case 1: /* VQADD */ | |
ad69471c | 4357 | GEN_NEON_INTEGER_OP_ENV(qadd); |
2c0262af | 4358 | break; |
9ee6e8bb PB |
4359 | case 2: /* VRHADD */ |
4360 | GEN_NEON_INTEGER_OP(rhadd); | |
2c0262af | 4361 | break; |
9ee6e8bb PB |
4362 | case 3: /* Logic ops. */ |
4363 | switch ((u << 2) | size) { | |
4364 | case 0: /* VAND */ | |
dd8fbd78 | 4365 | tcg_gen_and_i32(tmp, tmp, tmp2); |
9ee6e8bb PB |
4366 | break; |
4367 | case 1: /* BIC */ | |
f669df27 | 4368 | tcg_gen_andc_i32(tmp, tmp, tmp2); |
9ee6e8bb PB |
4369 | break; |
4370 | case 2: /* VORR */ | |
dd8fbd78 | 4371 | tcg_gen_or_i32(tmp, tmp, tmp2); |
9ee6e8bb PB |
4372 | break; |
4373 | case 3: /* VORN */ | |
f669df27 | 4374 | tcg_gen_orc_i32(tmp, tmp, tmp2); |
9ee6e8bb PB |
4375 | break; |
4376 | case 4: /* VEOR */ | |
dd8fbd78 | 4377 | tcg_gen_xor_i32(tmp, tmp, tmp2); |
9ee6e8bb PB |
4378 | break; |
4379 | case 5: /* VBSL */ | |
dd8fbd78 FN |
4380 | tmp3 = neon_load_reg(rd, pass); |
4381 | gen_neon_bsl(tmp, tmp, tmp2, tmp3); | |
4382 | dead_tmp(tmp3); | |
9ee6e8bb PB |
4383 | break; |
4384 | case 6: /* VBIT */ | |
dd8fbd78 FN |
4385 | tmp3 = neon_load_reg(rd, pass); |
4386 | gen_neon_bsl(tmp, tmp, tmp3, tmp2); | |
4387 | dead_tmp(tmp3); | |
9ee6e8bb PB |
4388 | break; |
4389 | case 7: /* VBIF */ | |
dd8fbd78 FN |
4390 | tmp3 = neon_load_reg(rd, pass); |
4391 | gen_neon_bsl(tmp, tmp3, tmp, tmp2); | |
4392 | dead_tmp(tmp3); | |
9ee6e8bb | 4393 | break; |
2c0262af FB |
4394 | } |
4395 | break; | |
9ee6e8bb PB |
4396 | case 4: /* VHSUB */ |
4397 | GEN_NEON_INTEGER_OP(hsub); | |
4398 | break; | |
4399 | case 5: /* VQSUB */ | |
ad69471c | 4400 | GEN_NEON_INTEGER_OP_ENV(qsub); |
2c0262af | 4401 | break; |
9ee6e8bb PB |
4402 | case 6: /* VCGT */ |
4403 | GEN_NEON_INTEGER_OP(cgt); | |
4404 | break; | |
4405 | case 7: /* VCGE */ | |
4406 | GEN_NEON_INTEGER_OP(cge); | |
4407 | break; | |
4408 | case 8: /* VSHL */ | |
ad69471c | 4409 | GEN_NEON_INTEGER_OP(shl); |
2c0262af | 4410 | break; |
9ee6e8bb | 4411 | case 9: /* VQSHL */ |
ad69471c | 4412 | GEN_NEON_INTEGER_OP_ENV(qshl); |
2c0262af | 4413 | break; |
9ee6e8bb | 4414 | case 10: /* VRSHL */ |
ad69471c | 4415 | GEN_NEON_INTEGER_OP(rshl); |
2c0262af | 4416 | break; |
9ee6e8bb | 4417 | case 11: /* VQRSHL */ |
ad69471c | 4418 | GEN_NEON_INTEGER_OP_ENV(qrshl); |
9ee6e8bb PB |
4419 | break; |
4420 | case 12: /* VMAX */ | |
4421 | GEN_NEON_INTEGER_OP(max); | |
4422 | break; | |
4423 | case 13: /* VMIN */ | |
4424 | GEN_NEON_INTEGER_OP(min); | |
4425 | break; | |
4426 | case 14: /* VABD */ | |
4427 | GEN_NEON_INTEGER_OP(abd); | |
4428 | break; | |
4429 | case 15: /* VABA */ | |
4430 | GEN_NEON_INTEGER_OP(abd); | |
dd8fbd78 FN |
4431 | dead_tmp(tmp2); |
4432 | tmp2 = neon_load_reg(rd, pass); | |
4433 | gen_neon_add(size, tmp, tmp2); | |
9ee6e8bb PB |
4434 | break; |
4435 | case 16: | |
4436 | if (!u) { /* VADD */ | |
dd8fbd78 | 4437 | if (gen_neon_add(size, tmp, tmp2)) |
9ee6e8bb PB |
4438 | return 1; |
4439 | } else { /* VSUB */ | |
4440 | switch (size) { | |
dd8fbd78 FN |
4441 | case 0: gen_helper_neon_sub_u8(tmp, tmp, tmp2); break; |
4442 | case 1: gen_helper_neon_sub_u16(tmp, tmp, tmp2); break; | |
4443 | case 2: tcg_gen_sub_i32(tmp, tmp, tmp2); break; | |
9ee6e8bb PB |
4444 | default: return 1; |
4445 | } | |
4446 | } | |
4447 | break; | |
4448 | case 17: | |
4449 | if (!u) { /* VTST */ | |
4450 | switch (size) { | |
dd8fbd78 FN |
4451 | case 0: gen_helper_neon_tst_u8(tmp, tmp, tmp2); break; |
4452 | case 1: gen_helper_neon_tst_u16(tmp, tmp, tmp2); break; | |
4453 | case 2: gen_helper_neon_tst_u32(tmp, tmp, tmp2); break; | |
9ee6e8bb PB |
4454 | default: return 1; |
4455 | } | |
4456 | } else { /* VCEQ */ | |
4457 | switch (size) { | |
dd8fbd78 FN |
4458 | case 0: gen_helper_neon_ceq_u8(tmp, tmp, tmp2); break; |
4459 | case 1: gen_helper_neon_ceq_u16(tmp, tmp, tmp2); break; | |
4460 | case 2: gen_helper_neon_ceq_u32(tmp, tmp, tmp2); break; | |
9ee6e8bb PB |
4461 | default: return 1; |
4462 | } | |
4463 | } | |
4464 | break; | |
4465 | case 18: /* Multiply. */ | |
4466 | switch (size) { | |
dd8fbd78 FN |
4467 | case 0: gen_helper_neon_mul_u8(tmp, tmp, tmp2); break; |
4468 | case 1: gen_helper_neon_mul_u16(tmp, tmp, tmp2); break; | |
4469 | case 2: tcg_gen_mul_i32(tmp, tmp, tmp2); break; | |
9ee6e8bb PB |
4470 | default: return 1; |
4471 | } | |
dd8fbd78 FN |
4472 | dead_tmp(tmp2); |
4473 | tmp2 = neon_load_reg(rd, pass); | |
9ee6e8bb | 4474 | if (u) { /* VMLS */ |
dd8fbd78 | 4475 | gen_neon_rsb(size, tmp, tmp2); |
9ee6e8bb | 4476 | } else { /* VMLA */ |
dd8fbd78 | 4477 | gen_neon_add(size, tmp, tmp2); |
9ee6e8bb PB |
4478 | } |
4479 | break; | |
4480 | case 19: /* VMUL */ | |
4481 | if (u) { /* polynomial */ | |
dd8fbd78 | 4482 | gen_helper_neon_mul_p8(tmp, tmp, tmp2); |
9ee6e8bb PB |
4483 | } else { /* Integer */ |
4484 | switch (size) { | |
dd8fbd78 FN |
4485 | case 0: gen_helper_neon_mul_u8(tmp, tmp, tmp2); break; |
4486 | case 1: gen_helper_neon_mul_u16(tmp, tmp, tmp2); break; | |
4487 | case 2: tcg_gen_mul_i32(tmp, tmp, tmp2); break; | |
9ee6e8bb PB |
4488 | default: return 1; |
4489 | } | |
4490 | } | |
4491 | break; | |
4492 | case 20: /* VPMAX */ | |
4493 | GEN_NEON_INTEGER_OP(pmax); | |
4494 | break; | |
4495 | case 21: /* VPMIN */ | |
4496 | GEN_NEON_INTEGER_OP(pmin); | |
4497 | break; | |
4498 | case 22: /* Hultiply high. */ | |
4499 | if (!u) { /* VQDMULH */ | |
4500 | switch (size) { | |
dd8fbd78 FN |
4501 | case 1: gen_helper_neon_qdmulh_s16(tmp, cpu_env, tmp, tmp2); break; |
4502 | case 2: gen_helper_neon_qdmulh_s32(tmp, cpu_env, tmp, tmp2); break; | |
9ee6e8bb PB |
4503 | default: return 1; |
4504 | } | |
4505 | } else { /* VQRDHMUL */ | |
4506 | switch (size) { | |
dd8fbd78 FN |
4507 | case 1: gen_helper_neon_qrdmulh_s16(tmp, cpu_env, tmp, tmp2); break; |
4508 | case 2: gen_helper_neon_qrdmulh_s32(tmp, cpu_env, tmp, tmp2); break; | |
9ee6e8bb PB |
4509 | default: return 1; |
4510 | } | |
4511 | } | |
4512 | break; | |
4513 | case 23: /* VPADD */ | |
4514 | if (u) | |
4515 | return 1; | |
4516 | switch (size) { | |
dd8fbd78 FN |
4517 | case 0: gen_helper_neon_padd_u8(tmp, tmp, tmp2); break; |
4518 | case 1: gen_helper_neon_padd_u16(tmp, tmp, tmp2); break; | |
4519 | case 2: tcg_gen_add_i32(tmp, tmp, tmp2); break; | |
9ee6e8bb PB |
4520 | default: return 1; |
4521 | } | |
4522 | break; | |
4523 | case 26: /* Floating point arithnetic. */ | |
4524 | switch ((u << 2) | size) { | |
4525 | case 0: /* VADD */ | |
dd8fbd78 | 4526 | gen_helper_neon_add_f32(tmp, tmp, tmp2); |
9ee6e8bb PB |
4527 | break; |
4528 | case 2: /* VSUB */ | |
dd8fbd78 | 4529 | gen_helper_neon_sub_f32(tmp, tmp, tmp2); |
9ee6e8bb PB |
4530 | break; |
4531 | case 4: /* VPADD */ | |
dd8fbd78 | 4532 | gen_helper_neon_add_f32(tmp, tmp, tmp2); |
9ee6e8bb PB |
4533 | break; |
4534 | case 6: /* VABD */ | |
dd8fbd78 | 4535 | gen_helper_neon_abd_f32(tmp, tmp, tmp2); |
9ee6e8bb PB |
4536 | break; |
4537 | default: | |
4538 | return 1; | |
4539 | } | |
4540 | break; | |
4541 | case 27: /* Float multiply. */ | |
dd8fbd78 | 4542 | gen_helper_neon_mul_f32(tmp, tmp, tmp2); |
9ee6e8bb | 4543 | if (!u) { |
dd8fbd78 FN |
4544 | dead_tmp(tmp2); |
4545 | tmp2 = neon_load_reg(rd, pass); | |
9ee6e8bb | 4546 | if (size == 0) { |
dd8fbd78 | 4547 | gen_helper_neon_add_f32(tmp, tmp, tmp2); |
9ee6e8bb | 4548 | } else { |
dd8fbd78 | 4549 | gen_helper_neon_sub_f32(tmp, tmp2, tmp); |
9ee6e8bb PB |
4550 | } |
4551 | } | |
4552 | break; | |
4553 | case 28: /* Float compare. */ | |
4554 | if (!u) { | |
dd8fbd78 | 4555 | gen_helper_neon_ceq_f32(tmp, tmp, tmp2); |
b5ff1b31 | 4556 | } else { |
9ee6e8bb | 4557 | if (size == 0) |
dd8fbd78 | 4558 | gen_helper_neon_cge_f32(tmp, tmp, tmp2); |
9ee6e8bb | 4559 | else |
dd8fbd78 | 4560 | gen_helper_neon_cgt_f32(tmp, tmp, tmp2); |
b5ff1b31 | 4561 | } |
2c0262af | 4562 | break; |
9ee6e8bb PB |
4563 | case 29: /* Float compare absolute. */ |
4564 | if (!u) | |
4565 | return 1; | |
4566 | if (size == 0) | |
dd8fbd78 | 4567 | gen_helper_neon_acge_f32(tmp, tmp, tmp2); |
9ee6e8bb | 4568 | else |
dd8fbd78 | 4569 | gen_helper_neon_acgt_f32(tmp, tmp, tmp2); |
2c0262af | 4570 | break; |
9ee6e8bb PB |
4571 | case 30: /* Float min/max. */ |
4572 | if (size == 0) | |
dd8fbd78 | 4573 | gen_helper_neon_max_f32(tmp, tmp, tmp2); |
9ee6e8bb | 4574 | else |
dd8fbd78 | 4575 | gen_helper_neon_min_f32(tmp, tmp, tmp2); |
9ee6e8bb PB |
4576 | break; |
4577 | case 31: | |
4578 | if (size == 0) | |
dd8fbd78 | 4579 | gen_helper_recps_f32(tmp, tmp, tmp2, cpu_env); |
9ee6e8bb | 4580 | else |
dd8fbd78 | 4581 | gen_helper_rsqrts_f32(tmp, tmp, tmp2, cpu_env); |
2c0262af | 4582 | break; |
9ee6e8bb PB |
4583 | default: |
4584 | abort(); | |
2c0262af | 4585 | } |
dd8fbd78 FN |
4586 | dead_tmp(tmp2); |
4587 | ||
9ee6e8bb PB |
4588 | /* Save the result. For elementwise operations we can put it |
4589 | straight into the destination register. For pairwise operations | |
4590 | we have to be careful to avoid clobbering the source operands. */ | |
4591 | if (pairwise && rd == rm) { | |
dd8fbd78 | 4592 | neon_store_scratch(pass, tmp); |
9ee6e8bb | 4593 | } else { |
dd8fbd78 | 4594 | neon_store_reg(rd, pass, tmp); |
9ee6e8bb PB |
4595 | } |
4596 | ||
4597 | } /* for pass */ | |
4598 | if (pairwise && rd == rm) { | |
4599 | for (pass = 0; pass < (q ? 4 : 2); pass++) { | |
dd8fbd78 FN |
4600 | tmp = neon_load_scratch(pass); |
4601 | neon_store_reg(rd, pass, tmp); | |
9ee6e8bb PB |
4602 | } |
4603 | } | |
ad69471c | 4604 | /* End of 3 register same size operations. */ |
9ee6e8bb PB |
4605 | } else if (insn & (1 << 4)) { |
4606 | if ((insn & 0x00380080) != 0) { | |
4607 | /* Two registers and shift. */ | |
4608 | op = (insn >> 8) & 0xf; | |
4609 | if (insn & (1 << 7)) { | |
4610 | /* 64-bit shift. */ | |
4611 | size = 3; | |
4612 | } else { | |
4613 | size = 2; | |
4614 | while ((insn & (1 << (size + 19))) == 0) | |
4615 | size--; | |
4616 | } | |
4617 | shift = (insn >> 16) & ((1 << (3 + size)) - 1); | |
4618 | /* To avoid excessive dumplication of ops we implement shift | |
4619 | by immediate using the variable shift operations. */ | |
4620 | if (op < 8) { | |
4621 | /* Shift by immediate: | |
4622 | VSHR, VSRA, VRSHR, VRSRA, VSRI, VSHL, VQSHL, VQSHLU. */ | |
4623 | /* Right shifts are encoded as N - shift, where N is the | |
4624 | element size in bits. */ | |
4625 | if (op <= 4) | |
4626 | shift = shift - (1 << (size + 3)); | |
9ee6e8bb PB |
4627 | if (size == 3) { |
4628 | count = q + 1; | |
4629 | } else { | |
4630 | count = q ? 4: 2; | |
4631 | } | |
4632 | switch (size) { | |
4633 | case 0: | |
4634 | imm = (uint8_t) shift; | |
4635 | imm |= imm << 8; | |
4636 | imm |= imm << 16; | |
4637 | break; | |
4638 | case 1: | |
4639 | imm = (uint16_t) shift; | |
4640 | imm |= imm << 16; | |
4641 | break; | |
4642 | case 2: | |
4643 | case 3: | |
4644 | imm = shift; | |
4645 | break; | |
4646 | default: | |
4647 | abort(); | |
4648 | } | |
4649 | ||
4650 | for (pass = 0; pass < count; pass++) { | |
ad69471c PB |
4651 | if (size == 3) { |
4652 | neon_load_reg64(cpu_V0, rm + pass); | |
4653 | tcg_gen_movi_i64(cpu_V1, imm); | |
4654 | switch (op) { | |
4655 | case 0: /* VSHR */ | |
4656 | case 1: /* VSRA */ | |
4657 | if (u) | |
4658 | gen_helper_neon_shl_u64(cpu_V0, cpu_V0, cpu_V1); | |
9ee6e8bb | 4659 | else |
ad69471c | 4660 | gen_helper_neon_shl_s64(cpu_V0, cpu_V0, cpu_V1); |
9ee6e8bb | 4661 | break; |
ad69471c PB |
4662 | case 2: /* VRSHR */ |
4663 | case 3: /* VRSRA */ | |
4664 | if (u) | |
4665 | gen_helper_neon_rshl_u64(cpu_V0, cpu_V0, cpu_V1); | |
9ee6e8bb | 4666 | else |
ad69471c | 4667 | gen_helper_neon_rshl_s64(cpu_V0, cpu_V0, cpu_V1); |
9ee6e8bb | 4668 | break; |
ad69471c PB |
4669 | case 4: /* VSRI */ |
4670 | if (!u) | |
4671 | return 1; | |
4672 | gen_helper_neon_shl_u64(cpu_V0, cpu_V0, cpu_V1); | |
4673 | break; | |
4674 | case 5: /* VSHL, VSLI */ | |
4675 | gen_helper_neon_shl_u64(cpu_V0, cpu_V0, cpu_V1); | |
4676 | break; | |
0322b26e PM |
4677 | case 6: /* VQSHLU */ |
4678 | if (u) { | |
4679 | gen_helper_neon_qshlu_s64(cpu_V0, cpu_env, | |
4680 | cpu_V0, cpu_V1); | |
4681 | } else { | |
4682 | return 1; | |
4683 | } | |
ad69471c | 4684 | break; |
0322b26e PM |
4685 | case 7: /* VQSHL */ |
4686 | if (u) { | |
4687 | gen_helper_neon_qshl_u64(cpu_V0, cpu_env, | |
4688 | cpu_V0, cpu_V1); | |
4689 | } else { | |
4690 | gen_helper_neon_qshl_s64(cpu_V0, cpu_env, | |
4691 | cpu_V0, cpu_V1); | |
4692 | } | |
9ee6e8bb | 4693 | break; |
9ee6e8bb | 4694 | } |
ad69471c PB |
4695 | if (op == 1 || op == 3) { |
4696 | /* Accumulate. */ | |
5371cb81 | 4697 | neon_load_reg64(cpu_V1, rd + pass); |
ad69471c PB |
4698 | tcg_gen_add_i64(cpu_V0, cpu_V0, cpu_V1); |
4699 | } else if (op == 4 || (op == 5 && u)) { | |
4700 | /* Insert */ | |
4701 | cpu_abort(env, "VS[LR]I.64 not implemented"); | |
4702 | } | |
4703 | neon_store_reg64(cpu_V0, rd + pass); | |
4704 | } else { /* size < 3 */ | |
4705 | /* Operands in T0 and T1. */ | |
dd8fbd78 FN |
4706 | tmp = neon_load_reg(rm, pass); |
4707 | tmp2 = new_tmp(); | |
4708 | tcg_gen_movi_i32(tmp2, imm); | |
ad69471c PB |
4709 | switch (op) { |
4710 | case 0: /* VSHR */ | |
4711 | case 1: /* VSRA */ | |
4712 | GEN_NEON_INTEGER_OP(shl); | |
4713 | break; | |
4714 | case 2: /* VRSHR */ | |
4715 | case 3: /* VRSRA */ | |
4716 | GEN_NEON_INTEGER_OP(rshl); | |
4717 | break; | |
4718 | case 4: /* VSRI */ | |
4719 | if (!u) | |
4720 | return 1; | |
4721 | GEN_NEON_INTEGER_OP(shl); | |
4722 | break; | |
4723 | case 5: /* VSHL, VSLI */ | |
4724 | switch (size) { | |
dd8fbd78 FN |
4725 | case 0: gen_helper_neon_shl_u8(tmp, tmp, tmp2); break; |
4726 | case 1: gen_helper_neon_shl_u16(tmp, tmp, tmp2); break; | |
4727 | case 2: gen_helper_neon_shl_u32(tmp, tmp, tmp2); break; | |
ad69471c PB |
4728 | default: return 1; |
4729 | } | |
4730 | break; | |
0322b26e PM |
4731 | case 6: /* VQSHLU */ |
4732 | if (!u) { | |
4733 | return 1; | |
4734 | } | |
ad69471c | 4735 | switch (size) { |
0322b26e PM |
4736 | case 0: |
4737 | gen_helper_neon_qshlu_s8(tmp, cpu_env, | |
4738 | tmp, tmp2); | |
4739 | break; | |
4740 | case 1: | |
4741 | gen_helper_neon_qshlu_s16(tmp, cpu_env, | |
4742 | tmp, tmp2); | |
4743 | break; | |
4744 | case 2: | |
4745 | gen_helper_neon_qshlu_s32(tmp, cpu_env, | |
4746 | tmp, tmp2); | |
4747 | break; | |
4748 | default: | |
4749 | return 1; | |
ad69471c PB |
4750 | } |
4751 | break; | |
0322b26e PM |
4752 | case 7: /* VQSHL */ |
4753 | GEN_NEON_INTEGER_OP_ENV(qshl); | |
4754 | break; | |
ad69471c | 4755 | } |
dd8fbd78 | 4756 | dead_tmp(tmp2); |
ad69471c PB |
4757 | |
4758 | if (op == 1 || op == 3) { | |
4759 | /* Accumulate. */ | |
dd8fbd78 | 4760 | tmp2 = neon_load_reg(rd, pass); |
5371cb81 | 4761 | gen_neon_add(size, tmp, tmp2); |
dd8fbd78 | 4762 | dead_tmp(tmp2); |
ad69471c PB |
4763 | } else if (op == 4 || (op == 5 && u)) { |
4764 | /* Insert */ | |
4765 | switch (size) { | |
4766 | case 0: | |
4767 | if (op == 4) | |
ca9a32e4 | 4768 | mask = 0xff >> -shift; |
ad69471c | 4769 | else |
ca9a32e4 JR |
4770 | mask = (uint8_t)(0xff << shift); |
4771 | mask |= mask << 8; | |
4772 | mask |= mask << 16; | |
ad69471c PB |
4773 | break; |
4774 | case 1: | |
4775 | if (op == 4) | |
ca9a32e4 | 4776 | mask = 0xffff >> -shift; |
ad69471c | 4777 | else |
ca9a32e4 JR |
4778 | mask = (uint16_t)(0xffff << shift); |
4779 | mask |= mask << 16; | |
ad69471c PB |
4780 | break; |
4781 | case 2: | |
ca9a32e4 JR |
4782 | if (shift < -31 || shift > 31) { |
4783 | mask = 0; | |
4784 | } else { | |
4785 | if (op == 4) | |
4786 | mask = 0xffffffffu >> -shift; | |
4787 | else | |
4788 | mask = 0xffffffffu << shift; | |
4789 | } | |
ad69471c PB |
4790 | break; |
4791 | default: | |
4792 | abort(); | |
4793 | } | |
dd8fbd78 | 4794 | tmp2 = neon_load_reg(rd, pass); |
ca9a32e4 JR |
4795 | tcg_gen_andi_i32(tmp, tmp, mask); |
4796 | tcg_gen_andi_i32(tmp2, tmp2, ~mask); | |
dd8fbd78 FN |
4797 | tcg_gen_or_i32(tmp, tmp, tmp2); |
4798 | dead_tmp(tmp2); | |
ad69471c | 4799 | } |
dd8fbd78 | 4800 | neon_store_reg(rd, pass, tmp); |
9ee6e8bb PB |
4801 | } |
4802 | } /* for pass */ | |
4803 | } else if (op < 10) { | |
ad69471c | 4804 | /* Shift by immediate and narrow: |
9ee6e8bb PB |
4805 | VSHRN, VRSHRN, VQSHRN, VQRSHRN. */ |
4806 | shift = shift - (1 << (size + 3)); | |
4807 | size++; | |
9ee6e8bb PB |
4808 | switch (size) { |
4809 | case 1: | |
ad69471c | 4810 | imm = (uint16_t)shift; |
9ee6e8bb | 4811 | imm |= imm << 16; |
ad69471c | 4812 | tmp2 = tcg_const_i32(imm); |
a7812ae4 | 4813 | TCGV_UNUSED_I64(tmp64); |
9ee6e8bb PB |
4814 | break; |
4815 | case 2: | |
ad69471c PB |
4816 | imm = (uint32_t)shift; |
4817 | tmp2 = tcg_const_i32(imm); | |
a7812ae4 | 4818 | TCGV_UNUSED_I64(tmp64); |
4cc633c3 | 4819 | break; |
9ee6e8bb | 4820 | case 3: |
a7812ae4 PB |
4821 | tmp64 = tcg_const_i64(shift); |
4822 | TCGV_UNUSED(tmp2); | |
9ee6e8bb PB |
4823 | break; |
4824 | default: | |
4825 | abort(); | |
4826 | } | |
4827 | ||
ad69471c PB |
4828 | for (pass = 0; pass < 2; pass++) { |
4829 | if (size == 3) { | |
4830 | neon_load_reg64(cpu_V0, rm + pass); | |
4831 | if (q) { | |
4832 | if (u) | |
a7812ae4 | 4833 | gen_helper_neon_rshl_u64(cpu_V0, cpu_V0, tmp64); |
ad69471c | 4834 | else |
a7812ae4 | 4835 | gen_helper_neon_rshl_s64(cpu_V0, cpu_V0, tmp64); |
ad69471c PB |
4836 | } else { |
4837 | if (u) | |
a7812ae4 | 4838 | gen_helper_neon_shl_u64(cpu_V0, cpu_V0, tmp64); |
ad69471c | 4839 | else |
a7812ae4 | 4840 | gen_helper_neon_shl_s64(cpu_V0, cpu_V0, tmp64); |
ad69471c | 4841 | } |
2c0262af | 4842 | } else { |
ad69471c PB |
4843 | tmp = neon_load_reg(rm + pass, 0); |
4844 | gen_neon_shift_narrow(size, tmp, tmp2, q, u); | |
36aa55dc PB |
4845 | tmp3 = neon_load_reg(rm + pass, 1); |
4846 | gen_neon_shift_narrow(size, tmp3, tmp2, q, u); | |
4847 | tcg_gen_concat_i32_i64(cpu_V0, tmp, tmp3); | |
ad69471c | 4848 | dead_tmp(tmp); |
36aa55dc | 4849 | dead_tmp(tmp3); |
9ee6e8bb | 4850 | } |
ad69471c PB |
4851 | tmp = new_tmp(); |
4852 | if (op == 8 && !u) { | |
4853 | gen_neon_narrow(size - 1, tmp, cpu_V0); | |
9ee6e8bb | 4854 | } else { |
ad69471c PB |
4855 | if (op == 8) |
4856 | gen_neon_narrow_sats(size - 1, tmp, cpu_V0); | |
9ee6e8bb | 4857 | else |
ad69471c PB |
4858 | gen_neon_narrow_satu(size - 1, tmp, cpu_V0); |
4859 | } | |
2301db49 | 4860 | neon_store_reg(rd, pass, tmp); |
9ee6e8bb | 4861 | } /* for pass */ |
b75263d6 JR |
4862 | if (size == 3) { |
4863 | tcg_temp_free_i64(tmp64); | |
2301db49 | 4864 | } else { |
c6067f04 | 4865 | tcg_temp_free_i32(tmp2); |
b75263d6 | 4866 | } |
9ee6e8bb PB |
4867 | } else if (op == 10) { |
4868 | /* VSHLL */ | |
ad69471c | 4869 | if (q || size == 3) |
9ee6e8bb | 4870 | return 1; |
ad69471c PB |
4871 | tmp = neon_load_reg(rm, 0); |
4872 | tmp2 = neon_load_reg(rm, 1); | |
9ee6e8bb | 4873 | for (pass = 0; pass < 2; pass++) { |
ad69471c PB |
4874 | if (pass == 1) |
4875 | tmp = tmp2; | |
4876 | ||
4877 | gen_neon_widen(cpu_V0, tmp, size, u); | |
9ee6e8bb | 4878 | |
9ee6e8bb PB |
4879 | if (shift != 0) { |
4880 | /* The shift is less than the width of the source | |
ad69471c PB |
4881 | type, so we can just shift the whole register. */ |
4882 | tcg_gen_shli_i64(cpu_V0, cpu_V0, shift); | |
4883 | if (size < 2 || !u) { | |
4884 | uint64_t imm64; | |
4885 | if (size == 0) { | |
4886 | imm = (0xffu >> (8 - shift)); | |
4887 | imm |= imm << 16; | |
4888 | } else { | |
4889 | imm = 0xffff >> (16 - shift); | |
9ee6e8bb | 4890 | } |
ad69471c PB |
4891 | imm64 = imm | (((uint64_t)imm) << 32); |
4892 | tcg_gen_andi_i64(cpu_V0, cpu_V0, imm64); | |
9ee6e8bb PB |
4893 | } |
4894 | } | |
ad69471c | 4895 | neon_store_reg64(cpu_V0, rd + pass); |
9ee6e8bb | 4896 | } |
f73534a5 | 4897 | } else if (op >= 14) { |
9ee6e8bb | 4898 | /* VCVT fixed-point. */ |
f73534a5 PM |
4899 | /* We have already masked out the must-be-1 top bit of imm6, |
4900 | * hence this 32-shift where the ARM ARM has 64-imm6. | |
4901 | */ | |
4902 | shift = 32 - shift; | |
9ee6e8bb | 4903 | for (pass = 0; pass < (q ? 4 : 2); pass++) { |
4373f3ce | 4904 | tcg_gen_ld_f32(cpu_F0s, cpu_env, neon_reg_offset(rm, pass)); |
f73534a5 | 4905 | if (!(op & 1)) { |
9ee6e8bb | 4906 | if (u) |
4373f3ce | 4907 | gen_vfp_ulto(0, shift); |
9ee6e8bb | 4908 | else |
4373f3ce | 4909 | gen_vfp_slto(0, shift); |
9ee6e8bb PB |
4910 | } else { |
4911 | if (u) | |
4373f3ce | 4912 | gen_vfp_toul(0, shift); |
9ee6e8bb | 4913 | else |
4373f3ce | 4914 | gen_vfp_tosl(0, shift); |
2c0262af | 4915 | } |
4373f3ce | 4916 | tcg_gen_st_f32(cpu_F0s, cpu_env, neon_reg_offset(rd, pass)); |
2c0262af FB |
4917 | } |
4918 | } else { | |
9ee6e8bb PB |
4919 | return 1; |
4920 | } | |
4921 | } else { /* (insn & 0x00380080) == 0 */ | |
4922 | int invert; | |
4923 | ||
4924 | op = (insn >> 8) & 0xf; | |
4925 | /* One register and immediate. */ | |
4926 | imm = (u << 7) | ((insn >> 12) & 0x70) | (insn & 0xf); | |
4927 | invert = (insn & (1 << 5)) != 0; | |
4928 | switch (op) { | |
4929 | case 0: case 1: | |
4930 | /* no-op */ | |
4931 | break; | |
4932 | case 2: case 3: | |
4933 | imm <<= 8; | |
4934 | break; | |
4935 | case 4: case 5: | |
4936 | imm <<= 16; | |
4937 | break; | |
4938 | case 6: case 7: | |
4939 | imm <<= 24; | |
4940 | break; | |
4941 | case 8: case 9: | |
4942 | imm |= imm << 16; | |
4943 | break; | |
4944 | case 10: case 11: | |
4945 | imm = (imm << 8) | (imm << 24); | |
4946 | break; | |
4947 | case 12: | |
8e31209e | 4948 | imm = (imm << 8) | 0xff; |
9ee6e8bb PB |
4949 | break; |
4950 | case 13: | |
4951 | imm = (imm << 16) | 0xffff; | |
4952 | break; | |
4953 | case 14: | |
4954 | imm |= (imm << 8) | (imm << 16) | (imm << 24); | |
4955 | if (invert) | |
4956 | imm = ~imm; | |
4957 | break; | |
4958 | case 15: | |
4959 | imm = ((imm & 0x80) << 24) | ((imm & 0x3f) << 19) | |
4960 | | ((imm & 0x40) ? (0x1f << 25) : (1 << 30)); | |
4961 | break; | |
4962 | } | |
4963 | if (invert) | |
4964 | imm = ~imm; | |
4965 | ||
9ee6e8bb PB |
4966 | for (pass = 0; pass < (q ? 4 : 2); pass++) { |
4967 | if (op & 1 && op < 12) { | |
ad69471c | 4968 | tmp = neon_load_reg(rd, pass); |
9ee6e8bb PB |
4969 | if (invert) { |
4970 | /* The immediate value has already been inverted, so | |
4971 | BIC becomes AND. */ | |
ad69471c | 4972 | tcg_gen_andi_i32(tmp, tmp, imm); |
9ee6e8bb | 4973 | } else { |
ad69471c | 4974 | tcg_gen_ori_i32(tmp, tmp, imm); |
9ee6e8bb | 4975 | } |
9ee6e8bb | 4976 | } else { |
ad69471c PB |
4977 | /* VMOV, VMVN. */ |
4978 | tmp = new_tmp(); | |
9ee6e8bb | 4979 | if (op == 14 && invert) { |
ad69471c PB |
4980 | uint32_t val; |
4981 | val = 0; | |
9ee6e8bb PB |
4982 | for (n = 0; n < 4; n++) { |
4983 | if (imm & (1 << (n + (pass & 1) * 4))) | |
ad69471c | 4984 | val |= 0xff << (n * 8); |
9ee6e8bb | 4985 | } |
ad69471c PB |
4986 | tcg_gen_movi_i32(tmp, val); |
4987 | } else { | |
4988 | tcg_gen_movi_i32(tmp, imm); | |
9ee6e8bb | 4989 | } |
9ee6e8bb | 4990 | } |
ad69471c | 4991 | neon_store_reg(rd, pass, tmp); |
9ee6e8bb PB |
4992 | } |
4993 | } | |
e4b3861d | 4994 | } else { /* (insn & 0x00800010 == 0x00800000) */ |
9ee6e8bb PB |
4995 | if (size != 3) { |
4996 | op = (insn >> 8) & 0xf; | |
4997 | if ((insn & (1 << 6)) == 0) { | |
4998 | /* Three registers of different lengths. */ | |
4999 | int src1_wide; | |
5000 | int src2_wide; | |
5001 | int prewiden; | |
5002 | /* prewiden, src1_wide, src2_wide */ | |
5003 | static const int neon_3reg_wide[16][3] = { | |
5004 | {1, 0, 0}, /* VADDL */ | |
5005 | {1, 1, 0}, /* VADDW */ | |
5006 | {1, 0, 0}, /* VSUBL */ | |
5007 | {1, 1, 0}, /* VSUBW */ | |
5008 | {0, 1, 1}, /* VADDHN */ | |
5009 | {0, 0, 0}, /* VABAL */ | |
5010 | {0, 1, 1}, /* VSUBHN */ | |
5011 | {0, 0, 0}, /* VABDL */ | |
5012 | {0, 0, 0}, /* VMLAL */ | |
5013 | {0, 0, 0}, /* VQDMLAL */ | |
5014 | {0, 0, 0}, /* VMLSL */ | |
5015 | {0, 0, 0}, /* VQDMLSL */ | |
5016 | {0, 0, 0}, /* Integer VMULL */ | |
5017 | {0, 0, 0}, /* VQDMULL */ | |
5018 | {0, 0, 0} /* Polynomial VMULL */ | |
5019 | }; | |
5020 | ||
5021 | prewiden = neon_3reg_wide[op][0]; | |
5022 | src1_wide = neon_3reg_wide[op][1]; | |
5023 | src2_wide = neon_3reg_wide[op][2]; | |
5024 | ||
ad69471c PB |
5025 | if (size == 0 && (op == 9 || op == 11 || op == 13)) |
5026 | return 1; | |
5027 | ||
9ee6e8bb PB |
5028 | /* Avoid overlapping operands. Wide source operands are |
5029 | always aligned so will never overlap with wide | |
5030 | destinations in problematic ways. */ | |
8f8e3aa4 | 5031 | if (rd == rm && !src2_wide) { |
dd8fbd78 FN |
5032 | tmp = neon_load_reg(rm, 1); |
5033 | neon_store_scratch(2, tmp); | |
8f8e3aa4 | 5034 | } else if (rd == rn && !src1_wide) { |
dd8fbd78 FN |
5035 | tmp = neon_load_reg(rn, 1); |
5036 | neon_store_scratch(2, tmp); | |
9ee6e8bb | 5037 | } |
a50f5b91 | 5038 | TCGV_UNUSED(tmp3); |
9ee6e8bb | 5039 | for (pass = 0; pass < 2; pass++) { |
ad69471c PB |
5040 | if (src1_wide) { |
5041 | neon_load_reg64(cpu_V0, rn + pass); | |
a50f5b91 | 5042 | TCGV_UNUSED(tmp); |
9ee6e8bb | 5043 | } else { |
ad69471c | 5044 | if (pass == 1 && rd == rn) { |
dd8fbd78 | 5045 | tmp = neon_load_scratch(2); |
9ee6e8bb | 5046 | } else { |
ad69471c PB |
5047 | tmp = neon_load_reg(rn, pass); |
5048 | } | |
5049 | if (prewiden) { | |
5050 | gen_neon_widen(cpu_V0, tmp, size, u); | |
9ee6e8bb PB |
5051 | } |
5052 | } | |
ad69471c PB |
5053 | if (src2_wide) { |
5054 | neon_load_reg64(cpu_V1, rm + pass); | |
a50f5b91 | 5055 | TCGV_UNUSED(tmp2); |
9ee6e8bb | 5056 | } else { |
ad69471c | 5057 | if (pass == 1 && rd == rm) { |
dd8fbd78 | 5058 | tmp2 = neon_load_scratch(2); |
9ee6e8bb | 5059 | } else { |
ad69471c PB |
5060 | tmp2 = neon_load_reg(rm, pass); |
5061 | } | |
5062 | if (prewiden) { | |
5063 | gen_neon_widen(cpu_V1, tmp2, size, u); | |
9ee6e8bb | 5064 | } |
9ee6e8bb PB |
5065 | } |
5066 | switch (op) { | |
5067 | case 0: case 1: case 4: /* VADDL, VADDW, VADDHN, VRADDHN */ | |
ad69471c | 5068 | gen_neon_addl(size); |
9ee6e8bb | 5069 | break; |
79b0e534 | 5070 | case 2: case 3: case 6: /* VSUBL, VSUBW, VSUBHN, VRSUBHN */ |
ad69471c | 5071 | gen_neon_subl(size); |
9ee6e8bb PB |
5072 | break; |
5073 | case 5: case 7: /* VABAL, VABDL */ | |
5074 | switch ((size << 1) | u) { | |
ad69471c PB |
5075 | case 0: |
5076 | gen_helper_neon_abdl_s16(cpu_V0, tmp, tmp2); | |
5077 | break; | |
5078 | case 1: | |
5079 | gen_helper_neon_abdl_u16(cpu_V0, tmp, tmp2); | |
5080 | break; | |
5081 | case 2: | |
5082 | gen_helper_neon_abdl_s32(cpu_V0, tmp, tmp2); | |
5083 | break; | |
5084 | case 3: | |
5085 | gen_helper_neon_abdl_u32(cpu_V0, tmp, tmp2); | |
5086 | break; | |
5087 | case 4: | |
5088 | gen_helper_neon_abdl_s64(cpu_V0, tmp, tmp2); | |
5089 | break; | |
5090 | case 5: | |
5091 | gen_helper_neon_abdl_u64(cpu_V0, tmp, tmp2); | |
5092 | break; | |
9ee6e8bb PB |
5093 | default: abort(); |
5094 | } | |
ad69471c PB |
5095 | dead_tmp(tmp2); |
5096 | dead_tmp(tmp); | |
9ee6e8bb PB |
5097 | break; |
5098 | case 8: case 9: case 10: case 11: case 12: case 13: | |
5099 | /* VMLAL, VQDMLAL, VMLSL, VQDMLSL, VMULL, VQDMULL */ | |
ad69471c | 5100 | gen_neon_mull(cpu_V0, tmp, tmp2, size, u); |
9ee6e8bb PB |
5101 | break; |
5102 | case 14: /* Polynomial VMULL */ | |
5103 | cpu_abort(env, "Polynomial VMULL not implemented"); | |
5104 | ||
5105 | default: /* 15 is RESERVED. */ | |
5106 | return 1; | |
5107 | } | |
5108 | if (op == 5 || op == 13 || (op >= 8 && op <= 11)) { | |
5109 | /* Accumulate. */ | |
5110 | if (op == 10 || op == 11) { | |
ad69471c | 5111 | gen_neon_negl(cpu_V0, size); |
9ee6e8bb PB |
5112 | } |
5113 | ||
9ee6e8bb | 5114 | if (op != 13) { |
ad69471c | 5115 | neon_load_reg64(cpu_V1, rd + pass); |
9ee6e8bb PB |
5116 | } |
5117 | ||
5118 | switch (op) { | |
5119 | case 5: case 8: case 10: /* VABAL, VMLAL, VMLSL */ | |
ad69471c | 5120 | gen_neon_addl(size); |
9ee6e8bb PB |
5121 | break; |
5122 | case 9: case 11: /* VQDMLAL, VQDMLSL */ | |
ad69471c PB |
5123 | gen_neon_addl_saturate(cpu_V0, cpu_V0, size); |
5124 | gen_neon_addl_saturate(cpu_V0, cpu_V1, size); | |
5125 | break; | |
9ee6e8bb PB |
5126 | /* Fall through. */ |
5127 | case 13: /* VQDMULL */ | |
ad69471c | 5128 | gen_neon_addl_saturate(cpu_V0, cpu_V0, size); |
9ee6e8bb PB |
5129 | break; |
5130 | default: | |
5131 | abort(); | |
5132 | } | |
ad69471c | 5133 | neon_store_reg64(cpu_V0, rd + pass); |
9ee6e8bb PB |
5134 | } else if (op == 4 || op == 6) { |
5135 | /* Narrowing operation. */ | |
ad69471c | 5136 | tmp = new_tmp(); |
79b0e534 | 5137 | if (!u) { |
9ee6e8bb | 5138 | switch (size) { |
ad69471c PB |
5139 | case 0: |
5140 | gen_helper_neon_narrow_high_u8(tmp, cpu_V0); | |
5141 | break; | |
5142 | case 1: | |
5143 | gen_helper_neon_narrow_high_u16(tmp, cpu_V0); | |
5144 | break; | |
5145 | case 2: | |
5146 | tcg_gen_shri_i64(cpu_V0, cpu_V0, 32); | |
5147 | tcg_gen_trunc_i64_i32(tmp, cpu_V0); | |
5148 | break; | |
9ee6e8bb PB |
5149 | default: abort(); |
5150 | } | |
5151 | } else { | |
5152 | switch (size) { | |
ad69471c PB |
5153 | case 0: |
5154 | gen_helper_neon_narrow_round_high_u8(tmp, cpu_V0); | |
5155 | break; | |
5156 | case 1: | |
5157 | gen_helper_neon_narrow_round_high_u16(tmp, cpu_V0); | |
5158 | break; | |
5159 | case 2: | |
5160 | tcg_gen_addi_i64(cpu_V0, cpu_V0, 1u << 31); | |
5161 | tcg_gen_shri_i64(cpu_V0, cpu_V0, 32); | |
5162 | tcg_gen_trunc_i64_i32(tmp, cpu_V0); | |
5163 | break; | |
9ee6e8bb PB |
5164 | default: abort(); |
5165 | } | |
5166 | } | |
ad69471c PB |
5167 | if (pass == 0) { |
5168 | tmp3 = tmp; | |
5169 | } else { | |
5170 | neon_store_reg(rd, 0, tmp3); | |
5171 | neon_store_reg(rd, 1, tmp); | |
5172 | } | |
9ee6e8bb PB |
5173 | } else { |
5174 | /* Write back the result. */ | |
ad69471c | 5175 | neon_store_reg64(cpu_V0, rd + pass); |
9ee6e8bb PB |
5176 | } |
5177 | } | |
5178 | } else { | |
5179 | /* Two registers and a scalar. */ | |
5180 | switch (op) { | |
5181 | case 0: /* Integer VMLA scalar */ | |
5182 | case 1: /* Float VMLA scalar */ | |
5183 | case 4: /* Integer VMLS scalar */ | |
5184 | case 5: /* Floating point VMLS scalar */ | |
5185 | case 8: /* Integer VMUL scalar */ | |
5186 | case 9: /* Floating point VMUL scalar */ | |
5187 | case 12: /* VQDMULH scalar */ | |
5188 | case 13: /* VQRDMULH scalar */ | |
dd8fbd78 FN |
5189 | tmp = neon_get_scalar(size, rm); |
5190 | neon_store_scratch(0, tmp); | |
9ee6e8bb | 5191 | for (pass = 0; pass < (u ? 4 : 2); pass++) { |
dd8fbd78 FN |
5192 | tmp = neon_load_scratch(0); |
5193 | tmp2 = neon_load_reg(rn, pass); | |
9ee6e8bb PB |
5194 | if (op == 12) { |
5195 | if (size == 1) { | |
dd8fbd78 | 5196 | gen_helper_neon_qdmulh_s16(tmp, cpu_env, tmp, tmp2); |
9ee6e8bb | 5197 | } else { |
dd8fbd78 | 5198 | gen_helper_neon_qdmulh_s32(tmp, cpu_env, tmp, tmp2); |
9ee6e8bb PB |
5199 | } |
5200 | } else if (op == 13) { | |
5201 | if (size == 1) { | |
dd8fbd78 | 5202 | gen_helper_neon_qrdmulh_s16(tmp, cpu_env, tmp, tmp2); |
9ee6e8bb | 5203 | } else { |
dd8fbd78 | 5204 | gen_helper_neon_qrdmulh_s32(tmp, cpu_env, tmp, tmp2); |
9ee6e8bb PB |
5205 | } |
5206 | } else if (op & 1) { | |
dd8fbd78 | 5207 | gen_helper_neon_mul_f32(tmp, tmp, tmp2); |
9ee6e8bb PB |
5208 | } else { |
5209 | switch (size) { | |
dd8fbd78 FN |
5210 | case 0: gen_helper_neon_mul_u8(tmp, tmp, tmp2); break; |
5211 | case 1: gen_helper_neon_mul_u16(tmp, tmp, tmp2); break; | |
5212 | case 2: tcg_gen_mul_i32(tmp, tmp, tmp2); break; | |
9ee6e8bb PB |
5213 | default: return 1; |
5214 | } | |
5215 | } | |
dd8fbd78 | 5216 | dead_tmp(tmp2); |
9ee6e8bb PB |
5217 | if (op < 8) { |
5218 | /* Accumulate. */ | |
dd8fbd78 | 5219 | tmp2 = neon_load_reg(rd, pass); |
9ee6e8bb PB |
5220 | switch (op) { |
5221 | case 0: | |
dd8fbd78 | 5222 | gen_neon_add(size, tmp, tmp2); |
9ee6e8bb PB |
5223 | break; |
5224 | case 1: | |
dd8fbd78 | 5225 | gen_helper_neon_add_f32(tmp, tmp, tmp2); |
9ee6e8bb PB |
5226 | break; |
5227 | case 4: | |
dd8fbd78 | 5228 | gen_neon_rsb(size, tmp, tmp2); |
9ee6e8bb PB |
5229 | break; |
5230 | case 5: | |
dd8fbd78 | 5231 | gen_helper_neon_sub_f32(tmp, tmp2, tmp); |
9ee6e8bb PB |
5232 | break; |
5233 | default: | |
5234 | abort(); | |
5235 | } | |
dd8fbd78 | 5236 | dead_tmp(tmp2); |
9ee6e8bb | 5237 | } |
dd8fbd78 | 5238 | neon_store_reg(rd, pass, tmp); |
9ee6e8bb PB |
5239 | } |
5240 | break; | |
5241 | case 2: /* VMLAL sclar */ | |
5242 | case 3: /* VQDMLAL scalar */ | |
5243 | case 6: /* VMLSL scalar */ | |
5244 | case 7: /* VQDMLSL scalar */ | |
5245 | case 10: /* VMULL scalar */ | |
5246 | case 11: /* VQDMULL scalar */ | |
ad69471c PB |
5247 | if (size == 0 && (op == 3 || op == 7 || op == 11)) |
5248 | return 1; | |
5249 | ||
dd8fbd78 | 5250 | tmp2 = neon_get_scalar(size, rm); |
c6067f04 CL |
5251 | /* We need a copy of tmp2 because gen_neon_mull |
5252 | * deletes it during pass 0. */ | |
5253 | tmp4 = new_tmp(); | |
5254 | tcg_gen_mov_i32(tmp4, tmp2); | |
dd8fbd78 | 5255 | tmp3 = neon_load_reg(rn, 1); |
ad69471c | 5256 | |
9ee6e8bb | 5257 | for (pass = 0; pass < 2; pass++) { |
ad69471c PB |
5258 | if (pass == 0) { |
5259 | tmp = neon_load_reg(rn, 0); | |
9ee6e8bb | 5260 | } else { |
dd8fbd78 | 5261 | tmp = tmp3; |
c6067f04 | 5262 | tmp2 = tmp4; |
9ee6e8bb | 5263 | } |
ad69471c | 5264 | gen_neon_mull(cpu_V0, tmp, tmp2, size, u); |
9ee6e8bb | 5265 | if (op == 6 || op == 7) { |
ad69471c PB |
5266 | gen_neon_negl(cpu_V0, size); |
5267 | } | |
5268 | if (op != 11) { | |
5269 | neon_load_reg64(cpu_V1, rd + pass); | |
9ee6e8bb | 5270 | } |
9ee6e8bb PB |
5271 | switch (op) { |
5272 | case 2: case 6: | |
ad69471c | 5273 | gen_neon_addl(size); |
9ee6e8bb PB |
5274 | break; |
5275 | case 3: case 7: | |
ad69471c PB |
5276 | gen_neon_addl_saturate(cpu_V0, cpu_V0, size); |
5277 | gen_neon_addl_saturate(cpu_V0, cpu_V1, size); | |
9ee6e8bb PB |
5278 | break; |
5279 | case 10: | |
5280 | /* no-op */ | |
5281 | break; | |
5282 | case 11: | |
ad69471c | 5283 | gen_neon_addl_saturate(cpu_V0, cpu_V0, size); |
9ee6e8bb PB |
5284 | break; |
5285 | default: | |
5286 | abort(); | |
5287 | } | |
ad69471c | 5288 | neon_store_reg64(cpu_V0, rd + pass); |
9ee6e8bb | 5289 | } |
dd8fbd78 | 5290 | |
dd8fbd78 | 5291 | |
9ee6e8bb PB |
5292 | break; |
5293 | default: /* 14 and 15 are RESERVED */ | |
5294 | return 1; | |
5295 | } | |
5296 | } | |
5297 | } else { /* size == 3 */ | |
5298 | if (!u) { | |
5299 | /* Extract. */ | |
9ee6e8bb | 5300 | imm = (insn >> 8) & 0xf; |
ad69471c PB |
5301 | |
5302 | if (imm > 7 && !q) | |
5303 | return 1; | |
5304 | ||
5305 | if (imm == 0) { | |
5306 | neon_load_reg64(cpu_V0, rn); | |
5307 | if (q) { | |
5308 | neon_load_reg64(cpu_V1, rn + 1); | |
9ee6e8bb | 5309 | } |
ad69471c PB |
5310 | } else if (imm == 8) { |
5311 | neon_load_reg64(cpu_V0, rn + 1); | |
5312 | if (q) { | |
5313 | neon_load_reg64(cpu_V1, rm); | |
9ee6e8bb | 5314 | } |
ad69471c | 5315 | } else if (q) { |
a7812ae4 | 5316 | tmp64 = tcg_temp_new_i64(); |
ad69471c PB |
5317 | if (imm < 8) { |
5318 | neon_load_reg64(cpu_V0, rn); | |
a7812ae4 | 5319 | neon_load_reg64(tmp64, rn + 1); |
ad69471c PB |
5320 | } else { |
5321 | neon_load_reg64(cpu_V0, rn + 1); | |
a7812ae4 | 5322 | neon_load_reg64(tmp64, rm); |
ad69471c PB |
5323 | } |
5324 | tcg_gen_shri_i64(cpu_V0, cpu_V0, (imm & 7) * 8); | |
a7812ae4 | 5325 | tcg_gen_shli_i64(cpu_V1, tmp64, 64 - ((imm & 7) * 8)); |
ad69471c PB |
5326 | tcg_gen_or_i64(cpu_V0, cpu_V0, cpu_V1); |
5327 | if (imm < 8) { | |
5328 | neon_load_reg64(cpu_V1, rm); | |
9ee6e8bb | 5329 | } else { |
ad69471c PB |
5330 | neon_load_reg64(cpu_V1, rm + 1); |
5331 | imm -= 8; | |
9ee6e8bb | 5332 | } |
ad69471c | 5333 | tcg_gen_shli_i64(cpu_V1, cpu_V1, 64 - (imm * 8)); |
a7812ae4 PB |
5334 | tcg_gen_shri_i64(tmp64, tmp64, imm * 8); |
5335 | tcg_gen_or_i64(cpu_V1, cpu_V1, tmp64); | |
b75263d6 | 5336 | tcg_temp_free_i64(tmp64); |
ad69471c | 5337 | } else { |
a7812ae4 | 5338 | /* BUGFIX */ |
ad69471c | 5339 | neon_load_reg64(cpu_V0, rn); |
a7812ae4 | 5340 | tcg_gen_shri_i64(cpu_V0, cpu_V0, imm * 8); |
ad69471c | 5341 | neon_load_reg64(cpu_V1, rm); |
a7812ae4 | 5342 | tcg_gen_shli_i64(cpu_V1, cpu_V1, 64 - (imm * 8)); |
ad69471c PB |
5343 | tcg_gen_or_i64(cpu_V0, cpu_V0, cpu_V1); |
5344 | } | |
5345 | neon_store_reg64(cpu_V0, rd); | |
5346 | if (q) { | |
5347 | neon_store_reg64(cpu_V1, rd + 1); | |
9ee6e8bb PB |
5348 | } |
5349 | } else if ((insn & (1 << 11)) == 0) { | |
5350 | /* Two register misc. */ | |
5351 | op = ((insn >> 12) & 0x30) | ((insn >> 7) & 0xf); | |
5352 | size = (insn >> 18) & 3; | |
5353 | switch (op) { | |
5354 | case 0: /* VREV64 */ | |
5355 | if (size == 3) | |
5356 | return 1; | |
5357 | for (pass = 0; pass < (q ? 2 : 1); pass++) { | |
dd8fbd78 FN |
5358 | tmp = neon_load_reg(rm, pass * 2); |
5359 | tmp2 = neon_load_reg(rm, pass * 2 + 1); | |
9ee6e8bb | 5360 | switch (size) { |
dd8fbd78 FN |
5361 | case 0: tcg_gen_bswap32_i32(tmp, tmp); break; |
5362 | case 1: gen_swap_half(tmp); break; | |
9ee6e8bb PB |
5363 | case 2: /* no-op */ break; |
5364 | default: abort(); | |
5365 | } | |
dd8fbd78 | 5366 | neon_store_reg(rd, pass * 2 + 1, tmp); |
9ee6e8bb | 5367 | if (size == 2) { |
dd8fbd78 | 5368 | neon_store_reg(rd, pass * 2, tmp2); |
9ee6e8bb | 5369 | } else { |
9ee6e8bb | 5370 | switch (size) { |
dd8fbd78 FN |
5371 | case 0: tcg_gen_bswap32_i32(tmp2, tmp2); break; |
5372 | case 1: gen_swap_half(tmp2); break; | |
9ee6e8bb PB |
5373 | default: abort(); |
5374 | } | |
dd8fbd78 | 5375 | neon_store_reg(rd, pass * 2, tmp2); |
9ee6e8bb PB |
5376 | } |
5377 | } | |
5378 | break; | |
5379 | case 4: case 5: /* VPADDL */ | |
5380 | case 12: case 13: /* VPADAL */ | |
9ee6e8bb PB |
5381 | if (size == 3) |
5382 | return 1; | |
ad69471c PB |
5383 | for (pass = 0; pass < q + 1; pass++) { |
5384 | tmp = neon_load_reg(rm, pass * 2); | |
5385 | gen_neon_widen(cpu_V0, tmp, size, op & 1); | |
5386 | tmp = neon_load_reg(rm, pass * 2 + 1); | |
5387 | gen_neon_widen(cpu_V1, tmp, size, op & 1); | |
5388 | switch (size) { | |
5389 | case 0: gen_helper_neon_paddl_u16(CPU_V001); break; | |
5390 | case 1: gen_helper_neon_paddl_u32(CPU_V001); break; | |
5391 | case 2: tcg_gen_add_i64(CPU_V001); break; | |
5392 | default: abort(); | |
5393 | } | |
9ee6e8bb PB |
5394 | if (op >= 12) { |
5395 | /* Accumulate. */ | |
ad69471c PB |
5396 | neon_load_reg64(cpu_V1, rd + pass); |
5397 | gen_neon_addl(size); | |
9ee6e8bb | 5398 | } |
ad69471c | 5399 | neon_store_reg64(cpu_V0, rd + pass); |
9ee6e8bb PB |
5400 | } |
5401 | break; | |
5402 | case 33: /* VTRN */ | |
5403 | if (size == 2) { | |
5404 | for (n = 0; n < (q ? 4 : 2); n += 2) { | |
dd8fbd78 FN |
5405 | tmp = neon_load_reg(rm, n); |
5406 | tmp2 = neon_load_reg(rd, n + 1); | |
5407 | neon_store_reg(rm, n, tmp2); | |
5408 | neon_store_reg(rd, n + 1, tmp); | |
9ee6e8bb PB |
5409 | } |
5410 | } else { | |
5411 | goto elementwise; | |
5412 | } | |
5413 | break; | |
5414 | case 34: /* VUZP */ | |
5415 | /* Reg Before After | |
5416 | Rd A3 A2 A1 A0 B2 B0 A2 A0 | |
5417 | Rm B3 B2 B1 B0 B3 B1 A3 A1 | |
5418 | */ | |
5419 | if (size == 3) | |
5420 | return 1; | |
5421 | gen_neon_unzip(rd, q, 0, size); | |
5422 | gen_neon_unzip(rm, q, 4, size); | |
5423 | if (q) { | |
5424 | static int unzip_order_q[8] = | |
5425 | {0, 2, 4, 6, 1, 3, 5, 7}; | |
5426 | for (n = 0; n < 8; n++) { | |
5427 | int reg = (n < 4) ? rd : rm; | |
dd8fbd78 FN |
5428 | tmp = neon_load_scratch(unzip_order_q[n]); |
5429 | neon_store_reg(reg, n % 4, tmp); | |
9ee6e8bb PB |
5430 | } |
5431 | } else { | |
5432 | static int unzip_order[4] = | |
5433 | {0, 4, 1, 5}; | |
5434 | for (n = 0; n < 4; n++) { | |
5435 | int reg = (n < 2) ? rd : rm; | |
dd8fbd78 FN |
5436 | tmp = neon_load_scratch(unzip_order[n]); |
5437 | neon_store_reg(reg, n % 2, tmp); | |
9ee6e8bb PB |
5438 | } |
5439 | } | |
5440 | break; | |
5441 | case 35: /* VZIP */ | |
5442 | /* Reg Before After | |
5443 | Rd A3 A2 A1 A0 B1 A1 B0 A0 | |
5444 | Rm B3 B2 B1 B0 B3 A3 B2 A2 | |
5445 | */ | |
5446 | if (size == 3) | |
5447 | return 1; | |
5448 | count = (q ? 4 : 2); | |
5449 | for (n = 0; n < count; n++) { | |
dd8fbd78 FN |
5450 | tmp = neon_load_reg(rd, n); |
5451 | tmp2 = neon_load_reg(rd, n); | |
9ee6e8bb | 5452 | switch (size) { |
dd8fbd78 FN |
5453 | case 0: gen_neon_zip_u8(tmp, tmp2); break; |
5454 | case 1: gen_neon_zip_u16(tmp, tmp2); break; | |
9ee6e8bb PB |
5455 | case 2: /* no-op */; break; |
5456 | default: abort(); | |
5457 | } | |
dd8fbd78 FN |
5458 | neon_store_scratch(n * 2, tmp); |
5459 | neon_store_scratch(n * 2 + 1, tmp2); | |
9ee6e8bb PB |
5460 | } |
5461 | for (n = 0; n < count * 2; n++) { | |
5462 | int reg = (n < count) ? rd : rm; | |
dd8fbd78 FN |
5463 | tmp = neon_load_scratch(n); |
5464 | neon_store_reg(reg, n % count, tmp); | |
9ee6e8bb PB |
5465 | } |
5466 | break; | |
5467 | case 36: case 37: /* VMOVN, VQMOVUN, VQMOVN */ | |
ad69471c PB |
5468 | if (size == 3) |
5469 | return 1; | |
a50f5b91 | 5470 | TCGV_UNUSED(tmp2); |
9ee6e8bb | 5471 | for (pass = 0; pass < 2; pass++) { |
ad69471c PB |
5472 | neon_load_reg64(cpu_V0, rm + pass); |
5473 | tmp = new_tmp(); | |
af1bbf30 JR |
5474 | if (op == 36) { |
5475 | if (q) { /* VQMOVUN */ | |
5476 | gen_neon_unarrow_sats(size, tmp, cpu_V0); | |
5477 | } else { /* VMOVN */ | |
5478 | gen_neon_narrow(size, tmp, cpu_V0); | |
5479 | } | |
5480 | } else { /* VQMOVN */ | |
5481 | if (q) { | |
5482 | gen_neon_narrow_satu(size, tmp, cpu_V0); | |
5483 | } else { | |
5484 | gen_neon_narrow_sats(size, tmp, cpu_V0); | |
5485 | } | |
ad69471c PB |
5486 | } |
5487 | if (pass == 0) { | |
5488 | tmp2 = tmp; | |
5489 | } else { | |
5490 | neon_store_reg(rd, 0, tmp2); | |
5491 | neon_store_reg(rd, 1, tmp); | |
9ee6e8bb | 5492 | } |
9ee6e8bb PB |
5493 | } |
5494 | break; | |
5495 | case 38: /* VSHLL */ | |
ad69471c | 5496 | if (q || size == 3) |
9ee6e8bb | 5497 | return 1; |
ad69471c PB |
5498 | tmp = neon_load_reg(rm, 0); |
5499 | tmp2 = neon_load_reg(rm, 1); | |
9ee6e8bb | 5500 | for (pass = 0; pass < 2; pass++) { |
ad69471c PB |
5501 | if (pass == 1) |
5502 | tmp = tmp2; | |
5503 | gen_neon_widen(cpu_V0, tmp, size, 1); | |
30d11a2a | 5504 | tcg_gen_shli_i64(cpu_V0, cpu_V0, 8 << size); |
ad69471c | 5505 | neon_store_reg64(cpu_V0, rd + pass); |
9ee6e8bb PB |
5506 | } |
5507 | break; | |
60011498 PB |
5508 | case 44: /* VCVT.F16.F32 */ |
5509 | if (!arm_feature(env, ARM_FEATURE_VFP_FP16)) | |
5510 | return 1; | |
5511 | tmp = new_tmp(); | |
5512 | tmp2 = new_tmp(); | |
5513 | tcg_gen_ld_f32(cpu_F0s, cpu_env, neon_reg_offset(rm, 0)); | |
5514 | gen_helper_vfp_fcvt_f32_to_f16(tmp, cpu_F0s, cpu_env); | |
5515 | tcg_gen_ld_f32(cpu_F0s, cpu_env, neon_reg_offset(rm, 1)); | |
5516 | gen_helper_vfp_fcvt_f32_to_f16(tmp2, cpu_F0s, cpu_env); | |
5517 | tcg_gen_shli_i32(tmp2, tmp2, 16); | |
5518 | tcg_gen_or_i32(tmp2, tmp2, tmp); | |
5519 | tcg_gen_ld_f32(cpu_F0s, cpu_env, neon_reg_offset(rm, 2)); | |
5520 | gen_helper_vfp_fcvt_f32_to_f16(tmp, cpu_F0s, cpu_env); | |
5521 | tcg_gen_ld_f32(cpu_F0s, cpu_env, neon_reg_offset(rm, 3)); | |
5522 | neon_store_reg(rd, 0, tmp2); | |
5523 | tmp2 = new_tmp(); | |
5524 | gen_helper_vfp_fcvt_f32_to_f16(tmp2, cpu_F0s, cpu_env); | |
5525 | tcg_gen_shli_i32(tmp2, tmp2, 16); | |
5526 | tcg_gen_or_i32(tmp2, tmp2, tmp); | |
5527 | neon_store_reg(rd, 1, tmp2); | |
5528 | dead_tmp(tmp); | |
5529 | break; | |
5530 | case 46: /* VCVT.F32.F16 */ | |
5531 | if (!arm_feature(env, ARM_FEATURE_VFP_FP16)) | |
5532 | return 1; | |
5533 | tmp3 = new_tmp(); | |
5534 | tmp = neon_load_reg(rm, 0); | |
5535 | tmp2 = neon_load_reg(rm, 1); | |
5536 | tcg_gen_ext16u_i32(tmp3, tmp); | |
5537 | gen_helper_vfp_fcvt_f16_to_f32(cpu_F0s, tmp3, cpu_env); | |
5538 | tcg_gen_st_f32(cpu_F0s, cpu_env, neon_reg_offset(rd, 0)); | |
5539 | tcg_gen_shri_i32(tmp3, tmp, 16); | |
5540 | gen_helper_vfp_fcvt_f16_to_f32(cpu_F0s, tmp3, cpu_env); | |
5541 | tcg_gen_st_f32(cpu_F0s, cpu_env, neon_reg_offset(rd, 1)); | |
5542 | dead_tmp(tmp); | |
5543 | tcg_gen_ext16u_i32(tmp3, tmp2); | |
5544 | gen_helper_vfp_fcvt_f16_to_f32(cpu_F0s, tmp3, cpu_env); | |
5545 | tcg_gen_st_f32(cpu_F0s, cpu_env, neon_reg_offset(rd, 2)); | |
5546 | tcg_gen_shri_i32(tmp3, tmp2, 16); | |
5547 | gen_helper_vfp_fcvt_f16_to_f32(cpu_F0s, tmp3, cpu_env); | |
5548 | tcg_gen_st_f32(cpu_F0s, cpu_env, neon_reg_offset(rd, 3)); | |
5549 | dead_tmp(tmp2); | |
5550 | dead_tmp(tmp3); | |
5551 | break; | |
9ee6e8bb PB |
5552 | default: |
5553 | elementwise: | |
5554 | for (pass = 0; pass < (q ? 4 : 2); pass++) { | |
5555 | if (op == 30 || op == 31 || op >= 58) { | |
4373f3ce PB |
5556 | tcg_gen_ld_f32(cpu_F0s, cpu_env, |
5557 | neon_reg_offset(rm, pass)); | |
dd8fbd78 | 5558 | TCGV_UNUSED(tmp); |
9ee6e8bb | 5559 | } else { |
dd8fbd78 | 5560 | tmp = neon_load_reg(rm, pass); |
9ee6e8bb PB |
5561 | } |
5562 | switch (op) { | |
5563 | case 1: /* VREV32 */ | |
5564 | switch (size) { | |
dd8fbd78 FN |
5565 | case 0: tcg_gen_bswap32_i32(tmp, tmp); break; |
5566 | case 1: gen_swap_half(tmp); break; | |
9ee6e8bb PB |
5567 | default: return 1; |
5568 | } | |
5569 | break; | |
5570 | case 2: /* VREV16 */ | |
5571 | if (size != 0) | |
5572 | return 1; | |
dd8fbd78 | 5573 | gen_rev16(tmp); |
9ee6e8bb | 5574 | break; |
9ee6e8bb PB |
5575 | case 8: /* CLS */ |
5576 | switch (size) { | |
dd8fbd78 FN |
5577 | case 0: gen_helper_neon_cls_s8(tmp, tmp); break; |
5578 | case 1: gen_helper_neon_cls_s16(tmp, tmp); break; | |
5579 | case 2: gen_helper_neon_cls_s32(tmp, tmp); break; | |
9ee6e8bb PB |
5580 | default: return 1; |
5581 | } | |
5582 | break; | |
5583 | case 9: /* CLZ */ | |
5584 | switch (size) { | |
dd8fbd78 FN |
5585 | case 0: gen_helper_neon_clz_u8(tmp, tmp); break; |
5586 | case 1: gen_helper_neon_clz_u16(tmp, tmp); break; | |
5587 | case 2: gen_helper_clz(tmp, tmp); break; | |
9ee6e8bb PB |
5588 | default: return 1; |
5589 | } | |
5590 | break; | |
5591 | case 10: /* CNT */ | |
5592 | if (size != 0) | |
5593 | return 1; | |
dd8fbd78 | 5594 | gen_helper_neon_cnt_u8(tmp, tmp); |
9ee6e8bb PB |
5595 | break; |
5596 | case 11: /* VNOT */ | |
5597 | if (size != 0) | |
5598 | return 1; | |
dd8fbd78 | 5599 | tcg_gen_not_i32(tmp, tmp); |
9ee6e8bb PB |
5600 | break; |
5601 | case 14: /* VQABS */ | |
5602 | switch (size) { | |
dd8fbd78 FN |
5603 | case 0: gen_helper_neon_qabs_s8(tmp, cpu_env, tmp); break; |
5604 | case 1: gen_helper_neon_qabs_s16(tmp, cpu_env, tmp); break; | |
5605 | case 2: gen_helper_neon_qabs_s32(tmp, cpu_env, tmp); break; | |
9ee6e8bb PB |
5606 | default: return 1; |
5607 | } | |
5608 | break; | |
5609 | case 15: /* VQNEG */ | |
5610 | switch (size) { | |
dd8fbd78 FN |
5611 | case 0: gen_helper_neon_qneg_s8(tmp, cpu_env, tmp); break; |
5612 | case 1: gen_helper_neon_qneg_s16(tmp, cpu_env, tmp); break; | |
5613 | case 2: gen_helper_neon_qneg_s32(tmp, cpu_env, tmp); break; | |
9ee6e8bb PB |
5614 | default: return 1; |
5615 | } | |
5616 | break; | |
5617 | case 16: case 19: /* VCGT #0, VCLE #0 */ | |
dd8fbd78 | 5618 | tmp2 = tcg_const_i32(0); |
9ee6e8bb | 5619 | switch(size) { |
dd8fbd78 FN |
5620 | case 0: gen_helper_neon_cgt_s8(tmp, tmp, tmp2); break; |
5621 | case 1: gen_helper_neon_cgt_s16(tmp, tmp, tmp2); break; | |
5622 | case 2: gen_helper_neon_cgt_s32(tmp, tmp, tmp2); break; | |
9ee6e8bb PB |
5623 | default: return 1; |
5624 | } | |
dd8fbd78 | 5625 | tcg_temp_free(tmp2); |
9ee6e8bb | 5626 | if (op == 19) |
dd8fbd78 | 5627 | tcg_gen_not_i32(tmp, tmp); |
9ee6e8bb PB |
5628 | break; |
5629 | case 17: case 20: /* VCGE #0, VCLT #0 */ | |
dd8fbd78 | 5630 | tmp2 = tcg_const_i32(0); |
9ee6e8bb | 5631 | switch(size) { |
dd8fbd78 FN |
5632 | case 0: gen_helper_neon_cge_s8(tmp, tmp, tmp2); break; |
5633 | case 1: gen_helper_neon_cge_s16(tmp, tmp, tmp2); break; | |
5634 | case 2: gen_helper_neon_cge_s32(tmp, tmp, tmp2); break; | |
9ee6e8bb PB |
5635 | default: return 1; |
5636 | } | |
dd8fbd78 | 5637 | tcg_temp_free(tmp2); |
9ee6e8bb | 5638 | if (op == 20) |
dd8fbd78 | 5639 | tcg_gen_not_i32(tmp, tmp); |
9ee6e8bb PB |
5640 | break; |
5641 | case 18: /* VCEQ #0 */ | |
dd8fbd78 | 5642 | tmp2 = tcg_const_i32(0); |
9ee6e8bb | 5643 | switch(size) { |
dd8fbd78 FN |
5644 | case 0: gen_helper_neon_ceq_u8(tmp, tmp, tmp2); break; |
5645 | case 1: gen_helper_neon_ceq_u16(tmp, tmp, tmp2); break; | |
5646 | case 2: gen_helper_neon_ceq_u32(tmp, tmp, tmp2); break; | |
9ee6e8bb PB |
5647 | default: return 1; |
5648 | } | |
dd8fbd78 | 5649 | tcg_temp_free(tmp2); |
9ee6e8bb PB |
5650 | break; |
5651 | case 22: /* VABS */ | |
5652 | switch(size) { | |
dd8fbd78 FN |
5653 | case 0: gen_helper_neon_abs_s8(tmp, tmp); break; |
5654 | case 1: gen_helper_neon_abs_s16(tmp, tmp); break; | |
5655 | case 2: tcg_gen_abs_i32(tmp, tmp); break; | |
9ee6e8bb PB |
5656 | default: return 1; |
5657 | } | |
5658 | break; | |
5659 | case 23: /* VNEG */ | |
ad69471c PB |
5660 | if (size == 3) |
5661 | return 1; | |
dd8fbd78 FN |
5662 | tmp2 = tcg_const_i32(0); |
5663 | gen_neon_rsb(size, tmp, tmp2); | |
5664 | tcg_temp_free(tmp2); | |
9ee6e8bb PB |
5665 | break; |
5666 | case 24: case 27: /* Float VCGT #0, Float VCLE #0 */ | |
dd8fbd78 FN |
5667 | tmp2 = tcg_const_i32(0); |
5668 | gen_helper_neon_cgt_f32(tmp, tmp, tmp2); | |
5669 | tcg_temp_free(tmp2); | |
9ee6e8bb | 5670 | if (op == 27) |
dd8fbd78 | 5671 | tcg_gen_not_i32(tmp, tmp); |
9ee6e8bb PB |
5672 | break; |
5673 | case 25: case 28: /* Float VCGE #0, Float VCLT #0 */ | |
dd8fbd78 FN |
5674 | tmp2 = tcg_const_i32(0); |
5675 | gen_helper_neon_cge_f32(tmp, tmp, tmp2); | |
5676 | tcg_temp_free(tmp2); | |
9ee6e8bb | 5677 | if (op == 28) |
dd8fbd78 | 5678 | tcg_gen_not_i32(tmp, tmp); |
9ee6e8bb PB |
5679 | break; |
5680 | case 26: /* Float VCEQ #0 */ | |
dd8fbd78 FN |
5681 | tmp2 = tcg_const_i32(0); |
5682 | gen_helper_neon_ceq_f32(tmp, tmp, tmp2); | |
5683 | tcg_temp_free(tmp2); | |
9ee6e8bb PB |
5684 | break; |
5685 | case 30: /* Float VABS */ | |
4373f3ce | 5686 | gen_vfp_abs(0); |
9ee6e8bb PB |
5687 | break; |
5688 | case 31: /* Float VNEG */ | |
4373f3ce | 5689 | gen_vfp_neg(0); |
9ee6e8bb PB |
5690 | break; |
5691 | case 32: /* VSWP */ | |
dd8fbd78 FN |
5692 | tmp2 = neon_load_reg(rd, pass); |
5693 | neon_store_reg(rm, pass, tmp2); | |
9ee6e8bb PB |
5694 | break; |
5695 | case 33: /* VTRN */ | |
dd8fbd78 | 5696 | tmp2 = neon_load_reg(rd, pass); |
9ee6e8bb | 5697 | switch (size) { |
dd8fbd78 FN |
5698 | case 0: gen_neon_trn_u8(tmp, tmp2); break; |
5699 | case 1: gen_neon_trn_u16(tmp, tmp2); break; | |
9ee6e8bb PB |
5700 | case 2: abort(); |
5701 | default: return 1; | |
5702 | } | |
dd8fbd78 | 5703 | neon_store_reg(rm, pass, tmp2); |
9ee6e8bb PB |
5704 | break; |
5705 | case 56: /* Integer VRECPE */ | |
dd8fbd78 | 5706 | gen_helper_recpe_u32(tmp, tmp, cpu_env); |
9ee6e8bb PB |
5707 | break; |
5708 | case 57: /* Integer VRSQRTE */ | |
dd8fbd78 | 5709 | gen_helper_rsqrte_u32(tmp, tmp, cpu_env); |
9ee6e8bb PB |
5710 | break; |
5711 | case 58: /* Float VRECPE */ | |
4373f3ce | 5712 | gen_helper_recpe_f32(cpu_F0s, cpu_F0s, cpu_env); |
9ee6e8bb PB |
5713 | break; |
5714 | case 59: /* Float VRSQRTE */ | |
4373f3ce | 5715 | gen_helper_rsqrte_f32(cpu_F0s, cpu_F0s, cpu_env); |
9ee6e8bb PB |
5716 | break; |
5717 | case 60: /* VCVT.F32.S32 */ | |
d3587ef8 | 5718 | gen_vfp_sito(0); |
9ee6e8bb PB |
5719 | break; |
5720 | case 61: /* VCVT.F32.U32 */ | |
d3587ef8 | 5721 | gen_vfp_uito(0); |
9ee6e8bb PB |
5722 | break; |
5723 | case 62: /* VCVT.S32.F32 */ | |
d3587ef8 | 5724 | gen_vfp_tosiz(0); |
9ee6e8bb PB |
5725 | break; |
5726 | case 63: /* VCVT.U32.F32 */ | |
d3587ef8 | 5727 | gen_vfp_touiz(0); |
9ee6e8bb PB |
5728 | break; |
5729 | default: | |
5730 | /* Reserved: 21, 29, 39-56 */ | |
5731 | return 1; | |
5732 | } | |
5733 | if (op == 30 || op == 31 || op >= 58) { | |
4373f3ce PB |
5734 | tcg_gen_st_f32(cpu_F0s, cpu_env, |
5735 | neon_reg_offset(rd, pass)); | |
9ee6e8bb | 5736 | } else { |
dd8fbd78 | 5737 | neon_store_reg(rd, pass, tmp); |
9ee6e8bb PB |
5738 | } |
5739 | } | |
5740 | break; | |
5741 | } | |
5742 | } else if ((insn & (1 << 10)) == 0) { | |
5743 | /* VTBL, VTBX. */ | |
3018f259 | 5744 | n = ((insn >> 5) & 0x18) + 8; |
9ee6e8bb | 5745 | if (insn & (1 << 6)) { |
8f8e3aa4 | 5746 | tmp = neon_load_reg(rd, 0); |
9ee6e8bb | 5747 | } else { |
8f8e3aa4 PB |
5748 | tmp = new_tmp(); |
5749 | tcg_gen_movi_i32(tmp, 0); | |
9ee6e8bb | 5750 | } |
8f8e3aa4 | 5751 | tmp2 = neon_load_reg(rm, 0); |
b75263d6 JR |
5752 | tmp4 = tcg_const_i32(rn); |
5753 | tmp5 = tcg_const_i32(n); | |
5754 | gen_helper_neon_tbl(tmp2, tmp2, tmp, tmp4, tmp5); | |
3018f259 | 5755 | dead_tmp(tmp); |
9ee6e8bb | 5756 | if (insn & (1 << 6)) { |
8f8e3aa4 | 5757 | tmp = neon_load_reg(rd, 1); |
9ee6e8bb | 5758 | } else { |
8f8e3aa4 PB |
5759 | tmp = new_tmp(); |
5760 | tcg_gen_movi_i32(tmp, 0); | |
9ee6e8bb | 5761 | } |
8f8e3aa4 | 5762 | tmp3 = neon_load_reg(rm, 1); |
b75263d6 | 5763 | gen_helper_neon_tbl(tmp3, tmp3, tmp, tmp4, tmp5); |
25aeb69b JR |
5764 | tcg_temp_free_i32(tmp5); |
5765 | tcg_temp_free_i32(tmp4); | |
8f8e3aa4 | 5766 | neon_store_reg(rd, 0, tmp2); |
3018f259 PB |
5767 | neon_store_reg(rd, 1, tmp3); |
5768 | dead_tmp(tmp); | |
9ee6e8bb PB |
5769 | } else if ((insn & 0x380) == 0) { |
5770 | /* VDUP */ | |
5771 | if (insn & (1 << 19)) { | |
dd8fbd78 | 5772 | tmp = neon_load_reg(rm, 1); |
9ee6e8bb | 5773 | } else { |
dd8fbd78 | 5774 | tmp = neon_load_reg(rm, 0); |
9ee6e8bb PB |
5775 | } |
5776 | if (insn & (1 << 16)) { | |
dd8fbd78 | 5777 | gen_neon_dup_u8(tmp, ((insn >> 17) & 3) * 8); |
9ee6e8bb PB |
5778 | } else if (insn & (1 << 17)) { |
5779 | if ((insn >> 18) & 1) | |
dd8fbd78 | 5780 | gen_neon_dup_high16(tmp); |
9ee6e8bb | 5781 | else |
dd8fbd78 | 5782 | gen_neon_dup_low16(tmp); |
9ee6e8bb PB |
5783 | } |
5784 | for (pass = 0; pass < (q ? 4 : 2); pass++) { | |
dd8fbd78 FN |
5785 | tmp2 = new_tmp(); |
5786 | tcg_gen_mov_i32(tmp2, tmp); | |
5787 | neon_store_reg(rd, pass, tmp2); | |
9ee6e8bb | 5788 | } |
dd8fbd78 | 5789 | dead_tmp(tmp); |
9ee6e8bb PB |
5790 | } else { |
5791 | return 1; | |
5792 | } | |
5793 | } | |
5794 | } | |
5795 | return 0; | |
5796 | } | |
5797 | ||
fe1479c3 PB |
5798 | static int disas_cp14_read(CPUState * env, DisasContext *s, uint32_t insn) |
5799 | { | |
5800 | int crn = (insn >> 16) & 0xf; | |
5801 | int crm = insn & 0xf; | |
5802 | int op1 = (insn >> 21) & 7; | |
5803 | int op2 = (insn >> 5) & 7; | |
5804 | int rt = (insn >> 12) & 0xf; | |
5805 | TCGv tmp; | |
5806 | ||
5807 | if (arm_feature(env, ARM_FEATURE_THUMB2EE)) { | |
5808 | if (op1 == 6 && crn == 0 && crm == 0 && op2 == 0) { | |
5809 | /* TEECR */ | |
5810 | if (IS_USER(s)) | |
5811 | return 1; | |
5812 | tmp = load_cpu_field(teecr); | |
5813 | store_reg(s, rt, tmp); | |
5814 | return 0; | |
5815 | } | |
5816 | if (op1 == 6 && crn == 1 && crm == 0 && op2 == 0) { | |
5817 | /* TEEHBR */ | |
5818 | if (IS_USER(s) && (env->teecr & 1)) | |
5819 | return 1; | |
5820 | tmp = load_cpu_field(teehbr); | |
5821 | store_reg(s, rt, tmp); | |
5822 | return 0; | |
5823 | } | |
5824 | } | |
5825 | fprintf(stderr, "Unknown cp14 read op1:%d crn:%d crm:%d op2:%d\n", | |
5826 | op1, crn, crm, op2); | |
5827 | return 1; | |
5828 | } | |
5829 | ||
5830 | static int disas_cp14_write(CPUState * env, DisasContext *s, uint32_t insn) | |
5831 | { | |
5832 | int crn = (insn >> 16) & 0xf; | |
5833 | int crm = insn & 0xf; | |
5834 | int op1 = (insn >> 21) & 7; | |
5835 | int op2 = (insn >> 5) & 7; | |
5836 | int rt = (insn >> 12) & 0xf; | |
5837 | TCGv tmp; | |
5838 | ||
5839 | if (arm_feature(env, ARM_FEATURE_THUMB2EE)) { | |
5840 | if (op1 == 6 && crn == 0 && crm == 0 && op2 == 0) { | |
5841 | /* TEECR */ | |
5842 | if (IS_USER(s)) | |
5843 | return 1; | |
5844 | tmp = load_reg(s, rt); | |
5845 | gen_helper_set_teecr(cpu_env, tmp); | |
5846 | dead_tmp(tmp); | |
5847 | return 0; | |
5848 | } | |
5849 | if (op1 == 6 && crn == 1 && crm == 0 && op2 == 0) { | |
5850 | /* TEEHBR */ | |
5851 | if (IS_USER(s) && (env->teecr & 1)) | |
5852 | return 1; | |
5853 | tmp = load_reg(s, rt); | |
5854 | store_cpu_field(tmp, teehbr); | |
5855 | return 0; | |
5856 | } | |
5857 | } | |
5858 | fprintf(stderr, "Unknown cp14 write op1:%d crn:%d crm:%d op2:%d\n", | |
5859 | op1, crn, crm, op2); | |
5860 | return 1; | |
5861 | } | |
5862 | ||
9ee6e8bb PB |
5863 | static int disas_coproc_insn(CPUState * env, DisasContext *s, uint32_t insn) |
5864 | { | |
5865 | int cpnum; | |
5866 | ||
5867 | cpnum = (insn >> 8) & 0xf; | |
5868 | if (arm_feature(env, ARM_FEATURE_XSCALE) | |
5869 | && ((env->cp15.c15_cpar ^ 0x3fff) & (1 << cpnum))) | |
5870 | return 1; | |
5871 | ||
5872 | switch (cpnum) { | |
5873 | case 0: | |
5874 | case 1: | |
5875 | if (arm_feature(env, ARM_FEATURE_IWMMXT)) { | |
5876 | return disas_iwmmxt_insn(env, s, insn); | |
5877 | } else if (arm_feature(env, ARM_FEATURE_XSCALE)) { | |
5878 | return disas_dsp_insn(env, s, insn); | |
5879 | } | |
5880 | return 1; | |
5881 | case 10: | |
5882 | case 11: | |
5883 | return disas_vfp_insn (env, s, insn); | |
fe1479c3 PB |
5884 | case 14: |
5885 | /* Coprocessors 7-15 are architecturally reserved by ARM. | |
5886 | Unfortunately Intel decided to ignore this. */ | |
5887 | if (arm_feature(env, ARM_FEATURE_XSCALE)) | |
5888 | goto board; | |
5889 | if (insn & (1 << 20)) | |
5890 | return disas_cp14_read(env, s, insn); | |
5891 | else | |
5892 | return disas_cp14_write(env, s, insn); | |
9ee6e8bb PB |
5893 | case 15: |
5894 | return disas_cp15_insn (env, s, insn); | |
5895 | default: | |
fe1479c3 | 5896 | board: |
9ee6e8bb PB |
5897 | /* Unknown coprocessor. See if the board has hooked it. */ |
5898 | return disas_cp_insn (env, s, insn); | |
5899 | } | |
5900 | } | |
5901 | ||
5e3f878a PB |
5902 | |
5903 | /* Store a 64-bit value to a register pair. Clobbers val. */ | |
a7812ae4 | 5904 | static void gen_storeq_reg(DisasContext *s, int rlow, int rhigh, TCGv_i64 val) |
5e3f878a PB |
5905 | { |
5906 | TCGv tmp; | |
5907 | tmp = new_tmp(); | |
5908 | tcg_gen_trunc_i64_i32(tmp, val); | |
5909 | store_reg(s, rlow, tmp); | |
5910 | tmp = new_tmp(); | |
5911 | tcg_gen_shri_i64(val, val, 32); | |
5912 | tcg_gen_trunc_i64_i32(tmp, val); | |
5913 | store_reg(s, rhigh, tmp); | |
5914 | } | |
5915 | ||
5916 | /* load a 32-bit value from a register and perform a 64-bit accumulate. */ | |
a7812ae4 | 5917 | static void gen_addq_lo(DisasContext *s, TCGv_i64 val, int rlow) |
5e3f878a | 5918 | { |
a7812ae4 | 5919 | TCGv_i64 tmp; |
5e3f878a PB |
5920 | TCGv tmp2; |
5921 | ||
36aa55dc | 5922 | /* Load value and extend to 64 bits. */ |
a7812ae4 | 5923 | tmp = tcg_temp_new_i64(); |
5e3f878a PB |
5924 | tmp2 = load_reg(s, rlow); |
5925 | tcg_gen_extu_i32_i64(tmp, tmp2); | |
5926 | dead_tmp(tmp2); | |
5927 | tcg_gen_add_i64(val, val, tmp); | |
b75263d6 | 5928 | tcg_temp_free_i64(tmp); |
5e3f878a PB |
5929 | } |
5930 | ||
5931 | /* load and add a 64-bit value from a register pair. */ | |
a7812ae4 | 5932 | static void gen_addq(DisasContext *s, TCGv_i64 val, int rlow, int rhigh) |
5e3f878a | 5933 | { |
a7812ae4 | 5934 | TCGv_i64 tmp; |
36aa55dc PB |
5935 | TCGv tmpl; |
5936 | TCGv tmph; | |
5e3f878a PB |
5937 | |
5938 | /* Load 64-bit value rd:rn. */ | |
36aa55dc PB |
5939 | tmpl = load_reg(s, rlow); |
5940 | tmph = load_reg(s, rhigh); | |
a7812ae4 | 5941 | tmp = tcg_temp_new_i64(); |
36aa55dc PB |
5942 | tcg_gen_concat_i32_i64(tmp, tmpl, tmph); |
5943 | dead_tmp(tmpl); | |
5944 | dead_tmp(tmph); | |
5e3f878a | 5945 | tcg_gen_add_i64(val, val, tmp); |
b75263d6 | 5946 | tcg_temp_free_i64(tmp); |
5e3f878a PB |
5947 | } |
5948 | ||
5949 | /* Set N and Z flags from a 64-bit value. */ | |
a7812ae4 | 5950 | static void gen_logicq_cc(TCGv_i64 val) |
5e3f878a PB |
5951 | { |
5952 | TCGv tmp = new_tmp(); | |
5953 | gen_helper_logicq_cc(tmp, val); | |
6fbe23d5 PB |
5954 | gen_logic_CC(tmp); |
5955 | dead_tmp(tmp); | |
5e3f878a PB |
5956 | } |
5957 | ||
426f5abc PB |
5958 | /* Load/Store exclusive instructions are implemented by remembering |
5959 | the value/address loaded, and seeing if these are the same | |
5960 | when the store is performed. This should be is sufficient to implement | |
5961 | the architecturally mandated semantics, and avoids having to monitor | |
5962 | regular stores. | |
5963 | ||
5964 | In system emulation mode only one CPU will be running at once, so | |
5965 | this sequence is effectively atomic. In user emulation mode we | |
5966 | throw an exception and handle the atomic operation elsewhere. */ | |
5967 | static void gen_load_exclusive(DisasContext *s, int rt, int rt2, | |
5968 | TCGv addr, int size) | |
5969 | { | |
5970 | TCGv tmp; | |
5971 | ||
5972 | switch (size) { | |
5973 | case 0: | |
5974 | tmp = gen_ld8u(addr, IS_USER(s)); | |
5975 | break; | |
5976 | case 1: | |
5977 | tmp = gen_ld16u(addr, IS_USER(s)); | |
5978 | break; | |
5979 | case 2: | |
5980 | case 3: | |
5981 | tmp = gen_ld32(addr, IS_USER(s)); | |
5982 | break; | |
5983 | default: | |
5984 | abort(); | |
5985 | } | |
5986 | tcg_gen_mov_i32(cpu_exclusive_val, tmp); | |
5987 | store_reg(s, rt, tmp); | |
5988 | if (size == 3) { | |
2c9adbda PM |
5989 | TCGv tmp2 = new_tmp(); |
5990 | tcg_gen_addi_i32(tmp2, addr, 4); | |
5991 | tmp = gen_ld32(tmp2, IS_USER(s)); | |
5992 | dead_tmp(tmp2); | |
426f5abc PB |
5993 | tcg_gen_mov_i32(cpu_exclusive_high, tmp); |
5994 | store_reg(s, rt2, tmp); | |
5995 | } | |
5996 | tcg_gen_mov_i32(cpu_exclusive_addr, addr); | |
5997 | } | |
5998 | ||
5999 | static void gen_clrex(DisasContext *s) | |
6000 | { | |
6001 | tcg_gen_movi_i32(cpu_exclusive_addr, -1); | |
6002 | } | |
6003 | ||
6004 | #ifdef CONFIG_USER_ONLY | |
6005 | static void gen_store_exclusive(DisasContext *s, int rd, int rt, int rt2, | |
6006 | TCGv addr, int size) | |
6007 | { | |
6008 | tcg_gen_mov_i32(cpu_exclusive_test, addr); | |
6009 | tcg_gen_movi_i32(cpu_exclusive_info, | |
6010 | size | (rd << 4) | (rt << 8) | (rt2 << 12)); | |
bc4a0de0 | 6011 | gen_exception_insn(s, 4, EXCP_STREX); |
426f5abc PB |
6012 | } |
6013 | #else | |
6014 | static void gen_store_exclusive(DisasContext *s, int rd, int rt, int rt2, | |
6015 | TCGv addr, int size) | |
6016 | { | |
6017 | TCGv tmp; | |
6018 | int done_label; | |
6019 | int fail_label; | |
6020 | ||
6021 | /* if (env->exclusive_addr == addr && env->exclusive_val == [addr]) { | |
6022 | [addr] = {Rt}; | |
6023 | {Rd} = 0; | |
6024 | } else { | |
6025 | {Rd} = 1; | |
6026 | } */ | |
6027 | fail_label = gen_new_label(); | |
6028 | done_label = gen_new_label(); | |
6029 | tcg_gen_brcond_i32(TCG_COND_NE, addr, cpu_exclusive_addr, fail_label); | |
6030 | switch (size) { | |
6031 | case 0: | |
6032 | tmp = gen_ld8u(addr, IS_USER(s)); | |
6033 | break; | |
6034 | case 1: | |
6035 | tmp = gen_ld16u(addr, IS_USER(s)); | |
6036 | break; | |
6037 | case 2: | |
6038 | case 3: | |
6039 | tmp = gen_ld32(addr, IS_USER(s)); | |
6040 | break; | |
6041 | default: | |
6042 | abort(); | |
6043 | } | |
6044 | tcg_gen_brcond_i32(TCG_COND_NE, tmp, cpu_exclusive_val, fail_label); | |
6045 | dead_tmp(tmp); | |
6046 | if (size == 3) { | |
6047 | TCGv tmp2 = new_tmp(); | |
6048 | tcg_gen_addi_i32(tmp2, addr, 4); | |
2c9adbda | 6049 | tmp = gen_ld32(tmp2, IS_USER(s)); |
426f5abc PB |
6050 | dead_tmp(tmp2); |
6051 | tcg_gen_brcond_i32(TCG_COND_NE, tmp, cpu_exclusive_high, fail_label); | |
6052 | dead_tmp(tmp); | |
6053 | } | |
6054 | tmp = load_reg(s, rt); | |
6055 | switch (size) { | |
6056 | case 0: | |
6057 | gen_st8(tmp, addr, IS_USER(s)); | |
6058 | break; | |
6059 | case 1: | |
6060 | gen_st16(tmp, addr, IS_USER(s)); | |
6061 | break; | |
6062 | case 2: | |
6063 | case 3: | |
6064 | gen_st32(tmp, addr, IS_USER(s)); | |
6065 | break; | |
6066 | default: | |
6067 | abort(); | |
6068 | } | |
6069 | if (size == 3) { | |
6070 | tcg_gen_addi_i32(addr, addr, 4); | |
6071 | tmp = load_reg(s, rt2); | |
6072 | gen_st32(tmp, addr, IS_USER(s)); | |
6073 | } | |
6074 | tcg_gen_movi_i32(cpu_R[rd], 0); | |
6075 | tcg_gen_br(done_label); | |
6076 | gen_set_label(fail_label); | |
6077 | tcg_gen_movi_i32(cpu_R[rd], 1); | |
6078 | gen_set_label(done_label); | |
6079 | tcg_gen_movi_i32(cpu_exclusive_addr, -1); | |
6080 | } | |
6081 | #endif | |
6082 | ||
9ee6e8bb PB |
6083 | static void disas_arm_insn(CPUState * env, DisasContext *s) |
6084 | { | |
6085 | unsigned int cond, insn, val, op1, i, shift, rm, rs, rn, rd, sh; | |
b26eefb6 | 6086 | TCGv tmp; |
3670669c | 6087 | TCGv tmp2; |
6ddbc6e4 | 6088 | TCGv tmp3; |
b0109805 | 6089 | TCGv addr; |
a7812ae4 | 6090 | TCGv_i64 tmp64; |
9ee6e8bb PB |
6091 | |
6092 | insn = ldl_code(s->pc); | |
6093 | s->pc += 4; | |
6094 | ||
6095 | /* M variants do not implement ARM mode. */ | |
6096 | if (IS_M(env)) | |
6097 | goto illegal_op; | |
6098 | cond = insn >> 28; | |
6099 | if (cond == 0xf){ | |
6100 | /* Unconditional instructions. */ | |
6101 | if (((insn >> 25) & 7) == 1) { | |
6102 | /* NEON Data processing. */ | |
6103 | if (!arm_feature(env, ARM_FEATURE_NEON)) | |
6104 | goto illegal_op; | |
6105 | ||
6106 | if (disas_neon_data_insn(env, s, insn)) | |
6107 | goto illegal_op; | |
6108 | return; | |
6109 | } | |
6110 | if ((insn & 0x0f100000) == 0x04000000) { | |
6111 | /* NEON load/store. */ | |
6112 | if (!arm_feature(env, ARM_FEATURE_NEON)) | |
6113 | goto illegal_op; | |
6114 | ||
6115 | if (disas_neon_ls_insn(env, s, insn)) | |
6116 | goto illegal_op; | |
6117 | return; | |
6118 | } | |
3d185e5d PM |
6119 | if (((insn & 0x0f30f000) == 0x0510f000) || |
6120 | ((insn & 0x0f30f010) == 0x0710f000)) { | |
6121 | if ((insn & (1 << 22)) == 0) { | |
6122 | /* PLDW; v7MP */ | |
6123 | if (!arm_feature(env, ARM_FEATURE_V7MP)) { | |
6124 | goto illegal_op; | |
6125 | } | |
6126 | } | |
6127 | /* Otherwise PLD; v5TE+ */ | |
6128 | return; | |
6129 | } | |
6130 | if (((insn & 0x0f70f000) == 0x0450f000) || | |
6131 | ((insn & 0x0f70f010) == 0x0650f000)) { | |
6132 | ARCH(7); | |
6133 | return; /* PLI; V7 */ | |
6134 | } | |
6135 | if (((insn & 0x0f700000) == 0x04100000) || | |
6136 | ((insn & 0x0f700010) == 0x06100000)) { | |
6137 | if (!arm_feature(env, ARM_FEATURE_V7MP)) { | |
6138 | goto illegal_op; | |
6139 | } | |
6140 | return; /* v7MP: Unallocated memory hint: must NOP */ | |
6141 | } | |
6142 | ||
6143 | if ((insn & 0x0ffffdff) == 0x01010000) { | |
9ee6e8bb PB |
6144 | ARCH(6); |
6145 | /* setend */ | |
6146 | if (insn & (1 << 9)) { | |
6147 | /* BE8 mode not implemented. */ | |
6148 | goto illegal_op; | |
6149 | } | |
6150 | return; | |
6151 | } else if ((insn & 0x0fffff00) == 0x057ff000) { | |
6152 | switch ((insn >> 4) & 0xf) { | |
6153 | case 1: /* clrex */ | |
6154 | ARCH(6K); | |
426f5abc | 6155 | gen_clrex(s); |
9ee6e8bb PB |
6156 | return; |
6157 | case 4: /* dsb */ | |
6158 | case 5: /* dmb */ | |
6159 | case 6: /* isb */ | |
6160 | ARCH(7); | |
6161 | /* We don't emulate caches so these are a no-op. */ | |
6162 | return; | |
6163 | default: | |
6164 | goto illegal_op; | |
6165 | } | |
6166 | } else if ((insn & 0x0e5fffe0) == 0x084d0500) { | |
6167 | /* srs */ | |
c67b6b71 | 6168 | int32_t offset; |
9ee6e8bb PB |
6169 | if (IS_USER(s)) |
6170 | goto illegal_op; | |
6171 | ARCH(6); | |
6172 | op1 = (insn & 0x1f); | |
39ea3d4e PM |
6173 | addr = new_tmp(); |
6174 | tmp = tcg_const_i32(op1); | |
6175 | gen_helper_get_r13_banked(addr, cpu_env, tmp); | |
6176 | tcg_temp_free_i32(tmp); | |
9ee6e8bb PB |
6177 | i = (insn >> 23) & 3; |
6178 | switch (i) { | |
6179 | case 0: offset = -4; break; /* DA */ | |
c67b6b71 FN |
6180 | case 1: offset = 0; break; /* IA */ |
6181 | case 2: offset = -8; break; /* DB */ | |
9ee6e8bb PB |
6182 | case 3: offset = 4; break; /* IB */ |
6183 | default: abort(); | |
6184 | } | |
6185 | if (offset) | |
b0109805 PB |
6186 | tcg_gen_addi_i32(addr, addr, offset); |
6187 | tmp = load_reg(s, 14); | |
6188 | gen_st32(tmp, addr, 0); | |
c67b6b71 | 6189 | tmp = load_cpu_field(spsr); |
b0109805 PB |
6190 | tcg_gen_addi_i32(addr, addr, 4); |
6191 | gen_st32(tmp, addr, 0); | |
9ee6e8bb PB |
6192 | if (insn & (1 << 21)) { |
6193 | /* Base writeback. */ | |
6194 | switch (i) { | |
6195 | case 0: offset = -8; break; | |
c67b6b71 FN |
6196 | case 1: offset = 4; break; |
6197 | case 2: offset = -4; break; | |
9ee6e8bb PB |
6198 | case 3: offset = 0; break; |
6199 | default: abort(); | |
6200 | } | |
6201 | if (offset) | |
c67b6b71 | 6202 | tcg_gen_addi_i32(addr, addr, offset); |
39ea3d4e PM |
6203 | tmp = tcg_const_i32(op1); |
6204 | gen_helper_set_r13_banked(cpu_env, tmp, addr); | |
6205 | tcg_temp_free_i32(tmp); | |
6206 | dead_tmp(addr); | |
b0109805 PB |
6207 | } else { |
6208 | dead_tmp(addr); | |
9ee6e8bb | 6209 | } |
a990f58f | 6210 | return; |
ea825eee | 6211 | } else if ((insn & 0x0e50ffe0) == 0x08100a00) { |
9ee6e8bb | 6212 | /* rfe */ |
c67b6b71 | 6213 | int32_t offset; |
9ee6e8bb PB |
6214 | if (IS_USER(s)) |
6215 | goto illegal_op; | |
6216 | ARCH(6); | |
6217 | rn = (insn >> 16) & 0xf; | |
b0109805 | 6218 | addr = load_reg(s, rn); |
9ee6e8bb PB |
6219 | i = (insn >> 23) & 3; |
6220 | switch (i) { | |
b0109805 | 6221 | case 0: offset = -4; break; /* DA */ |
c67b6b71 FN |
6222 | case 1: offset = 0; break; /* IA */ |
6223 | case 2: offset = -8; break; /* DB */ | |
b0109805 | 6224 | case 3: offset = 4; break; /* IB */ |
9ee6e8bb PB |
6225 | default: abort(); |
6226 | } | |
6227 | if (offset) | |
b0109805 PB |
6228 | tcg_gen_addi_i32(addr, addr, offset); |
6229 | /* Load PC into tmp and CPSR into tmp2. */ | |
6230 | tmp = gen_ld32(addr, 0); | |
6231 | tcg_gen_addi_i32(addr, addr, 4); | |
6232 | tmp2 = gen_ld32(addr, 0); | |
9ee6e8bb PB |
6233 | if (insn & (1 << 21)) { |
6234 | /* Base writeback. */ | |
6235 | switch (i) { | |
b0109805 | 6236 | case 0: offset = -8; break; |
c67b6b71 FN |
6237 | case 1: offset = 4; break; |
6238 | case 2: offset = -4; break; | |
b0109805 | 6239 | case 3: offset = 0; break; |
9ee6e8bb PB |
6240 | default: abort(); |
6241 | } | |
6242 | if (offset) | |
b0109805 PB |
6243 | tcg_gen_addi_i32(addr, addr, offset); |
6244 | store_reg(s, rn, addr); | |
6245 | } else { | |
6246 | dead_tmp(addr); | |
9ee6e8bb | 6247 | } |
b0109805 | 6248 | gen_rfe(s, tmp, tmp2); |
c67b6b71 | 6249 | return; |
9ee6e8bb PB |
6250 | } else if ((insn & 0x0e000000) == 0x0a000000) { |
6251 | /* branch link and change to thumb (blx <offset>) */ | |
6252 | int32_t offset; | |
6253 | ||
6254 | val = (uint32_t)s->pc; | |
d9ba4830 PB |
6255 | tmp = new_tmp(); |
6256 | tcg_gen_movi_i32(tmp, val); | |
6257 | store_reg(s, 14, tmp); | |
9ee6e8bb PB |
6258 | /* Sign-extend the 24-bit offset */ |
6259 | offset = (((int32_t)insn) << 8) >> 8; | |
6260 | /* offset * 4 + bit24 * 2 + (thumb bit) */ | |
6261 | val += (offset << 2) | ((insn >> 23) & 2) | 1; | |
6262 | /* pipeline offset */ | |
6263 | val += 4; | |
d9ba4830 | 6264 | gen_bx_im(s, val); |
9ee6e8bb PB |
6265 | return; |
6266 | } else if ((insn & 0x0e000f00) == 0x0c000100) { | |
6267 | if (arm_feature(env, ARM_FEATURE_IWMMXT)) { | |
6268 | /* iWMMXt register transfer. */ | |
6269 | if (env->cp15.c15_cpar & (1 << 1)) | |
6270 | if (!disas_iwmmxt_insn(env, s, insn)) | |
6271 | return; | |
6272 | } | |
6273 | } else if ((insn & 0x0fe00000) == 0x0c400000) { | |
6274 | /* Coprocessor double register transfer. */ | |
6275 | } else if ((insn & 0x0f000010) == 0x0e000010) { | |
6276 | /* Additional coprocessor register transfer. */ | |
7997d92f | 6277 | } else if ((insn & 0x0ff10020) == 0x01000000) { |
9ee6e8bb PB |
6278 | uint32_t mask; |
6279 | uint32_t val; | |
6280 | /* cps (privileged) */ | |
6281 | if (IS_USER(s)) | |
6282 | return; | |
6283 | mask = val = 0; | |
6284 | if (insn & (1 << 19)) { | |
6285 | if (insn & (1 << 8)) | |
6286 | mask |= CPSR_A; | |
6287 | if (insn & (1 << 7)) | |
6288 | mask |= CPSR_I; | |
6289 | if (insn & (1 << 6)) | |
6290 | mask |= CPSR_F; | |
6291 | if (insn & (1 << 18)) | |
6292 | val |= mask; | |
6293 | } | |
7997d92f | 6294 | if (insn & (1 << 17)) { |
9ee6e8bb PB |
6295 | mask |= CPSR_M; |
6296 | val |= (insn & 0x1f); | |
6297 | } | |
6298 | if (mask) { | |
2fbac54b | 6299 | gen_set_psr_im(s, mask, 0, val); |
9ee6e8bb PB |
6300 | } |
6301 | return; | |
6302 | } | |
6303 | goto illegal_op; | |
6304 | } | |
6305 | if (cond != 0xe) { | |
6306 | /* if not always execute, we generate a conditional jump to | |
6307 | next instruction */ | |
6308 | s->condlabel = gen_new_label(); | |
d9ba4830 | 6309 | gen_test_cc(cond ^ 1, s->condlabel); |
9ee6e8bb PB |
6310 | s->condjmp = 1; |
6311 | } | |
6312 | if ((insn & 0x0f900000) == 0x03000000) { | |
6313 | if ((insn & (1 << 21)) == 0) { | |
6314 | ARCH(6T2); | |
6315 | rd = (insn >> 12) & 0xf; | |
6316 | val = ((insn >> 4) & 0xf000) | (insn & 0xfff); | |
6317 | if ((insn & (1 << 22)) == 0) { | |
6318 | /* MOVW */ | |
5e3f878a PB |
6319 | tmp = new_tmp(); |
6320 | tcg_gen_movi_i32(tmp, val); | |
9ee6e8bb PB |
6321 | } else { |
6322 | /* MOVT */ | |
5e3f878a | 6323 | tmp = load_reg(s, rd); |
86831435 | 6324 | tcg_gen_ext16u_i32(tmp, tmp); |
5e3f878a | 6325 | tcg_gen_ori_i32(tmp, tmp, val << 16); |
9ee6e8bb | 6326 | } |
5e3f878a | 6327 | store_reg(s, rd, tmp); |
9ee6e8bb PB |
6328 | } else { |
6329 | if (((insn >> 12) & 0xf) != 0xf) | |
6330 | goto illegal_op; | |
6331 | if (((insn >> 16) & 0xf) == 0) { | |
6332 | gen_nop_hint(s, insn & 0xff); | |
6333 | } else { | |
6334 | /* CPSR = immediate */ | |
6335 | val = insn & 0xff; | |
6336 | shift = ((insn >> 8) & 0xf) * 2; | |
6337 | if (shift) | |
6338 | val = (val >> shift) | (val << (32 - shift)); | |
9ee6e8bb | 6339 | i = ((insn & (1 << 22)) != 0); |
2fbac54b | 6340 | if (gen_set_psr_im(s, msr_mask(env, s, (insn >> 16) & 0xf, i), i, val)) |
9ee6e8bb PB |
6341 | goto illegal_op; |
6342 | } | |
6343 | } | |
6344 | } else if ((insn & 0x0f900000) == 0x01000000 | |
6345 | && (insn & 0x00000090) != 0x00000090) { | |
6346 | /* miscellaneous instructions */ | |
6347 | op1 = (insn >> 21) & 3; | |
6348 | sh = (insn >> 4) & 0xf; | |
6349 | rm = insn & 0xf; | |
6350 | switch (sh) { | |
6351 | case 0x0: /* move program status register */ | |
6352 | if (op1 & 1) { | |
6353 | /* PSR = reg */ | |
2fbac54b | 6354 | tmp = load_reg(s, rm); |
9ee6e8bb | 6355 | i = ((op1 & 2) != 0); |
2fbac54b | 6356 | if (gen_set_psr(s, msr_mask(env, s, (insn >> 16) & 0xf, i), i, tmp)) |
9ee6e8bb PB |
6357 | goto illegal_op; |
6358 | } else { | |
6359 | /* reg = PSR */ | |
6360 | rd = (insn >> 12) & 0xf; | |
6361 | if (op1 & 2) { | |
6362 | if (IS_USER(s)) | |
6363 | goto illegal_op; | |
d9ba4830 | 6364 | tmp = load_cpu_field(spsr); |
9ee6e8bb | 6365 | } else { |
d9ba4830 PB |
6366 | tmp = new_tmp(); |
6367 | gen_helper_cpsr_read(tmp); | |
9ee6e8bb | 6368 | } |
d9ba4830 | 6369 | store_reg(s, rd, tmp); |
9ee6e8bb PB |
6370 | } |
6371 | break; | |
6372 | case 0x1: | |
6373 | if (op1 == 1) { | |
6374 | /* branch/exchange thumb (bx). */ | |
d9ba4830 PB |
6375 | tmp = load_reg(s, rm); |
6376 | gen_bx(s, tmp); | |
9ee6e8bb PB |
6377 | } else if (op1 == 3) { |
6378 | /* clz */ | |
6379 | rd = (insn >> 12) & 0xf; | |
1497c961 PB |
6380 | tmp = load_reg(s, rm); |
6381 | gen_helper_clz(tmp, tmp); | |
6382 | store_reg(s, rd, tmp); | |
9ee6e8bb PB |
6383 | } else { |
6384 | goto illegal_op; | |
6385 | } | |
6386 | break; | |
6387 | case 0x2: | |
6388 | if (op1 == 1) { | |
6389 | ARCH(5J); /* bxj */ | |
6390 | /* Trivial implementation equivalent to bx. */ | |
d9ba4830 PB |
6391 | tmp = load_reg(s, rm); |
6392 | gen_bx(s, tmp); | |
9ee6e8bb PB |
6393 | } else { |
6394 | goto illegal_op; | |
6395 | } | |
6396 | break; | |
6397 | case 0x3: | |
6398 | if (op1 != 1) | |
6399 | goto illegal_op; | |
6400 | ||
6401 | /* branch link/exchange thumb (blx) */ | |
d9ba4830 PB |
6402 | tmp = load_reg(s, rm); |
6403 | tmp2 = new_tmp(); | |
6404 | tcg_gen_movi_i32(tmp2, s->pc); | |
6405 | store_reg(s, 14, tmp2); | |
6406 | gen_bx(s, tmp); | |
9ee6e8bb PB |
6407 | break; |
6408 | case 0x5: /* saturating add/subtract */ | |
6409 | rd = (insn >> 12) & 0xf; | |
6410 | rn = (insn >> 16) & 0xf; | |
b40d0353 | 6411 | tmp = load_reg(s, rm); |
5e3f878a | 6412 | tmp2 = load_reg(s, rn); |
9ee6e8bb | 6413 | if (op1 & 2) |
5e3f878a | 6414 | gen_helper_double_saturate(tmp2, tmp2); |
9ee6e8bb | 6415 | if (op1 & 1) |
5e3f878a | 6416 | gen_helper_sub_saturate(tmp, tmp, tmp2); |
9ee6e8bb | 6417 | else |
5e3f878a PB |
6418 | gen_helper_add_saturate(tmp, tmp, tmp2); |
6419 | dead_tmp(tmp2); | |
6420 | store_reg(s, rd, tmp); | |
9ee6e8bb | 6421 | break; |
49e14940 AL |
6422 | case 7: |
6423 | /* SMC instruction (op1 == 3) | |
6424 | and undefined instructions (op1 == 0 || op1 == 2) | |
6425 | will trap */ | |
6426 | if (op1 != 1) { | |
6427 | goto illegal_op; | |
6428 | } | |
6429 | /* bkpt */ | |
bc4a0de0 | 6430 | gen_exception_insn(s, 4, EXCP_BKPT); |
9ee6e8bb PB |
6431 | break; |
6432 | case 0x8: /* signed multiply */ | |
6433 | case 0xa: | |
6434 | case 0xc: | |
6435 | case 0xe: | |
6436 | rs = (insn >> 8) & 0xf; | |
6437 | rn = (insn >> 12) & 0xf; | |
6438 | rd = (insn >> 16) & 0xf; | |
6439 | if (op1 == 1) { | |
6440 | /* (32 * 16) >> 16 */ | |
5e3f878a PB |
6441 | tmp = load_reg(s, rm); |
6442 | tmp2 = load_reg(s, rs); | |
9ee6e8bb | 6443 | if (sh & 4) |
5e3f878a | 6444 | tcg_gen_sari_i32(tmp2, tmp2, 16); |
9ee6e8bb | 6445 | else |
5e3f878a | 6446 | gen_sxth(tmp2); |
a7812ae4 PB |
6447 | tmp64 = gen_muls_i64_i32(tmp, tmp2); |
6448 | tcg_gen_shri_i64(tmp64, tmp64, 16); | |
5e3f878a | 6449 | tmp = new_tmp(); |
a7812ae4 | 6450 | tcg_gen_trunc_i64_i32(tmp, tmp64); |
b75263d6 | 6451 | tcg_temp_free_i64(tmp64); |
9ee6e8bb | 6452 | if ((sh & 2) == 0) { |
5e3f878a PB |
6453 | tmp2 = load_reg(s, rn); |
6454 | gen_helper_add_setq(tmp, tmp, tmp2); | |
6455 | dead_tmp(tmp2); | |
9ee6e8bb | 6456 | } |
5e3f878a | 6457 | store_reg(s, rd, tmp); |
9ee6e8bb PB |
6458 | } else { |
6459 | /* 16 * 16 */ | |
5e3f878a PB |
6460 | tmp = load_reg(s, rm); |
6461 | tmp2 = load_reg(s, rs); | |
6462 | gen_mulxy(tmp, tmp2, sh & 2, sh & 4); | |
6463 | dead_tmp(tmp2); | |
9ee6e8bb | 6464 | if (op1 == 2) { |
a7812ae4 PB |
6465 | tmp64 = tcg_temp_new_i64(); |
6466 | tcg_gen_ext_i32_i64(tmp64, tmp); | |
22478e79 | 6467 | dead_tmp(tmp); |
a7812ae4 PB |
6468 | gen_addq(s, tmp64, rn, rd); |
6469 | gen_storeq_reg(s, rn, rd, tmp64); | |
b75263d6 | 6470 | tcg_temp_free_i64(tmp64); |
9ee6e8bb PB |
6471 | } else { |
6472 | if (op1 == 0) { | |
5e3f878a PB |
6473 | tmp2 = load_reg(s, rn); |
6474 | gen_helper_add_setq(tmp, tmp, tmp2); | |
6475 | dead_tmp(tmp2); | |
9ee6e8bb | 6476 | } |
5e3f878a | 6477 | store_reg(s, rd, tmp); |
9ee6e8bb PB |
6478 | } |
6479 | } | |
6480 | break; | |
6481 | default: | |
6482 | goto illegal_op; | |
6483 | } | |
6484 | } else if (((insn & 0x0e000000) == 0 && | |
6485 | (insn & 0x00000090) != 0x90) || | |
6486 | ((insn & 0x0e000000) == (1 << 25))) { | |
6487 | int set_cc, logic_cc, shiftop; | |
6488 | ||
6489 | op1 = (insn >> 21) & 0xf; | |
6490 | set_cc = (insn >> 20) & 1; | |
6491 | logic_cc = table_logic_cc[op1] & set_cc; | |
6492 | ||
6493 | /* data processing instruction */ | |
6494 | if (insn & (1 << 25)) { | |
6495 | /* immediate operand */ | |
6496 | val = insn & 0xff; | |
6497 | shift = ((insn >> 8) & 0xf) * 2; | |
e9bb4aa9 | 6498 | if (shift) { |
9ee6e8bb | 6499 | val = (val >> shift) | (val << (32 - shift)); |
e9bb4aa9 JR |
6500 | } |
6501 | tmp2 = new_tmp(); | |
6502 | tcg_gen_movi_i32(tmp2, val); | |
6503 | if (logic_cc && shift) { | |
6504 | gen_set_CF_bit31(tmp2); | |
6505 | } | |
9ee6e8bb PB |
6506 | } else { |
6507 | /* register */ | |
6508 | rm = (insn) & 0xf; | |
e9bb4aa9 | 6509 | tmp2 = load_reg(s, rm); |
9ee6e8bb PB |
6510 | shiftop = (insn >> 5) & 3; |
6511 | if (!(insn & (1 << 4))) { | |
6512 | shift = (insn >> 7) & 0x1f; | |
e9bb4aa9 | 6513 | gen_arm_shift_im(tmp2, shiftop, shift, logic_cc); |
9ee6e8bb PB |
6514 | } else { |
6515 | rs = (insn >> 8) & 0xf; | |
8984bd2e | 6516 | tmp = load_reg(s, rs); |
e9bb4aa9 | 6517 | gen_arm_shift_reg(tmp2, shiftop, tmp, logic_cc); |
9ee6e8bb PB |
6518 | } |
6519 | } | |
6520 | if (op1 != 0x0f && op1 != 0x0d) { | |
6521 | rn = (insn >> 16) & 0xf; | |
e9bb4aa9 JR |
6522 | tmp = load_reg(s, rn); |
6523 | } else { | |
6524 | TCGV_UNUSED(tmp); | |
9ee6e8bb PB |
6525 | } |
6526 | rd = (insn >> 12) & 0xf; | |
6527 | switch(op1) { | |
6528 | case 0x00: | |
e9bb4aa9 JR |
6529 | tcg_gen_and_i32(tmp, tmp, tmp2); |
6530 | if (logic_cc) { | |
6531 | gen_logic_CC(tmp); | |
6532 | } | |
21aeb343 | 6533 | store_reg_bx(env, s, rd, tmp); |
9ee6e8bb PB |
6534 | break; |
6535 | case 0x01: | |
e9bb4aa9 JR |
6536 | tcg_gen_xor_i32(tmp, tmp, tmp2); |
6537 | if (logic_cc) { | |
6538 | gen_logic_CC(tmp); | |
6539 | } | |
21aeb343 | 6540 | store_reg_bx(env, s, rd, tmp); |
9ee6e8bb PB |
6541 | break; |
6542 | case 0x02: | |
6543 | if (set_cc && rd == 15) { | |
6544 | /* SUBS r15, ... is used for exception return. */ | |
e9bb4aa9 | 6545 | if (IS_USER(s)) { |
9ee6e8bb | 6546 | goto illegal_op; |
e9bb4aa9 JR |
6547 | } |
6548 | gen_helper_sub_cc(tmp, tmp, tmp2); | |
6549 | gen_exception_return(s, tmp); | |
9ee6e8bb | 6550 | } else { |
e9bb4aa9 JR |
6551 | if (set_cc) { |
6552 | gen_helper_sub_cc(tmp, tmp, tmp2); | |
6553 | } else { | |
6554 | tcg_gen_sub_i32(tmp, tmp, tmp2); | |
6555 | } | |
21aeb343 | 6556 | store_reg_bx(env, s, rd, tmp); |
9ee6e8bb PB |
6557 | } |
6558 | break; | |
6559 | case 0x03: | |
e9bb4aa9 JR |
6560 | if (set_cc) { |
6561 | gen_helper_sub_cc(tmp, tmp2, tmp); | |
6562 | } else { | |
6563 | tcg_gen_sub_i32(tmp, tmp2, tmp); | |
6564 | } | |
21aeb343 | 6565 | store_reg_bx(env, s, rd, tmp); |
9ee6e8bb PB |
6566 | break; |
6567 | case 0x04: | |
e9bb4aa9 JR |
6568 | if (set_cc) { |
6569 | gen_helper_add_cc(tmp, tmp, tmp2); | |
6570 | } else { | |
6571 | tcg_gen_add_i32(tmp, tmp, tmp2); | |
6572 | } | |
21aeb343 | 6573 | store_reg_bx(env, s, rd, tmp); |
9ee6e8bb PB |
6574 | break; |
6575 | case 0x05: | |
e9bb4aa9 JR |
6576 | if (set_cc) { |
6577 | gen_helper_adc_cc(tmp, tmp, tmp2); | |
6578 | } else { | |
6579 | gen_add_carry(tmp, tmp, tmp2); | |
6580 | } | |
21aeb343 | 6581 | store_reg_bx(env, s, rd, tmp); |
9ee6e8bb PB |
6582 | break; |
6583 | case 0x06: | |
e9bb4aa9 JR |
6584 | if (set_cc) { |
6585 | gen_helper_sbc_cc(tmp, tmp, tmp2); | |
6586 | } else { | |
6587 | gen_sub_carry(tmp, tmp, tmp2); | |
6588 | } | |
21aeb343 | 6589 | store_reg_bx(env, s, rd, tmp); |
9ee6e8bb PB |
6590 | break; |
6591 | case 0x07: | |
e9bb4aa9 JR |
6592 | if (set_cc) { |
6593 | gen_helper_sbc_cc(tmp, tmp2, tmp); | |
6594 | } else { | |
6595 | gen_sub_carry(tmp, tmp2, tmp); | |
6596 | } | |
21aeb343 | 6597 | store_reg_bx(env, s, rd, tmp); |
9ee6e8bb PB |
6598 | break; |
6599 | case 0x08: | |
6600 | if (set_cc) { | |
e9bb4aa9 JR |
6601 | tcg_gen_and_i32(tmp, tmp, tmp2); |
6602 | gen_logic_CC(tmp); | |
9ee6e8bb | 6603 | } |
e9bb4aa9 | 6604 | dead_tmp(tmp); |
9ee6e8bb PB |
6605 | break; |
6606 | case 0x09: | |
6607 | if (set_cc) { | |
e9bb4aa9 JR |
6608 | tcg_gen_xor_i32(tmp, tmp, tmp2); |
6609 | gen_logic_CC(tmp); | |
9ee6e8bb | 6610 | } |
e9bb4aa9 | 6611 | dead_tmp(tmp); |
9ee6e8bb PB |
6612 | break; |
6613 | case 0x0a: | |
6614 | if (set_cc) { | |
e9bb4aa9 | 6615 | gen_helper_sub_cc(tmp, tmp, tmp2); |
9ee6e8bb | 6616 | } |
e9bb4aa9 | 6617 | dead_tmp(tmp); |
9ee6e8bb PB |
6618 | break; |
6619 | case 0x0b: | |
6620 | if (set_cc) { | |
e9bb4aa9 | 6621 | gen_helper_add_cc(tmp, tmp, tmp2); |
9ee6e8bb | 6622 | } |
e9bb4aa9 | 6623 | dead_tmp(tmp); |
9ee6e8bb PB |
6624 | break; |
6625 | case 0x0c: | |
e9bb4aa9 JR |
6626 | tcg_gen_or_i32(tmp, tmp, tmp2); |
6627 | if (logic_cc) { | |
6628 | gen_logic_CC(tmp); | |
6629 | } | |
21aeb343 | 6630 | store_reg_bx(env, s, rd, tmp); |
9ee6e8bb PB |
6631 | break; |
6632 | case 0x0d: | |
6633 | if (logic_cc && rd == 15) { | |
6634 | /* MOVS r15, ... is used for exception return. */ | |
e9bb4aa9 | 6635 | if (IS_USER(s)) { |
9ee6e8bb | 6636 | goto illegal_op; |
e9bb4aa9 JR |
6637 | } |
6638 | gen_exception_return(s, tmp2); | |
9ee6e8bb | 6639 | } else { |
e9bb4aa9 JR |
6640 | if (logic_cc) { |
6641 | gen_logic_CC(tmp2); | |
6642 | } | |
21aeb343 | 6643 | store_reg_bx(env, s, rd, tmp2); |
9ee6e8bb PB |
6644 | } |
6645 | break; | |
6646 | case 0x0e: | |
f669df27 | 6647 | tcg_gen_andc_i32(tmp, tmp, tmp2); |
e9bb4aa9 JR |
6648 | if (logic_cc) { |
6649 | gen_logic_CC(tmp); | |
6650 | } | |
21aeb343 | 6651 | store_reg_bx(env, s, rd, tmp); |
9ee6e8bb PB |
6652 | break; |
6653 | default: | |
6654 | case 0x0f: | |
e9bb4aa9 JR |
6655 | tcg_gen_not_i32(tmp2, tmp2); |
6656 | if (logic_cc) { | |
6657 | gen_logic_CC(tmp2); | |
6658 | } | |
21aeb343 | 6659 | store_reg_bx(env, s, rd, tmp2); |
9ee6e8bb PB |
6660 | break; |
6661 | } | |
e9bb4aa9 JR |
6662 | if (op1 != 0x0f && op1 != 0x0d) { |
6663 | dead_tmp(tmp2); | |
6664 | } | |
9ee6e8bb PB |
6665 | } else { |
6666 | /* other instructions */ | |
6667 | op1 = (insn >> 24) & 0xf; | |
6668 | switch(op1) { | |
6669 | case 0x0: | |
6670 | case 0x1: | |
6671 | /* multiplies, extra load/stores */ | |
6672 | sh = (insn >> 5) & 3; | |
6673 | if (sh == 0) { | |
6674 | if (op1 == 0x0) { | |
6675 | rd = (insn >> 16) & 0xf; | |
6676 | rn = (insn >> 12) & 0xf; | |
6677 | rs = (insn >> 8) & 0xf; | |
6678 | rm = (insn) & 0xf; | |
6679 | op1 = (insn >> 20) & 0xf; | |
6680 | switch (op1) { | |
6681 | case 0: case 1: case 2: case 3: case 6: | |
6682 | /* 32 bit mul */ | |
5e3f878a PB |
6683 | tmp = load_reg(s, rs); |
6684 | tmp2 = load_reg(s, rm); | |
6685 | tcg_gen_mul_i32(tmp, tmp, tmp2); | |
6686 | dead_tmp(tmp2); | |
9ee6e8bb PB |
6687 | if (insn & (1 << 22)) { |
6688 | /* Subtract (mls) */ | |
6689 | ARCH(6T2); | |
5e3f878a PB |
6690 | tmp2 = load_reg(s, rn); |
6691 | tcg_gen_sub_i32(tmp, tmp2, tmp); | |
6692 | dead_tmp(tmp2); | |
9ee6e8bb PB |
6693 | } else if (insn & (1 << 21)) { |
6694 | /* Add */ | |
5e3f878a PB |
6695 | tmp2 = load_reg(s, rn); |
6696 | tcg_gen_add_i32(tmp, tmp, tmp2); | |
6697 | dead_tmp(tmp2); | |
9ee6e8bb PB |
6698 | } |
6699 | if (insn & (1 << 20)) | |
5e3f878a PB |
6700 | gen_logic_CC(tmp); |
6701 | store_reg(s, rd, tmp); | |
9ee6e8bb | 6702 | break; |
8aac08b1 AJ |
6703 | case 4: |
6704 | /* 64 bit mul double accumulate (UMAAL) */ | |
6705 | ARCH(6); | |
6706 | tmp = load_reg(s, rs); | |
6707 | tmp2 = load_reg(s, rm); | |
6708 | tmp64 = gen_mulu_i64_i32(tmp, tmp2); | |
6709 | gen_addq_lo(s, tmp64, rn); | |
6710 | gen_addq_lo(s, tmp64, rd); | |
6711 | gen_storeq_reg(s, rn, rd, tmp64); | |
6712 | tcg_temp_free_i64(tmp64); | |
6713 | break; | |
6714 | case 8: case 9: case 10: case 11: | |
6715 | case 12: case 13: case 14: case 15: | |
6716 | /* 64 bit mul: UMULL, UMLAL, SMULL, SMLAL. */ | |
5e3f878a PB |
6717 | tmp = load_reg(s, rs); |
6718 | tmp2 = load_reg(s, rm); | |
8aac08b1 | 6719 | if (insn & (1 << 22)) { |
a7812ae4 | 6720 | tmp64 = gen_muls_i64_i32(tmp, tmp2); |
8aac08b1 | 6721 | } else { |
a7812ae4 | 6722 | tmp64 = gen_mulu_i64_i32(tmp, tmp2); |
8aac08b1 AJ |
6723 | } |
6724 | if (insn & (1 << 21)) { /* mult accumulate */ | |
a7812ae4 | 6725 | gen_addq(s, tmp64, rn, rd); |
9ee6e8bb | 6726 | } |
8aac08b1 | 6727 | if (insn & (1 << 20)) { |
a7812ae4 | 6728 | gen_logicq_cc(tmp64); |
8aac08b1 | 6729 | } |
a7812ae4 | 6730 | gen_storeq_reg(s, rn, rd, tmp64); |
b75263d6 | 6731 | tcg_temp_free_i64(tmp64); |
9ee6e8bb | 6732 | break; |
8aac08b1 AJ |
6733 | default: |
6734 | goto illegal_op; | |
9ee6e8bb PB |
6735 | } |
6736 | } else { | |
6737 | rn = (insn >> 16) & 0xf; | |
6738 | rd = (insn >> 12) & 0xf; | |
6739 | if (insn & (1 << 23)) { | |
6740 | /* load/store exclusive */ | |
86753403 PB |
6741 | op1 = (insn >> 21) & 0x3; |
6742 | if (op1) | |
a47f43d2 | 6743 | ARCH(6K); |
86753403 PB |
6744 | else |
6745 | ARCH(6); | |
3174f8e9 | 6746 | addr = tcg_temp_local_new_i32(); |
98a46317 | 6747 | load_reg_var(s, addr, rn); |
9ee6e8bb | 6748 | if (insn & (1 << 20)) { |
86753403 PB |
6749 | switch (op1) { |
6750 | case 0: /* ldrex */ | |
426f5abc | 6751 | gen_load_exclusive(s, rd, 15, addr, 2); |
86753403 PB |
6752 | break; |
6753 | case 1: /* ldrexd */ | |
426f5abc | 6754 | gen_load_exclusive(s, rd, rd + 1, addr, 3); |
86753403 PB |
6755 | break; |
6756 | case 2: /* ldrexb */ | |
426f5abc | 6757 | gen_load_exclusive(s, rd, 15, addr, 0); |
86753403 PB |
6758 | break; |
6759 | case 3: /* ldrexh */ | |
426f5abc | 6760 | gen_load_exclusive(s, rd, 15, addr, 1); |
86753403 PB |
6761 | break; |
6762 | default: | |
6763 | abort(); | |
6764 | } | |
9ee6e8bb PB |
6765 | } else { |
6766 | rm = insn & 0xf; | |
86753403 PB |
6767 | switch (op1) { |
6768 | case 0: /* strex */ | |
426f5abc | 6769 | gen_store_exclusive(s, rd, rm, 15, addr, 2); |
86753403 PB |
6770 | break; |
6771 | case 1: /* strexd */ | |
502e64fe | 6772 | gen_store_exclusive(s, rd, rm, rm + 1, addr, 3); |
86753403 PB |
6773 | break; |
6774 | case 2: /* strexb */ | |
426f5abc | 6775 | gen_store_exclusive(s, rd, rm, 15, addr, 0); |
86753403 PB |
6776 | break; |
6777 | case 3: /* strexh */ | |
426f5abc | 6778 | gen_store_exclusive(s, rd, rm, 15, addr, 1); |
86753403 PB |
6779 | break; |
6780 | default: | |
6781 | abort(); | |
6782 | } | |
9ee6e8bb | 6783 | } |
3174f8e9 | 6784 | tcg_temp_free(addr); |
9ee6e8bb PB |
6785 | } else { |
6786 | /* SWP instruction */ | |
6787 | rm = (insn) & 0xf; | |
6788 | ||
8984bd2e PB |
6789 | /* ??? This is not really atomic. However we know |
6790 | we never have multiple CPUs running in parallel, | |
6791 | so it is good enough. */ | |
6792 | addr = load_reg(s, rn); | |
6793 | tmp = load_reg(s, rm); | |
9ee6e8bb | 6794 | if (insn & (1 << 22)) { |
8984bd2e PB |
6795 | tmp2 = gen_ld8u(addr, IS_USER(s)); |
6796 | gen_st8(tmp, addr, IS_USER(s)); | |
9ee6e8bb | 6797 | } else { |
8984bd2e PB |
6798 | tmp2 = gen_ld32(addr, IS_USER(s)); |
6799 | gen_st32(tmp, addr, IS_USER(s)); | |
9ee6e8bb | 6800 | } |
8984bd2e PB |
6801 | dead_tmp(addr); |
6802 | store_reg(s, rd, tmp2); | |
9ee6e8bb PB |
6803 | } |
6804 | } | |
6805 | } else { | |
6806 | int address_offset; | |
6807 | int load; | |
6808 | /* Misc load/store */ | |
6809 | rn = (insn >> 16) & 0xf; | |
6810 | rd = (insn >> 12) & 0xf; | |
b0109805 | 6811 | addr = load_reg(s, rn); |
9ee6e8bb | 6812 | if (insn & (1 << 24)) |
b0109805 | 6813 | gen_add_datah_offset(s, insn, 0, addr); |
9ee6e8bb PB |
6814 | address_offset = 0; |
6815 | if (insn & (1 << 20)) { | |
6816 | /* load */ | |
6817 | switch(sh) { | |
6818 | case 1: | |
b0109805 | 6819 | tmp = gen_ld16u(addr, IS_USER(s)); |
9ee6e8bb PB |
6820 | break; |
6821 | case 2: | |
b0109805 | 6822 | tmp = gen_ld8s(addr, IS_USER(s)); |
9ee6e8bb PB |
6823 | break; |
6824 | default: | |
6825 | case 3: | |
b0109805 | 6826 | tmp = gen_ld16s(addr, IS_USER(s)); |
9ee6e8bb PB |
6827 | break; |
6828 | } | |
6829 | load = 1; | |
6830 | } else if (sh & 2) { | |
6831 | /* doubleword */ | |
6832 | if (sh & 1) { | |
6833 | /* store */ | |
b0109805 PB |
6834 | tmp = load_reg(s, rd); |
6835 | gen_st32(tmp, addr, IS_USER(s)); | |
6836 | tcg_gen_addi_i32(addr, addr, 4); | |
6837 | tmp = load_reg(s, rd + 1); | |
6838 | gen_st32(tmp, addr, IS_USER(s)); | |
9ee6e8bb PB |
6839 | load = 0; |
6840 | } else { | |
6841 | /* load */ | |
b0109805 PB |
6842 | tmp = gen_ld32(addr, IS_USER(s)); |
6843 | store_reg(s, rd, tmp); | |
6844 | tcg_gen_addi_i32(addr, addr, 4); | |
6845 | tmp = gen_ld32(addr, IS_USER(s)); | |
9ee6e8bb PB |
6846 | rd++; |
6847 | load = 1; | |
6848 | } | |
6849 | address_offset = -4; | |
6850 | } else { | |
6851 | /* store */ | |
b0109805 PB |
6852 | tmp = load_reg(s, rd); |
6853 | gen_st16(tmp, addr, IS_USER(s)); | |
9ee6e8bb PB |
6854 | load = 0; |
6855 | } | |
6856 | /* Perform base writeback before the loaded value to | |
6857 | ensure correct behavior with overlapping index registers. | |
6858 | ldrd with base writeback is is undefined if the | |
6859 | destination and index registers overlap. */ | |
6860 | if (!(insn & (1 << 24))) { | |
b0109805 PB |
6861 | gen_add_datah_offset(s, insn, address_offset, addr); |
6862 | store_reg(s, rn, addr); | |
9ee6e8bb PB |
6863 | } else if (insn & (1 << 21)) { |
6864 | if (address_offset) | |
b0109805 PB |
6865 | tcg_gen_addi_i32(addr, addr, address_offset); |
6866 | store_reg(s, rn, addr); | |
6867 | } else { | |
6868 | dead_tmp(addr); | |
9ee6e8bb PB |
6869 | } |
6870 | if (load) { | |
6871 | /* Complete the load. */ | |
b0109805 | 6872 | store_reg(s, rd, tmp); |
9ee6e8bb PB |
6873 | } |
6874 | } | |
6875 | break; | |
6876 | case 0x4: | |
6877 | case 0x5: | |
6878 | goto do_ldst; | |
6879 | case 0x6: | |
6880 | case 0x7: | |
6881 | if (insn & (1 << 4)) { | |
6882 | ARCH(6); | |
6883 | /* Armv6 Media instructions. */ | |
6884 | rm = insn & 0xf; | |
6885 | rn = (insn >> 16) & 0xf; | |
2c0262af | 6886 | rd = (insn >> 12) & 0xf; |
9ee6e8bb PB |
6887 | rs = (insn >> 8) & 0xf; |
6888 | switch ((insn >> 23) & 3) { | |
6889 | case 0: /* Parallel add/subtract. */ | |
6890 | op1 = (insn >> 20) & 7; | |
6ddbc6e4 PB |
6891 | tmp = load_reg(s, rn); |
6892 | tmp2 = load_reg(s, rm); | |
9ee6e8bb PB |
6893 | sh = (insn >> 5) & 7; |
6894 | if ((op1 & 3) == 0 || sh == 5 || sh == 6) | |
6895 | goto illegal_op; | |
6ddbc6e4 PB |
6896 | gen_arm_parallel_addsub(op1, sh, tmp, tmp2); |
6897 | dead_tmp(tmp2); | |
6898 | store_reg(s, rd, tmp); | |
9ee6e8bb PB |
6899 | break; |
6900 | case 1: | |
6901 | if ((insn & 0x00700020) == 0) { | |
6c95676b | 6902 | /* Halfword pack. */ |
3670669c PB |
6903 | tmp = load_reg(s, rn); |
6904 | tmp2 = load_reg(s, rm); | |
9ee6e8bb | 6905 | shift = (insn >> 7) & 0x1f; |
3670669c PB |
6906 | if (insn & (1 << 6)) { |
6907 | /* pkhtb */ | |
22478e79 AZ |
6908 | if (shift == 0) |
6909 | shift = 31; | |
6910 | tcg_gen_sari_i32(tmp2, tmp2, shift); | |
3670669c | 6911 | tcg_gen_andi_i32(tmp, tmp, 0xffff0000); |
86831435 | 6912 | tcg_gen_ext16u_i32(tmp2, tmp2); |
3670669c PB |
6913 | } else { |
6914 | /* pkhbt */ | |
22478e79 AZ |
6915 | if (shift) |
6916 | tcg_gen_shli_i32(tmp2, tmp2, shift); | |
86831435 | 6917 | tcg_gen_ext16u_i32(tmp, tmp); |
3670669c PB |
6918 | tcg_gen_andi_i32(tmp2, tmp2, 0xffff0000); |
6919 | } | |
6920 | tcg_gen_or_i32(tmp, tmp, tmp2); | |
22478e79 | 6921 | dead_tmp(tmp2); |
3670669c | 6922 | store_reg(s, rd, tmp); |
9ee6e8bb PB |
6923 | } else if ((insn & 0x00200020) == 0x00200000) { |
6924 | /* [us]sat */ | |
6ddbc6e4 | 6925 | tmp = load_reg(s, rm); |
9ee6e8bb PB |
6926 | shift = (insn >> 7) & 0x1f; |
6927 | if (insn & (1 << 6)) { | |
6928 | if (shift == 0) | |
6929 | shift = 31; | |
6ddbc6e4 | 6930 | tcg_gen_sari_i32(tmp, tmp, shift); |
9ee6e8bb | 6931 | } else { |
6ddbc6e4 | 6932 | tcg_gen_shli_i32(tmp, tmp, shift); |
9ee6e8bb PB |
6933 | } |
6934 | sh = (insn >> 16) & 0x1f; | |
40d3c433 CL |
6935 | tmp2 = tcg_const_i32(sh); |
6936 | if (insn & (1 << 22)) | |
6937 | gen_helper_usat(tmp, tmp, tmp2); | |
6938 | else | |
6939 | gen_helper_ssat(tmp, tmp, tmp2); | |
6940 | tcg_temp_free_i32(tmp2); | |
6ddbc6e4 | 6941 | store_reg(s, rd, tmp); |
9ee6e8bb PB |
6942 | } else if ((insn & 0x00300fe0) == 0x00200f20) { |
6943 | /* [us]sat16 */ | |
6ddbc6e4 | 6944 | tmp = load_reg(s, rm); |
9ee6e8bb | 6945 | sh = (insn >> 16) & 0x1f; |
40d3c433 CL |
6946 | tmp2 = tcg_const_i32(sh); |
6947 | if (insn & (1 << 22)) | |
6948 | gen_helper_usat16(tmp, tmp, tmp2); | |
6949 | else | |
6950 | gen_helper_ssat16(tmp, tmp, tmp2); | |
6951 | tcg_temp_free_i32(tmp2); | |
6ddbc6e4 | 6952 | store_reg(s, rd, tmp); |
9ee6e8bb PB |
6953 | } else if ((insn & 0x00700fe0) == 0x00000fa0) { |
6954 | /* Select bytes. */ | |
6ddbc6e4 PB |
6955 | tmp = load_reg(s, rn); |
6956 | tmp2 = load_reg(s, rm); | |
6957 | tmp3 = new_tmp(); | |
6958 | tcg_gen_ld_i32(tmp3, cpu_env, offsetof(CPUState, GE)); | |
6959 | gen_helper_sel_flags(tmp, tmp3, tmp, tmp2); | |
6960 | dead_tmp(tmp3); | |
6961 | dead_tmp(tmp2); | |
6962 | store_reg(s, rd, tmp); | |
9ee6e8bb | 6963 | } else if ((insn & 0x000003e0) == 0x00000060) { |
5e3f878a | 6964 | tmp = load_reg(s, rm); |
9ee6e8bb PB |
6965 | shift = (insn >> 10) & 3; |
6966 | /* ??? In many cases it's not neccessary to do a | |
6967 | rotate, a shift is sufficient. */ | |
6968 | if (shift != 0) | |
f669df27 | 6969 | tcg_gen_rotri_i32(tmp, tmp, shift * 8); |
9ee6e8bb PB |
6970 | op1 = (insn >> 20) & 7; |
6971 | switch (op1) { | |
5e3f878a PB |
6972 | case 0: gen_sxtb16(tmp); break; |
6973 | case 2: gen_sxtb(tmp); break; | |
6974 | case 3: gen_sxth(tmp); break; | |
6975 | case 4: gen_uxtb16(tmp); break; | |
6976 | case 6: gen_uxtb(tmp); break; | |
6977 | case 7: gen_uxth(tmp); break; | |
9ee6e8bb PB |
6978 | default: goto illegal_op; |
6979 | } | |
6980 | if (rn != 15) { | |
5e3f878a | 6981 | tmp2 = load_reg(s, rn); |
9ee6e8bb | 6982 | if ((op1 & 3) == 0) { |
5e3f878a | 6983 | gen_add16(tmp, tmp2); |
9ee6e8bb | 6984 | } else { |
5e3f878a PB |
6985 | tcg_gen_add_i32(tmp, tmp, tmp2); |
6986 | dead_tmp(tmp2); | |
9ee6e8bb PB |
6987 | } |
6988 | } | |
6c95676b | 6989 | store_reg(s, rd, tmp); |
9ee6e8bb PB |
6990 | } else if ((insn & 0x003f0f60) == 0x003f0f20) { |
6991 | /* rev */ | |
b0109805 | 6992 | tmp = load_reg(s, rm); |
9ee6e8bb PB |
6993 | if (insn & (1 << 22)) { |
6994 | if (insn & (1 << 7)) { | |
b0109805 | 6995 | gen_revsh(tmp); |
9ee6e8bb PB |
6996 | } else { |
6997 | ARCH(6T2); | |
b0109805 | 6998 | gen_helper_rbit(tmp, tmp); |
9ee6e8bb PB |
6999 | } |
7000 | } else { | |
7001 | if (insn & (1 << 7)) | |
b0109805 | 7002 | gen_rev16(tmp); |
9ee6e8bb | 7003 | else |
66896cb8 | 7004 | tcg_gen_bswap32_i32(tmp, tmp); |
9ee6e8bb | 7005 | } |
b0109805 | 7006 | store_reg(s, rd, tmp); |
9ee6e8bb PB |
7007 | } else { |
7008 | goto illegal_op; | |
7009 | } | |
7010 | break; | |
7011 | case 2: /* Multiplies (Type 3). */ | |
5e3f878a PB |
7012 | tmp = load_reg(s, rm); |
7013 | tmp2 = load_reg(s, rs); | |
9ee6e8bb | 7014 | if (insn & (1 << 20)) { |
838fa72d AJ |
7015 | /* Signed multiply most significant [accumulate]. |
7016 | (SMMUL, SMMLA, SMMLS) */ | |
a7812ae4 | 7017 | tmp64 = gen_muls_i64_i32(tmp, tmp2); |
838fa72d | 7018 | |
955a7dd5 | 7019 | if (rd != 15) { |
838fa72d | 7020 | tmp = load_reg(s, rd); |
9ee6e8bb | 7021 | if (insn & (1 << 6)) { |
838fa72d | 7022 | tmp64 = gen_subq_msw(tmp64, tmp); |
9ee6e8bb | 7023 | } else { |
838fa72d | 7024 | tmp64 = gen_addq_msw(tmp64, tmp); |
9ee6e8bb PB |
7025 | } |
7026 | } | |
838fa72d AJ |
7027 | if (insn & (1 << 5)) { |
7028 | tcg_gen_addi_i64(tmp64, tmp64, 0x80000000u); | |
7029 | } | |
7030 | tcg_gen_shri_i64(tmp64, tmp64, 32); | |
7031 | tmp = new_tmp(); | |
7032 | tcg_gen_trunc_i64_i32(tmp, tmp64); | |
7033 | tcg_temp_free_i64(tmp64); | |
955a7dd5 | 7034 | store_reg(s, rn, tmp); |
9ee6e8bb PB |
7035 | } else { |
7036 | if (insn & (1 << 5)) | |
5e3f878a PB |
7037 | gen_swap_half(tmp2); |
7038 | gen_smul_dual(tmp, tmp2); | |
7039 | /* This addition cannot overflow. */ | |
7040 | if (insn & (1 << 6)) { | |
7041 | tcg_gen_sub_i32(tmp, tmp, tmp2); | |
7042 | } else { | |
7043 | tcg_gen_add_i32(tmp, tmp, tmp2); | |
7044 | } | |
7045 | dead_tmp(tmp2); | |
9ee6e8bb | 7046 | if (insn & (1 << 22)) { |
5e3f878a | 7047 | /* smlald, smlsld */ |
a7812ae4 PB |
7048 | tmp64 = tcg_temp_new_i64(); |
7049 | tcg_gen_ext_i32_i64(tmp64, tmp); | |
5e3f878a | 7050 | dead_tmp(tmp); |
a7812ae4 PB |
7051 | gen_addq(s, tmp64, rd, rn); |
7052 | gen_storeq_reg(s, rd, rn, tmp64); | |
b75263d6 | 7053 | tcg_temp_free_i64(tmp64); |
9ee6e8bb | 7054 | } else { |
5e3f878a | 7055 | /* smuad, smusd, smlad, smlsd */ |
22478e79 | 7056 | if (rd != 15) |
9ee6e8bb | 7057 | { |
22478e79 | 7058 | tmp2 = load_reg(s, rd); |
5e3f878a PB |
7059 | gen_helper_add_setq(tmp, tmp, tmp2); |
7060 | dead_tmp(tmp2); | |
9ee6e8bb | 7061 | } |
22478e79 | 7062 | store_reg(s, rn, tmp); |
9ee6e8bb PB |
7063 | } |
7064 | } | |
7065 | break; | |
7066 | case 3: | |
7067 | op1 = ((insn >> 17) & 0x38) | ((insn >> 5) & 7); | |
7068 | switch (op1) { | |
7069 | case 0: /* Unsigned sum of absolute differences. */ | |
6ddbc6e4 PB |
7070 | ARCH(6); |
7071 | tmp = load_reg(s, rm); | |
7072 | tmp2 = load_reg(s, rs); | |
7073 | gen_helper_usad8(tmp, tmp, tmp2); | |
7074 | dead_tmp(tmp2); | |
ded9d295 AZ |
7075 | if (rd != 15) { |
7076 | tmp2 = load_reg(s, rd); | |
6ddbc6e4 PB |
7077 | tcg_gen_add_i32(tmp, tmp, tmp2); |
7078 | dead_tmp(tmp2); | |
9ee6e8bb | 7079 | } |
ded9d295 | 7080 | store_reg(s, rn, tmp); |
9ee6e8bb PB |
7081 | break; |
7082 | case 0x20: case 0x24: case 0x28: case 0x2c: | |
7083 | /* Bitfield insert/clear. */ | |
7084 | ARCH(6T2); | |
7085 | shift = (insn >> 7) & 0x1f; | |
7086 | i = (insn >> 16) & 0x1f; | |
7087 | i = i + 1 - shift; | |
7088 | if (rm == 15) { | |
5e3f878a PB |
7089 | tmp = new_tmp(); |
7090 | tcg_gen_movi_i32(tmp, 0); | |
9ee6e8bb | 7091 | } else { |
5e3f878a | 7092 | tmp = load_reg(s, rm); |
9ee6e8bb PB |
7093 | } |
7094 | if (i != 32) { | |
5e3f878a | 7095 | tmp2 = load_reg(s, rd); |
8f8e3aa4 | 7096 | gen_bfi(tmp, tmp2, tmp, shift, (1u << i) - 1); |
5e3f878a | 7097 | dead_tmp(tmp2); |
9ee6e8bb | 7098 | } |
5e3f878a | 7099 | store_reg(s, rd, tmp); |
9ee6e8bb PB |
7100 | break; |
7101 | case 0x12: case 0x16: case 0x1a: case 0x1e: /* sbfx */ | |
7102 | case 0x32: case 0x36: case 0x3a: case 0x3e: /* ubfx */ | |
4cc633c3 | 7103 | ARCH(6T2); |
5e3f878a | 7104 | tmp = load_reg(s, rm); |
9ee6e8bb PB |
7105 | shift = (insn >> 7) & 0x1f; |
7106 | i = ((insn >> 16) & 0x1f) + 1; | |
7107 | if (shift + i > 32) | |
7108 | goto illegal_op; | |
7109 | if (i < 32) { | |
7110 | if (op1 & 0x20) { | |
5e3f878a | 7111 | gen_ubfx(tmp, shift, (1u << i) - 1); |
9ee6e8bb | 7112 | } else { |
5e3f878a | 7113 | gen_sbfx(tmp, shift, i); |
9ee6e8bb PB |
7114 | } |
7115 | } | |
5e3f878a | 7116 | store_reg(s, rd, tmp); |
9ee6e8bb PB |
7117 | break; |
7118 | default: | |
7119 | goto illegal_op; | |
7120 | } | |
7121 | break; | |
7122 | } | |
7123 | break; | |
7124 | } | |
7125 | do_ldst: | |
7126 | /* Check for undefined extension instructions | |
7127 | * per the ARM Bible IE: | |
7128 | * xxxx 0111 1111 xxxx xxxx xxxx 1111 xxxx | |
7129 | */ | |
7130 | sh = (0xf << 20) | (0xf << 4); | |
7131 | if (op1 == 0x7 && ((insn & sh) == sh)) | |
7132 | { | |
7133 | goto illegal_op; | |
7134 | } | |
7135 | /* load/store byte/word */ | |
7136 | rn = (insn >> 16) & 0xf; | |
7137 | rd = (insn >> 12) & 0xf; | |
b0109805 | 7138 | tmp2 = load_reg(s, rn); |
9ee6e8bb PB |
7139 | i = (IS_USER(s) || (insn & 0x01200000) == 0x00200000); |
7140 | if (insn & (1 << 24)) | |
b0109805 | 7141 | gen_add_data_offset(s, insn, tmp2); |
9ee6e8bb PB |
7142 | if (insn & (1 << 20)) { |
7143 | /* load */ | |
9ee6e8bb | 7144 | if (insn & (1 << 22)) { |
b0109805 | 7145 | tmp = gen_ld8u(tmp2, i); |
9ee6e8bb | 7146 | } else { |
b0109805 | 7147 | tmp = gen_ld32(tmp2, i); |
9ee6e8bb | 7148 | } |
9ee6e8bb PB |
7149 | } else { |
7150 | /* store */ | |
b0109805 | 7151 | tmp = load_reg(s, rd); |
9ee6e8bb | 7152 | if (insn & (1 << 22)) |
b0109805 | 7153 | gen_st8(tmp, tmp2, i); |
9ee6e8bb | 7154 | else |
b0109805 | 7155 | gen_st32(tmp, tmp2, i); |
9ee6e8bb PB |
7156 | } |
7157 | if (!(insn & (1 << 24))) { | |
b0109805 PB |
7158 | gen_add_data_offset(s, insn, tmp2); |
7159 | store_reg(s, rn, tmp2); | |
7160 | } else if (insn & (1 << 21)) { | |
7161 | store_reg(s, rn, tmp2); | |
7162 | } else { | |
7163 | dead_tmp(tmp2); | |
9ee6e8bb PB |
7164 | } |
7165 | if (insn & (1 << 20)) { | |
7166 | /* Complete the load. */ | |
7167 | if (rd == 15) | |
b0109805 | 7168 | gen_bx(s, tmp); |
9ee6e8bb | 7169 | else |
b0109805 | 7170 | store_reg(s, rd, tmp); |
9ee6e8bb PB |
7171 | } |
7172 | break; | |
7173 | case 0x08: | |
7174 | case 0x09: | |
7175 | { | |
7176 | int j, n, user, loaded_base; | |
b0109805 | 7177 | TCGv loaded_var; |
9ee6e8bb PB |
7178 | /* load/store multiple words */ |
7179 | /* XXX: store correct base if write back */ | |
7180 | user = 0; | |
7181 | if (insn & (1 << 22)) { | |
7182 | if (IS_USER(s)) | |
7183 | goto illegal_op; /* only usable in supervisor mode */ | |
7184 | ||
7185 | if ((insn & (1 << 15)) == 0) | |
7186 | user = 1; | |
7187 | } | |
7188 | rn = (insn >> 16) & 0xf; | |
b0109805 | 7189 | addr = load_reg(s, rn); |
9ee6e8bb PB |
7190 | |
7191 | /* compute total size */ | |
7192 | loaded_base = 0; | |
a50f5b91 | 7193 | TCGV_UNUSED(loaded_var); |
9ee6e8bb PB |
7194 | n = 0; |
7195 | for(i=0;i<16;i++) { | |
7196 | if (insn & (1 << i)) | |
7197 | n++; | |
7198 | } | |
7199 | /* XXX: test invalid n == 0 case ? */ | |
7200 | if (insn & (1 << 23)) { | |
7201 | if (insn & (1 << 24)) { | |
7202 | /* pre increment */ | |
b0109805 | 7203 | tcg_gen_addi_i32(addr, addr, 4); |
9ee6e8bb PB |
7204 | } else { |
7205 | /* post increment */ | |
7206 | } | |
7207 | } else { | |
7208 | if (insn & (1 << 24)) { | |
7209 | /* pre decrement */ | |
b0109805 | 7210 | tcg_gen_addi_i32(addr, addr, -(n * 4)); |
9ee6e8bb PB |
7211 | } else { |
7212 | /* post decrement */ | |
7213 | if (n != 1) | |
b0109805 | 7214 | tcg_gen_addi_i32(addr, addr, -((n - 1) * 4)); |
9ee6e8bb PB |
7215 | } |
7216 | } | |
7217 | j = 0; | |
7218 | for(i=0;i<16;i++) { | |
7219 | if (insn & (1 << i)) { | |
7220 | if (insn & (1 << 20)) { | |
7221 | /* load */ | |
b0109805 | 7222 | tmp = gen_ld32(addr, IS_USER(s)); |
9ee6e8bb | 7223 | if (i == 15) { |
b0109805 | 7224 | gen_bx(s, tmp); |
9ee6e8bb | 7225 | } else if (user) { |
b75263d6 JR |
7226 | tmp2 = tcg_const_i32(i); |
7227 | gen_helper_set_user_reg(tmp2, tmp); | |
7228 | tcg_temp_free_i32(tmp2); | |
b0109805 | 7229 | dead_tmp(tmp); |
9ee6e8bb | 7230 | } else if (i == rn) { |
b0109805 | 7231 | loaded_var = tmp; |
9ee6e8bb PB |
7232 | loaded_base = 1; |
7233 | } else { | |
b0109805 | 7234 | store_reg(s, i, tmp); |
9ee6e8bb PB |
7235 | } |
7236 | } else { | |
7237 | /* store */ | |
7238 | if (i == 15) { | |
7239 | /* special case: r15 = PC + 8 */ | |
7240 | val = (long)s->pc + 4; | |
b0109805 PB |
7241 | tmp = new_tmp(); |
7242 | tcg_gen_movi_i32(tmp, val); | |
9ee6e8bb | 7243 | } else if (user) { |
b0109805 | 7244 | tmp = new_tmp(); |
b75263d6 JR |
7245 | tmp2 = tcg_const_i32(i); |
7246 | gen_helper_get_user_reg(tmp, tmp2); | |
7247 | tcg_temp_free_i32(tmp2); | |
9ee6e8bb | 7248 | } else { |
b0109805 | 7249 | tmp = load_reg(s, i); |
9ee6e8bb | 7250 | } |
b0109805 | 7251 | gen_st32(tmp, addr, IS_USER(s)); |
9ee6e8bb PB |
7252 | } |
7253 | j++; | |
7254 | /* no need to add after the last transfer */ | |
7255 | if (j != n) | |
b0109805 | 7256 | tcg_gen_addi_i32(addr, addr, 4); |
9ee6e8bb PB |
7257 | } |
7258 | } | |
7259 | if (insn & (1 << 21)) { | |
7260 | /* write back */ | |
7261 | if (insn & (1 << 23)) { | |
7262 | if (insn & (1 << 24)) { | |
7263 | /* pre increment */ | |
7264 | } else { | |
7265 | /* post increment */ | |
b0109805 | 7266 | tcg_gen_addi_i32(addr, addr, 4); |
9ee6e8bb PB |
7267 | } |
7268 | } else { | |
7269 | if (insn & (1 << 24)) { | |
7270 | /* pre decrement */ | |
7271 | if (n != 1) | |
b0109805 | 7272 | tcg_gen_addi_i32(addr, addr, -((n - 1) * 4)); |
9ee6e8bb PB |
7273 | } else { |
7274 | /* post decrement */ | |
b0109805 | 7275 | tcg_gen_addi_i32(addr, addr, -(n * 4)); |
9ee6e8bb PB |
7276 | } |
7277 | } | |
b0109805 PB |
7278 | store_reg(s, rn, addr); |
7279 | } else { | |
7280 | dead_tmp(addr); | |
9ee6e8bb PB |
7281 | } |
7282 | if (loaded_base) { | |
b0109805 | 7283 | store_reg(s, rn, loaded_var); |
9ee6e8bb PB |
7284 | } |
7285 | if ((insn & (1 << 22)) && !user) { | |
7286 | /* Restore CPSR from SPSR. */ | |
d9ba4830 PB |
7287 | tmp = load_cpu_field(spsr); |
7288 | gen_set_cpsr(tmp, 0xffffffff); | |
7289 | dead_tmp(tmp); | |
9ee6e8bb PB |
7290 | s->is_jmp = DISAS_UPDATE; |
7291 | } | |
7292 | } | |
7293 | break; | |
7294 | case 0xa: | |
7295 | case 0xb: | |
7296 | { | |
7297 | int32_t offset; | |
7298 | ||
7299 | /* branch (and link) */ | |
7300 | val = (int32_t)s->pc; | |
7301 | if (insn & (1 << 24)) { | |
5e3f878a PB |
7302 | tmp = new_tmp(); |
7303 | tcg_gen_movi_i32(tmp, val); | |
7304 | store_reg(s, 14, tmp); | |
9ee6e8bb PB |
7305 | } |
7306 | offset = (((int32_t)insn << 8) >> 8); | |
7307 | val += (offset << 2) + 4; | |
7308 | gen_jmp(s, val); | |
7309 | } | |
7310 | break; | |
7311 | case 0xc: | |
7312 | case 0xd: | |
7313 | case 0xe: | |
7314 | /* Coprocessor. */ | |
7315 | if (disas_coproc_insn(env, s, insn)) | |
7316 | goto illegal_op; | |
7317 | break; | |
7318 | case 0xf: | |
7319 | /* swi */ | |
5e3f878a | 7320 | gen_set_pc_im(s->pc); |
9ee6e8bb PB |
7321 | s->is_jmp = DISAS_SWI; |
7322 | break; | |
7323 | default: | |
7324 | illegal_op: | |
bc4a0de0 | 7325 | gen_exception_insn(s, 4, EXCP_UDEF); |
9ee6e8bb PB |
7326 | break; |
7327 | } | |
7328 | } | |
7329 | } | |
7330 | ||
7331 | /* Return true if this is a Thumb-2 logical op. */ | |
7332 | static int | |
7333 | thumb2_logic_op(int op) | |
7334 | { | |
7335 | return (op < 8); | |
7336 | } | |
7337 | ||
7338 | /* Generate code for a Thumb-2 data processing operation. If CONDS is nonzero | |
7339 | then set condition code flags based on the result of the operation. | |
7340 | If SHIFTER_OUT is nonzero then set the carry flag for logical operations | |
7341 | to the high bit of T1. | |
7342 | Returns zero if the opcode is valid. */ | |
7343 | ||
7344 | static int | |
396e467c | 7345 | gen_thumb2_data_op(DisasContext *s, int op, int conds, uint32_t shifter_out, TCGv t0, TCGv t1) |
9ee6e8bb PB |
7346 | { |
7347 | int logic_cc; | |
7348 | ||
7349 | logic_cc = 0; | |
7350 | switch (op) { | |
7351 | case 0: /* and */ | |
396e467c | 7352 | tcg_gen_and_i32(t0, t0, t1); |
9ee6e8bb PB |
7353 | logic_cc = conds; |
7354 | break; | |
7355 | case 1: /* bic */ | |
f669df27 | 7356 | tcg_gen_andc_i32(t0, t0, t1); |
9ee6e8bb PB |
7357 | logic_cc = conds; |
7358 | break; | |
7359 | case 2: /* orr */ | |
396e467c | 7360 | tcg_gen_or_i32(t0, t0, t1); |
9ee6e8bb PB |
7361 | logic_cc = conds; |
7362 | break; | |
7363 | case 3: /* orn */ | |
396e467c FN |
7364 | tcg_gen_not_i32(t1, t1); |
7365 | tcg_gen_or_i32(t0, t0, t1); | |
9ee6e8bb PB |
7366 | logic_cc = conds; |
7367 | break; | |
7368 | case 4: /* eor */ | |
396e467c | 7369 | tcg_gen_xor_i32(t0, t0, t1); |
9ee6e8bb PB |
7370 | logic_cc = conds; |
7371 | break; | |
7372 | case 8: /* add */ | |
7373 | if (conds) | |
396e467c | 7374 | gen_helper_add_cc(t0, t0, t1); |
9ee6e8bb | 7375 | else |
396e467c | 7376 | tcg_gen_add_i32(t0, t0, t1); |
9ee6e8bb PB |
7377 | break; |
7378 | case 10: /* adc */ | |
7379 | if (conds) | |
396e467c | 7380 | gen_helper_adc_cc(t0, t0, t1); |
9ee6e8bb | 7381 | else |
396e467c | 7382 | gen_adc(t0, t1); |
9ee6e8bb PB |
7383 | break; |
7384 | case 11: /* sbc */ | |
7385 | if (conds) | |
396e467c | 7386 | gen_helper_sbc_cc(t0, t0, t1); |
9ee6e8bb | 7387 | else |
396e467c | 7388 | gen_sub_carry(t0, t0, t1); |
9ee6e8bb PB |
7389 | break; |
7390 | case 13: /* sub */ | |
7391 | if (conds) | |
396e467c | 7392 | gen_helper_sub_cc(t0, t0, t1); |
9ee6e8bb | 7393 | else |
396e467c | 7394 | tcg_gen_sub_i32(t0, t0, t1); |
9ee6e8bb PB |
7395 | break; |
7396 | case 14: /* rsb */ | |
7397 | if (conds) | |
396e467c | 7398 | gen_helper_sub_cc(t0, t1, t0); |
9ee6e8bb | 7399 | else |
396e467c | 7400 | tcg_gen_sub_i32(t0, t1, t0); |
9ee6e8bb PB |
7401 | break; |
7402 | default: /* 5, 6, 7, 9, 12, 15. */ | |
7403 | return 1; | |
7404 | } | |
7405 | if (logic_cc) { | |
396e467c | 7406 | gen_logic_CC(t0); |
9ee6e8bb | 7407 | if (shifter_out) |
396e467c | 7408 | gen_set_CF_bit31(t1); |
9ee6e8bb PB |
7409 | } |
7410 | return 0; | |
7411 | } | |
7412 | ||
7413 | /* Translate a 32-bit thumb instruction. Returns nonzero if the instruction | |
7414 | is not legal. */ | |
7415 | static int disas_thumb2_insn(CPUState *env, DisasContext *s, uint16_t insn_hw1) | |
7416 | { | |
b0109805 | 7417 | uint32_t insn, imm, shift, offset; |
9ee6e8bb | 7418 | uint32_t rd, rn, rm, rs; |
b26eefb6 | 7419 | TCGv tmp; |
6ddbc6e4 PB |
7420 | TCGv tmp2; |
7421 | TCGv tmp3; | |
b0109805 | 7422 | TCGv addr; |
a7812ae4 | 7423 | TCGv_i64 tmp64; |
9ee6e8bb PB |
7424 | int op; |
7425 | int shiftop; | |
7426 | int conds; | |
7427 | int logic_cc; | |
7428 | ||
7429 | if (!(arm_feature(env, ARM_FEATURE_THUMB2) | |
7430 | || arm_feature (env, ARM_FEATURE_M))) { | |
601d70b9 | 7431 | /* Thumb-1 cores may need to treat bl and blx as a pair of |
9ee6e8bb PB |
7432 | 16-bit instructions to get correct prefetch abort behavior. */ |
7433 | insn = insn_hw1; | |
7434 | if ((insn & (1 << 12)) == 0) { | |
7435 | /* Second half of blx. */ | |
7436 | offset = ((insn & 0x7ff) << 1); | |
d9ba4830 PB |
7437 | tmp = load_reg(s, 14); |
7438 | tcg_gen_addi_i32(tmp, tmp, offset); | |
7439 | tcg_gen_andi_i32(tmp, tmp, 0xfffffffc); | |
9ee6e8bb | 7440 | |
d9ba4830 | 7441 | tmp2 = new_tmp(); |
b0109805 | 7442 | tcg_gen_movi_i32(tmp2, s->pc | 1); |
d9ba4830 PB |
7443 | store_reg(s, 14, tmp2); |
7444 | gen_bx(s, tmp); | |
9ee6e8bb PB |
7445 | return 0; |
7446 | } | |
7447 | if (insn & (1 << 11)) { | |
7448 | /* Second half of bl. */ | |
7449 | offset = ((insn & 0x7ff) << 1) | 1; | |
d9ba4830 | 7450 | tmp = load_reg(s, 14); |
6a0d8a1d | 7451 | tcg_gen_addi_i32(tmp, tmp, offset); |
9ee6e8bb | 7452 | |
d9ba4830 | 7453 | tmp2 = new_tmp(); |
b0109805 | 7454 | tcg_gen_movi_i32(tmp2, s->pc | 1); |
d9ba4830 PB |
7455 | store_reg(s, 14, tmp2); |
7456 | gen_bx(s, tmp); | |
9ee6e8bb PB |
7457 | return 0; |
7458 | } | |
7459 | if ((s->pc & ~TARGET_PAGE_MASK) == 0) { | |
7460 | /* Instruction spans a page boundary. Implement it as two | |
7461 | 16-bit instructions in case the second half causes an | |
7462 | prefetch abort. */ | |
7463 | offset = ((int32_t)insn << 21) >> 9; | |
396e467c | 7464 | tcg_gen_movi_i32(cpu_R[14], s->pc + 2 + offset); |
9ee6e8bb PB |
7465 | return 0; |
7466 | } | |
7467 | /* Fall through to 32-bit decode. */ | |
7468 | } | |
7469 | ||
7470 | insn = lduw_code(s->pc); | |
7471 | s->pc += 2; | |
7472 | insn |= (uint32_t)insn_hw1 << 16; | |
7473 | ||
7474 | if ((insn & 0xf800e800) != 0xf000e800) { | |
7475 | ARCH(6T2); | |
7476 | } | |
7477 | ||
7478 | rn = (insn >> 16) & 0xf; | |
7479 | rs = (insn >> 12) & 0xf; | |
7480 | rd = (insn >> 8) & 0xf; | |
7481 | rm = insn & 0xf; | |
7482 | switch ((insn >> 25) & 0xf) { | |
7483 | case 0: case 1: case 2: case 3: | |
7484 | /* 16-bit instructions. Should never happen. */ | |
7485 | abort(); | |
7486 | case 4: | |
7487 | if (insn & (1 << 22)) { | |
7488 | /* Other load/store, table branch. */ | |
7489 | if (insn & 0x01200000) { | |
7490 | /* Load/store doubleword. */ | |
7491 | if (rn == 15) { | |
b0109805 PB |
7492 | addr = new_tmp(); |
7493 | tcg_gen_movi_i32(addr, s->pc & ~3); | |
9ee6e8bb | 7494 | } else { |
b0109805 | 7495 | addr = load_reg(s, rn); |
9ee6e8bb PB |
7496 | } |
7497 | offset = (insn & 0xff) * 4; | |
7498 | if ((insn & (1 << 23)) == 0) | |
7499 | offset = -offset; | |
7500 | if (insn & (1 << 24)) { | |
b0109805 | 7501 | tcg_gen_addi_i32(addr, addr, offset); |
9ee6e8bb PB |
7502 | offset = 0; |
7503 | } | |
7504 | if (insn & (1 << 20)) { | |
7505 | /* ldrd */ | |
b0109805 PB |
7506 | tmp = gen_ld32(addr, IS_USER(s)); |
7507 | store_reg(s, rs, tmp); | |
7508 | tcg_gen_addi_i32(addr, addr, 4); | |
7509 | tmp = gen_ld32(addr, IS_USER(s)); | |
7510 | store_reg(s, rd, tmp); | |
9ee6e8bb PB |
7511 | } else { |
7512 | /* strd */ | |
b0109805 PB |
7513 | tmp = load_reg(s, rs); |
7514 | gen_st32(tmp, addr, IS_USER(s)); | |
7515 | tcg_gen_addi_i32(addr, addr, 4); | |
7516 | tmp = load_reg(s, rd); | |
7517 | gen_st32(tmp, addr, IS_USER(s)); | |
9ee6e8bb PB |
7518 | } |
7519 | if (insn & (1 << 21)) { | |
7520 | /* Base writeback. */ | |
7521 | if (rn == 15) | |
7522 | goto illegal_op; | |
b0109805 PB |
7523 | tcg_gen_addi_i32(addr, addr, offset - 4); |
7524 | store_reg(s, rn, addr); | |
7525 | } else { | |
7526 | dead_tmp(addr); | |
9ee6e8bb PB |
7527 | } |
7528 | } else if ((insn & (1 << 23)) == 0) { | |
7529 | /* Load/store exclusive word. */ | |
3174f8e9 | 7530 | addr = tcg_temp_local_new(); |
98a46317 | 7531 | load_reg_var(s, addr, rn); |
426f5abc | 7532 | tcg_gen_addi_i32(addr, addr, (insn & 0xff) << 2); |
2c0262af | 7533 | if (insn & (1 << 20)) { |
426f5abc | 7534 | gen_load_exclusive(s, rs, 15, addr, 2); |
9ee6e8bb | 7535 | } else { |
426f5abc | 7536 | gen_store_exclusive(s, rd, rs, 15, addr, 2); |
9ee6e8bb | 7537 | } |
3174f8e9 | 7538 | tcg_temp_free(addr); |
9ee6e8bb PB |
7539 | } else if ((insn & (1 << 6)) == 0) { |
7540 | /* Table Branch. */ | |
7541 | if (rn == 15) { | |
b0109805 PB |
7542 | addr = new_tmp(); |
7543 | tcg_gen_movi_i32(addr, s->pc); | |
9ee6e8bb | 7544 | } else { |
b0109805 | 7545 | addr = load_reg(s, rn); |
9ee6e8bb | 7546 | } |
b26eefb6 | 7547 | tmp = load_reg(s, rm); |
b0109805 | 7548 | tcg_gen_add_i32(addr, addr, tmp); |
9ee6e8bb PB |
7549 | if (insn & (1 << 4)) { |
7550 | /* tbh */ | |
b0109805 | 7551 | tcg_gen_add_i32(addr, addr, tmp); |
b26eefb6 | 7552 | dead_tmp(tmp); |
b0109805 | 7553 | tmp = gen_ld16u(addr, IS_USER(s)); |
9ee6e8bb | 7554 | } else { /* tbb */ |
b26eefb6 | 7555 | dead_tmp(tmp); |
b0109805 | 7556 | tmp = gen_ld8u(addr, IS_USER(s)); |
9ee6e8bb | 7557 | } |
b0109805 PB |
7558 | dead_tmp(addr); |
7559 | tcg_gen_shli_i32(tmp, tmp, 1); | |
7560 | tcg_gen_addi_i32(tmp, tmp, s->pc); | |
7561 | store_reg(s, 15, tmp); | |
9ee6e8bb PB |
7562 | } else { |
7563 | /* Load/store exclusive byte/halfword/doubleword. */ | |
426f5abc | 7564 | ARCH(7); |
9ee6e8bb | 7565 | op = (insn >> 4) & 0x3; |
426f5abc PB |
7566 | if (op == 2) { |
7567 | goto illegal_op; | |
7568 | } | |
3174f8e9 | 7569 | addr = tcg_temp_local_new(); |
98a46317 | 7570 | load_reg_var(s, addr, rn); |
9ee6e8bb | 7571 | if (insn & (1 << 20)) { |
426f5abc | 7572 | gen_load_exclusive(s, rs, rd, addr, op); |
9ee6e8bb | 7573 | } else { |
426f5abc | 7574 | gen_store_exclusive(s, rm, rs, rd, addr, op); |
9ee6e8bb | 7575 | } |
3174f8e9 | 7576 | tcg_temp_free(addr); |
9ee6e8bb PB |
7577 | } |
7578 | } else { | |
7579 | /* Load/store multiple, RFE, SRS. */ | |
7580 | if (((insn >> 23) & 1) == ((insn >> 24) & 1)) { | |
7581 | /* Not available in user mode. */ | |
b0109805 | 7582 | if (IS_USER(s)) |
9ee6e8bb PB |
7583 | goto illegal_op; |
7584 | if (insn & (1 << 20)) { | |
7585 | /* rfe */ | |
b0109805 PB |
7586 | addr = load_reg(s, rn); |
7587 | if ((insn & (1 << 24)) == 0) | |
7588 | tcg_gen_addi_i32(addr, addr, -8); | |
7589 | /* Load PC into tmp and CPSR into tmp2. */ | |
7590 | tmp = gen_ld32(addr, 0); | |
7591 | tcg_gen_addi_i32(addr, addr, 4); | |
7592 | tmp2 = gen_ld32(addr, 0); | |
9ee6e8bb PB |
7593 | if (insn & (1 << 21)) { |
7594 | /* Base writeback. */ | |
b0109805 PB |
7595 | if (insn & (1 << 24)) { |
7596 | tcg_gen_addi_i32(addr, addr, 4); | |
7597 | } else { | |
7598 | tcg_gen_addi_i32(addr, addr, -4); | |
7599 | } | |
7600 | store_reg(s, rn, addr); | |
7601 | } else { | |
7602 | dead_tmp(addr); | |
9ee6e8bb | 7603 | } |
b0109805 | 7604 | gen_rfe(s, tmp, tmp2); |
9ee6e8bb PB |
7605 | } else { |
7606 | /* srs */ | |
7607 | op = (insn & 0x1f); | |
39ea3d4e PM |
7608 | addr = new_tmp(); |
7609 | tmp = tcg_const_i32(op); | |
7610 | gen_helper_get_r13_banked(addr, cpu_env, tmp); | |
7611 | tcg_temp_free_i32(tmp); | |
9ee6e8bb | 7612 | if ((insn & (1 << 24)) == 0) { |
b0109805 | 7613 | tcg_gen_addi_i32(addr, addr, -8); |
9ee6e8bb | 7614 | } |
b0109805 PB |
7615 | tmp = load_reg(s, 14); |
7616 | gen_st32(tmp, addr, 0); | |
7617 | tcg_gen_addi_i32(addr, addr, 4); | |
7618 | tmp = new_tmp(); | |
7619 | gen_helper_cpsr_read(tmp); | |
7620 | gen_st32(tmp, addr, 0); | |
9ee6e8bb PB |
7621 | if (insn & (1 << 21)) { |
7622 | if ((insn & (1 << 24)) == 0) { | |
b0109805 | 7623 | tcg_gen_addi_i32(addr, addr, -4); |
9ee6e8bb | 7624 | } else { |
b0109805 | 7625 | tcg_gen_addi_i32(addr, addr, 4); |
9ee6e8bb | 7626 | } |
39ea3d4e PM |
7627 | tmp = tcg_const_i32(op); |
7628 | gen_helper_set_r13_banked(cpu_env, tmp, addr); | |
7629 | tcg_temp_free_i32(tmp); | |
b0109805 PB |
7630 | } else { |
7631 | dead_tmp(addr); | |
9ee6e8bb PB |
7632 | } |
7633 | } | |
7634 | } else { | |
7635 | int i; | |
7636 | /* Load/store multiple. */ | |
b0109805 | 7637 | addr = load_reg(s, rn); |
9ee6e8bb PB |
7638 | offset = 0; |
7639 | for (i = 0; i < 16; i++) { | |
7640 | if (insn & (1 << i)) | |
7641 | offset += 4; | |
7642 | } | |
7643 | if (insn & (1 << 24)) { | |
b0109805 | 7644 | tcg_gen_addi_i32(addr, addr, -offset); |
9ee6e8bb PB |
7645 | } |
7646 | ||
7647 | for (i = 0; i < 16; i++) { | |
7648 | if ((insn & (1 << i)) == 0) | |
7649 | continue; | |
7650 | if (insn & (1 << 20)) { | |
7651 | /* Load. */ | |
b0109805 | 7652 | tmp = gen_ld32(addr, IS_USER(s)); |
9ee6e8bb | 7653 | if (i == 15) { |
b0109805 | 7654 | gen_bx(s, tmp); |
9ee6e8bb | 7655 | } else { |
b0109805 | 7656 | store_reg(s, i, tmp); |
9ee6e8bb PB |
7657 | } |
7658 | } else { | |
7659 | /* Store. */ | |
b0109805 PB |
7660 | tmp = load_reg(s, i); |
7661 | gen_st32(tmp, addr, IS_USER(s)); | |
9ee6e8bb | 7662 | } |
b0109805 | 7663 | tcg_gen_addi_i32(addr, addr, 4); |
9ee6e8bb PB |
7664 | } |
7665 | if (insn & (1 << 21)) { | |
7666 | /* Base register writeback. */ | |
7667 | if (insn & (1 << 24)) { | |
b0109805 | 7668 | tcg_gen_addi_i32(addr, addr, -offset); |
9ee6e8bb PB |
7669 | } |
7670 | /* Fault if writeback register is in register list. */ | |
7671 | if (insn & (1 << rn)) | |
7672 | goto illegal_op; | |
b0109805 PB |
7673 | store_reg(s, rn, addr); |
7674 | } else { | |
7675 | dead_tmp(addr); | |
9ee6e8bb PB |
7676 | } |
7677 | } | |
7678 | } | |
7679 | break; | |
2af9ab77 JB |
7680 | case 5: |
7681 | ||
9ee6e8bb | 7682 | op = (insn >> 21) & 0xf; |
2af9ab77 JB |
7683 | if (op == 6) { |
7684 | /* Halfword pack. */ | |
7685 | tmp = load_reg(s, rn); | |
7686 | tmp2 = load_reg(s, rm); | |
7687 | shift = ((insn >> 10) & 0x1c) | ((insn >> 6) & 0x3); | |
7688 | if (insn & (1 << 5)) { | |
7689 | /* pkhtb */ | |
7690 | if (shift == 0) | |
7691 | shift = 31; | |
7692 | tcg_gen_sari_i32(tmp2, tmp2, shift); | |
7693 | tcg_gen_andi_i32(tmp, tmp, 0xffff0000); | |
7694 | tcg_gen_ext16u_i32(tmp2, tmp2); | |
7695 | } else { | |
7696 | /* pkhbt */ | |
7697 | if (shift) | |
7698 | tcg_gen_shli_i32(tmp2, tmp2, shift); | |
7699 | tcg_gen_ext16u_i32(tmp, tmp); | |
7700 | tcg_gen_andi_i32(tmp2, tmp2, 0xffff0000); | |
7701 | } | |
7702 | tcg_gen_or_i32(tmp, tmp, tmp2); | |
7703 | dead_tmp(tmp2); | |
3174f8e9 FN |
7704 | store_reg(s, rd, tmp); |
7705 | } else { | |
2af9ab77 JB |
7706 | /* Data processing register constant shift. */ |
7707 | if (rn == 15) { | |
7708 | tmp = new_tmp(); | |
7709 | tcg_gen_movi_i32(tmp, 0); | |
7710 | } else { | |
7711 | tmp = load_reg(s, rn); | |
7712 | } | |
7713 | tmp2 = load_reg(s, rm); | |
7714 | ||
7715 | shiftop = (insn >> 4) & 3; | |
7716 | shift = ((insn >> 6) & 3) | ((insn >> 10) & 0x1c); | |
7717 | conds = (insn & (1 << 20)) != 0; | |
7718 | logic_cc = (conds && thumb2_logic_op(op)); | |
7719 | gen_arm_shift_im(tmp2, shiftop, shift, logic_cc); | |
7720 | if (gen_thumb2_data_op(s, op, conds, 0, tmp, tmp2)) | |
7721 | goto illegal_op; | |
7722 | dead_tmp(tmp2); | |
7723 | if (rd != 15) { | |
7724 | store_reg(s, rd, tmp); | |
7725 | } else { | |
7726 | dead_tmp(tmp); | |
7727 | } | |
3174f8e9 | 7728 | } |
9ee6e8bb PB |
7729 | break; |
7730 | case 13: /* Misc data processing. */ | |
7731 | op = ((insn >> 22) & 6) | ((insn >> 7) & 1); | |
7732 | if (op < 4 && (insn & 0xf000) != 0xf000) | |
7733 | goto illegal_op; | |
7734 | switch (op) { | |
7735 | case 0: /* Register controlled shift. */ | |
8984bd2e PB |
7736 | tmp = load_reg(s, rn); |
7737 | tmp2 = load_reg(s, rm); | |
9ee6e8bb PB |
7738 | if ((insn & 0x70) != 0) |
7739 | goto illegal_op; | |
7740 | op = (insn >> 21) & 3; | |
8984bd2e PB |
7741 | logic_cc = (insn & (1 << 20)) != 0; |
7742 | gen_arm_shift_reg(tmp, op, tmp2, logic_cc); | |
7743 | if (logic_cc) | |
7744 | gen_logic_CC(tmp); | |
21aeb343 | 7745 | store_reg_bx(env, s, rd, tmp); |
9ee6e8bb PB |
7746 | break; |
7747 | case 1: /* Sign/zero extend. */ | |
5e3f878a | 7748 | tmp = load_reg(s, rm); |
9ee6e8bb PB |
7749 | shift = (insn >> 4) & 3; |
7750 | /* ??? In many cases it's not neccessary to do a | |
7751 | rotate, a shift is sufficient. */ | |
7752 | if (shift != 0) | |
f669df27 | 7753 | tcg_gen_rotri_i32(tmp, tmp, shift * 8); |
9ee6e8bb PB |
7754 | op = (insn >> 20) & 7; |
7755 | switch (op) { | |
5e3f878a PB |
7756 | case 0: gen_sxth(tmp); break; |
7757 | case 1: gen_uxth(tmp); break; | |
7758 | case 2: gen_sxtb16(tmp); break; | |
7759 | case 3: gen_uxtb16(tmp); break; | |
7760 | case 4: gen_sxtb(tmp); break; | |
7761 | case 5: gen_uxtb(tmp); break; | |
9ee6e8bb PB |
7762 | default: goto illegal_op; |
7763 | } | |
7764 | if (rn != 15) { | |
5e3f878a | 7765 | tmp2 = load_reg(s, rn); |
9ee6e8bb | 7766 | if ((op >> 1) == 1) { |
5e3f878a | 7767 | gen_add16(tmp, tmp2); |
9ee6e8bb | 7768 | } else { |
5e3f878a PB |
7769 | tcg_gen_add_i32(tmp, tmp, tmp2); |
7770 | dead_tmp(tmp2); | |
9ee6e8bb PB |
7771 | } |
7772 | } | |
5e3f878a | 7773 | store_reg(s, rd, tmp); |
9ee6e8bb PB |
7774 | break; |
7775 | case 2: /* SIMD add/subtract. */ | |
7776 | op = (insn >> 20) & 7; | |
7777 | shift = (insn >> 4) & 7; | |
7778 | if ((op & 3) == 3 || (shift & 3) == 3) | |
7779 | goto illegal_op; | |
6ddbc6e4 PB |
7780 | tmp = load_reg(s, rn); |
7781 | tmp2 = load_reg(s, rm); | |
7782 | gen_thumb2_parallel_addsub(op, shift, tmp, tmp2); | |
7783 | dead_tmp(tmp2); | |
7784 | store_reg(s, rd, tmp); | |
9ee6e8bb PB |
7785 | break; |
7786 | case 3: /* Other data processing. */ | |
7787 | op = ((insn >> 17) & 0x38) | ((insn >> 4) & 7); | |
7788 | if (op < 4) { | |
7789 | /* Saturating add/subtract. */ | |
d9ba4830 PB |
7790 | tmp = load_reg(s, rn); |
7791 | tmp2 = load_reg(s, rm); | |
9ee6e8bb | 7792 | if (op & 1) |
4809c612 JB |
7793 | gen_helper_double_saturate(tmp, tmp); |
7794 | if (op & 2) | |
d9ba4830 | 7795 | gen_helper_sub_saturate(tmp, tmp2, tmp); |
9ee6e8bb | 7796 | else |
d9ba4830 PB |
7797 | gen_helper_add_saturate(tmp, tmp, tmp2); |
7798 | dead_tmp(tmp2); | |
9ee6e8bb | 7799 | } else { |
d9ba4830 | 7800 | tmp = load_reg(s, rn); |
9ee6e8bb PB |
7801 | switch (op) { |
7802 | case 0x0a: /* rbit */ | |
d9ba4830 | 7803 | gen_helper_rbit(tmp, tmp); |
9ee6e8bb PB |
7804 | break; |
7805 | case 0x08: /* rev */ | |
66896cb8 | 7806 | tcg_gen_bswap32_i32(tmp, tmp); |
9ee6e8bb PB |
7807 | break; |
7808 | case 0x09: /* rev16 */ | |
d9ba4830 | 7809 | gen_rev16(tmp); |
9ee6e8bb PB |
7810 | break; |
7811 | case 0x0b: /* revsh */ | |
d9ba4830 | 7812 | gen_revsh(tmp); |
9ee6e8bb PB |
7813 | break; |
7814 | case 0x10: /* sel */ | |
d9ba4830 | 7815 | tmp2 = load_reg(s, rm); |
6ddbc6e4 PB |
7816 | tmp3 = new_tmp(); |
7817 | tcg_gen_ld_i32(tmp3, cpu_env, offsetof(CPUState, GE)); | |
d9ba4830 | 7818 | gen_helper_sel_flags(tmp, tmp3, tmp, tmp2); |
6ddbc6e4 | 7819 | dead_tmp(tmp3); |
d9ba4830 | 7820 | dead_tmp(tmp2); |
9ee6e8bb PB |
7821 | break; |
7822 | case 0x18: /* clz */ | |
d9ba4830 | 7823 | gen_helper_clz(tmp, tmp); |
9ee6e8bb PB |
7824 | break; |
7825 | default: | |
7826 | goto illegal_op; | |
7827 | } | |
7828 | } | |
d9ba4830 | 7829 | store_reg(s, rd, tmp); |
9ee6e8bb PB |
7830 | break; |
7831 | case 4: case 5: /* 32-bit multiply. Sum of absolute differences. */ | |
7832 | op = (insn >> 4) & 0xf; | |
d9ba4830 PB |
7833 | tmp = load_reg(s, rn); |
7834 | tmp2 = load_reg(s, rm); | |
9ee6e8bb PB |
7835 | switch ((insn >> 20) & 7) { |
7836 | case 0: /* 32 x 32 -> 32 */ | |
d9ba4830 PB |
7837 | tcg_gen_mul_i32(tmp, tmp, tmp2); |
7838 | dead_tmp(tmp2); | |
9ee6e8bb | 7839 | if (rs != 15) { |
d9ba4830 | 7840 | tmp2 = load_reg(s, rs); |
9ee6e8bb | 7841 | if (op) |
d9ba4830 | 7842 | tcg_gen_sub_i32(tmp, tmp2, tmp); |
9ee6e8bb | 7843 | else |
d9ba4830 PB |
7844 | tcg_gen_add_i32(tmp, tmp, tmp2); |
7845 | dead_tmp(tmp2); | |
9ee6e8bb | 7846 | } |
9ee6e8bb PB |
7847 | break; |
7848 | case 1: /* 16 x 16 -> 32 */ | |
d9ba4830 PB |
7849 | gen_mulxy(tmp, tmp2, op & 2, op & 1); |
7850 | dead_tmp(tmp2); | |
9ee6e8bb | 7851 | if (rs != 15) { |
d9ba4830 PB |
7852 | tmp2 = load_reg(s, rs); |
7853 | gen_helper_add_setq(tmp, tmp, tmp2); | |
7854 | dead_tmp(tmp2); | |
9ee6e8bb | 7855 | } |
9ee6e8bb PB |
7856 | break; |
7857 | case 2: /* Dual multiply add. */ | |
7858 | case 4: /* Dual multiply subtract. */ | |
7859 | if (op) | |
d9ba4830 PB |
7860 | gen_swap_half(tmp2); |
7861 | gen_smul_dual(tmp, tmp2); | |
9ee6e8bb PB |
7862 | /* This addition cannot overflow. */ |
7863 | if (insn & (1 << 22)) { | |
d9ba4830 | 7864 | tcg_gen_sub_i32(tmp, tmp, tmp2); |
9ee6e8bb | 7865 | } else { |
d9ba4830 | 7866 | tcg_gen_add_i32(tmp, tmp, tmp2); |
9ee6e8bb | 7867 | } |
d9ba4830 | 7868 | dead_tmp(tmp2); |
9ee6e8bb PB |
7869 | if (rs != 15) |
7870 | { | |
d9ba4830 PB |
7871 | tmp2 = load_reg(s, rs); |
7872 | gen_helper_add_setq(tmp, tmp, tmp2); | |
7873 | dead_tmp(tmp2); | |
9ee6e8bb | 7874 | } |
9ee6e8bb PB |
7875 | break; |
7876 | case 3: /* 32 * 16 -> 32msb */ | |
7877 | if (op) | |
d9ba4830 | 7878 | tcg_gen_sari_i32(tmp2, tmp2, 16); |
9ee6e8bb | 7879 | else |
d9ba4830 | 7880 | gen_sxth(tmp2); |
a7812ae4 PB |
7881 | tmp64 = gen_muls_i64_i32(tmp, tmp2); |
7882 | tcg_gen_shri_i64(tmp64, tmp64, 16); | |
5e3f878a | 7883 | tmp = new_tmp(); |
a7812ae4 | 7884 | tcg_gen_trunc_i64_i32(tmp, tmp64); |
b75263d6 | 7885 | tcg_temp_free_i64(tmp64); |
9ee6e8bb PB |
7886 | if (rs != 15) |
7887 | { | |
d9ba4830 PB |
7888 | tmp2 = load_reg(s, rs); |
7889 | gen_helper_add_setq(tmp, tmp, tmp2); | |
7890 | dead_tmp(tmp2); | |
9ee6e8bb | 7891 | } |
9ee6e8bb | 7892 | break; |
838fa72d AJ |
7893 | case 5: case 6: /* 32 * 32 -> 32msb (SMMUL, SMMLA, SMMLS) */ |
7894 | tmp64 = gen_muls_i64_i32(tmp, tmp2); | |
9ee6e8bb | 7895 | if (rs != 15) { |
838fa72d AJ |
7896 | tmp = load_reg(s, rs); |
7897 | if (insn & (1 << 20)) { | |
7898 | tmp64 = gen_addq_msw(tmp64, tmp); | |
99c475ab | 7899 | } else { |
838fa72d | 7900 | tmp64 = gen_subq_msw(tmp64, tmp); |
99c475ab | 7901 | } |
2c0262af | 7902 | } |
838fa72d AJ |
7903 | if (insn & (1 << 4)) { |
7904 | tcg_gen_addi_i64(tmp64, tmp64, 0x80000000u); | |
7905 | } | |
7906 | tcg_gen_shri_i64(tmp64, tmp64, 32); | |
7907 | tmp = new_tmp(); | |
7908 | tcg_gen_trunc_i64_i32(tmp, tmp64); | |
7909 | tcg_temp_free_i64(tmp64); | |
9ee6e8bb PB |
7910 | break; |
7911 | case 7: /* Unsigned sum of absolute differences. */ | |
d9ba4830 PB |
7912 | gen_helper_usad8(tmp, tmp, tmp2); |
7913 | dead_tmp(tmp2); | |
9ee6e8bb | 7914 | if (rs != 15) { |
d9ba4830 PB |
7915 | tmp2 = load_reg(s, rs); |
7916 | tcg_gen_add_i32(tmp, tmp, tmp2); | |
7917 | dead_tmp(tmp2); | |
5fd46862 | 7918 | } |
9ee6e8bb | 7919 | break; |
2c0262af | 7920 | } |
d9ba4830 | 7921 | store_reg(s, rd, tmp); |
2c0262af | 7922 | break; |
9ee6e8bb PB |
7923 | case 6: case 7: /* 64-bit multiply, Divide. */ |
7924 | op = ((insn >> 4) & 0xf) | ((insn >> 16) & 0x70); | |
5e3f878a PB |
7925 | tmp = load_reg(s, rn); |
7926 | tmp2 = load_reg(s, rm); | |
9ee6e8bb PB |
7927 | if ((op & 0x50) == 0x10) { |
7928 | /* sdiv, udiv */ | |
7929 | if (!arm_feature(env, ARM_FEATURE_DIV)) | |
7930 | goto illegal_op; | |
7931 | if (op & 0x20) | |
5e3f878a | 7932 | gen_helper_udiv(tmp, tmp, tmp2); |
2c0262af | 7933 | else |
5e3f878a PB |
7934 | gen_helper_sdiv(tmp, tmp, tmp2); |
7935 | dead_tmp(tmp2); | |
7936 | store_reg(s, rd, tmp); | |
9ee6e8bb PB |
7937 | } else if ((op & 0xe) == 0xc) { |
7938 | /* Dual multiply accumulate long. */ | |
7939 | if (op & 1) | |
5e3f878a PB |
7940 | gen_swap_half(tmp2); |
7941 | gen_smul_dual(tmp, tmp2); | |
9ee6e8bb | 7942 | if (op & 0x10) { |
5e3f878a | 7943 | tcg_gen_sub_i32(tmp, tmp, tmp2); |
b5ff1b31 | 7944 | } else { |
5e3f878a | 7945 | tcg_gen_add_i32(tmp, tmp, tmp2); |
b5ff1b31 | 7946 | } |
5e3f878a | 7947 | dead_tmp(tmp2); |
a7812ae4 PB |
7948 | /* BUGFIX */ |
7949 | tmp64 = tcg_temp_new_i64(); | |
7950 | tcg_gen_ext_i32_i64(tmp64, tmp); | |
7951 | dead_tmp(tmp); | |
7952 | gen_addq(s, tmp64, rs, rd); | |
7953 | gen_storeq_reg(s, rs, rd, tmp64); | |
b75263d6 | 7954 | tcg_temp_free_i64(tmp64); |
2c0262af | 7955 | } else { |
9ee6e8bb PB |
7956 | if (op & 0x20) { |
7957 | /* Unsigned 64-bit multiply */ | |
a7812ae4 | 7958 | tmp64 = gen_mulu_i64_i32(tmp, tmp2); |
b5ff1b31 | 7959 | } else { |
9ee6e8bb PB |
7960 | if (op & 8) { |
7961 | /* smlalxy */ | |
5e3f878a PB |
7962 | gen_mulxy(tmp, tmp2, op & 2, op & 1); |
7963 | dead_tmp(tmp2); | |
a7812ae4 PB |
7964 | tmp64 = tcg_temp_new_i64(); |
7965 | tcg_gen_ext_i32_i64(tmp64, tmp); | |
5e3f878a | 7966 | dead_tmp(tmp); |
9ee6e8bb PB |
7967 | } else { |
7968 | /* Signed 64-bit multiply */ | |
a7812ae4 | 7969 | tmp64 = gen_muls_i64_i32(tmp, tmp2); |
9ee6e8bb | 7970 | } |
b5ff1b31 | 7971 | } |
9ee6e8bb PB |
7972 | if (op & 4) { |
7973 | /* umaal */ | |
a7812ae4 PB |
7974 | gen_addq_lo(s, tmp64, rs); |
7975 | gen_addq_lo(s, tmp64, rd); | |
9ee6e8bb PB |
7976 | } else if (op & 0x40) { |
7977 | /* 64-bit accumulate. */ | |
a7812ae4 | 7978 | gen_addq(s, tmp64, rs, rd); |
9ee6e8bb | 7979 | } |
a7812ae4 | 7980 | gen_storeq_reg(s, rs, rd, tmp64); |
b75263d6 | 7981 | tcg_temp_free_i64(tmp64); |
5fd46862 | 7982 | } |
2c0262af | 7983 | break; |
9ee6e8bb PB |
7984 | } |
7985 | break; | |
7986 | case 6: case 7: case 14: case 15: | |
7987 | /* Coprocessor. */ | |
7988 | if (((insn >> 24) & 3) == 3) { | |
7989 | /* Translate into the equivalent ARM encoding. */ | |
7990 | insn = (insn & 0xe2ffffff) | ((insn & (1 << 28)) >> 4); | |
7991 | if (disas_neon_data_insn(env, s, insn)) | |
7992 | goto illegal_op; | |
7993 | } else { | |
7994 | if (insn & (1 << 28)) | |
7995 | goto illegal_op; | |
7996 | if (disas_coproc_insn (env, s, insn)) | |
7997 | goto illegal_op; | |
7998 | } | |
7999 | break; | |
8000 | case 8: case 9: case 10: case 11: | |
8001 | if (insn & (1 << 15)) { | |
8002 | /* Branches, misc control. */ | |
8003 | if (insn & 0x5000) { | |
8004 | /* Unconditional branch. */ | |
8005 | /* signextend(hw1[10:0]) -> offset[:12]. */ | |
8006 | offset = ((int32_t)insn << 5) >> 9 & ~(int32_t)0xfff; | |
8007 | /* hw1[10:0] -> offset[11:1]. */ | |
8008 | offset |= (insn & 0x7ff) << 1; | |
8009 | /* (~hw2[13, 11] ^ offset[24]) -> offset[23,22] | |
8010 | offset[24:22] already have the same value because of the | |
8011 | sign extension above. */ | |
8012 | offset ^= ((~insn) & (1 << 13)) << 10; | |
8013 | offset ^= ((~insn) & (1 << 11)) << 11; | |
8014 | ||
9ee6e8bb PB |
8015 | if (insn & (1 << 14)) { |
8016 | /* Branch and link. */ | |
3174f8e9 | 8017 | tcg_gen_movi_i32(cpu_R[14], s->pc | 1); |
b5ff1b31 | 8018 | } |
3b46e624 | 8019 | |
b0109805 | 8020 | offset += s->pc; |
9ee6e8bb PB |
8021 | if (insn & (1 << 12)) { |
8022 | /* b/bl */ | |
b0109805 | 8023 | gen_jmp(s, offset); |
9ee6e8bb PB |
8024 | } else { |
8025 | /* blx */ | |
b0109805 PB |
8026 | offset &= ~(uint32_t)2; |
8027 | gen_bx_im(s, offset); | |
2c0262af | 8028 | } |
9ee6e8bb PB |
8029 | } else if (((insn >> 23) & 7) == 7) { |
8030 | /* Misc control */ | |
8031 | if (insn & (1 << 13)) | |
8032 | goto illegal_op; | |
8033 | ||
8034 | if (insn & (1 << 26)) { | |
8035 | /* Secure monitor call (v6Z) */ | |
8036 | goto illegal_op; /* not implemented. */ | |
2c0262af | 8037 | } else { |
9ee6e8bb PB |
8038 | op = (insn >> 20) & 7; |
8039 | switch (op) { | |
8040 | case 0: /* msr cpsr. */ | |
8041 | if (IS_M(env)) { | |
8984bd2e PB |
8042 | tmp = load_reg(s, rn); |
8043 | addr = tcg_const_i32(insn & 0xff); | |
8044 | gen_helper_v7m_msr(cpu_env, addr, tmp); | |
b75263d6 JR |
8045 | tcg_temp_free_i32(addr); |
8046 | dead_tmp(tmp); | |
9ee6e8bb PB |
8047 | gen_lookup_tb(s); |
8048 | break; | |
8049 | } | |
8050 | /* fall through */ | |
8051 | case 1: /* msr spsr. */ | |
8052 | if (IS_M(env)) | |
8053 | goto illegal_op; | |
2fbac54b FN |
8054 | tmp = load_reg(s, rn); |
8055 | if (gen_set_psr(s, | |
9ee6e8bb | 8056 | msr_mask(env, s, (insn >> 8) & 0xf, op == 1), |
2fbac54b | 8057 | op == 1, tmp)) |
9ee6e8bb PB |
8058 | goto illegal_op; |
8059 | break; | |
8060 | case 2: /* cps, nop-hint. */ | |
8061 | if (((insn >> 8) & 7) == 0) { | |
8062 | gen_nop_hint(s, insn & 0xff); | |
8063 | } | |
8064 | /* Implemented as NOP in user mode. */ | |
8065 | if (IS_USER(s)) | |
8066 | break; | |
8067 | offset = 0; | |
8068 | imm = 0; | |
8069 | if (insn & (1 << 10)) { | |
8070 | if (insn & (1 << 7)) | |
8071 | offset |= CPSR_A; | |
8072 | if (insn & (1 << 6)) | |
8073 | offset |= CPSR_I; | |
8074 | if (insn & (1 << 5)) | |
8075 | offset |= CPSR_F; | |
8076 | if (insn & (1 << 9)) | |
8077 | imm = CPSR_A | CPSR_I | CPSR_F; | |
8078 | } | |
8079 | if (insn & (1 << 8)) { | |
8080 | offset |= 0x1f; | |
8081 | imm |= (insn & 0x1f); | |
8082 | } | |
8083 | if (offset) { | |
2fbac54b | 8084 | gen_set_psr_im(s, offset, 0, imm); |
9ee6e8bb PB |
8085 | } |
8086 | break; | |
8087 | case 3: /* Special control operations. */ | |
426f5abc | 8088 | ARCH(7); |
9ee6e8bb PB |
8089 | op = (insn >> 4) & 0xf; |
8090 | switch (op) { | |
8091 | case 2: /* clrex */ | |
426f5abc | 8092 | gen_clrex(s); |
9ee6e8bb PB |
8093 | break; |
8094 | case 4: /* dsb */ | |
8095 | case 5: /* dmb */ | |
8096 | case 6: /* isb */ | |
8097 | /* These execute as NOPs. */ | |
9ee6e8bb PB |
8098 | break; |
8099 | default: | |
8100 | goto illegal_op; | |
8101 | } | |
8102 | break; | |
8103 | case 4: /* bxj */ | |
8104 | /* Trivial implementation equivalent to bx. */ | |
d9ba4830 PB |
8105 | tmp = load_reg(s, rn); |
8106 | gen_bx(s, tmp); | |
9ee6e8bb PB |
8107 | break; |
8108 | case 5: /* Exception return. */ | |
b8b45b68 RV |
8109 | if (IS_USER(s)) { |
8110 | goto illegal_op; | |
8111 | } | |
8112 | if (rn != 14 || rd != 15) { | |
8113 | goto illegal_op; | |
8114 | } | |
8115 | tmp = load_reg(s, rn); | |
8116 | tcg_gen_subi_i32(tmp, tmp, insn & 0xff); | |
8117 | gen_exception_return(s, tmp); | |
8118 | break; | |
9ee6e8bb | 8119 | case 6: /* mrs cpsr. */ |
8984bd2e | 8120 | tmp = new_tmp(); |
9ee6e8bb | 8121 | if (IS_M(env)) { |
8984bd2e PB |
8122 | addr = tcg_const_i32(insn & 0xff); |
8123 | gen_helper_v7m_mrs(tmp, cpu_env, addr); | |
b75263d6 | 8124 | tcg_temp_free_i32(addr); |
9ee6e8bb | 8125 | } else { |
8984bd2e | 8126 | gen_helper_cpsr_read(tmp); |
9ee6e8bb | 8127 | } |
8984bd2e | 8128 | store_reg(s, rd, tmp); |
9ee6e8bb PB |
8129 | break; |
8130 | case 7: /* mrs spsr. */ | |
8131 | /* Not accessible in user mode. */ | |
8132 | if (IS_USER(s) || IS_M(env)) | |
8133 | goto illegal_op; | |
d9ba4830 PB |
8134 | tmp = load_cpu_field(spsr); |
8135 | store_reg(s, rd, tmp); | |
9ee6e8bb | 8136 | break; |
2c0262af FB |
8137 | } |
8138 | } | |
9ee6e8bb PB |
8139 | } else { |
8140 | /* Conditional branch. */ | |
8141 | op = (insn >> 22) & 0xf; | |
8142 | /* Generate a conditional jump to next instruction. */ | |
8143 | s->condlabel = gen_new_label(); | |
d9ba4830 | 8144 | gen_test_cc(op ^ 1, s->condlabel); |
9ee6e8bb PB |
8145 | s->condjmp = 1; |
8146 | ||
8147 | /* offset[11:1] = insn[10:0] */ | |
8148 | offset = (insn & 0x7ff) << 1; | |
8149 | /* offset[17:12] = insn[21:16]. */ | |
8150 | offset |= (insn & 0x003f0000) >> 4; | |
8151 | /* offset[31:20] = insn[26]. */ | |
8152 | offset |= ((int32_t)((insn << 5) & 0x80000000)) >> 11; | |
8153 | /* offset[18] = insn[13]. */ | |
8154 | offset |= (insn & (1 << 13)) << 5; | |
8155 | /* offset[19] = insn[11]. */ | |
8156 | offset |= (insn & (1 << 11)) << 8; | |
8157 | ||
8158 | /* jump to the offset */ | |
b0109805 | 8159 | gen_jmp(s, s->pc + offset); |
9ee6e8bb PB |
8160 | } |
8161 | } else { | |
8162 | /* Data processing immediate. */ | |
8163 | if (insn & (1 << 25)) { | |
8164 | if (insn & (1 << 24)) { | |
8165 | if (insn & (1 << 20)) | |
8166 | goto illegal_op; | |
8167 | /* Bitfield/Saturate. */ | |
8168 | op = (insn >> 21) & 7; | |
8169 | imm = insn & 0x1f; | |
8170 | shift = ((insn >> 6) & 3) | ((insn >> 10) & 0x1c); | |
6ddbc6e4 PB |
8171 | if (rn == 15) { |
8172 | tmp = new_tmp(); | |
8173 | tcg_gen_movi_i32(tmp, 0); | |
8174 | } else { | |
8175 | tmp = load_reg(s, rn); | |
8176 | } | |
9ee6e8bb PB |
8177 | switch (op) { |
8178 | case 2: /* Signed bitfield extract. */ | |
8179 | imm++; | |
8180 | if (shift + imm > 32) | |
8181 | goto illegal_op; | |
8182 | if (imm < 32) | |
6ddbc6e4 | 8183 | gen_sbfx(tmp, shift, imm); |
9ee6e8bb PB |
8184 | break; |
8185 | case 6: /* Unsigned bitfield extract. */ | |
8186 | imm++; | |
8187 | if (shift + imm > 32) | |
8188 | goto illegal_op; | |
8189 | if (imm < 32) | |
6ddbc6e4 | 8190 | gen_ubfx(tmp, shift, (1u << imm) - 1); |
9ee6e8bb PB |
8191 | break; |
8192 | case 3: /* Bitfield insert/clear. */ | |
8193 | if (imm < shift) | |
8194 | goto illegal_op; | |
8195 | imm = imm + 1 - shift; | |
8196 | if (imm != 32) { | |
6ddbc6e4 | 8197 | tmp2 = load_reg(s, rd); |
8f8e3aa4 | 8198 | gen_bfi(tmp, tmp2, tmp, shift, (1u << imm) - 1); |
6ddbc6e4 | 8199 | dead_tmp(tmp2); |
9ee6e8bb PB |
8200 | } |
8201 | break; | |
8202 | case 7: | |
8203 | goto illegal_op; | |
8204 | default: /* Saturate. */ | |
9ee6e8bb PB |
8205 | if (shift) { |
8206 | if (op & 1) | |
6ddbc6e4 | 8207 | tcg_gen_sari_i32(tmp, tmp, shift); |
9ee6e8bb | 8208 | else |
6ddbc6e4 | 8209 | tcg_gen_shli_i32(tmp, tmp, shift); |
9ee6e8bb | 8210 | } |
6ddbc6e4 | 8211 | tmp2 = tcg_const_i32(imm); |
9ee6e8bb PB |
8212 | if (op & 4) { |
8213 | /* Unsigned. */ | |
9ee6e8bb | 8214 | if ((op & 1) && shift == 0) |
6ddbc6e4 | 8215 | gen_helper_usat16(tmp, tmp, tmp2); |
9ee6e8bb | 8216 | else |
6ddbc6e4 | 8217 | gen_helper_usat(tmp, tmp, tmp2); |
2c0262af | 8218 | } else { |
9ee6e8bb | 8219 | /* Signed. */ |
9ee6e8bb | 8220 | if ((op & 1) && shift == 0) |
6ddbc6e4 | 8221 | gen_helper_ssat16(tmp, tmp, tmp2); |
9ee6e8bb | 8222 | else |
6ddbc6e4 | 8223 | gen_helper_ssat(tmp, tmp, tmp2); |
2c0262af | 8224 | } |
b75263d6 | 8225 | tcg_temp_free_i32(tmp2); |
9ee6e8bb | 8226 | break; |
2c0262af | 8227 | } |
6ddbc6e4 | 8228 | store_reg(s, rd, tmp); |
9ee6e8bb PB |
8229 | } else { |
8230 | imm = ((insn & 0x04000000) >> 15) | |
8231 | | ((insn & 0x7000) >> 4) | (insn & 0xff); | |
8232 | if (insn & (1 << 22)) { | |
8233 | /* 16-bit immediate. */ | |
8234 | imm |= (insn >> 4) & 0xf000; | |
8235 | if (insn & (1 << 23)) { | |
8236 | /* movt */ | |
5e3f878a | 8237 | tmp = load_reg(s, rd); |
86831435 | 8238 | tcg_gen_ext16u_i32(tmp, tmp); |
5e3f878a | 8239 | tcg_gen_ori_i32(tmp, tmp, imm << 16); |
2c0262af | 8240 | } else { |
9ee6e8bb | 8241 | /* movw */ |
5e3f878a PB |
8242 | tmp = new_tmp(); |
8243 | tcg_gen_movi_i32(tmp, imm); | |
2c0262af FB |
8244 | } |
8245 | } else { | |
9ee6e8bb PB |
8246 | /* Add/sub 12-bit immediate. */ |
8247 | if (rn == 15) { | |
b0109805 | 8248 | offset = s->pc & ~(uint32_t)3; |
9ee6e8bb | 8249 | if (insn & (1 << 23)) |
b0109805 | 8250 | offset -= imm; |
9ee6e8bb | 8251 | else |
b0109805 | 8252 | offset += imm; |
5e3f878a PB |
8253 | tmp = new_tmp(); |
8254 | tcg_gen_movi_i32(tmp, offset); | |
2c0262af | 8255 | } else { |
5e3f878a | 8256 | tmp = load_reg(s, rn); |
9ee6e8bb | 8257 | if (insn & (1 << 23)) |
5e3f878a | 8258 | tcg_gen_subi_i32(tmp, tmp, imm); |
9ee6e8bb | 8259 | else |
5e3f878a | 8260 | tcg_gen_addi_i32(tmp, tmp, imm); |
2c0262af | 8261 | } |
9ee6e8bb | 8262 | } |
5e3f878a | 8263 | store_reg(s, rd, tmp); |
191abaa2 | 8264 | } |
9ee6e8bb PB |
8265 | } else { |
8266 | int shifter_out = 0; | |
8267 | /* modified 12-bit immediate. */ | |
8268 | shift = ((insn & 0x04000000) >> 23) | ((insn & 0x7000) >> 12); | |
8269 | imm = (insn & 0xff); | |
8270 | switch (shift) { | |
8271 | case 0: /* XY */ | |
8272 | /* Nothing to do. */ | |
8273 | break; | |
8274 | case 1: /* 00XY00XY */ | |
8275 | imm |= imm << 16; | |
8276 | break; | |
8277 | case 2: /* XY00XY00 */ | |
8278 | imm |= imm << 16; | |
8279 | imm <<= 8; | |
8280 | break; | |
8281 | case 3: /* XYXYXYXY */ | |
8282 | imm |= imm << 16; | |
8283 | imm |= imm << 8; | |
8284 | break; | |
8285 | default: /* Rotated constant. */ | |
8286 | shift = (shift << 1) | (imm >> 7); | |
8287 | imm |= 0x80; | |
8288 | imm = imm << (32 - shift); | |
8289 | shifter_out = 1; | |
8290 | break; | |
b5ff1b31 | 8291 | } |
3174f8e9 FN |
8292 | tmp2 = new_tmp(); |
8293 | tcg_gen_movi_i32(tmp2, imm); | |
9ee6e8bb | 8294 | rn = (insn >> 16) & 0xf; |
3174f8e9 FN |
8295 | if (rn == 15) { |
8296 | tmp = new_tmp(); | |
8297 | tcg_gen_movi_i32(tmp, 0); | |
8298 | } else { | |
8299 | tmp = load_reg(s, rn); | |
8300 | } | |
9ee6e8bb PB |
8301 | op = (insn >> 21) & 0xf; |
8302 | if (gen_thumb2_data_op(s, op, (insn & (1 << 20)) != 0, | |
3174f8e9 | 8303 | shifter_out, tmp, tmp2)) |
9ee6e8bb | 8304 | goto illegal_op; |
3174f8e9 | 8305 | dead_tmp(tmp2); |
9ee6e8bb PB |
8306 | rd = (insn >> 8) & 0xf; |
8307 | if (rd != 15) { | |
3174f8e9 FN |
8308 | store_reg(s, rd, tmp); |
8309 | } else { | |
8310 | dead_tmp(tmp); | |
2c0262af | 8311 | } |
2c0262af | 8312 | } |
9ee6e8bb PB |
8313 | } |
8314 | break; | |
8315 | case 12: /* Load/store single data item. */ | |
8316 | { | |
8317 | int postinc = 0; | |
8318 | int writeback = 0; | |
b0109805 | 8319 | int user; |
9ee6e8bb PB |
8320 | if ((insn & 0x01100000) == 0x01000000) { |
8321 | if (disas_neon_ls_insn(env, s, insn)) | |
c1713132 | 8322 | goto illegal_op; |
9ee6e8bb PB |
8323 | break; |
8324 | } | |
a2fdc890 PM |
8325 | op = ((insn >> 21) & 3) | ((insn >> 22) & 4); |
8326 | if (rs == 15) { | |
8327 | if (!(insn & (1 << 20))) { | |
8328 | goto illegal_op; | |
8329 | } | |
8330 | if (op != 2) { | |
8331 | /* Byte or halfword load space with dest == r15 : memory hints. | |
8332 | * Catch them early so we don't emit pointless addressing code. | |
8333 | * This space is a mix of: | |
8334 | * PLD/PLDW/PLI, which we implement as NOPs (note that unlike | |
8335 | * the ARM encodings, PLDW space doesn't UNDEF for non-v7MP | |
8336 | * cores) | |
8337 | * unallocated hints, which must be treated as NOPs | |
8338 | * UNPREDICTABLE space, which we NOP or UNDEF depending on | |
8339 | * which is easiest for the decoding logic | |
8340 | * Some space which must UNDEF | |
8341 | */ | |
8342 | int op1 = (insn >> 23) & 3; | |
8343 | int op2 = (insn >> 6) & 0x3f; | |
8344 | if (op & 2) { | |
8345 | goto illegal_op; | |
8346 | } | |
8347 | if (rn == 15) { | |
8348 | /* UNPREDICTABLE or unallocated hint */ | |
8349 | return 0; | |
8350 | } | |
8351 | if (op1 & 1) { | |
8352 | return 0; /* PLD* or unallocated hint */ | |
8353 | } | |
8354 | if ((op2 == 0) || ((op2 & 0x3c) == 0x30)) { | |
8355 | return 0; /* PLD* or unallocated hint */ | |
8356 | } | |
8357 | /* UNDEF space, or an UNPREDICTABLE */ | |
8358 | return 1; | |
8359 | } | |
8360 | } | |
b0109805 | 8361 | user = IS_USER(s); |
9ee6e8bb | 8362 | if (rn == 15) { |
b0109805 | 8363 | addr = new_tmp(); |
9ee6e8bb PB |
8364 | /* PC relative. */ |
8365 | /* s->pc has already been incremented by 4. */ | |
8366 | imm = s->pc & 0xfffffffc; | |
8367 | if (insn & (1 << 23)) | |
8368 | imm += insn & 0xfff; | |
8369 | else | |
8370 | imm -= insn & 0xfff; | |
b0109805 | 8371 | tcg_gen_movi_i32(addr, imm); |
9ee6e8bb | 8372 | } else { |
b0109805 | 8373 | addr = load_reg(s, rn); |
9ee6e8bb PB |
8374 | if (insn & (1 << 23)) { |
8375 | /* Positive offset. */ | |
8376 | imm = insn & 0xfff; | |
b0109805 | 8377 | tcg_gen_addi_i32(addr, addr, imm); |
9ee6e8bb | 8378 | } else { |
9ee6e8bb | 8379 | imm = insn & 0xff; |
a2fdc890 | 8380 | switch ((insn >> 8) & 7) { |
9ee6e8bb PB |
8381 | case 0: case 8: /* Shifted Register. */ |
8382 | shift = (insn >> 4) & 0xf; | |
8383 | if (shift > 3) | |
18c9b560 | 8384 | goto illegal_op; |
b26eefb6 | 8385 | tmp = load_reg(s, rm); |
9ee6e8bb | 8386 | if (shift) |
b26eefb6 | 8387 | tcg_gen_shli_i32(tmp, tmp, shift); |
b0109805 | 8388 | tcg_gen_add_i32(addr, addr, tmp); |
b26eefb6 | 8389 | dead_tmp(tmp); |
9ee6e8bb PB |
8390 | break; |
8391 | case 4: /* Negative offset. */ | |
b0109805 | 8392 | tcg_gen_addi_i32(addr, addr, -imm); |
9ee6e8bb PB |
8393 | break; |
8394 | case 6: /* User privilege. */ | |
b0109805 PB |
8395 | tcg_gen_addi_i32(addr, addr, imm); |
8396 | user = 1; | |
9ee6e8bb PB |
8397 | break; |
8398 | case 1: /* Post-decrement. */ | |
8399 | imm = -imm; | |
8400 | /* Fall through. */ | |
8401 | case 3: /* Post-increment. */ | |
9ee6e8bb PB |
8402 | postinc = 1; |
8403 | writeback = 1; | |
8404 | break; | |
8405 | case 5: /* Pre-decrement. */ | |
8406 | imm = -imm; | |
8407 | /* Fall through. */ | |
8408 | case 7: /* Pre-increment. */ | |
b0109805 | 8409 | tcg_gen_addi_i32(addr, addr, imm); |
9ee6e8bb PB |
8410 | writeback = 1; |
8411 | break; | |
8412 | default: | |
b7bcbe95 | 8413 | goto illegal_op; |
9ee6e8bb PB |
8414 | } |
8415 | } | |
8416 | } | |
9ee6e8bb PB |
8417 | if (insn & (1 << 20)) { |
8418 | /* Load. */ | |
a2fdc890 PM |
8419 | switch (op) { |
8420 | case 0: tmp = gen_ld8u(addr, user); break; | |
8421 | case 4: tmp = gen_ld8s(addr, user); break; | |
8422 | case 1: tmp = gen_ld16u(addr, user); break; | |
8423 | case 5: tmp = gen_ld16s(addr, user); break; | |
8424 | case 2: tmp = gen_ld32(addr, user); break; | |
8425 | default: goto illegal_op; | |
8426 | } | |
8427 | if (rs == 15) { | |
8428 | gen_bx(s, tmp); | |
9ee6e8bb | 8429 | } else { |
a2fdc890 | 8430 | store_reg(s, rs, tmp); |
9ee6e8bb PB |
8431 | } |
8432 | } else { | |
8433 | /* Store. */ | |
b0109805 | 8434 | tmp = load_reg(s, rs); |
9ee6e8bb | 8435 | switch (op) { |
b0109805 PB |
8436 | case 0: gen_st8(tmp, addr, user); break; |
8437 | case 1: gen_st16(tmp, addr, user); break; | |
8438 | case 2: gen_st32(tmp, addr, user); break; | |
9ee6e8bb | 8439 | default: goto illegal_op; |
b7bcbe95 | 8440 | } |
2c0262af | 8441 | } |
9ee6e8bb | 8442 | if (postinc) |
b0109805 PB |
8443 | tcg_gen_addi_i32(addr, addr, imm); |
8444 | if (writeback) { | |
8445 | store_reg(s, rn, addr); | |
8446 | } else { | |
8447 | dead_tmp(addr); | |
8448 | } | |
9ee6e8bb PB |
8449 | } |
8450 | break; | |
8451 | default: | |
8452 | goto illegal_op; | |
2c0262af | 8453 | } |
9ee6e8bb PB |
8454 | return 0; |
8455 | illegal_op: | |
8456 | return 1; | |
2c0262af FB |
8457 | } |
8458 | ||
9ee6e8bb | 8459 | static void disas_thumb_insn(CPUState *env, DisasContext *s) |
99c475ab FB |
8460 | { |
8461 | uint32_t val, insn, op, rm, rn, rd, shift, cond; | |
8462 | int32_t offset; | |
8463 | int i; | |
b26eefb6 | 8464 | TCGv tmp; |
d9ba4830 | 8465 | TCGv tmp2; |
b0109805 | 8466 | TCGv addr; |
99c475ab | 8467 | |
9ee6e8bb PB |
8468 | if (s->condexec_mask) { |
8469 | cond = s->condexec_cond; | |
bedd2912 JB |
8470 | if (cond != 0x0e) { /* Skip conditional when condition is AL. */ |
8471 | s->condlabel = gen_new_label(); | |
8472 | gen_test_cc(cond ^ 1, s->condlabel); | |
8473 | s->condjmp = 1; | |
8474 | } | |
9ee6e8bb PB |
8475 | } |
8476 | ||
b5ff1b31 | 8477 | insn = lduw_code(s->pc); |
99c475ab | 8478 | s->pc += 2; |
b5ff1b31 | 8479 | |
99c475ab FB |
8480 | switch (insn >> 12) { |
8481 | case 0: case 1: | |
396e467c | 8482 | |
99c475ab FB |
8483 | rd = insn & 7; |
8484 | op = (insn >> 11) & 3; | |
8485 | if (op == 3) { | |
8486 | /* add/subtract */ | |
8487 | rn = (insn >> 3) & 7; | |
396e467c | 8488 | tmp = load_reg(s, rn); |
99c475ab FB |
8489 | if (insn & (1 << 10)) { |
8490 | /* immediate */ | |
396e467c FN |
8491 | tmp2 = new_tmp(); |
8492 | tcg_gen_movi_i32(tmp2, (insn >> 6) & 7); | |
99c475ab FB |
8493 | } else { |
8494 | /* reg */ | |
8495 | rm = (insn >> 6) & 7; | |
396e467c | 8496 | tmp2 = load_reg(s, rm); |
99c475ab | 8497 | } |
9ee6e8bb PB |
8498 | if (insn & (1 << 9)) { |
8499 | if (s->condexec_mask) | |
396e467c | 8500 | tcg_gen_sub_i32(tmp, tmp, tmp2); |
9ee6e8bb | 8501 | else |
396e467c | 8502 | gen_helper_sub_cc(tmp, tmp, tmp2); |
9ee6e8bb PB |
8503 | } else { |
8504 | if (s->condexec_mask) | |
396e467c | 8505 | tcg_gen_add_i32(tmp, tmp, tmp2); |
9ee6e8bb | 8506 | else |
396e467c | 8507 | gen_helper_add_cc(tmp, tmp, tmp2); |
9ee6e8bb | 8508 | } |
396e467c FN |
8509 | dead_tmp(tmp2); |
8510 | store_reg(s, rd, tmp); | |
99c475ab FB |
8511 | } else { |
8512 | /* shift immediate */ | |
8513 | rm = (insn >> 3) & 7; | |
8514 | shift = (insn >> 6) & 0x1f; | |
9a119ff6 PB |
8515 | tmp = load_reg(s, rm); |
8516 | gen_arm_shift_im(tmp, op, shift, s->condexec_mask == 0); | |
8517 | if (!s->condexec_mask) | |
8518 | gen_logic_CC(tmp); | |
8519 | store_reg(s, rd, tmp); | |
99c475ab FB |
8520 | } |
8521 | break; | |
8522 | case 2: case 3: | |
8523 | /* arithmetic large immediate */ | |
8524 | op = (insn >> 11) & 3; | |
8525 | rd = (insn >> 8) & 0x7; | |
396e467c FN |
8526 | if (op == 0) { /* mov */ |
8527 | tmp = new_tmp(); | |
8528 | tcg_gen_movi_i32(tmp, insn & 0xff); | |
9ee6e8bb | 8529 | if (!s->condexec_mask) |
396e467c FN |
8530 | gen_logic_CC(tmp); |
8531 | store_reg(s, rd, tmp); | |
8532 | } else { | |
8533 | tmp = load_reg(s, rd); | |
8534 | tmp2 = new_tmp(); | |
8535 | tcg_gen_movi_i32(tmp2, insn & 0xff); | |
8536 | switch (op) { | |
8537 | case 1: /* cmp */ | |
8538 | gen_helper_sub_cc(tmp, tmp, tmp2); | |
8539 | dead_tmp(tmp); | |
8540 | dead_tmp(tmp2); | |
8541 | break; | |
8542 | case 2: /* add */ | |
8543 | if (s->condexec_mask) | |
8544 | tcg_gen_add_i32(tmp, tmp, tmp2); | |
8545 | else | |
8546 | gen_helper_add_cc(tmp, tmp, tmp2); | |
8547 | dead_tmp(tmp2); | |
8548 | store_reg(s, rd, tmp); | |
8549 | break; | |
8550 | case 3: /* sub */ | |
8551 | if (s->condexec_mask) | |
8552 | tcg_gen_sub_i32(tmp, tmp, tmp2); | |
8553 | else | |
8554 | gen_helper_sub_cc(tmp, tmp, tmp2); | |
8555 | dead_tmp(tmp2); | |
8556 | store_reg(s, rd, tmp); | |
8557 | break; | |
8558 | } | |
99c475ab | 8559 | } |
99c475ab FB |
8560 | break; |
8561 | case 4: | |
8562 | if (insn & (1 << 11)) { | |
8563 | rd = (insn >> 8) & 7; | |
5899f386 FB |
8564 | /* load pc-relative. Bit 1 of PC is ignored. */ |
8565 | val = s->pc + 2 + ((insn & 0xff) * 4); | |
8566 | val &= ~(uint32_t)2; | |
b0109805 PB |
8567 | addr = new_tmp(); |
8568 | tcg_gen_movi_i32(addr, val); | |
8569 | tmp = gen_ld32(addr, IS_USER(s)); | |
8570 | dead_tmp(addr); | |
8571 | store_reg(s, rd, tmp); | |
99c475ab FB |
8572 | break; |
8573 | } | |
8574 | if (insn & (1 << 10)) { | |
8575 | /* data processing extended or blx */ | |
8576 | rd = (insn & 7) | ((insn >> 4) & 8); | |
8577 | rm = (insn >> 3) & 0xf; | |
8578 | op = (insn >> 8) & 3; | |
8579 | switch (op) { | |
8580 | case 0: /* add */ | |
396e467c FN |
8581 | tmp = load_reg(s, rd); |
8582 | tmp2 = load_reg(s, rm); | |
8583 | tcg_gen_add_i32(tmp, tmp, tmp2); | |
8584 | dead_tmp(tmp2); | |
8585 | store_reg(s, rd, tmp); | |
99c475ab FB |
8586 | break; |
8587 | case 1: /* cmp */ | |
396e467c FN |
8588 | tmp = load_reg(s, rd); |
8589 | tmp2 = load_reg(s, rm); | |
8590 | gen_helper_sub_cc(tmp, tmp, tmp2); | |
8591 | dead_tmp(tmp2); | |
8592 | dead_tmp(tmp); | |
99c475ab FB |
8593 | break; |
8594 | case 2: /* mov/cpy */ | |
396e467c FN |
8595 | tmp = load_reg(s, rm); |
8596 | store_reg(s, rd, tmp); | |
99c475ab FB |
8597 | break; |
8598 | case 3:/* branch [and link] exchange thumb register */ | |
b0109805 | 8599 | tmp = load_reg(s, rm); |
99c475ab FB |
8600 | if (insn & (1 << 7)) { |
8601 | val = (uint32_t)s->pc | 1; | |
b0109805 PB |
8602 | tmp2 = new_tmp(); |
8603 | tcg_gen_movi_i32(tmp2, val); | |
8604 | store_reg(s, 14, tmp2); | |
99c475ab | 8605 | } |
d9ba4830 | 8606 | gen_bx(s, tmp); |
99c475ab FB |
8607 | break; |
8608 | } | |
8609 | break; | |
8610 | } | |
8611 | ||
8612 | /* data processing register */ | |
8613 | rd = insn & 7; | |
8614 | rm = (insn >> 3) & 7; | |
8615 | op = (insn >> 6) & 0xf; | |
8616 | if (op == 2 || op == 3 || op == 4 || op == 7) { | |
8617 | /* the shift/rotate ops want the operands backwards */ | |
8618 | val = rm; | |
8619 | rm = rd; | |
8620 | rd = val; | |
8621 | val = 1; | |
8622 | } else { | |
8623 | val = 0; | |
8624 | } | |
8625 | ||
396e467c FN |
8626 | if (op == 9) { /* neg */ |
8627 | tmp = new_tmp(); | |
8628 | tcg_gen_movi_i32(tmp, 0); | |
8629 | } else if (op != 0xf) { /* mvn doesn't read its first operand */ | |
8630 | tmp = load_reg(s, rd); | |
8631 | } else { | |
8632 | TCGV_UNUSED(tmp); | |
8633 | } | |
99c475ab | 8634 | |
396e467c | 8635 | tmp2 = load_reg(s, rm); |
5899f386 | 8636 | switch (op) { |
99c475ab | 8637 | case 0x0: /* and */ |
396e467c | 8638 | tcg_gen_and_i32(tmp, tmp, tmp2); |
9ee6e8bb | 8639 | if (!s->condexec_mask) |
396e467c | 8640 | gen_logic_CC(tmp); |
99c475ab FB |
8641 | break; |
8642 | case 0x1: /* eor */ | |
396e467c | 8643 | tcg_gen_xor_i32(tmp, tmp, tmp2); |
9ee6e8bb | 8644 | if (!s->condexec_mask) |
396e467c | 8645 | gen_logic_CC(tmp); |
99c475ab FB |
8646 | break; |
8647 | case 0x2: /* lsl */ | |
9ee6e8bb | 8648 | if (s->condexec_mask) { |
396e467c | 8649 | gen_helper_shl(tmp2, tmp2, tmp); |
9ee6e8bb | 8650 | } else { |
396e467c FN |
8651 | gen_helper_shl_cc(tmp2, tmp2, tmp); |
8652 | gen_logic_CC(tmp2); | |
9ee6e8bb | 8653 | } |
99c475ab FB |
8654 | break; |
8655 | case 0x3: /* lsr */ | |
9ee6e8bb | 8656 | if (s->condexec_mask) { |
396e467c | 8657 | gen_helper_shr(tmp2, tmp2, tmp); |
9ee6e8bb | 8658 | } else { |
396e467c FN |
8659 | gen_helper_shr_cc(tmp2, tmp2, tmp); |
8660 | gen_logic_CC(tmp2); | |
9ee6e8bb | 8661 | } |
99c475ab FB |
8662 | break; |
8663 | case 0x4: /* asr */ | |
9ee6e8bb | 8664 | if (s->condexec_mask) { |
396e467c | 8665 | gen_helper_sar(tmp2, tmp2, tmp); |
9ee6e8bb | 8666 | } else { |
396e467c FN |
8667 | gen_helper_sar_cc(tmp2, tmp2, tmp); |
8668 | gen_logic_CC(tmp2); | |
9ee6e8bb | 8669 | } |
99c475ab FB |
8670 | break; |
8671 | case 0x5: /* adc */ | |
9ee6e8bb | 8672 | if (s->condexec_mask) |
396e467c | 8673 | gen_adc(tmp, tmp2); |
9ee6e8bb | 8674 | else |
396e467c | 8675 | gen_helper_adc_cc(tmp, tmp, tmp2); |
99c475ab FB |
8676 | break; |
8677 | case 0x6: /* sbc */ | |
9ee6e8bb | 8678 | if (s->condexec_mask) |
396e467c | 8679 | gen_sub_carry(tmp, tmp, tmp2); |
9ee6e8bb | 8680 | else |
396e467c | 8681 | gen_helper_sbc_cc(tmp, tmp, tmp2); |
99c475ab FB |
8682 | break; |
8683 | case 0x7: /* ror */ | |
9ee6e8bb | 8684 | if (s->condexec_mask) { |
f669df27 AJ |
8685 | tcg_gen_andi_i32(tmp, tmp, 0x1f); |
8686 | tcg_gen_rotr_i32(tmp2, tmp2, tmp); | |
9ee6e8bb | 8687 | } else { |
396e467c FN |
8688 | gen_helper_ror_cc(tmp2, tmp2, tmp); |
8689 | gen_logic_CC(tmp2); | |
9ee6e8bb | 8690 | } |
99c475ab FB |
8691 | break; |
8692 | case 0x8: /* tst */ | |
396e467c FN |
8693 | tcg_gen_and_i32(tmp, tmp, tmp2); |
8694 | gen_logic_CC(tmp); | |
99c475ab | 8695 | rd = 16; |
5899f386 | 8696 | break; |
99c475ab | 8697 | case 0x9: /* neg */ |
9ee6e8bb | 8698 | if (s->condexec_mask) |
396e467c | 8699 | tcg_gen_neg_i32(tmp, tmp2); |
9ee6e8bb | 8700 | else |
396e467c | 8701 | gen_helper_sub_cc(tmp, tmp, tmp2); |
99c475ab FB |
8702 | break; |
8703 | case 0xa: /* cmp */ | |
396e467c | 8704 | gen_helper_sub_cc(tmp, tmp, tmp2); |
99c475ab FB |
8705 | rd = 16; |
8706 | break; | |
8707 | case 0xb: /* cmn */ | |
396e467c | 8708 | gen_helper_add_cc(tmp, tmp, tmp2); |
99c475ab FB |
8709 | rd = 16; |
8710 | break; | |
8711 | case 0xc: /* orr */ | |
396e467c | 8712 | tcg_gen_or_i32(tmp, tmp, tmp2); |
9ee6e8bb | 8713 | if (!s->condexec_mask) |
396e467c | 8714 | gen_logic_CC(tmp); |
99c475ab FB |
8715 | break; |
8716 | case 0xd: /* mul */ | |
7b2919a0 | 8717 | tcg_gen_mul_i32(tmp, tmp, tmp2); |
9ee6e8bb | 8718 | if (!s->condexec_mask) |
396e467c | 8719 | gen_logic_CC(tmp); |
99c475ab FB |
8720 | break; |
8721 | case 0xe: /* bic */ | |
f669df27 | 8722 | tcg_gen_andc_i32(tmp, tmp, tmp2); |
9ee6e8bb | 8723 | if (!s->condexec_mask) |
396e467c | 8724 | gen_logic_CC(tmp); |
99c475ab FB |
8725 | break; |
8726 | case 0xf: /* mvn */ | |
396e467c | 8727 | tcg_gen_not_i32(tmp2, tmp2); |
9ee6e8bb | 8728 | if (!s->condexec_mask) |
396e467c | 8729 | gen_logic_CC(tmp2); |
99c475ab | 8730 | val = 1; |
5899f386 | 8731 | rm = rd; |
99c475ab FB |
8732 | break; |
8733 | } | |
8734 | if (rd != 16) { | |
396e467c FN |
8735 | if (val) { |
8736 | store_reg(s, rm, tmp2); | |
8737 | if (op != 0xf) | |
8738 | dead_tmp(tmp); | |
8739 | } else { | |
8740 | store_reg(s, rd, tmp); | |
8741 | dead_tmp(tmp2); | |
8742 | } | |
8743 | } else { | |
8744 | dead_tmp(tmp); | |
8745 | dead_tmp(tmp2); | |
99c475ab FB |
8746 | } |
8747 | break; | |
8748 | ||
8749 | case 5: | |
8750 | /* load/store register offset. */ | |
8751 | rd = insn & 7; | |
8752 | rn = (insn >> 3) & 7; | |
8753 | rm = (insn >> 6) & 7; | |
8754 | op = (insn >> 9) & 7; | |
b0109805 | 8755 | addr = load_reg(s, rn); |
b26eefb6 | 8756 | tmp = load_reg(s, rm); |
b0109805 | 8757 | tcg_gen_add_i32(addr, addr, tmp); |
b26eefb6 | 8758 | dead_tmp(tmp); |
99c475ab FB |
8759 | |
8760 | if (op < 3) /* store */ | |
b0109805 | 8761 | tmp = load_reg(s, rd); |
99c475ab FB |
8762 | |
8763 | switch (op) { | |
8764 | case 0: /* str */ | |
b0109805 | 8765 | gen_st32(tmp, addr, IS_USER(s)); |
99c475ab FB |
8766 | break; |
8767 | case 1: /* strh */ | |
b0109805 | 8768 | gen_st16(tmp, addr, IS_USER(s)); |
99c475ab FB |
8769 | break; |
8770 | case 2: /* strb */ | |
b0109805 | 8771 | gen_st8(tmp, addr, IS_USER(s)); |
99c475ab FB |
8772 | break; |
8773 | case 3: /* ldrsb */ | |
b0109805 | 8774 | tmp = gen_ld8s(addr, IS_USER(s)); |
99c475ab FB |
8775 | break; |
8776 | case 4: /* ldr */ | |
b0109805 | 8777 | tmp = gen_ld32(addr, IS_USER(s)); |
99c475ab FB |
8778 | break; |
8779 | case 5: /* ldrh */ | |
b0109805 | 8780 | tmp = gen_ld16u(addr, IS_USER(s)); |
99c475ab FB |
8781 | break; |
8782 | case 6: /* ldrb */ | |
b0109805 | 8783 | tmp = gen_ld8u(addr, IS_USER(s)); |
99c475ab FB |
8784 | break; |
8785 | case 7: /* ldrsh */ | |
b0109805 | 8786 | tmp = gen_ld16s(addr, IS_USER(s)); |
99c475ab FB |
8787 | break; |
8788 | } | |
8789 | if (op >= 3) /* load */ | |
b0109805 PB |
8790 | store_reg(s, rd, tmp); |
8791 | dead_tmp(addr); | |
99c475ab FB |
8792 | break; |
8793 | ||
8794 | case 6: | |
8795 | /* load/store word immediate offset */ | |
8796 | rd = insn & 7; | |
8797 | rn = (insn >> 3) & 7; | |
b0109805 | 8798 | addr = load_reg(s, rn); |
99c475ab | 8799 | val = (insn >> 4) & 0x7c; |
b0109805 | 8800 | tcg_gen_addi_i32(addr, addr, val); |
99c475ab FB |
8801 | |
8802 | if (insn & (1 << 11)) { | |
8803 | /* load */ | |
b0109805 PB |
8804 | tmp = gen_ld32(addr, IS_USER(s)); |
8805 | store_reg(s, rd, tmp); | |
99c475ab FB |
8806 | } else { |
8807 | /* store */ | |
b0109805 PB |
8808 | tmp = load_reg(s, rd); |
8809 | gen_st32(tmp, addr, IS_USER(s)); | |
99c475ab | 8810 | } |
b0109805 | 8811 | dead_tmp(addr); |
99c475ab FB |
8812 | break; |
8813 | ||
8814 | case 7: | |
8815 | /* load/store byte immediate offset */ | |
8816 | rd = insn & 7; | |
8817 | rn = (insn >> 3) & 7; | |
b0109805 | 8818 | addr = load_reg(s, rn); |
99c475ab | 8819 | val = (insn >> 6) & 0x1f; |
b0109805 | 8820 | tcg_gen_addi_i32(addr, addr, val); |
99c475ab FB |
8821 | |
8822 | if (insn & (1 << 11)) { | |
8823 | /* load */ | |
b0109805 PB |
8824 | tmp = gen_ld8u(addr, IS_USER(s)); |
8825 | store_reg(s, rd, tmp); | |
99c475ab FB |
8826 | } else { |
8827 | /* store */ | |
b0109805 PB |
8828 | tmp = load_reg(s, rd); |
8829 | gen_st8(tmp, addr, IS_USER(s)); | |
99c475ab | 8830 | } |
b0109805 | 8831 | dead_tmp(addr); |
99c475ab FB |
8832 | break; |
8833 | ||
8834 | case 8: | |
8835 | /* load/store halfword immediate offset */ | |
8836 | rd = insn & 7; | |
8837 | rn = (insn >> 3) & 7; | |
b0109805 | 8838 | addr = load_reg(s, rn); |
99c475ab | 8839 | val = (insn >> 5) & 0x3e; |
b0109805 | 8840 | tcg_gen_addi_i32(addr, addr, val); |
99c475ab FB |
8841 | |
8842 | if (insn & (1 << 11)) { | |
8843 | /* load */ | |
b0109805 PB |
8844 | tmp = gen_ld16u(addr, IS_USER(s)); |
8845 | store_reg(s, rd, tmp); | |
99c475ab FB |
8846 | } else { |
8847 | /* store */ | |
b0109805 PB |
8848 | tmp = load_reg(s, rd); |
8849 | gen_st16(tmp, addr, IS_USER(s)); | |
99c475ab | 8850 | } |
b0109805 | 8851 | dead_tmp(addr); |
99c475ab FB |
8852 | break; |
8853 | ||
8854 | case 9: | |
8855 | /* load/store from stack */ | |
8856 | rd = (insn >> 8) & 7; | |
b0109805 | 8857 | addr = load_reg(s, 13); |
99c475ab | 8858 | val = (insn & 0xff) * 4; |
b0109805 | 8859 | tcg_gen_addi_i32(addr, addr, val); |
99c475ab FB |
8860 | |
8861 | if (insn & (1 << 11)) { | |
8862 | /* load */ | |
b0109805 PB |
8863 | tmp = gen_ld32(addr, IS_USER(s)); |
8864 | store_reg(s, rd, tmp); | |
99c475ab FB |
8865 | } else { |
8866 | /* store */ | |
b0109805 PB |
8867 | tmp = load_reg(s, rd); |
8868 | gen_st32(tmp, addr, IS_USER(s)); | |
99c475ab | 8869 | } |
b0109805 | 8870 | dead_tmp(addr); |
99c475ab FB |
8871 | break; |
8872 | ||
8873 | case 10: | |
8874 | /* add to high reg */ | |
8875 | rd = (insn >> 8) & 7; | |
5899f386 FB |
8876 | if (insn & (1 << 11)) { |
8877 | /* SP */ | |
5e3f878a | 8878 | tmp = load_reg(s, 13); |
5899f386 FB |
8879 | } else { |
8880 | /* PC. bit 1 is ignored. */ | |
5e3f878a PB |
8881 | tmp = new_tmp(); |
8882 | tcg_gen_movi_i32(tmp, (s->pc + 2) & ~(uint32_t)2); | |
5899f386 | 8883 | } |
99c475ab | 8884 | val = (insn & 0xff) * 4; |
5e3f878a PB |
8885 | tcg_gen_addi_i32(tmp, tmp, val); |
8886 | store_reg(s, rd, tmp); | |
99c475ab FB |
8887 | break; |
8888 | ||
8889 | case 11: | |
8890 | /* misc */ | |
8891 | op = (insn >> 8) & 0xf; | |
8892 | switch (op) { | |
8893 | case 0: | |
8894 | /* adjust stack pointer */ | |
b26eefb6 | 8895 | tmp = load_reg(s, 13); |
99c475ab FB |
8896 | val = (insn & 0x7f) * 4; |
8897 | if (insn & (1 << 7)) | |
6a0d8a1d | 8898 | val = -(int32_t)val; |
b26eefb6 PB |
8899 | tcg_gen_addi_i32(tmp, tmp, val); |
8900 | store_reg(s, 13, tmp); | |
99c475ab FB |
8901 | break; |
8902 | ||
9ee6e8bb PB |
8903 | case 2: /* sign/zero extend. */ |
8904 | ARCH(6); | |
8905 | rd = insn & 7; | |
8906 | rm = (insn >> 3) & 7; | |
b0109805 | 8907 | tmp = load_reg(s, rm); |
9ee6e8bb | 8908 | switch ((insn >> 6) & 3) { |
b0109805 PB |
8909 | case 0: gen_sxth(tmp); break; |
8910 | case 1: gen_sxtb(tmp); break; | |
8911 | case 2: gen_uxth(tmp); break; | |
8912 | case 3: gen_uxtb(tmp); break; | |
9ee6e8bb | 8913 | } |
b0109805 | 8914 | store_reg(s, rd, tmp); |
9ee6e8bb | 8915 | break; |
99c475ab FB |
8916 | case 4: case 5: case 0xc: case 0xd: |
8917 | /* push/pop */ | |
b0109805 | 8918 | addr = load_reg(s, 13); |
5899f386 FB |
8919 | if (insn & (1 << 8)) |
8920 | offset = 4; | |
99c475ab | 8921 | else |
5899f386 FB |
8922 | offset = 0; |
8923 | for (i = 0; i < 8; i++) { | |
8924 | if (insn & (1 << i)) | |
8925 | offset += 4; | |
8926 | } | |
8927 | if ((insn & (1 << 11)) == 0) { | |
b0109805 | 8928 | tcg_gen_addi_i32(addr, addr, -offset); |
5899f386 | 8929 | } |
99c475ab FB |
8930 | for (i = 0; i < 8; i++) { |
8931 | if (insn & (1 << i)) { | |
8932 | if (insn & (1 << 11)) { | |
8933 | /* pop */ | |
b0109805 PB |
8934 | tmp = gen_ld32(addr, IS_USER(s)); |
8935 | store_reg(s, i, tmp); | |
99c475ab FB |
8936 | } else { |
8937 | /* push */ | |
b0109805 PB |
8938 | tmp = load_reg(s, i); |
8939 | gen_st32(tmp, addr, IS_USER(s)); | |
99c475ab | 8940 | } |
5899f386 | 8941 | /* advance to the next address. */ |
b0109805 | 8942 | tcg_gen_addi_i32(addr, addr, 4); |
99c475ab FB |
8943 | } |
8944 | } | |
a50f5b91 | 8945 | TCGV_UNUSED(tmp); |
99c475ab FB |
8946 | if (insn & (1 << 8)) { |
8947 | if (insn & (1 << 11)) { | |
8948 | /* pop pc */ | |
b0109805 | 8949 | tmp = gen_ld32(addr, IS_USER(s)); |
99c475ab FB |
8950 | /* don't set the pc until the rest of the instruction |
8951 | has completed */ | |
8952 | } else { | |
8953 | /* push lr */ | |
b0109805 PB |
8954 | tmp = load_reg(s, 14); |
8955 | gen_st32(tmp, addr, IS_USER(s)); | |
99c475ab | 8956 | } |
b0109805 | 8957 | tcg_gen_addi_i32(addr, addr, 4); |
99c475ab | 8958 | } |
5899f386 | 8959 | if ((insn & (1 << 11)) == 0) { |
b0109805 | 8960 | tcg_gen_addi_i32(addr, addr, -offset); |
5899f386 | 8961 | } |
99c475ab | 8962 | /* write back the new stack pointer */ |
b0109805 | 8963 | store_reg(s, 13, addr); |
99c475ab FB |
8964 | /* set the new PC value */ |
8965 | if ((insn & 0x0900) == 0x0900) | |
b0109805 | 8966 | gen_bx(s, tmp); |
99c475ab FB |
8967 | break; |
8968 | ||
9ee6e8bb PB |
8969 | case 1: case 3: case 9: case 11: /* czb */ |
8970 | rm = insn & 7; | |
d9ba4830 | 8971 | tmp = load_reg(s, rm); |
9ee6e8bb PB |
8972 | s->condlabel = gen_new_label(); |
8973 | s->condjmp = 1; | |
8974 | if (insn & (1 << 11)) | |
cb63669a | 8975 | tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, s->condlabel); |
9ee6e8bb | 8976 | else |
cb63669a | 8977 | tcg_gen_brcondi_i32(TCG_COND_NE, tmp, 0, s->condlabel); |
d9ba4830 | 8978 | dead_tmp(tmp); |
9ee6e8bb PB |
8979 | offset = ((insn & 0xf8) >> 2) | (insn & 0x200) >> 3; |
8980 | val = (uint32_t)s->pc + 2; | |
8981 | val += offset; | |
8982 | gen_jmp(s, val); | |
8983 | break; | |
8984 | ||
8985 | case 15: /* IT, nop-hint. */ | |
8986 | if ((insn & 0xf) == 0) { | |
8987 | gen_nop_hint(s, (insn >> 4) & 0xf); | |
8988 | break; | |
8989 | } | |
8990 | /* If Then. */ | |
8991 | s->condexec_cond = (insn >> 4) & 0xe; | |
8992 | s->condexec_mask = insn & 0x1f; | |
8993 | /* No actual code generated for this insn, just setup state. */ | |
8994 | break; | |
8995 | ||
06c949e6 | 8996 | case 0xe: /* bkpt */ |
bc4a0de0 | 8997 | gen_exception_insn(s, 2, EXCP_BKPT); |
06c949e6 PB |
8998 | break; |
8999 | ||
9ee6e8bb PB |
9000 | case 0xa: /* rev */ |
9001 | ARCH(6); | |
9002 | rn = (insn >> 3) & 0x7; | |
9003 | rd = insn & 0x7; | |
b0109805 | 9004 | tmp = load_reg(s, rn); |
9ee6e8bb | 9005 | switch ((insn >> 6) & 3) { |
66896cb8 | 9006 | case 0: tcg_gen_bswap32_i32(tmp, tmp); break; |
b0109805 PB |
9007 | case 1: gen_rev16(tmp); break; |
9008 | case 3: gen_revsh(tmp); break; | |
9ee6e8bb PB |
9009 | default: goto illegal_op; |
9010 | } | |
b0109805 | 9011 | store_reg(s, rd, tmp); |
9ee6e8bb PB |
9012 | break; |
9013 | ||
9014 | case 6: /* cps */ | |
9015 | ARCH(6); | |
9016 | if (IS_USER(s)) | |
9017 | break; | |
9018 | if (IS_M(env)) { | |
8984bd2e | 9019 | tmp = tcg_const_i32((insn & (1 << 4)) != 0); |
9ee6e8bb | 9020 | /* PRIMASK */ |
8984bd2e PB |
9021 | if (insn & 1) { |
9022 | addr = tcg_const_i32(16); | |
9023 | gen_helper_v7m_msr(cpu_env, addr, tmp); | |
b75263d6 | 9024 | tcg_temp_free_i32(addr); |
8984bd2e | 9025 | } |
9ee6e8bb | 9026 | /* FAULTMASK */ |
8984bd2e PB |
9027 | if (insn & 2) { |
9028 | addr = tcg_const_i32(17); | |
9029 | gen_helper_v7m_msr(cpu_env, addr, tmp); | |
b75263d6 | 9030 | tcg_temp_free_i32(addr); |
8984bd2e | 9031 | } |
b75263d6 | 9032 | tcg_temp_free_i32(tmp); |
9ee6e8bb PB |
9033 | gen_lookup_tb(s); |
9034 | } else { | |
9035 | if (insn & (1 << 4)) | |
9036 | shift = CPSR_A | CPSR_I | CPSR_F; | |
9037 | else | |
9038 | shift = 0; | |
fa26df03 | 9039 | gen_set_psr_im(s, ((insn & 7) << 6), 0, shift); |
9ee6e8bb PB |
9040 | } |
9041 | break; | |
9042 | ||
99c475ab FB |
9043 | default: |
9044 | goto undef; | |
9045 | } | |
9046 | break; | |
9047 | ||
9048 | case 12: | |
9049 | /* load/store multiple */ | |
9050 | rn = (insn >> 8) & 0x7; | |
b0109805 | 9051 | addr = load_reg(s, rn); |
99c475ab FB |
9052 | for (i = 0; i < 8; i++) { |
9053 | if (insn & (1 << i)) { | |
99c475ab FB |
9054 | if (insn & (1 << 11)) { |
9055 | /* load */ | |
b0109805 PB |
9056 | tmp = gen_ld32(addr, IS_USER(s)); |
9057 | store_reg(s, i, tmp); | |
99c475ab FB |
9058 | } else { |
9059 | /* store */ | |
b0109805 PB |
9060 | tmp = load_reg(s, i); |
9061 | gen_st32(tmp, addr, IS_USER(s)); | |
99c475ab | 9062 | } |
5899f386 | 9063 | /* advance to the next address */ |
b0109805 | 9064 | tcg_gen_addi_i32(addr, addr, 4); |
99c475ab FB |
9065 | } |
9066 | } | |
5899f386 | 9067 | /* Base register writeback. */ |
b0109805 PB |
9068 | if ((insn & (1 << rn)) == 0) { |
9069 | store_reg(s, rn, addr); | |
9070 | } else { | |
9071 | dead_tmp(addr); | |
9072 | } | |
99c475ab FB |
9073 | break; |
9074 | ||
9075 | case 13: | |
9076 | /* conditional branch or swi */ | |
9077 | cond = (insn >> 8) & 0xf; | |
9078 | if (cond == 0xe) | |
9079 | goto undef; | |
9080 | ||
9081 | if (cond == 0xf) { | |
9082 | /* swi */ | |
422ebf69 | 9083 | gen_set_pc_im(s->pc); |
9ee6e8bb | 9084 | s->is_jmp = DISAS_SWI; |
99c475ab FB |
9085 | break; |
9086 | } | |
9087 | /* generate a conditional jump to next instruction */ | |
e50e6a20 | 9088 | s->condlabel = gen_new_label(); |
d9ba4830 | 9089 | gen_test_cc(cond ^ 1, s->condlabel); |
e50e6a20 | 9090 | s->condjmp = 1; |
99c475ab FB |
9091 | |
9092 | /* jump to the offset */ | |
5899f386 | 9093 | val = (uint32_t)s->pc + 2; |
99c475ab | 9094 | offset = ((int32_t)insn << 24) >> 24; |
5899f386 | 9095 | val += offset << 1; |
8aaca4c0 | 9096 | gen_jmp(s, val); |
99c475ab FB |
9097 | break; |
9098 | ||
9099 | case 14: | |
358bf29e | 9100 | if (insn & (1 << 11)) { |
9ee6e8bb PB |
9101 | if (disas_thumb2_insn(env, s, insn)) |
9102 | goto undef32; | |
358bf29e PB |
9103 | break; |
9104 | } | |
9ee6e8bb | 9105 | /* unconditional branch */ |
99c475ab FB |
9106 | val = (uint32_t)s->pc; |
9107 | offset = ((int32_t)insn << 21) >> 21; | |
9108 | val += (offset << 1) + 2; | |
8aaca4c0 | 9109 | gen_jmp(s, val); |
99c475ab FB |
9110 | break; |
9111 | ||
9112 | case 15: | |
9ee6e8bb | 9113 | if (disas_thumb2_insn(env, s, insn)) |
6a0d8a1d | 9114 | goto undef32; |
9ee6e8bb | 9115 | break; |
99c475ab FB |
9116 | } |
9117 | return; | |
9ee6e8bb | 9118 | undef32: |
bc4a0de0 | 9119 | gen_exception_insn(s, 4, EXCP_UDEF); |
9ee6e8bb PB |
9120 | return; |
9121 | illegal_op: | |
99c475ab | 9122 | undef: |
bc4a0de0 | 9123 | gen_exception_insn(s, 2, EXCP_UDEF); |
99c475ab FB |
9124 | } |
9125 | ||
2c0262af FB |
9126 | /* generate intermediate code in gen_opc_buf and gen_opparam_buf for |
9127 | basic block 'tb'. If search_pc is TRUE, also generate PC | |
9128 | information for each intermediate instruction. */ | |
2cfc5f17 TS |
9129 | static inline void gen_intermediate_code_internal(CPUState *env, |
9130 | TranslationBlock *tb, | |
9131 | int search_pc) | |
2c0262af FB |
9132 | { |
9133 | DisasContext dc1, *dc = &dc1; | |
a1d1bb31 | 9134 | CPUBreakpoint *bp; |
2c0262af FB |
9135 | uint16_t *gen_opc_end; |
9136 | int j, lj; | |
0fa85d43 | 9137 | target_ulong pc_start; |
b5ff1b31 | 9138 | uint32_t next_page_start; |
2e70f6ef PB |
9139 | int num_insns; |
9140 | int max_insns; | |
3b46e624 | 9141 | |
2c0262af | 9142 | /* generate intermediate code */ |
b26eefb6 | 9143 | num_temps = 0; |
b26eefb6 | 9144 | |
0fa85d43 | 9145 | pc_start = tb->pc; |
3b46e624 | 9146 | |
2c0262af FB |
9147 | dc->tb = tb; |
9148 | ||
2c0262af | 9149 | gen_opc_end = gen_opc_buf + OPC_MAX_SIZE; |
2c0262af FB |
9150 | |
9151 | dc->is_jmp = DISAS_NEXT; | |
9152 | dc->pc = pc_start; | |
8aaca4c0 | 9153 | dc->singlestep_enabled = env->singlestep_enabled; |
e50e6a20 | 9154 | dc->condjmp = 0; |
7204ab88 | 9155 | dc->thumb = ARM_TBFLAG_THUMB(tb->flags); |
98eac7ca PM |
9156 | dc->condexec_mask = (ARM_TBFLAG_CONDEXEC(tb->flags) & 0xf) << 1; |
9157 | dc->condexec_cond = ARM_TBFLAG_CONDEXEC(tb->flags) >> 4; | |
b5ff1b31 | 9158 | #if !defined(CONFIG_USER_ONLY) |
61f74d6a | 9159 | dc->user = (ARM_TBFLAG_PRIV(tb->flags) == 0); |
b5ff1b31 | 9160 | #endif |
5df8bac1 | 9161 | dc->vfp_enabled = ARM_TBFLAG_VFPEN(tb->flags); |
69d1fc22 PM |
9162 | dc->vec_len = ARM_TBFLAG_VECLEN(tb->flags); |
9163 | dc->vec_stride = ARM_TBFLAG_VECSTRIDE(tb->flags); | |
a7812ae4 PB |
9164 | cpu_F0s = tcg_temp_new_i32(); |
9165 | cpu_F1s = tcg_temp_new_i32(); | |
9166 | cpu_F0d = tcg_temp_new_i64(); | |
9167 | cpu_F1d = tcg_temp_new_i64(); | |
ad69471c PB |
9168 | cpu_V0 = cpu_F0d; |
9169 | cpu_V1 = cpu_F1d; | |
e677137d | 9170 | /* FIXME: cpu_M0 can probably be the same as cpu_V0. */ |
a7812ae4 | 9171 | cpu_M0 = tcg_temp_new_i64(); |
b5ff1b31 | 9172 | next_page_start = (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE; |
2c0262af | 9173 | lj = -1; |
2e70f6ef PB |
9174 | num_insns = 0; |
9175 | max_insns = tb->cflags & CF_COUNT_MASK; | |
9176 | if (max_insns == 0) | |
9177 | max_insns = CF_COUNT_MASK; | |
9178 | ||
9179 | gen_icount_start(); | |
e12ce78d PM |
9180 | |
9181 | /* A note on handling of the condexec (IT) bits: | |
9182 | * | |
9183 | * We want to avoid the overhead of having to write the updated condexec | |
9184 | * bits back to the CPUState for every instruction in an IT block. So: | |
9185 | * (1) if the condexec bits are not already zero then we write | |
9186 | * zero back into the CPUState now. This avoids complications trying | |
9187 | * to do it at the end of the block. (For example if we don't do this | |
9188 | * it's hard to identify whether we can safely skip writing condexec | |
9189 | * at the end of the TB, which we definitely want to do for the case | |
9190 | * where a TB doesn't do anything with the IT state at all.) | |
9191 | * (2) if we are going to leave the TB then we call gen_set_condexec() | |
9192 | * which will write the correct value into CPUState if zero is wrong. | |
9193 | * This is done both for leaving the TB at the end, and for leaving | |
9194 | * it because of an exception we know will happen, which is done in | |
9195 | * gen_exception_insn(). The latter is necessary because we need to | |
9196 | * leave the TB with the PC/IT state just prior to execution of the | |
9197 | * instruction which caused the exception. | |
9198 | * (3) if we leave the TB unexpectedly (eg a data abort on a load) | |
9199 | * then the CPUState will be wrong and we need to reset it. | |
9200 | * This is handled in the same way as restoration of the | |
9201 | * PC in these situations: we will be called again with search_pc=1 | |
9202 | * and generate a mapping of the condexec bits for each PC in | |
9203 | * gen_opc_condexec_bits[]. gen_pc_load[] then uses this to restore | |
9204 | * the condexec bits. | |
9205 | * | |
9206 | * Note that there are no instructions which can read the condexec | |
9207 | * bits, and none which can write non-static values to them, so | |
9208 | * we don't need to care about whether CPUState is correct in the | |
9209 | * middle of a TB. | |
9210 | */ | |
9211 | ||
9ee6e8bb PB |
9212 | /* Reset the conditional execution bits immediately. This avoids |
9213 | complications trying to do it at the end of the block. */ | |
98eac7ca | 9214 | if (dc->condexec_mask || dc->condexec_cond) |
8f01245e PB |
9215 | { |
9216 | TCGv tmp = new_tmp(); | |
9217 | tcg_gen_movi_i32(tmp, 0); | |
d9ba4830 | 9218 | store_cpu_field(tmp, condexec_bits); |
8f01245e | 9219 | } |
2c0262af | 9220 | do { |
fbb4a2e3 PB |
9221 | #ifdef CONFIG_USER_ONLY |
9222 | /* Intercept jump to the magic kernel page. */ | |
9223 | if (dc->pc >= 0xffff0000) { | |
9224 | /* We always get here via a jump, so know we are not in a | |
9225 | conditional execution block. */ | |
9226 | gen_exception(EXCP_KERNEL_TRAP); | |
9227 | dc->is_jmp = DISAS_UPDATE; | |
9228 | break; | |
9229 | } | |
9230 | #else | |
9ee6e8bb PB |
9231 | if (dc->pc >= 0xfffffff0 && IS_M(env)) { |
9232 | /* We always get here via a jump, so know we are not in a | |
9233 | conditional execution block. */ | |
d9ba4830 | 9234 | gen_exception(EXCP_EXCEPTION_EXIT); |
d60bb01c PB |
9235 | dc->is_jmp = DISAS_UPDATE; |
9236 | break; | |
9ee6e8bb PB |
9237 | } |
9238 | #endif | |
9239 | ||
72cf2d4f BS |
9240 | if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) { |
9241 | QTAILQ_FOREACH(bp, &env->breakpoints, entry) { | |
a1d1bb31 | 9242 | if (bp->pc == dc->pc) { |
bc4a0de0 | 9243 | gen_exception_insn(dc, 0, EXCP_DEBUG); |
9ee6e8bb PB |
9244 | /* Advance PC so that clearing the breakpoint will |
9245 | invalidate this TB. */ | |
9246 | dc->pc += 2; | |
9247 | goto done_generating; | |
1fddef4b FB |
9248 | break; |
9249 | } | |
9250 | } | |
9251 | } | |
2c0262af FB |
9252 | if (search_pc) { |
9253 | j = gen_opc_ptr - gen_opc_buf; | |
9254 | if (lj < j) { | |
9255 | lj++; | |
9256 | while (lj < j) | |
9257 | gen_opc_instr_start[lj++] = 0; | |
9258 | } | |
0fa85d43 | 9259 | gen_opc_pc[lj] = dc->pc; |
e12ce78d | 9260 | gen_opc_condexec_bits[lj] = (dc->condexec_cond << 4) | (dc->condexec_mask >> 1); |
2c0262af | 9261 | gen_opc_instr_start[lj] = 1; |
2e70f6ef | 9262 | gen_opc_icount[lj] = num_insns; |
2c0262af | 9263 | } |
e50e6a20 | 9264 | |
2e70f6ef PB |
9265 | if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO)) |
9266 | gen_io_start(); | |
9267 | ||
5642463a PM |
9268 | if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP))) { |
9269 | tcg_gen_debug_insn_start(dc->pc); | |
9270 | } | |
9271 | ||
7204ab88 | 9272 | if (dc->thumb) { |
9ee6e8bb PB |
9273 | disas_thumb_insn(env, dc); |
9274 | if (dc->condexec_mask) { | |
9275 | dc->condexec_cond = (dc->condexec_cond & 0xe) | |
9276 | | ((dc->condexec_mask >> 4) & 1); | |
9277 | dc->condexec_mask = (dc->condexec_mask << 1) & 0x1f; | |
9278 | if (dc->condexec_mask == 0) { | |
9279 | dc->condexec_cond = 0; | |
9280 | } | |
9281 | } | |
9282 | } else { | |
9283 | disas_arm_insn(env, dc); | |
9284 | } | |
b26eefb6 PB |
9285 | if (num_temps) { |
9286 | fprintf(stderr, "Internal resource leak before %08x\n", dc->pc); | |
9287 | num_temps = 0; | |
9288 | } | |
e50e6a20 FB |
9289 | |
9290 | if (dc->condjmp && !dc->is_jmp) { | |
9291 | gen_set_label(dc->condlabel); | |
9292 | dc->condjmp = 0; | |
9293 | } | |
aaf2d97d | 9294 | /* Translation stops when a conditional branch is encountered. |
e50e6a20 | 9295 | * Otherwise the subsequent code could get translated several times. |
b5ff1b31 | 9296 | * Also stop translation when a page boundary is reached. This |
bf20dc07 | 9297 | * ensures prefetch aborts occur at the right place. */ |
2e70f6ef | 9298 | num_insns ++; |
1fddef4b FB |
9299 | } while (!dc->is_jmp && gen_opc_ptr < gen_opc_end && |
9300 | !env->singlestep_enabled && | |
1b530a6d | 9301 | !singlestep && |
2e70f6ef PB |
9302 | dc->pc < next_page_start && |
9303 | num_insns < max_insns); | |
9304 | ||
9305 | if (tb->cflags & CF_LAST_IO) { | |
9306 | if (dc->condjmp) { | |
9307 | /* FIXME: This can theoretically happen with self-modifying | |
9308 | code. */ | |
9309 | cpu_abort(env, "IO on conditional branch instruction"); | |
9310 | } | |
9311 | gen_io_end(); | |
9312 | } | |
9ee6e8bb | 9313 | |
b5ff1b31 | 9314 | /* At this stage dc->condjmp will only be set when the skipped |
9ee6e8bb PB |
9315 | instruction was a conditional branch or trap, and the PC has |
9316 | already been written. */ | |
551bd27f | 9317 | if (unlikely(env->singlestep_enabled)) { |
8aaca4c0 | 9318 | /* Make sure the pc is updated, and raise a debug exception. */ |
e50e6a20 | 9319 | if (dc->condjmp) { |
9ee6e8bb PB |
9320 | gen_set_condexec(dc); |
9321 | if (dc->is_jmp == DISAS_SWI) { | |
d9ba4830 | 9322 | gen_exception(EXCP_SWI); |
9ee6e8bb | 9323 | } else { |
d9ba4830 | 9324 | gen_exception(EXCP_DEBUG); |
9ee6e8bb | 9325 | } |
e50e6a20 FB |
9326 | gen_set_label(dc->condlabel); |
9327 | } | |
9328 | if (dc->condjmp || !dc->is_jmp) { | |
5e3f878a | 9329 | gen_set_pc_im(dc->pc); |
e50e6a20 | 9330 | dc->condjmp = 0; |
8aaca4c0 | 9331 | } |
9ee6e8bb PB |
9332 | gen_set_condexec(dc); |
9333 | if (dc->is_jmp == DISAS_SWI && !dc->condjmp) { | |
d9ba4830 | 9334 | gen_exception(EXCP_SWI); |
9ee6e8bb PB |
9335 | } else { |
9336 | /* FIXME: Single stepping a WFI insn will not halt | |
9337 | the CPU. */ | |
d9ba4830 | 9338 | gen_exception(EXCP_DEBUG); |
9ee6e8bb | 9339 | } |
8aaca4c0 | 9340 | } else { |
9ee6e8bb PB |
9341 | /* While branches must always occur at the end of an IT block, |
9342 | there are a few other things that can cause us to terminate | |
9343 | the TB in the middel of an IT block: | |
9344 | - Exception generating instructions (bkpt, swi, undefined). | |
9345 | - Page boundaries. | |
9346 | - Hardware watchpoints. | |
9347 | Hardware breakpoints have already been handled and skip this code. | |
9348 | */ | |
9349 | gen_set_condexec(dc); | |
8aaca4c0 | 9350 | switch(dc->is_jmp) { |
8aaca4c0 | 9351 | case DISAS_NEXT: |
6e256c93 | 9352 | gen_goto_tb(dc, 1, dc->pc); |
8aaca4c0 FB |
9353 | break; |
9354 | default: | |
9355 | case DISAS_JUMP: | |
9356 | case DISAS_UPDATE: | |
9357 | /* indicate that the hash table must be used to find the next TB */ | |
57fec1fe | 9358 | tcg_gen_exit_tb(0); |
8aaca4c0 FB |
9359 | break; |
9360 | case DISAS_TB_JUMP: | |
9361 | /* nothing more to generate */ | |
9362 | break; | |
9ee6e8bb | 9363 | case DISAS_WFI: |
d9ba4830 | 9364 | gen_helper_wfi(); |
9ee6e8bb PB |
9365 | break; |
9366 | case DISAS_SWI: | |
d9ba4830 | 9367 | gen_exception(EXCP_SWI); |
9ee6e8bb | 9368 | break; |
8aaca4c0 | 9369 | } |
e50e6a20 FB |
9370 | if (dc->condjmp) { |
9371 | gen_set_label(dc->condlabel); | |
9ee6e8bb | 9372 | gen_set_condexec(dc); |
6e256c93 | 9373 | gen_goto_tb(dc, 1, dc->pc); |
e50e6a20 FB |
9374 | dc->condjmp = 0; |
9375 | } | |
2c0262af | 9376 | } |
2e70f6ef | 9377 | |
9ee6e8bb | 9378 | done_generating: |
2e70f6ef | 9379 | gen_icount_end(tb, num_insns); |
2c0262af FB |
9380 | *gen_opc_ptr = INDEX_op_end; |
9381 | ||
9382 | #ifdef DEBUG_DISAS | |
8fec2b8c | 9383 | if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) { |
93fcfe39 AL |
9384 | qemu_log("----------------\n"); |
9385 | qemu_log("IN: %s\n", lookup_symbol(pc_start)); | |
7204ab88 | 9386 | log_target_disas(pc_start, dc->pc - pc_start, dc->thumb); |
93fcfe39 | 9387 | qemu_log("\n"); |
2c0262af FB |
9388 | } |
9389 | #endif | |
b5ff1b31 FB |
9390 | if (search_pc) { |
9391 | j = gen_opc_ptr - gen_opc_buf; | |
9392 | lj++; | |
9393 | while (lj <= j) | |
9394 | gen_opc_instr_start[lj++] = 0; | |
b5ff1b31 | 9395 | } else { |
2c0262af | 9396 | tb->size = dc->pc - pc_start; |
2e70f6ef | 9397 | tb->icount = num_insns; |
b5ff1b31 | 9398 | } |
2c0262af FB |
9399 | } |
9400 | ||
2cfc5f17 | 9401 | void gen_intermediate_code(CPUState *env, TranslationBlock *tb) |
2c0262af | 9402 | { |
2cfc5f17 | 9403 | gen_intermediate_code_internal(env, tb, 0); |
2c0262af FB |
9404 | } |
9405 | ||
2cfc5f17 | 9406 | void gen_intermediate_code_pc(CPUState *env, TranslationBlock *tb) |
2c0262af | 9407 | { |
2cfc5f17 | 9408 | gen_intermediate_code_internal(env, tb, 1); |
2c0262af FB |
9409 | } |
9410 | ||
b5ff1b31 FB |
9411 | static const char *cpu_mode_names[16] = { |
9412 | "usr", "fiq", "irq", "svc", "???", "???", "???", "abt", | |
9413 | "???", "???", "???", "und", "???", "???", "???", "sys" | |
9414 | }; | |
9ee6e8bb | 9415 | |
9a78eead | 9416 | void cpu_dump_state(CPUState *env, FILE *f, fprintf_function cpu_fprintf, |
7fe48483 | 9417 | int flags) |
2c0262af FB |
9418 | { |
9419 | int i; | |
06e80fc9 | 9420 | #if 0 |
bc380d17 | 9421 | union { |
b7bcbe95 FB |
9422 | uint32_t i; |
9423 | float s; | |
9424 | } s0, s1; | |
9425 | CPU_DoubleU d; | |
a94a6abf PB |
9426 | /* ??? This assumes float64 and double have the same layout. |
9427 | Oh well, it's only debug dumps. */ | |
9428 | union { | |
9429 | float64 f64; | |
9430 | double d; | |
9431 | } d0; | |
06e80fc9 | 9432 | #endif |
b5ff1b31 | 9433 | uint32_t psr; |
2c0262af FB |
9434 | |
9435 | for(i=0;i<16;i++) { | |
7fe48483 | 9436 | cpu_fprintf(f, "R%02d=%08x", i, env->regs[i]); |
2c0262af | 9437 | if ((i % 4) == 3) |
7fe48483 | 9438 | cpu_fprintf(f, "\n"); |
2c0262af | 9439 | else |
7fe48483 | 9440 | cpu_fprintf(f, " "); |
2c0262af | 9441 | } |
b5ff1b31 | 9442 | psr = cpsr_read(env); |
687fa640 TS |
9443 | cpu_fprintf(f, "PSR=%08x %c%c%c%c %c %s%d\n", |
9444 | psr, | |
b5ff1b31 FB |
9445 | psr & (1 << 31) ? 'N' : '-', |
9446 | psr & (1 << 30) ? 'Z' : '-', | |
9447 | psr & (1 << 29) ? 'C' : '-', | |
9448 | psr & (1 << 28) ? 'V' : '-', | |
5fafdf24 | 9449 | psr & CPSR_T ? 'T' : 'A', |
b5ff1b31 | 9450 | cpu_mode_names[psr & 0xf], (psr & 0x10) ? 32 : 26); |
b7bcbe95 | 9451 | |
5e3f878a | 9452 | #if 0 |
b7bcbe95 | 9453 | for (i = 0; i < 16; i++) { |
8e96005d FB |
9454 | d.d = env->vfp.regs[i]; |
9455 | s0.i = d.l.lower; | |
9456 | s1.i = d.l.upper; | |
a94a6abf PB |
9457 | d0.f64 = d.d; |
9458 | cpu_fprintf(f, "s%02d=%08x(%8g) s%02d=%08x(%8g) d%02d=%08x%08x(%8g)\n", | |
b7bcbe95 | 9459 | i * 2, (int)s0.i, s0.s, |
a94a6abf | 9460 | i * 2 + 1, (int)s1.i, s1.s, |
b7bcbe95 | 9461 | i, (int)(uint32_t)d.l.upper, (int)(uint32_t)d.l.lower, |
a94a6abf | 9462 | d0.d); |
b7bcbe95 | 9463 | } |
40f137e1 | 9464 | cpu_fprintf(f, "FPSCR: %08x\n", (int)env->vfp.xregs[ARM_VFP_FPSCR]); |
5e3f878a | 9465 | #endif |
2c0262af | 9466 | } |
a6b025d3 | 9467 | |
d2856f1a AJ |
9468 | void gen_pc_load(CPUState *env, TranslationBlock *tb, |
9469 | unsigned long searched_pc, int pc_pos, void *puc) | |
9470 | { | |
9471 | env->regs[15] = gen_opc_pc[pc_pos]; | |
e12ce78d | 9472 | env->condexec_bits = gen_opc_condexec_bits[pc_pos]; |
d2856f1a | 9473 | } |