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f570c61e AG |
1 | #ifndef TARGET_ARM_TRANSLATE_H |
2 | #define TARGET_ARM_TRANSLATE_H | |
3 | ||
4 | /* internal defines */ | |
5 | typedef struct DisasContext { | |
6 | target_ulong pc; | |
14ade10f | 7 | uint32_t insn; |
f570c61e AG |
8 | int is_jmp; |
9 | /* Nonzero if this instruction has been conditionally skipped. */ | |
10 | int condjmp; | |
11 | /* The label that will be jumped to when the instruction is skipped. */ | |
42a268c2 | 12 | TCGLabel *condlabel; |
f570c61e AG |
13 | /* Thumb-2 conditional execution bits. */ |
14 | int condexec_mask; | |
15 | int condexec_cond; | |
16 | struct TranslationBlock *tb; | |
17 | int singlestep_enabled; | |
18 | int thumb; | |
f9fd40eb | 19 | int sctlr_b; |
dacf0a2f | 20 | TCGMemOp be_data; |
f570c61e AG |
21 | #if !defined(CONFIG_USER_ONLY) |
22 | int user; | |
23 | #endif | |
c1e37810 | 24 | ARMMMUIdx mmu_idx; /* MMU index to use for normal loads/stores */ |
3f342b9e | 25 | bool ns; /* Use non-secure CPREG bank on access */ |
9dbbc748 | 26 | int fp_excp_el; /* FP exception EL or 0 if enabled */ |
cef9ee70 SS |
27 | /* Flag indicating that exceptions from secure mode are routed to EL3. */ |
28 | bool secure_routed_to_el3; | |
8c6afa6a | 29 | bool vfp_enabled; /* FP enabled via FPSCR.EN */ |
f570c61e AG |
30 | int vec_len; |
31 | int vec_stride; | |
d4a2dc67 PM |
32 | /* Immediate value in AArch32 SVC insn; must be set if is_jmp == DISAS_SWI |
33 | * so that top level loop can generate correct syndrome information. | |
34 | */ | |
35 | uint32_t svc_imm; | |
3926cc84 | 36 | int aarch64; |
dcbff19b | 37 | int current_el; |
60322b39 | 38 | GHashTable *cp_regs; |
a984e42c | 39 | uint64_t features; /* CPU features bits */ |
90e49638 PM |
40 | /* Because unallocated encodings generate different exception syndrome |
41 | * information from traps due to FP being disabled, we can't do a single | |
42 | * "is fp access disabled" check at a high level in the decode tree. | |
43 | * To help in catching bugs where the access check was forgotten in some | |
44 | * code path, we set this flag when the access check is done, and assert | |
45 | * that it is set at the point where we actually touch the FP regs. | |
46 | */ | |
47 | bool fp_access_checked; | |
7ea47fe7 PM |
48 | /* ARMv8 single-step state (this is distinct from the QEMU gdbstub |
49 | * single-step support). | |
50 | */ | |
51 | bool ss_active; | |
52 | bool pstate_ss; | |
53 | /* True if the insn just emitted was a load-exclusive instruction | |
54 | * (necessary for syndrome information for single step exceptions), | |
55 | * ie A64 LDX*, LDAX*, A32/T32 LDREX*, LDAEX*. | |
56 | */ | |
57 | bool is_ldex; | |
58 | /* True if a single-step exception will be taken to the current EL */ | |
59 | bool ss_same_el; | |
c0f4af17 PM |
60 | /* Bottom two bits of XScale c15_cpar coprocessor access control reg */ |
61 | int c15_cpar; | |
aaa1f954 EI |
62 | /* TCG op index of the current insn_start. */ |
63 | int insn_start_idx; | |
11e169de AG |
64 | #define TMP_A64_MAX 16 |
65 | int tmp_a64_count; | |
66 | TCGv_i64 tmp_a64[TMP_A64_MAX]; | |
f570c61e AG |
67 | } DisasContext; |
68 | ||
6c2c63d3 RH |
69 | typedef struct DisasCompare { |
70 | TCGCond cond; | |
71 | TCGv_i32 value; | |
72 | bool value_global; | |
73 | } DisasCompare; | |
74 | ||
78bcaa3e | 75 | /* Share the TCG temporaries common between 32 and 64 bit modes. */ |
1bcea73e | 76 | extern TCGv_env cpu_env; |
78bcaa3e RH |
77 | extern TCGv_i32 cpu_NF, cpu_ZF, cpu_CF, cpu_VF; |
78 | extern TCGv_i64 cpu_exclusive_addr; | |
79 | extern TCGv_i64 cpu_exclusive_val; | |
80 | #ifdef CONFIG_USER_ONLY | |
81 | extern TCGv_i64 cpu_exclusive_test; | |
82 | extern TCGv_i32 cpu_exclusive_info; | |
83 | #endif | |
3407ad0e | 84 | |
a984e42c PM |
85 | static inline int arm_dc_feature(DisasContext *dc, int feature) |
86 | { | |
87 | return (dc->features & (1ULL << feature)) != 0; | |
88 | } | |
89 | ||
9d4c4e87 EI |
90 | static inline int get_mem_index(DisasContext *s) |
91 | { | |
c1e37810 | 92 | return s->mmu_idx; |
9d4c4e87 EI |
93 | } |
94 | ||
73710361 GB |
95 | /* Function used to determine the target exception EL when otherwise not known |
96 | * or default. | |
97 | */ | |
98 | static inline int default_exception_el(DisasContext *s) | |
99 | { | |
100 | /* If we are coming from secure EL0 in a system with a 32-bit EL3, then | |
101 | * there is no secure EL1, so we route exceptions to EL3. Otherwise, | |
102 | * exceptions can only be routed to ELs above 1, so we target the higher of | |
103 | * 1 or the current EL. | |
104 | */ | |
cef9ee70 | 105 | return (s->mmu_idx == ARMMMUIdx_S1SE0 && s->secure_routed_to_el3) |
73710361 GB |
106 | ? 3 : MAX(1, s->current_el); |
107 | } | |
108 | ||
40f860cd PM |
109 | /* target-specific extra values for is_jmp */ |
110 | /* These instructions trap after executing, so the A32/T32 decoder must | |
111 | * defer them until after the conditional execution state has been updated. | |
112 | * WFI also needs special handling when single-stepping. | |
113 | */ | |
114 | #define DISAS_WFI 4 | |
115 | #define DISAS_SWI 5 | |
116 | /* For instructions which unconditionally cause an exception we can skip | |
117 | * emitting unreachable code at the end of the TB in the A64 decoder | |
118 | */ | |
119 | #define DISAS_EXC 6 | |
72c1d3af PM |
120 | /* WFE */ |
121 | #define DISAS_WFE 7 | |
37e6456e PM |
122 | #define DISAS_HVC 8 |
123 | #define DISAS_SMC 9 | |
049e24a1 | 124 | #define DISAS_YIELD 10 |
40f860cd | 125 | |
14ade10f AG |
126 | #ifdef TARGET_AARCH64 |
127 | void a64_translate_init(void); | |
4e5e1215 | 128 | void gen_intermediate_code_a64(ARMCPU *cpu, TranslationBlock *tb); |
14ade10f | 129 | void gen_a64_set_pc_im(uint64_t val); |
17731115 PM |
130 | void aarch64_cpu_dump_state(CPUState *cs, FILE *f, |
131 | fprintf_function cpu_fprintf, int flags); | |
14ade10f AG |
132 | #else |
133 | static inline void a64_translate_init(void) | |
134 | { | |
135 | } | |
136 | ||
4e5e1215 | 137 | static inline void gen_intermediate_code_a64(ARMCPU *cpu, TranslationBlock *tb) |
14ade10f AG |
138 | { |
139 | } | |
140 | ||
141 | static inline void gen_a64_set_pc_im(uint64_t val) | |
142 | { | |
143 | } | |
17731115 PM |
144 | |
145 | static inline void aarch64_cpu_dump_state(CPUState *cs, FILE *f, | |
146 | fprintf_function cpu_fprintf, | |
147 | int flags) | |
148 | { | |
149 | } | |
14ade10f AG |
150 | #endif |
151 | ||
6c2c63d3 RH |
152 | void arm_test_cc(DisasCompare *cmp, int cc); |
153 | void arm_free_cc(DisasCompare *cmp); | |
154 | void arm_jump_cc(DisasCompare *cmp, TCGLabel *label); | |
42a268c2 | 155 | void arm_gen_test_cc(int cc, TCGLabel *label); |
39fb730a | 156 | |
f570c61e | 157 | #endif /* TARGET_ARM_TRANSLATE_H */ |