projects / mirror_qemu.git / blame
| Commit | Line | Data |
|---|---|---|
| f570c61e AG |
1 | #ifndef TARGET_ARM_TRANSLATE_H |
| 2 | #define TARGET_ARM_TRANSLATE_H | |
| 3 | ||
| 4 | /* internal defines */ | |
| 5 | typedef struct DisasContext { | |
| 6 | target_ulong pc; | |
| 14ade10f | 7 | uint32_t insn; |
| f570c61e AG |
8 | int is_jmp; |
| 9 | /* Nonzero if this instruction has been conditionally skipped. */ | |
| 10 | int condjmp; | |
| 11 | /* The label that will be jumped to when the instruction is skipped. */ | |
| 12 | int condlabel; | |
| 13 | /* Thumb-2 conditional execution bits. */ | |
| 14 | int condexec_mask; | |
| 15 | int condexec_cond; | |
| 16 | struct TranslationBlock *tb; | |
| 17 | int singlestep_enabled; | |
| 18 | int thumb; | |
| 19 | int bswap_code; | |
| 20 | #if !defined(CONFIG_USER_ONLY) | |
| 21 | int user; | |
| 22 | #endif | |
| 23 | int vfp_enabled; | |
| 24 | int vec_len; | |
| 25 | int vec_stride; | |
| 3926cc84 | 26 | int aarch64; |
| f570c61e AG |
27 | } DisasContext; |
| 28 | ||
| 3407ad0e AG |
29 | extern TCGv_ptr cpu_env; |
| 30 | ||
| 40f860cd PM |
31 | /* target-specific extra values for is_jmp */ |
| 32 | /* These instructions trap after executing, so the A32/T32 decoder must | |
| 33 | * defer them until after the conditional execution state has been updated. | |
| 34 | * WFI also needs special handling when single-stepping. | |
| 35 | */ | |
| 36 | #define DISAS_WFI 4 | |
| 37 | #define DISAS_SWI 5 | |
| 38 | /* For instructions which unconditionally cause an exception we can skip | |
| 39 | * emitting unreachable code at the end of the TB in the A64 decoder | |
| 40 | */ | |
| 41 | #define DISAS_EXC 6 | |
| 42 | ||
| 14ade10f AG |
43 | #ifdef TARGET_AARCH64 |
| 44 | void a64_translate_init(void); | |
| 40f860cd PM |
45 | void gen_intermediate_code_internal_a64(ARMCPU *cpu, |
| 46 | TranslationBlock *tb, | |
| 47 | bool search_pc); | |
| 14ade10f AG |
48 | void gen_a64_set_pc_im(uint64_t val); |
| 49 | #else | |
| 50 | static inline void a64_translate_init(void) | |
| 51 | { | |
| 52 | } | |
| 53 | ||
| 40f860cd PM |
54 | static inline void gen_intermediate_code_internal_a64(ARMCPU *cpu, |
| 55 | TranslationBlock *tb, | |
| 56 | bool search_pc) | |
| 14ade10f AG |
57 | { |
| 58 | } | |
| 59 | ||
| 60 | static inline void gen_a64_set_pc_im(uint64_t val) | |
| 61 | { | |
| 62 | } | |
| 63 | #endif | |
| 64 | ||
| f570c61e | 65 | #endif /* TARGET_ARM_TRANSLATE_H */ |