[mirror_qemu.git] / target-arm / translate.h

#ifndef TARGET_ARM_TRANSLATE_H
#define TARGET_ARM_TRANSLATE_H

/* internal defines */
typedef struct DisasContext {
    target_ulong pc;
    uint32_t insn;
    int is_jmp;
    /* Nonzero if this instruction has been conditionally skipped.  */
    int condjmp;
    /* The label that will be jumped to when the instruction is skipped.  */
    int condlabel;
    /* Thumb-2 conditional execution bits.  */
    int condexec_mask;
    int condexec_cond;
    struct TranslationBlock *tb;
    int singlestep_enabled;
    int thumb;
    int bswap_code;
#if !defined(CONFIG_USER_ONLY)
    int user;
#endif
    int vfp_enabled;
    int vec_len;
    int vec_stride;
    int aarch64;
    int current_pl;
    GHashTable *cp_regs;
    uint64_t features; /* CPU features bits */
#define TMP_A64_MAX 16
    int tmp_a64_count;
    TCGv_i64 tmp_a64[TMP_A64_MAX];
} DisasContext;

extern TCGv_ptr cpu_env;

static inline int arm_dc_feature(DisasContext *dc, int feature)
{
    return (dc->features & (1ULL << feature)) != 0;
}

/* target-specific extra values for is_jmp */
/* These instructions trap after executing, so the A32/T32 decoder must
 * defer them until after the conditional execution state has been updated.
 * WFI also needs special handling when single-stepping.
 */
#define DISAS_WFI 4
#define DISAS_SWI 5
/* For instructions which unconditionally cause an exception we can skip
 * emitting unreachable code at the end of the TB in the A64 decoder
 */
#define DISAS_EXC 6
/* WFE */
#define DISAS_WFE 7

#ifdef TARGET_AARCH64
void a64_translate_init(void);
void gen_intermediate_code_internal_a64(ARMCPU *cpu,
                                        TranslationBlock *tb,
                                        bool search_pc);
void gen_a64_set_pc_im(uint64_t val);
#else
static inline void a64_translate_init(void)
{
}

static inline void gen_intermediate_code_internal_a64(ARMCPU *cpu,
                                                      TranslationBlock *tb,
                                                      bool search_pc)
{
}

static inline void gen_a64_set_pc_im(uint64_t val)
{
}
#endif

void arm_gen_test_cc(int cc, int label);

#endif /* TARGET_ARM_TRANSLATE_H */
Commit	Line	Data
f570c61e AG	1	#ifndef TARGET_ARM_TRANSLATE_H
	2	#define TARGET_ARM_TRANSLATE_H
	3
	4	/* internal defines */
	5	typedef struct DisasContext {
	6	target_ulong pc;
14ade10f	7	uint32_t insn;
f570c61e AG	8	int is_jmp;
	9	/* Nonzero if this instruction has been conditionally skipped. */
	10	int condjmp;
	11	/* The label that will be jumped to when the instruction is skipped. */
	12	int condlabel;
	13	/* Thumb-2 conditional execution bits. */
	14	int condexec_mask;
	15	int condexec_cond;
	16	struct TranslationBlock *tb;
	17	int singlestep_enabled;
	18	int thumb;
	19	int bswap_code;
	20	#if !defined(CONFIG_USER_ONLY)
	21	int user;
	22	#endif
	23	int vfp_enabled;
	24	int vec_len;
	25	int vec_stride;
3926cc84	26	int aarch64;
60322b39 PM	27	int current_pl;
60322b39 PM	28	GHashTable *cp_regs;
a984e42c	29	uint64_t features; /* CPU features bits */
11e169de AG	30	#define TMP_A64_MAX 16
	31	int tmp_a64_count;
	32	TCGv_i64 tmp_a64[TMP_A64_MAX];
f570c61e AG	33	} DisasContext;
f570c61e AG	34
3407ad0e AG	35	extern TCGv_ptr cpu_env;
3407ad0e AG	36
a984e42c PM	37	static inline int arm_dc_feature(DisasContext *dc, int feature)
	38	{
	39	return (dc->features & (1ULL << feature)) != 0;
	40	}
	41
40f860cd PM	42	/* target-specific extra values for is_jmp */
	43	/* These instructions trap after executing, so the A32/T32 decoder must
	44	* defer them until after the conditional execution state has been updated.
	45	* WFI also needs special handling when single-stepping.
	46	*/
	47	#define DISAS_WFI 4
	48	#define DISAS_SWI 5
	49	/* For instructions which unconditionally cause an exception we can skip
	50	* emitting unreachable code at the end of the TB in the A64 decoder
	51	*/
	52	#define DISAS_EXC 6
72c1d3af PM	53	/* WFE */
72c1d3af PM	54	#define DISAS_WFE 7
40f860cd	55
14ade10f AG	56	#ifdef TARGET_AARCH64
14ade10f AG	57	void a64_translate_init(void);
40f860cd PM	58	void gen_intermediate_code_internal_a64(ARMCPU *cpu,
	59	TranslationBlock *tb,
	60	bool search_pc);
14ade10f AG	61	void gen_a64_set_pc_im(uint64_t val);
	62	#else
	63	static inline void a64_translate_init(void)
	64	{
	65	}
	66
40f860cd PM	67	static inline void gen_intermediate_code_internal_a64(ARMCPU *cpu,
	68	TranslationBlock *tb,
	69	bool search_pc)
14ade10f AG	70	{
	71	}
	72
	73	static inline void gen_a64_set_pc_im(uint64_t val)
	74	{
	75	}
	76	#endif
	77
39fb730a AG	78	void arm_gen_test_cc(int cc, int label);
39fb730a AG	79
f570c61e	80	#endif /* TARGET_ARM_TRANSLATE_H */