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Merge branch 'tcg-next' of git://github.com/rth7680/qemu
[mirror_qemu.git] / target-cris / cpu-qom.h
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1/*
2 * QEMU CRIS CPU
3 *
4 * Copyright (c) 2012 SUSE LINUX Products GmbH
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2.1 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see
18 * <http://www.gnu.org/licenses/lgpl-2.1.html>
19 */
20#ifndef QEMU_CRIS_CPU_QOM_H
21#define QEMU_CRIS_CPU_QOM_H
22
14cccb61 23#include "qom/cpu.h"
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24
25#define TYPE_CRIS_CPU "cris-cpu"
26
27#define CRIS_CPU_CLASS(klass) \
28 OBJECT_CLASS_CHECK(CRISCPUClass, (klass), TYPE_CRIS_CPU)
29#define CRIS_CPU(obj) \
30 OBJECT_CHECK(CRISCPU, (obj), TYPE_CRIS_CPU)
31#define CRIS_CPU_GET_CLASS(obj) \
32 OBJECT_GET_CLASS(CRISCPUClass, (obj), TYPE_CRIS_CPU)
33
34/**
35 * CRISCPUClass:
ca45f8b0 36 * @parent_realize: The parent class' realize handler.
e739a48e 37 * @parent_reset: The parent class' reset handler.
6ae064fc 38 * @vr: Version Register value.
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39 *
40 * A CRIS CPU model.
41 */
42typedef struct CRISCPUClass {
43 /*< private >*/
44 CPUClass parent_class;
45 /*< public >*/
46
ca45f8b0 47 DeviceRealize parent_realize;
e739a48e 48 void (*parent_reset)(CPUState *cpu);
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49
50 uint32_t vr;
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51} CRISCPUClass;
52
53/**
54 * CRISCPU:
55 * @env: #CPUCRISState
56 *
57 * A CRIS CPU.
58 */
59typedef struct CRISCPU {
60 /*< private >*/
61 CPUState parent_obj;
62 /*< public >*/
63
64 CPUCRISState env;
65} CRISCPU;
66
67static inline CRISCPU *cris_env_get_cpu(CPUCRISState *env)
68{
6e42be7c 69 return container_of(env, CRISCPU, env);
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70}
71
72#define ENV_GET_CPU(e) CPU(cris_env_get_cpu(e))
73
fadf9825 74#define ENV_OFFSET offsetof(CRISCPU, env)
e739a48e 75
97a8ea5a 76void cris_cpu_do_interrupt(CPUState *cpu);
b21bfeea 77void crisv10_cpu_do_interrupt(CPUState *cpu);
97a8ea5a 78
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79void cris_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,
80 int flags);
81
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82hwaddr cris_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
83
90431220 84int crisv10_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg);
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85int cris_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg);
86int cris_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
87
e739a48e 88#endif