projects / mirror_qemu.git / blame
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|---|---|---|
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1 | /* |
| 2 | * QEMU CRIS CPU | |
| 3 | * | |
| 1c3b52fb AF |
4 | * Copyright (c) 2008 AXIS Communications AB |
| 5 | * Written by Edgar E. Iglesias. | |
| 6 | * | |
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7 | * Copyright (c) 2012 SUSE LINUX Products GmbH |
| 8 | * | |
| 9 | * This library is free software; you can redistribute it and/or | |
| 10 | * modify it under the terms of the GNU Lesser General Public | |
| 11 | * License as published by the Free Software Foundation; either | |
| 12 | * version 2.1 of the License, or (at your option) any later version. | |
| 13 | * | |
| 14 | * This library is distributed in the hope that it will be useful, | |
| 15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
| 17 | * Lesser General Public License for more details. | |
| 18 | * | |
| 19 | * You should have received a copy of the GNU Lesser General Public | |
| 20 | * License along with this library; if not, see | |
| 21 | * <http://www.gnu.org/licenses/lgpl-2.1.html> | |
| 22 | */ | |
| 23 | ||
| 24 | #include "cpu.h" | |
| 25 | #include "qemu-common.h" | |
| 1c3b52fb | 26 | #include "mmu.h" |
| e739a48e AF |
27 | |
| 28 | ||
| 29 | /* CPUClass::reset() */ | |
| 30 | static void cris_cpu_reset(CPUState *s) | |
| 31 | { | |
| 32 | CRISCPU *cpu = CRIS_CPU(s); | |
| 33 | CRISCPUClass *ccc = CRIS_CPU_GET_CLASS(cpu); | |
| 34 | CPUCRISState *env = &cpu->env; | |
| 1c3b52fb AF |
35 | uint32_t vr; |
| 36 | ||
| 37 | if (qemu_loglevel_mask(CPU_LOG_RESET)) { | |
| 38 | qemu_log("CPU Reset (CPU %d)\n", env->cpu_index); | |
| 39 | log_cpu_state(env, 0); | |
| 40 | } | |
| e739a48e AF |
41 | |
| 42 | ccc->parent_reset(s); | |
| 43 | ||
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44 | vr = env->pregs[PR_VR]; |
| 45 | memset(env, 0, offsetof(CPUCRISState, breakpoints)); | |
| 46 | env->pregs[PR_VR] = vr; | |
| 47 | tlb_flush(env, 1); | |
| 48 | ||
| 49 | #if defined(CONFIG_USER_ONLY) | |
| 50 | /* start in user mode with interrupts enabled. */ | |
| 51 | env->pregs[PR_CCS] |= U_FLAG | I_FLAG | P_FLAG; | |
| 52 | #else | |
| 53 | cris_mmu_init(env); | |
| 54 | env->pregs[PR_CCS] = 0; | |
| 55 | #endif | |
| e739a48e AF |
56 | } |
| 57 | ||
| 58 | static void cris_cpu_class_init(ObjectClass *oc, void *data) | |
| 59 | { | |
| 60 | CPUClass *cc = CPU_CLASS(oc); | |
| 61 | CRISCPUClass *ccc = CRIS_CPU_CLASS(oc); | |
| 62 | ||
| 63 | ccc->parent_reset = cc->reset; | |
| 64 | cc->reset = cris_cpu_reset; | |
| 65 | } | |
| 66 | ||
| 67 | static const TypeInfo cris_cpu_type_info = { | |
| 68 | .name = TYPE_CRIS_CPU, | |
| 69 | .parent = TYPE_CPU, | |
| 70 | .instance_size = sizeof(CRISCPU), | |
| 71 | .abstract = false, | |
| 72 | .class_size = sizeof(CRISCPUClass), | |
| 73 | .class_init = cris_cpu_class_init, | |
| 74 | }; | |
| 75 | ||
| 76 | static void cris_cpu_register_types(void) | |
| 77 | { | |
| 78 | type_register_static(&cris_cpu_type_info); | |
| 79 | } | |
| 80 | ||
| 81 | type_init(cris_cpu_register_types) |