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Commit | Line | Data |
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8170028d TS |
1 | /* |
2 | * CRIS emulation for qemu: main translation routines. | |
3 | * | |
05ba7d5f | 4 | * Copyright (c) 2008 AXIS Communications AB |
8170028d TS |
5 | * Written by Edgar E. Iglesias. |
6 | * | |
7 | * This library is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU Lesser General Public | |
9 | * License as published by the Free Software Foundation; either | |
10 | * version 2 of the License, or (at your option) any later version. | |
11 | * | |
12 | * This library is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
15 | * Lesser General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU Lesser General Public | |
8167ee88 | 18 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. |
8170028d TS |
19 | */ |
20 | ||
b41f7df0 EI |
21 | /* |
22 | * FIXME: | |
cf1d97f0 | 23 | * The condition code translation is in need of attention. |
b41f7df0 EI |
24 | */ |
25 | ||
8170028d | 26 | #include "cpu.h" |
76cad711 | 27 | #include "disas/disas.h" |
57fec1fe | 28 | #include "tcg-op.h" |
2ef6175a | 29 | #include "exec/helper-proto.h" |
52819664 | 30 | #include "mmu.h" |
f08b6170 | 31 | #include "exec/cpu_ldst.h" |
8170028d TS |
32 | #include "crisv32-decode.h" |
33 | ||
2ef6175a | 34 | #include "exec/helper-gen.h" |
a7812ae4 | 35 | |
a7e30d84 LV |
36 | #include "trace-tcg.h" |
37 | ||
38 | ||
8170028d TS |
39 | #define DISAS_CRIS 0 |
40 | #if DISAS_CRIS | |
93fcfe39 | 41 | # define LOG_DIS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__) |
8170028d | 42 | #else |
d12d51d5 | 43 | # define LOG_DIS(...) do { } while (0) |
8170028d TS |
44 | #endif |
45 | ||
b41f7df0 | 46 | #define D(x) |
8170028d TS |
47 | #define BUG() (gen_BUG(dc, __FILE__, __LINE__)) |
48 | #define BUG_ON(x) ({if (x) BUG();}) | |
49 | ||
4f400ab5 EI |
50 | #define DISAS_SWI 5 |
51 | ||
8170028d TS |
52 | /* Used by the decoder. */ |
53 | #define EXTRACT_FIELD(src, start, end) \ | |
54 | (((src) >> start) & ((1 << (end - start + 1)) - 1)) | |
55 | ||
56 | #define CC_MASK_NZ 0xc | |
57 | #define CC_MASK_NZV 0xe | |
58 | #define CC_MASK_NZVC 0xf | |
59 | #define CC_MASK_RNZV 0x10e | |
60 | ||
a7812ae4 | 61 | static TCGv_ptr cpu_env; |
9b32fbf8 EI |
62 | static TCGv cpu_R[16]; |
63 | static TCGv cpu_PR[16]; | |
64 | static TCGv cc_x; | |
65 | static TCGv cc_src; | |
66 | static TCGv cc_dest; | |
67 | static TCGv cc_result; | |
68 | static TCGv cc_op; | |
69 | static TCGv cc_size; | |
70 | static TCGv cc_mask; | |
71 | ||
72 | static TCGv env_btaken; | |
73 | static TCGv env_btarget; | |
74 | static TCGv env_pc; | |
b41f7df0 | 75 | |
022c62cb | 76 | #include "exec/gen-icount.h" |
2e70f6ef | 77 | |
8170028d TS |
78 | /* This is the state at translation time. */ |
79 | typedef struct DisasContext { | |
0dd106c5 | 80 | CRISCPU *cpu; |
7b5eff4d | 81 | target_ulong pc, ppc; |
8170028d | 82 | |
7b5eff4d | 83 | /* Decoder. */ |
cf7e0c80 | 84 | unsigned int (*decoder)(CPUCRISState *env, struct DisasContext *dc); |
7b5eff4d EV |
85 | uint32_t ir; |
86 | uint32_t opcode; | |
87 | unsigned int op1; | |
88 | unsigned int op2; | |
89 | unsigned int zsize, zzsize; | |
90 | unsigned int mode; | |
91 | unsigned int postinc; | |
92 | ||
93 | unsigned int size; | |
94 | unsigned int src; | |
95 | unsigned int dst; | |
96 | unsigned int cond; | |
97 | ||
98 | int update_cc; | |
99 | int cc_op; | |
100 | int cc_size; | |
101 | uint32_t cc_mask; | |
102 | ||
103 | int cc_size_uptodate; /* -1 invalid or last written value. */ | |
104 | ||
105 | int cc_x_uptodate; /* 1 - ccs, 2 - known | X_FLAG. 0 not uptodate. */ | |
106 | int flags_uptodate; /* Wether or not $ccs is uptodate. */ | |
107 | int flagx_known; /* Wether or not flags_x has the x flag known at | |
108 | translation time. */ | |
109 | int flags_x; | |
110 | ||
111 | int clear_x; /* Clear x after this insn? */ | |
112 | int clear_prefix; /* Clear prefix after this insn? */ | |
113 | int clear_locked_irq; /* Clear the irq lockout. */ | |
114 | int cpustate_changed; | |
115 | unsigned int tb_flags; /* tb dependent flags. */ | |
116 | int is_jmp; | |
8170028d | 117 | |
5cabc5cc EI |
118 | #define JMP_NOJMP 0 |
119 | #define JMP_DIRECT 1 | |
120 | #define JMP_DIRECT_CC 2 | |
121 | #define JMP_INDIRECT 3 | |
7b5eff4d EV |
122 | int jmp; /* 0=nojmp, 1=direct, 2=indirect. */ |
123 | uint32_t jmp_pc; | |
2a44f7f1 | 124 | |
7b5eff4d | 125 | int delayed_branch; |
8170028d | 126 | |
7b5eff4d EV |
127 | struct TranslationBlock *tb; |
128 | int singlestep_enabled; | |
8170028d TS |
129 | } DisasContext; |
130 | ||
7ccfb2eb | 131 | static void gen_BUG(DisasContext *dc, const char *file, int line) |
8170028d | 132 | { |
7b5eff4d EV |
133 | printf("BUG: pc=%x %s %d\n", dc->pc, file, line); |
134 | qemu_log("BUG: pc=%x %s %d\n", dc->pc, file, line); | |
0dd106c5 | 135 | cpu_abort(CPU(dc->cpu), "%s:%d\n", file, line); |
8170028d TS |
136 | } |
137 | ||
9b32fbf8 | 138 | static const char *regnames[] = |
a825e703 | 139 | { |
7b5eff4d EV |
140 | "$r0", "$r1", "$r2", "$r3", |
141 | "$r4", "$r5", "$r6", "$r7", | |
142 | "$r8", "$r9", "$r10", "$r11", | |
143 | "$r12", "$r13", "$sp", "$acr", | |
a825e703 | 144 | }; |
9b32fbf8 | 145 | static const char *pregnames[] = |
a825e703 | 146 | { |
7b5eff4d EV |
147 | "$bz", "$vr", "$pid", "$srs", |
148 | "$wz", "$exs", "$eda", "$mof", | |
149 | "$dz", "$ebp", "$erp", "$srp", | |
150 | "$nrp", "$ccs", "$usp", "$spc", | |
a825e703 EI |
151 | }; |
152 | ||
05ba7d5f | 153 | /* We need this table to handle preg-moves with implicit width. */ |
9b32fbf8 | 154 | static int preg_sizes[] = { |
7b5eff4d EV |
155 | 1, /* bz. */ |
156 | 1, /* vr. */ | |
157 | 4, /* pid. */ | |
158 | 1, /* srs. */ | |
159 | 2, /* wz. */ | |
160 | 4, 4, 4, | |
161 | 4, 4, 4, 4, | |
162 | 4, 4, 4, 4, | |
05ba7d5f EI |
163 | }; |
164 | ||
165 | #define t_gen_mov_TN_env(tn, member) \ | |
37654d9e | 166 | tcg_gen_ld_tl(tn, cpu_env, offsetof(CPUCRISState, member)) |
05ba7d5f | 167 | #define t_gen_mov_env_TN(member, tn) \ |
37654d9e | 168 | tcg_gen_st_tl(tn, cpu_env, offsetof(CPUCRISState, member)) |
05ba7d5f EI |
169 | |
170 | static inline void t_gen_mov_TN_preg(TCGv tn, int r) | |
171 | { | |
7b5eff4d EV |
172 | if (r < 0 || r > 15) { |
173 | fprintf(stderr, "wrong register read $p%d\n", r); | |
174 | } | |
175 | if (r == PR_BZ || r == PR_WZ || r == PR_DZ) { | |
176 | tcg_gen_mov_tl(tn, tcg_const_tl(0)); | |
177 | } else if (r == PR_VR) { | |
178 | tcg_gen_mov_tl(tn, tcg_const_tl(32)); | |
179 | } else { | |
180 | tcg_gen_mov_tl(tn, cpu_PR[r]); | |
181 | } | |
05ba7d5f | 182 | } |
cf1d97f0 | 183 | static inline void t_gen_mov_preg_TN(DisasContext *dc, int r, TCGv tn) |
05ba7d5f | 184 | { |
7b5eff4d EV |
185 | if (r < 0 || r > 15) { |
186 | fprintf(stderr, "wrong register write $p%d\n", r); | |
187 | } | |
188 | if (r == PR_BZ || r == PR_WZ || r == PR_DZ) { | |
189 | return; | |
190 | } else if (r == PR_SRS) { | |
191 | tcg_gen_andi_tl(cpu_PR[r], tn, 3); | |
192 | } else { | |
193 | if (r == PR_PID) { | |
194 | gen_helper_tlb_flush_pid(cpu_env, tn); | |
195 | } | |
196 | if (dc->tb_flags & S_FLAG && r == PR_SPC) { | |
197 | gen_helper_spc_write(cpu_env, tn); | |
198 | } else if (r == PR_CCS) { | |
199 | dc->cpustate_changed = 1; | |
200 | } | |
201 | tcg_gen_mov_tl(cpu_PR[r], tn); | |
202 | } | |
05ba7d5f EI |
203 | } |
204 | ||
1884533c EI |
205 | /* Sign extend at translation time. */ |
206 | static int sign_extend(unsigned int val, unsigned int width) | |
207 | { | |
7b5eff4d | 208 | int sval; |
1884533c | 209 | |
7b5eff4d EV |
210 | /* LSL. */ |
211 | val <<= 31 - width; | |
212 | sval = val; | |
213 | /* ASR. */ | |
214 | sval >>= 31 - width; | |
215 | return sval; | |
1884533c EI |
216 | } |
217 | ||
cf7e0c80 | 218 | static int cris_fetch(CPUCRISState *env, DisasContext *dc, uint32_t addr, |
7b5eff4d EV |
219 | unsigned int size, unsigned int sign) |
220 | { | |
221 | int r; | |
222 | ||
223 | switch (size) { | |
224 | case 4: | |
225 | { | |
226 | r = cpu_ldl_code(env, addr); | |
227 | break; | |
228 | } | |
229 | case 2: | |
230 | { | |
231 | if (sign) { | |
232 | r = cpu_ldsw_code(env, addr); | |
233 | } else { | |
234 | r = cpu_lduw_code(env, addr); | |
235 | } | |
236 | break; | |
237 | } | |
238 | case 1: | |
239 | { | |
240 | if (sign) { | |
241 | r = cpu_ldsb_code(env, addr); | |
242 | } else { | |
243 | r = cpu_ldub_code(env, addr); | |
244 | } | |
245 | break; | |
246 | } | |
247 | default: | |
0dd106c5 | 248 | cpu_abort(CPU(dc->cpu), "Invalid fetch size %d\n", size); |
7b5eff4d EV |
249 | break; |
250 | } | |
251 | return r; | |
7de141cb EI |
252 | } |
253 | ||
40e9eddd EI |
254 | static void cris_lock_irq(DisasContext *dc) |
255 | { | |
7b5eff4d EV |
256 | dc->clear_locked_irq = 0; |
257 | t_gen_mov_env_TN(locked_irq, tcg_const_tl(1)); | |
40e9eddd EI |
258 | } |
259 | ||
dceaf394 | 260 | static inline void t_gen_raise_exception(uint32_t index) |
05ba7d5f | 261 | { |
a7812ae4 | 262 | TCGv_i32 tmp = tcg_const_i32(index); |
febc9920 | 263 | gen_helper_raise_exception(cpu_env, tmp); |
a7812ae4 | 264 | tcg_temp_free_i32(tmp); |
05ba7d5f EI |
265 | } |
266 | ||
267 | static void t_gen_lsl(TCGv d, TCGv a, TCGv b) | |
268 | { | |
7b5eff4d | 269 | TCGv t0, t_31; |
05ba7d5f | 270 | |
7b5eff4d EV |
271 | t0 = tcg_temp_new(); |
272 | t_31 = tcg_const_tl(31); | |
273 | tcg_gen_shl_tl(d, a, b); | |
7dcfb089 | 274 | |
7b5eff4d EV |
275 | tcg_gen_sub_tl(t0, t_31, b); |
276 | tcg_gen_sar_tl(t0, t0, t_31); | |
277 | tcg_gen_and_tl(t0, t0, d); | |
278 | tcg_gen_xor_tl(d, d, t0); | |
279 | tcg_temp_free(t0); | |
280 | tcg_temp_free(t_31); | |
05ba7d5f EI |
281 | } |
282 | ||
283 | static void t_gen_lsr(TCGv d, TCGv a, TCGv b) | |
284 | { | |
7b5eff4d | 285 | TCGv t0, t_31; |
05ba7d5f | 286 | |
7b5eff4d EV |
287 | t0 = tcg_temp_new(); |
288 | t_31 = tcg_temp_new(); | |
289 | tcg_gen_shr_tl(d, a, b); | |
7dcfb089 | 290 | |
7b5eff4d EV |
291 | tcg_gen_movi_tl(t_31, 31); |
292 | tcg_gen_sub_tl(t0, t_31, b); | |
293 | tcg_gen_sar_tl(t0, t0, t_31); | |
294 | tcg_gen_and_tl(t0, t0, d); | |
295 | tcg_gen_xor_tl(d, d, t0); | |
296 | tcg_temp_free(t0); | |
297 | tcg_temp_free(t_31); | |
05ba7d5f EI |
298 | } |
299 | ||
300 | static void t_gen_asr(TCGv d, TCGv a, TCGv b) | |
301 | { | |
7b5eff4d | 302 | TCGv t0, t_31; |
05ba7d5f | 303 | |
7b5eff4d EV |
304 | t0 = tcg_temp_new(); |
305 | t_31 = tcg_temp_new(); | |
306 | tcg_gen_sar_tl(d, a, b); | |
7dcfb089 | 307 | |
7b5eff4d EV |
308 | tcg_gen_movi_tl(t_31, 31); |
309 | tcg_gen_sub_tl(t0, t_31, b); | |
310 | tcg_gen_sar_tl(t0, t0, t_31); | |
311 | tcg_gen_or_tl(d, d, t0); | |
312 | tcg_temp_free(t0); | |
313 | tcg_temp_free(t_31); | |
05ba7d5f EI |
314 | } |
315 | ||
30abcfc7 | 316 | static void t_gen_cris_dstep(TCGv d, TCGv a, TCGv b) |
aae6b32a | 317 | { |
7b5eff4d | 318 | int l1; |
aae6b32a | 319 | |
7b5eff4d | 320 | l1 = gen_new_label(); |
aae6b32a | 321 | |
7b5eff4d EV |
322 | /* |
323 | * d <<= 1 | |
324 | * if (d >= s) | |
325 | * d -= s; | |
326 | */ | |
327 | tcg_gen_shli_tl(d, a, 1); | |
328 | tcg_gen_brcond_tl(TCG_COND_LTU, d, b, l1); | |
329 | tcg_gen_sub_tl(d, d, b); | |
330 | gen_set_label(l1); | |
aae6b32a EI |
331 | } |
332 | ||
40e9eddd EI |
333 | static void t_gen_cris_mstep(TCGv d, TCGv a, TCGv b, TCGv ccs) |
334 | { | |
7b5eff4d | 335 | TCGv t; |
40e9eddd | 336 | |
7b5eff4d EV |
337 | /* |
338 | * d <<= 1 | |
339 | * if (n) | |
340 | * d += s; | |
341 | */ | |
342 | t = tcg_temp_new(); | |
343 | tcg_gen_shli_tl(d, a, 1); | |
344 | tcg_gen_shli_tl(t, ccs, 31 - 3); | |
345 | tcg_gen_sari_tl(t, t, 31); | |
346 | tcg_gen_and_tl(t, t, b); | |
347 | tcg_gen_add_tl(d, d, t); | |
348 | tcg_temp_free(t); | |
40e9eddd EI |
349 | } |
350 | ||
3157a0a9 EI |
351 | /* Extended arithmetics on CRIS. */ |
352 | static inline void t_gen_add_flag(TCGv d, int flag) | |
353 | { | |
7b5eff4d | 354 | TCGv c; |
3157a0a9 | 355 | |
7b5eff4d EV |
356 | c = tcg_temp_new(); |
357 | t_gen_mov_TN_preg(c, PR_CCS); | |
358 | /* Propagate carry into d. */ | |
359 | tcg_gen_andi_tl(c, c, 1 << flag); | |
360 | if (flag) { | |
361 | tcg_gen_shri_tl(c, c, flag); | |
362 | } | |
363 | tcg_gen_add_tl(d, d, c); | |
364 | tcg_temp_free(c); | |
3157a0a9 EI |
365 | } |
366 | ||
30abcfc7 | 367 | static inline void t_gen_addx_carry(DisasContext *dc, TCGv d) |
3157a0a9 | 368 | { |
7b5eff4d EV |
369 | if (dc->flagx_known) { |
370 | if (dc->flags_x) { | |
371 | TCGv c; | |
30abcfc7 | 372 | |
7b5eff4d EV |
373 | c = tcg_temp_new(); |
374 | t_gen_mov_TN_preg(c, PR_CCS); | |
375 | /* C flag is already at bit 0. */ | |
376 | tcg_gen_andi_tl(c, c, C_FLAG); | |
377 | tcg_gen_add_tl(d, d, c); | |
378 | tcg_temp_free(c); | |
379 | } | |
380 | } else { | |
381 | TCGv x, c; | |
382 | ||
383 | x = tcg_temp_new(); | |
384 | c = tcg_temp_new(); | |
385 | t_gen_mov_TN_preg(x, PR_CCS); | |
386 | tcg_gen_mov_tl(c, x); | |
387 | ||
388 | /* Propagate carry into d if X is set. Branch free. */ | |
389 | tcg_gen_andi_tl(c, c, C_FLAG); | |
390 | tcg_gen_andi_tl(x, x, X_FLAG); | |
391 | tcg_gen_shri_tl(x, x, 4); | |
392 | ||
393 | tcg_gen_and_tl(x, x, c); | |
394 | tcg_gen_add_tl(d, d, x); | |
395 | tcg_temp_free(x); | |
396 | tcg_temp_free(c); | |
397 | } | |
3157a0a9 EI |
398 | } |
399 | ||
a39f8f3a | 400 | static inline void t_gen_subx_carry(DisasContext *dc, TCGv d) |
3157a0a9 | 401 | { |
7b5eff4d EV |
402 | if (dc->flagx_known) { |
403 | if (dc->flags_x) { | |
404 | TCGv c; | |
30abcfc7 | 405 | |
7b5eff4d EV |
406 | c = tcg_temp_new(); |
407 | t_gen_mov_TN_preg(c, PR_CCS); | |
408 | /* C flag is already at bit 0. */ | |
409 | tcg_gen_andi_tl(c, c, C_FLAG); | |
410 | tcg_gen_sub_tl(d, d, c); | |
411 | tcg_temp_free(c); | |
412 | } | |
413 | } else { | |
414 | TCGv x, c; | |
415 | ||
416 | x = tcg_temp_new(); | |
417 | c = tcg_temp_new(); | |
418 | t_gen_mov_TN_preg(x, PR_CCS); | |
419 | tcg_gen_mov_tl(c, x); | |
420 | ||
421 | /* Propagate carry into d if X is set. Branch free. */ | |
422 | tcg_gen_andi_tl(c, c, C_FLAG); | |
423 | tcg_gen_andi_tl(x, x, X_FLAG); | |
424 | tcg_gen_shri_tl(x, x, 4); | |
425 | ||
426 | tcg_gen_and_tl(x, x, c); | |
427 | tcg_gen_sub_tl(d, d, x); | |
428 | tcg_temp_free(x); | |
429 | tcg_temp_free(c); | |
430 | } | |
3157a0a9 EI |
431 | } |
432 | ||
433 | /* Swap the two bytes within each half word of the s operand. | |
434 | T0 = ((T0 << 8) & 0xff00ff00) | ((T0 >> 8) & 0x00ff00ff) */ | |
435 | static inline void t_gen_swapb(TCGv d, TCGv s) | |
436 | { | |
7b5eff4d | 437 | TCGv t, org_s; |
3157a0a9 | 438 | |
7b5eff4d EV |
439 | t = tcg_temp_new(); |
440 | org_s = tcg_temp_new(); | |
3157a0a9 | 441 | |
7b5eff4d EV |
442 | /* d and s may refer to the same object. */ |
443 | tcg_gen_mov_tl(org_s, s); | |
444 | tcg_gen_shli_tl(t, org_s, 8); | |
445 | tcg_gen_andi_tl(d, t, 0xff00ff00); | |
446 | tcg_gen_shri_tl(t, org_s, 8); | |
447 | tcg_gen_andi_tl(t, t, 0x00ff00ff); | |
448 | tcg_gen_or_tl(d, d, t); | |
449 | tcg_temp_free(t); | |
450 | tcg_temp_free(org_s); | |
3157a0a9 EI |
451 | } |
452 | ||
453 | /* Swap the halfwords of the s operand. */ | |
454 | static inline void t_gen_swapw(TCGv d, TCGv s) | |
455 | { | |
7b5eff4d EV |
456 | TCGv t; |
457 | /* d and s refer the same object. */ | |
458 | t = tcg_temp_new(); | |
459 | tcg_gen_mov_tl(t, s); | |
460 | tcg_gen_shli_tl(d, t, 16); | |
461 | tcg_gen_shri_tl(t, t, 16); | |
462 | tcg_gen_or_tl(d, d, t); | |
463 | tcg_temp_free(t); | |
3157a0a9 EI |
464 | } |
465 | ||
466 | /* Reverse the within each byte. | |
467 | T0 = (((T0 << 7) & 0x80808080) | | |
468 | ((T0 << 5) & 0x40404040) | | |
469 | ((T0 << 3) & 0x20202020) | | |
470 | ((T0 << 1) & 0x10101010) | | |
471 | ((T0 >> 1) & 0x08080808) | | |
472 | ((T0 >> 3) & 0x04040404) | | |
473 | ((T0 >> 5) & 0x02020202) | | |
474 | ((T0 >> 7) & 0x01010101)); | |
475 | */ | |
476 | static inline void t_gen_swapr(TCGv d, TCGv s) | |
477 | { | |
7b5eff4d EV |
478 | struct { |
479 | int shift; /* LSL when positive, LSR when negative. */ | |
480 | uint32_t mask; | |
481 | } bitrev[] = { | |
482 | {7, 0x80808080}, | |
483 | {5, 0x40404040}, | |
484 | {3, 0x20202020}, | |
485 | {1, 0x10101010}, | |
486 | {-1, 0x08080808}, | |
487 | {-3, 0x04040404}, | |
488 | {-5, 0x02020202}, | |
489 | {-7, 0x01010101} | |
490 | }; | |
491 | int i; | |
492 | TCGv t, org_s; | |
493 | ||
494 | /* d and s refer the same object. */ | |
495 | t = tcg_temp_new(); | |
496 | org_s = tcg_temp_new(); | |
497 | tcg_gen_mov_tl(org_s, s); | |
498 | ||
499 | tcg_gen_shli_tl(t, org_s, bitrev[0].shift); | |
500 | tcg_gen_andi_tl(d, t, bitrev[0].mask); | |
501 | for (i = 1; i < ARRAY_SIZE(bitrev); i++) { | |
502 | if (bitrev[i].shift >= 0) { | |
503 | tcg_gen_shli_tl(t, org_s, bitrev[i].shift); | |
504 | } else { | |
505 | tcg_gen_shri_tl(t, org_s, -bitrev[i].shift); | |
506 | } | |
507 | tcg_gen_andi_tl(t, t, bitrev[i].mask); | |
508 | tcg_gen_or_tl(d, d, t); | |
509 | } | |
510 | tcg_temp_free(t); | |
511 | tcg_temp_free(org_s); | |
3157a0a9 EI |
512 | } |
513 | ||
cf1d97f0 | 514 | static void t_gen_cc_jmp(TCGv pc_true, TCGv pc_false) |
17ac9754 | 515 | { |
7b5eff4d | 516 | int l1; |
17ac9754 | 517 | |
7b5eff4d | 518 | l1 = gen_new_label(); |
17ac9754 | 519 | |
7b5eff4d EV |
520 | /* Conditional jmp. */ |
521 | tcg_gen_mov_tl(env_pc, pc_false); | |
522 | tcg_gen_brcondi_tl(TCG_COND_EQ, env_btaken, 0, l1); | |
523 | tcg_gen_mov_tl(env_pc, pc_true); | |
524 | gen_set_label(l1); | |
17ac9754 EI |
525 | } |
526 | ||
8170028d TS |
527 | static void gen_goto_tb(DisasContext *dc, int n, target_ulong dest) |
528 | { | |
7b5eff4d EV |
529 | TranslationBlock *tb; |
530 | tb = dc->tb; | |
531 | if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK)) { | |
532 | tcg_gen_goto_tb(n); | |
533 | tcg_gen_movi_tl(env_pc, dest); | |
8cfd0495 | 534 | tcg_gen_exit_tb((uintptr_t)tb + n); |
7b5eff4d EV |
535 | } else { |
536 | tcg_gen_movi_tl(env_pc, dest); | |
537 | tcg_gen_exit_tb(0); | |
538 | } | |
8170028d TS |
539 | } |
540 | ||
05ba7d5f EI |
541 | static inline void cris_clear_x_flag(DisasContext *dc) |
542 | { | |
7b5eff4d EV |
543 | if (dc->flagx_known && dc->flags_x) { |
544 | dc->flags_uptodate = 0; | |
545 | } | |
2a44f7f1 | 546 | |
7b5eff4d EV |
547 | dc->flagx_known = 1; |
548 | dc->flags_x = 0; | |
05ba7d5f EI |
549 | } |
550 | ||
30abcfc7 | 551 | static void cris_flush_cc_state(DisasContext *dc) |
8170028d | 552 | { |
7b5eff4d EV |
553 | if (dc->cc_size_uptodate != dc->cc_size) { |
554 | tcg_gen_movi_tl(cc_size, dc->cc_size); | |
555 | dc->cc_size_uptodate = dc->cc_size; | |
556 | } | |
557 | tcg_gen_movi_tl(cc_op, dc->cc_op); | |
558 | tcg_gen_movi_tl(cc_mask, dc->cc_mask); | |
30abcfc7 EI |
559 | } |
560 | ||
561 | static void cris_evaluate_flags(DisasContext *dc) | |
562 | { | |
7b5eff4d EV |
563 | if (dc->flags_uptodate) { |
564 | return; | |
565 | } | |
566 | ||
567 | cris_flush_cc_state(dc); | |
568 | ||
569 | switch (dc->cc_op) { | |
570 | case CC_OP_MCP: | |
571 | gen_helper_evaluate_flags_mcp(cpu_PR[PR_CCS], cpu_env, | |
572 | cpu_PR[PR_CCS], cc_src, | |
573 | cc_dest, cc_result); | |
574 | break; | |
575 | case CC_OP_MULS: | |
576 | gen_helper_evaluate_flags_muls(cpu_PR[PR_CCS], cpu_env, | |
577 | cpu_PR[PR_CCS], cc_result, | |
578 | cpu_PR[PR_MOF]); | |
579 | break; | |
580 | case CC_OP_MULU: | |
581 | gen_helper_evaluate_flags_mulu(cpu_PR[PR_CCS], cpu_env, | |
582 | cpu_PR[PR_CCS], cc_result, | |
583 | cpu_PR[PR_MOF]); | |
584 | break; | |
585 | case CC_OP_MOVE: | |
586 | case CC_OP_AND: | |
587 | case CC_OP_OR: | |
588 | case CC_OP_XOR: | |
589 | case CC_OP_ASR: | |
590 | case CC_OP_LSR: | |
591 | case CC_OP_LSL: | |
592 | switch (dc->cc_size) { | |
593 | case 4: | |
594 | gen_helper_evaluate_flags_move_4(cpu_PR[PR_CCS], | |
595 | cpu_env, cpu_PR[PR_CCS], cc_result); | |
596 | break; | |
597 | case 2: | |
598 | gen_helper_evaluate_flags_move_2(cpu_PR[PR_CCS], | |
599 | cpu_env, cpu_PR[PR_CCS], cc_result); | |
600 | break; | |
601 | default: | |
602 | gen_helper_evaluate_flags(cpu_env); | |
603 | break; | |
604 | } | |
605 | break; | |
606 | case CC_OP_FLAGS: | |
607 | /* live. */ | |
608 | break; | |
609 | case CC_OP_SUB: | |
610 | case CC_OP_CMP: | |
611 | if (dc->cc_size == 4) { | |
612 | gen_helper_evaluate_flags_sub_4(cpu_PR[PR_CCS], cpu_env, | |
613 | cpu_PR[PR_CCS], cc_src, cc_dest, cc_result); | |
614 | } else { | |
615 | gen_helper_evaluate_flags(cpu_env); | |
616 | } | |
617 | ||
618 | break; | |
619 | default: | |
620 | switch (dc->cc_size) { | |
621 | case 4: | |
622 | gen_helper_evaluate_flags_alu_4(cpu_PR[PR_CCS], cpu_env, | |
623 | cpu_PR[PR_CCS], cc_src, cc_dest, cc_result); | |
624 | break; | |
625 | default: | |
626 | gen_helper_evaluate_flags(cpu_env); | |
627 | break; | |
6231868b | 628 | } |
7b5eff4d EV |
629 | break; |
630 | } | |
631 | ||
632 | if (dc->flagx_known) { | |
633 | if (dc->flags_x) { | |
634 | tcg_gen_ori_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], X_FLAG); | |
635 | } else if (dc->cc_op == CC_OP_FLAGS) { | |
636 | tcg_gen_andi_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], ~X_FLAG); | |
637 | } | |
638 | } | |
639 | dc->flags_uptodate = 1; | |
8170028d TS |
640 | } |
641 | ||
642 | static void cris_cc_mask(DisasContext *dc, unsigned int mask) | |
643 | { | |
7b5eff4d | 644 | uint32_t ovl; |
8170028d | 645 | |
7b5eff4d EV |
646 | if (!mask) { |
647 | dc->update_cc = 0; | |
648 | return; | |
649 | } | |
2a44f7f1 | 650 | |
7b5eff4d EV |
651 | /* Check if we need to evaluate the condition codes due to |
652 | CC overlaying. */ | |
653 | ovl = (dc->cc_mask ^ mask) & ~mask; | |
654 | if (ovl) { | |
655 | /* TODO: optimize this case. It trigs all the time. */ | |
656 | cris_evaluate_flags(dc); | |
657 | } | |
658 | dc->cc_mask = mask; | |
659 | dc->update_cc = 1; | |
8170028d TS |
660 | } |
661 | ||
b41f7df0 | 662 | static void cris_update_cc_op(DisasContext *dc, int op, int size) |
8170028d | 663 | { |
7b5eff4d EV |
664 | dc->cc_op = op; |
665 | dc->cc_size = size; | |
666 | dc->flags_uptodate = 0; | |
8170028d TS |
667 | } |
668 | ||
30abcfc7 EI |
669 | static inline void cris_update_cc_x(DisasContext *dc) |
670 | { | |
7b5eff4d EV |
671 | /* Save the x flag state at the time of the cc snapshot. */ |
672 | if (dc->flagx_known) { | |
673 | if (dc->cc_x_uptodate == (2 | dc->flags_x)) { | |
674 | return; | |
675 | } | |
676 | tcg_gen_movi_tl(cc_x, dc->flags_x); | |
677 | dc->cc_x_uptodate = 2 | dc->flags_x; | |
678 | } else { | |
679 | tcg_gen_andi_tl(cc_x, cpu_PR[PR_CCS], X_FLAG); | |
680 | dc->cc_x_uptodate = 1; | |
681 | } | |
30abcfc7 EI |
682 | } |
683 | ||
684 | /* Update cc prior to executing ALU op. Needs source operands untouched. */ | |
685 | static void cris_pre_alu_update_cc(DisasContext *dc, int op, | |
7b5eff4d EV |
686 | TCGv dst, TCGv src, int size) |
687 | { | |
688 | if (dc->update_cc) { | |
689 | cris_update_cc_op(dc, op, size); | |
690 | tcg_gen_mov_tl(cc_src, src); | |
691 | ||
692 | if (op != CC_OP_MOVE | |
693 | && op != CC_OP_AND | |
694 | && op != CC_OP_OR | |
695 | && op != CC_OP_XOR | |
696 | && op != CC_OP_ASR | |
697 | && op != CC_OP_LSR | |
698 | && op != CC_OP_LSL) { | |
699 | tcg_gen_mov_tl(cc_dest, dst); | |
700 | } | |
30abcfc7 | 701 | |
7b5eff4d EV |
702 | cris_update_cc_x(dc); |
703 | } | |
30abcfc7 | 704 | } |
3157a0a9 | 705 | |
30abcfc7 EI |
706 | /* Update cc after executing ALU op. needs the result. */ |
707 | static inline void cris_update_result(DisasContext *dc, TCGv res) | |
708 | { | |
7b5eff4d EV |
709 | if (dc->update_cc) { |
710 | tcg_gen_mov_tl(cc_result, res); | |
711 | } | |
30abcfc7 | 712 | } |
8170028d | 713 | |
30abcfc7 EI |
714 | /* Returns one if the write back stage should execute. */ |
715 | static void cris_alu_op_exec(DisasContext *dc, int op, | |
7b5eff4d EV |
716 | TCGv dst, TCGv a, TCGv b, int size) |
717 | { | |
718 | /* Emit the ALU insns. */ | |
719 | switch (op) { | |
720 | case CC_OP_ADD: | |
721 | tcg_gen_add_tl(dst, a, b); | |
722 | /* Extended arithmetics. */ | |
723 | t_gen_addx_carry(dc, dst); | |
724 | break; | |
725 | case CC_OP_ADDC: | |
726 | tcg_gen_add_tl(dst, a, b); | |
727 | t_gen_add_flag(dst, 0); /* C_FLAG. */ | |
728 | break; | |
729 | case CC_OP_MCP: | |
730 | tcg_gen_add_tl(dst, a, b); | |
731 | t_gen_add_flag(dst, 8); /* R_FLAG. */ | |
732 | break; | |
733 | case CC_OP_SUB: | |
734 | tcg_gen_sub_tl(dst, a, b); | |
735 | /* Extended arithmetics. */ | |
736 | t_gen_subx_carry(dc, dst); | |
737 | break; | |
738 | case CC_OP_MOVE: | |
739 | tcg_gen_mov_tl(dst, b); | |
740 | break; | |
741 | case CC_OP_OR: | |
742 | tcg_gen_or_tl(dst, a, b); | |
743 | break; | |
744 | case CC_OP_AND: | |
745 | tcg_gen_and_tl(dst, a, b); | |
746 | break; | |
747 | case CC_OP_XOR: | |
748 | tcg_gen_xor_tl(dst, a, b); | |
749 | break; | |
750 | case CC_OP_LSL: | |
751 | t_gen_lsl(dst, a, b); | |
752 | break; | |
753 | case CC_OP_LSR: | |
754 | t_gen_lsr(dst, a, b); | |
755 | break; | |
756 | case CC_OP_ASR: | |
757 | t_gen_asr(dst, a, b); | |
758 | break; | |
759 | case CC_OP_NEG: | |
760 | tcg_gen_neg_tl(dst, b); | |
761 | /* Extended arithmetics. */ | |
762 | t_gen_subx_carry(dc, dst); | |
763 | break; | |
764 | case CC_OP_LZ: | |
765 | gen_helper_lz(dst, b); | |
766 | break; | |
767 | case CC_OP_MULS: | |
bf45f971 | 768 | tcg_gen_muls2_tl(dst, cpu_PR[PR_MOF], a, b); |
7b5eff4d EV |
769 | break; |
770 | case CC_OP_MULU: | |
bf45f971 | 771 | tcg_gen_mulu2_tl(dst, cpu_PR[PR_MOF], a, b); |
7b5eff4d EV |
772 | break; |
773 | case CC_OP_DSTEP: | |
774 | t_gen_cris_dstep(dst, a, b); | |
775 | break; | |
776 | case CC_OP_MSTEP: | |
777 | t_gen_cris_mstep(dst, a, b, cpu_PR[PR_CCS]); | |
778 | break; | |
779 | case CC_OP_BOUND: | |
780 | { | |
781 | int l1; | |
782 | l1 = gen_new_label(); | |
783 | tcg_gen_mov_tl(dst, a); | |
784 | tcg_gen_brcond_tl(TCG_COND_LEU, a, b, l1); | |
785 | tcg_gen_mov_tl(dst, b); | |
786 | gen_set_label(l1); | |
787 | } | |
788 | break; | |
789 | case CC_OP_CMP: | |
790 | tcg_gen_sub_tl(dst, a, b); | |
791 | /* Extended arithmetics. */ | |
792 | t_gen_subx_carry(dc, dst); | |
793 | break; | |
794 | default: | |
795 | qemu_log("illegal ALU op.\n"); | |
796 | BUG(); | |
797 | break; | |
798 | } | |
799 | ||
800 | if (size == 1) { | |
801 | tcg_gen_andi_tl(dst, dst, 0xff); | |
802 | } else if (size == 2) { | |
803 | tcg_gen_andi_tl(dst, dst, 0xffff); | |
804 | } | |
30abcfc7 EI |
805 | } |
806 | ||
807 | static void cris_alu(DisasContext *dc, int op, | |
7b5eff4d | 808 | TCGv d, TCGv op_a, TCGv op_b, int size) |
30abcfc7 | 809 | { |
7b5eff4d EV |
810 | TCGv tmp; |
811 | int writeback; | |
30abcfc7 | 812 | |
7b5eff4d | 813 | writeback = 1; |
31c18d87 | 814 | |
7b5eff4d EV |
815 | if (op == CC_OP_CMP) { |
816 | tmp = tcg_temp_new(); | |
817 | writeback = 0; | |
818 | } else if (size == 4) { | |
819 | tmp = d; | |
820 | writeback = 0; | |
821 | } else { | |
822 | tmp = tcg_temp_new(); | |
823 | } | |
44696296 | 824 | |
30abcfc7 | 825 | |
7b5eff4d EV |
826 | cris_pre_alu_update_cc(dc, op, op_a, op_b, size); |
827 | cris_alu_op_exec(dc, op, tmp, op_a, op_b, size); | |
828 | cris_update_result(dc, tmp); | |
05ba7d5f | 829 | |
7b5eff4d EV |
830 | /* Writeback. */ |
831 | if (writeback) { | |
832 | if (size == 1) { | |
833 | tcg_gen_andi_tl(d, d, ~0xff); | |
834 | } else { | |
835 | tcg_gen_andi_tl(d, d, ~0xffff); | |
836 | } | |
837 | tcg_gen_or_tl(d, d, tmp); | |
838 | } | |
839 | if (!TCGV_EQUAL(tmp, d)) { | |
840 | tcg_temp_free(tmp); | |
841 | } | |
8170028d TS |
842 | } |
843 | ||
844 | static int arith_cc(DisasContext *dc) | |
845 | { | |
7b5eff4d EV |
846 | if (dc->update_cc) { |
847 | switch (dc->cc_op) { | |
848 | case CC_OP_ADDC: return 1; | |
849 | case CC_OP_ADD: return 1; | |
850 | case CC_OP_SUB: return 1; | |
851 | case CC_OP_DSTEP: return 1; | |
852 | case CC_OP_LSL: return 1; | |
853 | case CC_OP_LSR: return 1; | |
854 | case CC_OP_ASR: return 1; | |
855 | case CC_OP_CMP: return 1; | |
856 | case CC_OP_NEG: return 1; | |
857 | case CC_OP_OR: return 1; | |
858 | case CC_OP_AND: return 1; | |
859 | case CC_OP_XOR: return 1; | |
860 | case CC_OP_MULU: return 1; | |
861 | case CC_OP_MULS: return 1; | |
862 | default: | |
863 | return 0; | |
864 | } | |
865 | } | |
866 | return 0; | |
8170028d TS |
867 | } |
868 | ||
c5631f48 | 869 | static void gen_tst_cc (DisasContext *dc, TCGv cc, int cond) |
8170028d | 870 | { |
7b5eff4d EV |
871 | int arith_opt, move_opt; |
872 | ||
873 | /* TODO: optimize more condition codes. */ | |
874 | ||
875 | /* | |
876 | * If the flags are live, we've gotta look into the bits of CCS. | |
877 | * Otherwise, if we just did an arithmetic operation we try to | |
878 | * evaluate the condition code faster. | |
879 | * | |
880 | * When this function is done, T0 should be non-zero if the condition | |
881 | * code is true. | |
882 | */ | |
883 | arith_opt = arith_cc(dc) && !dc->flags_uptodate; | |
884 | move_opt = (dc->cc_op == CC_OP_MOVE); | |
885 | switch (cond) { | |
886 | case CC_EQ: | |
887 | if ((arith_opt || move_opt) | |
888 | && dc->cc_x_uptodate != (2 | X_FLAG)) { | |
889 | tcg_gen_setcond_tl(TCG_COND_EQ, cc, | |
890 | cc_result, tcg_const_tl(0)); | |
891 | } else { | |
892 | cris_evaluate_flags(dc); | |
893 | tcg_gen_andi_tl(cc, | |
894 | cpu_PR[PR_CCS], Z_FLAG); | |
895 | } | |
896 | break; | |
897 | case CC_NE: | |
898 | if ((arith_opt || move_opt) | |
899 | && dc->cc_x_uptodate != (2 | X_FLAG)) { | |
900 | tcg_gen_mov_tl(cc, cc_result); | |
901 | } else { | |
902 | cris_evaluate_flags(dc); | |
903 | tcg_gen_xori_tl(cc, cpu_PR[PR_CCS], | |
904 | Z_FLAG); | |
905 | tcg_gen_andi_tl(cc, cc, Z_FLAG); | |
906 | } | |
907 | break; | |
908 | case CC_CS: | |
909 | cris_evaluate_flags(dc); | |
910 | tcg_gen_andi_tl(cc, cpu_PR[PR_CCS], C_FLAG); | |
911 | break; | |
912 | case CC_CC: | |
913 | cris_evaluate_flags(dc); | |
914 | tcg_gen_xori_tl(cc, cpu_PR[PR_CCS], C_FLAG); | |
915 | tcg_gen_andi_tl(cc, cc, C_FLAG); | |
916 | break; | |
917 | case CC_VS: | |
918 | cris_evaluate_flags(dc); | |
919 | tcg_gen_andi_tl(cc, cpu_PR[PR_CCS], V_FLAG); | |
920 | break; | |
921 | case CC_VC: | |
922 | cris_evaluate_flags(dc); | |
923 | tcg_gen_xori_tl(cc, cpu_PR[PR_CCS], | |
924 | V_FLAG); | |
925 | tcg_gen_andi_tl(cc, cc, V_FLAG); | |
926 | break; | |
927 | case CC_PL: | |
928 | if (arith_opt || move_opt) { | |
929 | int bits = 31; | |
930 | ||
931 | if (dc->cc_size == 1) { | |
932 | bits = 7; | |
933 | } else if (dc->cc_size == 2) { | |
934 | bits = 15; | |
935 | } | |
936 | ||
937 | tcg_gen_shri_tl(cc, cc_result, bits); | |
938 | tcg_gen_xori_tl(cc, cc, 1); | |
939 | } else { | |
940 | cris_evaluate_flags(dc); | |
941 | tcg_gen_xori_tl(cc, cpu_PR[PR_CCS], | |
942 | N_FLAG); | |
943 | tcg_gen_andi_tl(cc, cc, N_FLAG); | |
944 | } | |
945 | break; | |
946 | case CC_MI: | |
947 | if (arith_opt || move_opt) { | |
948 | int bits = 31; | |
949 | ||
950 | if (dc->cc_size == 1) { | |
951 | bits = 7; | |
952 | } else if (dc->cc_size == 2) { | |
953 | bits = 15; | |
954 | } | |
955 | ||
956 | tcg_gen_shri_tl(cc, cc_result, bits); | |
957 | tcg_gen_andi_tl(cc, cc, 1); | |
958 | } else { | |
959 | cris_evaluate_flags(dc); | |
960 | tcg_gen_andi_tl(cc, cpu_PR[PR_CCS], | |
961 | N_FLAG); | |
962 | } | |
963 | break; | |
964 | case CC_LS: | |
965 | cris_evaluate_flags(dc); | |
966 | tcg_gen_andi_tl(cc, cpu_PR[PR_CCS], | |
967 | C_FLAG | Z_FLAG); | |
968 | break; | |
969 | case CC_HI: | |
970 | cris_evaluate_flags(dc); | |
971 | { | |
972 | TCGv tmp; | |
973 | ||
974 | tmp = tcg_temp_new(); | |
975 | tcg_gen_xori_tl(tmp, cpu_PR[PR_CCS], | |
976 | C_FLAG | Z_FLAG); | |
977 | /* Overlay the C flag on top of the Z. */ | |
978 | tcg_gen_shli_tl(cc, tmp, 2); | |
979 | tcg_gen_and_tl(cc, tmp, cc); | |
980 | tcg_gen_andi_tl(cc, cc, Z_FLAG); | |
981 | ||
982 | tcg_temp_free(tmp); | |
983 | } | |
984 | break; | |
985 | case CC_GE: | |
986 | cris_evaluate_flags(dc); | |
987 | /* Overlay the V flag on top of the N. */ | |
988 | tcg_gen_shli_tl(cc, cpu_PR[PR_CCS], 2); | |
989 | tcg_gen_xor_tl(cc, | |
990 | cpu_PR[PR_CCS], cc); | |
991 | tcg_gen_andi_tl(cc, cc, N_FLAG); | |
992 | tcg_gen_xori_tl(cc, cc, N_FLAG); | |
993 | break; | |
994 | case CC_LT: | |
995 | cris_evaluate_flags(dc); | |
996 | /* Overlay the V flag on top of the N. */ | |
997 | tcg_gen_shli_tl(cc, cpu_PR[PR_CCS], 2); | |
998 | tcg_gen_xor_tl(cc, | |
999 | cpu_PR[PR_CCS], cc); | |
1000 | tcg_gen_andi_tl(cc, cc, N_FLAG); | |
1001 | break; | |
1002 | case CC_GT: | |
1003 | cris_evaluate_flags(dc); | |
1004 | { | |
1005 | TCGv n, z; | |
1006 | ||
1007 | n = tcg_temp_new(); | |
1008 | z = tcg_temp_new(); | |
1009 | ||
1010 | /* To avoid a shift we overlay everything on | |
1011 | the V flag. */ | |
1012 | tcg_gen_shri_tl(n, cpu_PR[PR_CCS], 2); | |
1013 | tcg_gen_shri_tl(z, cpu_PR[PR_CCS], 1); | |
1014 | /* invert Z. */ | |
1015 | tcg_gen_xori_tl(z, z, 2); | |
1016 | ||
1017 | tcg_gen_xor_tl(n, n, cpu_PR[PR_CCS]); | |
1018 | tcg_gen_xori_tl(n, n, 2); | |
1019 | tcg_gen_and_tl(cc, z, n); | |
1020 | tcg_gen_andi_tl(cc, cc, 2); | |
1021 | ||
1022 | tcg_temp_free(n); | |
1023 | tcg_temp_free(z); | |
1024 | } | |
1025 | break; | |
1026 | case CC_LE: | |
1027 | cris_evaluate_flags(dc); | |
1028 | { | |
1029 | TCGv n, z; | |
1030 | ||
1031 | n = tcg_temp_new(); | |
1032 | z = tcg_temp_new(); | |
1033 | ||
1034 | /* To avoid a shift we overlay everything on | |
1035 | the V flag. */ | |
1036 | tcg_gen_shri_tl(n, cpu_PR[PR_CCS], 2); | |
1037 | tcg_gen_shri_tl(z, cpu_PR[PR_CCS], 1); | |
1038 | ||
1039 | tcg_gen_xor_tl(n, n, cpu_PR[PR_CCS]); | |
1040 | tcg_gen_or_tl(cc, z, n); | |
1041 | tcg_gen_andi_tl(cc, cc, 2); | |
1042 | ||
1043 | tcg_temp_free(n); | |
1044 | tcg_temp_free(z); | |
1045 | } | |
1046 | break; | |
1047 | case CC_P: | |
1048 | cris_evaluate_flags(dc); | |
1049 | tcg_gen_andi_tl(cc, cpu_PR[PR_CCS], P_FLAG); | |
1050 | break; | |
1051 | case CC_A: | |
1052 | tcg_gen_movi_tl(cc, 1); | |
1053 | break; | |
1054 | default: | |
1055 | BUG(); | |
1056 | break; | |
1057 | }; | |
8170028d TS |
1058 | } |
1059 | ||
2a44f7f1 EI |
1060 | static void cris_store_direct_jmp(DisasContext *dc) |
1061 | { | |
7b5eff4d EV |
1062 | /* Store the direct jmp state into the cpu-state. */ |
1063 | if (dc->jmp == JMP_DIRECT || dc->jmp == JMP_DIRECT_CC) { | |
1064 | if (dc->jmp == JMP_DIRECT) { | |
1065 | tcg_gen_movi_tl(env_btaken, 1); | |
1066 | } | |
1067 | tcg_gen_movi_tl(env_btarget, dc->jmp_pc); | |
1068 | dc->jmp = JMP_INDIRECT; | |
1069 | } | |
2a44f7f1 EI |
1070 | } |
1071 | ||
1072 | static void cris_prepare_cc_branch (DisasContext *dc, | |
7b5eff4d | 1073 | int offset, int cond) |
8170028d | 1074 | { |
7b5eff4d EV |
1075 | /* This helps us re-schedule the micro-code to insns in delay-slots |
1076 | before the actual jump. */ | |
1077 | dc->delayed_branch = 2; | |
1078 | dc->jmp = JMP_DIRECT_CC; | |
1079 | dc->jmp_pc = dc->pc + offset; | |
2a44f7f1 | 1080 | |
7b5eff4d EV |
1081 | gen_tst_cc(dc, env_btaken, cond); |
1082 | tcg_gen_movi_tl(env_btarget, dc->jmp_pc); | |
8170028d TS |
1083 | } |
1084 | ||
b41f7df0 | 1085 | |
2a44f7f1 EI |
1086 | /* jumps, when the dest is in a live reg for example. Direct should be set |
1087 | when the dest addr is constant to allow tb chaining. */ | |
1088 | static inline void cris_prepare_jmp (DisasContext *dc, unsigned int type) | |
8170028d | 1089 | { |
7b5eff4d EV |
1090 | /* This helps us re-schedule the micro-code to insns in delay-slots |
1091 | before the actual jump. */ | |
1092 | dc->delayed_branch = 2; | |
1093 | dc->jmp = type; | |
1094 | if (type == JMP_INDIRECT) { | |
1095 | tcg_gen_movi_tl(env_btaken, 1); | |
1096 | } | |
8170028d TS |
1097 | } |
1098 | ||
a7812ae4 PB |
1099 | static void gen_load64(DisasContext *dc, TCGv_i64 dst, TCGv addr) |
1100 | { | |
0dd106c5 | 1101 | int mem_index = cpu_mmu_index(&dc->cpu->env); |
a7812ae4 | 1102 | |
7b5eff4d EV |
1103 | /* If we get a fault on a delayslot we must keep the jmp state in |
1104 | the cpu-state to be able to re-execute the jmp. */ | |
1105 | if (dc->delayed_branch == 1) { | |
1106 | cris_store_direct_jmp(dc); | |
1107 | } | |
a7812ae4 | 1108 | |
a1d22a36 | 1109 | tcg_gen_qemu_ld_i64(dst, addr, mem_index, MO_TEQ); |
a7812ae4 PB |
1110 | } |
1111 | ||
9b32fbf8 | 1112 | static void gen_load(DisasContext *dc, TCGv dst, TCGv addr, |
7b5eff4d EV |
1113 | unsigned int size, int sign) |
1114 | { | |
0dd106c5 | 1115 | int mem_index = cpu_mmu_index(&dc->cpu->env); |
7b5eff4d EV |
1116 | |
1117 | /* If we get a fault on a delayslot we must keep the jmp state in | |
1118 | the cpu-state to be able to re-execute the jmp. */ | |
1119 | if (dc->delayed_branch == 1) { | |
1120 | cris_store_direct_jmp(dc); | |
1121 | } | |
1122 | ||
a1d22a36 RH |
1123 | tcg_gen_qemu_ld_tl(dst, addr, mem_index, |
1124 | MO_TE + ctz32(size) + (sign ? MO_SIGN : 0)); | |
8170028d TS |
1125 | } |
1126 | ||
9b32fbf8 | 1127 | static void gen_store (DisasContext *dc, TCGv addr, TCGv val, |
7b5eff4d | 1128 | unsigned int size) |
8170028d | 1129 | { |
0dd106c5 | 1130 | int mem_index = cpu_mmu_index(&dc->cpu->env); |
b41f7df0 | 1131 | |
7b5eff4d EV |
1132 | /* If we get a fault on a delayslot we must keep the jmp state in |
1133 | the cpu-state to be able to re-execute the jmp. */ | |
1134 | if (dc->delayed_branch == 1) { | |
1135 | cris_store_direct_jmp(dc); | |
1136 | } | |
2a44f7f1 EI |
1137 | |
1138 | ||
7b5eff4d EV |
1139 | /* Conditional writes. We only support the kind were X and P are known |
1140 | at translation time. */ | |
1141 | if (dc->flagx_known && dc->flags_x && (dc->tb_flags & P_FLAG)) { | |
1142 | dc->postinc = 0; | |
1143 | cris_evaluate_flags(dc); | |
1144 | tcg_gen_ori_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], C_FLAG); | |
1145 | return; | |
1146 | } | |
2a44f7f1 | 1147 | |
a1d22a36 | 1148 | tcg_gen_qemu_st_tl(val, addr, mem_index, MO_TE + ctz32(size)); |
2a44f7f1 | 1149 | |
7b5eff4d EV |
1150 | if (dc->flagx_known && dc->flags_x) { |
1151 | cris_evaluate_flags(dc); | |
1152 | tcg_gen_andi_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], ~C_FLAG); | |
1153 | } | |
8170028d TS |
1154 | } |
1155 | ||
05ba7d5f | 1156 | static inline void t_gen_sext(TCGv d, TCGv s, int size) |
8170028d | 1157 | { |
7b5eff4d EV |
1158 | if (size == 1) { |
1159 | tcg_gen_ext8s_i32(d, s); | |
1160 | } else if (size == 2) { | |
1161 | tcg_gen_ext16s_i32(d, s); | |
1162 | } else if (!TCGV_EQUAL(d, s)) { | |
1163 | tcg_gen_mov_tl(d, s); | |
1164 | } | |
8170028d TS |
1165 | } |
1166 | ||
05ba7d5f | 1167 | static inline void t_gen_zext(TCGv d, TCGv s, int size) |
8170028d | 1168 | { |
7b5eff4d EV |
1169 | if (size == 1) { |
1170 | tcg_gen_ext8u_i32(d, s); | |
1171 | } else if (size == 2) { | |
1172 | tcg_gen_ext16u_i32(d, s); | |
1173 | } else if (!TCGV_EQUAL(d, s)) { | |
1174 | tcg_gen_mov_tl(d, s); | |
1175 | } | |
8170028d TS |
1176 | } |
1177 | ||
1178 | #if DISAS_CRIS | |
1179 | static char memsize_char(int size) | |
1180 | { | |
7b5eff4d EV |
1181 | switch (size) { |
1182 | case 1: return 'b'; break; | |
1183 | case 2: return 'w'; break; | |
1184 | case 4: return 'd'; break; | |
1185 | default: | |
1186 | return 'x'; | |
1187 | break; | |
1188 | } | |
8170028d TS |
1189 | } |
1190 | #endif | |
1191 | ||
30abcfc7 | 1192 | static inline unsigned int memsize_z(DisasContext *dc) |
8170028d | 1193 | { |
7b5eff4d | 1194 | return dc->zsize + 1; |
8170028d TS |
1195 | } |
1196 | ||
30abcfc7 | 1197 | static inline unsigned int memsize_zz(DisasContext *dc) |
8170028d | 1198 | { |
7b5eff4d EV |
1199 | switch (dc->zzsize) { |
1200 | case 0: return 1; | |
1201 | case 1: return 2; | |
1202 | default: | |
1203 | return 4; | |
1204 | } | |
8170028d TS |
1205 | } |
1206 | ||
c7d05695 | 1207 | static inline void do_postinc (DisasContext *dc, int size) |
8170028d | 1208 | { |
7b5eff4d EV |
1209 | if (dc->postinc) { |
1210 | tcg_gen_addi_tl(cpu_R[dc->op1], cpu_R[dc->op1], size); | |
1211 | } | |
8170028d TS |
1212 | } |
1213 | ||
30abcfc7 | 1214 | static inline void dec_prep_move_r(DisasContext *dc, int rs, int rd, |
7b5eff4d | 1215 | int size, int s_ext, TCGv dst) |
8170028d | 1216 | { |
7b5eff4d EV |
1217 | if (s_ext) { |
1218 | t_gen_sext(dst, cpu_R[rs], size); | |
1219 | } else { | |
1220 | t_gen_zext(dst, cpu_R[rs], size); | |
1221 | } | |
8170028d TS |
1222 | } |
1223 | ||
1224 | /* Prepare T0 and T1 for a register alu operation. | |
1225 | s_ext decides if the operand1 should be sign-extended or zero-extended when | |
1226 | needed. */ | |
1227 | static void dec_prep_alu_r(DisasContext *dc, int rs, int rd, | |
7b5eff4d | 1228 | int size, int s_ext, TCGv dst, TCGv src) |
8170028d | 1229 | { |
7b5eff4d | 1230 | dec_prep_move_r(dc, rs, rd, size, s_ext, src); |
8170028d | 1231 | |
7b5eff4d EV |
1232 | if (s_ext) { |
1233 | t_gen_sext(dst, cpu_R[rd], size); | |
1234 | } else { | |
1235 | t_gen_zext(dst, cpu_R[rd], size); | |
1236 | } | |
8170028d TS |
1237 | } |
1238 | ||
cf7e0c80 AJ |
1239 | static int dec_prep_move_m(CPUCRISState *env, DisasContext *dc, |
1240 | int s_ext, int memsize, TCGv dst) | |
8170028d | 1241 | { |
7b5eff4d EV |
1242 | unsigned int rs; |
1243 | uint32_t imm; | |
1244 | int is_imm; | |
1245 | int insn_len = 2; | |
1246 | ||
1247 | rs = dc->op1; | |
1248 | is_imm = rs == 15 && dc->postinc; | |
1249 | ||
1250 | /* Load [$rs] onto T1. */ | |
1251 | if (is_imm) { | |
1252 | insn_len = 2 + memsize; | |
1253 | if (memsize == 1) { | |
1254 | insn_len++; | |
1255 | } | |
1256 | ||
1257 | imm = cris_fetch(env, dc, dc->pc + 2, memsize, s_ext); | |
1258 | tcg_gen_movi_tl(dst, imm); | |
1259 | dc->postinc = 0; | |
1260 | } else { | |
1261 | cris_flush_cc_state(dc); | |
1262 | gen_load(dc, dst, cpu_R[rs], memsize, 0); | |
1263 | if (s_ext) { | |
1264 | t_gen_sext(dst, dst, memsize); | |
1265 | } else { | |
1266 | t_gen_zext(dst, dst, memsize); | |
1267 | } | |
1268 | } | |
1269 | return insn_len; | |
cf1d97f0 EI |
1270 | } |
1271 | ||
1272 | /* Prepare T0 and T1 for a memory + alu operation. | |
1273 | s_ext decides if the operand1 should be sign-extended or zero-extended when | |
1274 | needed. */ | |
cf7e0c80 AJ |
1275 | static int dec_prep_alu_m(CPUCRISState *env, DisasContext *dc, |
1276 | int s_ext, int memsize, TCGv dst, TCGv src) | |
cf1d97f0 | 1277 | { |
7b5eff4d | 1278 | int insn_len; |
cf1d97f0 | 1279 | |
7b5eff4d EV |
1280 | insn_len = dec_prep_move_m(env, dc, s_ext, memsize, src); |
1281 | tcg_gen_mov_tl(dst, cpu_R[dc->op2]); | |
1282 | return insn_len; | |
8170028d TS |
1283 | } |
1284 | ||
1285 | #if DISAS_CRIS | |
1286 | static const char *cc_name(int cc) | |
1287 | { | |
7b5eff4d EV |
1288 | static const char *cc_names[16] = { |
1289 | "cc", "cs", "ne", "eq", "vc", "vs", "pl", "mi", | |
1290 | "ls", "hi", "ge", "lt", "gt", "le", "a", "p" | |
1291 | }; | |
1292 | assert(cc < 16); | |
1293 | return cc_names[cc]; | |
8170028d TS |
1294 | } |
1295 | #endif | |
1296 | ||
b41f7df0 EI |
1297 | /* Start of insn decoders. */ |
1298 | ||
cf7e0c80 | 1299 | static int dec_bccq(CPUCRISState *env, DisasContext *dc) |
8170028d | 1300 | { |
7b5eff4d EV |
1301 | int32_t offset; |
1302 | int sign; | |
1303 | uint32_t cond = dc->op2; | |
8170028d | 1304 | |
7b5eff4d EV |
1305 | offset = EXTRACT_FIELD(dc->ir, 1, 7); |
1306 | sign = EXTRACT_FIELD(dc->ir, 0, 0); | |
8170028d | 1307 | |
7b5eff4d EV |
1308 | offset *= 2; |
1309 | offset |= sign << 8; | |
1310 | offset = sign_extend(offset, 8); | |
8170028d | 1311 | |
7b5eff4d | 1312 | LOG_DIS("b%s %x\n", cc_name(cond), dc->pc + offset); |
2a44f7f1 | 1313 | |
7b5eff4d EV |
1314 | /* op2 holds the condition-code. */ |
1315 | cris_cc_mask(dc, 0); | |
1316 | cris_prepare_cc_branch(dc, offset, cond); | |
1317 | return 2; | |
8170028d | 1318 | } |
cf7e0c80 | 1319 | static int dec_addoq(CPUCRISState *env, DisasContext *dc) |
8170028d | 1320 | { |
7b5eff4d | 1321 | int32_t imm; |
8170028d | 1322 | |
7b5eff4d EV |
1323 | dc->op1 = EXTRACT_FIELD(dc->ir, 0, 7); |
1324 | imm = sign_extend(dc->op1, 7); | |
8170028d | 1325 | |
7b5eff4d EV |
1326 | LOG_DIS("addoq %d, $r%u\n", imm, dc->op2); |
1327 | cris_cc_mask(dc, 0); | |
1328 | /* Fetch register operand, */ | |
1329 | tcg_gen_addi_tl(cpu_R[R_ACR], cpu_R[dc->op2], imm); | |
fb48f71b | 1330 | |
7b5eff4d | 1331 | return 2; |
8170028d | 1332 | } |
cf7e0c80 | 1333 | static int dec_addq(CPUCRISState *env, DisasContext *dc) |
8170028d | 1334 | { |
7b5eff4d | 1335 | LOG_DIS("addq %u, $r%u\n", dc->op1, dc->op2); |
8170028d | 1336 | |
7b5eff4d | 1337 | dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5); |
8170028d | 1338 | |
7b5eff4d | 1339 | cris_cc_mask(dc, CC_MASK_NZVC); |
30abcfc7 | 1340 | |
7b5eff4d EV |
1341 | cris_alu(dc, CC_OP_ADD, |
1342 | cpu_R[dc->op2], cpu_R[dc->op2], tcg_const_tl(dc->op1), 4); | |
1343 | return 2; | |
8170028d | 1344 | } |
cf7e0c80 | 1345 | static int dec_moveq(CPUCRISState *env, DisasContext *dc) |
8170028d | 1346 | { |
7b5eff4d | 1347 | uint32_t imm; |
8170028d | 1348 | |
7b5eff4d EV |
1349 | dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5); |
1350 | imm = sign_extend(dc->op1, 5); | |
1351 | LOG_DIS("moveq %d, $r%u\n", imm, dc->op2); | |
8170028d | 1352 | |
7b5eff4d EV |
1353 | tcg_gen_movi_tl(cpu_R[dc->op2], imm); |
1354 | return 2; | |
8170028d | 1355 | } |
cf7e0c80 | 1356 | static int dec_subq(CPUCRISState *env, DisasContext *dc) |
8170028d | 1357 | { |
7b5eff4d | 1358 | dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5); |
8170028d | 1359 | |
7b5eff4d | 1360 | LOG_DIS("subq %u, $r%u\n", dc->op1, dc->op2); |
8170028d | 1361 | |
7b5eff4d EV |
1362 | cris_cc_mask(dc, CC_MASK_NZVC); |
1363 | cris_alu(dc, CC_OP_SUB, | |
1364 | cpu_R[dc->op2], cpu_R[dc->op2], tcg_const_tl(dc->op1), 4); | |
1365 | return 2; | |
8170028d | 1366 | } |
cf7e0c80 | 1367 | static int dec_cmpq(CPUCRISState *env, DisasContext *dc) |
8170028d | 1368 | { |
7b5eff4d EV |
1369 | uint32_t imm; |
1370 | dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5); | |
1371 | imm = sign_extend(dc->op1, 5); | |
8170028d | 1372 | |
7b5eff4d EV |
1373 | LOG_DIS("cmpq %d, $r%d\n", imm, dc->op2); |
1374 | cris_cc_mask(dc, CC_MASK_NZVC); | |
30abcfc7 | 1375 | |
7b5eff4d EV |
1376 | cris_alu(dc, CC_OP_CMP, |
1377 | cpu_R[dc->op2], cpu_R[dc->op2], tcg_const_tl(imm), 4); | |
1378 | return 2; | |
8170028d | 1379 | } |
cf7e0c80 | 1380 | static int dec_andq(CPUCRISState *env, DisasContext *dc) |
8170028d | 1381 | { |
7b5eff4d EV |
1382 | uint32_t imm; |
1383 | dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5); | |
1384 | imm = sign_extend(dc->op1, 5); | |
8170028d | 1385 | |
7b5eff4d EV |
1386 | LOG_DIS("andq %d, $r%d\n", imm, dc->op2); |
1387 | cris_cc_mask(dc, CC_MASK_NZ); | |
30abcfc7 | 1388 | |
7b5eff4d EV |
1389 | cris_alu(dc, CC_OP_AND, |
1390 | cpu_R[dc->op2], cpu_R[dc->op2], tcg_const_tl(imm), 4); | |
1391 | return 2; | |
8170028d | 1392 | } |
cf7e0c80 | 1393 | static int dec_orq(CPUCRISState *env, DisasContext *dc) |
8170028d | 1394 | { |
7b5eff4d EV |
1395 | uint32_t imm; |
1396 | dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5); | |
1397 | imm = sign_extend(dc->op1, 5); | |
1398 | LOG_DIS("orq %d, $r%d\n", imm, dc->op2); | |
1399 | cris_cc_mask(dc, CC_MASK_NZ); | |
30abcfc7 | 1400 | |
7b5eff4d EV |
1401 | cris_alu(dc, CC_OP_OR, |
1402 | cpu_R[dc->op2], cpu_R[dc->op2], tcg_const_tl(imm), 4); | |
1403 | return 2; | |
8170028d | 1404 | } |
cf7e0c80 | 1405 | static int dec_btstq(CPUCRISState *env, DisasContext *dc) |
8170028d | 1406 | { |
7b5eff4d EV |
1407 | dc->op1 = EXTRACT_FIELD(dc->ir, 0, 4); |
1408 | LOG_DIS("btstq %u, $r%d\n", dc->op1, dc->op2); | |
17ac9754 | 1409 | |
7b5eff4d EV |
1410 | cris_cc_mask(dc, CC_MASK_NZ); |
1411 | cris_evaluate_flags(dc); | |
febc9920 | 1412 | gen_helper_btst(cpu_PR[PR_CCS], cpu_env, cpu_R[dc->op2], |
7b5eff4d EV |
1413 | tcg_const_tl(dc->op1), cpu_PR[PR_CCS]); |
1414 | cris_alu(dc, CC_OP_MOVE, | |
1415 | cpu_R[dc->op2], cpu_R[dc->op2], cpu_R[dc->op2], 4); | |
1416 | cris_update_cc_op(dc, CC_OP_FLAGS, 4); | |
1417 | dc->flags_uptodate = 1; | |
1418 | return 2; | |
8170028d | 1419 | } |
cf7e0c80 | 1420 | static int dec_asrq(CPUCRISState *env, DisasContext *dc) |
8170028d | 1421 | { |
7b5eff4d EV |
1422 | dc->op1 = EXTRACT_FIELD(dc->ir, 0, 4); |
1423 | LOG_DIS("asrq %u, $r%d\n", dc->op1, dc->op2); | |
1424 | cris_cc_mask(dc, CC_MASK_NZ); | |
30abcfc7 | 1425 | |
7b5eff4d EV |
1426 | tcg_gen_sari_tl(cpu_R[dc->op2], cpu_R[dc->op2], dc->op1); |
1427 | cris_alu(dc, CC_OP_MOVE, | |
1428 | cpu_R[dc->op2], | |
1429 | cpu_R[dc->op2], cpu_R[dc->op2], 4); | |
1430 | return 2; | |
8170028d | 1431 | } |
cf7e0c80 | 1432 | static int dec_lslq(CPUCRISState *env, DisasContext *dc) |
8170028d | 1433 | { |
7b5eff4d EV |
1434 | dc->op1 = EXTRACT_FIELD(dc->ir, 0, 4); |
1435 | LOG_DIS("lslq %u, $r%d\n", dc->op1, dc->op2); | |
8170028d | 1436 | |
7b5eff4d | 1437 | cris_cc_mask(dc, CC_MASK_NZ); |
30abcfc7 | 1438 | |
7b5eff4d | 1439 | tcg_gen_shli_tl(cpu_R[dc->op2], cpu_R[dc->op2], dc->op1); |
2a44f7f1 | 1440 | |
7b5eff4d EV |
1441 | cris_alu(dc, CC_OP_MOVE, |
1442 | cpu_R[dc->op2], | |
1443 | cpu_R[dc->op2], cpu_R[dc->op2], 4); | |
1444 | return 2; | |
8170028d | 1445 | } |
cf7e0c80 | 1446 | static int dec_lsrq(CPUCRISState *env, DisasContext *dc) |
8170028d | 1447 | { |
7b5eff4d EV |
1448 | dc->op1 = EXTRACT_FIELD(dc->ir, 0, 4); |
1449 | LOG_DIS("lsrq %u, $r%d\n", dc->op1, dc->op2); | |
8170028d | 1450 | |
7b5eff4d | 1451 | cris_cc_mask(dc, CC_MASK_NZ); |
30abcfc7 | 1452 | |
7b5eff4d EV |
1453 | tcg_gen_shri_tl(cpu_R[dc->op2], cpu_R[dc->op2], dc->op1); |
1454 | cris_alu(dc, CC_OP_MOVE, | |
1455 | cpu_R[dc->op2], | |
1456 | cpu_R[dc->op2], cpu_R[dc->op2], 4); | |
1457 | return 2; | |
8170028d TS |
1458 | } |
1459 | ||
cf7e0c80 | 1460 | static int dec_move_r(CPUCRISState *env, DisasContext *dc) |
8170028d | 1461 | { |
7b5eff4d EV |
1462 | int size = memsize_zz(dc); |
1463 | ||
1464 | LOG_DIS("move.%c $r%u, $r%u\n", | |
1465 | memsize_char(size), dc->op1, dc->op2); | |
1466 | ||
1467 | cris_cc_mask(dc, CC_MASK_NZ); | |
1468 | if (size == 4) { | |
1469 | dec_prep_move_r(dc, dc->op1, dc->op2, size, 0, cpu_R[dc->op2]); | |
1470 | cris_cc_mask(dc, CC_MASK_NZ); | |
1471 | cris_update_cc_op(dc, CC_OP_MOVE, 4); | |
1472 | cris_update_cc_x(dc); | |
1473 | cris_update_result(dc, cpu_R[dc->op2]); | |
1474 | } else { | |
1475 | TCGv t0; | |
1476 | ||
1477 | t0 = tcg_temp_new(); | |
1478 | dec_prep_move_r(dc, dc->op1, dc->op2, size, 0, t0); | |
1479 | cris_alu(dc, CC_OP_MOVE, | |
1480 | cpu_R[dc->op2], | |
1481 | cpu_R[dc->op2], t0, size); | |
1482 | tcg_temp_free(t0); | |
1483 | } | |
1484 | return 2; | |
8170028d TS |
1485 | } |
1486 | ||
cf7e0c80 | 1487 | static int dec_scc_r(CPUCRISState *env, DisasContext *dc) |
8170028d | 1488 | { |
7b5eff4d | 1489 | int cond = dc->op2; |
8170028d | 1490 | |
7b5eff4d EV |
1491 | LOG_DIS("s%s $r%u\n", |
1492 | cc_name(cond), dc->op1); | |
8170028d | 1493 | |
7b5eff4d EV |
1494 | if (cond != CC_A) { |
1495 | int l1; | |
dceaf394 | 1496 | |
7b5eff4d EV |
1497 | gen_tst_cc(dc, cpu_R[dc->op1], cond); |
1498 | l1 = gen_new_label(); | |
1499 | tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_R[dc->op1], 0, l1); | |
1500 | tcg_gen_movi_tl(cpu_R[dc->op1], 1); | |
1501 | gen_set_label(l1); | |
1502 | } else { | |
1503 | tcg_gen_movi_tl(cpu_R[dc->op1], 1); | |
1504 | } | |
8170028d | 1505 | |
7b5eff4d EV |
1506 | cris_cc_mask(dc, 0); |
1507 | return 2; | |
8170028d TS |
1508 | } |
1509 | ||
fb48f71b EI |
1510 | static inline void cris_alu_alloc_temps(DisasContext *dc, int size, TCGv *t) |
1511 | { | |
7b5eff4d EV |
1512 | if (size == 4) { |
1513 | t[0] = cpu_R[dc->op2]; | |
1514 | t[1] = cpu_R[dc->op1]; | |
1515 | } else { | |
1516 | t[0] = tcg_temp_new(); | |
1517 | t[1] = tcg_temp_new(); | |
1518 | } | |
fb48f71b EI |
1519 | } |
1520 | ||
1521 | static inline void cris_alu_free_temps(DisasContext *dc, int size, TCGv *t) | |
1522 | { | |
7b5eff4d EV |
1523 | if (size != 4) { |
1524 | tcg_temp_free(t[0]); | |
1525 | tcg_temp_free(t[1]); | |
1526 | } | |
fb48f71b EI |
1527 | } |
1528 | ||
cf7e0c80 | 1529 | static int dec_and_r(CPUCRISState *env, DisasContext *dc) |
8170028d | 1530 | { |
7b5eff4d EV |
1531 | TCGv t[2]; |
1532 | int size = memsize_zz(dc); | |
8170028d | 1533 | |
7b5eff4d EV |
1534 | LOG_DIS("and.%c $r%u, $r%u\n", |
1535 | memsize_char(size), dc->op1, dc->op2); | |
fb48f71b | 1536 | |
7b5eff4d | 1537 | cris_cc_mask(dc, CC_MASK_NZ); |
30abcfc7 | 1538 | |
7b5eff4d EV |
1539 | cris_alu_alloc_temps(dc, size, t); |
1540 | dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]); | |
1541 | cris_alu(dc, CC_OP_AND, cpu_R[dc->op2], t[0], t[1], size); | |
1542 | cris_alu_free_temps(dc, size, t); | |
1543 | return 2; | |
8170028d TS |
1544 | } |
1545 | ||
cf7e0c80 | 1546 | static int dec_lz_r(CPUCRISState *env, DisasContext *dc) |
8170028d | 1547 | { |
7b5eff4d EV |
1548 | TCGv t0; |
1549 | LOG_DIS("lz $r%u, $r%u\n", | |
1550 | dc->op1, dc->op2); | |
1551 | cris_cc_mask(dc, CC_MASK_NZ); | |
1552 | t0 = tcg_temp_new(); | |
1553 | dec_prep_alu_r(dc, dc->op1, dc->op2, 4, 0, cpu_R[dc->op2], t0); | |
1554 | cris_alu(dc, CC_OP_LZ, cpu_R[dc->op2], cpu_R[dc->op2], t0, 4); | |
1555 | tcg_temp_free(t0); | |
1556 | return 2; | |
8170028d TS |
1557 | } |
1558 | ||
cf7e0c80 | 1559 | static int dec_lsl_r(CPUCRISState *env, DisasContext *dc) |
8170028d | 1560 | { |
7b5eff4d EV |
1561 | TCGv t[2]; |
1562 | int size = memsize_zz(dc); | |
8170028d | 1563 | |
7b5eff4d EV |
1564 | LOG_DIS("lsl.%c $r%u, $r%u\n", |
1565 | memsize_char(size), dc->op1, dc->op2); | |
30abcfc7 | 1566 | |
7b5eff4d EV |
1567 | cris_cc_mask(dc, CC_MASK_NZ); |
1568 | cris_alu_alloc_temps(dc, size, t); | |
1569 | dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]); | |
1570 | tcg_gen_andi_tl(t[1], t[1], 63); | |
1571 | cris_alu(dc, CC_OP_LSL, cpu_R[dc->op2], t[0], t[1], size); | |
1572 | cris_alu_alloc_temps(dc, size, t); | |
1573 | return 2; | |
8170028d TS |
1574 | } |
1575 | ||
cf7e0c80 | 1576 | static int dec_lsr_r(CPUCRISState *env, DisasContext *dc) |
8170028d | 1577 | { |
7b5eff4d EV |
1578 | TCGv t[2]; |
1579 | int size = memsize_zz(dc); | |
8170028d | 1580 | |
7b5eff4d EV |
1581 | LOG_DIS("lsr.%c $r%u, $r%u\n", |
1582 | memsize_char(size), dc->op1, dc->op2); | |
30abcfc7 | 1583 | |
7b5eff4d EV |
1584 | cris_cc_mask(dc, CC_MASK_NZ); |
1585 | cris_alu_alloc_temps(dc, size, t); | |
1586 | dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]); | |
1587 | tcg_gen_andi_tl(t[1], t[1], 63); | |
1588 | cris_alu(dc, CC_OP_LSR, cpu_R[dc->op2], t[0], t[1], size); | |
1589 | cris_alu_free_temps(dc, size, t); | |
1590 | return 2; | |
8170028d TS |
1591 | } |
1592 | ||
cf7e0c80 | 1593 | static int dec_asr_r(CPUCRISState *env, DisasContext *dc) |
8170028d | 1594 | { |
7b5eff4d EV |
1595 | TCGv t[2]; |
1596 | int size = memsize_zz(dc); | |
8170028d | 1597 | |
7b5eff4d EV |
1598 | LOG_DIS("asr.%c $r%u, $r%u\n", |
1599 | memsize_char(size), dc->op1, dc->op2); | |
30abcfc7 | 1600 | |
7b5eff4d EV |
1601 | cris_cc_mask(dc, CC_MASK_NZ); |
1602 | cris_alu_alloc_temps(dc, size, t); | |
1603 | dec_prep_alu_r(dc, dc->op1, dc->op2, size, 1, t[0], t[1]); | |
1604 | tcg_gen_andi_tl(t[1], t[1], 63); | |
1605 | cris_alu(dc, CC_OP_ASR, cpu_R[dc->op2], t[0], t[1], size); | |
1606 | cris_alu_free_temps(dc, size, t); | |
1607 | return 2; | |
8170028d TS |
1608 | } |
1609 | ||
cf7e0c80 | 1610 | static int dec_muls_r(CPUCRISState *env, DisasContext *dc) |
8170028d | 1611 | { |
7b5eff4d EV |
1612 | TCGv t[2]; |
1613 | int size = memsize_zz(dc); | |
8170028d | 1614 | |
7b5eff4d EV |
1615 | LOG_DIS("muls.%c $r%u, $r%u\n", |
1616 | memsize_char(size), dc->op1, dc->op2); | |
1617 | cris_cc_mask(dc, CC_MASK_NZV); | |
1618 | cris_alu_alloc_temps(dc, size, t); | |
1619 | dec_prep_alu_r(dc, dc->op1, dc->op2, size, 1, t[0], t[1]); | |
30abcfc7 | 1620 | |
7b5eff4d EV |
1621 | cris_alu(dc, CC_OP_MULS, cpu_R[dc->op2], t[0], t[1], 4); |
1622 | cris_alu_free_temps(dc, size, t); | |
1623 | return 2; | |
8170028d TS |
1624 | } |
1625 | ||
cf7e0c80 | 1626 | static int dec_mulu_r(CPUCRISState *env, DisasContext *dc) |
8170028d | 1627 | { |
7b5eff4d EV |
1628 | TCGv t[2]; |
1629 | int size = memsize_zz(dc); | |
8170028d | 1630 | |
7b5eff4d EV |
1631 | LOG_DIS("mulu.%c $r%u, $r%u\n", |
1632 | memsize_char(size), dc->op1, dc->op2); | |
1633 | cris_cc_mask(dc, CC_MASK_NZV); | |
1634 | cris_alu_alloc_temps(dc, size, t); | |
1635 | dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]); | |
30abcfc7 | 1636 | |
7b5eff4d EV |
1637 | cris_alu(dc, CC_OP_MULU, cpu_R[dc->op2], t[0], t[1], 4); |
1638 | cris_alu_alloc_temps(dc, size, t); | |
1639 | return 2; | |
8170028d TS |
1640 | } |
1641 | ||
1642 | ||
cf7e0c80 | 1643 | static int dec_dstep_r(CPUCRISState *env, DisasContext *dc) |
8170028d | 1644 | { |
7b5eff4d EV |
1645 | LOG_DIS("dstep $r%u, $r%u\n", dc->op1, dc->op2); |
1646 | cris_cc_mask(dc, CC_MASK_NZ); | |
1647 | cris_alu(dc, CC_OP_DSTEP, | |
1648 | cpu_R[dc->op2], cpu_R[dc->op2], cpu_R[dc->op1], 4); | |
1649 | return 2; | |
8170028d TS |
1650 | } |
1651 | ||
cf7e0c80 | 1652 | static int dec_xor_r(CPUCRISState *env, DisasContext *dc) |
8170028d | 1653 | { |
7b5eff4d EV |
1654 | TCGv t[2]; |
1655 | int size = memsize_zz(dc); | |
1656 | LOG_DIS("xor.%c $r%u, $r%u\n", | |
1657 | memsize_char(size), dc->op1, dc->op2); | |
1658 | BUG_ON(size != 4); /* xor is dword. */ | |
1659 | cris_cc_mask(dc, CC_MASK_NZ); | |
1660 | cris_alu_alloc_temps(dc, size, t); | |
1661 | dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]); | |
30abcfc7 | 1662 | |
7b5eff4d EV |
1663 | cris_alu(dc, CC_OP_XOR, cpu_R[dc->op2], t[0], t[1], 4); |
1664 | cris_alu_free_temps(dc, size, t); | |
1665 | return 2; | |
8170028d TS |
1666 | } |
1667 | ||
cf7e0c80 | 1668 | static int dec_bound_r(CPUCRISState *env, DisasContext *dc) |
8170028d | 1669 | { |
7b5eff4d EV |
1670 | TCGv l0; |
1671 | int size = memsize_zz(dc); | |
1672 | LOG_DIS("bound.%c $r%u, $r%u\n", | |
1673 | memsize_char(size), dc->op1, dc->op2); | |
1674 | cris_cc_mask(dc, CC_MASK_NZ); | |
1675 | l0 = tcg_temp_local_new(); | |
1676 | dec_prep_move_r(dc, dc->op1, dc->op2, size, 0, l0); | |
1677 | cris_alu(dc, CC_OP_BOUND, cpu_R[dc->op2], cpu_R[dc->op2], l0, 4); | |
1678 | tcg_temp_free(l0); | |
1679 | return 2; | |
8170028d TS |
1680 | } |
1681 | ||
cf7e0c80 | 1682 | static int dec_cmp_r(CPUCRISState *env, DisasContext *dc) |
8170028d | 1683 | { |
7b5eff4d EV |
1684 | TCGv t[2]; |
1685 | int size = memsize_zz(dc); | |
1686 | LOG_DIS("cmp.%c $r%u, $r%u\n", | |
1687 | memsize_char(size), dc->op1, dc->op2); | |
1688 | cris_cc_mask(dc, CC_MASK_NZVC); | |
1689 | cris_alu_alloc_temps(dc, size, t); | |
1690 | dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]); | |
30abcfc7 | 1691 | |
7b5eff4d EV |
1692 | cris_alu(dc, CC_OP_CMP, cpu_R[dc->op2], t[0], t[1], size); |
1693 | cris_alu_free_temps(dc, size, t); | |
1694 | return 2; | |
8170028d TS |
1695 | } |
1696 | ||
cf7e0c80 | 1697 | static int dec_abs_r(CPUCRISState *env, DisasContext *dc) |
8170028d | 1698 | { |
7b5eff4d | 1699 | TCGv t0; |
3157a0a9 | 1700 | |
7b5eff4d EV |
1701 | LOG_DIS("abs $r%u, $r%u\n", |
1702 | dc->op1, dc->op2); | |
1703 | cris_cc_mask(dc, CC_MASK_NZ); | |
3157a0a9 | 1704 | |
7b5eff4d EV |
1705 | t0 = tcg_temp_new(); |
1706 | tcg_gen_sari_tl(t0, cpu_R[dc->op1], 31); | |
1707 | tcg_gen_xor_tl(cpu_R[dc->op2], cpu_R[dc->op1], t0); | |
1708 | tcg_gen_sub_tl(cpu_R[dc->op2], cpu_R[dc->op2], t0); | |
1709 | tcg_temp_free(t0); | |
7dcfb089 | 1710 | |
7b5eff4d EV |
1711 | cris_alu(dc, CC_OP_MOVE, |
1712 | cpu_R[dc->op2], cpu_R[dc->op2], cpu_R[dc->op2], 4); | |
1713 | return 2; | |
8170028d TS |
1714 | } |
1715 | ||
cf7e0c80 | 1716 | static int dec_add_r(CPUCRISState *env, DisasContext *dc) |
8170028d | 1717 | { |
7b5eff4d EV |
1718 | TCGv t[2]; |
1719 | int size = memsize_zz(dc); | |
1720 | LOG_DIS("add.%c $r%u, $r%u\n", | |
1721 | memsize_char(size), dc->op1, dc->op2); | |
1722 | cris_cc_mask(dc, CC_MASK_NZVC); | |
1723 | cris_alu_alloc_temps(dc, size, t); | |
1724 | dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]); | |
30abcfc7 | 1725 | |
7b5eff4d EV |
1726 | cris_alu(dc, CC_OP_ADD, cpu_R[dc->op2], t[0], t[1], size); |
1727 | cris_alu_free_temps(dc, size, t); | |
1728 | return 2; | |
8170028d TS |
1729 | } |
1730 | ||
cf7e0c80 | 1731 | static int dec_addc_r(CPUCRISState *env, DisasContext *dc) |
8170028d | 1732 | { |
7b5eff4d EV |
1733 | LOG_DIS("addc $r%u, $r%u\n", |
1734 | dc->op1, dc->op2); | |
1735 | cris_evaluate_flags(dc); | |
1736 | /* Set for this insn. */ | |
1737 | dc->flagx_known = 1; | |
1738 | dc->flags_x = X_FLAG; | |
a8cf66bb | 1739 | |
7b5eff4d EV |
1740 | cris_cc_mask(dc, CC_MASK_NZVC); |
1741 | cris_alu(dc, CC_OP_ADDC, | |
1742 | cpu_R[dc->op2], cpu_R[dc->op2], cpu_R[dc->op1], 4); | |
1743 | return 2; | |
8170028d TS |
1744 | } |
1745 | ||
cf7e0c80 | 1746 | static int dec_mcp_r(CPUCRISState *env, DisasContext *dc) |
8170028d | 1747 | { |
7b5eff4d EV |
1748 | LOG_DIS("mcp $p%u, $r%u\n", |
1749 | dc->op2, dc->op1); | |
1750 | cris_evaluate_flags(dc); | |
1751 | cris_cc_mask(dc, CC_MASK_RNZV); | |
1752 | cris_alu(dc, CC_OP_MCP, | |
1753 | cpu_R[dc->op1], cpu_R[dc->op1], cpu_PR[dc->op2], 4); | |
1754 | return 2; | |
8170028d TS |
1755 | } |
1756 | ||
1757 | #if DISAS_CRIS | |
1758 | static char * swapmode_name(int mode, char *modename) { | |
7b5eff4d EV |
1759 | int i = 0; |
1760 | if (mode & 8) { | |
1761 | modename[i++] = 'n'; | |
1762 | } | |
1763 | if (mode & 4) { | |
1764 | modename[i++] = 'w'; | |
1765 | } | |
1766 | if (mode & 2) { | |
1767 | modename[i++] = 'b'; | |
1768 | } | |
1769 | if (mode & 1) { | |
1770 | modename[i++] = 'r'; | |
1771 | } | |
1772 | modename[i++] = 0; | |
1773 | return modename; | |
8170028d TS |
1774 | } |
1775 | #endif | |
1776 | ||
cf7e0c80 | 1777 | static int dec_swap_r(CPUCRISState *env, DisasContext *dc) |
8170028d | 1778 | { |
7b5eff4d | 1779 | TCGv t0; |
cf1d97f0 | 1780 | #if DISAS_CRIS |
7b5eff4d | 1781 | char modename[4]; |
cf1d97f0 | 1782 | #endif |
7b5eff4d EV |
1783 | LOG_DIS("swap%s $r%u\n", |
1784 | swapmode_name(dc->op2, modename), dc->op1); | |
1785 | ||
1786 | cris_cc_mask(dc, CC_MASK_NZ); | |
1787 | t0 = tcg_temp_new(); | |
08397c4b | 1788 | tcg_gen_mov_tl(t0, cpu_R[dc->op1]); |
7b5eff4d EV |
1789 | if (dc->op2 & 8) { |
1790 | tcg_gen_not_tl(t0, t0); | |
1791 | } | |
1792 | if (dc->op2 & 4) { | |
1793 | t_gen_swapw(t0, t0); | |
1794 | } | |
1795 | if (dc->op2 & 2) { | |
1796 | t_gen_swapb(t0, t0); | |
1797 | } | |
1798 | if (dc->op2 & 1) { | |
1799 | t_gen_swapr(t0, t0); | |
1800 | } | |
1801 | cris_alu(dc, CC_OP_MOVE, cpu_R[dc->op1], cpu_R[dc->op1], t0, 4); | |
1802 | tcg_temp_free(t0); | |
1803 | return 2; | |
8170028d TS |
1804 | } |
1805 | ||
cf7e0c80 | 1806 | static int dec_or_r(CPUCRISState *env, DisasContext *dc) |
8170028d | 1807 | { |
7b5eff4d EV |
1808 | TCGv t[2]; |
1809 | int size = memsize_zz(dc); | |
1810 | LOG_DIS("or.%c $r%u, $r%u\n", | |
1811 | memsize_char(size), dc->op1, dc->op2); | |
1812 | cris_cc_mask(dc, CC_MASK_NZ); | |
1813 | cris_alu_alloc_temps(dc, size, t); | |
1814 | dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]); | |
1815 | cris_alu(dc, CC_OP_OR, cpu_R[dc->op2], t[0], t[1], size); | |
1816 | cris_alu_free_temps(dc, size, t); | |
1817 | return 2; | |
8170028d TS |
1818 | } |
1819 | ||
cf7e0c80 | 1820 | static int dec_addi_r(CPUCRISState *env, DisasContext *dc) |
8170028d | 1821 | { |
7b5eff4d EV |
1822 | TCGv t0; |
1823 | LOG_DIS("addi.%c $r%u, $r%u\n", | |
1824 | memsize_char(memsize_zz(dc)), dc->op2, dc->op1); | |
1825 | cris_cc_mask(dc, 0); | |
1826 | t0 = tcg_temp_new(); | |
1827 | tcg_gen_shl_tl(t0, cpu_R[dc->op2], tcg_const_tl(dc->zzsize)); | |
1828 | tcg_gen_add_tl(cpu_R[dc->op1], cpu_R[dc->op1], t0); | |
1829 | tcg_temp_free(t0); | |
1830 | return 2; | |
8170028d TS |
1831 | } |
1832 | ||
cf7e0c80 | 1833 | static int dec_addi_acr(CPUCRISState *env, DisasContext *dc) |
8170028d | 1834 | { |
7b5eff4d EV |
1835 | TCGv t0; |
1836 | LOG_DIS("addi.%c $r%u, $r%u, $acr\n", | |
1837 | memsize_char(memsize_zz(dc)), dc->op2, dc->op1); | |
1838 | cris_cc_mask(dc, 0); | |
1839 | t0 = tcg_temp_new(); | |
1840 | tcg_gen_shl_tl(t0, cpu_R[dc->op2], tcg_const_tl(dc->zzsize)); | |
1841 | tcg_gen_add_tl(cpu_R[R_ACR], cpu_R[dc->op1], t0); | |
1842 | tcg_temp_free(t0); | |
1843 | return 2; | |
8170028d TS |
1844 | } |
1845 | ||
cf7e0c80 | 1846 | static int dec_neg_r(CPUCRISState *env, DisasContext *dc) |
8170028d | 1847 | { |
7b5eff4d EV |
1848 | TCGv t[2]; |
1849 | int size = memsize_zz(dc); | |
1850 | LOG_DIS("neg.%c $r%u, $r%u\n", | |
1851 | memsize_char(size), dc->op1, dc->op2); | |
1852 | cris_cc_mask(dc, CC_MASK_NZVC); | |
1853 | cris_alu_alloc_temps(dc, size, t); | |
1854 | dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]); | |
30abcfc7 | 1855 | |
7b5eff4d EV |
1856 | cris_alu(dc, CC_OP_NEG, cpu_R[dc->op2], t[0], t[1], size); |
1857 | cris_alu_free_temps(dc, size, t); | |
1858 | return 2; | |
8170028d TS |
1859 | } |
1860 | ||
cf7e0c80 | 1861 | static int dec_btst_r(CPUCRISState *env, DisasContext *dc) |
8170028d | 1862 | { |
7b5eff4d EV |
1863 | LOG_DIS("btst $r%u, $r%u\n", |
1864 | dc->op1, dc->op2); | |
1865 | cris_cc_mask(dc, CC_MASK_NZ); | |
1866 | cris_evaluate_flags(dc); | |
febc9920 | 1867 | gen_helper_btst(cpu_PR[PR_CCS], cpu_env, cpu_R[dc->op2], |
7b5eff4d EV |
1868 | cpu_R[dc->op1], cpu_PR[PR_CCS]); |
1869 | cris_alu(dc, CC_OP_MOVE, cpu_R[dc->op2], | |
1870 | cpu_R[dc->op2], cpu_R[dc->op2], 4); | |
1871 | cris_update_cc_op(dc, CC_OP_FLAGS, 4); | |
1872 | dc->flags_uptodate = 1; | |
1873 | return 2; | |
8170028d TS |
1874 | } |
1875 | ||
cf7e0c80 | 1876 | static int dec_sub_r(CPUCRISState *env, DisasContext *dc) |
8170028d | 1877 | { |
7b5eff4d EV |
1878 | TCGv t[2]; |
1879 | int size = memsize_zz(dc); | |
1880 | LOG_DIS("sub.%c $r%u, $r%u\n", | |
1881 | memsize_char(size), dc->op1, dc->op2); | |
1882 | cris_cc_mask(dc, CC_MASK_NZVC); | |
1883 | cris_alu_alloc_temps(dc, size, t); | |
1884 | dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]); | |
1885 | cris_alu(dc, CC_OP_SUB, cpu_R[dc->op2], t[0], t[1], size); | |
1886 | cris_alu_free_temps(dc, size, t); | |
1887 | return 2; | |
8170028d TS |
1888 | } |
1889 | ||
1890 | /* Zero extension. From size to dword. */ | |
cf7e0c80 | 1891 | static int dec_movu_r(CPUCRISState *env, DisasContext *dc) |
8170028d | 1892 | { |
7b5eff4d EV |
1893 | TCGv t0; |
1894 | int size = memsize_z(dc); | |
1895 | LOG_DIS("movu.%c $r%u, $r%u\n", | |
1896 | memsize_char(size), | |
1897 | dc->op1, dc->op2); | |
8170028d | 1898 | |
7b5eff4d EV |
1899 | cris_cc_mask(dc, CC_MASK_NZ); |
1900 | t0 = tcg_temp_new(); | |
1901 | dec_prep_move_r(dc, dc->op1, dc->op2, size, 0, t0); | |
1902 | cris_alu(dc, CC_OP_MOVE, cpu_R[dc->op2], cpu_R[dc->op2], t0, 4); | |
1903 | tcg_temp_free(t0); | |
1904 | return 2; | |
8170028d TS |
1905 | } |
1906 | ||
1907 | /* Sign extension. From size to dword. */ | |
cf7e0c80 | 1908 | static int dec_movs_r(CPUCRISState *env, DisasContext *dc) |
8170028d | 1909 | { |
7b5eff4d EV |
1910 | TCGv t0; |
1911 | int size = memsize_z(dc); | |
1912 | LOG_DIS("movs.%c $r%u, $r%u\n", | |
1913 | memsize_char(size), | |
1914 | dc->op1, dc->op2); | |
8170028d | 1915 | |
7b5eff4d EV |
1916 | cris_cc_mask(dc, CC_MASK_NZ); |
1917 | t0 = tcg_temp_new(); | |
1918 | /* Size can only be qi or hi. */ | |
1919 | t_gen_sext(t0, cpu_R[dc->op1], size); | |
1920 | cris_alu(dc, CC_OP_MOVE, | |
1921 | cpu_R[dc->op2], cpu_R[dc->op1], t0, 4); | |
1922 | tcg_temp_free(t0); | |
1923 | return 2; | |
8170028d TS |
1924 | } |
1925 | ||
1926 | /* zero extension. From size to dword. */ | |
cf7e0c80 | 1927 | static int dec_addu_r(CPUCRISState *env, DisasContext *dc) |
8170028d | 1928 | { |
7b5eff4d EV |
1929 | TCGv t0; |
1930 | int size = memsize_z(dc); | |
1931 | LOG_DIS("addu.%c $r%u, $r%u\n", | |
1932 | memsize_char(size), | |
1933 | dc->op1, dc->op2); | |
8170028d | 1934 | |
7b5eff4d EV |
1935 | cris_cc_mask(dc, CC_MASK_NZVC); |
1936 | t0 = tcg_temp_new(); | |
1937 | /* Size can only be qi or hi. */ | |
1938 | t_gen_zext(t0, cpu_R[dc->op1], size); | |
1939 | cris_alu(dc, CC_OP_ADD, cpu_R[dc->op2], cpu_R[dc->op2], t0, 4); | |
1940 | tcg_temp_free(t0); | |
1941 | return 2; | |
8170028d | 1942 | } |
05ba7d5f | 1943 | |
8170028d | 1944 | /* Sign extension. From size to dword. */ |
cf7e0c80 | 1945 | static int dec_adds_r(CPUCRISState *env, DisasContext *dc) |
8170028d | 1946 | { |
7b5eff4d EV |
1947 | TCGv t0; |
1948 | int size = memsize_z(dc); | |
1949 | LOG_DIS("adds.%c $r%u, $r%u\n", | |
1950 | memsize_char(size), | |
1951 | dc->op1, dc->op2); | |
8170028d | 1952 | |
7b5eff4d EV |
1953 | cris_cc_mask(dc, CC_MASK_NZVC); |
1954 | t0 = tcg_temp_new(); | |
1955 | /* Size can only be qi or hi. */ | |
1956 | t_gen_sext(t0, cpu_R[dc->op1], size); | |
1957 | cris_alu(dc, CC_OP_ADD, | |
1958 | cpu_R[dc->op2], cpu_R[dc->op2], t0, 4); | |
1959 | tcg_temp_free(t0); | |
1960 | return 2; | |
8170028d TS |
1961 | } |
1962 | ||
1963 | /* Zero extension. From size to dword. */ | |
cf7e0c80 | 1964 | static int dec_subu_r(CPUCRISState *env, DisasContext *dc) |
8170028d | 1965 | { |
7b5eff4d EV |
1966 | TCGv t0; |
1967 | int size = memsize_z(dc); | |
1968 | LOG_DIS("subu.%c $r%u, $r%u\n", | |
1969 | memsize_char(size), | |
1970 | dc->op1, dc->op2); | |
8170028d | 1971 | |
7b5eff4d EV |
1972 | cris_cc_mask(dc, CC_MASK_NZVC); |
1973 | t0 = tcg_temp_new(); | |
1974 | /* Size can only be qi or hi. */ | |
1975 | t_gen_zext(t0, cpu_R[dc->op1], size); | |
1976 | cris_alu(dc, CC_OP_SUB, | |
1977 | cpu_R[dc->op2], cpu_R[dc->op2], t0, 4); | |
1978 | tcg_temp_free(t0); | |
1979 | return 2; | |
8170028d TS |
1980 | } |
1981 | ||
1982 | /* Sign extension. From size to dword. */ | |
cf7e0c80 | 1983 | static int dec_subs_r(CPUCRISState *env, DisasContext *dc) |
8170028d | 1984 | { |
7b5eff4d EV |
1985 | TCGv t0; |
1986 | int size = memsize_z(dc); | |
1987 | LOG_DIS("subs.%c $r%u, $r%u\n", | |
1988 | memsize_char(size), | |
1989 | dc->op1, dc->op2); | |
8170028d | 1990 | |
7b5eff4d EV |
1991 | cris_cc_mask(dc, CC_MASK_NZVC); |
1992 | t0 = tcg_temp_new(); | |
1993 | /* Size can only be qi or hi. */ | |
1994 | t_gen_sext(t0, cpu_R[dc->op1], size); | |
1995 | cris_alu(dc, CC_OP_SUB, | |
1996 | cpu_R[dc->op2], cpu_R[dc->op2], t0, 4); | |
1997 | tcg_temp_free(t0); | |
1998 | return 2; | |
8170028d TS |
1999 | } |
2000 | ||
cf7e0c80 | 2001 | static int dec_setclrf(CPUCRISState *env, DisasContext *dc) |
8170028d | 2002 | { |
7b5eff4d EV |
2003 | uint32_t flags; |
2004 | int set = (~dc->opcode >> 2) & 1; | |
2005 | ||
2006 | ||
2007 | flags = (EXTRACT_FIELD(dc->ir, 12, 15) << 4) | |
2008 | | EXTRACT_FIELD(dc->ir, 0, 3); | |
2009 | if (set && flags == 0) { | |
2010 | LOG_DIS("nop\n"); | |
2011 | return 2; | |
2012 | } else if (!set && (flags & 0x20)) { | |
2013 | LOG_DIS("di\n"); | |
2014 | } else { | |
2015 | LOG_DIS("%sf %x\n", set ? "set" : "clr", flags); | |
2016 | } | |
2017 | ||
2018 | /* User space is not allowed to touch these. Silently ignore. */ | |
2019 | if (dc->tb_flags & U_FLAG) { | |
2020 | flags &= ~(S_FLAG | I_FLAG | U_FLAG); | |
2021 | } | |
2022 | ||
2023 | if (flags & X_FLAG) { | |
2024 | dc->flagx_known = 1; | |
2025 | if (set) { | |
2026 | dc->flags_x = X_FLAG; | |
2027 | } else { | |
2028 | dc->flags_x = 0; | |
2029 | } | |
2030 | } | |
2031 | ||
2032 | /* Break the TB if any of the SPI flag changes. */ | |
2033 | if (flags & (P_FLAG | S_FLAG)) { | |
2034 | tcg_gen_movi_tl(env_pc, dc->pc + 2); | |
2035 | dc->is_jmp = DISAS_UPDATE; | |
2036 | dc->cpustate_changed = 1; | |
2037 | } | |
2038 | ||
2039 | /* For the I flag, only act on posedge. */ | |
2040 | if ((flags & I_FLAG)) { | |
2041 | tcg_gen_movi_tl(env_pc, dc->pc + 2); | |
2042 | dc->is_jmp = DISAS_UPDATE; | |
2043 | dc->cpustate_changed = 1; | |
2044 | } | |
2045 | ||
2046 | ||
2047 | /* Simply decode the flags. */ | |
2048 | cris_evaluate_flags(dc); | |
2049 | cris_update_cc_op(dc, CC_OP_FLAGS, 4); | |
2050 | cris_update_cc_x(dc); | |
2051 | tcg_gen_movi_tl(cc_op, dc->cc_op); | |
2052 | ||
2053 | if (set) { | |
2054 | if (!(dc->tb_flags & U_FLAG) && (flags & U_FLAG)) { | |
2055 | /* Enter user mode. */ | |
2056 | t_gen_mov_env_TN(ksp, cpu_R[R_SP]); | |
2057 | tcg_gen_mov_tl(cpu_R[R_SP], cpu_PR[PR_USP]); | |
2058 | dc->cpustate_changed = 1; | |
2059 | } | |
2060 | tcg_gen_ori_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], flags); | |
2061 | } else { | |
2062 | tcg_gen_andi_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], ~flags); | |
2063 | } | |
2064 | ||
2065 | dc->flags_uptodate = 1; | |
2066 | dc->clear_x = 0; | |
2067 | return 2; | |
8170028d TS |
2068 | } |
2069 | ||
cf7e0c80 | 2070 | static int dec_move_rs(CPUCRISState *env, DisasContext *dc) |
8170028d | 2071 | { |
7b5eff4d EV |
2072 | LOG_DIS("move $r%u, $s%u\n", dc->op1, dc->op2); |
2073 | cris_cc_mask(dc, 0); | |
febc9920 AJ |
2074 | gen_helper_movl_sreg_reg(cpu_env, tcg_const_tl(dc->op2), |
2075 | tcg_const_tl(dc->op1)); | |
7b5eff4d | 2076 | return 2; |
8170028d | 2077 | } |
cf7e0c80 | 2078 | static int dec_move_sr(CPUCRISState *env, DisasContext *dc) |
8170028d | 2079 | { |
7b5eff4d EV |
2080 | LOG_DIS("move $s%u, $r%u\n", dc->op2, dc->op1); |
2081 | cris_cc_mask(dc, 0); | |
febc9920 AJ |
2082 | gen_helper_movl_reg_sreg(cpu_env, tcg_const_tl(dc->op1), |
2083 | tcg_const_tl(dc->op2)); | |
7b5eff4d | 2084 | return 2; |
8170028d | 2085 | } |
dceaf394 | 2086 | |
cf7e0c80 | 2087 | static int dec_move_rp(CPUCRISState *env, DisasContext *dc) |
8170028d | 2088 | { |
7b5eff4d EV |
2089 | TCGv t[2]; |
2090 | LOG_DIS("move $r%u, $p%u\n", dc->op1, dc->op2); | |
2091 | cris_cc_mask(dc, 0); | |
2092 | ||
2093 | t[0] = tcg_temp_new(); | |
2094 | if (dc->op2 == PR_CCS) { | |
2095 | cris_evaluate_flags(dc); | |
08397c4b | 2096 | tcg_gen_mov_tl(t[0], cpu_R[dc->op1]); |
7b5eff4d EV |
2097 | if (dc->tb_flags & U_FLAG) { |
2098 | t[1] = tcg_temp_new(); | |
2099 | /* User space is not allowed to touch all flags. */ | |
2100 | tcg_gen_andi_tl(t[0], t[0], 0x39f); | |
2101 | tcg_gen_andi_tl(t[1], cpu_PR[PR_CCS], ~0x39f); | |
2102 | tcg_gen_or_tl(t[0], t[1], t[0]); | |
2103 | tcg_temp_free(t[1]); | |
2104 | } | |
2105 | } else { | |
08397c4b | 2106 | tcg_gen_mov_tl(t[0], cpu_R[dc->op1]); |
7b5eff4d EV |
2107 | } |
2108 | ||
2109 | t_gen_mov_preg_TN(dc, dc->op2, t[0]); | |
2110 | if (dc->op2 == PR_CCS) { | |
2111 | cris_update_cc_op(dc, CC_OP_FLAGS, 4); | |
2112 | dc->flags_uptodate = 1; | |
2113 | } | |
2114 | tcg_temp_free(t[0]); | |
2115 | return 2; | |
8170028d | 2116 | } |
cf7e0c80 | 2117 | static int dec_move_pr(CPUCRISState *env, DisasContext *dc) |
8170028d | 2118 | { |
7b5eff4d EV |
2119 | TCGv t0; |
2120 | LOG_DIS("move $p%u, $r%u\n", dc->op2, dc->op1); | |
2121 | cris_cc_mask(dc, 0); | |
2a44f7f1 | 2122 | |
7b5eff4d EV |
2123 | if (dc->op2 == PR_CCS) { |
2124 | cris_evaluate_flags(dc); | |
2125 | } | |
2a44f7f1 | 2126 | |
7b5eff4d EV |
2127 | if (dc->op2 == PR_DZ) { |
2128 | tcg_gen_movi_tl(cpu_R[dc->op1], 0); | |
2129 | } else { | |
2130 | t0 = tcg_temp_new(); | |
2131 | t_gen_mov_TN_preg(t0, dc->op2); | |
2132 | cris_alu(dc, CC_OP_MOVE, | |
2133 | cpu_R[dc->op1], cpu_R[dc->op1], t0, | |
2134 | preg_sizes[dc->op2]); | |
2135 | tcg_temp_free(t0); | |
2136 | } | |
2137 | return 2; | |
8170028d TS |
2138 | } |
2139 | ||
cf7e0c80 | 2140 | static int dec_move_mr(CPUCRISState *env, DisasContext *dc) |
8170028d | 2141 | { |
7b5eff4d EV |
2142 | int memsize = memsize_zz(dc); |
2143 | int insn_len; | |
2144 | LOG_DIS("move.%c [$r%u%s, $r%u\n", | |
2145 | memsize_char(memsize), | |
2146 | dc->op1, dc->postinc ? "+]" : "]", | |
2147 | dc->op2); | |
2148 | ||
2149 | if (memsize == 4) { | |
2150 | insn_len = dec_prep_move_m(env, dc, 0, 4, cpu_R[dc->op2]); | |
2151 | cris_cc_mask(dc, CC_MASK_NZ); | |
2152 | cris_update_cc_op(dc, CC_OP_MOVE, 4); | |
2153 | cris_update_cc_x(dc); | |
2154 | cris_update_result(dc, cpu_R[dc->op2]); | |
2155 | } else { | |
2156 | TCGv t0; | |
2157 | ||
2158 | t0 = tcg_temp_new(); | |
2159 | insn_len = dec_prep_move_m(env, dc, 0, memsize, t0); | |
2160 | cris_cc_mask(dc, CC_MASK_NZ); | |
2161 | cris_alu(dc, CC_OP_MOVE, | |
2162 | cpu_R[dc->op2], cpu_R[dc->op2], t0, memsize); | |
2163 | tcg_temp_free(t0); | |
2164 | } | |
2165 | do_postinc(dc, memsize); | |
2166 | return insn_len; | |
8170028d TS |
2167 | } |
2168 | ||
31c18d87 EI |
2169 | static inline void cris_alu_m_alloc_temps(TCGv *t) |
2170 | { | |
7b5eff4d EV |
2171 | t[0] = tcg_temp_new(); |
2172 | t[1] = tcg_temp_new(); | |
31c18d87 EI |
2173 | } |
2174 | ||
2175 | static inline void cris_alu_m_free_temps(TCGv *t) | |
2176 | { | |
7b5eff4d EV |
2177 | tcg_temp_free(t[0]); |
2178 | tcg_temp_free(t[1]); | |
31c18d87 EI |
2179 | } |
2180 | ||
cf7e0c80 | 2181 | static int dec_movs_m(CPUCRISState *env, DisasContext *dc) |
8170028d | 2182 | { |
7b5eff4d EV |
2183 | TCGv t[2]; |
2184 | int memsize = memsize_z(dc); | |
2185 | int insn_len; | |
2186 | LOG_DIS("movs.%c [$r%u%s, $r%u\n", | |
2187 | memsize_char(memsize), | |
2188 | dc->op1, dc->postinc ? "+]" : "]", | |
2189 | dc->op2); | |
8170028d | 2190 | |
7b5eff4d EV |
2191 | cris_alu_m_alloc_temps(t); |
2192 | /* sign extend. */ | |
cf7e0c80 | 2193 | insn_len = dec_prep_alu_m(env, dc, 1, memsize, t[0], t[1]); |
7b5eff4d EV |
2194 | cris_cc_mask(dc, CC_MASK_NZ); |
2195 | cris_alu(dc, CC_OP_MOVE, | |
2196 | cpu_R[dc->op2], cpu_R[dc->op2], t[1], 4); | |
2197 | do_postinc(dc, memsize); | |
2198 | cris_alu_m_free_temps(t); | |
2199 | return insn_len; | |
8170028d TS |
2200 | } |
2201 | ||
cf7e0c80 | 2202 | static int dec_addu_m(CPUCRISState *env, DisasContext *dc) |
8170028d | 2203 | { |
7b5eff4d EV |
2204 | TCGv t[2]; |
2205 | int memsize = memsize_z(dc); | |
2206 | int insn_len; | |
2207 | LOG_DIS("addu.%c [$r%u%s, $r%u\n", | |
2208 | memsize_char(memsize), | |
2209 | dc->op1, dc->postinc ? "+]" : "]", | |
2210 | dc->op2); | |
8170028d | 2211 | |
7b5eff4d EV |
2212 | cris_alu_m_alloc_temps(t); |
2213 | /* sign extend. */ | |
cf7e0c80 | 2214 | insn_len = dec_prep_alu_m(env, dc, 0, memsize, t[0], t[1]); |
7b5eff4d EV |
2215 | cris_cc_mask(dc, CC_MASK_NZVC); |
2216 | cris_alu(dc, CC_OP_ADD, | |
2217 | cpu_R[dc->op2], cpu_R[dc->op2], t[1], 4); | |
2218 | do_postinc(dc, memsize); | |
2219 | cris_alu_m_free_temps(t); | |
2220 | return insn_len; | |
8170028d TS |
2221 | } |
2222 | ||
cf7e0c80 | 2223 | static int dec_adds_m(CPUCRISState *env, DisasContext *dc) |
8170028d | 2224 | { |
7b5eff4d EV |
2225 | TCGv t[2]; |
2226 | int memsize = memsize_z(dc); | |
2227 | int insn_len; | |
2228 | LOG_DIS("adds.%c [$r%u%s, $r%u\n", | |
2229 | memsize_char(memsize), | |
2230 | dc->op1, dc->postinc ? "+]" : "]", | |
2231 | dc->op2); | |
8170028d | 2232 | |
7b5eff4d EV |
2233 | cris_alu_m_alloc_temps(t); |
2234 | /* sign extend. */ | |
cf7e0c80 | 2235 | insn_len = dec_prep_alu_m(env, dc, 1, memsize, t[0], t[1]); |
7b5eff4d EV |
2236 | cris_cc_mask(dc, CC_MASK_NZVC); |
2237 | cris_alu(dc, CC_OP_ADD, cpu_R[dc->op2], cpu_R[dc->op2], t[1], 4); | |
2238 | do_postinc(dc, memsize); | |
2239 | cris_alu_m_free_temps(t); | |
2240 | return insn_len; | |
8170028d TS |
2241 | } |
2242 | ||
cf7e0c80 | 2243 | static int dec_subu_m(CPUCRISState *env, DisasContext *dc) |
8170028d | 2244 | { |
7b5eff4d EV |
2245 | TCGv t[2]; |
2246 | int memsize = memsize_z(dc); | |
2247 | int insn_len; | |
2248 | LOG_DIS("subu.%c [$r%u%s, $r%u\n", | |
2249 | memsize_char(memsize), | |
2250 | dc->op1, dc->postinc ? "+]" : "]", | |
2251 | dc->op2); | |
8170028d | 2252 | |
7b5eff4d EV |
2253 | cris_alu_m_alloc_temps(t); |
2254 | /* sign extend. */ | |
cf7e0c80 | 2255 | insn_len = dec_prep_alu_m(env, dc, 0, memsize, t[0], t[1]); |
7b5eff4d EV |
2256 | cris_cc_mask(dc, CC_MASK_NZVC); |
2257 | cris_alu(dc, CC_OP_SUB, cpu_R[dc->op2], cpu_R[dc->op2], t[1], 4); | |
2258 | do_postinc(dc, memsize); | |
2259 | cris_alu_m_free_temps(t); | |
2260 | return insn_len; | |
8170028d TS |
2261 | } |
2262 | ||
cf7e0c80 | 2263 | static int dec_subs_m(CPUCRISState *env, DisasContext *dc) |
8170028d | 2264 | { |
7b5eff4d EV |
2265 | TCGv t[2]; |
2266 | int memsize = memsize_z(dc); | |
2267 | int insn_len; | |
2268 | LOG_DIS("subs.%c [$r%u%s, $r%u\n", | |
2269 | memsize_char(memsize), | |
2270 | dc->op1, dc->postinc ? "+]" : "]", | |
2271 | dc->op2); | |
8170028d | 2272 | |
7b5eff4d EV |
2273 | cris_alu_m_alloc_temps(t); |
2274 | /* sign extend. */ | |
cf7e0c80 | 2275 | insn_len = dec_prep_alu_m(env, dc, 1, memsize, t[0], t[1]); |
7b5eff4d EV |
2276 | cris_cc_mask(dc, CC_MASK_NZVC); |
2277 | cris_alu(dc, CC_OP_SUB, cpu_R[dc->op2], cpu_R[dc->op2], t[1], 4); | |
2278 | do_postinc(dc, memsize); | |
2279 | cris_alu_m_free_temps(t); | |
2280 | return insn_len; | |
8170028d TS |
2281 | } |
2282 | ||
cf7e0c80 | 2283 | static int dec_movu_m(CPUCRISState *env, DisasContext *dc) |
8170028d | 2284 | { |
7b5eff4d EV |
2285 | TCGv t[2]; |
2286 | int memsize = memsize_z(dc); | |
2287 | int insn_len; | |
8170028d | 2288 | |
7b5eff4d EV |
2289 | LOG_DIS("movu.%c [$r%u%s, $r%u\n", |
2290 | memsize_char(memsize), | |
2291 | dc->op1, dc->postinc ? "+]" : "]", | |
2292 | dc->op2); | |
8170028d | 2293 | |
7b5eff4d | 2294 | cris_alu_m_alloc_temps(t); |
cf7e0c80 | 2295 | insn_len = dec_prep_alu_m(env, dc, 0, memsize, t[0], t[1]); |
7b5eff4d EV |
2296 | cris_cc_mask(dc, CC_MASK_NZ); |
2297 | cris_alu(dc, CC_OP_MOVE, cpu_R[dc->op2], cpu_R[dc->op2], t[1], 4); | |
2298 | do_postinc(dc, memsize); | |
2299 | cris_alu_m_free_temps(t); | |
2300 | return insn_len; | |
8170028d TS |
2301 | } |
2302 | ||
cf7e0c80 | 2303 | static int dec_cmpu_m(CPUCRISState *env, DisasContext *dc) |
8170028d | 2304 | { |
7b5eff4d EV |
2305 | TCGv t[2]; |
2306 | int memsize = memsize_z(dc); | |
2307 | int insn_len; | |
2308 | LOG_DIS("cmpu.%c [$r%u%s, $r%u\n", | |
2309 | memsize_char(memsize), | |
2310 | dc->op1, dc->postinc ? "+]" : "]", | |
2311 | dc->op2); | |
8170028d | 2312 | |
7b5eff4d | 2313 | cris_alu_m_alloc_temps(t); |
cf7e0c80 | 2314 | insn_len = dec_prep_alu_m(env, dc, 0, memsize, t[0], t[1]); |
7b5eff4d EV |
2315 | cris_cc_mask(dc, CC_MASK_NZVC); |
2316 | cris_alu(dc, CC_OP_CMP, cpu_R[dc->op2], cpu_R[dc->op2], t[1], 4); | |
2317 | do_postinc(dc, memsize); | |
2318 | cris_alu_m_free_temps(t); | |
2319 | return insn_len; | |
8170028d TS |
2320 | } |
2321 | ||
cf7e0c80 | 2322 | static int dec_cmps_m(CPUCRISState *env, DisasContext *dc) |
8170028d | 2323 | { |
7b5eff4d EV |
2324 | TCGv t[2]; |
2325 | int memsize = memsize_z(dc); | |
2326 | int insn_len; | |
2327 | LOG_DIS("cmps.%c [$r%u%s, $r%u\n", | |
2328 | memsize_char(memsize), | |
2329 | dc->op1, dc->postinc ? "+]" : "]", | |
2330 | dc->op2); | |
8170028d | 2331 | |
7b5eff4d | 2332 | cris_alu_m_alloc_temps(t); |
cf7e0c80 | 2333 | insn_len = dec_prep_alu_m(env, dc, 1, memsize, t[0], t[1]); |
7b5eff4d EV |
2334 | cris_cc_mask(dc, CC_MASK_NZVC); |
2335 | cris_alu(dc, CC_OP_CMP, | |
2336 | cpu_R[dc->op2], cpu_R[dc->op2], t[1], | |
2337 | memsize_zz(dc)); | |
2338 | do_postinc(dc, memsize); | |
2339 | cris_alu_m_free_temps(t); | |
2340 | return insn_len; | |
8170028d TS |
2341 | } |
2342 | ||
cf7e0c80 | 2343 | static int dec_cmp_m(CPUCRISState *env, DisasContext *dc) |
8170028d | 2344 | { |
7b5eff4d EV |
2345 | TCGv t[2]; |
2346 | int memsize = memsize_zz(dc); | |
2347 | int insn_len; | |
2348 | LOG_DIS("cmp.%c [$r%u%s, $r%u\n", | |
2349 | memsize_char(memsize), | |
2350 | dc->op1, dc->postinc ? "+]" : "]", | |
2351 | dc->op2); | |
8170028d | 2352 | |
7b5eff4d | 2353 | cris_alu_m_alloc_temps(t); |
cf7e0c80 | 2354 | insn_len = dec_prep_alu_m(env, dc, 0, memsize, t[0], t[1]); |
7b5eff4d EV |
2355 | cris_cc_mask(dc, CC_MASK_NZVC); |
2356 | cris_alu(dc, CC_OP_CMP, | |
2357 | cpu_R[dc->op2], cpu_R[dc->op2], t[1], | |
2358 | memsize_zz(dc)); | |
2359 | do_postinc(dc, memsize); | |
2360 | cris_alu_m_free_temps(t); | |
2361 | return insn_len; | |
8170028d TS |
2362 | } |
2363 | ||
cf7e0c80 | 2364 | static int dec_test_m(CPUCRISState *env, DisasContext *dc) |
8170028d | 2365 | { |
7b5eff4d EV |
2366 | TCGv t[2]; |
2367 | int memsize = memsize_zz(dc); | |
2368 | int insn_len; | |
2369 | LOG_DIS("test.%c [$r%u%s] op2=%x\n", | |
2370 | memsize_char(memsize), | |
2371 | dc->op1, dc->postinc ? "+]" : "]", | |
2372 | dc->op2); | |
8170028d | 2373 | |
7b5eff4d | 2374 | cris_evaluate_flags(dc); |
dceaf394 | 2375 | |
7b5eff4d | 2376 | cris_alu_m_alloc_temps(t); |
cf7e0c80 | 2377 | insn_len = dec_prep_alu_m(env, dc, 0, memsize, t[0], t[1]); |
7b5eff4d EV |
2378 | cris_cc_mask(dc, CC_MASK_NZ); |
2379 | tcg_gen_andi_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], ~3); | |
b41f7df0 | 2380 | |
7b5eff4d EV |
2381 | cris_alu(dc, CC_OP_CMP, |
2382 | cpu_R[dc->op2], t[1], tcg_const_tl(0), memsize_zz(dc)); | |
2383 | do_postinc(dc, memsize); | |
2384 | cris_alu_m_free_temps(t); | |
2385 | return insn_len; | |
8170028d TS |
2386 | } |
2387 | ||
cf7e0c80 | 2388 | static int dec_and_m(CPUCRISState *env, DisasContext *dc) |
8170028d | 2389 | { |
7b5eff4d EV |
2390 | TCGv t[2]; |
2391 | int memsize = memsize_zz(dc); | |
2392 | int insn_len; | |
2393 | LOG_DIS("and.%c [$r%u%s, $r%u\n", | |
2394 | memsize_char(memsize), | |
2395 | dc->op1, dc->postinc ? "+]" : "]", | |
2396 | dc->op2); | |
8170028d | 2397 | |
7b5eff4d | 2398 | cris_alu_m_alloc_temps(t); |
cf7e0c80 | 2399 | insn_len = dec_prep_alu_m(env, dc, 0, memsize, t[0], t[1]); |
7b5eff4d EV |
2400 | cris_cc_mask(dc, CC_MASK_NZ); |
2401 | cris_alu(dc, CC_OP_AND, cpu_R[dc->op2], t[0], t[1], memsize_zz(dc)); | |
2402 | do_postinc(dc, memsize); | |
2403 | cris_alu_m_free_temps(t); | |
2404 | return insn_len; | |
8170028d TS |
2405 | } |
2406 | ||
cf7e0c80 | 2407 | static int dec_add_m(CPUCRISState *env, DisasContext *dc) |
8170028d | 2408 | { |
7b5eff4d EV |
2409 | TCGv t[2]; |
2410 | int memsize = memsize_zz(dc); | |
2411 | int insn_len; | |
2412 | LOG_DIS("add.%c [$r%u%s, $r%u\n", | |
2413 | memsize_char(memsize), | |
2414 | dc->op1, dc->postinc ? "+]" : "]", | |
2415 | dc->op2); | |
8170028d | 2416 | |
7b5eff4d | 2417 | cris_alu_m_alloc_temps(t); |
cf7e0c80 | 2418 | insn_len = dec_prep_alu_m(env, dc, 0, memsize, t[0], t[1]); |
7b5eff4d EV |
2419 | cris_cc_mask(dc, CC_MASK_NZVC); |
2420 | cris_alu(dc, CC_OP_ADD, | |
2421 | cpu_R[dc->op2], t[0], t[1], memsize_zz(dc)); | |
2422 | do_postinc(dc, memsize); | |
2423 | cris_alu_m_free_temps(t); | |
2424 | return insn_len; | |
8170028d TS |
2425 | } |
2426 | ||
cf7e0c80 | 2427 | static int dec_addo_m(CPUCRISState *env, DisasContext *dc) |
8170028d | 2428 | { |
7b5eff4d EV |
2429 | TCGv t[2]; |
2430 | int memsize = memsize_zz(dc); | |
2431 | int insn_len; | |
2432 | LOG_DIS("add.%c [$r%u%s, $r%u\n", | |
2433 | memsize_char(memsize), | |
2434 | dc->op1, dc->postinc ? "+]" : "]", | |
2435 | dc->op2); | |
8170028d | 2436 | |
7b5eff4d | 2437 | cris_alu_m_alloc_temps(t); |
cf7e0c80 | 2438 | insn_len = dec_prep_alu_m(env, dc, 1, memsize, t[0], t[1]); |
7b5eff4d EV |
2439 | cris_cc_mask(dc, 0); |
2440 | cris_alu(dc, CC_OP_ADD, cpu_R[R_ACR], t[0], t[1], 4); | |
2441 | do_postinc(dc, memsize); | |
2442 | cris_alu_m_free_temps(t); | |
2443 | return insn_len; | |
8170028d TS |
2444 | } |
2445 | ||
cf7e0c80 | 2446 | static int dec_bound_m(CPUCRISState *env, DisasContext *dc) |
8170028d | 2447 | { |
7b5eff4d EV |
2448 | TCGv l[2]; |
2449 | int memsize = memsize_zz(dc); | |
2450 | int insn_len; | |
2451 | LOG_DIS("bound.%c [$r%u%s, $r%u\n", | |
2452 | memsize_char(memsize), | |
2453 | dc->op1, dc->postinc ? "+]" : "]", | |
2454 | dc->op2); | |
8170028d | 2455 | |
7b5eff4d EV |
2456 | l[0] = tcg_temp_local_new(); |
2457 | l[1] = tcg_temp_local_new(); | |
cf7e0c80 | 2458 | insn_len = dec_prep_alu_m(env, dc, 0, memsize, l[0], l[1]); |
7b5eff4d EV |
2459 | cris_cc_mask(dc, CC_MASK_NZ); |
2460 | cris_alu(dc, CC_OP_BOUND, cpu_R[dc->op2], l[0], l[1], 4); | |
2461 | do_postinc(dc, memsize); | |
2462 | tcg_temp_free(l[0]); | |
2463 | tcg_temp_free(l[1]); | |
2464 | return insn_len; | |
8170028d TS |
2465 | } |
2466 | ||
cf7e0c80 | 2467 | static int dec_addc_mr(CPUCRISState *env, DisasContext *dc) |
8170028d | 2468 | { |
7b5eff4d EV |
2469 | TCGv t[2]; |
2470 | int insn_len = 2; | |
2471 | LOG_DIS("addc [$r%u%s, $r%u\n", | |
2472 | dc->op1, dc->postinc ? "+]" : "]", | |
2473 | dc->op2); | |
8170028d | 2474 | |
7b5eff4d | 2475 | cris_evaluate_flags(dc); |
a8cf66bb | 2476 | |
7b5eff4d EV |
2477 | /* Set for this insn. */ |
2478 | dc->flagx_known = 1; | |
2479 | dc->flags_x = X_FLAG; | |
a8cf66bb | 2480 | |
7b5eff4d | 2481 | cris_alu_m_alloc_temps(t); |
cf7e0c80 | 2482 | insn_len = dec_prep_alu_m(env, dc, 0, 4, t[0], t[1]); |
7b5eff4d EV |
2483 | cris_cc_mask(dc, CC_MASK_NZVC); |
2484 | cris_alu(dc, CC_OP_ADDC, cpu_R[dc->op2], t[0], t[1], 4); | |
2485 | do_postinc(dc, 4); | |
2486 | cris_alu_m_free_temps(t); | |
2487 | return insn_len; | |
8170028d TS |
2488 | } |
2489 | ||
cf7e0c80 | 2490 | static int dec_sub_m(CPUCRISState *env, DisasContext *dc) |
8170028d | 2491 | { |
7b5eff4d EV |
2492 | TCGv t[2]; |
2493 | int memsize = memsize_zz(dc); | |
2494 | int insn_len; | |
2495 | LOG_DIS("sub.%c [$r%u%s, $r%u ir=%x zz=%x\n", | |
2496 | memsize_char(memsize), | |
2497 | dc->op1, dc->postinc ? "+]" : "]", | |
2498 | dc->op2, dc->ir, dc->zzsize); | |
8170028d | 2499 | |
7b5eff4d | 2500 | cris_alu_m_alloc_temps(t); |
cf7e0c80 | 2501 | insn_len = dec_prep_alu_m(env, dc, 0, memsize, t[0], t[1]); |
7b5eff4d EV |
2502 | cris_cc_mask(dc, CC_MASK_NZVC); |
2503 | cris_alu(dc, CC_OP_SUB, cpu_R[dc->op2], t[0], t[1], memsize); | |
2504 | do_postinc(dc, memsize); | |
2505 | cris_alu_m_free_temps(t); | |
2506 | return insn_len; | |
8170028d TS |
2507 | } |
2508 | ||
cf7e0c80 | 2509 | static int dec_or_m(CPUCRISState *env, DisasContext *dc) |
8170028d | 2510 | { |
7b5eff4d EV |
2511 | TCGv t[2]; |
2512 | int memsize = memsize_zz(dc); | |
2513 | int insn_len; | |
2514 | LOG_DIS("or.%c [$r%u%s, $r%u pc=%x\n", | |
2515 | memsize_char(memsize), | |
2516 | dc->op1, dc->postinc ? "+]" : "]", | |
2517 | dc->op2, dc->pc); | |
8170028d | 2518 | |
7b5eff4d | 2519 | cris_alu_m_alloc_temps(t); |
cf7e0c80 | 2520 | insn_len = dec_prep_alu_m(env, dc, 0, memsize, t[0], t[1]); |
7b5eff4d EV |
2521 | cris_cc_mask(dc, CC_MASK_NZ); |
2522 | cris_alu(dc, CC_OP_OR, | |
2523 | cpu_R[dc->op2], t[0], t[1], memsize_zz(dc)); | |
2524 | do_postinc(dc, memsize); | |
2525 | cris_alu_m_free_temps(t); | |
2526 | return insn_len; | |
8170028d TS |
2527 | } |
2528 | ||
cf7e0c80 | 2529 | static int dec_move_mp(CPUCRISState *env, DisasContext *dc) |
8170028d | 2530 | { |
7b5eff4d EV |
2531 | TCGv t[2]; |
2532 | int memsize = memsize_zz(dc); | |
2533 | int insn_len = 2; | |
8170028d | 2534 | |
7b5eff4d EV |
2535 | LOG_DIS("move.%c [$r%u%s, $p%u\n", |
2536 | memsize_char(memsize), | |
2537 | dc->op1, | |
2538 | dc->postinc ? "+]" : "]", | |
2539 | dc->op2); | |
8170028d | 2540 | |
7b5eff4d | 2541 | cris_alu_m_alloc_temps(t); |
cf7e0c80 | 2542 | insn_len = dec_prep_alu_m(env, dc, 0, memsize, t[0], t[1]); |
7b5eff4d EV |
2543 | cris_cc_mask(dc, 0); |
2544 | if (dc->op2 == PR_CCS) { | |
2545 | cris_evaluate_flags(dc); | |
2546 | if (dc->tb_flags & U_FLAG) { | |
2547 | /* User space is not allowed to touch all flags. */ | |
2548 | tcg_gen_andi_tl(t[1], t[1], 0x39f); | |
2549 | tcg_gen_andi_tl(t[0], cpu_PR[PR_CCS], ~0x39f); | |
2550 | tcg_gen_or_tl(t[1], t[0], t[1]); | |
2551 | } | |
2552 | } | |
b41f7df0 | 2553 | |
7b5eff4d | 2554 | t_gen_mov_preg_TN(dc, dc->op2, t[1]); |
8170028d | 2555 | |
7b5eff4d EV |
2556 | do_postinc(dc, memsize); |
2557 | cris_alu_m_free_temps(t); | |
2558 | return insn_len; | |
8170028d TS |
2559 | } |
2560 | ||
cf7e0c80 | 2561 | static int dec_move_pm(CPUCRISState *env, DisasContext *dc) |
8170028d | 2562 | { |
7b5eff4d EV |
2563 | TCGv t0; |
2564 | int memsize; | |
8170028d | 2565 | |
7b5eff4d | 2566 | memsize = preg_sizes[dc->op2]; |
8170028d | 2567 | |
7b5eff4d EV |
2568 | LOG_DIS("move.%c $p%u, [$r%u%s\n", |
2569 | memsize_char(memsize), | |
2570 | dc->op2, dc->op1, dc->postinc ? "+]" : "]"); | |
8170028d | 2571 | |
7b5eff4d EV |
2572 | /* prepare store. Address in T0, value in T1. */ |
2573 | if (dc->op2 == PR_CCS) { | |
2574 | cris_evaluate_flags(dc); | |
2575 | } | |
2576 | t0 = tcg_temp_new(); | |
2577 | t_gen_mov_TN_preg(t0, dc->op2); | |
2578 | cris_flush_cc_state(dc); | |
2579 | gen_store(dc, cpu_R[dc->op1], t0, memsize); | |
2580 | tcg_temp_free(t0); | |
2581 | ||
2582 | cris_cc_mask(dc, 0); | |
2583 | if (dc->postinc) { | |
2584 | tcg_gen_addi_tl(cpu_R[dc->op1], cpu_R[dc->op1], memsize); | |
2585 | } | |
2586 | return 2; | |
8170028d TS |
2587 | } |
2588 | ||
cf7e0c80 | 2589 | static int dec_movem_mr(CPUCRISState *env, DisasContext *dc) |
8170028d | 2590 | { |
7b5eff4d EV |
2591 | TCGv_i64 tmp[16]; |
2592 | TCGv tmp32; | |
2593 | TCGv addr; | |
2594 | int i; | |
2595 | int nr = dc->op2 + 1; | |
2596 | ||
2597 | LOG_DIS("movem [$r%u%s, $r%u\n", dc->op1, | |
2598 | dc->postinc ? "+]" : "]", dc->op2); | |
2599 | ||
2600 | addr = tcg_temp_new(); | |
2601 | /* There are probably better ways of doing this. */ | |
2602 | cris_flush_cc_state(dc); | |
2603 | for (i = 0; i < (nr >> 1); i++) { | |
2604 | tmp[i] = tcg_temp_new_i64(); | |
2605 | tcg_gen_addi_tl(addr, cpu_R[dc->op1], i * 8); | |
2606 | gen_load64(dc, tmp[i], addr); | |
2607 | } | |
2608 | if (nr & 1) { | |
2609 | tmp32 = tcg_temp_new_i32(); | |
2610 | tcg_gen_addi_tl(addr, cpu_R[dc->op1], i * 8); | |
2611 | gen_load(dc, tmp32, addr, 4, 0); | |
2612 | } else { | |
2613 | TCGV_UNUSED(tmp32); | |
2614 | } | |
2615 | tcg_temp_free(addr); | |
2616 | ||
2617 | for (i = 0; i < (nr >> 1); i++) { | |
2618 | tcg_gen_trunc_i64_i32(cpu_R[i * 2], tmp[i]); | |
2619 | tcg_gen_shri_i64(tmp[i], tmp[i], 32); | |
2620 | tcg_gen_trunc_i64_i32(cpu_R[i * 2 + 1], tmp[i]); | |
2621 | tcg_temp_free_i64(tmp[i]); | |
2622 | } | |
2623 | if (nr & 1) { | |
2624 | tcg_gen_mov_tl(cpu_R[dc->op2], tmp32); | |
2625 | tcg_temp_free(tmp32); | |
2626 | } | |
2627 | ||
2628 | /* writeback the updated pointer value. */ | |
2629 | if (dc->postinc) { | |
2630 | tcg_gen_addi_tl(cpu_R[dc->op1], cpu_R[dc->op1], nr * 4); | |
2631 | } | |
2632 | ||
2633 | /* gen_load might want to evaluate the previous insns flags. */ | |
2634 | cris_cc_mask(dc, 0); | |
2635 | return 2; | |
8170028d TS |
2636 | } |
2637 | ||
cf7e0c80 | 2638 | static int dec_movem_rm(CPUCRISState *env, DisasContext *dc) |
8170028d | 2639 | { |
7b5eff4d EV |
2640 | TCGv tmp; |
2641 | TCGv addr; | |
2642 | int i; | |
2643 | ||
2644 | LOG_DIS("movem $r%u, [$r%u%s\n", dc->op2, dc->op1, | |
2645 | dc->postinc ? "+]" : "]"); | |
2646 | ||
2647 | cris_flush_cc_state(dc); | |
2648 | ||
2649 | tmp = tcg_temp_new(); | |
2650 | addr = tcg_temp_new(); | |
2651 | tcg_gen_movi_tl(tmp, 4); | |
2652 | tcg_gen_mov_tl(addr, cpu_R[dc->op1]); | |
2653 | for (i = 0; i <= dc->op2; i++) { | |
2654 | /* Displace addr. */ | |
2655 | /* Perform the store. */ | |
2656 | gen_store(dc, addr, cpu_R[i], 4); | |
2657 | tcg_gen_add_tl(addr, addr, tmp); | |
2658 | } | |
2659 | if (dc->postinc) { | |
2660 | tcg_gen_mov_tl(cpu_R[dc->op1], addr); | |
2661 | } | |
2662 | cris_cc_mask(dc, 0); | |
2663 | tcg_temp_free(tmp); | |
2664 | tcg_temp_free(addr); | |
2665 | return 2; | |
8170028d TS |
2666 | } |
2667 | ||
cf7e0c80 | 2668 | static int dec_move_rm(CPUCRISState *env, DisasContext *dc) |
8170028d | 2669 | { |
7b5eff4d | 2670 | int memsize; |
8170028d | 2671 | |
7b5eff4d | 2672 | memsize = memsize_zz(dc); |
8170028d | 2673 | |
7b5eff4d EV |
2674 | LOG_DIS("move.%c $r%u, [$r%u]\n", |
2675 | memsize_char(memsize), dc->op2, dc->op1); | |
8170028d | 2676 | |
7b5eff4d EV |
2677 | /* prepare store. */ |
2678 | cris_flush_cc_state(dc); | |
2679 | gen_store(dc, cpu_R[dc->op1], cpu_R[dc->op2], memsize); | |
17ac9754 | 2680 | |
7b5eff4d EV |
2681 | if (dc->postinc) { |
2682 | tcg_gen_addi_tl(cpu_R[dc->op1], cpu_R[dc->op1], memsize); | |
2683 | } | |
2684 | cris_cc_mask(dc, 0); | |
2685 | return 2; | |
8170028d TS |
2686 | } |
2687 | ||
cf7e0c80 | 2688 | static int dec_lapcq(CPUCRISState *env, DisasContext *dc) |
8170028d | 2689 | { |
7b5eff4d EV |
2690 | LOG_DIS("lapcq %x, $r%u\n", |
2691 | dc->pc + dc->op1*2, dc->op2); | |
2692 | cris_cc_mask(dc, 0); | |
2693 | tcg_gen_movi_tl(cpu_R[dc->op2], dc->pc + dc->op1 * 2); | |
2694 | return 2; | |
8170028d TS |
2695 | } |
2696 | ||
cf7e0c80 | 2697 | static int dec_lapc_im(CPUCRISState *env, DisasContext *dc) |
8170028d | 2698 | { |
7b5eff4d EV |
2699 | unsigned int rd; |
2700 | int32_t imm; | |
2701 | int32_t pc; | |
8170028d | 2702 | |
7b5eff4d | 2703 | rd = dc->op2; |
8170028d | 2704 | |
7b5eff4d EV |
2705 | cris_cc_mask(dc, 0); |
2706 | imm = cris_fetch(env, dc, dc->pc + 2, 4, 0); | |
2707 | LOG_DIS("lapc 0x%x, $r%u\n", imm + dc->pc, dc->op2); | |
b41f7df0 | 2708 | |
7b5eff4d EV |
2709 | pc = dc->pc; |
2710 | pc += imm; | |
2711 | tcg_gen_movi_tl(cpu_R[rd], pc); | |
2712 | return 6; | |
8170028d TS |
2713 | } |
2714 | ||
2715 | /* Jump to special reg. */ | |
cf7e0c80 | 2716 | static int dec_jump_p(CPUCRISState *env, DisasContext *dc) |
8170028d | 2717 | { |
7b5eff4d | 2718 | LOG_DIS("jump $p%u\n", dc->op2); |
b41f7df0 | 2719 | |
7b5eff4d EV |
2720 | if (dc->op2 == PR_CCS) { |
2721 | cris_evaluate_flags(dc); | |
2722 | } | |
2723 | t_gen_mov_TN_preg(env_btarget, dc->op2); | |
2724 | /* rete will often have low bit set to indicate delayslot. */ | |
2725 | tcg_gen_andi_tl(env_btarget, env_btarget, ~1); | |
2726 | cris_cc_mask(dc, 0); | |
2727 | cris_prepare_jmp(dc, JMP_INDIRECT); | |
2728 | return 2; | |
8170028d TS |
2729 | } |
2730 | ||
2731 | /* Jump and save. */ | |
cf7e0c80 | 2732 | static int dec_jas_r(CPUCRISState *env, DisasContext *dc) |
8170028d | 2733 | { |
7b5eff4d EV |
2734 | LOG_DIS("jas $r%u, $p%u\n", dc->op1, dc->op2); |
2735 | cris_cc_mask(dc, 0); | |
2736 | /* Store the return address in Pd. */ | |
2737 | tcg_gen_mov_tl(env_btarget, cpu_R[dc->op1]); | |
2738 | if (dc->op2 > 15) { | |
2739 | abort(); | |
2740 | } | |
2741 | t_gen_mov_preg_TN(dc, dc->op2, tcg_const_tl(dc->pc + 4)); | |
b41f7df0 | 2742 | |
7b5eff4d EV |
2743 | cris_prepare_jmp(dc, JMP_INDIRECT); |
2744 | return 2; | |
8170028d TS |
2745 | } |
2746 | ||
cf7e0c80 | 2747 | static int dec_jas_im(CPUCRISState *env, DisasContext *dc) |
8170028d | 2748 | { |
7b5eff4d | 2749 | uint32_t imm; |
8170028d | 2750 | |
7b5eff4d | 2751 | imm = cris_fetch(env, dc, dc->pc + 2, 4, 0); |
8170028d | 2752 | |
7b5eff4d EV |
2753 | LOG_DIS("jas 0x%x\n", imm); |
2754 | cris_cc_mask(dc, 0); | |
2755 | /* Store the return address in Pd. */ | |
2756 | t_gen_mov_preg_TN(dc, dc->op2, tcg_const_tl(dc->pc + 8)); | |
2a44f7f1 | 2757 | |
7b5eff4d EV |
2758 | dc->jmp_pc = imm; |
2759 | cris_prepare_jmp(dc, JMP_DIRECT); | |
2760 | return 6; | |
8170028d TS |
2761 | } |
2762 | ||
cf7e0c80 | 2763 | static int dec_jasc_im(CPUCRISState *env, DisasContext *dc) |
8170028d | 2764 | { |
7b5eff4d | 2765 | uint32_t imm; |
8170028d | 2766 | |
7b5eff4d | 2767 | imm = cris_fetch(env, dc, dc->pc + 2, 4, 0); |
8170028d | 2768 | |
7b5eff4d EV |
2769 | LOG_DIS("jasc 0x%x\n", imm); |
2770 | cris_cc_mask(dc, 0); | |
2771 | /* Store the return address in Pd. */ | |
2772 | t_gen_mov_preg_TN(dc, dc->op2, tcg_const_tl(dc->pc + 8 + 4)); | |
2a44f7f1 | 2773 | |
7b5eff4d EV |
2774 | dc->jmp_pc = imm; |
2775 | cris_prepare_jmp(dc, JMP_DIRECT); | |
2776 | return 6; | |
8170028d TS |
2777 | } |
2778 | ||
cf7e0c80 | 2779 | static int dec_jasc_r(CPUCRISState *env, DisasContext *dc) |
8170028d | 2780 | { |
7b5eff4d EV |
2781 | LOG_DIS("jasc_r $r%u, $p%u\n", dc->op1, dc->op2); |
2782 | cris_cc_mask(dc, 0); | |
2783 | /* Store the return address in Pd. */ | |
2784 | tcg_gen_mov_tl(env_btarget, cpu_R[dc->op1]); | |
2785 | t_gen_mov_preg_TN(dc, dc->op2, tcg_const_tl(dc->pc + 4 + 4)); | |
2786 | cris_prepare_jmp(dc, JMP_INDIRECT); | |
2787 | return 2; | |
8170028d TS |
2788 | } |
2789 | ||
cf7e0c80 | 2790 | static int dec_bcc_im(CPUCRISState *env, DisasContext *dc) |
8170028d | 2791 | { |
7b5eff4d EV |
2792 | int32_t offset; |
2793 | uint32_t cond = dc->op2; | |
8170028d | 2794 | |
7b5eff4d | 2795 | offset = cris_fetch(env, dc, dc->pc + 2, 2, 1); |
8170028d | 2796 | |
7b5eff4d EV |
2797 | LOG_DIS("b%s %d pc=%x dst=%x\n", |
2798 | cc_name(cond), offset, | |
2799 | dc->pc, dc->pc + offset); | |
8170028d | 2800 | |
7b5eff4d EV |
2801 | cris_cc_mask(dc, 0); |
2802 | /* op2 holds the condition-code. */ | |
2803 | cris_prepare_cc_branch(dc, offset, cond); | |
2804 | return 4; | |
8170028d TS |
2805 | } |
2806 | ||
cf7e0c80 | 2807 | static int dec_bas_im(CPUCRISState *env, DisasContext *dc) |
8170028d | 2808 | { |
7b5eff4d | 2809 | int32_t simm; |
8170028d | 2810 | |
7b5eff4d | 2811 | simm = cris_fetch(env, dc, dc->pc + 2, 4, 0); |
8170028d | 2812 | |
7b5eff4d EV |
2813 | LOG_DIS("bas 0x%x, $p%u\n", dc->pc + simm, dc->op2); |
2814 | cris_cc_mask(dc, 0); | |
2815 | /* Store the return address in Pd. */ | |
2816 | t_gen_mov_preg_TN(dc, dc->op2, tcg_const_tl(dc->pc + 8)); | |
8170028d | 2817 | |
7b5eff4d EV |
2818 | dc->jmp_pc = dc->pc + simm; |
2819 | cris_prepare_jmp(dc, JMP_DIRECT); | |
2820 | return 6; | |
8170028d TS |
2821 | } |
2822 | ||
cf7e0c80 | 2823 | static int dec_basc_im(CPUCRISState *env, DisasContext *dc) |
8170028d | 2824 | { |
7b5eff4d EV |
2825 | int32_t simm; |
2826 | simm = cris_fetch(env, dc, dc->pc + 2, 4, 0); | |
8170028d | 2827 | |
7b5eff4d EV |
2828 | LOG_DIS("basc 0x%x, $p%u\n", dc->pc + simm, dc->op2); |
2829 | cris_cc_mask(dc, 0); | |
2830 | /* Store the return address in Pd. */ | |
2831 | t_gen_mov_preg_TN(dc, dc->op2, tcg_const_tl(dc->pc + 12)); | |
2a44f7f1 | 2832 | |
7b5eff4d EV |
2833 | dc->jmp_pc = dc->pc + simm; |
2834 | cris_prepare_jmp(dc, JMP_DIRECT); | |
2835 | return 6; | |
8170028d TS |
2836 | } |
2837 | ||
cf7e0c80 | 2838 | static int dec_rfe_etc(CPUCRISState *env, DisasContext *dc) |
8170028d | 2839 | { |
7b5eff4d EV |
2840 | cris_cc_mask(dc, 0); |
2841 | ||
2842 | if (dc->op2 == 15) { | |
259186a7 AF |
2843 | tcg_gen_st_i32(tcg_const_i32(1), cpu_env, |
2844 | -offsetof(CRISCPU, env) + offsetof(CPUState, halted)); | |
7b5eff4d EV |
2845 | tcg_gen_movi_tl(env_pc, dc->pc + 2); |
2846 | t_gen_raise_exception(EXCP_HLT); | |
2847 | return 2; | |
2848 | } | |
2849 | ||
2850 | switch (dc->op2 & 7) { | |
2851 | case 2: | |
2852 | /* rfe. */ | |
2853 | LOG_DIS("rfe\n"); | |
2854 | cris_evaluate_flags(dc); | |
2855 | gen_helper_rfe(cpu_env); | |
2856 | dc->is_jmp = DISAS_UPDATE; | |
2857 | break; | |
2858 | case 5: | |
2859 | /* rfn. */ | |
2860 | LOG_DIS("rfn\n"); | |
2861 | cris_evaluate_flags(dc); | |
2862 | gen_helper_rfn(cpu_env); | |
2863 | dc->is_jmp = DISAS_UPDATE; | |
2864 | break; | |
2865 | case 6: | |
2866 | LOG_DIS("break %d\n", dc->op1); | |
2867 | cris_evaluate_flags(dc); | |
2868 | /* break. */ | |
2869 | tcg_gen_movi_tl(env_pc, dc->pc + 2); | |
2870 | ||
2871 | /* Breaks start at 16 in the exception vector. */ | |
2872 | t_gen_mov_env_TN(trap_vector, | |
2873 | tcg_const_tl(dc->op1 + 16)); | |
2874 | t_gen_raise_exception(EXCP_BREAK); | |
2875 | dc->is_jmp = DISAS_UPDATE; | |
2876 | break; | |
2877 | default: | |
2878 | printf("op2=%x\n", dc->op2); | |
2879 | BUG(); | |
2880 | break; | |
2881 | ||
2882 | } | |
2883 | return 2; | |
8170028d TS |
2884 | } |
2885 | ||
cf7e0c80 | 2886 | static int dec_ftag_fidx_d_m(CPUCRISState *env, DisasContext *dc) |
5d4a534d | 2887 | { |
7b5eff4d | 2888 | return 2; |
5d4a534d EI |
2889 | } |
2890 | ||
cf7e0c80 | 2891 | static int dec_ftag_fidx_i_m(CPUCRISState *env, DisasContext *dc) |
5d4a534d | 2892 | { |
7b5eff4d | 2893 | return 2; |
5d4a534d EI |
2894 | } |
2895 | ||
cf7e0c80 | 2896 | static int dec_null(CPUCRISState *env, DisasContext *dc) |
8170028d | 2897 | { |
7b5eff4d EV |
2898 | printf("unknown insn pc=%x opc=%x op1=%x op2=%x\n", |
2899 | dc->pc, dc->opcode, dc->op1, dc->op2); | |
2900 | fflush(NULL); | |
2901 | BUG(); | |
2902 | return 2; | |
8170028d TS |
2903 | } |
2904 | ||
9b32fbf8 | 2905 | static struct decoder_info { |
7b5eff4d EV |
2906 | struct { |
2907 | uint32_t bits; | |
2908 | uint32_t mask; | |
2909 | }; | |
2910 | int (*dec)(CPUCRISState *env, DisasContext *dc); | |
8170028d | 2911 | } decinfo[] = { |
7b5eff4d EV |
2912 | /* Order matters here. */ |
2913 | {DEC_MOVEQ, dec_moveq}, | |
2914 | {DEC_BTSTQ, dec_btstq}, | |
2915 | {DEC_CMPQ, dec_cmpq}, | |
2916 | {DEC_ADDOQ, dec_addoq}, | |
2917 | {DEC_ADDQ, dec_addq}, | |
2918 | {DEC_SUBQ, dec_subq}, | |
2919 | {DEC_ANDQ, dec_andq}, | |
2920 | {DEC_ORQ, dec_orq}, | |
2921 | {DEC_ASRQ, dec_asrq}, | |
2922 | {DEC_LSLQ, dec_lslq}, | |
2923 | {DEC_LSRQ, dec_lsrq}, | |
2924 | {DEC_BCCQ, dec_bccq}, | |
2925 | ||
2926 | {DEC_BCC_IM, dec_bcc_im}, | |
2927 | {DEC_JAS_IM, dec_jas_im}, | |
2928 | {DEC_JAS_R, dec_jas_r}, | |
2929 | {DEC_JASC_IM, dec_jasc_im}, | |
2930 | {DEC_JASC_R, dec_jasc_r}, | |
2931 | {DEC_BAS_IM, dec_bas_im}, | |
2932 | {DEC_BASC_IM, dec_basc_im}, | |
2933 | {DEC_JUMP_P, dec_jump_p}, | |
2934 | {DEC_LAPC_IM, dec_lapc_im}, | |
2935 | {DEC_LAPCQ, dec_lapcq}, | |
2936 | ||
2937 | {DEC_RFE_ETC, dec_rfe_etc}, | |
2938 | {DEC_ADDC_MR, dec_addc_mr}, | |
2939 | ||
2940 | {DEC_MOVE_MP, dec_move_mp}, | |
2941 | {DEC_MOVE_PM, dec_move_pm}, | |
2942 | {DEC_MOVEM_MR, dec_movem_mr}, | |
2943 | {DEC_MOVEM_RM, dec_movem_rm}, | |
2944 | {DEC_MOVE_PR, dec_move_pr}, | |
2945 | {DEC_SCC_R, dec_scc_r}, | |
2946 | {DEC_SETF, dec_setclrf}, | |
2947 | {DEC_CLEARF, dec_setclrf}, | |
2948 | ||
2949 | {DEC_MOVE_SR, dec_move_sr}, | |
2950 | {DEC_MOVE_RP, dec_move_rp}, | |
2951 | {DEC_SWAP_R, dec_swap_r}, | |
2952 | {DEC_ABS_R, dec_abs_r}, | |
2953 | {DEC_LZ_R, dec_lz_r}, | |
2954 | {DEC_MOVE_RS, dec_move_rs}, | |
2955 | {DEC_BTST_R, dec_btst_r}, | |
2956 | {DEC_ADDC_R, dec_addc_r}, | |
2957 | ||
2958 | {DEC_DSTEP_R, dec_dstep_r}, | |
2959 | {DEC_XOR_R, dec_xor_r}, | |
2960 | {DEC_MCP_R, dec_mcp_r}, | |
2961 | {DEC_CMP_R, dec_cmp_r}, | |
2962 | ||
2963 | {DEC_ADDI_R, dec_addi_r}, | |
2964 | {DEC_ADDI_ACR, dec_addi_acr}, | |
2965 | ||
2966 | {DEC_ADD_R, dec_add_r}, | |
2967 | {DEC_SUB_R, dec_sub_r}, | |
2968 | ||
2969 | {DEC_ADDU_R, dec_addu_r}, | |
2970 | {DEC_ADDS_R, dec_adds_r}, | |
2971 | {DEC_SUBU_R, dec_subu_r}, | |
2972 | {DEC_SUBS_R, dec_subs_r}, | |
2973 | {DEC_LSL_R, dec_lsl_r}, | |
2974 | ||
2975 | {DEC_AND_R, dec_and_r}, | |
2976 | {DEC_OR_R, dec_or_r}, | |
2977 | {DEC_BOUND_R, dec_bound_r}, | |
2978 | {DEC_ASR_R, dec_asr_r}, | |
2979 | {DEC_LSR_R, dec_lsr_r}, | |
2980 | ||
2981 | {DEC_MOVU_R, dec_movu_r}, | |
2982 | {DEC_MOVS_R, dec_movs_r}, | |
2983 | {DEC_NEG_R, dec_neg_r}, | |
2984 | {DEC_MOVE_R, dec_move_r}, | |
2985 | ||
2986 | {DEC_FTAG_FIDX_I_M, dec_ftag_fidx_i_m}, | |
2987 | {DEC_FTAG_FIDX_D_M, dec_ftag_fidx_d_m}, | |
2988 | ||
2989 | {DEC_MULS_R, dec_muls_r}, | |
2990 | {DEC_MULU_R, dec_mulu_r}, | |
2991 | ||
2992 | {DEC_ADDU_M, dec_addu_m}, | |
2993 | {DEC_ADDS_M, dec_adds_m}, | |
2994 | {DEC_SUBU_M, dec_subu_m}, | |
2995 | {DEC_SUBS_M, dec_subs_m}, | |
2996 | ||
2997 | {DEC_CMPU_M, dec_cmpu_m}, | |
2998 | {DEC_CMPS_M, dec_cmps_m}, | |
2999 | {DEC_MOVU_M, dec_movu_m}, | |
3000 | {DEC_MOVS_M, dec_movs_m}, | |
3001 | ||
3002 | {DEC_CMP_M, dec_cmp_m}, | |
3003 | {DEC_ADDO_M, dec_addo_m}, | |
3004 | {DEC_BOUND_M, dec_bound_m}, | |
3005 | {DEC_ADD_M, dec_add_m}, | |
3006 | {DEC_SUB_M, dec_sub_m}, | |
3007 | {DEC_AND_M, dec_and_m}, | |
3008 | {DEC_OR_M, dec_or_m}, | |
3009 | {DEC_MOVE_RM, dec_move_rm}, | |
3010 | {DEC_TEST_M, dec_test_m}, | |
3011 | {DEC_MOVE_MR, dec_move_mr}, | |
3012 | ||
3013 | {{0, 0}, dec_null} | |
8170028d TS |
3014 | }; |
3015 | ||
cf7e0c80 | 3016 | static unsigned int crisv32_decoder(CPUCRISState *env, DisasContext *dc) |
8170028d | 3017 | { |
7b5eff4d EV |
3018 | int insn_len = 2; |
3019 | int i; | |
8170028d | 3020 | |
7b5eff4d EV |
3021 | if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) { |
3022 | tcg_gen_debug_insn_start(dc->pc); | |
fdefe51c | 3023 | } |
28de16da | 3024 | |
7b5eff4d | 3025 | /* Load a halfword onto the instruction register. */ |
cf7e0c80 | 3026 | dc->ir = cris_fetch(env, dc, dc->pc, 2, 0); |
8170028d | 3027 | |
7b5eff4d EV |
3028 | /* Now decode it. */ |
3029 | dc->opcode = EXTRACT_FIELD(dc->ir, 4, 11); | |
3030 | dc->op1 = EXTRACT_FIELD(dc->ir, 0, 3); | |
3031 | dc->op2 = EXTRACT_FIELD(dc->ir, 12, 15); | |
3032 | dc->zsize = EXTRACT_FIELD(dc->ir, 4, 4); | |
3033 | dc->zzsize = EXTRACT_FIELD(dc->ir, 4, 5); | |
3034 | dc->postinc = EXTRACT_FIELD(dc->ir, 10, 10); | |
3035 | ||
3036 | /* Large switch for all insns. */ | |
3037 | for (i = 0; i < ARRAY_SIZE(decinfo); i++) { | |
3038 | if ((dc->opcode & decinfo[i].mask) == decinfo[i].bits) { | |
3039 | insn_len = decinfo[i].dec(env, dc); | |
3040 | break; | |
3041 | } | |
3042 | } | |
8170028d | 3043 | |
dd20fcd0 | 3044 | #if !defined(CONFIG_USER_ONLY) |
7b5eff4d EV |
3045 | /* Single-stepping ? */ |
3046 | if (dc->tb_flags & S_FLAG) { | |
3047 | int l1; | |
3048 | ||
3049 | l1 = gen_new_label(); | |
3050 | tcg_gen_brcondi_tl(TCG_COND_NE, cpu_PR[PR_SPC], dc->pc, l1); | |
3051 | /* We treat SPC as a break with an odd trap vector. */ | |
3052 | cris_evaluate_flags(dc); | |
3053 | t_gen_mov_env_TN(trap_vector, tcg_const_tl(3)); | |
3054 | tcg_gen_movi_tl(env_pc, dc->pc + insn_len); | |
3055 | tcg_gen_movi_tl(cpu_PR[PR_SPC], dc->pc + insn_len); | |
3056 | t_gen_raise_exception(EXCP_BREAK); | |
3057 | gen_set_label(l1); | |
3058 | } | |
a1aebcb8 | 3059 | #endif |
7b5eff4d | 3060 | return insn_len; |
8170028d TS |
3061 | } |
3062 | ||
a1170bfd | 3063 | static void check_breakpoint(CPUCRISState *env, DisasContext *dc) |
8170028d | 3064 | { |
f0c3c505 | 3065 | CPUState *cs = CPU(cris_env_get_cpu(env)); |
7b5eff4d | 3066 | CPUBreakpoint *bp; |
a1d1bb31 | 3067 | |
f0c3c505 AF |
3068 | if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) { |
3069 | QTAILQ_FOREACH(bp, &cs->breakpoints, entry) { | |
7b5eff4d EV |
3070 | if (bp->pc == dc->pc) { |
3071 | cris_evaluate_flags(dc); | |
3072 | tcg_gen_movi_tl(env_pc, dc->pc); | |
3073 | t_gen_raise_exception(EXCP_DEBUG); | |
3074 | dc->is_jmp = DISAS_UPDATE; | |
3075 | } | |
3076 | } | |
3077 | } | |
8170028d TS |
3078 | } |
3079 | ||
40e9eddd | 3080 | #include "translate_v10.c" |
cf1d97f0 EI |
3081 | |
3082 | /* | |
3083 | * Delay slots on QEMU/CRIS. | |
3084 | * | |
3085 | * If an exception hits on a delayslot, the core will let ERP (the Exception | |
3086 | * Return Pointer) point to the branch (the previous) insn and set the lsb to | |
3087 | * to give SW a hint that the exception actually hit on the dslot. | |
3088 | * | |
3089 | * CRIS expects all PC addresses to be 16-bit aligned. The lsb is ignored by | |
3090 | * the core and any jmp to an odd addresses will mask off that lsb. It is | |
3091 | * simply there to let sw know there was an exception on a dslot. | |
3092 | * | |
3093 | * When the software returns from an exception, the branch will re-execute. | |
3094 | * On QEMU care needs to be taken when a branch+delayslot sequence is broken | |
3095 | * and the branch and delayslot dont share pages. | |
3096 | * | |
3097 | * The TB contaning the branch insn will set up env->btarget and evaluate | |
3098 | * env->btaken. When the translation loop exits we will note that the branch | |
3099 | * sequence is broken and let env->dslot be the size of the branch insn (those | |
3100 | * vary in length). | |
3101 | * | |
3102 | * The TB contaning the delayslot will have the PC of its real insn (i.e no lsb | |
3103 | * set). It will also expect to have env->dslot setup with the size of the | |
3104 | * delay slot so that env->pc - env->dslot point to the branch insn. This TB | |
3105 | * will execute the dslot and take the branch, either to btarget or just one | |
3106 | * insn ahead. | |
3107 | * | |
3108 | * When exceptions occur, we check for env->dslot in do_interrupt to detect | |
3109 | * broken branch sequences and setup $erp accordingly (i.e let it point to the | |
3110 | * branch and set lsb). Then env->dslot gets cleared so that the exception | |
3111 | * handler can enter. When returning from exceptions (jump $erp) the lsb gets | |
3112 | * masked off and we will reexecute the branch insn. | |
3113 | * | |
3114 | */ | |
3115 | ||
8170028d | 3116 | /* generate intermediate code for basic block 'tb'. */ |
6f47ec50 | 3117 | static inline void |
7fd2592d AF |
3118 | gen_intermediate_code_internal(CRISCPU *cpu, TranslationBlock *tb, |
3119 | bool search_pc) | |
8170028d | 3120 | { |
ed2803da | 3121 | CPUState *cs = CPU(cpu); |
7fd2592d | 3122 | CPUCRISState *env = &cpu->env; |
7b5eff4d EV |
3123 | uint16_t *gen_opc_end; |
3124 | uint32_t pc_start; | |
3125 | unsigned int insn_len; | |
3126 | int j, lj; | |
3127 | struct DisasContext ctx; | |
3128 | struct DisasContext *dc = &ctx; | |
3129 | uint32_t next_page_start; | |
3130 | target_ulong npc; | |
3131 | int num_insns; | |
3132 | int max_insns; | |
3133 | ||
7b5eff4d EV |
3134 | if (env->pregs[PR_VR] == 32) { |
3135 | dc->decoder = crisv32_decoder; | |
3136 | dc->clear_locked_irq = 0; | |
3137 | } else { | |
3138 | dc->decoder = crisv10_decoder; | |
3139 | dc->clear_locked_irq = 1; | |
3140 | } | |
3141 | ||
3142 | /* Odd PC indicates that branch is rexecuting due to exception in the | |
3143 | * delayslot, like in real hw. | |
3144 | */ | |
3145 | pc_start = tb->pc & ~1; | |
0dd106c5 | 3146 | dc->cpu = cpu; |
7b5eff4d EV |
3147 | dc->tb = tb; |
3148 | ||
92414b31 | 3149 | gen_opc_end = tcg_ctx.gen_opc_buf + OPC_MAX_SIZE; |
7b5eff4d EV |
3150 | |
3151 | dc->is_jmp = DISAS_NEXT; | |
3152 | dc->ppc = pc_start; | |
3153 | dc->pc = pc_start; | |
ed2803da | 3154 | dc->singlestep_enabled = cs->singlestep_enabled; |
7b5eff4d EV |
3155 | dc->flags_uptodate = 1; |
3156 | dc->flagx_known = 1; | |
3157 | dc->flags_x = tb->flags & X_FLAG; | |
3158 | dc->cc_x_uptodate = 0; | |
3159 | dc->cc_mask = 0; | |
3160 | dc->update_cc = 0; | |
3161 | dc->clear_prefix = 0; | |
3162 | ||
3163 | cris_update_cc_op(dc, CC_OP_FLAGS, 4); | |
3164 | dc->cc_size_uptodate = -1; | |
3165 | ||
3166 | /* Decode TB flags. */ | |
3167 | dc->tb_flags = tb->flags & (S_FLAG | P_FLAG | U_FLAG \ | |
3168 | | X_FLAG | PFIX_FLAG); | |
3169 | dc->delayed_branch = !!(tb->flags & 7); | |
3170 | if (dc->delayed_branch) { | |
3171 | dc->jmp = JMP_INDIRECT; | |
3172 | } else { | |
3173 | dc->jmp = JMP_NOJMP; | |
3174 | } | |
3175 | ||
3176 | dc->cpustate_changed = 0; | |
3177 | ||
3178 | if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) { | |
3179 | qemu_log( | |
3180 | "srch=%d pc=%x %x flg=%" PRIx64 " bt=%x ds=%u ccs=%x\n" | |
3181 | "pid=%x usp=%x\n" | |
3182 | "%x.%x.%x.%x\n" | |
3183 | "%x.%x.%x.%x\n" | |
3184 | "%x.%x.%x.%x\n" | |
3185 | "%x.%x.%x.%x\n", | |
3186 | search_pc, dc->pc, dc->ppc, | |
3187 | (uint64_t)tb->flags, | |
3188 | env->btarget, (unsigned)tb->flags & 7, | |
3189 | env->pregs[PR_CCS], | |
3190 | env->pregs[PR_PID], env->pregs[PR_USP], | |
3191 | env->regs[0], env->regs[1], env->regs[2], env->regs[3], | |
3192 | env->regs[4], env->regs[5], env->regs[6], env->regs[7], | |
3193 | env->regs[8], env->regs[9], | |
3194 | env->regs[10], env->regs[11], | |
3195 | env->regs[12], env->regs[13], | |
3196 | env->regs[14], env->regs[15]); | |
3197 | qemu_log("--------------\n"); | |
3198 | qemu_log("IN: %s\n", lookup_symbol(pc_start)); | |
3199 | } | |
3200 | ||
3201 | next_page_start = (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE; | |
3202 | lj = -1; | |
3203 | num_insns = 0; | |
3204 | max_insns = tb->cflags & CF_COUNT_MASK; | |
3205 | if (max_insns == 0) { | |
3206 | max_insns = CF_COUNT_MASK; | |
3207 | } | |
3208 | ||
806f352d | 3209 | gen_tb_start(); |
7b5eff4d EV |
3210 | do { |
3211 | check_breakpoint(env, dc); | |
3212 | ||
3213 | if (search_pc) { | |
92414b31 | 3214 | j = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf; |
7b5eff4d EV |
3215 | if (lj < j) { |
3216 | lj++; | |
3217 | while (lj < j) { | |
ab1103de | 3218 | tcg_ctx.gen_opc_instr_start[lj++] = 0; |
7b5eff4d EV |
3219 | } |
3220 | } | |
3221 | if (dc->delayed_branch == 1) { | |
25983cad | 3222 | tcg_ctx.gen_opc_pc[lj] = dc->ppc | 1; |
7b5eff4d | 3223 | } else { |
25983cad | 3224 | tcg_ctx.gen_opc_pc[lj] = dc->pc; |
7b5eff4d | 3225 | } |
ab1103de | 3226 | tcg_ctx.gen_opc_instr_start[lj] = 1; |
c9c99c22 | 3227 | tcg_ctx.gen_opc_icount[lj] = num_insns; |
7b5eff4d EV |
3228 | } |
3229 | ||
3230 | /* Pretty disas. */ | |
3231 | LOG_DIS("%8.8x:\t", dc->pc); | |
3232 | ||
3233 | if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO)) { | |
3234 | gen_io_start(); | |
3235 | } | |
3236 | dc->clear_x = 1; | |
3237 | ||
3238 | insn_len = dc->decoder(env, dc); | |
3239 | dc->ppc = dc->pc; | |
3240 | dc->pc += insn_len; | |
3241 | if (dc->clear_x) { | |
3242 | cris_clear_x_flag(dc); | |
3243 | } | |
3244 | ||
3245 | num_insns++; | |
3246 | /* Check for delayed branches here. If we do it before | |
3247 | actually generating any host code, the simulator will just | |
3248 | loop doing nothing for on this program location. */ | |
3249 | if (dc->delayed_branch) { | |
3250 | dc->delayed_branch--; | |
3251 | if (dc->delayed_branch == 0) { | |
3252 | if (tb->flags & 7) { | |
3253 | t_gen_mov_env_TN(dslot, tcg_const_tl(0)); | |
3254 | } | |
3255 | if (dc->cpustate_changed || !dc->flagx_known | |
3256 | || (dc->flags_x != (tb->flags & X_FLAG))) { | |
3257 | cris_store_direct_jmp(dc); | |
3258 | } | |
3259 | ||
3260 | if (dc->clear_locked_irq) { | |
3261 | dc->clear_locked_irq = 0; | |
3262 | t_gen_mov_env_TN(locked_irq, tcg_const_tl(0)); | |
3263 | } | |
3264 | ||
3265 | if (dc->jmp == JMP_DIRECT_CC) { | |
3266 | int l1; | |
3267 | ||
3268 | l1 = gen_new_label(); | |
3269 | cris_evaluate_flags(dc); | |
3270 | ||
3271 | /* Conditional jmp. */ | |
3272 | tcg_gen_brcondi_tl(TCG_COND_EQ, | |
3273 | env_btaken, 0, l1); | |
3274 | gen_goto_tb(dc, 1, dc->jmp_pc); | |
3275 | gen_set_label(l1); | |
3276 | gen_goto_tb(dc, 0, dc->pc); | |
3277 | dc->is_jmp = DISAS_TB_JUMP; | |
3278 | dc->jmp = JMP_NOJMP; | |
3279 | } else if (dc->jmp == JMP_DIRECT) { | |
3280 | cris_evaluate_flags(dc); | |
3281 | gen_goto_tb(dc, 0, dc->jmp_pc); | |
3282 | dc->is_jmp = DISAS_TB_JUMP; | |
3283 | dc->jmp = JMP_NOJMP; | |
3284 | } else { | |
3285 | t_gen_cc_jmp(env_btarget, tcg_const_tl(dc->pc)); | |
3286 | dc->is_jmp = DISAS_JUMP; | |
3287 | } | |
3288 | break; | |
3289 | } | |
3290 | } | |
3291 | ||
3292 | /* If we are rexecuting a branch due to exceptions on | |
3293 | delay slots dont break. */ | |
ed2803da | 3294 | if (!(tb->pc & 1) && cs->singlestep_enabled) { |
7b5eff4d EV |
3295 | break; |
3296 | } | |
3297 | } while (!dc->is_jmp && !dc->cpustate_changed | |
efd7f486 | 3298 | && tcg_ctx.gen_opc_ptr < gen_opc_end |
7b5eff4d EV |
3299 | && !singlestep |
3300 | && (dc->pc < next_page_start) | |
3301 | && num_insns < max_insns); | |
3302 | ||
3303 | if (dc->clear_locked_irq) { | |
3304 | t_gen_mov_env_TN(locked_irq, tcg_const_tl(0)); | |
3305 | } | |
3306 | ||
3307 | npc = dc->pc; | |
2a44f7f1 | 3308 | |
2e70f6ef PB |
3309 | if (tb->cflags & CF_LAST_IO) |
3310 | gen_io_end(); | |
7b5eff4d EV |
3311 | /* Force an update if the per-tb cpu state has changed. */ |
3312 | if (dc->is_jmp == DISAS_NEXT | |
3313 | && (dc->cpustate_changed || !dc->flagx_known | |
3314 | || (dc->flags_x != (tb->flags & X_FLAG)))) { | |
3315 | dc->is_jmp = DISAS_UPDATE; | |
3316 | tcg_gen_movi_tl(env_pc, npc); | |
3317 | } | |
3318 | /* Broken branch+delayslot sequence. */ | |
3319 | if (dc->delayed_branch == 1) { | |
3320 | /* Set env->dslot to the size of the branch insn. */ | |
3321 | t_gen_mov_env_TN(dslot, tcg_const_tl(dc->pc - dc->ppc)); | |
3322 | cris_store_direct_jmp(dc); | |
3323 | } | |
3324 | ||
3325 | cris_evaluate_flags(dc); | |
3326 | ||
ed2803da | 3327 | if (unlikely(cs->singlestep_enabled)) { |
7b5eff4d EV |
3328 | if (dc->is_jmp == DISAS_NEXT) { |
3329 | tcg_gen_movi_tl(env_pc, npc); | |
3330 | } | |
3331 | t_gen_raise_exception(EXCP_DEBUG); | |
3332 | } else { | |
3333 | switch (dc->is_jmp) { | |
3334 | case DISAS_NEXT: | |
3335 | gen_goto_tb(dc, 1, npc); | |
3336 | break; | |
3337 | default: | |
3338 | case DISAS_JUMP: | |
3339 | case DISAS_UPDATE: | |
3340 | /* indicate that the hash table must be used | |
3341 | to find the next TB */ | |
3342 | tcg_gen_exit_tb(0); | |
3343 | break; | |
3344 | case DISAS_SWI: | |
3345 | case DISAS_TB_JUMP: | |
3346 | /* nothing more to generate */ | |
3347 | break; | |
3348 | } | |
3349 | } | |
806f352d | 3350 | gen_tb_end(tb, num_insns); |
efd7f486 | 3351 | *tcg_ctx.gen_opc_ptr = INDEX_op_end; |
7b5eff4d | 3352 | if (search_pc) { |
92414b31 | 3353 | j = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf; |
7b5eff4d EV |
3354 | lj++; |
3355 | while (lj <= j) { | |
ab1103de | 3356 | tcg_ctx.gen_opc_instr_start[lj++] = 0; |
7b5eff4d EV |
3357 | } |
3358 | } else { | |
3359 | tb->size = dc->pc - pc_start; | |
3360 | tb->icount = num_insns; | |
3361 | } | |
8170028d TS |
3362 | |
3363 | #ifdef DEBUG_DISAS | |
a1aebcb8 | 3364 | #if !DISAS_CRIS |
7b5eff4d EV |
3365 | if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) { |
3366 | log_target_disas(env, pc_start, dc->pc - pc_start, | |
0dd106c5 | 3367 | env->pregs[PR_VR]); |
7b5eff4d | 3368 | qemu_log("\nisize=%d osize=%td\n", |
92414b31 | 3369 | dc->pc - pc_start, tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf); |
7b5eff4d | 3370 | } |
8170028d | 3371 | #endif |
a1aebcb8 | 3372 | #endif |
8170028d TS |
3373 | } |
3374 | ||
a1170bfd | 3375 | void gen_intermediate_code (CPUCRISState *env, struct TranslationBlock *tb) |
8170028d | 3376 | { |
7fd2592d | 3377 | gen_intermediate_code_internal(cris_env_get_cpu(env), tb, false); |
8170028d TS |
3378 | } |
3379 | ||
a1170bfd | 3380 | void gen_intermediate_code_pc (CPUCRISState *env, struct TranslationBlock *tb) |
8170028d | 3381 | { |
7fd2592d | 3382 | gen_intermediate_code_internal(cris_env_get_cpu(env), tb, true); |
8170028d TS |
3383 | } |
3384 | ||
878096ee AF |
3385 | void cris_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf, |
3386 | int flags) | |
8170028d | 3387 | { |
878096ee AF |
3388 | CRISCPU *cpu = CRIS_CPU(cs); |
3389 | CPUCRISState *env = &cpu->env; | |
7b5eff4d EV |
3390 | int i; |
3391 | uint32_t srs; | |
3392 | ||
3393 | if (!env || !f) { | |
3394 | return; | |
3395 | } | |
3396 | ||
3397 | cpu_fprintf(f, "PC=%x CCS=%x btaken=%d btarget=%x\n" | |
3398 | "cc_op=%d cc_src=%d cc_dest=%d cc_result=%x cc_mask=%x\n", | |
3399 | env->pc, env->pregs[PR_CCS], env->btaken, env->btarget, | |
3400 | env->cc_op, | |
3401 | env->cc_src, env->cc_dest, env->cc_result, env->cc_mask); | |
3402 | ||
3403 | ||
3404 | for (i = 0; i < 16; i++) { | |
3405 | cpu_fprintf(f, "%s=%8.8x ", regnames[i], env->regs[i]); | |
3406 | if ((i + 1) % 4 == 0) { | |
3407 | cpu_fprintf(f, "\n"); | |
3408 | } | |
3409 | } | |
3410 | cpu_fprintf(f, "\nspecial regs:\n"); | |
3411 | for (i = 0; i < 16; i++) { | |
3412 | cpu_fprintf(f, "%s=%8.8x ", pregnames[i], env->pregs[i]); | |
3413 | if ((i + 1) % 4 == 0) { | |
3414 | cpu_fprintf(f, "\n"); | |
3415 | } | |
3416 | } | |
3417 | srs = env->pregs[PR_SRS]; | |
3418 | cpu_fprintf(f, "\nsupport function regs bank %x:\n", srs); | |
3419 | if (srs < ARRAY_SIZE(env->sregs)) { | |
3420 | for (i = 0; i < 16; i++) { | |
3421 | cpu_fprintf(f, "s%2.2d=%8.8x ", | |
3422 | i, env->sregs[srs][i]); | |
3423 | if ((i + 1) % 4 == 0) { | |
3424 | cpu_fprintf(f, "\n"); | |
3425 | } | |
3426 | } | |
3427 | } | |
3428 | cpu_fprintf(f, "\n\n"); | |
8170028d TS |
3429 | |
3430 | } | |
3431 | ||
d1a94fec AF |
3432 | void cris_initialize_tcg(void) |
3433 | { | |
3434 | int i; | |
05ba7d5f | 3435 | |
dd10ce6d AF |
3436 | cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env"); |
3437 | cc_x = tcg_global_mem_new(TCG_AREG0, | |
3438 | offsetof(CPUCRISState, cc_x), "cc_x"); | |
3439 | cc_src = tcg_global_mem_new(TCG_AREG0, | |
3440 | offsetof(CPUCRISState, cc_src), "cc_src"); | |
3441 | cc_dest = tcg_global_mem_new(TCG_AREG0, | |
3442 | offsetof(CPUCRISState, cc_dest), | |
3443 | "cc_dest"); | |
3444 | cc_result = tcg_global_mem_new(TCG_AREG0, | |
3445 | offsetof(CPUCRISState, cc_result), | |
3446 | "cc_result"); | |
3447 | cc_op = tcg_global_mem_new(TCG_AREG0, | |
3448 | offsetof(CPUCRISState, cc_op), "cc_op"); | |
3449 | cc_size = tcg_global_mem_new(TCG_AREG0, | |
3450 | offsetof(CPUCRISState, cc_size), | |
3451 | "cc_size"); | |
3452 | cc_mask = tcg_global_mem_new(TCG_AREG0, | |
3453 | offsetof(CPUCRISState, cc_mask), | |
3454 | "cc_mask"); | |
3455 | ||
3456 | env_pc = tcg_global_mem_new(TCG_AREG0, | |
3457 | offsetof(CPUCRISState, pc), | |
3458 | "pc"); | |
3459 | env_btarget = tcg_global_mem_new(TCG_AREG0, | |
3460 | offsetof(CPUCRISState, btarget), | |
3461 | "btarget"); | |
3462 | env_btaken = tcg_global_mem_new(TCG_AREG0, | |
3463 | offsetof(CPUCRISState, btaken), | |
3464 | "btaken"); | |
3465 | for (i = 0; i < 16; i++) { | |
3466 | cpu_R[i] = tcg_global_mem_new(TCG_AREG0, | |
3467 | offsetof(CPUCRISState, regs[i]), | |
3468 | regnames[i]); | |
3469 | } | |
3470 | for (i = 0; i < 16; i++) { | |
3471 | cpu_PR[i] = tcg_global_mem_new(TCG_AREG0, | |
3472 | offsetof(CPUCRISState, pregs[i]), | |
3473 | pregnames[i]); | |
3474 | } | |
8170028d TS |
3475 | } |
3476 | ||
a1170bfd | 3477 | void restore_state_to_opc(CPUCRISState *env, TranslationBlock *tb, int pc_pos) |
d2856f1a | 3478 | { |
25983cad | 3479 | env->pc = tcg_ctx.gen_opc_pc[pc_pos]; |
d2856f1a | 3480 | } |