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tcg: Clean up direct block chaining safety checks
[mirror_qemu.git] / target-cris / translate.c
CommitLineData
8170028d
TS		 1/*
2 * CRIS emulation for qemu: main translation routines.
3 *
05ba7d5f 4 * Copyright (c) 2008 AXIS Communications AB
8170028d
TS		 5 * Written by Edgar E. Iglesias.
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
8167ee88 18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
8170028d
TS		 19 */
20
b41f7df0
EI		 21/*
22 * FIXME:
cf1d97f0 23 * The condition code translation is in need of attention.
b41f7df0
EI		 24 */
25
23b0d7df 26#include "qemu/osdep.h"
8170028d 27#include "cpu.h"
76cad711 28#include "disas/disas.h"
57fec1fe 29#include "tcg-op.h"
2ef6175a 30#include "exec/helper-proto.h"
52819664 31#include "mmu.h"
f08b6170 32#include "exec/cpu_ldst.h"
8170028d
TS		 33#include "crisv32-decode.h"
34
2ef6175a 35#include "exec/helper-gen.h"
a7812ae4 36
a7e30d84 37#include "trace-tcg.h"
508127e2 38#include "exec/log.h"
a7e30d84
LV		 39
40
8170028d
TS		 41#define DISAS_CRIS 0
42#if DISAS_CRIS
93fcfe39 43# define LOG_DIS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__)
8170028d 44#else
d12d51d5 45# define LOG_DIS(...) do { } while (0)
8170028d
TS		 46#endif
47
b41f7df0 48#define D(x)
8170028d
TS		 49#define BUG() (gen_BUG(dc, __FILE__, __LINE__))
50#define BUG_ON(x) ({if (x) BUG();})
51
4f400ab5
EI		 52#define DISAS_SWI 5
53
8170028d
TS		 54/* Used by the decoder. */
55#define EXTRACT_FIELD(src, start, end) \
56 (((src) >> start) & ((1 << (end - start + 1)) - 1))
57
58#define CC_MASK_NZ 0xc
59#define CC_MASK_NZV 0xe
60#define CC_MASK_NZVC 0xf
61#define CC_MASK_RNZV 0x10e
62
1bcea73e 63static TCGv_env cpu_env;
9b32fbf8
EI		 64static TCGv cpu_R[16];
65static TCGv cpu_PR[16];
66static TCGv cc_x;
67static TCGv cc_src;
68static TCGv cc_dest;
69static TCGv cc_result;
70static TCGv cc_op;
71static TCGv cc_size;
72static TCGv cc_mask;
73
74static TCGv env_btaken;
75static TCGv env_btarget;
76static TCGv env_pc;
b41f7df0 77
022c62cb 78#include "exec/gen-icount.h"
2e70f6ef 79
8170028d
TS		 80/* This is the state at translation time. */
81typedef struct DisasContext {
0dd106c5 82 CRISCPU *cpu;
7b5eff4d 83 target_ulong pc, ppc;
8170028d 84
7b5eff4d 85 /* Decoder. */
cf7e0c80 86 unsigned int (*decoder)(CPUCRISState *env, struct DisasContext *dc);
7b5eff4d
EV		 87 uint32_t ir;
88 uint32_t opcode;
89 unsigned int op1;
90 unsigned int op2;
91 unsigned int zsize, zzsize;
92 unsigned int mode;
93 unsigned int postinc;
94
95 unsigned int size;
96 unsigned int src;
97 unsigned int dst;
98 unsigned int cond;
99
100 int update_cc;
101 int cc_op;
102 int cc_size;
103 uint32_t cc_mask;
104
105 int cc_size_uptodate; /* -1 invalid or last written value. */
106
67cc32eb
VL		 107 int cc_x_uptodate; /* 1 - ccs, 2 - known | X_FLAG. 0 not up-to-date. */
108 int flags_uptodate; /* Whether or not $ccs is up-to-date. */
109 int flagx_known; /* Whether or not flags_x has the x flag known at
7b5eff4d
EV		 110 translation time. */
111 int flags_x;
112
113 int clear_x; /* Clear x after this insn? */
114 int clear_prefix; /* Clear prefix after this insn? */
115 int clear_locked_irq; /* Clear the irq lockout. */
116 int cpustate_changed;
117 unsigned int tb_flags; /* tb dependent flags. */
118 int is_jmp;
8170028d 119
5cabc5cc
EI		 120#define JMP_NOJMP 0
121#define JMP_DIRECT 1
122#define JMP_DIRECT_CC 2
123#define JMP_INDIRECT 3
7b5eff4d
EV		 124 int jmp; /* 0=nojmp, 1=direct, 2=indirect. */
125 uint32_t jmp_pc;
2a44f7f1 126
7b5eff4d 127 int delayed_branch;
8170028d 128
7b5eff4d
EV		 129 struct TranslationBlock *tb;
130 int singlestep_enabled;
8170028d
TS		 131} DisasContext;
132
7ccfb2eb 133static void gen_BUG(DisasContext *dc, const char *file, int line)
8170028d 134{
013a2942
PB		 135 fprintf(stderr, "BUG: pc=%x %s %d\n", dc->pc, file, line);
136 if (qemu_log_separate()) {
137 qemu_log("BUG: pc=%x %s %d\n", dc->pc, file, line);
138 }
0dd106c5 139 cpu_abort(CPU(dc->cpu), "%s:%d\n", file, line);
8170028d
TS		 140}
141
9b32fbf8 142static const char *regnames[] =
a825e703 143{
7b5eff4d
EV		 144 "$r0", "$r1", "$r2", "$r3",
145 "$r4", "$r5", "$r6", "$r7",
146 "$r8", "$r9", "$r10", "$r11",
147 "$r12", "$r13", "$sp", "$acr",
a825e703 148};
9b32fbf8 149static const char *pregnames[] =
a825e703 150{
7b5eff4d
EV		 151 "$bz", "$vr", "$pid", "$srs",
152 "$wz", "$exs", "$eda", "$mof",
153 "$dz", "$ebp", "$erp", "$srp",
154 "$nrp", "$ccs", "$usp", "$spc",
a825e703
EI		 155};
156
05ba7d5f 157/* We need this table to handle preg-moves with implicit width. */
9b32fbf8 158static int preg_sizes[] = {
7b5eff4d
EV		 159 1, /* bz. */
160 1, /* vr. */
161 4, /* pid. */
162 1, /* srs. */
163 2, /* wz. */
164 4, 4, 4,
165 4, 4, 4, 4,
166 4, 4, 4, 4,
05ba7d5f
EI		 167};
168
169#define t_gen_mov_TN_env(tn, member) \
37654d9e 170 tcg_gen_ld_tl(tn, cpu_env, offsetof(CPUCRISState, member))
05ba7d5f 171#define t_gen_mov_env_TN(member, tn) \
37654d9e 172 tcg_gen_st_tl(tn, cpu_env, offsetof(CPUCRISState, member))
05ba7d5f
EI		 173
174static inline void t_gen_mov_TN_preg(TCGv tn, int r)
175{
fae38221 176 assert(r >= 0 && r <= 15);
7b5eff4d
EV		 177 if (r == PR_BZ || r == PR_WZ || r == PR_DZ) {
178 tcg_gen_mov_tl(tn, tcg_const_tl(0));
179 } else if (r == PR_VR) {
180 tcg_gen_mov_tl(tn, tcg_const_tl(32));
181 } else {
182 tcg_gen_mov_tl(tn, cpu_PR[r]);
183 }
05ba7d5f 184}
cf1d97f0 185static inline void t_gen_mov_preg_TN(DisasContext *dc, int r, TCGv tn)
05ba7d5f 186{
fae38221 187 assert(r >= 0 && r <= 15);
7b5eff4d
EV		 188 if (r == PR_BZ || r == PR_WZ || r == PR_DZ) {
189 return;
190 } else if (r == PR_SRS) {
191 tcg_gen_andi_tl(cpu_PR[r], tn, 3);
192 } else {
193 if (r == PR_PID) {
194 gen_helper_tlb_flush_pid(cpu_env, tn);
195 }
196 if (dc->tb_flags & S_FLAG && r == PR_SPC) {
197 gen_helper_spc_write(cpu_env, tn);
198 } else if (r == PR_CCS) {
199 dc->cpustate_changed = 1;
200 }
201 tcg_gen_mov_tl(cpu_PR[r], tn);
202 }
05ba7d5f
EI		 203}
204
1884533c
EI		 205/* Sign extend at translation time. */
206static int sign_extend(unsigned int val, unsigned int width)
207{
7b5eff4d 208 int sval;
1884533c 209
7b5eff4d
EV		 210 /* LSL. */
211 val <<= 31 - width;
212 sval = val;
213 /* ASR. */
214 sval >>= 31 - width;
215 return sval;
1884533c
EI		 216}
217
cf7e0c80 218static int cris_fetch(CPUCRISState *env, DisasContext *dc, uint32_t addr,
7b5eff4d
EV		 219 unsigned int size, unsigned int sign)
220{
221 int r;
222
223 switch (size) {
224 case 4:
225 {
226 r = cpu_ldl_code(env, addr);
227 break;
228 }
229 case 2:
230 {
231 if (sign) {
232 r = cpu_ldsw_code(env, addr);
233 } else {
234 r = cpu_lduw_code(env, addr);
235 }
236 break;
237 }
238 case 1:
239 {
240 if (sign) {
241 r = cpu_ldsb_code(env, addr);
242 } else {
243 r = cpu_ldub_code(env, addr);
244 }
245 break;
246 }
247 default:
0dd106c5 248 cpu_abort(CPU(dc->cpu), "Invalid fetch size %d\n", size);
7b5eff4d
EV		 249 break;
250 }
251 return r;
7de141cb
EI		 252}
253
40e9eddd
EI		 254static void cris_lock_irq(DisasContext *dc)
255{
7b5eff4d
EV		 256 dc->clear_locked_irq = 0;
257 t_gen_mov_env_TN(locked_irq, tcg_const_tl(1));
40e9eddd
EI		 258}
259
dceaf394 260static inline void t_gen_raise_exception(uint32_t index)
05ba7d5f 261{
a7812ae4 262 TCGv_i32 tmp = tcg_const_i32(index);
febc9920 263 gen_helper_raise_exception(cpu_env, tmp);
a7812ae4 264 tcg_temp_free_i32(tmp);
05ba7d5f
EI		 265}
266
267static void t_gen_lsl(TCGv d, TCGv a, TCGv b)
268{
7b5eff4d 269 TCGv t0, t_31;
05ba7d5f 270
7b5eff4d
EV		 271 t0 = tcg_temp_new();
272 t_31 = tcg_const_tl(31);
273 tcg_gen_shl_tl(d, a, b);
7dcfb089 274
7b5eff4d
EV		 275 tcg_gen_sub_tl(t0, t_31, b);
276 tcg_gen_sar_tl(t0, t0, t_31);
277 tcg_gen_and_tl(t0, t0, d);
278 tcg_gen_xor_tl(d, d, t0);
279 tcg_temp_free(t0);
280 tcg_temp_free(t_31);
05ba7d5f
EI		 281}
282
283static void t_gen_lsr(TCGv d, TCGv a, TCGv b)
284{
7b5eff4d 285 TCGv t0, t_31;
05ba7d5f 286
7b5eff4d
EV		 287 t0 = tcg_temp_new();
288 t_31 = tcg_temp_new();
289 tcg_gen_shr_tl(d, a, b);
7dcfb089 290
7b5eff4d
EV		 291 tcg_gen_movi_tl(t_31, 31);
292 tcg_gen_sub_tl(t0, t_31, b);
293 tcg_gen_sar_tl(t0, t0, t_31);
294 tcg_gen_and_tl(t0, t0, d);
295 tcg_gen_xor_tl(d, d, t0);
296 tcg_temp_free(t0);
297 tcg_temp_free(t_31);
05ba7d5f
EI		 298}
299
300static void t_gen_asr(TCGv d, TCGv a, TCGv b)
301{
7b5eff4d 302 TCGv t0, t_31;
05ba7d5f 303
7b5eff4d
EV		 304 t0 = tcg_temp_new();
305 t_31 = tcg_temp_new();
306 tcg_gen_sar_tl(d, a, b);
7dcfb089 307
7b5eff4d
EV		 308 tcg_gen_movi_tl(t_31, 31);
309 tcg_gen_sub_tl(t0, t_31, b);
310 tcg_gen_sar_tl(t0, t0, t_31);
311 tcg_gen_or_tl(d, d, t0);
312 tcg_temp_free(t0);
313 tcg_temp_free(t_31);
05ba7d5f
EI		 314}
315
30abcfc7 316static void t_gen_cris_dstep(TCGv d, TCGv a, TCGv b)
aae6b32a 317{
88174019 318 TCGv t = tcg_temp_new();
aae6b32a 319
7b5eff4d
EV		 320 /*
321 * d <<= 1
322 * if (d >= s)
323 * d -= s;
324 */
325 tcg_gen_shli_tl(d, a, 1);
88174019
RH		 326 tcg_gen_sub_tl(t, d, b);
327 tcg_gen_movcond_tl(TCG_COND_GEU, d, d, b, t, d);
328 tcg_temp_free(t);
aae6b32a
EI		 329}
330
40e9eddd
EI		 331static void t_gen_cris_mstep(TCGv d, TCGv a, TCGv b, TCGv ccs)
332{
7b5eff4d 333 TCGv t;
40e9eddd 334
7b5eff4d
EV		 335 /*
336 * d <<= 1
337 * if (n)
338 * d += s;
339 */
340 t = tcg_temp_new();
341 tcg_gen_shli_tl(d, a, 1);
342 tcg_gen_shli_tl(t, ccs, 31 - 3);
343 tcg_gen_sari_tl(t, t, 31);
344 tcg_gen_and_tl(t, t, b);
345 tcg_gen_add_tl(d, d, t);
346 tcg_temp_free(t);
40e9eddd
EI		 347}
348
3157a0a9
EI		 349/* Extended arithmetics on CRIS. */
350static inline void t_gen_add_flag(TCGv d, int flag)
351{
7b5eff4d 352 TCGv c;
3157a0a9 353
7b5eff4d
EV		 354 c = tcg_temp_new();
355 t_gen_mov_TN_preg(c, PR_CCS);
356 /* Propagate carry into d. */
357 tcg_gen_andi_tl(c, c, 1 << flag);
358 if (flag) {
359 tcg_gen_shri_tl(c, c, flag);
360 }
361 tcg_gen_add_tl(d, d, c);
362 tcg_temp_free(c);
3157a0a9
EI		 363}
364
30abcfc7 365static inline void t_gen_addx_carry(DisasContext *dc, TCGv d)
3157a0a9 366{
7b5eff4d
EV		 367 if (dc->flagx_known) {
368 if (dc->flags_x) {
369 TCGv c;
30abcfc7 370
7b5eff4d
EV		 371 c = tcg_temp_new();
372 t_gen_mov_TN_preg(c, PR_CCS);
373 /* C flag is already at bit 0. */
374 tcg_gen_andi_tl(c, c, C_FLAG);
375 tcg_gen_add_tl(d, d, c);
376 tcg_temp_free(c);
377 }
378 } else {
379 TCGv x, c;
380
381 x = tcg_temp_new();
382 c = tcg_temp_new();
383 t_gen_mov_TN_preg(x, PR_CCS);
384 tcg_gen_mov_tl(c, x);
385
386 /* Propagate carry into d if X is set. Branch free. */
387 tcg_gen_andi_tl(c, c, C_FLAG);
388 tcg_gen_andi_tl(x, x, X_FLAG);
389 tcg_gen_shri_tl(x, x, 4);
390
391 tcg_gen_and_tl(x, x, c);
392 tcg_gen_add_tl(d, d, x);
393 tcg_temp_free(x);
394 tcg_temp_free(c);
395 }
3157a0a9
EI		 396}
397
a39f8f3a 398static inline void t_gen_subx_carry(DisasContext *dc, TCGv d)
3157a0a9 399{
7b5eff4d
EV		 400 if (dc->flagx_known) {
401 if (dc->flags_x) {
402 TCGv c;
30abcfc7 403
7b5eff4d
EV		 404 c = tcg_temp_new();
405 t_gen_mov_TN_preg(c, PR_CCS);
406 /* C flag is already at bit 0. */
407 tcg_gen_andi_tl(c, c, C_FLAG);
408 tcg_gen_sub_tl(d, d, c);
409 tcg_temp_free(c);
410 }
411 } else {
412 TCGv x, c;
413
414 x = tcg_temp_new();
415 c = tcg_temp_new();
416 t_gen_mov_TN_preg(x, PR_CCS);
417 tcg_gen_mov_tl(c, x);
418
419 /* Propagate carry into d if X is set. Branch free. */
420 tcg_gen_andi_tl(c, c, C_FLAG);
421 tcg_gen_andi_tl(x, x, X_FLAG);
422 tcg_gen_shri_tl(x, x, 4);
423
424 tcg_gen_and_tl(x, x, c);
425 tcg_gen_sub_tl(d, d, x);
426 tcg_temp_free(x);
427 tcg_temp_free(c);
428 }
3157a0a9
EI		 429}
430
431/* Swap the two bytes within each half word of the s operand.
432 T0 = ((T0 << 8) & 0xff00ff00) | ((T0 >> 8) & 0x00ff00ff) */
433static inline void t_gen_swapb(TCGv d, TCGv s)
434{
7b5eff4d 435 TCGv t, org_s;
3157a0a9 436
7b5eff4d
EV		 437 t = tcg_temp_new();
438 org_s = tcg_temp_new();
3157a0a9 439
7b5eff4d
EV		 440 /* d and s may refer to the same object. */
441 tcg_gen_mov_tl(org_s, s);
442 tcg_gen_shli_tl(t, org_s, 8);
443 tcg_gen_andi_tl(d, t, 0xff00ff00);
444 tcg_gen_shri_tl(t, org_s, 8);
445 tcg_gen_andi_tl(t, t, 0x00ff00ff);
446 tcg_gen_or_tl(d, d, t);
447 tcg_temp_free(t);
448 tcg_temp_free(org_s);
3157a0a9
EI		 449}
450
451/* Swap the halfwords of the s operand. */
452static inline void t_gen_swapw(TCGv d, TCGv s)
453{
7b5eff4d
EV		 454 TCGv t;
455 /* d and s refer the same object. */
456 t = tcg_temp_new();
457 tcg_gen_mov_tl(t, s);
458 tcg_gen_shli_tl(d, t, 16);
459 tcg_gen_shri_tl(t, t, 16);
460 tcg_gen_or_tl(d, d, t);
461 tcg_temp_free(t);
3157a0a9
EI		 462}
463
464/* Reverse the within each byte.
465 T0 = (((T0 << 7) & 0x80808080) |
466 ((T0 << 5) & 0x40404040) |
467 ((T0 << 3) & 0x20202020) |
468 ((T0 << 1) & 0x10101010) |
469 ((T0 >> 1) & 0x08080808) |
470 ((T0 >> 3) & 0x04040404) |
471 ((T0 >> 5) & 0x02020202) |
472 ((T0 >> 7) & 0x01010101));
473 */
474static inline void t_gen_swapr(TCGv d, TCGv s)
475{
7b5eff4d
EV		 476 struct {
477 int shift; /* LSL when positive, LSR when negative. */
478 uint32_t mask;
479 } bitrev[] = {
480 {7, 0x80808080},
481 {5, 0x40404040},
482 {3, 0x20202020},
483 {1, 0x10101010},
484 {-1, 0x08080808},
485 {-3, 0x04040404},
486 {-5, 0x02020202},
487 {-7, 0x01010101}
488 };
489 int i;
490 TCGv t, org_s;
491
492 /* d and s refer the same object. */
493 t = tcg_temp_new();
494 org_s = tcg_temp_new();
495 tcg_gen_mov_tl(org_s, s);
496
497 tcg_gen_shli_tl(t, org_s, bitrev[0].shift);
498 tcg_gen_andi_tl(d, t, bitrev[0].mask);
499 for (i = 1; i < ARRAY_SIZE(bitrev); i++) {
500 if (bitrev[i].shift >= 0) {
501 tcg_gen_shli_tl(t, org_s, bitrev[i].shift);
502 } else {
503 tcg_gen_shri_tl(t, org_s, -bitrev[i].shift);
504 }
505 tcg_gen_andi_tl(t, t, bitrev[i].mask);
506 tcg_gen_or_tl(d, d, t);
507 }
508 tcg_temp_free(t);
509 tcg_temp_free(org_s);
3157a0a9
EI		 510}
511
cf1d97f0 512static void t_gen_cc_jmp(TCGv pc_true, TCGv pc_false)
17ac9754 513{
42a268c2 514 TCGLabel *l1 = gen_new_label();
17ac9754 515
7b5eff4d
EV		 516 /* Conditional jmp. */
517 tcg_gen_mov_tl(env_pc, pc_false);
518 tcg_gen_brcondi_tl(TCG_COND_EQ, env_btaken, 0, l1);
519 tcg_gen_mov_tl(env_pc, pc_true);
520 gen_set_label(l1);
17ac9754
EI		 521}
522
8170028d
TS		 523static void gen_goto_tb(DisasContext *dc, int n, target_ulong dest)
524{
7b5eff4d
EV		 525 TranslationBlock *tb;
526 tb = dc->tb;
5b053a4a
SF		 527
528 if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK) ||
529 (dc->ppc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK)) {
7b5eff4d
EV		 530 tcg_gen_goto_tb(n);
531 tcg_gen_movi_tl(env_pc, dest);
8cfd0495 532 tcg_gen_exit_tb((uintptr_t)tb + n);
7b5eff4d
EV		 533 } else {
534 tcg_gen_movi_tl(env_pc, dest);
535 tcg_gen_exit_tb(0);
536 }
8170028d
TS		 537}
538
05ba7d5f
EI		 539static inline void cris_clear_x_flag(DisasContext *dc)
540{
7b5eff4d
EV		 541 if (dc->flagx_known && dc->flags_x) {
542 dc->flags_uptodate = 0;
543 }
2a44f7f1 544
7b5eff4d
EV		 545 dc->flagx_known = 1;
546 dc->flags_x = 0;
05ba7d5f
EI		 547}
548
30abcfc7 549static void cris_flush_cc_state(DisasContext *dc)
8170028d 550{
7b5eff4d
EV		 551 if (dc->cc_size_uptodate != dc->cc_size) {
552 tcg_gen_movi_tl(cc_size, dc->cc_size);
553 dc->cc_size_uptodate = dc->cc_size;
554 }
555 tcg_gen_movi_tl(cc_op, dc->cc_op);
556 tcg_gen_movi_tl(cc_mask, dc->cc_mask);
30abcfc7
EI		 557}
558
559static void cris_evaluate_flags(DisasContext *dc)
560{
7b5eff4d
EV		 561 if (dc->flags_uptodate) {
562 return;
563 }
564
565 cris_flush_cc_state(dc);
566
567 switch (dc->cc_op) {
568 case CC_OP_MCP:
569 gen_helper_evaluate_flags_mcp(cpu_PR[PR_CCS], cpu_env,
570 cpu_PR[PR_CCS], cc_src,
571 cc_dest, cc_result);
572 break;
573 case CC_OP_MULS:
574 gen_helper_evaluate_flags_muls(cpu_PR[PR_CCS], cpu_env,
575 cpu_PR[PR_CCS], cc_result,
576 cpu_PR[PR_MOF]);
577 break;
578 case CC_OP_MULU:
579 gen_helper_evaluate_flags_mulu(cpu_PR[PR_CCS], cpu_env,
580 cpu_PR[PR_CCS], cc_result,
581 cpu_PR[PR_MOF]);
582 break;
583 case CC_OP_MOVE:
584 case CC_OP_AND:
585 case CC_OP_OR:
586 case CC_OP_XOR:
587 case CC_OP_ASR:
588 case CC_OP_LSR:
589 case CC_OP_LSL:
590 switch (dc->cc_size) {
591 case 4:
592 gen_helper_evaluate_flags_move_4(cpu_PR[PR_CCS],
593 cpu_env, cpu_PR[PR_CCS], cc_result);
594 break;
595 case 2:
596 gen_helper_evaluate_flags_move_2(cpu_PR[PR_CCS],
597 cpu_env, cpu_PR[PR_CCS], cc_result);
598 break;
599 default:
600 gen_helper_evaluate_flags(cpu_env);
601 break;
602 }
603 break;
604 case CC_OP_FLAGS:
605 /* live. */
606 break;
607 case CC_OP_SUB:
608 case CC_OP_CMP:
609 if (dc->cc_size == 4) {
610 gen_helper_evaluate_flags_sub_4(cpu_PR[PR_CCS], cpu_env,
611 cpu_PR[PR_CCS], cc_src, cc_dest, cc_result);
612 } else {
613 gen_helper_evaluate_flags(cpu_env);
614 }
615
616 break;
617 default:
618 switch (dc->cc_size) {
619 case 4:
620 gen_helper_evaluate_flags_alu_4(cpu_PR[PR_CCS], cpu_env,
621 cpu_PR[PR_CCS], cc_src, cc_dest, cc_result);
622 break;
623 default:
624 gen_helper_evaluate_flags(cpu_env);
625 break;
6231868b 626 }
7b5eff4d
EV		 627 break;
628 }
629
630 if (dc->flagx_known) {
631 if (dc->flags_x) {
632 tcg_gen_ori_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], X_FLAG);
633 } else if (dc->cc_op == CC_OP_FLAGS) {
634 tcg_gen_andi_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], ~X_FLAG);
635 }
636 }
637 dc->flags_uptodate = 1;
8170028d
TS		 638}
639
640static void cris_cc_mask(DisasContext *dc, unsigned int mask)
641{
7b5eff4d 642 uint32_t ovl;
8170028d 643
7b5eff4d
EV		 644 if (!mask) {
645 dc->update_cc = 0;
646 return;
647 }
2a44f7f1 648
7b5eff4d
EV		 649 /* Check if we need to evaluate the condition codes due to
650 CC overlaying. */
651 ovl = (dc->cc_mask ^ mask) & ~mask;
652 if (ovl) {
653 /* TODO: optimize this case. It trigs all the time. */
654 cris_evaluate_flags(dc);
655 }
656 dc->cc_mask = mask;
657 dc->update_cc = 1;
8170028d
TS		 658}
659
b41f7df0 660static void cris_update_cc_op(DisasContext *dc, int op, int size)
8170028d 661{
7b5eff4d
EV		 662 dc->cc_op = op;
663 dc->cc_size = size;
664 dc->flags_uptodate = 0;
8170028d
TS		 665}
666
30abcfc7
EI		 667static inline void cris_update_cc_x(DisasContext *dc)
668{
7b5eff4d
EV		 669 /* Save the x flag state at the time of the cc snapshot. */
670 if (dc->flagx_known) {
671 if (dc->cc_x_uptodate == (2 | dc->flags_x)) {
672 return;
673 }
674 tcg_gen_movi_tl(cc_x, dc->flags_x);
675 dc->cc_x_uptodate = 2 | dc->flags_x;
676 } else {
677 tcg_gen_andi_tl(cc_x, cpu_PR[PR_CCS], X_FLAG);
678 dc->cc_x_uptodate = 1;
679 }
30abcfc7
EI		 680}
681
682/* Update cc prior to executing ALU op. Needs source operands untouched. */
683static void cris_pre_alu_update_cc(DisasContext *dc, int op,
7b5eff4d
EV		 684 TCGv dst, TCGv src, int size)
685{
686 if (dc->update_cc) {
687 cris_update_cc_op(dc, op, size);
688 tcg_gen_mov_tl(cc_src, src);
689
690 if (op != CC_OP_MOVE
691 && op != CC_OP_AND
692 && op != CC_OP_OR
693 && op != CC_OP_XOR
694 && op != CC_OP_ASR
695 && op != CC_OP_LSR
696 && op != CC_OP_LSL) {
697 tcg_gen_mov_tl(cc_dest, dst);
698 }
30abcfc7 699
7b5eff4d
EV		 700 cris_update_cc_x(dc);
701 }
30abcfc7 702}
3157a0a9 703
30abcfc7
EI		 704/* Update cc after executing ALU op. needs the result. */
705static inline void cris_update_result(DisasContext *dc, TCGv res)
706{
7b5eff4d
EV		 707 if (dc->update_cc) {
708 tcg_gen_mov_tl(cc_result, res);
709 }
30abcfc7 710}
8170028d 711
30abcfc7
EI		 712/* Returns one if the write back stage should execute. */
713static void cris_alu_op_exec(DisasContext *dc, int op,
7b5eff4d
EV		 714 TCGv dst, TCGv a, TCGv b, int size)
715{
716 /* Emit the ALU insns. */
717 switch (op) {
718 case CC_OP_ADD:
719 tcg_gen_add_tl(dst, a, b);
720 /* Extended arithmetics. */
721 t_gen_addx_carry(dc, dst);
722 break;
723 case CC_OP_ADDC:
724 tcg_gen_add_tl(dst, a, b);
725 t_gen_add_flag(dst, 0); /* C_FLAG. */
726 break;
727 case CC_OP_MCP:
728 tcg_gen_add_tl(dst, a, b);
729 t_gen_add_flag(dst, 8); /* R_FLAG. */
730 break;
731 case CC_OP_SUB:
732 tcg_gen_sub_tl(dst, a, b);
733 /* Extended arithmetics. */
734 t_gen_subx_carry(dc, dst);
735 break;
736 case CC_OP_MOVE:
737 tcg_gen_mov_tl(dst, b);
738 break;
739 case CC_OP_OR:
740 tcg_gen_or_tl(dst, a, b);
741 break;
742 case CC_OP_AND:
743 tcg_gen_and_tl(dst, a, b);
744 break;
745 case CC_OP_XOR:
746 tcg_gen_xor_tl(dst, a, b);
747 break;
748 case CC_OP_LSL:
749 t_gen_lsl(dst, a, b);
750 break;
751 case CC_OP_LSR:
752 t_gen_lsr(dst, a, b);
753 break;
754 case CC_OP_ASR:
755 t_gen_asr(dst, a, b);
756 break;
757 case CC_OP_NEG:
758 tcg_gen_neg_tl(dst, b);
759 /* Extended arithmetics. */
760 t_gen_subx_carry(dc, dst);
761 break;
762 case CC_OP_LZ:
763 gen_helper_lz(dst, b);
764 break;
765 case CC_OP_MULS:
bf45f971 766 tcg_gen_muls2_tl(dst, cpu_PR[PR_MOF], a, b);
7b5eff4d
EV		 767 break;
768 case CC_OP_MULU:
bf45f971 769 tcg_gen_mulu2_tl(dst, cpu_PR[PR_MOF], a, b);
7b5eff4d
EV		 770 break;
771 case CC_OP_DSTEP:
772 t_gen_cris_dstep(dst, a, b);
773 break;
774 case CC_OP_MSTEP:
775 t_gen_cris_mstep(dst, a, b, cpu_PR[PR_CCS]);
776 break;
777 case CC_OP_BOUND:
88174019 778 tcg_gen_movcond_tl(TCG_COND_LEU, dst, a, b, a, b);
7b5eff4d
EV		 779 break;
780 case CC_OP_CMP:
781 tcg_gen_sub_tl(dst, a, b);
782 /* Extended arithmetics. */
783 t_gen_subx_carry(dc, dst);
784 break;
785 default:
79e8ed35 786 qemu_log_mask(LOG_GUEST_ERROR, "illegal ALU op.\n");
7b5eff4d
EV		 787 BUG();
788 break;
789 }
790
791 if (size == 1) {
792 tcg_gen_andi_tl(dst, dst, 0xff);
793 } else if (size == 2) {
794 tcg_gen_andi_tl(dst, dst, 0xffff);
795 }
30abcfc7
EI		 796}
797
798static void cris_alu(DisasContext *dc, int op,
7b5eff4d 799 TCGv d, TCGv op_a, TCGv op_b, int size)
30abcfc7 800{
7b5eff4d
EV		 801 TCGv tmp;
802 int writeback;
30abcfc7 803
7b5eff4d 804 writeback = 1;
31c18d87 805
7b5eff4d
EV		 806 if (op == CC_OP_CMP) {
807 tmp = tcg_temp_new();
808 writeback = 0;
809 } else if (size == 4) {
810 tmp = d;
811 writeback = 0;
812 } else {
813 tmp = tcg_temp_new();
814 }
44696296 815
30abcfc7 816
7b5eff4d
EV		 817 cris_pre_alu_update_cc(dc, op, op_a, op_b, size);
818 cris_alu_op_exec(dc, op, tmp, op_a, op_b, size);
819 cris_update_result(dc, tmp);
05ba7d5f 820
7b5eff4d
EV		 821 /* Writeback. */
822 if (writeback) {
823 if (size == 1) {
824 tcg_gen_andi_tl(d, d, ~0xff);
825 } else {
826 tcg_gen_andi_tl(d, d, ~0xffff);
827 }
828 tcg_gen_or_tl(d, d, tmp);
829 }
830 if (!TCGV_EQUAL(tmp, d)) {
831 tcg_temp_free(tmp);
832 }
8170028d
TS		 833}
834
835static int arith_cc(DisasContext *dc)
836{
7b5eff4d
EV		 837 if (dc->update_cc) {
838 switch (dc->cc_op) {
839 case CC_OP_ADDC: return 1;
840 case CC_OP_ADD: return 1;
841 case CC_OP_SUB: return 1;
842 case CC_OP_DSTEP: return 1;
843 case CC_OP_LSL: return 1;
844 case CC_OP_LSR: return 1;
845 case CC_OP_ASR: return 1;
846 case CC_OP_CMP: return 1;
847 case CC_OP_NEG: return 1;
848 case CC_OP_OR: return 1;
849 case CC_OP_AND: return 1;
850 case CC_OP_XOR: return 1;
851 case CC_OP_MULU: return 1;
852 case CC_OP_MULS: return 1;
853 default:
854 return 0;
855 }
856 }
857 return 0;
8170028d
TS		 858}
859
c5631f48 860static void gen_tst_cc (DisasContext *dc, TCGv cc, int cond)
8170028d 861{
7b5eff4d
EV		 862 int arith_opt, move_opt;
863
864 /* TODO: optimize more condition codes. */
865
866 /*
867 * If the flags are live, we've gotta look into the bits of CCS.
868 * Otherwise, if we just did an arithmetic operation we try to
869 * evaluate the condition code faster.
870 *
871 * When this function is done, T0 should be non-zero if the condition
872 * code is true.
873 */
874 arith_opt = arith_cc(dc) && !dc->flags_uptodate;
875 move_opt = (dc->cc_op == CC_OP_MOVE);
876 switch (cond) {
877 case CC_EQ:
878 if ((arith_opt || move_opt)
879 && dc->cc_x_uptodate != (2 | X_FLAG)) {
880 tcg_gen_setcond_tl(TCG_COND_EQ, cc,
881 cc_result, tcg_const_tl(0));
882 } else {
883 cris_evaluate_flags(dc);
884 tcg_gen_andi_tl(cc,
885 cpu_PR[PR_CCS], Z_FLAG);
886 }
887 break;
888 case CC_NE:
889 if ((arith_opt || move_opt)
890 && dc->cc_x_uptodate != (2 | X_FLAG)) {
891 tcg_gen_mov_tl(cc, cc_result);
892 } else {
893 cris_evaluate_flags(dc);
894 tcg_gen_xori_tl(cc, cpu_PR[PR_CCS],
895 Z_FLAG);
896 tcg_gen_andi_tl(cc, cc, Z_FLAG);
897 }
898 break;
899 case CC_CS:
900 cris_evaluate_flags(dc);
901 tcg_gen_andi_tl(cc, cpu_PR[PR_CCS], C_FLAG);
902 break;
903 case CC_CC:
904 cris_evaluate_flags(dc);
905 tcg_gen_xori_tl(cc, cpu_PR[PR_CCS], C_FLAG);
906 tcg_gen_andi_tl(cc, cc, C_FLAG);
907 break;
908 case CC_VS:
909 cris_evaluate_flags(dc);
910 tcg_gen_andi_tl(cc, cpu_PR[PR_CCS], V_FLAG);
911 break;
912 case CC_VC:
913 cris_evaluate_flags(dc);
914 tcg_gen_xori_tl(cc, cpu_PR[PR_CCS],
915 V_FLAG);
916 tcg_gen_andi_tl(cc, cc, V_FLAG);
917 break;
918 case CC_PL:
919 if (arith_opt || move_opt) {
920 int bits = 31;
921
922 if (dc->cc_size == 1) {
923 bits = 7;
924 } else if (dc->cc_size == 2) {
925 bits = 15;
926 }
927
928 tcg_gen_shri_tl(cc, cc_result, bits);
929 tcg_gen_xori_tl(cc, cc, 1);
930 } else {
931 cris_evaluate_flags(dc);
932 tcg_gen_xori_tl(cc, cpu_PR[PR_CCS],
933 N_FLAG);
934 tcg_gen_andi_tl(cc, cc, N_FLAG);
935 }
936 break;
937 case CC_MI:
938 if (arith_opt || move_opt) {
939 int bits = 31;
940
941 if (dc->cc_size == 1) {
942 bits = 7;
943 } else if (dc->cc_size == 2) {
944 bits = 15;
945 }
946
947 tcg_gen_shri_tl(cc, cc_result, bits);
948 tcg_gen_andi_tl(cc, cc, 1);
949 } else {
950 cris_evaluate_flags(dc);
951 tcg_gen_andi_tl(cc, cpu_PR[PR_CCS],
952 N_FLAG);
953 }
954 break;
955 case CC_LS:
956 cris_evaluate_flags(dc);
957 tcg_gen_andi_tl(cc, cpu_PR[PR_CCS],
958 C_FLAG | Z_FLAG);
959 break;
960 case CC_HI:
961 cris_evaluate_flags(dc);
962 {
963 TCGv tmp;
964
965 tmp = tcg_temp_new();
966 tcg_gen_xori_tl(tmp, cpu_PR[PR_CCS],
967 C_FLAG | Z_FLAG);
968 /* Overlay the C flag on top of the Z. */
969 tcg_gen_shli_tl(cc, tmp, 2);
970 tcg_gen_and_tl(cc, tmp, cc);
971 tcg_gen_andi_tl(cc, cc, Z_FLAG);
972
973 tcg_temp_free(tmp);
974 }
975 break;
976 case CC_GE:
977 cris_evaluate_flags(dc);
978 /* Overlay the V flag on top of the N. */
979 tcg_gen_shli_tl(cc, cpu_PR[PR_CCS], 2);
980 tcg_gen_xor_tl(cc,
981 cpu_PR[PR_CCS], cc);
982 tcg_gen_andi_tl(cc, cc, N_FLAG);
983 tcg_gen_xori_tl(cc, cc, N_FLAG);
984 break;
985 case CC_LT:
986 cris_evaluate_flags(dc);
987 /* Overlay the V flag on top of the N. */
988 tcg_gen_shli_tl(cc, cpu_PR[PR_CCS], 2);
989 tcg_gen_xor_tl(cc,
990 cpu_PR[PR_CCS], cc);
991 tcg_gen_andi_tl(cc, cc, N_FLAG);
992 break;
993 case CC_GT:
994 cris_evaluate_flags(dc);
995 {
996 TCGv n, z;
997
998 n = tcg_temp_new();
999 z = tcg_temp_new();
1000
1001 /* To avoid a shift we overlay everything on
1002 the V flag. */
1003 tcg_gen_shri_tl(n, cpu_PR[PR_CCS], 2);
1004 tcg_gen_shri_tl(z, cpu_PR[PR_CCS], 1);
1005 /* invert Z. */
1006 tcg_gen_xori_tl(z, z, 2);
1007
1008 tcg_gen_xor_tl(n, n, cpu_PR[PR_CCS]);
1009 tcg_gen_xori_tl(n, n, 2);
1010 tcg_gen_and_tl(cc, z, n);
1011 tcg_gen_andi_tl(cc, cc, 2);
1012
1013 tcg_temp_free(n);
1014 tcg_temp_free(z);
1015 }
1016 break;
1017 case CC_LE:
1018 cris_evaluate_flags(dc);
1019 {
1020 TCGv n, z;
1021
1022 n = tcg_temp_new();
1023 z = tcg_temp_new();
1024
1025 /* To avoid a shift we overlay everything on
1026 the V flag. */
1027 tcg_gen_shri_tl(n, cpu_PR[PR_CCS], 2);
1028 tcg_gen_shri_tl(z, cpu_PR[PR_CCS], 1);
1029
1030 tcg_gen_xor_tl(n, n, cpu_PR[PR_CCS]);
1031 tcg_gen_or_tl(cc, z, n);
1032 tcg_gen_andi_tl(cc, cc, 2);
1033
1034 tcg_temp_free(n);
1035 tcg_temp_free(z);
1036 }
1037 break;
1038 case CC_P:
1039 cris_evaluate_flags(dc);
1040 tcg_gen_andi_tl(cc, cpu_PR[PR_CCS], P_FLAG);
1041 break;
1042 case CC_A:
1043 tcg_gen_movi_tl(cc, 1);
1044 break;
1045 default:
1046 BUG();
1047 break;
1048 };
8170028d
TS		 1049}
1050
2a44f7f1
EI		 1051static void cris_store_direct_jmp(DisasContext *dc)
1052{
7b5eff4d
EV		 1053 /* Store the direct jmp state into the cpu-state. */
1054 if (dc->jmp == JMP_DIRECT || dc->jmp == JMP_DIRECT_CC) {
1055 if (dc->jmp == JMP_DIRECT) {
1056 tcg_gen_movi_tl(env_btaken, 1);
1057 }
1058 tcg_gen_movi_tl(env_btarget, dc->jmp_pc);
1059 dc->jmp = JMP_INDIRECT;
1060 }
2a44f7f1
EI		 1061}
1062
1063static void cris_prepare_cc_branch (DisasContext *dc,
7b5eff4d 1064 int offset, int cond)
8170028d 1065{
7b5eff4d
EV		 1066 /* This helps us re-schedule the micro-code to insns in delay-slots
1067 before the actual jump. */
1068 dc->delayed_branch = 2;
1069 dc->jmp = JMP_DIRECT_CC;
1070 dc->jmp_pc = dc->pc + offset;
2a44f7f1 1071
7b5eff4d
EV		 1072 gen_tst_cc(dc, env_btaken, cond);
1073 tcg_gen_movi_tl(env_btarget, dc->jmp_pc);
8170028d
TS		 1074}
1075
b41f7df0 1076
2a44f7f1
EI		 1077/* jumps, when the dest is in a live reg for example. Direct should be set
1078 when the dest addr is constant to allow tb chaining. */
1079static inline void cris_prepare_jmp (DisasContext *dc, unsigned int type)
8170028d 1080{
7b5eff4d
EV		 1081 /* This helps us re-schedule the micro-code to insns in delay-slots
1082 before the actual jump. */
1083 dc->delayed_branch = 2;
1084 dc->jmp = type;
1085 if (type == JMP_INDIRECT) {
1086 tcg_gen_movi_tl(env_btaken, 1);
1087 }
8170028d
TS		 1088}
1089
a7812ae4
PB		 1090static void gen_load64(DisasContext *dc, TCGv_i64 dst, TCGv addr)
1091{
97ed5ccd 1092 int mem_index = cpu_mmu_index(&dc->cpu->env, false);
a7812ae4 1093
7b5eff4d
EV		 1094 /* If we get a fault on a delayslot we must keep the jmp state in
1095 the cpu-state to be able to re-execute the jmp. */
1096 if (dc->delayed_branch == 1) {
1097 cris_store_direct_jmp(dc);
1098 }
a7812ae4 1099
a1d22a36 1100 tcg_gen_qemu_ld_i64(dst, addr, mem_index, MO_TEQ);
a7812ae4
PB		 1101}
1102
9b32fbf8 1103static void gen_load(DisasContext *dc, TCGv dst, TCGv addr,
7b5eff4d
EV		 1104 unsigned int size, int sign)
1105{
97ed5ccd 1106 int mem_index = cpu_mmu_index(&dc->cpu->env, false);
7b5eff4d
EV		 1107
1108 /* If we get a fault on a delayslot we must keep the jmp state in
1109 the cpu-state to be able to re-execute the jmp. */
1110 if (dc->delayed_branch == 1) {
1111 cris_store_direct_jmp(dc);
1112 }
1113
a1d22a36
RH		 1114 tcg_gen_qemu_ld_tl(dst, addr, mem_index,
1115 MO_TE + ctz32(size) + (sign ? MO_SIGN : 0));
8170028d
TS		 1116}
1117
9b32fbf8 1118static void gen_store (DisasContext *dc, TCGv addr, TCGv val,
7b5eff4d 1119 unsigned int size)
8170028d 1120{
97ed5ccd 1121 int mem_index = cpu_mmu_index(&dc->cpu->env, false);
b41f7df0 1122
7b5eff4d
EV		 1123 /* If we get a fault on a delayslot we must keep the jmp state in
1124 the cpu-state to be able to re-execute the jmp. */
1125 if (dc->delayed_branch == 1) {
1126 cris_store_direct_jmp(dc);
1127 }
2a44f7f1
EI		 1128
1129
7b5eff4d
EV		 1130 /* Conditional writes. We only support the kind were X and P are known
1131 at translation time. */
1132 if (dc->flagx_known && dc->flags_x && (dc->tb_flags & P_FLAG)) {
1133 dc->postinc = 0;
1134 cris_evaluate_flags(dc);
1135 tcg_gen_ori_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], C_FLAG);
1136 return;
1137 }
2a44f7f1 1138
a1d22a36 1139 tcg_gen_qemu_st_tl(val, addr, mem_index, MO_TE + ctz32(size));
2a44f7f1 1140
7b5eff4d
EV		 1141 if (dc->flagx_known && dc->flags_x) {
1142 cris_evaluate_flags(dc);
1143 tcg_gen_andi_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], ~C_FLAG);
1144 }
8170028d
TS		 1145}
1146
05ba7d5f 1147static inline void t_gen_sext(TCGv d, TCGv s, int size)
8170028d 1148{
7b5eff4d
EV		 1149 if (size == 1) {
1150 tcg_gen_ext8s_i32(d, s);
1151 } else if (size == 2) {
1152 tcg_gen_ext16s_i32(d, s);
1153 } else if (!TCGV_EQUAL(d, s)) {
1154 tcg_gen_mov_tl(d, s);
1155 }
8170028d
TS		 1156}
1157
05ba7d5f 1158static inline void t_gen_zext(TCGv d, TCGv s, int size)
8170028d 1159{
7b5eff4d
EV		 1160 if (size == 1) {
1161 tcg_gen_ext8u_i32(d, s);
1162 } else if (size == 2) {
1163 tcg_gen_ext16u_i32(d, s);
1164 } else if (!TCGV_EQUAL(d, s)) {
1165 tcg_gen_mov_tl(d, s);
1166 }
8170028d
TS		 1167}
1168
1169#if DISAS_CRIS
1170static char memsize_char(int size)
1171{
7b5eff4d
EV		 1172 switch (size) {
1173 case 1: return 'b'; break;
1174 case 2: return 'w'; break;
1175 case 4: return 'd'; break;
1176 default:
1177 return 'x';
1178 break;
1179 }
8170028d
TS		 1180}
1181#endif
1182
30abcfc7 1183static inline unsigned int memsize_z(DisasContext *dc)
8170028d 1184{
7b5eff4d 1185 return dc->zsize + 1;
8170028d
TS		 1186}
1187
30abcfc7 1188static inline unsigned int memsize_zz(DisasContext *dc)
8170028d 1189{
7b5eff4d
EV		 1190 switch (dc->zzsize) {
1191 case 0: return 1;
1192 case 1: return 2;
1193 default:
1194 return 4;
1195 }
8170028d
TS		 1196}
1197
c7d05695 1198static inline void do_postinc (DisasContext *dc, int size)
8170028d 1199{
7b5eff4d
EV		 1200 if (dc->postinc) {
1201 tcg_gen_addi_tl(cpu_R[dc->op1], cpu_R[dc->op1], size);
1202 }
8170028d
TS		 1203}
1204
30abcfc7 1205static inline void dec_prep_move_r(DisasContext *dc, int rs, int rd,
7b5eff4d 1206 int size, int s_ext, TCGv dst)
8170028d 1207{
7b5eff4d
EV		 1208 if (s_ext) {
1209 t_gen_sext(dst, cpu_R[rs], size);
1210 } else {
1211 t_gen_zext(dst, cpu_R[rs], size);
1212 }
8170028d
TS		 1213}
1214
1215/* Prepare T0 and T1 for a register alu operation.
1216 s_ext decides if the operand1 should be sign-extended or zero-extended when
1217 needed. */
1218static void dec_prep_alu_r(DisasContext *dc, int rs, int rd,
7b5eff4d 1219 int size, int s_ext, TCGv dst, TCGv src)
8170028d 1220{
7b5eff4d 1221 dec_prep_move_r(dc, rs, rd, size, s_ext, src);
8170028d 1222
7b5eff4d
EV		 1223 if (s_ext) {
1224 t_gen_sext(dst, cpu_R[rd], size);
1225 } else {
1226 t_gen_zext(dst, cpu_R[rd], size);
1227 }
8170028d
TS		 1228}
1229
cf7e0c80
AJ		 1230static int dec_prep_move_m(CPUCRISState *env, DisasContext *dc,
1231 int s_ext, int memsize, TCGv dst)
8170028d 1232{
7b5eff4d
EV		 1233 unsigned int rs;
1234 uint32_t imm;
1235 int is_imm;
1236 int insn_len = 2;
1237
1238 rs = dc->op1;
1239 is_imm = rs == 15 && dc->postinc;
1240
1241 /* Load [$rs] onto T1. */
1242 if (is_imm) {
1243 insn_len = 2 + memsize;
1244 if (memsize == 1) {
1245 insn_len++;
1246 }
1247
1248 imm = cris_fetch(env, dc, dc->pc + 2, memsize, s_ext);
1249 tcg_gen_movi_tl(dst, imm);
1250 dc->postinc = 0;
1251 } else {
1252 cris_flush_cc_state(dc);
1253 gen_load(dc, dst, cpu_R[rs], memsize, 0);
1254 if (s_ext) {
1255 t_gen_sext(dst, dst, memsize);
1256 } else {
1257 t_gen_zext(dst, dst, memsize);
1258 }
1259 }
1260 return insn_len;
cf1d97f0
EI		 1261}
1262
1263/* Prepare T0 and T1 for a memory + alu operation.
1264 s_ext decides if the operand1 should be sign-extended or zero-extended when
1265 needed. */
cf7e0c80
AJ		 1266static int dec_prep_alu_m(CPUCRISState *env, DisasContext *dc,
1267 int s_ext, int memsize, TCGv dst, TCGv src)
cf1d97f0 1268{
7b5eff4d 1269 int insn_len;
cf1d97f0 1270
7b5eff4d
EV		 1271 insn_len = dec_prep_move_m(env, dc, s_ext, memsize, src);
1272 tcg_gen_mov_tl(dst, cpu_R[dc->op2]);
1273 return insn_len;
8170028d
TS		 1274}
1275
1276#if DISAS_CRIS
1277static const char *cc_name(int cc)
1278{
7b5eff4d
EV		 1279 static const char *cc_names[16] = {
1280 "cc", "cs", "ne", "eq", "vc", "vs", "pl", "mi",
1281 "ls", "hi", "ge", "lt", "gt", "le", "a", "p"
1282 };
1283 assert(cc < 16);
1284 return cc_names[cc];
8170028d
TS		 1285}
1286#endif
1287
b41f7df0
EI		 1288/* Start of insn decoders. */
1289
cf7e0c80 1290static int dec_bccq(CPUCRISState *env, DisasContext *dc)
8170028d 1291{
7b5eff4d
EV		 1292 int32_t offset;
1293 int sign;
1294 uint32_t cond = dc->op2;
8170028d 1295
7b5eff4d
EV		 1296 offset = EXTRACT_FIELD(dc->ir, 1, 7);
1297 sign = EXTRACT_FIELD(dc->ir, 0, 0);
8170028d 1298
7b5eff4d
EV		 1299 offset *= 2;
1300 offset |= sign << 8;
1301 offset = sign_extend(offset, 8);
8170028d 1302
7b5eff4d 1303 LOG_DIS("b%s %x\n", cc_name(cond), dc->pc + offset);
2a44f7f1 1304
7b5eff4d
EV		 1305 /* op2 holds the condition-code. */
1306 cris_cc_mask(dc, 0);
1307 cris_prepare_cc_branch(dc, offset, cond);
1308 return 2;
8170028d 1309}
cf7e0c80 1310static int dec_addoq(CPUCRISState *env, DisasContext *dc)
8170028d 1311{
7b5eff4d 1312 int32_t imm;
8170028d 1313
7b5eff4d
EV		 1314 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 7);
1315 imm = sign_extend(dc->op1, 7);
8170028d 1316
7b5eff4d
EV		 1317 LOG_DIS("addoq %d, $r%u\n", imm, dc->op2);
1318 cris_cc_mask(dc, 0);
1319 /* Fetch register operand, */
1320 tcg_gen_addi_tl(cpu_R[R_ACR], cpu_R[dc->op2], imm);
fb48f71b 1321
7b5eff4d 1322 return 2;
8170028d 1323}
cf7e0c80 1324static int dec_addq(CPUCRISState *env, DisasContext *dc)
8170028d 1325{
7b5eff4d 1326 LOG_DIS("addq %u, $r%u\n", dc->op1, dc->op2);
8170028d 1327
7b5eff4d 1328 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5);
8170028d 1329
7b5eff4d 1330 cris_cc_mask(dc, CC_MASK_NZVC);
30abcfc7 1331
7b5eff4d
EV		 1332 cris_alu(dc, CC_OP_ADD,
1333 cpu_R[dc->op2], cpu_R[dc->op2], tcg_const_tl(dc->op1), 4);
1334 return 2;
8170028d 1335}
cf7e0c80 1336static int dec_moveq(CPUCRISState *env, DisasContext *dc)
8170028d 1337{
7b5eff4d 1338 uint32_t imm;
8170028d 1339
7b5eff4d
EV		 1340 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5);
1341 imm = sign_extend(dc->op1, 5);
1342 LOG_DIS("moveq %d, $r%u\n", imm, dc->op2);
8170028d 1343
7b5eff4d
EV		 1344 tcg_gen_movi_tl(cpu_R[dc->op2], imm);
1345 return 2;
8170028d 1346}
cf7e0c80 1347static int dec_subq(CPUCRISState *env, DisasContext *dc)
8170028d 1348{
7b5eff4d 1349 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5);
8170028d 1350
7b5eff4d 1351 LOG_DIS("subq %u, $r%u\n", dc->op1, dc->op2);
8170028d 1352
7b5eff4d
EV		 1353 cris_cc_mask(dc, CC_MASK_NZVC);
1354 cris_alu(dc, CC_OP_SUB,
1355 cpu_R[dc->op2], cpu_R[dc->op2], tcg_const_tl(dc->op1), 4);
1356 return 2;
8170028d 1357}
cf7e0c80 1358static int dec_cmpq(CPUCRISState *env, DisasContext *dc)
8170028d 1359{
7b5eff4d
EV		 1360 uint32_t imm;
1361 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5);
1362 imm = sign_extend(dc->op1, 5);
8170028d 1363
7b5eff4d
EV		 1364 LOG_DIS("cmpq %d, $r%d\n", imm, dc->op2);
1365 cris_cc_mask(dc, CC_MASK_NZVC);
30abcfc7 1366
7b5eff4d
EV		 1367 cris_alu(dc, CC_OP_CMP,
1368 cpu_R[dc->op2], cpu_R[dc->op2], tcg_const_tl(imm), 4);
1369 return 2;
8170028d 1370}
cf7e0c80 1371static int dec_andq(CPUCRISState *env, DisasContext *dc)
8170028d 1372{
7b5eff4d
EV		 1373 uint32_t imm;
1374 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5);
1375 imm = sign_extend(dc->op1, 5);
8170028d 1376
7b5eff4d
EV		 1377 LOG_DIS("andq %d, $r%d\n", imm, dc->op2);
1378 cris_cc_mask(dc, CC_MASK_NZ);
30abcfc7 1379
7b5eff4d
EV		 1380 cris_alu(dc, CC_OP_AND,
1381 cpu_R[dc->op2], cpu_R[dc->op2], tcg_const_tl(imm), 4);
1382 return 2;
8170028d 1383}
cf7e0c80 1384static int dec_orq(CPUCRISState *env, DisasContext *dc)
8170028d 1385{
7b5eff4d
EV		 1386 uint32_t imm;
1387 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5);
1388 imm = sign_extend(dc->op1, 5);
1389 LOG_DIS("orq %d, $r%d\n", imm, dc->op2);
1390 cris_cc_mask(dc, CC_MASK_NZ);
30abcfc7 1391
7b5eff4d
EV		 1392 cris_alu(dc, CC_OP_OR,
1393 cpu_R[dc->op2], cpu_R[dc->op2], tcg_const_tl(imm), 4);
1394 return 2;
8170028d 1395}
cf7e0c80 1396static int dec_btstq(CPUCRISState *env, DisasContext *dc)
8170028d 1397{
7b5eff4d
EV		 1398 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 4);
1399 LOG_DIS("btstq %u, $r%d\n", dc->op1, dc->op2);
17ac9754 1400
7b5eff4d
EV		 1401 cris_cc_mask(dc, CC_MASK_NZ);
1402 cris_evaluate_flags(dc);
febc9920 1403 gen_helper_btst(cpu_PR[PR_CCS], cpu_env, cpu_R[dc->op2],
7b5eff4d
EV		 1404 tcg_const_tl(dc->op1), cpu_PR[PR_CCS]);
1405 cris_alu(dc, CC_OP_MOVE,
1406 cpu_R[dc->op2], cpu_R[dc->op2], cpu_R[dc->op2], 4);
1407 cris_update_cc_op(dc, CC_OP_FLAGS, 4);
1408 dc->flags_uptodate = 1;
1409 return 2;
8170028d 1410}
cf7e0c80 1411static int dec_asrq(CPUCRISState *env, DisasContext *dc)
8170028d 1412{
7b5eff4d
EV		 1413 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 4);
1414 LOG_DIS("asrq %u, $r%d\n", dc->op1, dc->op2);
1415 cris_cc_mask(dc, CC_MASK_NZ);
30abcfc7 1416
7b5eff4d
EV		 1417 tcg_gen_sari_tl(cpu_R[dc->op2], cpu_R[dc->op2], dc->op1);
1418 cris_alu(dc, CC_OP_MOVE,
1419 cpu_R[dc->op2],
1420 cpu_R[dc->op2], cpu_R[dc->op2], 4);
1421 return 2;
8170028d 1422}
cf7e0c80 1423static int dec_lslq(CPUCRISState *env, DisasContext *dc)
8170028d 1424{
7b5eff4d
EV		 1425 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 4);
1426 LOG_DIS("lslq %u, $r%d\n", dc->op1, dc->op2);
8170028d 1427
7b5eff4d 1428 cris_cc_mask(dc, CC_MASK_NZ);
30abcfc7 1429
7b5eff4d 1430 tcg_gen_shli_tl(cpu_R[dc->op2], cpu_R[dc->op2], dc->op1);
2a44f7f1 1431
7b5eff4d
EV		 1432 cris_alu(dc, CC_OP_MOVE,
1433 cpu_R[dc->op2],
1434 cpu_R[dc->op2], cpu_R[dc->op2], 4);
1435 return 2;
8170028d 1436}
cf7e0c80 1437static int dec_lsrq(CPUCRISState *env, DisasContext *dc)
8170028d 1438{
7b5eff4d
EV		 1439 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 4);
1440 LOG_DIS("lsrq %u, $r%d\n", dc->op1, dc->op2);
8170028d 1441
7b5eff4d 1442 cris_cc_mask(dc, CC_MASK_NZ);
30abcfc7 1443
7b5eff4d
EV		 1444 tcg_gen_shri_tl(cpu_R[dc->op2], cpu_R[dc->op2], dc->op1);
1445 cris_alu(dc, CC_OP_MOVE,
1446 cpu_R[dc->op2],
1447 cpu_R[dc->op2], cpu_R[dc->op2], 4);
1448 return 2;
8170028d
TS		 1449}
1450
cf7e0c80 1451static int dec_move_r(CPUCRISState *env, DisasContext *dc)
8170028d 1452{
7b5eff4d
EV		 1453 int size = memsize_zz(dc);
1454
1455 LOG_DIS("move.%c $r%u, $r%u\n",
1456 memsize_char(size), dc->op1, dc->op2);
1457
1458 cris_cc_mask(dc, CC_MASK_NZ);
1459 if (size == 4) {
1460 dec_prep_move_r(dc, dc->op1, dc->op2, size, 0, cpu_R[dc->op2]);
1461 cris_cc_mask(dc, CC_MASK_NZ);
1462 cris_update_cc_op(dc, CC_OP_MOVE, 4);
1463 cris_update_cc_x(dc);
1464 cris_update_result(dc, cpu_R[dc->op2]);
1465 } else {
1466 TCGv t0;
1467
1468 t0 = tcg_temp_new();
1469 dec_prep_move_r(dc, dc->op1, dc->op2, size, 0, t0);
1470 cris_alu(dc, CC_OP_MOVE,
1471 cpu_R[dc->op2],
1472 cpu_R[dc->op2], t0, size);
1473 tcg_temp_free(t0);
1474 }
1475 return 2;
8170028d
TS		 1476}
1477
cf7e0c80 1478static int dec_scc_r(CPUCRISState *env, DisasContext *dc)
8170028d 1479{
7b5eff4d 1480 int cond = dc->op2;
8170028d 1481
7b5eff4d
EV		 1482 LOG_DIS("s%s $r%u\n",
1483 cc_name(cond), dc->op1);
8170028d 1484
88174019
RH		 1485 gen_tst_cc(dc, cpu_R[dc->op1], cond);
1486 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_R[dc->op1], cpu_R[dc->op1], 0);
8170028d 1487
7b5eff4d
EV		 1488 cris_cc_mask(dc, 0);
1489 return 2;
8170028d
TS		 1490}
1491
fb48f71b
EI		 1492static inline void cris_alu_alloc_temps(DisasContext *dc, int size, TCGv *t)
1493{
7b5eff4d
EV		 1494 if (size == 4) {
1495 t[0] = cpu_R[dc->op2];
1496 t[1] = cpu_R[dc->op1];
1497 } else {
1498 t[0] = tcg_temp_new();
1499 t[1] = tcg_temp_new();
1500 }
fb48f71b
EI		 1501}
1502
1503static inline void cris_alu_free_temps(DisasContext *dc, int size, TCGv *t)
1504{
7b5eff4d
EV		 1505 if (size != 4) {
1506 tcg_temp_free(t[0]);
1507 tcg_temp_free(t[1]);
1508 }
fb48f71b
EI		 1509}
1510
cf7e0c80 1511static int dec_and_r(CPUCRISState *env, DisasContext *dc)
8170028d 1512{
7b5eff4d
EV		 1513 TCGv t[2];
1514 int size = memsize_zz(dc);
8170028d 1515
7b5eff4d
EV		 1516 LOG_DIS("and.%c $r%u, $r%u\n",
1517 memsize_char(size), dc->op1, dc->op2);
fb48f71b 1518
7b5eff4d 1519 cris_cc_mask(dc, CC_MASK_NZ);
30abcfc7 1520
7b5eff4d
EV		 1521 cris_alu_alloc_temps(dc, size, t);
1522 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]);
1523 cris_alu(dc, CC_OP_AND, cpu_R[dc->op2], t[0], t[1], size);
1524 cris_alu_free_temps(dc, size, t);
1525 return 2;
8170028d
TS		 1526}
1527
cf7e0c80 1528static int dec_lz_r(CPUCRISState *env, DisasContext *dc)
8170028d 1529{
7b5eff4d
EV		 1530 TCGv t0;
1531 LOG_DIS("lz $r%u, $r%u\n",
1532 dc->op1, dc->op2);
1533 cris_cc_mask(dc, CC_MASK_NZ);
1534 t0 = tcg_temp_new();
1535 dec_prep_alu_r(dc, dc->op1, dc->op2, 4, 0, cpu_R[dc->op2], t0);
1536 cris_alu(dc, CC_OP_LZ, cpu_R[dc->op2], cpu_R[dc->op2], t0, 4);
1537 tcg_temp_free(t0);
1538 return 2;
8170028d
TS		 1539}
1540
cf7e0c80 1541static int dec_lsl_r(CPUCRISState *env, DisasContext *dc)
8170028d 1542{
7b5eff4d
EV		 1543 TCGv t[2];
1544 int size = memsize_zz(dc);
8170028d 1545
7b5eff4d
EV		 1546 LOG_DIS("lsl.%c $r%u, $r%u\n",
1547 memsize_char(size), dc->op1, dc->op2);
30abcfc7 1548
7b5eff4d
EV		 1549 cris_cc_mask(dc, CC_MASK_NZ);
1550 cris_alu_alloc_temps(dc, size, t);
1551 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]);
1552 tcg_gen_andi_tl(t[1], t[1], 63);
1553 cris_alu(dc, CC_OP_LSL, cpu_R[dc->op2], t[0], t[1], size);
1554 cris_alu_alloc_temps(dc, size, t);
1555 return 2;
8170028d
TS		 1556}
1557
cf7e0c80 1558static int dec_lsr_r(CPUCRISState *env, DisasContext *dc)
8170028d 1559{
7b5eff4d
EV		 1560 TCGv t[2];
1561 int size = memsize_zz(dc);
8170028d 1562
7b5eff4d
EV		 1563 LOG_DIS("lsr.%c $r%u, $r%u\n",
1564 memsize_char(size), dc->op1, dc->op2);
30abcfc7 1565
7b5eff4d
EV		 1566 cris_cc_mask(dc, CC_MASK_NZ);
1567 cris_alu_alloc_temps(dc, size, t);
1568 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]);
1569 tcg_gen_andi_tl(t[1], t[1], 63);
1570 cris_alu(dc, CC_OP_LSR, cpu_R[dc->op2], t[0], t[1], size);
1571 cris_alu_free_temps(dc, size, t);
1572 return 2;
8170028d
TS		 1573}
1574
cf7e0c80 1575static int dec_asr_r(CPUCRISState *env, DisasContext *dc)
8170028d 1576{
7b5eff4d
EV		 1577 TCGv t[2];
1578 int size = memsize_zz(dc);
8170028d 1579
7b5eff4d
EV		 1580 LOG_DIS("asr.%c $r%u, $r%u\n",
1581 memsize_char(size), dc->op1, dc->op2);
30abcfc7 1582
7b5eff4d
EV		 1583 cris_cc_mask(dc, CC_MASK_NZ);
1584 cris_alu_alloc_temps(dc, size, t);
1585 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 1, t[0], t[1]);
1586 tcg_gen_andi_tl(t[1], t[1], 63);
1587 cris_alu(dc, CC_OP_ASR, cpu_R[dc->op2], t[0], t[1], size);
1588 cris_alu_free_temps(dc, size, t);
1589 return 2;
8170028d
TS		 1590}
1591
cf7e0c80 1592static int dec_muls_r(CPUCRISState *env, DisasContext *dc)
8170028d 1593{
7b5eff4d
EV		 1594 TCGv t[2];
1595 int size = memsize_zz(dc);
8170028d 1596
7b5eff4d
EV		 1597 LOG_DIS("muls.%c $r%u, $r%u\n",
1598 memsize_char(size), dc->op1, dc->op2);
1599 cris_cc_mask(dc, CC_MASK_NZV);
1600 cris_alu_alloc_temps(dc, size, t);
1601 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 1, t[0], t[1]);
30abcfc7 1602
7b5eff4d
EV		 1603 cris_alu(dc, CC_OP_MULS, cpu_R[dc->op2], t[0], t[1], 4);
1604 cris_alu_free_temps(dc, size, t);
1605 return 2;
8170028d
TS		 1606}
1607
cf7e0c80 1608static int dec_mulu_r(CPUCRISState *env, DisasContext *dc)
8170028d 1609{
7b5eff4d
EV		 1610 TCGv t[2];
1611 int size = memsize_zz(dc);
8170028d 1612
7b5eff4d
EV		 1613 LOG_DIS("mulu.%c $r%u, $r%u\n",
1614 memsize_char(size), dc->op1, dc->op2);
1615 cris_cc_mask(dc, CC_MASK_NZV);
1616 cris_alu_alloc_temps(dc, size, t);
1617 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]);
30abcfc7 1618
7b5eff4d
EV		 1619 cris_alu(dc, CC_OP_MULU, cpu_R[dc->op2], t[0], t[1], 4);
1620 cris_alu_alloc_temps(dc, size, t);
1621 return 2;
8170028d
TS		 1622}
1623
1624
cf7e0c80 1625static int dec_dstep_r(CPUCRISState *env, DisasContext *dc)
8170028d 1626{
7b5eff4d
EV		 1627 LOG_DIS("dstep $r%u, $r%u\n", dc->op1, dc->op2);
1628 cris_cc_mask(dc, CC_MASK_NZ);
1629 cris_alu(dc, CC_OP_DSTEP,
1630 cpu_R[dc->op2], cpu_R[dc->op2], cpu_R[dc->op1], 4);
1631 return 2;
8170028d
TS		 1632}
1633
cf7e0c80 1634static int dec_xor_r(CPUCRISState *env, DisasContext *dc)
8170028d 1635{
7b5eff4d
EV		 1636 TCGv t[2];
1637 int size = memsize_zz(dc);
1638 LOG_DIS("xor.%c $r%u, $r%u\n",
1639 memsize_char(size), dc->op1, dc->op2);
1640 BUG_ON(size != 4); /* xor is dword. */
1641 cris_cc_mask(dc, CC_MASK_NZ);
1642 cris_alu_alloc_temps(dc, size, t);
1643 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]);
30abcfc7 1644
7b5eff4d
EV		 1645 cris_alu(dc, CC_OP_XOR, cpu_R[dc->op2], t[0], t[1], 4);
1646 cris_alu_free_temps(dc, size, t);
1647 return 2;
8170028d
TS		 1648}
1649
cf7e0c80 1650static int dec_bound_r(CPUCRISState *env, DisasContext *dc)
8170028d 1651{
7b5eff4d
EV		 1652 TCGv l0;
1653 int size = memsize_zz(dc);
1654 LOG_DIS("bound.%c $r%u, $r%u\n",
1655 memsize_char(size), dc->op1, dc->op2);
1656 cris_cc_mask(dc, CC_MASK_NZ);
1657 l0 = tcg_temp_local_new();
1658 dec_prep_move_r(dc, dc->op1, dc->op2, size, 0, l0);
1659 cris_alu(dc, CC_OP_BOUND, cpu_R[dc->op2], cpu_R[dc->op2], l0, 4);
1660 tcg_temp_free(l0);
1661 return 2;
8170028d
TS		 1662}
1663
cf7e0c80 1664static int dec_cmp_r(CPUCRISState *env, DisasContext *dc)
8170028d 1665{
7b5eff4d
EV		 1666 TCGv t[2];
1667 int size = memsize_zz(dc);
1668 LOG_DIS("cmp.%c $r%u, $r%u\n",
1669 memsize_char(size), dc->op1, dc->op2);
1670 cris_cc_mask(dc, CC_MASK_NZVC);
1671 cris_alu_alloc_temps(dc, size, t);
1672 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]);
30abcfc7 1673
7b5eff4d
EV		 1674 cris_alu(dc, CC_OP_CMP, cpu_R[dc->op2], t[0], t[1], size);
1675 cris_alu_free_temps(dc, size, t);
1676 return 2;
8170028d
TS		 1677}
1678
cf7e0c80 1679static int dec_abs_r(CPUCRISState *env, DisasContext *dc)
8170028d 1680{
7b5eff4d 1681 TCGv t0;
3157a0a9 1682
7b5eff4d
EV		 1683 LOG_DIS("abs $r%u, $r%u\n",
1684 dc->op1, dc->op2);
1685 cris_cc_mask(dc, CC_MASK_NZ);
3157a0a9 1686
7b5eff4d
EV		 1687 t0 = tcg_temp_new();
1688 tcg_gen_sari_tl(t0, cpu_R[dc->op1], 31);
1689 tcg_gen_xor_tl(cpu_R[dc->op2], cpu_R[dc->op1], t0);
1690 tcg_gen_sub_tl(cpu_R[dc->op2], cpu_R[dc->op2], t0);
1691 tcg_temp_free(t0);
7dcfb089 1692
7b5eff4d
EV		 1693 cris_alu(dc, CC_OP_MOVE,
1694 cpu_R[dc->op2], cpu_R[dc->op2], cpu_R[dc->op2], 4);
1695 return 2;
8170028d
TS		 1696}
1697
cf7e0c80 1698static int dec_add_r(CPUCRISState *env, DisasContext *dc)
8170028d 1699{
7b5eff4d
EV		 1700 TCGv t[2];
1701 int size = memsize_zz(dc);
1702 LOG_DIS("add.%c $r%u, $r%u\n",
1703 memsize_char(size), dc->op1, dc->op2);
1704 cris_cc_mask(dc, CC_MASK_NZVC);
1705 cris_alu_alloc_temps(dc, size, t);
1706 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]);
30abcfc7 1707
7b5eff4d
EV		 1708 cris_alu(dc, CC_OP_ADD, cpu_R[dc->op2], t[0], t[1], size);
1709 cris_alu_free_temps(dc, size, t);
1710 return 2;
8170028d
TS		 1711}
1712
cf7e0c80 1713static int dec_addc_r(CPUCRISState *env, DisasContext *dc)
8170028d 1714{
7b5eff4d
EV		 1715 LOG_DIS("addc $r%u, $r%u\n",
1716 dc->op1, dc->op2);
1717 cris_evaluate_flags(dc);
1718 /* Set for this insn. */
1719 dc->flagx_known = 1;
1720 dc->flags_x = X_FLAG;
a8cf66bb 1721
7b5eff4d
EV		 1722 cris_cc_mask(dc, CC_MASK_NZVC);
1723 cris_alu(dc, CC_OP_ADDC,
1724 cpu_R[dc->op2], cpu_R[dc->op2], cpu_R[dc->op1], 4);
1725 return 2;
8170028d
TS		 1726}
1727
cf7e0c80 1728static int dec_mcp_r(CPUCRISState *env, DisasContext *dc)
8170028d 1729{
7b5eff4d
EV		 1730 LOG_DIS("mcp $p%u, $r%u\n",
1731 dc->op2, dc->op1);
1732 cris_evaluate_flags(dc);
1733 cris_cc_mask(dc, CC_MASK_RNZV);
1734 cris_alu(dc, CC_OP_MCP,
1735 cpu_R[dc->op1], cpu_R[dc->op1], cpu_PR[dc->op2], 4);
1736 return 2;
8170028d
TS		 1737}
1738
1739#if DISAS_CRIS
1740static char * swapmode_name(int mode, char *modename) {
7b5eff4d
EV		 1741 int i = 0;
1742 if (mode & 8) {
1743 modename[i++] = 'n';
1744 }
1745 if (mode & 4) {
1746 modename[i++] = 'w';
1747 }
1748 if (mode & 2) {
1749 modename[i++] = 'b';
1750 }
1751 if (mode & 1) {
1752 modename[i++] = 'r';
1753 }
1754 modename[i++] = 0;
1755 return modename;
8170028d
TS		 1756}
1757#endif
1758
cf7e0c80 1759static int dec_swap_r(CPUCRISState *env, DisasContext *dc)
8170028d 1760{
7b5eff4d 1761 TCGv t0;
cf1d97f0 1762#if DISAS_CRIS
7b5eff4d 1763 char modename[4];
cf1d97f0 1764#endif
7b5eff4d
EV		 1765 LOG_DIS("swap%s $r%u\n",
1766 swapmode_name(dc->op2, modename), dc->op1);
1767
1768 cris_cc_mask(dc, CC_MASK_NZ);
1769 t0 = tcg_temp_new();
08397c4b 1770 tcg_gen_mov_tl(t0, cpu_R[dc->op1]);
7b5eff4d
EV		 1771 if (dc->op2 & 8) {
1772 tcg_gen_not_tl(t0, t0);
1773 }
1774 if (dc->op2 & 4) {
1775 t_gen_swapw(t0, t0);
1776 }
1777 if (dc->op2 & 2) {
1778 t_gen_swapb(t0, t0);
1779 }
1780 if (dc->op2 & 1) {
1781 t_gen_swapr(t0, t0);
1782 }
1783 cris_alu(dc, CC_OP_MOVE, cpu_R[dc->op1], cpu_R[dc->op1], t0, 4);
1784 tcg_temp_free(t0);
1785 return 2;
8170028d
TS		 1786}
1787
cf7e0c80 1788static int dec_or_r(CPUCRISState *env, DisasContext *dc)
8170028d 1789{
7b5eff4d
EV		 1790 TCGv t[2];
1791 int size = memsize_zz(dc);
1792 LOG_DIS("or.%c $r%u, $r%u\n",
1793 memsize_char(size), dc->op1, dc->op2);
1794 cris_cc_mask(dc, CC_MASK_NZ);
1795 cris_alu_alloc_temps(dc, size, t);
1796 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]);
1797 cris_alu(dc, CC_OP_OR, cpu_R[dc->op2], t[0], t[1], size);
1798 cris_alu_free_temps(dc, size, t);
1799 return 2;
8170028d
TS		 1800}
1801
cf7e0c80 1802static int dec_addi_r(CPUCRISState *env, DisasContext *dc)
8170028d 1803{
7b5eff4d
EV		 1804 TCGv t0;
1805 LOG_DIS("addi.%c $r%u, $r%u\n",
1806 memsize_char(memsize_zz(dc)), dc->op2, dc->op1);
1807 cris_cc_mask(dc, 0);
1808 t0 = tcg_temp_new();
1809 tcg_gen_shl_tl(t0, cpu_R[dc->op2], tcg_const_tl(dc->zzsize));
1810 tcg_gen_add_tl(cpu_R[dc->op1], cpu_R[dc->op1], t0);
1811 tcg_temp_free(t0);
1812 return 2;
8170028d
TS		 1813}
1814
cf7e0c80 1815static int dec_addi_acr(CPUCRISState *env, DisasContext *dc)
8170028d 1816{
7b5eff4d
EV		 1817 TCGv t0;
1818 LOG_DIS("addi.%c $r%u, $r%u, $acr\n",
1819 memsize_char(memsize_zz(dc)), dc->op2, dc->op1);
1820 cris_cc_mask(dc, 0);
1821 t0 = tcg_temp_new();
1822 tcg_gen_shl_tl(t0, cpu_R[dc->op2], tcg_const_tl(dc->zzsize));
1823 tcg_gen_add_tl(cpu_R[R_ACR], cpu_R[dc->op1], t0);
1824 tcg_temp_free(t0);
1825 return 2;
8170028d
TS		 1826}
1827
cf7e0c80 1828static int dec_neg_r(CPUCRISState *env, DisasContext *dc)
8170028d 1829{
7b5eff4d
EV		 1830 TCGv t[2];
1831 int size = memsize_zz(dc);
1832 LOG_DIS("neg.%c $r%u, $r%u\n",
1833 memsize_char(size), dc->op1, dc->op2);
1834 cris_cc_mask(dc, CC_MASK_NZVC);
1835 cris_alu_alloc_temps(dc, size, t);
1836 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]);
30abcfc7 1837
7b5eff4d
EV		 1838 cris_alu(dc, CC_OP_NEG, cpu_R[dc->op2], t[0], t[1], size);
1839 cris_alu_free_temps(dc, size, t);
1840 return 2;
8170028d
TS		 1841}
1842
cf7e0c80 1843static int dec_btst_r(CPUCRISState *env, DisasContext *dc)
8170028d 1844{
7b5eff4d
EV		 1845 LOG_DIS("btst $r%u, $r%u\n",
1846 dc->op1, dc->op2);
1847 cris_cc_mask(dc, CC_MASK_NZ);
1848 cris_evaluate_flags(dc);
febc9920 1849 gen_helper_btst(cpu_PR[PR_CCS], cpu_env, cpu_R[dc->op2],
7b5eff4d
EV		 1850 cpu_R[dc->op1], cpu_PR[PR_CCS]);
1851 cris_alu(dc, CC_OP_MOVE, cpu_R[dc->op2],
1852 cpu_R[dc->op2], cpu_R[dc->op2], 4);
1853 cris_update_cc_op(dc, CC_OP_FLAGS, 4);
1854 dc->flags_uptodate = 1;
1855 return 2;
8170028d
TS		 1856}
1857
cf7e0c80 1858static int dec_sub_r(CPUCRISState *env, DisasContext *dc)
8170028d 1859{
7b5eff4d
EV		 1860 TCGv t[2];
1861 int size = memsize_zz(dc);
1862 LOG_DIS("sub.%c $r%u, $r%u\n",
1863 memsize_char(size), dc->op1, dc->op2);
1864 cris_cc_mask(dc, CC_MASK_NZVC);
1865 cris_alu_alloc_temps(dc, size, t);
1866 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]);
1867 cris_alu(dc, CC_OP_SUB, cpu_R[dc->op2], t[0], t[1], size);
1868 cris_alu_free_temps(dc, size, t);
1869 return 2;
8170028d
TS		 1870}
1871
1872/* Zero extension. From size to dword. */
cf7e0c80 1873static int dec_movu_r(CPUCRISState *env, DisasContext *dc)
8170028d 1874{
7b5eff4d
EV		 1875 TCGv t0;
1876 int size = memsize_z(dc);
1877 LOG_DIS("movu.%c $r%u, $r%u\n",
1878 memsize_char(size),
1879 dc->op1, dc->op2);
8170028d 1880
7b5eff4d
EV		 1881 cris_cc_mask(dc, CC_MASK_NZ);
1882 t0 = tcg_temp_new();
1883 dec_prep_move_r(dc, dc->op1, dc->op2, size, 0, t0);
1884 cris_alu(dc, CC_OP_MOVE, cpu_R[dc->op2], cpu_R[dc->op2], t0, 4);
1885 tcg_temp_free(t0);
1886 return 2;
8170028d
TS		 1887}
1888
1889/* Sign extension. From size to dword. */
cf7e0c80 1890static int dec_movs_r(CPUCRISState *env, DisasContext *dc)
8170028d 1891{
7b5eff4d
EV		 1892 TCGv t0;
1893 int size = memsize_z(dc);
1894 LOG_DIS("movs.%c $r%u, $r%u\n",
1895 memsize_char(size),
1896 dc->op1, dc->op2);
8170028d 1897
7b5eff4d
EV		 1898 cris_cc_mask(dc, CC_MASK_NZ);
1899 t0 = tcg_temp_new();
1900 /* Size can only be qi or hi. */
1901 t_gen_sext(t0, cpu_R[dc->op1], size);
1902 cris_alu(dc, CC_OP_MOVE,
1903 cpu_R[dc->op2], cpu_R[dc->op1], t0, 4);
1904 tcg_temp_free(t0);
1905 return 2;
8170028d
TS		 1906}
1907
1908/* zero extension. From size to dword. */
cf7e0c80 1909static int dec_addu_r(CPUCRISState *env, DisasContext *dc)
8170028d 1910{
7b5eff4d
EV		 1911 TCGv t0;
1912 int size = memsize_z(dc);
1913 LOG_DIS("addu.%c $r%u, $r%u\n",
1914 memsize_char(size),
1915 dc->op1, dc->op2);
8170028d 1916
7b5eff4d
EV		 1917 cris_cc_mask(dc, CC_MASK_NZVC);
1918 t0 = tcg_temp_new();
1919 /* Size can only be qi or hi. */
1920 t_gen_zext(t0, cpu_R[dc->op1], size);
1921 cris_alu(dc, CC_OP_ADD, cpu_R[dc->op2], cpu_R[dc->op2], t0, 4);
1922 tcg_temp_free(t0);
1923 return 2;
8170028d 1924}
05ba7d5f 1925
8170028d 1926/* Sign extension. From size to dword. */
cf7e0c80 1927static int dec_adds_r(CPUCRISState *env, DisasContext *dc)
8170028d 1928{
7b5eff4d
EV		 1929 TCGv t0;
1930 int size = memsize_z(dc);
1931 LOG_DIS("adds.%c $r%u, $r%u\n",
1932 memsize_char(size),
1933 dc->op1, dc->op2);
8170028d 1934
7b5eff4d
EV		 1935 cris_cc_mask(dc, CC_MASK_NZVC);
1936 t0 = tcg_temp_new();
1937 /* Size can only be qi or hi. */
1938 t_gen_sext(t0, cpu_R[dc->op1], size);
1939 cris_alu(dc, CC_OP_ADD,
1940 cpu_R[dc->op2], cpu_R[dc->op2], t0, 4);
1941 tcg_temp_free(t0);
1942 return 2;
8170028d
TS		 1943}
1944
1945/* Zero extension. From size to dword. */
cf7e0c80 1946static int dec_subu_r(CPUCRISState *env, DisasContext *dc)
8170028d 1947{
7b5eff4d
EV		 1948 TCGv t0;
1949 int size = memsize_z(dc);
1950 LOG_DIS("subu.%c $r%u, $r%u\n",
1951 memsize_char(size),
1952 dc->op1, dc->op2);
8170028d 1953
7b5eff4d
EV		 1954 cris_cc_mask(dc, CC_MASK_NZVC);
1955 t0 = tcg_temp_new();
1956 /* Size can only be qi or hi. */
1957 t_gen_zext(t0, cpu_R[dc->op1], size);
1958 cris_alu(dc, CC_OP_SUB,
1959 cpu_R[dc->op2], cpu_R[dc->op2], t0, 4);
1960 tcg_temp_free(t0);
1961 return 2;
8170028d
TS		 1962}
1963
1964/* Sign extension. From size to dword. */
cf7e0c80 1965static int dec_subs_r(CPUCRISState *env, DisasContext *dc)
8170028d 1966{
7b5eff4d
EV		 1967 TCGv t0;
1968 int size = memsize_z(dc);
1969 LOG_DIS("subs.%c $r%u, $r%u\n",
1970 memsize_char(size),
1971 dc->op1, dc->op2);
8170028d 1972
7b5eff4d
EV		 1973 cris_cc_mask(dc, CC_MASK_NZVC);
1974 t0 = tcg_temp_new();
1975 /* Size can only be qi or hi. */
1976 t_gen_sext(t0, cpu_R[dc->op1], size);
1977 cris_alu(dc, CC_OP_SUB,
1978 cpu_R[dc->op2], cpu_R[dc->op2], t0, 4);
1979 tcg_temp_free(t0);
1980 return 2;
8170028d
TS		 1981}
1982
cf7e0c80 1983static int dec_setclrf(CPUCRISState *env, DisasContext *dc)
8170028d 1984{
7b5eff4d
EV		 1985 uint32_t flags;
1986 int set = (~dc->opcode >> 2) & 1;
1987
1988
1989 flags = (EXTRACT_FIELD(dc->ir, 12, 15) << 4)
1990 | EXTRACT_FIELD(dc->ir, 0, 3);
1991 if (set && flags == 0) {
1992 LOG_DIS("nop\n");
1993 return 2;
1994 } else if (!set && (flags & 0x20)) {
1995 LOG_DIS("di\n");
1996 } else {
1997 LOG_DIS("%sf %x\n", set ? "set" : "clr", flags);
1998 }
1999
2000 /* User space is not allowed to touch these. Silently ignore. */
2001 if (dc->tb_flags & U_FLAG) {
2002 flags &= ~(S_FLAG | I_FLAG | U_FLAG);
2003 }
2004
2005 if (flags & X_FLAG) {
2006 dc->flagx_known = 1;
2007 if (set) {
2008 dc->flags_x = X_FLAG;
2009 } else {
2010 dc->flags_x = 0;
2011 }
2012 }
2013
2014 /* Break the TB if any of the SPI flag changes. */
2015 if (flags & (P_FLAG | S_FLAG)) {
2016 tcg_gen_movi_tl(env_pc, dc->pc + 2);
2017 dc->is_jmp = DISAS_UPDATE;
2018 dc->cpustate_changed = 1;
2019 }
2020
2021 /* For the I flag, only act on posedge. */
2022 if ((flags & I_FLAG)) {
2023 tcg_gen_movi_tl(env_pc, dc->pc + 2);
2024 dc->is_jmp = DISAS_UPDATE;
2025 dc->cpustate_changed = 1;
2026 }
2027
2028
2029 /* Simply decode the flags. */
2030 cris_evaluate_flags(dc);
2031 cris_update_cc_op(dc, CC_OP_FLAGS, 4);
2032 cris_update_cc_x(dc);
2033 tcg_gen_movi_tl(cc_op, dc->cc_op);
2034
2035 if (set) {
2036 if (!(dc->tb_flags & U_FLAG) && (flags & U_FLAG)) {
2037 /* Enter user mode. */
2038 t_gen_mov_env_TN(ksp, cpu_R[R_SP]);
2039 tcg_gen_mov_tl(cpu_R[R_SP], cpu_PR[PR_USP]);
2040 dc->cpustate_changed = 1;
2041 }
2042 tcg_gen_ori_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], flags);
2043 } else {
2044 tcg_gen_andi_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], ~flags);
2045 }
2046
2047 dc->flags_uptodate = 1;
2048 dc->clear_x = 0;
2049 return 2;
8170028d
TS		 2050}
2051
cf7e0c80 2052static int dec_move_rs(CPUCRISState *env, DisasContext *dc)
8170028d 2053{
7b5eff4d
EV		 2054 LOG_DIS("move $r%u, $s%u\n", dc->op1, dc->op2);
2055 cris_cc_mask(dc, 0);
febc9920
AJ		 2056 gen_helper_movl_sreg_reg(cpu_env, tcg_const_tl(dc->op2),
2057 tcg_const_tl(dc->op1));
7b5eff4d 2058 return 2;
8170028d 2059}
cf7e0c80 2060static int dec_move_sr(CPUCRISState *env, DisasContext *dc)
8170028d 2061{
7b5eff4d
EV		 2062 LOG_DIS("move $s%u, $r%u\n", dc->op2, dc->op1);
2063 cris_cc_mask(dc, 0);
febc9920
AJ		 2064 gen_helper_movl_reg_sreg(cpu_env, tcg_const_tl(dc->op1),
2065 tcg_const_tl(dc->op2));
7b5eff4d 2066 return 2;
8170028d 2067}
dceaf394 2068
cf7e0c80 2069static int dec_move_rp(CPUCRISState *env, DisasContext *dc)
8170028d 2070{
7b5eff4d
EV		 2071 TCGv t[2];
2072 LOG_DIS("move $r%u, $p%u\n", dc->op1, dc->op2);
2073 cris_cc_mask(dc, 0);
2074
2075 t[0] = tcg_temp_new();
2076 if (dc->op2 == PR_CCS) {
2077 cris_evaluate_flags(dc);
08397c4b 2078 tcg_gen_mov_tl(t[0], cpu_R[dc->op1]);
7b5eff4d
EV		 2079 if (dc->tb_flags & U_FLAG) {
2080 t[1] = tcg_temp_new();
2081 /* User space is not allowed to touch all flags. */
2082 tcg_gen_andi_tl(t[0], t[0], 0x39f);
2083 tcg_gen_andi_tl(t[1], cpu_PR[PR_CCS], ~0x39f);
2084 tcg_gen_or_tl(t[0], t[1], t[0]);
2085 tcg_temp_free(t[1]);
2086 }
2087 } else {
08397c4b 2088 tcg_gen_mov_tl(t[0], cpu_R[dc->op1]);
7b5eff4d
EV		 2089 }
2090
2091 t_gen_mov_preg_TN(dc, dc->op2, t[0]);
2092 if (dc->op2 == PR_CCS) {
2093 cris_update_cc_op(dc, CC_OP_FLAGS, 4);
2094 dc->flags_uptodate = 1;
2095 }
2096 tcg_temp_free(t[0]);
2097 return 2;
8170028d 2098}
cf7e0c80 2099static int dec_move_pr(CPUCRISState *env, DisasContext *dc)
8170028d 2100{
7b5eff4d
EV		 2101 TCGv t0;
2102 LOG_DIS("move $p%u, $r%u\n", dc->op2, dc->op1);
2103 cris_cc_mask(dc, 0);
2a44f7f1 2104
7b5eff4d
EV		 2105 if (dc->op2 == PR_CCS) {
2106 cris_evaluate_flags(dc);
2107 }
2a44f7f1 2108
7b5eff4d
EV		 2109 if (dc->op2 == PR_DZ) {
2110 tcg_gen_movi_tl(cpu_R[dc->op1], 0);
2111 } else {
2112 t0 = tcg_temp_new();
2113 t_gen_mov_TN_preg(t0, dc->op2);
2114 cris_alu(dc, CC_OP_MOVE,
2115 cpu_R[dc->op1], cpu_R[dc->op1], t0,
2116 preg_sizes[dc->op2]);
2117 tcg_temp_free(t0);
2118 }
2119 return 2;
8170028d
TS		 2120}
2121
cf7e0c80 2122static int dec_move_mr(CPUCRISState *env, DisasContext *dc)
8170028d 2123{
7b5eff4d
EV		 2124 int memsize = memsize_zz(dc);
2125 int insn_len;
2126 LOG_DIS("move.%c [$r%u%s, $r%u\n",
2127 memsize_char(memsize),
2128 dc->op1, dc->postinc ? "+]" : "]",
2129 dc->op2);
2130
2131 if (memsize == 4) {
2132 insn_len = dec_prep_move_m(env, dc, 0, 4, cpu_R[dc->op2]);
2133 cris_cc_mask(dc, CC_MASK_NZ);
2134 cris_update_cc_op(dc, CC_OP_MOVE, 4);
2135 cris_update_cc_x(dc);
2136 cris_update_result(dc, cpu_R[dc->op2]);
2137 } else {
2138 TCGv t0;
2139
2140 t0 = tcg_temp_new();
2141 insn_len = dec_prep_move_m(env, dc, 0, memsize, t0);
2142 cris_cc_mask(dc, CC_MASK_NZ);
2143 cris_alu(dc, CC_OP_MOVE,
2144 cpu_R[dc->op2], cpu_R[dc->op2], t0, memsize);
2145 tcg_temp_free(t0);
2146 }
2147 do_postinc(dc, memsize);
2148 return insn_len;
8170028d
TS		 2149}
2150
31c18d87
EI		 2151static inline void cris_alu_m_alloc_temps(TCGv *t)
2152{
7b5eff4d
EV		 2153 t[0] = tcg_temp_new();
2154 t[1] = tcg_temp_new();
31c18d87
EI		 2155}
2156
2157static inline void cris_alu_m_free_temps(TCGv *t)
2158{
7b5eff4d
EV		 2159 tcg_temp_free(t[0]);
2160 tcg_temp_free(t[1]);
31c18d87
EI		 2161}
2162
cf7e0c80 2163static int dec_movs_m(CPUCRISState *env, DisasContext *dc)
8170028d 2164{
7b5eff4d
EV		 2165 TCGv t[2];
2166 int memsize = memsize_z(dc);
2167 int insn_len;
2168 LOG_DIS("movs.%c [$r%u%s, $r%u\n",
2169 memsize_char(memsize),
2170 dc->op1, dc->postinc ? "+]" : "]",
2171 dc->op2);
8170028d 2172
7b5eff4d
EV		 2173 cris_alu_m_alloc_temps(t);
2174 /* sign extend. */
cf7e0c80 2175 insn_len = dec_prep_alu_m(env, dc, 1, memsize, t[0], t[1]);
7b5eff4d
EV		 2176 cris_cc_mask(dc, CC_MASK_NZ);
2177 cris_alu(dc, CC_OP_MOVE,
2178 cpu_R[dc->op2], cpu_R[dc->op2], t[1], 4);
2179 do_postinc(dc, memsize);
2180 cris_alu_m_free_temps(t);
2181 return insn_len;
8170028d
TS		 2182}
2183
cf7e0c80 2184static int dec_addu_m(CPUCRISState *env, DisasContext *dc)
8170028d 2185{
7b5eff4d
EV		 2186 TCGv t[2];
2187 int memsize = memsize_z(dc);
2188 int insn_len;
2189 LOG_DIS("addu.%c [$r%u%s, $r%u\n",
2190 memsize_char(memsize),
2191 dc->op1, dc->postinc ? "+]" : "]",
2192 dc->op2);
8170028d 2193
7b5eff4d
EV		 2194 cris_alu_m_alloc_temps(t);
2195 /* sign extend. */
cf7e0c80 2196 insn_len = dec_prep_alu_m(env, dc, 0, memsize, t[0], t[1]);
7b5eff4d
EV		 2197 cris_cc_mask(dc, CC_MASK_NZVC);
2198 cris_alu(dc, CC_OP_ADD,
2199 cpu_R[dc->op2], cpu_R[dc->op2], t[1], 4);
2200 do_postinc(dc, memsize);
2201 cris_alu_m_free_temps(t);
2202 return insn_len;
8170028d
TS		 2203}
2204
cf7e0c80 2205static int dec_adds_m(CPUCRISState *env, DisasContext *dc)
8170028d 2206{
7b5eff4d
EV		 2207 TCGv t[2];
2208 int memsize = memsize_z(dc);
2209 int insn_len;
2210 LOG_DIS("adds.%c [$r%u%s, $r%u\n",
2211 memsize_char(memsize),
2212 dc->op1, dc->postinc ? "+]" : "]",
2213 dc->op2);
8170028d 2214
7b5eff4d
EV		 2215 cris_alu_m_alloc_temps(t);
2216 /* sign extend. */
cf7e0c80 2217 insn_len = dec_prep_alu_m(env, dc, 1, memsize, t[0], t[1]);
7b5eff4d
EV		 2218 cris_cc_mask(dc, CC_MASK_NZVC);
2219 cris_alu(dc, CC_OP_ADD, cpu_R[dc->op2], cpu_R[dc->op2], t[1], 4);
2220 do_postinc(dc, memsize);
2221 cris_alu_m_free_temps(t);
2222 return insn_len;
8170028d
TS		 2223}
2224
cf7e0c80 2225static int dec_subu_m(CPUCRISState *env, DisasContext *dc)
8170028d 2226{
7b5eff4d
EV		 2227 TCGv t[2];
2228 int memsize = memsize_z(dc);
2229 int insn_len;
2230 LOG_DIS("subu.%c [$r%u%s, $r%u\n",
2231 memsize_char(memsize),
2232 dc->op1, dc->postinc ? "+]" : "]",
2233 dc->op2);
8170028d 2234
7b5eff4d
EV		 2235 cris_alu_m_alloc_temps(t);
2236 /* sign extend. */
cf7e0c80 2237 insn_len = dec_prep_alu_m(env, dc, 0, memsize, t[0], t[1]);
7b5eff4d
EV		 2238 cris_cc_mask(dc, CC_MASK_NZVC);
2239 cris_alu(dc, CC_OP_SUB, cpu_R[dc->op2], cpu_R[dc->op2], t[1], 4);
2240 do_postinc(dc, memsize);
2241 cris_alu_m_free_temps(t);
2242 return insn_len;
8170028d
TS		 2243}
2244
cf7e0c80 2245static int dec_subs_m(CPUCRISState *env, DisasContext *dc)
8170028d 2246{
7b5eff4d
EV		 2247 TCGv t[2];
2248 int memsize = memsize_z(dc);
2249 int insn_len;
2250 LOG_DIS("subs.%c [$r%u%s, $r%u\n",
2251 memsize_char(memsize),
2252 dc->op1, dc->postinc ? "+]" : "]",
2253 dc->op2);
8170028d 2254
7b5eff4d
EV		 2255 cris_alu_m_alloc_temps(t);
2256 /* sign extend. */
cf7e0c80 2257 insn_len = dec_prep_alu_m(env, dc, 1, memsize, t[0], t[1]);
7b5eff4d
EV		 2258 cris_cc_mask(dc, CC_MASK_NZVC);
2259 cris_alu(dc, CC_OP_SUB, cpu_R[dc->op2], cpu_R[dc->op2], t[1], 4);
2260 do_postinc(dc, memsize);
2261 cris_alu_m_free_temps(t);
2262 return insn_len;
8170028d
TS		 2263}
2264
cf7e0c80 2265static int dec_movu_m(CPUCRISState *env, DisasContext *dc)
8170028d 2266{
7b5eff4d
EV		 2267 TCGv t[2];
2268 int memsize = memsize_z(dc);
2269 int insn_len;
8170028d 2270
7b5eff4d
EV		 2271 LOG_DIS("movu.%c [$r%u%s, $r%u\n",
2272 memsize_char(memsize),
2273 dc->op1, dc->postinc ? "+]" : "]",
2274 dc->op2);
8170028d 2275
7b5eff4d 2276 cris_alu_m_alloc_temps(t);
cf7e0c80 2277 insn_len = dec_prep_alu_m(env, dc, 0, memsize, t[0], t[1]);
7b5eff4d
EV		 2278 cris_cc_mask(dc, CC_MASK_NZ);
2279 cris_alu(dc, CC_OP_MOVE, cpu_R[dc->op2], cpu_R[dc->op2], t[1], 4);
2280 do_postinc(dc, memsize);
2281 cris_alu_m_free_temps(t);
2282 return insn_len;
8170028d
TS		 2283}
2284
cf7e0c80 2285static int dec_cmpu_m(CPUCRISState *env, DisasContext *dc)
8170028d 2286{
7b5eff4d
EV		 2287 TCGv t[2];
2288 int memsize = memsize_z(dc);
2289 int insn_len;
2290 LOG_DIS("cmpu.%c [$r%u%s, $r%u\n",
2291 memsize_char(memsize),
2292 dc->op1, dc->postinc ? "+]" : "]",
2293 dc->op2);
8170028d 2294
7b5eff4d 2295 cris_alu_m_alloc_temps(t);
cf7e0c80 2296 insn_len = dec_prep_alu_m(env, dc, 0, memsize, t[0], t[1]);
7b5eff4d
EV		 2297 cris_cc_mask(dc, CC_MASK_NZVC);
2298 cris_alu(dc, CC_OP_CMP, cpu_R[dc->op2], cpu_R[dc->op2], t[1], 4);
2299 do_postinc(dc, memsize);
2300 cris_alu_m_free_temps(t);
2301 return insn_len;
8170028d
TS		 2302}
2303
cf7e0c80 2304static int dec_cmps_m(CPUCRISState *env, DisasContext *dc)
8170028d 2305{
7b5eff4d
EV		 2306 TCGv t[2];
2307 int memsize = memsize_z(dc);
2308 int insn_len;
2309 LOG_DIS("cmps.%c [$r%u%s, $r%u\n",
2310 memsize_char(memsize),
2311 dc->op1, dc->postinc ? "+]" : "]",
2312 dc->op2);
8170028d 2313
7b5eff4d 2314 cris_alu_m_alloc_temps(t);
cf7e0c80 2315 insn_len = dec_prep_alu_m(env, dc, 1, memsize, t[0], t[1]);
7b5eff4d
EV		 2316 cris_cc_mask(dc, CC_MASK_NZVC);
2317 cris_alu(dc, CC_OP_CMP,
2318 cpu_R[dc->op2], cpu_R[dc->op2], t[1],
2319 memsize_zz(dc));
2320 do_postinc(dc, memsize);
2321 cris_alu_m_free_temps(t);
2322 return insn_len;
8170028d
TS		 2323}
2324
cf7e0c80 2325static int dec_cmp_m(CPUCRISState *env, DisasContext *dc)
8170028d 2326{
7b5eff4d
EV		 2327 TCGv t[2];
2328 int memsize = memsize_zz(dc);
2329 int insn_len;
2330 LOG_DIS("cmp.%c [$r%u%s, $r%u\n",
2331 memsize_char(memsize),
2332 dc->op1, dc->postinc ? "+]" : "]",
2333 dc->op2);
8170028d 2334
7b5eff4d 2335 cris_alu_m_alloc_temps(t);
cf7e0c80 2336 insn_len = dec_prep_alu_m(env, dc, 0, memsize, t[0], t[1]);
7b5eff4d
EV		 2337 cris_cc_mask(dc, CC_MASK_NZVC);
2338 cris_alu(dc, CC_OP_CMP,
2339 cpu_R[dc->op2], cpu_R[dc->op2], t[1],
2340 memsize_zz(dc));
2341 do_postinc(dc, memsize);
2342 cris_alu_m_free_temps(t);
2343 return insn_len;
8170028d
TS		 2344}
2345
cf7e0c80 2346static int dec_test_m(CPUCRISState *env, DisasContext *dc)
8170028d 2347{
7b5eff4d
EV		 2348 TCGv t[2];
2349 int memsize = memsize_zz(dc);
2350 int insn_len;
2351 LOG_DIS("test.%c [$r%u%s] op2=%x\n",
2352 memsize_char(memsize),
2353 dc->op1, dc->postinc ? "+]" : "]",
2354 dc->op2);
8170028d 2355
7b5eff4d 2356 cris_evaluate_flags(dc);
dceaf394 2357
7b5eff4d 2358 cris_alu_m_alloc_temps(t);
cf7e0c80 2359 insn_len = dec_prep_alu_m(env, dc, 0, memsize, t[0], t[1]);
7b5eff4d
EV		 2360 cris_cc_mask(dc, CC_MASK_NZ);
2361 tcg_gen_andi_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], ~3);
b41f7df0 2362
7b5eff4d
EV		 2363 cris_alu(dc, CC_OP_CMP,
2364 cpu_R[dc->op2], t[1], tcg_const_tl(0), memsize_zz(dc));
2365 do_postinc(dc, memsize);
2366 cris_alu_m_free_temps(t);
2367 return insn_len;
8170028d
TS		 2368}
2369
cf7e0c80 2370static int dec_and_m(CPUCRISState *env, DisasContext *dc)
8170028d 2371{
7b5eff4d
EV		 2372 TCGv t[2];
2373 int memsize = memsize_zz(dc);
2374 int insn_len;
2375 LOG_DIS("and.%c [$r%u%s, $r%u\n",
2376 memsize_char(memsize),
2377 dc->op1, dc->postinc ? "+]" : "]",
2378 dc->op2);
8170028d 2379
7b5eff4d 2380 cris_alu_m_alloc_temps(t);
cf7e0c80 2381 insn_len = dec_prep_alu_m(env, dc, 0, memsize, t[0], t[1]);
7b5eff4d
EV		 2382 cris_cc_mask(dc, CC_MASK_NZ);
2383 cris_alu(dc, CC_OP_AND, cpu_R[dc->op2], t[0], t[1], memsize_zz(dc));
2384 do_postinc(dc, memsize);
2385 cris_alu_m_free_temps(t);
2386 return insn_len;
8170028d
TS		 2387}
2388
cf7e0c80 2389static int dec_add_m(CPUCRISState *env, DisasContext *dc)
8170028d 2390{
7b5eff4d
EV		 2391 TCGv t[2];
2392 int memsize = memsize_zz(dc);
2393 int insn_len;
2394 LOG_DIS("add.%c [$r%u%s, $r%u\n",
2395 memsize_char(memsize),
2396 dc->op1, dc->postinc ? "+]" : "]",
2397 dc->op2);
8170028d 2398
7b5eff4d 2399 cris_alu_m_alloc_temps(t);
cf7e0c80 2400 insn_len = dec_prep_alu_m(env, dc, 0, memsize, t[0], t[1]);
7b5eff4d
EV		 2401 cris_cc_mask(dc, CC_MASK_NZVC);
2402 cris_alu(dc, CC_OP_ADD,
2403 cpu_R[dc->op2], t[0], t[1], memsize_zz(dc));
2404 do_postinc(dc, memsize);
2405 cris_alu_m_free_temps(t);
2406 return insn_len;
8170028d
TS		 2407}
2408
cf7e0c80 2409static int dec_addo_m(CPUCRISState *env, DisasContext *dc)
8170028d 2410{
7b5eff4d
EV		 2411 TCGv t[2];
2412 int memsize = memsize_zz(dc);
2413 int insn_len;
2414 LOG_DIS("add.%c [$r%u%s, $r%u\n",
2415 memsize_char(memsize),
2416 dc->op1, dc->postinc ? "+]" : "]",
2417 dc->op2);
8170028d 2418
7b5eff4d 2419 cris_alu_m_alloc_temps(t);
cf7e0c80 2420 insn_len = dec_prep_alu_m(env, dc, 1, memsize, t[0], t[1]);
7b5eff4d
EV		 2421 cris_cc_mask(dc, 0);
2422 cris_alu(dc, CC_OP_ADD, cpu_R[R_ACR], t[0], t[1], 4);
2423 do_postinc(dc, memsize);
2424 cris_alu_m_free_temps(t);
2425 return insn_len;
8170028d
TS		 2426}
2427
cf7e0c80 2428static int dec_bound_m(CPUCRISState *env, DisasContext *dc)
8170028d 2429{
7b5eff4d
EV		 2430 TCGv l[2];
2431 int memsize = memsize_zz(dc);
2432 int insn_len;
2433 LOG_DIS("bound.%c [$r%u%s, $r%u\n",
2434 memsize_char(memsize),
2435 dc->op1, dc->postinc ? "+]" : "]",
2436 dc->op2);
8170028d 2437
7b5eff4d
EV		 2438 l[0] = tcg_temp_local_new();
2439 l[1] = tcg_temp_local_new();
cf7e0c80 2440 insn_len = dec_prep_alu_m(env, dc, 0, memsize, l[0], l[1]);
7b5eff4d
EV		 2441 cris_cc_mask(dc, CC_MASK_NZ);
2442 cris_alu(dc, CC_OP_BOUND, cpu_R[dc->op2], l[0], l[1], 4);
2443 do_postinc(dc, memsize);
2444 tcg_temp_free(l[0]);
2445 tcg_temp_free(l[1]);
2446 return insn_len;
8170028d
TS		 2447}
2448
cf7e0c80 2449static int dec_addc_mr(CPUCRISState *env, DisasContext *dc)
8170028d 2450{
7b5eff4d
EV		 2451 TCGv t[2];
2452 int insn_len = 2;
2453 LOG_DIS("addc [$r%u%s, $r%u\n",
2454 dc->op1, dc->postinc ? "+]" : "]",
2455 dc->op2);
8170028d 2456
7b5eff4d 2457 cris_evaluate_flags(dc);
a8cf66bb 2458
7b5eff4d
EV		 2459 /* Set for this insn. */
2460 dc->flagx_known = 1;
2461 dc->flags_x = X_FLAG;
a8cf66bb 2462
7b5eff4d 2463 cris_alu_m_alloc_temps(t);
cf7e0c80 2464 insn_len = dec_prep_alu_m(env, dc, 0, 4, t[0], t[1]);
7b5eff4d
EV		 2465 cris_cc_mask(dc, CC_MASK_NZVC);
2466 cris_alu(dc, CC_OP_ADDC, cpu_R[dc->op2], t[0], t[1], 4);
2467 do_postinc(dc, 4);
2468 cris_alu_m_free_temps(t);
2469 return insn_len;
8170028d
TS		 2470}
2471
cf7e0c80 2472static int dec_sub_m(CPUCRISState *env, DisasContext *dc)
8170028d 2473{
7b5eff4d
EV		 2474 TCGv t[2];
2475 int memsize = memsize_zz(dc);
2476 int insn_len;
2477 LOG_DIS("sub.%c [$r%u%s, $r%u ir=%x zz=%x\n",
2478 memsize_char(memsize),
2479 dc->op1, dc->postinc ? "+]" : "]",
2480 dc->op2, dc->ir, dc->zzsize);
8170028d 2481
7b5eff4d 2482 cris_alu_m_alloc_temps(t);
cf7e0c80 2483 insn_len = dec_prep_alu_m(env, dc, 0, memsize, t[0], t[1]);
7b5eff4d
EV		 2484 cris_cc_mask(dc, CC_MASK_NZVC);
2485 cris_alu(dc, CC_OP_SUB, cpu_R[dc->op2], t[0], t[1], memsize);
2486 do_postinc(dc, memsize);
2487 cris_alu_m_free_temps(t);
2488 return insn_len;
8170028d
TS		 2489}
2490
cf7e0c80 2491static int dec_or_m(CPUCRISState *env, DisasContext *dc)
8170028d 2492{
7b5eff4d
EV		 2493 TCGv t[2];
2494 int memsize = memsize_zz(dc);
2495 int insn_len;
2496 LOG_DIS("or.%c [$r%u%s, $r%u pc=%x\n",
2497 memsize_char(memsize),
2498 dc->op1, dc->postinc ? "+]" : "]",
2499 dc->op2, dc->pc);
8170028d 2500
7b5eff4d 2501 cris_alu_m_alloc_temps(t);
cf7e0c80 2502 insn_len = dec_prep_alu_m(env, dc, 0, memsize, t[0], t[1]);
7b5eff4d
EV		 2503 cris_cc_mask(dc, CC_MASK_NZ);
2504 cris_alu(dc, CC_OP_OR,
2505 cpu_R[dc->op2], t[0], t[1], memsize_zz(dc));
2506 do_postinc(dc, memsize);
2507 cris_alu_m_free_temps(t);
2508 return insn_len;
8170028d
TS		 2509}
2510
cf7e0c80 2511static int dec_move_mp(CPUCRISState *env, DisasContext *dc)
8170028d 2512{
7b5eff4d
EV		 2513 TCGv t[2];
2514 int memsize = memsize_zz(dc);
2515 int insn_len = 2;
8170028d 2516
7b5eff4d
EV		 2517 LOG_DIS("move.%c [$r%u%s, $p%u\n",
2518 memsize_char(memsize),
2519 dc->op1,
2520 dc->postinc ? "+]" : "]",
2521 dc->op2);
8170028d 2522
7b5eff4d 2523 cris_alu_m_alloc_temps(t);
cf7e0c80 2524 insn_len = dec_prep_alu_m(env, dc, 0, memsize, t[0], t[1]);
7b5eff4d
EV		 2525 cris_cc_mask(dc, 0);
2526 if (dc->op2 == PR_CCS) {
2527 cris_evaluate_flags(dc);
2528 if (dc->tb_flags & U_FLAG) {
2529 /* User space is not allowed to touch all flags. */
2530 tcg_gen_andi_tl(t[1], t[1], 0x39f);
2531 tcg_gen_andi_tl(t[0], cpu_PR[PR_CCS], ~0x39f);
2532 tcg_gen_or_tl(t[1], t[0], t[1]);
2533 }
2534 }
b41f7df0 2535
7b5eff4d 2536 t_gen_mov_preg_TN(dc, dc->op2, t[1]);
8170028d 2537
7b5eff4d
EV		 2538 do_postinc(dc, memsize);
2539 cris_alu_m_free_temps(t);
2540 return insn_len;
8170028d
TS		 2541}
2542
cf7e0c80 2543static int dec_move_pm(CPUCRISState *env, DisasContext *dc)
8170028d 2544{
7b5eff4d
EV		 2545 TCGv t0;
2546 int memsize;
8170028d 2547
7b5eff4d 2548 memsize = preg_sizes[dc->op2];
8170028d 2549
7b5eff4d
EV		 2550 LOG_DIS("move.%c $p%u, [$r%u%s\n",
2551 memsize_char(memsize),
2552 dc->op2, dc->op1, dc->postinc ? "+]" : "]");
8170028d 2553
7b5eff4d
EV		 2554 /* prepare store. Address in T0, value in T1. */
2555 if (dc->op2 == PR_CCS) {
2556 cris_evaluate_flags(dc);
2557 }
2558 t0 = tcg_temp_new();
2559 t_gen_mov_TN_preg(t0, dc->op2);
2560 cris_flush_cc_state(dc);
2561 gen_store(dc, cpu_R[dc->op1], t0, memsize);
2562 tcg_temp_free(t0);
2563
2564 cris_cc_mask(dc, 0);
2565 if (dc->postinc) {
2566 tcg_gen_addi_tl(cpu_R[dc->op1], cpu_R[dc->op1], memsize);
2567 }
2568 return 2;
8170028d
TS		 2569}
2570
cf7e0c80 2571static int dec_movem_mr(CPUCRISState *env, DisasContext *dc)
8170028d 2572{
7b5eff4d
EV		 2573 TCGv_i64 tmp[16];
2574 TCGv tmp32;
2575 TCGv addr;
2576 int i;
2577 int nr = dc->op2 + 1;
2578
2579 LOG_DIS("movem [$r%u%s, $r%u\n", dc->op1,
2580 dc->postinc ? "+]" : "]", dc->op2);
2581
2582 addr = tcg_temp_new();
2583 /* There are probably better ways of doing this. */
2584 cris_flush_cc_state(dc);
2585 for (i = 0; i < (nr >> 1); i++) {
2586 tmp[i] = tcg_temp_new_i64();
2587 tcg_gen_addi_tl(addr, cpu_R[dc->op1], i * 8);
2588 gen_load64(dc, tmp[i], addr);
2589 }
2590 if (nr & 1) {
2591 tmp32 = tcg_temp_new_i32();
2592 tcg_gen_addi_tl(addr, cpu_R[dc->op1], i * 8);
2593 gen_load(dc, tmp32, addr, 4, 0);
2594 } else {
2595 TCGV_UNUSED(tmp32);
2596 }
2597 tcg_temp_free(addr);
2598
2599 for (i = 0; i < (nr >> 1); i++) {
ecc7b3aa 2600 tcg_gen_extrl_i64_i32(cpu_R[i * 2], tmp[i]);
7b5eff4d 2601 tcg_gen_shri_i64(tmp[i], tmp[i], 32);
ecc7b3aa 2602 tcg_gen_extrl_i64_i32(cpu_R[i * 2 + 1], tmp[i]);
7b5eff4d
EV		 2603 tcg_temp_free_i64(tmp[i]);
2604 }
2605 if (nr & 1) {
2606 tcg_gen_mov_tl(cpu_R[dc->op2], tmp32);
2607 tcg_temp_free(tmp32);
2608 }
2609
2610 /* writeback the updated pointer value. */
2611 if (dc->postinc) {
2612 tcg_gen_addi_tl(cpu_R[dc->op1], cpu_R[dc->op1], nr * 4);
2613 }
2614
2615 /* gen_load might want to evaluate the previous insns flags. */
2616 cris_cc_mask(dc, 0);
2617 return 2;
8170028d
TS		 2618}
2619
cf7e0c80 2620static int dec_movem_rm(CPUCRISState *env, DisasContext *dc)
8170028d 2621{
7b5eff4d
EV		 2622 TCGv tmp;
2623 TCGv addr;
2624 int i;
2625
2626 LOG_DIS("movem $r%u, [$r%u%s\n", dc->op2, dc->op1,
2627 dc->postinc ? "+]" : "]");
2628
2629 cris_flush_cc_state(dc);
2630
2631 tmp = tcg_temp_new();
2632 addr = tcg_temp_new();
2633 tcg_gen_movi_tl(tmp, 4);
2634 tcg_gen_mov_tl(addr, cpu_R[dc->op1]);
2635 for (i = 0; i <= dc->op2; i++) {
2636 /* Displace addr. */
2637 /* Perform the store. */
2638 gen_store(dc, addr, cpu_R[i], 4);
2639 tcg_gen_add_tl(addr, addr, tmp);
2640 }
2641 if (dc->postinc) {
2642 tcg_gen_mov_tl(cpu_R[dc->op1], addr);
2643 }
2644 cris_cc_mask(dc, 0);
2645 tcg_temp_free(tmp);
2646 tcg_temp_free(addr);
2647 return 2;
8170028d
TS		 2648}
2649
cf7e0c80 2650static int dec_move_rm(CPUCRISState *env, DisasContext *dc)
8170028d 2651{
7b5eff4d 2652 int memsize;
8170028d 2653
7b5eff4d 2654 memsize = memsize_zz(dc);
8170028d 2655
7b5eff4d
EV		 2656 LOG_DIS("move.%c $r%u, [$r%u]\n",
2657 memsize_char(memsize), dc->op2, dc->op1);
8170028d 2658
7b5eff4d
EV		 2659 /* prepare store. */
2660 cris_flush_cc_state(dc);
2661 gen_store(dc, cpu_R[dc->op1], cpu_R[dc->op2], memsize);
17ac9754 2662
7b5eff4d
EV		 2663 if (dc->postinc) {
2664 tcg_gen_addi_tl(cpu_R[dc->op1], cpu_R[dc->op1], memsize);
2665 }
2666 cris_cc_mask(dc, 0);
2667 return 2;
8170028d
TS		 2668}
2669
cf7e0c80 2670static int dec_lapcq(CPUCRISState *env, DisasContext *dc)
8170028d 2671{
7b5eff4d
EV		 2672 LOG_DIS("lapcq %x, $r%u\n",
2673 dc->pc + dc->op1*2, dc->op2);
2674 cris_cc_mask(dc, 0);
2675 tcg_gen_movi_tl(cpu_R[dc->op2], dc->pc + dc->op1 * 2);
2676 return 2;
8170028d
TS		 2677}
2678
cf7e0c80 2679static int dec_lapc_im(CPUCRISState *env, DisasContext *dc)
8170028d 2680{
7b5eff4d
EV		 2681 unsigned int rd;
2682 int32_t imm;
2683 int32_t pc;
8170028d 2684
7b5eff4d 2685 rd = dc->op2;
8170028d 2686
7b5eff4d
EV		 2687 cris_cc_mask(dc, 0);
2688 imm = cris_fetch(env, dc, dc->pc + 2, 4, 0);
2689 LOG_DIS("lapc 0x%x, $r%u\n", imm + dc->pc, dc->op2);
b41f7df0 2690
7b5eff4d
EV		 2691 pc = dc->pc;
2692 pc += imm;
2693 tcg_gen_movi_tl(cpu_R[rd], pc);
2694 return 6;
8170028d
TS		 2695}
2696
2697/* Jump to special reg. */
cf7e0c80 2698static int dec_jump_p(CPUCRISState *env, DisasContext *dc)
8170028d 2699{
7b5eff4d 2700 LOG_DIS("jump $p%u\n", dc->op2);
b41f7df0 2701
7b5eff4d
EV		 2702 if (dc->op2 == PR_CCS) {
2703 cris_evaluate_flags(dc);
2704 }
2705 t_gen_mov_TN_preg(env_btarget, dc->op2);
2706 /* rete will often have low bit set to indicate delayslot. */
2707 tcg_gen_andi_tl(env_btarget, env_btarget, ~1);
2708 cris_cc_mask(dc, 0);
2709 cris_prepare_jmp(dc, JMP_INDIRECT);
2710 return 2;
8170028d
TS		 2711}
2712
2713/* Jump and save. */
cf7e0c80 2714static int dec_jas_r(CPUCRISState *env, DisasContext *dc)
8170028d 2715{
7b5eff4d
EV		 2716 LOG_DIS("jas $r%u, $p%u\n", dc->op1, dc->op2);
2717 cris_cc_mask(dc, 0);
2718 /* Store the return address in Pd. */
2719 tcg_gen_mov_tl(env_btarget, cpu_R[dc->op1]);
2720 if (dc->op2 > 15) {
2721 abort();
2722 }
2723 t_gen_mov_preg_TN(dc, dc->op2, tcg_const_tl(dc->pc + 4));
b41f7df0 2724
7b5eff4d
EV		 2725 cris_prepare_jmp(dc, JMP_INDIRECT);
2726 return 2;
8170028d
TS		 2727}
2728
cf7e0c80 2729static int dec_jas_im(CPUCRISState *env, DisasContext *dc)
8170028d 2730{
7b5eff4d 2731 uint32_t imm;
8170028d 2732
7b5eff4d 2733 imm = cris_fetch(env, dc, dc->pc + 2, 4, 0);
8170028d 2734
7b5eff4d
EV		 2735 LOG_DIS("jas 0x%x\n", imm);
2736 cris_cc_mask(dc, 0);
2737 /* Store the return address in Pd. */
2738 t_gen_mov_preg_TN(dc, dc->op2, tcg_const_tl(dc->pc + 8));
2a44f7f1 2739
7b5eff4d
EV		 2740 dc->jmp_pc = imm;
2741 cris_prepare_jmp(dc, JMP_DIRECT);
2742 return 6;
8170028d
TS		 2743}
2744
cf7e0c80 2745static int dec_jasc_im(CPUCRISState *env, DisasContext *dc)
8170028d 2746{
7b5eff4d 2747 uint32_t imm;
8170028d 2748
7b5eff4d 2749 imm = cris_fetch(env, dc, dc->pc + 2, 4, 0);
8170028d 2750
7b5eff4d
EV		 2751 LOG_DIS("jasc 0x%x\n", imm);
2752 cris_cc_mask(dc, 0);
2753 /* Store the return address in Pd. */
2754 t_gen_mov_preg_TN(dc, dc->op2, tcg_const_tl(dc->pc + 8 + 4));
2a44f7f1 2755
7b5eff4d
EV		 2756 dc->jmp_pc = imm;
2757 cris_prepare_jmp(dc, JMP_DIRECT);
2758 return 6;
8170028d
TS		 2759}
2760
cf7e0c80 2761static int dec_jasc_r(CPUCRISState *env, DisasContext *dc)
8170028d 2762{
7b5eff4d
EV		 2763 LOG_DIS("jasc_r $r%u, $p%u\n", dc->op1, dc->op2);
2764 cris_cc_mask(dc, 0);
2765 /* Store the return address in Pd. */
2766 tcg_gen_mov_tl(env_btarget, cpu_R[dc->op1]);
2767 t_gen_mov_preg_TN(dc, dc->op2, tcg_const_tl(dc->pc + 4 + 4));
2768 cris_prepare_jmp(dc, JMP_INDIRECT);
2769 return 2;
8170028d
TS		 2770}
2771
cf7e0c80 2772static int dec_bcc_im(CPUCRISState *env, DisasContext *dc)
8170028d 2773{
7b5eff4d
EV		 2774 int32_t offset;
2775 uint32_t cond = dc->op2;
8170028d 2776
7b5eff4d 2777 offset = cris_fetch(env, dc, dc->pc + 2, 2, 1);
8170028d 2778
7b5eff4d
EV		 2779 LOG_DIS("b%s %d pc=%x dst=%x\n",
2780 cc_name(cond), offset,
2781 dc->pc, dc->pc + offset);
8170028d 2782
7b5eff4d
EV		 2783 cris_cc_mask(dc, 0);
2784 /* op2 holds the condition-code. */
2785 cris_prepare_cc_branch(dc, offset, cond);
2786 return 4;
8170028d
TS		 2787}
2788
cf7e0c80 2789static int dec_bas_im(CPUCRISState *env, DisasContext *dc)
8170028d 2790{
7b5eff4d 2791 int32_t simm;
8170028d 2792
7b5eff4d 2793 simm = cris_fetch(env, dc, dc->pc + 2, 4, 0);
8170028d 2794
7b5eff4d
EV		 2795 LOG_DIS("bas 0x%x, $p%u\n", dc->pc + simm, dc->op2);
2796 cris_cc_mask(dc, 0);
2797 /* Store the return address in Pd. */
2798 t_gen_mov_preg_TN(dc, dc->op2, tcg_const_tl(dc->pc + 8));
8170028d 2799
7b5eff4d
EV		 2800 dc->jmp_pc = dc->pc + simm;
2801 cris_prepare_jmp(dc, JMP_DIRECT);
2802 return 6;
8170028d
TS		 2803}
2804
cf7e0c80 2805static int dec_basc_im(CPUCRISState *env, DisasContext *dc)
8170028d 2806{
7b5eff4d
EV		 2807 int32_t simm;
2808 simm = cris_fetch(env, dc, dc->pc + 2, 4, 0);
8170028d 2809
7b5eff4d
EV		 2810 LOG_DIS("basc 0x%x, $p%u\n", dc->pc + simm, dc->op2);
2811 cris_cc_mask(dc, 0);
2812 /* Store the return address in Pd. */
2813 t_gen_mov_preg_TN(dc, dc->op2, tcg_const_tl(dc->pc + 12));
2a44f7f1 2814
7b5eff4d
EV		 2815 dc->jmp_pc = dc->pc + simm;
2816 cris_prepare_jmp(dc, JMP_DIRECT);
2817 return 6;
8170028d
TS		 2818}
2819
cf7e0c80 2820static int dec_rfe_etc(CPUCRISState *env, DisasContext *dc)
8170028d 2821{
7b5eff4d
EV		 2822 cris_cc_mask(dc, 0);
2823
2824 if (dc->op2 == 15) {
259186a7
AF		 2825 tcg_gen_st_i32(tcg_const_i32(1), cpu_env,
2826 -offsetof(CRISCPU, env) + offsetof(CPUState, halted));
7b5eff4d
EV		 2827 tcg_gen_movi_tl(env_pc, dc->pc + 2);
2828 t_gen_raise_exception(EXCP_HLT);
2829 return 2;
2830 }
2831
2832 switch (dc->op2 & 7) {
2833 case 2:
2834 /* rfe. */
2835 LOG_DIS("rfe\n");
2836 cris_evaluate_flags(dc);
2837 gen_helper_rfe(cpu_env);
2838 dc->is_jmp = DISAS_UPDATE;
2839 break;
2840 case 5:
2841 /* rfn. */
2842 LOG_DIS("rfn\n");
2843 cris_evaluate_flags(dc);
2844 gen_helper_rfn(cpu_env);
2845 dc->is_jmp = DISAS_UPDATE;
2846 break;
2847 case 6:
2848 LOG_DIS("break %d\n", dc->op1);
2849 cris_evaluate_flags(dc);
2850 /* break. */
2851 tcg_gen_movi_tl(env_pc, dc->pc + 2);
2852
2853 /* Breaks start at 16 in the exception vector. */
2854 t_gen_mov_env_TN(trap_vector,
2855 tcg_const_tl(dc->op1 + 16));
2856 t_gen_raise_exception(EXCP_BREAK);
2857 dc->is_jmp = DISAS_UPDATE;
2858 break;
2859 default:
2860 printf("op2=%x\n", dc->op2);
2861 BUG();
2862 break;
2863
2864 }
2865 return 2;
8170028d
TS		 2866}
2867
cf7e0c80 2868static int dec_ftag_fidx_d_m(CPUCRISState *env, DisasContext *dc)
5d4a534d 2869{
7b5eff4d 2870 return 2;
5d4a534d
EI		 2871}
2872
cf7e0c80 2873static int dec_ftag_fidx_i_m(CPUCRISState *env, DisasContext *dc)
5d4a534d 2874{
7b5eff4d 2875 return 2;
5d4a534d
EI		 2876}
2877
cf7e0c80 2878static int dec_null(CPUCRISState *env, DisasContext *dc)
8170028d 2879{
7b5eff4d
EV		 2880 printf("unknown insn pc=%x opc=%x op1=%x op2=%x\n",
2881 dc->pc, dc->opcode, dc->op1, dc->op2);
2882 fflush(NULL);
2883 BUG();
2884 return 2;
8170028d
TS		 2885}
2886
9b32fbf8 2887static struct decoder_info {
7b5eff4d
EV		 2888 struct {
2889 uint32_t bits;
2890 uint32_t mask;
2891 };
2892 int (*dec)(CPUCRISState *env, DisasContext *dc);
8170028d 2893} decinfo[] = {
7b5eff4d
EV		 2894 /* Order matters here. */
2895 {DEC_MOVEQ, dec_moveq},
2896 {DEC_BTSTQ, dec_btstq},
2897 {DEC_CMPQ, dec_cmpq},
2898 {DEC_ADDOQ, dec_addoq},
2899 {DEC_ADDQ, dec_addq},
2900 {DEC_SUBQ, dec_subq},
2901 {DEC_ANDQ, dec_andq},
2902 {DEC_ORQ, dec_orq},
2903 {DEC_ASRQ, dec_asrq},
2904 {DEC_LSLQ, dec_lslq},
2905 {DEC_LSRQ, dec_lsrq},
2906 {DEC_BCCQ, dec_bccq},
2907
2908 {DEC_BCC_IM, dec_bcc_im},
2909 {DEC_JAS_IM, dec_jas_im},
2910 {DEC_JAS_R, dec_jas_r},
2911 {DEC_JASC_IM, dec_jasc_im},
2912 {DEC_JASC_R, dec_jasc_r},
2913 {DEC_BAS_IM, dec_bas_im},
2914 {DEC_BASC_IM, dec_basc_im},
2915 {DEC_JUMP_P, dec_jump_p},
2916 {DEC_LAPC_IM, dec_lapc_im},
2917 {DEC_LAPCQ, dec_lapcq},
2918
2919 {DEC_RFE_ETC, dec_rfe_etc},
2920 {DEC_ADDC_MR, dec_addc_mr},
2921
2922 {DEC_MOVE_MP, dec_move_mp},
2923 {DEC_MOVE_PM, dec_move_pm},
2924 {DEC_MOVEM_MR, dec_movem_mr},
2925 {DEC_MOVEM_RM, dec_movem_rm},
2926 {DEC_MOVE_PR, dec_move_pr},
2927 {DEC_SCC_R, dec_scc_r},
2928 {DEC_SETF, dec_setclrf},
2929 {DEC_CLEARF, dec_setclrf},
2930
2931 {DEC_MOVE_SR, dec_move_sr},
2932 {DEC_MOVE_RP, dec_move_rp},
2933 {DEC_SWAP_R, dec_swap_r},
2934 {DEC_ABS_R, dec_abs_r},
2935 {DEC_LZ_R, dec_lz_r},
2936 {DEC_MOVE_RS, dec_move_rs},
2937 {DEC_BTST_R, dec_btst_r},
2938 {DEC_ADDC_R, dec_addc_r},
2939
2940 {DEC_DSTEP_R, dec_dstep_r},
2941 {DEC_XOR_R, dec_xor_r},
2942 {DEC_MCP_R, dec_mcp_r},
2943 {DEC_CMP_R, dec_cmp_r},
2944
2945 {DEC_ADDI_R, dec_addi_r},
2946 {DEC_ADDI_ACR, dec_addi_acr},
2947
2948 {DEC_ADD_R, dec_add_r},
2949 {DEC_SUB_R, dec_sub_r},
2950
2951 {DEC_ADDU_R, dec_addu_r},
2952 {DEC_ADDS_R, dec_adds_r},
2953 {DEC_SUBU_R, dec_subu_r},
2954 {DEC_SUBS_R, dec_subs_r},
2955 {DEC_LSL_R, dec_lsl_r},
2956
2957 {DEC_AND_R, dec_and_r},
2958 {DEC_OR_R, dec_or_r},
2959 {DEC_BOUND_R, dec_bound_r},
2960 {DEC_ASR_R, dec_asr_r},
2961 {DEC_LSR_R, dec_lsr_r},
2962
2963 {DEC_MOVU_R, dec_movu_r},
2964 {DEC_MOVS_R, dec_movs_r},
2965 {DEC_NEG_R, dec_neg_r},
2966 {DEC_MOVE_R, dec_move_r},
2967
2968 {DEC_FTAG_FIDX_I_M, dec_ftag_fidx_i_m},
2969 {DEC_FTAG_FIDX_D_M, dec_ftag_fidx_d_m},
2970
2971 {DEC_MULS_R, dec_muls_r},
2972 {DEC_MULU_R, dec_mulu_r},
2973
2974 {DEC_ADDU_M, dec_addu_m},
2975 {DEC_ADDS_M, dec_adds_m},
2976 {DEC_SUBU_M, dec_subu_m},
2977 {DEC_SUBS_M, dec_subs_m},
2978
2979 {DEC_CMPU_M, dec_cmpu_m},
2980 {DEC_CMPS_M, dec_cmps_m},
2981 {DEC_MOVU_M, dec_movu_m},
2982 {DEC_MOVS_M, dec_movs_m},
2983
2984 {DEC_CMP_M, dec_cmp_m},
2985 {DEC_ADDO_M, dec_addo_m},
2986 {DEC_BOUND_M, dec_bound_m},
2987 {DEC_ADD_M, dec_add_m},
2988 {DEC_SUB_M, dec_sub_m},
2989 {DEC_AND_M, dec_and_m},
2990 {DEC_OR_M, dec_or_m},
2991 {DEC_MOVE_RM, dec_move_rm},
2992 {DEC_TEST_M, dec_test_m},
2993 {DEC_MOVE_MR, dec_move_mr},
2994
2995 {{0, 0}, dec_null}
8170028d
TS		 2996};
2997
cf7e0c80 2998static unsigned int crisv32_decoder(CPUCRISState *env, DisasContext *dc)
8170028d 2999{
7b5eff4d
EV		 3000 int insn_len = 2;
3001 int i;
8170028d 3002
7b5eff4d 3003 /* Load a halfword onto the instruction register. */
cf7e0c80 3004 dc->ir = cris_fetch(env, dc, dc->pc, 2, 0);
8170028d 3005
7b5eff4d
EV		 3006 /* Now decode it. */
3007 dc->opcode = EXTRACT_FIELD(dc->ir, 4, 11);
3008 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 3);
3009 dc->op2 = EXTRACT_FIELD(dc->ir, 12, 15);
3010 dc->zsize = EXTRACT_FIELD(dc->ir, 4, 4);
3011 dc->zzsize = EXTRACT_FIELD(dc->ir, 4, 5);
3012 dc->postinc = EXTRACT_FIELD(dc->ir, 10, 10);
3013
3014 /* Large switch for all insns. */
3015 for (i = 0; i < ARRAY_SIZE(decinfo); i++) {
3016 if ((dc->opcode & decinfo[i].mask) == decinfo[i].bits) {
3017 insn_len = decinfo[i].dec(env, dc);
3018 break;
3019 }
3020 }
8170028d 3021
dd20fcd0 3022#if !defined(CONFIG_USER_ONLY)
7b5eff4d
EV		 3023 /* Single-stepping ? */
3024 if (dc->tb_flags & S_FLAG) {
42a268c2 3025 TCGLabel *l1 = gen_new_label();
7b5eff4d
EV		 3026 tcg_gen_brcondi_tl(TCG_COND_NE, cpu_PR[PR_SPC], dc->pc, l1);
3027 /* We treat SPC as a break with an odd trap vector. */
3028 cris_evaluate_flags(dc);
3029 t_gen_mov_env_TN(trap_vector, tcg_const_tl(3));
3030 tcg_gen_movi_tl(env_pc, dc->pc + insn_len);
3031 tcg_gen_movi_tl(cpu_PR[PR_SPC], dc->pc + insn_len);
3032 t_gen_raise_exception(EXCP_BREAK);
3033 gen_set_label(l1);
3034 }
a1aebcb8 3035#endif
7b5eff4d 3036 return insn_len;
8170028d
TS		 3037}
3038
40e9eddd 3039#include "translate_v10.c"
cf1d97f0
EI		 3040
3041/*
3042 * Delay slots on QEMU/CRIS.
3043 *
3044 * If an exception hits on a delayslot, the core will let ERP (the Exception
3045 * Return Pointer) point to the branch (the previous) insn and set the lsb to
3046 * to give SW a hint that the exception actually hit on the dslot.
3047 *
3048 * CRIS expects all PC addresses to be 16-bit aligned. The lsb is ignored by
3049 * the core and any jmp to an odd addresses will mask off that lsb. It is
3050 * simply there to let sw know there was an exception on a dslot.
3051 *
3052 * When the software returns from an exception, the branch will re-execute.
3053 * On QEMU care needs to be taken when a branch+delayslot sequence is broken
3054 * and the branch and delayslot dont share pages.
3055 *
3056 * The TB contaning the branch insn will set up env->btarget and evaluate
3057 * env->btaken. When the translation loop exits we will note that the branch
3058 * sequence is broken and let env->dslot be the size of the branch insn (those
3059 * vary in length).
3060 *
3061 * The TB contaning the delayslot will have the PC of its real insn (i.e no lsb
3062 * set). It will also expect to have env->dslot setup with the size of the
3063 * delay slot so that env->pc - env->dslot point to the branch insn. This TB
3064 * will execute the dslot and take the branch, either to btarget or just one
3065 * insn ahead.
3066 *
3067 * When exceptions occur, we check for env->dslot in do_interrupt to detect
3068 * broken branch sequences and setup $erp accordingly (i.e let it point to the
3069 * branch and set lsb). Then env->dslot gets cleared so that the exception
3070 * handler can enter. When returning from exceptions (jump $erp) the lsb gets
3071 * masked off and we will reexecute the branch insn.
3072 *
3073 */
3074
8170028d 3075/* generate intermediate code for basic block 'tb'. */
4e5e1215 3076void gen_intermediate_code(CPUCRISState *env, struct TranslationBlock *tb)
8170028d 3077{
4e5e1215 3078 CRISCPU *cpu = cris_env_get_cpu(env);
ed2803da 3079 CPUState *cs = CPU(cpu);
7b5eff4d
EV		 3080 uint32_t pc_start;
3081 unsigned int insn_len;
7b5eff4d
EV		 3082 struct DisasContext ctx;
3083 struct DisasContext *dc = &ctx;
3084 uint32_t next_page_start;
3085 target_ulong npc;
3086 int num_insns;
3087 int max_insns;
3088
7b5eff4d
EV		 3089 if (env->pregs[PR_VR] == 32) {
3090 dc->decoder = crisv32_decoder;
3091 dc->clear_locked_irq = 0;
3092 } else {
3093 dc->decoder = crisv10_decoder;
3094 dc->clear_locked_irq = 1;
3095 }
3096
3097 /* Odd PC indicates that branch is rexecuting due to exception in the
3098 * delayslot, like in real hw.
3099 */
3100 pc_start = tb->pc & ~1;
0dd106c5 3101 dc->cpu = cpu;
7b5eff4d
EV		 3102 dc->tb = tb;
3103
7b5eff4d
EV		 3104 dc->is_jmp = DISAS_NEXT;
3105 dc->ppc = pc_start;
3106 dc->pc = pc_start;
ed2803da 3107 dc->singlestep_enabled = cs->singlestep_enabled;
7b5eff4d
EV		 3108 dc->flags_uptodate = 1;
3109 dc->flagx_known = 1;
3110 dc->flags_x = tb->flags & X_FLAG;
3111 dc->cc_x_uptodate = 0;
3112 dc->cc_mask = 0;
3113 dc->update_cc = 0;
3114 dc->clear_prefix = 0;
3115
3116 cris_update_cc_op(dc, CC_OP_FLAGS, 4);
3117 dc->cc_size_uptodate = -1;
3118
3119 /* Decode TB flags. */
3120 dc->tb_flags = tb->flags & (S_FLAG | P_FLAG | U_FLAG \
3121 | X_FLAG | PFIX_FLAG);
3122 dc->delayed_branch = !!(tb->flags & 7);
3123 if (dc->delayed_branch) {
3124 dc->jmp = JMP_INDIRECT;
3125 } else {
3126 dc->jmp = JMP_NOJMP;
3127 }
3128
3129 dc->cpustate_changed = 0;
3130
3131 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
3132 qemu_log(
4e5e1215 3133 "pc=%x %x flg=%" PRIx64 " bt=%x ds=%u ccs=%x\n"
7b5eff4d
EV		 3134 "pid=%x usp=%x\n"
3135 "%x.%x.%x.%x\n"
3136 "%x.%x.%x.%x\n"
3137 "%x.%x.%x.%x\n"
3138 "%x.%x.%x.%x\n",
4e5e1215 3139 dc->pc, dc->ppc,
7b5eff4d
EV		 3140 (uint64_t)tb->flags,
3141 env->btarget, (unsigned)tb->flags & 7,
3142 env->pregs[PR_CCS],
3143 env->pregs[PR_PID], env->pregs[PR_USP],
3144 env->regs[0], env->regs[1], env->regs[2], env->regs[3],
3145 env->regs[4], env->regs[5], env->regs[6], env->regs[7],
3146 env->regs[8], env->regs[9],
3147 env->regs[10], env->regs[11],
3148 env->regs[12], env->regs[13],
3149 env->regs[14], env->regs[15]);
3150 qemu_log("--------------\n");
3151 qemu_log("IN: %s\n", lookup_symbol(pc_start));
3152 }
3153
3154 next_page_start = (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
7b5eff4d
EV		 3155 num_insns = 0;
3156 max_insns = tb->cflags & CF_COUNT_MASK;
3157 if (max_insns == 0) {
3158 max_insns = CF_COUNT_MASK;
3159 }
190ce7fb
RH		 3160 if (max_insns > TCG_MAX_INSNS) {
3161 max_insns = TCG_MAX_INSNS;
3162 }
7b5eff4d 3163
cd42d5b2 3164 gen_tb_start(tb);
7b5eff4d 3165 do {
bd03c791
RH		 3166 tcg_gen_insn_start(dc->delayed_branch == 1
3167 ? dc->ppc | 1 : dc->pc);
959082fc 3168 num_insns++;
7b5eff4d 3169
b933066a
RH		 3170 if (unlikely(cpu_breakpoint_test(cs, dc->pc, BP_ANY))) {
3171 cris_evaluate_flags(dc);
3172 tcg_gen_movi_tl(env_pc, dc->pc);
3173 t_gen_raise_exception(EXCP_DEBUG);
3174 dc->is_jmp = DISAS_UPDATE;
522a0d4e
RH		 3175 /* The address covered by the breakpoint must be included in
3176 [tb->pc, tb->pc + tb->size) in order to for it to be
3177 properly cleared -- thus we increment the PC here so that
3178 the logic setting tb->size below does the right thing. */
3179 dc->pc += 2;
b933066a
RH		 3180 break;
3181 }
3182
7b5eff4d
EV		 3183 /* Pretty disas. */
3184 LOG_DIS("%8.8x:\t", dc->pc);
3185
959082fc 3186 if (num_insns == max_insns && (tb->cflags & CF_LAST_IO)) {
7b5eff4d
EV		 3187 gen_io_start();
3188 }
3189 dc->clear_x = 1;
3190
3191 insn_len = dc->decoder(env, dc);
3192 dc->ppc = dc->pc;
3193 dc->pc += insn_len;
3194 if (dc->clear_x) {
3195 cris_clear_x_flag(dc);
3196 }
3197
7b5eff4d
EV		 3198 /* Check for delayed branches here. If we do it before
3199 actually generating any host code, the simulator will just
3200 loop doing nothing for on this program location. */
3201 if (dc->delayed_branch) {
3202 dc->delayed_branch--;
3203 if (dc->delayed_branch == 0) {
3204 if (tb->flags & 7) {
3205 t_gen_mov_env_TN(dslot, tcg_const_tl(0));
3206 }
3207 if (dc->cpustate_changed || !dc->flagx_known
3208 || (dc->flags_x != (tb->flags & X_FLAG))) {
3209 cris_store_direct_jmp(dc);
3210 }
3211
3212 if (dc->clear_locked_irq) {
3213 dc->clear_locked_irq = 0;
3214 t_gen_mov_env_TN(locked_irq, tcg_const_tl(0));
3215 }
3216
3217 if (dc->jmp == JMP_DIRECT_CC) {
42a268c2 3218 TCGLabel *l1 = gen_new_label();
7b5eff4d
EV		 3219 cris_evaluate_flags(dc);
3220
3221 /* Conditional jmp. */
3222 tcg_gen_brcondi_tl(TCG_COND_EQ,
3223 env_btaken, 0, l1);
3224 gen_goto_tb(dc, 1, dc->jmp_pc);
3225 gen_set_label(l1);
3226 gen_goto_tb(dc, 0, dc->pc);
3227 dc->is_jmp = DISAS_TB_JUMP;
3228 dc->jmp = JMP_NOJMP;
3229 } else if (dc->jmp == JMP_DIRECT) {
3230 cris_evaluate_flags(dc);
3231 gen_goto_tb(dc, 0, dc->jmp_pc);
3232 dc->is_jmp = DISAS_TB_JUMP;
3233 dc->jmp = JMP_NOJMP;
3234 } else {
3235 t_gen_cc_jmp(env_btarget, tcg_const_tl(dc->pc));
3236 dc->is_jmp = DISAS_JUMP;
3237 }
3238 break;
3239 }
3240 }
3241
3242 /* If we are rexecuting a branch due to exceptions on
3243 delay slots dont break. */
ed2803da 3244 if (!(tb->pc & 1) && cs->singlestep_enabled) {
7b5eff4d
EV		 3245 break;
3246 }
3247 } while (!dc->is_jmp && !dc->cpustate_changed
fe700adb 3248 && !tcg_op_buf_full()
7b5eff4d
EV		 3249 && !singlestep
3250 && (dc->pc < next_page_start)
3251 && num_insns < max_insns);
3252
3253 if (dc->clear_locked_irq) {
3254 t_gen_mov_env_TN(locked_irq, tcg_const_tl(0));
3255 }
3256
3257 npc = dc->pc;
2a44f7f1 3258
2e70f6ef
PB		 3259 if (tb->cflags & CF_LAST_IO)
3260 gen_io_end();
7b5eff4d
EV		 3261 /* Force an update if the per-tb cpu state has changed. */
3262 if (dc->is_jmp == DISAS_NEXT
3263 && (dc->cpustate_changed || !dc->flagx_known
3264 || (dc->flags_x != (tb->flags & X_FLAG)))) {
3265 dc->is_jmp = DISAS_UPDATE;
3266 tcg_gen_movi_tl(env_pc, npc);
3267 }
3268 /* Broken branch+delayslot sequence. */
3269 if (dc->delayed_branch == 1) {
3270 /* Set env->dslot to the size of the branch insn. */
3271 t_gen_mov_env_TN(dslot, tcg_const_tl(dc->pc - dc->ppc));
3272 cris_store_direct_jmp(dc);
3273 }
3274
3275 cris_evaluate_flags(dc);
3276
ed2803da 3277 if (unlikely(cs->singlestep_enabled)) {
7b5eff4d
EV		 3278 if (dc->is_jmp == DISAS_NEXT) {
3279 tcg_gen_movi_tl(env_pc, npc);
3280 }
3281 t_gen_raise_exception(EXCP_DEBUG);
3282 } else {
3283 switch (dc->is_jmp) {
3284 case DISAS_NEXT:
3285 gen_goto_tb(dc, 1, npc);
3286 break;
3287 default:
3288 case DISAS_JUMP:
3289 case DISAS_UPDATE:
3290 /* indicate that the hash table must be used
3291 to find the next TB */
3292 tcg_gen_exit_tb(0);
3293 break;
3294 case DISAS_SWI:
3295 case DISAS_TB_JUMP:
3296 /* nothing more to generate */
3297 break;
3298 }
3299 }
806f352d 3300 gen_tb_end(tb, num_insns);
0a7df5da 3301
4e5e1215
RH		 3302 tb->size = dc->pc - pc_start;
3303 tb->icount = num_insns;
8170028d
TS		 3304
3305#ifdef DEBUG_DISAS
a1aebcb8 3306#if !DISAS_CRIS
7b5eff4d 3307 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
d49190c4 3308 log_target_disas(cs, pc_start, dc->pc - pc_start,
0dd106c5 3309 env->pregs[PR_VR]);
fe700adb
RH		 3310 qemu_log("\nisize=%d osize=%d\n",
3311 dc->pc - pc_start, tcg_op_buf_count());
7b5eff4d 3312 }
8170028d 3313#endif
a1aebcb8 3314#endif
8170028d
TS		 3315}
3316
878096ee
AF		 3317void cris_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,
3318 int flags)
8170028d 3319{
878096ee
AF		 3320 CRISCPU *cpu = CRIS_CPU(cs);
3321 CPUCRISState *env = &cpu->env;
7b5eff4d
EV		 3322 int i;
3323 uint32_t srs;
3324
3325 if (!env || !f) {
3326 return;
3327 }
3328
3329 cpu_fprintf(f, "PC=%x CCS=%x btaken=%d btarget=%x\n"
3330 "cc_op=%d cc_src=%d cc_dest=%d cc_result=%x cc_mask=%x\n",
3331 env->pc, env->pregs[PR_CCS], env->btaken, env->btarget,
3332 env->cc_op,
3333 env->cc_src, env->cc_dest, env->cc_result, env->cc_mask);
3334
3335
3336 for (i = 0; i < 16; i++) {
3337 cpu_fprintf(f, "%s=%8.8x ", regnames[i], env->regs[i]);
3338 if ((i + 1) % 4 == 0) {
3339 cpu_fprintf(f, "\n");
3340 }
3341 }
3342 cpu_fprintf(f, "\nspecial regs:\n");
3343 for (i = 0; i < 16; i++) {
3344 cpu_fprintf(f, "%s=%8.8x ", pregnames[i], env->pregs[i]);
3345 if ((i + 1) % 4 == 0) {
3346 cpu_fprintf(f, "\n");
3347 }
3348 }
3349 srs = env->pregs[PR_SRS];
3350 cpu_fprintf(f, "\nsupport function regs bank %x:\n", srs);
3351 if (srs < ARRAY_SIZE(env->sregs)) {
3352 for (i = 0; i < 16; i++) {
3353 cpu_fprintf(f, "s%2.2d=%8.8x ",
3354 i, env->sregs[srs][i]);
3355 if ((i + 1) % 4 == 0) {
3356 cpu_fprintf(f, "\n");
3357 }
3358 }
3359 }
3360 cpu_fprintf(f, "\n\n");
8170028d
TS		 3361
3362}
3363
d1a94fec
AF		 3364void cris_initialize_tcg(void)
3365{
3366 int i;
05ba7d5f 3367
dd10ce6d 3368 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
e1ccc054 3369 cc_x = tcg_global_mem_new(cpu_env,
dd10ce6d 3370 offsetof(CPUCRISState, cc_x), "cc_x");
e1ccc054 3371 cc_src = tcg_global_mem_new(cpu_env,
dd10ce6d 3372 offsetof(CPUCRISState, cc_src), "cc_src");
e1ccc054 3373 cc_dest = tcg_global_mem_new(cpu_env,
dd10ce6d
AF		 3374 offsetof(CPUCRISState, cc_dest),
3375 "cc_dest");
e1ccc054 3376 cc_result = tcg_global_mem_new(cpu_env,
dd10ce6d
AF		 3377 offsetof(CPUCRISState, cc_result),
3378 "cc_result");
e1ccc054 3379 cc_op = tcg_global_mem_new(cpu_env,
dd10ce6d 3380 offsetof(CPUCRISState, cc_op), "cc_op");
e1ccc054 3381 cc_size = tcg_global_mem_new(cpu_env,
dd10ce6d
AF		 3382 offsetof(CPUCRISState, cc_size),
3383 "cc_size");
e1ccc054 3384 cc_mask = tcg_global_mem_new(cpu_env,
dd10ce6d
AF		 3385 offsetof(CPUCRISState, cc_mask),
3386 "cc_mask");
3387
e1ccc054 3388 env_pc = tcg_global_mem_new(cpu_env,
dd10ce6d
AF		 3389 offsetof(CPUCRISState, pc),
3390 "pc");
e1ccc054 3391 env_btarget = tcg_global_mem_new(cpu_env,
dd10ce6d
AF		 3392 offsetof(CPUCRISState, btarget),
3393 "btarget");
e1ccc054 3394 env_btaken = tcg_global_mem_new(cpu_env,
dd10ce6d
AF		 3395 offsetof(CPUCRISState, btaken),
3396 "btaken");
3397 for (i = 0; i < 16; i++) {
e1ccc054 3398 cpu_R[i] = tcg_global_mem_new(cpu_env,
dd10ce6d
AF		 3399 offsetof(CPUCRISState, regs[i]),
3400 regnames[i]);
3401 }
3402 for (i = 0; i < 16; i++) {
e1ccc054 3403 cpu_PR[i] = tcg_global_mem_new(cpu_env,
dd10ce6d
AF		 3404 offsetof(CPUCRISState, pregs[i]),
3405 pregnames[i]);
3406 }
8170028d
TS		 3407}
3408
bad729e2
RH		 3409void restore_state_to_opc(CPUCRISState *env, TranslationBlock *tb,
3410 target_ulong *data)
d2856f1a 3411{
bad729e2 3412 env->pc = data[0];
d2856f1a 3413}
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