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2c0262af FB |
1 | /* |
2 | * i386 helpers | |
3 | * | |
4 | * Copyright (c) 2003 Fabrice Bellard | |
5 | * | |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
9 | * version 2 of the License, or (at your option) any later version. | |
10 | * | |
11 | * This library is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU Lesser General Public | |
17 | * License along with this library; if not, write to the Free Software | |
18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
19 | */ | |
20 | #include "exec.h" | |
21 | ||
f3f2d9be FB |
22 | //#define DEBUG_PCALL |
23 | ||
8145122b FB |
24 | #if 0 |
25 | #define raise_exception_err(a, b)\ | |
26 | do {\ | |
2ee73ac3 | 27 | fprintf(logfile, "raise_exception line=%d\n", __LINE__);\ |
8145122b FB |
28 | (raise_exception_err)(a, b);\ |
29 | } while (0) | |
30 | #endif | |
31 | ||
2c0262af FB |
32 | const uint8_t parity_table[256] = { |
33 | CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0, | |
34 | 0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P, | |
35 | 0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P, | |
36 | CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0, | |
37 | 0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P, | |
38 | CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0, | |
39 | CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0, | |
40 | 0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P, | |
41 | 0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P, | |
42 | CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0, | |
43 | CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0, | |
44 | 0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P, | |
45 | CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0, | |
46 | 0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P, | |
47 | 0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P, | |
48 | CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0, | |
49 | 0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P, | |
50 | CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0, | |
51 | CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0, | |
52 | 0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P, | |
53 | CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0, | |
54 | 0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P, | |
55 | 0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P, | |
56 | CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0, | |
57 | CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0, | |
58 | 0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P, | |
59 | 0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P, | |
60 | CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0, | |
61 | 0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P, | |
62 | CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0, | |
63 | CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0, | |
64 | 0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P, | |
65 | }; | |
66 | ||
67 | /* modulo 17 table */ | |
68 | const uint8_t rclw_table[32] = { | |
69 | 0, 1, 2, 3, 4, 5, 6, 7, | |
70 | 8, 9,10,11,12,13,14,15, | |
71 | 16, 0, 1, 2, 3, 4, 5, 6, | |
72 | 7, 8, 9,10,11,12,13,14, | |
73 | }; | |
74 | ||
75 | /* modulo 9 table */ | |
76 | const uint8_t rclb_table[32] = { | |
77 | 0, 1, 2, 3, 4, 5, 6, 7, | |
78 | 8, 0, 1, 2, 3, 4, 5, 6, | |
79 | 7, 8, 0, 1, 2, 3, 4, 5, | |
80 | 6, 7, 8, 0, 1, 2, 3, 4, | |
81 | }; | |
82 | ||
83 | const CPU86_LDouble f15rk[7] = | |
84 | { | |
85 | 0.00000000000000000000L, | |
86 | 1.00000000000000000000L, | |
87 | 3.14159265358979323851L, /*pi*/ | |
88 | 0.30102999566398119523L, /*lg2*/ | |
89 | 0.69314718055994530943L, /*ln2*/ | |
90 | 1.44269504088896340739L, /*l2e*/ | |
91 | 3.32192809488736234781L, /*l2t*/ | |
92 | }; | |
93 | ||
94 | /* thread support */ | |
95 | ||
96 | spinlock_t global_cpu_lock = SPIN_LOCK_UNLOCKED; | |
97 | ||
98 | void cpu_lock(void) | |
99 | { | |
100 | spin_lock(&global_cpu_lock); | |
101 | } | |
102 | ||
103 | void cpu_unlock(void) | |
104 | { | |
105 | spin_unlock(&global_cpu_lock); | |
106 | } | |
107 | ||
108 | void cpu_loop_exit(void) | |
109 | { | |
110 | /* NOTE: the register at this point must be saved by hand because | |
111 | longjmp restore them */ | |
0d1a29f9 | 112 | regs_to_env(); |
2c0262af FB |
113 | longjmp(env->jmp_env, 1); |
114 | } | |
115 | ||
7e84c249 FB |
116 | /* return non zero if error */ |
117 | static inline int load_segment(uint32_t *e1_ptr, uint32_t *e2_ptr, | |
118 | int selector) | |
119 | { | |
120 | SegmentCache *dt; | |
121 | int index; | |
14ce26e7 | 122 | target_ulong ptr; |
7e84c249 FB |
123 | |
124 | if (selector & 0x4) | |
125 | dt = &env->ldt; | |
126 | else | |
127 | dt = &env->gdt; | |
128 | index = selector & ~7; | |
129 | if ((index + 7) > dt->limit) | |
130 | return -1; | |
131 | ptr = dt->base + index; | |
132 | *e1_ptr = ldl_kernel(ptr); | |
133 | *e2_ptr = ldl_kernel(ptr + 4); | |
134 | return 0; | |
135 | } | |
136 | ||
137 | static inline unsigned int get_seg_limit(uint32_t e1, uint32_t e2) | |
138 | { | |
139 | unsigned int limit; | |
140 | limit = (e1 & 0xffff) | (e2 & 0x000f0000); | |
141 | if (e2 & DESC_G_MASK) | |
142 | limit = (limit << 12) | 0xfff; | |
143 | return limit; | |
144 | } | |
145 | ||
14ce26e7 | 146 | static inline uint32_t get_seg_base(uint32_t e1, uint32_t e2) |
7e84c249 | 147 | { |
14ce26e7 | 148 | return ((e1 >> 16) | ((e2 & 0xff) << 16) | (e2 & 0xff000000)); |
7e84c249 FB |
149 | } |
150 | ||
151 | static inline void load_seg_cache_raw_dt(SegmentCache *sc, uint32_t e1, uint32_t e2) | |
152 | { | |
153 | sc->base = get_seg_base(e1, e2); | |
154 | sc->limit = get_seg_limit(e1, e2); | |
155 | sc->flags = e2; | |
156 | } | |
157 | ||
158 | /* init the segment cache in vm86 mode. */ | |
159 | static inline void load_seg_vm(int seg, int selector) | |
160 | { | |
161 | selector &= 0xffff; | |
162 | cpu_x86_load_seg_cache(env, seg, selector, | |
14ce26e7 | 163 | (selector << 4), 0xffff, 0); |
7e84c249 FB |
164 | } |
165 | ||
2c0262af FB |
166 | static inline void get_ss_esp_from_tss(uint32_t *ss_ptr, |
167 | uint32_t *esp_ptr, int dpl) | |
168 | { | |
169 | int type, index, shift; | |
170 | ||
171 | #if 0 | |
172 | { | |
173 | int i; | |
174 | printf("TR: base=%p limit=%x\n", env->tr.base, env->tr.limit); | |
175 | for(i=0;i<env->tr.limit;i++) { | |
176 | printf("%02x ", env->tr.base[i]); | |
177 | if ((i & 7) == 7) printf("\n"); | |
178 | } | |
179 | printf("\n"); | |
180 | } | |
181 | #endif | |
182 | ||
183 | if (!(env->tr.flags & DESC_P_MASK)) | |
184 | cpu_abort(env, "invalid tss"); | |
185 | type = (env->tr.flags >> DESC_TYPE_SHIFT) & 0xf; | |
186 | if ((type & 7) != 1) | |
187 | cpu_abort(env, "invalid tss type"); | |
188 | shift = type >> 3; | |
189 | index = (dpl * 4 + 2) << shift; | |
190 | if (index + (4 << shift) - 1 > env->tr.limit) | |
191 | raise_exception_err(EXCP0A_TSS, env->tr.selector & 0xfffc); | |
192 | if (shift == 0) { | |
61382a50 FB |
193 | *esp_ptr = lduw_kernel(env->tr.base + index); |
194 | *ss_ptr = lduw_kernel(env->tr.base + index + 2); | |
2c0262af | 195 | } else { |
61382a50 FB |
196 | *esp_ptr = ldl_kernel(env->tr.base + index); |
197 | *ss_ptr = lduw_kernel(env->tr.base + index + 4); | |
2c0262af FB |
198 | } |
199 | } | |
200 | ||
7e84c249 FB |
201 | /* XXX: merge with load_seg() */ |
202 | static void tss_load_seg(int seg_reg, int selector) | |
203 | { | |
204 | uint32_t e1, e2; | |
205 | int rpl, dpl, cpl; | |
206 | ||
207 | if ((selector & 0xfffc) != 0) { | |
208 | if (load_segment(&e1, &e2, selector) != 0) | |
209 | raise_exception_err(EXCP0A_TSS, selector & 0xfffc); | |
210 | if (!(e2 & DESC_S_MASK)) | |
211 | raise_exception_err(EXCP0A_TSS, selector & 0xfffc); | |
212 | rpl = selector & 3; | |
213 | dpl = (e2 >> DESC_DPL_SHIFT) & 3; | |
214 | cpl = env->hflags & HF_CPL_MASK; | |
215 | if (seg_reg == R_CS) { | |
216 | if (!(e2 & DESC_CS_MASK)) | |
217 | raise_exception_err(EXCP0A_TSS, selector & 0xfffc); | |
218 | if (dpl != rpl) | |
219 | raise_exception_err(EXCP0A_TSS, selector & 0xfffc); | |
220 | if ((e2 & DESC_C_MASK) && dpl > rpl) | |
221 | raise_exception_err(EXCP0A_TSS, selector & 0xfffc); | |
222 | ||
223 | } else if (seg_reg == R_SS) { | |
224 | /* SS must be writable data */ | |
225 | if ((e2 & DESC_CS_MASK) || !(e2 & DESC_W_MASK)) | |
226 | raise_exception_err(EXCP0A_TSS, selector & 0xfffc); | |
227 | if (dpl != cpl || dpl != rpl) | |
228 | raise_exception_err(EXCP0A_TSS, selector & 0xfffc); | |
229 | } else { | |
230 | /* not readable code */ | |
231 | if ((e2 & DESC_CS_MASK) && !(e2 & DESC_R_MASK)) | |
232 | raise_exception_err(EXCP0A_TSS, selector & 0xfffc); | |
233 | /* if data or non conforming code, checks the rights */ | |
234 | if (((e2 >> DESC_TYPE_SHIFT) & 0xf) < 12) { | |
235 | if (dpl < cpl || dpl < rpl) | |
236 | raise_exception_err(EXCP0A_TSS, selector & 0xfffc); | |
237 | } | |
238 | } | |
239 | if (!(e2 & DESC_P_MASK)) | |
240 | raise_exception_err(EXCP0B_NOSEG, selector & 0xfffc); | |
241 | cpu_x86_load_seg_cache(env, seg_reg, selector, | |
242 | get_seg_base(e1, e2), | |
243 | get_seg_limit(e1, e2), | |
244 | e2); | |
245 | } else { | |
246 | if (seg_reg == R_SS || seg_reg == R_CS) | |
247 | raise_exception_err(EXCP0A_TSS, selector & 0xfffc); | |
248 | } | |
249 | } | |
250 | ||
251 | #define SWITCH_TSS_JMP 0 | |
252 | #define SWITCH_TSS_IRET 1 | |
253 | #define SWITCH_TSS_CALL 2 | |
254 | ||
255 | /* XXX: restore CPU state in registers (PowerPC case) */ | |
256 | static void switch_tss(int tss_selector, | |
883da8e2 FB |
257 | uint32_t e1, uint32_t e2, int source, |
258 | uint32_t next_eip) | |
2c0262af | 259 | { |
7e84c249 | 260 | int tss_limit, tss_limit_max, type, old_tss_limit_max, old_type, v1, v2, i; |
14ce26e7 | 261 | target_ulong tss_base; |
7e84c249 FB |
262 | uint32_t new_regs[8], new_segs[6]; |
263 | uint32_t new_eflags, new_eip, new_cr3, new_ldt, new_trap; | |
264 | uint32_t old_eflags, eflags_mask; | |
2c0262af FB |
265 | SegmentCache *dt; |
266 | int index; | |
14ce26e7 | 267 | target_ulong ptr; |
2c0262af | 268 | |
7e84c249 | 269 | type = (e2 >> DESC_TYPE_SHIFT) & 0xf; |
dc6f57fd | 270 | #ifdef DEBUG_PCALL |
e19e89a5 | 271 | if (loglevel & CPU_LOG_PCALL) |
dc6f57fd FB |
272 | fprintf(logfile, "switch_tss: sel=0x%04x type=%d src=%d\n", tss_selector, type, source); |
273 | #endif | |
7e84c249 FB |
274 | |
275 | /* if task gate, we read the TSS segment and we load it */ | |
276 | if (type == 5) { | |
277 | if (!(e2 & DESC_P_MASK)) | |
278 | raise_exception_err(EXCP0B_NOSEG, tss_selector & 0xfffc); | |
279 | tss_selector = e1 >> 16; | |
280 | if (tss_selector & 4) | |
281 | raise_exception_err(EXCP0A_TSS, tss_selector & 0xfffc); | |
282 | if (load_segment(&e1, &e2, tss_selector) != 0) | |
283 | raise_exception_err(EXCP0D_GPF, tss_selector & 0xfffc); | |
284 | if (e2 & DESC_S_MASK) | |
285 | raise_exception_err(EXCP0D_GPF, tss_selector & 0xfffc); | |
286 | type = (e2 >> DESC_TYPE_SHIFT) & 0xf; | |
287 | if ((type & 7) != 1) | |
288 | raise_exception_err(EXCP0D_GPF, tss_selector & 0xfffc); | |
289 | } | |
290 | ||
291 | if (!(e2 & DESC_P_MASK)) | |
292 | raise_exception_err(EXCP0B_NOSEG, tss_selector & 0xfffc); | |
293 | ||
294 | if (type & 8) | |
295 | tss_limit_max = 103; | |
2c0262af | 296 | else |
7e84c249 FB |
297 | tss_limit_max = 43; |
298 | tss_limit = get_seg_limit(e1, e2); | |
299 | tss_base = get_seg_base(e1, e2); | |
300 | if ((tss_selector & 4) != 0 || | |
301 | tss_limit < tss_limit_max) | |
302 | raise_exception_err(EXCP0A_TSS, tss_selector & 0xfffc); | |
303 | old_type = (env->tr.flags >> DESC_TYPE_SHIFT) & 0xf; | |
304 | if (old_type & 8) | |
305 | old_tss_limit_max = 103; | |
306 | else | |
307 | old_tss_limit_max = 43; | |
308 | ||
309 | /* read all the registers from the new TSS */ | |
310 | if (type & 8) { | |
311 | /* 32 bit */ | |
312 | new_cr3 = ldl_kernel(tss_base + 0x1c); | |
313 | new_eip = ldl_kernel(tss_base + 0x20); | |
314 | new_eflags = ldl_kernel(tss_base + 0x24); | |
315 | for(i = 0; i < 8; i++) | |
316 | new_regs[i] = ldl_kernel(tss_base + (0x28 + i * 4)); | |
317 | for(i = 0; i < 6; i++) | |
318 | new_segs[i] = lduw_kernel(tss_base + (0x48 + i * 4)); | |
319 | new_ldt = lduw_kernel(tss_base + 0x60); | |
320 | new_trap = ldl_kernel(tss_base + 0x64); | |
321 | } else { | |
322 | /* 16 bit */ | |
323 | new_cr3 = 0; | |
324 | new_eip = lduw_kernel(tss_base + 0x0e); | |
325 | new_eflags = lduw_kernel(tss_base + 0x10); | |
326 | for(i = 0; i < 8; i++) | |
327 | new_regs[i] = lduw_kernel(tss_base + (0x12 + i * 2)) | 0xffff0000; | |
328 | for(i = 0; i < 4; i++) | |
329 | new_segs[i] = lduw_kernel(tss_base + (0x22 + i * 4)); | |
330 | new_ldt = lduw_kernel(tss_base + 0x2a); | |
331 | new_segs[R_FS] = 0; | |
332 | new_segs[R_GS] = 0; | |
333 | new_trap = 0; | |
334 | } | |
335 | ||
336 | /* NOTE: we must avoid memory exceptions during the task switch, | |
337 | so we make dummy accesses before */ | |
338 | /* XXX: it can still fail in some cases, so a bigger hack is | |
339 | necessary to valid the TLB after having done the accesses */ | |
340 | ||
341 | v1 = ldub_kernel(env->tr.base); | |
342 | v2 = ldub(env->tr.base + old_tss_limit_max); | |
343 | stb_kernel(env->tr.base, v1); | |
344 | stb_kernel(env->tr.base + old_tss_limit_max, v2); | |
345 | ||
346 | /* clear busy bit (it is restartable) */ | |
347 | if (source == SWITCH_TSS_JMP || source == SWITCH_TSS_IRET) { | |
14ce26e7 | 348 | target_ulong ptr; |
7e84c249 | 349 | uint32_t e2; |
883da8e2 | 350 | ptr = env->gdt.base + (env->tr.selector & ~7); |
7e84c249 FB |
351 | e2 = ldl_kernel(ptr + 4); |
352 | e2 &= ~DESC_TSS_BUSY_MASK; | |
353 | stl_kernel(ptr + 4, e2); | |
354 | } | |
355 | old_eflags = compute_eflags(); | |
356 | if (source == SWITCH_TSS_IRET) | |
357 | old_eflags &= ~NT_MASK; | |
358 | ||
359 | /* save the current state in the old TSS */ | |
360 | if (type & 8) { | |
361 | /* 32 bit */ | |
883da8e2 | 362 | stl_kernel(env->tr.base + 0x20, next_eip); |
7e84c249 | 363 | stl_kernel(env->tr.base + 0x24, old_eflags); |
0d1a29f9 FB |
364 | stl_kernel(env->tr.base + (0x28 + 0 * 4), EAX); |
365 | stl_kernel(env->tr.base + (0x28 + 1 * 4), ECX); | |
366 | stl_kernel(env->tr.base + (0x28 + 2 * 4), EDX); | |
367 | stl_kernel(env->tr.base + (0x28 + 3 * 4), EBX); | |
368 | stl_kernel(env->tr.base + (0x28 + 4 * 4), ESP); | |
369 | stl_kernel(env->tr.base + (0x28 + 5 * 4), EBP); | |
370 | stl_kernel(env->tr.base + (0x28 + 6 * 4), ESI); | |
371 | stl_kernel(env->tr.base + (0x28 + 7 * 4), EDI); | |
7e84c249 FB |
372 | for(i = 0; i < 6; i++) |
373 | stw_kernel(env->tr.base + (0x48 + i * 4), env->segs[i].selector); | |
374 | } else { | |
375 | /* 16 bit */ | |
883da8e2 | 376 | stw_kernel(env->tr.base + 0x0e, next_eip); |
7e84c249 | 377 | stw_kernel(env->tr.base + 0x10, old_eflags); |
0d1a29f9 FB |
378 | stw_kernel(env->tr.base + (0x12 + 0 * 2), EAX); |
379 | stw_kernel(env->tr.base + (0x12 + 1 * 2), ECX); | |
380 | stw_kernel(env->tr.base + (0x12 + 2 * 2), EDX); | |
381 | stw_kernel(env->tr.base + (0x12 + 3 * 2), EBX); | |
382 | stw_kernel(env->tr.base + (0x12 + 4 * 2), ESP); | |
383 | stw_kernel(env->tr.base + (0x12 + 5 * 2), EBP); | |
384 | stw_kernel(env->tr.base + (0x12 + 6 * 2), ESI); | |
385 | stw_kernel(env->tr.base + (0x12 + 7 * 2), EDI); | |
7e84c249 FB |
386 | for(i = 0; i < 4; i++) |
387 | stw_kernel(env->tr.base + (0x22 + i * 4), env->segs[i].selector); | |
388 | } | |
389 | ||
390 | /* now if an exception occurs, it will occurs in the next task | |
391 | context */ | |
392 | ||
393 | if (source == SWITCH_TSS_CALL) { | |
394 | stw_kernel(tss_base, env->tr.selector); | |
395 | new_eflags |= NT_MASK; | |
396 | } | |
397 | ||
398 | /* set busy bit */ | |
399 | if (source == SWITCH_TSS_JMP || source == SWITCH_TSS_CALL) { | |
14ce26e7 | 400 | target_ulong ptr; |
7e84c249 | 401 | uint32_t e2; |
883da8e2 | 402 | ptr = env->gdt.base + (tss_selector & ~7); |
7e84c249 FB |
403 | e2 = ldl_kernel(ptr + 4); |
404 | e2 |= DESC_TSS_BUSY_MASK; | |
405 | stl_kernel(ptr + 4, e2); | |
406 | } | |
407 | ||
408 | /* set the new CPU state */ | |
409 | /* from this point, any exception which occurs can give problems */ | |
410 | env->cr[0] |= CR0_TS_MASK; | |
883da8e2 | 411 | env->hflags |= HF_TS_MASK; |
7e84c249 FB |
412 | env->tr.selector = tss_selector; |
413 | env->tr.base = tss_base; | |
414 | env->tr.limit = tss_limit; | |
415 | env->tr.flags = e2 & ~DESC_TSS_BUSY_MASK; | |
416 | ||
417 | if ((type & 8) && (env->cr[0] & CR0_PG_MASK)) { | |
1ac157da | 418 | cpu_x86_update_cr3(env, new_cr3); |
7e84c249 FB |
419 | } |
420 | ||
421 | /* load all registers without an exception, then reload them with | |
422 | possible exception */ | |
423 | env->eip = new_eip; | |
4136f33c | 424 | eflags_mask = TF_MASK | AC_MASK | ID_MASK | |
8145122b | 425 | IF_MASK | IOPL_MASK | VM_MASK | RF_MASK | NT_MASK; |
7e84c249 FB |
426 | if (!(type & 8)) |
427 | eflags_mask &= 0xffff; | |
428 | load_eflags(new_eflags, eflags_mask); | |
0d1a29f9 FB |
429 | /* XXX: what to do in 16 bit case ? */ |
430 | EAX = new_regs[0]; | |
431 | ECX = new_regs[1]; | |
432 | EDX = new_regs[2]; | |
433 | EBX = new_regs[3]; | |
434 | ESP = new_regs[4]; | |
435 | EBP = new_regs[5]; | |
436 | ESI = new_regs[6]; | |
437 | EDI = new_regs[7]; | |
7e84c249 FB |
438 | if (new_eflags & VM_MASK) { |
439 | for(i = 0; i < 6; i++) | |
440 | load_seg_vm(i, new_segs[i]); | |
441 | /* in vm86, CPL is always 3 */ | |
442 | cpu_x86_set_cpl(env, 3); | |
443 | } else { | |
444 | /* CPL is set the RPL of CS */ | |
445 | cpu_x86_set_cpl(env, new_segs[R_CS] & 3); | |
446 | /* first just selectors as the rest may trigger exceptions */ | |
447 | for(i = 0; i < 6; i++) | |
14ce26e7 | 448 | cpu_x86_load_seg_cache(env, i, new_segs[i], 0, 0, 0); |
7e84c249 FB |
449 | } |
450 | ||
451 | env->ldt.selector = new_ldt & ~4; | |
14ce26e7 | 452 | env->ldt.base = 0; |
7e84c249 FB |
453 | env->ldt.limit = 0; |
454 | env->ldt.flags = 0; | |
455 | ||
456 | /* load the LDT */ | |
457 | if (new_ldt & 4) | |
458 | raise_exception_err(EXCP0A_TSS, new_ldt & 0xfffc); | |
459 | ||
8145122b FB |
460 | if ((new_ldt & 0xfffc) != 0) { |
461 | dt = &env->gdt; | |
462 | index = new_ldt & ~7; | |
463 | if ((index + 7) > dt->limit) | |
464 | raise_exception_err(EXCP0A_TSS, new_ldt & 0xfffc); | |
465 | ptr = dt->base + index; | |
466 | e1 = ldl_kernel(ptr); | |
467 | e2 = ldl_kernel(ptr + 4); | |
468 | if ((e2 & DESC_S_MASK) || ((e2 >> DESC_TYPE_SHIFT) & 0xf) != 2) | |
469 | raise_exception_err(EXCP0A_TSS, new_ldt & 0xfffc); | |
470 | if (!(e2 & DESC_P_MASK)) | |
471 | raise_exception_err(EXCP0A_TSS, new_ldt & 0xfffc); | |
472 | load_seg_cache_raw_dt(&env->ldt, e1, e2); | |
473 | } | |
7e84c249 FB |
474 | |
475 | /* load the segments */ | |
476 | if (!(new_eflags & VM_MASK)) { | |
477 | tss_load_seg(R_CS, new_segs[R_CS]); | |
478 | tss_load_seg(R_SS, new_segs[R_SS]); | |
479 | tss_load_seg(R_ES, new_segs[R_ES]); | |
480 | tss_load_seg(R_DS, new_segs[R_DS]); | |
481 | tss_load_seg(R_FS, new_segs[R_FS]); | |
482 | tss_load_seg(R_GS, new_segs[R_GS]); | |
483 | } | |
484 | ||
485 | /* check that EIP is in the CS segment limits */ | |
486 | if (new_eip > env->segs[R_CS].limit) { | |
883da8e2 | 487 | /* XXX: different exception if CALL ? */ |
7e84c249 FB |
488 | raise_exception_err(EXCP0D_GPF, 0); |
489 | } | |
2c0262af | 490 | } |
7e84c249 FB |
491 | |
492 | /* check if Port I/O is allowed in TSS */ | |
493 | static inline void check_io(int addr, int size) | |
2c0262af | 494 | { |
7e84c249 FB |
495 | int io_offset, val, mask; |
496 | ||
497 | /* TSS must be a valid 32 bit one */ | |
498 | if (!(env->tr.flags & DESC_P_MASK) || | |
499 | ((env->tr.flags >> DESC_TYPE_SHIFT) & 0xf) != 9 || | |
500 | env->tr.limit < 103) | |
501 | goto fail; | |
502 | io_offset = lduw_kernel(env->tr.base + 0x66); | |
503 | io_offset += (addr >> 3); | |
504 | /* Note: the check needs two bytes */ | |
505 | if ((io_offset + 1) > env->tr.limit) | |
506 | goto fail; | |
507 | val = lduw_kernel(env->tr.base + io_offset); | |
508 | val >>= (addr & 7); | |
509 | mask = (1 << size) - 1; | |
510 | /* all bits must be zero to allow the I/O */ | |
511 | if ((val & mask) != 0) { | |
512 | fail: | |
513 | raise_exception_err(EXCP0D_GPF, 0); | |
514 | } | |
2c0262af FB |
515 | } |
516 | ||
7e84c249 | 517 | void check_iob_T0(void) |
2c0262af | 518 | { |
7e84c249 | 519 | check_io(T0, 1); |
2c0262af FB |
520 | } |
521 | ||
7e84c249 | 522 | void check_iow_T0(void) |
2c0262af | 523 | { |
7e84c249 | 524 | check_io(T0, 2); |
2c0262af FB |
525 | } |
526 | ||
7e84c249 | 527 | void check_iol_T0(void) |
2c0262af | 528 | { |
7e84c249 FB |
529 | check_io(T0, 4); |
530 | } | |
531 | ||
532 | void check_iob_DX(void) | |
533 | { | |
534 | check_io(EDX & 0xffff, 1); | |
535 | } | |
536 | ||
537 | void check_iow_DX(void) | |
538 | { | |
539 | check_io(EDX & 0xffff, 2); | |
540 | } | |
541 | ||
542 | void check_iol_DX(void) | |
543 | { | |
544 | check_io(EDX & 0xffff, 4); | |
2c0262af FB |
545 | } |
546 | ||
891b38e4 FB |
547 | static inline unsigned int get_sp_mask(unsigned int e2) |
548 | { | |
549 | if (e2 & DESC_B_MASK) | |
550 | return 0xffffffff; | |
551 | else | |
552 | return 0xffff; | |
553 | } | |
554 | ||
555 | /* XXX: add a is_user flag to have proper security support */ | |
556 | #define PUSHW(ssp, sp, sp_mask, val)\ | |
557 | {\ | |
558 | sp -= 2;\ | |
559 | stw_kernel((ssp) + (sp & (sp_mask)), (val));\ | |
560 | } | |
561 | ||
562 | #define PUSHL(ssp, sp, sp_mask, val)\ | |
563 | {\ | |
564 | sp -= 4;\ | |
565 | stl_kernel((ssp) + (sp & (sp_mask)), (val));\ | |
566 | } | |
567 | ||
568 | #define POPW(ssp, sp, sp_mask, val)\ | |
569 | {\ | |
570 | val = lduw_kernel((ssp) + (sp & (sp_mask)));\ | |
571 | sp += 2;\ | |
572 | } | |
573 | ||
574 | #define POPL(ssp, sp, sp_mask, val)\ | |
575 | {\ | |
14ce26e7 | 576 | val = (uint32_t)ldl_kernel((ssp) + (sp & (sp_mask)));\ |
891b38e4 FB |
577 | sp += 4;\ |
578 | } | |
579 | ||
2c0262af FB |
580 | /* protected mode interrupt */ |
581 | static void do_interrupt_protected(int intno, int is_int, int error_code, | |
582 | unsigned int next_eip, int is_hw) | |
583 | { | |
584 | SegmentCache *dt; | |
14ce26e7 | 585 | target_ulong ptr, ssp; |
891b38e4 | 586 | int type, dpl, selector, ss_dpl, cpl, sp_mask; |
2c0262af | 587 | int has_error_code, new_stack, shift; |
891b38e4 FB |
588 | uint32_t e1, e2, offset, ss, esp, ss_e1, ss_e2; |
589 | uint32_t old_eip; | |
2c0262af | 590 | |
7e84c249 FB |
591 | has_error_code = 0; |
592 | if (!is_int && !is_hw) { | |
593 | switch(intno) { | |
594 | case 8: | |
595 | case 10: | |
596 | case 11: | |
597 | case 12: | |
598 | case 13: | |
599 | case 14: | |
600 | case 17: | |
601 | has_error_code = 1; | |
602 | break; | |
603 | } | |
604 | } | |
883da8e2 FB |
605 | if (is_int) |
606 | old_eip = next_eip; | |
607 | else | |
608 | old_eip = env->eip; | |
7e84c249 | 609 | |
2c0262af FB |
610 | dt = &env->idt; |
611 | if (intno * 8 + 7 > dt->limit) | |
612 | raise_exception_err(EXCP0D_GPF, intno * 8 + 2); | |
613 | ptr = dt->base + intno * 8; | |
61382a50 FB |
614 | e1 = ldl_kernel(ptr); |
615 | e2 = ldl_kernel(ptr + 4); | |
2c0262af FB |
616 | /* check gate type */ |
617 | type = (e2 >> DESC_TYPE_SHIFT) & 0x1f; | |
618 | switch(type) { | |
619 | case 5: /* task gate */ | |
7e84c249 FB |
620 | /* must do that check here to return the correct error code */ |
621 | if (!(e2 & DESC_P_MASK)) | |
622 | raise_exception_err(EXCP0B_NOSEG, intno * 8 + 2); | |
883da8e2 | 623 | switch_tss(intno * 8, e1, e2, SWITCH_TSS_CALL, old_eip); |
7e84c249 FB |
624 | if (has_error_code) { |
625 | int mask; | |
626 | /* push the error code */ | |
627 | shift = (env->segs[R_CS].flags >> DESC_B_SHIFT) & 1; | |
628 | if (env->segs[R_SS].flags & DESC_B_MASK) | |
629 | mask = 0xffffffff; | |
630 | else | |
631 | mask = 0xffff; | |
0d1a29f9 | 632 | esp = (ESP - (2 << shift)) & mask; |
7e84c249 FB |
633 | ssp = env->segs[R_SS].base + esp; |
634 | if (shift) | |
635 | stl_kernel(ssp, error_code); | |
636 | else | |
637 | stw_kernel(ssp, error_code); | |
0d1a29f9 | 638 | ESP = (esp & mask) | (ESP & ~mask); |
7e84c249 FB |
639 | } |
640 | return; | |
2c0262af FB |
641 | case 6: /* 286 interrupt gate */ |
642 | case 7: /* 286 trap gate */ | |
643 | case 14: /* 386 interrupt gate */ | |
644 | case 15: /* 386 trap gate */ | |
645 | break; | |
646 | default: | |
647 | raise_exception_err(EXCP0D_GPF, intno * 8 + 2); | |
648 | break; | |
649 | } | |
650 | dpl = (e2 >> DESC_DPL_SHIFT) & 3; | |
651 | cpl = env->hflags & HF_CPL_MASK; | |
652 | /* check privledge if software int */ | |
653 | if (is_int && dpl < cpl) | |
654 | raise_exception_err(EXCP0D_GPF, intno * 8 + 2); | |
655 | /* check valid bit */ | |
656 | if (!(e2 & DESC_P_MASK)) | |
657 | raise_exception_err(EXCP0B_NOSEG, intno * 8 + 2); | |
658 | selector = e1 >> 16; | |
659 | offset = (e2 & 0xffff0000) | (e1 & 0x0000ffff); | |
660 | if ((selector & 0xfffc) == 0) | |
661 | raise_exception_err(EXCP0D_GPF, 0); | |
662 | ||
663 | if (load_segment(&e1, &e2, selector) != 0) | |
664 | raise_exception_err(EXCP0D_GPF, selector & 0xfffc); | |
665 | if (!(e2 & DESC_S_MASK) || !(e2 & (DESC_CS_MASK))) | |
666 | raise_exception_err(EXCP0D_GPF, selector & 0xfffc); | |
667 | dpl = (e2 >> DESC_DPL_SHIFT) & 3; | |
668 | if (dpl > cpl) | |
669 | raise_exception_err(EXCP0D_GPF, selector & 0xfffc); | |
670 | if (!(e2 & DESC_P_MASK)) | |
671 | raise_exception_err(EXCP0B_NOSEG, selector & 0xfffc); | |
672 | if (!(e2 & DESC_C_MASK) && dpl < cpl) { | |
673 | /* to inner priviledge */ | |
674 | get_ss_esp_from_tss(&ss, &esp, dpl); | |
675 | if ((ss & 0xfffc) == 0) | |
676 | raise_exception_err(EXCP0A_TSS, ss & 0xfffc); | |
677 | if ((ss & 3) != dpl) | |
678 | raise_exception_err(EXCP0A_TSS, ss & 0xfffc); | |
679 | if (load_segment(&ss_e1, &ss_e2, ss) != 0) | |
680 | raise_exception_err(EXCP0A_TSS, ss & 0xfffc); | |
681 | ss_dpl = (ss_e2 >> DESC_DPL_SHIFT) & 3; | |
682 | if (ss_dpl != dpl) | |
683 | raise_exception_err(EXCP0A_TSS, ss & 0xfffc); | |
684 | if (!(ss_e2 & DESC_S_MASK) || | |
685 | (ss_e2 & DESC_CS_MASK) || | |
686 | !(ss_e2 & DESC_W_MASK)) | |
687 | raise_exception_err(EXCP0A_TSS, ss & 0xfffc); | |
688 | if (!(ss_e2 & DESC_P_MASK)) | |
689 | raise_exception_err(EXCP0A_TSS, ss & 0xfffc); | |
690 | new_stack = 1; | |
891b38e4 FB |
691 | sp_mask = get_sp_mask(ss_e2); |
692 | ssp = get_seg_base(ss_e1, ss_e2); | |
2c0262af FB |
693 | } else if ((e2 & DESC_C_MASK) || dpl == cpl) { |
694 | /* to same priviledge */ | |
8e682019 FB |
695 | if (env->eflags & VM_MASK) |
696 | raise_exception_err(EXCP0D_GPF, selector & 0xfffc); | |
2c0262af | 697 | new_stack = 0; |
891b38e4 FB |
698 | sp_mask = get_sp_mask(env->segs[R_SS].flags); |
699 | ssp = env->segs[R_SS].base; | |
700 | esp = ESP; | |
4796f5e9 | 701 | dpl = cpl; |
2c0262af FB |
702 | } else { |
703 | raise_exception_err(EXCP0D_GPF, selector & 0xfffc); | |
704 | new_stack = 0; /* avoid warning */ | |
891b38e4 | 705 | sp_mask = 0; /* avoid warning */ |
14ce26e7 | 706 | ssp = 0; /* avoid warning */ |
891b38e4 | 707 | esp = 0; /* avoid warning */ |
2c0262af FB |
708 | } |
709 | ||
710 | shift = type >> 3; | |
891b38e4 FB |
711 | |
712 | #if 0 | |
713 | /* XXX: check that enough room is available */ | |
2c0262af FB |
714 | push_size = 6 + (new_stack << 2) + (has_error_code << 1); |
715 | if (env->eflags & VM_MASK) | |
716 | push_size += 8; | |
717 | push_size <<= shift; | |
891b38e4 | 718 | #endif |
2c0262af | 719 | if (shift == 1) { |
2c0262af | 720 | if (new_stack) { |
8e682019 FB |
721 | if (env->eflags & VM_MASK) { |
722 | PUSHL(ssp, esp, sp_mask, env->segs[R_GS].selector); | |
723 | PUSHL(ssp, esp, sp_mask, env->segs[R_FS].selector); | |
724 | PUSHL(ssp, esp, sp_mask, env->segs[R_DS].selector); | |
725 | PUSHL(ssp, esp, sp_mask, env->segs[R_ES].selector); | |
726 | } | |
891b38e4 FB |
727 | PUSHL(ssp, esp, sp_mask, env->segs[R_SS].selector); |
728 | PUSHL(ssp, esp, sp_mask, ESP); | |
2c0262af | 729 | } |
891b38e4 FB |
730 | PUSHL(ssp, esp, sp_mask, compute_eflags()); |
731 | PUSHL(ssp, esp, sp_mask, env->segs[R_CS].selector); | |
732 | PUSHL(ssp, esp, sp_mask, old_eip); | |
2c0262af | 733 | if (has_error_code) { |
891b38e4 | 734 | PUSHL(ssp, esp, sp_mask, error_code); |
2c0262af FB |
735 | } |
736 | } else { | |
737 | if (new_stack) { | |
8e682019 FB |
738 | if (env->eflags & VM_MASK) { |
739 | PUSHW(ssp, esp, sp_mask, env->segs[R_GS].selector); | |
740 | PUSHW(ssp, esp, sp_mask, env->segs[R_FS].selector); | |
741 | PUSHW(ssp, esp, sp_mask, env->segs[R_DS].selector); | |
742 | PUSHW(ssp, esp, sp_mask, env->segs[R_ES].selector); | |
743 | } | |
891b38e4 FB |
744 | PUSHW(ssp, esp, sp_mask, env->segs[R_SS].selector); |
745 | PUSHW(ssp, esp, sp_mask, ESP); | |
2c0262af | 746 | } |
891b38e4 FB |
747 | PUSHW(ssp, esp, sp_mask, compute_eflags()); |
748 | PUSHW(ssp, esp, sp_mask, env->segs[R_CS].selector); | |
749 | PUSHW(ssp, esp, sp_mask, old_eip); | |
2c0262af | 750 | if (has_error_code) { |
891b38e4 | 751 | PUSHW(ssp, esp, sp_mask, error_code); |
2c0262af FB |
752 | } |
753 | } | |
754 | ||
891b38e4 | 755 | if (new_stack) { |
8e682019 | 756 | if (env->eflags & VM_MASK) { |
14ce26e7 FB |
757 | cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0, 0); |
758 | cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0, 0); | |
759 | cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0, 0); | |
760 | cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0, 0); | |
8e682019 | 761 | } |
891b38e4 FB |
762 | ss = (ss & ~3) | dpl; |
763 | cpu_x86_load_seg_cache(env, R_SS, ss, | |
764 | ssp, get_seg_limit(ss_e1, ss_e2), ss_e2); | |
765 | } | |
766 | ESP = (ESP & ~sp_mask) | (esp & sp_mask); | |
767 | ||
768 | selector = (selector & ~3) | dpl; | |
769 | cpu_x86_load_seg_cache(env, R_CS, selector, | |
770 | get_seg_base(e1, e2), | |
771 | get_seg_limit(e1, e2), | |
772 | e2); | |
773 | cpu_x86_set_cpl(env, dpl); | |
774 | env->eip = offset; | |
775 | ||
2c0262af FB |
776 | /* interrupt gate clear IF mask */ |
777 | if ((type & 1) == 0) { | |
778 | env->eflags &= ~IF_MASK; | |
779 | } | |
780 | env->eflags &= ~(TF_MASK | VM_MASK | RF_MASK | NT_MASK); | |
781 | } | |
782 | ||
14ce26e7 FB |
783 | #ifdef TARGET_X86_64 |
784 | ||
785 | #define PUSHQ(sp, val)\ | |
786 | {\ | |
787 | sp -= 8;\ | |
788 | stq_kernel(sp, (val));\ | |
789 | } | |
790 | ||
791 | #define POPQ(sp, val)\ | |
792 | {\ | |
793 | val = ldq_kernel(sp);\ | |
794 | sp += 8;\ | |
795 | } | |
796 | ||
797 | static inline target_ulong get_rsp_from_tss(int level) | |
798 | { | |
799 | int index; | |
800 | ||
801 | #if 0 | |
802 | printf("TR: base=" TARGET_FMT_lx " limit=%x\n", | |
803 | env->tr.base, env->tr.limit); | |
804 | #endif | |
805 | ||
806 | if (!(env->tr.flags & DESC_P_MASK)) | |
807 | cpu_abort(env, "invalid tss"); | |
808 | index = 8 * level + 4; | |
809 | if ((index + 7) > env->tr.limit) | |
810 | raise_exception_err(EXCP0A_TSS, env->tr.selector & 0xfffc); | |
811 | return ldq_kernel(env->tr.base + index); | |
812 | } | |
813 | ||
814 | /* 64 bit interrupt */ | |
815 | static void do_interrupt64(int intno, int is_int, int error_code, | |
816 | target_ulong next_eip, int is_hw) | |
817 | { | |
818 | SegmentCache *dt; | |
819 | target_ulong ptr; | |
820 | int type, dpl, selector, cpl, ist; | |
821 | int has_error_code, new_stack; | |
822 | uint32_t e1, e2, e3, ss; | |
823 | target_ulong old_eip, esp, offset; | |
824 | ||
825 | has_error_code = 0; | |
826 | if (!is_int && !is_hw) { | |
827 | switch(intno) { | |
828 | case 8: | |
829 | case 10: | |
830 | case 11: | |
831 | case 12: | |
832 | case 13: | |
833 | case 14: | |
834 | case 17: | |
835 | has_error_code = 1; | |
836 | break; | |
837 | } | |
838 | } | |
839 | if (is_int) | |
840 | old_eip = next_eip; | |
841 | else | |
842 | old_eip = env->eip; | |
843 | ||
844 | dt = &env->idt; | |
845 | if (intno * 16 + 15 > dt->limit) | |
846 | raise_exception_err(EXCP0D_GPF, intno * 16 + 2); | |
847 | ptr = dt->base + intno * 16; | |
848 | e1 = ldl_kernel(ptr); | |
849 | e2 = ldl_kernel(ptr + 4); | |
850 | e3 = ldl_kernel(ptr + 8); | |
851 | /* check gate type */ | |
852 | type = (e2 >> DESC_TYPE_SHIFT) & 0x1f; | |
853 | switch(type) { | |
854 | case 14: /* 386 interrupt gate */ | |
855 | case 15: /* 386 trap gate */ | |
856 | break; | |
857 | default: | |
858 | raise_exception_err(EXCP0D_GPF, intno * 16 + 2); | |
859 | break; | |
860 | } | |
861 | dpl = (e2 >> DESC_DPL_SHIFT) & 3; | |
862 | cpl = env->hflags & HF_CPL_MASK; | |
863 | /* check privledge if software int */ | |
864 | if (is_int && dpl < cpl) | |
865 | raise_exception_err(EXCP0D_GPF, intno * 16 + 2); | |
866 | /* check valid bit */ | |
867 | if (!(e2 & DESC_P_MASK)) | |
868 | raise_exception_err(EXCP0B_NOSEG, intno * 16 + 2); | |
869 | selector = e1 >> 16; | |
870 | offset = ((target_ulong)e3 << 32) | (e2 & 0xffff0000) | (e1 & 0x0000ffff); | |
871 | ist = e2 & 7; | |
872 | if ((selector & 0xfffc) == 0) | |
873 | raise_exception_err(EXCP0D_GPF, 0); | |
874 | ||
875 | if (load_segment(&e1, &e2, selector) != 0) | |
876 | raise_exception_err(EXCP0D_GPF, selector & 0xfffc); | |
877 | if (!(e2 & DESC_S_MASK) || !(e2 & (DESC_CS_MASK))) | |
878 | raise_exception_err(EXCP0D_GPF, selector & 0xfffc); | |
879 | dpl = (e2 >> DESC_DPL_SHIFT) & 3; | |
880 | if (dpl > cpl) | |
881 | raise_exception_err(EXCP0D_GPF, selector & 0xfffc); | |
882 | if (!(e2 & DESC_P_MASK)) | |
883 | raise_exception_err(EXCP0B_NOSEG, selector & 0xfffc); | |
884 | if (!(e2 & DESC_L_MASK) || (e2 & DESC_B_MASK)) | |
885 | raise_exception_err(EXCP0D_GPF, selector & 0xfffc); | |
886 | if ((!(e2 & DESC_C_MASK) && dpl < cpl) || ist != 0) { | |
887 | /* to inner priviledge */ | |
888 | if (ist != 0) | |
889 | esp = get_rsp_from_tss(ist + 3); | |
890 | else | |
891 | esp = get_rsp_from_tss(dpl); | |
892 | ss = 0; | |
893 | new_stack = 1; | |
894 | } else if ((e2 & DESC_C_MASK) || dpl == cpl) { | |
895 | /* to same priviledge */ | |
896 | if (env->eflags & VM_MASK) | |
897 | raise_exception_err(EXCP0D_GPF, selector & 0xfffc); | |
898 | new_stack = 0; | |
899 | esp = ESP & ~0xf; /* align stack */ | |
900 | dpl = cpl; | |
901 | } else { | |
902 | raise_exception_err(EXCP0D_GPF, selector & 0xfffc); | |
903 | new_stack = 0; /* avoid warning */ | |
904 | esp = 0; /* avoid warning */ | |
905 | } | |
906 | ||
907 | PUSHQ(esp, env->segs[R_SS].selector); | |
908 | PUSHQ(esp, ESP); | |
909 | PUSHQ(esp, compute_eflags()); | |
910 | PUSHQ(esp, env->segs[R_CS].selector); | |
911 | PUSHQ(esp, old_eip); | |
912 | if (has_error_code) { | |
913 | PUSHQ(esp, error_code); | |
914 | } | |
915 | ||
916 | if (new_stack) { | |
917 | ss = 0 | dpl; | |
918 | cpu_x86_load_seg_cache(env, R_SS, ss, 0, 0, 0); | |
919 | } | |
920 | ESP = esp; | |
921 | ||
922 | selector = (selector & ~3) | dpl; | |
923 | cpu_x86_load_seg_cache(env, R_CS, selector, | |
924 | get_seg_base(e1, e2), | |
925 | get_seg_limit(e1, e2), | |
926 | e2); | |
927 | cpu_x86_set_cpl(env, dpl); | |
928 | env->eip = offset; | |
929 | ||
930 | /* interrupt gate clear IF mask */ | |
931 | if ((type & 1) == 0) { | |
932 | env->eflags &= ~IF_MASK; | |
933 | } | |
934 | env->eflags &= ~(TF_MASK | VM_MASK | RF_MASK | NT_MASK); | |
935 | } | |
f419b321 | 936 | #endif |
14ce26e7 | 937 | |
06c2f506 | 938 | void helper_syscall(int next_eip_addend) |
14ce26e7 FB |
939 | { |
940 | int selector; | |
941 | ||
942 | if (!(env->efer & MSR_EFER_SCE)) { | |
943 | raise_exception_err(EXCP06_ILLOP, 0); | |
944 | } | |
945 | selector = (env->star >> 32) & 0xffff; | |
f419b321 | 946 | #ifdef TARGET_X86_64 |
14ce26e7 | 947 | if (env->hflags & HF_LMA_MASK) { |
06c2f506 | 948 | ECX = env->eip + next_eip_addend; |
14ce26e7 FB |
949 | env->regs[11] = compute_eflags(); |
950 | ||
951 | cpu_x86_set_cpl(env, 0); | |
952 | cpu_x86_load_seg_cache(env, R_CS, selector & 0xfffc, | |
953 | 0, 0xffffffff, | |
954 | DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | | |
955 | DESC_S_MASK | | |
956 | DESC_CS_MASK | DESC_R_MASK | DESC_A_MASK | DESC_L_MASK); | |
957 | cpu_x86_load_seg_cache(env, R_SS, (selector + 8) & 0xfffc, | |
958 | 0, 0xffffffff, | |
959 | DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | | |
960 | DESC_S_MASK | | |
961 | DESC_W_MASK | DESC_A_MASK); | |
962 | env->eflags &= ~env->fmask; | |
963 | if (env->hflags & HF_CS64_MASK) | |
964 | env->eip = env->lstar; | |
965 | else | |
966 | env->eip = env->cstar; | |
f419b321 FB |
967 | } else |
968 | #endif | |
969 | { | |
06c2f506 | 970 | ECX = (uint32_t)(env->eip + next_eip_addend); |
14ce26e7 FB |
971 | |
972 | cpu_x86_set_cpl(env, 0); | |
973 | cpu_x86_load_seg_cache(env, R_CS, selector & 0xfffc, | |
974 | 0, 0xffffffff, | |
975 | DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | | |
976 | DESC_S_MASK | | |
977 | DESC_CS_MASK | DESC_R_MASK | DESC_A_MASK); | |
978 | cpu_x86_load_seg_cache(env, R_SS, (selector + 8) & 0xfffc, | |
979 | 0, 0xffffffff, | |
980 | DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | | |
981 | DESC_S_MASK | | |
982 | DESC_W_MASK | DESC_A_MASK); | |
983 | env->eflags &= ~(IF_MASK | RF_MASK | VM_MASK); | |
984 | env->eip = (uint32_t)env->star; | |
985 | } | |
986 | } | |
987 | ||
988 | void helper_sysret(int dflag) | |
989 | { | |
990 | int cpl, selector; | |
991 | ||
f419b321 FB |
992 | if (!(env->efer & MSR_EFER_SCE)) { |
993 | raise_exception_err(EXCP06_ILLOP, 0); | |
994 | } | |
14ce26e7 FB |
995 | cpl = env->hflags & HF_CPL_MASK; |
996 | if (!(env->cr[0] & CR0_PE_MASK) || cpl != 0) { | |
997 | raise_exception_err(EXCP0D_GPF, 0); | |
998 | } | |
999 | selector = (env->star >> 48) & 0xffff; | |
f419b321 | 1000 | #ifdef TARGET_X86_64 |
14ce26e7 FB |
1001 | if (env->hflags & HF_LMA_MASK) { |
1002 | if (dflag == 2) { | |
1003 | cpu_x86_load_seg_cache(env, R_CS, (selector + 16) | 3, | |
1004 | 0, 0xffffffff, | |
1005 | DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | | |
1006 | DESC_S_MASK | (3 << DESC_DPL_SHIFT) | | |
1007 | DESC_CS_MASK | DESC_R_MASK | DESC_A_MASK | | |
1008 | DESC_L_MASK); | |
1009 | env->eip = ECX; | |
1010 | } else { | |
1011 | cpu_x86_load_seg_cache(env, R_CS, selector | 3, | |
1012 | 0, 0xffffffff, | |
1013 | DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | | |
1014 | DESC_S_MASK | (3 << DESC_DPL_SHIFT) | | |
1015 | DESC_CS_MASK | DESC_R_MASK | DESC_A_MASK); | |
1016 | env->eip = (uint32_t)ECX; | |
1017 | } | |
1018 | cpu_x86_load_seg_cache(env, R_SS, selector + 8, | |
1019 | 0, 0xffffffff, | |
1020 | DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | | |
1021 | DESC_S_MASK | (3 << DESC_DPL_SHIFT) | | |
1022 | DESC_W_MASK | DESC_A_MASK); | |
31313213 FB |
1023 | load_eflags((uint32_t)(env->regs[11]), TF_MASK | AC_MASK | ID_MASK | |
1024 | IF_MASK | IOPL_MASK | VM_MASK | RF_MASK | NT_MASK); | |
14ce26e7 | 1025 | cpu_x86_set_cpl(env, 3); |
f419b321 FB |
1026 | } else |
1027 | #endif | |
1028 | { | |
14ce26e7 FB |
1029 | cpu_x86_load_seg_cache(env, R_CS, selector | 3, |
1030 | 0, 0xffffffff, | |
1031 | DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | | |
1032 | DESC_S_MASK | (3 << DESC_DPL_SHIFT) | | |
1033 | DESC_CS_MASK | DESC_R_MASK | DESC_A_MASK); | |
1034 | env->eip = (uint32_t)ECX; | |
1035 | cpu_x86_load_seg_cache(env, R_SS, selector + 8, | |
1036 | 0, 0xffffffff, | |
1037 | DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | | |
1038 | DESC_S_MASK | (3 << DESC_DPL_SHIFT) | | |
1039 | DESC_W_MASK | DESC_A_MASK); | |
1040 | env->eflags |= IF_MASK; | |
1041 | cpu_x86_set_cpl(env, 3); | |
1042 | } | |
f419b321 FB |
1043 | #ifdef USE_KQEMU |
1044 | if (kqemu_is_ok(env)) { | |
1045 | if (env->hflags & HF_LMA_MASK) | |
1046 | CC_OP = CC_OP_EFLAGS; | |
1047 | env->exception_index = -1; | |
1048 | cpu_loop_exit(); | |
1049 | } | |
14ce26e7 | 1050 | #endif |
f419b321 | 1051 | } |
14ce26e7 | 1052 | |
2c0262af FB |
1053 | /* real mode interrupt */ |
1054 | static void do_interrupt_real(int intno, int is_int, int error_code, | |
4136f33c | 1055 | unsigned int next_eip) |
2c0262af FB |
1056 | { |
1057 | SegmentCache *dt; | |
14ce26e7 | 1058 | target_ulong ptr, ssp; |
2c0262af FB |
1059 | int selector; |
1060 | uint32_t offset, esp; | |
1061 | uint32_t old_cs, old_eip; | |
1062 | ||
1063 | /* real mode (simpler !) */ | |
1064 | dt = &env->idt; | |
1065 | if (intno * 4 + 3 > dt->limit) | |
1066 | raise_exception_err(EXCP0D_GPF, intno * 8 + 2); | |
1067 | ptr = dt->base + intno * 4; | |
61382a50 FB |
1068 | offset = lduw_kernel(ptr); |
1069 | selector = lduw_kernel(ptr + 2); | |
2c0262af FB |
1070 | esp = ESP; |
1071 | ssp = env->segs[R_SS].base; | |
1072 | if (is_int) | |
1073 | old_eip = next_eip; | |
1074 | else | |
1075 | old_eip = env->eip; | |
1076 | old_cs = env->segs[R_CS].selector; | |
891b38e4 FB |
1077 | /* XXX: use SS segment size ? */ |
1078 | PUSHW(ssp, esp, 0xffff, compute_eflags()); | |
1079 | PUSHW(ssp, esp, 0xffff, old_cs); | |
1080 | PUSHW(ssp, esp, 0xffff, old_eip); | |
2c0262af FB |
1081 | |
1082 | /* update processor state */ | |
1083 | ESP = (ESP & ~0xffff) | (esp & 0xffff); | |
1084 | env->eip = offset; | |
1085 | env->segs[R_CS].selector = selector; | |
14ce26e7 | 1086 | env->segs[R_CS].base = (selector << 4); |
2c0262af FB |
1087 | env->eflags &= ~(IF_MASK | TF_MASK | AC_MASK | RF_MASK); |
1088 | } | |
1089 | ||
1090 | /* fake user mode interrupt */ | |
1091 | void do_interrupt_user(int intno, int is_int, int error_code, | |
14ce26e7 | 1092 | target_ulong next_eip) |
2c0262af FB |
1093 | { |
1094 | SegmentCache *dt; | |
14ce26e7 | 1095 | target_ulong ptr; |
2c0262af FB |
1096 | int dpl, cpl; |
1097 | uint32_t e2; | |
1098 | ||
1099 | dt = &env->idt; | |
1100 | ptr = dt->base + (intno * 8); | |
61382a50 | 1101 | e2 = ldl_kernel(ptr + 4); |
2c0262af FB |
1102 | |
1103 | dpl = (e2 >> DESC_DPL_SHIFT) & 3; | |
1104 | cpl = env->hflags & HF_CPL_MASK; | |
1105 | /* check privledge if software int */ | |
1106 | if (is_int && dpl < cpl) | |
1107 | raise_exception_err(EXCP0D_GPF, intno * 8 + 2); | |
1108 | ||
1109 | /* Since we emulate only user space, we cannot do more than | |
1110 | exiting the emulation with the suitable exception and error | |
1111 | code */ | |
1112 | if (is_int) | |
1113 | EIP = next_eip; | |
1114 | } | |
1115 | ||
1116 | /* | |
e19e89a5 | 1117 | * Begin execution of an interruption. is_int is TRUE if coming from |
2c0262af FB |
1118 | * the int instruction. next_eip is the EIP value AFTER the interrupt |
1119 | * instruction. It is only relevant if is_int is TRUE. | |
1120 | */ | |
1121 | void do_interrupt(int intno, int is_int, int error_code, | |
14ce26e7 | 1122 | target_ulong next_eip, int is_hw) |
2c0262af | 1123 | { |
e19e89a5 FB |
1124 | #ifdef DEBUG_PCALL |
1125 | if (loglevel & (CPU_LOG_PCALL | CPU_LOG_INT)) { | |
1126 | if ((env->cr[0] & CR0_PE_MASK)) { | |
1127 | static int count; | |
14ce26e7 | 1128 | fprintf(logfile, "%6d: v=%02x e=%04x i=%d cpl=%d IP=%04x:" TARGET_FMT_lx " pc=" TARGET_FMT_lx " SP=%04x:" TARGET_FMT_lx, |
dc6f57fd FB |
1129 | count, intno, error_code, is_int, |
1130 | env->hflags & HF_CPL_MASK, | |
1131 | env->segs[R_CS].selector, EIP, | |
2ee73ac3 | 1132 | (int)env->segs[R_CS].base + EIP, |
8145122b FB |
1133 | env->segs[R_SS].selector, ESP); |
1134 | if (intno == 0x0e) { | |
14ce26e7 | 1135 | fprintf(logfile, " CR2=" TARGET_FMT_lx, env->cr[2]); |
8145122b | 1136 | } else { |
14ce26e7 | 1137 | fprintf(logfile, " EAX=" TARGET_FMT_lx, EAX); |
8145122b | 1138 | } |
e19e89a5 | 1139 | fprintf(logfile, "\n"); |
14ce26e7 | 1140 | #if 0 |
06c2f506 | 1141 | cpu_dump_state(env, logfile, fprintf, X86_DUMP_CCOP); |
e19e89a5 FB |
1142 | { |
1143 | int i; | |
1144 | uint8_t *ptr; | |
1145 | fprintf(logfile, " code="); | |
1146 | ptr = env->segs[R_CS].base + env->eip; | |
1147 | for(i = 0; i < 16; i++) { | |
1148 | fprintf(logfile, " %02x", ldub(ptr + i)); | |
dc6f57fd | 1149 | } |
e19e89a5 | 1150 | fprintf(logfile, "\n"); |
dc6f57fd | 1151 | } |
8e682019 | 1152 | #endif |
e19e89a5 | 1153 | count++; |
4136f33c | 1154 | } |
4136f33c FB |
1155 | } |
1156 | #endif | |
2c0262af | 1157 | if (env->cr[0] & CR0_PE_MASK) { |
14ce26e7 FB |
1158 | #if TARGET_X86_64 |
1159 | if (env->hflags & HF_LMA_MASK) { | |
1160 | do_interrupt64(intno, is_int, error_code, next_eip, is_hw); | |
1161 | } else | |
1162 | #endif | |
1163 | { | |
1164 | do_interrupt_protected(intno, is_int, error_code, next_eip, is_hw); | |
1165 | } | |
2c0262af FB |
1166 | } else { |
1167 | do_interrupt_real(intno, is_int, error_code, next_eip); | |
1168 | } | |
1169 | } | |
1170 | ||
1171 | /* | |
1172 | * Signal an interruption. It is executed in the main CPU loop. | |
1173 | * is_int is TRUE if coming from the int instruction. next_eip is the | |
1174 | * EIP value AFTER the interrupt instruction. It is only relevant if | |
1175 | * is_int is TRUE. | |
1176 | */ | |
1177 | void raise_interrupt(int intno, int is_int, int error_code, | |
a8ede8ba | 1178 | int next_eip_addend) |
2c0262af FB |
1179 | { |
1180 | env->exception_index = intno; | |
1181 | env->error_code = error_code; | |
1182 | env->exception_is_int = is_int; | |
a8ede8ba | 1183 | env->exception_next_eip = env->eip + next_eip_addend; |
2c0262af FB |
1184 | cpu_loop_exit(); |
1185 | } | |
1186 | ||
0d1a29f9 FB |
1187 | /* same as raise_exception_err, but do not restore global registers */ |
1188 | static void raise_exception_err_norestore(int exception_index, int error_code) | |
1189 | { | |
1190 | env->exception_index = exception_index; | |
1191 | env->error_code = error_code; | |
1192 | env->exception_is_int = 0; | |
1193 | env->exception_next_eip = 0; | |
1194 | longjmp(env->jmp_env, 1); | |
1195 | } | |
1196 | ||
2c0262af | 1197 | /* shortcuts to generate exceptions */ |
8145122b FB |
1198 | |
1199 | void (raise_exception_err)(int exception_index, int error_code) | |
2c0262af FB |
1200 | { |
1201 | raise_interrupt(exception_index, 0, error_code, 0); | |
1202 | } | |
1203 | ||
1204 | void raise_exception(int exception_index) | |
1205 | { | |
1206 | raise_interrupt(exception_index, 0, 0, 0); | |
1207 | } | |
1208 | ||
1209 | #ifdef BUGGY_GCC_DIV64 | |
1210 | /* gcc 2.95.4 on PowerPC does not seem to like using __udivdi3, so we | |
1211 | call it from another function */ | |
14ce26e7 | 1212 | uint32_t div32(uint32_t *q_ptr, uint64_t num, uint32_t den) |
2c0262af FB |
1213 | { |
1214 | *q_ptr = num / den; | |
1215 | return num % den; | |
1216 | } | |
1217 | ||
14ce26e7 | 1218 | int32_t idiv32(int32_t *q_ptr, int64_t num, int32_t den) |
2c0262af FB |
1219 | { |
1220 | *q_ptr = num / den; | |
1221 | return num % den; | |
1222 | } | |
1223 | #endif | |
1224 | ||
14ce26e7 | 1225 | void helper_divl_EAX_T0(void) |
2c0262af FB |
1226 | { |
1227 | unsigned int den, q, r; | |
1228 | uint64_t num; | |
1229 | ||
31313213 | 1230 | num = ((uint32_t)EAX) | ((uint64_t)((uint32_t)EDX) << 32); |
2c0262af FB |
1231 | den = T0; |
1232 | if (den == 0) { | |
2c0262af FB |
1233 | raise_exception(EXCP00_DIVZ); |
1234 | } | |
1235 | #ifdef BUGGY_GCC_DIV64 | |
14ce26e7 | 1236 | r = div32(&q, num, den); |
2c0262af FB |
1237 | #else |
1238 | q = (num / den); | |
1239 | r = (num % den); | |
1240 | #endif | |
14ce26e7 FB |
1241 | EAX = (uint32_t)q; |
1242 | EDX = (uint32_t)r; | |
2c0262af FB |
1243 | } |
1244 | ||
14ce26e7 | 1245 | void helper_idivl_EAX_T0(void) |
2c0262af FB |
1246 | { |
1247 | int den, q, r; | |
1248 | int64_t num; | |
1249 | ||
31313213 | 1250 | num = ((uint32_t)EAX) | ((uint64_t)((uint32_t)EDX) << 32); |
2c0262af FB |
1251 | den = T0; |
1252 | if (den == 0) { | |
2c0262af FB |
1253 | raise_exception(EXCP00_DIVZ); |
1254 | } | |
1255 | #ifdef BUGGY_GCC_DIV64 | |
14ce26e7 | 1256 | r = idiv32(&q, num, den); |
2c0262af FB |
1257 | #else |
1258 | q = (num / den); | |
1259 | r = (num % den); | |
1260 | #endif | |
14ce26e7 FB |
1261 | EAX = (uint32_t)q; |
1262 | EDX = (uint32_t)r; | |
2c0262af FB |
1263 | } |
1264 | ||
1265 | void helper_cmpxchg8b(void) | |
1266 | { | |
1267 | uint64_t d; | |
1268 | int eflags; | |
1269 | ||
1270 | eflags = cc_table[CC_OP].compute_all(); | |
14ce26e7 | 1271 | d = ldq(A0); |
2c0262af | 1272 | if (d == (((uint64_t)EDX << 32) | EAX)) { |
14ce26e7 | 1273 | stq(A0, ((uint64_t)ECX << 32) | EBX); |
2c0262af FB |
1274 | eflags |= CC_Z; |
1275 | } else { | |
1276 | EDX = d >> 32; | |
1277 | EAX = d; | |
1278 | eflags &= ~CC_Z; | |
1279 | } | |
1280 | CC_SRC = eflags; | |
1281 | } | |
1282 | ||
2c0262af FB |
1283 | void helper_cpuid(void) |
1284 | { | |
f419b321 FB |
1285 | uint32_t index; |
1286 | index = (uint32_t)EAX; | |
1287 | ||
1288 | /* test if maximum index reached */ | |
1289 | if (index & 0x80000000) { | |
1290 | if (index > env->cpuid_xlevel) | |
1291 | index = env->cpuid_level; | |
1292 | } else { | |
1293 | if (index > env->cpuid_level) | |
1294 | index = env->cpuid_level; | |
1295 | } | |
1296 | ||
1297 | switch(index) { | |
8e682019 | 1298 | case 0: |
f419b321 | 1299 | EAX = env->cpuid_level; |
14ce26e7 FB |
1300 | EBX = env->cpuid_vendor1; |
1301 | EDX = env->cpuid_vendor2; | |
1302 | ECX = env->cpuid_vendor3; | |
8e682019 FB |
1303 | break; |
1304 | case 1: | |
14ce26e7 FB |
1305 | EAX = env->cpuid_version; |
1306 | EBX = 0; | |
9df217a3 | 1307 | ECX = env->cpuid_ext_features; |
14ce26e7 | 1308 | EDX = env->cpuid_features; |
8e682019 | 1309 | break; |
f419b321 | 1310 | case 2: |
8e682019 FB |
1311 | /* cache info: needed for Pentium Pro compatibility */ |
1312 | EAX = 0x410601; | |
2c0262af FB |
1313 | EBX = 0; |
1314 | ECX = 0; | |
8e682019 FB |
1315 | EDX = 0; |
1316 | break; | |
14ce26e7 | 1317 | case 0x80000000: |
f419b321 | 1318 | EAX = env->cpuid_xlevel; |
14ce26e7 FB |
1319 | EBX = env->cpuid_vendor1; |
1320 | EDX = env->cpuid_vendor2; | |
1321 | ECX = env->cpuid_vendor3; | |
1322 | break; | |
1323 | case 0x80000001: | |
1324 | EAX = env->cpuid_features; | |
1325 | EBX = 0; | |
1326 | ECX = 0; | |
f419b321 FB |
1327 | EDX = env->cpuid_ext2_features; |
1328 | break; | |
1329 | case 0x80000002: | |
1330 | case 0x80000003: | |
1331 | case 0x80000004: | |
1332 | EAX = env->cpuid_model[(index - 0x80000002) * 4 + 0]; | |
1333 | EBX = env->cpuid_model[(index - 0x80000002) * 4 + 1]; | |
1334 | ECX = env->cpuid_model[(index - 0x80000002) * 4 + 2]; | |
1335 | EDX = env->cpuid_model[(index - 0x80000002) * 4 + 3]; | |
14ce26e7 FB |
1336 | break; |
1337 | case 0x80000008: | |
1338 | /* virtual & phys address size in low 2 bytes. */ | |
1339 | EAX = 0x00003028; | |
1340 | EBX = 0; | |
1341 | ECX = 0; | |
1342 | EDX = 0; | |
1343 | break; | |
f419b321 FB |
1344 | default: |
1345 | /* reserved values: zero */ | |
1346 | EAX = 0; | |
1347 | EBX = 0; | |
1348 | ECX = 0; | |
1349 | EDX = 0; | |
1350 | break; | |
2c0262af FB |
1351 | } |
1352 | } | |
1353 | ||
61a8c4ec FB |
1354 | void helper_enter_level(int level, int data32) |
1355 | { | |
14ce26e7 | 1356 | target_ulong ssp; |
61a8c4ec FB |
1357 | uint32_t esp_mask, esp, ebp; |
1358 | ||
1359 | esp_mask = get_sp_mask(env->segs[R_SS].flags); | |
1360 | ssp = env->segs[R_SS].base; | |
1361 | ebp = EBP; | |
1362 | esp = ESP; | |
1363 | if (data32) { | |
1364 | /* 32 bit */ | |
1365 | esp -= 4; | |
1366 | while (--level) { | |
1367 | esp -= 4; | |
1368 | ebp -= 4; | |
1369 | stl(ssp + (esp & esp_mask), ldl(ssp + (ebp & esp_mask))); | |
1370 | } | |
1371 | esp -= 4; | |
1372 | stl(ssp + (esp & esp_mask), T1); | |
1373 | } else { | |
1374 | /* 16 bit */ | |
1375 | esp -= 2; | |
1376 | while (--level) { | |
1377 | esp -= 2; | |
1378 | ebp -= 2; | |
1379 | stw(ssp + (esp & esp_mask), lduw(ssp + (ebp & esp_mask))); | |
1380 | } | |
1381 | esp -= 2; | |
1382 | stw(ssp + (esp & esp_mask), T1); | |
1383 | } | |
1384 | } | |
1385 | ||
2c0262af FB |
1386 | void helper_lldt_T0(void) |
1387 | { | |
1388 | int selector; | |
1389 | SegmentCache *dt; | |
1390 | uint32_t e1, e2; | |
14ce26e7 FB |
1391 | int index, entry_limit; |
1392 | target_ulong ptr; | |
2c0262af FB |
1393 | |
1394 | selector = T0 & 0xffff; | |
1395 | if ((selector & 0xfffc) == 0) { | |
1396 | /* XXX: NULL selector case: invalid LDT */ | |
14ce26e7 | 1397 | env->ldt.base = 0; |
2c0262af FB |
1398 | env->ldt.limit = 0; |
1399 | } else { | |
1400 | if (selector & 0x4) | |
1401 | raise_exception_err(EXCP0D_GPF, selector & 0xfffc); | |
1402 | dt = &env->gdt; | |
1403 | index = selector & ~7; | |
14ce26e7 FB |
1404 | #ifdef TARGET_X86_64 |
1405 | if (env->hflags & HF_LMA_MASK) | |
1406 | entry_limit = 15; | |
1407 | else | |
1408 | #endif | |
1409 | entry_limit = 7; | |
1410 | if ((index + entry_limit) > dt->limit) | |
2c0262af FB |
1411 | raise_exception_err(EXCP0D_GPF, selector & 0xfffc); |
1412 | ptr = dt->base + index; | |
61382a50 FB |
1413 | e1 = ldl_kernel(ptr); |
1414 | e2 = ldl_kernel(ptr + 4); | |
2c0262af FB |
1415 | if ((e2 & DESC_S_MASK) || ((e2 >> DESC_TYPE_SHIFT) & 0xf) != 2) |
1416 | raise_exception_err(EXCP0D_GPF, selector & 0xfffc); | |
1417 | if (!(e2 & DESC_P_MASK)) | |
1418 | raise_exception_err(EXCP0B_NOSEG, selector & 0xfffc); | |
14ce26e7 FB |
1419 | #ifdef TARGET_X86_64 |
1420 | if (env->hflags & HF_LMA_MASK) { | |
1421 | uint32_t e3; | |
1422 | e3 = ldl_kernel(ptr + 8); | |
1423 | load_seg_cache_raw_dt(&env->ldt, e1, e2); | |
1424 | env->ldt.base |= (target_ulong)e3 << 32; | |
1425 | } else | |
1426 | #endif | |
1427 | { | |
1428 | load_seg_cache_raw_dt(&env->ldt, e1, e2); | |
1429 | } | |
2c0262af FB |
1430 | } |
1431 | env->ldt.selector = selector; | |
1432 | } | |
1433 | ||
1434 | void helper_ltr_T0(void) | |
1435 | { | |
1436 | int selector; | |
1437 | SegmentCache *dt; | |
1438 | uint32_t e1, e2; | |
14ce26e7 FB |
1439 | int index, type, entry_limit; |
1440 | target_ulong ptr; | |
2c0262af FB |
1441 | |
1442 | selector = T0 & 0xffff; | |
1443 | if ((selector & 0xfffc) == 0) { | |
14ce26e7 FB |
1444 | /* NULL selector case: invalid TR */ |
1445 | env->tr.base = 0; | |
2c0262af FB |
1446 | env->tr.limit = 0; |
1447 | env->tr.flags = 0; | |
1448 | } else { | |
1449 | if (selector & 0x4) | |
1450 | raise_exception_err(EXCP0D_GPF, selector & 0xfffc); | |
1451 | dt = &env->gdt; | |
1452 | index = selector & ~7; | |
14ce26e7 FB |
1453 | #ifdef TARGET_X86_64 |
1454 | if (env->hflags & HF_LMA_MASK) | |
1455 | entry_limit = 15; | |
1456 | else | |
1457 | #endif | |
1458 | entry_limit = 7; | |
1459 | if ((index + entry_limit) > dt->limit) | |
2c0262af FB |
1460 | raise_exception_err(EXCP0D_GPF, selector & 0xfffc); |
1461 | ptr = dt->base + index; | |
61382a50 FB |
1462 | e1 = ldl_kernel(ptr); |
1463 | e2 = ldl_kernel(ptr + 4); | |
2c0262af FB |
1464 | type = (e2 >> DESC_TYPE_SHIFT) & 0xf; |
1465 | if ((e2 & DESC_S_MASK) || | |
7e84c249 | 1466 | (type != 1 && type != 9)) |
2c0262af FB |
1467 | raise_exception_err(EXCP0D_GPF, selector & 0xfffc); |
1468 | if (!(e2 & DESC_P_MASK)) | |
1469 | raise_exception_err(EXCP0B_NOSEG, selector & 0xfffc); | |
14ce26e7 FB |
1470 | #ifdef TARGET_X86_64 |
1471 | if (env->hflags & HF_LMA_MASK) { | |
1472 | uint32_t e3; | |
1473 | e3 = ldl_kernel(ptr + 8); | |
1474 | load_seg_cache_raw_dt(&env->tr, e1, e2); | |
1475 | env->tr.base |= (target_ulong)e3 << 32; | |
1476 | } else | |
1477 | #endif | |
1478 | { | |
1479 | load_seg_cache_raw_dt(&env->tr, e1, e2); | |
1480 | } | |
8e682019 | 1481 | e2 |= DESC_TSS_BUSY_MASK; |
61382a50 | 1482 | stl_kernel(ptr + 4, e2); |
2c0262af FB |
1483 | } |
1484 | env->tr.selector = selector; | |
1485 | } | |
1486 | ||
3ab493de | 1487 | /* only works if protected mode and not VM86. seg_reg must be != R_CS */ |
8e682019 | 1488 | void load_seg(int seg_reg, int selector) |
2c0262af FB |
1489 | { |
1490 | uint32_t e1, e2; | |
3ab493de FB |
1491 | int cpl, dpl, rpl; |
1492 | SegmentCache *dt; | |
1493 | int index; | |
14ce26e7 | 1494 | target_ulong ptr; |
3ab493de | 1495 | |
8e682019 | 1496 | selector &= 0xffff; |
b359d4e7 | 1497 | cpl = env->hflags & HF_CPL_MASK; |
2c0262af FB |
1498 | if ((selector & 0xfffc) == 0) { |
1499 | /* null selector case */ | |
4d6b6c0a FB |
1500 | if (seg_reg == R_SS |
1501 | #ifdef TARGET_X86_64 | |
b359d4e7 | 1502 | && (!(env->hflags & HF_CS64_MASK) || cpl == 3) |
4d6b6c0a FB |
1503 | #endif |
1504 | ) | |
2c0262af | 1505 | raise_exception_err(EXCP0D_GPF, 0); |
14ce26e7 | 1506 | cpu_x86_load_seg_cache(env, seg_reg, selector, 0, 0, 0); |
2c0262af | 1507 | } else { |
3ab493de FB |
1508 | |
1509 | if (selector & 0x4) | |
1510 | dt = &env->ldt; | |
1511 | else | |
1512 | dt = &env->gdt; | |
1513 | index = selector & ~7; | |
8e682019 | 1514 | if ((index + 7) > dt->limit) |
2c0262af | 1515 | raise_exception_err(EXCP0D_GPF, selector & 0xfffc); |
3ab493de FB |
1516 | ptr = dt->base + index; |
1517 | e1 = ldl_kernel(ptr); | |
1518 | e2 = ldl_kernel(ptr + 4); | |
14ce26e7 | 1519 | |
8e682019 | 1520 | if (!(e2 & DESC_S_MASK)) |
2c0262af | 1521 | raise_exception_err(EXCP0D_GPF, selector & 0xfffc); |
3ab493de FB |
1522 | rpl = selector & 3; |
1523 | dpl = (e2 >> DESC_DPL_SHIFT) & 3; | |
2c0262af | 1524 | if (seg_reg == R_SS) { |
3ab493de | 1525 | /* must be writable segment */ |
8e682019 | 1526 | if ((e2 & DESC_CS_MASK) || !(e2 & DESC_W_MASK)) |
2c0262af | 1527 | raise_exception_err(EXCP0D_GPF, selector & 0xfffc); |
8e682019 | 1528 | if (rpl != cpl || dpl != cpl) |
3ab493de | 1529 | raise_exception_err(EXCP0D_GPF, selector & 0xfffc); |
2c0262af | 1530 | } else { |
3ab493de | 1531 | /* must be readable segment */ |
8e682019 | 1532 | if ((e2 & (DESC_CS_MASK | DESC_R_MASK)) == DESC_CS_MASK) |
2c0262af | 1533 | raise_exception_err(EXCP0D_GPF, selector & 0xfffc); |
3ab493de FB |
1534 | |
1535 | if (!(e2 & DESC_CS_MASK) || !(e2 & DESC_C_MASK)) { | |
1536 | /* if not conforming code, test rights */ | |
8e682019 | 1537 | if (dpl < cpl || dpl < rpl) |
3ab493de | 1538 | raise_exception_err(EXCP0D_GPF, selector & 0xfffc); |
3ab493de | 1539 | } |
2c0262af FB |
1540 | } |
1541 | ||
1542 | if (!(e2 & DESC_P_MASK)) { | |
2c0262af FB |
1543 | if (seg_reg == R_SS) |
1544 | raise_exception_err(EXCP0C_STACK, selector & 0xfffc); | |
1545 | else | |
1546 | raise_exception_err(EXCP0B_NOSEG, selector & 0xfffc); | |
1547 | } | |
3ab493de FB |
1548 | |
1549 | /* set the access bit if not already set */ | |
1550 | if (!(e2 & DESC_A_MASK)) { | |
1551 | e2 |= DESC_A_MASK; | |
1552 | stl_kernel(ptr + 4, e2); | |
1553 | } | |
1554 | ||
2c0262af FB |
1555 | cpu_x86_load_seg_cache(env, seg_reg, selector, |
1556 | get_seg_base(e1, e2), | |
1557 | get_seg_limit(e1, e2), | |
1558 | e2); | |
1559 | #if 0 | |
1560 | fprintf(logfile, "load_seg: sel=0x%04x base=0x%08lx limit=0x%08lx flags=%08x\n", | |
1561 | selector, (unsigned long)sc->base, sc->limit, sc->flags); | |
1562 | #endif | |
1563 | } | |
1564 | } | |
1565 | ||
1566 | /* protected mode jump */ | |
f419b321 | 1567 | void helper_ljmp_protected_T0_T1(int next_eip_addend) |
2c0262af | 1568 | { |
14ce26e7 | 1569 | int new_cs, gate_cs, type; |
2c0262af | 1570 | uint32_t e1, e2, cpl, dpl, rpl, limit; |
f419b321 | 1571 | target_ulong new_eip, next_eip; |
14ce26e7 | 1572 | |
2c0262af FB |
1573 | new_cs = T0; |
1574 | new_eip = T1; | |
1575 | if ((new_cs & 0xfffc) == 0) | |
1576 | raise_exception_err(EXCP0D_GPF, 0); | |
1577 | if (load_segment(&e1, &e2, new_cs) != 0) | |
1578 | raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc); | |
1579 | cpl = env->hflags & HF_CPL_MASK; | |
1580 | if (e2 & DESC_S_MASK) { | |
1581 | if (!(e2 & DESC_CS_MASK)) | |
1582 | raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc); | |
1583 | dpl = (e2 >> DESC_DPL_SHIFT) & 3; | |
7e84c249 | 1584 | if (e2 & DESC_C_MASK) { |
2c0262af FB |
1585 | /* conforming code segment */ |
1586 | if (dpl > cpl) | |
1587 | raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc); | |
1588 | } else { | |
1589 | /* non conforming code segment */ | |
1590 | rpl = new_cs & 3; | |
1591 | if (rpl > cpl) | |
1592 | raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc); | |
1593 | if (dpl != cpl) | |
1594 | raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc); | |
1595 | } | |
1596 | if (!(e2 & DESC_P_MASK)) | |
1597 | raise_exception_err(EXCP0B_NOSEG, new_cs & 0xfffc); | |
1598 | limit = get_seg_limit(e1, e2); | |
ca954f6d FB |
1599 | if (new_eip > limit && |
1600 | !(env->hflags & HF_LMA_MASK) && !(e2 & DESC_L_MASK)) | |
2c0262af FB |
1601 | raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc); |
1602 | cpu_x86_load_seg_cache(env, R_CS, (new_cs & 0xfffc) | cpl, | |
1603 | get_seg_base(e1, e2), limit, e2); | |
1604 | EIP = new_eip; | |
1605 | } else { | |
7e84c249 FB |
1606 | /* jump to call or task gate */ |
1607 | dpl = (e2 >> DESC_DPL_SHIFT) & 3; | |
1608 | rpl = new_cs & 3; | |
1609 | cpl = env->hflags & HF_CPL_MASK; | |
1610 | type = (e2 >> DESC_TYPE_SHIFT) & 0xf; | |
1611 | switch(type) { | |
1612 | case 1: /* 286 TSS */ | |
1613 | case 9: /* 386 TSS */ | |
1614 | case 5: /* task gate */ | |
1615 | if (dpl < cpl || dpl < rpl) | |
1616 | raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc); | |
f419b321 | 1617 | next_eip = env->eip + next_eip_addend; |
08cea4ee | 1618 | switch_tss(new_cs, e1, e2, SWITCH_TSS_JMP, next_eip); |
7e84c249 FB |
1619 | break; |
1620 | case 4: /* 286 call gate */ | |
1621 | case 12: /* 386 call gate */ | |
1622 | if ((dpl < cpl) || (dpl < rpl)) | |
1623 | raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc); | |
1624 | if (!(e2 & DESC_P_MASK)) | |
1625 | raise_exception_err(EXCP0B_NOSEG, new_cs & 0xfffc); | |
1626 | gate_cs = e1 >> 16; | |
516633dc FB |
1627 | new_eip = (e1 & 0xffff); |
1628 | if (type == 12) | |
1629 | new_eip |= (e2 & 0xffff0000); | |
7e84c249 FB |
1630 | if (load_segment(&e1, &e2, gate_cs) != 0) |
1631 | raise_exception_err(EXCP0D_GPF, gate_cs & 0xfffc); | |
1632 | dpl = (e2 >> DESC_DPL_SHIFT) & 3; | |
1633 | /* must be code segment */ | |
1634 | if (((e2 & (DESC_S_MASK | DESC_CS_MASK)) != | |
1635 | (DESC_S_MASK | DESC_CS_MASK))) | |
1636 | raise_exception_err(EXCP0D_GPF, gate_cs & 0xfffc); | |
14ce26e7 | 1637 | if (((e2 & DESC_C_MASK) && (dpl > cpl)) || |
7e84c249 FB |
1638 | (!(e2 & DESC_C_MASK) && (dpl != cpl))) |
1639 | raise_exception_err(EXCP0D_GPF, gate_cs & 0xfffc); | |
1640 | if (!(e2 & DESC_P_MASK)) | |
1641 | raise_exception_err(EXCP0D_GPF, gate_cs & 0xfffc); | |
7e84c249 FB |
1642 | limit = get_seg_limit(e1, e2); |
1643 | if (new_eip > limit) | |
1644 | raise_exception_err(EXCP0D_GPF, 0); | |
1645 | cpu_x86_load_seg_cache(env, R_CS, (gate_cs & 0xfffc) | cpl, | |
1646 | get_seg_base(e1, e2), limit, e2); | |
1647 | EIP = new_eip; | |
1648 | break; | |
1649 | default: | |
1650 | raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc); | |
1651 | break; | |
1652 | } | |
2c0262af FB |
1653 | } |
1654 | } | |
1655 | ||
1656 | /* real mode call */ | |
1657 | void helper_lcall_real_T0_T1(int shift, int next_eip) | |
1658 | { | |
1659 | int new_cs, new_eip; | |
1660 | uint32_t esp, esp_mask; | |
14ce26e7 | 1661 | target_ulong ssp; |
2c0262af FB |
1662 | |
1663 | new_cs = T0; | |
1664 | new_eip = T1; | |
1665 | esp = ESP; | |
891b38e4 | 1666 | esp_mask = get_sp_mask(env->segs[R_SS].flags); |
2c0262af FB |
1667 | ssp = env->segs[R_SS].base; |
1668 | if (shift) { | |
891b38e4 FB |
1669 | PUSHL(ssp, esp, esp_mask, env->segs[R_CS].selector); |
1670 | PUSHL(ssp, esp, esp_mask, next_eip); | |
2c0262af | 1671 | } else { |
891b38e4 FB |
1672 | PUSHW(ssp, esp, esp_mask, env->segs[R_CS].selector); |
1673 | PUSHW(ssp, esp, esp_mask, next_eip); | |
2c0262af FB |
1674 | } |
1675 | ||
891b38e4 | 1676 | ESP = (ESP & ~esp_mask) | (esp & esp_mask); |
2c0262af FB |
1677 | env->eip = new_eip; |
1678 | env->segs[R_CS].selector = new_cs; | |
14ce26e7 | 1679 | env->segs[R_CS].base = (new_cs << 4); |
2c0262af FB |
1680 | } |
1681 | ||
1682 | /* protected mode call */ | |
f419b321 | 1683 | void helper_lcall_protected_T0_T1(int shift, int next_eip_addend) |
2c0262af | 1684 | { |
891b38e4 | 1685 | int new_cs, new_eip, new_stack, i; |
2c0262af | 1686 | uint32_t e1, e2, cpl, dpl, rpl, selector, offset, param_count; |
891b38e4 FB |
1687 | uint32_t ss, ss_e1, ss_e2, sp, type, ss_dpl, sp_mask; |
1688 | uint32_t val, limit, old_sp_mask; | |
f419b321 | 1689 | target_ulong ssp, old_ssp, next_eip; |
2c0262af FB |
1690 | |
1691 | new_cs = T0; | |
1692 | new_eip = T1; | |
f419b321 | 1693 | next_eip = env->eip + next_eip_addend; |
f3f2d9be | 1694 | #ifdef DEBUG_PCALL |
e19e89a5 FB |
1695 | if (loglevel & CPU_LOG_PCALL) { |
1696 | fprintf(logfile, "lcall %04x:%08x s=%d\n", | |
1697 | new_cs, new_eip, shift); | |
7fe48483 | 1698 | cpu_dump_state(env, logfile, fprintf, X86_DUMP_CCOP); |
f3f2d9be FB |
1699 | } |
1700 | #endif | |
2c0262af FB |
1701 | if ((new_cs & 0xfffc) == 0) |
1702 | raise_exception_err(EXCP0D_GPF, 0); | |
1703 | if (load_segment(&e1, &e2, new_cs) != 0) | |
1704 | raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc); | |
1705 | cpl = env->hflags & HF_CPL_MASK; | |
f3f2d9be | 1706 | #ifdef DEBUG_PCALL |
e19e89a5 | 1707 | if (loglevel & CPU_LOG_PCALL) { |
f3f2d9be FB |
1708 | fprintf(logfile, "desc=%08x:%08x\n", e1, e2); |
1709 | } | |
1710 | #endif | |
2c0262af FB |
1711 | if (e2 & DESC_S_MASK) { |
1712 | if (!(e2 & DESC_CS_MASK)) | |
1713 | raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc); | |
1714 | dpl = (e2 >> DESC_DPL_SHIFT) & 3; | |
7e84c249 | 1715 | if (e2 & DESC_C_MASK) { |
2c0262af FB |
1716 | /* conforming code segment */ |
1717 | if (dpl > cpl) | |
1718 | raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc); | |
1719 | } else { | |
1720 | /* non conforming code segment */ | |
1721 | rpl = new_cs & 3; | |
1722 | if (rpl > cpl) | |
1723 | raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc); | |
1724 | if (dpl != cpl) | |
1725 | raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc); | |
1726 | } | |
1727 | if (!(e2 & DESC_P_MASK)) | |
1728 | raise_exception_err(EXCP0B_NOSEG, new_cs & 0xfffc); | |
1729 | ||
f419b321 FB |
1730 | #ifdef TARGET_X86_64 |
1731 | /* XXX: check 16/32 bit cases in long mode */ | |
1732 | if (shift == 2) { | |
1733 | target_ulong rsp; | |
1734 | /* 64 bit case */ | |
1735 | rsp = ESP; | |
1736 | PUSHQ(rsp, env->segs[R_CS].selector); | |
1737 | PUSHQ(rsp, next_eip); | |
1738 | /* from this point, not restartable */ | |
1739 | ESP = rsp; | |
1740 | cpu_x86_load_seg_cache(env, R_CS, (new_cs & 0xfffc) | cpl, | |
1741 | get_seg_base(e1, e2), | |
1742 | get_seg_limit(e1, e2), e2); | |
1743 | EIP = new_eip; | |
1744 | } else | |
1745 | #endif | |
1746 | { | |
1747 | sp = ESP; | |
1748 | sp_mask = get_sp_mask(env->segs[R_SS].flags); | |
1749 | ssp = env->segs[R_SS].base; | |
1750 | if (shift) { | |
1751 | PUSHL(ssp, sp, sp_mask, env->segs[R_CS].selector); | |
1752 | PUSHL(ssp, sp, sp_mask, next_eip); | |
1753 | } else { | |
1754 | PUSHW(ssp, sp, sp_mask, env->segs[R_CS].selector); | |
1755 | PUSHW(ssp, sp, sp_mask, next_eip); | |
1756 | } | |
1757 | ||
1758 | limit = get_seg_limit(e1, e2); | |
1759 | if (new_eip > limit) | |
1760 | raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc); | |
1761 | /* from this point, not restartable */ | |
1762 | ESP = (ESP & ~sp_mask) | (sp & sp_mask); | |
1763 | cpu_x86_load_seg_cache(env, R_CS, (new_cs & 0xfffc) | cpl, | |
1764 | get_seg_base(e1, e2), limit, e2); | |
1765 | EIP = new_eip; | |
2c0262af | 1766 | } |
2c0262af FB |
1767 | } else { |
1768 | /* check gate type */ | |
1769 | type = (e2 >> DESC_TYPE_SHIFT) & 0x1f; | |
7e84c249 FB |
1770 | dpl = (e2 >> DESC_DPL_SHIFT) & 3; |
1771 | rpl = new_cs & 3; | |
2c0262af FB |
1772 | switch(type) { |
1773 | case 1: /* available 286 TSS */ | |
1774 | case 9: /* available 386 TSS */ | |
1775 | case 5: /* task gate */ | |
7e84c249 FB |
1776 | if (dpl < cpl || dpl < rpl) |
1777 | raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc); | |
883da8e2 | 1778 | switch_tss(new_cs, e1, e2, SWITCH_TSS_CALL, next_eip); |
8145122b | 1779 | return; |
2c0262af FB |
1780 | case 4: /* 286 call gate */ |
1781 | case 12: /* 386 call gate */ | |
1782 | break; | |
1783 | default: | |
1784 | raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc); | |
1785 | break; | |
1786 | } | |
1787 | shift = type >> 3; | |
1788 | ||
2c0262af FB |
1789 | if (dpl < cpl || dpl < rpl) |
1790 | raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc); | |
1791 | /* check valid bit */ | |
1792 | if (!(e2 & DESC_P_MASK)) | |
1793 | raise_exception_err(EXCP0B_NOSEG, new_cs & 0xfffc); | |
1794 | selector = e1 >> 16; | |
1795 | offset = (e2 & 0xffff0000) | (e1 & 0x0000ffff); | |
f3f2d9be | 1796 | param_count = e2 & 0x1f; |
2c0262af FB |
1797 | if ((selector & 0xfffc) == 0) |
1798 | raise_exception_err(EXCP0D_GPF, 0); | |
1799 | ||
1800 | if (load_segment(&e1, &e2, selector) != 0) | |
1801 | raise_exception_err(EXCP0D_GPF, selector & 0xfffc); | |
1802 | if (!(e2 & DESC_S_MASK) || !(e2 & (DESC_CS_MASK))) | |
1803 | raise_exception_err(EXCP0D_GPF, selector & 0xfffc); | |
1804 | dpl = (e2 >> DESC_DPL_SHIFT) & 3; | |
1805 | if (dpl > cpl) | |
1806 | raise_exception_err(EXCP0D_GPF, selector & 0xfffc); | |
1807 | if (!(e2 & DESC_P_MASK)) | |
1808 | raise_exception_err(EXCP0B_NOSEG, selector & 0xfffc); | |
1809 | ||
1810 | if (!(e2 & DESC_C_MASK) && dpl < cpl) { | |
1811 | /* to inner priviledge */ | |
1812 | get_ss_esp_from_tss(&ss, &sp, dpl); | |
f3f2d9be | 1813 | #ifdef DEBUG_PCALL |
e19e89a5 | 1814 | if (loglevel & CPU_LOG_PCALL) |
14ce26e7 | 1815 | fprintf(logfile, "new ss:esp=%04x:%08x param_count=%d ESP=" TARGET_FMT_lx "\n", |
f3f2d9be FB |
1816 | ss, sp, param_count, ESP); |
1817 | #endif | |
2c0262af FB |
1818 | if ((ss & 0xfffc) == 0) |
1819 | raise_exception_err(EXCP0A_TSS, ss & 0xfffc); | |
1820 | if ((ss & 3) != dpl) | |
1821 | raise_exception_err(EXCP0A_TSS, ss & 0xfffc); | |
1822 | if (load_segment(&ss_e1, &ss_e2, ss) != 0) | |
1823 | raise_exception_err(EXCP0A_TSS, ss & 0xfffc); | |
1824 | ss_dpl = (ss_e2 >> DESC_DPL_SHIFT) & 3; | |
1825 | if (ss_dpl != dpl) | |
1826 | raise_exception_err(EXCP0A_TSS, ss & 0xfffc); | |
1827 | if (!(ss_e2 & DESC_S_MASK) || | |
1828 | (ss_e2 & DESC_CS_MASK) || | |
1829 | !(ss_e2 & DESC_W_MASK)) | |
1830 | raise_exception_err(EXCP0A_TSS, ss & 0xfffc); | |
1831 | if (!(ss_e2 & DESC_P_MASK)) | |
1832 | raise_exception_err(EXCP0A_TSS, ss & 0xfffc); | |
1833 | ||
891b38e4 | 1834 | // push_size = ((param_count * 2) + 8) << shift; |
2c0262af | 1835 | |
891b38e4 FB |
1836 | old_sp_mask = get_sp_mask(env->segs[R_SS].flags); |
1837 | old_ssp = env->segs[R_SS].base; | |
2c0262af | 1838 | |
891b38e4 FB |
1839 | sp_mask = get_sp_mask(ss_e2); |
1840 | ssp = get_seg_base(ss_e1, ss_e2); | |
2c0262af | 1841 | if (shift) { |
891b38e4 FB |
1842 | PUSHL(ssp, sp, sp_mask, env->segs[R_SS].selector); |
1843 | PUSHL(ssp, sp, sp_mask, ESP); | |
1844 | for(i = param_count - 1; i >= 0; i--) { | |
1845 | val = ldl_kernel(old_ssp + ((ESP + i * 4) & old_sp_mask)); | |
1846 | PUSHL(ssp, sp, sp_mask, val); | |
2c0262af FB |
1847 | } |
1848 | } else { | |
891b38e4 FB |
1849 | PUSHW(ssp, sp, sp_mask, env->segs[R_SS].selector); |
1850 | PUSHW(ssp, sp, sp_mask, ESP); | |
1851 | for(i = param_count - 1; i >= 0; i--) { | |
1852 | val = lduw_kernel(old_ssp + ((ESP + i * 2) & old_sp_mask)); | |
1853 | PUSHW(ssp, sp, sp_mask, val); | |
2c0262af FB |
1854 | } |
1855 | } | |
891b38e4 | 1856 | new_stack = 1; |
2c0262af FB |
1857 | } else { |
1858 | /* to same priviledge */ | |
891b38e4 FB |
1859 | sp = ESP; |
1860 | sp_mask = get_sp_mask(env->segs[R_SS].flags); | |
1861 | ssp = env->segs[R_SS].base; | |
1862 | // push_size = (4 << shift); | |
1863 | new_stack = 0; | |
2c0262af FB |
1864 | } |
1865 | ||
1866 | if (shift) { | |
891b38e4 FB |
1867 | PUSHL(ssp, sp, sp_mask, env->segs[R_CS].selector); |
1868 | PUSHL(ssp, sp, sp_mask, next_eip); | |
2c0262af | 1869 | } else { |
891b38e4 FB |
1870 | PUSHW(ssp, sp, sp_mask, env->segs[R_CS].selector); |
1871 | PUSHW(ssp, sp, sp_mask, next_eip); | |
1872 | } | |
1873 | ||
1874 | /* from this point, not restartable */ | |
1875 | ||
1876 | if (new_stack) { | |
1877 | ss = (ss & ~3) | dpl; | |
1878 | cpu_x86_load_seg_cache(env, R_SS, ss, | |
1879 | ssp, | |
1880 | get_seg_limit(ss_e1, ss_e2), | |
1881 | ss_e2); | |
2c0262af FB |
1882 | } |
1883 | ||
2c0262af FB |
1884 | selector = (selector & ~3) | dpl; |
1885 | cpu_x86_load_seg_cache(env, R_CS, selector, | |
1886 | get_seg_base(e1, e2), | |
1887 | get_seg_limit(e1, e2), | |
1888 | e2); | |
1889 | cpu_x86_set_cpl(env, dpl); | |
891b38e4 | 1890 | ESP = (ESP & ~sp_mask) | (sp & sp_mask); |
2c0262af FB |
1891 | EIP = offset; |
1892 | } | |
9df217a3 FB |
1893 | #ifdef USE_KQEMU |
1894 | if (kqemu_is_ok(env)) { | |
1895 | env->exception_index = -1; | |
1896 | cpu_loop_exit(); | |
1897 | } | |
1898 | #endif | |
2c0262af FB |
1899 | } |
1900 | ||
7e84c249 | 1901 | /* real and vm86 mode iret */ |
2c0262af FB |
1902 | void helper_iret_real(int shift) |
1903 | { | |
891b38e4 | 1904 | uint32_t sp, new_cs, new_eip, new_eflags, sp_mask; |
14ce26e7 | 1905 | target_ulong ssp; |
2c0262af | 1906 | int eflags_mask; |
7e84c249 | 1907 | |
891b38e4 FB |
1908 | sp_mask = 0xffff; /* XXXX: use SS segment size ? */ |
1909 | sp = ESP; | |
1910 | ssp = env->segs[R_SS].base; | |
2c0262af FB |
1911 | if (shift == 1) { |
1912 | /* 32 bits */ | |
891b38e4 FB |
1913 | POPL(ssp, sp, sp_mask, new_eip); |
1914 | POPL(ssp, sp, sp_mask, new_cs); | |
1915 | new_cs &= 0xffff; | |
1916 | POPL(ssp, sp, sp_mask, new_eflags); | |
2c0262af FB |
1917 | } else { |
1918 | /* 16 bits */ | |
891b38e4 FB |
1919 | POPW(ssp, sp, sp_mask, new_eip); |
1920 | POPW(ssp, sp, sp_mask, new_cs); | |
1921 | POPW(ssp, sp, sp_mask, new_eflags); | |
2c0262af | 1922 | } |
4136f33c | 1923 | ESP = (ESP & ~sp_mask) | (sp & sp_mask); |
2c0262af FB |
1924 | load_seg_vm(R_CS, new_cs); |
1925 | env->eip = new_eip; | |
7e84c249 | 1926 | if (env->eflags & VM_MASK) |
8145122b | 1927 | eflags_mask = TF_MASK | AC_MASK | ID_MASK | IF_MASK | RF_MASK | NT_MASK; |
7e84c249 | 1928 | else |
8145122b | 1929 | eflags_mask = TF_MASK | AC_MASK | ID_MASK | IF_MASK | IOPL_MASK | RF_MASK | NT_MASK; |
2c0262af FB |
1930 | if (shift == 0) |
1931 | eflags_mask &= 0xffff; | |
1932 | load_eflags(new_eflags, eflags_mask); | |
1933 | } | |
1934 | ||
8e682019 FB |
1935 | static inline void validate_seg(int seg_reg, int cpl) |
1936 | { | |
1937 | int dpl; | |
1938 | uint32_t e2; | |
1939 | ||
1940 | e2 = env->segs[seg_reg].flags; | |
1941 | dpl = (e2 >> DESC_DPL_SHIFT) & 3; | |
1942 | if (!(e2 & DESC_CS_MASK) || !(e2 & DESC_C_MASK)) { | |
1943 | /* data or non conforming code segment */ | |
1944 | if (dpl < cpl) { | |
14ce26e7 | 1945 | cpu_x86_load_seg_cache(env, seg_reg, 0, 0, 0, 0); |
8e682019 FB |
1946 | } |
1947 | } | |
1948 | } | |
1949 | ||
2c0262af FB |
1950 | /* protected mode iret */ |
1951 | static inline void helper_ret_protected(int shift, int is_iret, int addend) | |
1952 | { | |
14ce26e7 | 1953 | uint32_t new_cs, new_eflags, new_ss; |
2c0262af FB |
1954 | uint32_t new_es, new_ds, new_fs, new_gs; |
1955 | uint32_t e1, e2, ss_e1, ss_e2; | |
4136f33c | 1956 | int cpl, dpl, rpl, eflags_mask, iopl; |
14ce26e7 | 1957 | target_ulong ssp, sp, new_eip, new_esp, sp_mask; |
2c0262af | 1958 | |
14ce26e7 FB |
1959 | #ifdef TARGET_X86_64 |
1960 | if (shift == 2) | |
1961 | sp_mask = -1; | |
1962 | else | |
1963 | #endif | |
1964 | sp_mask = get_sp_mask(env->segs[R_SS].flags); | |
2c0262af | 1965 | sp = ESP; |
891b38e4 | 1966 | ssp = env->segs[R_SS].base; |
354ff226 | 1967 | new_eflags = 0; /* avoid warning */ |
14ce26e7 FB |
1968 | #ifdef TARGET_X86_64 |
1969 | if (shift == 2) { | |
1970 | POPQ(sp, new_eip); | |
1971 | POPQ(sp, new_cs); | |
1972 | new_cs &= 0xffff; | |
1973 | if (is_iret) { | |
1974 | POPQ(sp, new_eflags); | |
1975 | } | |
1976 | } else | |
1977 | #endif | |
2c0262af FB |
1978 | if (shift == 1) { |
1979 | /* 32 bits */ | |
891b38e4 FB |
1980 | POPL(ssp, sp, sp_mask, new_eip); |
1981 | POPL(ssp, sp, sp_mask, new_cs); | |
1982 | new_cs &= 0xffff; | |
1983 | if (is_iret) { | |
1984 | POPL(ssp, sp, sp_mask, new_eflags); | |
1985 | if (new_eflags & VM_MASK) | |
1986 | goto return_to_vm86; | |
1987 | } | |
2c0262af FB |
1988 | } else { |
1989 | /* 16 bits */ | |
891b38e4 FB |
1990 | POPW(ssp, sp, sp_mask, new_eip); |
1991 | POPW(ssp, sp, sp_mask, new_cs); | |
2c0262af | 1992 | if (is_iret) |
891b38e4 | 1993 | POPW(ssp, sp, sp_mask, new_eflags); |
2c0262af | 1994 | } |
891b38e4 | 1995 | #ifdef DEBUG_PCALL |
e19e89a5 | 1996 | if (loglevel & CPU_LOG_PCALL) { |
14ce26e7 | 1997 | fprintf(logfile, "lret new %04x:" TARGET_FMT_lx " s=%d addend=0x%x\n", |
e19e89a5 | 1998 | new_cs, new_eip, shift, addend); |
7fe48483 | 1999 | cpu_dump_state(env, logfile, fprintf, X86_DUMP_CCOP); |
891b38e4 FB |
2000 | } |
2001 | #endif | |
2c0262af FB |
2002 | if ((new_cs & 0xfffc) == 0) |
2003 | raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc); | |
2004 | if (load_segment(&e1, &e2, new_cs) != 0) | |
2005 | raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc); | |
2006 | if (!(e2 & DESC_S_MASK) || | |
2007 | !(e2 & DESC_CS_MASK)) | |
2008 | raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc); | |
2009 | cpl = env->hflags & HF_CPL_MASK; | |
2010 | rpl = new_cs & 3; | |
2011 | if (rpl < cpl) | |
2012 | raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc); | |
2013 | dpl = (e2 >> DESC_DPL_SHIFT) & 3; | |
7e84c249 | 2014 | if (e2 & DESC_C_MASK) { |
2c0262af FB |
2015 | if (dpl > rpl) |
2016 | raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc); | |
2017 | } else { | |
2018 | if (dpl != rpl) | |
2019 | raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc); | |
2020 | } | |
2021 | if (!(e2 & DESC_P_MASK)) | |
2022 | raise_exception_err(EXCP0B_NOSEG, new_cs & 0xfffc); | |
2023 | ||
891b38e4 | 2024 | sp += addend; |
ca954f6d FB |
2025 | if (rpl == cpl && (!(env->hflags & HF_CS64_MASK) || |
2026 | ((env->hflags & HF_CS64_MASK) && !is_iret))) { | |
2c0262af FB |
2027 | /* return to same priledge level */ |
2028 | cpu_x86_load_seg_cache(env, R_CS, new_cs, | |
2029 | get_seg_base(e1, e2), | |
2030 | get_seg_limit(e1, e2), | |
2031 | e2); | |
2c0262af FB |
2032 | } else { |
2033 | /* return to different priviledge level */ | |
14ce26e7 FB |
2034 | #ifdef TARGET_X86_64 |
2035 | if (shift == 2) { | |
2036 | POPQ(sp, new_esp); | |
2037 | POPQ(sp, new_ss); | |
2038 | new_ss &= 0xffff; | |
2039 | } else | |
2040 | #endif | |
2c0262af FB |
2041 | if (shift == 1) { |
2042 | /* 32 bits */ | |
891b38e4 FB |
2043 | POPL(ssp, sp, sp_mask, new_esp); |
2044 | POPL(ssp, sp, sp_mask, new_ss); | |
2045 | new_ss &= 0xffff; | |
2c0262af FB |
2046 | } else { |
2047 | /* 16 bits */ | |
891b38e4 FB |
2048 | POPW(ssp, sp, sp_mask, new_esp); |
2049 | POPW(ssp, sp, sp_mask, new_ss); | |
2c0262af | 2050 | } |
e19e89a5 FB |
2051 | #ifdef DEBUG_PCALL |
2052 | if (loglevel & CPU_LOG_PCALL) { | |
14ce26e7 | 2053 | fprintf(logfile, "new ss:esp=%04x:" TARGET_FMT_lx "\n", |
e19e89a5 FB |
2054 | new_ss, new_esp); |
2055 | } | |
2056 | #endif | |
b359d4e7 FB |
2057 | if ((new_ss & 0xfffc) == 0) { |
2058 | #ifdef TARGET_X86_64 | |
2059 | /* NULL ss is allowed in long mode if cpl != 3*/ | |
2060 | if ((env->hflags & HF_LMA_MASK) && rpl != 3) { | |
2061 | cpu_x86_load_seg_cache(env, R_SS, new_ss, | |
2062 | 0, 0xffffffff, | |
2063 | DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | | |
2064 | DESC_S_MASK | (rpl << DESC_DPL_SHIFT) | | |
2065 | DESC_W_MASK | DESC_A_MASK); | |
2066 | } else | |
2067 | #endif | |
2068 | { | |
2069 | raise_exception_err(EXCP0D_GPF, 0); | |
2070 | } | |
14ce26e7 FB |
2071 | } else { |
2072 | if ((new_ss & 3) != rpl) | |
2073 | raise_exception_err(EXCP0D_GPF, new_ss & 0xfffc); | |
2074 | if (load_segment(&ss_e1, &ss_e2, new_ss) != 0) | |
2075 | raise_exception_err(EXCP0D_GPF, new_ss & 0xfffc); | |
2076 | if (!(ss_e2 & DESC_S_MASK) || | |
2077 | (ss_e2 & DESC_CS_MASK) || | |
2078 | !(ss_e2 & DESC_W_MASK)) | |
2079 | raise_exception_err(EXCP0D_GPF, new_ss & 0xfffc); | |
2080 | dpl = (ss_e2 >> DESC_DPL_SHIFT) & 3; | |
2081 | if (dpl != rpl) | |
2082 | raise_exception_err(EXCP0D_GPF, new_ss & 0xfffc); | |
2083 | if (!(ss_e2 & DESC_P_MASK)) | |
2084 | raise_exception_err(EXCP0B_NOSEG, new_ss & 0xfffc); | |
2085 | cpu_x86_load_seg_cache(env, R_SS, new_ss, | |
2086 | get_seg_base(ss_e1, ss_e2), | |
2087 | get_seg_limit(ss_e1, ss_e2), | |
2088 | ss_e2); | |
2089 | } | |
2c0262af FB |
2090 | |
2091 | cpu_x86_load_seg_cache(env, R_CS, new_cs, | |
2092 | get_seg_base(e1, e2), | |
2093 | get_seg_limit(e1, e2), | |
2094 | e2); | |
2c0262af | 2095 | cpu_x86_set_cpl(env, rpl); |
891b38e4 | 2096 | sp = new_esp; |
14ce26e7 FB |
2097 | #ifdef TARGET_X86_64 |
2098 | if (shift == 2) | |
2099 | sp_mask = -1; | |
2100 | else | |
2101 | #endif | |
2102 | sp_mask = get_sp_mask(ss_e2); | |
8e682019 FB |
2103 | |
2104 | /* validate data segments */ | |
2105 | validate_seg(R_ES, cpl); | |
2106 | validate_seg(R_DS, cpl); | |
2107 | validate_seg(R_FS, cpl); | |
2108 | validate_seg(R_GS, cpl); | |
4afa6482 FB |
2109 | |
2110 | sp += addend; | |
2c0262af | 2111 | } |
891b38e4 | 2112 | ESP = (ESP & ~sp_mask) | (sp & sp_mask); |
2c0262af FB |
2113 | env->eip = new_eip; |
2114 | if (is_iret) { | |
4136f33c | 2115 | /* NOTE: 'cpl' is the _old_ CPL */ |
8145122b | 2116 | eflags_mask = TF_MASK | AC_MASK | ID_MASK | RF_MASK | NT_MASK; |
2c0262af | 2117 | if (cpl == 0) |
4136f33c FB |
2118 | eflags_mask |= IOPL_MASK; |
2119 | iopl = (env->eflags >> IOPL_SHIFT) & 3; | |
2120 | if (cpl <= iopl) | |
2121 | eflags_mask |= IF_MASK; | |
2c0262af FB |
2122 | if (shift == 0) |
2123 | eflags_mask &= 0xffff; | |
2124 | load_eflags(new_eflags, eflags_mask); | |
2125 | } | |
2126 | return; | |
2127 | ||
2128 | return_to_vm86: | |
891b38e4 FB |
2129 | POPL(ssp, sp, sp_mask, new_esp); |
2130 | POPL(ssp, sp, sp_mask, new_ss); | |
2131 | POPL(ssp, sp, sp_mask, new_es); | |
2132 | POPL(ssp, sp, sp_mask, new_ds); | |
2133 | POPL(ssp, sp, sp_mask, new_fs); | |
2134 | POPL(ssp, sp, sp_mask, new_gs); | |
2c0262af FB |
2135 | |
2136 | /* modify processor state */ | |
4136f33c | 2137 | load_eflags(new_eflags, TF_MASK | AC_MASK | ID_MASK | |
8145122b | 2138 | IF_MASK | IOPL_MASK | VM_MASK | NT_MASK | VIF_MASK | VIP_MASK); |
891b38e4 | 2139 | load_seg_vm(R_CS, new_cs & 0xffff); |
2c0262af | 2140 | cpu_x86_set_cpl(env, 3); |
891b38e4 FB |
2141 | load_seg_vm(R_SS, new_ss & 0xffff); |
2142 | load_seg_vm(R_ES, new_es & 0xffff); | |
2143 | load_seg_vm(R_DS, new_ds & 0xffff); | |
2144 | load_seg_vm(R_FS, new_fs & 0xffff); | |
2145 | load_seg_vm(R_GS, new_gs & 0xffff); | |
2c0262af | 2146 | |
fd836909 | 2147 | env->eip = new_eip & 0xffff; |
2c0262af FB |
2148 | ESP = new_esp; |
2149 | } | |
2150 | ||
08cea4ee | 2151 | void helper_iret_protected(int shift, int next_eip) |
2c0262af | 2152 | { |
7e84c249 FB |
2153 | int tss_selector, type; |
2154 | uint32_t e1, e2; | |
2155 | ||
2156 | /* specific case for TSS */ | |
2157 | if (env->eflags & NT_MASK) { | |
14ce26e7 FB |
2158 | #ifdef TARGET_X86_64 |
2159 | if (env->hflags & HF_LMA_MASK) | |
2160 | raise_exception_err(EXCP0D_GPF, 0); | |
2161 | #endif | |
7e84c249 FB |
2162 | tss_selector = lduw_kernel(env->tr.base + 0); |
2163 | if (tss_selector & 4) | |
2164 | raise_exception_err(EXCP0A_TSS, tss_selector & 0xfffc); | |
2165 | if (load_segment(&e1, &e2, tss_selector) != 0) | |
2166 | raise_exception_err(EXCP0A_TSS, tss_selector & 0xfffc); | |
2167 | type = (e2 >> DESC_TYPE_SHIFT) & 0x17; | |
2168 | /* NOTE: we check both segment and busy TSS */ | |
2169 | if (type != 3) | |
2170 | raise_exception_err(EXCP0A_TSS, tss_selector & 0xfffc); | |
08cea4ee | 2171 | switch_tss(tss_selector, e1, e2, SWITCH_TSS_IRET, next_eip); |
7e84c249 FB |
2172 | } else { |
2173 | helper_ret_protected(shift, 1, 0); | |
2174 | } | |
9df217a3 FB |
2175 | #ifdef USE_KQEMU |
2176 | if (kqemu_is_ok(env)) { | |
2177 | CC_OP = CC_OP_EFLAGS; | |
2178 | env->exception_index = -1; | |
2179 | cpu_loop_exit(); | |
2180 | } | |
2181 | #endif | |
2c0262af FB |
2182 | } |
2183 | ||
2184 | void helper_lret_protected(int shift, int addend) | |
2185 | { | |
2186 | helper_ret_protected(shift, 0, addend); | |
9df217a3 FB |
2187 | #ifdef USE_KQEMU |
2188 | if (kqemu_is_ok(env)) { | |
9df217a3 FB |
2189 | env->exception_index = -1; |
2190 | cpu_loop_exit(); | |
2191 | } | |
2192 | #endif | |
2c0262af FB |
2193 | } |
2194 | ||
023fe10d FB |
2195 | void helper_sysenter(void) |
2196 | { | |
2197 | if (env->sysenter_cs == 0) { | |
2198 | raise_exception_err(EXCP0D_GPF, 0); | |
2199 | } | |
2200 | env->eflags &= ~(VM_MASK | IF_MASK | RF_MASK); | |
2201 | cpu_x86_set_cpl(env, 0); | |
2202 | cpu_x86_load_seg_cache(env, R_CS, env->sysenter_cs & 0xfffc, | |
14ce26e7 | 2203 | 0, 0xffffffff, |
023fe10d FB |
2204 | DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | |
2205 | DESC_S_MASK | | |
2206 | DESC_CS_MASK | DESC_R_MASK | DESC_A_MASK); | |
2207 | cpu_x86_load_seg_cache(env, R_SS, (env->sysenter_cs + 8) & 0xfffc, | |
14ce26e7 | 2208 | 0, 0xffffffff, |
023fe10d FB |
2209 | DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | |
2210 | DESC_S_MASK | | |
2211 | DESC_W_MASK | DESC_A_MASK); | |
2212 | ESP = env->sysenter_esp; | |
2213 | EIP = env->sysenter_eip; | |
2214 | } | |
2215 | ||
2216 | void helper_sysexit(void) | |
2217 | { | |
2218 | int cpl; | |
2219 | ||
2220 | cpl = env->hflags & HF_CPL_MASK; | |
2221 | if (env->sysenter_cs == 0 || cpl != 0) { | |
2222 | raise_exception_err(EXCP0D_GPF, 0); | |
2223 | } | |
2224 | cpu_x86_set_cpl(env, 3); | |
2225 | cpu_x86_load_seg_cache(env, R_CS, ((env->sysenter_cs + 16) & 0xfffc) | 3, | |
14ce26e7 | 2226 | 0, 0xffffffff, |
023fe10d FB |
2227 | DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | |
2228 | DESC_S_MASK | (3 << DESC_DPL_SHIFT) | | |
2229 | DESC_CS_MASK | DESC_R_MASK | DESC_A_MASK); | |
2230 | cpu_x86_load_seg_cache(env, R_SS, ((env->sysenter_cs + 24) & 0xfffc) | 3, | |
14ce26e7 | 2231 | 0, 0xffffffff, |
023fe10d FB |
2232 | DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | |
2233 | DESC_S_MASK | (3 << DESC_DPL_SHIFT) | | |
2234 | DESC_W_MASK | DESC_A_MASK); | |
2235 | ESP = ECX; | |
2236 | EIP = EDX; | |
9df217a3 FB |
2237 | #ifdef USE_KQEMU |
2238 | if (kqemu_is_ok(env)) { | |
2239 | env->exception_index = -1; | |
2240 | cpu_loop_exit(); | |
2241 | } | |
2242 | #endif | |
023fe10d FB |
2243 | } |
2244 | ||
2c0262af FB |
2245 | void helper_movl_crN_T0(int reg) |
2246 | { | |
4d6b6c0a | 2247 | #if !defined(CONFIG_USER_ONLY) |
2c0262af FB |
2248 | switch(reg) { |
2249 | case 0: | |
1ac157da | 2250 | cpu_x86_update_cr0(env, T0); |
2c0262af FB |
2251 | break; |
2252 | case 3: | |
1ac157da FB |
2253 | cpu_x86_update_cr3(env, T0); |
2254 | break; | |
2255 | case 4: | |
2256 | cpu_x86_update_cr4(env, T0); | |
2257 | break; | |
4d6b6c0a FB |
2258 | case 8: |
2259 | cpu_set_apic_tpr(env, T0); | |
2260 | break; | |
1ac157da FB |
2261 | default: |
2262 | env->cr[reg] = T0; | |
2c0262af FB |
2263 | break; |
2264 | } | |
4d6b6c0a | 2265 | #endif |
2c0262af FB |
2266 | } |
2267 | ||
2268 | /* XXX: do more */ | |
2269 | void helper_movl_drN_T0(int reg) | |
2270 | { | |
2271 | env->dr[reg] = T0; | |
2272 | } | |
2273 | ||
2274 | void helper_invlpg(unsigned int addr) | |
2275 | { | |
2276 | cpu_x86_flush_tlb(env, addr); | |
2277 | } | |
2278 | ||
2c0262af FB |
2279 | void helper_rdtsc(void) |
2280 | { | |
2281 | uint64_t val; | |
28ab0e2e FB |
2282 | |
2283 | val = cpu_get_tsc(env); | |
14ce26e7 FB |
2284 | EAX = (uint32_t)(val); |
2285 | EDX = (uint32_t)(val >> 32); | |
2286 | } | |
2287 | ||
2288 | #if defined(CONFIG_USER_ONLY) | |
2289 | void helper_wrmsr(void) | |
2290 | { | |
2c0262af FB |
2291 | } |
2292 | ||
14ce26e7 FB |
2293 | void helper_rdmsr(void) |
2294 | { | |
2295 | } | |
2296 | #else | |
2c0262af FB |
2297 | void helper_wrmsr(void) |
2298 | { | |
14ce26e7 FB |
2299 | uint64_t val; |
2300 | ||
2301 | val = ((uint32_t)EAX) | ((uint64_t)((uint32_t)EDX) << 32); | |
2302 | ||
2303 | switch((uint32_t)ECX) { | |
2c0262af | 2304 | case MSR_IA32_SYSENTER_CS: |
14ce26e7 | 2305 | env->sysenter_cs = val & 0xffff; |
2c0262af FB |
2306 | break; |
2307 | case MSR_IA32_SYSENTER_ESP: | |
14ce26e7 | 2308 | env->sysenter_esp = val; |
2c0262af FB |
2309 | break; |
2310 | case MSR_IA32_SYSENTER_EIP: | |
14ce26e7 FB |
2311 | env->sysenter_eip = val; |
2312 | break; | |
2313 | case MSR_IA32_APICBASE: | |
2314 | cpu_set_apic_base(env, val); | |
2315 | break; | |
14ce26e7 | 2316 | case MSR_EFER: |
f419b321 FB |
2317 | { |
2318 | uint64_t update_mask; | |
2319 | update_mask = 0; | |
2320 | if (env->cpuid_ext2_features & CPUID_EXT2_SYSCALL) | |
2321 | update_mask |= MSR_EFER_SCE; | |
2322 | if (env->cpuid_ext2_features & CPUID_EXT2_LM) | |
2323 | update_mask |= MSR_EFER_LME; | |
2324 | if (env->cpuid_ext2_features & CPUID_EXT2_FFXSR) | |
2325 | update_mask |= MSR_EFER_FFXSR; | |
2326 | if (env->cpuid_ext2_features & CPUID_EXT2_NX) | |
2327 | update_mask |= MSR_EFER_NXE; | |
2328 | env->efer = (env->efer & ~update_mask) | | |
2329 | (val & update_mask); | |
2330 | } | |
2c0262af | 2331 | break; |
14ce26e7 FB |
2332 | case MSR_STAR: |
2333 | env->star = val; | |
2334 | break; | |
f419b321 | 2335 | #ifdef TARGET_X86_64 |
14ce26e7 FB |
2336 | case MSR_LSTAR: |
2337 | env->lstar = val; | |
2338 | break; | |
2339 | case MSR_CSTAR: | |
2340 | env->cstar = val; | |
2341 | break; | |
2342 | case MSR_FMASK: | |
2343 | env->fmask = val; | |
2344 | break; | |
2345 | case MSR_FSBASE: | |
2346 | env->segs[R_FS].base = val; | |
2347 | break; | |
2348 | case MSR_GSBASE: | |
2349 | env->segs[R_GS].base = val; | |
2350 | break; | |
2351 | case MSR_KERNELGSBASE: | |
2352 | env->kernelgsbase = val; | |
2353 | break; | |
2354 | #endif | |
2c0262af FB |
2355 | default: |
2356 | /* XXX: exception ? */ | |
2357 | break; | |
2358 | } | |
2359 | } | |
2360 | ||
2361 | void helper_rdmsr(void) | |
2362 | { | |
14ce26e7 FB |
2363 | uint64_t val; |
2364 | switch((uint32_t)ECX) { | |
2c0262af | 2365 | case MSR_IA32_SYSENTER_CS: |
14ce26e7 | 2366 | val = env->sysenter_cs; |
2c0262af FB |
2367 | break; |
2368 | case MSR_IA32_SYSENTER_ESP: | |
14ce26e7 | 2369 | val = env->sysenter_esp; |
2c0262af FB |
2370 | break; |
2371 | case MSR_IA32_SYSENTER_EIP: | |
14ce26e7 FB |
2372 | val = env->sysenter_eip; |
2373 | break; | |
2374 | case MSR_IA32_APICBASE: | |
2375 | val = cpu_get_apic_base(env); | |
2376 | break; | |
14ce26e7 FB |
2377 | case MSR_EFER: |
2378 | val = env->efer; | |
2379 | break; | |
2380 | case MSR_STAR: | |
2381 | val = env->star; | |
2382 | break; | |
f419b321 | 2383 | #ifdef TARGET_X86_64 |
14ce26e7 FB |
2384 | case MSR_LSTAR: |
2385 | val = env->lstar; | |
2386 | break; | |
2387 | case MSR_CSTAR: | |
2388 | val = env->cstar; | |
2389 | break; | |
2390 | case MSR_FMASK: | |
2391 | val = env->fmask; | |
2392 | break; | |
2393 | case MSR_FSBASE: | |
2394 | val = env->segs[R_FS].base; | |
2395 | break; | |
2396 | case MSR_GSBASE: | |
2397 | val = env->segs[R_GS].base; | |
2c0262af | 2398 | break; |
14ce26e7 FB |
2399 | case MSR_KERNELGSBASE: |
2400 | val = env->kernelgsbase; | |
2401 | break; | |
2402 | #endif | |
2c0262af FB |
2403 | default: |
2404 | /* XXX: exception ? */ | |
14ce26e7 | 2405 | val = 0; |
2c0262af FB |
2406 | break; |
2407 | } | |
14ce26e7 FB |
2408 | EAX = (uint32_t)(val); |
2409 | EDX = (uint32_t)(val >> 32); | |
2c0262af | 2410 | } |
14ce26e7 | 2411 | #endif |
2c0262af FB |
2412 | |
2413 | void helper_lsl(void) | |
2414 | { | |
2415 | unsigned int selector, limit; | |
5516d670 | 2416 | uint32_t e1, e2, eflags; |
3ab493de | 2417 | int rpl, dpl, cpl, type; |
2c0262af | 2418 | |
5516d670 | 2419 | eflags = cc_table[CC_OP].compute_all(); |
2c0262af FB |
2420 | selector = T0 & 0xffff; |
2421 | if (load_segment(&e1, &e2, selector) != 0) | |
5516d670 | 2422 | goto fail; |
3ab493de FB |
2423 | rpl = selector & 3; |
2424 | dpl = (e2 >> DESC_DPL_SHIFT) & 3; | |
2425 | cpl = env->hflags & HF_CPL_MASK; | |
2426 | if (e2 & DESC_S_MASK) { | |
2427 | if ((e2 & DESC_CS_MASK) && (e2 & DESC_C_MASK)) { | |
2428 | /* conforming */ | |
2429 | } else { | |
2430 | if (dpl < cpl || dpl < rpl) | |
5516d670 | 2431 | goto fail; |
3ab493de FB |
2432 | } |
2433 | } else { | |
2434 | type = (e2 >> DESC_TYPE_SHIFT) & 0xf; | |
2435 | switch(type) { | |
2436 | case 1: | |
2437 | case 2: | |
2438 | case 3: | |
2439 | case 9: | |
2440 | case 11: | |
2441 | break; | |
2442 | default: | |
5516d670 | 2443 | goto fail; |
3ab493de | 2444 | } |
5516d670 FB |
2445 | if (dpl < cpl || dpl < rpl) { |
2446 | fail: | |
2447 | CC_SRC = eflags & ~CC_Z; | |
3ab493de | 2448 | return; |
5516d670 | 2449 | } |
3ab493de FB |
2450 | } |
2451 | limit = get_seg_limit(e1, e2); | |
2c0262af | 2452 | T1 = limit; |
5516d670 | 2453 | CC_SRC = eflags | CC_Z; |
2c0262af FB |
2454 | } |
2455 | ||
2456 | void helper_lar(void) | |
2457 | { | |
2458 | unsigned int selector; | |
5516d670 | 2459 | uint32_t e1, e2, eflags; |
3ab493de | 2460 | int rpl, dpl, cpl, type; |
2c0262af | 2461 | |
5516d670 | 2462 | eflags = cc_table[CC_OP].compute_all(); |
2c0262af | 2463 | selector = T0 & 0xffff; |
3ab493de | 2464 | if ((selector & 0xfffc) == 0) |
5516d670 | 2465 | goto fail; |
2c0262af | 2466 | if (load_segment(&e1, &e2, selector) != 0) |
5516d670 | 2467 | goto fail; |
3ab493de FB |
2468 | rpl = selector & 3; |
2469 | dpl = (e2 >> DESC_DPL_SHIFT) & 3; | |
2470 | cpl = env->hflags & HF_CPL_MASK; | |
2471 | if (e2 & DESC_S_MASK) { | |
2472 | if ((e2 & DESC_CS_MASK) && (e2 & DESC_C_MASK)) { | |
2473 | /* conforming */ | |
2474 | } else { | |
2475 | if (dpl < cpl || dpl < rpl) | |
5516d670 | 2476 | goto fail; |
3ab493de FB |
2477 | } |
2478 | } else { | |
2479 | type = (e2 >> DESC_TYPE_SHIFT) & 0xf; | |
2480 | switch(type) { | |
2481 | case 1: | |
2482 | case 2: | |
2483 | case 3: | |
2484 | case 4: | |
2485 | case 5: | |
2486 | case 9: | |
2487 | case 11: | |
2488 | case 12: | |
2489 | break; | |
2490 | default: | |
5516d670 | 2491 | goto fail; |
3ab493de | 2492 | } |
5516d670 FB |
2493 | if (dpl < cpl || dpl < rpl) { |
2494 | fail: | |
2495 | CC_SRC = eflags & ~CC_Z; | |
3ab493de | 2496 | return; |
5516d670 | 2497 | } |
3ab493de | 2498 | } |
2c0262af | 2499 | T1 = e2 & 0x00f0ff00; |
5516d670 | 2500 | CC_SRC = eflags | CC_Z; |
2c0262af FB |
2501 | } |
2502 | ||
3ab493de FB |
2503 | void helper_verr(void) |
2504 | { | |
2505 | unsigned int selector; | |
5516d670 | 2506 | uint32_t e1, e2, eflags; |
3ab493de FB |
2507 | int rpl, dpl, cpl; |
2508 | ||
5516d670 | 2509 | eflags = cc_table[CC_OP].compute_all(); |
3ab493de FB |
2510 | selector = T0 & 0xffff; |
2511 | if ((selector & 0xfffc) == 0) | |
5516d670 | 2512 | goto fail; |
3ab493de | 2513 | if (load_segment(&e1, &e2, selector) != 0) |
5516d670 | 2514 | goto fail; |
3ab493de | 2515 | if (!(e2 & DESC_S_MASK)) |
5516d670 | 2516 | goto fail; |
3ab493de FB |
2517 | rpl = selector & 3; |
2518 | dpl = (e2 >> DESC_DPL_SHIFT) & 3; | |
2519 | cpl = env->hflags & HF_CPL_MASK; | |
2520 | if (e2 & DESC_CS_MASK) { | |
2521 | if (!(e2 & DESC_R_MASK)) | |
5516d670 | 2522 | goto fail; |
3ab493de FB |
2523 | if (!(e2 & DESC_C_MASK)) { |
2524 | if (dpl < cpl || dpl < rpl) | |
5516d670 | 2525 | goto fail; |
3ab493de FB |
2526 | } |
2527 | } else { | |
5516d670 FB |
2528 | if (dpl < cpl || dpl < rpl) { |
2529 | fail: | |
2530 | CC_SRC = eflags & ~CC_Z; | |
3ab493de | 2531 | return; |
5516d670 | 2532 | } |
3ab493de | 2533 | } |
5516d670 | 2534 | CC_SRC = eflags | CC_Z; |
3ab493de FB |
2535 | } |
2536 | ||
2537 | void helper_verw(void) | |
2538 | { | |
2539 | unsigned int selector; | |
5516d670 | 2540 | uint32_t e1, e2, eflags; |
3ab493de FB |
2541 | int rpl, dpl, cpl; |
2542 | ||
5516d670 | 2543 | eflags = cc_table[CC_OP].compute_all(); |
3ab493de FB |
2544 | selector = T0 & 0xffff; |
2545 | if ((selector & 0xfffc) == 0) | |
5516d670 | 2546 | goto fail; |
3ab493de | 2547 | if (load_segment(&e1, &e2, selector) != 0) |
5516d670 | 2548 | goto fail; |
3ab493de | 2549 | if (!(e2 & DESC_S_MASK)) |
5516d670 | 2550 | goto fail; |
3ab493de FB |
2551 | rpl = selector & 3; |
2552 | dpl = (e2 >> DESC_DPL_SHIFT) & 3; | |
2553 | cpl = env->hflags & HF_CPL_MASK; | |
2554 | if (e2 & DESC_CS_MASK) { | |
5516d670 | 2555 | goto fail; |
3ab493de FB |
2556 | } else { |
2557 | if (dpl < cpl || dpl < rpl) | |
5516d670 FB |
2558 | goto fail; |
2559 | if (!(e2 & DESC_W_MASK)) { | |
2560 | fail: | |
2561 | CC_SRC = eflags & ~CC_Z; | |
3ab493de | 2562 | return; |
5516d670 | 2563 | } |
3ab493de | 2564 | } |
5516d670 | 2565 | CC_SRC = eflags | CC_Z; |
3ab493de FB |
2566 | } |
2567 | ||
2c0262af FB |
2568 | /* FPU helpers */ |
2569 | ||
2c0262af FB |
2570 | void helper_fldt_ST0_A0(void) |
2571 | { | |
2572 | int new_fpstt; | |
2573 | new_fpstt = (env->fpstt - 1) & 7; | |
664e0f19 | 2574 | env->fpregs[new_fpstt].d = helper_fldt(A0); |
2c0262af FB |
2575 | env->fpstt = new_fpstt; |
2576 | env->fptags[new_fpstt] = 0; /* validate stack entry */ | |
2577 | } | |
2578 | ||
2579 | void helper_fstt_ST0_A0(void) | |
2580 | { | |
14ce26e7 | 2581 | helper_fstt(ST0, A0); |
2c0262af | 2582 | } |
2c0262af | 2583 | |
2ee73ac3 FB |
2584 | void fpu_set_exception(int mask) |
2585 | { | |
2586 | env->fpus |= mask; | |
2587 | if (env->fpus & (~env->fpuc & FPUC_EM)) | |
2588 | env->fpus |= FPUS_SE | FPUS_B; | |
2589 | } | |
2590 | ||
2591 | CPU86_LDouble helper_fdiv(CPU86_LDouble a, CPU86_LDouble b) | |
2592 | { | |
2593 | if (b == 0.0) | |
2594 | fpu_set_exception(FPUS_ZE); | |
2595 | return a / b; | |
2596 | } | |
2597 | ||
2598 | void fpu_raise_exception(void) | |
2599 | { | |
2600 | if (env->cr[0] & CR0_NE_MASK) { | |
2601 | raise_exception(EXCP10_COPR); | |
2602 | } | |
2603 | #if !defined(CONFIG_USER_ONLY) | |
2604 | else { | |
2605 | cpu_set_ferr(env); | |
2606 | } | |
2607 | #endif | |
2608 | } | |
2609 | ||
2c0262af FB |
2610 | /* BCD ops */ |
2611 | ||
2c0262af FB |
2612 | void helper_fbld_ST0_A0(void) |
2613 | { | |
2614 | CPU86_LDouble tmp; | |
2615 | uint64_t val; | |
2616 | unsigned int v; | |
2617 | int i; | |
2618 | ||
2619 | val = 0; | |
2620 | for(i = 8; i >= 0; i--) { | |
14ce26e7 | 2621 | v = ldub(A0 + i); |
2c0262af FB |
2622 | val = (val * 100) + ((v >> 4) * 10) + (v & 0xf); |
2623 | } | |
2624 | tmp = val; | |
14ce26e7 | 2625 | if (ldub(A0 + 9) & 0x80) |
2c0262af FB |
2626 | tmp = -tmp; |
2627 | fpush(); | |
2628 | ST0 = tmp; | |
2629 | } | |
2630 | ||
2631 | void helper_fbst_ST0_A0(void) | |
2632 | { | |
2c0262af | 2633 | int v; |
14ce26e7 | 2634 | target_ulong mem_ref, mem_end; |
2c0262af FB |
2635 | int64_t val; |
2636 | ||
7a0e1f41 | 2637 | val = floatx_to_int64(ST0, &env->fp_status); |
14ce26e7 | 2638 | mem_ref = A0; |
2c0262af FB |
2639 | mem_end = mem_ref + 9; |
2640 | if (val < 0) { | |
2641 | stb(mem_end, 0x80); | |
2642 | val = -val; | |
2643 | } else { | |
2644 | stb(mem_end, 0x00); | |
2645 | } | |
2646 | while (mem_ref < mem_end) { | |
2647 | if (val == 0) | |
2648 | break; | |
2649 | v = val % 100; | |
2650 | val = val / 100; | |
2651 | v = ((v / 10) << 4) | (v % 10); | |
2652 | stb(mem_ref++, v); | |
2653 | } | |
2654 | while (mem_ref < mem_end) { | |
2655 | stb(mem_ref++, 0); | |
2656 | } | |
2657 | } | |
2658 | ||
2659 | void helper_f2xm1(void) | |
2660 | { | |
2661 | ST0 = pow(2.0,ST0) - 1.0; | |
2662 | } | |
2663 | ||
2664 | void helper_fyl2x(void) | |
2665 | { | |
2666 | CPU86_LDouble fptemp; | |
2667 | ||
2668 | fptemp = ST0; | |
2669 | if (fptemp>0.0){ | |
2670 | fptemp = log(fptemp)/log(2.0); /* log2(ST) */ | |
2671 | ST1 *= fptemp; | |
2672 | fpop(); | |
2673 | } else { | |
2674 | env->fpus &= (~0x4700); | |
2675 | env->fpus |= 0x400; | |
2676 | } | |
2677 | } | |
2678 | ||
2679 | void helper_fptan(void) | |
2680 | { | |
2681 | CPU86_LDouble fptemp; | |
2682 | ||
2683 | fptemp = ST0; | |
2684 | if((fptemp > MAXTAN)||(fptemp < -MAXTAN)) { | |
2685 | env->fpus |= 0x400; | |
2686 | } else { | |
2687 | ST0 = tan(fptemp); | |
2688 | fpush(); | |
2689 | ST0 = 1.0; | |
2690 | env->fpus &= (~0x400); /* C2 <-- 0 */ | |
2691 | /* the above code is for |arg| < 2**52 only */ | |
2692 | } | |
2693 | } | |
2694 | ||
2695 | void helper_fpatan(void) | |
2696 | { | |
2697 | CPU86_LDouble fptemp, fpsrcop; | |
2698 | ||
2699 | fpsrcop = ST1; | |
2700 | fptemp = ST0; | |
2701 | ST1 = atan2(fpsrcop,fptemp); | |
2702 | fpop(); | |
2703 | } | |
2704 | ||
2705 | void helper_fxtract(void) | |
2706 | { | |
2707 | CPU86_LDoubleU temp; | |
2708 | unsigned int expdif; | |
2709 | ||
2710 | temp.d = ST0; | |
2711 | expdif = EXPD(temp) - EXPBIAS; | |
2712 | /*DP exponent bias*/ | |
2713 | ST0 = expdif; | |
2714 | fpush(); | |
2715 | BIASEXPONENT(temp); | |
2716 | ST0 = temp.d; | |
2717 | } | |
2718 | ||
2719 | void helper_fprem1(void) | |
2720 | { | |
2721 | CPU86_LDouble dblq, fpsrcop, fptemp; | |
2722 | CPU86_LDoubleU fpsrcop1, fptemp1; | |
2723 | int expdif; | |
2724 | int q; | |
2725 | ||
2726 | fpsrcop = ST0; | |
2727 | fptemp = ST1; | |
2728 | fpsrcop1.d = fpsrcop; | |
2729 | fptemp1.d = fptemp; | |
2730 | expdif = EXPD(fpsrcop1) - EXPD(fptemp1); | |
2731 | if (expdif < 53) { | |
2732 | dblq = fpsrcop / fptemp; | |
2733 | dblq = (dblq < 0.0)? ceil(dblq): floor(dblq); | |
2734 | ST0 = fpsrcop - fptemp*dblq; | |
2735 | q = (int)dblq; /* cutting off top bits is assumed here */ | |
2736 | env->fpus &= (~0x4700); /* (C3,C2,C1,C0) <-- 0000 */ | |
2737 | /* (C0,C1,C3) <-- (q2,q1,q0) */ | |
2738 | env->fpus |= (q&0x4) << 6; /* (C0) <-- q2 */ | |
2739 | env->fpus |= (q&0x2) << 8; /* (C1) <-- q1 */ | |
2740 | env->fpus |= (q&0x1) << 14; /* (C3) <-- q0 */ | |
2741 | } else { | |
2742 | env->fpus |= 0x400; /* C2 <-- 1 */ | |
2743 | fptemp = pow(2.0, expdif-50); | |
2744 | fpsrcop = (ST0 / ST1) / fptemp; | |
2745 | /* fpsrcop = integer obtained by rounding to the nearest */ | |
2746 | fpsrcop = (fpsrcop-floor(fpsrcop) < ceil(fpsrcop)-fpsrcop)? | |
2747 | floor(fpsrcop): ceil(fpsrcop); | |
2748 | ST0 -= (ST1 * fpsrcop * fptemp); | |
2749 | } | |
2750 | } | |
2751 | ||
2752 | void helper_fprem(void) | |
2753 | { | |
2754 | CPU86_LDouble dblq, fpsrcop, fptemp; | |
2755 | CPU86_LDoubleU fpsrcop1, fptemp1; | |
2756 | int expdif; | |
2757 | int q; | |
2758 | ||
2759 | fpsrcop = ST0; | |
2760 | fptemp = ST1; | |
2761 | fpsrcop1.d = fpsrcop; | |
2762 | fptemp1.d = fptemp; | |
2763 | expdif = EXPD(fpsrcop1) - EXPD(fptemp1); | |
2764 | if ( expdif < 53 ) { | |
2765 | dblq = fpsrcop / fptemp; | |
2766 | dblq = (dblq < 0.0)? ceil(dblq): floor(dblq); | |
2767 | ST0 = fpsrcop - fptemp*dblq; | |
2768 | q = (int)dblq; /* cutting off top bits is assumed here */ | |
2769 | env->fpus &= (~0x4700); /* (C3,C2,C1,C0) <-- 0000 */ | |
2770 | /* (C0,C1,C3) <-- (q2,q1,q0) */ | |
2771 | env->fpus |= (q&0x4) << 6; /* (C0) <-- q2 */ | |
2772 | env->fpus |= (q&0x2) << 8; /* (C1) <-- q1 */ | |
2773 | env->fpus |= (q&0x1) << 14; /* (C3) <-- q0 */ | |
2774 | } else { | |
2775 | env->fpus |= 0x400; /* C2 <-- 1 */ | |
2776 | fptemp = pow(2.0, expdif-50); | |
2777 | fpsrcop = (ST0 / ST1) / fptemp; | |
2778 | /* fpsrcop = integer obtained by chopping */ | |
2779 | fpsrcop = (fpsrcop < 0.0)? | |
2780 | -(floor(fabs(fpsrcop))): floor(fpsrcop); | |
2781 | ST0 -= (ST1 * fpsrcop * fptemp); | |
2782 | } | |
2783 | } | |
2784 | ||
2785 | void helper_fyl2xp1(void) | |
2786 | { | |
2787 | CPU86_LDouble fptemp; | |
2788 | ||
2789 | fptemp = ST0; | |
2790 | if ((fptemp+1.0)>0.0) { | |
2791 | fptemp = log(fptemp+1.0) / log(2.0); /* log2(ST+1.0) */ | |
2792 | ST1 *= fptemp; | |
2793 | fpop(); | |
2794 | } else { | |
2795 | env->fpus &= (~0x4700); | |
2796 | env->fpus |= 0x400; | |
2797 | } | |
2798 | } | |
2799 | ||
2800 | void helper_fsqrt(void) | |
2801 | { | |
2802 | CPU86_LDouble fptemp; | |
2803 | ||
2804 | fptemp = ST0; | |
2805 | if (fptemp<0.0) { | |
2806 | env->fpus &= (~0x4700); /* (C3,C2,C1,C0) <-- 0000 */ | |
2807 | env->fpus |= 0x400; | |
2808 | } | |
2809 | ST0 = sqrt(fptemp); | |
2810 | } | |
2811 | ||
2812 | void helper_fsincos(void) | |
2813 | { | |
2814 | CPU86_LDouble fptemp; | |
2815 | ||
2816 | fptemp = ST0; | |
2817 | if ((fptemp > MAXTAN)||(fptemp < -MAXTAN)) { | |
2818 | env->fpus |= 0x400; | |
2819 | } else { | |
2820 | ST0 = sin(fptemp); | |
2821 | fpush(); | |
2822 | ST0 = cos(fptemp); | |
2823 | env->fpus &= (~0x400); /* C2 <-- 0 */ | |
2824 | /* the above code is for |arg| < 2**63 only */ | |
2825 | } | |
2826 | } | |
2827 | ||
2828 | void helper_frndint(void) | |
2829 | { | |
7a0e1f41 | 2830 | ST0 = floatx_round_to_int(ST0, &env->fp_status); |
2c0262af FB |
2831 | } |
2832 | ||
2833 | void helper_fscale(void) | |
2834 | { | |
2835 | CPU86_LDouble fpsrcop, fptemp; | |
2836 | ||
2837 | fpsrcop = 2.0; | |
2838 | fptemp = pow(fpsrcop,ST1); | |
2839 | ST0 *= fptemp; | |
2840 | } | |
2841 | ||
2842 | void helper_fsin(void) | |
2843 | { | |
2844 | CPU86_LDouble fptemp; | |
2845 | ||
2846 | fptemp = ST0; | |
2847 | if ((fptemp > MAXTAN)||(fptemp < -MAXTAN)) { | |
2848 | env->fpus |= 0x400; | |
2849 | } else { | |
2850 | ST0 = sin(fptemp); | |
2851 | env->fpus &= (~0x400); /* C2 <-- 0 */ | |
2852 | /* the above code is for |arg| < 2**53 only */ | |
2853 | } | |
2854 | } | |
2855 | ||
2856 | void helper_fcos(void) | |
2857 | { | |
2858 | CPU86_LDouble fptemp; | |
2859 | ||
2860 | fptemp = ST0; | |
2861 | if((fptemp > MAXTAN)||(fptemp < -MAXTAN)) { | |
2862 | env->fpus |= 0x400; | |
2863 | } else { | |
2864 | ST0 = cos(fptemp); | |
2865 | env->fpus &= (~0x400); /* C2 <-- 0 */ | |
2866 | /* the above code is for |arg5 < 2**63 only */ | |
2867 | } | |
2868 | } | |
2869 | ||
2870 | void helper_fxam_ST0(void) | |
2871 | { | |
2872 | CPU86_LDoubleU temp; | |
2873 | int expdif; | |
2874 | ||
2875 | temp.d = ST0; | |
2876 | ||
2877 | env->fpus &= (~0x4700); /* (C3,C2,C1,C0) <-- 0000 */ | |
2878 | if (SIGND(temp)) | |
2879 | env->fpus |= 0x200; /* C1 <-- 1 */ | |
2880 | ||
2881 | expdif = EXPD(temp); | |
2882 | if (expdif == MAXEXPD) { | |
2883 | if (MANTD(temp) == 0) | |
2884 | env->fpus |= 0x500 /*Infinity*/; | |
2885 | else | |
2886 | env->fpus |= 0x100 /*NaN*/; | |
2887 | } else if (expdif == 0) { | |
2888 | if (MANTD(temp) == 0) | |
2889 | env->fpus |= 0x4000 /*Zero*/; | |
2890 | else | |
2891 | env->fpus |= 0x4400 /*Denormal*/; | |
2892 | } else { | |
2893 | env->fpus |= 0x400; | |
2894 | } | |
2895 | } | |
2896 | ||
14ce26e7 | 2897 | void helper_fstenv(target_ulong ptr, int data32) |
2c0262af FB |
2898 | { |
2899 | int fpus, fptag, exp, i; | |
2900 | uint64_t mant; | |
2901 | CPU86_LDoubleU tmp; | |
2902 | ||
2903 | fpus = (env->fpus & ~0x3800) | (env->fpstt & 0x7) << 11; | |
2904 | fptag = 0; | |
2905 | for (i=7; i>=0; i--) { | |
2906 | fptag <<= 2; | |
2907 | if (env->fptags[i]) { | |
2908 | fptag |= 3; | |
2909 | } else { | |
664e0f19 | 2910 | tmp.d = env->fpregs[i].d; |
2c0262af FB |
2911 | exp = EXPD(tmp); |
2912 | mant = MANTD(tmp); | |
2913 | if (exp == 0 && mant == 0) { | |
2914 | /* zero */ | |
2915 | fptag |= 1; | |
2916 | } else if (exp == 0 || exp == MAXEXPD | |
2917 | #ifdef USE_X86LDOUBLE | |
2918 | || (mant & (1LL << 63)) == 0 | |
2919 | #endif | |
2920 | ) { | |
2921 | /* NaNs, infinity, denormal */ | |
2922 | fptag |= 2; | |
2923 | } | |
2924 | } | |
2925 | } | |
2926 | if (data32) { | |
2927 | /* 32 bit */ | |
2928 | stl(ptr, env->fpuc); | |
2929 | stl(ptr + 4, fpus); | |
2930 | stl(ptr + 8, fptag); | |
2edcdce3 FB |
2931 | stl(ptr + 12, 0); /* fpip */ |
2932 | stl(ptr + 16, 0); /* fpcs */ | |
2933 | stl(ptr + 20, 0); /* fpoo */ | |
2934 | stl(ptr + 24, 0); /* fpos */ | |
2c0262af FB |
2935 | } else { |
2936 | /* 16 bit */ | |
2937 | stw(ptr, env->fpuc); | |
2938 | stw(ptr + 2, fpus); | |
2939 | stw(ptr + 4, fptag); | |
2940 | stw(ptr + 6, 0); | |
2941 | stw(ptr + 8, 0); | |
2942 | stw(ptr + 10, 0); | |
2943 | stw(ptr + 12, 0); | |
2944 | } | |
2945 | } | |
2946 | ||
14ce26e7 | 2947 | void helper_fldenv(target_ulong ptr, int data32) |
2c0262af FB |
2948 | { |
2949 | int i, fpus, fptag; | |
2950 | ||
2951 | if (data32) { | |
2952 | env->fpuc = lduw(ptr); | |
2953 | fpus = lduw(ptr + 4); | |
2954 | fptag = lduw(ptr + 8); | |
2955 | } | |
2956 | else { | |
2957 | env->fpuc = lduw(ptr); | |
2958 | fpus = lduw(ptr + 2); | |
2959 | fptag = lduw(ptr + 4); | |
2960 | } | |
2961 | env->fpstt = (fpus >> 11) & 7; | |
2962 | env->fpus = fpus & ~0x3800; | |
2edcdce3 | 2963 | for(i = 0;i < 8; i++) { |
2c0262af FB |
2964 | env->fptags[i] = ((fptag & 3) == 3); |
2965 | fptag >>= 2; | |
2966 | } | |
2967 | } | |
2968 | ||
14ce26e7 | 2969 | void helper_fsave(target_ulong ptr, int data32) |
2c0262af FB |
2970 | { |
2971 | CPU86_LDouble tmp; | |
2972 | int i; | |
2973 | ||
2974 | helper_fstenv(ptr, data32); | |
2975 | ||
2976 | ptr += (14 << data32); | |
2977 | for(i = 0;i < 8; i++) { | |
2978 | tmp = ST(i); | |
2c0262af | 2979 | helper_fstt(tmp, ptr); |
2c0262af FB |
2980 | ptr += 10; |
2981 | } | |
2982 | ||
2983 | /* fninit */ | |
2984 | env->fpus = 0; | |
2985 | env->fpstt = 0; | |
2986 | env->fpuc = 0x37f; | |
2987 | env->fptags[0] = 1; | |
2988 | env->fptags[1] = 1; | |
2989 | env->fptags[2] = 1; | |
2990 | env->fptags[3] = 1; | |
2991 | env->fptags[4] = 1; | |
2992 | env->fptags[5] = 1; | |
2993 | env->fptags[6] = 1; | |
2994 | env->fptags[7] = 1; | |
2995 | } | |
2996 | ||
14ce26e7 | 2997 | void helper_frstor(target_ulong ptr, int data32) |
2c0262af FB |
2998 | { |
2999 | CPU86_LDouble tmp; | |
3000 | int i; | |
3001 | ||
3002 | helper_fldenv(ptr, data32); | |
3003 | ptr += (14 << data32); | |
3004 | ||
3005 | for(i = 0;i < 8; i++) { | |
2c0262af | 3006 | tmp = helper_fldt(ptr); |
2c0262af FB |
3007 | ST(i) = tmp; |
3008 | ptr += 10; | |
3009 | } | |
3010 | } | |
3011 | ||
14ce26e7 FB |
3012 | void helper_fxsave(target_ulong ptr, int data64) |
3013 | { | |
3014 | int fpus, fptag, i, nb_xmm_regs; | |
3015 | CPU86_LDouble tmp; | |
3016 | target_ulong addr; | |
3017 | ||
3018 | fpus = (env->fpus & ~0x3800) | (env->fpstt & 0x7) << 11; | |
3019 | fptag = 0; | |
3020 | for(i = 0; i < 8; i++) { | |
d3c61721 | 3021 | fptag |= (env->fptags[i] << i); |
14ce26e7 FB |
3022 | } |
3023 | stw(ptr, env->fpuc); | |
3024 | stw(ptr + 2, fpus); | |
d3c61721 | 3025 | stw(ptr + 4, fptag ^ 0xff); |
14ce26e7 FB |
3026 | |
3027 | addr = ptr + 0x20; | |
3028 | for(i = 0;i < 8; i++) { | |
3029 | tmp = ST(i); | |
3030 | helper_fstt(tmp, addr); | |
3031 | addr += 16; | |
3032 | } | |
3033 | ||
3034 | if (env->cr[4] & CR4_OSFXSR_MASK) { | |
a8ede8ba | 3035 | /* XXX: finish it */ |
664e0f19 | 3036 | stl(ptr + 0x18, env->mxcsr); /* mxcsr */ |
d3c61721 | 3037 | stl(ptr + 0x1c, 0x0000ffff); /* mxcsr_mask */ |
14ce26e7 FB |
3038 | nb_xmm_regs = 8 << data64; |
3039 | addr = ptr + 0xa0; | |
3040 | for(i = 0; i < nb_xmm_regs; i++) { | |
a8ede8ba FB |
3041 | stq(addr, env->xmm_regs[i].XMM_Q(0)); |
3042 | stq(addr + 8, env->xmm_regs[i].XMM_Q(1)); | |
14ce26e7 FB |
3043 | addr += 16; |
3044 | } | |
3045 | } | |
3046 | } | |
3047 | ||
3048 | void helper_fxrstor(target_ulong ptr, int data64) | |
3049 | { | |
3050 | int i, fpus, fptag, nb_xmm_regs; | |
3051 | CPU86_LDouble tmp; | |
3052 | target_ulong addr; | |
3053 | ||
3054 | env->fpuc = lduw(ptr); | |
3055 | fpus = lduw(ptr + 2); | |
d3c61721 | 3056 | fptag = lduw(ptr + 4); |
14ce26e7 FB |
3057 | env->fpstt = (fpus >> 11) & 7; |
3058 | env->fpus = fpus & ~0x3800; | |
3059 | fptag ^= 0xff; | |
3060 | for(i = 0;i < 8; i++) { | |
d3c61721 | 3061 | env->fptags[i] = ((fptag >> i) & 1); |
14ce26e7 FB |
3062 | } |
3063 | ||
3064 | addr = ptr + 0x20; | |
3065 | for(i = 0;i < 8; i++) { | |
3066 | tmp = helper_fldt(addr); | |
3067 | ST(i) = tmp; | |
3068 | addr += 16; | |
3069 | } | |
3070 | ||
3071 | if (env->cr[4] & CR4_OSFXSR_MASK) { | |
31313213 | 3072 | /* XXX: finish it */ |
664e0f19 | 3073 | env->mxcsr = ldl(ptr + 0x18); |
14ce26e7 FB |
3074 | //ldl(ptr + 0x1c); |
3075 | nb_xmm_regs = 8 << data64; | |
3076 | addr = ptr + 0xa0; | |
3077 | for(i = 0; i < nb_xmm_regs; i++) { | |
a8ede8ba FB |
3078 | env->xmm_regs[i].XMM_Q(0) = ldq(addr); |
3079 | env->xmm_regs[i].XMM_Q(1) = ldq(addr + 8); | |
14ce26e7 FB |
3080 | addr += 16; |
3081 | } | |
3082 | } | |
3083 | } | |
1f1af9fd FB |
3084 | |
3085 | #ifndef USE_X86LDOUBLE | |
3086 | ||
3087 | void cpu_get_fp80(uint64_t *pmant, uint16_t *pexp, CPU86_LDouble f) | |
3088 | { | |
3089 | CPU86_LDoubleU temp; | |
3090 | int e; | |
3091 | ||
3092 | temp.d = f; | |
3093 | /* mantissa */ | |
3094 | *pmant = (MANTD(temp) << 11) | (1LL << 63); | |
3095 | /* exponent + sign */ | |
3096 | e = EXPD(temp) - EXPBIAS + 16383; | |
3097 | e |= SIGND(temp) >> 16; | |
3098 | *pexp = e; | |
3099 | } | |
3100 | ||
3101 | CPU86_LDouble cpu_set_fp80(uint64_t mant, uint16_t upper) | |
3102 | { | |
3103 | CPU86_LDoubleU temp; | |
3104 | int e; | |
3105 | uint64_t ll; | |
3106 | ||
3107 | /* XXX: handle overflow ? */ | |
3108 | e = (upper & 0x7fff) - 16383 + EXPBIAS; /* exponent */ | |
3109 | e |= (upper >> 4) & 0x800; /* sign */ | |
3110 | ll = (mant >> 11) & ((1LL << 52) - 1); | |
3111 | #ifdef __arm__ | |
3112 | temp.l.upper = (e << 20) | (ll >> 32); | |
3113 | temp.l.lower = ll; | |
3114 | #else | |
3115 | temp.ll = ll | ((uint64_t)e << 52); | |
3116 | #endif | |
3117 | return temp.d; | |
3118 | } | |
3119 | ||
3120 | #else | |
3121 | ||
3122 | void cpu_get_fp80(uint64_t *pmant, uint16_t *pexp, CPU86_LDouble f) | |
3123 | { | |
3124 | CPU86_LDoubleU temp; | |
3125 | ||
3126 | temp.d = f; | |
3127 | *pmant = temp.l.lower; | |
3128 | *pexp = temp.l.upper; | |
3129 | } | |
3130 | ||
3131 | CPU86_LDouble cpu_set_fp80(uint64_t mant, uint16_t upper) | |
3132 | { | |
3133 | CPU86_LDoubleU temp; | |
3134 | ||
3135 | temp.l.upper = upper; | |
3136 | temp.l.lower = mant; | |
3137 | return temp.d; | |
3138 | } | |
3139 | #endif | |
3140 | ||
14ce26e7 FB |
3141 | #ifdef TARGET_X86_64 |
3142 | ||
3143 | //#define DEBUG_MULDIV | |
3144 | ||
3145 | static void add128(uint64_t *plow, uint64_t *phigh, uint64_t a, uint64_t b) | |
3146 | { | |
3147 | *plow += a; | |
3148 | /* carry test */ | |
3149 | if (*plow < a) | |
3150 | (*phigh)++; | |
3151 | *phigh += b; | |
3152 | } | |
3153 | ||
3154 | static void neg128(uint64_t *plow, uint64_t *phigh) | |
3155 | { | |
3156 | *plow = ~ *plow; | |
3157 | *phigh = ~ *phigh; | |
3158 | add128(plow, phigh, 1, 0); | |
3159 | } | |
3160 | ||
3161 | static void mul64(uint64_t *plow, uint64_t *phigh, uint64_t a, uint64_t b) | |
3162 | { | |
3163 | uint32_t a0, a1, b0, b1; | |
3164 | uint64_t v; | |
3165 | ||
3166 | a0 = a; | |
3167 | a1 = a >> 32; | |
3168 | ||
3169 | b0 = b; | |
3170 | b1 = b >> 32; | |
3171 | ||
3172 | v = (uint64_t)a0 * (uint64_t)b0; | |
3173 | *plow = v; | |
3174 | *phigh = 0; | |
3175 | ||
3176 | v = (uint64_t)a0 * (uint64_t)b1; | |
3177 | add128(plow, phigh, v << 32, v >> 32); | |
3178 | ||
3179 | v = (uint64_t)a1 * (uint64_t)b0; | |
3180 | add128(plow, phigh, v << 32, v >> 32); | |
3181 | ||
3182 | v = (uint64_t)a1 * (uint64_t)b1; | |
3183 | *phigh += v; | |
3184 | #ifdef DEBUG_MULDIV | |
3185 | printf("mul: 0x%016llx * 0x%016llx = 0x%016llx%016llx\n", | |
3186 | a, b, *phigh, *plow); | |
3187 | #endif | |
3188 | } | |
3189 | ||
3190 | static void imul64(uint64_t *plow, uint64_t *phigh, int64_t a, int64_t b) | |
3191 | { | |
3192 | int sa, sb; | |
3193 | sa = (a < 0); | |
3194 | if (sa) | |
3195 | a = -a; | |
3196 | sb = (b < 0); | |
3197 | if (sb) | |
3198 | b = -b; | |
3199 | mul64(plow, phigh, a, b); | |
3200 | if (sa ^ sb) { | |
3201 | neg128(plow, phigh); | |
3202 | } | |
3203 | } | |
3204 | ||
a8ede8ba | 3205 | /* XXX: overflow support */ |
14ce26e7 FB |
3206 | static void div64(uint64_t *plow, uint64_t *phigh, uint64_t b) |
3207 | { | |
3208 | uint64_t q, r, a1, a0; | |
3209 | int i, qb; | |
3210 | ||
3211 | a0 = *plow; | |
3212 | a1 = *phigh; | |
3213 | if (a1 == 0) { | |
3214 | q = a0 / b; | |
3215 | r = a0 % b; | |
3216 | *plow = q; | |
3217 | *phigh = r; | |
3218 | } else { | |
3219 | /* XXX: use a better algorithm */ | |
3220 | for(i = 0; i < 64; i++) { | |
a8ede8ba | 3221 | a1 = (a1 << 1) | (a0 >> 63); |
14ce26e7 FB |
3222 | if (a1 >= b) { |
3223 | a1 -= b; | |
3224 | qb = 1; | |
3225 | } else { | |
3226 | qb = 0; | |
3227 | } | |
14ce26e7 FB |
3228 | a0 = (a0 << 1) | qb; |
3229 | } | |
a8ede8ba | 3230 | #if defined(DEBUG_MULDIV) |
14ce26e7 FB |
3231 | printf("div: 0x%016llx%016llx / 0x%016llx: q=0x%016llx r=0x%016llx\n", |
3232 | *phigh, *plow, b, a0, a1); | |
3233 | #endif | |
3234 | *plow = a0; | |
3235 | *phigh = a1; | |
3236 | } | |
3237 | } | |
3238 | ||
31313213 | 3239 | static void idiv64(uint64_t *plow, uint64_t *phigh, int64_t b) |
14ce26e7 FB |
3240 | { |
3241 | int sa, sb; | |
3242 | sa = ((int64_t)*phigh < 0); | |
3243 | if (sa) | |
3244 | neg128(plow, phigh); | |
3245 | sb = (b < 0); | |
3246 | if (sb) | |
3247 | b = -b; | |
3248 | div64(plow, phigh, b); | |
3249 | if (sa ^ sb) | |
3250 | *plow = - *plow; | |
31313213 | 3251 | if (sa) |
14ce26e7 FB |
3252 | *phigh = - *phigh; |
3253 | } | |
3254 | ||
3255 | void helper_mulq_EAX_T0(void) | |
3256 | { | |
3257 | uint64_t r0, r1; | |
3258 | ||
3259 | mul64(&r0, &r1, EAX, T0); | |
3260 | EAX = r0; | |
3261 | EDX = r1; | |
3262 | CC_DST = r0; | |
3263 | CC_SRC = r1; | |
3264 | } | |
3265 | ||
3266 | void helper_imulq_EAX_T0(void) | |
3267 | { | |
3268 | uint64_t r0, r1; | |
3269 | ||
3270 | imul64(&r0, &r1, EAX, T0); | |
3271 | EAX = r0; | |
3272 | EDX = r1; | |
3273 | CC_DST = r0; | |
a8ede8ba | 3274 | CC_SRC = ((int64_t)r1 != ((int64_t)r0 >> 63)); |
14ce26e7 FB |
3275 | } |
3276 | ||
3277 | void helper_imulq_T0_T1(void) | |
3278 | { | |
3279 | uint64_t r0, r1; | |
3280 | ||
3281 | imul64(&r0, &r1, T0, T1); | |
3282 | T0 = r0; | |
3283 | CC_DST = r0; | |
3284 | CC_SRC = ((int64_t)r1 != ((int64_t)r0 >> 63)); | |
3285 | } | |
3286 | ||
3287 | void helper_divq_EAX_T0(void) | |
3288 | { | |
3289 | uint64_t r0, r1; | |
3290 | if (T0 == 0) { | |
3291 | raise_exception(EXCP00_DIVZ); | |
3292 | } | |
3293 | r0 = EAX; | |
3294 | r1 = EDX; | |
3295 | div64(&r0, &r1, T0); | |
3296 | EAX = r0; | |
3297 | EDX = r1; | |
3298 | } | |
3299 | ||
3300 | void helper_idivq_EAX_T0(void) | |
3301 | { | |
3302 | uint64_t r0, r1; | |
3303 | if (T0 == 0) { | |
3304 | raise_exception(EXCP00_DIVZ); | |
3305 | } | |
3306 | r0 = EAX; | |
3307 | r1 = EDX; | |
3308 | idiv64(&r0, &r1, T0); | |
3309 | EAX = r0; | |
3310 | EDX = r1; | |
3311 | } | |
3312 | ||
3313 | #endif | |
3314 | ||
664e0f19 FB |
3315 | float approx_rsqrt(float a) |
3316 | { | |
3317 | return 1.0 / sqrt(a); | |
3318 | } | |
3319 | ||
3320 | float approx_rcp(float a) | |
3321 | { | |
3322 | return 1.0 / a; | |
3323 | } | |
3324 | ||
7a0e1f41 | 3325 | void update_fp_status(void) |
4d6b6c0a | 3326 | { |
7a0e1f41 | 3327 | int rnd_type; |
4d6b6c0a | 3328 | |
7a0e1f41 FB |
3329 | /* set rounding mode */ |
3330 | switch(env->fpuc & RC_MASK) { | |
3331 | default: | |
3332 | case RC_NEAR: | |
3333 | rnd_type = float_round_nearest_even; | |
3334 | break; | |
3335 | case RC_DOWN: | |
3336 | rnd_type = float_round_down; | |
3337 | break; | |
3338 | case RC_UP: | |
3339 | rnd_type = float_round_up; | |
3340 | break; | |
3341 | case RC_CHOP: | |
3342 | rnd_type = float_round_to_zero; | |
3343 | break; | |
3344 | } | |
3345 | set_float_rounding_mode(rnd_type, &env->fp_status); | |
3346 | #ifdef FLOATX80 | |
3347 | switch((env->fpuc >> 8) & 3) { | |
3348 | case 0: | |
3349 | rnd_type = 32; | |
3350 | break; | |
3351 | case 2: | |
3352 | rnd_type = 64; | |
3353 | break; | |
3354 | case 3: | |
3355 | default: | |
3356 | rnd_type = 80; | |
3357 | break; | |
3358 | } | |
3359 | set_floatx80_rounding_precision(rnd_type, &env->fp_status); | |
4d6b6c0a | 3360 | #endif |
7a0e1f41 | 3361 | } |
664e0f19 | 3362 | |
61382a50 FB |
3363 | #if !defined(CONFIG_USER_ONLY) |
3364 | ||
3365 | #define MMUSUFFIX _mmu | |
3366 | #define GETPC() (__builtin_return_address(0)) | |
3367 | ||
2c0262af FB |
3368 | #define SHIFT 0 |
3369 | #include "softmmu_template.h" | |
3370 | ||
3371 | #define SHIFT 1 | |
3372 | #include "softmmu_template.h" | |
3373 | ||
3374 | #define SHIFT 2 | |
3375 | #include "softmmu_template.h" | |
3376 | ||
3377 | #define SHIFT 3 | |
3378 | #include "softmmu_template.h" | |
3379 | ||
61382a50 FB |
3380 | #endif |
3381 | ||
3382 | /* try to fill the TLB and return an exception if error. If retaddr is | |
3383 | NULL, it means that the function was called in C code (i.e. not | |
3384 | from generated code or from helper.c) */ | |
3385 | /* XXX: fix it to restore all registers */ | |
14ce26e7 | 3386 | void tlb_fill(target_ulong addr, int is_write, int is_user, void *retaddr) |
2c0262af FB |
3387 | { |
3388 | TranslationBlock *tb; | |
3389 | int ret; | |
3390 | unsigned long pc; | |
61382a50 FB |
3391 | CPUX86State *saved_env; |
3392 | ||
3393 | /* XXX: hack to restore env in all cases, even if not called from | |
3394 | generated code */ | |
3395 | saved_env = env; | |
3396 | env = cpu_single_env; | |
61382a50 FB |
3397 | |
3398 | ret = cpu_x86_handle_mmu_fault(env, addr, is_write, is_user, 1); | |
2c0262af | 3399 | if (ret) { |
61382a50 FB |
3400 | if (retaddr) { |
3401 | /* now we have a real cpu fault */ | |
3402 | pc = (unsigned long)retaddr; | |
3403 | tb = tb_find_pc(pc); | |
3404 | if (tb) { | |
3405 | /* the PC is inside the translated code. It means that we have | |
3406 | a virtual CPU fault */ | |
58fe2f10 | 3407 | cpu_restore_state(tb, env, pc, NULL); |
61382a50 | 3408 | } |
2c0262af | 3409 | } |
0d1a29f9 FB |
3410 | if (retaddr) |
3411 | raise_exception_err(EXCP0E_PAGE, env->error_code); | |
3412 | else | |
3413 | raise_exception_err_norestore(EXCP0E_PAGE, env->error_code); | |
2c0262af | 3414 | } |
61382a50 | 3415 | env = saved_env; |
2c0262af | 3416 | } |