[mirror_qemu.git] / target-i386 / int_helper.c

/*
 *  x86 integer helpers
 *
 *  Copyright (c) 2003 Fabrice Bellard
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
 */

#include "qemu/osdep.h"
#include "cpu.h"
#include "exec/exec-all.h"
#include "qemu/host-utils.h"
#include "exec/helper-proto.h"

//#define DEBUG_MULDIV

/* modulo 9 table */
static const uint8_t rclb_table[32] = {
    0, 1, 2, 3, 4, 5, 6, 7,
    8, 0, 1, 2, 3, 4, 5, 6,
    7, 8, 0, 1, 2, 3, 4, 5,
    6, 7, 8, 0, 1, 2, 3, 4,
};

/* modulo 17 table */
static const uint8_t rclw_table[32] = {
    0, 1, 2, 3, 4, 5, 6, 7,
    8, 9, 10, 11, 12, 13, 14, 15,
    16, 0, 1, 2, 3, 4, 5, 6,
    7, 8, 9, 10, 11, 12, 13, 14,
};

/* division, flags are undefined */

void helper_divb_AL(CPUX86State *env, target_ulong t0)
{
    unsigned int num, den, q, r;

    num = (env->regs[R_EAX] & 0xffff);
    den = (t0 & 0xff);
    if (den == 0) {
        raise_exception_ra(env, EXCP00_DIVZ, GETPC());
    }
    q = (num / den);
    if (q > 0xff) {
        raise_exception_ra(env, EXCP00_DIVZ, GETPC());
    }
    q &= 0xff;
    r = (num % den) & 0xff;
    env->regs[R_EAX] = (env->regs[R_EAX] & ~0xffff) | (r << 8) | q;
}

void helper_idivb_AL(CPUX86State *env, target_ulong t0)
{
    int num, den, q, r;

    num = (int16_t)env->regs[R_EAX];
    den = (int8_t)t0;
    if (den == 0) {
        raise_exception_ra(env, EXCP00_DIVZ, GETPC());
    }
    q = (num / den);
    if (q != (int8_t)q) {
        raise_exception_ra(env, EXCP00_DIVZ, GETPC());
    }
    q &= 0xff;
    r = (num % den) & 0xff;
    env->regs[R_EAX] = (env->regs[R_EAX] & ~0xffff) | (r << 8) | q;
}

void helper_divw_AX(CPUX86State *env, target_ulong t0)
{
    unsigned int num, den, q, r;

    num = (env->regs[R_EAX] & 0xffff) | ((env->regs[R_EDX] & 0xffff) << 16);
    den = (t0 & 0xffff);
    if (den == 0) {
        raise_exception_ra(env, EXCP00_DIVZ, GETPC());
    }
    q = (num / den);
    if (q > 0xffff) {
        raise_exception_ra(env, EXCP00_DIVZ, GETPC());
    }
    q &= 0xffff;
    r = (num % den) & 0xffff;
    env->regs[R_EAX] = (env->regs[R_EAX] & ~0xffff) | q;
    env->regs[R_EDX] = (env->regs[R_EDX] & ~0xffff) | r;
}

void helper_idivw_AX(CPUX86State *env, target_ulong t0)
{
    int num, den, q, r;

    num = (env->regs[R_EAX] & 0xffff) | ((env->regs[R_EDX] & 0xffff) << 16);
    den = (int16_t)t0;
    if (den == 0) {
        raise_exception_ra(env, EXCP00_DIVZ, GETPC());
    }
    q = (num / den);
    if (q != (int16_t)q) {
        raise_exception_ra(env, EXCP00_DIVZ, GETPC());
    }
    q &= 0xffff;
    r = (num % den) & 0xffff;
    env->regs[R_EAX] = (env->regs[R_EAX] & ~0xffff) | q;
    env->regs[R_EDX] = (env->regs[R_EDX] & ~0xffff) | r;
}

void helper_divl_EAX(CPUX86State *env, target_ulong t0)
{
    unsigned int den, r;
    uint64_t num, q;

    num = ((uint32_t)env->regs[R_EAX]) | ((uint64_t)((uint32_t)env->regs[R_EDX]) << 32);
    den = t0;
    if (den == 0) {
        raise_exception_ra(env, EXCP00_DIVZ, GETPC());
    }
    q = (num / den);
    r = (num % den);
    if (q > 0xffffffff) {
        raise_exception_ra(env, EXCP00_DIVZ, GETPC());
    }
    env->regs[R_EAX] = (uint32_t)q;
    env->regs[R_EDX] = (uint32_t)r;
}

void helper_idivl_EAX(CPUX86State *env, target_ulong t0)
{
    int den, r;
    int64_t num, q;

    num = ((uint32_t)env->regs[R_EAX]) | ((uint64_t)((uint32_t)env->regs[R_EDX]) << 32);
    den = t0;
    if (den == 0) {
        raise_exception_ra(env, EXCP00_DIVZ, GETPC());
    }
    q = (num / den);
    r = (num % den);
    if (q != (int32_t)q) {
        raise_exception_ra(env, EXCP00_DIVZ, GETPC());
    }
    env->regs[R_EAX] = (uint32_t)q;
    env->regs[R_EDX] = (uint32_t)r;
}

/* bcd */

/* XXX: exception */
void helper_aam(CPUX86State *env, int base)
{
    int al, ah;

    al = env->regs[R_EAX] & 0xff;
    ah = al / base;
    al = al % base;
    env->regs[R_EAX] = (env->regs[R_EAX] & ~0xffff) | al | (ah << 8);
    CC_DST = al;
}

void helper_aad(CPUX86State *env, int base)
{
    int al, ah;

    al = env->regs[R_EAX] & 0xff;
    ah = (env->regs[R_EAX] >> 8) & 0xff;
    al = ((ah * base) + al) & 0xff;
    env->regs[R_EAX] = (env->regs[R_EAX] & ~0xffff) | al;
    CC_DST = al;
}

void helper_aaa(CPUX86State *env)
{
    int icarry;
    int al, ah, af;
    int eflags;

    eflags = cpu_cc_compute_all(env, CC_OP);
    af = eflags & CC_A;
    al = env->regs[R_EAX] & 0xff;
    ah = (env->regs[R_EAX] >> 8) & 0xff;

    icarry = (al > 0xf9);
    if (((al & 0x0f) > 9) || af) {
        al = (al + 6) & 0x0f;
        ah = (ah + 1 + icarry) & 0xff;
        eflags |= CC_C | CC_A;
    } else {
        eflags &= ~(CC_C | CC_A);
        al &= 0x0f;
    }
    env->regs[R_EAX] = (env->regs[R_EAX] & ~0xffff) | al | (ah << 8);
    CC_SRC = eflags;
}

void helper_aas(CPUX86State *env)
{
    int icarry;
    int al, ah, af;
    int eflags;

    eflags = cpu_cc_compute_all(env, CC_OP);
    af = eflags & CC_A;
    al = env->regs[R_EAX] & 0xff;
    ah = (env->regs[R_EAX] >> 8) & 0xff;

    icarry = (al < 6);
    if (((al & 0x0f) > 9) || af) {
        al = (al - 6) & 0x0f;
        ah = (ah - 1 - icarry) & 0xff;
        eflags |= CC_C | CC_A;
    } else {
        eflags &= ~(CC_C | CC_A);
        al &= 0x0f;
    }
    env->regs[R_EAX] = (env->regs[R_EAX] & ~0xffff) | al | (ah << 8);
    CC_SRC = eflags;
}

void helper_daa(CPUX86State *env)
{
    int old_al, al, af, cf;
    int eflags;

    eflags = cpu_cc_compute_all(env, CC_OP);
    cf = eflags & CC_C;
    af = eflags & CC_A;
    old_al = al = env->regs[R_EAX] & 0xff;

    eflags = 0;
    if (((al & 0x0f) > 9) || af) {
        al = (al + 6) & 0xff;
        eflags |= CC_A;
    }
    if ((old_al > 0x99) || cf) {
        al = (al + 0x60) & 0xff;
        eflags |= CC_C;
    }
    env->regs[R_EAX] = (env->regs[R_EAX] & ~0xff) | al;
    /* well, speed is not an issue here, so we compute the flags by hand */
    eflags |= (al == 0) << 6; /* zf */
    eflags |= parity_table[al]; /* pf */
    eflags |= (al & 0x80); /* sf */
    CC_SRC = eflags;
}

void helper_das(CPUX86State *env)
{
    int al, al1, af, cf;
    int eflags;

    eflags = cpu_cc_compute_all(env, CC_OP);
    cf = eflags & CC_C;
    af = eflags & CC_A;
    al = env->regs[R_EAX] & 0xff;

    eflags = 0;
    al1 = al;
    if (((al & 0x0f) > 9) || af) {
        eflags |= CC_A;
        if (al < 6 || cf) {
            eflags |= CC_C;
        }
        al = (al - 6) & 0xff;
    }
    if ((al1 > 0x99) || cf) {
        al = (al - 0x60) & 0xff;
        eflags |= CC_C;
    }
    env->regs[R_EAX] = (env->regs[R_EAX] & ~0xff) | al;
    /* well, speed is not an issue here, so we compute the flags by hand */
    eflags |= (al == 0) << 6; /* zf */
    eflags |= parity_table[al]; /* pf */
    eflags |= (al & 0x80); /* sf */
    CC_SRC = eflags;
}

#ifdef TARGET_X86_64
static void add128(uint64_t *plow, uint64_t *phigh, uint64_t a, uint64_t b)
{
    *plow += a;
    /* carry test */
    if (*plow < a) {
        (*phigh)++;
    }
    *phigh += b;
}

static void neg128(uint64_t *plow, uint64_t *phigh)
{
    *plow = ~*plow;
    *phigh = ~*phigh;
    add128(plow, phigh, 1, 0);
}

/* return TRUE if overflow */
static int div64(uint64_t *plow, uint64_t *phigh, uint64_t b)
{
    uint64_t q, r, a1, a0;
    int i, qb, ab;

    a0 = *plow;
    a1 = *phigh;
    if (a1 == 0) {
        q = a0 / b;
        r = a0 % b;
        *plow = q;
        *phigh = r;
    } else {
        if (a1 >= b) {
            return 1;
        }
        /* XXX: use a better algorithm */
        for (i = 0; i < 64; i++) {
            ab = a1 >> 63;
            a1 = (a1 << 1) | (a0 >> 63);
            if (ab || a1 >= b) {
                a1 -= b;
                qb = 1;
            } else {
                qb = 0;
            }
            a0 = (a0 << 1) | qb;
        }
#if defined(DEBUG_MULDIV)
        printf("div: 0x%016" PRIx64 "%016" PRIx64 " / 0x%016" PRIx64
               ": q=0x%016" PRIx64 " r=0x%016" PRIx64 "\n",
               *phigh, *plow, b, a0, a1);
#endif
        *plow = a0;
        *phigh = a1;
    }
    return 0;
}

/* return TRUE if overflow */
static int idiv64(uint64_t *plow, uint64_t *phigh, int64_t b)
{
    int sa, sb;

    sa = ((int64_t)*phigh < 0);
    if (sa) {
        neg128(plow, phigh);
    }
    sb = (b < 0);
    if (sb) {
        b = -b;
    }
    if (div64(plow, phigh, b) != 0) {
        return 1;
    }
    if (sa ^ sb) {
        if (*plow > (1ULL << 63)) {
            return 1;
        }
        *plow = -*plow;
    } else {
        if (*plow >= (1ULL << 63)) {
            return 1;
        }
    }
    if (sa) {
        *phigh = -*phigh;
    }
    return 0;
}

void helper_divq_EAX(CPUX86State *env, target_ulong t0)
{
    uint64_t r0, r1;

    if (t0 == 0) {
        raise_exception_ra(env, EXCP00_DIVZ, GETPC());
    }
    r0 = env->regs[R_EAX];
    r1 = env->regs[R_EDX];
    if (div64(&r0, &r1, t0)) {
        raise_exception_ra(env, EXCP00_DIVZ, GETPC());
    }
    env->regs[R_EAX] = r0;
    env->regs[R_EDX] = r1;
}

void helper_idivq_EAX(CPUX86State *env, target_ulong t0)
{
    uint64_t r0, r1;

    if (t0 == 0) {
        raise_exception_ra(env, EXCP00_DIVZ, GETPC());
    }
    r0 = env->regs[R_EAX];
    r1 = env->regs[R_EDX];
    if (idiv64(&r0, &r1, t0)) {
        raise_exception_ra(env, EXCP00_DIVZ, GETPC());
    }
    env->regs[R_EAX] = r0;
    env->regs[R_EDX] = r1;
}
#endif

#if TARGET_LONG_BITS == 32
# define ctztl  ctz32
# define clztl  clz32
#else
# define ctztl  ctz64
# define clztl  clz64
#endif

/* bit operations */
target_ulong helper_ctz(target_ulong t0)
{
    return ctztl(t0);
}

target_ulong helper_clz(target_ulong t0)
{
    return clztl(t0);
}

target_ulong helper_pdep(target_ulong src, target_ulong mask)
{
    target_ulong dest = 0;
    int i, o;

    for (i = 0; mask != 0; i++) {
        o = ctztl(mask);
        mask &= mask - 1;
        dest |= ((src >> i) & 1) << o;
    }
    return dest;
}

target_ulong helper_pext(target_ulong src, target_ulong mask)
{
    target_ulong dest = 0;
    int i, o;

    for (o = 0; mask != 0; o++) {
        i = ctztl(mask);
        mask &= mask - 1;
        dest |= ((src >> i) & 1) << o;
    }
    return dest;
}

#define SHIFT 0
#include "shift_helper_template.h"
#undef SHIFT

#define SHIFT 1
#include "shift_helper_template.h"
#undef SHIFT

#define SHIFT 2
#include "shift_helper_template.h"
#undef SHIFT

#ifdef TARGET_X86_64
#define SHIFT 3
#include "shift_helper_template.h"
#undef SHIFT
#endif

/* Test that BIT is enabled in CR4.  If not, raise an illegal opcode
   exception.  This reduces the requirements for rare CR4 bits being
   mapped into HFLAGS.  */
void helper_cr4_testbit(CPUX86State *env, uint32_t bit)
{
    if (unlikely((env->cr[4] & bit) == 0)) {
        raise_exception_ra(env, EXCP06_ILLOP, GETPC());
    }
}
Commit	Line	Data
d7582078 BS	1	/*
	2	* x86 integer helpers
	3	*
	4	* Copyright (c) 2003 Fabrice Bellard
	5	*
	6	* This library is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU Lesser General Public
	8	* License as published by the Free Software Foundation; either
	9	* version 2 of the License, or (at your option) any later version.
	10	*
	11	* This library is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	14	* Lesser General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU Lesser General Public
	17	* License along with this library; if not, see <http://www.gnu.org/licenses/>.
	18	*/
	19
b6a0aa05	20	#include "qemu/osdep.h"
d7582078	21	#include "cpu.h"
63c91552	22	#include "exec/exec-all.h"
1de7afc9	23	#include "qemu/host-utils.h"
2ef6175a	24	#include "exec/helper-proto.h"
d7582078 BS	25
	26	//#define DEBUG_MULDIV
	27
	28	/* modulo 9 table */
	29	static const uint8_t rclb_table[32] = {
	30	0, 1, 2, 3, 4, 5, 6, 7,
	31	8, 0, 1, 2, 3, 4, 5, 6,
	32	7, 8, 0, 1, 2, 3, 4, 5,
	33	6, 7, 8, 0, 1, 2, 3, 4,
	34	};
	35
	36	/* modulo 17 table */
	37	static const uint8_t rclw_table[32] = {
	38	0, 1, 2, 3, 4, 5, 6, 7,
	39	8, 9, 10, 11, 12, 13, 14, 15,
	40	16, 0, 1, 2, 3, 4, 5, 6,
	41	7, 8, 9, 10, 11, 12, 13, 14,
	42	};
	43
	44	/* division, flags are undefined */
	45
7923057b	46	void helper_divb_AL(CPUX86State *env, target_ulong t0)
d7582078 BS	47	{
	48	unsigned int num, den, q, r;
	49
4b34e3ad	50	num = (env->regs[R_EAX] & 0xffff);
d7582078 BS	51	den = (t0 & 0xff);
d7582078 BS	52	if (den == 0) {
cc33c5d6	53	raise_exception_ra(env, EXCP00_DIVZ, GETPC());
d7582078 BS	54	}
	55	q = (num / den);
	56	if (q > 0xff) {
cc33c5d6	57	raise_exception_ra(env, EXCP00_DIVZ, GETPC());
d7582078 BS	58	}
	59	q &= 0xff;
	60	r = (num % den) & 0xff;
4b34e3ad	61	env->regs[R_EAX] = (env->regs[R_EAX] & ~0xffff) \| (r << 8) \| q;
d7582078 BS	62	}
d7582078 BS	63
7923057b	64	void helper_idivb_AL(CPUX86State *env, target_ulong t0)
d7582078 BS	65	{
	66	int num, den, q, r;
	67
4b34e3ad	68	num = (int16_t)env->regs[R_EAX];
d7582078 BS	69	den = (int8_t)t0;
d7582078 BS	70	if (den == 0) {
cc33c5d6	71	raise_exception_ra(env, EXCP00_DIVZ, GETPC());
d7582078 BS	72	}
	73	q = (num / den);
	74	if (q != (int8_t)q) {
cc33c5d6	75	raise_exception_ra(env, EXCP00_DIVZ, GETPC());
d7582078 BS	76	}
	77	q &= 0xff;
	78	r = (num % den) & 0xff;
4b34e3ad	79	env->regs[R_EAX] = (env->regs[R_EAX] & ~0xffff) \| (r << 8) \| q;
d7582078 BS	80	}
d7582078 BS	81
7923057b	82	void helper_divw_AX(CPUX86State *env, target_ulong t0)
d7582078 BS	83	{
	84	unsigned int num, den, q, r;
	85
00f5e6f2	86	num = (env->regs[R_EAX] & 0xffff) \| ((env->regs[R_EDX] & 0xffff) << 16);
d7582078 BS	87	den = (t0 & 0xffff);
d7582078 BS	88	if (den == 0) {
cc33c5d6	89	raise_exception_ra(env, EXCP00_DIVZ, GETPC());
d7582078 BS	90	}
	91	q = (num / den);
	92	if (q > 0xffff) {
cc33c5d6	93	raise_exception_ra(env, EXCP00_DIVZ, GETPC());
d7582078 BS	94	}
	95	q &= 0xffff;
	96	r = (num % den) & 0xffff;
4b34e3ad	97	env->regs[R_EAX] = (env->regs[R_EAX] & ~0xffff) \| q;
00f5e6f2	98	env->regs[R_EDX] = (env->regs[R_EDX] & ~0xffff) \| r;
d7582078 BS	99	}
d7582078 BS	100
7923057b	101	void helper_idivw_AX(CPUX86State *env, target_ulong t0)
d7582078 BS	102	{
	103	int num, den, q, r;
	104
00f5e6f2	105	num = (env->regs[R_EAX] & 0xffff) \| ((env->regs[R_EDX] & 0xffff) << 16);
d7582078 BS	106	den = (int16_t)t0;
d7582078 BS	107	if (den == 0) {
cc33c5d6	108	raise_exception_ra(env, EXCP00_DIVZ, GETPC());
d7582078 BS	109	}
	110	q = (num / den);
	111	if (q != (int16_t)q) {
cc33c5d6	112	raise_exception_ra(env, EXCP00_DIVZ, GETPC());
d7582078 BS	113	}
	114	q &= 0xffff;
	115	r = (num % den) & 0xffff;
4b34e3ad	116	env->regs[R_EAX] = (env->regs[R_EAX] & ~0xffff) \| q;
00f5e6f2	117	env->regs[R_EDX] = (env->regs[R_EDX] & ~0xffff) \| r;
d7582078 BS	118	}
d7582078 BS	119
7923057b	120	void helper_divl_EAX(CPUX86State *env, target_ulong t0)
d7582078 BS	121	{
	122	unsigned int den, r;
	123	uint64_t num, q;
	124
00f5e6f2	125	num = ((uint32_t)env->regs[R_EAX]) \| ((uint64_t)((uint32_t)env->regs[R_EDX]) << 32);
d7582078 BS	126	den = t0;
d7582078 BS	127	if (den == 0) {
cc33c5d6	128	raise_exception_ra(env, EXCP00_DIVZ, GETPC());
d7582078 BS	129	}
	130	q = (num / den);
	131	r = (num % den);
	132	if (q > 0xffffffff) {
cc33c5d6	133	raise_exception_ra(env, EXCP00_DIVZ, GETPC());
d7582078	134	}
4b34e3ad	135	env->regs[R_EAX] = (uint32_t)q;
00f5e6f2	136	env->regs[R_EDX] = (uint32_t)r;
d7582078 BS	137	}
d7582078 BS	138
7923057b	139	void helper_idivl_EAX(CPUX86State *env, target_ulong t0)
d7582078 BS	140	{
	141	int den, r;
	142	int64_t num, q;
	143
00f5e6f2	144	num = ((uint32_t)env->regs[R_EAX]) \| ((uint64_t)((uint32_t)env->regs[R_EDX]) << 32);
d7582078 BS	145	den = t0;
d7582078 BS	146	if (den == 0) {
cc33c5d6	147	raise_exception_ra(env, EXCP00_DIVZ, GETPC());
d7582078 BS	148	}
	149	q = (num / den);
	150	r = (num % den);
	151	if (q != (int32_t)q) {
cc33c5d6	152	raise_exception_ra(env, EXCP00_DIVZ, GETPC());
d7582078	153	}
4b34e3ad	154	env->regs[R_EAX] = (uint32_t)q;
00f5e6f2	155	env->regs[R_EDX] = (uint32_t)r;
d7582078 BS	156	}
	157
	158	/* bcd */
	159
	160	/* XXX: exception */
7923057b	161	void helper_aam(CPUX86State *env, int base)
d7582078 BS	162	{
	163	int al, ah;
	164
4b34e3ad	165	al = env->regs[R_EAX] & 0xff;
d7582078 BS	166	ah = al / base;
d7582078 BS	167	al = al % base;
4b34e3ad	168	env->regs[R_EAX] = (env->regs[R_EAX] & ~0xffff) \| al \| (ah << 8);
d7582078 BS	169	CC_DST = al;
	170	}
	171
7923057b	172	void helper_aad(CPUX86State *env, int base)
d7582078 BS	173	{
	174	int al, ah;
	175
4b34e3ad LG	176	al = env->regs[R_EAX] & 0xff;
4b34e3ad LG	177	ah = (env->regs[R_EAX] >> 8) & 0xff;
d7582078	178	al = ((ah * base) + al) & 0xff;
4b34e3ad	179	env->regs[R_EAX] = (env->regs[R_EAX] & ~0xffff) \| al;
d7582078 BS	180	CC_DST = al;
	181	}
	182
7923057b	183	void helper_aaa(CPUX86State *env)
d7582078 BS	184	{
	185	int icarry;
	186	int al, ah, af;
	187	int eflags;
	188
f0967a1a	189	eflags = cpu_cc_compute_all(env, CC_OP);
d7582078	190	af = eflags & CC_A;
4b34e3ad LG	191	al = env->regs[R_EAX] & 0xff;
4b34e3ad LG	192	ah = (env->regs[R_EAX] >> 8) & 0xff;
d7582078 BS	193
	194	icarry = (al > 0xf9);
	195	if (((al & 0x0f) > 9) \|\| af) {
	196	al = (al + 6) & 0x0f;
	197	ah = (ah + 1 + icarry) & 0xff;
	198	eflags \|= CC_C \| CC_A;
	199	} else {
	200	eflags &= ~(CC_C \| CC_A);
	201	al &= 0x0f;
	202	}
4b34e3ad	203	env->regs[R_EAX] = (env->regs[R_EAX] & ~0xffff) \| al \| (ah << 8);
d7582078 BS	204	CC_SRC = eflags;
	205	}
	206
7923057b	207	void helper_aas(CPUX86State *env)
d7582078 BS	208	{
	209	int icarry;
	210	int al, ah, af;
	211	int eflags;
	212
f0967a1a	213	eflags = cpu_cc_compute_all(env, CC_OP);
d7582078	214	af = eflags & CC_A;
4b34e3ad LG	215	al = env->regs[R_EAX] & 0xff;
4b34e3ad LG	216	ah = (env->regs[R_EAX] >> 8) & 0xff;
d7582078 BS	217
	218	icarry = (al < 6);
	219	if (((al & 0x0f) > 9) \|\| af) {
	220	al = (al - 6) & 0x0f;
	221	ah = (ah - 1 - icarry) & 0xff;
	222	eflags \|= CC_C \| CC_A;
	223	} else {
	224	eflags &= ~(CC_C \| CC_A);
	225	al &= 0x0f;
	226	}
4b34e3ad	227	env->regs[R_EAX] = (env->regs[R_EAX] & ~0xffff) \| al \| (ah << 8);
d7582078 BS	228	CC_SRC = eflags;
	229	}
	230
7923057b	231	void helper_daa(CPUX86State *env)
d7582078 BS	232	{
	233	int old_al, al, af, cf;
	234	int eflags;
	235
f0967a1a	236	eflags = cpu_cc_compute_all(env, CC_OP);
d7582078 BS	237	cf = eflags & CC_C;
d7582078 BS	238	af = eflags & CC_A;
4b34e3ad	239	old_al = al = env->regs[R_EAX] & 0xff;
d7582078 BS	240
	241	eflags = 0;
	242	if (((al & 0x0f) > 9) \|\| af) {
	243	al = (al + 6) & 0xff;
	244	eflags \|= CC_A;
	245	}
	246	if ((old_al > 0x99) \|\| cf) {
	247	al = (al + 0x60) & 0xff;
	248	eflags \|= CC_C;
	249	}
4b34e3ad	250	env->regs[R_EAX] = (env->regs[R_EAX] & ~0xff) \| al;
d7582078 BS	251	/* well, speed is not an issue here, so we compute the flags by hand */
	252	eflags \|= (al == 0) << 6; /* zf */
	253	eflags \|= parity_table[al]; /* pf */
	254	eflags \|= (al & 0x80); /* sf */
	255	CC_SRC = eflags;
	256	}
	257
7923057b	258	void helper_das(CPUX86State *env)
d7582078 BS	259	{
	260	int al, al1, af, cf;
	261	int eflags;
	262
f0967a1a	263	eflags = cpu_cc_compute_all(env, CC_OP);
d7582078 BS	264	cf = eflags & CC_C;
d7582078 BS	265	af = eflags & CC_A;
4b34e3ad	266	al = env->regs[R_EAX] & 0xff;
d7582078 BS	267
	268	eflags = 0;
	269	al1 = al;
	270	if (((al & 0x0f) > 9) \|\| af) {
	271	eflags \|= CC_A;
	272	if (al < 6 \|\| cf) {
	273	eflags \|= CC_C;
	274	}
	275	al = (al - 6) & 0xff;
	276	}
	277	if ((al1 > 0x99) \|\| cf) {
	278	al = (al - 0x60) & 0xff;
	279	eflags \|= CC_C;
	280	}
4b34e3ad	281	env->regs[R_EAX] = (env->regs[R_EAX] & ~0xff) \| al;
d7582078 BS	282	/* well, speed is not an issue here, so we compute the flags by hand */
	283	eflags \|= (al == 0) << 6; /* zf */
	284	eflags \|= parity_table[al]; /* pf */
	285	eflags \|= (al & 0x80); /* sf */
	286	CC_SRC = eflags;
	287	}
	288
	289	#ifdef TARGET_X86_64
	290	static void add128(uint64_t plow, uint64_t phigh, uint64_t a, uint64_t b)
	291	{
	292	*plow += a;
	293	/* carry test */
	294	if (*plow < a) {
	295	(*phigh)++;
	296	}
	297	*phigh += b;
	298	}
	299
	300	static void neg128(uint64_t plow, uint64_t phigh)
	301	{
	302	plow = ~plow;
	303	phigh = ~phigh;
	304	add128(plow, phigh, 1, 0);
	305	}
	306
	307	/* return TRUE if overflow */
	308	static int div64(uint64_t plow, uint64_t phigh, uint64_t b)
	309	{
	310	uint64_t q, r, a1, a0;
	311	int i, qb, ab;
	312
	313	a0 = *plow;
	314	a1 = *phigh;
	315	if (a1 == 0) {
	316	q = a0 / b;
	317	r = a0 % b;
	318	*plow = q;
	319	*phigh = r;
	320	} else {
	321	if (a1 >= b) {
	322	return 1;
	323	}
	324	/* XXX: use a better algorithm */
	325	for (i = 0; i < 64; i++) {
	326	ab = a1 >> 63;
	327	a1 = (a1 << 1) \| (a0 >> 63);
	328	if (ab \|\| a1 >= b) {
	329	a1 -= b;
	330	qb = 1;
	331	} else {
	332	qb = 0;
	333	}
	334	a0 = (a0 << 1) \| qb;
	335	}
	336	#if defined(DEBUG_MULDIV)
	337	printf("div: 0x%016" PRIx64 "%016" PRIx64 " / 0x%016" PRIx64
	338	": q=0x%016" PRIx64 " r=0x%016" PRIx64 "\n",
	339	phigh, plow, b, a0, a1);
	340	#endif
	341	*plow = a0;
	342	*phigh = a1;
	343	}
	344	return 0;
	345	}
346
347	/* return TRUE if overflow */
348	static int idiv64(uint64_t plow, uint64_t phigh, int64_t b)
349	{
350	int sa, sb;
351
352	sa = ((int64_t)*phigh < 0);
353	if (sa) {
354	neg128(plow, phigh);
355	}
356	sb = (b < 0);
357	if (sb) {
358	b = -b;
359	}
360	if (div64(plow, phigh, b) != 0) {
361	return 1;
362	}
363	if (sa ^ sb) {
364	if (*plow > (1ULL << 63)) {
365	return 1;
366	}
367	plow = -plow;
368	} else {
369	if (*plow >= (1ULL << 63)) {
370	return 1;
371	}
372	}
373	if (sa) {
374	phigh = -phigh;
375	}
376	return 0;
377	}
378
7923057b	379	void helper_divq_EAX(CPUX86State *env, target_ulong t0)
d7582078 BS	380	{
	381	uint64_t r0, r1;
	382
	383	if (t0 == 0) {
cc33c5d6	384	raise_exception_ra(env, EXCP00_DIVZ, GETPC());
d7582078	385	}
4b34e3ad	386	r0 = env->regs[R_EAX];
00f5e6f2	387	r1 = env->regs[R_EDX];
d7582078	388	if (div64(&r0, &r1, t0)) {
cc33c5d6	389	raise_exception_ra(env, EXCP00_DIVZ, GETPC());
d7582078	390	}
4b34e3ad	391	env->regs[R_EAX] = r0;
00f5e6f2	392	env->regs[R_EDX] = r1;
d7582078 BS	393	}
d7582078 BS	394
7923057b	395	void helper_idivq_EAX(CPUX86State *env, target_ulong t0)
d7582078 BS	396	{
	397	uint64_t r0, r1;
	398
	399	if (t0 == 0) {
cc33c5d6	400	raise_exception_ra(env, EXCP00_DIVZ, GETPC());
d7582078	401	}
4b34e3ad	402	r0 = env->regs[R_EAX];
00f5e6f2	403	r1 = env->regs[R_EDX];
d7582078	404	if (idiv64(&r0, &r1, t0)) {
cc33c5d6	405	raise_exception_ra(env, EXCP00_DIVZ, GETPC());
d7582078	406	}
4b34e3ad	407	env->regs[R_EAX] = r0;
00f5e6f2	408	env->regs[R_EDX] = r1;
d7582078 BS	409	}
	410	#endif
	411
f1300734 RH	412	#if TARGET_LONG_BITS == 32
	413	# define ctztl ctz32
	414	# define clztl clz32
	415	#else
	416	# define ctztl ctz64
	417	# define clztl clz64
	418	#endif
	419
d7582078	420	/* bit operations */
321c5351	421	target_ulong helper_ctz(target_ulong t0)
d7582078	422	{
f1300734	423	return ctztl(t0);
d7582078 BS	424	}
d7582078 BS	425
321c5351	426	target_ulong helper_clz(target_ulong t0)
d7582078	427	{
321c5351	428	return clztl(t0);
d7582078 BS	429	}
d7582078 BS	430
0592f74a RH	431	target_ulong helper_pdep(target_ulong src, target_ulong mask)
	432	{
	433	target_ulong dest = 0;
	434	int i, o;
	435
	436	for (i = 0; mask != 0; i++) {
	437	o = ctztl(mask);
	438	mask &= mask - 1;
	439	dest \|= ((src >> i) & 1) << o;
	440	}
	441	return dest;
	442	}
	443
	444	target_ulong helper_pext(target_ulong src, target_ulong mask)
	445	{
	446	target_ulong dest = 0;
	447	int i, o;
	448
	449	for (o = 0; mask != 0; o++) {
	450	i = ctztl(mask);
	451	mask &= mask - 1;
	452	dest \|= ((src >> i) & 1) << o;
	453	}
	454	return dest;
	455	}
	456
d7582078 BS	457	#define SHIFT 0
	458	#include "shift_helper_template.h"
	459	#undef SHIFT
	460
	461	#define SHIFT 1
	462	#include "shift_helper_template.h"
	463	#undef SHIFT
	464
	465	#define SHIFT 2
	466	#include "shift_helper_template.h"
	467	#undef SHIFT
	468
	469	#ifdef TARGET_X86_64
	470	#define SHIFT 3
	471	#include "shift_helper_template.h"
	472	#undef SHIFT
	473	#endif
07929f2a RH	474
	475	/* Test that BIT is enabled in CR4. If not, raise an illegal opcode
	476	exception. This reduces the requirements for rare CR4 bits being
	477	mapped into HFLAGS. */
	478	void helper_cr4_testbit(CPUX86State *env, uint32_t bit)
	479	{
	480	if (unlikely((env->cr[4] & bit) == 0)) {
	481	raise_exception_ra(env, EXCP06_ILLOP, GETPC());
	482	}
	483	}