[mirror_qemu.git] / target-i386 / int_helper.c

/*
 *  x86 integer helpers
 *
 *  Copyright (c) 2003 Fabrice Bellard
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
 */

#include "qemu/osdep.h"
#include "cpu.h"
#include "qemu/host-utils.h"
#include "exec/helper-proto.h"

//#define DEBUG_MULDIV

/* modulo 9 table */
static const uint8_t rclb_table[32] = {
    0, 1, 2, 3, 4, 5, 6, 7,
    8, 0, 1, 2, 3, 4, 5, 6,
    7, 8, 0, 1, 2, 3, 4, 5,
    6, 7, 8, 0, 1, 2, 3, 4,
};

/* modulo 17 table */
static const uint8_t rclw_table[32] = {
    0, 1, 2, 3, 4, 5, 6, 7,
    8, 9, 10, 11, 12, 13, 14, 15,
    16, 0, 1, 2, 3, 4, 5, 6,
    7, 8, 9, 10, 11, 12, 13, 14,
};

/* division, flags are undefined */

void helper_divb_AL(CPUX86State *env, target_ulong t0)
{
    unsigned int num, den, q, r;

    num = (env->regs[R_EAX] & 0xffff);
    den = (t0 & 0xff);
    if (den == 0) {
        raise_exception_ra(env, EXCP00_DIVZ, GETPC());
    }
    q = (num / den);
    if (q > 0xff) {
        raise_exception_ra(env, EXCP00_DIVZ, GETPC());
    }
    q &= 0xff;
    r = (num % den) & 0xff;
    env->regs[R_EAX] = (env->regs[R_EAX] & ~0xffff) | (r << 8) | q;
}

void helper_idivb_AL(CPUX86State *env, target_ulong t0)
{
    int num, den, q, r;

    num = (int16_t)env->regs[R_EAX];
    den = (int8_t)t0;
    if (den == 0) {
        raise_exception_ra(env, EXCP00_DIVZ, GETPC());
    }
    q = (num / den);
    if (q != (int8_t)q) {
        raise_exception_ra(env, EXCP00_DIVZ, GETPC());
    }
    q &= 0xff;
    r = (num % den) & 0xff;
    env->regs[R_EAX] = (env->regs[R_EAX] & ~0xffff) | (r << 8) | q;
}

void helper_divw_AX(CPUX86State *env, target_ulong t0)
{
    unsigned int num, den, q, r;

    num = (env->regs[R_EAX] & 0xffff) | ((env->regs[R_EDX] & 0xffff) << 16);
    den = (t0 & 0xffff);
    if (den == 0) {
        raise_exception_ra(env, EXCP00_DIVZ, GETPC());
    }
    q = (num / den);
    if (q > 0xffff) {
        raise_exception_ra(env, EXCP00_DIVZ, GETPC());
    }
    q &= 0xffff;
    r = (num % den) & 0xffff;
    env->regs[R_EAX] = (env->regs[R_EAX] & ~0xffff) | q;
    env->regs[R_EDX] = (env->regs[R_EDX] & ~0xffff) | r;
}

void helper_idivw_AX(CPUX86State *env, target_ulong t0)
{
    int num, den, q, r;

    num = (env->regs[R_EAX] & 0xffff) | ((env->regs[R_EDX] & 0xffff) << 16);
    den = (int16_t)t0;
    if (den == 0) {
        raise_exception_ra(env, EXCP00_DIVZ, GETPC());
    }
    q = (num / den);
    if (q != (int16_t)q) {
        raise_exception_ra(env, EXCP00_DIVZ, GETPC());
    }
    q &= 0xffff;
    r = (num % den) & 0xffff;
    env->regs[R_EAX] = (env->regs[R_EAX] & ~0xffff) | q;
    env->regs[R_EDX] = (env->regs[R_EDX] & ~0xffff) | r;
}

void helper_divl_EAX(CPUX86State *env, target_ulong t0)
{
    unsigned int den, r;
    uint64_t num, q;

    num = ((uint32_t)env->regs[R_EAX]) | ((uint64_t)((uint32_t)env->regs[R_EDX]) << 32);
    den = t0;
    if (den == 0) {
        raise_exception_ra(env, EXCP00_DIVZ, GETPC());
    }
    q = (num / den);
    r = (num % den);
    if (q > 0xffffffff) {
        raise_exception_ra(env, EXCP00_DIVZ, GETPC());
    }
    env->regs[R_EAX] = (uint32_t)q;
    env->regs[R_EDX] = (uint32_t)r;
}

void helper_idivl_EAX(CPUX86State *env, target_ulong t0)
{
    int den, r;
    int64_t num, q;

    num = ((uint32_t)env->regs[R_EAX]) | ((uint64_t)((uint32_t)env->regs[R_EDX]) << 32);
    den = t0;
    if (den == 0) {
        raise_exception_ra(env, EXCP00_DIVZ, GETPC());
    }
    q = (num / den);
    r = (num % den);
    if (q != (int32_t)q) {
        raise_exception_ra(env, EXCP00_DIVZ, GETPC());
    }
    env->regs[R_EAX] = (uint32_t)q;
    env->regs[R_EDX] = (uint32_t)r;
}

/* bcd */

/* XXX: exception */
void helper_aam(CPUX86State *env, int base)
{
    int al, ah;

    al = env->regs[R_EAX] & 0xff;
    ah = al / base;
    al = al % base;
    env->regs[R_EAX] = (env->regs[R_EAX] & ~0xffff) | al | (ah << 8);
    CC_DST = al;
}

void helper_aad(CPUX86State *env, int base)
{
    int al, ah;

    al = env->regs[R_EAX] & 0xff;
    ah = (env->regs[R_EAX] >> 8) & 0xff;
    al = ((ah * base) + al) & 0xff;
    env->regs[R_EAX] = (env->regs[R_EAX] & ~0xffff) | al;
    CC_DST = al;
}

void helper_aaa(CPUX86State *env)
{
    int icarry;
    int al, ah, af;
    int eflags;

    eflags = cpu_cc_compute_all(env, CC_OP);
    af = eflags & CC_A;
    al = env->regs[R_EAX] & 0xff;
    ah = (env->regs[R_EAX] >> 8) & 0xff;

    icarry = (al > 0xf9);
    if (((al & 0x0f) > 9) || af) {
        al = (al + 6) & 0x0f;
        ah = (ah + 1 + icarry) & 0xff;
        eflags |= CC_C | CC_A;
    } else {
        eflags &= ~(CC_C | CC_A);
        al &= 0x0f;
    }
    env->regs[R_EAX] = (env->regs[R_EAX] & ~0xffff) | al | (ah << 8);
    CC_SRC = eflags;
}

void helper_aas(CPUX86State *env)
{
    int icarry;
    int al, ah, af;
    int eflags;

    eflags = cpu_cc_compute_all(env, CC_OP);
    af = eflags & CC_A;
    al = env->regs[R_EAX] & 0xff;
    ah = (env->regs[R_EAX] >> 8) & 0xff;

    icarry = (al < 6);
    if (((al & 0x0f) > 9) || af) {
        al = (al - 6) & 0x0f;
        ah = (ah - 1 - icarry) & 0xff;
        eflags |= CC_C | CC_A;
    } else {
        eflags &= ~(CC_C | CC_A);
        al &= 0x0f;
    }
    env->regs[R_EAX] = (env->regs[R_EAX] & ~0xffff) | al | (ah << 8);
    CC_SRC = eflags;
}

void helper_daa(CPUX86State *env)
{
    int old_al, al, af, cf;
    int eflags;

    eflags = cpu_cc_compute_all(env, CC_OP);
    cf = eflags & CC_C;
    af = eflags & CC_A;
    old_al = al = env->regs[R_EAX] & 0xff;

    eflags = 0;
    if (((al & 0x0f) > 9) || af) {
        al = (al + 6) & 0xff;
        eflags |= CC_A;
    }
    if ((old_al > 0x99) || cf) {
        al = (al + 0x60) & 0xff;
        eflags |= CC_C;
    }
    env->regs[R_EAX] = (env->regs[R_EAX] & ~0xff) | al;
    /* well, speed is not an issue here, so we compute the flags by hand */
    eflags |= (al == 0) << 6; /* zf */
    eflags |= parity_table[al]; /* pf */
    eflags |= (al & 0x80); /* sf */
    CC_SRC = eflags;
}

void helper_das(CPUX86State *env)
{
    int al, al1, af, cf;
    int eflags;

    eflags = cpu_cc_compute_all(env, CC_OP);
    cf = eflags & CC_C;
    af = eflags & CC_A;
    al = env->regs[R_EAX] & 0xff;

    eflags = 0;
    al1 = al;
    if (((al & 0x0f) > 9) || af) {
        eflags |= CC_A;
        if (al < 6 || cf) {
            eflags |= CC_C;
        }
        al = (al - 6) & 0xff;
    }
    if ((al1 > 0x99) || cf) {
        al = (al - 0x60) & 0xff;
        eflags |= CC_C;
    }
    env->regs[R_EAX] = (env->regs[R_EAX] & ~0xff) | al;
    /* well, speed is not an issue here, so we compute the flags by hand */
    eflags |= (al == 0) << 6; /* zf */
    eflags |= parity_table[al]; /* pf */
    eflags |= (al & 0x80); /* sf */
    CC_SRC = eflags;
}

#ifdef TARGET_X86_64
static void add128(uint64_t *plow, uint64_t *phigh, uint64_t a, uint64_t b)
{
    *plow += a;
    /* carry test */
    if (*plow < a) {
        (*phigh)++;
    }
    *phigh += b;
}

static void neg128(uint64_t *plow, uint64_t *phigh)
{
    *plow = ~*plow;
    *phigh = ~*phigh;
    add128(plow, phigh, 1, 0);
}

/* return TRUE if overflow */
static int div64(uint64_t *plow, uint64_t *phigh, uint64_t b)
{
    uint64_t q, r, a1, a0;
    int i, qb, ab;

    a0 = *plow;
    a1 = *phigh;
    if (a1 == 0) {
        q = a0 / b;
        r = a0 % b;
        *plow = q;
        *phigh = r;
    } else {
        if (a1 >= b) {
            return 1;
        }
        /* XXX: use a better algorithm */
        for (i = 0; i < 64; i++) {
            ab = a1 >> 63;
            a1 = (a1 << 1) | (a0 >> 63);
            if (ab || a1 >= b) {
                a1 -= b;
                qb = 1;
            } else {
                qb = 0;
            }
            a0 = (a0 << 1) | qb;
        }
#if defined(DEBUG_MULDIV)
        printf("div: 0x%016" PRIx64 "%016" PRIx64 " / 0x%016" PRIx64
               ": q=0x%016" PRIx64 " r=0x%016" PRIx64 "\n",
               *phigh, *plow, b, a0, a1);
#endif
        *plow = a0;
        *phigh = a1;
    }
    return 0;
}

/* return TRUE if overflow */
static int idiv64(uint64_t *plow, uint64_t *phigh, int64_t b)
{
    int sa, sb;

    sa = ((int64_t)*phigh < 0);
    if (sa) {
        neg128(plow, phigh);
    }
    sb = (b < 0);
    if (sb) {
        b = -b;
    }
    if (div64(plow, phigh, b) != 0) {
        return 1;
    }
    if (sa ^ sb) {
        if (*plow > (1ULL << 63)) {
            return 1;
        }
        *plow = -*plow;
    } else {
        if (*plow >= (1ULL << 63)) {
            return 1;
        }
    }
    if (sa) {
        *phigh = -*phigh;
    }
    return 0;
}

void helper_divq_EAX(CPUX86State *env, target_ulong t0)
{
    uint64_t r0, r1;

    if (t0 == 0) {
        raise_exception_ra(env, EXCP00_DIVZ, GETPC());
    }
    r0 = env->regs[R_EAX];
    r1 = env->regs[R_EDX];
    if (div64(&r0, &r1, t0)) {
        raise_exception_ra(env, EXCP00_DIVZ, GETPC());
    }
    env->regs[R_EAX] = r0;
    env->regs[R_EDX] = r1;
}

void helper_idivq_EAX(CPUX86State *env, target_ulong t0)
{
    uint64_t r0, r1;

    if (t0 == 0) {
        raise_exception_ra(env, EXCP00_DIVZ, GETPC());
    }
    r0 = env->regs[R_EAX];
    r1 = env->regs[R_EDX];
    if (idiv64(&r0, &r1, t0)) {
        raise_exception_ra(env, EXCP00_DIVZ, GETPC());
    }
    env->regs[R_EAX] = r0;
    env->regs[R_EDX] = r1;
}
#endif

#if TARGET_LONG_BITS == 32
# define ctztl  ctz32
# define clztl  clz32
#else
# define ctztl  ctz64
# define clztl  clz64
#endif

/* bit operations */
target_ulong helper_ctz(target_ulong t0)
{
    return ctztl(t0);
}

target_ulong helper_clz(target_ulong t0)
{
    return clztl(t0);
}

target_ulong helper_pdep(target_ulong src, target_ulong mask)
{
    target_ulong dest = 0;
    int i, o;

    for (i = 0; mask != 0; i++) {
        o = ctztl(mask);
        mask &= mask - 1;
        dest |= ((src >> i) & 1) << o;
    }
    return dest;
}

target_ulong helper_pext(target_ulong src, target_ulong mask)
{
    target_ulong dest = 0;
    int i, o;

    for (o = 0; mask != 0; o++) {
        i = ctztl(mask);
        mask &= mask - 1;
        dest |= ((src >> i) & 1) << o;
    }
    return dest;
}

#define SHIFT 0
#include "shift_helper_template.h"
#undef SHIFT

#define SHIFT 1
#include "shift_helper_template.h"
#undef SHIFT

#define SHIFT 2
#include "shift_helper_template.h"
#undef SHIFT

#ifdef TARGET_X86_64
#define SHIFT 3
#include "shift_helper_template.h"
#undef SHIFT
#endif

/* Test that BIT is enabled in CR4.  If not, raise an illegal opcode
   exception.  This reduces the requirements for rare CR4 bits being
   mapped into HFLAGS.  */
void helper_cr4_testbit(CPUX86State *env, uint32_t bit)
{
    if (unlikely((env->cr[4] & bit) == 0)) {
        raise_exception_ra(env, EXCP06_ILLOP, GETPC());
    }
}
Commit	Line	Data
d7582078 BS	1	/*
	2	* x86 integer helpers
	3	*
	4	* Copyright (c) 2003 Fabrice Bellard
	5	*
	6	* This library is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU Lesser General Public
	8	* License as published by the Free Software Foundation; either
	9	* version 2 of the License, or (at your option) any later version.
	10	*
	11	* This library is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	14	* Lesser General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU Lesser General Public
	17	* License along with this library; if not, see <http://www.gnu.org/licenses/>.
	18	*/
	19
b6a0aa05	20	#include "qemu/osdep.h"
d7582078	21	#include "cpu.h"
1de7afc9	22	#include "qemu/host-utils.h"
2ef6175a	23	#include "exec/helper-proto.h"
d7582078 BS	24
	25	//#define DEBUG_MULDIV
	26
	27	/* modulo 9 table */
	28	static const uint8_t rclb_table[32] = {
	29	0, 1, 2, 3, 4, 5, 6, 7,
	30	8, 0, 1, 2, 3, 4, 5, 6,
	31	7, 8, 0, 1, 2, 3, 4, 5,
	32	6, 7, 8, 0, 1, 2, 3, 4,
	33	};
	34
	35	/* modulo 17 table */
	36	static const uint8_t rclw_table[32] = {
	37	0, 1, 2, 3, 4, 5, 6, 7,
	38	8, 9, 10, 11, 12, 13, 14, 15,
	39	16, 0, 1, 2, 3, 4, 5, 6,
	40	7, 8, 9, 10, 11, 12, 13, 14,
	41	};
	42
	43	/* division, flags are undefined */
	44
7923057b	45	void helper_divb_AL(CPUX86State *env, target_ulong t0)
d7582078 BS	46	{
	47	unsigned int num, den, q, r;
	48
4b34e3ad	49	num = (env->regs[R_EAX] & 0xffff);
d7582078 BS	50	den = (t0 & 0xff);
d7582078 BS	51	if (den == 0) {
cc33c5d6	52	raise_exception_ra(env, EXCP00_DIVZ, GETPC());
d7582078 BS	53	}
	54	q = (num / den);
	55	if (q > 0xff) {
cc33c5d6	56	raise_exception_ra(env, EXCP00_DIVZ, GETPC());
d7582078 BS	57	}
	58	q &= 0xff;
	59	r = (num % den) & 0xff;
4b34e3ad	60	env->regs[R_EAX] = (env->regs[R_EAX] & ~0xffff) \| (r << 8) \| q;
d7582078 BS	61	}
d7582078 BS	62
7923057b	63	void helper_idivb_AL(CPUX86State *env, target_ulong t0)
d7582078 BS	64	{
	65	int num, den, q, r;
	66
4b34e3ad	67	num = (int16_t)env->regs[R_EAX];
d7582078 BS	68	den = (int8_t)t0;
d7582078 BS	69	if (den == 0) {
cc33c5d6	70	raise_exception_ra(env, EXCP00_DIVZ, GETPC());
d7582078 BS	71	}
	72	q = (num / den);
	73	if (q != (int8_t)q) {
cc33c5d6	74	raise_exception_ra(env, EXCP00_DIVZ, GETPC());
d7582078 BS	75	}
	76	q &= 0xff;
	77	r = (num % den) & 0xff;
4b34e3ad	78	env->regs[R_EAX] = (env->regs[R_EAX] & ~0xffff) \| (r << 8) \| q;
d7582078 BS	79	}
d7582078 BS	80
7923057b	81	void helper_divw_AX(CPUX86State *env, target_ulong t0)
d7582078 BS	82	{
	83	unsigned int num, den, q, r;
	84
00f5e6f2	85	num = (env->regs[R_EAX] & 0xffff) \| ((env->regs[R_EDX] & 0xffff) << 16);
d7582078 BS	86	den = (t0 & 0xffff);
d7582078 BS	87	if (den == 0) {
cc33c5d6	88	raise_exception_ra(env, EXCP00_DIVZ, GETPC());
d7582078 BS	89	}
	90	q = (num / den);
	91	if (q > 0xffff) {
cc33c5d6	92	raise_exception_ra(env, EXCP00_DIVZ, GETPC());
d7582078 BS	93	}
	94	q &= 0xffff;
	95	r = (num % den) & 0xffff;
4b34e3ad	96	env->regs[R_EAX] = (env->regs[R_EAX] & ~0xffff) \| q;
00f5e6f2	97	env->regs[R_EDX] = (env->regs[R_EDX] & ~0xffff) \| r;
d7582078 BS	98	}
d7582078 BS	99
7923057b	100	void helper_idivw_AX(CPUX86State *env, target_ulong t0)
d7582078 BS	101	{
	102	int num, den, q, r;
	103
00f5e6f2	104	num = (env->regs[R_EAX] & 0xffff) \| ((env->regs[R_EDX] & 0xffff) << 16);
d7582078 BS	105	den = (int16_t)t0;
d7582078 BS	106	if (den == 0) {
cc33c5d6	107	raise_exception_ra(env, EXCP00_DIVZ, GETPC());
d7582078 BS	108	}
	109	q = (num / den);
	110	if (q != (int16_t)q) {
cc33c5d6	111	raise_exception_ra(env, EXCP00_DIVZ, GETPC());
d7582078 BS	112	}
	113	q &= 0xffff;
	114	r = (num % den) & 0xffff;
4b34e3ad	115	env->regs[R_EAX] = (env->regs[R_EAX] & ~0xffff) \| q;
00f5e6f2	116	env->regs[R_EDX] = (env->regs[R_EDX] & ~0xffff) \| r;
d7582078 BS	117	}
d7582078 BS	118
7923057b	119	void helper_divl_EAX(CPUX86State *env, target_ulong t0)
d7582078 BS	120	{
	121	unsigned int den, r;
	122	uint64_t num, q;
	123
00f5e6f2	124	num = ((uint32_t)env->regs[R_EAX]) \| ((uint64_t)((uint32_t)env->regs[R_EDX]) << 32);
d7582078 BS	125	den = t0;
d7582078 BS	126	if (den == 0) {
cc33c5d6	127	raise_exception_ra(env, EXCP00_DIVZ, GETPC());
d7582078 BS	128	}
	129	q = (num / den);
	130	r = (num % den);
	131	if (q > 0xffffffff) {
cc33c5d6	132	raise_exception_ra(env, EXCP00_DIVZ, GETPC());
d7582078	133	}
4b34e3ad	134	env->regs[R_EAX] = (uint32_t)q;
00f5e6f2	135	env->regs[R_EDX] = (uint32_t)r;
d7582078 BS	136	}
d7582078 BS	137
7923057b	138	void helper_idivl_EAX(CPUX86State *env, target_ulong t0)
d7582078 BS	139	{
	140	int den, r;
	141	int64_t num, q;
	142
00f5e6f2	143	num = ((uint32_t)env->regs[R_EAX]) \| ((uint64_t)((uint32_t)env->regs[R_EDX]) << 32);
d7582078 BS	144	den = t0;
d7582078 BS	145	if (den == 0) {
cc33c5d6	146	raise_exception_ra(env, EXCP00_DIVZ, GETPC());
d7582078 BS	147	}
	148	q = (num / den);
	149	r = (num % den);
	150	if (q != (int32_t)q) {
cc33c5d6	151	raise_exception_ra(env, EXCP00_DIVZ, GETPC());
d7582078	152	}
4b34e3ad	153	env->regs[R_EAX] = (uint32_t)q;
00f5e6f2	154	env->regs[R_EDX] = (uint32_t)r;
d7582078 BS	155	}
	156
	157	/* bcd */
	158
	159	/* XXX: exception */
7923057b	160	void helper_aam(CPUX86State *env, int base)
d7582078 BS	161	{
	162	int al, ah;
	163
4b34e3ad	164	al = env->regs[R_EAX] & 0xff;
d7582078 BS	165	ah = al / base;
d7582078 BS	166	al = al % base;
4b34e3ad	167	env->regs[R_EAX] = (env->regs[R_EAX] & ~0xffff) \| al \| (ah << 8);
d7582078 BS	168	CC_DST = al;
	169	}
	170
7923057b	171	void helper_aad(CPUX86State *env, int base)
d7582078 BS	172	{
	173	int al, ah;
	174
4b34e3ad LG	175	al = env->regs[R_EAX] & 0xff;
4b34e3ad LG	176	ah = (env->regs[R_EAX] >> 8) & 0xff;
d7582078	177	al = ((ah * base) + al) & 0xff;
4b34e3ad	178	env->regs[R_EAX] = (env->regs[R_EAX] & ~0xffff) \| al;
d7582078 BS	179	CC_DST = al;
	180	}
	181
7923057b	182	void helper_aaa(CPUX86State *env)
d7582078 BS	183	{
	184	int icarry;
	185	int al, ah, af;
	186	int eflags;
	187
f0967a1a	188	eflags = cpu_cc_compute_all(env, CC_OP);
d7582078	189	af = eflags & CC_A;
4b34e3ad LG	190	al = env->regs[R_EAX] & 0xff;
4b34e3ad LG	191	ah = (env->regs[R_EAX] >> 8) & 0xff;
d7582078 BS	192
	193	icarry = (al > 0xf9);
	194	if (((al & 0x0f) > 9) \|\| af) {
	195	al = (al + 6) & 0x0f;
	196	ah = (ah + 1 + icarry) & 0xff;
	197	eflags \|= CC_C \| CC_A;
	198	} else {
	199	eflags &= ~(CC_C \| CC_A);
	200	al &= 0x0f;
	201	}
4b34e3ad	202	env->regs[R_EAX] = (env->regs[R_EAX] & ~0xffff) \| al \| (ah << 8);
d7582078 BS	203	CC_SRC = eflags;
	204	}
	205
7923057b	206	void helper_aas(CPUX86State *env)
d7582078 BS	207	{
	208	int icarry;
	209	int al, ah, af;
	210	int eflags;
	211
f0967a1a	212	eflags = cpu_cc_compute_all(env, CC_OP);
d7582078	213	af = eflags & CC_A;
4b34e3ad LG	214	al = env->regs[R_EAX] & 0xff;
4b34e3ad LG	215	ah = (env->regs[R_EAX] >> 8) & 0xff;
d7582078 BS	216
	217	icarry = (al < 6);
	218	if (((al & 0x0f) > 9) \|\| af) {
	219	al = (al - 6) & 0x0f;
	220	ah = (ah - 1 - icarry) & 0xff;
	221	eflags \|= CC_C \| CC_A;
	222	} else {
	223	eflags &= ~(CC_C \| CC_A);
	224	al &= 0x0f;
	225	}
4b34e3ad	226	env->regs[R_EAX] = (env->regs[R_EAX] & ~0xffff) \| al \| (ah << 8);
d7582078 BS	227	CC_SRC = eflags;
	228	}
	229
7923057b	230	void helper_daa(CPUX86State *env)
d7582078 BS	231	{
	232	int old_al, al, af, cf;
	233	int eflags;
	234
f0967a1a	235	eflags = cpu_cc_compute_all(env, CC_OP);
d7582078 BS	236	cf = eflags & CC_C;
d7582078 BS	237	af = eflags & CC_A;
4b34e3ad	238	old_al = al = env->regs[R_EAX] & 0xff;
d7582078 BS	239
	240	eflags = 0;
	241	if (((al & 0x0f) > 9) \|\| af) {
	242	al = (al + 6) & 0xff;
	243	eflags \|= CC_A;
	244	}
	245	if ((old_al > 0x99) \|\| cf) {
	246	al = (al + 0x60) & 0xff;
	247	eflags \|= CC_C;
	248	}
4b34e3ad	249	env->regs[R_EAX] = (env->regs[R_EAX] & ~0xff) \| al;
d7582078 BS	250	/* well, speed is not an issue here, so we compute the flags by hand */
	251	eflags \|= (al == 0) << 6; /* zf */
	252	eflags \|= parity_table[al]; /* pf */
	253	eflags \|= (al & 0x80); /* sf */
	254	CC_SRC = eflags;
	255	}
	256
7923057b	257	void helper_das(CPUX86State *env)
d7582078 BS	258	{
	259	int al, al1, af, cf;
	260	int eflags;
	261
f0967a1a	262	eflags = cpu_cc_compute_all(env, CC_OP);
d7582078 BS	263	cf = eflags & CC_C;
d7582078 BS	264	af = eflags & CC_A;
4b34e3ad	265	al = env->regs[R_EAX] & 0xff;
d7582078 BS	266
	267	eflags = 0;
	268	al1 = al;
	269	if (((al & 0x0f) > 9) \|\| af) {
	270	eflags \|= CC_A;
	271	if (al < 6 \|\| cf) {
	272	eflags \|= CC_C;
	273	}
	274	al = (al - 6) & 0xff;
	275	}
	276	if ((al1 > 0x99) \|\| cf) {
	277	al = (al - 0x60) & 0xff;
	278	eflags \|= CC_C;
	279	}
4b34e3ad	280	env->regs[R_EAX] = (env->regs[R_EAX] & ~0xff) \| al;
d7582078 BS	281	/* well, speed is not an issue here, so we compute the flags by hand */
	282	eflags \|= (al == 0) << 6; /* zf */
	283	eflags \|= parity_table[al]; /* pf */
	284	eflags \|= (al & 0x80); /* sf */
	285	CC_SRC = eflags;
	286	}
	287
	288	#ifdef TARGET_X86_64
	289	static void add128(uint64_t plow, uint64_t phigh, uint64_t a, uint64_t b)
	290	{
	291	*plow += a;
	292	/* carry test */
	293	if (*plow < a) {
	294	(*phigh)++;
	295	}
	296	*phigh += b;
	297	}
	298
	299	static void neg128(uint64_t plow, uint64_t phigh)
	300	{
	301	plow = ~plow;
	302	phigh = ~phigh;
	303	add128(plow, phigh, 1, 0);
	304	}
	305
	306	/* return TRUE if overflow */
	307	static int div64(uint64_t plow, uint64_t phigh, uint64_t b)
	308	{
	309	uint64_t q, r, a1, a0;
	310	int i, qb, ab;
	311
	312	a0 = *plow;
	313	a1 = *phigh;
	314	if (a1 == 0) {
	315	q = a0 / b;
	316	r = a0 % b;
	317	*plow = q;
	318	*phigh = r;
	319	} else {
	320	if (a1 >= b) {
	321	return 1;
	322	}
	323	/* XXX: use a better algorithm */
	324	for (i = 0; i < 64; i++) {
	325	ab = a1 >> 63;
	326	a1 = (a1 << 1) \| (a0 >> 63);
	327	if (ab \|\| a1 >= b) {
	328	a1 -= b;
	329	qb = 1;
	330	} else {
	331	qb = 0;
	332	}
	333	a0 = (a0 << 1) \| qb;
	334	}
	335	#if defined(DEBUG_MULDIV)
	336	printf("div: 0x%016" PRIx64 "%016" PRIx64 " / 0x%016" PRIx64
	337	": q=0x%016" PRIx64 " r=0x%016" PRIx64 "\n",
	338	phigh, plow, b, a0, a1);
	339	#endif
	340	*plow = a0;
	341	*phigh = a1;
	342	}
	343	return 0;
	344	}
345
346	/* return TRUE if overflow */
347	static int idiv64(uint64_t plow, uint64_t phigh, int64_t b)
348	{
349	int sa, sb;
350
351	sa = ((int64_t)*phigh < 0);
352	if (sa) {
353	neg128(plow, phigh);
354	}
355	sb = (b < 0);
356	if (sb) {
357	b = -b;
358	}
359	if (div64(plow, phigh, b) != 0) {
360	return 1;
361	}
362	if (sa ^ sb) {
363	if (*plow > (1ULL << 63)) {
364	return 1;
365	}
366	plow = -plow;
367	} else {
368	if (*plow >= (1ULL << 63)) {
369	return 1;
370	}
371	}
372	if (sa) {
373	phigh = -phigh;
374	}
375	return 0;
376	}
377
7923057b	378	void helper_divq_EAX(CPUX86State *env, target_ulong t0)
d7582078 BS	379	{
	380	uint64_t r0, r1;
	381
	382	if (t0 == 0) {
cc33c5d6	383	raise_exception_ra(env, EXCP00_DIVZ, GETPC());
d7582078	384	}
4b34e3ad	385	r0 = env->regs[R_EAX];
00f5e6f2	386	r1 = env->regs[R_EDX];
d7582078	387	if (div64(&r0, &r1, t0)) {
cc33c5d6	388	raise_exception_ra(env, EXCP00_DIVZ, GETPC());
d7582078	389	}
4b34e3ad	390	env->regs[R_EAX] = r0;
00f5e6f2	391	env->regs[R_EDX] = r1;
d7582078 BS	392	}
d7582078 BS	393
7923057b	394	void helper_idivq_EAX(CPUX86State *env, target_ulong t0)
d7582078 BS	395	{
	396	uint64_t r0, r1;
	397
	398	if (t0 == 0) {
cc33c5d6	399	raise_exception_ra(env, EXCP00_DIVZ, GETPC());
d7582078	400	}
4b34e3ad	401	r0 = env->regs[R_EAX];
00f5e6f2	402	r1 = env->regs[R_EDX];
d7582078	403	if (idiv64(&r0, &r1, t0)) {
cc33c5d6	404	raise_exception_ra(env, EXCP00_DIVZ, GETPC());
d7582078	405	}
4b34e3ad	406	env->regs[R_EAX] = r0;
00f5e6f2	407	env->regs[R_EDX] = r1;
d7582078 BS	408	}
	409	#endif
	410
f1300734 RH	411	#if TARGET_LONG_BITS == 32
	412	# define ctztl ctz32
	413	# define clztl clz32
	414	#else
	415	# define ctztl ctz64
	416	# define clztl clz64
	417	#endif
	418
d7582078	419	/* bit operations */
321c5351	420	target_ulong helper_ctz(target_ulong t0)
d7582078	421	{
f1300734	422	return ctztl(t0);
d7582078 BS	423	}
d7582078 BS	424
321c5351	425	target_ulong helper_clz(target_ulong t0)
d7582078	426	{
321c5351	427	return clztl(t0);
d7582078 BS	428	}
d7582078 BS	429
0592f74a RH	430	target_ulong helper_pdep(target_ulong src, target_ulong mask)
	431	{
	432	target_ulong dest = 0;
	433	int i, o;
	434
	435	for (i = 0; mask != 0; i++) {
	436	o = ctztl(mask);
	437	mask &= mask - 1;
	438	dest \|= ((src >> i) & 1) << o;
	439	}
	440	return dest;
	441	}
	442
	443	target_ulong helper_pext(target_ulong src, target_ulong mask)
	444	{
	445	target_ulong dest = 0;
	446	int i, o;
	447
	448	for (o = 0; mask != 0; o++) {
	449	i = ctztl(mask);
	450	mask &= mask - 1;
	451	dest \|= ((src >> i) & 1) << o;
	452	}
	453	return dest;
	454	}
	455
d7582078 BS	456	#define SHIFT 0
	457	#include "shift_helper_template.h"
	458	#undef SHIFT
	459
	460	#define SHIFT 1
	461	#include "shift_helper_template.h"
	462	#undef SHIFT
	463
	464	#define SHIFT 2
	465	#include "shift_helper_template.h"
	466	#undef SHIFT
	467
	468	#ifdef TARGET_X86_64
	469	#define SHIFT 3
	470	#include "shift_helper_template.h"
	471	#undef SHIFT
	472	#endif
07929f2a RH	473
	474	/* Test that BIT is enabled in CR4. If not, raise an illegal opcode
	475	exception. This reduces the requirements for rare CR4 bits being
	476	mapped into HFLAGS. */
	477	void helper_cr4_testbit(CPUX86State *env, uint32_t bit)
	478	{
	479	if (unlikely((env->cr[4] & bit) == 0)) {
	480	raise_exception_ra(env, EXCP06_ILLOP, GETPC());
	481	}
	482	}