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virtio-blk: remove dead variable in virtio_blk_handle_scsi
[mirror_qemu.git] / target-i386 / kvm.c
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05330448
AL		 1/*
2 * QEMU KVM support
3 *
4 * Copyright (C) 2006-2008 Qumranet Technologies
5 * Copyright IBM, Corp. 2008
6 *
7 * Authors:
8 * Anthony Liguori <aliguori@us.ibm.com>
9 *
10 * This work is licensed under the terms of the GNU GPL, version 2 or later.
11 * See the COPYING file in the top-level directory.
12 *
13 */
14
15#include <sys/types.h>
16#include <sys/ioctl.h>
17#include <sys/mman.h>
18
19#include <linux/kvm.h>
20
21#include "qemu-common.h"
22#include "sysemu.h"
23#include "kvm.h"
24#include "cpu.h"
e22a25c9 25#include "gdbstub.h"
0e607a80 26#include "host-utils.h"
05330448
AL		 27
28//#define DEBUG_KVM
29
30#ifdef DEBUG_KVM
31#define dprintf(fmt, ...) \
32 do { fprintf(stderr, fmt, ## __VA_ARGS__); } while (0)
33#else
34#define dprintf(fmt, ...) \
35 do { } while (0)
36#endif
37
1a03675d
GC		 38#define MSR_KVM_WALL_CLOCK 0x11
39#define MSR_KVM_SYSTEM_TIME 0x12
40
b827df58
AK		 41#ifdef KVM_CAP_EXT_CPUID
42
43static struct kvm_cpuid2 *try_get_cpuid(KVMState *s, int max)
44{
45 struct kvm_cpuid2 *cpuid;
46 int r, size;
47
48 size = sizeof(*cpuid) + max * sizeof(*cpuid->entries);
49 cpuid = (struct kvm_cpuid2 *)qemu_mallocz(size);
50 cpuid->nent = max;
51 r = kvm_ioctl(s, KVM_GET_SUPPORTED_CPUID, cpuid);
76ae317f
MM		 52 if (r == 0 && cpuid->nent >= max) {
53 r = -E2BIG;
54 }
b827df58
AK		 55 if (r < 0) {
56 if (r == -E2BIG) {
57 qemu_free(cpuid);
58 return NULL;
59 } else {
60 fprintf(stderr, "KVM_GET_SUPPORTED_CPUID failed: %s\n",
61 strerror(-r));
62 exit(1);
63 }
64 }
65 return cpuid;
66}
67
68uint32_t kvm_arch_get_supported_cpuid(CPUState *env, uint32_t function, int reg)
69{
70 struct kvm_cpuid2 *cpuid;
71 int i, max;
72 uint32_t ret = 0;
73 uint32_t cpuid_1_edx;
74
75 if (!kvm_check_extension(env->kvm_state, KVM_CAP_EXT_CPUID)) {
76 return -1U;
77 }
78
79 max = 1;
80 while ((cpuid = try_get_cpuid(env->kvm_state, max)) == NULL) {
81 max *= 2;
82 }
83
84 for (i = 0; i < cpuid->nent; ++i) {
85 if (cpuid->entries[i].function == function) {
86 switch (reg) {
87 case R_EAX:
88 ret = cpuid->entries[i].eax;
89 break;
90 case R_EBX:
91 ret = cpuid->entries[i].ebx;
92 break;
93 case R_ECX:
94 ret = cpuid->entries[i].ecx;
95 break;
96 case R_EDX:
97 ret = cpuid->entries[i].edx;
98 if (function == 0x80000001) {
99 /* On Intel, kvm returns cpuid according to the Intel spec,
100 * so add missing bits according to the AMD spec:
101 */
102 cpuid_1_edx = kvm_arch_get_supported_cpuid(env, 1, R_EDX);
103 ret |= cpuid_1_edx & 0xdfeff7ff;
104 }
105 break;
106 }
107 }
108 }
109
110 qemu_free(cpuid);
111
112 return ret;
113}
114
115#else
116
117uint32_t kvm_arch_get_supported_cpuid(CPUState *env, uint32_t function, int reg)
118{
119 return -1U;
120}
121
122#endif
123
6c1f42fe
AP		 124static void kvm_trim_features(uint32_t *features, uint32_t supported)
125{
126 int i;
127 uint32_t mask;
128
129 for (i = 0; i < 32; ++i) {
130 mask = 1U << i;
131 if ((*features & mask) && !(supported & mask)) {
132 *features &= ~mask;
133 }
134 }
135}
136
05330448
AL		 137int kvm_arch_init_vcpu(CPUState *env)
138{
139 struct {
486bd5a2
AL		 140 struct kvm_cpuid2 cpuid;
141 struct kvm_cpuid_entry2 entries[100];
05330448 142 } __attribute__((packed)) cpuid_data;
486bd5a2 143 uint32_t limit, i, j, cpuid_i;
a33609ca 144 uint32_t unused;
05330448 145
f8d926e9
JK		 146 env->mp_state = KVM_MP_STATE_RUNNABLE;
147
6c1f42fe
AP		 148 kvm_trim_features(&env->cpuid_features,
149 kvm_arch_get_supported_cpuid(env, 1, R_EDX));
6c0d7ee8
AP		 150
151 i = env->cpuid_ext_features & CPUID_EXT_HYPERVISOR;
6c1f42fe
AP		 152 kvm_trim_features(&env->cpuid_ext_features,
153 kvm_arch_get_supported_cpuid(env, 1, R_ECX));
6c0d7ee8
AP		 154 env->cpuid_ext_features |= i;
155
6c1f42fe
AP		 156 kvm_trim_features(&env->cpuid_ext2_features,
157 kvm_arch_get_supported_cpuid(env, 0x80000001, R_EDX));
158 kvm_trim_features(&env->cpuid_ext3_features,
159 kvm_arch_get_supported_cpuid(env, 0x80000001, R_ECX));
160
05330448
AL		 161 cpuid_i = 0;
162
a33609ca 163 cpu_x86_cpuid(env, 0, 0, &limit, &unused, &unused, &unused);
05330448
AL		 164
165 for (i = 0; i <= limit; i++) {
486bd5a2
AL		 166 struct kvm_cpuid_entry2 *c = &cpuid_data.entries[cpuid_i++];
167
168 switch (i) {
a36b1029
AL		 169 case 2: {
170 /* Keep reading function 2 till all the input is received */
171 int times;
172
a36b1029 173 c->function = i;
a33609ca
AL		 174 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC |
175 KVM_CPUID_FLAG_STATE_READ_NEXT;
176 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
177 times = c->eax & 0xff;
a36b1029
AL		 178
179 for (j = 1; j < times; ++j) {
a33609ca 180 c = &cpuid_data.entries[cpuid_i++];
a36b1029 181 c->function = i;
a33609ca
AL		 182 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC;
183 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
a36b1029
AL		 184 }
185 break;
186 }
486bd5a2
AL		 187 case 4:
188 case 0xb:
189 case 0xd:
190 for (j = 0; ; j++) {
486bd5a2
AL		 191 c->function = i;
192 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
193 c->index = j;
a33609ca 194 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
486bd5a2 195
a33609ca 196 if (i == 4 && c->eax == 0)
486bd5a2 197 break;
a33609ca 198 if (i == 0xb && !(c->ecx & 0xff00))
486bd5a2 199 break;
a33609ca 200 if (i == 0xd && c->eax == 0)
486bd5a2 201 break;
a33609ca
AL		 202
203 c = &cpuid_data.entries[cpuid_i++];
486bd5a2
AL		 204 }
205 break;
206 default:
486bd5a2 207 c->function = i;
a33609ca
AL		 208 c->flags = 0;
209 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
486bd5a2
AL		 210 break;
211 }
05330448 212 }
a33609ca 213 cpu_x86_cpuid(env, 0x80000000, 0, &limit, &unused, &unused, &unused);
05330448
AL		 214
215 for (i = 0x80000000; i <= limit; i++) {
486bd5a2 216 struct kvm_cpuid_entry2 *c = &cpuid_data.entries[cpuid_i++];
05330448 217
05330448 218 c->function = i;
a33609ca
AL		 219 c->flags = 0;
220 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
05330448
AL		 221 }
222
223 cpuid_data.cpuid.nent = cpuid_i;
224
486bd5a2 225 return kvm_vcpu_ioctl(env, KVM_SET_CPUID2, &cpuid_data);
05330448
AL		 226}
227
caa5af0f
JK		 228void kvm_arch_reset_vcpu(CPUState *env)
229{
e73223a5 230 env->exception_injected = -1;
0e607a80 231 env->interrupt_injected = -1;
a0fb002c
JK		 232 env->nmi_injected = 0;
233 env->nmi_pending = 0;
caa5af0f
JK		 234}
235
05330448
AL		 236static int kvm_has_msr_star(CPUState *env)
237{
238 static int has_msr_star;
239 int ret;
240
241 /* first time */
242 if (has_msr_star == 0) {
243 struct kvm_msr_list msr_list, *kvm_msr_list;
244
245 has_msr_star = -1;
246
247 /* Obtain MSR list from KVM. These are the MSRs that we must
248 * save/restore */
4c9f7372 249 msr_list.nmsrs = 0;
05330448 250 ret = kvm_ioctl(env->kvm_state, KVM_GET_MSR_INDEX_LIST, &msr_list);
6fb6d245 251 if (ret < 0 && ret != -E2BIG) {
05330448 252 return 0;
6fb6d245 253 }
d9db889f
JK		 254 /* Old kernel modules had a bug and could write beyond the provided
255 memory. Allocate at least a safe amount of 1K. */
256 kvm_msr_list = qemu_mallocz(MAX(1024, sizeof(msr_list) +
257 msr_list.nmsrs *
258 sizeof(msr_list.indices[0])));
05330448 259
55308450 260 kvm_msr_list->nmsrs = msr_list.nmsrs;
05330448
AL		 261 ret = kvm_ioctl(env->kvm_state, KVM_GET_MSR_INDEX_LIST, kvm_msr_list);
262 if (ret >= 0) {
263 int i;
264
265 for (i = 0; i < kvm_msr_list->nmsrs; i++) {
266 if (kvm_msr_list->indices[i] == MSR_STAR) {
267 has_msr_star = 1;
268 break;
269 }
270 }
271 }
272
273 free(kvm_msr_list);
274 }
275
276 if (has_msr_star == 1)
277 return 1;
278 return 0;
279}
280
281int kvm_arch_init(KVMState *s, int smp_cpus)
282{
283 int ret;
284
285 /* create vm86 tss. KVM uses vm86 mode to emulate 16-bit code
286 * directly. In order to use vm86 mode, a TSS is needed. Since this
287 * must be part of guest physical memory, we need to allocate it. Older
288 * versions of KVM just assumed that it would be at the end of physical
289 * memory but that doesn't work with more than 4GB of memory. We simply
290 * refuse to work with those older versions of KVM. */
984b5181 291 ret = kvm_ioctl(s, KVM_CHECK_EXTENSION, KVM_CAP_SET_TSS_ADDR);
05330448
AL		 292 if (ret <= 0) {
293 fprintf(stderr, "kvm does not support KVM_CAP_SET_TSS_ADDR\n");
294 return ret;
295 }
296
297 /* this address is 3 pages before the bios, and the bios should present
298 * as unavaible memory. FIXME, need to ensure the e820 map deals with
299 * this?
300 */
984b5181 301 return kvm_vm_ioctl(s, KVM_SET_TSS_ADDR, 0xfffbd000);
05330448
AL		 302}
303
304static void set_v8086_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
305{
306 lhs->selector = rhs->selector;
307 lhs->base = rhs->base;
308 lhs->limit = rhs->limit;
309 lhs->type = 3;
310 lhs->present = 1;
311 lhs->dpl = 3;
312 lhs->db = 0;
313 lhs->s = 1;
314 lhs->l = 0;
315 lhs->g = 0;
316 lhs->avl = 0;
317 lhs->unusable = 0;
318}
319
320static void set_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
321{
322 unsigned flags = rhs->flags;
323 lhs->selector = rhs->selector;
324 lhs->base = rhs->base;
325 lhs->limit = rhs->limit;
326 lhs->type = (flags >> DESC_TYPE_SHIFT) & 15;
327 lhs->present = (flags & DESC_P_MASK) != 0;
328 lhs->dpl = rhs->selector & 3;
329 lhs->db = (flags >> DESC_B_SHIFT) & 1;
330 lhs->s = (flags & DESC_S_MASK) != 0;
331 lhs->l = (flags >> DESC_L_SHIFT) & 1;
332 lhs->g = (flags & DESC_G_MASK) != 0;
333 lhs->avl = (flags & DESC_AVL_MASK) != 0;
334 lhs->unusable = 0;
335}
336
337static void get_seg(SegmentCache *lhs, const struct kvm_segment *rhs)
338{
339 lhs->selector = rhs->selector;
340 lhs->base = rhs->base;
341 lhs->limit = rhs->limit;
342 lhs->flags =
343 (rhs->type << DESC_TYPE_SHIFT)
344 | (rhs->present * DESC_P_MASK)
345 | (rhs->dpl << DESC_DPL_SHIFT)
346 | (rhs->db << DESC_B_SHIFT)
347 | (rhs->s * DESC_S_MASK)
348 | (rhs->l << DESC_L_SHIFT)
349 | (rhs->g * DESC_G_MASK)
350 | (rhs->avl * DESC_AVL_MASK);
351}
352
353static void kvm_getput_reg(__u64 *kvm_reg, target_ulong *qemu_reg, int set)
354{
355 if (set)
356 *kvm_reg = *qemu_reg;
357 else
358 *qemu_reg = *kvm_reg;
359}
360
361static int kvm_getput_regs(CPUState *env, int set)
362{
363 struct kvm_regs regs;
364 int ret = 0;
365
366 if (!set) {
367 ret = kvm_vcpu_ioctl(env, KVM_GET_REGS, &regs);
368 if (ret < 0)
369 return ret;
370 }
371
372 kvm_getput_reg(&regs.rax, &env->regs[R_EAX], set);
373 kvm_getput_reg(&regs.rbx, &env->regs[R_EBX], set);
374 kvm_getput_reg(&regs.rcx, &env->regs[R_ECX], set);
375 kvm_getput_reg(&regs.rdx, &env->regs[R_EDX], set);
376 kvm_getput_reg(&regs.rsi, &env->regs[R_ESI], set);
377 kvm_getput_reg(&regs.rdi, &env->regs[R_EDI], set);
378 kvm_getput_reg(&regs.rsp, &env->regs[R_ESP], set);
379 kvm_getput_reg(&regs.rbp, &env->regs[R_EBP], set);
380#ifdef TARGET_X86_64
381 kvm_getput_reg(&regs.r8, &env->regs[8], set);
382 kvm_getput_reg(&regs.r9, &env->regs[9], set);
383 kvm_getput_reg(&regs.r10, &env->regs[10], set);
384 kvm_getput_reg(&regs.r11, &env->regs[11], set);
385 kvm_getput_reg(&regs.r12, &env->regs[12], set);
386 kvm_getput_reg(&regs.r13, &env->regs[13], set);
387 kvm_getput_reg(&regs.r14, &env->regs[14], set);
388 kvm_getput_reg(&regs.r15, &env->regs[15], set);
389#endif
390
391 kvm_getput_reg(&regs.rflags, &env->eflags, set);
392 kvm_getput_reg(&regs.rip, &env->eip, set);
393
394 if (set)
395 ret = kvm_vcpu_ioctl(env, KVM_SET_REGS, &regs);
396
397 return ret;
398}
399
400static int kvm_put_fpu(CPUState *env)
401{
402 struct kvm_fpu fpu;
403 int i;
404
405 memset(&fpu, 0, sizeof fpu);
406 fpu.fsw = env->fpus & ~(7 << 11);
407 fpu.fsw |= (env->fpstt & 7) << 11;
408 fpu.fcw = env->fpuc;
409 for (i = 0; i < 8; ++i)
410 fpu.ftwx |= (!env->fptags[i]) << i;
411 memcpy(fpu.fpr, env->fpregs, sizeof env->fpregs);
412 memcpy(fpu.xmm, env->xmm_regs, sizeof env->xmm_regs);
413 fpu.mxcsr = env->mxcsr;
414
415 return kvm_vcpu_ioctl(env, KVM_SET_FPU, &fpu);
416}
417
418static int kvm_put_sregs(CPUState *env)
419{
420 struct kvm_sregs sregs;
421
0e607a80
JK		 422 memset(sregs.interrupt_bitmap, 0, sizeof(sregs.interrupt_bitmap));
423 if (env->interrupt_injected >= 0) {
424 sregs.interrupt_bitmap[env->interrupt_injected / 64] |=
425 (uint64_t)1 << (env->interrupt_injected % 64);
426 }
05330448
AL		 427
428 if ((env->eflags & VM_MASK)) {
429 set_v8086_seg(&sregs.cs, &env->segs[R_CS]);
430 set_v8086_seg(&sregs.ds, &env->segs[R_DS]);
431 set_v8086_seg(&sregs.es, &env->segs[R_ES]);
432 set_v8086_seg(&sregs.fs, &env->segs[R_FS]);
433 set_v8086_seg(&sregs.gs, &env->segs[R_GS]);
434 set_v8086_seg(&sregs.ss, &env->segs[R_SS]);
435 } else {
436 set_seg(&sregs.cs, &env->segs[R_CS]);
437 set_seg(&sregs.ds, &env->segs[R_DS]);
438 set_seg(&sregs.es, &env->segs[R_ES]);
439 set_seg(&sregs.fs, &env->segs[R_FS]);
440 set_seg(&sregs.gs, &env->segs[R_GS]);
441 set_seg(&sregs.ss, &env->segs[R_SS]);
442
443 if (env->cr[0] & CR0_PE_MASK) {
444 /* force ss cpl to cs cpl */
445 sregs.ss.selector = (sregs.ss.selector & ~3) |
446 (sregs.cs.selector & 3);
447 sregs.ss.dpl = sregs.ss.selector & 3;
448 }
449 }
450
451 set_seg(&sregs.tr, &env->tr);
452 set_seg(&sregs.ldt, &env->ldt);
453
454 sregs.idt.limit = env->idt.limit;
455 sregs.idt.base = env->idt.base;
456 sregs.gdt.limit = env->gdt.limit;
457 sregs.gdt.base = env->gdt.base;
458
459 sregs.cr0 = env->cr[0];
460 sregs.cr2 = env->cr[2];
461 sregs.cr3 = env->cr[3];
462 sregs.cr4 = env->cr[4];
463
464 sregs.cr8 = cpu_get_apic_tpr(env);
465 sregs.apic_base = cpu_get_apic_base(env);
466
467 sregs.efer = env->efer;
468
469 return kvm_vcpu_ioctl(env, KVM_SET_SREGS, &sregs);
470}
471
472static void kvm_msr_entry_set(struct kvm_msr_entry *entry,
473 uint32_t index, uint64_t value)
474{
475 entry->index = index;
476 entry->data = value;
477}
478
479static int kvm_put_msrs(CPUState *env)
480{
481 struct {
482 struct kvm_msrs info;
483 struct kvm_msr_entry entries[100];
484 } msr_data;
485 struct kvm_msr_entry *msrs = msr_data.entries;
486 int n = 0;
487
488 kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_CS, env->sysenter_cs);
489 kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_ESP, env->sysenter_esp);
490 kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_EIP, env->sysenter_eip);
491 if (kvm_has_msr_star(env))
492 kvm_msr_entry_set(&msrs[n++], MSR_STAR, env->star);
493 kvm_msr_entry_set(&msrs[n++], MSR_IA32_TSC, env->tsc);
494#ifdef TARGET_X86_64
495 /* FIXME if lm capable */
496 kvm_msr_entry_set(&msrs[n++], MSR_CSTAR, env->cstar);
497 kvm_msr_entry_set(&msrs[n++], MSR_KERNELGSBASE, env->kernelgsbase);
498 kvm_msr_entry_set(&msrs[n++], MSR_FMASK, env->fmask);
499 kvm_msr_entry_set(&msrs[n++], MSR_LSTAR, env->lstar);
500#endif
1a03675d
GC		 501 kvm_msr_entry_set(&msrs[n++], MSR_KVM_SYSTEM_TIME, env->system_time_msr);
502 kvm_msr_entry_set(&msrs[n++], MSR_KVM_WALL_CLOCK, env->wall_clock_msr);
503
05330448
AL		 504 msr_data.info.nmsrs = n;
505
506 return kvm_vcpu_ioctl(env, KVM_SET_MSRS, &msr_data);
507
508}
509
510
511static int kvm_get_fpu(CPUState *env)
512{
513 struct kvm_fpu fpu;
514 int i, ret;
515
516 ret = kvm_vcpu_ioctl(env, KVM_GET_FPU, &fpu);
517 if (ret < 0)
518 return ret;
519
520 env->fpstt = (fpu.fsw >> 11) & 7;
521 env->fpus = fpu.fsw;
522 env->fpuc = fpu.fcw;
523 for (i = 0; i < 8; ++i)
524 env->fptags[i] = !((fpu.ftwx >> i) & 1);
525 memcpy(env->fpregs, fpu.fpr, sizeof env->fpregs);
526 memcpy(env->xmm_regs, fpu.xmm, sizeof env->xmm_regs);
527 env->mxcsr = fpu.mxcsr;
528
529 return 0;
530}
531
532static int kvm_get_sregs(CPUState *env)
533{
534 struct kvm_sregs sregs;
535 uint32_t hflags;
0e607a80 536 int bit, i, ret;
05330448
AL		 537
538 ret = kvm_vcpu_ioctl(env, KVM_GET_SREGS, &sregs);
539 if (ret < 0)
540 return ret;
541
0e607a80
JK		 542 /* There can only be one pending IRQ set in the bitmap at a time, so try
543 to find it and save its number instead (-1 for none). */
544 env->interrupt_injected = -1;
545 for (i = 0; i < ARRAY_SIZE(sregs.interrupt_bitmap); i++) {
546 if (sregs.interrupt_bitmap[i]) {
547 bit = ctz64(sregs.interrupt_bitmap[i]);
548 env->interrupt_injected = i * 64 + bit;
549 break;
550 }
551 }
05330448
AL		 552
553 get_seg(&env->segs[R_CS], &sregs.cs);
554 get_seg(&env->segs[R_DS], &sregs.ds);
555 get_seg(&env->segs[R_ES], &sregs.es);
556 get_seg(&env->segs[R_FS], &sregs.fs);
557 get_seg(&env->segs[R_GS], &sregs.gs);
558 get_seg(&env->segs[R_SS], &sregs.ss);
559
560 get_seg(&env->tr, &sregs.tr);
561 get_seg(&env->ldt, &sregs.ldt);
562
563 env->idt.limit = sregs.idt.limit;
564 env->idt.base = sregs.idt.base;
565 env->gdt.limit = sregs.gdt.limit;
566 env->gdt.base = sregs.gdt.base;
567
568 env->cr[0] = sregs.cr0;
569 env->cr[2] = sregs.cr2;
570 env->cr[3] = sregs.cr3;
571 env->cr[4] = sregs.cr4;
572
573 cpu_set_apic_base(env, sregs.apic_base);
574
575 env->efer = sregs.efer;
576 //cpu_set_apic_tpr(env, sregs.cr8);
577
578#define HFLAG_COPY_MASK ~( \
579 HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \
580 HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \
581 HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \
582 HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK)
583
584
585
586 hflags = (env->segs[R_CS].flags >> DESC_DPL_SHIFT) & HF_CPL_MASK;
587 hflags |= (env->cr[0] & CR0_PE_MASK) << (HF_PE_SHIFT - CR0_PE_SHIFT);
588 hflags |= (env->cr[0] << (HF_MP_SHIFT - CR0_MP_SHIFT)) &
589 (HF_MP_MASK | HF_EM_MASK | HF_TS_MASK);
590 hflags |= (env->eflags & (HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK));
591 hflags |= (env->cr[4] & CR4_OSFXSR_MASK) <<
592 (HF_OSFXSR_SHIFT - CR4_OSFXSR_SHIFT);
593
594 if (env->efer & MSR_EFER_LMA) {
595 hflags |= HF_LMA_MASK;
596 }
597
598 if ((hflags & HF_LMA_MASK) && (env->segs[R_CS].flags & DESC_L_MASK)) {
599 hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK;
600 } else {
601 hflags |= (env->segs[R_CS].flags & DESC_B_MASK) >>
602 (DESC_B_SHIFT - HF_CS32_SHIFT);
603 hflags |= (env->segs[R_SS].flags & DESC_B_MASK) >>
604 (DESC_B_SHIFT - HF_SS32_SHIFT);
605 if (!(env->cr[0] & CR0_PE_MASK) ||
606 (env->eflags & VM_MASK) ||
607 !(hflags & HF_CS32_MASK)) {
608 hflags |= HF_ADDSEG_MASK;
609 } else {
610 hflags |= ((env->segs[R_DS].base |
611 env->segs[R_ES].base |
612 env->segs[R_SS].base) != 0) <<
613 HF_ADDSEG_SHIFT;
614 }
615 }
616 env->hflags = (env->hflags & HFLAG_COPY_MASK) | hflags;
05330448
AL		 617
618 return 0;
619}
620
621static int kvm_get_msrs(CPUState *env)
622{
623 struct {
624 struct kvm_msrs info;
625 struct kvm_msr_entry entries[100];
626 } msr_data;
627 struct kvm_msr_entry *msrs = msr_data.entries;
628 int ret, i, n;
629
630 n = 0;
631 msrs[n++].index = MSR_IA32_SYSENTER_CS;
632 msrs[n++].index = MSR_IA32_SYSENTER_ESP;
633 msrs[n++].index = MSR_IA32_SYSENTER_EIP;
634 if (kvm_has_msr_star(env))
635 msrs[n++].index = MSR_STAR;
636 msrs[n++].index = MSR_IA32_TSC;
637#ifdef TARGET_X86_64
638 /* FIXME lm_capable_kernel */
639 msrs[n++].index = MSR_CSTAR;
640 msrs[n++].index = MSR_KERNELGSBASE;
641 msrs[n++].index = MSR_FMASK;
642 msrs[n++].index = MSR_LSTAR;
643#endif
1a03675d
GC		 644 msrs[n++].index = MSR_KVM_SYSTEM_TIME;
645 msrs[n++].index = MSR_KVM_WALL_CLOCK;
646
05330448
AL		 647 msr_data.info.nmsrs = n;
648 ret = kvm_vcpu_ioctl(env, KVM_GET_MSRS, &msr_data);
649 if (ret < 0)
650 return ret;
651
652 for (i = 0; i < ret; i++) {
653 switch (msrs[i].index) {
654 case MSR_IA32_SYSENTER_CS:
655 env->sysenter_cs = msrs[i].data;
656 break;
657 case MSR_IA32_SYSENTER_ESP:
658 env->sysenter_esp = msrs[i].data;
659 break;
660 case MSR_IA32_SYSENTER_EIP:
661 env->sysenter_eip = msrs[i].data;
662 break;
663 case MSR_STAR:
664 env->star = msrs[i].data;
665 break;
666#ifdef TARGET_X86_64
667 case MSR_CSTAR:
668 env->cstar = msrs[i].data;
669 break;
670 case MSR_KERNELGSBASE:
671 env->kernelgsbase = msrs[i].data;
672 break;
673 case MSR_FMASK:
674 env->fmask = msrs[i].data;
675 break;
676 case MSR_LSTAR:
677 env->lstar = msrs[i].data;
678 break;
679#endif
680 case MSR_IA32_TSC:
681 env->tsc = msrs[i].data;
682 break;
1a03675d
GC		 683 case MSR_KVM_SYSTEM_TIME:
684 env->system_time_msr = msrs[i].data;
685 break;
686 case MSR_KVM_WALL_CLOCK:
687 env->wall_clock_msr = msrs[i].data;
688 break;
05330448
AL		 689 }
690 }
691
692 return 0;
693}
694
9bdbe550
HB		 695static int kvm_put_mp_state(CPUState *env)
696{
697 struct kvm_mp_state mp_state = { .mp_state = env->mp_state };
698
699 return kvm_vcpu_ioctl(env, KVM_SET_MP_STATE, &mp_state);
700}
701
702static int kvm_get_mp_state(CPUState *env)
703{
704 struct kvm_mp_state mp_state;
705 int ret;
706
707 ret = kvm_vcpu_ioctl(env, KVM_GET_MP_STATE, &mp_state);
708 if (ret < 0) {
709 return ret;
710 }
711 env->mp_state = mp_state.mp_state;
712 return 0;
713}
714
a0fb002c
JK		 715static int kvm_put_vcpu_events(CPUState *env)
716{
717#ifdef KVM_CAP_VCPU_EVENTS
718 struct kvm_vcpu_events events;
719
720 if (!kvm_has_vcpu_events()) {
721 return 0;
722 }
723
31827373
JK		 724 events.exception.injected = (env->exception_injected >= 0);
725 events.exception.nr = env->exception_injected;
a0fb002c
JK		 726 events.exception.has_error_code = env->has_error_code;
727 events.exception.error_code = env->error_code;
728
729 events.interrupt.injected = (env->interrupt_injected >= 0);
730 events.interrupt.nr = env->interrupt_injected;
731 events.interrupt.soft = env->soft_interrupt;
732
733 events.nmi.injected = env->nmi_injected;
734 events.nmi.pending = env->nmi_pending;
735 events.nmi.masked = !!(env->hflags2 & HF2_NMI_MASK);
736
737 events.sipi_vector = env->sipi_vector;
738
739 return kvm_vcpu_ioctl(env, KVM_SET_VCPU_EVENTS, &events);
740#else
741 return 0;
742#endif
743}
744
745static int kvm_get_vcpu_events(CPUState *env)
746{
747#ifdef KVM_CAP_VCPU_EVENTS
748 struct kvm_vcpu_events events;
749 int ret;
750
751 if (!kvm_has_vcpu_events()) {
752 return 0;
753 }
754
755 ret = kvm_vcpu_ioctl(env, KVM_GET_VCPU_EVENTS, &events);
756 if (ret < 0) {
757 return ret;
758 }
31827373 759 env->exception_injected =
a0fb002c
JK		 760 events.exception.injected ? events.exception.nr : -1;
761 env->has_error_code = events.exception.has_error_code;
762 env->error_code = events.exception.error_code;
763
764 env->interrupt_injected =
765 events.interrupt.injected ? events.interrupt.nr : -1;
766 env->soft_interrupt = events.interrupt.soft;
767
768 env->nmi_injected = events.nmi.injected;
769 env->nmi_pending = events.nmi.pending;
770 if (events.nmi.masked) {
771 env->hflags2 |= HF2_NMI_MASK;
772 } else {
773 env->hflags2 &= ~HF2_NMI_MASK;
774 }
775
776 env->sipi_vector = events.sipi_vector;
777#endif
778
779 return 0;
780}
781
05330448
AL		 782int kvm_arch_put_registers(CPUState *env)
783{
784 int ret;
785
786 ret = kvm_getput_regs(env, 1);
787 if (ret < 0)
788 return ret;
789
790 ret = kvm_put_fpu(env);
791 if (ret < 0)
792 return ret;
793
794 ret = kvm_put_sregs(env);
795 if (ret < 0)
796 return ret;
797
798 ret = kvm_put_msrs(env);
799 if (ret < 0)
800 return ret;
801
f8d926e9
JK		 802 ret = kvm_put_mp_state(env);
803 if (ret < 0)
804 return ret;
805
a0fb002c
JK		 806 ret = kvm_put_vcpu_events(env);
807 if (ret < 0)
808 return ret;
809
05330448
AL		 810 return 0;
811}
812
813int kvm_arch_get_registers(CPUState *env)
814{
815 int ret;
816
817 ret = kvm_getput_regs(env, 0);
818 if (ret < 0)
819 return ret;
820
821 ret = kvm_get_fpu(env);
822 if (ret < 0)
823 return ret;
824
825 ret = kvm_get_sregs(env);
826 if (ret < 0)
827 return ret;
828
829 ret = kvm_get_msrs(env);
830 if (ret < 0)
831 return ret;
832
5a2e3c2e
JK		 833 ret = kvm_get_mp_state(env);
834 if (ret < 0)
835 return ret;
836
a0fb002c
JK		 837 ret = kvm_get_vcpu_events(env);
838 if (ret < 0)
839 return ret;
840
05330448
AL		 841 return 0;
842}
843
844int kvm_arch_pre_run(CPUState *env, struct kvm_run *run)
845{
846 /* Try to inject an interrupt if the guest can accept it */
847 if (run->ready_for_interrupt_injection &&
848 (env->interrupt_request & CPU_INTERRUPT_HARD) &&
849 (env->eflags & IF_MASK)) {
850 int irq;
851
852 env->interrupt_request &= ~CPU_INTERRUPT_HARD;
853 irq = cpu_get_pic_interrupt(env);
854 if (irq >= 0) {
855 struct kvm_interrupt intr;
856 intr.irq = irq;
857 /* FIXME: errors */
858 dprintf("injected interrupt %d\n", irq);
859 kvm_vcpu_ioctl(env, KVM_INTERRUPT, &intr);
860 }
861 }
862
863 /* If we have an interrupt but the guest is not ready to receive an
864 * interrupt, request an interrupt window exit. This will
865 * cause a return to userspace as soon as the guest is ready to
866 * receive interrupts. */
867 if ((env->interrupt_request & CPU_INTERRUPT_HARD))
868 run->request_interrupt_window = 1;
869 else
870 run->request_interrupt_window = 0;
871
872 dprintf("setting tpr\n");
873 run->cr8 = cpu_get_apic_tpr(env);
874
875 return 0;
876}
877
878int kvm_arch_post_run(CPUState *env, struct kvm_run *run)
879{
880 if (run->if_flag)
881 env->eflags |= IF_MASK;
882 else
883 env->eflags &= ~IF_MASK;
884
885 cpu_set_apic_tpr(env, run->cr8);
886 cpu_set_apic_base(env, run->apic_base);
887
888 return 0;
889}
890
891static int kvm_handle_halt(CPUState *env)
892{
893 if (!((env->interrupt_request & CPU_INTERRUPT_HARD) &&
894 (env->eflags & IF_MASK)) &&
895 !(env->interrupt_request & CPU_INTERRUPT_NMI)) {
896 env->halted = 1;
897 env->exception_index = EXCP_HLT;
898 return 0;
899 }
900
901 return 1;
902}
903
904int kvm_arch_handle_exit(CPUState *env, struct kvm_run *run)
905{
906 int ret = 0;
907
908 switch (run->exit_reason) {
909 case KVM_EXIT_HLT:
910 dprintf("handle_hlt\n");
911 ret = kvm_handle_halt(env);
912 break;
913 }
914
915 return ret;
916}
e22a25c9
AL		 917
918#ifdef KVM_CAP_SET_GUEST_DEBUG
e22a25c9
AL		 919int kvm_arch_insert_sw_breakpoint(CPUState *env, struct kvm_sw_breakpoint *bp)
920{
38972938 921 static const uint8_t int3 = 0xcc;
64bf3f4e 922
e22a25c9 923 if (cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&bp->saved_insn, 1, 0) ||
64bf3f4e 924 cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&int3, 1, 1))
e22a25c9
AL		 925 return -EINVAL;
926 return 0;
927}
928
929int kvm_arch_remove_sw_breakpoint(CPUState *env, struct kvm_sw_breakpoint *bp)
930{
931 uint8_t int3;
932
933 if (cpu_memory_rw_debug(env, bp->pc, &int3, 1, 0) || int3 != 0xcc ||
64bf3f4e 934 cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&bp->saved_insn, 1, 1))
e22a25c9
AL		 935 return -EINVAL;
936 return 0;
937}
938
939static struct {
940 target_ulong addr;
941 int len;
942 int type;
943} hw_breakpoint[4];
944
945static int nb_hw_breakpoint;
946
947static int find_hw_breakpoint(target_ulong addr, int len, int type)
948{
949 int n;
950
951 for (n = 0; n < nb_hw_breakpoint; n++)
952 if (hw_breakpoint[n].addr == addr && hw_breakpoint[n].type == type &&
953 (hw_breakpoint[n].len == len || len == -1))
954 return n;
955 return -1;
956}
957
958int kvm_arch_insert_hw_breakpoint(target_ulong addr,
959 target_ulong len, int type)
960{
961 switch (type) {
962 case GDB_BREAKPOINT_HW:
963 len = 1;
964 break;
965 case GDB_WATCHPOINT_WRITE:
966 case GDB_WATCHPOINT_ACCESS:
967 switch (len) {
968 case 1:
969 break;
970 case 2:
971 case 4:
972 case 8:
973 if (addr & (len - 1))
974 return -EINVAL;
975 break;
976 default:
977 return -EINVAL;
978 }
979 break;
980 default:
981 return -ENOSYS;
982 }
983
984 if (nb_hw_breakpoint == 4)
985 return -ENOBUFS;
986
987 if (find_hw_breakpoint(addr, len, type) >= 0)
988 return -EEXIST;
989
990 hw_breakpoint[nb_hw_breakpoint].addr = addr;
991 hw_breakpoint[nb_hw_breakpoint].len = len;
992 hw_breakpoint[nb_hw_breakpoint].type = type;
993 nb_hw_breakpoint++;
994
995 return 0;
996}
997
998int kvm_arch_remove_hw_breakpoint(target_ulong addr,
999 target_ulong len, int type)
1000{
1001 int n;
1002
1003 n = find_hw_breakpoint(addr, (type == GDB_BREAKPOINT_HW) ? 1 : len, type);
1004 if (n < 0)
1005 return -ENOENT;
1006
1007 nb_hw_breakpoint--;
1008 hw_breakpoint[n] = hw_breakpoint[nb_hw_breakpoint];
1009
1010 return 0;
1011}
1012
1013void kvm_arch_remove_all_hw_breakpoints(void)
1014{
1015 nb_hw_breakpoint = 0;
1016}
1017
1018static CPUWatchpoint hw_watchpoint;
1019
1020int kvm_arch_debug(struct kvm_debug_exit_arch *arch_info)
1021{
1022 int handle = 0;
1023 int n;
1024
1025 if (arch_info->exception == 1) {
1026 if (arch_info->dr6 & (1 << 14)) {
1027 if (cpu_single_env->singlestep_enabled)
1028 handle = 1;
1029 } else {
1030 for (n = 0; n < 4; n++)
1031 if (arch_info->dr6 & (1 << n))
1032 switch ((arch_info->dr7 >> (16 + n*4)) & 0x3) {
1033 case 0x0:
1034 handle = 1;
1035 break;
1036 case 0x1:
1037 handle = 1;
1038 cpu_single_env->watchpoint_hit = &hw_watchpoint;
1039 hw_watchpoint.vaddr = hw_breakpoint[n].addr;
1040 hw_watchpoint.flags = BP_MEM_WRITE;
1041 break;
1042 case 0x3:
1043 handle = 1;
1044 cpu_single_env->watchpoint_hit = &hw_watchpoint;
1045 hw_watchpoint.vaddr = hw_breakpoint[n].addr;
1046 hw_watchpoint.flags = BP_MEM_ACCESS;
1047 break;
1048 }
1049 }
1050 } else if (kvm_find_sw_breakpoint(cpu_single_env, arch_info->pc))
1051 handle = 1;
1052
1053 if (!handle)
1054 kvm_update_guest_debug(cpu_single_env,
1055 (arch_info->exception == 1) ?
1056 KVM_GUESTDBG_INJECT_DB : KVM_GUESTDBG_INJECT_BP);
1057
1058 return handle;
1059}
1060
1061void kvm_arch_update_guest_debug(CPUState *env, struct kvm_guest_debug *dbg)
1062{
1063 const uint8_t type_code[] = {
1064 [GDB_BREAKPOINT_HW] = 0x0,
1065 [GDB_WATCHPOINT_WRITE] = 0x1,
1066 [GDB_WATCHPOINT_ACCESS] = 0x3
1067 };
1068 const uint8_t len_code[] = {
1069 [1] = 0x0, [2] = 0x1, [4] = 0x3, [8] = 0x2
1070 };
1071 int n;
1072
1073 if (kvm_sw_breakpoints_active(env))
1074 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP;
1075
1076 if (nb_hw_breakpoint > 0) {
1077 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP;
1078 dbg->arch.debugreg[7] = 0x0600;
1079 for (n = 0; n < nb_hw_breakpoint; n++) {
1080 dbg->arch.debugreg[n] = hw_breakpoint[n].addr;
1081 dbg->arch.debugreg[7] |= (2 << (n * 2)) |
1082 (type_code[hw_breakpoint[n].type] << (16 + n*4)) |
1083 (len_code[hw_breakpoint[n].len] << (18 + n*4));
1084 }
1085 }
1086}
1087#endif /* KVM_CAP_SET_GUEST_DEBUG */
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