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05330448
AL		 1/*
2 * QEMU KVM support
3 *
4 * Copyright (C) 2006-2008 Qumranet Technologies
5 * Copyright IBM, Corp. 2008
6 *
7 * Authors:
8 * Anthony Liguori <aliguori@us.ibm.com>
9 *
10 * This work is licensed under the terms of the GNU GPL, version 2 or later.
11 * See the COPYING file in the top-level directory.
12 *
13 */
14
15#include <sys/types.h>
16#include <sys/ioctl.h>
17#include <sys/mman.h>
18
19#include <linux/kvm.h>
20
21#include "qemu-common.h"
22#include "sysemu.h"
23#include "kvm.h"
24#include "cpu.h"
e22a25c9 25#include "gdbstub.h"
0e607a80 26#include "host-utils.h"
4c5b10b7 27#include "hw/pc.h"
35bed8ee 28#include "ioport.h"
05330448 29
bb0300dc
GN		 30#ifdef CONFIG_KVM_PARA
31#include <linux/kvm_para.h>
32#endif
33//
05330448
AL		 34//#define DEBUG_KVM
35
36#ifdef DEBUG_KVM
8c0d577e 37#define DPRINTF(fmt, ...) \
05330448
AL		 38 do { fprintf(stderr, fmt, ## __VA_ARGS__); } while (0)
39#else
8c0d577e 40#define DPRINTF(fmt, ...) \
05330448
AL		 41 do { } while (0)
42#endif
43
1a03675d
GC		 44#define MSR_KVM_WALL_CLOCK 0x11
45#define MSR_KVM_SYSTEM_TIME 0x12
46
b827df58
AK		 47#ifdef KVM_CAP_EXT_CPUID
48
49static struct kvm_cpuid2 *try_get_cpuid(KVMState *s, int max)
50{
51 struct kvm_cpuid2 *cpuid;
52 int r, size;
53
54 size = sizeof(*cpuid) + max * sizeof(*cpuid->entries);
55 cpuid = (struct kvm_cpuid2 *)qemu_mallocz(size);
56 cpuid->nent = max;
57 r = kvm_ioctl(s, KVM_GET_SUPPORTED_CPUID, cpuid);
76ae317f
MM		 58 if (r == 0 && cpuid->nent >= max) {
59 r = -E2BIG;
60 }
b827df58
AK		 61 if (r < 0) {
62 if (r == -E2BIG) {
63 qemu_free(cpuid);
64 return NULL;
65 } else {
66 fprintf(stderr, "KVM_GET_SUPPORTED_CPUID failed: %s\n",
67 strerror(-r));
68 exit(1);
69 }
70 }
71 return cpuid;
72}
73
c958a8bd
SY		 74uint32_t kvm_arch_get_supported_cpuid(CPUState *env, uint32_t function,
75 uint32_t index, int reg)
b827df58
AK		 76{
77 struct kvm_cpuid2 *cpuid;
78 int i, max;
79 uint32_t ret = 0;
80 uint32_t cpuid_1_edx;
81
82 if (!kvm_check_extension(env->kvm_state, KVM_CAP_EXT_CPUID)) {
83 return -1U;
84 }
85
86 max = 1;
87 while ((cpuid = try_get_cpuid(env->kvm_state, max)) == NULL) {
88 max *= 2;
89 }
90
91 for (i = 0; i < cpuid->nent; ++i) {
c958a8bd
SY		 92 if (cpuid->entries[i].function == function &&
93 cpuid->entries[i].index == index) {
b827df58
AK		 94 switch (reg) {
95 case R_EAX:
96 ret = cpuid->entries[i].eax;
97 break;
98 case R_EBX:
99 ret = cpuid->entries[i].ebx;
100 break;
101 case R_ECX:
102 ret = cpuid->entries[i].ecx;
103 break;
104 case R_EDX:
105 ret = cpuid->entries[i].edx;
19ccb8ea
JK		 106 switch (function) {
107 case 1:
108 /* KVM before 2.6.30 misreports the following features */
109 ret |= CPUID_MTRR | CPUID_PAT | CPUID_MCE | CPUID_MCA;
110 break;
111 case 0x80000001:
b827df58
AK		 112 /* On Intel, kvm returns cpuid according to the Intel spec,
113 * so add missing bits according to the AMD spec:
114 */
c958a8bd 115 cpuid_1_edx = kvm_arch_get_supported_cpuid(env, 1, 0, R_EDX);
c1667e40 116 ret |= cpuid_1_edx & 0x183f7ff;
19ccb8ea 117 break;
b827df58
AK		 118 }
119 break;
120 }
121 }
122 }
123
124 qemu_free(cpuid);
125
126 return ret;
127}
128
129#else
130
c958a8bd
SY		 131uint32_t kvm_arch_get_supported_cpuid(CPUState *env, uint32_t function,
132 uint32_t index, int reg)
b827df58
AK		 133{
134 return -1U;
135}
136
137#endif
138
bb0300dc
GN		 139#ifdef CONFIG_KVM_PARA
140struct kvm_para_features {
141 int cap;
142 int feature;
143} para_features[] = {
144#ifdef KVM_CAP_CLOCKSOURCE
145 { KVM_CAP_CLOCKSOURCE, KVM_FEATURE_CLOCKSOURCE },
146#endif
147#ifdef KVM_CAP_NOP_IO_DELAY
148 { KVM_CAP_NOP_IO_DELAY, KVM_FEATURE_NOP_IO_DELAY },
149#endif
150#ifdef KVM_CAP_PV_MMU
151 { KVM_CAP_PV_MMU, KVM_FEATURE_MMU_OP },
bb0300dc
GN		 152#endif
153 { -1, -1 }
154};
155
156static int get_para_features(CPUState *env)
157{
158 int i, features = 0;
159
160 for (i = 0; i < ARRAY_SIZE(para_features) - 1; i++) {
161 if (kvm_check_extension(env->kvm_state, para_features[i].cap))
162 features |= (1 << para_features[i].feature);
163 }
164
165 return features;
166}
167#endif
168
05330448
AL		 169int kvm_arch_init_vcpu(CPUState *env)
170{
171 struct {
486bd5a2
AL		 172 struct kvm_cpuid2 cpuid;
173 struct kvm_cpuid_entry2 entries[100];
05330448 174 } __attribute__((packed)) cpuid_data;
486bd5a2 175 uint32_t limit, i, j, cpuid_i;
a33609ca 176 uint32_t unused;
bb0300dc
GN		 177 struct kvm_cpuid_entry2 *c;
178#ifdef KVM_CPUID_SIGNATURE
179 uint32_t signature[3];
180#endif
05330448 181
f8d926e9
JK		 182 env->mp_state = KVM_MP_STATE_RUNNABLE;
183
c958a8bd 184 env->cpuid_features &= kvm_arch_get_supported_cpuid(env, 1, 0, R_EDX);
6c0d7ee8
AP		 185
186 i = env->cpuid_ext_features & CPUID_EXT_HYPERVISOR;
c958a8bd 187 env->cpuid_ext_features &= kvm_arch_get_supported_cpuid(env, 1, 0, R_ECX);
6c0d7ee8
AP		 188 env->cpuid_ext_features |= i;
189
457dfed6 190 env->cpuid_ext2_features &= kvm_arch_get_supported_cpuid(env, 0x80000001,
c958a8bd 191 0, R_EDX);
457dfed6 192 env->cpuid_ext3_features &= kvm_arch_get_supported_cpuid(env, 0x80000001,
c958a8bd 193 0, R_ECX);
6c1f42fe 194
05330448
AL		 195 cpuid_i = 0;
196
bb0300dc
GN		 197#ifdef CONFIG_KVM_PARA
198 /* Paravirtualization CPUIDs */
199 memcpy(signature, "KVMKVMKVM\0\0\0", 12);
200 c = &cpuid_data.entries[cpuid_i++];
201 memset(c, 0, sizeof(*c));
202 c->function = KVM_CPUID_SIGNATURE;
203 c->eax = 0;
204 c->ebx = signature[0];
205 c->ecx = signature[1];
206 c->edx = signature[2];
207
208 c = &cpuid_data.entries[cpuid_i++];
209 memset(c, 0, sizeof(*c));
210 c->function = KVM_CPUID_FEATURES;
211 c->eax = env->cpuid_kvm_features & get_para_features(env);
212#endif
213
a33609ca 214 cpu_x86_cpuid(env, 0, 0, &limit, &unused, &unused, &unused);
05330448
AL		 215
216 for (i = 0; i <= limit; i++) {
bb0300dc 217 c = &cpuid_data.entries[cpuid_i++];
486bd5a2
AL		 218
219 switch (i) {
a36b1029
AL		 220 case 2: {
221 /* Keep reading function 2 till all the input is received */
222 int times;
223
a36b1029 224 c->function = i;
a33609ca
AL		 225 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC |
226 KVM_CPUID_FLAG_STATE_READ_NEXT;
227 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
228 times = c->eax & 0xff;
a36b1029
AL		 229
230 for (j = 1; j < times; ++j) {
a33609ca 231 c = &cpuid_data.entries[cpuid_i++];
a36b1029 232 c->function = i;
a33609ca
AL		 233 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC;
234 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
a36b1029
AL		 235 }
236 break;
237 }
486bd5a2
AL		 238 case 4:
239 case 0xb:
240 case 0xd:
241 for (j = 0; ; j++) {
486bd5a2
AL		 242 c->function = i;
243 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
244 c->index = j;
a33609ca 245 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
486bd5a2 246
a33609ca 247 if (i == 4 && c->eax == 0)
486bd5a2 248 break;
a33609ca 249 if (i == 0xb && !(c->ecx & 0xff00))
486bd5a2 250 break;
a33609ca 251 if (i == 0xd && c->eax == 0)
486bd5a2 252 break;
a33609ca
AL		 253
254 c = &cpuid_data.entries[cpuid_i++];
486bd5a2
AL		 255 }
256 break;
257 default:
486bd5a2 258 c->function = i;
a33609ca
AL		 259 c->flags = 0;
260 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
486bd5a2
AL		 261 break;
262 }
05330448 263 }
a33609ca 264 cpu_x86_cpuid(env, 0x80000000, 0, &limit, &unused, &unused, &unused);
05330448
AL		 265
266 for (i = 0x80000000; i <= limit; i++) {
bb0300dc 267 c = &cpuid_data.entries[cpuid_i++];
05330448 268
05330448 269 c->function = i;
a33609ca
AL		 270 c->flags = 0;
271 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
05330448
AL		 272 }
273
274 cpuid_data.cpuid.nent = cpuid_i;
275
486bd5a2 276 return kvm_vcpu_ioctl(env, KVM_SET_CPUID2, &cpuid_data);
05330448
AL		 277}
278
caa5af0f
JK		 279void kvm_arch_reset_vcpu(CPUState *env)
280{
e73223a5 281 env->exception_injected = -1;
0e607a80 282 env->interrupt_injected = -1;
a0fb002c
JK		 283 env->nmi_injected = 0;
284 env->nmi_pending = 0;
caa5af0f
JK		 285}
286
05330448
AL		 287static int kvm_has_msr_star(CPUState *env)
288{
289 static int has_msr_star;
290 int ret;
291
292 /* first time */
293 if (has_msr_star == 0) {
294 struct kvm_msr_list msr_list, *kvm_msr_list;
295
296 has_msr_star = -1;
297
298 /* Obtain MSR list from KVM. These are the MSRs that we must
299 * save/restore */
4c9f7372 300 msr_list.nmsrs = 0;
05330448 301 ret = kvm_ioctl(env->kvm_state, KVM_GET_MSR_INDEX_LIST, &msr_list);
6fb6d245 302 if (ret < 0 && ret != -E2BIG) {
05330448 303 return 0;
6fb6d245 304 }
d9db889f
JK		 305 /* Old kernel modules had a bug and could write beyond the provided
306 memory. Allocate at least a safe amount of 1K. */
307 kvm_msr_list = qemu_mallocz(MAX(1024, sizeof(msr_list) +
308 msr_list.nmsrs *
309 sizeof(msr_list.indices[0])));
05330448 310
55308450 311 kvm_msr_list->nmsrs = msr_list.nmsrs;
05330448
AL		 312 ret = kvm_ioctl(env->kvm_state, KVM_GET_MSR_INDEX_LIST, kvm_msr_list);
313 if (ret >= 0) {
314 int i;
315
316 for (i = 0; i < kvm_msr_list->nmsrs; i++) {
317 if (kvm_msr_list->indices[i] == MSR_STAR) {
318 has_msr_star = 1;
319 break;
320 }
321 }
322 }
323
324 free(kvm_msr_list);
325 }
326
327 if (has_msr_star == 1)
328 return 1;
329 return 0;
330}
331
20420430
SY		 332static int kvm_init_identity_map_page(KVMState *s)
333{
334#ifdef KVM_CAP_SET_IDENTITY_MAP_ADDR
335 int ret;
336 uint64_t addr = 0xfffbc000;
337
338 if (!kvm_check_extension(s, KVM_CAP_SET_IDENTITY_MAP_ADDR)) {
339 return 0;
340 }
341
342 ret = kvm_vm_ioctl(s, KVM_SET_IDENTITY_MAP_ADDR, &addr);
343 if (ret < 0) {
344 fprintf(stderr, "kvm_set_identity_map_addr: %s\n", strerror(ret));
345 return ret;
346 }
347#endif
348 return 0;
349}
350
05330448
AL		 351int kvm_arch_init(KVMState *s, int smp_cpus)
352{
353 int ret;
354
355 /* create vm86 tss. KVM uses vm86 mode to emulate 16-bit code
356 * directly. In order to use vm86 mode, a TSS is needed. Since this
357 * must be part of guest physical memory, we need to allocate it. Older
358 * versions of KVM just assumed that it would be at the end of physical
359 * memory but that doesn't work with more than 4GB of memory. We simply
360 * refuse to work with those older versions of KVM. */
984b5181 361 ret = kvm_ioctl(s, KVM_CHECK_EXTENSION, KVM_CAP_SET_TSS_ADDR);
05330448
AL		 362 if (ret <= 0) {
363 fprintf(stderr, "kvm does not support KVM_CAP_SET_TSS_ADDR\n");
364 return ret;
365 }
366
367 /* this address is 3 pages before the bios, and the bios should present
368 * as unavaible memory. FIXME, need to ensure the e820 map deals with
369 * this?
370 */
4c5b10b7
JS		 371 /*
372 * Tell fw_cfg to notify the BIOS to reserve the range.
373 */
374 if (e820_add_entry(0xfffbc000, 0x4000, E820_RESERVED) < 0) {
375 perror("e820_add_entry() table is full");
376 exit(1);
377 }
20420430
SY		 378 ret = kvm_vm_ioctl(s, KVM_SET_TSS_ADDR, 0xfffbd000);
379 if (ret < 0) {
380 return ret;
381 }
382
383 return kvm_init_identity_map_page(s);
05330448
AL		 384}
385
386static void set_v8086_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
387{
388 lhs->selector = rhs->selector;
389 lhs->base = rhs->base;
390 lhs->limit = rhs->limit;
391 lhs->type = 3;
392 lhs->present = 1;
393 lhs->dpl = 3;
394 lhs->db = 0;
395 lhs->s = 1;
396 lhs->l = 0;
397 lhs->g = 0;
398 lhs->avl = 0;
399 lhs->unusable = 0;
400}
401
402static void set_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
403{
404 unsigned flags = rhs->flags;
405 lhs->selector = rhs->selector;
406 lhs->base = rhs->base;
407 lhs->limit = rhs->limit;
408 lhs->type = (flags >> DESC_TYPE_SHIFT) & 15;
409 lhs->present = (flags & DESC_P_MASK) != 0;
410 lhs->dpl = rhs->selector & 3;
411 lhs->db = (flags >> DESC_B_SHIFT) & 1;
412 lhs->s = (flags & DESC_S_MASK) != 0;
413 lhs->l = (flags >> DESC_L_SHIFT) & 1;
414 lhs->g = (flags & DESC_G_MASK) != 0;
415 lhs->avl = (flags & DESC_AVL_MASK) != 0;
416 lhs->unusable = 0;
417}
418
419static void get_seg(SegmentCache *lhs, const struct kvm_segment *rhs)
420{
421 lhs->selector = rhs->selector;
422 lhs->base = rhs->base;
423 lhs->limit = rhs->limit;
424 lhs->flags =
425 (rhs->type << DESC_TYPE_SHIFT)
426 | (rhs->present * DESC_P_MASK)
427 | (rhs->dpl << DESC_DPL_SHIFT)
428 | (rhs->db << DESC_B_SHIFT)
429 | (rhs->s * DESC_S_MASK)
430 | (rhs->l << DESC_L_SHIFT)
431 | (rhs->g * DESC_G_MASK)
432 | (rhs->avl * DESC_AVL_MASK);
433}
434
435static void kvm_getput_reg(__u64 *kvm_reg, target_ulong *qemu_reg, int set)
436{
437 if (set)
438 *kvm_reg = *qemu_reg;
439 else
440 *qemu_reg = *kvm_reg;
441}
442
443static int kvm_getput_regs(CPUState *env, int set)
444{
445 struct kvm_regs regs;
446 int ret = 0;
447
448 if (!set) {
449 ret = kvm_vcpu_ioctl(env, KVM_GET_REGS, &regs);
450 if (ret < 0)
451 return ret;
452 }
453
454 kvm_getput_reg(&regs.rax, &env->regs[R_EAX], set);
455 kvm_getput_reg(&regs.rbx, &env->regs[R_EBX], set);
456 kvm_getput_reg(&regs.rcx, &env->regs[R_ECX], set);
457 kvm_getput_reg(&regs.rdx, &env->regs[R_EDX], set);
458 kvm_getput_reg(&regs.rsi, &env->regs[R_ESI], set);
459 kvm_getput_reg(&regs.rdi, &env->regs[R_EDI], set);
460 kvm_getput_reg(&regs.rsp, &env->regs[R_ESP], set);
461 kvm_getput_reg(&regs.rbp, &env->regs[R_EBP], set);
462#ifdef TARGET_X86_64
463 kvm_getput_reg(&regs.r8, &env->regs[8], set);
464 kvm_getput_reg(&regs.r9, &env->regs[9], set);
465 kvm_getput_reg(&regs.r10, &env->regs[10], set);
466 kvm_getput_reg(&regs.r11, &env->regs[11], set);
467 kvm_getput_reg(&regs.r12, &env->regs[12], set);
468 kvm_getput_reg(&regs.r13, &env->regs[13], set);
469 kvm_getput_reg(&regs.r14, &env->regs[14], set);
470 kvm_getput_reg(&regs.r15, &env->regs[15], set);
471#endif
472
473 kvm_getput_reg(&regs.rflags, &env->eflags, set);
474 kvm_getput_reg(&regs.rip, &env->eip, set);
475
476 if (set)
477 ret = kvm_vcpu_ioctl(env, KVM_SET_REGS, &regs);
478
479 return ret;
480}
481
482static int kvm_put_fpu(CPUState *env)
483{
484 struct kvm_fpu fpu;
485 int i;
486
487 memset(&fpu, 0, sizeof fpu);
488 fpu.fsw = env->fpus & ~(7 << 11);
489 fpu.fsw |= (env->fpstt & 7) << 11;
490 fpu.fcw = env->fpuc;
491 for (i = 0; i < 8; ++i)
492 fpu.ftwx |= (!env->fptags[i]) << i;
493 memcpy(fpu.fpr, env->fpregs, sizeof env->fpregs);
494 memcpy(fpu.xmm, env->xmm_regs, sizeof env->xmm_regs);
495 fpu.mxcsr = env->mxcsr;
496
497 return kvm_vcpu_ioctl(env, KVM_SET_FPU, &fpu);
498}
499
500static int kvm_put_sregs(CPUState *env)
501{
502 struct kvm_sregs sregs;
503
0e607a80
JK		 504 memset(sregs.interrupt_bitmap, 0, sizeof(sregs.interrupt_bitmap));
505 if (env->interrupt_injected >= 0) {
506 sregs.interrupt_bitmap[env->interrupt_injected / 64] |=
507 (uint64_t)1 << (env->interrupt_injected % 64);
508 }
05330448
AL		 509
510 if ((env->eflags & VM_MASK)) {
511 set_v8086_seg(&sregs.cs, &env->segs[R_CS]);
512 set_v8086_seg(&sregs.ds, &env->segs[R_DS]);
513 set_v8086_seg(&sregs.es, &env->segs[R_ES]);
514 set_v8086_seg(&sregs.fs, &env->segs[R_FS]);
515 set_v8086_seg(&sregs.gs, &env->segs[R_GS]);
516 set_v8086_seg(&sregs.ss, &env->segs[R_SS]);
517 } else {
518 set_seg(&sregs.cs, &env->segs[R_CS]);
519 set_seg(&sregs.ds, &env->segs[R_DS]);
520 set_seg(&sregs.es, &env->segs[R_ES]);
521 set_seg(&sregs.fs, &env->segs[R_FS]);
522 set_seg(&sregs.gs, &env->segs[R_GS]);
523 set_seg(&sregs.ss, &env->segs[R_SS]);
524
525 if (env->cr[0] & CR0_PE_MASK) {
526 /* force ss cpl to cs cpl */
527 sregs.ss.selector = (sregs.ss.selector & ~3) |
528 (sregs.cs.selector & 3);
529 sregs.ss.dpl = sregs.ss.selector & 3;
530 }
531 }
532
533 set_seg(&sregs.tr, &env->tr);
534 set_seg(&sregs.ldt, &env->ldt);
535
536 sregs.idt.limit = env->idt.limit;
537 sregs.idt.base = env->idt.base;
538 sregs.gdt.limit = env->gdt.limit;
539 sregs.gdt.base = env->gdt.base;
540
541 sregs.cr0 = env->cr[0];
542 sregs.cr2 = env->cr[2];
543 sregs.cr3 = env->cr[3];
544 sregs.cr4 = env->cr[4];
545
4a942cea
BS		 546 sregs.cr8 = cpu_get_apic_tpr(env->apic_state);
547 sregs.apic_base = cpu_get_apic_base(env->apic_state);
05330448
AL		 548
549 sregs.efer = env->efer;
550
551 return kvm_vcpu_ioctl(env, KVM_SET_SREGS, &sregs);
552}
553
554static void kvm_msr_entry_set(struct kvm_msr_entry *entry,
555 uint32_t index, uint64_t value)
556{
557 entry->index = index;
558 entry->data = value;
559}
560
ea643051 561static int kvm_put_msrs(CPUState *env, int level)
05330448
AL		 562{
563 struct {
564 struct kvm_msrs info;
565 struct kvm_msr_entry entries[100];
566 } msr_data;
567 struct kvm_msr_entry *msrs = msr_data.entries;
568 int n = 0;
569
570 kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_CS, env->sysenter_cs);
571 kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_ESP, env->sysenter_esp);
572 kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_EIP, env->sysenter_eip);
573 if (kvm_has_msr_star(env))
574 kvm_msr_entry_set(&msrs[n++], MSR_STAR, env->star);
05330448
AL		 575#ifdef TARGET_X86_64
576 /* FIXME if lm capable */
577 kvm_msr_entry_set(&msrs[n++], MSR_CSTAR, env->cstar);
578 kvm_msr_entry_set(&msrs[n++], MSR_KERNELGSBASE, env->kernelgsbase);
579 kvm_msr_entry_set(&msrs[n++], MSR_FMASK, env->fmask);
580 kvm_msr_entry_set(&msrs[n++], MSR_LSTAR, env->lstar);
581#endif
ea643051
JK		 582 if (level == KVM_PUT_FULL_STATE) {
583 kvm_msr_entry_set(&msrs[n++], MSR_IA32_TSC, env->tsc);
584 kvm_msr_entry_set(&msrs[n++], MSR_KVM_SYSTEM_TIME,
585 env->system_time_msr);
586 kvm_msr_entry_set(&msrs[n++], MSR_KVM_WALL_CLOCK, env->wall_clock_msr);
587 }
1a03675d 588
05330448
AL		 589 msr_data.info.nmsrs = n;
590
591 return kvm_vcpu_ioctl(env, KVM_SET_MSRS, &msr_data);
592
593}
594
595
596static int kvm_get_fpu(CPUState *env)
597{
598 struct kvm_fpu fpu;
599 int i, ret;
600
601 ret = kvm_vcpu_ioctl(env, KVM_GET_FPU, &fpu);
602 if (ret < 0)
603 return ret;
604
605 env->fpstt = (fpu.fsw >> 11) & 7;
606 env->fpus = fpu.fsw;
607 env->fpuc = fpu.fcw;
608 for (i = 0; i < 8; ++i)
609 env->fptags[i] = !((fpu.ftwx >> i) & 1);
610 memcpy(env->fpregs, fpu.fpr, sizeof env->fpregs);
611 memcpy(env->xmm_regs, fpu.xmm, sizeof env->xmm_regs);
612 env->mxcsr = fpu.mxcsr;
613
614 return 0;
615}
616
617static int kvm_get_sregs(CPUState *env)
618{
619 struct kvm_sregs sregs;
620 uint32_t hflags;
0e607a80 621 int bit, i, ret;
05330448
AL		 622
623 ret = kvm_vcpu_ioctl(env, KVM_GET_SREGS, &sregs);
624 if (ret < 0)
625 return ret;
626
0e607a80
JK		 627 /* There can only be one pending IRQ set in the bitmap at a time, so try
628 to find it and save its number instead (-1 for none). */
629 env->interrupt_injected = -1;
630 for (i = 0; i < ARRAY_SIZE(sregs.interrupt_bitmap); i++) {
631 if (sregs.interrupt_bitmap[i]) {
632 bit = ctz64(sregs.interrupt_bitmap[i]);
633 env->interrupt_injected = i * 64 + bit;
634 break;
635 }
636 }
05330448
AL		 637
638 get_seg(&env->segs[R_CS], &sregs.cs);
639 get_seg(&env->segs[R_DS], &sregs.ds);
640 get_seg(&env->segs[R_ES], &sregs.es);
641 get_seg(&env->segs[R_FS], &sregs.fs);
642 get_seg(&env->segs[R_GS], &sregs.gs);
643 get_seg(&env->segs[R_SS], &sregs.ss);
644
645 get_seg(&env->tr, &sregs.tr);
646 get_seg(&env->ldt, &sregs.ldt);
647
648 env->idt.limit = sregs.idt.limit;
649 env->idt.base = sregs.idt.base;
650 env->gdt.limit = sregs.gdt.limit;
651 env->gdt.base = sregs.gdt.base;
652
653 env->cr[0] = sregs.cr0;
654 env->cr[2] = sregs.cr2;
655 env->cr[3] = sregs.cr3;
656 env->cr[4] = sregs.cr4;
657
4a942cea 658 cpu_set_apic_base(env->apic_state, sregs.apic_base);
05330448
AL		 659
660 env->efer = sregs.efer;
4a942cea 661 //cpu_set_apic_tpr(env->apic_state, sregs.cr8);
05330448
AL		 662
663#define HFLAG_COPY_MASK ~( \
664 HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \
665 HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \
666 HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \
667 HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK)
668
669
670
671 hflags = (env->segs[R_CS].flags >> DESC_DPL_SHIFT) & HF_CPL_MASK;
672 hflags |= (env->cr[0] & CR0_PE_MASK) << (HF_PE_SHIFT - CR0_PE_SHIFT);
673 hflags |= (env->cr[0] << (HF_MP_SHIFT - CR0_MP_SHIFT)) &
674 (HF_MP_MASK | HF_EM_MASK | HF_TS_MASK);
675 hflags |= (env->eflags & (HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK));
676 hflags |= (env->cr[4] & CR4_OSFXSR_MASK) <<
677 (HF_OSFXSR_SHIFT - CR4_OSFXSR_SHIFT);
678
679 if (env->efer & MSR_EFER_LMA) {
680 hflags |= HF_LMA_MASK;
681 }
682
683 if ((hflags & HF_LMA_MASK) && (env->segs[R_CS].flags & DESC_L_MASK)) {
684 hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK;
685 } else {
686 hflags |= (env->segs[R_CS].flags & DESC_B_MASK) >>
687 (DESC_B_SHIFT - HF_CS32_SHIFT);
688 hflags |= (env->segs[R_SS].flags & DESC_B_MASK) >>
689 (DESC_B_SHIFT - HF_SS32_SHIFT);
690 if (!(env->cr[0] & CR0_PE_MASK) ||
691 (env->eflags & VM_MASK) ||
692 !(hflags & HF_CS32_MASK)) {
693 hflags |= HF_ADDSEG_MASK;
694 } else {
695 hflags |= ((env->segs[R_DS].base |
696 env->segs[R_ES].base |
697 env->segs[R_SS].base) != 0) <<
698 HF_ADDSEG_SHIFT;
699 }
700 }
701 env->hflags = (env->hflags & HFLAG_COPY_MASK) | hflags;
05330448
AL		 702
703 return 0;
704}
705
706static int kvm_get_msrs(CPUState *env)
707{
708 struct {
709 struct kvm_msrs info;
710 struct kvm_msr_entry entries[100];
711 } msr_data;
712 struct kvm_msr_entry *msrs = msr_data.entries;
713 int ret, i, n;
714
715 n = 0;
716 msrs[n++].index = MSR_IA32_SYSENTER_CS;
717 msrs[n++].index = MSR_IA32_SYSENTER_ESP;
718 msrs[n++].index = MSR_IA32_SYSENTER_EIP;
719 if (kvm_has_msr_star(env))
720 msrs[n++].index = MSR_STAR;
721 msrs[n++].index = MSR_IA32_TSC;
722#ifdef TARGET_X86_64
723 /* FIXME lm_capable_kernel */
724 msrs[n++].index = MSR_CSTAR;
725 msrs[n++].index = MSR_KERNELGSBASE;
726 msrs[n++].index = MSR_FMASK;
727 msrs[n++].index = MSR_LSTAR;
728#endif
1a03675d
GC		 729 msrs[n++].index = MSR_KVM_SYSTEM_TIME;
730 msrs[n++].index = MSR_KVM_WALL_CLOCK;
731
05330448
AL		 732 msr_data.info.nmsrs = n;
733 ret = kvm_vcpu_ioctl(env, KVM_GET_MSRS, &msr_data);
734 if (ret < 0)
735 return ret;
736
737 for (i = 0; i < ret; i++) {
738 switch (msrs[i].index) {
739 case MSR_IA32_SYSENTER_CS:
740 env->sysenter_cs = msrs[i].data;
741 break;
742 case MSR_IA32_SYSENTER_ESP:
743 env->sysenter_esp = msrs[i].data;
744 break;
745 case MSR_IA32_SYSENTER_EIP:
746 env->sysenter_eip = msrs[i].data;
747 break;
748 case MSR_STAR:
749 env->star = msrs[i].data;
750 break;
751#ifdef TARGET_X86_64
752 case MSR_CSTAR:
753 env->cstar = msrs[i].data;
754 break;
755 case MSR_KERNELGSBASE:
756 env->kernelgsbase = msrs[i].data;
757 break;
758 case MSR_FMASK:
759 env->fmask = msrs[i].data;
760 break;
761 case MSR_LSTAR:
762 env->lstar = msrs[i].data;
763 break;
764#endif
765 case MSR_IA32_TSC:
766 env->tsc = msrs[i].data;
767 break;
1a03675d
GC		 768 case MSR_KVM_SYSTEM_TIME:
769 env->system_time_msr = msrs[i].data;
770 break;
771 case MSR_KVM_WALL_CLOCK:
772 env->wall_clock_msr = msrs[i].data;
773 break;
05330448
AL		 774 }
775 }
776
777 return 0;
778}
779
9bdbe550
HB		 780static int kvm_put_mp_state(CPUState *env)
781{
782 struct kvm_mp_state mp_state = { .mp_state = env->mp_state };
783
784 return kvm_vcpu_ioctl(env, KVM_SET_MP_STATE, &mp_state);
785}
786
787static int kvm_get_mp_state(CPUState *env)
788{
789 struct kvm_mp_state mp_state;
790 int ret;
791
792 ret = kvm_vcpu_ioctl(env, KVM_GET_MP_STATE, &mp_state);
793 if (ret < 0) {
794 return ret;
795 }
796 env->mp_state = mp_state.mp_state;
797 return 0;
798}
799
ea643051 800static int kvm_put_vcpu_events(CPUState *env, int level)
a0fb002c
JK		 801{
802#ifdef KVM_CAP_VCPU_EVENTS
803 struct kvm_vcpu_events events;
804
805 if (!kvm_has_vcpu_events()) {
806 return 0;
807 }
808
31827373
JK		 809 events.exception.injected = (env->exception_injected >= 0);
810 events.exception.nr = env->exception_injected;
a0fb002c
JK		 811 events.exception.has_error_code = env->has_error_code;
812 events.exception.error_code = env->error_code;
813
814 events.interrupt.injected = (env->interrupt_injected >= 0);
815 events.interrupt.nr = env->interrupt_injected;
816 events.interrupt.soft = env->soft_interrupt;
817
818 events.nmi.injected = env->nmi_injected;
819 events.nmi.pending = env->nmi_pending;
820 events.nmi.masked = !!(env->hflags2 & HF2_NMI_MASK);
821
822 events.sipi_vector = env->sipi_vector;
823
ea643051
JK		 824 events.flags = 0;
825 if (level >= KVM_PUT_RESET_STATE) {
826 events.flags |=
827 KVM_VCPUEVENT_VALID_NMI_PENDING | KVM_VCPUEVENT_VALID_SIPI_VECTOR;
828 }
aee028b9 829
a0fb002c
JK		 830 return kvm_vcpu_ioctl(env, KVM_SET_VCPU_EVENTS, &events);
831#else
832 return 0;
833#endif
834}
835
836static int kvm_get_vcpu_events(CPUState *env)
837{
838#ifdef KVM_CAP_VCPU_EVENTS
839 struct kvm_vcpu_events events;
840 int ret;
841
842 if (!kvm_has_vcpu_events()) {
843 return 0;
844 }
845
846 ret = kvm_vcpu_ioctl(env, KVM_GET_VCPU_EVENTS, &events);
847 if (ret < 0) {
848 return ret;
849 }
31827373 850 env->exception_injected =
a0fb002c
JK		 851 events.exception.injected ? events.exception.nr : -1;
852 env->has_error_code = events.exception.has_error_code;
853 env->error_code = events.exception.error_code;
854
855 env->interrupt_injected =
856 events.interrupt.injected ? events.interrupt.nr : -1;
857 env->soft_interrupt = events.interrupt.soft;
858
859 env->nmi_injected = events.nmi.injected;
860 env->nmi_pending = events.nmi.pending;
861 if (events.nmi.masked) {
862 env->hflags2 |= HF2_NMI_MASK;
863 } else {
864 env->hflags2 &= ~HF2_NMI_MASK;
865 }
866
867 env->sipi_vector = events.sipi_vector;
868#endif
869
870 return 0;
871}
872
b0b1d690
JK		 873static int kvm_guest_debug_workarounds(CPUState *env)
874{
875 int ret = 0;
876#ifdef KVM_CAP_SET_GUEST_DEBUG
877 unsigned long reinject_trap = 0;
878
879 if (!kvm_has_vcpu_events()) {
880 if (env->exception_injected == 1) {
881 reinject_trap = KVM_GUESTDBG_INJECT_DB;
882 } else if (env->exception_injected == 3) {
883 reinject_trap = KVM_GUESTDBG_INJECT_BP;
884 }
885 env->exception_injected = -1;
886 }
887
888 /*
889 * Kernels before KVM_CAP_X86_ROBUST_SINGLESTEP overwrote flags.TF
890 * injected via SET_GUEST_DEBUG while updating GP regs. Work around this
891 * by updating the debug state once again if single-stepping is on.
892 * Another reason to call kvm_update_guest_debug here is a pending debug
893 * trap raise by the guest. On kernels without SET_VCPU_EVENTS we have to
894 * reinject them via SET_GUEST_DEBUG.
895 */
896 if (reinject_trap ||
897 (!kvm_has_robust_singlestep() && env->singlestep_enabled)) {
898 ret = kvm_update_guest_debug(env, reinject_trap);
899 }
900#endif /* KVM_CAP_SET_GUEST_DEBUG */
901 return ret;
902}
903
ff44f1a3
JK		 904static int kvm_put_debugregs(CPUState *env)
905{
906#ifdef KVM_CAP_DEBUGREGS
907 struct kvm_debugregs dbgregs;
908 int i;
909
910 if (!kvm_has_debugregs()) {
911 return 0;
912 }
913
914 for (i = 0; i < 4; i++) {
915 dbgregs.db[i] = env->dr[i];
916 }
917 dbgregs.dr6 = env->dr[6];
918 dbgregs.dr7 = env->dr[7];
919 dbgregs.flags = 0;
920
921 return kvm_vcpu_ioctl(env, KVM_SET_DEBUGREGS, &dbgregs);
922#else
923 return 0;
924#endif
925}
926
927static int kvm_get_debugregs(CPUState *env)
928{
929#ifdef KVM_CAP_DEBUGREGS
930 struct kvm_debugregs dbgregs;
931 int i, ret;
932
933 if (!kvm_has_debugregs()) {
934 return 0;
935 }
936
937 ret = kvm_vcpu_ioctl(env, KVM_GET_DEBUGREGS, &dbgregs);
938 if (ret < 0) {
939 return ret;
940 }
941 for (i = 0; i < 4; i++) {
942 env->dr[i] = dbgregs.db[i];
943 }
944 env->dr[4] = env->dr[6] = dbgregs.dr6;
945 env->dr[5] = env->dr[7] = dbgregs.dr7;
946#endif
947
948 return 0;
949}
950
ea375f9a 951int kvm_arch_put_registers(CPUState *env, int level)
05330448
AL		 952{
953 int ret;
954
dbaa07c4
JK		 955 assert(cpu_is_stopped(env) || qemu_cpu_self(env));
956
05330448
AL		 957 ret = kvm_getput_regs(env, 1);
958 if (ret < 0)
959 return ret;
960
961 ret = kvm_put_fpu(env);
962 if (ret < 0)
963 return ret;
964
965 ret = kvm_put_sregs(env);
966 if (ret < 0)
967 return ret;
968
ea643051 969 ret = kvm_put_msrs(env, level);
05330448
AL		 970 if (ret < 0)
971 return ret;
972
ea643051
JK		 973 if (level >= KVM_PUT_RESET_STATE) {
974 ret = kvm_put_mp_state(env);
975 if (ret < 0)
976 return ret;
977 }
f8d926e9 978
ea643051 979 ret = kvm_put_vcpu_events(env, level);
a0fb002c
JK		 980 if (ret < 0)
981 return ret;
982
b0b1d690
JK		 983 /* must be last */
984 ret = kvm_guest_debug_workarounds(env);
985 if (ret < 0)
986 return ret;
987
ff44f1a3
JK		 988 ret = kvm_put_debugregs(env);
989 if (ret < 0)
990 return ret;
991
05330448
AL		 992 return 0;
993}
994
995int kvm_arch_get_registers(CPUState *env)
996{
997 int ret;
998
dbaa07c4
JK		 999 assert(cpu_is_stopped(env) || qemu_cpu_self(env));
1000
05330448
AL		 1001 ret = kvm_getput_regs(env, 0);
1002 if (ret < 0)
1003 return ret;
1004
1005 ret = kvm_get_fpu(env);
1006 if (ret < 0)
1007 return ret;
1008
1009 ret = kvm_get_sregs(env);
1010 if (ret < 0)
1011 return ret;
1012
1013 ret = kvm_get_msrs(env);
1014 if (ret < 0)
1015 return ret;
1016
5a2e3c2e
JK		 1017 ret = kvm_get_mp_state(env);
1018 if (ret < 0)
1019 return ret;
1020
a0fb002c
JK		 1021 ret = kvm_get_vcpu_events(env);
1022 if (ret < 0)
1023 return ret;
1024
ff44f1a3
JK		 1025 ret = kvm_get_debugregs(env);
1026 if (ret < 0)
1027 return ret;
1028
05330448
AL		 1029 return 0;
1030}
1031
1032int kvm_arch_pre_run(CPUState *env, struct kvm_run *run)
1033{
1034 /* Try to inject an interrupt if the guest can accept it */
1035 if (run->ready_for_interrupt_injection &&
1036 (env->interrupt_request & CPU_INTERRUPT_HARD) &&
1037 (env->eflags & IF_MASK)) {
1038 int irq;
1039
1040 env->interrupt_request &= ~CPU_INTERRUPT_HARD;
1041 irq = cpu_get_pic_interrupt(env);
1042 if (irq >= 0) {
1043 struct kvm_interrupt intr;
1044 intr.irq = irq;
1045 /* FIXME: errors */
8c0d577e 1046 DPRINTF("injected interrupt %d\n", irq);
05330448
AL		 1047 kvm_vcpu_ioctl(env, KVM_INTERRUPT, &intr);
1048 }
1049 }
1050
1051 /* If we have an interrupt but the guest is not ready to receive an
1052 * interrupt, request an interrupt window exit. This will
1053 * cause a return to userspace as soon as the guest is ready to
1054 * receive interrupts. */
1055 if ((env->interrupt_request & CPU_INTERRUPT_HARD))
1056 run->request_interrupt_window = 1;
1057 else
1058 run->request_interrupt_window = 0;
1059
8c0d577e 1060 DPRINTF("setting tpr\n");
4a942cea 1061 run->cr8 = cpu_get_apic_tpr(env->apic_state);
05330448
AL		 1062
1063 return 0;
1064}
1065
1066int kvm_arch_post_run(CPUState *env, struct kvm_run *run)
1067{
1068 if (run->if_flag)
1069 env->eflags |= IF_MASK;
1070 else
1071 env->eflags &= ~IF_MASK;
1072
4a942cea
BS		 1073 cpu_set_apic_tpr(env->apic_state, run->cr8);
1074 cpu_set_apic_base(env->apic_state, run->apic_base);
05330448
AL		 1075
1076 return 0;
1077}
1078
0af691d7
MT		 1079int kvm_arch_process_irqchip_events(CPUState *env)
1080{
1081 if (env->interrupt_request & CPU_INTERRUPT_INIT) {
1082 kvm_cpu_synchronize_state(env);
1083 do_cpu_init(env);
1084 env->exception_index = EXCP_HALTED;
1085 }
1086
1087 if (env->interrupt_request & CPU_INTERRUPT_SIPI) {
1088 kvm_cpu_synchronize_state(env);
1089 do_cpu_sipi(env);
1090 }
1091
1092 return env->halted;
1093}
1094
05330448
AL		 1095static int kvm_handle_halt(CPUState *env)
1096{
1097 if (!((env->interrupt_request & CPU_INTERRUPT_HARD) &&
1098 (env->eflags & IF_MASK)) &&
1099 !(env->interrupt_request & CPU_INTERRUPT_NMI)) {
1100 env->halted = 1;
1101 env->exception_index = EXCP_HLT;
1102 return 0;
1103 }
1104
1105 return 1;
1106}
1107
1108int kvm_arch_handle_exit(CPUState *env, struct kvm_run *run)
1109{
1110 int ret = 0;
1111
1112 switch (run->exit_reason) {
1113 case KVM_EXIT_HLT:
8c0d577e 1114 DPRINTF("handle_hlt\n");
05330448
AL		 1115 ret = kvm_handle_halt(env);
1116 break;
1117 }
1118
1119 return ret;
1120}
e22a25c9
AL		 1121
1122#ifdef KVM_CAP_SET_GUEST_DEBUG
e22a25c9
AL		 1123int kvm_arch_insert_sw_breakpoint(CPUState *env, struct kvm_sw_breakpoint *bp)
1124{
38972938 1125 static const uint8_t int3 = 0xcc;
64bf3f4e 1126
e22a25c9 1127 if (cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&bp->saved_insn, 1, 0) ||
64bf3f4e 1128 cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&int3, 1, 1))
e22a25c9
AL		 1129 return -EINVAL;
1130 return 0;
1131}
1132
1133int kvm_arch_remove_sw_breakpoint(CPUState *env, struct kvm_sw_breakpoint *bp)
1134{
1135 uint8_t int3;
1136
1137 if (cpu_memory_rw_debug(env, bp->pc, &int3, 1, 0) || int3 != 0xcc ||
64bf3f4e 1138 cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&bp->saved_insn, 1, 1))
e22a25c9
AL		 1139 return -EINVAL;
1140 return 0;
1141}
1142
1143static struct {
1144 target_ulong addr;
1145 int len;
1146 int type;
1147} hw_breakpoint[4];
1148
1149static int nb_hw_breakpoint;
1150
1151static int find_hw_breakpoint(target_ulong addr, int len, int type)
1152{
1153 int n;
1154
1155 for (n = 0; n < nb_hw_breakpoint; n++)
1156 if (hw_breakpoint[n].addr == addr && hw_breakpoint[n].type == type &&
1157 (hw_breakpoint[n].len == len || len == -1))
1158 return n;
1159 return -1;
1160}
1161
1162int kvm_arch_insert_hw_breakpoint(target_ulong addr,
1163 target_ulong len, int type)
1164{
1165 switch (type) {
1166 case GDB_BREAKPOINT_HW:
1167 len = 1;
1168 break;
1169 case GDB_WATCHPOINT_WRITE:
1170 case GDB_WATCHPOINT_ACCESS:
1171 switch (len) {
1172 case 1:
1173 break;
1174 case 2:
1175 case 4:
1176 case 8:
1177 if (addr & (len - 1))
1178 return -EINVAL;
1179 break;
1180 default:
1181 return -EINVAL;
1182 }
1183 break;
1184 default:
1185 return -ENOSYS;
1186 }
1187
1188 if (nb_hw_breakpoint == 4)
1189 return -ENOBUFS;
1190
1191 if (find_hw_breakpoint(addr, len, type) >= 0)
1192 return -EEXIST;
1193
1194 hw_breakpoint[nb_hw_breakpoint].addr = addr;
1195 hw_breakpoint[nb_hw_breakpoint].len = len;
1196 hw_breakpoint[nb_hw_breakpoint].type = type;
1197 nb_hw_breakpoint++;
1198
1199 return 0;
1200}
1201
1202int kvm_arch_remove_hw_breakpoint(target_ulong addr,
1203 target_ulong len, int type)
1204{
1205 int n;
1206
1207 n = find_hw_breakpoint(addr, (type == GDB_BREAKPOINT_HW) ? 1 : len, type);
1208 if (n < 0)
1209 return -ENOENT;
1210
1211 nb_hw_breakpoint--;
1212 hw_breakpoint[n] = hw_breakpoint[nb_hw_breakpoint];
1213
1214 return 0;
1215}
1216
1217void kvm_arch_remove_all_hw_breakpoints(void)
1218{
1219 nb_hw_breakpoint = 0;
1220}
1221
1222static CPUWatchpoint hw_watchpoint;
1223
1224int kvm_arch_debug(struct kvm_debug_exit_arch *arch_info)
1225{
1226 int handle = 0;
1227 int n;
1228
1229 if (arch_info->exception == 1) {
1230 if (arch_info->dr6 & (1 << 14)) {
1231 if (cpu_single_env->singlestep_enabled)
1232 handle = 1;
1233 } else {
1234 for (n = 0; n < 4; n++)
1235 if (arch_info->dr6 & (1 << n))
1236 switch ((arch_info->dr7 >> (16 + n*4)) & 0x3) {
1237 case 0x0:
1238 handle = 1;
1239 break;
1240 case 0x1:
1241 handle = 1;
1242 cpu_single_env->watchpoint_hit = &hw_watchpoint;
1243 hw_watchpoint.vaddr = hw_breakpoint[n].addr;
1244 hw_watchpoint.flags = BP_MEM_WRITE;
1245 break;
1246 case 0x3:
1247 handle = 1;
1248 cpu_single_env->watchpoint_hit = &hw_watchpoint;
1249 hw_watchpoint.vaddr = hw_breakpoint[n].addr;
1250 hw_watchpoint.flags = BP_MEM_ACCESS;
1251 break;
1252 }
1253 }
1254 } else if (kvm_find_sw_breakpoint(cpu_single_env, arch_info->pc))
1255 handle = 1;
1256
b0b1d690
JK		 1257 if (!handle) {
1258 cpu_synchronize_state(cpu_single_env);
1259 assert(cpu_single_env->exception_injected == -1);
1260
1261 cpu_single_env->exception_injected = arch_info->exception;
1262 cpu_single_env->has_error_code = 0;
1263 }
e22a25c9
AL		 1264
1265 return handle;
1266}
1267
1268void kvm_arch_update_guest_debug(CPUState *env, struct kvm_guest_debug *dbg)
1269{
1270 const uint8_t type_code[] = {
1271 [GDB_BREAKPOINT_HW] = 0x0,
1272 [GDB_WATCHPOINT_WRITE] = 0x1,
1273 [GDB_WATCHPOINT_ACCESS] = 0x3
1274 };
1275 const uint8_t len_code[] = {
1276 [1] = 0x0, [2] = 0x1, [4] = 0x3, [8] = 0x2
1277 };
1278 int n;
1279
1280 if (kvm_sw_breakpoints_active(env))
1281 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP;
1282
1283 if (nb_hw_breakpoint > 0) {
1284 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP;
1285 dbg->arch.debugreg[7] = 0x0600;
1286 for (n = 0; n < nb_hw_breakpoint; n++) {
1287 dbg->arch.debugreg[n] = hw_breakpoint[n].addr;
1288 dbg->arch.debugreg[7] |= (2 << (n * 2)) |
1289 (type_code[hw_breakpoint[n].type] << (16 + n*4)) |
1290 (len_code[hw_breakpoint[n].len] << (18 + n*4));
1291 }
1292 }
1293}
1294#endif /* KVM_CAP_SET_GUEST_DEBUG */
4513d923
GN		 1295
1296bool kvm_arch_stop_on_emulation_error(CPUState *env)
1297{
1298 return !(env->cr[0] & CR0_PE_MASK) ||
1299 ((env->segs[R_CS].selector & 3) != 3);
1300}
1301
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