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05330448 AL |
1 | /* |
2 | * QEMU KVM support | |
3 | * | |
4 | * Copyright (C) 2006-2008 Qumranet Technologies | |
5 | * Copyright IBM, Corp. 2008 | |
6 | * | |
7 | * Authors: | |
8 | * Anthony Liguori <aliguori@us.ibm.com> | |
9 | * | |
10 | * This work is licensed under the terms of the GNU GPL, version 2 or later. | |
11 | * See the COPYING file in the top-level directory. | |
12 | * | |
13 | */ | |
14 | ||
15 | #include <sys/types.h> | |
16 | #include <sys/ioctl.h> | |
17 | #include <sys/mman.h> | |
25d2e361 | 18 | #include <sys/utsname.h> |
05330448 AL |
19 | |
20 | #include <linux/kvm.h> | |
5802e066 | 21 | #include <linux/kvm_para.h> |
05330448 AL |
22 | |
23 | #include "qemu-common.h" | |
24 | #include "sysemu.h" | |
25 | #include "kvm.h" | |
26 | #include "cpu.h" | |
e22a25c9 | 27 | #include "gdbstub.h" |
0e607a80 | 28 | #include "host-utils.h" |
4c5b10b7 | 29 | #include "hw/pc.h" |
408392b3 | 30 | #include "hw/apic.h" |
35bed8ee | 31 | #include "ioport.h" |
05330448 AL |
32 | |
33 | //#define DEBUG_KVM | |
34 | ||
35 | #ifdef DEBUG_KVM | |
8c0d577e | 36 | #define DPRINTF(fmt, ...) \ |
05330448 AL |
37 | do { fprintf(stderr, fmt, ## __VA_ARGS__); } while (0) |
38 | #else | |
8c0d577e | 39 | #define DPRINTF(fmt, ...) \ |
05330448 AL |
40 | do { } while (0) |
41 | #endif | |
42 | ||
1a03675d GC |
43 | #define MSR_KVM_WALL_CLOCK 0x11 |
44 | #define MSR_KVM_SYSTEM_TIME 0x12 | |
45 | ||
c0532a76 MT |
46 | #ifndef BUS_MCEERR_AR |
47 | #define BUS_MCEERR_AR 4 | |
48 | #endif | |
49 | #ifndef BUS_MCEERR_AO | |
50 | #define BUS_MCEERR_AO 5 | |
51 | #endif | |
52 | ||
94a8d39a JK |
53 | const KVMCapabilityInfo kvm_arch_required_capabilities[] = { |
54 | KVM_CAP_INFO(SET_TSS_ADDR), | |
55 | KVM_CAP_INFO(EXT_CPUID), | |
56 | KVM_CAP_INFO(MP_STATE), | |
57 | KVM_CAP_LAST_INFO | |
58 | }; | |
25d2e361 | 59 | |
c3a3a7d3 JK |
60 | static bool has_msr_star; |
61 | static bool has_msr_hsave_pa; | |
c5999bfc | 62 | static bool has_msr_async_pf_en; |
25d2e361 | 63 | static int lm_capable_kernel; |
b827df58 AK |
64 | |
65 | static struct kvm_cpuid2 *try_get_cpuid(KVMState *s, int max) | |
66 | { | |
67 | struct kvm_cpuid2 *cpuid; | |
68 | int r, size; | |
69 | ||
70 | size = sizeof(*cpuid) + max * sizeof(*cpuid->entries); | |
71 | cpuid = (struct kvm_cpuid2 *)qemu_mallocz(size); | |
72 | cpuid->nent = max; | |
73 | r = kvm_ioctl(s, KVM_GET_SUPPORTED_CPUID, cpuid); | |
76ae317f MM |
74 | if (r == 0 && cpuid->nent >= max) { |
75 | r = -E2BIG; | |
76 | } | |
b827df58 AK |
77 | if (r < 0) { |
78 | if (r == -E2BIG) { | |
79 | qemu_free(cpuid); | |
80 | return NULL; | |
81 | } else { | |
82 | fprintf(stderr, "KVM_GET_SUPPORTED_CPUID failed: %s\n", | |
83 | strerror(-r)); | |
84 | exit(1); | |
85 | } | |
86 | } | |
87 | return cpuid; | |
88 | } | |
89 | ||
0c31b744 GC |
90 | struct kvm_para_features { |
91 | int cap; | |
92 | int feature; | |
93 | } para_features[] = { | |
94 | { KVM_CAP_CLOCKSOURCE, KVM_FEATURE_CLOCKSOURCE }, | |
95 | { KVM_CAP_NOP_IO_DELAY, KVM_FEATURE_NOP_IO_DELAY }, | |
96 | { KVM_CAP_PV_MMU, KVM_FEATURE_MMU_OP }, | |
97 | #ifdef KVM_CAP_ASYNC_PF | |
98 | { KVM_CAP_ASYNC_PF, KVM_FEATURE_ASYNC_PF }, | |
99 | #endif | |
100 | { -1, -1 } | |
101 | }; | |
102 | ||
103 | static int get_para_features(CPUState *env) | |
104 | { | |
105 | int i, features = 0; | |
106 | ||
107 | for (i = 0; i < ARRAY_SIZE(para_features) - 1; i++) { | |
108 | if (kvm_check_extension(env->kvm_state, para_features[i].cap)) { | |
109 | features |= (1 << para_features[i].feature); | |
110 | } | |
111 | } | |
112 | ||
113 | return features; | |
114 | } | |
0c31b744 GC |
115 | |
116 | ||
c958a8bd SY |
117 | uint32_t kvm_arch_get_supported_cpuid(CPUState *env, uint32_t function, |
118 | uint32_t index, int reg) | |
b827df58 AK |
119 | { |
120 | struct kvm_cpuid2 *cpuid; | |
121 | int i, max; | |
122 | uint32_t ret = 0; | |
123 | uint32_t cpuid_1_edx; | |
0c31b744 | 124 | int has_kvm_features = 0; |
b827df58 | 125 | |
b827df58 AK |
126 | max = 1; |
127 | while ((cpuid = try_get_cpuid(env->kvm_state, max)) == NULL) { | |
128 | max *= 2; | |
129 | } | |
130 | ||
131 | for (i = 0; i < cpuid->nent; ++i) { | |
c958a8bd SY |
132 | if (cpuid->entries[i].function == function && |
133 | cpuid->entries[i].index == index) { | |
0c31b744 GC |
134 | if (cpuid->entries[i].function == KVM_CPUID_FEATURES) { |
135 | has_kvm_features = 1; | |
136 | } | |
b827df58 AK |
137 | switch (reg) { |
138 | case R_EAX: | |
139 | ret = cpuid->entries[i].eax; | |
140 | break; | |
141 | case R_EBX: | |
142 | ret = cpuid->entries[i].ebx; | |
143 | break; | |
144 | case R_ECX: | |
145 | ret = cpuid->entries[i].ecx; | |
146 | break; | |
147 | case R_EDX: | |
148 | ret = cpuid->entries[i].edx; | |
19ccb8ea JK |
149 | switch (function) { |
150 | case 1: | |
151 | /* KVM before 2.6.30 misreports the following features */ | |
152 | ret |= CPUID_MTRR | CPUID_PAT | CPUID_MCE | CPUID_MCA; | |
153 | break; | |
154 | case 0x80000001: | |
b827df58 AK |
155 | /* On Intel, kvm returns cpuid according to the Intel spec, |
156 | * so add missing bits according to the AMD spec: | |
157 | */ | |
c958a8bd | 158 | cpuid_1_edx = kvm_arch_get_supported_cpuid(env, 1, 0, R_EDX); |
c1667e40 | 159 | ret |= cpuid_1_edx & 0x183f7ff; |
19ccb8ea | 160 | break; |
b827df58 AK |
161 | } |
162 | break; | |
163 | } | |
164 | } | |
165 | } | |
166 | ||
167 | qemu_free(cpuid); | |
168 | ||
0c31b744 GC |
169 | /* fallback for older kernels */ |
170 | if (!has_kvm_features && (function == KVM_CPUID_FEATURES)) { | |
171 | ret = get_para_features(env); | |
b9bec74b | 172 | } |
0c31b744 GC |
173 | |
174 | return ret; | |
bb0300dc | 175 | } |
bb0300dc | 176 | |
3c85e74f HY |
177 | typedef struct HWPoisonPage { |
178 | ram_addr_t ram_addr; | |
179 | QLIST_ENTRY(HWPoisonPage) list; | |
180 | } HWPoisonPage; | |
181 | ||
182 | static QLIST_HEAD(, HWPoisonPage) hwpoison_page_list = | |
183 | QLIST_HEAD_INITIALIZER(hwpoison_page_list); | |
184 | ||
185 | static void kvm_unpoison_all(void *param) | |
186 | { | |
187 | HWPoisonPage *page, *next_page; | |
188 | ||
189 | QLIST_FOREACH_SAFE(page, &hwpoison_page_list, list, next_page) { | |
190 | QLIST_REMOVE(page, list); | |
191 | qemu_ram_remap(page->ram_addr, TARGET_PAGE_SIZE); | |
192 | qemu_free(page); | |
193 | } | |
194 | } | |
195 | ||
e7701825 | 196 | #ifdef KVM_CAP_MCE |
3c85e74f HY |
197 | static void kvm_hwpoison_page_add(ram_addr_t ram_addr) |
198 | { | |
199 | HWPoisonPage *page; | |
200 | ||
201 | QLIST_FOREACH(page, &hwpoison_page_list, list) { | |
202 | if (page->ram_addr == ram_addr) { | |
203 | return; | |
204 | } | |
205 | } | |
206 | page = qemu_malloc(sizeof(HWPoisonPage)); | |
207 | page->ram_addr = ram_addr; | |
208 | QLIST_INSERT_HEAD(&hwpoison_page_list, page, list); | |
209 | } | |
210 | ||
e7701825 MT |
211 | static int kvm_get_mce_cap_supported(KVMState *s, uint64_t *mce_cap, |
212 | int *max_banks) | |
213 | { | |
214 | int r; | |
215 | ||
14a09518 | 216 | r = kvm_check_extension(s, KVM_CAP_MCE); |
e7701825 MT |
217 | if (r > 0) { |
218 | *max_banks = r; | |
219 | return kvm_ioctl(s, KVM_X86_GET_MCE_CAP_SUPPORTED, mce_cap); | |
220 | } | |
221 | return -ENOSYS; | |
222 | } | |
223 | ||
c34d440a | 224 | static void kvm_mce_inject(CPUState *env, target_phys_addr_t paddr, int code) |
e7701825 | 225 | { |
c34d440a JK |
226 | uint64_t status = MCI_STATUS_VAL | MCI_STATUS_UC | MCI_STATUS_EN | |
227 | MCI_STATUS_MISCV | MCI_STATUS_ADDRV | MCI_STATUS_S; | |
228 | uint64_t mcg_status = MCG_STATUS_MCIP; | |
e7701825 | 229 | |
c34d440a JK |
230 | if (code == BUS_MCEERR_AR) { |
231 | status |= MCI_STATUS_AR | 0x134; | |
232 | mcg_status |= MCG_STATUS_EIPV; | |
233 | } else { | |
234 | status |= 0xc0; | |
235 | mcg_status |= MCG_STATUS_RIPV; | |
419fb20a | 236 | } |
c34d440a JK |
237 | cpu_x86_inject_mce(NULL, env, 9, status, mcg_status, paddr, |
238 | (MCM_ADDR_PHYS << 6) | 0xc, | |
239 | cpu_x86_support_mca_broadcast(env) ? | |
240 | MCE_INJECT_BROADCAST : 0); | |
419fb20a JK |
241 | } |
242 | #endif /* KVM_CAP_MCE */ | |
243 | ||
244 | static void hardware_memory_error(void) | |
245 | { | |
246 | fprintf(stderr, "Hardware memory error!\n"); | |
247 | exit(1); | |
248 | } | |
249 | ||
250 | int kvm_arch_on_sigbus_vcpu(CPUState *env, int code, void *addr) | |
251 | { | |
252 | #ifdef KVM_CAP_MCE | |
419fb20a JK |
253 | ram_addr_t ram_addr; |
254 | target_phys_addr_t paddr; | |
255 | ||
256 | if ((env->mcg_cap & MCG_SER_P) && addr | |
c34d440a JK |
257 | && (code == BUS_MCEERR_AR || code == BUS_MCEERR_AO)) { |
258 | if (qemu_ram_addr_from_host(addr, &ram_addr) || | |
259 | !kvm_physical_memory_addr_from_ram(env->kvm_state, ram_addr, | |
260 | &paddr)) { | |
419fb20a JK |
261 | fprintf(stderr, "Hardware memory error for memory used by " |
262 | "QEMU itself instead of guest system!\n"); | |
263 | /* Hope we are lucky for AO MCE */ | |
264 | if (code == BUS_MCEERR_AO) { | |
265 | return 0; | |
266 | } else { | |
267 | hardware_memory_error(); | |
268 | } | |
269 | } | |
3c85e74f | 270 | kvm_hwpoison_page_add(ram_addr); |
c34d440a | 271 | kvm_mce_inject(env, paddr, code); |
419fb20a JK |
272 | } else |
273 | #endif /* KVM_CAP_MCE */ | |
274 | { | |
275 | if (code == BUS_MCEERR_AO) { | |
276 | return 0; | |
277 | } else if (code == BUS_MCEERR_AR) { | |
278 | hardware_memory_error(); | |
279 | } else { | |
280 | return 1; | |
281 | } | |
282 | } | |
283 | return 0; | |
284 | } | |
285 | ||
286 | int kvm_arch_on_sigbus(int code, void *addr) | |
287 | { | |
288 | #ifdef KVM_CAP_MCE | |
289 | if ((first_cpu->mcg_cap & MCG_SER_P) && addr && code == BUS_MCEERR_AO) { | |
419fb20a JK |
290 | ram_addr_t ram_addr; |
291 | target_phys_addr_t paddr; | |
292 | ||
293 | /* Hope we are lucky for AO MCE */ | |
c34d440a | 294 | if (qemu_ram_addr_from_host(addr, &ram_addr) || |
419fb20a JK |
295 | !kvm_physical_memory_addr_from_ram(first_cpu->kvm_state, ram_addr, |
296 | &paddr)) { | |
297 | fprintf(stderr, "Hardware memory error for memory used by " | |
298 | "QEMU itself instead of guest system!: %p\n", addr); | |
299 | return 0; | |
300 | } | |
3c85e74f | 301 | kvm_hwpoison_page_add(ram_addr); |
c34d440a | 302 | kvm_mce_inject(first_cpu, paddr, code); |
419fb20a JK |
303 | } else |
304 | #endif /* KVM_CAP_MCE */ | |
305 | { | |
306 | if (code == BUS_MCEERR_AO) { | |
307 | return 0; | |
308 | } else if (code == BUS_MCEERR_AR) { | |
309 | hardware_memory_error(); | |
310 | } else { | |
311 | return 1; | |
312 | } | |
313 | } | |
314 | return 0; | |
315 | } | |
e7701825 | 316 | |
ab443475 JK |
317 | static int kvm_inject_mce_oldstyle(CPUState *env) |
318 | { | |
319 | #ifdef KVM_CAP_MCE | |
320 | if (!kvm_has_vcpu_events() && env->exception_injected == EXCP12_MCHK) { | |
321 | unsigned int bank, bank_num = env->mcg_cap & 0xff; | |
322 | struct kvm_x86_mce mce; | |
323 | ||
324 | env->exception_injected = -1; | |
325 | ||
326 | /* | |
327 | * There must be at least one bank in use if an MCE is pending. | |
328 | * Find it and use its values for the event injection. | |
329 | */ | |
330 | for (bank = 0; bank < bank_num; bank++) { | |
331 | if (env->mce_banks[bank * 4 + 1] & MCI_STATUS_VAL) { | |
332 | break; | |
333 | } | |
334 | } | |
335 | assert(bank < bank_num); | |
336 | ||
337 | mce.bank = bank; | |
338 | mce.status = env->mce_banks[bank * 4 + 1]; | |
339 | mce.mcg_status = env->mcg_status; | |
340 | mce.addr = env->mce_banks[bank * 4 + 2]; | |
341 | mce.misc = env->mce_banks[bank * 4 + 3]; | |
342 | ||
343 | return kvm_vcpu_ioctl(env, KVM_X86_SET_MCE, &mce); | |
344 | } | |
345 | #endif /* KVM_CAP_MCE */ | |
346 | return 0; | |
347 | } | |
348 | ||
b8cc45d6 GC |
349 | static void cpu_update_state(void *opaque, int running, int reason) |
350 | { | |
351 | CPUState *env = opaque; | |
352 | ||
353 | if (running) { | |
354 | env->tsc_valid = false; | |
355 | } | |
356 | } | |
357 | ||
05330448 AL |
358 | int kvm_arch_init_vcpu(CPUState *env) |
359 | { | |
360 | struct { | |
486bd5a2 AL |
361 | struct kvm_cpuid2 cpuid; |
362 | struct kvm_cpuid_entry2 entries[100]; | |
05330448 | 363 | } __attribute__((packed)) cpuid_data; |
486bd5a2 | 364 | uint32_t limit, i, j, cpuid_i; |
a33609ca | 365 | uint32_t unused; |
bb0300dc | 366 | struct kvm_cpuid_entry2 *c; |
bb0300dc | 367 | uint32_t signature[3]; |
05330448 | 368 | |
c958a8bd | 369 | env->cpuid_features &= kvm_arch_get_supported_cpuid(env, 1, 0, R_EDX); |
6c0d7ee8 AP |
370 | |
371 | i = env->cpuid_ext_features & CPUID_EXT_HYPERVISOR; | |
c958a8bd | 372 | env->cpuid_ext_features &= kvm_arch_get_supported_cpuid(env, 1, 0, R_ECX); |
6c0d7ee8 AP |
373 | env->cpuid_ext_features |= i; |
374 | ||
457dfed6 | 375 | env->cpuid_ext2_features &= kvm_arch_get_supported_cpuid(env, 0x80000001, |
c958a8bd | 376 | 0, R_EDX); |
457dfed6 | 377 | env->cpuid_ext3_features &= kvm_arch_get_supported_cpuid(env, 0x80000001, |
c958a8bd | 378 | 0, R_ECX); |
296acb64 JR |
379 | env->cpuid_svm_features &= kvm_arch_get_supported_cpuid(env, 0x8000000A, |
380 | 0, R_EDX); | |
381 | ||
6c1f42fe | 382 | |
05330448 AL |
383 | cpuid_i = 0; |
384 | ||
bb0300dc GN |
385 | /* Paravirtualization CPUIDs */ |
386 | memcpy(signature, "KVMKVMKVM\0\0\0", 12); | |
387 | c = &cpuid_data.entries[cpuid_i++]; | |
388 | memset(c, 0, sizeof(*c)); | |
389 | c->function = KVM_CPUID_SIGNATURE; | |
390 | c->eax = 0; | |
391 | c->ebx = signature[0]; | |
392 | c->ecx = signature[1]; | |
393 | c->edx = signature[2]; | |
394 | ||
395 | c = &cpuid_data.entries[cpuid_i++]; | |
396 | memset(c, 0, sizeof(*c)); | |
397 | c->function = KVM_CPUID_FEATURES; | |
0c31b744 GC |
398 | c->eax = env->cpuid_kvm_features & kvm_arch_get_supported_cpuid(env, |
399 | KVM_CPUID_FEATURES, 0, R_EAX); | |
400 | ||
401 | #ifdef KVM_CAP_ASYNC_PF | |
402 | has_msr_async_pf_en = c->eax & (1 << KVM_FEATURE_ASYNC_PF); | |
bb0300dc GN |
403 | #endif |
404 | ||
a33609ca | 405 | cpu_x86_cpuid(env, 0, 0, &limit, &unused, &unused, &unused); |
05330448 AL |
406 | |
407 | for (i = 0; i <= limit; i++) { | |
bb0300dc | 408 | c = &cpuid_data.entries[cpuid_i++]; |
486bd5a2 AL |
409 | |
410 | switch (i) { | |
a36b1029 AL |
411 | case 2: { |
412 | /* Keep reading function 2 till all the input is received */ | |
413 | int times; | |
414 | ||
a36b1029 | 415 | c->function = i; |
a33609ca AL |
416 | c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC | |
417 | KVM_CPUID_FLAG_STATE_READ_NEXT; | |
418 | cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx); | |
419 | times = c->eax & 0xff; | |
a36b1029 AL |
420 | |
421 | for (j = 1; j < times; ++j) { | |
a33609ca | 422 | c = &cpuid_data.entries[cpuid_i++]; |
a36b1029 | 423 | c->function = i; |
a33609ca AL |
424 | c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC; |
425 | cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx); | |
a36b1029 AL |
426 | } |
427 | break; | |
428 | } | |
486bd5a2 AL |
429 | case 4: |
430 | case 0xb: | |
431 | case 0xd: | |
432 | for (j = 0; ; j++) { | |
486bd5a2 AL |
433 | c->function = i; |
434 | c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX; | |
435 | c->index = j; | |
a33609ca | 436 | cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx); |
486bd5a2 | 437 | |
b9bec74b | 438 | if (i == 4 && c->eax == 0) { |
486bd5a2 | 439 | break; |
b9bec74b JK |
440 | } |
441 | if (i == 0xb && !(c->ecx & 0xff00)) { | |
486bd5a2 | 442 | break; |
b9bec74b JK |
443 | } |
444 | if (i == 0xd && c->eax == 0) { | |
486bd5a2 | 445 | break; |
b9bec74b | 446 | } |
a33609ca | 447 | c = &cpuid_data.entries[cpuid_i++]; |
486bd5a2 AL |
448 | } |
449 | break; | |
450 | default: | |
486bd5a2 | 451 | c->function = i; |
a33609ca AL |
452 | c->flags = 0; |
453 | cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx); | |
486bd5a2 AL |
454 | break; |
455 | } | |
05330448 | 456 | } |
a33609ca | 457 | cpu_x86_cpuid(env, 0x80000000, 0, &limit, &unused, &unused, &unused); |
05330448 AL |
458 | |
459 | for (i = 0x80000000; i <= limit; i++) { | |
bb0300dc | 460 | c = &cpuid_data.entries[cpuid_i++]; |
05330448 | 461 | |
05330448 | 462 | c->function = i; |
a33609ca AL |
463 | c->flags = 0; |
464 | cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx); | |
05330448 AL |
465 | } |
466 | ||
b3baa152 BW |
467 | /* Call Centaur's CPUID instructions they are supported. */ |
468 | if (env->cpuid_xlevel2 > 0) { | |
469 | env->cpuid_ext4_features &= | |
470 | kvm_arch_get_supported_cpuid(env, 0xC0000001, 0, R_EDX); | |
471 | cpu_x86_cpuid(env, 0xC0000000, 0, &limit, &unused, &unused, &unused); | |
472 | ||
473 | for (i = 0xC0000000; i <= limit; i++) { | |
474 | c = &cpuid_data.entries[cpuid_i++]; | |
475 | ||
476 | c->function = i; | |
477 | c->flags = 0; | |
478 | cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx); | |
479 | } | |
480 | } | |
481 | ||
05330448 AL |
482 | cpuid_data.cpuid.nent = cpuid_i; |
483 | ||
e7701825 MT |
484 | #ifdef KVM_CAP_MCE |
485 | if (((env->cpuid_version >> 8)&0xF) >= 6 | |
486 | && (env->cpuid_features&(CPUID_MCE|CPUID_MCA)) == (CPUID_MCE|CPUID_MCA) | |
487 | && kvm_check_extension(env->kvm_state, KVM_CAP_MCE) > 0) { | |
488 | uint64_t mcg_cap; | |
489 | int banks; | |
32a42024 | 490 | int ret; |
e7701825 | 491 | |
75d49497 JK |
492 | ret = kvm_get_mce_cap_supported(env->kvm_state, &mcg_cap, &banks); |
493 | if (ret < 0) { | |
494 | fprintf(stderr, "kvm_get_mce_cap_supported: %s", strerror(-ret)); | |
495 | return ret; | |
e7701825 | 496 | } |
75d49497 JK |
497 | |
498 | if (banks > MCE_BANKS_DEF) { | |
499 | banks = MCE_BANKS_DEF; | |
500 | } | |
501 | mcg_cap &= MCE_CAP_DEF; | |
502 | mcg_cap |= banks; | |
503 | ret = kvm_vcpu_ioctl(env, KVM_X86_SETUP_MCE, &mcg_cap); | |
504 | if (ret < 0) { | |
505 | fprintf(stderr, "KVM_X86_SETUP_MCE: %s", strerror(-ret)); | |
506 | return ret; | |
507 | } | |
508 | ||
509 | env->mcg_cap = mcg_cap; | |
e7701825 MT |
510 | } |
511 | #endif | |
512 | ||
b8cc45d6 GC |
513 | qemu_add_vm_change_state_handler(cpu_update_state, env); |
514 | ||
486bd5a2 | 515 | return kvm_vcpu_ioctl(env, KVM_SET_CPUID2, &cpuid_data); |
05330448 AL |
516 | } |
517 | ||
caa5af0f JK |
518 | void kvm_arch_reset_vcpu(CPUState *env) |
519 | { | |
e73223a5 | 520 | env->exception_injected = -1; |
0e607a80 | 521 | env->interrupt_injected = -1; |
1a5e9d2f | 522 | env->xcr0 = 1; |
ddced198 MT |
523 | if (kvm_irqchip_in_kernel()) { |
524 | env->mp_state = cpu_is_bsp(env) ? KVM_MP_STATE_RUNNABLE : | |
525 | KVM_MP_STATE_UNINITIALIZED; | |
526 | } else { | |
527 | env->mp_state = KVM_MP_STATE_RUNNABLE; | |
528 | } | |
caa5af0f JK |
529 | } |
530 | ||
c3a3a7d3 | 531 | static int kvm_get_supported_msrs(KVMState *s) |
05330448 | 532 | { |
75b10c43 | 533 | static int kvm_supported_msrs; |
c3a3a7d3 | 534 | int ret = 0; |
05330448 AL |
535 | |
536 | /* first time */ | |
75b10c43 | 537 | if (kvm_supported_msrs == 0) { |
05330448 AL |
538 | struct kvm_msr_list msr_list, *kvm_msr_list; |
539 | ||
75b10c43 | 540 | kvm_supported_msrs = -1; |
05330448 AL |
541 | |
542 | /* Obtain MSR list from KVM. These are the MSRs that we must | |
543 | * save/restore */ | |
4c9f7372 | 544 | msr_list.nmsrs = 0; |
c3a3a7d3 | 545 | ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, &msr_list); |
6fb6d245 | 546 | if (ret < 0 && ret != -E2BIG) { |
c3a3a7d3 | 547 | return ret; |
6fb6d245 | 548 | } |
d9db889f JK |
549 | /* Old kernel modules had a bug and could write beyond the provided |
550 | memory. Allocate at least a safe amount of 1K. */ | |
551 | kvm_msr_list = qemu_mallocz(MAX(1024, sizeof(msr_list) + | |
552 | msr_list.nmsrs * | |
553 | sizeof(msr_list.indices[0]))); | |
05330448 | 554 | |
55308450 | 555 | kvm_msr_list->nmsrs = msr_list.nmsrs; |
c3a3a7d3 | 556 | ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, kvm_msr_list); |
05330448 AL |
557 | if (ret >= 0) { |
558 | int i; | |
559 | ||
560 | for (i = 0; i < kvm_msr_list->nmsrs; i++) { | |
561 | if (kvm_msr_list->indices[i] == MSR_STAR) { | |
c3a3a7d3 | 562 | has_msr_star = true; |
75b10c43 MT |
563 | continue; |
564 | } | |
565 | if (kvm_msr_list->indices[i] == MSR_VM_HSAVE_PA) { | |
c3a3a7d3 | 566 | has_msr_hsave_pa = true; |
75b10c43 | 567 | continue; |
05330448 AL |
568 | } |
569 | } | |
570 | } | |
571 | ||
4a043713 | 572 | qemu_free(kvm_msr_list); |
05330448 AL |
573 | } |
574 | ||
c3a3a7d3 | 575 | return ret; |
05330448 AL |
576 | } |
577 | ||
cad1e282 | 578 | int kvm_arch_init(KVMState *s) |
20420430 | 579 | { |
11076198 | 580 | uint64_t identity_base = 0xfffbc000; |
20420430 | 581 | int ret; |
25d2e361 | 582 | struct utsname utsname; |
20420430 | 583 | |
c3a3a7d3 | 584 | ret = kvm_get_supported_msrs(s); |
20420430 | 585 | if (ret < 0) { |
20420430 SY |
586 | return ret; |
587 | } | |
25d2e361 MT |
588 | |
589 | uname(&utsname); | |
590 | lm_capable_kernel = strcmp(utsname.machine, "x86_64") == 0; | |
591 | ||
4c5b10b7 | 592 | /* |
11076198 JK |
593 | * On older Intel CPUs, KVM uses vm86 mode to emulate 16-bit code directly. |
594 | * In order to use vm86 mode, an EPT identity map and a TSS are needed. | |
595 | * Since these must be part of guest physical memory, we need to allocate | |
596 | * them, both by setting their start addresses in the kernel and by | |
597 | * creating a corresponding e820 entry. We need 4 pages before the BIOS. | |
598 | * | |
599 | * Older KVM versions may not support setting the identity map base. In | |
600 | * that case we need to stick with the default, i.e. a 256K maximum BIOS | |
601 | * size. | |
4c5b10b7 | 602 | */ |
11076198 JK |
603 | #ifdef KVM_CAP_SET_IDENTITY_MAP_ADDR |
604 | if (kvm_check_extension(s, KVM_CAP_SET_IDENTITY_MAP_ADDR)) { | |
605 | /* Allows up to 16M BIOSes. */ | |
606 | identity_base = 0xfeffc000; | |
607 | ||
608 | ret = kvm_vm_ioctl(s, KVM_SET_IDENTITY_MAP_ADDR, &identity_base); | |
609 | if (ret < 0) { | |
610 | return ret; | |
611 | } | |
4c5b10b7 | 612 | } |
11076198 JK |
613 | #endif |
614 | /* Set TSS base one page after EPT identity map. */ | |
615 | ret = kvm_vm_ioctl(s, KVM_SET_TSS_ADDR, identity_base + 0x1000); | |
20420430 SY |
616 | if (ret < 0) { |
617 | return ret; | |
618 | } | |
619 | ||
11076198 JK |
620 | /* Tell fw_cfg to notify the BIOS to reserve the range. */ |
621 | ret = e820_add_entry(identity_base, 0x4000, E820_RESERVED); | |
20420430 | 622 | if (ret < 0) { |
11076198 | 623 | fprintf(stderr, "e820_add_entry() table is full\n"); |
20420430 SY |
624 | return ret; |
625 | } | |
3c85e74f | 626 | qemu_register_reset(kvm_unpoison_all, NULL); |
20420430 | 627 | |
11076198 | 628 | return 0; |
05330448 | 629 | } |
b9bec74b | 630 | |
05330448 AL |
631 | static void set_v8086_seg(struct kvm_segment *lhs, const SegmentCache *rhs) |
632 | { | |
633 | lhs->selector = rhs->selector; | |
634 | lhs->base = rhs->base; | |
635 | lhs->limit = rhs->limit; | |
636 | lhs->type = 3; | |
637 | lhs->present = 1; | |
638 | lhs->dpl = 3; | |
639 | lhs->db = 0; | |
640 | lhs->s = 1; | |
641 | lhs->l = 0; | |
642 | lhs->g = 0; | |
643 | lhs->avl = 0; | |
644 | lhs->unusable = 0; | |
645 | } | |
646 | ||
647 | static void set_seg(struct kvm_segment *lhs, const SegmentCache *rhs) | |
648 | { | |
649 | unsigned flags = rhs->flags; | |
650 | lhs->selector = rhs->selector; | |
651 | lhs->base = rhs->base; | |
652 | lhs->limit = rhs->limit; | |
653 | lhs->type = (flags >> DESC_TYPE_SHIFT) & 15; | |
654 | lhs->present = (flags & DESC_P_MASK) != 0; | |
acaa7550 | 655 | lhs->dpl = (flags >> DESC_DPL_SHIFT) & 3; |
05330448 AL |
656 | lhs->db = (flags >> DESC_B_SHIFT) & 1; |
657 | lhs->s = (flags & DESC_S_MASK) != 0; | |
658 | lhs->l = (flags >> DESC_L_SHIFT) & 1; | |
659 | lhs->g = (flags & DESC_G_MASK) != 0; | |
660 | lhs->avl = (flags & DESC_AVL_MASK) != 0; | |
661 | lhs->unusable = 0; | |
662 | } | |
663 | ||
664 | static void get_seg(SegmentCache *lhs, const struct kvm_segment *rhs) | |
665 | { | |
666 | lhs->selector = rhs->selector; | |
667 | lhs->base = rhs->base; | |
668 | lhs->limit = rhs->limit; | |
b9bec74b JK |
669 | lhs->flags = (rhs->type << DESC_TYPE_SHIFT) | |
670 | (rhs->present * DESC_P_MASK) | | |
671 | (rhs->dpl << DESC_DPL_SHIFT) | | |
672 | (rhs->db << DESC_B_SHIFT) | | |
673 | (rhs->s * DESC_S_MASK) | | |
674 | (rhs->l << DESC_L_SHIFT) | | |
675 | (rhs->g * DESC_G_MASK) | | |
676 | (rhs->avl * DESC_AVL_MASK); | |
05330448 AL |
677 | } |
678 | ||
679 | static void kvm_getput_reg(__u64 *kvm_reg, target_ulong *qemu_reg, int set) | |
680 | { | |
b9bec74b | 681 | if (set) { |
05330448 | 682 | *kvm_reg = *qemu_reg; |
b9bec74b | 683 | } else { |
05330448 | 684 | *qemu_reg = *kvm_reg; |
b9bec74b | 685 | } |
05330448 AL |
686 | } |
687 | ||
688 | static int kvm_getput_regs(CPUState *env, int set) | |
689 | { | |
690 | struct kvm_regs regs; | |
691 | int ret = 0; | |
692 | ||
693 | if (!set) { | |
694 | ret = kvm_vcpu_ioctl(env, KVM_GET_REGS, ®s); | |
b9bec74b | 695 | if (ret < 0) { |
05330448 | 696 | return ret; |
b9bec74b | 697 | } |
05330448 AL |
698 | } |
699 | ||
700 | kvm_getput_reg(®s.rax, &env->regs[R_EAX], set); | |
701 | kvm_getput_reg(®s.rbx, &env->regs[R_EBX], set); | |
702 | kvm_getput_reg(®s.rcx, &env->regs[R_ECX], set); | |
703 | kvm_getput_reg(®s.rdx, &env->regs[R_EDX], set); | |
704 | kvm_getput_reg(®s.rsi, &env->regs[R_ESI], set); | |
705 | kvm_getput_reg(®s.rdi, &env->regs[R_EDI], set); | |
706 | kvm_getput_reg(®s.rsp, &env->regs[R_ESP], set); | |
707 | kvm_getput_reg(®s.rbp, &env->regs[R_EBP], set); | |
708 | #ifdef TARGET_X86_64 | |
709 | kvm_getput_reg(®s.r8, &env->regs[8], set); | |
710 | kvm_getput_reg(®s.r9, &env->regs[9], set); | |
711 | kvm_getput_reg(®s.r10, &env->regs[10], set); | |
712 | kvm_getput_reg(®s.r11, &env->regs[11], set); | |
713 | kvm_getput_reg(®s.r12, &env->regs[12], set); | |
714 | kvm_getput_reg(®s.r13, &env->regs[13], set); | |
715 | kvm_getput_reg(®s.r14, &env->regs[14], set); | |
716 | kvm_getput_reg(®s.r15, &env->regs[15], set); | |
717 | #endif | |
718 | ||
719 | kvm_getput_reg(®s.rflags, &env->eflags, set); | |
720 | kvm_getput_reg(®s.rip, &env->eip, set); | |
721 | ||
b9bec74b | 722 | if (set) { |
05330448 | 723 | ret = kvm_vcpu_ioctl(env, KVM_SET_REGS, ®s); |
b9bec74b | 724 | } |
05330448 AL |
725 | |
726 | return ret; | |
727 | } | |
728 | ||
729 | static int kvm_put_fpu(CPUState *env) | |
730 | { | |
731 | struct kvm_fpu fpu; | |
732 | int i; | |
733 | ||
734 | memset(&fpu, 0, sizeof fpu); | |
735 | fpu.fsw = env->fpus & ~(7 << 11); | |
736 | fpu.fsw |= (env->fpstt & 7) << 11; | |
737 | fpu.fcw = env->fpuc; | |
42cc8fa6 JK |
738 | fpu.last_opcode = env->fpop; |
739 | fpu.last_ip = env->fpip; | |
740 | fpu.last_dp = env->fpdp; | |
b9bec74b JK |
741 | for (i = 0; i < 8; ++i) { |
742 | fpu.ftwx |= (!env->fptags[i]) << i; | |
743 | } | |
05330448 AL |
744 | memcpy(fpu.fpr, env->fpregs, sizeof env->fpregs); |
745 | memcpy(fpu.xmm, env->xmm_regs, sizeof env->xmm_regs); | |
746 | fpu.mxcsr = env->mxcsr; | |
747 | ||
748 | return kvm_vcpu_ioctl(env, KVM_SET_FPU, &fpu); | |
749 | } | |
750 | ||
f1665b21 SY |
751 | #ifdef KVM_CAP_XSAVE |
752 | #define XSAVE_CWD_RIP 2 | |
753 | #define XSAVE_CWD_RDP 4 | |
754 | #define XSAVE_MXCSR 6 | |
755 | #define XSAVE_ST_SPACE 8 | |
756 | #define XSAVE_XMM_SPACE 40 | |
757 | #define XSAVE_XSTATE_BV 128 | |
758 | #define XSAVE_YMMH_SPACE 144 | |
759 | #endif | |
760 | ||
761 | static int kvm_put_xsave(CPUState *env) | |
762 | { | |
763 | #ifdef KVM_CAP_XSAVE | |
0f53994f | 764 | int i, r; |
f1665b21 | 765 | struct kvm_xsave* xsave; |
42cc8fa6 | 766 | uint16_t cwd, swd, twd; |
f1665b21 | 767 | |
b9bec74b | 768 | if (!kvm_has_xsave()) { |
f1665b21 | 769 | return kvm_put_fpu(env); |
b9bec74b | 770 | } |
f1665b21 SY |
771 | |
772 | xsave = qemu_memalign(4096, sizeof(struct kvm_xsave)); | |
773 | memset(xsave, 0, sizeof(struct kvm_xsave)); | |
42cc8fa6 | 774 | cwd = swd = twd = 0; |
f1665b21 SY |
775 | swd = env->fpus & ~(7 << 11); |
776 | swd |= (env->fpstt & 7) << 11; | |
777 | cwd = env->fpuc; | |
b9bec74b | 778 | for (i = 0; i < 8; ++i) { |
f1665b21 | 779 | twd |= (!env->fptags[i]) << i; |
b9bec74b | 780 | } |
f1665b21 | 781 | xsave->region[0] = (uint32_t)(swd << 16) + cwd; |
42cc8fa6 JK |
782 | xsave->region[1] = (uint32_t)(env->fpop << 16) + twd; |
783 | memcpy(&xsave->region[XSAVE_CWD_RIP], &env->fpip, sizeof(env->fpip)); | |
784 | memcpy(&xsave->region[XSAVE_CWD_RDP], &env->fpdp, sizeof(env->fpdp)); | |
f1665b21 SY |
785 | memcpy(&xsave->region[XSAVE_ST_SPACE], env->fpregs, |
786 | sizeof env->fpregs); | |
787 | memcpy(&xsave->region[XSAVE_XMM_SPACE], env->xmm_regs, | |
788 | sizeof env->xmm_regs); | |
789 | xsave->region[XSAVE_MXCSR] = env->mxcsr; | |
790 | *(uint64_t *)&xsave->region[XSAVE_XSTATE_BV] = env->xstate_bv; | |
791 | memcpy(&xsave->region[XSAVE_YMMH_SPACE], env->ymmh_regs, | |
792 | sizeof env->ymmh_regs); | |
0f53994f MT |
793 | r = kvm_vcpu_ioctl(env, KVM_SET_XSAVE, xsave); |
794 | qemu_free(xsave); | |
795 | return r; | |
f1665b21 SY |
796 | #else |
797 | return kvm_put_fpu(env); | |
798 | #endif | |
799 | } | |
800 | ||
801 | static int kvm_put_xcrs(CPUState *env) | |
802 | { | |
803 | #ifdef KVM_CAP_XCRS | |
804 | struct kvm_xcrs xcrs; | |
805 | ||
b9bec74b | 806 | if (!kvm_has_xcrs()) { |
f1665b21 | 807 | return 0; |
b9bec74b | 808 | } |
f1665b21 SY |
809 | |
810 | xcrs.nr_xcrs = 1; | |
811 | xcrs.flags = 0; | |
812 | xcrs.xcrs[0].xcr = 0; | |
813 | xcrs.xcrs[0].value = env->xcr0; | |
814 | return kvm_vcpu_ioctl(env, KVM_SET_XCRS, &xcrs); | |
815 | #else | |
816 | return 0; | |
817 | #endif | |
818 | } | |
819 | ||
05330448 AL |
820 | static int kvm_put_sregs(CPUState *env) |
821 | { | |
822 | struct kvm_sregs sregs; | |
823 | ||
0e607a80 JK |
824 | memset(sregs.interrupt_bitmap, 0, sizeof(sregs.interrupt_bitmap)); |
825 | if (env->interrupt_injected >= 0) { | |
826 | sregs.interrupt_bitmap[env->interrupt_injected / 64] |= | |
827 | (uint64_t)1 << (env->interrupt_injected % 64); | |
828 | } | |
05330448 AL |
829 | |
830 | if ((env->eflags & VM_MASK)) { | |
b9bec74b JK |
831 | set_v8086_seg(&sregs.cs, &env->segs[R_CS]); |
832 | set_v8086_seg(&sregs.ds, &env->segs[R_DS]); | |
833 | set_v8086_seg(&sregs.es, &env->segs[R_ES]); | |
834 | set_v8086_seg(&sregs.fs, &env->segs[R_FS]); | |
835 | set_v8086_seg(&sregs.gs, &env->segs[R_GS]); | |
836 | set_v8086_seg(&sregs.ss, &env->segs[R_SS]); | |
05330448 | 837 | } else { |
b9bec74b JK |
838 | set_seg(&sregs.cs, &env->segs[R_CS]); |
839 | set_seg(&sregs.ds, &env->segs[R_DS]); | |
840 | set_seg(&sregs.es, &env->segs[R_ES]); | |
841 | set_seg(&sregs.fs, &env->segs[R_FS]); | |
842 | set_seg(&sregs.gs, &env->segs[R_GS]); | |
843 | set_seg(&sregs.ss, &env->segs[R_SS]); | |
05330448 AL |
844 | } |
845 | ||
846 | set_seg(&sregs.tr, &env->tr); | |
847 | set_seg(&sregs.ldt, &env->ldt); | |
848 | ||
849 | sregs.idt.limit = env->idt.limit; | |
850 | sregs.idt.base = env->idt.base; | |
851 | sregs.gdt.limit = env->gdt.limit; | |
852 | sregs.gdt.base = env->gdt.base; | |
853 | ||
854 | sregs.cr0 = env->cr[0]; | |
855 | sregs.cr2 = env->cr[2]; | |
856 | sregs.cr3 = env->cr[3]; | |
857 | sregs.cr4 = env->cr[4]; | |
858 | ||
4a942cea BS |
859 | sregs.cr8 = cpu_get_apic_tpr(env->apic_state); |
860 | sregs.apic_base = cpu_get_apic_base(env->apic_state); | |
05330448 AL |
861 | |
862 | sregs.efer = env->efer; | |
863 | ||
864 | return kvm_vcpu_ioctl(env, KVM_SET_SREGS, &sregs); | |
865 | } | |
866 | ||
867 | static void kvm_msr_entry_set(struct kvm_msr_entry *entry, | |
868 | uint32_t index, uint64_t value) | |
869 | { | |
870 | entry->index = index; | |
871 | entry->data = value; | |
872 | } | |
873 | ||
ea643051 | 874 | static int kvm_put_msrs(CPUState *env, int level) |
05330448 AL |
875 | { |
876 | struct { | |
877 | struct kvm_msrs info; | |
878 | struct kvm_msr_entry entries[100]; | |
879 | } msr_data; | |
880 | struct kvm_msr_entry *msrs = msr_data.entries; | |
d8da8574 | 881 | int n = 0; |
05330448 AL |
882 | |
883 | kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_CS, env->sysenter_cs); | |
884 | kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_ESP, env->sysenter_esp); | |
885 | kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_EIP, env->sysenter_eip); | |
0c03266a | 886 | kvm_msr_entry_set(&msrs[n++], MSR_PAT, env->pat); |
c3a3a7d3 | 887 | if (has_msr_star) { |
b9bec74b JK |
888 | kvm_msr_entry_set(&msrs[n++], MSR_STAR, env->star); |
889 | } | |
c3a3a7d3 | 890 | if (has_msr_hsave_pa) { |
75b10c43 | 891 | kvm_msr_entry_set(&msrs[n++], MSR_VM_HSAVE_PA, env->vm_hsave); |
b9bec74b | 892 | } |
05330448 | 893 | #ifdef TARGET_X86_64 |
25d2e361 MT |
894 | if (lm_capable_kernel) { |
895 | kvm_msr_entry_set(&msrs[n++], MSR_CSTAR, env->cstar); | |
896 | kvm_msr_entry_set(&msrs[n++], MSR_KERNELGSBASE, env->kernelgsbase); | |
897 | kvm_msr_entry_set(&msrs[n++], MSR_FMASK, env->fmask); | |
898 | kvm_msr_entry_set(&msrs[n++], MSR_LSTAR, env->lstar); | |
899 | } | |
05330448 | 900 | #endif |
ea643051 | 901 | if (level == KVM_PUT_FULL_STATE) { |
384331a6 MT |
902 | /* |
903 | * KVM is yet unable to synchronize TSC values of multiple VCPUs on | |
904 | * writeback. Until this is fixed, we only write the offset to SMP | |
905 | * guests after migration, desynchronizing the VCPUs, but avoiding | |
906 | * huge jump-backs that would occur without any writeback at all. | |
907 | */ | |
908 | if (smp_cpus == 1 || env->tsc != 0) { | |
909 | kvm_msr_entry_set(&msrs[n++], MSR_IA32_TSC, env->tsc); | |
910 | } | |
ff5c186b JK |
911 | } |
912 | /* | |
913 | * The following paravirtual MSRs have side effects on the guest or are | |
914 | * too heavy for normal writeback. Limit them to reset or full state | |
915 | * updates. | |
916 | */ | |
917 | if (level >= KVM_PUT_RESET_STATE) { | |
ea643051 JK |
918 | kvm_msr_entry_set(&msrs[n++], MSR_KVM_SYSTEM_TIME, |
919 | env->system_time_msr); | |
920 | kvm_msr_entry_set(&msrs[n++], MSR_KVM_WALL_CLOCK, env->wall_clock_msr); | |
c5999bfc JK |
921 | if (has_msr_async_pf_en) { |
922 | kvm_msr_entry_set(&msrs[n++], MSR_KVM_ASYNC_PF_EN, | |
923 | env->async_pf_en_msr); | |
924 | } | |
ea643051 | 925 | } |
57780495 MT |
926 | #ifdef KVM_CAP_MCE |
927 | if (env->mcg_cap) { | |
d8da8574 | 928 | int i; |
b9bec74b | 929 | |
c34d440a JK |
930 | kvm_msr_entry_set(&msrs[n++], MSR_MCG_STATUS, env->mcg_status); |
931 | kvm_msr_entry_set(&msrs[n++], MSR_MCG_CTL, env->mcg_ctl); | |
932 | for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) { | |
933 | kvm_msr_entry_set(&msrs[n++], MSR_MC0_CTL + i, env->mce_banks[i]); | |
57780495 MT |
934 | } |
935 | } | |
936 | #endif | |
1a03675d | 937 | |
05330448 AL |
938 | msr_data.info.nmsrs = n; |
939 | ||
940 | return kvm_vcpu_ioctl(env, KVM_SET_MSRS, &msr_data); | |
941 | ||
942 | } | |
943 | ||
944 | ||
945 | static int kvm_get_fpu(CPUState *env) | |
946 | { | |
947 | struct kvm_fpu fpu; | |
948 | int i, ret; | |
949 | ||
950 | ret = kvm_vcpu_ioctl(env, KVM_GET_FPU, &fpu); | |
b9bec74b | 951 | if (ret < 0) { |
05330448 | 952 | return ret; |
b9bec74b | 953 | } |
05330448 AL |
954 | |
955 | env->fpstt = (fpu.fsw >> 11) & 7; | |
956 | env->fpus = fpu.fsw; | |
957 | env->fpuc = fpu.fcw; | |
42cc8fa6 JK |
958 | env->fpop = fpu.last_opcode; |
959 | env->fpip = fpu.last_ip; | |
960 | env->fpdp = fpu.last_dp; | |
b9bec74b JK |
961 | for (i = 0; i < 8; ++i) { |
962 | env->fptags[i] = !((fpu.ftwx >> i) & 1); | |
963 | } | |
05330448 AL |
964 | memcpy(env->fpregs, fpu.fpr, sizeof env->fpregs); |
965 | memcpy(env->xmm_regs, fpu.xmm, sizeof env->xmm_regs); | |
966 | env->mxcsr = fpu.mxcsr; | |
967 | ||
968 | return 0; | |
969 | } | |
970 | ||
f1665b21 SY |
971 | static int kvm_get_xsave(CPUState *env) |
972 | { | |
973 | #ifdef KVM_CAP_XSAVE | |
974 | struct kvm_xsave* xsave; | |
975 | int ret, i; | |
42cc8fa6 | 976 | uint16_t cwd, swd, twd; |
f1665b21 | 977 | |
b9bec74b | 978 | if (!kvm_has_xsave()) { |
f1665b21 | 979 | return kvm_get_fpu(env); |
b9bec74b | 980 | } |
f1665b21 SY |
981 | |
982 | xsave = qemu_memalign(4096, sizeof(struct kvm_xsave)); | |
983 | ret = kvm_vcpu_ioctl(env, KVM_GET_XSAVE, xsave); | |
0f53994f MT |
984 | if (ret < 0) { |
985 | qemu_free(xsave); | |
f1665b21 | 986 | return ret; |
0f53994f | 987 | } |
f1665b21 SY |
988 | |
989 | cwd = (uint16_t)xsave->region[0]; | |
990 | swd = (uint16_t)(xsave->region[0] >> 16); | |
991 | twd = (uint16_t)xsave->region[1]; | |
42cc8fa6 | 992 | env->fpop = (uint16_t)(xsave->region[1] >> 16); |
f1665b21 SY |
993 | env->fpstt = (swd >> 11) & 7; |
994 | env->fpus = swd; | |
995 | env->fpuc = cwd; | |
b9bec74b | 996 | for (i = 0; i < 8; ++i) { |
f1665b21 | 997 | env->fptags[i] = !((twd >> i) & 1); |
b9bec74b | 998 | } |
42cc8fa6 JK |
999 | memcpy(&env->fpip, &xsave->region[XSAVE_CWD_RIP], sizeof(env->fpip)); |
1000 | memcpy(&env->fpdp, &xsave->region[XSAVE_CWD_RDP], sizeof(env->fpdp)); | |
f1665b21 SY |
1001 | env->mxcsr = xsave->region[XSAVE_MXCSR]; |
1002 | memcpy(env->fpregs, &xsave->region[XSAVE_ST_SPACE], | |
1003 | sizeof env->fpregs); | |
1004 | memcpy(env->xmm_regs, &xsave->region[XSAVE_XMM_SPACE], | |
1005 | sizeof env->xmm_regs); | |
1006 | env->xstate_bv = *(uint64_t *)&xsave->region[XSAVE_XSTATE_BV]; | |
1007 | memcpy(env->ymmh_regs, &xsave->region[XSAVE_YMMH_SPACE], | |
1008 | sizeof env->ymmh_regs); | |
0f53994f | 1009 | qemu_free(xsave); |
f1665b21 SY |
1010 | return 0; |
1011 | #else | |
1012 | return kvm_get_fpu(env); | |
1013 | #endif | |
1014 | } | |
1015 | ||
1016 | static int kvm_get_xcrs(CPUState *env) | |
1017 | { | |
1018 | #ifdef KVM_CAP_XCRS | |
1019 | int i, ret; | |
1020 | struct kvm_xcrs xcrs; | |
1021 | ||
b9bec74b | 1022 | if (!kvm_has_xcrs()) { |
f1665b21 | 1023 | return 0; |
b9bec74b | 1024 | } |
f1665b21 SY |
1025 | |
1026 | ret = kvm_vcpu_ioctl(env, KVM_GET_XCRS, &xcrs); | |
b9bec74b | 1027 | if (ret < 0) { |
f1665b21 | 1028 | return ret; |
b9bec74b | 1029 | } |
f1665b21 | 1030 | |
b9bec74b | 1031 | for (i = 0; i < xcrs.nr_xcrs; i++) { |
f1665b21 SY |
1032 | /* Only support xcr0 now */ |
1033 | if (xcrs.xcrs[0].xcr == 0) { | |
1034 | env->xcr0 = xcrs.xcrs[0].value; | |
1035 | break; | |
1036 | } | |
b9bec74b | 1037 | } |
f1665b21 SY |
1038 | return 0; |
1039 | #else | |
1040 | return 0; | |
1041 | #endif | |
1042 | } | |
1043 | ||
05330448 AL |
1044 | static int kvm_get_sregs(CPUState *env) |
1045 | { | |
1046 | struct kvm_sregs sregs; | |
1047 | uint32_t hflags; | |
0e607a80 | 1048 | int bit, i, ret; |
05330448 AL |
1049 | |
1050 | ret = kvm_vcpu_ioctl(env, KVM_GET_SREGS, &sregs); | |
b9bec74b | 1051 | if (ret < 0) { |
05330448 | 1052 | return ret; |
b9bec74b | 1053 | } |
05330448 | 1054 | |
0e607a80 JK |
1055 | /* There can only be one pending IRQ set in the bitmap at a time, so try |
1056 | to find it and save its number instead (-1 for none). */ | |
1057 | env->interrupt_injected = -1; | |
1058 | for (i = 0; i < ARRAY_SIZE(sregs.interrupt_bitmap); i++) { | |
1059 | if (sregs.interrupt_bitmap[i]) { | |
1060 | bit = ctz64(sregs.interrupt_bitmap[i]); | |
1061 | env->interrupt_injected = i * 64 + bit; | |
1062 | break; | |
1063 | } | |
1064 | } | |
05330448 AL |
1065 | |
1066 | get_seg(&env->segs[R_CS], &sregs.cs); | |
1067 | get_seg(&env->segs[R_DS], &sregs.ds); | |
1068 | get_seg(&env->segs[R_ES], &sregs.es); | |
1069 | get_seg(&env->segs[R_FS], &sregs.fs); | |
1070 | get_seg(&env->segs[R_GS], &sregs.gs); | |
1071 | get_seg(&env->segs[R_SS], &sregs.ss); | |
1072 | ||
1073 | get_seg(&env->tr, &sregs.tr); | |
1074 | get_seg(&env->ldt, &sregs.ldt); | |
1075 | ||
1076 | env->idt.limit = sregs.idt.limit; | |
1077 | env->idt.base = sregs.idt.base; | |
1078 | env->gdt.limit = sregs.gdt.limit; | |
1079 | env->gdt.base = sregs.gdt.base; | |
1080 | ||
1081 | env->cr[0] = sregs.cr0; | |
1082 | env->cr[2] = sregs.cr2; | |
1083 | env->cr[3] = sregs.cr3; | |
1084 | env->cr[4] = sregs.cr4; | |
1085 | ||
4a942cea | 1086 | cpu_set_apic_base(env->apic_state, sregs.apic_base); |
05330448 AL |
1087 | |
1088 | env->efer = sregs.efer; | |
4a942cea | 1089 | //cpu_set_apic_tpr(env->apic_state, sregs.cr8); |
05330448 | 1090 | |
b9bec74b JK |
1091 | #define HFLAG_COPY_MASK \ |
1092 | ~( HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \ | |
1093 | HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \ | |
1094 | HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \ | |
1095 | HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK) | |
05330448 AL |
1096 | |
1097 | hflags = (env->segs[R_CS].flags >> DESC_DPL_SHIFT) & HF_CPL_MASK; | |
1098 | hflags |= (env->cr[0] & CR0_PE_MASK) << (HF_PE_SHIFT - CR0_PE_SHIFT); | |
1099 | hflags |= (env->cr[0] << (HF_MP_SHIFT - CR0_MP_SHIFT)) & | |
b9bec74b | 1100 | (HF_MP_MASK | HF_EM_MASK | HF_TS_MASK); |
05330448 AL |
1101 | hflags |= (env->eflags & (HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK)); |
1102 | hflags |= (env->cr[4] & CR4_OSFXSR_MASK) << | |
b9bec74b | 1103 | (HF_OSFXSR_SHIFT - CR4_OSFXSR_SHIFT); |
05330448 AL |
1104 | |
1105 | if (env->efer & MSR_EFER_LMA) { | |
1106 | hflags |= HF_LMA_MASK; | |
1107 | } | |
1108 | ||
1109 | if ((hflags & HF_LMA_MASK) && (env->segs[R_CS].flags & DESC_L_MASK)) { | |
1110 | hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK; | |
1111 | } else { | |
1112 | hflags |= (env->segs[R_CS].flags & DESC_B_MASK) >> | |
b9bec74b | 1113 | (DESC_B_SHIFT - HF_CS32_SHIFT); |
05330448 | 1114 | hflags |= (env->segs[R_SS].flags & DESC_B_MASK) >> |
b9bec74b JK |
1115 | (DESC_B_SHIFT - HF_SS32_SHIFT); |
1116 | if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK) || | |
1117 | !(hflags & HF_CS32_MASK)) { | |
1118 | hflags |= HF_ADDSEG_MASK; | |
1119 | } else { | |
1120 | hflags |= ((env->segs[R_DS].base | env->segs[R_ES].base | | |
1121 | env->segs[R_SS].base) != 0) << HF_ADDSEG_SHIFT; | |
1122 | } | |
05330448 AL |
1123 | } |
1124 | env->hflags = (env->hflags & HFLAG_COPY_MASK) | hflags; | |
05330448 AL |
1125 | |
1126 | return 0; | |
1127 | } | |
1128 | ||
1129 | static int kvm_get_msrs(CPUState *env) | |
1130 | { | |
1131 | struct { | |
1132 | struct kvm_msrs info; | |
1133 | struct kvm_msr_entry entries[100]; | |
1134 | } msr_data; | |
1135 | struct kvm_msr_entry *msrs = msr_data.entries; | |
1136 | int ret, i, n; | |
1137 | ||
1138 | n = 0; | |
1139 | msrs[n++].index = MSR_IA32_SYSENTER_CS; | |
1140 | msrs[n++].index = MSR_IA32_SYSENTER_ESP; | |
1141 | msrs[n++].index = MSR_IA32_SYSENTER_EIP; | |
0c03266a | 1142 | msrs[n++].index = MSR_PAT; |
c3a3a7d3 | 1143 | if (has_msr_star) { |
b9bec74b JK |
1144 | msrs[n++].index = MSR_STAR; |
1145 | } | |
c3a3a7d3 | 1146 | if (has_msr_hsave_pa) { |
75b10c43 | 1147 | msrs[n++].index = MSR_VM_HSAVE_PA; |
b9bec74b | 1148 | } |
b8cc45d6 GC |
1149 | |
1150 | if (!env->tsc_valid) { | |
1151 | msrs[n++].index = MSR_IA32_TSC; | |
1152 | env->tsc_valid = !vm_running; | |
1153 | } | |
1154 | ||
05330448 | 1155 | #ifdef TARGET_X86_64 |
25d2e361 MT |
1156 | if (lm_capable_kernel) { |
1157 | msrs[n++].index = MSR_CSTAR; | |
1158 | msrs[n++].index = MSR_KERNELGSBASE; | |
1159 | msrs[n++].index = MSR_FMASK; | |
1160 | msrs[n++].index = MSR_LSTAR; | |
1161 | } | |
05330448 | 1162 | #endif |
1a03675d GC |
1163 | msrs[n++].index = MSR_KVM_SYSTEM_TIME; |
1164 | msrs[n++].index = MSR_KVM_WALL_CLOCK; | |
c5999bfc JK |
1165 | if (has_msr_async_pf_en) { |
1166 | msrs[n++].index = MSR_KVM_ASYNC_PF_EN; | |
1167 | } | |
1a03675d | 1168 | |
57780495 MT |
1169 | #ifdef KVM_CAP_MCE |
1170 | if (env->mcg_cap) { | |
1171 | msrs[n++].index = MSR_MCG_STATUS; | |
1172 | msrs[n++].index = MSR_MCG_CTL; | |
b9bec74b | 1173 | for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) { |
57780495 | 1174 | msrs[n++].index = MSR_MC0_CTL + i; |
b9bec74b | 1175 | } |
57780495 MT |
1176 | } |
1177 | #endif | |
1178 | ||
05330448 AL |
1179 | msr_data.info.nmsrs = n; |
1180 | ret = kvm_vcpu_ioctl(env, KVM_GET_MSRS, &msr_data); | |
b9bec74b | 1181 | if (ret < 0) { |
05330448 | 1182 | return ret; |
b9bec74b | 1183 | } |
05330448 AL |
1184 | |
1185 | for (i = 0; i < ret; i++) { | |
1186 | switch (msrs[i].index) { | |
1187 | case MSR_IA32_SYSENTER_CS: | |
1188 | env->sysenter_cs = msrs[i].data; | |
1189 | break; | |
1190 | case MSR_IA32_SYSENTER_ESP: | |
1191 | env->sysenter_esp = msrs[i].data; | |
1192 | break; | |
1193 | case MSR_IA32_SYSENTER_EIP: | |
1194 | env->sysenter_eip = msrs[i].data; | |
1195 | break; | |
0c03266a JK |
1196 | case MSR_PAT: |
1197 | env->pat = msrs[i].data; | |
1198 | break; | |
05330448 AL |
1199 | case MSR_STAR: |
1200 | env->star = msrs[i].data; | |
1201 | break; | |
1202 | #ifdef TARGET_X86_64 | |
1203 | case MSR_CSTAR: | |
1204 | env->cstar = msrs[i].data; | |
1205 | break; | |
1206 | case MSR_KERNELGSBASE: | |
1207 | env->kernelgsbase = msrs[i].data; | |
1208 | break; | |
1209 | case MSR_FMASK: | |
1210 | env->fmask = msrs[i].data; | |
1211 | break; | |
1212 | case MSR_LSTAR: | |
1213 | env->lstar = msrs[i].data; | |
1214 | break; | |
1215 | #endif | |
1216 | case MSR_IA32_TSC: | |
1217 | env->tsc = msrs[i].data; | |
1218 | break; | |
aa851e36 MT |
1219 | case MSR_VM_HSAVE_PA: |
1220 | env->vm_hsave = msrs[i].data; | |
1221 | break; | |
1a03675d GC |
1222 | case MSR_KVM_SYSTEM_TIME: |
1223 | env->system_time_msr = msrs[i].data; | |
1224 | break; | |
1225 | case MSR_KVM_WALL_CLOCK: | |
1226 | env->wall_clock_msr = msrs[i].data; | |
1227 | break; | |
57780495 MT |
1228 | #ifdef KVM_CAP_MCE |
1229 | case MSR_MCG_STATUS: | |
1230 | env->mcg_status = msrs[i].data; | |
1231 | break; | |
1232 | case MSR_MCG_CTL: | |
1233 | env->mcg_ctl = msrs[i].data; | |
1234 | break; | |
1235 | #endif | |
1236 | default: | |
1237 | #ifdef KVM_CAP_MCE | |
1238 | if (msrs[i].index >= MSR_MC0_CTL && | |
1239 | msrs[i].index < MSR_MC0_CTL + (env->mcg_cap & 0xff) * 4) { | |
1240 | env->mce_banks[msrs[i].index - MSR_MC0_CTL] = msrs[i].data; | |
57780495 MT |
1241 | } |
1242 | #endif | |
d8da8574 | 1243 | break; |
f6584ee2 GN |
1244 | case MSR_KVM_ASYNC_PF_EN: |
1245 | env->async_pf_en_msr = msrs[i].data; | |
1246 | break; | |
05330448 AL |
1247 | } |
1248 | } | |
1249 | ||
1250 | return 0; | |
1251 | } | |
1252 | ||
9bdbe550 HB |
1253 | static int kvm_put_mp_state(CPUState *env) |
1254 | { | |
1255 | struct kvm_mp_state mp_state = { .mp_state = env->mp_state }; | |
1256 | ||
1257 | return kvm_vcpu_ioctl(env, KVM_SET_MP_STATE, &mp_state); | |
1258 | } | |
1259 | ||
1260 | static int kvm_get_mp_state(CPUState *env) | |
1261 | { | |
1262 | struct kvm_mp_state mp_state; | |
1263 | int ret; | |
1264 | ||
1265 | ret = kvm_vcpu_ioctl(env, KVM_GET_MP_STATE, &mp_state); | |
1266 | if (ret < 0) { | |
1267 | return ret; | |
1268 | } | |
1269 | env->mp_state = mp_state.mp_state; | |
c14750e8 JK |
1270 | if (kvm_irqchip_in_kernel()) { |
1271 | env->halted = (mp_state.mp_state == KVM_MP_STATE_HALTED); | |
1272 | } | |
9bdbe550 HB |
1273 | return 0; |
1274 | } | |
1275 | ||
ea643051 | 1276 | static int kvm_put_vcpu_events(CPUState *env, int level) |
a0fb002c JK |
1277 | { |
1278 | #ifdef KVM_CAP_VCPU_EVENTS | |
1279 | struct kvm_vcpu_events events; | |
1280 | ||
1281 | if (!kvm_has_vcpu_events()) { | |
1282 | return 0; | |
1283 | } | |
1284 | ||
31827373 JK |
1285 | events.exception.injected = (env->exception_injected >= 0); |
1286 | events.exception.nr = env->exception_injected; | |
a0fb002c JK |
1287 | events.exception.has_error_code = env->has_error_code; |
1288 | events.exception.error_code = env->error_code; | |
1289 | ||
1290 | events.interrupt.injected = (env->interrupt_injected >= 0); | |
1291 | events.interrupt.nr = env->interrupt_injected; | |
1292 | events.interrupt.soft = env->soft_interrupt; | |
1293 | ||
1294 | events.nmi.injected = env->nmi_injected; | |
1295 | events.nmi.pending = env->nmi_pending; | |
1296 | events.nmi.masked = !!(env->hflags2 & HF2_NMI_MASK); | |
1297 | ||
1298 | events.sipi_vector = env->sipi_vector; | |
1299 | ||
ea643051 JK |
1300 | events.flags = 0; |
1301 | if (level >= KVM_PUT_RESET_STATE) { | |
1302 | events.flags |= | |
1303 | KVM_VCPUEVENT_VALID_NMI_PENDING | KVM_VCPUEVENT_VALID_SIPI_VECTOR; | |
1304 | } | |
aee028b9 | 1305 | |
a0fb002c JK |
1306 | return kvm_vcpu_ioctl(env, KVM_SET_VCPU_EVENTS, &events); |
1307 | #else | |
1308 | return 0; | |
1309 | #endif | |
1310 | } | |
1311 | ||
1312 | static int kvm_get_vcpu_events(CPUState *env) | |
1313 | { | |
1314 | #ifdef KVM_CAP_VCPU_EVENTS | |
1315 | struct kvm_vcpu_events events; | |
1316 | int ret; | |
1317 | ||
1318 | if (!kvm_has_vcpu_events()) { | |
1319 | return 0; | |
1320 | } | |
1321 | ||
1322 | ret = kvm_vcpu_ioctl(env, KVM_GET_VCPU_EVENTS, &events); | |
1323 | if (ret < 0) { | |
1324 | return ret; | |
1325 | } | |
31827373 | 1326 | env->exception_injected = |
a0fb002c JK |
1327 | events.exception.injected ? events.exception.nr : -1; |
1328 | env->has_error_code = events.exception.has_error_code; | |
1329 | env->error_code = events.exception.error_code; | |
1330 | ||
1331 | env->interrupt_injected = | |
1332 | events.interrupt.injected ? events.interrupt.nr : -1; | |
1333 | env->soft_interrupt = events.interrupt.soft; | |
1334 | ||
1335 | env->nmi_injected = events.nmi.injected; | |
1336 | env->nmi_pending = events.nmi.pending; | |
1337 | if (events.nmi.masked) { | |
1338 | env->hflags2 |= HF2_NMI_MASK; | |
1339 | } else { | |
1340 | env->hflags2 &= ~HF2_NMI_MASK; | |
1341 | } | |
1342 | ||
1343 | env->sipi_vector = events.sipi_vector; | |
1344 | #endif | |
1345 | ||
1346 | return 0; | |
1347 | } | |
1348 | ||
b0b1d690 JK |
1349 | static int kvm_guest_debug_workarounds(CPUState *env) |
1350 | { | |
1351 | int ret = 0; | |
1352 | #ifdef KVM_CAP_SET_GUEST_DEBUG | |
1353 | unsigned long reinject_trap = 0; | |
1354 | ||
1355 | if (!kvm_has_vcpu_events()) { | |
1356 | if (env->exception_injected == 1) { | |
1357 | reinject_trap = KVM_GUESTDBG_INJECT_DB; | |
1358 | } else if (env->exception_injected == 3) { | |
1359 | reinject_trap = KVM_GUESTDBG_INJECT_BP; | |
1360 | } | |
1361 | env->exception_injected = -1; | |
1362 | } | |
1363 | ||
1364 | /* | |
1365 | * Kernels before KVM_CAP_X86_ROBUST_SINGLESTEP overwrote flags.TF | |
1366 | * injected via SET_GUEST_DEBUG while updating GP regs. Work around this | |
1367 | * by updating the debug state once again if single-stepping is on. | |
1368 | * Another reason to call kvm_update_guest_debug here is a pending debug | |
1369 | * trap raise by the guest. On kernels without SET_VCPU_EVENTS we have to | |
1370 | * reinject them via SET_GUEST_DEBUG. | |
1371 | */ | |
1372 | if (reinject_trap || | |
1373 | (!kvm_has_robust_singlestep() && env->singlestep_enabled)) { | |
1374 | ret = kvm_update_guest_debug(env, reinject_trap); | |
1375 | } | |
1376 | #endif /* KVM_CAP_SET_GUEST_DEBUG */ | |
1377 | return ret; | |
1378 | } | |
1379 | ||
ff44f1a3 JK |
1380 | static int kvm_put_debugregs(CPUState *env) |
1381 | { | |
1382 | #ifdef KVM_CAP_DEBUGREGS | |
1383 | struct kvm_debugregs dbgregs; | |
1384 | int i; | |
1385 | ||
1386 | if (!kvm_has_debugregs()) { | |
1387 | return 0; | |
1388 | } | |
1389 | ||
1390 | for (i = 0; i < 4; i++) { | |
1391 | dbgregs.db[i] = env->dr[i]; | |
1392 | } | |
1393 | dbgregs.dr6 = env->dr[6]; | |
1394 | dbgregs.dr7 = env->dr[7]; | |
1395 | dbgregs.flags = 0; | |
1396 | ||
1397 | return kvm_vcpu_ioctl(env, KVM_SET_DEBUGREGS, &dbgregs); | |
1398 | #else | |
1399 | return 0; | |
1400 | #endif | |
1401 | } | |
1402 | ||
1403 | static int kvm_get_debugregs(CPUState *env) | |
1404 | { | |
1405 | #ifdef KVM_CAP_DEBUGREGS | |
1406 | struct kvm_debugregs dbgregs; | |
1407 | int i, ret; | |
1408 | ||
1409 | if (!kvm_has_debugregs()) { | |
1410 | return 0; | |
1411 | } | |
1412 | ||
1413 | ret = kvm_vcpu_ioctl(env, KVM_GET_DEBUGREGS, &dbgregs); | |
1414 | if (ret < 0) { | |
b9bec74b | 1415 | return ret; |
ff44f1a3 JK |
1416 | } |
1417 | for (i = 0; i < 4; i++) { | |
1418 | env->dr[i] = dbgregs.db[i]; | |
1419 | } | |
1420 | env->dr[4] = env->dr[6] = dbgregs.dr6; | |
1421 | env->dr[5] = env->dr[7] = dbgregs.dr7; | |
1422 | #endif | |
1423 | ||
1424 | return 0; | |
1425 | } | |
1426 | ||
ea375f9a | 1427 | int kvm_arch_put_registers(CPUState *env, int level) |
05330448 AL |
1428 | { |
1429 | int ret; | |
1430 | ||
b7680cb6 | 1431 | assert(cpu_is_stopped(env) || qemu_cpu_is_self(env)); |
dbaa07c4 | 1432 | |
05330448 | 1433 | ret = kvm_getput_regs(env, 1); |
b9bec74b | 1434 | if (ret < 0) { |
05330448 | 1435 | return ret; |
b9bec74b | 1436 | } |
f1665b21 | 1437 | ret = kvm_put_xsave(env); |
b9bec74b | 1438 | if (ret < 0) { |
f1665b21 | 1439 | return ret; |
b9bec74b | 1440 | } |
f1665b21 | 1441 | ret = kvm_put_xcrs(env); |
b9bec74b | 1442 | if (ret < 0) { |
05330448 | 1443 | return ret; |
b9bec74b | 1444 | } |
05330448 | 1445 | ret = kvm_put_sregs(env); |
b9bec74b | 1446 | if (ret < 0) { |
05330448 | 1447 | return ret; |
b9bec74b | 1448 | } |
ab443475 JK |
1449 | /* must be before kvm_put_msrs */ |
1450 | ret = kvm_inject_mce_oldstyle(env); | |
1451 | if (ret < 0) { | |
1452 | return ret; | |
1453 | } | |
ea643051 | 1454 | ret = kvm_put_msrs(env, level); |
b9bec74b | 1455 | if (ret < 0) { |
05330448 | 1456 | return ret; |
b9bec74b | 1457 | } |
ea643051 JK |
1458 | if (level >= KVM_PUT_RESET_STATE) { |
1459 | ret = kvm_put_mp_state(env); | |
b9bec74b | 1460 | if (ret < 0) { |
ea643051 | 1461 | return ret; |
b9bec74b | 1462 | } |
ea643051 | 1463 | } |
ea643051 | 1464 | ret = kvm_put_vcpu_events(env, level); |
b9bec74b | 1465 | if (ret < 0) { |
a0fb002c | 1466 | return ret; |
b9bec74b | 1467 | } |
0d75a9ec | 1468 | ret = kvm_put_debugregs(env); |
b9bec74b | 1469 | if (ret < 0) { |
b0b1d690 | 1470 | return ret; |
b9bec74b | 1471 | } |
b0b1d690 JK |
1472 | /* must be last */ |
1473 | ret = kvm_guest_debug_workarounds(env); | |
b9bec74b | 1474 | if (ret < 0) { |
ff44f1a3 | 1475 | return ret; |
b9bec74b | 1476 | } |
05330448 AL |
1477 | return 0; |
1478 | } | |
1479 | ||
1480 | int kvm_arch_get_registers(CPUState *env) | |
1481 | { | |
1482 | int ret; | |
1483 | ||
b7680cb6 | 1484 | assert(cpu_is_stopped(env) || qemu_cpu_is_self(env)); |
dbaa07c4 | 1485 | |
05330448 | 1486 | ret = kvm_getput_regs(env, 0); |
b9bec74b | 1487 | if (ret < 0) { |
05330448 | 1488 | return ret; |
b9bec74b | 1489 | } |
f1665b21 | 1490 | ret = kvm_get_xsave(env); |
b9bec74b | 1491 | if (ret < 0) { |
f1665b21 | 1492 | return ret; |
b9bec74b | 1493 | } |
f1665b21 | 1494 | ret = kvm_get_xcrs(env); |
b9bec74b | 1495 | if (ret < 0) { |
05330448 | 1496 | return ret; |
b9bec74b | 1497 | } |
05330448 | 1498 | ret = kvm_get_sregs(env); |
b9bec74b | 1499 | if (ret < 0) { |
05330448 | 1500 | return ret; |
b9bec74b | 1501 | } |
05330448 | 1502 | ret = kvm_get_msrs(env); |
b9bec74b | 1503 | if (ret < 0) { |
05330448 | 1504 | return ret; |
b9bec74b | 1505 | } |
5a2e3c2e | 1506 | ret = kvm_get_mp_state(env); |
b9bec74b | 1507 | if (ret < 0) { |
5a2e3c2e | 1508 | return ret; |
b9bec74b | 1509 | } |
a0fb002c | 1510 | ret = kvm_get_vcpu_events(env); |
b9bec74b | 1511 | if (ret < 0) { |
a0fb002c | 1512 | return ret; |
b9bec74b | 1513 | } |
ff44f1a3 | 1514 | ret = kvm_get_debugregs(env); |
b9bec74b | 1515 | if (ret < 0) { |
ff44f1a3 | 1516 | return ret; |
b9bec74b | 1517 | } |
05330448 AL |
1518 | return 0; |
1519 | } | |
1520 | ||
7a39fe58 | 1521 | void kvm_arch_pre_run(CPUState *env, struct kvm_run *run) |
05330448 | 1522 | { |
ce377af3 JK |
1523 | int ret; |
1524 | ||
276ce815 LJ |
1525 | /* Inject NMI */ |
1526 | if (env->interrupt_request & CPU_INTERRUPT_NMI) { | |
1527 | env->interrupt_request &= ~CPU_INTERRUPT_NMI; | |
1528 | DPRINTF("injected NMI\n"); | |
ce377af3 JK |
1529 | ret = kvm_vcpu_ioctl(env, KVM_NMI); |
1530 | if (ret < 0) { | |
1531 | fprintf(stderr, "KVM: injection failed, NMI lost (%s)\n", | |
1532 | strerror(-ret)); | |
1533 | } | |
276ce815 LJ |
1534 | } |
1535 | ||
db1669bc JK |
1536 | if (!kvm_irqchip_in_kernel()) { |
1537 | /* Force the VCPU out of its inner loop to process the INIT request */ | |
1538 | if (env->interrupt_request & CPU_INTERRUPT_INIT) { | |
1539 | env->exit_request = 1; | |
05330448 | 1540 | } |
05330448 | 1541 | |
db1669bc JK |
1542 | /* Try to inject an interrupt if the guest can accept it */ |
1543 | if (run->ready_for_interrupt_injection && | |
1544 | (env->interrupt_request & CPU_INTERRUPT_HARD) && | |
1545 | (env->eflags & IF_MASK)) { | |
1546 | int irq; | |
1547 | ||
1548 | env->interrupt_request &= ~CPU_INTERRUPT_HARD; | |
1549 | irq = cpu_get_pic_interrupt(env); | |
1550 | if (irq >= 0) { | |
1551 | struct kvm_interrupt intr; | |
1552 | ||
1553 | intr.irq = irq; | |
db1669bc | 1554 | DPRINTF("injected interrupt %d\n", irq); |
ce377af3 JK |
1555 | ret = kvm_vcpu_ioctl(env, KVM_INTERRUPT, &intr); |
1556 | if (ret < 0) { | |
1557 | fprintf(stderr, | |
1558 | "KVM: injection failed, interrupt lost (%s)\n", | |
1559 | strerror(-ret)); | |
1560 | } | |
db1669bc JK |
1561 | } |
1562 | } | |
05330448 | 1563 | |
db1669bc JK |
1564 | /* If we have an interrupt but the guest is not ready to receive an |
1565 | * interrupt, request an interrupt window exit. This will | |
1566 | * cause a return to userspace as soon as the guest is ready to | |
1567 | * receive interrupts. */ | |
1568 | if ((env->interrupt_request & CPU_INTERRUPT_HARD)) { | |
1569 | run->request_interrupt_window = 1; | |
1570 | } else { | |
1571 | run->request_interrupt_window = 0; | |
1572 | } | |
1573 | ||
1574 | DPRINTF("setting tpr\n"); | |
1575 | run->cr8 = cpu_get_apic_tpr(env->apic_state); | |
1576 | } | |
05330448 AL |
1577 | } |
1578 | ||
7a39fe58 | 1579 | void kvm_arch_post_run(CPUState *env, struct kvm_run *run) |
05330448 | 1580 | { |
b9bec74b | 1581 | if (run->if_flag) { |
05330448 | 1582 | env->eflags |= IF_MASK; |
b9bec74b | 1583 | } else { |
05330448 | 1584 | env->eflags &= ~IF_MASK; |
b9bec74b | 1585 | } |
4a942cea BS |
1586 | cpu_set_apic_tpr(env->apic_state, run->cr8); |
1587 | cpu_set_apic_base(env->apic_state, run->apic_base); | |
05330448 AL |
1588 | } |
1589 | ||
99036865 | 1590 | int kvm_arch_process_async_events(CPUState *env) |
0af691d7 | 1591 | { |
ab443475 JK |
1592 | if (env->interrupt_request & CPU_INTERRUPT_MCE) { |
1593 | /* We must not raise CPU_INTERRUPT_MCE if it's not supported. */ | |
1594 | assert(env->mcg_cap); | |
1595 | ||
1596 | env->interrupt_request &= ~CPU_INTERRUPT_MCE; | |
1597 | ||
1598 | kvm_cpu_synchronize_state(env); | |
1599 | ||
1600 | if (env->exception_injected == EXCP08_DBLE) { | |
1601 | /* this means triple fault */ | |
1602 | qemu_system_reset_request(); | |
1603 | env->exit_request = 1; | |
1604 | return 0; | |
1605 | } | |
1606 | env->exception_injected = EXCP12_MCHK; | |
1607 | env->has_error_code = 0; | |
1608 | ||
1609 | env->halted = 0; | |
1610 | if (kvm_irqchip_in_kernel() && env->mp_state == KVM_MP_STATE_HALTED) { | |
1611 | env->mp_state = KVM_MP_STATE_RUNNABLE; | |
1612 | } | |
1613 | } | |
1614 | ||
db1669bc JK |
1615 | if (kvm_irqchip_in_kernel()) { |
1616 | return 0; | |
1617 | } | |
1618 | ||
4601f7b0 JK |
1619 | if (((env->interrupt_request & CPU_INTERRUPT_HARD) && |
1620 | (env->eflags & IF_MASK)) || | |
1621 | (env->interrupt_request & CPU_INTERRUPT_NMI)) { | |
6792a57b JK |
1622 | env->halted = 0; |
1623 | } | |
0af691d7 MT |
1624 | if (env->interrupt_request & CPU_INTERRUPT_INIT) { |
1625 | kvm_cpu_synchronize_state(env); | |
1626 | do_cpu_init(env); | |
0af691d7 | 1627 | } |
0af691d7 MT |
1628 | if (env->interrupt_request & CPU_INTERRUPT_SIPI) { |
1629 | kvm_cpu_synchronize_state(env); | |
1630 | do_cpu_sipi(env); | |
1631 | } | |
1632 | ||
1633 | return env->halted; | |
1634 | } | |
1635 | ||
05330448 AL |
1636 | static int kvm_handle_halt(CPUState *env) |
1637 | { | |
1638 | if (!((env->interrupt_request & CPU_INTERRUPT_HARD) && | |
1639 | (env->eflags & IF_MASK)) && | |
1640 | !(env->interrupt_request & CPU_INTERRUPT_NMI)) { | |
1641 | env->halted = 1; | |
bb4ea393 | 1642 | return EXCP_HLT; |
05330448 AL |
1643 | } |
1644 | ||
bb4ea393 | 1645 | return 0; |
05330448 AL |
1646 | } |
1647 | ||
e22a25c9 | 1648 | #ifdef KVM_CAP_SET_GUEST_DEBUG |
e22a25c9 AL |
1649 | int kvm_arch_insert_sw_breakpoint(CPUState *env, struct kvm_sw_breakpoint *bp) |
1650 | { | |
38972938 | 1651 | static const uint8_t int3 = 0xcc; |
64bf3f4e | 1652 | |
e22a25c9 | 1653 | if (cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&bp->saved_insn, 1, 0) || |
b9bec74b | 1654 | cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&int3, 1, 1)) { |
e22a25c9 | 1655 | return -EINVAL; |
b9bec74b | 1656 | } |
e22a25c9 AL |
1657 | return 0; |
1658 | } | |
1659 | ||
1660 | int kvm_arch_remove_sw_breakpoint(CPUState *env, struct kvm_sw_breakpoint *bp) | |
1661 | { | |
1662 | uint8_t int3; | |
1663 | ||
1664 | if (cpu_memory_rw_debug(env, bp->pc, &int3, 1, 0) || int3 != 0xcc || | |
b9bec74b | 1665 | cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&bp->saved_insn, 1, 1)) { |
e22a25c9 | 1666 | return -EINVAL; |
b9bec74b | 1667 | } |
e22a25c9 AL |
1668 | return 0; |
1669 | } | |
1670 | ||
1671 | static struct { | |
1672 | target_ulong addr; | |
1673 | int len; | |
1674 | int type; | |
1675 | } hw_breakpoint[4]; | |
1676 | ||
1677 | static int nb_hw_breakpoint; | |
1678 | ||
1679 | static int find_hw_breakpoint(target_ulong addr, int len, int type) | |
1680 | { | |
1681 | int n; | |
1682 | ||
b9bec74b | 1683 | for (n = 0; n < nb_hw_breakpoint; n++) { |
e22a25c9 | 1684 | if (hw_breakpoint[n].addr == addr && hw_breakpoint[n].type == type && |
b9bec74b | 1685 | (hw_breakpoint[n].len == len || len == -1)) { |
e22a25c9 | 1686 | return n; |
b9bec74b JK |
1687 | } |
1688 | } | |
e22a25c9 AL |
1689 | return -1; |
1690 | } | |
1691 | ||
1692 | int kvm_arch_insert_hw_breakpoint(target_ulong addr, | |
1693 | target_ulong len, int type) | |
1694 | { | |
1695 | switch (type) { | |
1696 | case GDB_BREAKPOINT_HW: | |
1697 | len = 1; | |
1698 | break; | |
1699 | case GDB_WATCHPOINT_WRITE: | |
1700 | case GDB_WATCHPOINT_ACCESS: | |
1701 | switch (len) { | |
1702 | case 1: | |
1703 | break; | |
1704 | case 2: | |
1705 | case 4: | |
1706 | case 8: | |
b9bec74b | 1707 | if (addr & (len - 1)) { |
e22a25c9 | 1708 | return -EINVAL; |
b9bec74b | 1709 | } |
e22a25c9 AL |
1710 | break; |
1711 | default: | |
1712 | return -EINVAL; | |
1713 | } | |
1714 | break; | |
1715 | default: | |
1716 | return -ENOSYS; | |
1717 | } | |
1718 | ||
b9bec74b | 1719 | if (nb_hw_breakpoint == 4) { |
e22a25c9 | 1720 | return -ENOBUFS; |
b9bec74b JK |
1721 | } |
1722 | if (find_hw_breakpoint(addr, len, type) >= 0) { | |
e22a25c9 | 1723 | return -EEXIST; |
b9bec74b | 1724 | } |
e22a25c9 AL |
1725 | hw_breakpoint[nb_hw_breakpoint].addr = addr; |
1726 | hw_breakpoint[nb_hw_breakpoint].len = len; | |
1727 | hw_breakpoint[nb_hw_breakpoint].type = type; | |
1728 | nb_hw_breakpoint++; | |
1729 | ||
1730 | return 0; | |
1731 | } | |
1732 | ||
1733 | int kvm_arch_remove_hw_breakpoint(target_ulong addr, | |
1734 | target_ulong len, int type) | |
1735 | { | |
1736 | int n; | |
1737 | ||
1738 | n = find_hw_breakpoint(addr, (type == GDB_BREAKPOINT_HW) ? 1 : len, type); | |
b9bec74b | 1739 | if (n < 0) { |
e22a25c9 | 1740 | return -ENOENT; |
b9bec74b | 1741 | } |
e22a25c9 AL |
1742 | nb_hw_breakpoint--; |
1743 | hw_breakpoint[n] = hw_breakpoint[nb_hw_breakpoint]; | |
1744 | ||
1745 | return 0; | |
1746 | } | |
1747 | ||
1748 | void kvm_arch_remove_all_hw_breakpoints(void) | |
1749 | { | |
1750 | nb_hw_breakpoint = 0; | |
1751 | } | |
1752 | ||
1753 | static CPUWatchpoint hw_watchpoint; | |
1754 | ||
f2574737 | 1755 | static int kvm_handle_debug(struct kvm_debug_exit_arch *arch_info) |
e22a25c9 | 1756 | { |
f2574737 | 1757 | int ret = 0; |
e22a25c9 AL |
1758 | int n; |
1759 | ||
1760 | if (arch_info->exception == 1) { | |
1761 | if (arch_info->dr6 & (1 << 14)) { | |
b9bec74b | 1762 | if (cpu_single_env->singlestep_enabled) { |
f2574737 | 1763 | ret = EXCP_DEBUG; |
b9bec74b | 1764 | } |
e22a25c9 | 1765 | } else { |
b9bec74b JK |
1766 | for (n = 0; n < 4; n++) { |
1767 | if (arch_info->dr6 & (1 << n)) { | |
e22a25c9 AL |
1768 | switch ((arch_info->dr7 >> (16 + n*4)) & 0x3) { |
1769 | case 0x0: | |
f2574737 | 1770 | ret = EXCP_DEBUG; |
e22a25c9 AL |
1771 | break; |
1772 | case 0x1: | |
f2574737 | 1773 | ret = EXCP_DEBUG; |
e22a25c9 AL |
1774 | cpu_single_env->watchpoint_hit = &hw_watchpoint; |
1775 | hw_watchpoint.vaddr = hw_breakpoint[n].addr; | |
1776 | hw_watchpoint.flags = BP_MEM_WRITE; | |
1777 | break; | |
1778 | case 0x3: | |
f2574737 | 1779 | ret = EXCP_DEBUG; |
e22a25c9 AL |
1780 | cpu_single_env->watchpoint_hit = &hw_watchpoint; |
1781 | hw_watchpoint.vaddr = hw_breakpoint[n].addr; | |
1782 | hw_watchpoint.flags = BP_MEM_ACCESS; | |
1783 | break; | |
1784 | } | |
b9bec74b JK |
1785 | } |
1786 | } | |
e22a25c9 | 1787 | } |
b9bec74b | 1788 | } else if (kvm_find_sw_breakpoint(cpu_single_env, arch_info->pc)) { |
f2574737 | 1789 | ret = EXCP_DEBUG; |
b9bec74b | 1790 | } |
f2574737 | 1791 | if (ret == 0) { |
b0b1d690 JK |
1792 | cpu_synchronize_state(cpu_single_env); |
1793 | assert(cpu_single_env->exception_injected == -1); | |
1794 | ||
f2574737 | 1795 | /* pass to guest */ |
b0b1d690 JK |
1796 | cpu_single_env->exception_injected = arch_info->exception; |
1797 | cpu_single_env->has_error_code = 0; | |
1798 | } | |
e22a25c9 | 1799 | |
f2574737 | 1800 | return ret; |
e22a25c9 AL |
1801 | } |
1802 | ||
1803 | void kvm_arch_update_guest_debug(CPUState *env, struct kvm_guest_debug *dbg) | |
1804 | { | |
1805 | const uint8_t type_code[] = { | |
1806 | [GDB_BREAKPOINT_HW] = 0x0, | |
1807 | [GDB_WATCHPOINT_WRITE] = 0x1, | |
1808 | [GDB_WATCHPOINT_ACCESS] = 0x3 | |
1809 | }; | |
1810 | const uint8_t len_code[] = { | |
1811 | [1] = 0x0, [2] = 0x1, [4] = 0x3, [8] = 0x2 | |
1812 | }; | |
1813 | int n; | |
1814 | ||
b9bec74b | 1815 | if (kvm_sw_breakpoints_active(env)) { |
e22a25c9 | 1816 | dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP; |
b9bec74b | 1817 | } |
e22a25c9 AL |
1818 | if (nb_hw_breakpoint > 0) { |
1819 | dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP; | |
1820 | dbg->arch.debugreg[7] = 0x0600; | |
1821 | for (n = 0; n < nb_hw_breakpoint; n++) { | |
1822 | dbg->arch.debugreg[n] = hw_breakpoint[n].addr; | |
1823 | dbg->arch.debugreg[7] |= (2 << (n * 2)) | | |
1824 | (type_code[hw_breakpoint[n].type] << (16 + n*4)) | | |
95c077c9 | 1825 | ((uint32_t)len_code[hw_breakpoint[n].len] << (18 + n*4)); |
e22a25c9 AL |
1826 | } |
1827 | } | |
1828 | } | |
1829 | #endif /* KVM_CAP_SET_GUEST_DEBUG */ | |
4513d923 | 1830 | |
2a4dac83 JK |
1831 | static bool host_supports_vmx(void) |
1832 | { | |
1833 | uint32_t ecx, unused; | |
1834 | ||
1835 | host_cpuid(1, 0, &unused, &unused, &ecx, &unused); | |
1836 | return ecx & CPUID_EXT_VMX; | |
1837 | } | |
1838 | ||
1839 | #define VMX_INVALID_GUEST_STATE 0x80000021 | |
1840 | ||
1841 | int kvm_arch_handle_exit(CPUState *env, struct kvm_run *run) | |
1842 | { | |
1843 | uint64_t code; | |
1844 | int ret; | |
1845 | ||
1846 | switch (run->exit_reason) { | |
1847 | case KVM_EXIT_HLT: | |
1848 | DPRINTF("handle_hlt\n"); | |
1849 | ret = kvm_handle_halt(env); | |
1850 | break; | |
1851 | case KVM_EXIT_SET_TPR: | |
1852 | ret = 0; | |
1853 | break; | |
1854 | case KVM_EXIT_FAIL_ENTRY: | |
1855 | code = run->fail_entry.hardware_entry_failure_reason; | |
1856 | fprintf(stderr, "KVM: entry failed, hardware error 0x%" PRIx64 "\n", | |
1857 | code); | |
1858 | if (host_supports_vmx() && code == VMX_INVALID_GUEST_STATE) { | |
1859 | fprintf(stderr, | |
1860 | "\nIf you're runnning a guest on an Intel machine without " | |
1861 | "unrestricted mode\n" | |
1862 | "support, the failure can be most likely due to the guest " | |
1863 | "entering an invalid\n" | |
1864 | "state for Intel VT. For example, the guest maybe running " | |
1865 | "in big real mode\n" | |
1866 | "which is not supported on less recent Intel processors." | |
1867 | "\n\n"); | |
1868 | } | |
1869 | ret = -1; | |
1870 | break; | |
1871 | case KVM_EXIT_EXCEPTION: | |
1872 | fprintf(stderr, "KVM: exception %d exit (error code 0x%x)\n", | |
1873 | run->ex.exception, run->ex.error_code); | |
1874 | ret = -1; | |
1875 | break; | |
f2574737 JK |
1876 | #ifdef KVM_CAP_SET_GUEST_DEBUG |
1877 | case KVM_EXIT_DEBUG: | |
1878 | DPRINTF("kvm_exit_debug\n"); | |
1879 | ret = kvm_handle_debug(&run->debug.arch); | |
1880 | break; | |
1881 | #endif /* KVM_CAP_SET_GUEST_DEBUG */ | |
2a4dac83 JK |
1882 | default: |
1883 | fprintf(stderr, "KVM: unknown exit reason %d\n", run->exit_reason); | |
1884 | ret = -1; | |
1885 | break; | |
1886 | } | |
1887 | ||
1888 | return ret; | |
1889 | } | |
1890 | ||
4513d923 GN |
1891 | bool kvm_arch_stop_on_emulation_error(CPUState *env) |
1892 | { | |
b9bec74b JK |
1893 | return !(env->cr[0] & CR0_PE_MASK) || |
1894 | ((env->segs[R_CS].selector & 3) != 3); | |
4513d923 | 1895 | } |