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05330448 AL |
1 | /* |
2 | * QEMU KVM support | |
3 | * | |
4 | * Copyright (C) 2006-2008 Qumranet Technologies | |
5 | * Copyright IBM, Corp. 2008 | |
6 | * | |
7 | * Authors: | |
8 | * Anthony Liguori <aliguori@us.ibm.com> | |
9 | * | |
10 | * This work is licensed under the terms of the GNU GPL, version 2 or later. | |
11 | * See the COPYING file in the top-level directory. | |
12 | * | |
13 | */ | |
14 | ||
15 | #include <sys/types.h> | |
16 | #include <sys/ioctl.h> | |
17 | #include <sys/mman.h> | |
25d2e361 | 18 | #include <sys/utsname.h> |
05330448 AL |
19 | |
20 | #include <linux/kvm.h> | |
21 | ||
22 | #include "qemu-common.h" | |
23 | #include "sysemu.h" | |
24 | #include "kvm.h" | |
25 | #include "cpu.h" | |
e22a25c9 | 26 | #include "gdbstub.h" |
0e607a80 | 27 | #include "host-utils.h" |
4c5b10b7 | 28 | #include "hw/pc.h" |
408392b3 | 29 | #include "hw/apic.h" |
35bed8ee | 30 | #include "ioport.h" |
e7701825 | 31 | #include "kvm_x86.h" |
05330448 | 32 | |
bb0300dc GN |
33 | #ifdef CONFIG_KVM_PARA |
34 | #include <linux/kvm_para.h> | |
35 | #endif | |
36 | // | |
05330448 AL |
37 | //#define DEBUG_KVM |
38 | ||
39 | #ifdef DEBUG_KVM | |
8c0d577e | 40 | #define DPRINTF(fmt, ...) \ |
05330448 AL |
41 | do { fprintf(stderr, fmt, ## __VA_ARGS__); } while (0) |
42 | #else | |
8c0d577e | 43 | #define DPRINTF(fmt, ...) \ |
05330448 AL |
44 | do { } while (0) |
45 | #endif | |
46 | ||
1a03675d GC |
47 | #define MSR_KVM_WALL_CLOCK 0x11 |
48 | #define MSR_KVM_SYSTEM_TIME 0x12 | |
49 | ||
c0532a76 MT |
50 | #ifndef BUS_MCEERR_AR |
51 | #define BUS_MCEERR_AR 4 | |
52 | #endif | |
53 | #ifndef BUS_MCEERR_AO | |
54 | #define BUS_MCEERR_AO 5 | |
55 | #endif | |
56 | ||
25d2e361 MT |
57 | static int lm_capable_kernel; |
58 | ||
b827df58 AK |
59 | #ifdef KVM_CAP_EXT_CPUID |
60 | ||
61 | static struct kvm_cpuid2 *try_get_cpuid(KVMState *s, int max) | |
62 | { | |
63 | struct kvm_cpuid2 *cpuid; | |
64 | int r, size; | |
65 | ||
66 | size = sizeof(*cpuid) + max * sizeof(*cpuid->entries); | |
67 | cpuid = (struct kvm_cpuid2 *)qemu_mallocz(size); | |
68 | cpuid->nent = max; | |
69 | r = kvm_ioctl(s, KVM_GET_SUPPORTED_CPUID, cpuid); | |
76ae317f MM |
70 | if (r == 0 && cpuid->nent >= max) { |
71 | r = -E2BIG; | |
72 | } | |
b827df58 AK |
73 | if (r < 0) { |
74 | if (r == -E2BIG) { | |
75 | qemu_free(cpuid); | |
76 | return NULL; | |
77 | } else { | |
78 | fprintf(stderr, "KVM_GET_SUPPORTED_CPUID failed: %s\n", | |
79 | strerror(-r)); | |
80 | exit(1); | |
81 | } | |
82 | } | |
83 | return cpuid; | |
84 | } | |
85 | ||
c958a8bd SY |
86 | uint32_t kvm_arch_get_supported_cpuid(CPUState *env, uint32_t function, |
87 | uint32_t index, int reg) | |
b827df58 AK |
88 | { |
89 | struct kvm_cpuid2 *cpuid; | |
90 | int i, max; | |
91 | uint32_t ret = 0; | |
92 | uint32_t cpuid_1_edx; | |
93 | ||
94 | if (!kvm_check_extension(env->kvm_state, KVM_CAP_EXT_CPUID)) { | |
95 | return -1U; | |
96 | } | |
97 | ||
98 | max = 1; | |
99 | while ((cpuid = try_get_cpuid(env->kvm_state, max)) == NULL) { | |
100 | max *= 2; | |
101 | } | |
102 | ||
103 | for (i = 0; i < cpuid->nent; ++i) { | |
c958a8bd SY |
104 | if (cpuid->entries[i].function == function && |
105 | cpuid->entries[i].index == index) { | |
b827df58 AK |
106 | switch (reg) { |
107 | case R_EAX: | |
108 | ret = cpuid->entries[i].eax; | |
109 | break; | |
110 | case R_EBX: | |
111 | ret = cpuid->entries[i].ebx; | |
112 | break; | |
113 | case R_ECX: | |
114 | ret = cpuid->entries[i].ecx; | |
115 | break; | |
116 | case R_EDX: | |
117 | ret = cpuid->entries[i].edx; | |
19ccb8ea JK |
118 | switch (function) { |
119 | case 1: | |
120 | /* KVM before 2.6.30 misreports the following features */ | |
121 | ret |= CPUID_MTRR | CPUID_PAT | CPUID_MCE | CPUID_MCA; | |
122 | break; | |
123 | case 0x80000001: | |
b827df58 AK |
124 | /* On Intel, kvm returns cpuid according to the Intel spec, |
125 | * so add missing bits according to the AMD spec: | |
126 | */ | |
c958a8bd | 127 | cpuid_1_edx = kvm_arch_get_supported_cpuid(env, 1, 0, R_EDX); |
c1667e40 | 128 | ret |= cpuid_1_edx & 0x183f7ff; |
19ccb8ea | 129 | break; |
b827df58 AK |
130 | } |
131 | break; | |
132 | } | |
133 | } | |
134 | } | |
135 | ||
136 | qemu_free(cpuid); | |
137 | ||
138 | return ret; | |
139 | } | |
140 | ||
141 | #else | |
142 | ||
c958a8bd SY |
143 | uint32_t kvm_arch_get_supported_cpuid(CPUState *env, uint32_t function, |
144 | uint32_t index, int reg) | |
b827df58 AK |
145 | { |
146 | return -1U; | |
147 | } | |
148 | ||
149 | #endif | |
150 | ||
bb0300dc GN |
151 | #ifdef CONFIG_KVM_PARA |
152 | struct kvm_para_features { | |
b9bec74b JK |
153 | int cap; |
154 | int feature; | |
bb0300dc GN |
155 | } para_features[] = { |
156 | #ifdef KVM_CAP_CLOCKSOURCE | |
b9bec74b | 157 | { KVM_CAP_CLOCKSOURCE, KVM_FEATURE_CLOCKSOURCE }, |
bb0300dc GN |
158 | #endif |
159 | #ifdef KVM_CAP_NOP_IO_DELAY | |
b9bec74b | 160 | { KVM_CAP_NOP_IO_DELAY, KVM_FEATURE_NOP_IO_DELAY }, |
bb0300dc GN |
161 | #endif |
162 | #ifdef KVM_CAP_PV_MMU | |
b9bec74b | 163 | { KVM_CAP_PV_MMU, KVM_FEATURE_MMU_OP }, |
f6584ee2 GN |
164 | #endif |
165 | #ifdef KVM_CAP_ASYNC_PF | |
b9bec74b | 166 | { KVM_CAP_ASYNC_PF, KVM_FEATURE_ASYNC_PF }, |
bb0300dc | 167 | #endif |
b9bec74b | 168 | { -1, -1 } |
bb0300dc GN |
169 | }; |
170 | ||
171 | static int get_para_features(CPUState *env) | |
172 | { | |
b9bec74b | 173 | int i, features = 0; |
bb0300dc | 174 | |
b9bec74b JK |
175 | for (i = 0; i < ARRAY_SIZE(para_features) - 1; i++) { |
176 | if (kvm_check_extension(env->kvm_state, para_features[i].cap)) { | |
177 | features |= (1 << para_features[i].feature); | |
bb0300dc | 178 | } |
b9bec74b JK |
179 | } |
180 | return features; | |
bb0300dc GN |
181 | } |
182 | #endif | |
183 | ||
e7701825 MT |
184 | #ifdef KVM_CAP_MCE |
185 | static int kvm_get_mce_cap_supported(KVMState *s, uint64_t *mce_cap, | |
186 | int *max_banks) | |
187 | { | |
188 | int r; | |
189 | ||
14a09518 | 190 | r = kvm_check_extension(s, KVM_CAP_MCE); |
e7701825 MT |
191 | if (r > 0) { |
192 | *max_banks = r; | |
193 | return kvm_ioctl(s, KVM_X86_GET_MCE_CAP_SUPPORTED, mce_cap); | |
194 | } | |
195 | return -ENOSYS; | |
196 | } | |
197 | ||
198 | static int kvm_setup_mce(CPUState *env, uint64_t *mcg_cap) | |
199 | { | |
200 | return kvm_vcpu_ioctl(env, KVM_X86_SETUP_MCE, mcg_cap); | |
201 | } | |
202 | ||
203 | static int kvm_set_mce(CPUState *env, struct kvm_x86_mce *m) | |
204 | { | |
205 | return kvm_vcpu_ioctl(env, KVM_X86_SET_MCE, m); | |
206 | } | |
207 | ||
c0532a76 MT |
208 | static int kvm_get_msr(CPUState *env, struct kvm_msr_entry *msrs, int n) |
209 | { | |
210 | struct kvm_msrs *kmsrs = qemu_malloc(sizeof *kmsrs + n * sizeof *msrs); | |
211 | int r; | |
212 | ||
213 | kmsrs->nmsrs = n; | |
214 | memcpy(kmsrs->entries, msrs, n * sizeof *msrs); | |
215 | r = kvm_vcpu_ioctl(env, KVM_GET_MSRS, kmsrs); | |
216 | memcpy(msrs, kmsrs->entries, n * sizeof *msrs); | |
217 | free(kmsrs); | |
218 | return r; | |
219 | } | |
220 | ||
221 | /* FIXME: kill this and kvm_get_msr, use env->mcg_status instead */ | |
6643e2f0 | 222 | static int kvm_mce_in_progress(CPUState *env) |
c0532a76 MT |
223 | { |
224 | struct kvm_msr_entry msr_mcg_status = { | |
225 | .index = MSR_MCG_STATUS, | |
226 | }; | |
227 | int r; | |
228 | ||
229 | r = kvm_get_msr(env, &msr_mcg_status, 1); | |
230 | if (r == -1 || r == 0) { | |
6643e2f0 JD |
231 | fprintf(stderr, "Failed to get MCE status\n"); |
232 | return 0; | |
c0532a76 MT |
233 | } |
234 | return !!(msr_mcg_status.data & MCG_STATUS_MCIP); | |
235 | } | |
236 | ||
e7701825 MT |
237 | struct kvm_x86_mce_data |
238 | { | |
239 | CPUState *env; | |
240 | struct kvm_x86_mce *mce; | |
c0532a76 | 241 | int abort_on_error; |
e7701825 MT |
242 | }; |
243 | ||
244 | static void kvm_do_inject_x86_mce(void *_data) | |
245 | { | |
246 | struct kvm_x86_mce_data *data = _data; | |
247 | int r; | |
248 | ||
f8502cfb HS |
249 | /* If there is an MCE exception being processed, ignore this SRAO MCE */ |
250 | if ((data->env->mcg_cap & MCG_SER_P) && | |
251 | !(data->mce->status & MCI_STATUS_AR)) { | |
6643e2f0 | 252 | if (kvm_mce_in_progress(data->env)) { |
f8502cfb HS |
253 | return; |
254 | } | |
255 | } | |
c0532a76 | 256 | |
e7701825 | 257 | r = kvm_set_mce(data->env, data->mce); |
c0532a76 | 258 | if (r < 0) { |
e7701825 | 259 | perror("kvm_set_mce FAILED"); |
c0532a76 MT |
260 | if (data->abort_on_error) { |
261 | abort(); | |
262 | } | |
263 | } | |
e7701825 | 264 | } |
31ce5e0c | 265 | |
7cc2cc3e JD |
266 | static void kvm_inject_x86_mce_on(CPUState *env, struct kvm_x86_mce *mce, |
267 | int flag) | |
268 | { | |
269 | struct kvm_x86_mce_data data = { | |
270 | .env = env, | |
271 | .mce = mce, | |
272 | .abort_on_error = (flag & ABORT_ON_ERROR), | |
273 | }; | |
274 | ||
275 | if (!env->mcg_cap) { | |
276 | fprintf(stderr, "MCE support is not enabled!\n"); | |
277 | return; | |
278 | } | |
279 | ||
280 | run_on_cpu(env, kvm_do_inject_x86_mce, &data); | |
281 | } | |
282 | ||
31ce5e0c | 283 | static void kvm_mce_broadcast_rest(CPUState *env); |
e7701825 MT |
284 | #endif |
285 | ||
286 | void kvm_inject_x86_mce(CPUState *cenv, int bank, uint64_t status, | |
c0532a76 | 287 | uint64_t mcg_status, uint64_t addr, uint64_t misc, |
31ce5e0c | 288 | int flag) |
e7701825 MT |
289 | { |
290 | #ifdef KVM_CAP_MCE | |
291 | struct kvm_x86_mce mce = { | |
292 | .bank = bank, | |
293 | .status = status, | |
294 | .mcg_status = mcg_status, | |
295 | .addr = addr, | |
296 | .misc = misc, | |
297 | }; | |
c0532a76 | 298 | |
31ce5e0c JD |
299 | if (flag & MCE_BROADCAST) { |
300 | kvm_mce_broadcast_rest(cenv); | |
301 | } | |
302 | ||
7cc2cc3e | 303 | kvm_inject_x86_mce_on(cenv, &mce, flag); |
c0532a76 | 304 | #else |
31ce5e0c | 305 | if (flag & ABORT_ON_ERROR) { |
c0532a76 | 306 | abort(); |
31ce5e0c | 307 | } |
e7701825 MT |
308 | #endif |
309 | } | |
310 | ||
05330448 AL |
311 | int kvm_arch_init_vcpu(CPUState *env) |
312 | { | |
313 | struct { | |
486bd5a2 AL |
314 | struct kvm_cpuid2 cpuid; |
315 | struct kvm_cpuid_entry2 entries[100]; | |
05330448 | 316 | } __attribute__((packed)) cpuid_data; |
486bd5a2 | 317 | uint32_t limit, i, j, cpuid_i; |
a33609ca | 318 | uint32_t unused; |
bb0300dc GN |
319 | struct kvm_cpuid_entry2 *c; |
320 | #ifdef KVM_CPUID_SIGNATURE | |
321 | uint32_t signature[3]; | |
322 | #endif | |
05330448 | 323 | |
f8d926e9 JK |
324 | env->mp_state = KVM_MP_STATE_RUNNABLE; |
325 | ||
c958a8bd | 326 | env->cpuid_features &= kvm_arch_get_supported_cpuid(env, 1, 0, R_EDX); |
6c0d7ee8 AP |
327 | |
328 | i = env->cpuid_ext_features & CPUID_EXT_HYPERVISOR; | |
c958a8bd | 329 | env->cpuid_ext_features &= kvm_arch_get_supported_cpuid(env, 1, 0, R_ECX); |
6c0d7ee8 AP |
330 | env->cpuid_ext_features |= i; |
331 | ||
457dfed6 | 332 | env->cpuid_ext2_features &= kvm_arch_get_supported_cpuid(env, 0x80000001, |
c958a8bd | 333 | 0, R_EDX); |
457dfed6 | 334 | env->cpuid_ext3_features &= kvm_arch_get_supported_cpuid(env, 0x80000001, |
c958a8bd | 335 | 0, R_ECX); |
296acb64 JR |
336 | env->cpuid_svm_features &= kvm_arch_get_supported_cpuid(env, 0x8000000A, |
337 | 0, R_EDX); | |
338 | ||
6c1f42fe | 339 | |
05330448 AL |
340 | cpuid_i = 0; |
341 | ||
bb0300dc GN |
342 | #ifdef CONFIG_KVM_PARA |
343 | /* Paravirtualization CPUIDs */ | |
344 | memcpy(signature, "KVMKVMKVM\0\0\0", 12); | |
345 | c = &cpuid_data.entries[cpuid_i++]; | |
346 | memset(c, 0, sizeof(*c)); | |
347 | c->function = KVM_CPUID_SIGNATURE; | |
348 | c->eax = 0; | |
349 | c->ebx = signature[0]; | |
350 | c->ecx = signature[1]; | |
351 | c->edx = signature[2]; | |
352 | ||
353 | c = &cpuid_data.entries[cpuid_i++]; | |
354 | memset(c, 0, sizeof(*c)); | |
355 | c->function = KVM_CPUID_FEATURES; | |
356 | c->eax = env->cpuid_kvm_features & get_para_features(env); | |
357 | #endif | |
358 | ||
a33609ca | 359 | cpu_x86_cpuid(env, 0, 0, &limit, &unused, &unused, &unused); |
05330448 AL |
360 | |
361 | for (i = 0; i <= limit; i++) { | |
bb0300dc | 362 | c = &cpuid_data.entries[cpuid_i++]; |
486bd5a2 AL |
363 | |
364 | switch (i) { | |
a36b1029 AL |
365 | case 2: { |
366 | /* Keep reading function 2 till all the input is received */ | |
367 | int times; | |
368 | ||
a36b1029 | 369 | c->function = i; |
a33609ca AL |
370 | c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC | |
371 | KVM_CPUID_FLAG_STATE_READ_NEXT; | |
372 | cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx); | |
373 | times = c->eax & 0xff; | |
a36b1029 AL |
374 | |
375 | for (j = 1; j < times; ++j) { | |
a33609ca | 376 | c = &cpuid_data.entries[cpuid_i++]; |
a36b1029 | 377 | c->function = i; |
a33609ca AL |
378 | c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC; |
379 | cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx); | |
a36b1029 AL |
380 | } |
381 | break; | |
382 | } | |
486bd5a2 AL |
383 | case 4: |
384 | case 0xb: | |
385 | case 0xd: | |
386 | for (j = 0; ; j++) { | |
486bd5a2 AL |
387 | c->function = i; |
388 | c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX; | |
389 | c->index = j; | |
a33609ca | 390 | cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx); |
486bd5a2 | 391 | |
b9bec74b | 392 | if (i == 4 && c->eax == 0) { |
486bd5a2 | 393 | break; |
b9bec74b JK |
394 | } |
395 | if (i == 0xb && !(c->ecx & 0xff00)) { | |
486bd5a2 | 396 | break; |
b9bec74b JK |
397 | } |
398 | if (i == 0xd && c->eax == 0) { | |
486bd5a2 | 399 | break; |
b9bec74b | 400 | } |
a33609ca | 401 | c = &cpuid_data.entries[cpuid_i++]; |
486bd5a2 AL |
402 | } |
403 | break; | |
404 | default: | |
486bd5a2 | 405 | c->function = i; |
a33609ca AL |
406 | c->flags = 0; |
407 | cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx); | |
486bd5a2 AL |
408 | break; |
409 | } | |
05330448 | 410 | } |
a33609ca | 411 | cpu_x86_cpuid(env, 0x80000000, 0, &limit, &unused, &unused, &unused); |
05330448 AL |
412 | |
413 | for (i = 0x80000000; i <= limit; i++) { | |
bb0300dc | 414 | c = &cpuid_data.entries[cpuid_i++]; |
05330448 | 415 | |
05330448 | 416 | c->function = i; |
a33609ca AL |
417 | c->flags = 0; |
418 | cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx); | |
05330448 AL |
419 | } |
420 | ||
421 | cpuid_data.cpuid.nent = cpuid_i; | |
422 | ||
e7701825 MT |
423 | #ifdef KVM_CAP_MCE |
424 | if (((env->cpuid_version >> 8)&0xF) >= 6 | |
425 | && (env->cpuid_features&(CPUID_MCE|CPUID_MCA)) == (CPUID_MCE|CPUID_MCA) | |
426 | && kvm_check_extension(env->kvm_state, KVM_CAP_MCE) > 0) { | |
427 | uint64_t mcg_cap; | |
428 | int banks; | |
429 | ||
b9bec74b | 430 | if (kvm_get_mce_cap_supported(env->kvm_state, &mcg_cap, &banks)) { |
e7701825 | 431 | perror("kvm_get_mce_cap_supported FAILED"); |
b9bec74b | 432 | } else { |
e7701825 MT |
433 | if (banks > MCE_BANKS_DEF) |
434 | banks = MCE_BANKS_DEF; | |
435 | mcg_cap &= MCE_CAP_DEF; | |
436 | mcg_cap |= banks; | |
b9bec74b | 437 | if (kvm_setup_mce(env, &mcg_cap)) { |
e7701825 | 438 | perror("kvm_setup_mce FAILED"); |
b9bec74b | 439 | } else { |
e7701825 | 440 | env->mcg_cap = mcg_cap; |
b9bec74b | 441 | } |
e7701825 MT |
442 | } |
443 | } | |
444 | #endif | |
445 | ||
486bd5a2 | 446 | return kvm_vcpu_ioctl(env, KVM_SET_CPUID2, &cpuid_data); |
05330448 AL |
447 | } |
448 | ||
caa5af0f JK |
449 | void kvm_arch_reset_vcpu(CPUState *env) |
450 | { | |
e73223a5 | 451 | env->exception_injected = -1; |
0e607a80 | 452 | env->interrupt_injected = -1; |
a0fb002c JK |
453 | env->nmi_injected = 0; |
454 | env->nmi_pending = 0; | |
ddced198 MT |
455 | if (kvm_irqchip_in_kernel()) { |
456 | env->mp_state = cpu_is_bsp(env) ? KVM_MP_STATE_RUNNABLE : | |
457 | KVM_MP_STATE_UNINITIALIZED; | |
458 | } else { | |
459 | env->mp_state = KVM_MP_STATE_RUNNABLE; | |
460 | } | |
caa5af0f JK |
461 | } |
462 | ||
75b10c43 MT |
463 | int has_msr_star; |
464 | int has_msr_hsave_pa; | |
465 | ||
466 | static void kvm_supported_msrs(CPUState *env) | |
05330448 | 467 | { |
75b10c43 | 468 | static int kvm_supported_msrs; |
05330448 AL |
469 | int ret; |
470 | ||
471 | /* first time */ | |
75b10c43 | 472 | if (kvm_supported_msrs == 0) { |
05330448 AL |
473 | struct kvm_msr_list msr_list, *kvm_msr_list; |
474 | ||
75b10c43 | 475 | kvm_supported_msrs = -1; |
05330448 AL |
476 | |
477 | /* Obtain MSR list from KVM. These are the MSRs that we must | |
478 | * save/restore */ | |
4c9f7372 | 479 | msr_list.nmsrs = 0; |
05330448 | 480 | ret = kvm_ioctl(env->kvm_state, KVM_GET_MSR_INDEX_LIST, &msr_list); |
6fb6d245 | 481 | if (ret < 0 && ret != -E2BIG) { |
75b10c43 | 482 | return; |
6fb6d245 | 483 | } |
d9db889f JK |
484 | /* Old kernel modules had a bug and could write beyond the provided |
485 | memory. Allocate at least a safe amount of 1K. */ | |
486 | kvm_msr_list = qemu_mallocz(MAX(1024, sizeof(msr_list) + | |
487 | msr_list.nmsrs * | |
488 | sizeof(msr_list.indices[0]))); | |
05330448 | 489 | |
55308450 | 490 | kvm_msr_list->nmsrs = msr_list.nmsrs; |
05330448 AL |
491 | ret = kvm_ioctl(env->kvm_state, KVM_GET_MSR_INDEX_LIST, kvm_msr_list); |
492 | if (ret >= 0) { | |
493 | int i; | |
494 | ||
495 | for (i = 0; i < kvm_msr_list->nmsrs; i++) { | |
496 | if (kvm_msr_list->indices[i] == MSR_STAR) { | |
497 | has_msr_star = 1; | |
75b10c43 MT |
498 | continue; |
499 | } | |
500 | if (kvm_msr_list->indices[i] == MSR_VM_HSAVE_PA) { | |
501 | has_msr_hsave_pa = 1; | |
502 | continue; | |
05330448 AL |
503 | } |
504 | } | |
505 | } | |
506 | ||
507 | free(kvm_msr_list); | |
508 | } | |
509 | ||
75b10c43 MT |
510 | return; |
511 | } | |
512 | ||
513 | static int kvm_has_msr_hsave_pa(CPUState *env) | |
514 | { | |
515 | kvm_supported_msrs(env); | |
516 | return has_msr_hsave_pa; | |
517 | } | |
518 | ||
519 | static int kvm_has_msr_star(CPUState *env) | |
520 | { | |
521 | kvm_supported_msrs(env); | |
522 | return has_msr_star; | |
05330448 AL |
523 | } |
524 | ||
20420430 SY |
525 | static int kvm_init_identity_map_page(KVMState *s) |
526 | { | |
527 | #ifdef KVM_CAP_SET_IDENTITY_MAP_ADDR | |
528 | int ret; | |
529 | uint64_t addr = 0xfffbc000; | |
530 | ||
531 | if (!kvm_check_extension(s, KVM_CAP_SET_IDENTITY_MAP_ADDR)) { | |
532 | return 0; | |
533 | } | |
534 | ||
535 | ret = kvm_vm_ioctl(s, KVM_SET_IDENTITY_MAP_ADDR, &addr); | |
536 | if (ret < 0) { | |
537 | fprintf(stderr, "kvm_set_identity_map_addr: %s\n", strerror(ret)); | |
538 | return ret; | |
539 | } | |
540 | #endif | |
541 | return 0; | |
542 | } | |
543 | ||
05330448 AL |
544 | int kvm_arch_init(KVMState *s, int smp_cpus) |
545 | { | |
546 | int ret; | |
547 | ||
25d2e361 MT |
548 | struct utsname utsname; |
549 | ||
550 | uname(&utsname); | |
551 | lm_capable_kernel = strcmp(utsname.machine, "x86_64") == 0; | |
552 | ||
05330448 AL |
553 | /* create vm86 tss. KVM uses vm86 mode to emulate 16-bit code |
554 | * directly. In order to use vm86 mode, a TSS is needed. Since this | |
555 | * must be part of guest physical memory, we need to allocate it. Older | |
556 | * versions of KVM just assumed that it would be at the end of physical | |
557 | * memory but that doesn't work with more than 4GB of memory. We simply | |
558 | * refuse to work with those older versions of KVM. */ | |
14a09518 | 559 | ret = kvm_check_extension(s, KVM_CAP_SET_TSS_ADDR); |
05330448 AL |
560 | if (ret <= 0) { |
561 | fprintf(stderr, "kvm does not support KVM_CAP_SET_TSS_ADDR\n"); | |
562 | return ret; | |
563 | } | |
564 | ||
565 | /* this address is 3 pages before the bios, and the bios should present | |
566 | * as unavaible memory. FIXME, need to ensure the e820 map deals with | |
567 | * this? | |
568 | */ | |
4c5b10b7 JS |
569 | /* |
570 | * Tell fw_cfg to notify the BIOS to reserve the range. | |
571 | */ | |
572 | if (e820_add_entry(0xfffbc000, 0x4000, E820_RESERVED) < 0) { | |
573 | perror("e820_add_entry() table is full"); | |
574 | exit(1); | |
575 | } | |
20420430 SY |
576 | ret = kvm_vm_ioctl(s, KVM_SET_TSS_ADDR, 0xfffbd000); |
577 | if (ret < 0) { | |
578 | return ret; | |
579 | } | |
580 | ||
581 | return kvm_init_identity_map_page(s); | |
05330448 | 582 | } |
b9bec74b | 583 | |
05330448 AL |
584 | static void set_v8086_seg(struct kvm_segment *lhs, const SegmentCache *rhs) |
585 | { | |
586 | lhs->selector = rhs->selector; | |
587 | lhs->base = rhs->base; | |
588 | lhs->limit = rhs->limit; | |
589 | lhs->type = 3; | |
590 | lhs->present = 1; | |
591 | lhs->dpl = 3; | |
592 | lhs->db = 0; | |
593 | lhs->s = 1; | |
594 | lhs->l = 0; | |
595 | lhs->g = 0; | |
596 | lhs->avl = 0; | |
597 | lhs->unusable = 0; | |
598 | } | |
599 | ||
600 | static void set_seg(struct kvm_segment *lhs, const SegmentCache *rhs) | |
601 | { | |
602 | unsigned flags = rhs->flags; | |
603 | lhs->selector = rhs->selector; | |
604 | lhs->base = rhs->base; | |
605 | lhs->limit = rhs->limit; | |
606 | lhs->type = (flags >> DESC_TYPE_SHIFT) & 15; | |
607 | lhs->present = (flags & DESC_P_MASK) != 0; | |
acaa7550 | 608 | lhs->dpl = (flags >> DESC_DPL_SHIFT) & 3; |
05330448 AL |
609 | lhs->db = (flags >> DESC_B_SHIFT) & 1; |
610 | lhs->s = (flags & DESC_S_MASK) != 0; | |
611 | lhs->l = (flags >> DESC_L_SHIFT) & 1; | |
612 | lhs->g = (flags & DESC_G_MASK) != 0; | |
613 | lhs->avl = (flags & DESC_AVL_MASK) != 0; | |
614 | lhs->unusable = 0; | |
615 | } | |
616 | ||
617 | static void get_seg(SegmentCache *lhs, const struct kvm_segment *rhs) | |
618 | { | |
619 | lhs->selector = rhs->selector; | |
620 | lhs->base = rhs->base; | |
621 | lhs->limit = rhs->limit; | |
b9bec74b JK |
622 | lhs->flags = (rhs->type << DESC_TYPE_SHIFT) | |
623 | (rhs->present * DESC_P_MASK) | | |
624 | (rhs->dpl << DESC_DPL_SHIFT) | | |
625 | (rhs->db << DESC_B_SHIFT) | | |
626 | (rhs->s * DESC_S_MASK) | | |
627 | (rhs->l << DESC_L_SHIFT) | | |
628 | (rhs->g * DESC_G_MASK) | | |
629 | (rhs->avl * DESC_AVL_MASK); | |
05330448 AL |
630 | } |
631 | ||
632 | static void kvm_getput_reg(__u64 *kvm_reg, target_ulong *qemu_reg, int set) | |
633 | { | |
b9bec74b | 634 | if (set) { |
05330448 | 635 | *kvm_reg = *qemu_reg; |
b9bec74b | 636 | } else { |
05330448 | 637 | *qemu_reg = *kvm_reg; |
b9bec74b | 638 | } |
05330448 AL |
639 | } |
640 | ||
641 | static int kvm_getput_regs(CPUState *env, int set) | |
642 | { | |
643 | struct kvm_regs regs; | |
644 | int ret = 0; | |
645 | ||
646 | if (!set) { | |
647 | ret = kvm_vcpu_ioctl(env, KVM_GET_REGS, ®s); | |
b9bec74b | 648 | if (ret < 0) { |
05330448 | 649 | return ret; |
b9bec74b | 650 | } |
05330448 AL |
651 | } |
652 | ||
653 | kvm_getput_reg(®s.rax, &env->regs[R_EAX], set); | |
654 | kvm_getput_reg(®s.rbx, &env->regs[R_EBX], set); | |
655 | kvm_getput_reg(®s.rcx, &env->regs[R_ECX], set); | |
656 | kvm_getput_reg(®s.rdx, &env->regs[R_EDX], set); | |
657 | kvm_getput_reg(®s.rsi, &env->regs[R_ESI], set); | |
658 | kvm_getput_reg(®s.rdi, &env->regs[R_EDI], set); | |
659 | kvm_getput_reg(®s.rsp, &env->regs[R_ESP], set); | |
660 | kvm_getput_reg(®s.rbp, &env->regs[R_EBP], set); | |
661 | #ifdef TARGET_X86_64 | |
662 | kvm_getput_reg(®s.r8, &env->regs[8], set); | |
663 | kvm_getput_reg(®s.r9, &env->regs[9], set); | |
664 | kvm_getput_reg(®s.r10, &env->regs[10], set); | |
665 | kvm_getput_reg(®s.r11, &env->regs[11], set); | |
666 | kvm_getput_reg(®s.r12, &env->regs[12], set); | |
667 | kvm_getput_reg(®s.r13, &env->regs[13], set); | |
668 | kvm_getput_reg(®s.r14, &env->regs[14], set); | |
669 | kvm_getput_reg(®s.r15, &env->regs[15], set); | |
670 | #endif | |
671 | ||
672 | kvm_getput_reg(®s.rflags, &env->eflags, set); | |
673 | kvm_getput_reg(®s.rip, &env->eip, set); | |
674 | ||
b9bec74b | 675 | if (set) { |
05330448 | 676 | ret = kvm_vcpu_ioctl(env, KVM_SET_REGS, ®s); |
b9bec74b | 677 | } |
05330448 AL |
678 | |
679 | return ret; | |
680 | } | |
681 | ||
682 | static int kvm_put_fpu(CPUState *env) | |
683 | { | |
684 | struct kvm_fpu fpu; | |
685 | int i; | |
686 | ||
687 | memset(&fpu, 0, sizeof fpu); | |
688 | fpu.fsw = env->fpus & ~(7 << 11); | |
689 | fpu.fsw |= (env->fpstt & 7) << 11; | |
690 | fpu.fcw = env->fpuc; | |
b9bec74b JK |
691 | for (i = 0; i < 8; ++i) { |
692 | fpu.ftwx |= (!env->fptags[i]) << i; | |
693 | } | |
05330448 AL |
694 | memcpy(fpu.fpr, env->fpregs, sizeof env->fpregs); |
695 | memcpy(fpu.xmm, env->xmm_regs, sizeof env->xmm_regs); | |
696 | fpu.mxcsr = env->mxcsr; | |
697 | ||
698 | return kvm_vcpu_ioctl(env, KVM_SET_FPU, &fpu); | |
699 | } | |
700 | ||
f1665b21 SY |
701 | #ifdef KVM_CAP_XSAVE |
702 | #define XSAVE_CWD_RIP 2 | |
703 | #define XSAVE_CWD_RDP 4 | |
704 | #define XSAVE_MXCSR 6 | |
705 | #define XSAVE_ST_SPACE 8 | |
706 | #define XSAVE_XMM_SPACE 40 | |
707 | #define XSAVE_XSTATE_BV 128 | |
708 | #define XSAVE_YMMH_SPACE 144 | |
709 | #endif | |
710 | ||
711 | static int kvm_put_xsave(CPUState *env) | |
712 | { | |
713 | #ifdef KVM_CAP_XSAVE | |
0f53994f | 714 | int i, r; |
f1665b21 SY |
715 | struct kvm_xsave* xsave; |
716 | uint16_t cwd, swd, twd, fop; | |
717 | ||
b9bec74b | 718 | if (!kvm_has_xsave()) { |
f1665b21 | 719 | return kvm_put_fpu(env); |
b9bec74b | 720 | } |
f1665b21 SY |
721 | |
722 | xsave = qemu_memalign(4096, sizeof(struct kvm_xsave)); | |
723 | memset(xsave, 0, sizeof(struct kvm_xsave)); | |
724 | cwd = swd = twd = fop = 0; | |
725 | swd = env->fpus & ~(7 << 11); | |
726 | swd |= (env->fpstt & 7) << 11; | |
727 | cwd = env->fpuc; | |
b9bec74b | 728 | for (i = 0; i < 8; ++i) { |
f1665b21 | 729 | twd |= (!env->fptags[i]) << i; |
b9bec74b | 730 | } |
f1665b21 SY |
731 | xsave->region[0] = (uint32_t)(swd << 16) + cwd; |
732 | xsave->region[1] = (uint32_t)(fop << 16) + twd; | |
733 | memcpy(&xsave->region[XSAVE_ST_SPACE], env->fpregs, | |
734 | sizeof env->fpregs); | |
735 | memcpy(&xsave->region[XSAVE_XMM_SPACE], env->xmm_regs, | |
736 | sizeof env->xmm_regs); | |
737 | xsave->region[XSAVE_MXCSR] = env->mxcsr; | |
738 | *(uint64_t *)&xsave->region[XSAVE_XSTATE_BV] = env->xstate_bv; | |
739 | memcpy(&xsave->region[XSAVE_YMMH_SPACE], env->ymmh_regs, | |
740 | sizeof env->ymmh_regs); | |
0f53994f MT |
741 | r = kvm_vcpu_ioctl(env, KVM_SET_XSAVE, xsave); |
742 | qemu_free(xsave); | |
743 | return r; | |
f1665b21 SY |
744 | #else |
745 | return kvm_put_fpu(env); | |
746 | #endif | |
747 | } | |
748 | ||
749 | static int kvm_put_xcrs(CPUState *env) | |
750 | { | |
751 | #ifdef KVM_CAP_XCRS | |
752 | struct kvm_xcrs xcrs; | |
753 | ||
b9bec74b | 754 | if (!kvm_has_xcrs()) { |
f1665b21 | 755 | return 0; |
b9bec74b | 756 | } |
f1665b21 SY |
757 | |
758 | xcrs.nr_xcrs = 1; | |
759 | xcrs.flags = 0; | |
760 | xcrs.xcrs[0].xcr = 0; | |
761 | xcrs.xcrs[0].value = env->xcr0; | |
762 | return kvm_vcpu_ioctl(env, KVM_SET_XCRS, &xcrs); | |
763 | #else | |
764 | return 0; | |
765 | #endif | |
766 | } | |
767 | ||
05330448 AL |
768 | static int kvm_put_sregs(CPUState *env) |
769 | { | |
770 | struct kvm_sregs sregs; | |
771 | ||
0e607a80 JK |
772 | memset(sregs.interrupt_bitmap, 0, sizeof(sregs.interrupt_bitmap)); |
773 | if (env->interrupt_injected >= 0) { | |
774 | sregs.interrupt_bitmap[env->interrupt_injected / 64] |= | |
775 | (uint64_t)1 << (env->interrupt_injected % 64); | |
776 | } | |
05330448 AL |
777 | |
778 | if ((env->eflags & VM_MASK)) { | |
b9bec74b JK |
779 | set_v8086_seg(&sregs.cs, &env->segs[R_CS]); |
780 | set_v8086_seg(&sregs.ds, &env->segs[R_DS]); | |
781 | set_v8086_seg(&sregs.es, &env->segs[R_ES]); | |
782 | set_v8086_seg(&sregs.fs, &env->segs[R_FS]); | |
783 | set_v8086_seg(&sregs.gs, &env->segs[R_GS]); | |
784 | set_v8086_seg(&sregs.ss, &env->segs[R_SS]); | |
05330448 | 785 | } else { |
b9bec74b JK |
786 | set_seg(&sregs.cs, &env->segs[R_CS]); |
787 | set_seg(&sregs.ds, &env->segs[R_DS]); | |
788 | set_seg(&sregs.es, &env->segs[R_ES]); | |
789 | set_seg(&sregs.fs, &env->segs[R_FS]); | |
790 | set_seg(&sregs.gs, &env->segs[R_GS]); | |
791 | set_seg(&sregs.ss, &env->segs[R_SS]); | |
05330448 AL |
792 | } |
793 | ||
794 | set_seg(&sregs.tr, &env->tr); | |
795 | set_seg(&sregs.ldt, &env->ldt); | |
796 | ||
797 | sregs.idt.limit = env->idt.limit; | |
798 | sregs.idt.base = env->idt.base; | |
799 | sregs.gdt.limit = env->gdt.limit; | |
800 | sregs.gdt.base = env->gdt.base; | |
801 | ||
802 | sregs.cr0 = env->cr[0]; | |
803 | sregs.cr2 = env->cr[2]; | |
804 | sregs.cr3 = env->cr[3]; | |
805 | sregs.cr4 = env->cr[4]; | |
806 | ||
4a942cea BS |
807 | sregs.cr8 = cpu_get_apic_tpr(env->apic_state); |
808 | sregs.apic_base = cpu_get_apic_base(env->apic_state); | |
05330448 AL |
809 | |
810 | sregs.efer = env->efer; | |
811 | ||
812 | return kvm_vcpu_ioctl(env, KVM_SET_SREGS, &sregs); | |
813 | } | |
814 | ||
815 | static void kvm_msr_entry_set(struct kvm_msr_entry *entry, | |
816 | uint32_t index, uint64_t value) | |
817 | { | |
818 | entry->index = index; | |
819 | entry->data = value; | |
820 | } | |
821 | ||
ea643051 | 822 | static int kvm_put_msrs(CPUState *env, int level) |
05330448 AL |
823 | { |
824 | struct { | |
825 | struct kvm_msrs info; | |
826 | struct kvm_msr_entry entries[100]; | |
827 | } msr_data; | |
828 | struct kvm_msr_entry *msrs = msr_data.entries; | |
d8da8574 | 829 | int n = 0; |
05330448 AL |
830 | |
831 | kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_CS, env->sysenter_cs); | |
832 | kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_ESP, env->sysenter_esp); | |
833 | kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_EIP, env->sysenter_eip); | |
b9bec74b JK |
834 | if (kvm_has_msr_star(env)) { |
835 | kvm_msr_entry_set(&msrs[n++], MSR_STAR, env->star); | |
836 | } | |
837 | if (kvm_has_msr_hsave_pa(env)) { | |
75b10c43 | 838 | kvm_msr_entry_set(&msrs[n++], MSR_VM_HSAVE_PA, env->vm_hsave); |
b9bec74b | 839 | } |
05330448 | 840 | #ifdef TARGET_X86_64 |
25d2e361 MT |
841 | if (lm_capable_kernel) { |
842 | kvm_msr_entry_set(&msrs[n++], MSR_CSTAR, env->cstar); | |
843 | kvm_msr_entry_set(&msrs[n++], MSR_KERNELGSBASE, env->kernelgsbase); | |
844 | kvm_msr_entry_set(&msrs[n++], MSR_FMASK, env->fmask); | |
845 | kvm_msr_entry_set(&msrs[n++], MSR_LSTAR, env->lstar); | |
846 | } | |
05330448 | 847 | #endif |
ea643051 | 848 | if (level == KVM_PUT_FULL_STATE) { |
384331a6 MT |
849 | /* |
850 | * KVM is yet unable to synchronize TSC values of multiple VCPUs on | |
851 | * writeback. Until this is fixed, we only write the offset to SMP | |
852 | * guests after migration, desynchronizing the VCPUs, but avoiding | |
853 | * huge jump-backs that would occur without any writeback at all. | |
854 | */ | |
855 | if (smp_cpus == 1 || env->tsc != 0) { | |
856 | kvm_msr_entry_set(&msrs[n++], MSR_IA32_TSC, env->tsc); | |
857 | } | |
ea643051 JK |
858 | kvm_msr_entry_set(&msrs[n++], MSR_KVM_SYSTEM_TIME, |
859 | env->system_time_msr); | |
860 | kvm_msr_entry_set(&msrs[n++], MSR_KVM_WALL_CLOCK, env->wall_clock_msr); | |
f6584ee2 GN |
861 | #ifdef KVM_CAP_ASYNC_PF |
862 | kvm_msr_entry_set(&msrs[n++], MSR_KVM_ASYNC_PF_EN, env->async_pf_en_msr); | |
863 | #endif | |
ea643051 | 864 | } |
57780495 MT |
865 | #ifdef KVM_CAP_MCE |
866 | if (env->mcg_cap) { | |
d8da8574 | 867 | int i; |
b9bec74b JK |
868 | |
869 | if (level == KVM_PUT_RESET_STATE) { | |
57780495 | 870 | kvm_msr_entry_set(&msrs[n++], MSR_MCG_STATUS, env->mcg_status); |
b9bec74b | 871 | } else if (level == KVM_PUT_FULL_STATE) { |
57780495 MT |
872 | kvm_msr_entry_set(&msrs[n++], MSR_MCG_STATUS, env->mcg_status); |
873 | kvm_msr_entry_set(&msrs[n++], MSR_MCG_CTL, env->mcg_ctl); | |
b9bec74b | 874 | for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) { |
57780495 | 875 | kvm_msr_entry_set(&msrs[n++], MSR_MC0_CTL + i, env->mce_banks[i]); |
b9bec74b | 876 | } |
57780495 MT |
877 | } |
878 | } | |
879 | #endif | |
1a03675d | 880 | |
05330448 AL |
881 | msr_data.info.nmsrs = n; |
882 | ||
883 | return kvm_vcpu_ioctl(env, KVM_SET_MSRS, &msr_data); | |
884 | ||
885 | } | |
886 | ||
887 | ||
888 | static int kvm_get_fpu(CPUState *env) | |
889 | { | |
890 | struct kvm_fpu fpu; | |
891 | int i, ret; | |
892 | ||
893 | ret = kvm_vcpu_ioctl(env, KVM_GET_FPU, &fpu); | |
b9bec74b | 894 | if (ret < 0) { |
05330448 | 895 | return ret; |
b9bec74b | 896 | } |
05330448 AL |
897 | |
898 | env->fpstt = (fpu.fsw >> 11) & 7; | |
899 | env->fpus = fpu.fsw; | |
900 | env->fpuc = fpu.fcw; | |
b9bec74b JK |
901 | for (i = 0; i < 8; ++i) { |
902 | env->fptags[i] = !((fpu.ftwx >> i) & 1); | |
903 | } | |
05330448 AL |
904 | memcpy(env->fpregs, fpu.fpr, sizeof env->fpregs); |
905 | memcpy(env->xmm_regs, fpu.xmm, sizeof env->xmm_regs); | |
906 | env->mxcsr = fpu.mxcsr; | |
907 | ||
908 | return 0; | |
909 | } | |
910 | ||
f1665b21 SY |
911 | static int kvm_get_xsave(CPUState *env) |
912 | { | |
913 | #ifdef KVM_CAP_XSAVE | |
914 | struct kvm_xsave* xsave; | |
915 | int ret, i; | |
916 | uint16_t cwd, swd, twd, fop; | |
917 | ||
b9bec74b | 918 | if (!kvm_has_xsave()) { |
f1665b21 | 919 | return kvm_get_fpu(env); |
b9bec74b | 920 | } |
f1665b21 SY |
921 | |
922 | xsave = qemu_memalign(4096, sizeof(struct kvm_xsave)); | |
923 | ret = kvm_vcpu_ioctl(env, KVM_GET_XSAVE, xsave); | |
0f53994f MT |
924 | if (ret < 0) { |
925 | qemu_free(xsave); | |
f1665b21 | 926 | return ret; |
0f53994f | 927 | } |
f1665b21 SY |
928 | |
929 | cwd = (uint16_t)xsave->region[0]; | |
930 | swd = (uint16_t)(xsave->region[0] >> 16); | |
931 | twd = (uint16_t)xsave->region[1]; | |
932 | fop = (uint16_t)(xsave->region[1] >> 16); | |
933 | env->fpstt = (swd >> 11) & 7; | |
934 | env->fpus = swd; | |
935 | env->fpuc = cwd; | |
b9bec74b | 936 | for (i = 0; i < 8; ++i) { |
f1665b21 | 937 | env->fptags[i] = !((twd >> i) & 1); |
b9bec74b | 938 | } |
f1665b21 SY |
939 | env->mxcsr = xsave->region[XSAVE_MXCSR]; |
940 | memcpy(env->fpregs, &xsave->region[XSAVE_ST_SPACE], | |
941 | sizeof env->fpregs); | |
942 | memcpy(env->xmm_regs, &xsave->region[XSAVE_XMM_SPACE], | |
943 | sizeof env->xmm_regs); | |
944 | env->xstate_bv = *(uint64_t *)&xsave->region[XSAVE_XSTATE_BV]; | |
945 | memcpy(env->ymmh_regs, &xsave->region[XSAVE_YMMH_SPACE], | |
946 | sizeof env->ymmh_regs); | |
0f53994f | 947 | qemu_free(xsave); |
f1665b21 SY |
948 | return 0; |
949 | #else | |
950 | return kvm_get_fpu(env); | |
951 | #endif | |
952 | } | |
953 | ||
954 | static int kvm_get_xcrs(CPUState *env) | |
955 | { | |
956 | #ifdef KVM_CAP_XCRS | |
957 | int i, ret; | |
958 | struct kvm_xcrs xcrs; | |
959 | ||
b9bec74b | 960 | if (!kvm_has_xcrs()) { |
f1665b21 | 961 | return 0; |
b9bec74b | 962 | } |
f1665b21 SY |
963 | |
964 | ret = kvm_vcpu_ioctl(env, KVM_GET_XCRS, &xcrs); | |
b9bec74b | 965 | if (ret < 0) { |
f1665b21 | 966 | return ret; |
b9bec74b | 967 | } |
f1665b21 | 968 | |
b9bec74b | 969 | for (i = 0; i < xcrs.nr_xcrs; i++) { |
f1665b21 SY |
970 | /* Only support xcr0 now */ |
971 | if (xcrs.xcrs[0].xcr == 0) { | |
972 | env->xcr0 = xcrs.xcrs[0].value; | |
973 | break; | |
974 | } | |
b9bec74b | 975 | } |
f1665b21 SY |
976 | return 0; |
977 | #else | |
978 | return 0; | |
979 | #endif | |
980 | } | |
981 | ||
05330448 AL |
982 | static int kvm_get_sregs(CPUState *env) |
983 | { | |
984 | struct kvm_sregs sregs; | |
985 | uint32_t hflags; | |
0e607a80 | 986 | int bit, i, ret; |
05330448 AL |
987 | |
988 | ret = kvm_vcpu_ioctl(env, KVM_GET_SREGS, &sregs); | |
b9bec74b | 989 | if (ret < 0) { |
05330448 | 990 | return ret; |
b9bec74b | 991 | } |
05330448 | 992 | |
0e607a80 JK |
993 | /* There can only be one pending IRQ set in the bitmap at a time, so try |
994 | to find it and save its number instead (-1 for none). */ | |
995 | env->interrupt_injected = -1; | |
996 | for (i = 0; i < ARRAY_SIZE(sregs.interrupt_bitmap); i++) { | |
997 | if (sregs.interrupt_bitmap[i]) { | |
998 | bit = ctz64(sregs.interrupt_bitmap[i]); | |
999 | env->interrupt_injected = i * 64 + bit; | |
1000 | break; | |
1001 | } | |
1002 | } | |
05330448 AL |
1003 | |
1004 | get_seg(&env->segs[R_CS], &sregs.cs); | |
1005 | get_seg(&env->segs[R_DS], &sregs.ds); | |
1006 | get_seg(&env->segs[R_ES], &sregs.es); | |
1007 | get_seg(&env->segs[R_FS], &sregs.fs); | |
1008 | get_seg(&env->segs[R_GS], &sregs.gs); | |
1009 | get_seg(&env->segs[R_SS], &sregs.ss); | |
1010 | ||
1011 | get_seg(&env->tr, &sregs.tr); | |
1012 | get_seg(&env->ldt, &sregs.ldt); | |
1013 | ||
1014 | env->idt.limit = sregs.idt.limit; | |
1015 | env->idt.base = sregs.idt.base; | |
1016 | env->gdt.limit = sregs.gdt.limit; | |
1017 | env->gdt.base = sregs.gdt.base; | |
1018 | ||
1019 | env->cr[0] = sregs.cr0; | |
1020 | env->cr[2] = sregs.cr2; | |
1021 | env->cr[3] = sregs.cr3; | |
1022 | env->cr[4] = sregs.cr4; | |
1023 | ||
4a942cea | 1024 | cpu_set_apic_base(env->apic_state, sregs.apic_base); |
05330448 AL |
1025 | |
1026 | env->efer = sregs.efer; | |
4a942cea | 1027 | //cpu_set_apic_tpr(env->apic_state, sregs.cr8); |
05330448 | 1028 | |
b9bec74b JK |
1029 | #define HFLAG_COPY_MASK \ |
1030 | ~( HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \ | |
1031 | HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \ | |
1032 | HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \ | |
1033 | HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK) | |
05330448 AL |
1034 | |
1035 | hflags = (env->segs[R_CS].flags >> DESC_DPL_SHIFT) & HF_CPL_MASK; | |
1036 | hflags |= (env->cr[0] & CR0_PE_MASK) << (HF_PE_SHIFT - CR0_PE_SHIFT); | |
1037 | hflags |= (env->cr[0] << (HF_MP_SHIFT - CR0_MP_SHIFT)) & | |
b9bec74b | 1038 | (HF_MP_MASK | HF_EM_MASK | HF_TS_MASK); |
05330448 AL |
1039 | hflags |= (env->eflags & (HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK)); |
1040 | hflags |= (env->cr[4] & CR4_OSFXSR_MASK) << | |
b9bec74b | 1041 | (HF_OSFXSR_SHIFT - CR4_OSFXSR_SHIFT); |
05330448 AL |
1042 | |
1043 | if (env->efer & MSR_EFER_LMA) { | |
1044 | hflags |= HF_LMA_MASK; | |
1045 | } | |
1046 | ||
1047 | if ((hflags & HF_LMA_MASK) && (env->segs[R_CS].flags & DESC_L_MASK)) { | |
1048 | hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK; | |
1049 | } else { | |
1050 | hflags |= (env->segs[R_CS].flags & DESC_B_MASK) >> | |
b9bec74b | 1051 | (DESC_B_SHIFT - HF_CS32_SHIFT); |
05330448 | 1052 | hflags |= (env->segs[R_SS].flags & DESC_B_MASK) >> |
b9bec74b JK |
1053 | (DESC_B_SHIFT - HF_SS32_SHIFT); |
1054 | if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK) || | |
1055 | !(hflags & HF_CS32_MASK)) { | |
1056 | hflags |= HF_ADDSEG_MASK; | |
1057 | } else { | |
1058 | hflags |= ((env->segs[R_DS].base | env->segs[R_ES].base | | |
1059 | env->segs[R_SS].base) != 0) << HF_ADDSEG_SHIFT; | |
1060 | } | |
05330448 AL |
1061 | } |
1062 | env->hflags = (env->hflags & HFLAG_COPY_MASK) | hflags; | |
05330448 AL |
1063 | |
1064 | return 0; | |
1065 | } | |
1066 | ||
1067 | static int kvm_get_msrs(CPUState *env) | |
1068 | { | |
1069 | struct { | |
1070 | struct kvm_msrs info; | |
1071 | struct kvm_msr_entry entries[100]; | |
1072 | } msr_data; | |
1073 | struct kvm_msr_entry *msrs = msr_data.entries; | |
1074 | int ret, i, n; | |
1075 | ||
1076 | n = 0; | |
1077 | msrs[n++].index = MSR_IA32_SYSENTER_CS; | |
1078 | msrs[n++].index = MSR_IA32_SYSENTER_ESP; | |
1079 | msrs[n++].index = MSR_IA32_SYSENTER_EIP; | |
b9bec74b JK |
1080 | if (kvm_has_msr_star(env)) { |
1081 | msrs[n++].index = MSR_STAR; | |
1082 | } | |
1083 | if (kvm_has_msr_hsave_pa(env)) { | |
75b10c43 | 1084 | msrs[n++].index = MSR_VM_HSAVE_PA; |
b9bec74b | 1085 | } |
05330448 AL |
1086 | msrs[n++].index = MSR_IA32_TSC; |
1087 | #ifdef TARGET_X86_64 | |
25d2e361 MT |
1088 | if (lm_capable_kernel) { |
1089 | msrs[n++].index = MSR_CSTAR; | |
1090 | msrs[n++].index = MSR_KERNELGSBASE; | |
1091 | msrs[n++].index = MSR_FMASK; | |
1092 | msrs[n++].index = MSR_LSTAR; | |
1093 | } | |
05330448 | 1094 | #endif |
1a03675d GC |
1095 | msrs[n++].index = MSR_KVM_SYSTEM_TIME; |
1096 | msrs[n++].index = MSR_KVM_WALL_CLOCK; | |
f6584ee2 GN |
1097 | #ifdef KVM_CAP_ASYNC_PF |
1098 | msrs[n++].index = MSR_KVM_ASYNC_PF_EN; | |
1099 | #endif | |
1a03675d | 1100 | |
57780495 MT |
1101 | #ifdef KVM_CAP_MCE |
1102 | if (env->mcg_cap) { | |
1103 | msrs[n++].index = MSR_MCG_STATUS; | |
1104 | msrs[n++].index = MSR_MCG_CTL; | |
b9bec74b | 1105 | for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) { |
57780495 | 1106 | msrs[n++].index = MSR_MC0_CTL + i; |
b9bec74b | 1107 | } |
57780495 MT |
1108 | } |
1109 | #endif | |
1110 | ||
05330448 AL |
1111 | msr_data.info.nmsrs = n; |
1112 | ret = kvm_vcpu_ioctl(env, KVM_GET_MSRS, &msr_data); | |
b9bec74b | 1113 | if (ret < 0) { |
05330448 | 1114 | return ret; |
b9bec74b | 1115 | } |
05330448 AL |
1116 | |
1117 | for (i = 0; i < ret; i++) { | |
1118 | switch (msrs[i].index) { | |
1119 | case MSR_IA32_SYSENTER_CS: | |
1120 | env->sysenter_cs = msrs[i].data; | |
1121 | break; | |
1122 | case MSR_IA32_SYSENTER_ESP: | |
1123 | env->sysenter_esp = msrs[i].data; | |
1124 | break; | |
1125 | case MSR_IA32_SYSENTER_EIP: | |
1126 | env->sysenter_eip = msrs[i].data; | |
1127 | break; | |
1128 | case MSR_STAR: | |
1129 | env->star = msrs[i].data; | |
1130 | break; | |
1131 | #ifdef TARGET_X86_64 | |
1132 | case MSR_CSTAR: | |
1133 | env->cstar = msrs[i].data; | |
1134 | break; | |
1135 | case MSR_KERNELGSBASE: | |
1136 | env->kernelgsbase = msrs[i].data; | |
1137 | break; | |
1138 | case MSR_FMASK: | |
1139 | env->fmask = msrs[i].data; | |
1140 | break; | |
1141 | case MSR_LSTAR: | |
1142 | env->lstar = msrs[i].data; | |
1143 | break; | |
1144 | #endif | |
1145 | case MSR_IA32_TSC: | |
1146 | env->tsc = msrs[i].data; | |
1147 | break; | |
aa851e36 MT |
1148 | case MSR_VM_HSAVE_PA: |
1149 | env->vm_hsave = msrs[i].data; | |
1150 | break; | |
1a03675d GC |
1151 | case MSR_KVM_SYSTEM_TIME: |
1152 | env->system_time_msr = msrs[i].data; | |
1153 | break; | |
1154 | case MSR_KVM_WALL_CLOCK: | |
1155 | env->wall_clock_msr = msrs[i].data; | |
1156 | break; | |
57780495 MT |
1157 | #ifdef KVM_CAP_MCE |
1158 | case MSR_MCG_STATUS: | |
1159 | env->mcg_status = msrs[i].data; | |
1160 | break; | |
1161 | case MSR_MCG_CTL: | |
1162 | env->mcg_ctl = msrs[i].data; | |
1163 | break; | |
1164 | #endif | |
1165 | default: | |
1166 | #ifdef KVM_CAP_MCE | |
1167 | if (msrs[i].index >= MSR_MC0_CTL && | |
1168 | msrs[i].index < MSR_MC0_CTL + (env->mcg_cap & 0xff) * 4) { | |
1169 | env->mce_banks[msrs[i].index - MSR_MC0_CTL] = msrs[i].data; | |
57780495 MT |
1170 | } |
1171 | #endif | |
d8da8574 | 1172 | break; |
f6584ee2 GN |
1173 | #ifdef KVM_CAP_ASYNC_PF |
1174 | case MSR_KVM_ASYNC_PF_EN: | |
1175 | env->async_pf_en_msr = msrs[i].data; | |
1176 | break; | |
1177 | #endif | |
05330448 AL |
1178 | } |
1179 | } | |
1180 | ||
1181 | return 0; | |
1182 | } | |
1183 | ||
9bdbe550 HB |
1184 | static int kvm_put_mp_state(CPUState *env) |
1185 | { | |
1186 | struct kvm_mp_state mp_state = { .mp_state = env->mp_state }; | |
1187 | ||
1188 | return kvm_vcpu_ioctl(env, KVM_SET_MP_STATE, &mp_state); | |
1189 | } | |
1190 | ||
1191 | static int kvm_get_mp_state(CPUState *env) | |
1192 | { | |
1193 | struct kvm_mp_state mp_state; | |
1194 | int ret; | |
1195 | ||
1196 | ret = kvm_vcpu_ioctl(env, KVM_GET_MP_STATE, &mp_state); | |
1197 | if (ret < 0) { | |
1198 | return ret; | |
1199 | } | |
1200 | env->mp_state = mp_state.mp_state; | |
1201 | return 0; | |
1202 | } | |
1203 | ||
ea643051 | 1204 | static int kvm_put_vcpu_events(CPUState *env, int level) |
a0fb002c JK |
1205 | { |
1206 | #ifdef KVM_CAP_VCPU_EVENTS | |
1207 | struct kvm_vcpu_events events; | |
1208 | ||
1209 | if (!kvm_has_vcpu_events()) { | |
1210 | return 0; | |
1211 | } | |
1212 | ||
31827373 JK |
1213 | events.exception.injected = (env->exception_injected >= 0); |
1214 | events.exception.nr = env->exception_injected; | |
a0fb002c JK |
1215 | events.exception.has_error_code = env->has_error_code; |
1216 | events.exception.error_code = env->error_code; | |
1217 | ||
1218 | events.interrupt.injected = (env->interrupt_injected >= 0); | |
1219 | events.interrupt.nr = env->interrupt_injected; | |
1220 | events.interrupt.soft = env->soft_interrupt; | |
1221 | ||
1222 | events.nmi.injected = env->nmi_injected; | |
1223 | events.nmi.pending = env->nmi_pending; | |
1224 | events.nmi.masked = !!(env->hflags2 & HF2_NMI_MASK); | |
1225 | ||
1226 | events.sipi_vector = env->sipi_vector; | |
1227 | ||
ea643051 JK |
1228 | events.flags = 0; |
1229 | if (level >= KVM_PUT_RESET_STATE) { | |
1230 | events.flags |= | |
1231 | KVM_VCPUEVENT_VALID_NMI_PENDING | KVM_VCPUEVENT_VALID_SIPI_VECTOR; | |
1232 | } | |
aee028b9 | 1233 | |
a0fb002c JK |
1234 | return kvm_vcpu_ioctl(env, KVM_SET_VCPU_EVENTS, &events); |
1235 | #else | |
1236 | return 0; | |
1237 | #endif | |
1238 | } | |
1239 | ||
1240 | static int kvm_get_vcpu_events(CPUState *env) | |
1241 | { | |
1242 | #ifdef KVM_CAP_VCPU_EVENTS | |
1243 | struct kvm_vcpu_events events; | |
1244 | int ret; | |
1245 | ||
1246 | if (!kvm_has_vcpu_events()) { | |
1247 | return 0; | |
1248 | } | |
1249 | ||
1250 | ret = kvm_vcpu_ioctl(env, KVM_GET_VCPU_EVENTS, &events); | |
1251 | if (ret < 0) { | |
1252 | return ret; | |
1253 | } | |
31827373 | 1254 | env->exception_injected = |
a0fb002c JK |
1255 | events.exception.injected ? events.exception.nr : -1; |
1256 | env->has_error_code = events.exception.has_error_code; | |
1257 | env->error_code = events.exception.error_code; | |
1258 | ||
1259 | env->interrupt_injected = | |
1260 | events.interrupt.injected ? events.interrupt.nr : -1; | |
1261 | env->soft_interrupt = events.interrupt.soft; | |
1262 | ||
1263 | env->nmi_injected = events.nmi.injected; | |
1264 | env->nmi_pending = events.nmi.pending; | |
1265 | if (events.nmi.masked) { | |
1266 | env->hflags2 |= HF2_NMI_MASK; | |
1267 | } else { | |
1268 | env->hflags2 &= ~HF2_NMI_MASK; | |
1269 | } | |
1270 | ||
1271 | env->sipi_vector = events.sipi_vector; | |
1272 | #endif | |
1273 | ||
1274 | return 0; | |
1275 | } | |
1276 | ||
b0b1d690 JK |
1277 | static int kvm_guest_debug_workarounds(CPUState *env) |
1278 | { | |
1279 | int ret = 0; | |
1280 | #ifdef KVM_CAP_SET_GUEST_DEBUG | |
1281 | unsigned long reinject_trap = 0; | |
1282 | ||
1283 | if (!kvm_has_vcpu_events()) { | |
1284 | if (env->exception_injected == 1) { | |
1285 | reinject_trap = KVM_GUESTDBG_INJECT_DB; | |
1286 | } else if (env->exception_injected == 3) { | |
1287 | reinject_trap = KVM_GUESTDBG_INJECT_BP; | |
1288 | } | |
1289 | env->exception_injected = -1; | |
1290 | } | |
1291 | ||
1292 | /* | |
1293 | * Kernels before KVM_CAP_X86_ROBUST_SINGLESTEP overwrote flags.TF | |
1294 | * injected via SET_GUEST_DEBUG while updating GP regs. Work around this | |
1295 | * by updating the debug state once again if single-stepping is on. | |
1296 | * Another reason to call kvm_update_guest_debug here is a pending debug | |
1297 | * trap raise by the guest. On kernels without SET_VCPU_EVENTS we have to | |
1298 | * reinject them via SET_GUEST_DEBUG. | |
1299 | */ | |
1300 | if (reinject_trap || | |
1301 | (!kvm_has_robust_singlestep() && env->singlestep_enabled)) { | |
1302 | ret = kvm_update_guest_debug(env, reinject_trap); | |
1303 | } | |
1304 | #endif /* KVM_CAP_SET_GUEST_DEBUG */ | |
1305 | return ret; | |
1306 | } | |
1307 | ||
ff44f1a3 JK |
1308 | static int kvm_put_debugregs(CPUState *env) |
1309 | { | |
1310 | #ifdef KVM_CAP_DEBUGREGS | |
1311 | struct kvm_debugregs dbgregs; | |
1312 | int i; | |
1313 | ||
1314 | if (!kvm_has_debugregs()) { | |
1315 | return 0; | |
1316 | } | |
1317 | ||
1318 | for (i = 0; i < 4; i++) { | |
1319 | dbgregs.db[i] = env->dr[i]; | |
1320 | } | |
1321 | dbgregs.dr6 = env->dr[6]; | |
1322 | dbgregs.dr7 = env->dr[7]; | |
1323 | dbgregs.flags = 0; | |
1324 | ||
1325 | return kvm_vcpu_ioctl(env, KVM_SET_DEBUGREGS, &dbgregs); | |
1326 | #else | |
1327 | return 0; | |
1328 | #endif | |
1329 | } | |
1330 | ||
1331 | static int kvm_get_debugregs(CPUState *env) | |
1332 | { | |
1333 | #ifdef KVM_CAP_DEBUGREGS | |
1334 | struct kvm_debugregs dbgregs; | |
1335 | int i, ret; | |
1336 | ||
1337 | if (!kvm_has_debugregs()) { | |
1338 | return 0; | |
1339 | } | |
1340 | ||
1341 | ret = kvm_vcpu_ioctl(env, KVM_GET_DEBUGREGS, &dbgregs); | |
1342 | if (ret < 0) { | |
b9bec74b | 1343 | return ret; |
ff44f1a3 JK |
1344 | } |
1345 | for (i = 0; i < 4; i++) { | |
1346 | env->dr[i] = dbgregs.db[i]; | |
1347 | } | |
1348 | env->dr[4] = env->dr[6] = dbgregs.dr6; | |
1349 | env->dr[5] = env->dr[7] = dbgregs.dr7; | |
1350 | #endif | |
1351 | ||
1352 | return 0; | |
1353 | } | |
1354 | ||
ea375f9a | 1355 | int kvm_arch_put_registers(CPUState *env, int level) |
05330448 AL |
1356 | { |
1357 | int ret; | |
1358 | ||
dbaa07c4 JK |
1359 | assert(cpu_is_stopped(env) || qemu_cpu_self(env)); |
1360 | ||
05330448 | 1361 | ret = kvm_getput_regs(env, 1); |
b9bec74b | 1362 | if (ret < 0) { |
05330448 | 1363 | return ret; |
b9bec74b | 1364 | } |
f1665b21 | 1365 | ret = kvm_put_xsave(env); |
b9bec74b | 1366 | if (ret < 0) { |
f1665b21 | 1367 | return ret; |
b9bec74b | 1368 | } |
f1665b21 | 1369 | ret = kvm_put_xcrs(env); |
b9bec74b | 1370 | if (ret < 0) { |
05330448 | 1371 | return ret; |
b9bec74b | 1372 | } |
05330448 | 1373 | ret = kvm_put_sregs(env); |
b9bec74b | 1374 | if (ret < 0) { |
05330448 | 1375 | return ret; |
b9bec74b | 1376 | } |
ea643051 | 1377 | ret = kvm_put_msrs(env, level); |
b9bec74b | 1378 | if (ret < 0) { |
05330448 | 1379 | return ret; |
b9bec74b | 1380 | } |
ea643051 JK |
1381 | if (level >= KVM_PUT_RESET_STATE) { |
1382 | ret = kvm_put_mp_state(env); | |
b9bec74b | 1383 | if (ret < 0) { |
ea643051 | 1384 | return ret; |
b9bec74b | 1385 | } |
ea643051 | 1386 | } |
ea643051 | 1387 | ret = kvm_put_vcpu_events(env, level); |
b9bec74b | 1388 | if (ret < 0) { |
a0fb002c | 1389 | return ret; |
b9bec74b | 1390 | } |
b0b1d690 JK |
1391 | /* must be last */ |
1392 | ret = kvm_guest_debug_workarounds(env); | |
b9bec74b | 1393 | if (ret < 0) { |
b0b1d690 | 1394 | return ret; |
b9bec74b | 1395 | } |
ff44f1a3 | 1396 | ret = kvm_put_debugregs(env); |
b9bec74b | 1397 | if (ret < 0) { |
ff44f1a3 | 1398 | return ret; |
b9bec74b | 1399 | } |
05330448 AL |
1400 | return 0; |
1401 | } | |
1402 | ||
1403 | int kvm_arch_get_registers(CPUState *env) | |
1404 | { | |
1405 | int ret; | |
1406 | ||
dbaa07c4 JK |
1407 | assert(cpu_is_stopped(env) || qemu_cpu_self(env)); |
1408 | ||
05330448 | 1409 | ret = kvm_getput_regs(env, 0); |
b9bec74b | 1410 | if (ret < 0) { |
05330448 | 1411 | return ret; |
b9bec74b | 1412 | } |
f1665b21 | 1413 | ret = kvm_get_xsave(env); |
b9bec74b | 1414 | if (ret < 0) { |
f1665b21 | 1415 | return ret; |
b9bec74b | 1416 | } |
f1665b21 | 1417 | ret = kvm_get_xcrs(env); |
b9bec74b | 1418 | if (ret < 0) { |
05330448 | 1419 | return ret; |
b9bec74b | 1420 | } |
05330448 | 1421 | ret = kvm_get_sregs(env); |
b9bec74b | 1422 | if (ret < 0) { |
05330448 | 1423 | return ret; |
b9bec74b | 1424 | } |
05330448 | 1425 | ret = kvm_get_msrs(env); |
b9bec74b | 1426 | if (ret < 0) { |
05330448 | 1427 | return ret; |
b9bec74b | 1428 | } |
5a2e3c2e | 1429 | ret = kvm_get_mp_state(env); |
b9bec74b | 1430 | if (ret < 0) { |
5a2e3c2e | 1431 | return ret; |
b9bec74b | 1432 | } |
a0fb002c | 1433 | ret = kvm_get_vcpu_events(env); |
b9bec74b | 1434 | if (ret < 0) { |
a0fb002c | 1435 | return ret; |
b9bec74b | 1436 | } |
ff44f1a3 | 1437 | ret = kvm_get_debugregs(env); |
b9bec74b | 1438 | if (ret < 0) { |
ff44f1a3 | 1439 | return ret; |
b9bec74b | 1440 | } |
05330448 AL |
1441 | return 0; |
1442 | } | |
1443 | ||
1444 | int kvm_arch_pre_run(CPUState *env, struct kvm_run *run) | |
1445 | { | |
276ce815 LJ |
1446 | /* Inject NMI */ |
1447 | if (env->interrupt_request & CPU_INTERRUPT_NMI) { | |
1448 | env->interrupt_request &= ~CPU_INTERRUPT_NMI; | |
1449 | DPRINTF("injected NMI\n"); | |
1450 | kvm_vcpu_ioctl(env, KVM_NMI); | |
1451 | } | |
1452 | ||
05330448 AL |
1453 | /* Try to inject an interrupt if the guest can accept it */ |
1454 | if (run->ready_for_interrupt_injection && | |
1455 | (env->interrupt_request & CPU_INTERRUPT_HARD) && | |
1456 | (env->eflags & IF_MASK)) { | |
1457 | int irq; | |
1458 | ||
1459 | env->interrupt_request &= ~CPU_INTERRUPT_HARD; | |
1460 | irq = cpu_get_pic_interrupt(env); | |
1461 | if (irq >= 0) { | |
1462 | struct kvm_interrupt intr; | |
1463 | intr.irq = irq; | |
1464 | /* FIXME: errors */ | |
8c0d577e | 1465 | DPRINTF("injected interrupt %d\n", irq); |
05330448 AL |
1466 | kvm_vcpu_ioctl(env, KVM_INTERRUPT, &intr); |
1467 | } | |
1468 | } | |
1469 | ||
1470 | /* If we have an interrupt but the guest is not ready to receive an | |
1471 | * interrupt, request an interrupt window exit. This will | |
1472 | * cause a return to userspace as soon as the guest is ready to | |
1473 | * receive interrupts. */ | |
b9bec74b | 1474 | if ((env->interrupt_request & CPU_INTERRUPT_HARD)) { |
05330448 | 1475 | run->request_interrupt_window = 1; |
b9bec74b | 1476 | } else { |
05330448 | 1477 | run->request_interrupt_window = 0; |
b9bec74b | 1478 | } |
05330448 | 1479 | |
8c0d577e | 1480 | DPRINTF("setting tpr\n"); |
4a942cea | 1481 | run->cr8 = cpu_get_apic_tpr(env->apic_state); |
05330448 AL |
1482 | |
1483 | return 0; | |
1484 | } | |
1485 | ||
1486 | int kvm_arch_post_run(CPUState *env, struct kvm_run *run) | |
1487 | { | |
b9bec74b | 1488 | if (run->if_flag) { |
05330448 | 1489 | env->eflags |= IF_MASK; |
b9bec74b | 1490 | } else { |
05330448 | 1491 | env->eflags &= ~IF_MASK; |
b9bec74b | 1492 | } |
4a942cea BS |
1493 | cpu_set_apic_tpr(env->apic_state, run->cr8); |
1494 | cpu_set_apic_base(env->apic_state, run->apic_base); | |
05330448 AL |
1495 | |
1496 | return 0; | |
1497 | } | |
1498 | ||
0af691d7 MT |
1499 | int kvm_arch_process_irqchip_events(CPUState *env) |
1500 | { | |
1501 | if (env->interrupt_request & CPU_INTERRUPT_INIT) { | |
1502 | kvm_cpu_synchronize_state(env); | |
1503 | do_cpu_init(env); | |
1504 | env->exception_index = EXCP_HALTED; | |
1505 | } | |
1506 | ||
1507 | if (env->interrupt_request & CPU_INTERRUPT_SIPI) { | |
1508 | kvm_cpu_synchronize_state(env); | |
1509 | do_cpu_sipi(env); | |
1510 | } | |
1511 | ||
1512 | return env->halted; | |
1513 | } | |
1514 | ||
05330448 AL |
1515 | static int kvm_handle_halt(CPUState *env) |
1516 | { | |
1517 | if (!((env->interrupt_request & CPU_INTERRUPT_HARD) && | |
1518 | (env->eflags & IF_MASK)) && | |
1519 | !(env->interrupt_request & CPU_INTERRUPT_NMI)) { | |
1520 | env->halted = 1; | |
1521 | env->exception_index = EXCP_HLT; | |
1522 | return 0; | |
1523 | } | |
1524 | ||
1525 | return 1; | |
1526 | } | |
1527 | ||
1528 | int kvm_arch_handle_exit(CPUState *env, struct kvm_run *run) | |
1529 | { | |
1530 | int ret = 0; | |
1531 | ||
1532 | switch (run->exit_reason) { | |
1533 | case KVM_EXIT_HLT: | |
8c0d577e | 1534 | DPRINTF("handle_hlt\n"); |
05330448 AL |
1535 | ret = kvm_handle_halt(env); |
1536 | break; | |
646042e1 JK |
1537 | case KVM_EXIT_SET_TPR: |
1538 | ret = 1; | |
1539 | break; | |
05330448 AL |
1540 | } |
1541 | ||
1542 | return ret; | |
1543 | } | |
e22a25c9 AL |
1544 | |
1545 | #ifdef KVM_CAP_SET_GUEST_DEBUG | |
e22a25c9 AL |
1546 | int kvm_arch_insert_sw_breakpoint(CPUState *env, struct kvm_sw_breakpoint *bp) |
1547 | { | |
38972938 | 1548 | static const uint8_t int3 = 0xcc; |
64bf3f4e | 1549 | |
e22a25c9 | 1550 | if (cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&bp->saved_insn, 1, 0) || |
b9bec74b | 1551 | cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&int3, 1, 1)) { |
e22a25c9 | 1552 | return -EINVAL; |
b9bec74b | 1553 | } |
e22a25c9 AL |
1554 | return 0; |
1555 | } | |
1556 | ||
1557 | int kvm_arch_remove_sw_breakpoint(CPUState *env, struct kvm_sw_breakpoint *bp) | |
1558 | { | |
1559 | uint8_t int3; | |
1560 | ||
1561 | if (cpu_memory_rw_debug(env, bp->pc, &int3, 1, 0) || int3 != 0xcc || | |
b9bec74b | 1562 | cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&bp->saved_insn, 1, 1)) { |
e22a25c9 | 1563 | return -EINVAL; |
b9bec74b | 1564 | } |
e22a25c9 AL |
1565 | return 0; |
1566 | } | |
1567 | ||
1568 | static struct { | |
1569 | target_ulong addr; | |
1570 | int len; | |
1571 | int type; | |
1572 | } hw_breakpoint[4]; | |
1573 | ||
1574 | static int nb_hw_breakpoint; | |
1575 | ||
1576 | static int find_hw_breakpoint(target_ulong addr, int len, int type) | |
1577 | { | |
1578 | int n; | |
1579 | ||
b9bec74b | 1580 | for (n = 0; n < nb_hw_breakpoint; n++) { |
e22a25c9 | 1581 | if (hw_breakpoint[n].addr == addr && hw_breakpoint[n].type == type && |
b9bec74b | 1582 | (hw_breakpoint[n].len == len || len == -1)) { |
e22a25c9 | 1583 | return n; |
b9bec74b JK |
1584 | } |
1585 | } | |
e22a25c9 AL |
1586 | return -1; |
1587 | } | |
1588 | ||
1589 | int kvm_arch_insert_hw_breakpoint(target_ulong addr, | |
1590 | target_ulong len, int type) | |
1591 | { | |
1592 | switch (type) { | |
1593 | case GDB_BREAKPOINT_HW: | |
1594 | len = 1; | |
1595 | break; | |
1596 | case GDB_WATCHPOINT_WRITE: | |
1597 | case GDB_WATCHPOINT_ACCESS: | |
1598 | switch (len) { | |
1599 | case 1: | |
1600 | break; | |
1601 | case 2: | |
1602 | case 4: | |
1603 | case 8: | |
b9bec74b | 1604 | if (addr & (len - 1)) { |
e22a25c9 | 1605 | return -EINVAL; |
b9bec74b | 1606 | } |
e22a25c9 AL |
1607 | break; |
1608 | default: | |
1609 | return -EINVAL; | |
1610 | } | |
1611 | break; | |
1612 | default: | |
1613 | return -ENOSYS; | |
1614 | } | |
1615 | ||
b9bec74b | 1616 | if (nb_hw_breakpoint == 4) { |
e22a25c9 | 1617 | return -ENOBUFS; |
b9bec74b JK |
1618 | } |
1619 | if (find_hw_breakpoint(addr, len, type) >= 0) { | |
e22a25c9 | 1620 | return -EEXIST; |
b9bec74b | 1621 | } |
e22a25c9 AL |
1622 | hw_breakpoint[nb_hw_breakpoint].addr = addr; |
1623 | hw_breakpoint[nb_hw_breakpoint].len = len; | |
1624 | hw_breakpoint[nb_hw_breakpoint].type = type; | |
1625 | nb_hw_breakpoint++; | |
1626 | ||
1627 | return 0; | |
1628 | } | |
1629 | ||
1630 | int kvm_arch_remove_hw_breakpoint(target_ulong addr, | |
1631 | target_ulong len, int type) | |
1632 | { | |
1633 | int n; | |
1634 | ||
1635 | n = find_hw_breakpoint(addr, (type == GDB_BREAKPOINT_HW) ? 1 : len, type); | |
b9bec74b | 1636 | if (n < 0) { |
e22a25c9 | 1637 | return -ENOENT; |
b9bec74b | 1638 | } |
e22a25c9 AL |
1639 | nb_hw_breakpoint--; |
1640 | hw_breakpoint[n] = hw_breakpoint[nb_hw_breakpoint]; | |
1641 | ||
1642 | return 0; | |
1643 | } | |
1644 | ||
1645 | void kvm_arch_remove_all_hw_breakpoints(void) | |
1646 | { | |
1647 | nb_hw_breakpoint = 0; | |
1648 | } | |
1649 | ||
1650 | static CPUWatchpoint hw_watchpoint; | |
1651 | ||
1652 | int kvm_arch_debug(struct kvm_debug_exit_arch *arch_info) | |
1653 | { | |
1654 | int handle = 0; | |
1655 | int n; | |
1656 | ||
1657 | if (arch_info->exception == 1) { | |
1658 | if (arch_info->dr6 & (1 << 14)) { | |
b9bec74b | 1659 | if (cpu_single_env->singlestep_enabled) { |
e22a25c9 | 1660 | handle = 1; |
b9bec74b | 1661 | } |
e22a25c9 | 1662 | } else { |
b9bec74b JK |
1663 | for (n = 0; n < 4; n++) { |
1664 | if (arch_info->dr6 & (1 << n)) { | |
e22a25c9 AL |
1665 | switch ((arch_info->dr7 >> (16 + n*4)) & 0x3) { |
1666 | case 0x0: | |
1667 | handle = 1; | |
1668 | break; | |
1669 | case 0x1: | |
1670 | handle = 1; | |
1671 | cpu_single_env->watchpoint_hit = &hw_watchpoint; | |
1672 | hw_watchpoint.vaddr = hw_breakpoint[n].addr; | |
1673 | hw_watchpoint.flags = BP_MEM_WRITE; | |
1674 | break; | |
1675 | case 0x3: | |
1676 | handle = 1; | |
1677 | cpu_single_env->watchpoint_hit = &hw_watchpoint; | |
1678 | hw_watchpoint.vaddr = hw_breakpoint[n].addr; | |
1679 | hw_watchpoint.flags = BP_MEM_ACCESS; | |
1680 | break; | |
1681 | } | |
b9bec74b JK |
1682 | } |
1683 | } | |
e22a25c9 | 1684 | } |
b9bec74b | 1685 | } else if (kvm_find_sw_breakpoint(cpu_single_env, arch_info->pc)) { |
e22a25c9 | 1686 | handle = 1; |
b9bec74b | 1687 | } |
b0b1d690 JK |
1688 | if (!handle) { |
1689 | cpu_synchronize_state(cpu_single_env); | |
1690 | assert(cpu_single_env->exception_injected == -1); | |
1691 | ||
1692 | cpu_single_env->exception_injected = arch_info->exception; | |
1693 | cpu_single_env->has_error_code = 0; | |
1694 | } | |
e22a25c9 AL |
1695 | |
1696 | return handle; | |
1697 | } | |
1698 | ||
1699 | void kvm_arch_update_guest_debug(CPUState *env, struct kvm_guest_debug *dbg) | |
1700 | { | |
1701 | const uint8_t type_code[] = { | |
1702 | [GDB_BREAKPOINT_HW] = 0x0, | |
1703 | [GDB_WATCHPOINT_WRITE] = 0x1, | |
1704 | [GDB_WATCHPOINT_ACCESS] = 0x3 | |
1705 | }; | |
1706 | const uint8_t len_code[] = { | |
1707 | [1] = 0x0, [2] = 0x1, [4] = 0x3, [8] = 0x2 | |
1708 | }; | |
1709 | int n; | |
1710 | ||
b9bec74b | 1711 | if (kvm_sw_breakpoints_active(env)) { |
e22a25c9 | 1712 | dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP; |
b9bec74b | 1713 | } |
e22a25c9 AL |
1714 | if (nb_hw_breakpoint > 0) { |
1715 | dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP; | |
1716 | dbg->arch.debugreg[7] = 0x0600; | |
1717 | for (n = 0; n < nb_hw_breakpoint; n++) { | |
1718 | dbg->arch.debugreg[n] = hw_breakpoint[n].addr; | |
1719 | dbg->arch.debugreg[7] |= (2 << (n * 2)) | | |
1720 | (type_code[hw_breakpoint[n].type] << (16 + n*4)) | | |
95c077c9 | 1721 | ((uint32_t)len_code[hw_breakpoint[n].len] << (18 + n*4)); |
e22a25c9 AL |
1722 | } |
1723 | } | |
f1665b21 SY |
1724 | /* Legal xcr0 for loading */ |
1725 | env->xcr0 = 1; | |
e22a25c9 AL |
1726 | } |
1727 | #endif /* KVM_CAP_SET_GUEST_DEBUG */ | |
4513d923 GN |
1728 | |
1729 | bool kvm_arch_stop_on_emulation_error(CPUState *env) | |
1730 | { | |
b9bec74b JK |
1731 | return !(env->cr[0] & CR0_PE_MASK) || |
1732 | ((env->segs[R_CS].selector & 3) != 3); | |
4513d923 GN |
1733 | } |
1734 | ||
c0532a76 MT |
1735 | static void hardware_memory_error(void) |
1736 | { | |
1737 | fprintf(stderr, "Hardware memory error!\n"); | |
1738 | exit(1); | |
1739 | } | |
1740 | ||
f71ac88f HS |
1741 | #ifdef KVM_CAP_MCE |
1742 | static void kvm_mce_broadcast_rest(CPUState *env) | |
1743 | { | |
7cc2cc3e JD |
1744 | struct kvm_x86_mce mce = { |
1745 | .bank = 1, | |
1746 | .status = MCI_STATUS_VAL | MCI_STATUS_UC, | |
1747 | .mcg_status = MCG_STATUS_MCIP | MCG_STATUS_RIPV, | |
1748 | .addr = 0, | |
1749 | .misc = 0, | |
1750 | }; | |
f71ac88f | 1751 | CPUState *cenv; |
f71ac88f HS |
1752 | |
1753 | /* Broadcast MCA signal for processor version 06H_EH and above */ | |
2bd3e04c | 1754 | if (cpu_x86_support_mca_broadcast(env)) { |
f71ac88f HS |
1755 | for (cenv = first_cpu; cenv != NULL; cenv = cenv->next_cpu) { |
1756 | if (cenv == env) { | |
1757 | continue; | |
1758 | } | |
7cc2cc3e | 1759 | kvm_inject_x86_mce_on(cenv, &mce, ABORT_ON_ERROR); |
f71ac88f HS |
1760 | } |
1761 | } | |
1762 | } | |
e387c338 JD |
1763 | |
1764 | static void kvm_mce_inj_srar_dataload(CPUState *env, target_phys_addr_t paddr) | |
1765 | { | |
1766 | struct kvm_x86_mce mce = { | |
1767 | .bank = 9, | |
1768 | .status = MCI_STATUS_VAL | MCI_STATUS_UC | MCI_STATUS_EN | |
1769 | | MCI_STATUS_MISCV | MCI_STATUS_ADDRV | MCI_STATUS_S | |
1770 | | MCI_STATUS_AR | 0x134, | |
1771 | .mcg_status = MCG_STATUS_MCIP | MCG_STATUS_EIPV, | |
1772 | .addr = paddr, | |
1773 | .misc = (MCM_ADDR_PHYS << 6) | 0xc, | |
1774 | }; | |
1775 | int r; | |
1776 | ||
1777 | r = kvm_set_mce(env, &mce); | |
1778 | if (r < 0) { | |
1779 | fprintf(stderr, "kvm_set_mce: %s\n", strerror(errno)); | |
1780 | abort(); | |
1781 | } | |
1782 | kvm_mce_broadcast_rest(env); | |
1783 | } | |
1784 | ||
1785 | static void kvm_mce_inj_srao_memscrub(CPUState *env, target_phys_addr_t paddr) | |
1786 | { | |
1787 | struct kvm_x86_mce mce = { | |
1788 | .bank = 9, | |
1789 | .status = MCI_STATUS_VAL | MCI_STATUS_UC | MCI_STATUS_EN | |
1790 | | MCI_STATUS_MISCV | MCI_STATUS_ADDRV | MCI_STATUS_S | |
1791 | | 0xc0, | |
1792 | .mcg_status = MCG_STATUS_MCIP | MCG_STATUS_RIPV, | |
1793 | .addr = paddr, | |
1794 | .misc = (MCM_ADDR_PHYS << 6) | 0xc, | |
1795 | }; | |
1796 | int r; | |
1797 | ||
1798 | r = kvm_set_mce(env, &mce); | |
1799 | if (r < 0) { | |
1800 | fprintf(stderr, "kvm_set_mce: %s\n", strerror(errno)); | |
1801 | abort(); | |
1802 | } | |
1803 | kvm_mce_broadcast_rest(env); | |
1804 | } | |
1805 | ||
1806 | static void kvm_mce_inj_srao_memscrub2(CPUState *env, target_phys_addr_t paddr) | |
1807 | { | |
7cc2cc3e JD |
1808 | struct kvm_x86_mce mce = { |
1809 | .bank = 9, | |
1810 | .status = MCI_STATUS_VAL | MCI_STATUS_UC | MCI_STATUS_EN | |
1811 | | MCI_STATUS_MISCV | MCI_STATUS_ADDRV | MCI_STATUS_S | |
1812 | | 0xc0, | |
1813 | .mcg_status = MCG_STATUS_MCIP | MCG_STATUS_RIPV, | |
1814 | .addr = paddr, | |
1815 | .misc = (MCM_ADDR_PHYS << 6) | 0xc, | |
1816 | }; | |
e387c338 | 1817 | |
7cc2cc3e | 1818 | kvm_inject_x86_mce_on(env, &mce, ABORT_ON_ERROR); |
e387c338 JD |
1819 | kvm_mce_broadcast_rest(env); |
1820 | } | |
1821 | ||
f71ac88f HS |
1822 | #endif |
1823 | ||
c0532a76 MT |
1824 | int kvm_on_sigbus_vcpu(CPUState *env, int code, void *addr) |
1825 | { | |
1826 | #if defined(KVM_CAP_MCE) | |
c0532a76 MT |
1827 | void *vaddr; |
1828 | ram_addr_t ram_addr; | |
1829 | target_phys_addr_t paddr; | |
c0532a76 MT |
1830 | |
1831 | if ((env->mcg_cap & MCG_SER_P) && addr | |
1832 | && (code == BUS_MCEERR_AR | |
1833 | || code == BUS_MCEERR_AO)) { | |
c0532a76 MT |
1834 | vaddr = (void *)addr; |
1835 | if (qemu_ram_addr_from_host(vaddr, &ram_addr) || | |
1836 | !kvm_physical_memory_addr_from_ram(env->kvm_state, ram_addr, &paddr)) { | |
1837 | fprintf(stderr, "Hardware memory error for memory used by " | |
1838 | "QEMU itself instead of guest system!\n"); | |
1839 | /* Hope we are lucky for AO MCE */ | |
1840 | if (code == BUS_MCEERR_AO) { | |
1841 | return 0; | |
1842 | } else { | |
1843 | hardware_memory_error(); | |
1844 | } | |
1845 | } | |
e387c338 JD |
1846 | |
1847 | if (code == BUS_MCEERR_AR) { | |
1848 | /* Fake an Intel architectural Data Load SRAR UCR */ | |
1849 | kvm_mce_inj_srar_dataload(env, paddr); | |
1850 | } else { | |
1851 | /* | |
1852 | * If there is an MCE excpetion being processed, ignore | |
1853 | * this SRAO MCE | |
1854 | */ | |
1855 | if (!kvm_mce_in_progress(env)) { | |
1856 | /* Fake an Intel architectural Memory scrubbing UCR */ | |
1857 | kvm_mce_inj_srao_memscrub(env, paddr); | |
1858 | } | |
c0532a76 MT |
1859 | } |
1860 | } else | |
1861 | #endif | |
1862 | { | |
1863 | if (code == BUS_MCEERR_AO) { | |
1864 | return 0; | |
1865 | } else if (code == BUS_MCEERR_AR) { | |
1866 | hardware_memory_error(); | |
1867 | } else { | |
1868 | return 1; | |
1869 | } | |
1870 | } | |
1871 | return 0; | |
1872 | } | |
1873 | ||
1874 | int kvm_on_sigbus(int code, void *addr) | |
1875 | { | |
1876 | #if defined(KVM_CAP_MCE) | |
1877 | if ((first_cpu->mcg_cap & MCG_SER_P) && addr && code == BUS_MCEERR_AO) { | |
c0532a76 MT |
1878 | void *vaddr; |
1879 | ram_addr_t ram_addr; | |
1880 | target_phys_addr_t paddr; | |
c0532a76 MT |
1881 | |
1882 | /* Hope we are lucky for AO MCE */ | |
1883 | vaddr = addr; | |
1884 | if (qemu_ram_addr_from_host(vaddr, &ram_addr) || | |
1885 | !kvm_physical_memory_addr_from_ram(first_cpu->kvm_state, ram_addr, &paddr)) { | |
1886 | fprintf(stderr, "Hardware memory error for memory used by " | |
1887 | "QEMU itself instead of guest system!: %p\n", addr); | |
1888 | return 0; | |
1889 | } | |
e387c338 | 1890 | kvm_mce_inj_srao_memscrub2(first_cpu, paddr); |
c0532a76 MT |
1891 | } else |
1892 | #endif | |
1893 | { | |
1894 | if (code == BUS_MCEERR_AO) { | |
1895 | return 0; | |
1896 | } else if (code == BUS_MCEERR_AR) { | |
1897 | hardware_memory_error(); | |
1898 | } else { | |
1899 | return 1; | |
1900 | } | |
1901 | } | |
1902 | return 0; | |
1903 | } |