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05330448
AL		 1/*
2 * QEMU KVM support
3 *
4 * Copyright (C) 2006-2008 Qumranet Technologies
5 * Copyright IBM, Corp. 2008
6 *
7 * Authors:
8 * Anthony Liguori <aliguori@us.ibm.com>
9 *
10 * This work is licensed under the terms of the GNU GPL, version 2 or later.
11 * See the COPYING file in the top-level directory.
12 *
13 */
14
15#include <sys/types.h>
16#include <sys/ioctl.h>
17#include <sys/mman.h>
18
19#include <linux/kvm.h>
20
21#include "qemu-common.h"
22#include "sysemu.h"
23#include "kvm.h"
24#include "cpu.h"
e22a25c9 25#include "gdbstub.h"
0e607a80 26#include "host-utils.h"
4c5b10b7 27#include "hw/pc.h"
408392b3 28#include "hw/apic.h"
35bed8ee 29#include "ioport.h"
05330448 30
bb0300dc
GN		 31#ifdef CONFIG_KVM_PARA
32#include <linux/kvm_para.h>
33#endif
34//
05330448
AL		 35//#define DEBUG_KVM
36
37#ifdef DEBUG_KVM
8c0d577e 38#define DPRINTF(fmt, ...) \
05330448
AL		 39 do { fprintf(stderr, fmt, ## __VA_ARGS__); } while (0)
40#else
8c0d577e 41#define DPRINTF(fmt, ...) \
05330448
AL		 42 do { } while (0)
43#endif
44
1a03675d
GC		 45#define MSR_KVM_WALL_CLOCK 0x11
46#define MSR_KVM_SYSTEM_TIME 0x12
47
b827df58
AK		 48#ifdef KVM_CAP_EXT_CPUID
49
50static struct kvm_cpuid2 *try_get_cpuid(KVMState *s, int max)
51{
52 struct kvm_cpuid2 *cpuid;
53 int r, size;
54
55 size = sizeof(*cpuid) + max * sizeof(*cpuid->entries);
56 cpuid = (struct kvm_cpuid2 *)qemu_mallocz(size);
57 cpuid->nent = max;
58 r = kvm_ioctl(s, KVM_GET_SUPPORTED_CPUID, cpuid);
76ae317f
MM		 59 if (r == 0 && cpuid->nent >= max) {
60 r = -E2BIG;
61 }
b827df58
AK		 62 if (r < 0) {
63 if (r == -E2BIG) {
64 qemu_free(cpuid);
65 return NULL;
66 } else {
67 fprintf(stderr, "KVM_GET_SUPPORTED_CPUID failed: %s\n",
68 strerror(-r));
69 exit(1);
70 }
71 }
72 return cpuid;
73}
74
c958a8bd
SY		 75uint32_t kvm_arch_get_supported_cpuid(CPUState *env, uint32_t function,
76 uint32_t index, int reg)
b827df58
AK		 77{
78 struct kvm_cpuid2 *cpuid;
79 int i, max;
80 uint32_t ret = 0;
81 uint32_t cpuid_1_edx;
82
83 if (!kvm_check_extension(env->kvm_state, KVM_CAP_EXT_CPUID)) {
84 return -1U;
85 }
86
87 max = 1;
88 while ((cpuid = try_get_cpuid(env->kvm_state, max)) == NULL) {
89 max *= 2;
90 }
91
92 for (i = 0; i < cpuid->nent; ++i) {
c958a8bd
SY		 93 if (cpuid->entries[i].function == function &&
94 cpuid->entries[i].index == index) {
b827df58
AK		 95 switch (reg) {
96 case R_EAX:
97 ret = cpuid->entries[i].eax;
98 break;
99 case R_EBX:
100 ret = cpuid->entries[i].ebx;
101 break;
102 case R_ECX:
103 ret = cpuid->entries[i].ecx;
104 break;
105 case R_EDX:
106 ret = cpuid->entries[i].edx;
19ccb8ea
JK		 107 switch (function) {
108 case 1:
109 /* KVM before 2.6.30 misreports the following features */
110 ret |= CPUID_MTRR | CPUID_PAT | CPUID_MCE | CPUID_MCA;
111 break;
112 case 0x80000001:
b827df58
AK		 113 /* On Intel, kvm returns cpuid according to the Intel spec,
114 * so add missing bits according to the AMD spec:
115 */
c958a8bd 116 cpuid_1_edx = kvm_arch_get_supported_cpuid(env, 1, 0, R_EDX);
c1667e40 117 ret |= cpuid_1_edx & 0x183f7ff;
19ccb8ea 118 break;
b827df58
AK		 119 }
120 break;
121 }
122 }
123 }
124
125 qemu_free(cpuid);
126
127 return ret;
128}
129
130#else
131
c958a8bd
SY		 132uint32_t kvm_arch_get_supported_cpuid(CPUState *env, uint32_t function,
133 uint32_t index, int reg)
b827df58
AK		 134{
135 return -1U;
136}
137
138#endif
139
bb0300dc
GN		 140#ifdef CONFIG_KVM_PARA
141struct kvm_para_features {
142 int cap;
143 int feature;
144} para_features[] = {
145#ifdef KVM_CAP_CLOCKSOURCE
146 { KVM_CAP_CLOCKSOURCE, KVM_FEATURE_CLOCKSOURCE },
147#endif
148#ifdef KVM_CAP_NOP_IO_DELAY
149 { KVM_CAP_NOP_IO_DELAY, KVM_FEATURE_NOP_IO_DELAY },
150#endif
151#ifdef KVM_CAP_PV_MMU
152 { KVM_CAP_PV_MMU, KVM_FEATURE_MMU_OP },
bb0300dc
GN		 153#endif
154 { -1, -1 }
155};
156
157static int get_para_features(CPUState *env)
158{
159 int i, features = 0;
160
161 for (i = 0; i < ARRAY_SIZE(para_features) - 1; i++) {
162 if (kvm_check_extension(env->kvm_state, para_features[i].cap))
163 features |= (1 << para_features[i].feature);
164 }
165
166 return features;
167}
168#endif
169
05330448
AL		 170int kvm_arch_init_vcpu(CPUState *env)
171{
172 struct {
486bd5a2
AL		 173 struct kvm_cpuid2 cpuid;
174 struct kvm_cpuid_entry2 entries[100];
05330448 175 } __attribute__((packed)) cpuid_data;
486bd5a2 176 uint32_t limit, i, j, cpuid_i;
a33609ca 177 uint32_t unused;
bb0300dc
GN		 178 struct kvm_cpuid_entry2 *c;
179#ifdef KVM_CPUID_SIGNATURE
180 uint32_t signature[3];
181#endif
05330448 182
f8d926e9
JK		 183 env->mp_state = KVM_MP_STATE_RUNNABLE;
184
c958a8bd 185 env->cpuid_features &= kvm_arch_get_supported_cpuid(env, 1, 0, R_EDX);
6c0d7ee8
AP		 186
187 i = env->cpuid_ext_features & CPUID_EXT_HYPERVISOR;
c958a8bd 188 env->cpuid_ext_features &= kvm_arch_get_supported_cpuid(env, 1, 0, R_ECX);
6c0d7ee8
AP		 189 env->cpuid_ext_features |= i;
190
457dfed6 191 env->cpuid_ext2_features &= kvm_arch_get_supported_cpuid(env, 0x80000001,
c958a8bd 192 0, R_EDX);
457dfed6 193 env->cpuid_ext3_features &= kvm_arch_get_supported_cpuid(env, 0x80000001,
c958a8bd 194 0, R_ECX);
296acb64
JR		 195 env->cpuid_svm_features &= kvm_arch_get_supported_cpuid(env, 0x8000000A,
196 0, R_EDX);
197
6c1f42fe 198
05330448
AL		 199 cpuid_i = 0;
200
bb0300dc
GN		 201#ifdef CONFIG_KVM_PARA
202 /* Paravirtualization CPUIDs */
203 memcpy(signature, "KVMKVMKVM\0\0\0", 12);
204 c = &cpuid_data.entries[cpuid_i++];
205 memset(c, 0, sizeof(*c));
206 c->function = KVM_CPUID_SIGNATURE;
207 c->eax = 0;
208 c->ebx = signature[0];
209 c->ecx = signature[1];
210 c->edx = signature[2];
211
212 c = &cpuid_data.entries[cpuid_i++];
213 memset(c, 0, sizeof(*c));
214 c->function = KVM_CPUID_FEATURES;
215 c->eax = env->cpuid_kvm_features & get_para_features(env);
216#endif
217
a33609ca 218 cpu_x86_cpuid(env, 0, 0, &limit, &unused, &unused, &unused);
05330448
AL		 219
220 for (i = 0; i <= limit; i++) {
bb0300dc 221 c = &cpuid_data.entries[cpuid_i++];
486bd5a2
AL		 222
223 switch (i) {
a36b1029
AL		 224 case 2: {
225 /* Keep reading function 2 till all the input is received */
226 int times;
227
a36b1029 228 c->function = i;
a33609ca
AL		 229 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC |
230 KVM_CPUID_FLAG_STATE_READ_NEXT;
231 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
232 times = c->eax & 0xff;
a36b1029
AL		 233
234 for (j = 1; j < times; ++j) {
a33609ca 235 c = &cpuid_data.entries[cpuid_i++];
a36b1029 236 c->function = i;
a33609ca
AL		 237 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC;
238 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
a36b1029
AL		 239 }
240 break;
241 }
486bd5a2
AL		 242 case 4:
243 case 0xb:
244 case 0xd:
245 for (j = 0; ; j++) {
486bd5a2
AL		 246 c->function = i;
247 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
248 c->index = j;
a33609ca 249 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
486bd5a2 250
a33609ca 251 if (i == 4 && c->eax == 0)
486bd5a2 252 break;
a33609ca 253 if (i == 0xb && !(c->ecx & 0xff00))
486bd5a2 254 break;
a33609ca 255 if (i == 0xd && c->eax == 0)
486bd5a2 256 break;
a33609ca
AL		 257
258 c = &cpuid_data.entries[cpuid_i++];
486bd5a2
AL		 259 }
260 break;
261 default:
486bd5a2 262 c->function = i;
a33609ca
AL		 263 c->flags = 0;
264 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
486bd5a2
AL		 265 break;
266 }
05330448 267 }
a33609ca 268 cpu_x86_cpuid(env, 0x80000000, 0, &limit, &unused, &unused, &unused);
05330448
AL		 269
270 for (i = 0x80000000; i <= limit; i++) {
bb0300dc 271 c = &cpuid_data.entries[cpuid_i++];
05330448 272
05330448 273 c->function = i;
a33609ca
AL		 274 c->flags = 0;
275 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
05330448
AL		 276 }
277
278 cpuid_data.cpuid.nent = cpuid_i;
279
486bd5a2 280 return kvm_vcpu_ioctl(env, KVM_SET_CPUID2, &cpuid_data);
05330448
AL		 281}
282
caa5af0f
JK		 283void kvm_arch_reset_vcpu(CPUState *env)
284{
e73223a5 285 env->exception_injected = -1;
0e607a80 286 env->interrupt_injected = -1;
a0fb002c
JK		 287 env->nmi_injected = 0;
288 env->nmi_pending = 0;
ddced198
MT		 289 if (kvm_irqchip_in_kernel()) {
290 env->mp_state = cpu_is_bsp(env) ? KVM_MP_STATE_RUNNABLE :
291 KVM_MP_STATE_UNINITIALIZED;
292 } else {
293 env->mp_state = KVM_MP_STATE_RUNNABLE;
294 }
caa5af0f
JK		 295}
296
05330448
AL		 297static int kvm_has_msr_star(CPUState *env)
298{
299 static int has_msr_star;
300 int ret;
301
302 /* first time */
303 if (has_msr_star == 0) {
304 struct kvm_msr_list msr_list, *kvm_msr_list;
305
306 has_msr_star = -1;
307
308 /* Obtain MSR list from KVM. These are the MSRs that we must
309 * save/restore */
4c9f7372 310 msr_list.nmsrs = 0;
05330448 311 ret = kvm_ioctl(env->kvm_state, KVM_GET_MSR_INDEX_LIST, &msr_list);
6fb6d245 312 if (ret < 0 && ret != -E2BIG) {
05330448 313 return 0;
6fb6d245 314 }
d9db889f
JK		 315 /* Old kernel modules had a bug and could write beyond the provided
316 memory. Allocate at least a safe amount of 1K. */
317 kvm_msr_list = qemu_mallocz(MAX(1024, sizeof(msr_list) +
318 msr_list.nmsrs *
319 sizeof(msr_list.indices[0])));
05330448 320
55308450 321 kvm_msr_list->nmsrs = msr_list.nmsrs;
05330448
AL		 322 ret = kvm_ioctl(env->kvm_state, KVM_GET_MSR_INDEX_LIST, kvm_msr_list);
323 if (ret >= 0) {
324 int i;
325
326 for (i = 0; i < kvm_msr_list->nmsrs; i++) {
327 if (kvm_msr_list->indices[i] == MSR_STAR) {
328 has_msr_star = 1;
329 break;
330 }
331 }
332 }
333
334 free(kvm_msr_list);
335 }
336
337 if (has_msr_star == 1)
338 return 1;
339 return 0;
340}
341
20420430
SY		 342static int kvm_init_identity_map_page(KVMState *s)
343{
344#ifdef KVM_CAP_SET_IDENTITY_MAP_ADDR
345 int ret;
346 uint64_t addr = 0xfffbc000;
347
348 if (!kvm_check_extension(s, KVM_CAP_SET_IDENTITY_MAP_ADDR)) {
349 return 0;
350 }
351
352 ret = kvm_vm_ioctl(s, KVM_SET_IDENTITY_MAP_ADDR, &addr);
353 if (ret < 0) {
354 fprintf(stderr, "kvm_set_identity_map_addr: %s\n", strerror(ret));
355 return ret;
356 }
357#endif
358 return 0;
359}
360
05330448
AL		 361int kvm_arch_init(KVMState *s, int smp_cpus)
362{
363 int ret;
364
365 /* create vm86 tss. KVM uses vm86 mode to emulate 16-bit code
366 * directly. In order to use vm86 mode, a TSS is needed. Since this
367 * must be part of guest physical memory, we need to allocate it. Older
368 * versions of KVM just assumed that it would be at the end of physical
369 * memory but that doesn't work with more than 4GB of memory. We simply
370 * refuse to work with those older versions of KVM. */
984b5181 371 ret = kvm_ioctl(s, KVM_CHECK_EXTENSION, KVM_CAP_SET_TSS_ADDR);
05330448
AL		 372 if (ret <= 0) {
373 fprintf(stderr, "kvm does not support KVM_CAP_SET_TSS_ADDR\n");
374 return ret;
375 }
376
377 /* this address is 3 pages before the bios, and the bios should present
378 * as unavaible memory. FIXME, need to ensure the e820 map deals with
379 * this?
380 */
4c5b10b7
JS		 381 /*
382 * Tell fw_cfg to notify the BIOS to reserve the range.
383 */
384 if (e820_add_entry(0xfffbc000, 0x4000, E820_RESERVED) < 0) {
385 perror("e820_add_entry() table is full");
386 exit(1);
387 }
20420430
SY		 388 ret = kvm_vm_ioctl(s, KVM_SET_TSS_ADDR, 0xfffbd000);
389 if (ret < 0) {
390 return ret;
391 }
392
393 return kvm_init_identity_map_page(s);
05330448
AL		 394}
395
396static void set_v8086_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
397{
398 lhs->selector = rhs->selector;
399 lhs->base = rhs->base;
400 lhs->limit = rhs->limit;
401 lhs->type = 3;
402 lhs->present = 1;
403 lhs->dpl = 3;
404 lhs->db = 0;
405 lhs->s = 1;
406 lhs->l = 0;
407 lhs->g = 0;
408 lhs->avl = 0;
409 lhs->unusable = 0;
410}
411
412static void set_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
413{
414 unsigned flags = rhs->flags;
415 lhs->selector = rhs->selector;
416 lhs->base = rhs->base;
417 lhs->limit = rhs->limit;
418 lhs->type = (flags >> DESC_TYPE_SHIFT) & 15;
419 lhs->present = (flags & DESC_P_MASK) != 0;
420 lhs->dpl = rhs->selector & 3;
421 lhs->db = (flags >> DESC_B_SHIFT) & 1;
422 lhs->s = (flags & DESC_S_MASK) != 0;
423 lhs->l = (flags >> DESC_L_SHIFT) & 1;
424 lhs->g = (flags & DESC_G_MASK) != 0;
425 lhs->avl = (flags & DESC_AVL_MASK) != 0;
426 lhs->unusable = 0;
427}
428
429static void get_seg(SegmentCache *lhs, const struct kvm_segment *rhs)
430{
431 lhs->selector = rhs->selector;
432 lhs->base = rhs->base;
433 lhs->limit = rhs->limit;
434 lhs->flags =
435 (rhs->type << DESC_TYPE_SHIFT)
436 | (rhs->present * DESC_P_MASK)
437 | (rhs->dpl << DESC_DPL_SHIFT)
438 | (rhs->db << DESC_B_SHIFT)
439 | (rhs->s * DESC_S_MASK)
440 | (rhs->l << DESC_L_SHIFT)
441 | (rhs->g * DESC_G_MASK)
442 | (rhs->avl * DESC_AVL_MASK);
443}
444
445static void kvm_getput_reg(__u64 *kvm_reg, target_ulong *qemu_reg, int set)
446{
447 if (set)
448 *kvm_reg = *qemu_reg;
449 else
450 *qemu_reg = *kvm_reg;
451}
452
453static int kvm_getput_regs(CPUState *env, int set)
454{
455 struct kvm_regs regs;
456 int ret = 0;
457
458 if (!set) {
459 ret = kvm_vcpu_ioctl(env, KVM_GET_REGS, &regs);
460 if (ret < 0)
461 return ret;
462 }
463
464 kvm_getput_reg(&regs.rax, &env->regs[R_EAX], set);
465 kvm_getput_reg(&regs.rbx, &env->regs[R_EBX], set);
466 kvm_getput_reg(&regs.rcx, &env->regs[R_ECX], set);
467 kvm_getput_reg(&regs.rdx, &env->regs[R_EDX], set);
468 kvm_getput_reg(&regs.rsi, &env->regs[R_ESI], set);
469 kvm_getput_reg(&regs.rdi, &env->regs[R_EDI], set);
470 kvm_getput_reg(&regs.rsp, &env->regs[R_ESP], set);
471 kvm_getput_reg(&regs.rbp, &env->regs[R_EBP], set);
472#ifdef TARGET_X86_64
473 kvm_getput_reg(&regs.r8, &env->regs[8], set);
474 kvm_getput_reg(&regs.r9, &env->regs[9], set);
475 kvm_getput_reg(&regs.r10, &env->regs[10], set);
476 kvm_getput_reg(&regs.r11, &env->regs[11], set);
477 kvm_getput_reg(&regs.r12, &env->regs[12], set);
478 kvm_getput_reg(&regs.r13, &env->regs[13], set);
479 kvm_getput_reg(&regs.r14, &env->regs[14], set);
480 kvm_getput_reg(&regs.r15, &env->regs[15], set);
481#endif
482
483 kvm_getput_reg(&regs.rflags, &env->eflags, set);
484 kvm_getput_reg(&regs.rip, &env->eip, set);
485
486 if (set)
487 ret = kvm_vcpu_ioctl(env, KVM_SET_REGS, &regs);
488
489 return ret;
490}
491
492static int kvm_put_fpu(CPUState *env)
493{
494 struct kvm_fpu fpu;
495 int i;
496
497 memset(&fpu, 0, sizeof fpu);
498 fpu.fsw = env->fpus & ~(7 << 11);
499 fpu.fsw |= (env->fpstt & 7) << 11;
500 fpu.fcw = env->fpuc;
501 for (i = 0; i < 8; ++i)
502 fpu.ftwx |= (!env->fptags[i]) << i;
503 memcpy(fpu.fpr, env->fpregs, sizeof env->fpregs);
504 memcpy(fpu.xmm, env->xmm_regs, sizeof env->xmm_regs);
505 fpu.mxcsr = env->mxcsr;
506
507 return kvm_vcpu_ioctl(env, KVM_SET_FPU, &fpu);
508}
509
f1665b21
SY		 510#ifdef KVM_CAP_XSAVE
511#define XSAVE_CWD_RIP 2
512#define XSAVE_CWD_RDP 4
513#define XSAVE_MXCSR 6
514#define XSAVE_ST_SPACE 8
515#define XSAVE_XMM_SPACE 40
516#define XSAVE_XSTATE_BV 128
517#define XSAVE_YMMH_SPACE 144
518#endif
519
520static int kvm_put_xsave(CPUState *env)
521{
522#ifdef KVM_CAP_XSAVE
523 int i;
524 struct kvm_xsave* xsave;
525 uint16_t cwd, swd, twd, fop;
526
527 if (!kvm_has_xsave())
528 return kvm_put_fpu(env);
529
530 xsave = qemu_memalign(4096, sizeof(struct kvm_xsave));
531 memset(xsave, 0, sizeof(struct kvm_xsave));
532 cwd = swd = twd = fop = 0;
533 swd = env->fpus & ~(7 << 11);
534 swd |= (env->fpstt & 7) << 11;
535 cwd = env->fpuc;
536 for (i = 0; i < 8; ++i)
537 twd |= (!env->fptags[i]) << i;
538 xsave->region[0] = (uint32_t)(swd << 16) + cwd;
539 xsave->region[1] = (uint32_t)(fop << 16) + twd;
540 memcpy(&xsave->region[XSAVE_ST_SPACE], env->fpregs,
541 sizeof env->fpregs);
542 memcpy(&xsave->region[XSAVE_XMM_SPACE], env->xmm_regs,
543 sizeof env->xmm_regs);
544 xsave->region[XSAVE_MXCSR] = env->mxcsr;
545 *(uint64_t *)&xsave->region[XSAVE_XSTATE_BV] = env->xstate_bv;
546 memcpy(&xsave->region[XSAVE_YMMH_SPACE], env->ymmh_regs,
547 sizeof env->ymmh_regs);
548 return kvm_vcpu_ioctl(env, KVM_SET_XSAVE, xsave);
549#else
550 return kvm_put_fpu(env);
551#endif
552}
553
554static int kvm_put_xcrs(CPUState *env)
555{
556#ifdef KVM_CAP_XCRS
557 struct kvm_xcrs xcrs;
558
559 if (!kvm_has_xcrs())
560 return 0;
561
562 xcrs.nr_xcrs = 1;
563 xcrs.flags = 0;
564 xcrs.xcrs[0].xcr = 0;
565 xcrs.xcrs[0].value = env->xcr0;
566 return kvm_vcpu_ioctl(env, KVM_SET_XCRS, &xcrs);
567#else
568 return 0;
569#endif
570}
571
05330448
AL		 572static int kvm_put_sregs(CPUState *env)
573{
574 struct kvm_sregs sregs;
575
0e607a80
JK		 576 memset(sregs.interrupt_bitmap, 0, sizeof(sregs.interrupt_bitmap));
577 if (env->interrupt_injected >= 0) {
578 sregs.interrupt_bitmap[env->interrupt_injected / 64] |=
579 (uint64_t)1 << (env->interrupt_injected % 64);
580 }
05330448
AL		 581
582 if ((env->eflags & VM_MASK)) {
583 set_v8086_seg(&sregs.cs, &env->segs[R_CS]);
584 set_v8086_seg(&sregs.ds, &env->segs[R_DS]);
585 set_v8086_seg(&sregs.es, &env->segs[R_ES]);
586 set_v8086_seg(&sregs.fs, &env->segs[R_FS]);
587 set_v8086_seg(&sregs.gs, &env->segs[R_GS]);
588 set_v8086_seg(&sregs.ss, &env->segs[R_SS]);
589 } else {
590 set_seg(&sregs.cs, &env->segs[R_CS]);
591 set_seg(&sregs.ds, &env->segs[R_DS]);
592 set_seg(&sregs.es, &env->segs[R_ES]);
593 set_seg(&sregs.fs, &env->segs[R_FS]);
594 set_seg(&sregs.gs, &env->segs[R_GS]);
595 set_seg(&sregs.ss, &env->segs[R_SS]);
596
597 if (env->cr[0] & CR0_PE_MASK) {
598 /* force ss cpl to cs cpl */
599 sregs.ss.selector = (sregs.ss.selector & ~3) |
600 (sregs.cs.selector & 3);
601 sregs.ss.dpl = sregs.ss.selector & 3;
602 }
603 }
604
605 set_seg(&sregs.tr, &env->tr);
606 set_seg(&sregs.ldt, &env->ldt);
607
608 sregs.idt.limit = env->idt.limit;
609 sregs.idt.base = env->idt.base;
610 sregs.gdt.limit = env->gdt.limit;
611 sregs.gdt.base = env->gdt.base;
612
613 sregs.cr0 = env->cr[0];
614 sregs.cr2 = env->cr[2];
615 sregs.cr3 = env->cr[3];
616 sregs.cr4 = env->cr[4];
617
4a942cea
BS		 618 sregs.cr8 = cpu_get_apic_tpr(env->apic_state);
619 sregs.apic_base = cpu_get_apic_base(env->apic_state);
05330448
AL		 620
621 sregs.efer = env->efer;
622
623 return kvm_vcpu_ioctl(env, KVM_SET_SREGS, &sregs);
624}
625
626static void kvm_msr_entry_set(struct kvm_msr_entry *entry,
627 uint32_t index, uint64_t value)
628{
629 entry->index = index;
630 entry->data = value;
631}
632
ea643051 633static int kvm_put_msrs(CPUState *env, int level)
05330448
AL		 634{
635 struct {
636 struct kvm_msrs info;
637 struct kvm_msr_entry entries[100];
638 } msr_data;
639 struct kvm_msr_entry *msrs = msr_data.entries;
640 int n = 0;
641
642 kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_CS, env->sysenter_cs);
643 kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_ESP, env->sysenter_esp);
644 kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_EIP, env->sysenter_eip);
645 if (kvm_has_msr_star(env))
646 kvm_msr_entry_set(&msrs[n++], MSR_STAR, env->star);
05330448
AL		 647#ifdef TARGET_X86_64
648 /* FIXME if lm capable */
649 kvm_msr_entry_set(&msrs[n++], MSR_CSTAR, env->cstar);
650 kvm_msr_entry_set(&msrs[n++], MSR_KERNELGSBASE, env->kernelgsbase);
651 kvm_msr_entry_set(&msrs[n++], MSR_FMASK, env->fmask);
652 kvm_msr_entry_set(&msrs[n++], MSR_LSTAR, env->lstar);
653#endif
ea643051
JK		 654 if (level == KVM_PUT_FULL_STATE) {
655 kvm_msr_entry_set(&msrs[n++], MSR_IA32_TSC, env->tsc);
656 kvm_msr_entry_set(&msrs[n++], MSR_KVM_SYSTEM_TIME,
657 env->system_time_msr);
658 kvm_msr_entry_set(&msrs[n++], MSR_KVM_WALL_CLOCK, env->wall_clock_msr);
659 }
1a03675d 660
05330448
AL		 661 msr_data.info.nmsrs = n;
662
663 return kvm_vcpu_ioctl(env, KVM_SET_MSRS, &msr_data);
664
665}
666
667
668static int kvm_get_fpu(CPUState *env)
669{
670 struct kvm_fpu fpu;
671 int i, ret;
672
673 ret = kvm_vcpu_ioctl(env, KVM_GET_FPU, &fpu);
674 if (ret < 0)
675 return ret;
676
677 env->fpstt = (fpu.fsw >> 11) & 7;
678 env->fpus = fpu.fsw;
679 env->fpuc = fpu.fcw;
680 for (i = 0; i < 8; ++i)
681 env->fptags[i] = !((fpu.ftwx >> i) & 1);
682 memcpy(env->fpregs, fpu.fpr, sizeof env->fpregs);
683 memcpy(env->xmm_regs, fpu.xmm, sizeof env->xmm_regs);
684 env->mxcsr = fpu.mxcsr;
685
686 return 0;
687}
688
f1665b21
SY		 689static int kvm_get_xsave(CPUState *env)
690{
691#ifdef KVM_CAP_XSAVE
692 struct kvm_xsave* xsave;
693 int ret, i;
694 uint16_t cwd, swd, twd, fop;
695
696 if (!kvm_has_xsave())
697 return kvm_get_fpu(env);
698
699 xsave = qemu_memalign(4096, sizeof(struct kvm_xsave));
700 ret = kvm_vcpu_ioctl(env, KVM_GET_XSAVE, xsave);
701 if (ret < 0)
702 return ret;
703
704 cwd = (uint16_t)xsave->region[0];
705 swd = (uint16_t)(xsave->region[0] >> 16);
706 twd = (uint16_t)xsave->region[1];
707 fop = (uint16_t)(xsave->region[1] >> 16);
708 env->fpstt = (swd >> 11) & 7;
709 env->fpus = swd;
710 env->fpuc = cwd;
711 for (i = 0; i < 8; ++i)
712 env->fptags[i] = !((twd >> i) & 1);
713 env->mxcsr = xsave->region[XSAVE_MXCSR];
714 memcpy(env->fpregs, &xsave->region[XSAVE_ST_SPACE],
715 sizeof env->fpregs);
716 memcpy(env->xmm_regs, &xsave->region[XSAVE_XMM_SPACE],
717 sizeof env->xmm_regs);
718 env->xstate_bv = *(uint64_t *)&xsave->region[XSAVE_XSTATE_BV];
719 memcpy(env->ymmh_regs, &xsave->region[XSAVE_YMMH_SPACE],
720 sizeof env->ymmh_regs);
721 return 0;
722#else
723 return kvm_get_fpu(env);
724#endif
725}
726
727static int kvm_get_xcrs(CPUState *env)
728{
729#ifdef KVM_CAP_XCRS
730 int i, ret;
731 struct kvm_xcrs xcrs;
732
733 if (!kvm_has_xcrs())
734 return 0;
735
736 ret = kvm_vcpu_ioctl(env, KVM_GET_XCRS, &xcrs);
737 if (ret < 0)
738 return ret;
739
740 for (i = 0; i < xcrs.nr_xcrs; i++)
741 /* Only support xcr0 now */
742 if (xcrs.xcrs[0].xcr == 0) {
743 env->xcr0 = xcrs.xcrs[0].value;
744 break;
745 }
746 return 0;
747#else
748 return 0;
749#endif
750}
751
05330448
AL		 752static int kvm_get_sregs(CPUState *env)
753{
754 struct kvm_sregs sregs;
755 uint32_t hflags;
0e607a80 756 int bit, i, ret;
05330448
AL		 757
758 ret = kvm_vcpu_ioctl(env, KVM_GET_SREGS, &sregs);
759 if (ret < 0)
760 return ret;
761
0e607a80
JK		 762 /* There can only be one pending IRQ set in the bitmap at a time, so try
763 to find it and save its number instead (-1 for none). */
764 env->interrupt_injected = -1;
765 for (i = 0; i < ARRAY_SIZE(sregs.interrupt_bitmap); i++) {
766 if (sregs.interrupt_bitmap[i]) {
767 bit = ctz64(sregs.interrupt_bitmap[i]);
768 env->interrupt_injected = i * 64 + bit;
769 break;
770 }
771 }
05330448
AL		 772
773 get_seg(&env->segs[R_CS], &sregs.cs);
774 get_seg(&env->segs[R_DS], &sregs.ds);
775 get_seg(&env->segs[R_ES], &sregs.es);
776 get_seg(&env->segs[R_FS], &sregs.fs);
777 get_seg(&env->segs[R_GS], &sregs.gs);
778 get_seg(&env->segs[R_SS], &sregs.ss);
779
780 get_seg(&env->tr, &sregs.tr);
781 get_seg(&env->ldt, &sregs.ldt);
782
783 env->idt.limit = sregs.idt.limit;
784 env->idt.base = sregs.idt.base;
785 env->gdt.limit = sregs.gdt.limit;
786 env->gdt.base = sregs.gdt.base;
787
788 env->cr[0] = sregs.cr0;
789 env->cr[2] = sregs.cr2;
790 env->cr[3] = sregs.cr3;
791 env->cr[4] = sregs.cr4;
792
4a942cea 793 cpu_set_apic_base(env->apic_state, sregs.apic_base);
05330448
AL		 794
795 env->efer = sregs.efer;
4a942cea 796 //cpu_set_apic_tpr(env->apic_state, sregs.cr8);
05330448
AL		 797
798#define HFLAG_COPY_MASK ~( \
799 HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \
800 HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \
801 HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \
802 HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK)
803
804
805
806 hflags = (env->segs[R_CS].flags >> DESC_DPL_SHIFT) & HF_CPL_MASK;
807 hflags |= (env->cr[0] & CR0_PE_MASK) << (HF_PE_SHIFT - CR0_PE_SHIFT);
808 hflags |= (env->cr[0] << (HF_MP_SHIFT - CR0_MP_SHIFT)) &
809 (HF_MP_MASK | HF_EM_MASK | HF_TS_MASK);
810 hflags |= (env->eflags & (HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK));
811 hflags |= (env->cr[4] & CR4_OSFXSR_MASK) <<
812 (HF_OSFXSR_SHIFT - CR4_OSFXSR_SHIFT);
813
814 if (env->efer & MSR_EFER_LMA) {
815 hflags |= HF_LMA_MASK;
816 }
817
818 if ((hflags & HF_LMA_MASK) && (env->segs[R_CS].flags & DESC_L_MASK)) {
819 hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK;
820 } else {
821 hflags |= (env->segs[R_CS].flags & DESC_B_MASK) >>
822 (DESC_B_SHIFT - HF_CS32_SHIFT);
823 hflags |= (env->segs[R_SS].flags & DESC_B_MASK) >>
824 (DESC_B_SHIFT - HF_SS32_SHIFT);
825 if (!(env->cr[0] & CR0_PE_MASK) ||
826 (env->eflags & VM_MASK) ||
827 !(hflags & HF_CS32_MASK)) {
828 hflags |= HF_ADDSEG_MASK;
829 } else {
830 hflags |= ((env->segs[R_DS].base |
831 env->segs[R_ES].base |
832 env->segs[R_SS].base) != 0) <<
833 HF_ADDSEG_SHIFT;
834 }
835 }
836 env->hflags = (env->hflags & HFLAG_COPY_MASK) | hflags;
05330448
AL		 837
838 return 0;
839}
840
841static int kvm_get_msrs(CPUState *env)
842{
843 struct {
844 struct kvm_msrs info;
845 struct kvm_msr_entry entries[100];
846 } msr_data;
847 struct kvm_msr_entry *msrs = msr_data.entries;
848 int ret, i, n;
849
850 n = 0;
851 msrs[n++].index = MSR_IA32_SYSENTER_CS;
852 msrs[n++].index = MSR_IA32_SYSENTER_ESP;
853 msrs[n++].index = MSR_IA32_SYSENTER_EIP;
854 if (kvm_has_msr_star(env))
855 msrs[n++].index = MSR_STAR;
856 msrs[n++].index = MSR_IA32_TSC;
857#ifdef TARGET_X86_64
858 /* FIXME lm_capable_kernel */
859 msrs[n++].index = MSR_CSTAR;
860 msrs[n++].index = MSR_KERNELGSBASE;
861 msrs[n++].index = MSR_FMASK;
862 msrs[n++].index = MSR_LSTAR;
863#endif
1a03675d
GC		 864 msrs[n++].index = MSR_KVM_SYSTEM_TIME;
865 msrs[n++].index = MSR_KVM_WALL_CLOCK;
866
05330448
AL		 867 msr_data.info.nmsrs = n;
868 ret = kvm_vcpu_ioctl(env, KVM_GET_MSRS, &msr_data);
869 if (ret < 0)
870 return ret;
871
872 for (i = 0; i < ret; i++) {
873 switch (msrs[i].index) {
874 case MSR_IA32_SYSENTER_CS:
875 env->sysenter_cs = msrs[i].data;
876 break;
877 case MSR_IA32_SYSENTER_ESP:
878 env->sysenter_esp = msrs[i].data;
879 break;
880 case MSR_IA32_SYSENTER_EIP:
881 env->sysenter_eip = msrs[i].data;
882 break;
883 case MSR_STAR:
884 env->star = msrs[i].data;
885 break;
886#ifdef TARGET_X86_64
887 case MSR_CSTAR:
888 env->cstar = msrs[i].data;
889 break;
890 case MSR_KERNELGSBASE:
891 env->kernelgsbase = msrs[i].data;
892 break;
893 case MSR_FMASK:
894 env->fmask = msrs[i].data;
895 break;
896 case MSR_LSTAR:
897 env->lstar = msrs[i].data;
898 break;
899#endif
900 case MSR_IA32_TSC:
901 env->tsc = msrs[i].data;
902 break;
1a03675d
GC		 903 case MSR_KVM_SYSTEM_TIME:
904 env->system_time_msr = msrs[i].data;
905 break;
906 case MSR_KVM_WALL_CLOCK:
907 env->wall_clock_msr = msrs[i].data;
908 break;
05330448
AL		 909 }
910 }
911
912 return 0;
913}
914
9bdbe550
HB		 915static int kvm_put_mp_state(CPUState *env)
916{
917 struct kvm_mp_state mp_state = { .mp_state = env->mp_state };
918
919 return kvm_vcpu_ioctl(env, KVM_SET_MP_STATE, &mp_state);
920}
921
922static int kvm_get_mp_state(CPUState *env)
923{
924 struct kvm_mp_state mp_state;
925 int ret;
926
927 ret = kvm_vcpu_ioctl(env, KVM_GET_MP_STATE, &mp_state);
928 if (ret < 0) {
929 return ret;
930 }
931 env->mp_state = mp_state.mp_state;
932 return 0;
933}
934
ea643051 935static int kvm_put_vcpu_events(CPUState *env, int level)
a0fb002c
JK		 936{
937#ifdef KVM_CAP_VCPU_EVENTS
938 struct kvm_vcpu_events events;
939
940 if (!kvm_has_vcpu_events()) {
941 return 0;
942 }
943
31827373
JK		 944 events.exception.injected = (env->exception_injected >= 0);
945 events.exception.nr = env->exception_injected;
a0fb002c
JK		 946 events.exception.has_error_code = env->has_error_code;
947 events.exception.error_code = env->error_code;
948
949 events.interrupt.injected = (env->interrupt_injected >= 0);
950 events.interrupt.nr = env->interrupt_injected;
951 events.interrupt.soft = env->soft_interrupt;
952
953 events.nmi.injected = env->nmi_injected;
954 events.nmi.pending = env->nmi_pending;
955 events.nmi.masked = !!(env->hflags2 & HF2_NMI_MASK);
956
957 events.sipi_vector = env->sipi_vector;
958
ea643051
JK		 959 events.flags = 0;
960 if (level >= KVM_PUT_RESET_STATE) {
961 events.flags |=
962 KVM_VCPUEVENT_VALID_NMI_PENDING | KVM_VCPUEVENT_VALID_SIPI_VECTOR;
963 }
aee028b9 964
a0fb002c
JK		 965 return kvm_vcpu_ioctl(env, KVM_SET_VCPU_EVENTS, &events);
966#else
967 return 0;
968#endif
969}
970
971static int kvm_get_vcpu_events(CPUState *env)
972{
973#ifdef KVM_CAP_VCPU_EVENTS
974 struct kvm_vcpu_events events;
975 int ret;
976
977 if (!kvm_has_vcpu_events()) {
978 return 0;
979 }
980
981 ret = kvm_vcpu_ioctl(env, KVM_GET_VCPU_EVENTS, &events);
982 if (ret < 0) {
983 return ret;
984 }
31827373 985 env->exception_injected =
a0fb002c
JK		 986 events.exception.injected ? events.exception.nr : -1;
987 env->has_error_code = events.exception.has_error_code;
988 env->error_code = events.exception.error_code;
989
990 env->interrupt_injected =
991 events.interrupt.injected ? events.interrupt.nr : -1;
992 env->soft_interrupt = events.interrupt.soft;
993
994 env->nmi_injected = events.nmi.injected;
995 env->nmi_pending = events.nmi.pending;
996 if (events.nmi.masked) {
997 env->hflags2 |= HF2_NMI_MASK;
998 } else {
999 env->hflags2 &= ~HF2_NMI_MASK;
1000 }
1001
1002 env->sipi_vector = events.sipi_vector;
1003#endif
1004
1005 return 0;
1006}
1007
b0b1d690
JK		 1008static int kvm_guest_debug_workarounds(CPUState *env)
1009{
1010 int ret = 0;
1011#ifdef KVM_CAP_SET_GUEST_DEBUG
1012 unsigned long reinject_trap = 0;
1013
1014 if (!kvm_has_vcpu_events()) {
1015 if (env->exception_injected == 1) {
1016 reinject_trap = KVM_GUESTDBG_INJECT_DB;
1017 } else if (env->exception_injected == 3) {
1018 reinject_trap = KVM_GUESTDBG_INJECT_BP;
1019 }
1020 env->exception_injected = -1;
1021 }
1022
1023 /*
1024 * Kernels before KVM_CAP_X86_ROBUST_SINGLESTEP overwrote flags.TF
1025 * injected via SET_GUEST_DEBUG while updating GP regs. Work around this
1026 * by updating the debug state once again if single-stepping is on.
1027 * Another reason to call kvm_update_guest_debug here is a pending debug
1028 * trap raise by the guest. On kernels without SET_VCPU_EVENTS we have to
1029 * reinject them via SET_GUEST_DEBUG.
1030 */
1031 if (reinject_trap ||
1032 (!kvm_has_robust_singlestep() && env->singlestep_enabled)) {
1033 ret = kvm_update_guest_debug(env, reinject_trap);
1034 }
1035#endif /* KVM_CAP_SET_GUEST_DEBUG */
1036 return ret;
1037}
1038
ff44f1a3
JK		 1039static int kvm_put_debugregs(CPUState *env)
1040{
1041#ifdef KVM_CAP_DEBUGREGS
1042 struct kvm_debugregs dbgregs;
1043 int i;
1044
1045 if (!kvm_has_debugregs()) {
1046 return 0;
1047 }
1048
1049 for (i = 0; i < 4; i++) {
1050 dbgregs.db[i] = env->dr[i];
1051 }
1052 dbgregs.dr6 = env->dr[6];
1053 dbgregs.dr7 = env->dr[7];
1054 dbgregs.flags = 0;
1055
1056 return kvm_vcpu_ioctl(env, KVM_SET_DEBUGREGS, &dbgregs);
1057#else
1058 return 0;
1059#endif
1060}
1061
1062static int kvm_get_debugregs(CPUState *env)
1063{
1064#ifdef KVM_CAP_DEBUGREGS
1065 struct kvm_debugregs dbgregs;
1066 int i, ret;
1067
1068 if (!kvm_has_debugregs()) {
1069 return 0;
1070 }
1071
1072 ret = kvm_vcpu_ioctl(env, KVM_GET_DEBUGREGS, &dbgregs);
1073 if (ret < 0) {
1074 return ret;
1075 }
1076 for (i = 0; i < 4; i++) {
1077 env->dr[i] = dbgregs.db[i];
1078 }
1079 env->dr[4] = env->dr[6] = dbgregs.dr6;
1080 env->dr[5] = env->dr[7] = dbgregs.dr7;
1081#endif
1082
1083 return 0;
1084}
1085
ea375f9a 1086int kvm_arch_put_registers(CPUState *env, int level)
05330448
AL		 1087{
1088 int ret;
1089
dbaa07c4
JK		 1090 assert(cpu_is_stopped(env) || qemu_cpu_self(env));
1091
05330448
AL		 1092 ret = kvm_getput_regs(env, 1);
1093 if (ret < 0)
1094 return ret;
1095
f1665b21
SY		 1096 ret = kvm_put_xsave(env);
1097 if (ret < 0)
1098 return ret;
1099
1100 ret = kvm_put_xcrs(env);
05330448
AL		 1101 if (ret < 0)
1102 return ret;
1103
1104 ret = kvm_put_sregs(env);
1105 if (ret < 0)
1106 return ret;
1107
ea643051 1108 ret = kvm_put_msrs(env, level);
05330448
AL		 1109 if (ret < 0)
1110 return ret;
1111
ea643051
JK		 1112 if (level >= KVM_PUT_RESET_STATE) {
1113 ret = kvm_put_mp_state(env);
1114 if (ret < 0)
1115 return ret;
1116 }
f8d926e9 1117
ea643051 1118 ret = kvm_put_vcpu_events(env, level);
a0fb002c
JK		 1119 if (ret < 0)
1120 return ret;
1121
b0b1d690
JK		 1122 /* must be last */
1123 ret = kvm_guest_debug_workarounds(env);
1124 if (ret < 0)
1125 return ret;
1126
ff44f1a3
JK		 1127 ret = kvm_put_debugregs(env);
1128 if (ret < 0)
1129 return ret;
1130
05330448
AL		 1131 return 0;
1132}
1133
1134int kvm_arch_get_registers(CPUState *env)
1135{
1136 int ret;
1137
dbaa07c4
JK		 1138 assert(cpu_is_stopped(env) || qemu_cpu_self(env));
1139
05330448
AL		 1140 ret = kvm_getput_regs(env, 0);
1141 if (ret < 0)
1142 return ret;
1143
f1665b21
SY		 1144 ret = kvm_get_xsave(env);
1145 if (ret < 0)
1146 return ret;
1147
1148 ret = kvm_get_xcrs(env);
05330448
AL		 1149 if (ret < 0)
1150 return ret;
1151
1152 ret = kvm_get_sregs(env);
1153 if (ret < 0)
1154 return ret;
1155
1156 ret = kvm_get_msrs(env);
1157 if (ret < 0)
1158 return ret;
1159
5a2e3c2e
JK		 1160 ret = kvm_get_mp_state(env);
1161 if (ret < 0)
1162 return ret;
1163
a0fb002c
JK		 1164 ret = kvm_get_vcpu_events(env);
1165 if (ret < 0)
1166 return ret;
1167
ff44f1a3
JK		 1168 ret = kvm_get_debugregs(env);
1169 if (ret < 0)
1170 return ret;
1171
05330448
AL		 1172 return 0;
1173}
1174
1175int kvm_arch_pre_run(CPUState *env, struct kvm_run *run)
1176{
1177 /* Try to inject an interrupt if the guest can accept it */
1178 if (run->ready_for_interrupt_injection &&
1179 (env->interrupt_request & CPU_INTERRUPT_HARD) &&
1180 (env->eflags & IF_MASK)) {
1181 int irq;
1182
1183 env->interrupt_request &= ~CPU_INTERRUPT_HARD;
1184 irq = cpu_get_pic_interrupt(env);
1185 if (irq >= 0) {
1186 struct kvm_interrupt intr;
1187 intr.irq = irq;
1188 /* FIXME: errors */
8c0d577e 1189 DPRINTF("injected interrupt %d\n", irq);
05330448
AL		 1190 kvm_vcpu_ioctl(env, KVM_INTERRUPT, &intr);
1191 }
1192 }
1193
1194 /* If we have an interrupt but the guest is not ready to receive an
1195 * interrupt, request an interrupt window exit. This will
1196 * cause a return to userspace as soon as the guest is ready to
1197 * receive interrupts. */
1198 if ((env->interrupt_request & CPU_INTERRUPT_HARD))
1199 run->request_interrupt_window = 1;
1200 else
1201 run->request_interrupt_window = 0;
1202
8c0d577e 1203 DPRINTF("setting tpr\n");
4a942cea 1204 run->cr8 = cpu_get_apic_tpr(env->apic_state);
05330448
AL		 1205
1206 return 0;
1207}
1208
1209int kvm_arch_post_run(CPUState *env, struct kvm_run *run)
1210{
1211 if (run->if_flag)
1212 env->eflags |= IF_MASK;
1213 else
1214 env->eflags &= ~IF_MASK;
1215
4a942cea
BS		 1216 cpu_set_apic_tpr(env->apic_state, run->cr8);
1217 cpu_set_apic_base(env->apic_state, run->apic_base);
05330448
AL		 1218
1219 return 0;
1220}
1221
0af691d7
MT		 1222int kvm_arch_process_irqchip_events(CPUState *env)
1223{
1224 if (env->interrupt_request & CPU_INTERRUPT_INIT) {
1225 kvm_cpu_synchronize_state(env);
1226 do_cpu_init(env);
1227 env->exception_index = EXCP_HALTED;
1228 }
1229
1230 if (env->interrupt_request & CPU_INTERRUPT_SIPI) {
1231 kvm_cpu_synchronize_state(env);
1232 do_cpu_sipi(env);
1233 }
1234
1235 return env->halted;
1236}
1237
05330448
AL		 1238static int kvm_handle_halt(CPUState *env)
1239{
1240 if (!((env->interrupt_request & CPU_INTERRUPT_HARD) &&
1241 (env->eflags & IF_MASK)) &&
1242 !(env->interrupt_request & CPU_INTERRUPT_NMI)) {
1243 env->halted = 1;
1244 env->exception_index = EXCP_HLT;
1245 return 0;
1246 }
1247
1248 return 1;
1249}
1250
1251int kvm_arch_handle_exit(CPUState *env, struct kvm_run *run)
1252{
1253 int ret = 0;
1254
1255 switch (run->exit_reason) {
1256 case KVM_EXIT_HLT:
8c0d577e 1257 DPRINTF("handle_hlt\n");
05330448
AL		 1258 ret = kvm_handle_halt(env);
1259 break;
1260 }
1261
1262 return ret;
1263}
e22a25c9
AL		 1264
1265#ifdef KVM_CAP_SET_GUEST_DEBUG
e22a25c9
AL		 1266int kvm_arch_insert_sw_breakpoint(CPUState *env, struct kvm_sw_breakpoint *bp)
1267{
38972938 1268 static const uint8_t int3 = 0xcc;
64bf3f4e 1269
e22a25c9 1270 if (cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&bp->saved_insn, 1, 0) ||
64bf3f4e 1271 cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&int3, 1, 1))
e22a25c9
AL		 1272 return -EINVAL;
1273 return 0;
1274}
1275
1276int kvm_arch_remove_sw_breakpoint(CPUState *env, struct kvm_sw_breakpoint *bp)
1277{
1278 uint8_t int3;
1279
1280 if (cpu_memory_rw_debug(env, bp->pc, &int3, 1, 0) || int3 != 0xcc ||
64bf3f4e 1281 cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&bp->saved_insn, 1, 1))
e22a25c9
AL		 1282 return -EINVAL;
1283 return 0;
1284}
1285
1286static struct {
1287 target_ulong addr;
1288 int len;
1289 int type;
1290} hw_breakpoint[4];
1291
1292static int nb_hw_breakpoint;
1293
1294static int find_hw_breakpoint(target_ulong addr, int len, int type)
1295{
1296 int n;
1297
1298 for (n = 0; n < nb_hw_breakpoint; n++)
1299 if (hw_breakpoint[n].addr == addr && hw_breakpoint[n].type == type &&
1300 (hw_breakpoint[n].len == len || len == -1))
1301 return n;
1302 return -1;
1303}
1304
1305int kvm_arch_insert_hw_breakpoint(target_ulong addr,
1306 target_ulong len, int type)
1307{
1308 switch (type) {
1309 case GDB_BREAKPOINT_HW:
1310 len = 1;
1311 break;
1312 case GDB_WATCHPOINT_WRITE:
1313 case GDB_WATCHPOINT_ACCESS:
1314 switch (len) {
1315 case 1:
1316 break;
1317 case 2:
1318 case 4:
1319 case 8:
1320 if (addr & (len - 1))
1321 return -EINVAL;
1322 break;
1323 default:
1324 return -EINVAL;
1325 }
1326 break;
1327 default:
1328 return -ENOSYS;
1329 }
1330
1331 if (nb_hw_breakpoint == 4)
1332 return -ENOBUFS;
1333
1334 if (find_hw_breakpoint(addr, len, type) >= 0)
1335 return -EEXIST;
1336
1337 hw_breakpoint[nb_hw_breakpoint].addr = addr;
1338 hw_breakpoint[nb_hw_breakpoint].len = len;
1339 hw_breakpoint[nb_hw_breakpoint].type = type;
1340 nb_hw_breakpoint++;
1341
1342 return 0;
1343}
1344
1345int kvm_arch_remove_hw_breakpoint(target_ulong addr,
1346 target_ulong len, int type)
1347{
1348 int n;
1349
1350 n = find_hw_breakpoint(addr, (type == GDB_BREAKPOINT_HW) ? 1 : len, type);
1351 if (n < 0)
1352 return -ENOENT;
1353
1354 nb_hw_breakpoint--;
1355 hw_breakpoint[n] = hw_breakpoint[nb_hw_breakpoint];
1356
1357 return 0;
1358}
1359
1360void kvm_arch_remove_all_hw_breakpoints(void)
1361{
1362 nb_hw_breakpoint = 0;
1363}
1364
1365static CPUWatchpoint hw_watchpoint;
1366
1367int kvm_arch_debug(struct kvm_debug_exit_arch *arch_info)
1368{
1369 int handle = 0;
1370 int n;
1371
1372 if (arch_info->exception == 1) {
1373 if (arch_info->dr6 & (1 << 14)) {
1374 if (cpu_single_env->singlestep_enabled)
1375 handle = 1;
1376 } else {
1377 for (n = 0; n < 4; n++)
1378 if (arch_info->dr6 & (1 << n))
1379 switch ((arch_info->dr7 >> (16 + n*4)) & 0x3) {
1380 case 0x0:
1381 handle = 1;
1382 break;
1383 case 0x1:
1384 handle = 1;
1385 cpu_single_env->watchpoint_hit = &hw_watchpoint;
1386 hw_watchpoint.vaddr = hw_breakpoint[n].addr;
1387 hw_watchpoint.flags = BP_MEM_WRITE;
1388 break;
1389 case 0x3:
1390 handle = 1;
1391 cpu_single_env->watchpoint_hit = &hw_watchpoint;
1392 hw_watchpoint.vaddr = hw_breakpoint[n].addr;
1393 hw_watchpoint.flags = BP_MEM_ACCESS;
1394 break;
1395 }
1396 }
1397 } else if (kvm_find_sw_breakpoint(cpu_single_env, arch_info->pc))
1398 handle = 1;
1399
b0b1d690
JK		 1400 if (!handle) {
1401 cpu_synchronize_state(cpu_single_env);
1402 assert(cpu_single_env->exception_injected == -1);
1403
1404 cpu_single_env->exception_injected = arch_info->exception;
1405 cpu_single_env->has_error_code = 0;
1406 }
e22a25c9
AL		 1407
1408 return handle;
1409}
1410
1411void kvm_arch_update_guest_debug(CPUState *env, struct kvm_guest_debug *dbg)
1412{
1413 const uint8_t type_code[] = {
1414 [GDB_BREAKPOINT_HW] = 0x0,
1415 [GDB_WATCHPOINT_WRITE] = 0x1,
1416 [GDB_WATCHPOINT_ACCESS] = 0x3
1417 };
1418 const uint8_t len_code[] = {
1419 [1] = 0x0, [2] = 0x1, [4] = 0x3, [8] = 0x2
1420 };
1421 int n;
1422
1423 if (kvm_sw_breakpoints_active(env))
1424 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP;
1425
1426 if (nb_hw_breakpoint > 0) {
1427 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP;
1428 dbg->arch.debugreg[7] = 0x0600;
1429 for (n = 0; n < nb_hw_breakpoint; n++) {
1430 dbg->arch.debugreg[n] = hw_breakpoint[n].addr;
1431 dbg->arch.debugreg[7] |= (2 << (n * 2)) |
1432 (type_code[hw_breakpoint[n].type] << (16 + n*4)) |
1433 (len_code[hw_breakpoint[n].len] << (18 + n*4));
1434 }
1435 }
f1665b21
SY		 1436 /* Legal xcr0 for loading */
1437 env->xcr0 = 1;
e22a25c9
AL		 1438}
1439#endif /* KVM_CAP_SET_GUEST_DEBUG */
4513d923
GN		 1440
1441bool kvm_arch_stop_on_emulation_error(CPUState *env)
1442{
1443 return !(env->cr[0] & CR0_PE_MASK) ||
1444 ((env->segs[R_CS].selector & 3) != 3);
1445}
1446
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