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05330448 AL |
1 | /* |
2 | * QEMU KVM support | |
3 | * | |
4 | * Copyright (C) 2006-2008 Qumranet Technologies | |
5 | * Copyright IBM, Corp. 2008 | |
6 | * | |
7 | * Authors: | |
8 | * Anthony Liguori <aliguori@us.ibm.com> | |
9 | * | |
10 | * This work is licensed under the terms of the GNU GPL, version 2 or later. | |
11 | * See the COPYING file in the top-level directory. | |
12 | * | |
13 | */ | |
14 | ||
15 | #include <sys/types.h> | |
16 | #include <sys/ioctl.h> | |
17 | #include <sys/mman.h> | |
25d2e361 | 18 | #include <sys/utsname.h> |
05330448 AL |
19 | |
20 | #include <linux/kvm.h> | |
21 | ||
22 | #include "qemu-common.h" | |
23 | #include "sysemu.h" | |
24 | #include "kvm.h" | |
25 | #include "cpu.h" | |
e22a25c9 | 26 | #include "gdbstub.h" |
0e607a80 | 27 | #include "host-utils.h" |
4c5b10b7 | 28 | #include "hw/pc.h" |
408392b3 | 29 | #include "hw/apic.h" |
35bed8ee | 30 | #include "ioport.h" |
05330448 | 31 | |
bb0300dc GN |
32 | #ifdef CONFIG_KVM_PARA |
33 | #include <linux/kvm_para.h> | |
34 | #endif | |
35 | // | |
05330448 AL |
36 | //#define DEBUG_KVM |
37 | ||
38 | #ifdef DEBUG_KVM | |
8c0d577e | 39 | #define DPRINTF(fmt, ...) \ |
05330448 AL |
40 | do { fprintf(stderr, fmt, ## __VA_ARGS__); } while (0) |
41 | #else | |
8c0d577e | 42 | #define DPRINTF(fmt, ...) \ |
05330448 AL |
43 | do { } while (0) |
44 | #endif | |
45 | ||
1a03675d GC |
46 | #define MSR_KVM_WALL_CLOCK 0x11 |
47 | #define MSR_KVM_SYSTEM_TIME 0x12 | |
48 | ||
c0532a76 MT |
49 | #ifndef BUS_MCEERR_AR |
50 | #define BUS_MCEERR_AR 4 | |
51 | #endif | |
52 | #ifndef BUS_MCEERR_AO | |
53 | #define BUS_MCEERR_AO 5 | |
54 | #endif | |
55 | ||
94a8d39a JK |
56 | const KVMCapabilityInfo kvm_arch_required_capabilities[] = { |
57 | KVM_CAP_INFO(SET_TSS_ADDR), | |
58 | KVM_CAP_INFO(EXT_CPUID), | |
59 | KVM_CAP_INFO(MP_STATE), | |
60 | KVM_CAP_LAST_INFO | |
61 | }; | |
25d2e361 | 62 | |
c3a3a7d3 JK |
63 | static bool has_msr_star; |
64 | static bool has_msr_hsave_pa; | |
c5999bfc JK |
65 | #if defined(CONFIG_KVM_PARA) && defined(KVM_CAP_ASYNC_PF) |
66 | static bool has_msr_async_pf_en; | |
67 | #endif | |
25d2e361 | 68 | static int lm_capable_kernel; |
b827df58 AK |
69 | |
70 | static struct kvm_cpuid2 *try_get_cpuid(KVMState *s, int max) | |
71 | { | |
72 | struct kvm_cpuid2 *cpuid; | |
73 | int r, size; | |
74 | ||
75 | size = sizeof(*cpuid) + max * sizeof(*cpuid->entries); | |
76 | cpuid = (struct kvm_cpuid2 *)qemu_mallocz(size); | |
77 | cpuid->nent = max; | |
78 | r = kvm_ioctl(s, KVM_GET_SUPPORTED_CPUID, cpuid); | |
76ae317f MM |
79 | if (r == 0 && cpuid->nent >= max) { |
80 | r = -E2BIG; | |
81 | } | |
b827df58 AK |
82 | if (r < 0) { |
83 | if (r == -E2BIG) { | |
84 | qemu_free(cpuid); | |
85 | return NULL; | |
86 | } else { | |
87 | fprintf(stderr, "KVM_GET_SUPPORTED_CPUID failed: %s\n", | |
88 | strerror(-r)); | |
89 | exit(1); | |
90 | } | |
91 | } | |
92 | return cpuid; | |
93 | } | |
94 | ||
c958a8bd SY |
95 | uint32_t kvm_arch_get_supported_cpuid(CPUState *env, uint32_t function, |
96 | uint32_t index, int reg) | |
b827df58 AK |
97 | { |
98 | struct kvm_cpuid2 *cpuid; | |
99 | int i, max; | |
100 | uint32_t ret = 0; | |
101 | uint32_t cpuid_1_edx; | |
102 | ||
b827df58 AK |
103 | max = 1; |
104 | while ((cpuid = try_get_cpuid(env->kvm_state, max)) == NULL) { | |
105 | max *= 2; | |
106 | } | |
107 | ||
108 | for (i = 0; i < cpuid->nent; ++i) { | |
c958a8bd SY |
109 | if (cpuid->entries[i].function == function && |
110 | cpuid->entries[i].index == index) { | |
b827df58 AK |
111 | switch (reg) { |
112 | case R_EAX: | |
113 | ret = cpuid->entries[i].eax; | |
114 | break; | |
115 | case R_EBX: | |
116 | ret = cpuid->entries[i].ebx; | |
117 | break; | |
118 | case R_ECX: | |
119 | ret = cpuid->entries[i].ecx; | |
120 | break; | |
121 | case R_EDX: | |
122 | ret = cpuid->entries[i].edx; | |
19ccb8ea JK |
123 | switch (function) { |
124 | case 1: | |
125 | /* KVM before 2.6.30 misreports the following features */ | |
126 | ret |= CPUID_MTRR | CPUID_PAT | CPUID_MCE | CPUID_MCA; | |
127 | break; | |
128 | case 0x80000001: | |
b827df58 AK |
129 | /* On Intel, kvm returns cpuid according to the Intel spec, |
130 | * so add missing bits according to the AMD spec: | |
131 | */ | |
c958a8bd | 132 | cpuid_1_edx = kvm_arch_get_supported_cpuid(env, 1, 0, R_EDX); |
c1667e40 | 133 | ret |= cpuid_1_edx & 0x183f7ff; |
19ccb8ea | 134 | break; |
b827df58 AK |
135 | } |
136 | break; | |
137 | } | |
138 | } | |
139 | } | |
140 | ||
141 | qemu_free(cpuid); | |
142 | ||
143 | return ret; | |
144 | } | |
145 | ||
bb0300dc GN |
146 | #ifdef CONFIG_KVM_PARA |
147 | struct kvm_para_features { | |
b9bec74b JK |
148 | int cap; |
149 | int feature; | |
bb0300dc | 150 | } para_features[] = { |
b9bec74b | 151 | { KVM_CAP_CLOCKSOURCE, KVM_FEATURE_CLOCKSOURCE }, |
b9bec74b | 152 | { KVM_CAP_NOP_IO_DELAY, KVM_FEATURE_NOP_IO_DELAY }, |
b9bec74b | 153 | { KVM_CAP_PV_MMU, KVM_FEATURE_MMU_OP }, |
f6584ee2 | 154 | #ifdef KVM_CAP_ASYNC_PF |
b9bec74b | 155 | { KVM_CAP_ASYNC_PF, KVM_FEATURE_ASYNC_PF }, |
bb0300dc | 156 | #endif |
b9bec74b | 157 | { -1, -1 } |
bb0300dc GN |
158 | }; |
159 | ||
160 | static int get_para_features(CPUState *env) | |
161 | { | |
b9bec74b | 162 | int i, features = 0; |
bb0300dc | 163 | |
b9bec74b JK |
164 | for (i = 0; i < ARRAY_SIZE(para_features) - 1; i++) { |
165 | if (kvm_check_extension(env->kvm_state, para_features[i].cap)) { | |
166 | features |= (1 << para_features[i].feature); | |
bb0300dc | 167 | } |
b9bec74b | 168 | } |
b3a98367 | 169 | #ifdef KVM_CAP_ASYNC_PF |
c5999bfc | 170 | has_msr_async_pf_en = features & (1 << KVM_FEATURE_ASYNC_PF); |
b3a98367 | 171 | #endif |
b9bec74b | 172 | return features; |
bb0300dc | 173 | } |
419fb20a | 174 | #endif /* CONFIG_KVM_PARA */ |
bb0300dc | 175 | |
e7701825 MT |
176 | #ifdef KVM_CAP_MCE |
177 | static int kvm_get_mce_cap_supported(KVMState *s, uint64_t *mce_cap, | |
178 | int *max_banks) | |
179 | { | |
180 | int r; | |
181 | ||
14a09518 | 182 | r = kvm_check_extension(s, KVM_CAP_MCE); |
e7701825 MT |
183 | if (r > 0) { |
184 | *max_banks = r; | |
185 | return kvm_ioctl(s, KVM_X86_GET_MCE_CAP_SUPPORTED, mce_cap); | |
186 | } | |
187 | return -ENOSYS; | |
188 | } | |
189 | ||
190 | static int kvm_setup_mce(CPUState *env, uint64_t *mcg_cap) | |
191 | { | |
192 | return kvm_vcpu_ioctl(env, KVM_X86_SETUP_MCE, mcg_cap); | |
193 | } | |
194 | ||
c34d440a | 195 | static void kvm_mce_inject(CPUState *env, target_phys_addr_t paddr, int code) |
e7701825 | 196 | { |
c34d440a JK |
197 | uint64_t status = MCI_STATUS_VAL | MCI_STATUS_UC | MCI_STATUS_EN | |
198 | MCI_STATUS_MISCV | MCI_STATUS_ADDRV | MCI_STATUS_S; | |
199 | uint64_t mcg_status = MCG_STATUS_MCIP; | |
e7701825 | 200 | |
c34d440a JK |
201 | if (code == BUS_MCEERR_AR) { |
202 | status |= MCI_STATUS_AR | 0x134; | |
203 | mcg_status |= MCG_STATUS_EIPV; | |
204 | } else { | |
205 | status |= 0xc0; | |
206 | mcg_status |= MCG_STATUS_RIPV; | |
419fb20a | 207 | } |
c34d440a JK |
208 | cpu_x86_inject_mce(NULL, env, 9, status, mcg_status, paddr, |
209 | (MCM_ADDR_PHYS << 6) | 0xc, | |
210 | cpu_x86_support_mca_broadcast(env) ? | |
211 | MCE_INJECT_BROADCAST : 0); | |
419fb20a JK |
212 | } |
213 | #endif /* KVM_CAP_MCE */ | |
214 | ||
215 | static void hardware_memory_error(void) | |
216 | { | |
217 | fprintf(stderr, "Hardware memory error!\n"); | |
218 | exit(1); | |
219 | } | |
220 | ||
221 | int kvm_arch_on_sigbus_vcpu(CPUState *env, int code, void *addr) | |
222 | { | |
223 | #ifdef KVM_CAP_MCE | |
419fb20a JK |
224 | ram_addr_t ram_addr; |
225 | target_phys_addr_t paddr; | |
226 | ||
227 | if ((env->mcg_cap & MCG_SER_P) && addr | |
c34d440a JK |
228 | && (code == BUS_MCEERR_AR || code == BUS_MCEERR_AO)) { |
229 | if (qemu_ram_addr_from_host(addr, &ram_addr) || | |
230 | !kvm_physical_memory_addr_from_ram(env->kvm_state, ram_addr, | |
231 | &paddr)) { | |
419fb20a JK |
232 | fprintf(stderr, "Hardware memory error for memory used by " |
233 | "QEMU itself instead of guest system!\n"); | |
234 | /* Hope we are lucky for AO MCE */ | |
235 | if (code == BUS_MCEERR_AO) { | |
236 | return 0; | |
237 | } else { | |
238 | hardware_memory_error(); | |
239 | } | |
240 | } | |
c34d440a | 241 | kvm_mce_inject(env, paddr, code); |
419fb20a JK |
242 | } else |
243 | #endif /* KVM_CAP_MCE */ | |
244 | { | |
245 | if (code == BUS_MCEERR_AO) { | |
246 | return 0; | |
247 | } else if (code == BUS_MCEERR_AR) { | |
248 | hardware_memory_error(); | |
249 | } else { | |
250 | return 1; | |
251 | } | |
252 | } | |
253 | return 0; | |
254 | } | |
255 | ||
256 | int kvm_arch_on_sigbus(int code, void *addr) | |
257 | { | |
258 | #ifdef KVM_CAP_MCE | |
259 | if ((first_cpu->mcg_cap & MCG_SER_P) && addr && code == BUS_MCEERR_AO) { | |
419fb20a JK |
260 | ram_addr_t ram_addr; |
261 | target_phys_addr_t paddr; | |
262 | ||
263 | /* Hope we are lucky for AO MCE */ | |
c34d440a | 264 | if (qemu_ram_addr_from_host(addr, &ram_addr) || |
419fb20a JK |
265 | !kvm_physical_memory_addr_from_ram(first_cpu->kvm_state, ram_addr, |
266 | &paddr)) { | |
267 | fprintf(stderr, "Hardware memory error for memory used by " | |
268 | "QEMU itself instead of guest system!: %p\n", addr); | |
269 | return 0; | |
270 | } | |
c34d440a | 271 | kvm_mce_inject(first_cpu, paddr, code); |
419fb20a JK |
272 | } else |
273 | #endif /* KVM_CAP_MCE */ | |
274 | { | |
275 | if (code == BUS_MCEERR_AO) { | |
276 | return 0; | |
277 | } else if (code == BUS_MCEERR_AR) { | |
278 | hardware_memory_error(); | |
279 | } else { | |
280 | return 1; | |
281 | } | |
282 | } | |
283 | return 0; | |
284 | } | |
e7701825 | 285 | |
ab443475 JK |
286 | static int kvm_inject_mce_oldstyle(CPUState *env) |
287 | { | |
288 | #ifdef KVM_CAP_MCE | |
289 | if (!kvm_has_vcpu_events() && env->exception_injected == EXCP12_MCHK) { | |
290 | unsigned int bank, bank_num = env->mcg_cap & 0xff; | |
291 | struct kvm_x86_mce mce; | |
292 | ||
293 | env->exception_injected = -1; | |
294 | ||
295 | /* | |
296 | * There must be at least one bank in use if an MCE is pending. | |
297 | * Find it and use its values for the event injection. | |
298 | */ | |
299 | for (bank = 0; bank < bank_num; bank++) { | |
300 | if (env->mce_banks[bank * 4 + 1] & MCI_STATUS_VAL) { | |
301 | break; | |
302 | } | |
303 | } | |
304 | assert(bank < bank_num); | |
305 | ||
306 | mce.bank = bank; | |
307 | mce.status = env->mce_banks[bank * 4 + 1]; | |
308 | mce.mcg_status = env->mcg_status; | |
309 | mce.addr = env->mce_banks[bank * 4 + 2]; | |
310 | mce.misc = env->mce_banks[bank * 4 + 3]; | |
311 | ||
312 | return kvm_vcpu_ioctl(env, KVM_X86_SET_MCE, &mce); | |
313 | } | |
314 | #endif /* KVM_CAP_MCE */ | |
315 | return 0; | |
316 | } | |
317 | ||
b8cc45d6 GC |
318 | static void cpu_update_state(void *opaque, int running, int reason) |
319 | { | |
320 | CPUState *env = opaque; | |
321 | ||
322 | if (running) { | |
323 | env->tsc_valid = false; | |
324 | } | |
325 | } | |
326 | ||
05330448 AL |
327 | int kvm_arch_init_vcpu(CPUState *env) |
328 | { | |
329 | struct { | |
486bd5a2 AL |
330 | struct kvm_cpuid2 cpuid; |
331 | struct kvm_cpuid_entry2 entries[100]; | |
05330448 | 332 | } __attribute__((packed)) cpuid_data; |
486bd5a2 | 333 | uint32_t limit, i, j, cpuid_i; |
a33609ca | 334 | uint32_t unused; |
bb0300dc | 335 | struct kvm_cpuid_entry2 *c; |
521f0798 | 336 | #ifdef CONFIG_KVM_PARA |
bb0300dc GN |
337 | uint32_t signature[3]; |
338 | #endif | |
05330448 | 339 | |
c958a8bd | 340 | env->cpuid_features &= kvm_arch_get_supported_cpuid(env, 1, 0, R_EDX); |
6c0d7ee8 AP |
341 | |
342 | i = env->cpuid_ext_features & CPUID_EXT_HYPERVISOR; | |
c958a8bd | 343 | env->cpuid_ext_features &= kvm_arch_get_supported_cpuid(env, 1, 0, R_ECX); |
6c0d7ee8 AP |
344 | env->cpuid_ext_features |= i; |
345 | ||
457dfed6 | 346 | env->cpuid_ext2_features &= kvm_arch_get_supported_cpuid(env, 0x80000001, |
c958a8bd | 347 | 0, R_EDX); |
457dfed6 | 348 | env->cpuid_ext3_features &= kvm_arch_get_supported_cpuid(env, 0x80000001, |
c958a8bd | 349 | 0, R_ECX); |
296acb64 JR |
350 | env->cpuid_svm_features &= kvm_arch_get_supported_cpuid(env, 0x8000000A, |
351 | 0, R_EDX); | |
352 | ||
6c1f42fe | 353 | |
05330448 AL |
354 | cpuid_i = 0; |
355 | ||
bb0300dc GN |
356 | #ifdef CONFIG_KVM_PARA |
357 | /* Paravirtualization CPUIDs */ | |
358 | memcpy(signature, "KVMKVMKVM\0\0\0", 12); | |
359 | c = &cpuid_data.entries[cpuid_i++]; | |
360 | memset(c, 0, sizeof(*c)); | |
361 | c->function = KVM_CPUID_SIGNATURE; | |
362 | c->eax = 0; | |
363 | c->ebx = signature[0]; | |
364 | c->ecx = signature[1]; | |
365 | c->edx = signature[2]; | |
366 | ||
367 | c = &cpuid_data.entries[cpuid_i++]; | |
368 | memset(c, 0, sizeof(*c)); | |
369 | c->function = KVM_CPUID_FEATURES; | |
370 | c->eax = env->cpuid_kvm_features & get_para_features(env); | |
371 | #endif | |
372 | ||
a33609ca | 373 | cpu_x86_cpuid(env, 0, 0, &limit, &unused, &unused, &unused); |
05330448 AL |
374 | |
375 | for (i = 0; i <= limit; i++) { | |
bb0300dc | 376 | c = &cpuid_data.entries[cpuid_i++]; |
486bd5a2 AL |
377 | |
378 | switch (i) { | |
a36b1029 AL |
379 | case 2: { |
380 | /* Keep reading function 2 till all the input is received */ | |
381 | int times; | |
382 | ||
a36b1029 | 383 | c->function = i; |
a33609ca AL |
384 | c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC | |
385 | KVM_CPUID_FLAG_STATE_READ_NEXT; | |
386 | cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx); | |
387 | times = c->eax & 0xff; | |
a36b1029 AL |
388 | |
389 | for (j = 1; j < times; ++j) { | |
a33609ca | 390 | c = &cpuid_data.entries[cpuid_i++]; |
a36b1029 | 391 | c->function = i; |
a33609ca AL |
392 | c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC; |
393 | cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx); | |
a36b1029 AL |
394 | } |
395 | break; | |
396 | } | |
486bd5a2 AL |
397 | case 4: |
398 | case 0xb: | |
399 | case 0xd: | |
400 | for (j = 0; ; j++) { | |
486bd5a2 AL |
401 | c->function = i; |
402 | c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX; | |
403 | c->index = j; | |
a33609ca | 404 | cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx); |
486bd5a2 | 405 | |
b9bec74b | 406 | if (i == 4 && c->eax == 0) { |
486bd5a2 | 407 | break; |
b9bec74b JK |
408 | } |
409 | if (i == 0xb && !(c->ecx & 0xff00)) { | |
486bd5a2 | 410 | break; |
b9bec74b JK |
411 | } |
412 | if (i == 0xd && c->eax == 0) { | |
486bd5a2 | 413 | break; |
b9bec74b | 414 | } |
a33609ca | 415 | c = &cpuid_data.entries[cpuid_i++]; |
486bd5a2 AL |
416 | } |
417 | break; | |
418 | default: | |
486bd5a2 | 419 | c->function = i; |
a33609ca AL |
420 | c->flags = 0; |
421 | cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx); | |
486bd5a2 AL |
422 | break; |
423 | } | |
05330448 | 424 | } |
a33609ca | 425 | cpu_x86_cpuid(env, 0x80000000, 0, &limit, &unused, &unused, &unused); |
05330448 AL |
426 | |
427 | for (i = 0x80000000; i <= limit; i++) { | |
bb0300dc | 428 | c = &cpuid_data.entries[cpuid_i++]; |
05330448 | 429 | |
05330448 | 430 | c->function = i; |
a33609ca AL |
431 | c->flags = 0; |
432 | cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx); | |
05330448 AL |
433 | } |
434 | ||
435 | cpuid_data.cpuid.nent = cpuid_i; | |
436 | ||
e7701825 MT |
437 | #ifdef KVM_CAP_MCE |
438 | if (((env->cpuid_version >> 8)&0xF) >= 6 | |
439 | && (env->cpuid_features&(CPUID_MCE|CPUID_MCA)) == (CPUID_MCE|CPUID_MCA) | |
440 | && kvm_check_extension(env->kvm_state, KVM_CAP_MCE) > 0) { | |
441 | uint64_t mcg_cap; | |
442 | int banks; | |
443 | ||
b9bec74b | 444 | if (kvm_get_mce_cap_supported(env->kvm_state, &mcg_cap, &banks)) { |
e7701825 | 445 | perror("kvm_get_mce_cap_supported FAILED"); |
b9bec74b | 446 | } else { |
e7701825 MT |
447 | if (banks > MCE_BANKS_DEF) |
448 | banks = MCE_BANKS_DEF; | |
449 | mcg_cap &= MCE_CAP_DEF; | |
450 | mcg_cap |= banks; | |
b9bec74b | 451 | if (kvm_setup_mce(env, &mcg_cap)) { |
e7701825 | 452 | perror("kvm_setup_mce FAILED"); |
b9bec74b | 453 | } else { |
e7701825 | 454 | env->mcg_cap = mcg_cap; |
b9bec74b | 455 | } |
e7701825 MT |
456 | } |
457 | } | |
458 | #endif | |
459 | ||
b8cc45d6 GC |
460 | qemu_add_vm_change_state_handler(cpu_update_state, env); |
461 | ||
486bd5a2 | 462 | return kvm_vcpu_ioctl(env, KVM_SET_CPUID2, &cpuid_data); |
05330448 AL |
463 | } |
464 | ||
caa5af0f JK |
465 | void kvm_arch_reset_vcpu(CPUState *env) |
466 | { | |
e73223a5 | 467 | env->exception_injected = -1; |
0e607a80 | 468 | env->interrupt_injected = -1; |
1a5e9d2f | 469 | env->xcr0 = 1; |
ddced198 MT |
470 | if (kvm_irqchip_in_kernel()) { |
471 | env->mp_state = cpu_is_bsp(env) ? KVM_MP_STATE_RUNNABLE : | |
472 | KVM_MP_STATE_UNINITIALIZED; | |
473 | } else { | |
474 | env->mp_state = KVM_MP_STATE_RUNNABLE; | |
475 | } | |
caa5af0f JK |
476 | } |
477 | ||
c3a3a7d3 | 478 | static int kvm_get_supported_msrs(KVMState *s) |
05330448 | 479 | { |
75b10c43 | 480 | static int kvm_supported_msrs; |
c3a3a7d3 | 481 | int ret = 0; |
05330448 AL |
482 | |
483 | /* first time */ | |
75b10c43 | 484 | if (kvm_supported_msrs == 0) { |
05330448 AL |
485 | struct kvm_msr_list msr_list, *kvm_msr_list; |
486 | ||
75b10c43 | 487 | kvm_supported_msrs = -1; |
05330448 AL |
488 | |
489 | /* Obtain MSR list from KVM. These are the MSRs that we must | |
490 | * save/restore */ | |
4c9f7372 | 491 | msr_list.nmsrs = 0; |
c3a3a7d3 | 492 | ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, &msr_list); |
6fb6d245 | 493 | if (ret < 0 && ret != -E2BIG) { |
c3a3a7d3 | 494 | return ret; |
6fb6d245 | 495 | } |
d9db889f JK |
496 | /* Old kernel modules had a bug and could write beyond the provided |
497 | memory. Allocate at least a safe amount of 1K. */ | |
498 | kvm_msr_list = qemu_mallocz(MAX(1024, sizeof(msr_list) + | |
499 | msr_list.nmsrs * | |
500 | sizeof(msr_list.indices[0]))); | |
05330448 | 501 | |
55308450 | 502 | kvm_msr_list->nmsrs = msr_list.nmsrs; |
c3a3a7d3 | 503 | ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, kvm_msr_list); |
05330448 AL |
504 | if (ret >= 0) { |
505 | int i; | |
506 | ||
507 | for (i = 0; i < kvm_msr_list->nmsrs; i++) { | |
508 | if (kvm_msr_list->indices[i] == MSR_STAR) { | |
c3a3a7d3 | 509 | has_msr_star = true; |
75b10c43 MT |
510 | continue; |
511 | } | |
512 | if (kvm_msr_list->indices[i] == MSR_VM_HSAVE_PA) { | |
c3a3a7d3 | 513 | has_msr_hsave_pa = true; |
75b10c43 | 514 | continue; |
05330448 AL |
515 | } |
516 | } | |
517 | } | |
518 | ||
519 | free(kvm_msr_list); | |
520 | } | |
521 | ||
c3a3a7d3 | 522 | return ret; |
05330448 AL |
523 | } |
524 | ||
cad1e282 | 525 | int kvm_arch_init(KVMState *s) |
20420430 | 526 | { |
11076198 | 527 | uint64_t identity_base = 0xfffbc000; |
20420430 | 528 | int ret; |
25d2e361 | 529 | struct utsname utsname; |
20420430 | 530 | |
c3a3a7d3 | 531 | ret = kvm_get_supported_msrs(s); |
20420430 | 532 | if (ret < 0) { |
20420430 SY |
533 | return ret; |
534 | } | |
25d2e361 MT |
535 | |
536 | uname(&utsname); | |
537 | lm_capable_kernel = strcmp(utsname.machine, "x86_64") == 0; | |
538 | ||
4c5b10b7 | 539 | /* |
11076198 JK |
540 | * On older Intel CPUs, KVM uses vm86 mode to emulate 16-bit code directly. |
541 | * In order to use vm86 mode, an EPT identity map and a TSS are needed. | |
542 | * Since these must be part of guest physical memory, we need to allocate | |
543 | * them, both by setting their start addresses in the kernel and by | |
544 | * creating a corresponding e820 entry. We need 4 pages before the BIOS. | |
545 | * | |
546 | * Older KVM versions may not support setting the identity map base. In | |
547 | * that case we need to stick with the default, i.e. a 256K maximum BIOS | |
548 | * size. | |
4c5b10b7 | 549 | */ |
11076198 JK |
550 | #ifdef KVM_CAP_SET_IDENTITY_MAP_ADDR |
551 | if (kvm_check_extension(s, KVM_CAP_SET_IDENTITY_MAP_ADDR)) { | |
552 | /* Allows up to 16M BIOSes. */ | |
553 | identity_base = 0xfeffc000; | |
554 | ||
555 | ret = kvm_vm_ioctl(s, KVM_SET_IDENTITY_MAP_ADDR, &identity_base); | |
556 | if (ret < 0) { | |
557 | return ret; | |
558 | } | |
4c5b10b7 | 559 | } |
11076198 JK |
560 | #endif |
561 | /* Set TSS base one page after EPT identity map. */ | |
562 | ret = kvm_vm_ioctl(s, KVM_SET_TSS_ADDR, identity_base + 0x1000); | |
20420430 SY |
563 | if (ret < 0) { |
564 | return ret; | |
565 | } | |
566 | ||
11076198 JK |
567 | /* Tell fw_cfg to notify the BIOS to reserve the range. */ |
568 | ret = e820_add_entry(identity_base, 0x4000, E820_RESERVED); | |
20420430 | 569 | if (ret < 0) { |
11076198 | 570 | fprintf(stderr, "e820_add_entry() table is full\n"); |
20420430 SY |
571 | return ret; |
572 | } | |
573 | ||
11076198 | 574 | return 0; |
05330448 | 575 | } |
b9bec74b | 576 | |
05330448 AL |
577 | static void set_v8086_seg(struct kvm_segment *lhs, const SegmentCache *rhs) |
578 | { | |
579 | lhs->selector = rhs->selector; | |
580 | lhs->base = rhs->base; | |
581 | lhs->limit = rhs->limit; | |
582 | lhs->type = 3; | |
583 | lhs->present = 1; | |
584 | lhs->dpl = 3; | |
585 | lhs->db = 0; | |
586 | lhs->s = 1; | |
587 | lhs->l = 0; | |
588 | lhs->g = 0; | |
589 | lhs->avl = 0; | |
590 | lhs->unusable = 0; | |
591 | } | |
592 | ||
593 | static void set_seg(struct kvm_segment *lhs, const SegmentCache *rhs) | |
594 | { | |
595 | unsigned flags = rhs->flags; | |
596 | lhs->selector = rhs->selector; | |
597 | lhs->base = rhs->base; | |
598 | lhs->limit = rhs->limit; | |
599 | lhs->type = (flags >> DESC_TYPE_SHIFT) & 15; | |
600 | lhs->present = (flags & DESC_P_MASK) != 0; | |
acaa7550 | 601 | lhs->dpl = (flags >> DESC_DPL_SHIFT) & 3; |
05330448 AL |
602 | lhs->db = (flags >> DESC_B_SHIFT) & 1; |
603 | lhs->s = (flags & DESC_S_MASK) != 0; | |
604 | lhs->l = (flags >> DESC_L_SHIFT) & 1; | |
605 | lhs->g = (flags & DESC_G_MASK) != 0; | |
606 | lhs->avl = (flags & DESC_AVL_MASK) != 0; | |
607 | lhs->unusable = 0; | |
608 | } | |
609 | ||
610 | static void get_seg(SegmentCache *lhs, const struct kvm_segment *rhs) | |
611 | { | |
612 | lhs->selector = rhs->selector; | |
613 | lhs->base = rhs->base; | |
614 | lhs->limit = rhs->limit; | |
b9bec74b JK |
615 | lhs->flags = (rhs->type << DESC_TYPE_SHIFT) | |
616 | (rhs->present * DESC_P_MASK) | | |
617 | (rhs->dpl << DESC_DPL_SHIFT) | | |
618 | (rhs->db << DESC_B_SHIFT) | | |
619 | (rhs->s * DESC_S_MASK) | | |
620 | (rhs->l << DESC_L_SHIFT) | | |
621 | (rhs->g * DESC_G_MASK) | | |
622 | (rhs->avl * DESC_AVL_MASK); | |
05330448 AL |
623 | } |
624 | ||
625 | static void kvm_getput_reg(__u64 *kvm_reg, target_ulong *qemu_reg, int set) | |
626 | { | |
b9bec74b | 627 | if (set) { |
05330448 | 628 | *kvm_reg = *qemu_reg; |
b9bec74b | 629 | } else { |
05330448 | 630 | *qemu_reg = *kvm_reg; |
b9bec74b | 631 | } |
05330448 AL |
632 | } |
633 | ||
634 | static int kvm_getput_regs(CPUState *env, int set) | |
635 | { | |
636 | struct kvm_regs regs; | |
637 | int ret = 0; | |
638 | ||
639 | if (!set) { | |
640 | ret = kvm_vcpu_ioctl(env, KVM_GET_REGS, ®s); | |
b9bec74b | 641 | if (ret < 0) { |
05330448 | 642 | return ret; |
b9bec74b | 643 | } |
05330448 AL |
644 | } |
645 | ||
646 | kvm_getput_reg(®s.rax, &env->regs[R_EAX], set); | |
647 | kvm_getput_reg(®s.rbx, &env->regs[R_EBX], set); | |
648 | kvm_getput_reg(®s.rcx, &env->regs[R_ECX], set); | |
649 | kvm_getput_reg(®s.rdx, &env->regs[R_EDX], set); | |
650 | kvm_getput_reg(®s.rsi, &env->regs[R_ESI], set); | |
651 | kvm_getput_reg(®s.rdi, &env->regs[R_EDI], set); | |
652 | kvm_getput_reg(®s.rsp, &env->regs[R_ESP], set); | |
653 | kvm_getput_reg(®s.rbp, &env->regs[R_EBP], set); | |
654 | #ifdef TARGET_X86_64 | |
655 | kvm_getput_reg(®s.r8, &env->regs[8], set); | |
656 | kvm_getput_reg(®s.r9, &env->regs[9], set); | |
657 | kvm_getput_reg(®s.r10, &env->regs[10], set); | |
658 | kvm_getput_reg(®s.r11, &env->regs[11], set); | |
659 | kvm_getput_reg(®s.r12, &env->regs[12], set); | |
660 | kvm_getput_reg(®s.r13, &env->regs[13], set); | |
661 | kvm_getput_reg(®s.r14, &env->regs[14], set); | |
662 | kvm_getput_reg(®s.r15, &env->regs[15], set); | |
663 | #endif | |
664 | ||
665 | kvm_getput_reg(®s.rflags, &env->eflags, set); | |
666 | kvm_getput_reg(®s.rip, &env->eip, set); | |
667 | ||
b9bec74b | 668 | if (set) { |
05330448 | 669 | ret = kvm_vcpu_ioctl(env, KVM_SET_REGS, ®s); |
b9bec74b | 670 | } |
05330448 AL |
671 | |
672 | return ret; | |
673 | } | |
674 | ||
675 | static int kvm_put_fpu(CPUState *env) | |
676 | { | |
677 | struct kvm_fpu fpu; | |
678 | int i; | |
679 | ||
680 | memset(&fpu, 0, sizeof fpu); | |
681 | fpu.fsw = env->fpus & ~(7 << 11); | |
682 | fpu.fsw |= (env->fpstt & 7) << 11; | |
683 | fpu.fcw = env->fpuc; | |
b9bec74b JK |
684 | for (i = 0; i < 8; ++i) { |
685 | fpu.ftwx |= (!env->fptags[i]) << i; | |
686 | } | |
05330448 AL |
687 | memcpy(fpu.fpr, env->fpregs, sizeof env->fpregs); |
688 | memcpy(fpu.xmm, env->xmm_regs, sizeof env->xmm_regs); | |
689 | fpu.mxcsr = env->mxcsr; | |
690 | ||
691 | return kvm_vcpu_ioctl(env, KVM_SET_FPU, &fpu); | |
692 | } | |
693 | ||
f1665b21 SY |
694 | #ifdef KVM_CAP_XSAVE |
695 | #define XSAVE_CWD_RIP 2 | |
696 | #define XSAVE_CWD_RDP 4 | |
697 | #define XSAVE_MXCSR 6 | |
698 | #define XSAVE_ST_SPACE 8 | |
699 | #define XSAVE_XMM_SPACE 40 | |
700 | #define XSAVE_XSTATE_BV 128 | |
701 | #define XSAVE_YMMH_SPACE 144 | |
702 | #endif | |
703 | ||
704 | static int kvm_put_xsave(CPUState *env) | |
705 | { | |
706 | #ifdef KVM_CAP_XSAVE | |
0f53994f | 707 | int i, r; |
f1665b21 SY |
708 | struct kvm_xsave* xsave; |
709 | uint16_t cwd, swd, twd, fop; | |
710 | ||
b9bec74b | 711 | if (!kvm_has_xsave()) { |
f1665b21 | 712 | return kvm_put_fpu(env); |
b9bec74b | 713 | } |
f1665b21 SY |
714 | |
715 | xsave = qemu_memalign(4096, sizeof(struct kvm_xsave)); | |
716 | memset(xsave, 0, sizeof(struct kvm_xsave)); | |
717 | cwd = swd = twd = fop = 0; | |
718 | swd = env->fpus & ~(7 << 11); | |
719 | swd |= (env->fpstt & 7) << 11; | |
720 | cwd = env->fpuc; | |
b9bec74b | 721 | for (i = 0; i < 8; ++i) { |
f1665b21 | 722 | twd |= (!env->fptags[i]) << i; |
b9bec74b | 723 | } |
f1665b21 SY |
724 | xsave->region[0] = (uint32_t)(swd << 16) + cwd; |
725 | xsave->region[1] = (uint32_t)(fop << 16) + twd; | |
726 | memcpy(&xsave->region[XSAVE_ST_SPACE], env->fpregs, | |
727 | sizeof env->fpregs); | |
728 | memcpy(&xsave->region[XSAVE_XMM_SPACE], env->xmm_regs, | |
729 | sizeof env->xmm_regs); | |
730 | xsave->region[XSAVE_MXCSR] = env->mxcsr; | |
731 | *(uint64_t *)&xsave->region[XSAVE_XSTATE_BV] = env->xstate_bv; | |
732 | memcpy(&xsave->region[XSAVE_YMMH_SPACE], env->ymmh_regs, | |
733 | sizeof env->ymmh_regs); | |
0f53994f MT |
734 | r = kvm_vcpu_ioctl(env, KVM_SET_XSAVE, xsave); |
735 | qemu_free(xsave); | |
736 | return r; | |
f1665b21 SY |
737 | #else |
738 | return kvm_put_fpu(env); | |
739 | #endif | |
740 | } | |
741 | ||
742 | static int kvm_put_xcrs(CPUState *env) | |
743 | { | |
744 | #ifdef KVM_CAP_XCRS | |
745 | struct kvm_xcrs xcrs; | |
746 | ||
b9bec74b | 747 | if (!kvm_has_xcrs()) { |
f1665b21 | 748 | return 0; |
b9bec74b | 749 | } |
f1665b21 SY |
750 | |
751 | xcrs.nr_xcrs = 1; | |
752 | xcrs.flags = 0; | |
753 | xcrs.xcrs[0].xcr = 0; | |
754 | xcrs.xcrs[0].value = env->xcr0; | |
755 | return kvm_vcpu_ioctl(env, KVM_SET_XCRS, &xcrs); | |
756 | #else | |
757 | return 0; | |
758 | #endif | |
759 | } | |
760 | ||
05330448 AL |
761 | static int kvm_put_sregs(CPUState *env) |
762 | { | |
763 | struct kvm_sregs sregs; | |
764 | ||
0e607a80 JK |
765 | memset(sregs.interrupt_bitmap, 0, sizeof(sregs.interrupt_bitmap)); |
766 | if (env->interrupt_injected >= 0) { | |
767 | sregs.interrupt_bitmap[env->interrupt_injected / 64] |= | |
768 | (uint64_t)1 << (env->interrupt_injected % 64); | |
769 | } | |
05330448 AL |
770 | |
771 | if ((env->eflags & VM_MASK)) { | |
b9bec74b JK |
772 | set_v8086_seg(&sregs.cs, &env->segs[R_CS]); |
773 | set_v8086_seg(&sregs.ds, &env->segs[R_DS]); | |
774 | set_v8086_seg(&sregs.es, &env->segs[R_ES]); | |
775 | set_v8086_seg(&sregs.fs, &env->segs[R_FS]); | |
776 | set_v8086_seg(&sregs.gs, &env->segs[R_GS]); | |
777 | set_v8086_seg(&sregs.ss, &env->segs[R_SS]); | |
05330448 | 778 | } else { |
b9bec74b JK |
779 | set_seg(&sregs.cs, &env->segs[R_CS]); |
780 | set_seg(&sregs.ds, &env->segs[R_DS]); | |
781 | set_seg(&sregs.es, &env->segs[R_ES]); | |
782 | set_seg(&sregs.fs, &env->segs[R_FS]); | |
783 | set_seg(&sregs.gs, &env->segs[R_GS]); | |
784 | set_seg(&sregs.ss, &env->segs[R_SS]); | |
05330448 AL |
785 | } |
786 | ||
787 | set_seg(&sregs.tr, &env->tr); | |
788 | set_seg(&sregs.ldt, &env->ldt); | |
789 | ||
790 | sregs.idt.limit = env->idt.limit; | |
791 | sregs.idt.base = env->idt.base; | |
792 | sregs.gdt.limit = env->gdt.limit; | |
793 | sregs.gdt.base = env->gdt.base; | |
794 | ||
795 | sregs.cr0 = env->cr[0]; | |
796 | sregs.cr2 = env->cr[2]; | |
797 | sregs.cr3 = env->cr[3]; | |
798 | sregs.cr4 = env->cr[4]; | |
799 | ||
4a942cea BS |
800 | sregs.cr8 = cpu_get_apic_tpr(env->apic_state); |
801 | sregs.apic_base = cpu_get_apic_base(env->apic_state); | |
05330448 AL |
802 | |
803 | sregs.efer = env->efer; | |
804 | ||
805 | return kvm_vcpu_ioctl(env, KVM_SET_SREGS, &sregs); | |
806 | } | |
807 | ||
808 | static void kvm_msr_entry_set(struct kvm_msr_entry *entry, | |
809 | uint32_t index, uint64_t value) | |
810 | { | |
811 | entry->index = index; | |
812 | entry->data = value; | |
813 | } | |
814 | ||
ea643051 | 815 | static int kvm_put_msrs(CPUState *env, int level) |
05330448 AL |
816 | { |
817 | struct { | |
818 | struct kvm_msrs info; | |
819 | struct kvm_msr_entry entries[100]; | |
820 | } msr_data; | |
821 | struct kvm_msr_entry *msrs = msr_data.entries; | |
d8da8574 | 822 | int n = 0; |
05330448 AL |
823 | |
824 | kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_CS, env->sysenter_cs); | |
825 | kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_ESP, env->sysenter_esp); | |
826 | kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_EIP, env->sysenter_eip); | |
c3a3a7d3 | 827 | if (has_msr_star) { |
b9bec74b JK |
828 | kvm_msr_entry_set(&msrs[n++], MSR_STAR, env->star); |
829 | } | |
c3a3a7d3 | 830 | if (has_msr_hsave_pa) { |
75b10c43 | 831 | kvm_msr_entry_set(&msrs[n++], MSR_VM_HSAVE_PA, env->vm_hsave); |
b9bec74b | 832 | } |
05330448 | 833 | #ifdef TARGET_X86_64 |
25d2e361 MT |
834 | if (lm_capable_kernel) { |
835 | kvm_msr_entry_set(&msrs[n++], MSR_CSTAR, env->cstar); | |
836 | kvm_msr_entry_set(&msrs[n++], MSR_KERNELGSBASE, env->kernelgsbase); | |
837 | kvm_msr_entry_set(&msrs[n++], MSR_FMASK, env->fmask); | |
838 | kvm_msr_entry_set(&msrs[n++], MSR_LSTAR, env->lstar); | |
839 | } | |
05330448 | 840 | #endif |
ea643051 | 841 | if (level == KVM_PUT_FULL_STATE) { |
384331a6 MT |
842 | /* |
843 | * KVM is yet unable to synchronize TSC values of multiple VCPUs on | |
844 | * writeback. Until this is fixed, we only write the offset to SMP | |
845 | * guests after migration, desynchronizing the VCPUs, but avoiding | |
846 | * huge jump-backs that would occur without any writeback at all. | |
847 | */ | |
848 | if (smp_cpus == 1 || env->tsc != 0) { | |
849 | kvm_msr_entry_set(&msrs[n++], MSR_IA32_TSC, env->tsc); | |
850 | } | |
ff5c186b JK |
851 | } |
852 | /* | |
853 | * The following paravirtual MSRs have side effects on the guest or are | |
854 | * too heavy for normal writeback. Limit them to reset or full state | |
855 | * updates. | |
856 | */ | |
857 | if (level >= KVM_PUT_RESET_STATE) { | |
ea643051 JK |
858 | kvm_msr_entry_set(&msrs[n++], MSR_KVM_SYSTEM_TIME, |
859 | env->system_time_msr); | |
860 | kvm_msr_entry_set(&msrs[n++], MSR_KVM_WALL_CLOCK, env->wall_clock_msr); | |
521f0798 | 861 | #if defined(CONFIG_KVM_PARA) && defined(KVM_CAP_ASYNC_PF) |
c5999bfc JK |
862 | if (has_msr_async_pf_en) { |
863 | kvm_msr_entry_set(&msrs[n++], MSR_KVM_ASYNC_PF_EN, | |
864 | env->async_pf_en_msr); | |
865 | } | |
f6584ee2 | 866 | #endif |
ea643051 | 867 | } |
57780495 MT |
868 | #ifdef KVM_CAP_MCE |
869 | if (env->mcg_cap) { | |
d8da8574 | 870 | int i; |
b9bec74b | 871 | |
c34d440a JK |
872 | kvm_msr_entry_set(&msrs[n++], MSR_MCG_STATUS, env->mcg_status); |
873 | kvm_msr_entry_set(&msrs[n++], MSR_MCG_CTL, env->mcg_ctl); | |
874 | for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) { | |
875 | kvm_msr_entry_set(&msrs[n++], MSR_MC0_CTL + i, env->mce_banks[i]); | |
57780495 MT |
876 | } |
877 | } | |
878 | #endif | |
1a03675d | 879 | |
05330448 AL |
880 | msr_data.info.nmsrs = n; |
881 | ||
882 | return kvm_vcpu_ioctl(env, KVM_SET_MSRS, &msr_data); | |
883 | ||
884 | } | |
885 | ||
886 | ||
887 | static int kvm_get_fpu(CPUState *env) | |
888 | { | |
889 | struct kvm_fpu fpu; | |
890 | int i, ret; | |
891 | ||
892 | ret = kvm_vcpu_ioctl(env, KVM_GET_FPU, &fpu); | |
b9bec74b | 893 | if (ret < 0) { |
05330448 | 894 | return ret; |
b9bec74b | 895 | } |
05330448 AL |
896 | |
897 | env->fpstt = (fpu.fsw >> 11) & 7; | |
898 | env->fpus = fpu.fsw; | |
899 | env->fpuc = fpu.fcw; | |
b9bec74b JK |
900 | for (i = 0; i < 8; ++i) { |
901 | env->fptags[i] = !((fpu.ftwx >> i) & 1); | |
902 | } | |
05330448 AL |
903 | memcpy(env->fpregs, fpu.fpr, sizeof env->fpregs); |
904 | memcpy(env->xmm_regs, fpu.xmm, sizeof env->xmm_regs); | |
905 | env->mxcsr = fpu.mxcsr; | |
906 | ||
907 | return 0; | |
908 | } | |
909 | ||
f1665b21 SY |
910 | static int kvm_get_xsave(CPUState *env) |
911 | { | |
912 | #ifdef KVM_CAP_XSAVE | |
913 | struct kvm_xsave* xsave; | |
914 | int ret, i; | |
915 | uint16_t cwd, swd, twd, fop; | |
916 | ||
b9bec74b | 917 | if (!kvm_has_xsave()) { |
f1665b21 | 918 | return kvm_get_fpu(env); |
b9bec74b | 919 | } |
f1665b21 SY |
920 | |
921 | xsave = qemu_memalign(4096, sizeof(struct kvm_xsave)); | |
922 | ret = kvm_vcpu_ioctl(env, KVM_GET_XSAVE, xsave); | |
0f53994f MT |
923 | if (ret < 0) { |
924 | qemu_free(xsave); | |
f1665b21 | 925 | return ret; |
0f53994f | 926 | } |
f1665b21 SY |
927 | |
928 | cwd = (uint16_t)xsave->region[0]; | |
929 | swd = (uint16_t)(xsave->region[0] >> 16); | |
930 | twd = (uint16_t)xsave->region[1]; | |
931 | fop = (uint16_t)(xsave->region[1] >> 16); | |
932 | env->fpstt = (swd >> 11) & 7; | |
933 | env->fpus = swd; | |
934 | env->fpuc = cwd; | |
b9bec74b | 935 | for (i = 0; i < 8; ++i) { |
f1665b21 | 936 | env->fptags[i] = !((twd >> i) & 1); |
b9bec74b | 937 | } |
f1665b21 SY |
938 | env->mxcsr = xsave->region[XSAVE_MXCSR]; |
939 | memcpy(env->fpregs, &xsave->region[XSAVE_ST_SPACE], | |
940 | sizeof env->fpregs); | |
941 | memcpy(env->xmm_regs, &xsave->region[XSAVE_XMM_SPACE], | |
942 | sizeof env->xmm_regs); | |
943 | env->xstate_bv = *(uint64_t *)&xsave->region[XSAVE_XSTATE_BV]; | |
944 | memcpy(env->ymmh_regs, &xsave->region[XSAVE_YMMH_SPACE], | |
945 | sizeof env->ymmh_regs); | |
0f53994f | 946 | qemu_free(xsave); |
f1665b21 SY |
947 | return 0; |
948 | #else | |
949 | return kvm_get_fpu(env); | |
950 | #endif | |
951 | } | |
952 | ||
953 | static int kvm_get_xcrs(CPUState *env) | |
954 | { | |
955 | #ifdef KVM_CAP_XCRS | |
956 | int i, ret; | |
957 | struct kvm_xcrs xcrs; | |
958 | ||
b9bec74b | 959 | if (!kvm_has_xcrs()) { |
f1665b21 | 960 | return 0; |
b9bec74b | 961 | } |
f1665b21 SY |
962 | |
963 | ret = kvm_vcpu_ioctl(env, KVM_GET_XCRS, &xcrs); | |
b9bec74b | 964 | if (ret < 0) { |
f1665b21 | 965 | return ret; |
b9bec74b | 966 | } |
f1665b21 | 967 | |
b9bec74b | 968 | for (i = 0; i < xcrs.nr_xcrs; i++) { |
f1665b21 SY |
969 | /* Only support xcr0 now */ |
970 | if (xcrs.xcrs[0].xcr == 0) { | |
971 | env->xcr0 = xcrs.xcrs[0].value; | |
972 | break; | |
973 | } | |
b9bec74b | 974 | } |
f1665b21 SY |
975 | return 0; |
976 | #else | |
977 | return 0; | |
978 | #endif | |
979 | } | |
980 | ||
05330448 AL |
981 | static int kvm_get_sregs(CPUState *env) |
982 | { | |
983 | struct kvm_sregs sregs; | |
984 | uint32_t hflags; | |
0e607a80 | 985 | int bit, i, ret; |
05330448 AL |
986 | |
987 | ret = kvm_vcpu_ioctl(env, KVM_GET_SREGS, &sregs); | |
b9bec74b | 988 | if (ret < 0) { |
05330448 | 989 | return ret; |
b9bec74b | 990 | } |
05330448 | 991 | |
0e607a80 JK |
992 | /* There can only be one pending IRQ set in the bitmap at a time, so try |
993 | to find it and save its number instead (-1 for none). */ | |
994 | env->interrupt_injected = -1; | |
995 | for (i = 0; i < ARRAY_SIZE(sregs.interrupt_bitmap); i++) { | |
996 | if (sregs.interrupt_bitmap[i]) { | |
997 | bit = ctz64(sregs.interrupt_bitmap[i]); | |
998 | env->interrupt_injected = i * 64 + bit; | |
999 | break; | |
1000 | } | |
1001 | } | |
05330448 AL |
1002 | |
1003 | get_seg(&env->segs[R_CS], &sregs.cs); | |
1004 | get_seg(&env->segs[R_DS], &sregs.ds); | |
1005 | get_seg(&env->segs[R_ES], &sregs.es); | |
1006 | get_seg(&env->segs[R_FS], &sregs.fs); | |
1007 | get_seg(&env->segs[R_GS], &sregs.gs); | |
1008 | get_seg(&env->segs[R_SS], &sregs.ss); | |
1009 | ||
1010 | get_seg(&env->tr, &sregs.tr); | |
1011 | get_seg(&env->ldt, &sregs.ldt); | |
1012 | ||
1013 | env->idt.limit = sregs.idt.limit; | |
1014 | env->idt.base = sregs.idt.base; | |
1015 | env->gdt.limit = sregs.gdt.limit; | |
1016 | env->gdt.base = sregs.gdt.base; | |
1017 | ||
1018 | env->cr[0] = sregs.cr0; | |
1019 | env->cr[2] = sregs.cr2; | |
1020 | env->cr[3] = sregs.cr3; | |
1021 | env->cr[4] = sregs.cr4; | |
1022 | ||
4a942cea | 1023 | cpu_set_apic_base(env->apic_state, sregs.apic_base); |
05330448 AL |
1024 | |
1025 | env->efer = sregs.efer; | |
4a942cea | 1026 | //cpu_set_apic_tpr(env->apic_state, sregs.cr8); |
05330448 | 1027 | |
b9bec74b JK |
1028 | #define HFLAG_COPY_MASK \ |
1029 | ~( HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \ | |
1030 | HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \ | |
1031 | HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \ | |
1032 | HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK) | |
05330448 AL |
1033 | |
1034 | hflags = (env->segs[R_CS].flags >> DESC_DPL_SHIFT) & HF_CPL_MASK; | |
1035 | hflags |= (env->cr[0] & CR0_PE_MASK) << (HF_PE_SHIFT - CR0_PE_SHIFT); | |
1036 | hflags |= (env->cr[0] << (HF_MP_SHIFT - CR0_MP_SHIFT)) & | |
b9bec74b | 1037 | (HF_MP_MASK | HF_EM_MASK | HF_TS_MASK); |
05330448 AL |
1038 | hflags |= (env->eflags & (HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK)); |
1039 | hflags |= (env->cr[4] & CR4_OSFXSR_MASK) << | |
b9bec74b | 1040 | (HF_OSFXSR_SHIFT - CR4_OSFXSR_SHIFT); |
05330448 AL |
1041 | |
1042 | if (env->efer & MSR_EFER_LMA) { | |
1043 | hflags |= HF_LMA_MASK; | |
1044 | } | |
1045 | ||
1046 | if ((hflags & HF_LMA_MASK) && (env->segs[R_CS].flags & DESC_L_MASK)) { | |
1047 | hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK; | |
1048 | } else { | |
1049 | hflags |= (env->segs[R_CS].flags & DESC_B_MASK) >> | |
b9bec74b | 1050 | (DESC_B_SHIFT - HF_CS32_SHIFT); |
05330448 | 1051 | hflags |= (env->segs[R_SS].flags & DESC_B_MASK) >> |
b9bec74b JK |
1052 | (DESC_B_SHIFT - HF_SS32_SHIFT); |
1053 | if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK) || | |
1054 | !(hflags & HF_CS32_MASK)) { | |
1055 | hflags |= HF_ADDSEG_MASK; | |
1056 | } else { | |
1057 | hflags |= ((env->segs[R_DS].base | env->segs[R_ES].base | | |
1058 | env->segs[R_SS].base) != 0) << HF_ADDSEG_SHIFT; | |
1059 | } | |
05330448 AL |
1060 | } |
1061 | env->hflags = (env->hflags & HFLAG_COPY_MASK) | hflags; | |
05330448 AL |
1062 | |
1063 | return 0; | |
1064 | } | |
1065 | ||
1066 | static int kvm_get_msrs(CPUState *env) | |
1067 | { | |
1068 | struct { | |
1069 | struct kvm_msrs info; | |
1070 | struct kvm_msr_entry entries[100]; | |
1071 | } msr_data; | |
1072 | struct kvm_msr_entry *msrs = msr_data.entries; | |
1073 | int ret, i, n; | |
1074 | ||
1075 | n = 0; | |
1076 | msrs[n++].index = MSR_IA32_SYSENTER_CS; | |
1077 | msrs[n++].index = MSR_IA32_SYSENTER_ESP; | |
1078 | msrs[n++].index = MSR_IA32_SYSENTER_EIP; | |
c3a3a7d3 | 1079 | if (has_msr_star) { |
b9bec74b JK |
1080 | msrs[n++].index = MSR_STAR; |
1081 | } | |
c3a3a7d3 | 1082 | if (has_msr_hsave_pa) { |
75b10c43 | 1083 | msrs[n++].index = MSR_VM_HSAVE_PA; |
b9bec74b | 1084 | } |
b8cc45d6 GC |
1085 | |
1086 | if (!env->tsc_valid) { | |
1087 | msrs[n++].index = MSR_IA32_TSC; | |
1088 | env->tsc_valid = !vm_running; | |
1089 | } | |
1090 | ||
05330448 | 1091 | #ifdef TARGET_X86_64 |
25d2e361 MT |
1092 | if (lm_capable_kernel) { |
1093 | msrs[n++].index = MSR_CSTAR; | |
1094 | msrs[n++].index = MSR_KERNELGSBASE; | |
1095 | msrs[n++].index = MSR_FMASK; | |
1096 | msrs[n++].index = MSR_LSTAR; | |
1097 | } | |
05330448 | 1098 | #endif |
1a03675d GC |
1099 | msrs[n++].index = MSR_KVM_SYSTEM_TIME; |
1100 | msrs[n++].index = MSR_KVM_WALL_CLOCK; | |
521f0798 | 1101 | #if defined(CONFIG_KVM_PARA) && defined(KVM_CAP_ASYNC_PF) |
c5999bfc JK |
1102 | if (has_msr_async_pf_en) { |
1103 | msrs[n++].index = MSR_KVM_ASYNC_PF_EN; | |
1104 | } | |
f6584ee2 | 1105 | #endif |
1a03675d | 1106 | |
57780495 MT |
1107 | #ifdef KVM_CAP_MCE |
1108 | if (env->mcg_cap) { | |
1109 | msrs[n++].index = MSR_MCG_STATUS; | |
1110 | msrs[n++].index = MSR_MCG_CTL; | |
b9bec74b | 1111 | for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) { |
57780495 | 1112 | msrs[n++].index = MSR_MC0_CTL + i; |
b9bec74b | 1113 | } |
57780495 MT |
1114 | } |
1115 | #endif | |
1116 | ||
05330448 AL |
1117 | msr_data.info.nmsrs = n; |
1118 | ret = kvm_vcpu_ioctl(env, KVM_GET_MSRS, &msr_data); | |
b9bec74b | 1119 | if (ret < 0) { |
05330448 | 1120 | return ret; |
b9bec74b | 1121 | } |
05330448 AL |
1122 | |
1123 | for (i = 0; i < ret; i++) { | |
1124 | switch (msrs[i].index) { | |
1125 | case MSR_IA32_SYSENTER_CS: | |
1126 | env->sysenter_cs = msrs[i].data; | |
1127 | break; | |
1128 | case MSR_IA32_SYSENTER_ESP: | |
1129 | env->sysenter_esp = msrs[i].data; | |
1130 | break; | |
1131 | case MSR_IA32_SYSENTER_EIP: | |
1132 | env->sysenter_eip = msrs[i].data; | |
1133 | break; | |
1134 | case MSR_STAR: | |
1135 | env->star = msrs[i].data; | |
1136 | break; | |
1137 | #ifdef TARGET_X86_64 | |
1138 | case MSR_CSTAR: | |
1139 | env->cstar = msrs[i].data; | |
1140 | break; | |
1141 | case MSR_KERNELGSBASE: | |
1142 | env->kernelgsbase = msrs[i].data; | |
1143 | break; | |
1144 | case MSR_FMASK: | |
1145 | env->fmask = msrs[i].data; | |
1146 | break; | |
1147 | case MSR_LSTAR: | |
1148 | env->lstar = msrs[i].data; | |
1149 | break; | |
1150 | #endif | |
1151 | case MSR_IA32_TSC: | |
1152 | env->tsc = msrs[i].data; | |
1153 | break; | |
aa851e36 MT |
1154 | case MSR_VM_HSAVE_PA: |
1155 | env->vm_hsave = msrs[i].data; | |
1156 | break; | |
1a03675d GC |
1157 | case MSR_KVM_SYSTEM_TIME: |
1158 | env->system_time_msr = msrs[i].data; | |
1159 | break; | |
1160 | case MSR_KVM_WALL_CLOCK: | |
1161 | env->wall_clock_msr = msrs[i].data; | |
1162 | break; | |
57780495 MT |
1163 | #ifdef KVM_CAP_MCE |
1164 | case MSR_MCG_STATUS: | |
1165 | env->mcg_status = msrs[i].data; | |
1166 | break; | |
1167 | case MSR_MCG_CTL: | |
1168 | env->mcg_ctl = msrs[i].data; | |
1169 | break; | |
1170 | #endif | |
1171 | default: | |
1172 | #ifdef KVM_CAP_MCE | |
1173 | if (msrs[i].index >= MSR_MC0_CTL && | |
1174 | msrs[i].index < MSR_MC0_CTL + (env->mcg_cap & 0xff) * 4) { | |
1175 | env->mce_banks[msrs[i].index - MSR_MC0_CTL] = msrs[i].data; | |
57780495 MT |
1176 | } |
1177 | #endif | |
d8da8574 | 1178 | break; |
521f0798 | 1179 | #if defined(CONFIG_KVM_PARA) && defined(KVM_CAP_ASYNC_PF) |
f6584ee2 GN |
1180 | case MSR_KVM_ASYNC_PF_EN: |
1181 | env->async_pf_en_msr = msrs[i].data; | |
1182 | break; | |
1183 | #endif | |
05330448 AL |
1184 | } |
1185 | } | |
1186 | ||
1187 | return 0; | |
1188 | } | |
1189 | ||
9bdbe550 HB |
1190 | static int kvm_put_mp_state(CPUState *env) |
1191 | { | |
1192 | struct kvm_mp_state mp_state = { .mp_state = env->mp_state }; | |
1193 | ||
1194 | return kvm_vcpu_ioctl(env, KVM_SET_MP_STATE, &mp_state); | |
1195 | } | |
1196 | ||
1197 | static int kvm_get_mp_state(CPUState *env) | |
1198 | { | |
1199 | struct kvm_mp_state mp_state; | |
1200 | int ret; | |
1201 | ||
1202 | ret = kvm_vcpu_ioctl(env, KVM_GET_MP_STATE, &mp_state); | |
1203 | if (ret < 0) { | |
1204 | return ret; | |
1205 | } | |
1206 | env->mp_state = mp_state.mp_state; | |
c14750e8 JK |
1207 | if (kvm_irqchip_in_kernel()) { |
1208 | env->halted = (mp_state.mp_state == KVM_MP_STATE_HALTED); | |
1209 | } | |
9bdbe550 HB |
1210 | return 0; |
1211 | } | |
1212 | ||
ea643051 | 1213 | static int kvm_put_vcpu_events(CPUState *env, int level) |
a0fb002c JK |
1214 | { |
1215 | #ifdef KVM_CAP_VCPU_EVENTS | |
1216 | struct kvm_vcpu_events events; | |
1217 | ||
1218 | if (!kvm_has_vcpu_events()) { | |
1219 | return 0; | |
1220 | } | |
1221 | ||
31827373 JK |
1222 | events.exception.injected = (env->exception_injected >= 0); |
1223 | events.exception.nr = env->exception_injected; | |
a0fb002c JK |
1224 | events.exception.has_error_code = env->has_error_code; |
1225 | events.exception.error_code = env->error_code; | |
1226 | ||
1227 | events.interrupt.injected = (env->interrupt_injected >= 0); | |
1228 | events.interrupt.nr = env->interrupt_injected; | |
1229 | events.interrupt.soft = env->soft_interrupt; | |
1230 | ||
1231 | events.nmi.injected = env->nmi_injected; | |
1232 | events.nmi.pending = env->nmi_pending; | |
1233 | events.nmi.masked = !!(env->hflags2 & HF2_NMI_MASK); | |
1234 | ||
1235 | events.sipi_vector = env->sipi_vector; | |
1236 | ||
ea643051 JK |
1237 | events.flags = 0; |
1238 | if (level >= KVM_PUT_RESET_STATE) { | |
1239 | events.flags |= | |
1240 | KVM_VCPUEVENT_VALID_NMI_PENDING | KVM_VCPUEVENT_VALID_SIPI_VECTOR; | |
1241 | } | |
aee028b9 | 1242 | |
a0fb002c JK |
1243 | return kvm_vcpu_ioctl(env, KVM_SET_VCPU_EVENTS, &events); |
1244 | #else | |
1245 | return 0; | |
1246 | #endif | |
1247 | } | |
1248 | ||
1249 | static int kvm_get_vcpu_events(CPUState *env) | |
1250 | { | |
1251 | #ifdef KVM_CAP_VCPU_EVENTS | |
1252 | struct kvm_vcpu_events events; | |
1253 | int ret; | |
1254 | ||
1255 | if (!kvm_has_vcpu_events()) { | |
1256 | return 0; | |
1257 | } | |
1258 | ||
1259 | ret = kvm_vcpu_ioctl(env, KVM_GET_VCPU_EVENTS, &events); | |
1260 | if (ret < 0) { | |
1261 | return ret; | |
1262 | } | |
31827373 | 1263 | env->exception_injected = |
a0fb002c JK |
1264 | events.exception.injected ? events.exception.nr : -1; |
1265 | env->has_error_code = events.exception.has_error_code; | |
1266 | env->error_code = events.exception.error_code; | |
1267 | ||
1268 | env->interrupt_injected = | |
1269 | events.interrupt.injected ? events.interrupt.nr : -1; | |
1270 | env->soft_interrupt = events.interrupt.soft; | |
1271 | ||
1272 | env->nmi_injected = events.nmi.injected; | |
1273 | env->nmi_pending = events.nmi.pending; | |
1274 | if (events.nmi.masked) { | |
1275 | env->hflags2 |= HF2_NMI_MASK; | |
1276 | } else { | |
1277 | env->hflags2 &= ~HF2_NMI_MASK; | |
1278 | } | |
1279 | ||
1280 | env->sipi_vector = events.sipi_vector; | |
1281 | #endif | |
1282 | ||
1283 | return 0; | |
1284 | } | |
1285 | ||
b0b1d690 JK |
1286 | static int kvm_guest_debug_workarounds(CPUState *env) |
1287 | { | |
1288 | int ret = 0; | |
1289 | #ifdef KVM_CAP_SET_GUEST_DEBUG | |
1290 | unsigned long reinject_trap = 0; | |
1291 | ||
1292 | if (!kvm_has_vcpu_events()) { | |
1293 | if (env->exception_injected == 1) { | |
1294 | reinject_trap = KVM_GUESTDBG_INJECT_DB; | |
1295 | } else if (env->exception_injected == 3) { | |
1296 | reinject_trap = KVM_GUESTDBG_INJECT_BP; | |
1297 | } | |
1298 | env->exception_injected = -1; | |
1299 | } | |
1300 | ||
1301 | /* | |
1302 | * Kernels before KVM_CAP_X86_ROBUST_SINGLESTEP overwrote flags.TF | |
1303 | * injected via SET_GUEST_DEBUG while updating GP regs. Work around this | |
1304 | * by updating the debug state once again if single-stepping is on. | |
1305 | * Another reason to call kvm_update_guest_debug here is a pending debug | |
1306 | * trap raise by the guest. On kernels without SET_VCPU_EVENTS we have to | |
1307 | * reinject them via SET_GUEST_DEBUG. | |
1308 | */ | |
1309 | if (reinject_trap || | |
1310 | (!kvm_has_robust_singlestep() && env->singlestep_enabled)) { | |
1311 | ret = kvm_update_guest_debug(env, reinject_trap); | |
1312 | } | |
1313 | #endif /* KVM_CAP_SET_GUEST_DEBUG */ | |
1314 | return ret; | |
1315 | } | |
1316 | ||
ff44f1a3 JK |
1317 | static int kvm_put_debugregs(CPUState *env) |
1318 | { | |
1319 | #ifdef KVM_CAP_DEBUGREGS | |
1320 | struct kvm_debugregs dbgregs; | |
1321 | int i; | |
1322 | ||
1323 | if (!kvm_has_debugregs()) { | |
1324 | return 0; | |
1325 | } | |
1326 | ||
1327 | for (i = 0; i < 4; i++) { | |
1328 | dbgregs.db[i] = env->dr[i]; | |
1329 | } | |
1330 | dbgregs.dr6 = env->dr[6]; | |
1331 | dbgregs.dr7 = env->dr[7]; | |
1332 | dbgregs.flags = 0; | |
1333 | ||
1334 | return kvm_vcpu_ioctl(env, KVM_SET_DEBUGREGS, &dbgregs); | |
1335 | #else | |
1336 | return 0; | |
1337 | #endif | |
1338 | } | |
1339 | ||
1340 | static int kvm_get_debugregs(CPUState *env) | |
1341 | { | |
1342 | #ifdef KVM_CAP_DEBUGREGS | |
1343 | struct kvm_debugregs dbgregs; | |
1344 | int i, ret; | |
1345 | ||
1346 | if (!kvm_has_debugregs()) { | |
1347 | return 0; | |
1348 | } | |
1349 | ||
1350 | ret = kvm_vcpu_ioctl(env, KVM_GET_DEBUGREGS, &dbgregs); | |
1351 | if (ret < 0) { | |
b9bec74b | 1352 | return ret; |
ff44f1a3 JK |
1353 | } |
1354 | for (i = 0; i < 4; i++) { | |
1355 | env->dr[i] = dbgregs.db[i]; | |
1356 | } | |
1357 | env->dr[4] = env->dr[6] = dbgregs.dr6; | |
1358 | env->dr[5] = env->dr[7] = dbgregs.dr7; | |
1359 | #endif | |
1360 | ||
1361 | return 0; | |
1362 | } | |
1363 | ||
ea375f9a | 1364 | int kvm_arch_put_registers(CPUState *env, int level) |
05330448 AL |
1365 | { |
1366 | int ret; | |
1367 | ||
b7680cb6 | 1368 | assert(cpu_is_stopped(env) || qemu_cpu_is_self(env)); |
dbaa07c4 | 1369 | |
05330448 | 1370 | ret = kvm_getput_regs(env, 1); |
b9bec74b | 1371 | if (ret < 0) { |
05330448 | 1372 | return ret; |
b9bec74b | 1373 | } |
f1665b21 | 1374 | ret = kvm_put_xsave(env); |
b9bec74b | 1375 | if (ret < 0) { |
f1665b21 | 1376 | return ret; |
b9bec74b | 1377 | } |
f1665b21 | 1378 | ret = kvm_put_xcrs(env); |
b9bec74b | 1379 | if (ret < 0) { |
05330448 | 1380 | return ret; |
b9bec74b | 1381 | } |
05330448 | 1382 | ret = kvm_put_sregs(env); |
b9bec74b | 1383 | if (ret < 0) { |
05330448 | 1384 | return ret; |
b9bec74b | 1385 | } |
ab443475 JK |
1386 | /* must be before kvm_put_msrs */ |
1387 | ret = kvm_inject_mce_oldstyle(env); | |
1388 | if (ret < 0) { | |
1389 | return ret; | |
1390 | } | |
ea643051 | 1391 | ret = kvm_put_msrs(env, level); |
b9bec74b | 1392 | if (ret < 0) { |
05330448 | 1393 | return ret; |
b9bec74b | 1394 | } |
ea643051 JK |
1395 | if (level >= KVM_PUT_RESET_STATE) { |
1396 | ret = kvm_put_mp_state(env); | |
b9bec74b | 1397 | if (ret < 0) { |
ea643051 | 1398 | return ret; |
b9bec74b | 1399 | } |
ea643051 | 1400 | } |
ea643051 | 1401 | ret = kvm_put_vcpu_events(env, level); |
b9bec74b | 1402 | if (ret < 0) { |
a0fb002c | 1403 | return ret; |
b9bec74b | 1404 | } |
0d75a9ec | 1405 | ret = kvm_put_debugregs(env); |
b9bec74b | 1406 | if (ret < 0) { |
b0b1d690 | 1407 | return ret; |
b9bec74b | 1408 | } |
b0b1d690 JK |
1409 | /* must be last */ |
1410 | ret = kvm_guest_debug_workarounds(env); | |
b9bec74b | 1411 | if (ret < 0) { |
ff44f1a3 | 1412 | return ret; |
b9bec74b | 1413 | } |
05330448 AL |
1414 | return 0; |
1415 | } | |
1416 | ||
1417 | int kvm_arch_get_registers(CPUState *env) | |
1418 | { | |
1419 | int ret; | |
1420 | ||
b7680cb6 | 1421 | assert(cpu_is_stopped(env) || qemu_cpu_is_self(env)); |
dbaa07c4 | 1422 | |
05330448 | 1423 | ret = kvm_getput_regs(env, 0); |
b9bec74b | 1424 | if (ret < 0) { |
05330448 | 1425 | return ret; |
b9bec74b | 1426 | } |
f1665b21 | 1427 | ret = kvm_get_xsave(env); |
b9bec74b | 1428 | if (ret < 0) { |
f1665b21 | 1429 | return ret; |
b9bec74b | 1430 | } |
f1665b21 | 1431 | ret = kvm_get_xcrs(env); |
b9bec74b | 1432 | if (ret < 0) { |
05330448 | 1433 | return ret; |
b9bec74b | 1434 | } |
05330448 | 1435 | ret = kvm_get_sregs(env); |
b9bec74b | 1436 | if (ret < 0) { |
05330448 | 1437 | return ret; |
b9bec74b | 1438 | } |
05330448 | 1439 | ret = kvm_get_msrs(env); |
b9bec74b | 1440 | if (ret < 0) { |
05330448 | 1441 | return ret; |
b9bec74b | 1442 | } |
5a2e3c2e | 1443 | ret = kvm_get_mp_state(env); |
b9bec74b | 1444 | if (ret < 0) { |
5a2e3c2e | 1445 | return ret; |
b9bec74b | 1446 | } |
a0fb002c | 1447 | ret = kvm_get_vcpu_events(env); |
b9bec74b | 1448 | if (ret < 0) { |
a0fb002c | 1449 | return ret; |
b9bec74b | 1450 | } |
ff44f1a3 | 1451 | ret = kvm_get_debugregs(env); |
b9bec74b | 1452 | if (ret < 0) { |
ff44f1a3 | 1453 | return ret; |
b9bec74b | 1454 | } |
05330448 AL |
1455 | return 0; |
1456 | } | |
1457 | ||
7a39fe58 | 1458 | void kvm_arch_pre_run(CPUState *env, struct kvm_run *run) |
05330448 | 1459 | { |
ce377af3 JK |
1460 | int ret; |
1461 | ||
276ce815 LJ |
1462 | /* Inject NMI */ |
1463 | if (env->interrupt_request & CPU_INTERRUPT_NMI) { | |
1464 | env->interrupt_request &= ~CPU_INTERRUPT_NMI; | |
1465 | DPRINTF("injected NMI\n"); | |
ce377af3 JK |
1466 | ret = kvm_vcpu_ioctl(env, KVM_NMI); |
1467 | if (ret < 0) { | |
1468 | fprintf(stderr, "KVM: injection failed, NMI lost (%s)\n", | |
1469 | strerror(-ret)); | |
1470 | } | |
276ce815 LJ |
1471 | } |
1472 | ||
db1669bc JK |
1473 | if (!kvm_irqchip_in_kernel()) { |
1474 | /* Force the VCPU out of its inner loop to process the INIT request */ | |
1475 | if (env->interrupt_request & CPU_INTERRUPT_INIT) { | |
1476 | env->exit_request = 1; | |
05330448 | 1477 | } |
05330448 | 1478 | |
db1669bc JK |
1479 | /* Try to inject an interrupt if the guest can accept it */ |
1480 | if (run->ready_for_interrupt_injection && | |
1481 | (env->interrupt_request & CPU_INTERRUPT_HARD) && | |
1482 | (env->eflags & IF_MASK)) { | |
1483 | int irq; | |
1484 | ||
1485 | env->interrupt_request &= ~CPU_INTERRUPT_HARD; | |
1486 | irq = cpu_get_pic_interrupt(env); | |
1487 | if (irq >= 0) { | |
1488 | struct kvm_interrupt intr; | |
1489 | ||
1490 | intr.irq = irq; | |
db1669bc | 1491 | DPRINTF("injected interrupt %d\n", irq); |
ce377af3 JK |
1492 | ret = kvm_vcpu_ioctl(env, KVM_INTERRUPT, &intr); |
1493 | if (ret < 0) { | |
1494 | fprintf(stderr, | |
1495 | "KVM: injection failed, interrupt lost (%s)\n", | |
1496 | strerror(-ret)); | |
1497 | } | |
db1669bc JK |
1498 | } |
1499 | } | |
05330448 | 1500 | |
db1669bc JK |
1501 | /* If we have an interrupt but the guest is not ready to receive an |
1502 | * interrupt, request an interrupt window exit. This will | |
1503 | * cause a return to userspace as soon as the guest is ready to | |
1504 | * receive interrupts. */ | |
1505 | if ((env->interrupt_request & CPU_INTERRUPT_HARD)) { | |
1506 | run->request_interrupt_window = 1; | |
1507 | } else { | |
1508 | run->request_interrupt_window = 0; | |
1509 | } | |
1510 | ||
1511 | DPRINTF("setting tpr\n"); | |
1512 | run->cr8 = cpu_get_apic_tpr(env->apic_state); | |
1513 | } | |
05330448 AL |
1514 | } |
1515 | ||
7a39fe58 | 1516 | void kvm_arch_post_run(CPUState *env, struct kvm_run *run) |
05330448 | 1517 | { |
b9bec74b | 1518 | if (run->if_flag) { |
05330448 | 1519 | env->eflags |= IF_MASK; |
b9bec74b | 1520 | } else { |
05330448 | 1521 | env->eflags &= ~IF_MASK; |
b9bec74b | 1522 | } |
4a942cea BS |
1523 | cpu_set_apic_tpr(env->apic_state, run->cr8); |
1524 | cpu_set_apic_base(env->apic_state, run->apic_base); | |
05330448 AL |
1525 | } |
1526 | ||
99036865 | 1527 | int kvm_arch_process_async_events(CPUState *env) |
0af691d7 | 1528 | { |
ab443475 JK |
1529 | if (env->interrupt_request & CPU_INTERRUPT_MCE) { |
1530 | /* We must not raise CPU_INTERRUPT_MCE if it's not supported. */ | |
1531 | assert(env->mcg_cap); | |
1532 | ||
1533 | env->interrupt_request &= ~CPU_INTERRUPT_MCE; | |
1534 | ||
1535 | kvm_cpu_synchronize_state(env); | |
1536 | ||
1537 | if (env->exception_injected == EXCP08_DBLE) { | |
1538 | /* this means triple fault */ | |
1539 | qemu_system_reset_request(); | |
1540 | env->exit_request = 1; | |
1541 | return 0; | |
1542 | } | |
1543 | env->exception_injected = EXCP12_MCHK; | |
1544 | env->has_error_code = 0; | |
1545 | ||
1546 | env->halted = 0; | |
1547 | if (kvm_irqchip_in_kernel() && env->mp_state == KVM_MP_STATE_HALTED) { | |
1548 | env->mp_state = KVM_MP_STATE_RUNNABLE; | |
1549 | } | |
1550 | } | |
1551 | ||
db1669bc JK |
1552 | if (kvm_irqchip_in_kernel()) { |
1553 | return 0; | |
1554 | } | |
1555 | ||
6792a57b JK |
1556 | if (env->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_NMI)) { |
1557 | env->halted = 0; | |
1558 | } | |
0af691d7 MT |
1559 | if (env->interrupt_request & CPU_INTERRUPT_INIT) { |
1560 | kvm_cpu_synchronize_state(env); | |
1561 | do_cpu_init(env); | |
0af691d7 | 1562 | } |
0af691d7 MT |
1563 | if (env->interrupt_request & CPU_INTERRUPT_SIPI) { |
1564 | kvm_cpu_synchronize_state(env); | |
1565 | do_cpu_sipi(env); | |
1566 | } | |
1567 | ||
1568 | return env->halted; | |
1569 | } | |
1570 | ||
05330448 AL |
1571 | static int kvm_handle_halt(CPUState *env) |
1572 | { | |
1573 | if (!((env->interrupt_request & CPU_INTERRUPT_HARD) && | |
1574 | (env->eflags & IF_MASK)) && | |
1575 | !(env->interrupt_request & CPU_INTERRUPT_NMI)) { | |
1576 | env->halted = 1; | |
05330448 AL |
1577 | return 0; |
1578 | } | |
1579 | ||
1580 | return 1; | |
1581 | } | |
1582 | ||
bb44e0d1 JK |
1583 | static bool host_supports_vmx(void) |
1584 | { | |
1585 | uint32_t ecx, unused; | |
1586 | ||
1587 | host_cpuid(1, 0, &unused, &unused, &ecx, &unused); | |
1588 | return ecx & CPUID_EXT_VMX; | |
1589 | } | |
1590 | ||
1591 | #define VMX_INVALID_GUEST_STATE 0x80000021 | |
1592 | ||
05330448 AL |
1593 | int kvm_arch_handle_exit(CPUState *env, struct kvm_run *run) |
1594 | { | |
bb44e0d1 | 1595 | uint64_t code; |
05330448 AL |
1596 | int ret = 0; |
1597 | ||
1598 | switch (run->exit_reason) { | |
1599 | case KVM_EXIT_HLT: | |
8c0d577e | 1600 | DPRINTF("handle_hlt\n"); |
05330448 AL |
1601 | ret = kvm_handle_halt(env); |
1602 | break; | |
646042e1 JK |
1603 | case KVM_EXIT_SET_TPR: |
1604 | ret = 1; | |
1605 | break; | |
bb44e0d1 JK |
1606 | case KVM_EXIT_FAIL_ENTRY: |
1607 | code = run->fail_entry.hardware_entry_failure_reason; | |
1608 | fprintf(stderr, "KVM: entry failed, hardware error 0x%" PRIx64 "\n", | |
1609 | code); | |
1610 | if (host_supports_vmx() && code == VMX_INVALID_GUEST_STATE) { | |
1611 | fprintf(stderr, | |
1612 | "\nIf you're runnning a guest on an Intel machine without " | |
1613 | "unrestricted mode\n" | |
1614 | "support, the failure can be most likely due to the guest " | |
1615 | "entering an invalid\n" | |
1616 | "state for Intel VT. For example, the guest maybe running " | |
1617 | "in big real mode\n" | |
1618 | "which is not supported on less recent Intel processors." | |
1619 | "\n\n"); | |
1620 | } | |
1621 | ret = -1; | |
1622 | break; | |
1623 | case KVM_EXIT_EXCEPTION: | |
1624 | fprintf(stderr, "KVM: exception %d exit (error code 0x%x)\n", | |
1625 | run->ex.exception, run->ex.error_code); | |
1626 | ret = -1; | |
1627 | break; | |
73aaec4a JK |
1628 | default: |
1629 | fprintf(stderr, "KVM: unknown exit reason %d\n", run->exit_reason); | |
1630 | ret = -1; | |
1631 | break; | |
05330448 AL |
1632 | } |
1633 | ||
1634 | return ret; | |
1635 | } | |
e22a25c9 AL |
1636 | |
1637 | #ifdef KVM_CAP_SET_GUEST_DEBUG | |
e22a25c9 AL |
1638 | int kvm_arch_insert_sw_breakpoint(CPUState *env, struct kvm_sw_breakpoint *bp) |
1639 | { | |
38972938 | 1640 | static const uint8_t int3 = 0xcc; |
64bf3f4e | 1641 | |
e22a25c9 | 1642 | if (cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&bp->saved_insn, 1, 0) || |
b9bec74b | 1643 | cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&int3, 1, 1)) { |
e22a25c9 | 1644 | return -EINVAL; |
b9bec74b | 1645 | } |
e22a25c9 AL |
1646 | return 0; |
1647 | } | |
1648 | ||
1649 | int kvm_arch_remove_sw_breakpoint(CPUState *env, struct kvm_sw_breakpoint *bp) | |
1650 | { | |
1651 | uint8_t int3; | |
1652 | ||
1653 | if (cpu_memory_rw_debug(env, bp->pc, &int3, 1, 0) || int3 != 0xcc || | |
b9bec74b | 1654 | cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&bp->saved_insn, 1, 1)) { |
e22a25c9 | 1655 | return -EINVAL; |
b9bec74b | 1656 | } |
e22a25c9 AL |
1657 | return 0; |
1658 | } | |
1659 | ||
1660 | static struct { | |
1661 | target_ulong addr; | |
1662 | int len; | |
1663 | int type; | |
1664 | } hw_breakpoint[4]; | |
1665 | ||
1666 | static int nb_hw_breakpoint; | |
1667 | ||
1668 | static int find_hw_breakpoint(target_ulong addr, int len, int type) | |
1669 | { | |
1670 | int n; | |
1671 | ||
b9bec74b | 1672 | for (n = 0; n < nb_hw_breakpoint; n++) { |
e22a25c9 | 1673 | if (hw_breakpoint[n].addr == addr && hw_breakpoint[n].type == type && |
b9bec74b | 1674 | (hw_breakpoint[n].len == len || len == -1)) { |
e22a25c9 | 1675 | return n; |
b9bec74b JK |
1676 | } |
1677 | } | |
e22a25c9 AL |
1678 | return -1; |
1679 | } | |
1680 | ||
1681 | int kvm_arch_insert_hw_breakpoint(target_ulong addr, | |
1682 | target_ulong len, int type) | |
1683 | { | |
1684 | switch (type) { | |
1685 | case GDB_BREAKPOINT_HW: | |
1686 | len = 1; | |
1687 | break; | |
1688 | case GDB_WATCHPOINT_WRITE: | |
1689 | case GDB_WATCHPOINT_ACCESS: | |
1690 | switch (len) { | |
1691 | case 1: | |
1692 | break; | |
1693 | case 2: | |
1694 | case 4: | |
1695 | case 8: | |
b9bec74b | 1696 | if (addr & (len - 1)) { |
e22a25c9 | 1697 | return -EINVAL; |
b9bec74b | 1698 | } |
e22a25c9 AL |
1699 | break; |
1700 | default: | |
1701 | return -EINVAL; | |
1702 | } | |
1703 | break; | |
1704 | default: | |
1705 | return -ENOSYS; | |
1706 | } | |
1707 | ||
b9bec74b | 1708 | if (nb_hw_breakpoint == 4) { |
e22a25c9 | 1709 | return -ENOBUFS; |
b9bec74b JK |
1710 | } |
1711 | if (find_hw_breakpoint(addr, len, type) >= 0) { | |
e22a25c9 | 1712 | return -EEXIST; |
b9bec74b | 1713 | } |
e22a25c9 AL |
1714 | hw_breakpoint[nb_hw_breakpoint].addr = addr; |
1715 | hw_breakpoint[nb_hw_breakpoint].len = len; | |
1716 | hw_breakpoint[nb_hw_breakpoint].type = type; | |
1717 | nb_hw_breakpoint++; | |
1718 | ||
1719 | return 0; | |
1720 | } | |
1721 | ||
1722 | int kvm_arch_remove_hw_breakpoint(target_ulong addr, | |
1723 | target_ulong len, int type) | |
1724 | { | |
1725 | int n; | |
1726 | ||
1727 | n = find_hw_breakpoint(addr, (type == GDB_BREAKPOINT_HW) ? 1 : len, type); | |
b9bec74b | 1728 | if (n < 0) { |
e22a25c9 | 1729 | return -ENOENT; |
b9bec74b | 1730 | } |
e22a25c9 AL |
1731 | nb_hw_breakpoint--; |
1732 | hw_breakpoint[n] = hw_breakpoint[nb_hw_breakpoint]; | |
1733 | ||
1734 | return 0; | |
1735 | } | |
1736 | ||
1737 | void kvm_arch_remove_all_hw_breakpoints(void) | |
1738 | { | |
1739 | nb_hw_breakpoint = 0; | |
1740 | } | |
1741 | ||
1742 | static CPUWatchpoint hw_watchpoint; | |
1743 | ||
1744 | int kvm_arch_debug(struct kvm_debug_exit_arch *arch_info) | |
1745 | { | |
1746 | int handle = 0; | |
1747 | int n; | |
1748 | ||
1749 | if (arch_info->exception == 1) { | |
1750 | if (arch_info->dr6 & (1 << 14)) { | |
b9bec74b | 1751 | if (cpu_single_env->singlestep_enabled) { |
e22a25c9 | 1752 | handle = 1; |
b9bec74b | 1753 | } |
e22a25c9 | 1754 | } else { |
b9bec74b JK |
1755 | for (n = 0; n < 4; n++) { |
1756 | if (arch_info->dr6 & (1 << n)) { | |
e22a25c9 AL |
1757 | switch ((arch_info->dr7 >> (16 + n*4)) & 0x3) { |
1758 | case 0x0: | |
1759 | handle = 1; | |
1760 | break; | |
1761 | case 0x1: | |
1762 | handle = 1; | |
1763 | cpu_single_env->watchpoint_hit = &hw_watchpoint; | |
1764 | hw_watchpoint.vaddr = hw_breakpoint[n].addr; | |
1765 | hw_watchpoint.flags = BP_MEM_WRITE; | |
1766 | break; | |
1767 | case 0x3: | |
1768 | handle = 1; | |
1769 | cpu_single_env->watchpoint_hit = &hw_watchpoint; | |
1770 | hw_watchpoint.vaddr = hw_breakpoint[n].addr; | |
1771 | hw_watchpoint.flags = BP_MEM_ACCESS; | |
1772 | break; | |
1773 | } | |
b9bec74b JK |
1774 | } |
1775 | } | |
e22a25c9 | 1776 | } |
b9bec74b | 1777 | } else if (kvm_find_sw_breakpoint(cpu_single_env, arch_info->pc)) { |
e22a25c9 | 1778 | handle = 1; |
b9bec74b | 1779 | } |
b0b1d690 JK |
1780 | if (!handle) { |
1781 | cpu_synchronize_state(cpu_single_env); | |
1782 | assert(cpu_single_env->exception_injected == -1); | |
1783 | ||
1784 | cpu_single_env->exception_injected = arch_info->exception; | |
1785 | cpu_single_env->has_error_code = 0; | |
1786 | } | |
e22a25c9 AL |
1787 | |
1788 | return handle; | |
1789 | } | |
1790 | ||
1791 | void kvm_arch_update_guest_debug(CPUState *env, struct kvm_guest_debug *dbg) | |
1792 | { | |
1793 | const uint8_t type_code[] = { | |
1794 | [GDB_BREAKPOINT_HW] = 0x0, | |
1795 | [GDB_WATCHPOINT_WRITE] = 0x1, | |
1796 | [GDB_WATCHPOINT_ACCESS] = 0x3 | |
1797 | }; | |
1798 | const uint8_t len_code[] = { | |
1799 | [1] = 0x0, [2] = 0x1, [4] = 0x3, [8] = 0x2 | |
1800 | }; | |
1801 | int n; | |
1802 | ||
b9bec74b | 1803 | if (kvm_sw_breakpoints_active(env)) { |
e22a25c9 | 1804 | dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP; |
b9bec74b | 1805 | } |
e22a25c9 AL |
1806 | if (nb_hw_breakpoint > 0) { |
1807 | dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP; | |
1808 | dbg->arch.debugreg[7] = 0x0600; | |
1809 | for (n = 0; n < nb_hw_breakpoint; n++) { | |
1810 | dbg->arch.debugreg[n] = hw_breakpoint[n].addr; | |
1811 | dbg->arch.debugreg[7] |= (2 << (n * 2)) | | |
1812 | (type_code[hw_breakpoint[n].type] << (16 + n*4)) | | |
95c077c9 | 1813 | ((uint32_t)len_code[hw_breakpoint[n].len] << (18 + n*4)); |
e22a25c9 AL |
1814 | } |
1815 | } | |
1816 | } | |
1817 | #endif /* KVM_CAP_SET_GUEST_DEBUG */ | |
4513d923 GN |
1818 | |
1819 | bool kvm_arch_stop_on_emulation_error(CPUState *env) | |
1820 | { | |
b9bec74b JK |
1821 | return !(env->cr[0] & CR0_PE_MASK) || |
1822 | ((env->segs[R_CS].selector & 3) != 3); | |
4513d923 | 1823 | } |