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05330448 AL |
1 | /* |
2 | * QEMU KVM support | |
3 | * | |
4 | * Copyright (C) 2006-2008 Qumranet Technologies | |
5 | * Copyright IBM, Corp. 2008 | |
6 | * | |
7 | * Authors: | |
8 | * Anthony Liguori <aliguori@us.ibm.com> | |
9 | * | |
10 | * This work is licensed under the terms of the GNU GPL, version 2 or later. | |
11 | * See the COPYING file in the top-level directory. | |
12 | * | |
13 | */ | |
14 | ||
15 | #include <sys/types.h> | |
16 | #include <sys/ioctl.h> | |
17 | #include <sys/mman.h> | |
25d2e361 | 18 | #include <sys/utsname.h> |
05330448 AL |
19 | |
20 | #include <linux/kvm.h> | |
21 | ||
22 | #include "qemu-common.h" | |
23 | #include "sysemu.h" | |
24 | #include "kvm.h" | |
25 | #include "cpu.h" | |
e22a25c9 | 26 | #include "gdbstub.h" |
0e607a80 | 27 | #include "host-utils.h" |
4c5b10b7 | 28 | #include "hw/pc.h" |
408392b3 | 29 | #include "hw/apic.h" |
35bed8ee | 30 | #include "ioport.h" |
e7701825 | 31 | #include "kvm_x86.h" |
05330448 | 32 | |
bb0300dc GN |
33 | #ifdef CONFIG_KVM_PARA |
34 | #include <linux/kvm_para.h> | |
35 | #endif | |
36 | // | |
05330448 AL |
37 | //#define DEBUG_KVM |
38 | ||
39 | #ifdef DEBUG_KVM | |
8c0d577e | 40 | #define DPRINTF(fmt, ...) \ |
05330448 AL |
41 | do { fprintf(stderr, fmt, ## __VA_ARGS__); } while (0) |
42 | #else | |
8c0d577e | 43 | #define DPRINTF(fmt, ...) \ |
05330448 AL |
44 | do { } while (0) |
45 | #endif | |
46 | ||
1a03675d GC |
47 | #define MSR_KVM_WALL_CLOCK 0x11 |
48 | #define MSR_KVM_SYSTEM_TIME 0x12 | |
49 | ||
c0532a76 MT |
50 | #ifndef BUS_MCEERR_AR |
51 | #define BUS_MCEERR_AR 4 | |
52 | #endif | |
53 | #ifndef BUS_MCEERR_AO | |
54 | #define BUS_MCEERR_AO 5 | |
55 | #endif | |
56 | ||
94a8d39a JK |
57 | const KVMCapabilityInfo kvm_arch_required_capabilities[] = { |
58 | KVM_CAP_INFO(SET_TSS_ADDR), | |
59 | KVM_CAP_INFO(EXT_CPUID), | |
60 | KVM_CAP_INFO(MP_STATE), | |
61 | KVM_CAP_LAST_INFO | |
62 | }; | |
25d2e361 | 63 | |
c3a3a7d3 JK |
64 | static bool has_msr_star; |
65 | static bool has_msr_hsave_pa; | |
c5999bfc JK |
66 | #if defined(CONFIG_KVM_PARA) && defined(KVM_CAP_ASYNC_PF) |
67 | static bool has_msr_async_pf_en; | |
68 | #endif | |
25d2e361 | 69 | static int lm_capable_kernel; |
b827df58 AK |
70 | |
71 | static struct kvm_cpuid2 *try_get_cpuid(KVMState *s, int max) | |
72 | { | |
73 | struct kvm_cpuid2 *cpuid; | |
74 | int r, size; | |
75 | ||
76 | size = sizeof(*cpuid) + max * sizeof(*cpuid->entries); | |
77 | cpuid = (struct kvm_cpuid2 *)qemu_mallocz(size); | |
78 | cpuid->nent = max; | |
79 | r = kvm_ioctl(s, KVM_GET_SUPPORTED_CPUID, cpuid); | |
76ae317f MM |
80 | if (r == 0 && cpuid->nent >= max) { |
81 | r = -E2BIG; | |
82 | } | |
b827df58 AK |
83 | if (r < 0) { |
84 | if (r == -E2BIG) { | |
85 | qemu_free(cpuid); | |
86 | return NULL; | |
87 | } else { | |
88 | fprintf(stderr, "KVM_GET_SUPPORTED_CPUID failed: %s\n", | |
89 | strerror(-r)); | |
90 | exit(1); | |
91 | } | |
92 | } | |
93 | return cpuid; | |
94 | } | |
95 | ||
c958a8bd SY |
96 | uint32_t kvm_arch_get_supported_cpuid(CPUState *env, uint32_t function, |
97 | uint32_t index, int reg) | |
b827df58 AK |
98 | { |
99 | struct kvm_cpuid2 *cpuid; | |
100 | int i, max; | |
101 | uint32_t ret = 0; | |
102 | uint32_t cpuid_1_edx; | |
103 | ||
b827df58 AK |
104 | max = 1; |
105 | while ((cpuid = try_get_cpuid(env->kvm_state, max)) == NULL) { | |
106 | max *= 2; | |
107 | } | |
108 | ||
109 | for (i = 0; i < cpuid->nent; ++i) { | |
c958a8bd SY |
110 | if (cpuid->entries[i].function == function && |
111 | cpuid->entries[i].index == index) { | |
b827df58 AK |
112 | switch (reg) { |
113 | case R_EAX: | |
114 | ret = cpuid->entries[i].eax; | |
115 | break; | |
116 | case R_EBX: | |
117 | ret = cpuid->entries[i].ebx; | |
118 | break; | |
119 | case R_ECX: | |
120 | ret = cpuid->entries[i].ecx; | |
121 | break; | |
122 | case R_EDX: | |
123 | ret = cpuid->entries[i].edx; | |
19ccb8ea JK |
124 | switch (function) { |
125 | case 1: | |
126 | /* KVM before 2.6.30 misreports the following features */ | |
127 | ret |= CPUID_MTRR | CPUID_PAT | CPUID_MCE | CPUID_MCA; | |
128 | break; | |
129 | case 0x80000001: | |
b827df58 AK |
130 | /* On Intel, kvm returns cpuid according to the Intel spec, |
131 | * so add missing bits according to the AMD spec: | |
132 | */ | |
c958a8bd | 133 | cpuid_1_edx = kvm_arch_get_supported_cpuid(env, 1, 0, R_EDX); |
c1667e40 | 134 | ret |= cpuid_1_edx & 0x183f7ff; |
19ccb8ea | 135 | break; |
b827df58 AK |
136 | } |
137 | break; | |
138 | } | |
139 | } | |
140 | } | |
141 | ||
142 | qemu_free(cpuid); | |
143 | ||
144 | return ret; | |
145 | } | |
146 | ||
bb0300dc GN |
147 | #ifdef CONFIG_KVM_PARA |
148 | struct kvm_para_features { | |
b9bec74b JK |
149 | int cap; |
150 | int feature; | |
bb0300dc | 151 | } para_features[] = { |
b9bec74b | 152 | { KVM_CAP_CLOCKSOURCE, KVM_FEATURE_CLOCKSOURCE }, |
b9bec74b | 153 | { KVM_CAP_NOP_IO_DELAY, KVM_FEATURE_NOP_IO_DELAY }, |
b9bec74b | 154 | { KVM_CAP_PV_MMU, KVM_FEATURE_MMU_OP }, |
f6584ee2 | 155 | #ifdef KVM_CAP_ASYNC_PF |
b9bec74b | 156 | { KVM_CAP_ASYNC_PF, KVM_FEATURE_ASYNC_PF }, |
bb0300dc | 157 | #endif |
b9bec74b | 158 | { -1, -1 } |
bb0300dc GN |
159 | }; |
160 | ||
161 | static int get_para_features(CPUState *env) | |
162 | { | |
b9bec74b | 163 | int i, features = 0; |
bb0300dc | 164 | |
b9bec74b JK |
165 | for (i = 0; i < ARRAY_SIZE(para_features) - 1; i++) { |
166 | if (kvm_check_extension(env->kvm_state, para_features[i].cap)) { | |
167 | features |= (1 << para_features[i].feature); | |
bb0300dc | 168 | } |
b9bec74b | 169 | } |
b3a98367 | 170 | #ifdef KVM_CAP_ASYNC_PF |
c5999bfc | 171 | has_msr_async_pf_en = features & (1 << KVM_FEATURE_ASYNC_PF); |
b3a98367 | 172 | #endif |
b9bec74b | 173 | return features; |
bb0300dc GN |
174 | } |
175 | #endif | |
176 | ||
e7701825 MT |
177 | #ifdef KVM_CAP_MCE |
178 | static int kvm_get_mce_cap_supported(KVMState *s, uint64_t *mce_cap, | |
179 | int *max_banks) | |
180 | { | |
181 | int r; | |
182 | ||
14a09518 | 183 | r = kvm_check_extension(s, KVM_CAP_MCE); |
e7701825 MT |
184 | if (r > 0) { |
185 | *max_banks = r; | |
186 | return kvm_ioctl(s, KVM_X86_GET_MCE_CAP_SUPPORTED, mce_cap); | |
187 | } | |
188 | return -ENOSYS; | |
189 | } | |
190 | ||
191 | static int kvm_setup_mce(CPUState *env, uint64_t *mcg_cap) | |
192 | { | |
193 | return kvm_vcpu_ioctl(env, KVM_X86_SETUP_MCE, mcg_cap); | |
194 | } | |
195 | ||
196 | static int kvm_set_mce(CPUState *env, struct kvm_x86_mce *m) | |
197 | { | |
198 | return kvm_vcpu_ioctl(env, KVM_X86_SET_MCE, m); | |
199 | } | |
200 | ||
c0532a76 MT |
201 | static int kvm_get_msr(CPUState *env, struct kvm_msr_entry *msrs, int n) |
202 | { | |
203 | struct kvm_msrs *kmsrs = qemu_malloc(sizeof *kmsrs + n * sizeof *msrs); | |
204 | int r; | |
205 | ||
206 | kmsrs->nmsrs = n; | |
207 | memcpy(kmsrs->entries, msrs, n * sizeof *msrs); | |
208 | r = kvm_vcpu_ioctl(env, KVM_GET_MSRS, kmsrs); | |
209 | memcpy(msrs, kmsrs->entries, n * sizeof *msrs); | |
210 | free(kmsrs); | |
211 | return r; | |
212 | } | |
213 | ||
214 | /* FIXME: kill this and kvm_get_msr, use env->mcg_status instead */ | |
6643e2f0 | 215 | static int kvm_mce_in_progress(CPUState *env) |
c0532a76 MT |
216 | { |
217 | struct kvm_msr_entry msr_mcg_status = { | |
218 | .index = MSR_MCG_STATUS, | |
219 | }; | |
220 | int r; | |
221 | ||
222 | r = kvm_get_msr(env, &msr_mcg_status, 1); | |
223 | if (r == -1 || r == 0) { | |
6643e2f0 JD |
224 | fprintf(stderr, "Failed to get MCE status\n"); |
225 | return 0; | |
c0532a76 MT |
226 | } |
227 | return !!(msr_mcg_status.data & MCG_STATUS_MCIP); | |
228 | } | |
229 | ||
e7701825 MT |
230 | struct kvm_x86_mce_data |
231 | { | |
232 | CPUState *env; | |
233 | struct kvm_x86_mce *mce; | |
c0532a76 | 234 | int abort_on_error; |
e7701825 MT |
235 | }; |
236 | ||
237 | static void kvm_do_inject_x86_mce(void *_data) | |
238 | { | |
239 | struct kvm_x86_mce_data *data = _data; | |
240 | int r; | |
241 | ||
f8502cfb HS |
242 | /* If there is an MCE exception being processed, ignore this SRAO MCE */ |
243 | if ((data->env->mcg_cap & MCG_SER_P) && | |
244 | !(data->mce->status & MCI_STATUS_AR)) { | |
6643e2f0 | 245 | if (kvm_mce_in_progress(data->env)) { |
f8502cfb HS |
246 | return; |
247 | } | |
248 | } | |
c0532a76 | 249 | |
e7701825 | 250 | r = kvm_set_mce(data->env, data->mce); |
c0532a76 | 251 | if (r < 0) { |
e7701825 | 252 | perror("kvm_set_mce FAILED"); |
c0532a76 MT |
253 | if (data->abort_on_error) { |
254 | abort(); | |
255 | } | |
256 | } | |
e7701825 | 257 | } |
31ce5e0c | 258 | |
7cc2cc3e JD |
259 | static void kvm_inject_x86_mce_on(CPUState *env, struct kvm_x86_mce *mce, |
260 | int flag) | |
261 | { | |
262 | struct kvm_x86_mce_data data = { | |
263 | .env = env, | |
264 | .mce = mce, | |
265 | .abort_on_error = (flag & ABORT_ON_ERROR), | |
266 | }; | |
267 | ||
268 | if (!env->mcg_cap) { | |
269 | fprintf(stderr, "MCE support is not enabled!\n"); | |
270 | return; | |
271 | } | |
272 | ||
273 | run_on_cpu(env, kvm_do_inject_x86_mce, &data); | |
274 | } | |
275 | ||
31ce5e0c | 276 | static void kvm_mce_broadcast_rest(CPUState *env); |
e7701825 MT |
277 | #endif |
278 | ||
279 | void kvm_inject_x86_mce(CPUState *cenv, int bank, uint64_t status, | |
c0532a76 | 280 | uint64_t mcg_status, uint64_t addr, uint64_t misc, |
31ce5e0c | 281 | int flag) |
e7701825 MT |
282 | { |
283 | #ifdef KVM_CAP_MCE | |
284 | struct kvm_x86_mce mce = { | |
285 | .bank = bank, | |
286 | .status = status, | |
287 | .mcg_status = mcg_status, | |
288 | .addr = addr, | |
289 | .misc = misc, | |
290 | }; | |
e7701825 | 291 | |
31ce5e0c JD |
292 | if (flag & MCE_BROADCAST) { |
293 | kvm_mce_broadcast_rest(cenv); | |
c0532a76 MT |
294 | } |
295 | ||
7cc2cc3e | 296 | kvm_inject_x86_mce_on(cenv, &mce, flag); |
c0532a76 | 297 | #else |
31ce5e0c | 298 | if (flag & ABORT_ON_ERROR) { |
c0532a76 | 299 | abort(); |
31ce5e0c | 300 | } |
e7701825 MT |
301 | #endif |
302 | } | |
303 | ||
05330448 AL |
304 | int kvm_arch_init_vcpu(CPUState *env) |
305 | { | |
306 | struct { | |
486bd5a2 AL |
307 | struct kvm_cpuid2 cpuid; |
308 | struct kvm_cpuid_entry2 entries[100]; | |
05330448 | 309 | } __attribute__((packed)) cpuid_data; |
486bd5a2 | 310 | uint32_t limit, i, j, cpuid_i; |
a33609ca | 311 | uint32_t unused; |
bb0300dc | 312 | struct kvm_cpuid_entry2 *c; |
521f0798 | 313 | #ifdef CONFIG_KVM_PARA |
bb0300dc GN |
314 | uint32_t signature[3]; |
315 | #endif | |
05330448 | 316 | |
c958a8bd | 317 | env->cpuid_features &= kvm_arch_get_supported_cpuid(env, 1, 0, R_EDX); |
6c0d7ee8 AP |
318 | |
319 | i = env->cpuid_ext_features & CPUID_EXT_HYPERVISOR; | |
c958a8bd | 320 | env->cpuid_ext_features &= kvm_arch_get_supported_cpuid(env, 1, 0, R_ECX); |
6c0d7ee8 AP |
321 | env->cpuid_ext_features |= i; |
322 | ||
457dfed6 | 323 | env->cpuid_ext2_features &= kvm_arch_get_supported_cpuid(env, 0x80000001, |
c958a8bd | 324 | 0, R_EDX); |
457dfed6 | 325 | env->cpuid_ext3_features &= kvm_arch_get_supported_cpuid(env, 0x80000001, |
c958a8bd | 326 | 0, R_ECX); |
296acb64 JR |
327 | env->cpuid_svm_features &= kvm_arch_get_supported_cpuid(env, 0x8000000A, |
328 | 0, R_EDX); | |
329 | ||
6c1f42fe | 330 | |
05330448 AL |
331 | cpuid_i = 0; |
332 | ||
bb0300dc GN |
333 | #ifdef CONFIG_KVM_PARA |
334 | /* Paravirtualization CPUIDs */ | |
335 | memcpy(signature, "KVMKVMKVM\0\0\0", 12); | |
336 | c = &cpuid_data.entries[cpuid_i++]; | |
337 | memset(c, 0, sizeof(*c)); | |
338 | c->function = KVM_CPUID_SIGNATURE; | |
339 | c->eax = 0; | |
340 | c->ebx = signature[0]; | |
341 | c->ecx = signature[1]; | |
342 | c->edx = signature[2]; | |
343 | ||
344 | c = &cpuid_data.entries[cpuid_i++]; | |
345 | memset(c, 0, sizeof(*c)); | |
346 | c->function = KVM_CPUID_FEATURES; | |
347 | c->eax = env->cpuid_kvm_features & get_para_features(env); | |
348 | #endif | |
349 | ||
a33609ca | 350 | cpu_x86_cpuid(env, 0, 0, &limit, &unused, &unused, &unused); |
05330448 AL |
351 | |
352 | for (i = 0; i <= limit; i++) { | |
bb0300dc | 353 | c = &cpuid_data.entries[cpuid_i++]; |
486bd5a2 AL |
354 | |
355 | switch (i) { | |
a36b1029 AL |
356 | case 2: { |
357 | /* Keep reading function 2 till all the input is received */ | |
358 | int times; | |
359 | ||
a36b1029 | 360 | c->function = i; |
a33609ca AL |
361 | c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC | |
362 | KVM_CPUID_FLAG_STATE_READ_NEXT; | |
363 | cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx); | |
364 | times = c->eax & 0xff; | |
a36b1029 AL |
365 | |
366 | for (j = 1; j < times; ++j) { | |
a33609ca | 367 | c = &cpuid_data.entries[cpuid_i++]; |
a36b1029 | 368 | c->function = i; |
a33609ca AL |
369 | c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC; |
370 | cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx); | |
a36b1029 AL |
371 | } |
372 | break; | |
373 | } | |
486bd5a2 AL |
374 | case 4: |
375 | case 0xb: | |
376 | case 0xd: | |
377 | for (j = 0; ; j++) { | |
486bd5a2 AL |
378 | c->function = i; |
379 | c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX; | |
380 | c->index = j; | |
a33609ca | 381 | cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx); |
486bd5a2 | 382 | |
b9bec74b | 383 | if (i == 4 && c->eax == 0) { |
486bd5a2 | 384 | break; |
b9bec74b JK |
385 | } |
386 | if (i == 0xb && !(c->ecx & 0xff00)) { | |
486bd5a2 | 387 | break; |
b9bec74b JK |
388 | } |
389 | if (i == 0xd && c->eax == 0) { | |
486bd5a2 | 390 | break; |
b9bec74b | 391 | } |
a33609ca | 392 | c = &cpuid_data.entries[cpuid_i++]; |
486bd5a2 AL |
393 | } |
394 | break; | |
395 | default: | |
486bd5a2 | 396 | c->function = i; |
a33609ca AL |
397 | c->flags = 0; |
398 | cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx); | |
486bd5a2 AL |
399 | break; |
400 | } | |
05330448 | 401 | } |
a33609ca | 402 | cpu_x86_cpuid(env, 0x80000000, 0, &limit, &unused, &unused, &unused); |
05330448 AL |
403 | |
404 | for (i = 0x80000000; i <= limit; i++) { | |
bb0300dc | 405 | c = &cpuid_data.entries[cpuid_i++]; |
05330448 | 406 | |
05330448 | 407 | c->function = i; |
a33609ca AL |
408 | c->flags = 0; |
409 | cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx); | |
05330448 AL |
410 | } |
411 | ||
412 | cpuid_data.cpuid.nent = cpuid_i; | |
413 | ||
e7701825 MT |
414 | #ifdef KVM_CAP_MCE |
415 | if (((env->cpuid_version >> 8)&0xF) >= 6 | |
416 | && (env->cpuid_features&(CPUID_MCE|CPUID_MCA)) == (CPUID_MCE|CPUID_MCA) | |
417 | && kvm_check_extension(env->kvm_state, KVM_CAP_MCE) > 0) { | |
418 | uint64_t mcg_cap; | |
419 | int banks; | |
420 | ||
b9bec74b | 421 | if (kvm_get_mce_cap_supported(env->kvm_state, &mcg_cap, &banks)) { |
e7701825 | 422 | perror("kvm_get_mce_cap_supported FAILED"); |
b9bec74b | 423 | } else { |
e7701825 MT |
424 | if (banks > MCE_BANKS_DEF) |
425 | banks = MCE_BANKS_DEF; | |
426 | mcg_cap &= MCE_CAP_DEF; | |
427 | mcg_cap |= banks; | |
b9bec74b | 428 | if (kvm_setup_mce(env, &mcg_cap)) { |
e7701825 | 429 | perror("kvm_setup_mce FAILED"); |
b9bec74b | 430 | } else { |
e7701825 | 431 | env->mcg_cap = mcg_cap; |
b9bec74b | 432 | } |
e7701825 MT |
433 | } |
434 | } | |
435 | #endif | |
436 | ||
486bd5a2 | 437 | return kvm_vcpu_ioctl(env, KVM_SET_CPUID2, &cpuid_data); |
05330448 AL |
438 | } |
439 | ||
caa5af0f JK |
440 | void kvm_arch_reset_vcpu(CPUState *env) |
441 | { | |
e73223a5 | 442 | env->exception_injected = -1; |
0e607a80 | 443 | env->interrupt_injected = -1; |
1a5e9d2f | 444 | env->xcr0 = 1; |
ddced198 MT |
445 | if (kvm_irqchip_in_kernel()) { |
446 | env->mp_state = cpu_is_bsp(env) ? KVM_MP_STATE_RUNNABLE : | |
447 | KVM_MP_STATE_UNINITIALIZED; | |
448 | } else { | |
449 | env->mp_state = KVM_MP_STATE_RUNNABLE; | |
450 | } | |
caa5af0f JK |
451 | } |
452 | ||
c3a3a7d3 | 453 | static int kvm_get_supported_msrs(KVMState *s) |
05330448 | 454 | { |
75b10c43 | 455 | static int kvm_supported_msrs; |
c3a3a7d3 | 456 | int ret = 0; |
05330448 AL |
457 | |
458 | /* first time */ | |
75b10c43 | 459 | if (kvm_supported_msrs == 0) { |
05330448 AL |
460 | struct kvm_msr_list msr_list, *kvm_msr_list; |
461 | ||
75b10c43 | 462 | kvm_supported_msrs = -1; |
05330448 AL |
463 | |
464 | /* Obtain MSR list from KVM. These are the MSRs that we must | |
465 | * save/restore */ | |
4c9f7372 | 466 | msr_list.nmsrs = 0; |
c3a3a7d3 | 467 | ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, &msr_list); |
6fb6d245 | 468 | if (ret < 0 && ret != -E2BIG) { |
c3a3a7d3 | 469 | return ret; |
6fb6d245 | 470 | } |
d9db889f JK |
471 | /* Old kernel modules had a bug and could write beyond the provided |
472 | memory. Allocate at least a safe amount of 1K. */ | |
473 | kvm_msr_list = qemu_mallocz(MAX(1024, sizeof(msr_list) + | |
474 | msr_list.nmsrs * | |
475 | sizeof(msr_list.indices[0]))); | |
05330448 | 476 | |
55308450 | 477 | kvm_msr_list->nmsrs = msr_list.nmsrs; |
c3a3a7d3 | 478 | ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, kvm_msr_list); |
05330448 AL |
479 | if (ret >= 0) { |
480 | int i; | |
481 | ||
482 | for (i = 0; i < kvm_msr_list->nmsrs; i++) { | |
483 | if (kvm_msr_list->indices[i] == MSR_STAR) { | |
c3a3a7d3 | 484 | has_msr_star = true; |
75b10c43 MT |
485 | continue; |
486 | } | |
487 | if (kvm_msr_list->indices[i] == MSR_VM_HSAVE_PA) { | |
c3a3a7d3 | 488 | has_msr_hsave_pa = true; |
75b10c43 | 489 | continue; |
05330448 AL |
490 | } |
491 | } | |
492 | } | |
493 | ||
494 | free(kvm_msr_list); | |
495 | } | |
496 | ||
c3a3a7d3 | 497 | return ret; |
05330448 AL |
498 | } |
499 | ||
cad1e282 | 500 | int kvm_arch_init(KVMState *s) |
20420430 | 501 | { |
11076198 | 502 | uint64_t identity_base = 0xfffbc000; |
20420430 | 503 | int ret; |
25d2e361 | 504 | struct utsname utsname; |
20420430 | 505 | |
c3a3a7d3 | 506 | ret = kvm_get_supported_msrs(s); |
20420430 | 507 | if (ret < 0) { |
20420430 SY |
508 | return ret; |
509 | } | |
25d2e361 MT |
510 | |
511 | uname(&utsname); | |
512 | lm_capable_kernel = strcmp(utsname.machine, "x86_64") == 0; | |
513 | ||
4c5b10b7 | 514 | /* |
11076198 JK |
515 | * On older Intel CPUs, KVM uses vm86 mode to emulate 16-bit code directly. |
516 | * In order to use vm86 mode, an EPT identity map and a TSS are needed. | |
517 | * Since these must be part of guest physical memory, we need to allocate | |
518 | * them, both by setting their start addresses in the kernel and by | |
519 | * creating a corresponding e820 entry. We need 4 pages before the BIOS. | |
520 | * | |
521 | * Older KVM versions may not support setting the identity map base. In | |
522 | * that case we need to stick with the default, i.e. a 256K maximum BIOS | |
523 | * size. | |
4c5b10b7 | 524 | */ |
11076198 JK |
525 | #ifdef KVM_CAP_SET_IDENTITY_MAP_ADDR |
526 | if (kvm_check_extension(s, KVM_CAP_SET_IDENTITY_MAP_ADDR)) { | |
527 | /* Allows up to 16M BIOSes. */ | |
528 | identity_base = 0xfeffc000; | |
529 | ||
530 | ret = kvm_vm_ioctl(s, KVM_SET_IDENTITY_MAP_ADDR, &identity_base); | |
531 | if (ret < 0) { | |
532 | return ret; | |
533 | } | |
4c5b10b7 | 534 | } |
11076198 JK |
535 | #endif |
536 | /* Set TSS base one page after EPT identity map. */ | |
537 | ret = kvm_vm_ioctl(s, KVM_SET_TSS_ADDR, identity_base + 0x1000); | |
20420430 SY |
538 | if (ret < 0) { |
539 | return ret; | |
540 | } | |
541 | ||
11076198 JK |
542 | /* Tell fw_cfg to notify the BIOS to reserve the range. */ |
543 | ret = e820_add_entry(identity_base, 0x4000, E820_RESERVED); | |
20420430 | 544 | if (ret < 0) { |
11076198 | 545 | fprintf(stderr, "e820_add_entry() table is full\n"); |
20420430 SY |
546 | return ret; |
547 | } | |
548 | ||
11076198 | 549 | return 0; |
05330448 | 550 | } |
b9bec74b | 551 | |
05330448 AL |
552 | static void set_v8086_seg(struct kvm_segment *lhs, const SegmentCache *rhs) |
553 | { | |
554 | lhs->selector = rhs->selector; | |
555 | lhs->base = rhs->base; | |
556 | lhs->limit = rhs->limit; | |
557 | lhs->type = 3; | |
558 | lhs->present = 1; | |
559 | lhs->dpl = 3; | |
560 | lhs->db = 0; | |
561 | lhs->s = 1; | |
562 | lhs->l = 0; | |
563 | lhs->g = 0; | |
564 | lhs->avl = 0; | |
565 | lhs->unusable = 0; | |
566 | } | |
567 | ||
568 | static void set_seg(struct kvm_segment *lhs, const SegmentCache *rhs) | |
569 | { | |
570 | unsigned flags = rhs->flags; | |
571 | lhs->selector = rhs->selector; | |
572 | lhs->base = rhs->base; | |
573 | lhs->limit = rhs->limit; | |
574 | lhs->type = (flags >> DESC_TYPE_SHIFT) & 15; | |
575 | lhs->present = (flags & DESC_P_MASK) != 0; | |
acaa7550 | 576 | lhs->dpl = (flags >> DESC_DPL_SHIFT) & 3; |
05330448 AL |
577 | lhs->db = (flags >> DESC_B_SHIFT) & 1; |
578 | lhs->s = (flags & DESC_S_MASK) != 0; | |
579 | lhs->l = (flags >> DESC_L_SHIFT) & 1; | |
580 | lhs->g = (flags & DESC_G_MASK) != 0; | |
581 | lhs->avl = (flags & DESC_AVL_MASK) != 0; | |
582 | lhs->unusable = 0; | |
583 | } | |
584 | ||
585 | static void get_seg(SegmentCache *lhs, const struct kvm_segment *rhs) | |
586 | { | |
587 | lhs->selector = rhs->selector; | |
588 | lhs->base = rhs->base; | |
589 | lhs->limit = rhs->limit; | |
b9bec74b JK |
590 | lhs->flags = (rhs->type << DESC_TYPE_SHIFT) | |
591 | (rhs->present * DESC_P_MASK) | | |
592 | (rhs->dpl << DESC_DPL_SHIFT) | | |
593 | (rhs->db << DESC_B_SHIFT) | | |
594 | (rhs->s * DESC_S_MASK) | | |
595 | (rhs->l << DESC_L_SHIFT) | | |
596 | (rhs->g * DESC_G_MASK) | | |
597 | (rhs->avl * DESC_AVL_MASK); | |
05330448 AL |
598 | } |
599 | ||
600 | static void kvm_getput_reg(__u64 *kvm_reg, target_ulong *qemu_reg, int set) | |
601 | { | |
b9bec74b | 602 | if (set) { |
05330448 | 603 | *kvm_reg = *qemu_reg; |
b9bec74b | 604 | } else { |
05330448 | 605 | *qemu_reg = *kvm_reg; |
b9bec74b | 606 | } |
05330448 AL |
607 | } |
608 | ||
609 | static int kvm_getput_regs(CPUState *env, int set) | |
610 | { | |
611 | struct kvm_regs regs; | |
612 | int ret = 0; | |
613 | ||
614 | if (!set) { | |
615 | ret = kvm_vcpu_ioctl(env, KVM_GET_REGS, ®s); | |
b9bec74b | 616 | if (ret < 0) { |
05330448 | 617 | return ret; |
b9bec74b | 618 | } |
05330448 AL |
619 | } |
620 | ||
621 | kvm_getput_reg(®s.rax, &env->regs[R_EAX], set); | |
622 | kvm_getput_reg(®s.rbx, &env->regs[R_EBX], set); | |
623 | kvm_getput_reg(®s.rcx, &env->regs[R_ECX], set); | |
624 | kvm_getput_reg(®s.rdx, &env->regs[R_EDX], set); | |
625 | kvm_getput_reg(®s.rsi, &env->regs[R_ESI], set); | |
626 | kvm_getput_reg(®s.rdi, &env->regs[R_EDI], set); | |
627 | kvm_getput_reg(®s.rsp, &env->regs[R_ESP], set); | |
628 | kvm_getput_reg(®s.rbp, &env->regs[R_EBP], set); | |
629 | #ifdef TARGET_X86_64 | |
630 | kvm_getput_reg(®s.r8, &env->regs[8], set); | |
631 | kvm_getput_reg(®s.r9, &env->regs[9], set); | |
632 | kvm_getput_reg(®s.r10, &env->regs[10], set); | |
633 | kvm_getput_reg(®s.r11, &env->regs[11], set); | |
634 | kvm_getput_reg(®s.r12, &env->regs[12], set); | |
635 | kvm_getput_reg(®s.r13, &env->regs[13], set); | |
636 | kvm_getput_reg(®s.r14, &env->regs[14], set); | |
637 | kvm_getput_reg(®s.r15, &env->regs[15], set); | |
638 | #endif | |
639 | ||
640 | kvm_getput_reg(®s.rflags, &env->eflags, set); | |
641 | kvm_getput_reg(®s.rip, &env->eip, set); | |
642 | ||
b9bec74b | 643 | if (set) { |
05330448 | 644 | ret = kvm_vcpu_ioctl(env, KVM_SET_REGS, ®s); |
b9bec74b | 645 | } |
05330448 AL |
646 | |
647 | return ret; | |
648 | } | |
649 | ||
650 | static int kvm_put_fpu(CPUState *env) | |
651 | { | |
652 | struct kvm_fpu fpu; | |
653 | int i; | |
654 | ||
655 | memset(&fpu, 0, sizeof fpu); | |
656 | fpu.fsw = env->fpus & ~(7 << 11); | |
657 | fpu.fsw |= (env->fpstt & 7) << 11; | |
658 | fpu.fcw = env->fpuc; | |
b9bec74b JK |
659 | for (i = 0; i < 8; ++i) { |
660 | fpu.ftwx |= (!env->fptags[i]) << i; | |
661 | } | |
05330448 AL |
662 | memcpy(fpu.fpr, env->fpregs, sizeof env->fpregs); |
663 | memcpy(fpu.xmm, env->xmm_regs, sizeof env->xmm_regs); | |
664 | fpu.mxcsr = env->mxcsr; | |
665 | ||
666 | return kvm_vcpu_ioctl(env, KVM_SET_FPU, &fpu); | |
667 | } | |
668 | ||
f1665b21 SY |
669 | #ifdef KVM_CAP_XSAVE |
670 | #define XSAVE_CWD_RIP 2 | |
671 | #define XSAVE_CWD_RDP 4 | |
672 | #define XSAVE_MXCSR 6 | |
673 | #define XSAVE_ST_SPACE 8 | |
674 | #define XSAVE_XMM_SPACE 40 | |
675 | #define XSAVE_XSTATE_BV 128 | |
676 | #define XSAVE_YMMH_SPACE 144 | |
677 | #endif | |
678 | ||
679 | static int kvm_put_xsave(CPUState *env) | |
680 | { | |
681 | #ifdef KVM_CAP_XSAVE | |
0f53994f | 682 | int i, r; |
f1665b21 SY |
683 | struct kvm_xsave* xsave; |
684 | uint16_t cwd, swd, twd, fop; | |
685 | ||
b9bec74b | 686 | if (!kvm_has_xsave()) { |
f1665b21 | 687 | return kvm_put_fpu(env); |
b9bec74b | 688 | } |
f1665b21 SY |
689 | |
690 | xsave = qemu_memalign(4096, sizeof(struct kvm_xsave)); | |
691 | memset(xsave, 0, sizeof(struct kvm_xsave)); | |
692 | cwd = swd = twd = fop = 0; | |
693 | swd = env->fpus & ~(7 << 11); | |
694 | swd |= (env->fpstt & 7) << 11; | |
695 | cwd = env->fpuc; | |
b9bec74b | 696 | for (i = 0; i < 8; ++i) { |
f1665b21 | 697 | twd |= (!env->fptags[i]) << i; |
b9bec74b | 698 | } |
f1665b21 SY |
699 | xsave->region[0] = (uint32_t)(swd << 16) + cwd; |
700 | xsave->region[1] = (uint32_t)(fop << 16) + twd; | |
701 | memcpy(&xsave->region[XSAVE_ST_SPACE], env->fpregs, | |
702 | sizeof env->fpregs); | |
703 | memcpy(&xsave->region[XSAVE_XMM_SPACE], env->xmm_regs, | |
704 | sizeof env->xmm_regs); | |
705 | xsave->region[XSAVE_MXCSR] = env->mxcsr; | |
706 | *(uint64_t *)&xsave->region[XSAVE_XSTATE_BV] = env->xstate_bv; | |
707 | memcpy(&xsave->region[XSAVE_YMMH_SPACE], env->ymmh_regs, | |
708 | sizeof env->ymmh_regs); | |
0f53994f MT |
709 | r = kvm_vcpu_ioctl(env, KVM_SET_XSAVE, xsave); |
710 | qemu_free(xsave); | |
711 | return r; | |
f1665b21 SY |
712 | #else |
713 | return kvm_put_fpu(env); | |
714 | #endif | |
715 | } | |
716 | ||
717 | static int kvm_put_xcrs(CPUState *env) | |
718 | { | |
719 | #ifdef KVM_CAP_XCRS | |
720 | struct kvm_xcrs xcrs; | |
721 | ||
b9bec74b | 722 | if (!kvm_has_xcrs()) { |
f1665b21 | 723 | return 0; |
b9bec74b | 724 | } |
f1665b21 SY |
725 | |
726 | xcrs.nr_xcrs = 1; | |
727 | xcrs.flags = 0; | |
728 | xcrs.xcrs[0].xcr = 0; | |
729 | xcrs.xcrs[0].value = env->xcr0; | |
730 | return kvm_vcpu_ioctl(env, KVM_SET_XCRS, &xcrs); | |
731 | #else | |
732 | return 0; | |
733 | #endif | |
734 | } | |
735 | ||
05330448 AL |
736 | static int kvm_put_sregs(CPUState *env) |
737 | { | |
738 | struct kvm_sregs sregs; | |
739 | ||
0e607a80 JK |
740 | memset(sregs.interrupt_bitmap, 0, sizeof(sregs.interrupt_bitmap)); |
741 | if (env->interrupt_injected >= 0) { | |
742 | sregs.interrupt_bitmap[env->interrupt_injected / 64] |= | |
743 | (uint64_t)1 << (env->interrupt_injected % 64); | |
744 | } | |
05330448 AL |
745 | |
746 | if ((env->eflags & VM_MASK)) { | |
b9bec74b JK |
747 | set_v8086_seg(&sregs.cs, &env->segs[R_CS]); |
748 | set_v8086_seg(&sregs.ds, &env->segs[R_DS]); | |
749 | set_v8086_seg(&sregs.es, &env->segs[R_ES]); | |
750 | set_v8086_seg(&sregs.fs, &env->segs[R_FS]); | |
751 | set_v8086_seg(&sregs.gs, &env->segs[R_GS]); | |
752 | set_v8086_seg(&sregs.ss, &env->segs[R_SS]); | |
05330448 | 753 | } else { |
b9bec74b JK |
754 | set_seg(&sregs.cs, &env->segs[R_CS]); |
755 | set_seg(&sregs.ds, &env->segs[R_DS]); | |
756 | set_seg(&sregs.es, &env->segs[R_ES]); | |
757 | set_seg(&sregs.fs, &env->segs[R_FS]); | |
758 | set_seg(&sregs.gs, &env->segs[R_GS]); | |
759 | set_seg(&sregs.ss, &env->segs[R_SS]); | |
05330448 AL |
760 | } |
761 | ||
762 | set_seg(&sregs.tr, &env->tr); | |
763 | set_seg(&sregs.ldt, &env->ldt); | |
764 | ||
765 | sregs.idt.limit = env->idt.limit; | |
766 | sregs.idt.base = env->idt.base; | |
767 | sregs.gdt.limit = env->gdt.limit; | |
768 | sregs.gdt.base = env->gdt.base; | |
769 | ||
770 | sregs.cr0 = env->cr[0]; | |
771 | sregs.cr2 = env->cr[2]; | |
772 | sregs.cr3 = env->cr[3]; | |
773 | sregs.cr4 = env->cr[4]; | |
774 | ||
4a942cea BS |
775 | sregs.cr8 = cpu_get_apic_tpr(env->apic_state); |
776 | sregs.apic_base = cpu_get_apic_base(env->apic_state); | |
05330448 AL |
777 | |
778 | sregs.efer = env->efer; | |
779 | ||
780 | return kvm_vcpu_ioctl(env, KVM_SET_SREGS, &sregs); | |
781 | } | |
782 | ||
783 | static void kvm_msr_entry_set(struct kvm_msr_entry *entry, | |
784 | uint32_t index, uint64_t value) | |
785 | { | |
786 | entry->index = index; | |
787 | entry->data = value; | |
788 | } | |
789 | ||
ea643051 | 790 | static int kvm_put_msrs(CPUState *env, int level) |
05330448 AL |
791 | { |
792 | struct { | |
793 | struct kvm_msrs info; | |
794 | struct kvm_msr_entry entries[100]; | |
795 | } msr_data; | |
796 | struct kvm_msr_entry *msrs = msr_data.entries; | |
d8da8574 | 797 | int n = 0; |
05330448 AL |
798 | |
799 | kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_CS, env->sysenter_cs); | |
800 | kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_ESP, env->sysenter_esp); | |
801 | kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_EIP, env->sysenter_eip); | |
c3a3a7d3 | 802 | if (has_msr_star) { |
b9bec74b JK |
803 | kvm_msr_entry_set(&msrs[n++], MSR_STAR, env->star); |
804 | } | |
c3a3a7d3 | 805 | if (has_msr_hsave_pa) { |
75b10c43 | 806 | kvm_msr_entry_set(&msrs[n++], MSR_VM_HSAVE_PA, env->vm_hsave); |
b9bec74b | 807 | } |
05330448 | 808 | #ifdef TARGET_X86_64 |
25d2e361 MT |
809 | if (lm_capable_kernel) { |
810 | kvm_msr_entry_set(&msrs[n++], MSR_CSTAR, env->cstar); | |
811 | kvm_msr_entry_set(&msrs[n++], MSR_KERNELGSBASE, env->kernelgsbase); | |
812 | kvm_msr_entry_set(&msrs[n++], MSR_FMASK, env->fmask); | |
813 | kvm_msr_entry_set(&msrs[n++], MSR_LSTAR, env->lstar); | |
814 | } | |
05330448 | 815 | #endif |
ea643051 | 816 | if (level == KVM_PUT_FULL_STATE) { |
384331a6 MT |
817 | /* |
818 | * KVM is yet unable to synchronize TSC values of multiple VCPUs on | |
819 | * writeback. Until this is fixed, we only write the offset to SMP | |
820 | * guests after migration, desynchronizing the VCPUs, but avoiding | |
821 | * huge jump-backs that would occur without any writeback at all. | |
822 | */ | |
823 | if (smp_cpus == 1 || env->tsc != 0) { | |
824 | kvm_msr_entry_set(&msrs[n++], MSR_IA32_TSC, env->tsc); | |
825 | } | |
ff5c186b JK |
826 | } |
827 | /* | |
828 | * The following paravirtual MSRs have side effects on the guest or are | |
829 | * too heavy for normal writeback. Limit them to reset or full state | |
830 | * updates. | |
831 | */ | |
832 | if (level >= KVM_PUT_RESET_STATE) { | |
ea643051 JK |
833 | kvm_msr_entry_set(&msrs[n++], MSR_KVM_SYSTEM_TIME, |
834 | env->system_time_msr); | |
835 | kvm_msr_entry_set(&msrs[n++], MSR_KVM_WALL_CLOCK, env->wall_clock_msr); | |
521f0798 | 836 | #if defined(CONFIG_KVM_PARA) && defined(KVM_CAP_ASYNC_PF) |
c5999bfc JK |
837 | if (has_msr_async_pf_en) { |
838 | kvm_msr_entry_set(&msrs[n++], MSR_KVM_ASYNC_PF_EN, | |
839 | env->async_pf_en_msr); | |
840 | } | |
f6584ee2 | 841 | #endif |
ea643051 | 842 | } |
57780495 MT |
843 | #ifdef KVM_CAP_MCE |
844 | if (env->mcg_cap) { | |
d8da8574 | 845 | int i; |
b9bec74b JK |
846 | |
847 | if (level == KVM_PUT_RESET_STATE) { | |
57780495 | 848 | kvm_msr_entry_set(&msrs[n++], MSR_MCG_STATUS, env->mcg_status); |
b9bec74b | 849 | } else if (level == KVM_PUT_FULL_STATE) { |
57780495 MT |
850 | kvm_msr_entry_set(&msrs[n++], MSR_MCG_STATUS, env->mcg_status); |
851 | kvm_msr_entry_set(&msrs[n++], MSR_MCG_CTL, env->mcg_ctl); | |
b9bec74b | 852 | for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) { |
57780495 | 853 | kvm_msr_entry_set(&msrs[n++], MSR_MC0_CTL + i, env->mce_banks[i]); |
b9bec74b | 854 | } |
57780495 MT |
855 | } |
856 | } | |
857 | #endif | |
1a03675d | 858 | |
05330448 AL |
859 | msr_data.info.nmsrs = n; |
860 | ||
861 | return kvm_vcpu_ioctl(env, KVM_SET_MSRS, &msr_data); | |
862 | ||
863 | } | |
864 | ||
865 | ||
866 | static int kvm_get_fpu(CPUState *env) | |
867 | { | |
868 | struct kvm_fpu fpu; | |
869 | int i, ret; | |
870 | ||
871 | ret = kvm_vcpu_ioctl(env, KVM_GET_FPU, &fpu); | |
b9bec74b | 872 | if (ret < 0) { |
05330448 | 873 | return ret; |
b9bec74b | 874 | } |
05330448 AL |
875 | |
876 | env->fpstt = (fpu.fsw >> 11) & 7; | |
877 | env->fpus = fpu.fsw; | |
878 | env->fpuc = fpu.fcw; | |
b9bec74b JK |
879 | for (i = 0; i < 8; ++i) { |
880 | env->fptags[i] = !((fpu.ftwx >> i) & 1); | |
881 | } | |
05330448 AL |
882 | memcpy(env->fpregs, fpu.fpr, sizeof env->fpregs); |
883 | memcpy(env->xmm_regs, fpu.xmm, sizeof env->xmm_regs); | |
884 | env->mxcsr = fpu.mxcsr; | |
885 | ||
886 | return 0; | |
887 | } | |
888 | ||
f1665b21 SY |
889 | static int kvm_get_xsave(CPUState *env) |
890 | { | |
891 | #ifdef KVM_CAP_XSAVE | |
892 | struct kvm_xsave* xsave; | |
893 | int ret, i; | |
894 | uint16_t cwd, swd, twd, fop; | |
895 | ||
b9bec74b | 896 | if (!kvm_has_xsave()) { |
f1665b21 | 897 | return kvm_get_fpu(env); |
b9bec74b | 898 | } |
f1665b21 SY |
899 | |
900 | xsave = qemu_memalign(4096, sizeof(struct kvm_xsave)); | |
901 | ret = kvm_vcpu_ioctl(env, KVM_GET_XSAVE, xsave); | |
0f53994f MT |
902 | if (ret < 0) { |
903 | qemu_free(xsave); | |
f1665b21 | 904 | return ret; |
0f53994f | 905 | } |
f1665b21 SY |
906 | |
907 | cwd = (uint16_t)xsave->region[0]; | |
908 | swd = (uint16_t)(xsave->region[0] >> 16); | |
909 | twd = (uint16_t)xsave->region[1]; | |
910 | fop = (uint16_t)(xsave->region[1] >> 16); | |
911 | env->fpstt = (swd >> 11) & 7; | |
912 | env->fpus = swd; | |
913 | env->fpuc = cwd; | |
b9bec74b | 914 | for (i = 0; i < 8; ++i) { |
f1665b21 | 915 | env->fptags[i] = !((twd >> i) & 1); |
b9bec74b | 916 | } |
f1665b21 SY |
917 | env->mxcsr = xsave->region[XSAVE_MXCSR]; |
918 | memcpy(env->fpregs, &xsave->region[XSAVE_ST_SPACE], | |
919 | sizeof env->fpregs); | |
920 | memcpy(env->xmm_regs, &xsave->region[XSAVE_XMM_SPACE], | |
921 | sizeof env->xmm_regs); | |
922 | env->xstate_bv = *(uint64_t *)&xsave->region[XSAVE_XSTATE_BV]; | |
923 | memcpy(env->ymmh_regs, &xsave->region[XSAVE_YMMH_SPACE], | |
924 | sizeof env->ymmh_regs); | |
0f53994f | 925 | qemu_free(xsave); |
f1665b21 SY |
926 | return 0; |
927 | #else | |
928 | return kvm_get_fpu(env); | |
929 | #endif | |
930 | } | |
931 | ||
932 | static int kvm_get_xcrs(CPUState *env) | |
933 | { | |
934 | #ifdef KVM_CAP_XCRS | |
935 | int i, ret; | |
936 | struct kvm_xcrs xcrs; | |
937 | ||
b9bec74b | 938 | if (!kvm_has_xcrs()) { |
f1665b21 | 939 | return 0; |
b9bec74b | 940 | } |
f1665b21 SY |
941 | |
942 | ret = kvm_vcpu_ioctl(env, KVM_GET_XCRS, &xcrs); | |
b9bec74b | 943 | if (ret < 0) { |
f1665b21 | 944 | return ret; |
b9bec74b | 945 | } |
f1665b21 | 946 | |
b9bec74b | 947 | for (i = 0; i < xcrs.nr_xcrs; i++) { |
f1665b21 SY |
948 | /* Only support xcr0 now */ |
949 | if (xcrs.xcrs[0].xcr == 0) { | |
950 | env->xcr0 = xcrs.xcrs[0].value; | |
951 | break; | |
952 | } | |
b9bec74b | 953 | } |
f1665b21 SY |
954 | return 0; |
955 | #else | |
956 | return 0; | |
957 | #endif | |
958 | } | |
959 | ||
05330448 AL |
960 | static int kvm_get_sregs(CPUState *env) |
961 | { | |
962 | struct kvm_sregs sregs; | |
963 | uint32_t hflags; | |
0e607a80 | 964 | int bit, i, ret; |
05330448 AL |
965 | |
966 | ret = kvm_vcpu_ioctl(env, KVM_GET_SREGS, &sregs); | |
b9bec74b | 967 | if (ret < 0) { |
05330448 | 968 | return ret; |
b9bec74b | 969 | } |
05330448 | 970 | |
0e607a80 JK |
971 | /* There can only be one pending IRQ set in the bitmap at a time, so try |
972 | to find it and save its number instead (-1 for none). */ | |
973 | env->interrupt_injected = -1; | |
974 | for (i = 0; i < ARRAY_SIZE(sregs.interrupt_bitmap); i++) { | |
975 | if (sregs.interrupt_bitmap[i]) { | |
976 | bit = ctz64(sregs.interrupt_bitmap[i]); | |
977 | env->interrupt_injected = i * 64 + bit; | |
978 | break; | |
979 | } | |
980 | } | |
05330448 AL |
981 | |
982 | get_seg(&env->segs[R_CS], &sregs.cs); | |
983 | get_seg(&env->segs[R_DS], &sregs.ds); | |
984 | get_seg(&env->segs[R_ES], &sregs.es); | |
985 | get_seg(&env->segs[R_FS], &sregs.fs); | |
986 | get_seg(&env->segs[R_GS], &sregs.gs); | |
987 | get_seg(&env->segs[R_SS], &sregs.ss); | |
988 | ||
989 | get_seg(&env->tr, &sregs.tr); | |
990 | get_seg(&env->ldt, &sregs.ldt); | |
991 | ||
992 | env->idt.limit = sregs.idt.limit; | |
993 | env->idt.base = sregs.idt.base; | |
994 | env->gdt.limit = sregs.gdt.limit; | |
995 | env->gdt.base = sregs.gdt.base; | |
996 | ||
997 | env->cr[0] = sregs.cr0; | |
998 | env->cr[2] = sregs.cr2; | |
999 | env->cr[3] = sregs.cr3; | |
1000 | env->cr[4] = sregs.cr4; | |
1001 | ||
4a942cea | 1002 | cpu_set_apic_base(env->apic_state, sregs.apic_base); |
05330448 AL |
1003 | |
1004 | env->efer = sregs.efer; | |
4a942cea | 1005 | //cpu_set_apic_tpr(env->apic_state, sregs.cr8); |
05330448 | 1006 | |
b9bec74b JK |
1007 | #define HFLAG_COPY_MASK \ |
1008 | ~( HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \ | |
1009 | HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \ | |
1010 | HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \ | |
1011 | HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK) | |
05330448 AL |
1012 | |
1013 | hflags = (env->segs[R_CS].flags >> DESC_DPL_SHIFT) & HF_CPL_MASK; | |
1014 | hflags |= (env->cr[0] & CR0_PE_MASK) << (HF_PE_SHIFT - CR0_PE_SHIFT); | |
1015 | hflags |= (env->cr[0] << (HF_MP_SHIFT - CR0_MP_SHIFT)) & | |
b9bec74b | 1016 | (HF_MP_MASK | HF_EM_MASK | HF_TS_MASK); |
05330448 AL |
1017 | hflags |= (env->eflags & (HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK)); |
1018 | hflags |= (env->cr[4] & CR4_OSFXSR_MASK) << | |
b9bec74b | 1019 | (HF_OSFXSR_SHIFT - CR4_OSFXSR_SHIFT); |
05330448 AL |
1020 | |
1021 | if (env->efer & MSR_EFER_LMA) { | |
1022 | hflags |= HF_LMA_MASK; | |
1023 | } | |
1024 | ||
1025 | if ((hflags & HF_LMA_MASK) && (env->segs[R_CS].flags & DESC_L_MASK)) { | |
1026 | hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK; | |
1027 | } else { | |
1028 | hflags |= (env->segs[R_CS].flags & DESC_B_MASK) >> | |
b9bec74b | 1029 | (DESC_B_SHIFT - HF_CS32_SHIFT); |
05330448 | 1030 | hflags |= (env->segs[R_SS].flags & DESC_B_MASK) >> |
b9bec74b JK |
1031 | (DESC_B_SHIFT - HF_SS32_SHIFT); |
1032 | if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK) || | |
1033 | !(hflags & HF_CS32_MASK)) { | |
1034 | hflags |= HF_ADDSEG_MASK; | |
1035 | } else { | |
1036 | hflags |= ((env->segs[R_DS].base | env->segs[R_ES].base | | |
1037 | env->segs[R_SS].base) != 0) << HF_ADDSEG_SHIFT; | |
1038 | } | |
05330448 AL |
1039 | } |
1040 | env->hflags = (env->hflags & HFLAG_COPY_MASK) | hflags; | |
05330448 AL |
1041 | |
1042 | return 0; | |
1043 | } | |
1044 | ||
1045 | static int kvm_get_msrs(CPUState *env) | |
1046 | { | |
1047 | struct { | |
1048 | struct kvm_msrs info; | |
1049 | struct kvm_msr_entry entries[100]; | |
1050 | } msr_data; | |
1051 | struct kvm_msr_entry *msrs = msr_data.entries; | |
1052 | int ret, i, n; | |
1053 | ||
1054 | n = 0; | |
1055 | msrs[n++].index = MSR_IA32_SYSENTER_CS; | |
1056 | msrs[n++].index = MSR_IA32_SYSENTER_ESP; | |
1057 | msrs[n++].index = MSR_IA32_SYSENTER_EIP; | |
c3a3a7d3 | 1058 | if (has_msr_star) { |
b9bec74b JK |
1059 | msrs[n++].index = MSR_STAR; |
1060 | } | |
c3a3a7d3 | 1061 | if (has_msr_hsave_pa) { |
75b10c43 | 1062 | msrs[n++].index = MSR_VM_HSAVE_PA; |
b9bec74b | 1063 | } |
05330448 AL |
1064 | msrs[n++].index = MSR_IA32_TSC; |
1065 | #ifdef TARGET_X86_64 | |
25d2e361 MT |
1066 | if (lm_capable_kernel) { |
1067 | msrs[n++].index = MSR_CSTAR; | |
1068 | msrs[n++].index = MSR_KERNELGSBASE; | |
1069 | msrs[n++].index = MSR_FMASK; | |
1070 | msrs[n++].index = MSR_LSTAR; | |
1071 | } | |
05330448 | 1072 | #endif |
1a03675d GC |
1073 | msrs[n++].index = MSR_KVM_SYSTEM_TIME; |
1074 | msrs[n++].index = MSR_KVM_WALL_CLOCK; | |
521f0798 | 1075 | #if defined(CONFIG_KVM_PARA) && defined(KVM_CAP_ASYNC_PF) |
c5999bfc JK |
1076 | if (has_msr_async_pf_en) { |
1077 | msrs[n++].index = MSR_KVM_ASYNC_PF_EN; | |
1078 | } | |
f6584ee2 | 1079 | #endif |
1a03675d | 1080 | |
57780495 MT |
1081 | #ifdef KVM_CAP_MCE |
1082 | if (env->mcg_cap) { | |
1083 | msrs[n++].index = MSR_MCG_STATUS; | |
1084 | msrs[n++].index = MSR_MCG_CTL; | |
b9bec74b | 1085 | for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) { |
57780495 | 1086 | msrs[n++].index = MSR_MC0_CTL + i; |
b9bec74b | 1087 | } |
57780495 MT |
1088 | } |
1089 | #endif | |
1090 | ||
05330448 AL |
1091 | msr_data.info.nmsrs = n; |
1092 | ret = kvm_vcpu_ioctl(env, KVM_GET_MSRS, &msr_data); | |
b9bec74b | 1093 | if (ret < 0) { |
05330448 | 1094 | return ret; |
b9bec74b | 1095 | } |
05330448 AL |
1096 | |
1097 | for (i = 0; i < ret; i++) { | |
1098 | switch (msrs[i].index) { | |
1099 | case MSR_IA32_SYSENTER_CS: | |
1100 | env->sysenter_cs = msrs[i].data; | |
1101 | break; | |
1102 | case MSR_IA32_SYSENTER_ESP: | |
1103 | env->sysenter_esp = msrs[i].data; | |
1104 | break; | |
1105 | case MSR_IA32_SYSENTER_EIP: | |
1106 | env->sysenter_eip = msrs[i].data; | |
1107 | break; | |
1108 | case MSR_STAR: | |
1109 | env->star = msrs[i].data; | |
1110 | break; | |
1111 | #ifdef TARGET_X86_64 | |
1112 | case MSR_CSTAR: | |
1113 | env->cstar = msrs[i].data; | |
1114 | break; | |
1115 | case MSR_KERNELGSBASE: | |
1116 | env->kernelgsbase = msrs[i].data; | |
1117 | break; | |
1118 | case MSR_FMASK: | |
1119 | env->fmask = msrs[i].data; | |
1120 | break; | |
1121 | case MSR_LSTAR: | |
1122 | env->lstar = msrs[i].data; | |
1123 | break; | |
1124 | #endif | |
1125 | case MSR_IA32_TSC: | |
1126 | env->tsc = msrs[i].data; | |
1127 | break; | |
aa851e36 MT |
1128 | case MSR_VM_HSAVE_PA: |
1129 | env->vm_hsave = msrs[i].data; | |
1130 | break; | |
1a03675d GC |
1131 | case MSR_KVM_SYSTEM_TIME: |
1132 | env->system_time_msr = msrs[i].data; | |
1133 | break; | |
1134 | case MSR_KVM_WALL_CLOCK: | |
1135 | env->wall_clock_msr = msrs[i].data; | |
1136 | break; | |
57780495 MT |
1137 | #ifdef KVM_CAP_MCE |
1138 | case MSR_MCG_STATUS: | |
1139 | env->mcg_status = msrs[i].data; | |
1140 | break; | |
1141 | case MSR_MCG_CTL: | |
1142 | env->mcg_ctl = msrs[i].data; | |
1143 | break; | |
1144 | #endif | |
1145 | default: | |
1146 | #ifdef KVM_CAP_MCE | |
1147 | if (msrs[i].index >= MSR_MC0_CTL && | |
1148 | msrs[i].index < MSR_MC0_CTL + (env->mcg_cap & 0xff) * 4) { | |
1149 | env->mce_banks[msrs[i].index - MSR_MC0_CTL] = msrs[i].data; | |
57780495 MT |
1150 | } |
1151 | #endif | |
d8da8574 | 1152 | break; |
521f0798 | 1153 | #if defined(CONFIG_KVM_PARA) && defined(KVM_CAP_ASYNC_PF) |
f6584ee2 GN |
1154 | case MSR_KVM_ASYNC_PF_EN: |
1155 | env->async_pf_en_msr = msrs[i].data; | |
1156 | break; | |
1157 | #endif | |
05330448 AL |
1158 | } |
1159 | } | |
1160 | ||
1161 | return 0; | |
1162 | } | |
1163 | ||
9bdbe550 HB |
1164 | static int kvm_put_mp_state(CPUState *env) |
1165 | { | |
1166 | struct kvm_mp_state mp_state = { .mp_state = env->mp_state }; | |
1167 | ||
1168 | return kvm_vcpu_ioctl(env, KVM_SET_MP_STATE, &mp_state); | |
1169 | } | |
1170 | ||
1171 | static int kvm_get_mp_state(CPUState *env) | |
1172 | { | |
1173 | struct kvm_mp_state mp_state; | |
1174 | int ret; | |
1175 | ||
1176 | ret = kvm_vcpu_ioctl(env, KVM_GET_MP_STATE, &mp_state); | |
1177 | if (ret < 0) { | |
1178 | return ret; | |
1179 | } | |
1180 | env->mp_state = mp_state.mp_state; | |
c14750e8 JK |
1181 | if (kvm_irqchip_in_kernel()) { |
1182 | env->halted = (mp_state.mp_state == KVM_MP_STATE_HALTED); | |
1183 | } | |
9bdbe550 HB |
1184 | return 0; |
1185 | } | |
1186 | ||
ea643051 | 1187 | static int kvm_put_vcpu_events(CPUState *env, int level) |
a0fb002c JK |
1188 | { |
1189 | #ifdef KVM_CAP_VCPU_EVENTS | |
1190 | struct kvm_vcpu_events events; | |
1191 | ||
1192 | if (!kvm_has_vcpu_events()) { | |
1193 | return 0; | |
1194 | } | |
1195 | ||
31827373 JK |
1196 | events.exception.injected = (env->exception_injected >= 0); |
1197 | events.exception.nr = env->exception_injected; | |
a0fb002c JK |
1198 | events.exception.has_error_code = env->has_error_code; |
1199 | events.exception.error_code = env->error_code; | |
1200 | ||
1201 | events.interrupt.injected = (env->interrupt_injected >= 0); | |
1202 | events.interrupt.nr = env->interrupt_injected; | |
1203 | events.interrupt.soft = env->soft_interrupt; | |
1204 | ||
1205 | events.nmi.injected = env->nmi_injected; | |
1206 | events.nmi.pending = env->nmi_pending; | |
1207 | events.nmi.masked = !!(env->hflags2 & HF2_NMI_MASK); | |
1208 | ||
1209 | events.sipi_vector = env->sipi_vector; | |
1210 | ||
ea643051 JK |
1211 | events.flags = 0; |
1212 | if (level >= KVM_PUT_RESET_STATE) { | |
1213 | events.flags |= | |
1214 | KVM_VCPUEVENT_VALID_NMI_PENDING | KVM_VCPUEVENT_VALID_SIPI_VECTOR; | |
1215 | } | |
aee028b9 | 1216 | |
a0fb002c JK |
1217 | return kvm_vcpu_ioctl(env, KVM_SET_VCPU_EVENTS, &events); |
1218 | #else | |
1219 | return 0; | |
1220 | #endif | |
1221 | } | |
1222 | ||
1223 | static int kvm_get_vcpu_events(CPUState *env) | |
1224 | { | |
1225 | #ifdef KVM_CAP_VCPU_EVENTS | |
1226 | struct kvm_vcpu_events events; | |
1227 | int ret; | |
1228 | ||
1229 | if (!kvm_has_vcpu_events()) { | |
1230 | return 0; | |
1231 | } | |
1232 | ||
1233 | ret = kvm_vcpu_ioctl(env, KVM_GET_VCPU_EVENTS, &events); | |
1234 | if (ret < 0) { | |
1235 | return ret; | |
1236 | } | |
31827373 | 1237 | env->exception_injected = |
a0fb002c JK |
1238 | events.exception.injected ? events.exception.nr : -1; |
1239 | env->has_error_code = events.exception.has_error_code; | |
1240 | env->error_code = events.exception.error_code; | |
1241 | ||
1242 | env->interrupt_injected = | |
1243 | events.interrupt.injected ? events.interrupt.nr : -1; | |
1244 | env->soft_interrupt = events.interrupt.soft; | |
1245 | ||
1246 | env->nmi_injected = events.nmi.injected; | |
1247 | env->nmi_pending = events.nmi.pending; | |
1248 | if (events.nmi.masked) { | |
1249 | env->hflags2 |= HF2_NMI_MASK; | |
1250 | } else { | |
1251 | env->hflags2 &= ~HF2_NMI_MASK; | |
1252 | } | |
1253 | ||
1254 | env->sipi_vector = events.sipi_vector; | |
1255 | #endif | |
1256 | ||
1257 | return 0; | |
1258 | } | |
1259 | ||
b0b1d690 JK |
1260 | static int kvm_guest_debug_workarounds(CPUState *env) |
1261 | { | |
1262 | int ret = 0; | |
1263 | #ifdef KVM_CAP_SET_GUEST_DEBUG | |
1264 | unsigned long reinject_trap = 0; | |
1265 | ||
1266 | if (!kvm_has_vcpu_events()) { | |
1267 | if (env->exception_injected == 1) { | |
1268 | reinject_trap = KVM_GUESTDBG_INJECT_DB; | |
1269 | } else if (env->exception_injected == 3) { | |
1270 | reinject_trap = KVM_GUESTDBG_INJECT_BP; | |
1271 | } | |
1272 | env->exception_injected = -1; | |
1273 | } | |
1274 | ||
1275 | /* | |
1276 | * Kernels before KVM_CAP_X86_ROBUST_SINGLESTEP overwrote flags.TF | |
1277 | * injected via SET_GUEST_DEBUG while updating GP regs. Work around this | |
1278 | * by updating the debug state once again if single-stepping is on. | |
1279 | * Another reason to call kvm_update_guest_debug here is a pending debug | |
1280 | * trap raise by the guest. On kernels without SET_VCPU_EVENTS we have to | |
1281 | * reinject them via SET_GUEST_DEBUG. | |
1282 | */ | |
1283 | if (reinject_trap || | |
1284 | (!kvm_has_robust_singlestep() && env->singlestep_enabled)) { | |
1285 | ret = kvm_update_guest_debug(env, reinject_trap); | |
1286 | } | |
1287 | #endif /* KVM_CAP_SET_GUEST_DEBUG */ | |
1288 | return ret; | |
1289 | } | |
1290 | ||
ff44f1a3 JK |
1291 | static int kvm_put_debugregs(CPUState *env) |
1292 | { | |
1293 | #ifdef KVM_CAP_DEBUGREGS | |
1294 | struct kvm_debugregs dbgregs; | |
1295 | int i; | |
1296 | ||
1297 | if (!kvm_has_debugregs()) { | |
1298 | return 0; | |
1299 | } | |
1300 | ||
1301 | for (i = 0; i < 4; i++) { | |
1302 | dbgregs.db[i] = env->dr[i]; | |
1303 | } | |
1304 | dbgregs.dr6 = env->dr[6]; | |
1305 | dbgregs.dr7 = env->dr[7]; | |
1306 | dbgregs.flags = 0; | |
1307 | ||
1308 | return kvm_vcpu_ioctl(env, KVM_SET_DEBUGREGS, &dbgregs); | |
1309 | #else | |
1310 | return 0; | |
1311 | #endif | |
1312 | } | |
1313 | ||
1314 | static int kvm_get_debugregs(CPUState *env) | |
1315 | { | |
1316 | #ifdef KVM_CAP_DEBUGREGS | |
1317 | struct kvm_debugregs dbgregs; | |
1318 | int i, ret; | |
1319 | ||
1320 | if (!kvm_has_debugregs()) { | |
1321 | return 0; | |
1322 | } | |
1323 | ||
1324 | ret = kvm_vcpu_ioctl(env, KVM_GET_DEBUGREGS, &dbgregs); | |
1325 | if (ret < 0) { | |
b9bec74b | 1326 | return ret; |
ff44f1a3 JK |
1327 | } |
1328 | for (i = 0; i < 4; i++) { | |
1329 | env->dr[i] = dbgregs.db[i]; | |
1330 | } | |
1331 | env->dr[4] = env->dr[6] = dbgregs.dr6; | |
1332 | env->dr[5] = env->dr[7] = dbgregs.dr7; | |
1333 | #endif | |
1334 | ||
1335 | return 0; | |
1336 | } | |
1337 | ||
ea375f9a | 1338 | int kvm_arch_put_registers(CPUState *env, int level) |
05330448 AL |
1339 | { |
1340 | int ret; | |
1341 | ||
dbaa07c4 JK |
1342 | assert(cpu_is_stopped(env) || qemu_cpu_self(env)); |
1343 | ||
05330448 | 1344 | ret = kvm_getput_regs(env, 1); |
b9bec74b | 1345 | if (ret < 0) { |
05330448 | 1346 | return ret; |
b9bec74b | 1347 | } |
f1665b21 | 1348 | ret = kvm_put_xsave(env); |
b9bec74b | 1349 | if (ret < 0) { |
f1665b21 | 1350 | return ret; |
b9bec74b | 1351 | } |
f1665b21 | 1352 | ret = kvm_put_xcrs(env); |
b9bec74b | 1353 | if (ret < 0) { |
05330448 | 1354 | return ret; |
b9bec74b | 1355 | } |
05330448 | 1356 | ret = kvm_put_sregs(env); |
b9bec74b | 1357 | if (ret < 0) { |
05330448 | 1358 | return ret; |
b9bec74b | 1359 | } |
ea643051 | 1360 | ret = kvm_put_msrs(env, level); |
b9bec74b | 1361 | if (ret < 0) { |
05330448 | 1362 | return ret; |
b9bec74b | 1363 | } |
ea643051 JK |
1364 | if (level >= KVM_PUT_RESET_STATE) { |
1365 | ret = kvm_put_mp_state(env); | |
b9bec74b | 1366 | if (ret < 0) { |
ea643051 | 1367 | return ret; |
b9bec74b | 1368 | } |
ea643051 | 1369 | } |
ea643051 | 1370 | ret = kvm_put_vcpu_events(env, level); |
b9bec74b | 1371 | if (ret < 0) { |
a0fb002c | 1372 | return ret; |
b9bec74b | 1373 | } |
0d75a9ec | 1374 | ret = kvm_put_debugregs(env); |
b9bec74b | 1375 | if (ret < 0) { |
b0b1d690 | 1376 | return ret; |
b9bec74b | 1377 | } |
b0b1d690 JK |
1378 | /* must be last */ |
1379 | ret = kvm_guest_debug_workarounds(env); | |
b9bec74b | 1380 | if (ret < 0) { |
ff44f1a3 | 1381 | return ret; |
b9bec74b | 1382 | } |
05330448 AL |
1383 | return 0; |
1384 | } | |
1385 | ||
1386 | int kvm_arch_get_registers(CPUState *env) | |
1387 | { | |
1388 | int ret; | |
1389 | ||
dbaa07c4 JK |
1390 | assert(cpu_is_stopped(env) || qemu_cpu_self(env)); |
1391 | ||
05330448 | 1392 | ret = kvm_getput_regs(env, 0); |
b9bec74b | 1393 | if (ret < 0) { |
05330448 | 1394 | return ret; |
b9bec74b | 1395 | } |
f1665b21 | 1396 | ret = kvm_get_xsave(env); |
b9bec74b | 1397 | if (ret < 0) { |
f1665b21 | 1398 | return ret; |
b9bec74b | 1399 | } |
f1665b21 | 1400 | ret = kvm_get_xcrs(env); |
b9bec74b | 1401 | if (ret < 0) { |
05330448 | 1402 | return ret; |
b9bec74b | 1403 | } |
05330448 | 1404 | ret = kvm_get_sregs(env); |
b9bec74b | 1405 | if (ret < 0) { |
05330448 | 1406 | return ret; |
b9bec74b | 1407 | } |
05330448 | 1408 | ret = kvm_get_msrs(env); |
b9bec74b | 1409 | if (ret < 0) { |
05330448 | 1410 | return ret; |
b9bec74b | 1411 | } |
5a2e3c2e | 1412 | ret = kvm_get_mp_state(env); |
b9bec74b | 1413 | if (ret < 0) { |
5a2e3c2e | 1414 | return ret; |
b9bec74b | 1415 | } |
a0fb002c | 1416 | ret = kvm_get_vcpu_events(env); |
b9bec74b | 1417 | if (ret < 0) { |
a0fb002c | 1418 | return ret; |
b9bec74b | 1419 | } |
ff44f1a3 | 1420 | ret = kvm_get_debugregs(env); |
b9bec74b | 1421 | if (ret < 0) { |
ff44f1a3 | 1422 | return ret; |
b9bec74b | 1423 | } |
05330448 AL |
1424 | return 0; |
1425 | } | |
1426 | ||
1427 | int kvm_arch_pre_run(CPUState *env, struct kvm_run *run) | |
1428 | { | |
9ccfac9e JK |
1429 | /* Force the VCPU out of its inner loop to process the INIT request */ |
1430 | if (env->interrupt_request & CPU_INTERRUPT_INIT) { | |
1431 | env->exit_request = 1; | |
1432 | } | |
1433 | ||
276ce815 LJ |
1434 | /* Inject NMI */ |
1435 | if (env->interrupt_request & CPU_INTERRUPT_NMI) { | |
1436 | env->interrupt_request &= ~CPU_INTERRUPT_NMI; | |
1437 | DPRINTF("injected NMI\n"); | |
1438 | kvm_vcpu_ioctl(env, KVM_NMI); | |
1439 | } | |
1440 | ||
05330448 AL |
1441 | /* Try to inject an interrupt if the guest can accept it */ |
1442 | if (run->ready_for_interrupt_injection && | |
1443 | (env->interrupt_request & CPU_INTERRUPT_HARD) && | |
1444 | (env->eflags & IF_MASK)) { | |
1445 | int irq; | |
1446 | ||
1447 | env->interrupt_request &= ~CPU_INTERRUPT_HARD; | |
1448 | irq = cpu_get_pic_interrupt(env); | |
1449 | if (irq >= 0) { | |
1450 | struct kvm_interrupt intr; | |
1451 | intr.irq = irq; | |
1452 | /* FIXME: errors */ | |
8c0d577e | 1453 | DPRINTF("injected interrupt %d\n", irq); |
05330448 AL |
1454 | kvm_vcpu_ioctl(env, KVM_INTERRUPT, &intr); |
1455 | } | |
1456 | } | |
1457 | ||
1458 | /* If we have an interrupt but the guest is not ready to receive an | |
1459 | * interrupt, request an interrupt window exit. This will | |
1460 | * cause a return to userspace as soon as the guest is ready to | |
1461 | * receive interrupts. */ | |
b9bec74b | 1462 | if ((env->interrupt_request & CPU_INTERRUPT_HARD)) { |
05330448 | 1463 | run->request_interrupt_window = 1; |
b9bec74b | 1464 | } else { |
05330448 | 1465 | run->request_interrupt_window = 0; |
b9bec74b | 1466 | } |
05330448 | 1467 | |
8c0d577e | 1468 | DPRINTF("setting tpr\n"); |
4a942cea | 1469 | run->cr8 = cpu_get_apic_tpr(env->apic_state); |
05330448 AL |
1470 | |
1471 | return 0; | |
1472 | } | |
1473 | ||
1474 | int kvm_arch_post_run(CPUState *env, struct kvm_run *run) | |
1475 | { | |
b9bec74b | 1476 | if (run->if_flag) { |
05330448 | 1477 | env->eflags |= IF_MASK; |
b9bec74b | 1478 | } else { |
05330448 | 1479 | env->eflags &= ~IF_MASK; |
b9bec74b | 1480 | } |
4a942cea BS |
1481 | cpu_set_apic_tpr(env->apic_state, run->cr8); |
1482 | cpu_set_apic_base(env->apic_state, run->apic_base); | |
05330448 AL |
1483 | |
1484 | return 0; | |
1485 | } | |
1486 | ||
0af691d7 MT |
1487 | int kvm_arch_process_irqchip_events(CPUState *env) |
1488 | { | |
1489 | if (env->interrupt_request & CPU_INTERRUPT_INIT) { | |
1490 | kvm_cpu_synchronize_state(env); | |
1491 | do_cpu_init(env); | |
1492 | env->exception_index = EXCP_HALTED; | |
1493 | } | |
1494 | ||
1495 | if (env->interrupt_request & CPU_INTERRUPT_SIPI) { | |
1496 | kvm_cpu_synchronize_state(env); | |
1497 | do_cpu_sipi(env); | |
1498 | } | |
1499 | ||
1500 | return env->halted; | |
1501 | } | |
1502 | ||
05330448 AL |
1503 | static int kvm_handle_halt(CPUState *env) |
1504 | { | |
1505 | if (!((env->interrupt_request & CPU_INTERRUPT_HARD) && | |
1506 | (env->eflags & IF_MASK)) && | |
1507 | !(env->interrupt_request & CPU_INTERRUPT_NMI)) { | |
1508 | env->halted = 1; | |
1509 | env->exception_index = EXCP_HLT; | |
1510 | return 0; | |
1511 | } | |
1512 | ||
1513 | return 1; | |
1514 | } | |
1515 | ||
bb44e0d1 JK |
1516 | static bool host_supports_vmx(void) |
1517 | { | |
1518 | uint32_t ecx, unused; | |
1519 | ||
1520 | host_cpuid(1, 0, &unused, &unused, &ecx, &unused); | |
1521 | return ecx & CPUID_EXT_VMX; | |
1522 | } | |
1523 | ||
1524 | #define VMX_INVALID_GUEST_STATE 0x80000021 | |
1525 | ||
05330448 AL |
1526 | int kvm_arch_handle_exit(CPUState *env, struct kvm_run *run) |
1527 | { | |
bb44e0d1 | 1528 | uint64_t code; |
05330448 AL |
1529 | int ret = 0; |
1530 | ||
1531 | switch (run->exit_reason) { | |
1532 | case KVM_EXIT_HLT: | |
8c0d577e | 1533 | DPRINTF("handle_hlt\n"); |
05330448 AL |
1534 | ret = kvm_handle_halt(env); |
1535 | break; | |
646042e1 JK |
1536 | case KVM_EXIT_SET_TPR: |
1537 | ret = 1; | |
1538 | break; | |
bb44e0d1 JK |
1539 | case KVM_EXIT_FAIL_ENTRY: |
1540 | code = run->fail_entry.hardware_entry_failure_reason; | |
1541 | fprintf(stderr, "KVM: entry failed, hardware error 0x%" PRIx64 "\n", | |
1542 | code); | |
1543 | if (host_supports_vmx() && code == VMX_INVALID_GUEST_STATE) { | |
1544 | fprintf(stderr, | |
1545 | "\nIf you're runnning a guest on an Intel machine without " | |
1546 | "unrestricted mode\n" | |
1547 | "support, the failure can be most likely due to the guest " | |
1548 | "entering an invalid\n" | |
1549 | "state for Intel VT. For example, the guest maybe running " | |
1550 | "in big real mode\n" | |
1551 | "which is not supported on less recent Intel processors." | |
1552 | "\n\n"); | |
1553 | } | |
1554 | ret = -1; | |
1555 | break; | |
1556 | case KVM_EXIT_EXCEPTION: | |
1557 | fprintf(stderr, "KVM: exception %d exit (error code 0x%x)\n", | |
1558 | run->ex.exception, run->ex.error_code); | |
1559 | ret = -1; | |
1560 | break; | |
73aaec4a JK |
1561 | default: |
1562 | fprintf(stderr, "KVM: unknown exit reason %d\n", run->exit_reason); | |
1563 | ret = -1; | |
1564 | break; | |
05330448 AL |
1565 | } |
1566 | ||
1567 | return ret; | |
1568 | } | |
e22a25c9 AL |
1569 | |
1570 | #ifdef KVM_CAP_SET_GUEST_DEBUG | |
e22a25c9 AL |
1571 | int kvm_arch_insert_sw_breakpoint(CPUState *env, struct kvm_sw_breakpoint *bp) |
1572 | { | |
38972938 | 1573 | static const uint8_t int3 = 0xcc; |
64bf3f4e | 1574 | |
e22a25c9 | 1575 | if (cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&bp->saved_insn, 1, 0) || |
b9bec74b | 1576 | cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&int3, 1, 1)) { |
e22a25c9 | 1577 | return -EINVAL; |
b9bec74b | 1578 | } |
e22a25c9 AL |
1579 | return 0; |
1580 | } | |
1581 | ||
1582 | int kvm_arch_remove_sw_breakpoint(CPUState *env, struct kvm_sw_breakpoint *bp) | |
1583 | { | |
1584 | uint8_t int3; | |
1585 | ||
1586 | if (cpu_memory_rw_debug(env, bp->pc, &int3, 1, 0) || int3 != 0xcc || | |
b9bec74b | 1587 | cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&bp->saved_insn, 1, 1)) { |
e22a25c9 | 1588 | return -EINVAL; |
b9bec74b | 1589 | } |
e22a25c9 AL |
1590 | return 0; |
1591 | } | |
1592 | ||
1593 | static struct { | |
1594 | target_ulong addr; | |
1595 | int len; | |
1596 | int type; | |
1597 | } hw_breakpoint[4]; | |
1598 | ||
1599 | static int nb_hw_breakpoint; | |
1600 | ||
1601 | static int find_hw_breakpoint(target_ulong addr, int len, int type) | |
1602 | { | |
1603 | int n; | |
1604 | ||
b9bec74b | 1605 | for (n = 0; n < nb_hw_breakpoint; n++) { |
e22a25c9 | 1606 | if (hw_breakpoint[n].addr == addr && hw_breakpoint[n].type == type && |
b9bec74b | 1607 | (hw_breakpoint[n].len == len || len == -1)) { |
e22a25c9 | 1608 | return n; |
b9bec74b JK |
1609 | } |
1610 | } | |
e22a25c9 AL |
1611 | return -1; |
1612 | } | |
1613 | ||
1614 | int kvm_arch_insert_hw_breakpoint(target_ulong addr, | |
1615 | target_ulong len, int type) | |
1616 | { | |
1617 | switch (type) { | |
1618 | case GDB_BREAKPOINT_HW: | |
1619 | len = 1; | |
1620 | break; | |
1621 | case GDB_WATCHPOINT_WRITE: | |
1622 | case GDB_WATCHPOINT_ACCESS: | |
1623 | switch (len) { | |
1624 | case 1: | |
1625 | break; | |
1626 | case 2: | |
1627 | case 4: | |
1628 | case 8: | |
b9bec74b | 1629 | if (addr & (len - 1)) { |
e22a25c9 | 1630 | return -EINVAL; |
b9bec74b | 1631 | } |
e22a25c9 AL |
1632 | break; |
1633 | default: | |
1634 | return -EINVAL; | |
1635 | } | |
1636 | break; | |
1637 | default: | |
1638 | return -ENOSYS; | |
1639 | } | |
1640 | ||
b9bec74b | 1641 | if (nb_hw_breakpoint == 4) { |
e22a25c9 | 1642 | return -ENOBUFS; |
b9bec74b JK |
1643 | } |
1644 | if (find_hw_breakpoint(addr, len, type) >= 0) { | |
e22a25c9 | 1645 | return -EEXIST; |
b9bec74b | 1646 | } |
e22a25c9 AL |
1647 | hw_breakpoint[nb_hw_breakpoint].addr = addr; |
1648 | hw_breakpoint[nb_hw_breakpoint].len = len; | |
1649 | hw_breakpoint[nb_hw_breakpoint].type = type; | |
1650 | nb_hw_breakpoint++; | |
1651 | ||
1652 | return 0; | |
1653 | } | |
1654 | ||
1655 | int kvm_arch_remove_hw_breakpoint(target_ulong addr, | |
1656 | target_ulong len, int type) | |
1657 | { | |
1658 | int n; | |
1659 | ||
1660 | n = find_hw_breakpoint(addr, (type == GDB_BREAKPOINT_HW) ? 1 : len, type); | |
b9bec74b | 1661 | if (n < 0) { |
e22a25c9 | 1662 | return -ENOENT; |
b9bec74b | 1663 | } |
e22a25c9 AL |
1664 | nb_hw_breakpoint--; |
1665 | hw_breakpoint[n] = hw_breakpoint[nb_hw_breakpoint]; | |
1666 | ||
1667 | return 0; | |
1668 | } | |
1669 | ||
1670 | void kvm_arch_remove_all_hw_breakpoints(void) | |
1671 | { | |
1672 | nb_hw_breakpoint = 0; | |
1673 | } | |
1674 | ||
1675 | static CPUWatchpoint hw_watchpoint; | |
1676 | ||
1677 | int kvm_arch_debug(struct kvm_debug_exit_arch *arch_info) | |
1678 | { | |
1679 | int handle = 0; | |
1680 | int n; | |
1681 | ||
1682 | if (arch_info->exception == 1) { | |
1683 | if (arch_info->dr6 & (1 << 14)) { | |
b9bec74b | 1684 | if (cpu_single_env->singlestep_enabled) { |
e22a25c9 | 1685 | handle = 1; |
b9bec74b | 1686 | } |
e22a25c9 | 1687 | } else { |
b9bec74b JK |
1688 | for (n = 0; n < 4; n++) { |
1689 | if (arch_info->dr6 & (1 << n)) { | |
e22a25c9 AL |
1690 | switch ((arch_info->dr7 >> (16 + n*4)) & 0x3) { |
1691 | case 0x0: | |
1692 | handle = 1; | |
1693 | break; | |
1694 | case 0x1: | |
1695 | handle = 1; | |
1696 | cpu_single_env->watchpoint_hit = &hw_watchpoint; | |
1697 | hw_watchpoint.vaddr = hw_breakpoint[n].addr; | |
1698 | hw_watchpoint.flags = BP_MEM_WRITE; | |
1699 | break; | |
1700 | case 0x3: | |
1701 | handle = 1; | |
1702 | cpu_single_env->watchpoint_hit = &hw_watchpoint; | |
1703 | hw_watchpoint.vaddr = hw_breakpoint[n].addr; | |
1704 | hw_watchpoint.flags = BP_MEM_ACCESS; | |
1705 | break; | |
1706 | } | |
b9bec74b JK |
1707 | } |
1708 | } | |
e22a25c9 | 1709 | } |
b9bec74b | 1710 | } else if (kvm_find_sw_breakpoint(cpu_single_env, arch_info->pc)) { |
e22a25c9 | 1711 | handle = 1; |
b9bec74b | 1712 | } |
b0b1d690 JK |
1713 | if (!handle) { |
1714 | cpu_synchronize_state(cpu_single_env); | |
1715 | assert(cpu_single_env->exception_injected == -1); | |
1716 | ||
1717 | cpu_single_env->exception_injected = arch_info->exception; | |
1718 | cpu_single_env->has_error_code = 0; | |
1719 | } | |
e22a25c9 AL |
1720 | |
1721 | return handle; | |
1722 | } | |
1723 | ||
1724 | void kvm_arch_update_guest_debug(CPUState *env, struct kvm_guest_debug *dbg) | |
1725 | { | |
1726 | const uint8_t type_code[] = { | |
1727 | [GDB_BREAKPOINT_HW] = 0x0, | |
1728 | [GDB_WATCHPOINT_WRITE] = 0x1, | |
1729 | [GDB_WATCHPOINT_ACCESS] = 0x3 | |
1730 | }; | |
1731 | const uint8_t len_code[] = { | |
1732 | [1] = 0x0, [2] = 0x1, [4] = 0x3, [8] = 0x2 | |
1733 | }; | |
1734 | int n; | |
1735 | ||
b9bec74b | 1736 | if (kvm_sw_breakpoints_active(env)) { |
e22a25c9 | 1737 | dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP; |
b9bec74b | 1738 | } |
e22a25c9 AL |
1739 | if (nb_hw_breakpoint > 0) { |
1740 | dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP; | |
1741 | dbg->arch.debugreg[7] = 0x0600; | |
1742 | for (n = 0; n < nb_hw_breakpoint; n++) { | |
1743 | dbg->arch.debugreg[n] = hw_breakpoint[n].addr; | |
1744 | dbg->arch.debugreg[7] |= (2 << (n * 2)) | | |
1745 | (type_code[hw_breakpoint[n].type] << (16 + n*4)) | | |
95c077c9 | 1746 | ((uint32_t)len_code[hw_breakpoint[n].len] << (18 + n*4)); |
e22a25c9 AL |
1747 | } |
1748 | } | |
1749 | } | |
1750 | #endif /* KVM_CAP_SET_GUEST_DEBUG */ | |
4513d923 GN |
1751 | |
1752 | bool kvm_arch_stop_on_emulation_error(CPUState *env) | |
1753 | { | |
b9bec74b JK |
1754 | return !(env->cr[0] & CR0_PE_MASK) || |
1755 | ((env->segs[R_CS].selector & 3) != 3); | |
4513d923 GN |
1756 | } |
1757 | ||
c0532a76 MT |
1758 | static void hardware_memory_error(void) |
1759 | { | |
1760 | fprintf(stderr, "Hardware memory error!\n"); | |
1761 | exit(1); | |
1762 | } | |
1763 | ||
f71ac88f HS |
1764 | #ifdef KVM_CAP_MCE |
1765 | static void kvm_mce_broadcast_rest(CPUState *env) | |
1766 | { | |
7cc2cc3e JD |
1767 | struct kvm_x86_mce mce = { |
1768 | .bank = 1, | |
1769 | .status = MCI_STATUS_VAL | MCI_STATUS_UC, | |
1770 | .mcg_status = MCG_STATUS_MCIP | MCG_STATUS_RIPV, | |
1771 | .addr = 0, | |
1772 | .misc = 0, | |
1773 | }; | |
f71ac88f | 1774 | CPUState *cenv; |
f71ac88f HS |
1775 | |
1776 | /* Broadcast MCA signal for processor version 06H_EH and above */ | |
2bd3e04c | 1777 | if (cpu_x86_support_mca_broadcast(env)) { |
f71ac88f HS |
1778 | for (cenv = first_cpu; cenv != NULL; cenv = cenv->next_cpu) { |
1779 | if (cenv == env) { | |
1780 | continue; | |
1781 | } | |
7cc2cc3e | 1782 | kvm_inject_x86_mce_on(cenv, &mce, ABORT_ON_ERROR); |
f71ac88f HS |
1783 | } |
1784 | } | |
1785 | } | |
e387c338 JD |
1786 | |
1787 | static void kvm_mce_inj_srar_dataload(CPUState *env, target_phys_addr_t paddr) | |
1788 | { | |
1789 | struct kvm_x86_mce mce = { | |
1790 | .bank = 9, | |
1791 | .status = MCI_STATUS_VAL | MCI_STATUS_UC | MCI_STATUS_EN | |
1792 | | MCI_STATUS_MISCV | MCI_STATUS_ADDRV | MCI_STATUS_S | |
1793 | | MCI_STATUS_AR | 0x134, | |
1794 | .mcg_status = MCG_STATUS_MCIP | MCG_STATUS_EIPV, | |
1795 | .addr = paddr, | |
1796 | .misc = (MCM_ADDR_PHYS << 6) | 0xc, | |
1797 | }; | |
1798 | int r; | |
1799 | ||
1800 | r = kvm_set_mce(env, &mce); | |
1801 | if (r < 0) { | |
1802 | fprintf(stderr, "kvm_set_mce: %s\n", strerror(errno)); | |
1803 | abort(); | |
1804 | } | |
1805 | kvm_mce_broadcast_rest(env); | |
1806 | } | |
1807 | ||
1808 | static void kvm_mce_inj_srao_memscrub(CPUState *env, target_phys_addr_t paddr) | |
1809 | { | |
1810 | struct kvm_x86_mce mce = { | |
1811 | .bank = 9, | |
1812 | .status = MCI_STATUS_VAL | MCI_STATUS_UC | MCI_STATUS_EN | |
1813 | | MCI_STATUS_MISCV | MCI_STATUS_ADDRV | MCI_STATUS_S | |
1814 | | 0xc0, | |
1815 | .mcg_status = MCG_STATUS_MCIP | MCG_STATUS_RIPV, | |
1816 | .addr = paddr, | |
1817 | .misc = (MCM_ADDR_PHYS << 6) | 0xc, | |
1818 | }; | |
1819 | int r; | |
1820 | ||
1821 | r = kvm_set_mce(env, &mce); | |
1822 | if (r < 0) { | |
1823 | fprintf(stderr, "kvm_set_mce: %s\n", strerror(errno)); | |
1824 | abort(); | |
1825 | } | |
1826 | kvm_mce_broadcast_rest(env); | |
1827 | } | |
1828 | ||
1829 | static void kvm_mce_inj_srao_memscrub2(CPUState *env, target_phys_addr_t paddr) | |
1830 | { | |
7cc2cc3e JD |
1831 | struct kvm_x86_mce mce = { |
1832 | .bank = 9, | |
1833 | .status = MCI_STATUS_VAL | MCI_STATUS_UC | MCI_STATUS_EN | |
1834 | | MCI_STATUS_MISCV | MCI_STATUS_ADDRV | MCI_STATUS_S | |
1835 | | 0xc0, | |
1836 | .mcg_status = MCG_STATUS_MCIP | MCG_STATUS_RIPV, | |
1837 | .addr = paddr, | |
1838 | .misc = (MCM_ADDR_PHYS << 6) | 0xc, | |
1839 | }; | |
e387c338 | 1840 | |
7cc2cc3e | 1841 | kvm_inject_x86_mce_on(env, &mce, ABORT_ON_ERROR); |
e387c338 JD |
1842 | kvm_mce_broadcast_rest(env); |
1843 | } | |
1844 | ||
f71ac88f HS |
1845 | #endif |
1846 | ||
a1b87fe0 | 1847 | int kvm_arch_on_sigbus_vcpu(CPUState *env, int code, void *addr) |
c0532a76 MT |
1848 | { |
1849 | #if defined(KVM_CAP_MCE) | |
c0532a76 MT |
1850 | void *vaddr; |
1851 | ram_addr_t ram_addr; | |
1852 | target_phys_addr_t paddr; | |
c0532a76 MT |
1853 | |
1854 | if ((env->mcg_cap & MCG_SER_P) && addr | |
1855 | && (code == BUS_MCEERR_AR | |
1856 | || code == BUS_MCEERR_AO)) { | |
c0532a76 MT |
1857 | vaddr = (void *)addr; |
1858 | if (qemu_ram_addr_from_host(vaddr, &ram_addr) || | |
1859 | !kvm_physical_memory_addr_from_ram(env->kvm_state, ram_addr, &paddr)) { | |
1860 | fprintf(stderr, "Hardware memory error for memory used by " | |
1861 | "QEMU itself instead of guest system!\n"); | |
1862 | /* Hope we are lucky for AO MCE */ | |
1863 | if (code == BUS_MCEERR_AO) { | |
1864 | return 0; | |
1865 | } else { | |
1866 | hardware_memory_error(); | |
1867 | } | |
1868 | } | |
e387c338 JD |
1869 | |
1870 | if (code == BUS_MCEERR_AR) { | |
1871 | /* Fake an Intel architectural Data Load SRAR UCR */ | |
1872 | kvm_mce_inj_srar_dataload(env, paddr); | |
1873 | } else { | |
1874 | /* | |
1875 | * If there is an MCE excpetion being processed, ignore | |
1876 | * this SRAO MCE | |
1877 | */ | |
1878 | if (!kvm_mce_in_progress(env)) { | |
1879 | /* Fake an Intel architectural Memory scrubbing UCR */ | |
1880 | kvm_mce_inj_srao_memscrub(env, paddr); | |
1881 | } | |
c0532a76 MT |
1882 | } |
1883 | } else | |
1884 | #endif | |
1885 | { | |
1886 | if (code == BUS_MCEERR_AO) { | |
1887 | return 0; | |
1888 | } else if (code == BUS_MCEERR_AR) { | |
1889 | hardware_memory_error(); | |
1890 | } else { | |
1891 | return 1; | |
1892 | } | |
1893 | } | |
1894 | return 0; | |
1895 | } | |
1896 | ||
a1b87fe0 | 1897 | int kvm_arch_on_sigbus(int code, void *addr) |
c0532a76 MT |
1898 | { |
1899 | #if defined(KVM_CAP_MCE) | |
1900 | if ((first_cpu->mcg_cap & MCG_SER_P) && addr && code == BUS_MCEERR_AO) { | |
c0532a76 MT |
1901 | void *vaddr; |
1902 | ram_addr_t ram_addr; | |
1903 | target_phys_addr_t paddr; | |
c0532a76 MT |
1904 | |
1905 | /* Hope we are lucky for AO MCE */ | |
1906 | vaddr = addr; | |
1907 | if (qemu_ram_addr_from_host(vaddr, &ram_addr) || | |
1908 | !kvm_physical_memory_addr_from_ram(first_cpu->kvm_state, ram_addr, &paddr)) { | |
1909 | fprintf(stderr, "Hardware memory error for memory used by " | |
1910 | "QEMU itself instead of guest system!: %p\n", addr); | |
1911 | return 0; | |
1912 | } | |
e387c338 | 1913 | kvm_mce_inj_srao_memscrub2(first_cpu, paddr); |
c0532a76 MT |
1914 | } else |
1915 | #endif | |
1916 | { | |
1917 | if (code == BUS_MCEERR_AO) { | |
1918 | return 0; | |
1919 | } else if (code == BUS_MCEERR_AR) { | |
1920 | hardware_memory_error(); | |
1921 | } else { | |
1922 | return 1; | |
1923 | } | |
1924 | } | |
1925 | return 0; | |
1926 | } |