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05330448 AL |
1 | /* |
2 | * QEMU KVM support | |
3 | * | |
4 | * Copyright (C) 2006-2008 Qumranet Technologies | |
5 | * Copyright IBM, Corp. 2008 | |
6 | * | |
7 | * Authors: | |
8 | * Anthony Liguori <aliguori@us.ibm.com> | |
9 | * | |
10 | * This work is licensed under the terms of the GNU GPL, version 2 or later. | |
11 | * See the COPYING file in the top-level directory. | |
12 | * | |
13 | */ | |
14 | ||
15 | #include <sys/types.h> | |
16 | #include <sys/ioctl.h> | |
17 | #include <sys/mman.h> | |
25d2e361 | 18 | #include <sys/utsname.h> |
05330448 AL |
19 | |
20 | #include <linux/kvm.h> | |
21 | ||
22 | #include "qemu-common.h" | |
23 | #include "sysemu.h" | |
24 | #include "kvm.h" | |
25 | #include "cpu.h" | |
e22a25c9 | 26 | #include "gdbstub.h" |
0e607a80 | 27 | #include "host-utils.h" |
4c5b10b7 | 28 | #include "hw/pc.h" |
408392b3 | 29 | #include "hw/apic.h" |
35bed8ee | 30 | #include "ioport.h" |
e7701825 | 31 | #include "kvm_x86.h" |
05330448 | 32 | |
bb0300dc GN |
33 | #ifdef CONFIG_KVM_PARA |
34 | #include <linux/kvm_para.h> | |
35 | #endif | |
36 | // | |
05330448 AL |
37 | //#define DEBUG_KVM |
38 | ||
39 | #ifdef DEBUG_KVM | |
8c0d577e | 40 | #define DPRINTF(fmt, ...) \ |
05330448 AL |
41 | do { fprintf(stderr, fmt, ## __VA_ARGS__); } while (0) |
42 | #else | |
8c0d577e | 43 | #define DPRINTF(fmt, ...) \ |
05330448 AL |
44 | do { } while (0) |
45 | #endif | |
46 | ||
1a03675d GC |
47 | #define MSR_KVM_WALL_CLOCK 0x11 |
48 | #define MSR_KVM_SYSTEM_TIME 0x12 | |
49 | ||
c0532a76 MT |
50 | #ifndef BUS_MCEERR_AR |
51 | #define BUS_MCEERR_AR 4 | |
52 | #endif | |
53 | #ifndef BUS_MCEERR_AO | |
54 | #define BUS_MCEERR_AO 5 | |
55 | #endif | |
56 | ||
94a8d39a JK |
57 | const KVMCapabilityInfo kvm_arch_required_capabilities[] = { |
58 | KVM_CAP_INFO(SET_TSS_ADDR), | |
59 | KVM_CAP_INFO(EXT_CPUID), | |
60 | KVM_CAP_INFO(MP_STATE), | |
61 | KVM_CAP_LAST_INFO | |
62 | }; | |
25d2e361 | 63 | |
c3a3a7d3 JK |
64 | static bool has_msr_star; |
65 | static bool has_msr_hsave_pa; | |
c5999bfc JK |
66 | #if defined(CONFIG_KVM_PARA) && defined(KVM_CAP_ASYNC_PF) |
67 | static bool has_msr_async_pf_en; | |
68 | #endif | |
25d2e361 | 69 | static int lm_capable_kernel; |
b827df58 AK |
70 | |
71 | static struct kvm_cpuid2 *try_get_cpuid(KVMState *s, int max) | |
72 | { | |
73 | struct kvm_cpuid2 *cpuid; | |
74 | int r, size; | |
75 | ||
76 | size = sizeof(*cpuid) + max * sizeof(*cpuid->entries); | |
77 | cpuid = (struct kvm_cpuid2 *)qemu_mallocz(size); | |
78 | cpuid->nent = max; | |
79 | r = kvm_ioctl(s, KVM_GET_SUPPORTED_CPUID, cpuid); | |
76ae317f MM |
80 | if (r == 0 && cpuid->nent >= max) { |
81 | r = -E2BIG; | |
82 | } | |
b827df58 AK |
83 | if (r < 0) { |
84 | if (r == -E2BIG) { | |
85 | qemu_free(cpuid); | |
86 | return NULL; | |
87 | } else { | |
88 | fprintf(stderr, "KVM_GET_SUPPORTED_CPUID failed: %s\n", | |
89 | strerror(-r)); | |
90 | exit(1); | |
91 | } | |
92 | } | |
93 | return cpuid; | |
94 | } | |
95 | ||
c958a8bd SY |
96 | uint32_t kvm_arch_get_supported_cpuid(CPUState *env, uint32_t function, |
97 | uint32_t index, int reg) | |
b827df58 AK |
98 | { |
99 | struct kvm_cpuid2 *cpuid; | |
100 | int i, max; | |
101 | uint32_t ret = 0; | |
102 | uint32_t cpuid_1_edx; | |
103 | ||
b827df58 AK |
104 | max = 1; |
105 | while ((cpuid = try_get_cpuid(env->kvm_state, max)) == NULL) { | |
106 | max *= 2; | |
107 | } | |
108 | ||
109 | for (i = 0; i < cpuid->nent; ++i) { | |
c958a8bd SY |
110 | if (cpuid->entries[i].function == function && |
111 | cpuid->entries[i].index == index) { | |
b827df58 AK |
112 | switch (reg) { |
113 | case R_EAX: | |
114 | ret = cpuid->entries[i].eax; | |
115 | break; | |
116 | case R_EBX: | |
117 | ret = cpuid->entries[i].ebx; | |
118 | break; | |
119 | case R_ECX: | |
120 | ret = cpuid->entries[i].ecx; | |
121 | break; | |
122 | case R_EDX: | |
123 | ret = cpuid->entries[i].edx; | |
19ccb8ea JK |
124 | switch (function) { |
125 | case 1: | |
126 | /* KVM before 2.6.30 misreports the following features */ | |
127 | ret |= CPUID_MTRR | CPUID_PAT | CPUID_MCE | CPUID_MCA; | |
128 | break; | |
129 | case 0x80000001: | |
b827df58 AK |
130 | /* On Intel, kvm returns cpuid according to the Intel spec, |
131 | * so add missing bits according to the AMD spec: | |
132 | */ | |
c958a8bd | 133 | cpuid_1_edx = kvm_arch_get_supported_cpuid(env, 1, 0, R_EDX); |
c1667e40 | 134 | ret |= cpuid_1_edx & 0x183f7ff; |
19ccb8ea | 135 | break; |
b827df58 AK |
136 | } |
137 | break; | |
138 | } | |
139 | } | |
140 | } | |
141 | ||
142 | qemu_free(cpuid); | |
143 | ||
144 | return ret; | |
145 | } | |
146 | ||
bb0300dc GN |
147 | #ifdef CONFIG_KVM_PARA |
148 | struct kvm_para_features { | |
b9bec74b JK |
149 | int cap; |
150 | int feature; | |
bb0300dc | 151 | } para_features[] = { |
b9bec74b | 152 | { KVM_CAP_CLOCKSOURCE, KVM_FEATURE_CLOCKSOURCE }, |
b9bec74b | 153 | { KVM_CAP_NOP_IO_DELAY, KVM_FEATURE_NOP_IO_DELAY }, |
b9bec74b | 154 | { KVM_CAP_PV_MMU, KVM_FEATURE_MMU_OP }, |
f6584ee2 | 155 | #ifdef KVM_CAP_ASYNC_PF |
b9bec74b | 156 | { KVM_CAP_ASYNC_PF, KVM_FEATURE_ASYNC_PF }, |
bb0300dc | 157 | #endif |
b9bec74b | 158 | { -1, -1 } |
bb0300dc GN |
159 | }; |
160 | ||
161 | static int get_para_features(CPUState *env) | |
162 | { | |
b9bec74b | 163 | int i, features = 0; |
bb0300dc | 164 | |
b9bec74b JK |
165 | for (i = 0; i < ARRAY_SIZE(para_features) - 1; i++) { |
166 | if (kvm_check_extension(env->kvm_state, para_features[i].cap)) { | |
167 | features |= (1 << para_features[i].feature); | |
bb0300dc | 168 | } |
b9bec74b | 169 | } |
b3a98367 | 170 | #ifdef KVM_CAP_ASYNC_PF |
c5999bfc | 171 | has_msr_async_pf_en = features & (1 << KVM_FEATURE_ASYNC_PF); |
b3a98367 | 172 | #endif |
b9bec74b | 173 | return features; |
bb0300dc | 174 | } |
419fb20a | 175 | #endif /* CONFIG_KVM_PARA */ |
bb0300dc | 176 | |
e7701825 MT |
177 | #ifdef KVM_CAP_MCE |
178 | static int kvm_get_mce_cap_supported(KVMState *s, uint64_t *mce_cap, | |
179 | int *max_banks) | |
180 | { | |
181 | int r; | |
182 | ||
14a09518 | 183 | r = kvm_check_extension(s, KVM_CAP_MCE); |
e7701825 MT |
184 | if (r > 0) { |
185 | *max_banks = r; | |
186 | return kvm_ioctl(s, KVM_X86_GET_MCE_CAP_SUPPORTED, mce_cap); | |
187 | } | |
188 | return -ENOSYS; | |
189 | } | |
190 | ||
191 | static int kvm_setup_mce(CPUState *env, uint64_t *mcg_cap) | |
192 | { | |
193 | return kvm_vcpu_ioctl(env, KVM_X86_SETUP_MCE, mcg_cap); | |
194 | } | |
195 | ||
196 | static int kvm_set_mce(CPUState *env, struct kvm_x86_mce *m) | |
197 | { | |
198 | return kvm_vcpu_ioctl(env, KVM_X86_SET_MCE, m); | |
199 | } | |
200 | ||
c0532a76 MT |
201 | static int kvm_get_msr(CPUState *env, struct kvm_msr_entry *msrs, int n) |
202 | { | |
203 | struct kvm_msrs *kmsrs = qemu_malloc(sizeof *kmsrs + n * sizeof *msrs); | |
204 | int r; | |
205 | ||
206 | kmsrs->nmsrs = n; | |
207 | memcpy(kmsrs->entries, msrs, n * sizeof *msrs); | |
208 | r = kvm_vcpu_ioctl(env, KVM_GET_MSRS, kmsrs); | |
209 | memcpy(msrs, kmsrs->entries, n * sizeof *msrs); | |
210 | free(kmsrs); | |
211 | return r; | |
212 | } | |
213 | ||
214 | /* FIXME: kill this and kvm_get_msr, use env->mcg_status instead */ | |
6643e2f0 | 215 | static int kvm_mce_in_progress(CPUState *env) |
c0532a76 MT |
216 | { |
217 | struct kvm_msr_entry msr_mcg_status = { | |
218 | .index = MSR_MCG_STATUS, | |
219 | }; | |
220 | int r; | |
221 | ||
222 | r = kvm_get_msr(env, &msr_mcg_status, 1); | |
223 | if (r == -1 || r == 0) { | |
6643e2f0 JD |
224 | fprintf(stderr, "Failed to get MCE status\n"); |
225 | return 0; | |
c0532a76 MT |
226 | } |
227 | return !!(msr_mcg_status.data & MCG_STATUS_MCIP); | |
228 | } | |
229 | ||
e7701825 MT |
230 | struct kvm_x86_mce_data |
231 | { | |
232 | CPUState *env; | |
233 | struct kvm_x86_mce *mce; | |
c0532a76 | 234 | int abort_on_error; |
e7701825 MT |
235 | }; |
236 | ||
237 | static void kvm_do_inject_x86_mce(void *_data) | |
238 | { | |
239 | struct kvm_x86_mce_data *data = _data; | |
240 | int r; | |
241 | ||
f8502cfb HS |
242 | /* If there is an MCE exception being processed, ignore this SRAO MCE */ |
243 | if ((data->env->mcg_cap & MCG_SER_P) && | |
244 | !(data->mce->status & MCI_STATUS_AR)) { | |
6643e2f0 | 245 | if (kvm_mce_in_progress(data->env)) { |
f8502cfb HS |
246 | return; |
247 | } | |
248 | } | |
c0532a76 | 249 | |
e7701825 | 250 | r = kvm_set_mce(data->env, data->mce); |
c0532a76 | 251 | if (r < 0) { |
e7701825 | 252 | perror("kvm_set_mce FAILED"); |
c0532a76 MT |
253 | if (data->abort_on_error) { |
254 | abort(); | |
255 | } | |
256 | } | |
e7701825 | 257 | } |
31ce5e0c | 258 | |
7cc2cc3e JD |
259 | static void kvm_inject_x86_mce_on(CPUState *env, struct kvm_x86_mce *mce, |
260 | int flag) | |
261 | { | |
262 | struct kvm_x86_mce_data data = { | |
263 | .env = env, | |
264 | .mce = mce, | |
265 | .abort_on_error = (flag & ABORT_ON_ERROR), | |
266 | }; | |
267 | ||
268 | if (!env->mcg_cap) { | |
269 | fprintf(stderr, "MCE support is not enabled!\n"); | |
270 | return; | |
271 | } | |
272 | ||
273 | run_on_cpu(env, kvm_do_inject_x86_mce, &data); | |
274 | } | |
275 | ||
419fb20a JK |
276 | static void kvm_mce_broadcast_rest(CPUState *env) |
277 | { | |
278 | struct kvm_x86_mce mce = { | |
279 | .bank = 1, | |
280 | .status = MCI_STATUS_VAL | MCI_STATUS_UC, | |
281 | .mcg_status = MCG_STATUS_MCIP | MCG_STATUS_RIPV, | |
282 | .addr = 0, | |
283 | .misc = 0, | |
284 | }; | |
285 | CPUState *cenv; | |
286 | ||
287 | /* Broadcast MCA signal for processor version 06H_EH and above */ | |
288 | if (cpu_x86_support_mca_broadcast(env)) { | |
289 | for (cenv = first_cpu; cenv != NULL; cenv = cenv->next_cpu) { | |
290 | if (cenv == env) { | |
291 | continue; | |
292 | } | |
293 | kvm_inject_x86_mce_on(cenv, &mce, ABORT_ON_ERROR); | |
294 | } | |
295 | } | |
296 | } | |
297 | ||
298 | static void kvm_mce_inj_srar_dataload(CPUState *env, target_phys_addr_t paddr) | |
299 | { | |
300 | struct kvm_x86_mce mce = { | |
301 | .bank = 9, | |
302 | .status = MCI_STATUS_VAL | MCI_STATUS_UC | MCI_STATUS_EN | |
303 | | MCI_STATUS_MISCV | MCI_STATUS_ADDRV | MCI_STATUS_S | |
304 | | MCI_STATUS_AR | 0x134, | |
305 | .mcg_status = MCG_STATUS_MCIP | MCG_STATUS_EIPV, | |
306 | .addr = paddr, | |
307 | .misc = (MCM_ADDR_PHYS << 6) | 0xc, | |
308 | }; | |
309 | int r; | |
310 | ||
311 | r = kvm_set_mce(env, &mce); | |
312 | if (r < 0) { | |
313 | fprintf(stderr, "kvm_set_mce: %s\n", strerror(errno)); | |
314 | abort(); | |
315 | } | |
316 | kvm_mce_broadcast_rest(env); | |
317 | } | |
318 | ||
319 | static void kvm_mce_inj_srao_memscrub(CPUState *env, target_phys_addr_t paddr) | |
320 | { | |
321 | struct kvm_x86_mce mce = { | |
322 | .bank = 9, | |
323 | .status = MCI_STATUS_VAL | MCI_STATUS_UC | MCI_STATUS_EN | |
324 | | MCI_STATUS_MISCV | MCI_STATUS_ADDRV | MCI_STATUS_S | |
325 | | 0xc0, | |
326 | .mcg_status = MCG_STATUS_MCIP | MCG_STATUS_RIPV, | |
327 | .addr = paddr, | |
328 | .misc = (MCM_ADDR_PHYS << 6) | 0xc, | |
329 | }; | |
330 | int r; | |
331 | ||
332 | r = kvm_set_mce(env, &mce); | |
333 | if (r < 0) { | |
334 | fprintf(stderr, "kvm_set_mce: %s\n", strerror(errno)); | |
335 | abort(); | |
336 | } | |
337 | kvm_mce_broadcast_rest(env); | |
338 | } | |
339 | ||
340 | static void kvm_mce_inj_srao_memscrub2(CPUState *env, target_phys_addr_t paddr) | |
341 | { | |
342 | struct kvm_x86_mce mce = { | |
343 | .bank = 9, | |
344 | .status = MCI_STATUS_VAL | MCI_STATUS_UC | MCI_STATUS_EN | |
345 | | MCI_STATUS_MISCV | MCI_STATUS_ADDRV | MCI_STATUS_S | |
346 | | 0xc0, | |
347 | .mcg_status = MCG_STATUS_MCIP | MCG_STATUS_RIPV, | |
348 | .addr = paddr, | |
349 | .misc = (MCM_ADDR_PHYS << 6) | 0xc, | |
350 | }; | |
351 | ||
352 | kvm_inject_x86_mce_on(env, &mce, ABORT_ON_ERROR); | |
353 | kvm_mce_broadcast_rest(env); | |
354 | } | |
355 | #endif /* KVM_CAP_MCE */ | |
356 | ||
357 | static void hardware_memory_error(void) | |
358 | { | |
359 | fprintf(stderr, "Hardware memory error!\n"); | |
360 | exit(1); | |
361 | } | |
362 | ||
363 | int kvm_arch_on_sigbus_vcpu(CPUState *env, int code, void *addr) | |
364 | { | |
365 | #ifdef KVM_CAP_MCE | |
366 | void *vaddr; | |
367 | ram_addr_t ram_addr; | |
368 | target_phys_addr_t paddr; | |
369 | ||
370 | if ((env->mcg_cap & MCG_SER_P) && addr | |
371 | && (code == BUS_MCEERR_AR | |
372 | || code == BUS_MCEERR_AO)) { | |
373 | vaddr = (void *)addr; | |
374 | if (qemu_ram_addr_from_host(vaddr, &ram_addr) || | |
375 | !kvm_physical_memory_addr_from_ram(env->kvm_state, ram_addr, &paddr)) { | |
376 | fprintf(stderr, "Hardware memory error for memory used by " | |
377 | "QEMU itself instead of guest system!\n"); | |
378 | /* Hope we are lucky for AO MCE */ | |
379 | if (code == BUS_MCEERR_AO) { | |
380 | return 0; | |
381 | } else { | |
382 | hardware_memory_error(); | |
383 | } | |
384 | } | |
385 | ||
386 | if (code == BUS_MCEERR_AR) { | |
387 | /* Fake an Intel architectural Data Load SRAR UCR */ | |
388 | kvm_mce_inj_srar_dataload(env, paddr); | |
389 | } else { | |
390 | /* | |
391 | * If there is an MCE excpetion being processed, ignore | |
392 | * this SRAO MCE | |
393 | */ | |
394 | if (!kvm_mce_in_progress(env)) { | |
395 | /* Fake an Intel architectural Memory scrubbing UCR */ | |
396 | kvm_mce_inj_srao_memscrub(env, paddr); | |
397 | } | |
398 | } | |
399 | } else | |
400 | #endif /* KVM_CAP_MCE */ | |
401 | { | |
402 | if (code == BUS_MCEERR_AO) { | |
403 | return 0; | |
404 | } else if (code == BUS_MCEERR_AR) { | |
405 | hardware_memory_error(); | |
406 | } else { | |
407 | return 1; | |
408 | } | |
409 | } | |
410 | return 0; | |
411 | } | |
412 | ||
413 | int kvm_arch_on_sigbus(int code, void *addr) | |
414 | { | |
415 | #ifdef KVM_CAP_MCE | |
416 | if ((first_cpu->mcg_cap & MCG_SER_P) && addr && code == BUS_MCEERR_AO) { | |
417 | void *vaddr; | |
418 | ram_addr_t ram_addr; | |
419 | target_phys_addr_t paddr; | |
420 | ||
421 | /* Hope we are lucky for AO MCE */ | |
422 | vaddr = addr; | |
423 | if (qemu_ram_addr_from_host(vaddr, &ram_addr) || | |
424 | !kvm_physical_memory_addr_from_ram(first_cpu->kvm_state, ram_addr, | |
425 | &paddr)) { | |
426 | fprintf(stderr, "Hardware memory error for memory used by " | |
427 | "QEMU itself instead of guest system!: %p\n", addr); | |
428 | return 0; | |
429 | } | |
430 | kvm_mce_inj_srao_memscrub2(first_cpu, paddr); | |
431 | } else | |
432 | #endif /* KVM_CAP_MCE */ | |
433 | { | |
434 | if (code == BUS_MCEERR_AO) { | |
435 | return 0; | |
436 | } else if (code == BUS_MCEERR_AR) { | |
437 | hardware_memory_error(); | |
438 | } else { | |
439 | return 1; | |
440 | } | |
441 | } | |
442 | return 0; | |
443 | } | |
e7701825 MT |
444 | |
445 | void kvm_inject_x86_mce(CPUState *cenv, int bank, uint64_t status, | |
c0532a76 | 446 | uint64_t mcg_status, uint64_t addr, uint64_t misc, |
31ce5e0c | 447 | int flag) |
e7701825 MT |
448 | { |
449 | #ifdef KVM_CAP_MCE | |
450 | struct kvm_x86_mce mce = { | |
451 | .bank = bank, | |
452 | .status = status, | |
453 | .mcg_status = mcg_status, | |
454 | .addr = addr, | |
455 | .misc = misc, | |
456 | }; | |
e7701825 | 457 | |
31ce5e0c JD |
458 | if (flag & MCE_BROADCAST) { |
459 | kvm_mce_broadcast_rest(cenv); | |
c0532a76 MT |
460 | } |
461 | ||
7cc2cc3e | 462 | kvm_inject_x86_mce_on(cenv, &mce, flag); |
419fb20a | 463 | #else /* !KVM_CAP_MCE*/ |
31ce5e0c | 464 | if (flag & ABORT_ON_ERROR) { |
c0532a76 | 465 | abort(); |
31ce5e0c | 466 | } |
419fb20a | 467 | #endif /* !KVM_CAP_MCE*/ |
e7701825 MT |
468 | } |
469 | ||
ab443475 JK |
470 | static int kvm_inject_mce_oldstyle(CPUState *env) |
471 | { | |
472 | #ifdef KVM_CAP_MCE | |
473 | if (!kvm_has_vcpu_events() && env->exception_injected == EXCP12_MCHK) { | |
474 | unsigned int bank, bank_num = env->mcg_cap & 0xff; | |
475 | struct kvm_x86_mce mce; | |
476 | ||
477 | env->exception_injected = -1; | |
478 | ||
479 | /* | |
480 | * There must be at least one bank in use if an MCE is pending. | |
481 | * Find it and use its values for the event injection. | |
482 | */ | |
483 | for (bank = 0; bank < bank_num; bank++) { | |
484 | if (env->mce_banks[bank * 4 + 1] & MCI_STATUS_VAL) { | |
485 | break; | |
486 | } | |
487 | } | |
488 | assert(bank < bank_num); | |
489 | ||
490 | mce.bank = bank; | |
491 | mce.status = env->mce_banks[bank * 4 + 1]; | |
492 | mce.mcg_status = env->mcg_status; | |
493 | mce.addr = env->mce_banks[bank * 4 + 2]; | |
494 | mce.misc = env->mce_banks[bank * 4 + 3]; | |
495 | ||
496 | return kvm_vcpu_ioctl(env, KVM_X86_SET_MCE, &mce); | |
497 | } | |
498 | #endif /* KVM_CAP_MCE */ | |
499 | return 0; | |
500 | } | |
501 | ||
b8cc45d6 GC |
502 | static void cpu_update_state(void *opaque, int running, int reason) |
503 | { | |
504 | CPUState *env = opaque; | |
505 | ||
506 | if (running) { | |
507 | env->tsc_valid = false; | |
508 | } | |
509 | } | |
510 | ||
05330448 AL |
511 | int kvm_arch_init_vcpu(CPUState *env) |
512 | { | |
513 | struct { | |
486bd5a2 AL |
514 | struct kvm_cpuid2 cpuid; |
515 | struct kvm_cpuid_entry2 entries[100]; | |
05330448 | 516 | } __attribute__((packed)) cpuid_data; |
486bd5a2 | 517 | uint32_t limit, i, j, cpuid_i; |
a33609ca | 518 | uint32_t unused; |
bb0300dc | 519 | struct kvm_cpuid_entry2 *c; |
521f0798 | 520 | #ifdef CONFIG_KVM_PARA |
bb0300dc GN |
521 | uint32_t signature[3]; |
522 | #endif | |
05330448 | 523 | |
c958a8bd | 524 | env->cpuid_features &= kvm_arch_get_supported_cpuid(env, 1, 0, R_EDX); |
6c0d7ee8 AP |
525 | |
526 | i = env->cpuid_ext_features & CPUID_EXT_HYPERVISOR; | |
c958a8bd | 527 | env->cpuid_ext_features &= kvm_arch_get_supported_cpuid(env, 1, 0, R_ECX); |
6c0d7ee8 AP |
528 | env->cpuid_ext_features |= i; |
529 | ||
457dfed6 | 530 | env->cpuid_ext2_features &= kvm_arch_get_supported_cpuid(env, 0x80000001, |
c958a8bd | 531 | 0, R_EDX); |
457dfed6 | 532 | env->cpuid_ext3_features &= kvm_arch_get_supported_cpuid(env, 0x80000001, |
c958a8bd | 533 | 0, R_ECX); |
296acb64 JR |
534 | env->cpuid_svm_features &= kvm_arch_get_supported_cpuid(env, 0x8000000A, |
535 | 0, R_EDX); | |
536 | ||
6c1f42fe | 537 | |
05330448 AL |
538 | cpuid_i = 0; |
539 | ||
bb0300dc GN |
540 | #ifdef CONFIG_KVM_PARA |
541 | /* Paravirtualization CPUIDs */ | |
542 | memcpy(signature, "KVMKVMKVM\0\0\0", 12); | |
543 | c = &cpuid_data.entries[cpuid_i++]; | |
544 | memset(c, 0, sizeof(*c)); | |
545 | c->function = KVM_CPUID_SIGNATURE; | |
546 | c->eax = 0; | |
547 | c->ebx = signature[0]; | |
548 | c->ecx = signature[1]; | |
549 | c->edx = signature[2]; | |
550 | ||
551 | c = &cpuid_data.entries[cpuid_i++]; | |
552 | memset(c, 0, sizeof(*c)); | |
553 | c->function = KVM_CPUID_FEATURES; | |
554 | c->eax = env->cpuid_kvm_features & get_para_features(env); | |
555 | #endif | |
556 | ||
a33609ca | 557 | cpu_x86_cpuid(env, 0, 0, &limit, &unused, &unused, &unused); |
05330448 AL |
558 | |
559 | for (i = 0; i <= limit; i++) { | |
bb0300dc | 560 | c = &cpuid_data.entries[cpuid_i++]; |
486bd5a2 AL |
561 | |
562 | switch (i) { | |
a36b1029 AL |
563 | case 2: { |
564 | /* Keep reading function 2 till all the input is received */ | |
565 | int times; | |
566 | ||
a36b1029 | 567 | c->function = i; |
a33609ca AL |
568 | c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC | |
569 | KVM_CPUID_FLAG_STATE_READ_NEXT; | |
570 | cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx); | |
571 | times = c->eax & 0xff; | |
a36b1029 AL |
572 | |
573 | for (j = 1; j < times; ++j) { | |
a33609ca | 574 | c = &cpuid_data.entries[cpuid_i++]; |
a36b1029 | 575 | c->function = i; |
a33609ca AL |
576 | c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC; |
577 | cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx); | |
a36b1029 AL |
578 | } |
579 | break; | |
580 | } | |
486bd5a2 AL |
581 | case 4: |
582 | case 0xb: | |
583 | case 0xd: | |
584 | for (j = 0; ; j++) { | |
486bd5a2 AL |
585 | c->function = i; |
586 | c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX; | |
587 | c->index = j; | |
a33609ca | 588 | cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx); |
486bd5a2 | 589 | |
b9bec74b | 590 | if (i == 4 && c->eax == 0) { |
486bd5a2 | 591 | break; |
b9bec74b JK |
592 | } |
593 | if (i == 0xb && !(c->ecx & 0xff00)) { | |
486bd5a2 | 594 | break; |
b9bec74b JK |
595 | } |
596 | if (i == 0xd && c->eax == 0) { | |
486bd5a2 | 597 | break; |
b9bec74b | 598 | } |
a33609ca | 599 | c = &cpuid_data.entries[cpuid_i++]; |
486bd5a2 AL |
600 | } |
601 | break; | |
602 | default: | |
486bd5a2 | 603 | c->function = i; |
a33609ca AL |
604 | c->flags = 0; |
605 | cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx); | |
486bd5a2 AL |
606 | break; |
607 | } | |
05330448 | 608 | } |
a33609ca | 609 | cpu_x86_cpuid(env, 0x80000000, 0, &limit, &unused, &unused, &unused); |
05330448 AL |
610 | |
611 | for (i = 0x80000000; i <= limit; i++) { | |
bb0300dc | 612 | c = &cpuid_data.entries[cpuid_i++]; |
05330448 | 613 | |
05330448 | 614 | c->function = i; |
a33609ca AL |
615 | c->flags = 0; |
616 | cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx); | |
05330448 AL |
617 | } |
618 | ||
619 | cpuid_data.cpuid.nent = cpuid_i; | |
620 | ||
e7701825 MT |
621 | #ifdef KVM_CAP_MCE |
622 | if (((env->cpuid_version >> 8)&0xF) >= 6 | |
623 | && (env->cpuid_features&(CPUID_MCE|CPUID_MCA)) == (CPUID_MCE|CPUID_MCA) | |
624 | && kvm_check_extension(env->kvm_state, KVM_CAP_MCE) > 0) { | |
625 | uint64_t mcg_cap; | |
626 | int banks; | |
627 | ||
b9bec74b | 628 | if (kvm_get_mce_cap_supported(env->kvm_state, &mcg_cap, &banks)) { |
e7701825 | 629 | perror("kvm_get_mce_cap_supported FAILED"); |
b9bec74b | 630 | } else { |
e7701825 MT |
631 | if (banks > MCE_BANKS_DEF) |
632 | banks = MCE_BANKS_DEF; | |
633 | mcg_cap &= MCE_CAP_DEF; | |
634 | mcg_cap |= banks; | |
b9bec74b | 635 | if (kvm_setup_mce(env, &mcg_cap)) { |
e7701825 | 636 | perror("kvm_setup_mce FAILED"); |
b9bec74b | 637 | } else { |
e7701825 | 638 | env->mcg_cap = mcg_cap; |
b9bec74b | 639 | } |
e7701825 MT |
640 | } |
641 | } | |
642 | #endif | |
643 | ||
b8cc45d6 GC |
644 | qemu_add_vm_change_state_handler(cpu_update_state, env); |
645 | ||
486bd5a2 | 646 | return kvm_vcpu_ioctl(env, KVM_SET_CPUID2, &cpuid_data); |
05330448 AL |
647 | } |
648 | ||
caa5af0f JK |
649 | void kvm_arch_reset_vcpu(CPUState *env) |
650 | { | |
e73223a5 | 651 | env->exception_injected = -1; |
0e607a80 | 652 | env->interrupt_injected = -1; |
1a5e9d2f | 653 | env->xcr0 = 1; |
ddced198 MT |
654 | if (kvm_irqchip_in_kernel()) { |
655 | env->mp_state = cpu_is_bsp(env) ? KVM_MP_STATE_RUNNABLE : | |
656 | KVM_MP_STATE_UNINITIALIZED; | |
657 | } else { | |
658 | env->mp_state = KVM_MP_STATE_RUNNABLE; | |
659 | } | |
caa5af0f JK |
660 | } |
661 | ||
c3a3a7d3 | 662 | static int kvm_get_supported_msrs(KVMState *s) |
05330448 | 663 | { |
75b10c43 | 664 | static int kvm_supported_msrs; |
c3a3a7d3 | 665 | int ret = 0; |
05330448 AL |
666 | |
667 | /* first time */ | |
75b10c43 | 668 | if (kvm_supported_msrs == 0) { |
05330448 AL |
669 | struct kvm_msr_list msr_list, *kvm_msr_list; |
670 | ||
75b10c43 | 671 | kvm_supported_msrs = -1; |
05330448 AL |
672 | |
673 | /* Obtain MSR list from KVM. These are the MSRs that we must | |
674 | * save/restore */ | |
4c9f7372 | 675 | msr_list.nmsrs = 0; |
c3a3a7d3 | 676 | ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, &msr_list); |
6fb6d245 | 677 | if (ret < 0 && ret != -E2BIG) { |
c3a3a7d3 | 678 | return ret; |
6fb6d245 | 679 | } |
d9db889f JK |
680 | /* Old kernel modules had a bug and could write beyond the provided |
681 | memory. Allocate at least a safe amount of 1K. */ | |
682 | kvm_msr_list = qemu_mallocz(MAX(1024, sizeof(msr_list) + | |
683 | msr_list.nmsrs * | |
684 | sizeof(msr_list.indices[0]))); | |
05330448 | 685 | |
55308450 | 686 | kvm_msr_list->nmsrs = msr_list.nmsrs; |
c3a3a7d3 | 687 | ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, kvm_msr_list); |
05330448 AL |
688 | if (ret >= 0) { |
689 | int i; | |
690 | ||
691 | for (i = 0; i < kvm_msr_list->nmsrs; i++) { | |
692 | if (kvm_msr_list->indices[i] == MSR_STAR) { | |
c3a3a7d3 | 693 | has_msr_star = true; |
75b10c43 MT |
694 | continue; |
695 | } | |
696 | if (kvm_msr_list->indices[i] == MSR_VM_HSAVE_PA) { | |
c3a3a7d3 | 697 | has_msr_hsave_pa = true; |
75b10c43 | 698 | continue; |
05330448 AL |
699 | } |
700 | } | |
701 | } | |
702 | ||
703 | free(kvm_msr_list); | |
704 | } | |
705 | ||
c3a3a7d3 | 706 | return ret; |
05330448 AL |
707 | } |
708 | ||
cad1e282 | 709 | int kvm_arch_init(KVMState *s) |
20420430 | 710 | { |
11076198 | 711 | uint64_t identity_base = 0xfffbc000; |
20420430 | 712 | int ret; |
25d2e361 | 713 | struct utsname utsname; |
20420430 | 714 | |
c3a3a7d3 | 715 | ret = kvm_get_supported_msrs(s); |
20420430 | 716 | if (ret < 0) { |
20420430 SY |
717 | return ret; |
718 | } | |
25d2e361 MT |
719 | |
720 | uname(&utsname); | |
721 | lm_capable_kernel = strcmp(utsname.machine, "x86_64") == 0; | |
722 | ||
4c5b10b7 | 723 | /* |
11076198 JK |
724 | * On older Intel CPUs, KVM uses vm86 mode to emulate 16-bit code directly. |
725 | * In order to use vm86 mode, an EPT identity map and a TSS are needed. | |
726 | * Since these must be part of guest physical memory, we need to allocate | |
727 | * them, both by setting their start addresses in the kernel and by | |
728 | * creating a corresponding e820 entry. We need 4 pages before the BIOS. | |
729 | * | |
730 | * Older KVM versions may not support setting the identity map base. In | |
731 | * that case we need to stick with the default, i.e. a 256K maximum BIOS | |
732 | * size. | |
4c5b10b7 | 733 | */ |
11076198 JK |
734 | #ifdef KVM_CAP_SET_IDENTITY_MAP_ADDR |
735 | if (kvm_check_extension(s, KVM_CAP_SET_IDENTITY_MAP_ADDR)) { | |
736 | /* Allows up to 16M BIOSes. */ | |
737 | identity_base = 0xfeffc000; | |
738 | ||
739 | ret = kvm_vm_ioctl(s, KVM_SET_IDENTITY_MAP_ADDR, &identity_base); | |
740 | if (ret < 0) { | |
741 | return ret; | |
742 | } | |
4c5b10b7 | 743 | } |
11076198 JK |
744 | #endif |
745 | /* Set TSS base one page after EPT identity map. */ | |
746 | ret = kvm_vm_ioctl(s, KVM_SET_TSS_ADDR, identity_base + 0x1000); | |
20420430 SY |
747 | if (ret < 0) { |
748 | return ret; | |
749 | } | |
750 | ||
11076198 JK |
751 | /* Tell fw_cfg to notify the BIOS to reserve the range. */ |
752 | ret = e820_add_entry(identity_base, 0x4000, E820_RESERVED); | |
20420430 | 753 | if (ret < 0) { |
11076198 | 754 | fprintf(stderr, "e820_add_entry() table is full\n"); |
20420430 SY |
755 | return ret; |
756 | } | |
757 | ||
11076198 | 758 | return 0; |
05330448 | 759 | } |
b9bec74b | 760 | |
05330448 AL |
761 | static void set_v8086_seg(struct kvm_segment *lhs, const SegmentCache *rhs) |
762 | { | |
763 | lhs->selector = rhs->selector; | |
764 | lhs->base = rhs->base; | |
765 | lhs->limit = rhs->limit; | |
766 | lhs->type = 3; | |
767 | lhs->present = 1; | |
768 | lhs->dpl = 3; | |
769 | lhs->db = 0; | |
770 | lhs->s = 1; | |
771 | lhs->l = 0; | |
772 | lhs->g = 0; | |
773 | lhs->avl = 0; | |
774 | lhs->unusable = 0; | |
775 | } | |
776 | ||
777 | static void set_seg(struct kvm_segment *lhs, const SegmentCache *rhs) | |
778 | { | |
779 | unsigned flags = rhs->flags; | |
780 | lhs->selector = rhs->selector; | |
781 | lhs->base = rhs->base; | |
782 | lhs->limit = rhs->limit; | |
783 | lhs->type = (flags >> DESC_TYPE_SHIFT) & 15; | |
784 | lhs->present = (flags & DESC_P_MASK) != 0; | |
acaa7550 | 785 | lhs->dpl = (flags >> DESC_DPL_SHIFT) & 3; |
05330448 AL |
786 | lhs->db = (flags >> DESC_B_SHIFT) & 1; |
787 | lhs->s = (flags & DESC_S_MASK) != 0; | |
788 | lhs->l = (flags >> DESC_L_SHIFT) & 1; | |
789 | lhs->g = (flags & DESC_G_MASK) != 0; | |
790 | lhs->avl = (flags & DESC_AVL_MASK) != 0; | |
791 | lhs->unusable = 0; | |
792 | } | |
793 | ||
794 | static void get_seg(SegmentCache *lhs, const struct kvm_segment *rhs) | |
795 | { | |
796 | lhs->selector = rhs->selector; | |
797 | lhs->base = rhs->base; | |
798 | lhs->limit = rhs->limit; | |
b9bec74b JK |
799 | lhs->flags = (rhs->type << DESC_TYPE_SHIFT) | |
800 | (rhs->present * DESC_P_MASK) | | |
801 | (rhs->dpl << DESC_DPL_SHIFT) | | |
802 | (rhs->db << DESC_B_SHIFT) | | |
803 | (rhs->s * DESC_S_MASK) | | |
804 | (rhs->l << DESC_L_SHIFT) | | |
805 | (rhs->g * DESC_G_MASK) | | |
806 | (rhs->avl * DESC_AVL_MASK); | |
05330448 AL |
807 | } |
808 | ||
809 | static void kvm_getput_reg(__u64 *kvm_reg, target_ulong *qemu_reg, int set) | |
810 | { | |
b9bec74b | 811 | if (set) { |
05330448 | 812 | *kvm_reg = *qemu_reg; |
b9bec74b | 813 | } else { |
05330448 | 814 | *qemu_reg = *kvm_reg; |
b9bec74b | 815 | } |
05330448 AL |
816 | } |
817 | ||
818 | static int kvm_getput_regs(CPUState *env, int set) | |
819 | { | |
820 | struct kvm_regs regs; | |
821 | int ret = 0; | |
822 | ||
823 | if (!set) { | |
824 | ret = kvm_vcpu_ioctl(env, KVM_GET_REGS, ®s); | |
b9bec74b | 825 | if (ret < 0) { |
05330448 | 826 | return ret; |
b9bec74b | 827 | } |
05330448 AL |
828 | } |
829 | ||
830 | kvm_getput_reg(®s.rax, &env->regs[R_EAX], set); | |
831 | kvm_getput_reg(®s.rbx, &env->regs[R_EBX], set); | |
832 | kvm_getput_reg(®s.rcx, &env->regs[R_ECX], set); | |
833 | kvm_getput_reg(®s.rdx, &env->regs[R_EDX], set); | |
834 | kvm_getput_reg(®s.rsi, &env->regs[R_ESI], set); | |
835 | kvm_getput_reg(®s.rdi, &env->regs[R_EDI], set); | |
836 | kvm_getput_reg(®s.rsp, &env->regs[R_ESP], set); | |
837 | kvm_getput_reg(®s.rbp, &env->regs[R_EBP], set); | |
838 | #ifdef TARGET_X86_64 | |
839 | kvm_getput_reg(®s.r8, &env->regs[8], set); | |
840 | kvm_getput_reg(®s.r9, &env->regs[9], set); | |
841 | kvm_getput_reg(®s.r10, &env->regs[10], set); | |
842 | kvm_getput_reg(®s.r11, &env->regs[11], set); | |
843 | kvm_getput_reg(®s.r12, &env->regs[12], set); | |
844 | kvm_getput_reg(®s.r13, &env->regs[13], set); | |
845 | kvm_getput_reg(®s.r14, &env->regs[14], set); | |
846 | kvm_getput_reg(®s.r15, &env->regs[15], set); | |
847 | #endif | |
848 | ||
849 | kvm_getput_reg(®s.rflags, &env->eflags, set); | |
850 | kvm_getput_reg(®s.rip, &env->eip, set); | |
851 | ||
b9bec74b | 852 | if (set) { |
05330448 | 853 | ret = kvm_vcpu_ioctl(env, KVM_SET_REGS, ®s); |
b9bec74b | 854 | } |
05330448 AL |
855 | |
856 | return ret; | |
857 | } | |
858 | ||
859 | static int kvm_put_fpu(CPUState *env) | |
860 | { | |
861 | struct kvm_fpu fpu; | |
862 | int i; | |
863 | ||
864 | memset(&fpu, 0, sizeof fpu); | |
865 | fpu.fsw = env->fpus & ~(7 << 11); | |
866 | fpu.fsw |= (env->fpstt & 7) << 11; | |
867 | fpu.fcw = env->fpuc; | |
b9bec74b JK |
868 | for (i = 0; i < 8; ++i) { |
869 | fpu.ftwx |= (!env->fptags[i]) << i; | |
870 | } | |
05330448 AL |
871 | memcpy(fpu.fpr, env->fpregs, sizeof env->fpregs); |
872 | memcpy(fpu.xmm, env->xmm_regs, sizeof env->xmm_regs); | |
873 | fpu.mxcsr = env->mxcsr; | |
874 | ||
875 | return kvm_vcpu_ioctl(env, KVM_SET_FPU, &fpu); | |
876 | } | |
877 | ||
f1665b21 SY |
878 | #ifdef KVM_CAP_XSAVE |
879 | #define XSAVE_CWD_RIP 2 | |
880 | #define XSAVE_CWD_RDP 4 | |
881 | #define XSAVE_MXCSR 6 | |
882 | #define XSAVE_ST_SPACE 8 | |
883 | #define XSAVE_XMM_SPACE 40 | |
884 | #define XSAVE_XSTATE_BV 128 | |
885 | #define XSAVE_YMMH_SPACE 144 | |
886 | #endif | |
887 | ||
888 | static int kvm_put_xsave(CPUState *env) | |
889 | { | |
890 | #ifdef KVM_CAP_XSAVE | |
0f53994f | 891 | int i, r; |
f1665b21 SY |
892 | struct kvm_xsave* xsave; |
893 | uint16_t cwd, swd, twd, fop; | |
894 | ||
b9bec74b | 895 | if (!kvm_has_xsave()) { |
f1665b21 | 896 | return kvm_put_fpu(env); |
b9bec74b | 897 | } |
f1665b21 SY |
898 | |
899 | xsave = qemu_memalign(4096, sizeof(struct kvm_xsave)); | |
900 | memset(xsave, 0, sizeof(struct kvm_xsave)); | |
901 | cwd = swd = twd = fop = 0; | |
902 | swd = env->fpus & ~(7 << 11); | |
903 | swd |= (env->fpstt & 7) << 11; | |
904 | cwd = env->fpuc; | |
b9bec74b | 905 | for (i = 0; i < 8; ++i) { |
f1665b21 | 906 | twd |= (!env->fptags[i]) << i; |
b9bec74b | 907 | } |
f1665b21 SY |
908 | xsave->region[0] = (uint32_t)(swd << 16) + cwd; |
909 | xsave->region[1] = (uint32_t)(fop << 16) + twd; | |
910 | memcpy(&xsave->region[XSAVE_ST_SPACE], env->fpregs, | |
911 | sizeof env->fpregs); | |
912 | memcpy(&xsave->region[XSAVE_XMM_SPACE], env->xmm_regs, | |
913 | sizeof env->xmm_regs); | |
914 | xsave->region[XSAVE_MXCSR] = env->mxcsr; | |
915 | *(uint64_t *)&xsave->region[XSAVE_XSTATE_BV] = env->xstate_bv; | |
916 | memcpy(&xsave->region[XSAVE_YMMH_SPACE], env->ymmh_regs, | |
917 | sizeof env->ymmh_regs); | |
0f53994f MT |
918 | r = kvm_vcpu_ioctl(env, KVM_SET_XSAVE, xsave); |
919 | qemu_free(xsave); | |
920 | return r; | |
f1665b21 SY |
921 | #else |
922 | return kvm_put_fpu(env); | |
923 | #endif | |
924 | } | |
925 | ||
926 | static int kvm_put_xcrs(CPUState *env) | |
927 | { | |
928 | #ifdef KVM_CAP_XCRS | |
929 | struct kvm_xcrs xcrs; | |
930 | ||
b9bec74b | 931 | if (!kvm_has_xcrs()) { |
f1665b21 | 932 | return 0; |
b9bec74b | 933 | } |
f1665b21 SY |
934 | |
935 | xcrs.nr_xcrs = 1; | |
936 | xcrs.flags = 0; | |
937 | xcrs.xcrs[0].xcr = 0; | |
938 | xcrs.xcrs[0].value = env->xcr0; | |
939 | return kvm_vcpu_ioctl(env, KVM_SET_XCRS, &xcrs); | |
940 | #else | |
941 | return 0; | |
942 | #endif | |
943 | } | |
944 | ||
05330448 AL |
945 | static int kvm_put_sregs(CPUState *env) |
946 | { | |
947 | struct kvm_sregs sregs; | |
948 | ||
0e607a80 JK |
949 | memset(sregs.interrupt_bitmap, 0, sizeof(sregs.interrupt_bitmap)); |
950 | if (env->interrupt_injected >= 0) { | |
951 | sregs.interrupt_bitmap[env->interrupt_injected / 64] |= | |
952 | (uint64_t)1 << (env->interrupt_injected % 64); | |
953 | } | |
05330448 AL |
954 | |
955 | if ((env->eflags & VM_MASK)) { | |
b9bec74b JK |
956 | set_v8086_seg(&sregs.cs, &env->segs[R_CS]); |
957 | set_v8086_seg(&sregs.ds, &env->segs[R_DS]); | |
958 | set_v8086_seg(&sregs.es, &env->segs[R_ES]); | |
959 | set_v8086_seg(&sregs.fs, &env->segs[R_FS]); | |
960 | set_v8086_seg(&sregs.gs, &env->segs[R_GS]); | |
961 | set_v8086_seg(&sregs.ss, &env->segs[R_SS]); | |
05330448 | 962 | } else { |
b9bec74b JK |
963 | set_seg(&sregs.cs, &env->segs[R_CS]); |
964 | set_seg(&sregs.ds, &env->segs[R_DS]); | |
965 | set_seg(&sregs.es, &env->segs[R_ES]); | |
966 | set_seg(&sregs.fs, &env->segs[R_FS]); | |
967 | set_seg(&sregs.gs, &env->segs[R_GS]); | |
968 | set_seg(&sregs.ss, &env->segs[R_SS]); | |
05330448 AL |
969 | } |
970 | ||
971 | set_seg(&sregs.tr, &env->tr); | |
972 | set_seg(&sregs.ldt, &env->ldt); | |
973 | ||
974 | sregs.idt.limit = env->idt.limit; | |
975 | sregs.idt.base = env->idt.base; | |
976 | sregs.gdt.limit = env->gdt.limit; | |
977 | sregs.gdt.base = env->gdt.base; | |
978 | ||
979 | sregs.cr0 = env->cr[0]; | |
980 | sregs.cr2 = env->cr[2]; | |
981 | sregs.cr3 = env->cr[3]; | |
982 | sregs.cr4 = env->cr[4]; | |
983 | ||
4a942cea BS |
984 | sregs.cr8 = cpu_get_apic_tpr(env->apic_state); |
985 | sregs.apic_base = cpu_get_apic_base(env->apic_state); | |
05330448 AL |
986 | |
987 | sregs.efer = env->efer; | |
988 | ||
989 | return kvm_vcpu_ioctl(env, KVM_SET_SREGS, &sregs); | |
990 | } | |
991 | ||
992 | static void kvm_msr_entry_set(struct kvm_msr_entry *entry, | |
993 | uint32_t index, uint64_t value) | |
994 | { | |
995 | entry->index = index; | |
996 | entry->data = value; | |
997 | } | |
998 | ||
ea643051 | 999 | static int kvm_put_msrs(CPUState *env, int level) |
05330448 AL |
1000 | { |
1001 | struct { | |
1002 | struct kvm_msrs info; | |
1003 | struct kvm_msr_entry entries[100]; | |
1004 | } msr_data; | |
1005 | struct kvm_msr_entry *msrs = msr_data.entries; | |
d8da8574 | 1006 | int n = 0; |
05330448 AL |
1007 | |
1008 | kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_CS, env->sysenter_cs); | |
1009 | kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_ESP, env->sysenter_esp); | |
1010 | kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_EIP, env->sysenter_eip); | |
c3a3a7d3 | 1011 | if (has_msr_star) { |
b9bec74b JK |
1012 | kvm_msr_entry_set(&msrs[n++], MSR_STAR, env->star); |
1013 | } | |
c3a3a7d3 | 1014 | if (has_msr_hsave_pa) { |
75b10c43 | 1015 | kvm_msr_entry_set(&msrs[n++], MSR_VM_HSAVE_PA, env->vm_hsave); |
b9bec74b | 1016 | } |
05330448 | 1017 | #ifdef TARGET_X86_64 |
25d2e361 MT |
1018 | if (lm_capable_kernel) { |
1019 | kvm_msr_entry_set(&msrs[n++], MSR_CSTAR, env->cstar); | |
1020 | kvm_msr_entry_set(&msrs[n++], MSR_KERNELGSBASE, env->kernelgsbase); | |
1021 | kvm_msr_entry_set(&msrs[n++], MSR_FMASK, env->fmask); | |
1022 | kvm_msr_entry_set(&msrs[n++], MSR_LSTAR, env->lstar); | |
1023 | } | |
05330448 | 1024 | #endif |
ea643051 | 1025 | if (level == KVM_PUT_FULL_STATE) { |
384331a6 MT |
1026 | /* |
1027 | * KVM is yet unable to synchronize TSC values of multiple VCPUs on | |
1028 | * writeback. Until this is fixed, we only write the offset to SMP | |
1029 | * guests after migration, desynchronizing the VCPUs, but avoiding | |
1030 | * huge jump-backs that would occur without any writeback at all. | |
1031 | */ | |
1032 | if (smp_cpus == 1 || env->tsc != 0) { | |
1033 | kvm_msr_entry_set(&msrs[n++], MSR_IA32_TSC, env->tsc); | |
1034 | } | |
ff5c186b JK |
1035 | } |
1036 | /* | |
1037 | * The following paravirtual MSRs have side effects on the guest or are | |
1038 | * too heavy for normal writeback. Limit them to reset or full state | |
1039 | * updates. | |
1040 | */ | |
1041 | if (level >= KVM_PUT_RESET_STATE) { | |
ea643051 JK |
1042 | kvm_msr_entry_set(&msrs[n++], MSR_KVM_SYSTEM_TIME, |
1043 | env->system_time_msr); | |
1044 | kvm_msr_entry_set(&msrs[n++], MSR_KVM_WALL_CLOCK, env->wall_clock_msr); | |
521f0798 | 1045 | #if defined(CONFIG_KVM_PARA) && defined(KVM_CAP_ASYNC_PF) |
c5999bfc JK |
1046 | if (has_msr_async_pf_en) { |
1047 | kvm_msr_entry_set(&msrs[n++], MSR_KVM_ASYNC_PF_EN, | |
1048 | env->async_pf_en_msr); | |
1049 | } | |
f6584ee2 | 1050 | #endif |
ea643051 | 1051 | } |
57780495 MT |
1052 | #ifdef KVM_CAP_MCE |
1053 | if (env->mcg_cap) { | |
d8da8574 | 1054 | int i; |
b9bec74b JK |
1055 | |
1056 | if (level == KVM_PUT_RESET_STATE) { | |
57780495 | 1057 | kvm_msr_entry_set(&msrs[n++], MSR_MCG_STATUS, env->mcg_status); |
b9bec74b | 1058 | } else if (level == KVM_PUT_FULL_STATE) { |
57780495 MT |
1059 | kvm_msr_entry_set(&msrs[n++], MSR_MCG_STATUS, env->mcg_status); |
1060 | kvm_msr_entry_set(&msrs[n++], MSR_MCG_CTL, env->mcg_ctl); | |
b9bec74b | 1061 | for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) { |
57780495 | 1062 | kvm_msr_entry_set(&msrs[n++], MSR_MC0_CTL + i, env->mce_banks[i]); |
b9bec74b | 1063 | } |
57780495 MT |
1064 | } |
1065 | } | |
1066 | #endif | |
1a03675d | 1067 | |
05330448 AL |
1068 | msr_data.info.nmsrs = n; |
1069 | ||
1070 | return kvm_vcpu_ioctl(env, KVM_SET_MSRS, &msr_data); | |
1071 | ||
1072 | } | |
1073 | ||
1074 | ||
1075 | static int kvm_get_fpu(CPUState *env) | |
1076 | { | |
1077 | struct kvm_fpu fpu; | |
1078 | int i, ret; | |
1079 | ||
1080 | ret = kvm_vcpu_ioctl(env, KVM_GET_FPU, &fpu); | |
b9bec74b | 1081 | if (ret < 0) { |
05330448 | 1082 | return ret; |
b9bec74b | 1083 | } |
05330448 AL |
1084 | |
1085 | env->fpstt = (fpu.fsw >> 11) & 7; | |
1086 | env->fpus = fpu.fsw; | |
1087 | env->fpuc = fpu.fcw; | |
b9bec74b JK |
1088 | for (i = 0; i < 8; ++i) { |
1089 | env->fptags[i] = !((fpu.ftwx >> i) & 1); | |
1090 | } | |
05330448 AL |
1091 | memcpy(env->fpregs, fpu.fpr, sizeof env->fpregs); |
1092 | memcpy(env->xmm_regs, fpu.xmm, sizeof env->xmm_regs); | |
1093 | env->mxcsr = fpu.mxcsr; | |
1094 | ||
1095 | return 0; | |
1096 | } | |
1097 | ||
f1665b21 SY |
1098 | static int kvm_get_xsave(CPUState *env) |
1099 | { | |
1100 | #ifdef KVM_CAP_XSAVE | |
1101 | struct kvm_xsave* xsave; | |
1102 | int ret, i; | |
1103 | uint16_t cwd, swd, twd, fop; | |
1104 | ||
b9bec74b | 1105 | if (!kvm_has_xsave()) { |
f1665b21 | 1106 | return kvm_get_fpu(env); |
b9bec74b | 1107 | } |
f1665b21 SY |
1108 | |
1109 | xsave = qemu_memalign(4096, sizeof(struct kvm_xsave)); | |
1110 | ret = kvm_vcpu_ioctl(env, KVM_GET_XSAVE, xsave); | |
0f53994f MT |
1111 | if (ret < 0) { |
1112 | qemu_free(xsave); | |
f1665b21 | 1113 | return ret; |
0f53994f | 1114 | } |
f1665b21 SY |
1115 | |
1116 | cwd = (uint16_t)xsave->region[0]; | |
1117 | swd = (uint16_t)(xsave->region[0] >> 16); | |
1118 | twd = (uint16_t)xsave->region[1]; | |
1119 | fop = (uint16_t)(xsave->region[1] >> 16); | |
1120 | env->fpstt = (swd >> 11) & 7; | |
1121 | env->fpus = swd; | |
1122 | env->fpuc = cwd; | |
b9bec74b | 1123 | for (i = 0; i < 8; ++i) { |
f1665b21 | 1124 | env->fptags[i] = !((twd >> i) & 1); |
b9bec74b | 1125 | } |
f1665b21 SY |
1126 | env->mxcsr = xsave->region[XSAVE_MXCSR]; |
1127 | memcpy(env->fpregs, &xsave->region[XSAVE_ST_SPACE], | |
1128 | sizeof env->fpregs); | |
1129 | memcpy(env->xmm_regs, &xsave->region[XSAVE_XMM_SPACE], | |
1130 | sizeof env->xmm_regs); | |
1131 | env->xstate_bv = *(uint64_t *)&xsave->region[XSAVE_XSTATE_BV]; | |
1132 | memcpy(env->ymmh_regs, &xsave->region[XSAVE_YMMH_SPACE], | |
1133 | sizeof env->ymmh_regs); | |
0f53994f | 1134 | qemu_free(xsave); |
f1665b21 SY |
1135 | return 0; |
1136 | #else | |
1137 | return kvm_get_fpu(env); | |
1138 | #endif | |
1139 | } | |
1140 | ||
1141 | static int kvm_get_xcrs(CPUState *env) | |
1142 | { | |
1143 | #ifdef KVM_CAP_XCRS | |
1144 | int i, ret; | |
1145 | struct kvm_xcrs xcrs; | |
1146 | ||
b9bec74b | 1147 | if (!kvm_has_xcrs()) { |
f1665b21 | 1148 | return 0; |
b9bec74b | 1149 | } |
f1665b21 SY |
1150 | |
1151 | ret = kvm_vcpu_ioctl(env, KVM_GET_XCRS, &xcrs); | |
b9bec74b | 1152 | if (ret < 0) { |
f1665b21 | 1153 | return ret; |
b9bec74b | 1154 | } |
f1665b21 | 1155 | |
b9bec74b | 1156 | for (i = 0; i < xcrs.nr_xcrs; i++) { |
f1665b21 SY |
1157 | /* Only support xcr0 now */ |
1158 | if (xcrs.xcrs[0].xcr == 0) { | |
1159 | env->xcr0 = xcrs.xcrs[0].value; | |
1160 | break; | |
1161 | } | |
b9bec74b | 1162 | } |
f1665b21 SY |
1163 | return 0; |
1164 | #else | |
1165 | return 0; | |
1166 | #endif | |
1167 | } | |
1168 | ||
05330448 AL |
1169 | static int kvm_get_sregs(CPUState *env) |
1170 | { | |
1171 | struct kvm_sregs sregs; | |
1172 | uint32_t hflags; | |
0e607a80 | 1173 | int bit, i, ret; |
05330448 AL |
1174 | |
1175 | ret = kvm_vcpu_ioctl(env, KVM_GET_SREGS, &sregs); | |
b9bec74b | 1176 | if (ret < 0) { |
05330448 | 1177 | return ret; |
b9bec74b | 1178 | } |
05330448 | 1179 | |
0e607a80 JK |
1180 | /* There can only be one pending IRQ set in the bitmap at a time, so try |
1181 | to find it and save its number instead (-1 for none). */ | |
1182 | env->interrupt_injected = -1; | |
1183 | for (i = 0; i < ARRAY_SIZE(sregs.interrupt_bitmap); i++) { | |
1184 | if (sregs.interrupt_bitmap[i]) { | |
1185 | bit = ctz64(sregs.interrupt_bitmap[i]); | |
1186 | env->interrupt_injected = i * 64 + bit; | |
1187 | break; | |
1188 | } | |
1189 | } | |
05330448 AL |
1190 | |
1191 | get_seg(&env->segs[R_CS], &sregs.cs); | |
1192 | get_seg(&env->segs[R_DS], &sregs.ds); | |
1193 | get_seg(&env->segs[R_ES], &sregs.es); | |
1194 | get_seg(&env->segs[R_FS], &sregs.fs); | |
1195 | get_seg(&env->segs[R_GS], &sregs.gs); | |
1196 | get_seg(&env->segs[R_SS], &sregs.ss); | |
1197 | ||
1198 | get_seg(&env->tr, &sregs.tr); | |
1199 | get_seg(&env->ldt, &sregs.ldt); | |
1200 | ||
1201 | env->idt.limit = sregs.idt.limit; | |
1202 | env->idt.base = sregs.idt.base; | |
1203 | env->gdt.limit = sregs.gdt.limit; | |
1204 | env->gdt.base = sregs.gdt.base; | |
1205 | ||
1206 | env->cr[0] = sregs.cr0; | |
1207 | env->cr[2] = sregs.cr2; | |
1208 | env->cr[3] = sregs.cr3; | |
1209 | env->cr[4] = sregs.cr4; | |
1210 | ||
4a942cea | 1211 | cpu_set_apic_base(env->apic_state, sregs.apic_base); |
05330448 AL |
1212 | |
1213 | env->efer = sregs.efer; | |
4a942cea | 1214 | //cpu_set_apic_tpr(env->apic_state, sregs.cr8); |
05330448 | 1215 | |
b9bec74b JK |
1216 | #define HFLAG_COPY_MASK \ |
1217 | ~( HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \ | |
1218 | HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \ | |
1219 | HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \ | |
1220 | HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK) | |
05330448 AL |
1221 | |
1222 | hflags = (env->segs[R_CS].flags >> DESC_DPL_SHIFT) & HF_CPL_MASK; | |
1223 | hflags |= (env->cr[0] & CR0_PE_MASK) << (HF_PE_SHIFT - CR0_PE_SHIFT); | |
1224 | hflags |= (env->cr[0] << (HF_MP_SHIFT - CR0_MP_SHIFT)) & | |
b9bec74b | 1225 | (HF_MP_MASK | HF_EM_MASK | HF_TS_MASK); |
05330448 AL |
1226 | hflags |= (env->eflags & (HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK)); |
1227 | hflags |= (env->cr[4] & CR4_OSFXSR_MASK) << | |
b9bec74b | 1228 | (HF_OSFXSR_SHIFT - CR4_OSFXSR_SHIFT); |
05330448 AL |
1229 | |
1230 | if (env->efer & MSR_EFER_LMA) { | |
1231 | hflags |= HF_LMA_MASK; | |
1232 | } | |
1233 | ||
1234 | if ((hflags & HF_LMA_MASK) && (env->segs[R_CS].flags & DESC_L_MASK)) { | |
1235 | hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK; | |
1236 | } else { | |
1237 | hflags |= (env->segs[R_CS].flags & DESC_B_MASK) >> | |
b9bec74b | 1238 | (DESC_B_SHIFT - HF_CS32_SHIFT); |
05330448 | 1239 | hflags |= (env->segs[R_SS].flags & DESC_B_MASK) >> |
b9bec74b JK |
1240 | (DESC_B_SHIFT - HF_SS32_SHIFT); |
1241 | if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK) || | |
1242 | !(hflags & HF_CS32_MASK)) { | |
1243 | hflags |= HF_ADDSEG_MASK; | |
1244 | } else { | |
1245 | hflags |= ((env->segs[R_DS].base | env->segs[R_ES].base | | |
1246 | env->segs[R_SS].base) != 0) << HF_ADDSEG_SHIFT; | |
1247 | } | |
05330448 AL |
1248 | } |
1249 | env->hflags = (env->hflags & HFLAG_COPY_MASK) | hflags; | |
05330448 AL |
1250 | |
1251 | return 0; | |
1252 | } | |
1253 | ||
1254 | static int kvm_get_msrs(CPUState *env) | |
1255 | { | |
1256 | struct { | |
1257 | struct kvm_msrs info; | |
1258 | struct kvm_msr_entry entries[100]; | |
1259 | } msr_data; | |
1260 | struct kvm_msr_entry *msrs = msr_data.entries; | |
1261 | int ret, i, n; | |
1262 | ||
1263 | n = 0; | |
1264 | msrs[n++].index = MSR_IA32_SYSENTER_CS; | |
1265 | msrs[n++].index = MSR_IA32_SYSENTER_ESP; | |
1266 | msrs[n++].index = MSR_IA32_SYSENTER_EIP; | |
c3a3a7d3 | 1267 | if (has_msr_star) { |
b9bec74b JK |
1268 | msrs[n++].index = MSR_STAR; |
1269 | } | |
c3a3a7d3 | 1270 | if (has_msr_hsave_pa) { |
75b10c43 | 1271 | msrs[n++].index = MSR_VM_HSAVE_PA; |
b9bec74b | 1272 | } |
b8cc45d6 GC |
1273 | |
1274 | if (!env->tsc_valid) { | |
1275 | msrs[n++].index = MSR_IA32_TSC; | |
1276 | env->tsc_valid = !vm_running; | |
1277 | } | |
1278 | ||
05330448 | 1279 | #ifdef TARGET_X86_64 |
25d2e361 MT |
1280 | if (lm_capable_kernel) { |
1281 | msrs[n++].index = MSR_CSTAR; | |
1282 | msrs[n++].index = MSR_KERNELGSBASE; | |
1283 | msrs[n++].index = MSR_FMASK; | |
1284 | msrs[n++].index = MSR_LSTAR; | |
1285 | } | |
05330448 | 1286 | #endif |
1a03675d GC |
1287 | msrs[n++].index = MSR_KVM_SYSTEM_TIME; |
1288 | msrs[n++].index = MSR_KVM_WALL_CLOCK; | |
521f0798 | 1289 | #if defined(CONFIG_KVM_PARA) && defined(KVM_CAP_ASYNC_PF) |
c5999bfc JK |
1290 | if (has_msr_async_pf_en) { |
1291 | msrs[n++].index = MSR_KVM_ASYNC_PF_EN; | |
1292 | } | |
f6584ee2 | 1293 | #endif |
1a03675d | 1294 | |
57780495 MT |
1295 | #ifdef KVM_CAP_MCE |
1296 | if (env->mcg_cap) { | |
1297 | msrs[n++].index = MSR_MCG_STATUS; | |
1298 | msrs[n++].index = MSR_MCG_CTL; | |
b9bec74b | 1299 | for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) { |
57780495 | 1300 | msrs[n++].index = MSR_MC0_CTL + i; |
b9bec74b | 1301 | } |
57780495 MT |
1302 | } |
1303 | #endif | |
1304 | ||
05330448 AL |
1305 | msr_data.info.nmsrs = n; |
1306 | ret = kvm_vcpu_ioctl(env, KVM_GET_MSRS, &msr_data); | |
b9bec74b | 1307 | if (ret < 0) { |
05330448 | 1308 | return ret; |
b9bec74b | 1309 | } |
05330448 AL |
1310 | |
1311 | for (i = 0; i < ret; i++) { | |
1312 | switch (msrs[i].index) { | |
1313 | case MSR_IA32_SYSENTER_CS: | |
1314 | env->sysenter_cs = msrs[i].data; | |
1315 | break; | |
1316 | case MSR_IA32_SYSENTER_ESP: | |
1317 | env->sysenter_esp = msrs[i].data; | |
1318 | break; | |
1319 | case MSR_IA32_SYSENTER_EIP: | |
1320 | env->sysenter_eip = msrs[i].data; | |
1321 | break; | |
1322 | case MSR_STAR: | |
1323 | env->star = msrs[i].data; | |
1324 | break; | |
1325 | #ifdef TARGET_X86_64 | |
1326 | case MSR_CSTAR: | |
1327 | env->cstar = msrs[i].data; | |
1328 | break; | |
1329 | case MSR_KERNELGSBASE: | |
1330 | env->kernelgsbase = msrs[i].data; | |
1331 | break; | |
1332 | case MSR_FMASK: | |
1333 | env->fmask = msrs[i].data; | |
1334 | break; | |
1335 | case MSR_LSTAR: | |
1336 | env->lstar = msrs[i].data; | |
1337 | break; | |
1338 | #endif | |
1339 | case MSR_IA32_TSC: | |
1340 | env->tsc = msrs[i].data; | |
1341 | break; | |
aa851e36 MT |
1342 | case MSR_VM_HSAVE_PA: |
1343 | env->vm_hsave = msrs[i].data; | |
1344 | break; | |
1a03675d GC |
1345 | case MSR_KVM_SYSTEM_TIME: |
1346 | env->system_time_msr = msrs[i].data; | |
1347 | break; | |
1348 | case MSR_KVM_WALL_CLOCK: | |
1349 | env->wall_clock_msr = msrs[i].data; | |
1350 | break; | |
57780495 MT |
1351 | #ifdef KVM_CAP_MCE |
1352 | case MSR_MCG_STATUS: | |
1353 | env->mcg_status = msrs[i].data; | |
1354 | break; | |
1355 | case MSR_MCG_CTL: | |
1356 | env->mcg_ctl = msrs[i].data; | |
1357 | break; | |
1358 | #endif | |
1359 | default: | |
1360 | #ifdef KVM_CAP_MCE | |
1361 | if (msrs[i].index >= MSR_MC0_CTL && | |
1362 | msrs[i].index < MSR_MC0_CTL + (env->mcg_cap & 0xff) * 4) { | |
1363 | env->mce_banks[msrs[i].index - MSR_MC0_CTL] = msrs[i].data; | |
57780495 MT |
1364 | } |
1365 | #endif | |
d8da8574 | 1366 | break; |
521f0798 | 1367 | #if defined(CONFIG_KVM_PARA) && defined(KVM_CAP_ASYNC_PF) |
f6584ee2 GN |
1368 | case MSR_KVM_ASYNC_PF_EN: |
1369 | env->async_pf_en_msr = msrs[i].data; | |
1370 | break; | |
1371 | #endif | |
05330448 AL |
1372 | } |
1373 | } | |
1374 | ||
1375 | return 0; | |
1376 | } | |
1377 | ||
9bdbe550 HB |
1378 | static int kvm_put_mp_state(CPUState *env) |
1379 | { | |
1380 | struct kvm_mp_state mp_state = { .mp_state = env->mp_state }; | |
1381 | ||
1382 | return kvm_vcpu_ioctl(env, KVM_SET_MP_STATE, &mp_state); | |
1383 | } | |
1384 | ||
1385 | static int kvm_get_mp_state(CPUState *env) | |
1386 | { | |
1387 | struct kvm_mp_state mp_state; | |
1388 | int ret; | |
1389 | ||
1390 | ret = kvm_vcpu_ioctl(env, KVM_GET_MP_STATE, &mp_state); | |
1391 | if (ret < 0) { | |
1392 | return ret; | |
1393 | } | |
1394 | env->mp_state = mp_state.mp_state; | |
c14750e8 JK |
1395 | if (kvm_irqchip_in_kernel()) { |
1396 | env->halted = (mp_state.mp_state == KVM_MP_STATE_HALTED); | |
1397 | } | |
9bdbe550 HB |
1398 | return 0; |
1399 | } | |
1400 | ||
ea643051 | 1401 | static int kvm_put_vcpu_events(CPUState *env, int level) |
a0fb002c JK |
1402 | { |
1403 | #ifdef KVM_CAP_VCPU_EVENTS | |
1404 | struct kvm_vcpu_events events; | |
1405 | ||
1406 | if (!kvm_has_vcpu_events()) { | |
1407 | return 0; | |
1408 | } | |
1409 | ||
31827373 JK |
1410 | events.exception.injected = (env->exception_injected >= 0); |
1411 | events.exception.nr = env->exception_injected; | |
a0fb002c JK |
1412 | events.exception.has_error_code = env->has_error_code; |
1413 | events.exception.error_code = env->error_code; | |
1414 | ||
1415 | events.interrupt.injected = (env->interrupt_injected >= 0); | |
1416 | events.interrupt.nr = env->interrupt_injected; | |
1417 | events.interrupt.soft = env->soft_interrupt; | |
1418 | ||
1419 | events.nmi.injected = env->nmi_injected; | |
1420 | events.nmi.pending = env->nmi_pending; | |
1421 | events.nmi.masked = !!(env->hflags2 & HF2_NMI_MASK); | |
1422 | ||
1423 | events.sipi_vector = env->sipi_vector; | |
1424 | ||
ea643051 JK |
1425 | events.flags = 0; |
1426 | if (level >= KVM_PUT_RESET_STATE) { | |
1427 | events.flags |= | |
1428 | KVM_VCPUEVENT_VALID_NMI_PENDING | KVM_VCPUEVENT_VALID_SIPI_VECTOR; | |
1429 | } | |
aee028b9 | 1430 | |
a0fb002c JK |
1431 | return kvm_vcpu_ioctl(env, KVM_SET_VCPU_EVENTS, &events); |
1432 | #else | |
1433 | return 0; | |
1434 | #endif | |
1435 | } | |
1436 | ||
1437 | static int kvm_get_vcpu_events(CPUState *env) | |
1438 | { | |
1439 | #ifdef KVM_CAP_VCPU_EVENTS | |
1440 | struct kvm_vcpu_events events; | |
1441 | int ret; | |
1442 | ||
1443 | if (!kvm_has_vcpu_events()) { | |
1444 | return 0; | |
1445 | } | |
1446 | ||
1447 | ret = kvm_vcpu_ioctl(env, KVM_GET_VCPU_EVENTS, &events); | |
1448 | if (ret < 0) { | |
1449 | return ret; | |
1450 | } | |
31827373 | 1451 | env->exception_injected = |
a0fb002c JK |
1452 | events.exception.injected ? events.exception.nr : -1; |
1453 | env->has_error_code = events.exception.has_error_code; | |
1454 | env->error_code = events.exception.error_code; | |
1455 | ||
1456 | env->interrupt_injected = | |
1457 | events.interrupt.injected ? events.interrupt.nr : -1; | |
1458 | env->soft_interrupt = events.interrupt.soft; | |
1459 | ||
1460 | env->nmi_injected = events.nmi.injected; | |
1461 | env->nmi_pending = events.nmi.pending; | |
1462 | if (events.nmi.masked) { | |
1463 | env->hflags2 |= HF2_NMI_MASK; | |
1464 | } else { | |
1465 | env->hflags2 &= ~HF2_NMI_MASK; | |
1466 | } | |
1467 | ||
1468 | env->sipi_vector = events.sipi_vector; | |
1469 | #endif | |
1470 | ||
1471 | return 0; | |
1472 | } | |
1473 | ||
b0b1d690 JK |
1474 | static int kvm_guest_debug_workarounds(CPUState *env) |
1475 | { | |
1476 | int ret = 0; | |
1477 | #ifdef KVM_CAP_SET_GUEST_DEBUG | |
1478 | unsigned long reinject_trap = 0; | |
1479 | ||
1480 | if (!kvm_has_vcpu_events()) { | |
1481 | if (env->exception_injected == 1) { | |
1482 | reinject_trap = KVM_GUESTDBG_INJECT_DB; | |
1483 | } else if (env->exception_injected == 3) { | |
1484 | reinject_trap = KVM_GUESTDBG_INJECT_BP; | |
1485 | } | |
1486 | env->exception_injected = -1; | |
1487 | } | |
1488 | ||
1489 | /* | |
1490 | * Kernels before KVM_CAP_X86_ROBUST_SINGLESTEP overwrote flags.TF | |
1491 | * injected via SET_GUEST_DEBUG while updating GP regs. Work around this | |
1492 | * by updating the debug state once again if single-stepping is on. | |
1493 | * Another reason to call kvm_update_guest_debug here is a pending debug | |
1494 | * trap raise by the guest. On kernels without SET_VCPU_EVENTS we have to | |
1495 | * reinject them via SET_GUEST_DEBUG. | |
1496 | */ | |
1497 | if (reinject_trap || | |
1498 | (!kvm_has_robust_singlestep() && env->singlestep_enabled)) { | |
1499 | ret = kvm_update_guest_debug(env, reinject_trap); | |
1500 | } | |
1501 | #endif /* KVM_CAP_SET_GUEST_DEBUG */ | |
1502 | return ret; | |
1503 | } | |
1504 | ||
ff44f1a3 JK |
1505 | static int kvm_put_debugregs(CPUState *env) |
1506 | { | |
1507 | #ifdef KVM_CAP_DEBUGREGS | |
1508 | struct kvm_debugregs dbgregs; | |
1509 | int i; | |
1510 | ||
1511 | if (!kvm_has_debugregs()) { | |
1512 | return 0; | |
1513 | } | |
1514 | ||
1515 | for (i = 0; i < 4; i++) { | |
1516 | dbgregs.db[i] = env->dr[i]; | |
1517 | } | |
1518 | dbgregs.dr6 = env->dr[6]; | |
1519 | dbgregs.dr7 = env->dr[7]; | |
1520 | dbgregs.flags = 0; | |
1521 | ||
1522 | return kvm_vcpu_ioctl(env, KVM_SET_DEBUGREGS, &dbgregs); | |
1523 | #else | |
1524 | return 0; | |
1525 | #endif | |
1526 | } | |
1527 | ||
1528 | static int kvm_get_debugregs(CPUState *env) | |
1529 | { | |
1530 | #ifdef KVM_CAP_DEBUGREGS | |
1531 | struct kvm_debugregs dbgregs; | |
1532 | int i, ret; | |
1533 | ||
1534 | if (!kvm_has_debugregs()) { | |
1535 | return 0; | |
1536 | } | |
1537 | ||
1538 | ret = kvm_vcpu_ioctl(env, KVM_GET_DEBUGREGS, &dbgregs); | |
1539 | if (ret < 0) { | |
b9bec74b | 1540 | return ret; |
ff44f1a3 JK |
1541 | } |
1542 | for (i = 0; i < 4; i++) { | |
1543 | env->dr[i] = dbgregs.db[i]; | |
1544 | } | |
1545 | env->dr[4] = env->dr[6] = dbgregs.dr6; | |
1546 | env->dr[5] = env->dr[7] = dbgregs.dr7; | |
1547 | #endif | |
1548 | ||
1549 | return 0; | |
1550 | } | |
1551 | ||
ea375f9a | 1552 | int kvm_arch_put_registers(CPUState *env, int level) |
05330448 AL |
1553 | { |
1554 | int ret; | |
1555 | ||
b7680cb6 | 1556 | assert(cpu_is_stopped(env) || qemu_cpu_is_self(env)); |
dbaa07c4 | 1557 | |
05330448 | 1558 | ret = kvm_getput_regs(env, 1); |
b9bec74b | 1559 | if (ret < 0) { |
05330448 | 1560 | return ret; |
b9bec74b | 1561 | } |
f1665b21 | 1562 | ret = kvm_put_xsave(env); |
b9bec74b | 1563 | if (ret < 0) { |
f1665b21 | 1564 | return ret; |
b9bec74b | 1565 | } |
f1665b21 | 1566 | ret = kvm_put_xcrs(env); |
b9bec74b | 1567 | if (ret < 0) { |
05330448 | 1568 | return ret; |
b9bec74b | 1569 | } |
05330448 | 1570 | ret = kvm_put_sregs(env); |
b9bec74b | 1571 | if (ret < 0) { |
05330448 | 1572 | return ret; |
b9bec74b | 1573 | } |
ab443475 JK |
1574 | /* must be before kvm_put_msrs */ |
1575 | ret = kvm_inject_mce_oldstyle(env); | |
1576 | if (ret < 0) { | |
1577 | return ret; | |
1578 | } | |
ea643051 | 1579 | ret = kvm_put_msrs(env, level); |
b9bec74b | 1580 | if (ret < 0) { |
05330448 | 1581 | return ret; |
b9bec74b | 1582 | } |
ea643051 JK |
1583 | if (level >= KVM_PUT_RESET_STATE) { |
1584 | ret = kvm_put_mp_state(env); | |
b9bec74b | 1585 | if (ret < 0) { |
ea643051 | 1586 | return ret; |
b9bec74b | 1587 | } |
ea643051 | 1588 | } |
ea643051 | 1589 | ret = kvm_put_vcpu_events(env, level); |
b9bec74b | 1590 | if (ret < 0) { |
a0fb002c | 1591 | return ret; |
b9bec74b | 1592 | } |
0d75a9ec | 1593 | ret = kvm_put_debugregs(env); |
b9bec74b | 1594 | if (ret < 0) { |
b0b1d690 | 1595 | return ret; |
b9bec74b | 1596 | } |
b0b1d690 JK |
1597 | /* must be last */ |
1598 | ret = kvm_guest_debug_workarounds(env); | |
b9bec74b | 1599 | if (ret < 0) { |
ff44f1a3 | 1600 | return ret; |
b9bec74b | 1601 | } |
05330448 AL |
1602 | return 0; |
1603 | } | |
1604 | ||
1605 | int kvm_arch_get_registers(CPUState *env) | |
1606 | { | |
1607 | int ret; | |
1608 | ||
b7680cb6 | 1609 | assert(cpu_is_stopped(env) || qemu_cpu_is_self(env)); |
dbaa07c4 | 1610 | |
05330448 | 1611 | ret = kvm_getput_regs(env, 0); |
b9bec74b | 1612 | if (ret < 0) { |
05330448 | 1613 | return ret; |
b9bec74b | 1614 | } |
f1665b21 | 1615 | ret = kvm_get_xsave(env); |
b9bec74b | 1616 | if (ret < 0) { |
f1665b21 | 1617 | return ret; |
b9bec74b | 1618 | } |
f1665b21 | 1619 | ret = kvm_get_xcrs(env); |
b9bec74b | 1620 | if (ret < 0) { |
05330448 | 1621 | return ret; |
b9bec74b | 1622 | } |
05330448 | 1623 | ret = kvm_get_sregs(env); |
b9bec74b | 1624 | if (ret < 0) { |
05330448 | 1625 | return ret; |
b9bec74b | 1626 | } |
05330448 | 1627 | ret = kvm_get_msrs(env); |
b9bec74b | 1628 | if (ret < 0) { |
05330448 | 1629 | return ret; |
b9bec74b | 1630 | } |
5a2e3c2e | 1631 | ret = kvm_get_mp_state(env); |
b9bec74b | 1632 | if (ret < 0) { |
5a2e3c2e | 1633 | return ret; |
b9bec74b | 1634 | } |
a0fb002c | 1635 | ret = kvm_get_vcpu_events(env); |
b9bec74b | 1636 | if (ret < 0) { |
a0fb002c | 1637 | return ret; |
b9bec74b | 1638 | } |
ff44f1a3 | 1639 | ret = kvm_get_debugregs(env); |
b9bec74b | 1640 | if (ret < 0) { |
ff44f1a3 | 1641 | return ret; |
b9bec74b | 1642 | } |
05330448 AL |
1643 | return 0; |
1644 | } | |
1645 | ||
7a39fe58 | 1646 | void kvm_arch_pre_run(CPUState *env, struct kvm_run *run) |
05330448 | 1647 | { |
ce377af3 JK |
1648 | int ret; |
1649 | ||
276ce815 LJ |
1650 | /* Inject NMI */ |
1651 | if (env->interrupt_request & CPU_INTERRUPT_NMI) { | |
1652 | env->interrupt_request &= ~CPU_INTERRUPT_NMI; | |
1653 | DPRINTF("injected NMI\n"); | |
ce377af3 JK |
1654 | ret = kvm_vcpu_ioctl(env, KVM_NMI); |
1655 | if (ret < 0) { | |
1656 | fprintf(stderr, "KVM: injection failed, NMI lost (%s)\n", | |
1657 | strerror(-ret)); | |
1658 | } | |
276ce815 LJ |
1659 | } |
1660 | ||
db1669bc JK |
1661 | if (!kvm_irqchip_in_kernel()) { |
1662 | /* Force the VCPU out of its inner loop to process the INIT request */ | |
1663 | if (env->interrupt_request & CPU_INTERRUPT_INIT) { | |
1664 | env->exit_request = 1; | |
05330448 | 1665 | } |
05330448 | 1666 | |
db1669bc JK |
1667 | /* Try to inject an interrupt if the guest can accept it */ |
1668 | if (run->ready_for_interrupt_injection && | |
1669 | (env->interrupt_request & CPU_INTERRUPT_HARD) && | |
1670 | (env->eflags & IF_MASK)) { | |
1671 | int irq; | |
1672 | ||
1673 | env->interrupt_request &= ~CPU_INTERRUPT_HARD; | |
1674 | irq = cpu_get_pic_interrupt(env); | |
1675 | if (irq >= 0) { | |
1676 | struct kvm_interrupt intr; | |
1677 | ||
1678 | intr.irq = irq; | |
db1669bc | 1679 | DPRINTF("injected interrupt %d\n", irq); |
ce377af3 JK |
1680 | ret = kvm_vcpu_ioctl(env, KVM_INTERRUPT, &intr); |
1681 | if (ret < 0) { | |
1682 | fprintf(stderr, | |
1683 | "KVM: injection failed, interrupt lost (%s)\n", | |
1684 | strerror(-ret)); | |
1685 | } | |
db1669bc JK |
1686 | } |
1687 | } | |
05330448 | 1688 | |
db1669bc JK |
1689 | /* If we have an interrupt but the guest is not ready to receive an |
1690 | * interrupt, request an interrupt window exit. This will | |
1691 | * cause a return to userspace as soon as the guest is ready to | |
1692 | * receive interrupts. */ | |
1693 | if ((env->interrupt_request & CPU_INTERRUPT_HARD)) { | |
1694 | run->request_interrupt_window = 1; | |
1695 | } else { | |
1696 | run->request_interrupt_window = 0; | |
1697 | } | |
1698 | ||
1699 | DPRINTF("setting tpr\n"); | |
1700 | run->cr8 = cpu_get_apic_tpr(env->apic_state); | |
1701 | } | |
05330448 AL |
1702 | } |
1703 | ||
7a39fe58 | 1704 | void kvm_arch_post_run(CPUState *env, struct kvm_run *run) |
05330448 | 1705 | { |
b9bec74b | 1706 | if (run->if_flag) { |
05330448 | 1707 | env->eflags |= IF_MASK; |
b9bec74b | 1708 | } else { |
05330448 | 1709 | env->eflags &= ~IF_MASK; |
b9bec74b | 1710 | } |
4a942cea BS |
1711 | cpu_set_apic_tpr(env->apic_state, run->cr8); |
1712 | cpu_set_apic_base(env->apic_state, run->apic_base); | |
05330448 AL |
1713 | } |
1714 | ||
99036865 | 1715 | int kvm_arch_process_async_events(CPUState *env) |
0af691d7 | 1716 | { |
ab443475 JK |
1717 | if (env->interrupt_request & CPU_INTERRUPT_MCE) { |
1718 | /* We must not raise CPU_INTERRUPT_MCE if it's not supported. */ | |
1719 | assert(env->mcg_cap); | |
1720 | ||
1721 | env->interrupt_request &= ~CPU_INTERRUPT_MCE; | |
1722 | ||
1723 | kvm_cpu_synchronize_state(env); | |
1724 | ||
1725 | if (env->exception_injected == EXCP08_DBLE) { | |
1726 | /* this means triple fault */ | |
1727 | qemu_system_reset_request(); | |
1728 | env->exit_request = 1; | |
1729 | return 0; | |
1730 | } | |
1731 | env->exception_injected = EXCP12_MCHK; | |
1732 | env->has_error_code = 0; | |
1733 | ||
1734 | env->halted = 0; | |
1735 | if (kvm_irqchip_in_kernel() && env->mp_state == KVM_MP_STATE_HALTED) { | |
1736 | env->mp_state = KVM_MP_STATE_RUNNABLE; | |
1737 | } | |
1738 | } | |
1739 | ||
db1669bc JK |
1740 | if (kvm_irqchip_in_kernel()) { |
1741 | return 0; | |
1742 | } | |
1743 | ||
6792a57b JK |
1744 | if (env->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_NMI)) { |
1745 | env->halted = 0; | |
1746 | } | |
0af691d7 MT |
1747 | if (env->interrupt_request & CPU_INTERRUPT_INIT) { |
1748 | kvm_cpu_synchronize_state(env); | |
1749 | do_cpu_init(env); | |
0af691d7 | 1750 | } |
0af691d7 MT |
1751 | if (env->interrupt_request & CPU_INTERRUPT_SIPI) { |
1752 | kvm_cpu_synchronize_state(env); | |
1753 | do_cpu_sipi(env); | |
1754 | } | |
1755 | ||
1756 | return env->halted; | |
1757 | } | |
1758 | ||
05330448 AL |
1759 | static int kvm_handle_halt(CPUState *env) |
1760 | { | |
1761 | if (!((env->interrupt_request & CPU_INTERRUPT_HARD) && | |
1762 | (env->eflags & IF_MASK)) && | |
1763 | !(env->interrupt_request & CPU_INTERRUPT_NMI)) { | |
1764 | env->halted = 1; | |
05330448 AL |
1765 | return 0; |
1766 | } | |
1767 | ||
1768 | return 1; | |
1769 | } | |
1770 | ||
bb44e0d1 JK |
1771 | static bool host_supports_vmx(void) |
1772 | { | |
1773 | uint32_t ecx, unused; | |
1774 | ||
1775 | host_cpuid(1, 0, &unused, &unused, &ecx, &unused); | |
1776 | return ecx & CPUID_EXT_VMX; | |
1777 | } | |
1778 | ||
1779 | #define VMX_INVALID_GUEST_STATE 0x80000021 | |
1780 | ||
05330448 AL |
1781 | int kvm_arch_handle_exit(CPUState *env, struct kvm_run *run) |
1782 | { | |
bb44e0d1 | 1783 | uint64_t code; |
05330448 AL |
1784 | int ret = 0; |
1785 | ||
1786 | switch (run->exit_reason) { | |
1787 | case KVM_EXIT_HLT: | |
8c0d577e | 1788 | DPRINTF("handle_hlt\n"); |
05330448 AL |
1789 | ret = kvm_handle_halt(env); |
1790 | break; | |
646042e1 JK |
1791 | case KVM_EXIT_SET_TPR: |
1792 | ret = 1; | |
1793 | break; | |
bb44e0d1 JK |
1794 | case KVM_EXIT_FAIL_ENTRY: |
1795 | code = run->fail_entry.hardware_entry_failure_reason; | |
1796 | fprintf(stderr, "KVM: entry failed, hardware error 0x%" PRIx64 "\n", | |
1797 | code); | |
1798 | if (host_supports_vmx() && code == VMX_INVALID_GUEST_STATE) { | |
1799 | fprintf(stderr, | |
1800 | "\nIf you're runnning a guest on an Intel machine without " | |
1801 | "unrestricted mode\n" | |
1802 | "support, the failure can be most likely due to the guest " | |
1803 | "entering an invalid\n" | |
1804 | "state for Intel VT. For example, the guest maybe running " | |
1805 | "in big real mode\n" | |
1806 | "which is not supported on less recent Intel processors." | |
1807 | "\n\n"); | |
1808 | } | |
1809 | ret = -1; | |
1810 | break; | |
1811 | case KVM_EXIT_EXCEPTION: | |
1812 | fprintf(stderr, "KVM: exception %d exit (error code 0x%x)\n", | |
1813 | run->ex.exception, run->ex.error_code); | |
1814 | ret = -1; | |
1815 | break; | |
73aaec4a JK |
1816 | default: |
1817 | fprintf(stderr, "KVM: unknown exit reason %d\n", run->exit_reason); | |
1818 | ret = -1; | |
1819 | break; | |
05330448 AL |
1820 | } |
1821 | ||
1822 | return ret; | |
1823 | } | |
e22a25c9 AL |
1824 | |
1825 | #ifdef KVM_CAP_SET_GUEST_DEBUG | |
e22a25c9 AL |
1826 | int kvm_arch_insert_sw_breakpoint(CPUState *env, struct kvm_sw_breakpoint *bp) |
1827 | { | |
38972938 | 1828 | static const uint8_t int3 = 0xcc; |
64bf3f4e | 1829 | |
e22a25c9 | 1830 | if (cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&bp->saved_insn, 1, 0) || |
b9bec74b | 1831 | cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&int3, 1, 1)) { |
e22a25c9 | 1832 | return -EINVAL; |
b9bec74b | 1833 | } |
e22a25c9 AL |
1834 | return 0; |
1835 | } | |
1836 | ||
1837 | int kvm_arch_remove_sw_breakpoint(CPUState *env, struct kvm_sw_breakpoint *bp) | |
1838 | { | |
1839 | uint8_t int3; | |
1840 | ||
1841 | if (cpu_memory_rw_debug(env, bp->pc, &int3, 1, 0) || int3 != 0xcc || | |
b9bec74b | 1842 | cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&bp->saved_insn, 1, 1)) { |
e22a25c9 | 1843 | return -EINVAL; |
b9bec74b | 1844 | } |
e22a25c9 AL |
1845 | return 0; |
1846 | } | |
1847 | ||
1848 | static struct { | |
1849 | target_ulong addr; | |
1850 | int len; | |
1851 | int type; | |
1852 | } hw_breakpoint[4]; | |
1853 | ||
1854 | static int nb_hw_breakpoint; | |
1855 | ||
1856 | static int find_hw_breakpoint(target_ulong addr, int len, int type) | |
1857 | { | |
1858 | int n; | |
1859 | ||
b9bec74b | 1860 | for (n = 0; n < nb_hw_breakpoint; n++) { |
e22a25c9 | 1861 | if (hw_breakpoint[n].addr == addr && hw_breakpoint[n].type == type && |
b9bec74b | 1862 | (hw_breakpoint[n].len == len || len == -1)) { |
e22a25c9 | 1863 | return n; |
b9bec74b JK |
1864 | } |
1865 | } | |
e22a25c9 AL |
1866 | return -1; |
1867 | } | |
1868 | ||
1869 | int kvm_arch_insert_hw_breakpoint(target_ulong addr, | |
1870 | target_ulong len, int type) | |
1871 | { | |
1872 | switch (type) { | |
1873 | case GDB_BREAKPOINT_HW: | |
1874 | len = 1; | |
1875 | break; | |
1876 | case GDB_WATCHPOINT_WRITE: | |
1877 | case GDB_WATCHPOINT_ACCESS: | |
1878 | switch (len) { | |
1879 | case 1: | |
1880 | break; | |
1881 | case 2: | |
1882 | case 4: | |
1883 | case 8: | |
b9bec74b | 1884 | if (addr & (len - 1)) { |
e22a25c9 | 1885 | return -EINVAL; |
b9bec74b | 1886 | } |
e22a25c9 AL |
1887 | break; |
1888 | default: | |
1889 | return -EINVAL; | |
1890 | } | |
1891 | break; | |
1892 | default: | |
1893 | return -ENOSYS; | |
1894 | } | |
1895 | ||
b9bec74b | 1896 | if (nb_hw_breakpoint == 4) { |
e22a25c9 | 1897 | return -ENOBUFS; |
b9bec74b JK |
1898 | } |
1899 | if (find_hw_breakpoint(addr, len, type) >= 0) { | |
e22a25c9 | 1900 | return -EEXIST; |
b9bec74b | 1901 | } |
e22a25c9 AL |
1902 | hw_breakpoint[nb_hw_breakpoint].addr = addr; |
1903 | hw_breakpoint[nb_hw_breakpoint].len = len; | |
1904 | hw_breakpoint[nb_hw_breakpoint].type = type; | |
1905 | nb_hw_breakpoint++; | |
1906 | ||
1907 | return 0; | |
1908 | } | |
1909 | ||
1910 | int kvm_arch_remove_hw_breakpoint(target_ulong addr, | |
1911 | target_ulong len, int type) | |
1912 | { | |
1913 | int n; | |
1914 | ||
1915 | n = find_hw_breakpoint(addr, (type == GDB_BREAKPOINT_HW) ? 1 : len, type); | |
b9bec74b | 1916 | if (n < 0) { |
e22a25c9 | 1917 | return -ENOENT; |
b9bec74b | 1918 | } |
e22a25c9 AL |
1919 | nb_hw_breakpoint--; |
1920 | hw_breakpoint[n] = hw_breakpoint[nb_hw_breakpoint]; | |
1921 | ||
1922 | return 0; | |
1923 | } | |
1924 | ||
1925 | void kvm_arch_remove_all_hw_breakpoints(void) | |
1926 | { | |
1927 | nb_hw_breakpoint = 0; | |
1928 | } | |
1929 | ||
1930 | static CPUWatchpoint hw_watchpoint; | |
1931 | ||
1932 | int kvm_arch_debug(struct kvm_debug_exit_arch *arch_info) | |
1933 | { | |
1934 | int handle = 0; | |
1935 | int n; | |
1936 | ||
1937 | if (arch_info->exception == 1) { | |
1938 | if (arch_info->dr6 & (1 << 14)) { | |
b9bec74b | 1939 | if (cpu_single_env->singlestep_enabled) { |
e22a25c9 | 1940 | handle = 1; |
b9bec74b | 1941 | } |
e22a25c9 | 1942 | } else { |
b9bec74b JK |
1943 | for (n = 0; n < 4; n++) { |
1944 | if (arch_info->dr6 & (1 << n)) { | |
e22a25c9 AL |
1945 | switch ((arch_info->dr7 >> (16 + n*4)) & 0x3) { |
1946 | case 0x0: | |
1947 | handle = 1; | |
1948 | break; | |
1949 | case 0x1: | |
1950 | handle = 1; | |
1951 | cpu_single_env->watchpoint_hit = &hw_watchpoint; | |
1952 | hw_watchpoint.vaddr = hw_breakpoint[n].addr; | |
1953 | hw_watchpoint.flags = BP_MEM_WRITE; | |
1954 | break; | |
1955 | case 0x3: | |
1956 | handle = 1; | |
1957 | cpu_single_env->watchpoint_hit = &hw_watchpoint; | |
1958 | hw_watchpoint.vaddr = hw_breakpoint[n].addr; | |
1959 | hw_watchpoint.flags = BP_MEM_ACCESS; | |
1960 | break; | |
1961 | } | |
b9bec74b JK |
1962 | } |
1963 | } | |
e22a25c9 | 1964 | } |
b9bec74b | 1965 | } else if (kvm_find_sw_breakpoint(cpu_single_env, arch_info->pc)) { |
e22a25c9 | 1966 | handle = 1; |
b9bec74b | 1967 | } |
b0b1d690 JK |
1968 | if (!handle) { |
1969 | cpu_synchronize_state(cpu_single_env); | |
1970 | assert(cpu_single_env->exception_injected == -1); | |
1971 | ||
1972 | cpu_single_env->exception_injected = arch_info->exception; | |
1973 | cpu_single_env->has_error_code = 0; | |
1974 | } | |
e22a25c9 AL |
1975 | |
1976 | return handle; | |
1977 | } | |
1978 | ||
1979 | void kvm_arch_update_guest_debug(CPUState *env, struct kvm_guest_debug *dbg) | |
1980 | { | |
1981 | const uint8_t type_code[] = { | |
1982 | [GDB_BREAKPOINT_HW] = 0x0, | |
1983 | [GDB_WATCHPOINT_WRITE] = 0x1, | |
1984 | [GDB_WATCHPOINT_ACCESS] = 0x3 | |
1985 | }; | |
1986 | const uint8_t len_code[] = { | |
1987 | [1] = 0x0, [2] = 0x1, [4] = 0x3, [8] = 0x2 | |
1988 | }; | |
1989 | int n; | |
1990 | ||
b9bec74b | 1991 | if (kvm_sw_breakpoints_active(env)) { |
e22a25c9 | 1992 | dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP; |
b9bec74b | 1993 | } |
e22a25c9 AL |
1994 | if (nb_hw_breakpoint > 0) { |
1995 | dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP; | |
1996 | dbg->arch.debugreg[7] = 0x0600; | |
1997 | for (n = 0; n < nb_hw_breakpoint; n++) { | |
1998 | dbg->arch.debugreg[n] = hw_breakpoint[n].addr; | |
1999 | dbg->arch.debugreg[7] |= (2 << (n * 2)) | | |
2000 | (type_code[hw_breakpoint[n].type] << (16 + n*4)) | | |
95c077c9 | 2001 | ((uint32_t)len_code[hw_breakpoint[n].len] << (18 + n*4)); |
e22a25c9 AL |
2002 | } |
2003 | } | |
2004 | } | |
2005 | #endif /* KVM_CAP_SET_GUEST_DEBUG */ | |
4513d923 GN |
2006 | |
2007 | bool kvm_arch_stop_on_emulation_error(CPUState *env) | |
2008 | { | |
b9bec74b JK |
2009 | return !(env->cr[0] & CR0_PE_MASK) || |
2010 | ((env->segs[R_CS].selector & 3) != 3); | |
4513d923 | 2011 | } |