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kvm: kvm_mce_inj_* subroutines for templated error injections
[mirror_qemu.git] / target-i386 / kvm.c
CommitLineData
05330448
AL		 1/*
2 * QEMU KVM support
3 *
4 * Copyright (C) 2006-2008 Qumranet Technologies
5 * Copyright IBM, Corp. 2008
6 *
7 * Authors:
8 * Anthony Liguori <aliguori@us.ibm.com>
9 *
10 * This work is licensed under the terms of the GNU GPL, version 2 or later.
11 * See the COPYING file in the top-level directory.
12 *
13 */
14
15#include <sys/types.h>
16#include <sys/ioctl.h>
17#include <sys/mman.h>
25d2e361 18#include <sys/utsname.h>
05330448
AL		 19
20#include <linux/kvm.h>
21
22#include "qemu-common.h"
23#include "sysemu.h"
24#include "kvm.h"
25#include "cpu.h"
e22a25c9 26#include "gdbstub.h"
0e607a80 27#include "host-utils.h"
4c5b10b7 28#include "hw/pc.h"
408392b3 29#include "hw/apic.h"
35bed8ee 30#include "ioport.h"
e7701825 31#include "kvm_x86.h"
05330448 32
bb0300dc
GN		 33#ifdef CONFIG_KVM_PARA
34#include <linux/kvm_para.h>
35#endif
36//
05330448
AL		 37//#define DEBUG_KVM
38
39#ifdef DEBUG_KVM
8c0d577e 40#define DPRINTF(fmt, ...) \
05330448
AL		 41 do { fprintf(stderr, fmt, ## __VA_ARGS__); } while (0)
42#else
8c0d577e 43#define DPRINTF(fmt, ...) \
05330448
AL		 44 do { } while (0)
45#endif
46
1a03675d
GC		 47#define MSR_KVM_WALL_CLOCK 0x11
48#define MSR_KVM_SYSTEM_TIME 0x12
49
c0532a76
MT		 50#ifndef BUS_MCEERR_AR
51#define BUS_MCEERR_AR 4
52#endif
53#ifndef BUS_MCEERR_AO
54#define BUS_MCEERR_AO 5
55#endif
56
25d2e361
MT		 57static int lm_capable_kernel;
58
b827df58
AK		 59#ifdef KVM_CAP_EXT_CPUID
60
61static struct kvm_cpuid2 *try_get_cpuid(KVMState *s, int max)
62{
63 struct kvm_cpuid2 *cpuid;
64 int r, size;
65
66 size = sizeof(*cpuid) + max * sizeof(*cpuid->entries);
67 cpuid = (struct kvm_cpuid2 *)qemu_mallocz(size);
68 cpuid->nent = max;
69 r = kvm_ioctl(s, KVM_GET_SUPPORTED_CPUID, cpuid);
76ae317f
MM		 70 if (r == 0 && cpuid->nent >= max) {
71 r = -E2BIG;
72 }
b827df58
AK		 73 if (r < 0) {
74 if (r == -E2BIG) {
75 qemu_free(cpuid);
76 return NULL;
77 } else {
78 fprintf(stderr, "KVM_GET_SUPPORTED_CPUID failed: %s\n",
79 strerror(-r));
80 exit(1);
81 }
82 }
83 return cpuid;
84}
85
c958a8bd
SY		 86uint32_t kvm_arch_get_supported_cpuid(CPUState *env, uint32_t function,
87 uint32_t index, int reg)
b827df58
AK		 88{
89 struct kvm_cpuid2 *cpuid;
90 int i, max;
91 uint32_t ret = 0;
92 uint32_t cpuid_1_edx;
93
94 if (!kvm_check_extension(env->kvm_state, KVM_CAP_EXT_CPUID)) {
95 return -1U;
96 }
97
98 max = 1;
99 while ((cpuid = try_get_cpuid(env->kvm_state, max)) == NULL) {
100 max *= 2;
101 }
102
103 for (i = 0; i < cpuid->nent; ++i) {
c958a8bd
SY		 104 if (cpuid->entries[i].function == function &&
105 cpuid->entries[i].index == index) {
b827df58
AK		 106 switch (reg) {
107 case R_EAX:
108 ret = cpuid->entries[i].eax;
109 break;
110 case R_EBX:
111 ret = cpuid->entries[i].ebx;
112 break;
113 case R_ECX:
114 ret = cpuid->entries[i].ecx;
115 break;
116 case R_EDX:
117 ret = cpuid->entries[i].edx;
19ccb8ea
JK		 118 switch (function) {
119 case 1:
120 /* KVM before 2.6.30 misreports the following features */
121 ret |= CPUID_MTRR | CPUID_PAT | CPUID_MCE | CPUID_MCA;
122 break;
123 case 0x80000001:
b827df58
AK		 124 /* On Intel, kvm returns cpuid according to the Intel spec,
125 * so add missing bits according to the AMD spec:
126 */
c958a8bd 127 cpuid_1_edx = kvm_arch_get_supported_cpuid(env, 1, 0, R_EDX);
c1667e40 128 ret |= cpuid_1_edx & 0x183f7ff;
19ccb8ea 129 break;
b827df58
AK		 130 }
131 break;
132 }
133 }
134 }
135
136 qemu_free(cpuid);
137
138 return ret;
139}
140
141#else
142
c958a8bd
SY		 143uint32_t kvm_arch_get_supported_cpuid(CPUState *env, uint32_t function,
144 uint32_t index, int reg)
b827df58
AK		 145{
146 return -1U;
147}
148
149#endif
150
bb0300dc
GN		 151#ifdef CONFIG_KVM_PARA
152struct kvm_para_features {
153 int cap;
154 int feature;
155} para_features[] = {
156#ifdef KVM_CAP_CLOCKSOURCE
157 { KVM_CAP_CLOCKSOURCE, KVM_FEATURE_CLOCKSOURCE },
158#endif
159#ifdef KVM_CAP_NOP_IO_DELAY
160 { KVM_CAP_NOP_IO_DELAY, KVM_FEATURE_NOP_IO_DELAY },
161#endif
162#ifdef KVM_CAP_PV_MMU
163 { KVM_CAP_PV_MMU, KVM_FEATURE_MMU_OP },
f6584ee2
GN		 164#endif
165#ifdef KVM_CAP_ASYNC_PF
166 { KVM_CAP_ASYNC_PF, KVM_FEATURE_ASYNC_PF },
bb0300dc
GN		 167#endif
168 { -1, -1 }
169};
170
171static int get_para_features(CPUState *env)
172{
173 int i, features = 0;
174
175 for (i = 0; i < ARRAY_SIZE(para_features) - 1; i++) {
176 if (kvm_check_extension(env->kvm_state, para_features[i].cap))
177 features |= (1 << para_features[i].feature);
178 }
179
180 return features;
181}
182#endif
183
e7701825
MT		 184#ifdef KVM_CAP_MCE
185static int kvm_get_mce_cap_supported(KVMState *s, uint64_t *mce_cap,
186 int *max_banks)
187{
188 int r;
189
14a09518 190 r = kvm_check_extension(s, KVM_CAP_MCE);
e7701825
MT		 191 if (r > 0) {
192 *max_banks = r;
193 return kvm_ioctl(s, KVM_X86_GET_MCE_CAP_SUPPORTED, mce_cap);
194 }
195 return -ENOSYS;
196}
197
198static int kvm_setup_mce(CPUState *env, uint64_t *mcg_cap)
199{
200 return kvm_vcpu_ioctl(env, KVM_X86_SETUP_MCE, mcg_cap);
201}
202
203static int kvm_set_mce(CPUState *env, struct kvm_x86_mce *m)
204{
205 return kvm_vcpu_ioctl(env, KVM_X86_SET_MCE, m);
206}
207
c0532a76
MT		 208static int kvm_get_msr(CPUState *env, struct kvm_msr_entry *msrs, int n)
209{
210 struct kvm_msrs *kmsrs = qemu_malloc(sizeof *kmsrs + n * sizeof *msrs);
211 int r;
212
213 kmsrs->nmsrs = n;
214 memcpy(kmsrs->entries, msrs, n * sizeof *msrs);
215 r = kvm_vcpu_ioctl(env, KVM_GET_MSRS, kmsrs);
216 memcpy(msrs, kmsrs->entries, n * sizeof *msrs);
217 free(kmsrs);
218 return r;
219}
220
221/* FIXME: kill this and kvm_get_msr, use env->mcg_status instead */
6643e2f0 222static int kvm_mce_in_progress(CPUState *env)
c0532a76
MT		 223{
224 struct kvm_msr_entry msr_mcg_status = {
225 .index = MSR_MCG_STATUS,
226 };
227 int r;
228
229 r = kvm_get_msr(env, &msr_mcg_status, 1);
230 if (r == -1 || r == 0) {
6643e2f0
JD		 231 fprintf(stderr, "Failed to get MCE status\n");
232 return 0;
c0532a76
MT		 233 }
234 return !!(msr_mcg_status.data & MCG_STATUS_MCIP);
235}
236
e7701825
MT		 237struct kvm_x86_mce_data
238{
239 CPUState *env;
240 struct kvm_x86_mce *mce;
c0532a76 241 int abort_on_error;
e7701825
MT		 242};
243
244static void kvm_do_inject_x86_mce(void *_data)
245{
246 struct kvm_x86_mce_data *data = _data;
247 int r;
248
f8502cfb
HS		 249 /* If there is an MCE exception being processed, ignore this SRAO MCE */
250 if ((data->env->mcg_cap & MCG_SER_P) &&
251 !(data->mce->status & MCI_STATUS_AR)) {
6643e2f0 252 if (kvm_mce_in_progress(data->env)) {
f8502cfb
HS		 253 return;
254 }
255 }
c0532a76 256
e7701825 257 r = kvm_set_mce(data->env, data->mce);
c0532a76 258 if (r < 0) {
e7701825 259 perror("kvm_set_mce FAILED");
c0532a76
MT		 260 if (data->abort_on_error) {
261 abort();
262 }
263 }
e7701825 264}
31ce5e0c
JD		 265
266static void kvm_mce_broadcast_rest(CPUState *env);
e7701825
MT		 267#endif
268
269void kvm_inject_x86_mce(CPUState *cenv, int bank, uint64_t status,
c0532a76 270 uint64_t mcg_status, uint64_t addr, uint64_t misc,
31ce5e0c 271 int flag)
e7701825
MT		 272{
273#ifdef KVM_CAP_MCE
274 struct kvm_x86_mce mce = {
275 .bank = bank,
276 .status = status,
277 .mcg_status = mcg_status,
278 .addr = addr,
279 .misc = misc,
280 };
281 struct kvm_x86_mce_data data = {
282 .env = cenv,
283 .mce = &mce,
284 };
285
c0532a76
MT		 286 if (!cenv->mcg_cap) {
287 fprintf(stderr, "MCE support is not enabled!\n");
288 return;
289 }
290
31ce5e0c
JD		 291 if (flag & MCE_BROADCAST) {
292 kvm_mce_broadcast_rest(cenv);
293 }
294
e7701825 295 run_on_cpu(cenv, kvm_do_inject_x86_mce, &data);
c0532a76 296#else
31ce5e0c 297 if (flag & ABORT_ON_ERROR) {
c0532a76 298 abort();
31ce5e0c 299 }
e7701825
MT		 300#endif
301}
302
05330448
AL		 303int kvm_arch_init_vcpu(CPUState *env)
304{
305 struct {
486bd5a2
AL		 306 struct kvm_cpuid2 cpuid;
307 struct kvm_cpuid_entry2 entries[100];
05330448 308 } __attribute__((packed)) cpuid_data;
486bd5a2 309 uint32_t limit, i, j, cpuid_i;
a33609ca 310 uint32_t unused;
bb0300dc
GN		 311 struct kvm_cpuid_entry2 *c;
312#ifdef KVM_CPUID_SIGNATURE
313 uint32_t signature[3];
314#endif
05330448 315
f8d926e9
JK		 316 env->mp_state = KVM_MP_STATE_RUNNABLE;
317
c958a8bd 318 env->cpuid_features &= kvm_arch_get_supported_cpuid(env, 1, 0, R_EDX);
6c0d7ee8
AP		 319
320 i = env->cpuid_ext_features & CPUID_EXT_HYPERVISOR;
c958a8bd 321 env->cpuid_ext_features &= kvm_arch_get_supported_cpuid(env, 1, 0, R_ECX);
6c0d7ee8
AP		 322 env->cpuid_ext_features |= i;
323
457dfed6 324 env->cpuid_ext2_features &= kvm_arch_get_supported_cpuid(env, 0x80000001,
c958a8bd 325 0, R_EDX);
457dfed6 326 env->cpuid_ext3_features &= kvm_arch_get_supported_cpuid(env, 0x80000001,
c958a8bd 327 0, R_ECX);
296acb64
JR		 328 env->cpuid_svm_features &= kvm_arch_get_supported_cpuid(env, 0x8000000A,
329 0, R_EDX);
330
6c1f42fe 331
05330448
AL		 332 cpuid_i = 0;
333
bb0300dc
GN		 334#ifdef CONFIG_KVM_PARA
335 /* Paravirtualization CPUIDs */
336 memcpy(signature, "KVMKVMKVM\0\0\0", 12);
337 c = &cpuid_data.entries[cpuid_i++];
338 memset(c, 0, sizeof(*c));
339 c->function = KVM_CPUID_SIGNATURE;
340 c->eax = 0;
341 c->ebx = signature[0];
342 c->ecx = signature[1];
343 c->edx = signature[2];
344
345 c = &cpuid_data.entries[cpuid_i++];
346 memset(c, 0, sizeof(*c));
347 c->function = KVM_CPUID_FEATURES;
348 c->eax = env->cpuid_kvm_features & get_para_features(env);
349#endif
350
a33609ca 351 cpu_x86_cpuid(env, 0, 0, &limit, &unused, &unused, &unused);
05330448
AL		 352
353 for (i = 0; i <= limit; i++) {
bb0300dc 354 c = &cpuid_data.entries[cpuid_i++];
486bd5a2
AL		 355
356 switch (i) {
a36b1029
AL		 357 case 2: {
358 /* Keep reading function 2 till all the input is received */
359 int times;
360
a36b1029 361 c->function = i;
a33609ca
AL		 362 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC |
363 KVM_CPUID_FLAG_STATE_READ_NEXT;
364 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
365 times = c->eax & 0xff;
a36b1029
AL		 366
367 for (j = 1; j < times; ++j) {
a33609ca 368 c = &cpuid_data.entries[cpuid_i++];
a36b1029 369 c->function = i;
a33609ca
AL		 370 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC;
371 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
a36b1029
AL		 372 }
373 break;
374 }
486bd5a2
AL		 375 case 4:
376 case 0xb:
377 case 0xd:
378 for (j = 0; ; j++) {
486bd5a2
AL		 379 c->function = i;
380 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
381 c->index = j;
a33609ca 382 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
486bd5a2 383
a33609ca 384 if (i == 4 && c->eax == 0)
486bd5a2 385 break;
a33609ca 386 if (i == 0xb && !(c->ecx & 0xff00))
486bd5a2 387 break;
a33609ca 388 if (i == 0xd && c->eax == 0)
486bd5a2 389 break;
a33609ca
AL		 390
391 c = &cpuid_data.entries[cpuid_i++];
486bd5a2
AL		 392 }
393 break;
394 default:
486bd5a2 395 c->function = i;
a33609ca
AL		 396 c->flags = 0;
397 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
486bd5a2
AL		 398 break;
399 }
05330448 400 }
a33609ca 401 cpu_x86_cpuid(env, 0x80000000, 0, &limit, &unused, &unused, &unused);
05330448
AL		 402
403 for (i = 0x80000000; i <= limit; i++) {
bb0300dc 404 c = &cpuid_data.entries[cpuid_i++];
05330448 405
05330448 406 c->function = i;
a33609ca
AL		 407 c->flags = 0;
408 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
05330448
AL		 409 }
410
411 cpuid_data.cpuid.nent = cpuid_i;
412
e7701825
MT		 413#ifdef KVM_CAP_MCE
414 if (((env->cpuid_version >> 8)&0xF) >= 6
415 && (env->cpuid_features&(CPUID_MCE|CPUID_MCA)) == (CPUID_MCE|CPUID_MCA)
416 && kvm_check_extension(env->kvm_state, KVM_CAP_MCE) > 0) {
417 uint64_t mcg_cap;
418 int banks;
419
420 if (kvm_get_mce_cap_supported(env->kvm_state, &mcg_cap, &banks))
421 perror("kvm_get_mce_cap_supported FAILED");
422 else {
423 if (banks > MCE_BANKS_DEF)
424 banks = MCE_BANKS_DEF;
425 mcg_cap &= MCE_CAP_DEF;
426 mcg_cap |= banks;
427 if (kvm_setup_mce(env, &mcg_cap))
428 perror("kvm_setup_mce FAILED");
429 else
430 env->mcg_cap = mcg_cap;
431 }
432 }
433#endif
434
486bd5a2 435 return kvm_vcpu_ioctl(env, KVM_SET_CPUID2, &cpuid_data);
05330448
AL		 436}
437
caa5af0f
JK		 438void kvm_arch_reset_vcpu(CPUState *env)
439{
e73223a5 440 env->exception_injected = -1;
0e607a80 441 env->interrupt_injected = -1;
a0fb002c
JK		 442 env->nmi_injected = 0;
443 env->nmi_pending = 0;
ddced198
MT		 444 if (kvm_irqchip_in_kernel()) {
445 env->mp_state = cpu_is_bsp(env) ? KVM_MP_STATE_RUNNABLE :
446 KVM_MP_STATE_UNINITIALIZED;
447 } else {
448 env->mp_state = KVM_MP_STATE_RUNNABLE;
449 }
caa5af0f
JK		 450}
451
75b10c43
MT		 452int has_msr_star;
453int has_msr_hsave_pa;
454
455static void kvm_supported_msrs(CPUState *env)
05330448 456{
75b10c43 457 static int kvm_supported_msrs;
05330448
AL		 458 int ret;
459
460 /* first time */
75b10c43 461 if (kvm_supported_msrs == 0) {
05330448
AL		 462 struct kvm_msr_list msr_list, *kvm_msr_list;
463
75b10c43 464 kvm_supported_msrs = -1;
05330448
AL		 465
466 /* Obtain MSR list from KVM. These are the MSRs that we must
467 * save/restore */
4c9f7372 468 msr_list.nmsrs = 0;
05330448 469 ret = kvm_ioctl(env->kvm_state, KVM_GET_MSR_INDEX_LIST, &msr_list);
6fb6d245 470 if (ret < 0 && ret != -E2BIG) {
75b10c43 471 return;
6fb6d245 472 }
d9db889f
JK		 473 /* Old kernel modules had a bug and could write beyond the provided
474 memory. Allocate at least a safe amount of 1K. */
475 kvm_msr_list = qemu_mallocz(MAX(1024, sizeof(msr_list) +
476 msr_list.nmsrs *
477 sizeof(msr_list.indices[0])));
05330448 478
55308450 479 kvm_msr_list->nmsrs = msr_list.nmsrs;
05330448
AL		 480 ret = kvm_ioctl(env->kvm_state, KVM_GET_MSR_INDEX_LIST, kvm_msr_list);
481 if (ret >= 0) {
482 int i;
483
484 for (i = 0; i < kvm_msr_list->nmsrs; i++) {
485 if (kvm_msr_list->indices[i] == MSR_STAR) {
486 has_msr_star = 1;
75b10c43
MT		 487 continue;
488 }
489 if (kvm_msr_list->indices[i] == MSR_VM_HSAVE_PA) {
490 has_msr_hsave_pa = 1;
491 continue;
05330448
AL		 492 }
493 }
494 }
495
496 free(kvm_msr_list);
497 }
498
75b10c43
MT		 499 return;
500}
501
502static int kvm_has_msr_hsave_pa(CPUState *env)
503{
504 kvm_supported_msrs(env);
505 return has_msr_hsave_pa;
506}
507
508static int kvm_has_msr_star(CPUState *env)
509{
510 kvm_supported_msrs(env);
511 return has_msr_star;
05330448
AL		 512}
513
20420430
SY		 514static int kvm_init_identity_map_page(KVMState *s)
515{
516#ifdef KVM_CAP_SET_IDENTITY_MAP_ADDR
517 int ret;
518 uint64_t addr = 0xfffbc000;
519
520 if (!kvm_check_extension(s, KVM_CAP_SET_IDENTITY_MAP_ADDR)) {
521 return 0;
522 }
523
524 ret = kvm_vm_ioctl(s, KVM_SET_IDENTITY_MAP_ADDR, &addr);
525 if (ret < 0) {
526 fprintf(stderr, "kvm_set_identity_map_addr: %s\n", strerror(ret));
527 return ret;
528 }
529#endif
530 return 0;
531}
532
05330448
AL		 533int kvm_arch_init(KVMState *s, int smp_cpus)
534{
535 int ret;
536
25d2e361
MT		 537 struct utsname utsname;
538
539 uname(&utsname);
540 lm_capable_kernel = strcmp(utsname.machine, "x86_64") == 0;
541
05330448
AL		 542 /* create vm86 tss. KVM uses vm86 mode to emulate 16-bit code
543 * directly. In order to use vm86 mode, a TSS is needed. Since this
544 * must be part of guest physical memory, we need to allocate it. Older
545 * versions of KVM just assumed that it would be at the end of physical
546 * memory but that doesn't work with more than 4GB of memory. We simply
547 * refuse to work with those older versions of KVM. */
14a09518 548 ret = kvm_check_extension(s, KVM_CAP_SET_TSS_ADDR);
05330448
AL		 549 if (ret <= 0) {
550 fprintf(stderr, "kvm does not support KVM_CAP_SET_TSS_ADDR\n");
551 return ret;
552 }
553
554 /* this address is 3 pages before the bios, and the bios should present
555 * as unavaible memory. FIXME, need to ensure the e820 map deals with
556 * this?
557 */
4c5b10b7
JS		 558 /*
559 * Tell fw_cfg to notify the BIOS to reserve the range.
560 */
561 if (e820_add_entry(0xfffbc000, 0x4000, E820_RESERVED) < 0) {
562 perror("e820_add_entry() table is full");
563 exit(1);
564 }
20420430
SY		 565 ret = kvm_vm_ioctl(s, KVM_SET_TSS_ADDR, 0xfffbd000);
566 if (ret < 0) {
567 return ret;
568 }
569
570 return kvm_init_identity_map_page(s);
05330448
AL		 571}
572
573static void set_v8086_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
574{
575 lhs->selector = rhs->selector;
576 lhs->base = rhs->base;
577 lhs->limit = rhs->limit;
578 lhs->type = 3;
579 lhs->present = 1;
580 lhs->dpl = 3;
581 lhs->db = 0;
582 lhs->s = 1;
583 lhs->l = 0;
584 lhs->g = 0;
585 lhs->avl = 0;
586 lhs->unusable = 0;
587}
588
589static void set_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
590{
591 unsigned flags = rhs->flags;
592 lhs->selector = rhs->selector;
593 lhs->base = rhs->base;
594 lhs->limit = rhs->limit;
595 lhs->type = (flags >> DESC_TYPE_SHIFT) & 15;
596 lhs->present = (flags & DESC_P_MASK) != 0;
597 lhs->dpl = rhs->selector & 3;
598 lhs->db = (flags >> DESC_B_SHIFT) & 1;
599 lhs->s = (flags & DESC_S_MASK) != 0;
600 lhs->l = (flags >> DESC_L_SHIFT) & 1;
601 lhs->g = (flags & DESC_G_MASK) != 0;
602 lhs->avl = (flags & DESC_AVL_MASK) != 0;
603 lhs->unusable = 0;
604}
605
606static void get_seg(SegmentCache *lhs, const struct kvm_segment *rhs)
607{
608 lhs->selector = rhs->selector;
609 lhs->base = rhs->base;
610 lhs->limit = rhs->limit;
611 lhs->flags =
612 (rhs->type << DESC_TYPE_SHIFT)
613 | (rhs->present * DESC_P_MASK)
614 | (rhs->dpl << DESC_DPL_SHIFT)
615 | (rhs->db << DESC_B_SHIFT)
616 | (rhs->s * DESC_S_MASK)
617 | (rhs->l << DESC_L_SHIFT)
618 | (rhs->g * DESC_G_MASK)
619 | (rhs->avl * DESC_AVL_MASK);
620}
621
622static void kvm_getput_reg(__u64 *kvm_reg, target_ulong *qemu_reg, int set)
623{
624 if (set)
625 *kvm_reg = *qemu_reg;
626 else
627 *qemu_reg = *kvm_reg;
628}
629
630static int kvm_getput_regs(CPUState *env, int set)
631{
632 struct kvm_regs regs;
633 int ret = 0;
634
635 if (!set) {
636 ret = kvm_vcpu_ioctl(env, KVM_GET_REGS, &regs);
637 if (ret < 0)
638 return ret;
639 }
640
641 kvm_getput_reg(&regs.rax, &env->regs[R_EAX], set);
642 kvm_getput_reg(&regs.rbx, &env->regs[R_EBX], set);
643 kvm_getput_reg(&regs.rcx, &env->regs[R_ECX], set);
644 kvm_getput_reg(&regs.rdx, &env->regs[R_EDX], set);
645 kvm_getput_reg(&regs.rsi, &env->regs[R_ESI], set);
646 kvm_getput_reg(&regs.rdi, &env->regs[R_EDI], set);
647 kvm_getput_reg(&regs.rsp, &env->regs[R_ESP], set);
648 kvm_getput_reg(&regs.rbp, &env->regs[R_EBP], set);
649#ifdef TARGET_X86_64
650 kvm_getput_reg(&regs.r8, &env->regs[8], set);
651 kvm_getput_reg(&regs.r9, &env->regs[9], set);
652 kvm_getput_reg(&regs.r10, &env->regs[10], set);
653 kvm_getput_reg(&regs.r11, &env->regs[11], set);
654 kvm_getput_reg(&regs.r12, &env->regs[12], set);
655 kvm_getput_reg(&regs.r13, &env->regs[13], set);
656 kvm_getput_reg(&regs.r14, &env->regs[14], set);
657 kvm_getput_reg(&regs.r15, &env->regs[15], set);
658#endif
659
660 kvm_getput_reg(&regs.rflags, &env->eflags, set);
661 kvm_getput_reg(&regs.rip, &env->eip, set);
662
663 if (set)
664 ret = kvm_vcpu_ioctl(env, KVM_SET_REGS, &regs);
665
666 return ret;
667}
668
669static int kvm_put_fpu(CPUState *env)
670{
671 struct kvm_fpu fpu;
672 int i;
673
674 memset(&fpu, 0, sizeof fpu);
675 fpu.fsw = env->fpus & ~(7 << 11);
676 fpu.fsw |= (env->fpstt & 7) << 11;
677 fpu.fcw = env->fpuc;
678 for (i = 0; i < 8; ++i)
679 fpu.ftwx |= (!env->fptags[i]) << i;
680 memcpy(fpu.fpr, env->fpregs, sizeof env->fpregs);
681 memcpy(fpu.xmm, env->xmm_regs, sizeof env->xmm_regs);
682 fpu.mxcsr = env->mxcsr;
683
684 return kvm_vcpu_ioctl(env, KVM_SET_FPU, &fpu);
685}
686
f1665b21
SY		 687#ifdef KVM_CAP_XSAVE
688#define XSAVE_CWD_RIP 2
689#define XSAVE_CWD_RDP 4
690#define XSAVE_MXCSR 6
691#define XSAVE_ST_SPACE 8
692#define XSAVE_XMM_SPACE 40
693#define XSAVE_XSTATE_BV 128
694#define XSAVE_YMMH_SPACE 144
695#endif
696
697static int kvm_put_xsave(CPUState *env)
698{
699#ifdef KVM_CAP_XSAVE
0f53994f 700 int i, r;
f1665b21
SY		 701 struct kvm_xsave* xsave;
702 uint16_t cwd, swd, twd, fop;
703
704 if (!kvm_has_xsave())
705 return kvm_put_fpu(env);
706
707 xsave = qemu_memalign(4096, sizeof(struct kvm_xsave));
708 memset(xsave, 0, sizeof(struct kvm_xsave));
709 cwd = swd = twd = fop = 0;
710 swd = env->fpus & ~(7 << 11);
711 swd |= (env->fpstt & 7) << 11;
712 cwd = env->fpuc;
713 for (i = 0; i < 8; ++i)
714 twd |= (!env->fptags[i]) << i;
715 xsave->region[0] = (uint32_t)(swd << 16) + cwd;
716 xsave->region[1] = (uint32_t)(fop << 16) + twd;
717 memcpy(&xsave->region[XSAVE_ST_SPACE], env->fpregs,
718 sizeof env->fpregs);
719 memcpy(&xsave->region[XSAVE_XMM_SPACE], env->xmm_regs,
720 sizeof env->xmm_regs);
721 xsave->region[XSAVE_MXCSR] = env->mxcsr;
722 *(uint64_t *)&xsave->region[XSAVE_XSTATE_BV] = env->xstate_bv;
723 memcpy(&xsave->region[XSAVE_YMMH_SPACE], env->ymmh_regs,
724 sizeof env->ymmh_regs);
0f53994f
MT		 725 r = kvm_vcpu_ioctl(env, KVM_SET_XSAVE, xsave);
726 qemu_free(xsave);
727 return r;
f1665b21
SY		 728#else
729 return kvm_put_fpu(env);
730#endif
731}
732
733static int kvm_put_xcrs(CPUState *env)
734{
735#ifdef KVM_CAP_XCRS
736 struct kvm_xcrs xcrs;
737
738 if (!kvm_has_xcrs())
739 return 0;
740
741 xcrs.nr_xcrs = 1;
742 xcrs.flags = 0;
743 xcrs.xcrs[0].xcr = 0;
744 xcrs.xcrs[0].value = env->xcr0;
745 return kvm_vcpu_ioctl(env, KVM_SET_XCRS, &xcrs);
746#else
747 return 0;
748#endif
749}
750
05330448
AL		 751static int kvm_put_sregs(CPUState *env)
752{
753 struct kvm_sregs sregs;
754
0e607a80
JK		 755 memset(sregs.interrupt_bitmap, 0, sizeof(sregs.interrupt_bitmap));
756 if (env->interrupt_injected >= 0) {
757 sregs.interrupt_bitmap[env->interrupt_injected / 64] |=
758 (uint64_t)1 << (env->interrupt_injected % 64);
759 }
05330448
AL		 760
761 if ((env->eflags & VM_MASK)) {
762 set_v8086_seg(&sregs.cs, &env->segs[R_CS]);
763 set_v8086_seg(&sregs.ds, &env->segs[R_DS]);
764 set_v8086_seg(&sregs.es, &env->segs[R_ES]);
765 set_v8086_seg(&sregs.fs, &env->segs[R_FS]);
766 set_v8086_seg(&sregs.gs, &env->segs[R_GS]);
767 set_v8086_seg(&sregs.ss, &env->segs[R_SS]);
768 } else {
769 set_seg(&sregs.cs, &env->segs[R_CS]);
770 set_seg(&sregs.ds, &env->segs[R_DS]);
771 set_seg(&sregs.es, &env->segs[R_ES]);
772 set_seg(&sregs.fs, &env->segs[R_FS]);
773 set_seg(&sregs.gs, &env->segs[R_GS]);
774 set_seg(&sregs.ss, &env->segs[R_SS]);
775
776 if (env->cr[0] & CR0_PE_MASK) {
777 /* force ss cpl to cs cpl */
778 sregs.ss.selector = (sregs.ss.selector & ~3) |
779 (sregs.cs.selector & 3);
780 sregs.ss.dpl = sregs.ss.selector & 3;
781 }
782 }
783
784 set_seg(&sregs.tr, &env->tr);
785 set_seg(&sregs.ldt, &env->ldt);
786
787 sregs.idt.limit = env->idt.limit;
788 sregs.idt.base = env->idt.base;
789 sregs.gdt.limit = env->gdt.limit;
790 sregs.gdt.base = env->gdt.base;
791
792 sregs.cr0 = env->cr[0];
793 sregs.cr2 = env->cr[2];
794 sregs.cr3 = env->cr[3];
795 sregs.cr4 = env->cr[4];
796
4a942cea
BS		 797 sregs.cr8 = cpu_get_apic_tpr(env->apic_state);
798 sregs.apic_base = cpu_get_apic_base(env->apic_state);
05330448
AL		 799
800 sregs.efer = env->efer;
801
802 return kvm_vcpu_ioctl(env, KVM_SET_SREGS, &sregs);
803}
804
805static void kvm_msr_entry_set(struct kvm_msr_entry *entry,
806 uint32_t index, uint64_t value)
807{
808 entry->index = index;
809 entry->data = value;
810}
811
ea643051 812static int kvm_put_msrs(CPUState *env, int level)
05330448
AL		 813{
814 struct {
815 struct kvm_msrs info;
816 struct kvm_msr_entry entries[100];
817 } msr_data;
818 struct kvm_msr_entry *msrs = msr_data.entries;
d8da8574 819 int n = 0;
05330448
AL		 820
821 kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_CS, env->sysenter_cs);
822 kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_ESP, env->sysenter_esp);
823 kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_EIP, env->sysenter_eip);
824 if (kvm_has_msr_star(env))
825 kvm_msr_entry_set(&msrs[n++], MSR_STAR, env->star);
75b10c43
MT		 826 if (kvm_has_msr_hsave_pa(env))
827 kvm_msr_entry_set(&msrs[n++], MSR_VM_HSAVE_PA, env->vm_hsave);
05330448 828#ifdef TARGET_X86_64
25d2e361
MT		 829 if (lm_capable_kernel) {
830 kvm_msr_entry_set(&msrs[n++], MSR_CSTAR, env->cstar);
831 kvm_msr_entry_set(&msrs[n++], MSR_KERNELGSBASE, env->kernelgsbase);
832 kvm_msr_entry_set(&msrs[n++], MSR_FMASK, env->fmask);
833 kvm_msr_entry_set(&msrs[n++], MSR_LSTAR, env->lstar);
834 }
05330448 835#endif
ea643051 836 if (level == KVM_PUT_FULL_STATE) {
384331a6
MT		 837 /*
838 * KVM is yet unable to synchronize TSC values of multiple VCPUs on
839 * writeback. Until this is fixed, we only write the offset to SMP
840 * guests after migration, desynchronizing the VCPUs, but avoiding
841 * huge jump-backs that would occur without any writeback at all.
842 */
843 if (smp_cpus == 1 || env->tsc != 0) {
844 kvm_msr_entry_set(&msrs[n++], MSR_IA32_TSC, env->tsc);
845 }
ea643051
JK		 846 kvm_msr_entry_set(&msrs[n++], MSR_KVM_SYSTEM_TIME,
847 env->system_time_msr);
848 kvm_msr_entry_set(&msrs[n++], MSR_KVM_WALL_CLOCK, env->wall_clock_msr);
f6584ee2
GN		 849#ifdef KVM_CAP_ASYNC_PF
850 kvm_msr_entry_set(&msrs[n++], MSR_KVM_ASYNC_PF_EN, env->async_pf_en_msr);
851#endif
ea643051 852 }
57780495
MT		 853#ifdef KVM_CAP_MCE
854 if (env->mcg_cap) {
d8da8574 855 int i;
57780495
MT		 856 if (level == KVM_PUT_RESET_STATE)
857 kvm_msr_entry_set(&msrs[n++], MSR_MCG_STATUS, env->mcg_status);
858 else if (level == KVM_PUT_FULL_STATE) {
859 kvm_msr_entry_set(&msrs[n++], MSR_MCG_STATUS, env->mcg_status);
860 kvm_msr_entry_set(&msrs[n++], MSR_MCG_CTL, env->mcg_ctl);
861 for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++)
862 kvm_msr_entry_set(&msrs[n++], MSR_MC0_CTL + i, env->mce_banks[i]);
863 }
864 }
865#endif
1a03675d 866
05330448
AL		 867 msr_data.info.nmsrs = n;
868
869 return kvm_vcpu_ioctl(env, KVM_SET_MSRS, &msr_data);
870
871}
872
873
874static int kvm_get_fpu(CPUState *env)
875{
876 struct kvm_fpu fpu;
877 int i, ret;
878
879 ret = kvm_vcpu_ioctl(env, KVM_GET_FPU, &fpu);
880 if (ret < 0)
881 return ret;
882
883 env->fpstt = (fpu.fsw >> 11) & 7;
884 env->fpus = fpu.fsw;
885 env->fpuc = fpu.fcw;
886 for (i = 0; i < 8; ++i)
887 env->fptags[i] = !((fpu.ftwx >> i) & 1);
888 memcpy(env->fpregs, fpu.fpr, sizeof env->fpregs);
889 memcpy(env->xmm_regs, fpu.xmm, sizeof env->xmm_regs);
890 env->mxcsr = fpu.mxcsr;
891
892 return 0;
893}
894
f1665b21
SY		 895static int kvm_get_xsave(CPUState *env)
896{
897#ifdef KVM_CAP_XSAVE
898 struct kvm_xsave* xsave;
899 int ret, i;
900 uint16_t cwd, swd, twd, fop;
901
902 if (!kvm_has_xsave())
903 return kvm_get_fpu(env);
904
905 xsave = qemu_memalign(4096, sizeof(struct kvm_xsave));
906 ret = kvm_vcpu_ioctl(env, KVM_GET_XSAVE, xsave);
0f53994f
MT		 907 if (ret < 0) {
908 qemu_free(xsave);
f1665b21 909 return ret;
0f53994f 910 }
f1665b21
SY		 911
912 cwd = (uint16_t)xsave->region[0];
913 swd = (uint16_t)(xsave->region[0] >> 16);
914 twd = (uint16_t)xsave->region[1];
915 fop = (uint16_t)(xsave->region[1] >> 16);
916 env->fpstt = (swd >> 11) & 7;
917 env->fpus = swd;
918 env->fpuc = cwd;
919 for (i = 0; i < 8; ++i)
920 env->fptags[i] = !((twd >> i) & 1);
921 env->mxcsr = xsave->region[XSAVE_MXCSR];
922 memcpy(env->fpregs, &xsave->region[XSAVE_ST_SPACE],
923 sizeof env->fpregs);
924 memcpy(env->xmm_regs, &xsave->region[XSAVE_XMM_SPACE],
925 sizeof env->xmm_regs);
926 env->xstate_bv = *(uint64_t *)&xsave->region[XSAVE_XSTATE_BV];
927 memcpy(env->ymmh_regs, &xsave->region[XSAVE_YMMH_SPACE],
928 sizeof env->ymmh_regs);
0f53994f 929 qemu_free(xsave);
f1665b21
SY		 930 return 0;
931#else
932 return kvm_get_fpu(env);
933#endif
934}
935
936static int kvm_get_xcrs(CPUState *env)
937{
938#ifdef KVM_CAP_XCRS
939 int i, ret;
940 struct kvm_xcrs xcrs;
941
942 if (!kvm_has_xcrs())
943 return 0;
944
945 ret = kvm_vcpu_ioctl(env, KVM_GET_XCRS, &xcrs);
946 if (ret < 0)
947 return ret;
948
949 for (i = 0; i < xcrs.nr_xcrs; i++)
950 /* Only support xcr0 now */
951 if (xcrs.xcrs[0].xcr == 0) {
952 env->xcr0 = xcrs.xcrs[0].value;
953 break;
954 }
955 return 0;
956#else
957 return 0;
958#endif
959}
960
05330448
AL		 961static int kvm_get_sregs(CPUState *env)
962{
963 struct kvm_sregs sregs;
964 uint32_t hflags;
0e607a80 965 int bit, i, ret;
05330448
AL		 966
967 ret = kvm_vcpu_ioctl(env, KVM_GET_SREGS, &sregs);
968 if (ret < 0)
969 return ret;
970
0e607a80
JK		 971 /* There can only be one pending IRQ set in the bitmap at a time, so try
972 to find it and save its number instead (-1 for none). */
973 env->interrupt_injected = -1;
974 for (i = 0; i < ARRAY_SIZE(sregs.interrupt_bitmap); i++) {
975 if (sregs.interrupt_bitmap[i]) {
976 bit = ctz64(sregs.interrupt_bitmap[i]);
977 env->interrupt_injected = i * 64 + bit;
978 break;
979 }
980 }
05330448
AL		 981
982 get_seg(&env->segs[R_CS], &sregs.cs);
983 get_seg(&env->segs[R_DS], &sregs.ds);
984 get_seg(&env->segs[R_ES], &sregs.es);
985 get_seg(&env->segs[R_FS], &sregs.fs);
986 get_seg(&env->segs[R_GS], &sregs.gs);
987 get_seg(&env->segs[R_SS], &sregs.ss);
988
989 get_seg(&env->tr, &sregs.tr);
990 get_seg(&env->ldt, &sregs.ldt);
991
992 env->idt.limit = sregs.idt.limit;
993 env->idt.base = sregs.idt.base;
994 env->gdt.limit = sregs.gdt.limit;
995 env->gdt.base = sregs.gdt.base;
996
997 env->cr[0] = sregs.cr0;
998 env->cr[2] = sregs.cr2;
999 env->cr[3] = sregs.cr3;
1000 env->cr[4] = sregs.cr4;
1001
4a942cea 1002 cpu_set_apic_base(env->apic_state, sregs.apic_base);
05330448
AL		 1003
1004 env->efer = sregs.efer;
4a942cea 1005 //cpu_set_apic_tpr(env->apic_state, sregs.cr8);
05330448
AL		 1006
1007#define HFLAG_COPY_MASK ~( \
1008 HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \
1009 HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \
1010 HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \
1011 HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK)
1012
1013
1014
1015 hflags = (env->segs[R_CS].flags >> DESC_DPL_SHIFT) & HF_CPL_MASK;
1016 hflags |= (env->cr[0] & CR0_PE_MASK) << (HF_PE_SHIFT - CR0_PE_SHIFT);
1017 hflags |= (env->cr[0] << (HF_MP_SHIFT - CR0_MP_SHIFT)) &
1018 (HF_MP_MASK | HF_EM_MASK | HF_TS_MASK);
1019 hflags |= (env->eflags & (HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK));
1020 hflags |= (env->cr[4] & CR4_OSFXSR_MASK) <<
1021 (HF_OSFXSR_SHIFT - CR4_OSFXSR_SHIFT);
1022
1023 if (env->efer & MSR_EFER_LMA) {
1024 hflags |= HF_LMA_MASK;
1025 }
1026
1027 if ((hflags & HF_LMA_MASK) && (env->segs[R_CS].flags & DESC_L_MASK)) {
1028 hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK;
1029 } else {
1030 hflags |= (env->segs[R_CS].flags & DESC_B_MASK) >>
1031 (DESC_B_SHIFT - HF_CS32_SHIFT);
1032 hflags |= (env->segs[R_SS].flags & DESC_B_MASK) >>
1033 (DESC_B_SHIFT - HF_SS32_SHIFT);
1034 if (!(env->cr[0] & CR0_PE_MASK) ||
1035 (env->eflags & VM_MASK) ||
1036 !(hflags & HF_CS32_MASK)) {
1037 hflags |= HF_ADDSEG_MASK;
1038 } else {
1039 hflags |= ((env->segs[R_DS].base |
1040 env->segs[R_ES].base |
1041 env->segs[R_SS].base) != 0) <<
1042 HF_ADDSEG_SHIFT;
1043 }
1044 }
1045 env->hflags = (env->hflags & HFLAG_COPY_MASK) | hflags;
05330448
AL		 1046
1047 return 0;
1048}
1049
1050static int kvm_get_msrs(CPUState *env)
1051{
1052 struct {
1053 struct kvm_msrs info;
1054 struct kvm_msr_entry entries[100];
1055 } msr_data;
1056 struct kvm_msr_entry *msrs = msr_data.entries;
1057 int ret, i, n;
1058
1059 n = 0;
1060 msrs[n++].index = MSR_IA32_SYSENTER_CS;
1061 msrs[n++].index = MSR_IA32_SYSENTER_ESP;
1062 msrs[n++].index = MSR_IA32_SYSENTER_EIP;
1063 if (kvm_has_msr_star(env))
1064 msrs[n++].index = MSR_STAR;
75b10c43
MT		 1065 if (kvm_has_msr_hsave_pa(env))
1066 msrs[n++].index = MSR_VM_HSAVE_PA;
05330448
AL		 1067 msrs[n++].index = MSR_IA32_TSC;
1068#ifdef TARGET_X86_64
25d2e361
MT		 1069 if (lm_capable_kernel) {
1070 msrs[n++].index = MSR_CSTAR;
1071 msrs[n++].index = MSR_KERNELGSBASE;
1072 msrs[n++].index = MSR_FMASK;
1073 msrs[n++].index = MSR_LSTAR;
1074 }
05330448 1075#endif
1a03675d
GC		 1076 msrs[n++].index = MSR_KVM_SYSTEM_TIME;
1077 msrs[n++].index = MSR_KVM_WALL_CLOCK;
f6584ee2
GN		 1078#ifdef KVM_CAP_ASYNC_PF
1079 msrs[n++].index = MSR_KVM_ASYNC_PF_EN;
1080#endif
1a03675d 1081
57780495
MT		 1082#ifdef KVM_CAP_MCE
1083 if (env->mcg_cap) {
1084 msrs[n++].index = MSR_MCG_STATUS;
1085 msrs[n++].index = MSR_MCG_CTL;
1086 for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++)
1087 msrs[n++].index = MSR_MC0_CTL + i;
1088 }
1089#endif
1090
05330448
AL		 1091 msr_data.info.nmsrs = n;
1092 ret = kvm_vcpu_ioctl(env, KVM_GET_MSRS, &msr_data);
1093 if (ret < 0)
1094 return ret;
1095
1096 for (i = 0; i < ret; i++) {
1097 switch (msrs[i].index) {
1098 case MSR_IA32_SYSENTER_CS:
1099 env->sysenter_cs = msrs[i].data;
1100 break;
1101 case MSR_IA32_SYSENTER_ESP:
1102 env->sysenter_esp = msrs[i].data;
1103 break;
1104 case MSR_IA32_SYSENTER_EIP:
1105 env->sysenter_eip = msrs[i].data;
1106 break;
1107 case MSR_STAR:
1108 env->star = msrs[i].data;
1109 break;
1110#ifdef TARGET_X86_64
1111 case MSR_CSTAR:
1112 env->cstar = msrs[i].data;
1113 break;
1114 case MSR_KERNELGSBASE:
1115 env->kernelgsbase = msrs[i].data;
1116 break;
1117 case MSR_FMASK:
1118 env->fmask = msrs[i].data;
1119 break;
1120 case MSR_LSTAR:
1121 env->lstar = msrs[i].data;
1122 break;
1123#endif
1124 case MSR_IA32_TSC:
1125 env->tsc = msrs[i].data;
1126 break;
aa851e36
MT		 1127 case MSR_VM_HSAVE_PA:
1128 env->vm_hsave = msrs[i].data;
1129 break;
1a03675d
GC		 1130 case MSR_KVM_SYSTEM_TIME:
1131 env->system_time_msr = msrs[i].data;
1132 break;
1133 case MSR_KVM_WALL_CLOCK:
1134 env->wall_clock_msr = msrs[i].data;
1135 break;
57780495
MT		 1136#ifdef KVM_CAP_MCE
1137 case MSR_MCG_STATUS:
1138 env->mcg_status = msrs[i].data;
1139 break;
1140 case MSR_MCG_CTL:
1141 env->mcg_ctl = msrs[i].data;
1142 break;
1143#endif
1144 default:
1145#ifdef KVM_CAP_MCE
1146 if (msrs[i].index >= MSR_MC0_CTL &&
1147 msrs[i].index < MSR_MC0_CTL + (env->mcg_cap & 0xff) * 4) {
1148 env->mce_banks[msrs[i].index - MSR_MC0_CTL] = msrs[i].data;
57780495
MT		 1149 }
1150#endif
d8da8574 1151 break;
f6584ee2
GN		 1152#ifdef KVM_CAP_ASYNC_PF
1153 case MSR_KVM_ASYNC_PF_EN:
1154 env->async_pf_en_msr = msrs[i].data;
1155 break;
1156#endif
05330448
AL		 1157 }
1158 }
1159
1160 return 0;
1161}
1162
9bdbe550
HB		 1163static int kvm_put_mp_state(CPUState *env)
1164{
1165 struct kvm_mp_state mp_state = { .mp_state = env->mp_state };
1166
1167 return kvm_vcpu_ioctl(env, KVM_SET_MP_STATE, &mp_state);
1168}
1169
1170static int kvm_get_mp_state(CPUState *env)
1171{
1172 struct kvm_mp_state mp_state;
1173 int ret;
1174
1175 ret = kvm_vcpu_ioctl(env, KVM_GET_MP_STATE, &mp_state);
1176 if (ret < 0) {
1177 return ret;
1178 }
1179 env->mp_state = mp_state.mp_state;
1180 return 0;
1181}
1182
ea643051 1183static int kvm_put_vcpu_events(CPUState *env, int level)
a0fb002c
JK		 1184{
1185#ifdef KVM_CAP_VCPU_EVENTS
1186 struct kvm_vcpu_events events;
1187
1188 if (!kvm_has_vcpu_events()) {
1189 return 0;
1190 }
1191
31827373
JK		 1192 events.exception.injected = (env->exception_injected >= 0);
1193 events.exception.nr = env->exception_injected;
a0fb002c
JK		 1194 events.exception.has_error_code = env->has_error_code;
1195 events.exception.error_code = env->error_code;
1196
1197 events.interrupt.injected = (env->interrupt_injected >= 0);
1198 events.interrupt.nr = env->interrupt_injected;
1199 events.interrupt.soft = env->soft_interrupt;
1200
1201 events.nmi.injected = env->nmi_injected;
1202 events.nmi.pending = env->nmi_pending;
1203 events.nmi.masked = !!(env->hflags2 & HF2_NMI_MASK);
1204
1205 events.sipi_vector = env->sipi_vector;
1206
ea643051
JK		 1207 events.flags = 0;
1208 if (level >= KVM_PUT_RESET_STATE) {
1209 events.flags |=
1210 KVM_VCPUEVENT_VALID_NMI_PENDING | KVM_VCPUEVENT_VALID_SIPI_VECTOR;
1211 }
aee028b9 1212
a0fb002c
JK		 1213 return kvm_vcpu_ioctl(env, KVM_SET_VCPU_EVENTS, &events);
1214#else
1215 return 0;
1216#endif
1217}
1218
1219static int kvm_get_vcpu_events(CPUState *env)
1220{
1221#ifdef KVM_CAP_VCPU_EVENTS
1222 struct kvm_vcpu_events events;
1223 int ret;
1224
1225 if (!kvm_has_vcpu_events()) {
1226 return 0;
1227 }
1228
1229 ret = kvm_vcpu_ioctl(env, KVM_GET_VCPU_EVENTS, &events);
1230 if (ret < 0) {
1231 return ret;
1232 }
31827373 1233 env->exception_injected =
a0fb002c
JK		 1234 events.exception.injected ? events.exception.nr : -1;
1235 env->has_error_code = events.exception.has_error_code;
1236 env->error_code = events.exception.error_code;
1237
1238 env->interrupt_injected =
1239 events.interrupt.injected ? events.interrupt.nr : -1;
1240 env->soft_interrupt = events.interrupt.soft;
1241
1242 env->nmi_injected = events.nmi.injected;
1243 env->nmi_pending = events.nmi.pending;
1244 if (events.nmi.masked) {
1245 env->hflags2 |= HF2_NMI_MASK;
1246 } else {
1247 env->hflags2 &= ~HF2_NMI_MASK;
1248 }
1249
1250 env->sipi_vector = events.sipi_vector;
1251#endif
1252
1253 return 0;
1254}
1255
b0b1d690
JK		 1256static int kvm_guest_debug_workarounds(CPUState *env)
1257{
1258 int ret = 0;
1259#ifdef KVM_CAP_SET_GUEST_DEBUG
1260 unsigned long reinject_trap = 0;
1261
1262 if (!kvm_has_vcpu_events()) {
1263 if (env->exception_injected == 1) {
1264 reinject_trap = KVM_GUESTDBG_INJECT_DB;
1265 } else if (env->exception_injected == 3) {
1266 reinject_trap = KVM_GUESTDBG_INJECT_BP;
1267 }
1268 env->exception_injected = -1;
1269 }
1270
1271 /*
1272 * Kernels before KVM_CAP_X86_ROBUST_SINGLESTEP overwrote flags.TF
1273 * injected via SET_GUEST_DEBUG while updating GP regs. Work around this
1274 * by updating the debug state once again if single-stepping is on.
1275 * Another reason to call kvm_update_guest_debug here is a pending debug
1276 * trap raise by the guest. On kernels without SET_VCPU_EVENTS we have to
1277 * reinject them via SET_GUEST_DEBUG.
1278 */
1279 if (reinject_trap ||
1280 (!kvm_has_robust_singlestep() && env->singlestep_enabled)) {
1281 ret = kvm_update_guest_debug(env, reinject_trap);
1282 }
1283#endif /* KVM_CAP_SET_GUEST_DEBUG */
1284 return ret;
1285}
1286
ff44f1a3
JK		 1287static int kvm_put_debugregs(CPUState *env)
1288{
1289#ifdef KVM_CAP_DEBUGREGS
1290 struct kvm_debugregs dbgregs;
1291 int i;
1292
1293 if (!kvm_has_debugregs()) {
1294 return 0;
1295 }
1296
1297 for (i = 0; i < 4; i++) {
1298 dbgregs.db[i] = env->dr[i];
1299 }
1300 dbgregs.dr6 = env->dr[6];
1301 dbgregs.dr7 = env->dr[7];
1302 dbgregs.flags = 0;
1303
1304 return kvm_vcpu_ioctl(env, KVM_SET_DEBUGREGS, &dbgregs);
1305#else
1306 return 0;
1307#endif
1308}
1309
1310static int kvm_get_debugregs(CPUState *env)
1311{
1312#ifdef KVM_CAP_DEBUGREGS
1313 struct kvm_debugregs dbgregs;
1314 int i, ret;
1315
1316 if (!kvm_has_debugregs()) {
1317 return 0;
1318 }
1319
1320 ret = kvm_vcpu_ioctl(env, KVM_GET_DEBUGREGS, &dbgregs);
1321 if (ret < 0) {
1322 return ret;
1323 }
1324 for (i = 0; i < 4; i++) {
1325 env->dr[i] = dbgregs.db[i];
1326 }
1327 env->dr[4] = env->dr[6] = dbgregs.dr6;
1328 env->dr[5] = env->dr[7] = dbgregs.dr7;
1329#endif
1330
1331 return 0;
1332}
1333
ea375f9a 1334int kvm_arch_put_registers(CPUState *env, int level)
05330448
AL		 1335{
1336 int ret;
1337
dbaa07c4
JK		 1338 assert(cpu_is_stopped(env) || qemu_cpu_self(env));
1339
05330448
AL		 1340 ret = kvm_getput_regs(env, 1);
1341 if (ret < 0)
1342 return ret;
1343
f1665b21
SY		 1344 ret = kvm_put_xsave(env);
1345 if (ret < 0)
1346 return ret;
1347
1348 ret = kvm_put_xcrs(env);
05330448
AL		 1349 if (ret < 0)
1350 return ret;
1351
1352 ret = kvm_put_sregs(env);
1353 if (ret < 0)
1354 return ret;
1355
ea643051 1356 ret = kvm_put_msrs(env, level);
05330448
AL		 1357 if (ret < 0)
1358 return ret;
1359
ea643051
JK		 1360 if (level >= KVM_PUT_RESET_STATE) {
1361 ret = kvm_put_mp_state(env);
1362 if (ret < 0)
1363 return ret;
1364 }
f8d926e9 1365
ea643051 1366 ret = kvm_put_vcpu_events(env, level);
a0fb002c
JK		 1367 if (ret < 0)
1368 return ret;
1369
b0b1d690
JK		 1370 /* must be last */
1371 ret = kvm_guest_debug_workarounds(env);
1372 if (ret < 0)
1373 return ret;
1374
ff44f1a3
JK		 1375 ret = kvm_put_debugregs(env);
1376 if (ret < 0)
1377 return ret;
1378
05330448
AL		 1379 return 0;
1380}
1381
1382int kvm_arch_get_registers(CPUState *env)
1383{
1384 int ret;
1385
dbaa07c4
JK		 1386 assert(cpu_is_stopped(env) || qemu_cpu_self(env));
1387
05330448
AL		 1388 ret = kvm_getput_regs(env, 0);
1389 if (ret < 0)
1390 return ret;
1391
f1665b21
SY		 1392 ret = kvm_get_xsave(env);
1393 if (ret < 0)
1394 return ret;
1395
1396 ret = kvm_get_xcrs(env);
05330448
AL		 1397 if (ret < 0)
1398 return ret;
1399
1400 ret = kvm_get_sregs(env);
1401 if (ret < 0)
1402 return ret;
1403
1404 ret = kvm_get_msrs(env);
1405 if (ret < 0)
1406 return ret;
1407
5a2e3c2e
JK		 1408 ret = kvm_get_mp_state(env);
1409 if (ret < 0)
1410 return ret;
1411
a0fb002c
JK		 1412 ret = kvm_get_vcpu_events(env);
1413 if (ret < 0)
1414 return ret;
1415
ff44f1a3
JK		 1416 ret = kvm_get_debugregs(env);
1417 if (ret < 0)
1418 return ret;
1419
05330448
AL		 1420 return 0;
1421}
1422
1423int kvm_arch_pre_run(CPUState *env, struct kvm_run *run)
1424{
276ce815
LJ		 1425 /* Inject NMI */
1426 if (env->interrupt_request & CPU_INTERRUPT_NMI) {
1427 env->interrupt_request &= ~CPU_INTERRUPT_NMI;
1428 DPRINTF("injected NMI\n");
1429 kvm_vcpu_ioctl(env, KVM_NMI);
1430 }
1431
05330448
AL		 1432 /* Try to inject an interrupt if the guest can accept it */
1433 if (run->ready_for_interrupt_injection &&
1434 (env->interrupt_request & CPU_INTERRUPT_HARD) &&
1435 (env->eflags & IF_MASK)) {
1436 int irq;
1437
1438 env->interrupt_request &= ~CPU_INTERRUPT_HARD;
1439 irq = cpu_get_pic_interrupt(env);
1440 if (irq >= 0) {
1441 struct kvm_interrupt intr;
1442 intr.irq = irq;
1443 /* FIXME: errors */
8c0d577e 1444 DPRINTF("injected interrupt %d\n", irq);
05330448
AL		 1445 kvm_vcpu_ioctl(env, KVM_INTERRUPT, &intr);
1446 }
1447 }
1448
1449 /* If we have an interrupt but the guest is not ready to receive an
1450 * interrupt, request an interrupt window exit. This will
1451 * cause a return to userspace as soon as the guest is ready to
1452 * receive interrupts. */
1453 if ((env->interrupt_request & CPU_INTERRUPT_HARD))
1454 run->request_interrupt_window = 1;
1455 else
1456 run->request_interrupt_window = 0;
1457
8c0d577e 1458 DPRINTF("setting tpr\n");
4a942cea 1459 run->cr8 = cpu_get_apic_tpr(env->apic_state);
05330448
AL		 1460
1461 return 0;
1462}
1463
1464int kvm_arch_post_run(CPUState *env, struct kvm_run *run)
1465{
1466 if (run->if_flag)
1467 env->eflags |= IF_MASK;
1468 else
1469 env->eflags &= ~IF_MASK;
1470
4a942cea
BS		 1471 cpu_set_apic_tpr(env->apic_state, run->cr8);
1472 cpu_set_apic_base(env->apic_state, run->apic_base);
05330448
AL		 1473
1474 return 0;
1475}
1476
0af691d7
MT		 1477int kvm_arch_process_irqchip_events(CPUState *env)
1478{
1479 if (env->interrupt_request & CPU_INTERRUPT_INIT) {
1480 kvm_cpu_synchronize_state(env);
1481 do_cpu_init(env);
1482 env->exception_index = EXCP_HALTED;
1483 }
1484
1485 if (env->interrupt_request & CPU_INTERRUPT_SIPI) {
1486 kvm_cpu_synchronize_state(env);
1487 do_cpu_sipi(env);
1488 }
1489
1490 return env->halted;
1491}
1492
05330448
AL		 1493static int kvm_handle_halt(CPUState *env)
1494{
1495 if (!((env->interrupt_request & CPU_INTERRUPT_HARD) &&
1496 (env->eflags & IF_MASK)) &&
1497 !(env->interrupt_request & CPU_INTERRUPT_NMI)) {
1498 env->halted = 1;
1499 env->exception_index = EXCP_HLT;
1500 return 0;
1501 }
1502
1503 return 1;
1504}
1505
1506int kvm_arch_handle_exit(CPUState *env, struct kvm_run *run)
1507{
1508 int ret = 0;
1509
1510 switch (run->exit_reason) {
1511 case KVM_EXIT_HLT:
8c0d577e 1512 DPRINTF("handle_hlt\n");
05330448
AL		 1513 ret = kvm_handle_halt(env);
1514 break;
1515 }
1516
1517 return ret;
1518}
e22a25c9
AL		 1519
1520#ifdef KVM_CAP_SET_GUEST_DEBUG
e22a25c9
AL		 1521int kvm_arch_insert_sw_breakpoint(CPUState *env, struct kvm_sw_breakpoint *bp)
1522{
38972938 1523 static const uint8_t int3 = 0xcc;
64bf3f4e 1524
e22a25c9 1525 if (cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&bp->saved_insn, 1, 0) ||
64bf3f4e 1526 cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&int3, 1, 1))
e22a25c9
AL		 1527 return -EINVAL;
1528 return 0;
1529}
1530
1531int kvm_arch_remove_sw_breakpoint(CPUState *env, struct kvm_sw_breakpoint *bp)
1532{
1533 uint8_t int3;
1534
1535 if (cpu_memory_rw_debug(env, bp->pc, &int3, 1, 0) || int3 != 0xcc ||
64bf3f4e 1536 cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&bp->saved_insn, 1, 1))
e22a25c9
AL		 1537 return -EINVAL;
1538 return 0;
1539}
1540
1541static struct {
1542 target_ulong addr;
1543 int len;
1544 int type;
1545} hw_breakpoint[4];
1546
1547static int nb_hw_breakpoint;
1548
1549static int find_hw_breakpoint(target_ulong addr, int len, int type)
1550{
1551 int n;
1552
1553 for (n = 0; n < nb_hw_breakpoint; n++)
1554 if (hw_breakpoint[n].addr == addr && hw_breakpoint[n].type == type &&
1555 (hw_breakpoint[n].len == len || len == -1))
1556 return n;
1557 return -1;
1558}
1559
1560int kvm_arch_insert_hw_breakpoint(target_ulong addr,
1561 target_ulong len, int type)
1562{
1563 switch (type) {
1564 case GDB_BREAKPOINT_HW:
1565 len = 1;
1566 break;
1567 case GDB_WATCHPOINT_WRITE:
1568 case GDB_WATCHPOINT_ACCESS:
1569 switch (len) {
1570 case 1:
1571 break;
1572 case 2:
1573 case 4:
1574 case 8:
1575 if (addr & (len - 1))
1576 return -EINVAL;
1577 break;
1578 default:
1579 return -EINVAL;
1580 }
1581 break;
1582 default:
1583 return -ENOSYS;
1584 }
1585
1586 if (nb_hw_breakpoint == 4)
1587 return -ENOBUFS;
1588
1589 if (find_hw_breakpoint(addr, len, type) >= 0)
1590 return -EEXIST;
1591
1592 hw_breakpoint[nb_hw_breakpoint].addr = addr;
1593 hw_breakpoint[nb_hw_breakpoint].len = len;
1594 hw_breakpoint[nb_hw_breakpoint].type = type;
1595 nb_hw_breakpoint++;
1596
1597 return 0;
1598}
1599
1600int kvm_arch_remove_hw_breakpoint(target_ulong addr,
1601 target_ulong len, int type)
1602{
1603 int n;
1604
1605 n = find_hw_breakpoint(addr, (type == GDB_BREAKPOINT_HW) ? 1 : len, type);
1606 if (n < 0)
1607 return -ENOENT;
1608
1609 nb_hw_breakpoint--;
1610 hw_breakpoint[n] = hw_breakpoint[nb_hw_breakpoint];
1611
1612 return 0;
1613}
1614
1615void kvm_arch_remove_all_hw_breakpoints(void)
1616{
1617 nb_hw_breakpoint = 0;
1618}
1619
1620static CPUWatchpoint hw_watchpoint;
1621
1622int kvm_arch_debug(struct kvm_debug_exit_arch *arch_info)
1623{
1624 int handle = 0;
1625 int n;
1626
1627 if (arch_info->exception == 1) {
1628 if (arch_info->dr6 & (1 << 14)) {
1629 if (cpu_single_env->singlestep_enabled)
1630 handle = 1;
1631 } else {
1632 for (n = 0; n < 4; n++)
1633 if (arch_info->dr6 & (1 << n))
1634 switch ((arch_info->dr7 >> (16 + n*4)) & 0x3) {
1635 case 0x0:
1636 handle = 1;
1637 break;
1638 case 0x1:
1639 handle = 1;
1640 cpu_single_env->watchpoint_hit = &hw_watchpoint;
1641 hw_watchpoint.vaddr = hw_breakpoint[n].addr;
1642 hw_watchpoint.flags = BP_MEM_WRITE;
1643 break;
1644 case 0x3:
1645 handle = 1;
1646 cpu_single_env->watchpoint_hit = &hw_watchpoint;
1647 hw_watchpoint.vaddr = hw_breakpoint[n].addr;
1648 hw_watchpoint.flags = BP_MEM_ACCESS;
1649 break;
1650 }
1651 }
1652 } else if (kvm_find_sw_breakpoint(cpu_single_env, arch_info->pc))
1653 handle = 1;
1654
b0b1d690
JK		 1655 if (!handle) {
1656 cpu_synchronize_state(cpu_single_env);
1657 assert(cpu_single_env->exception_injected == -1);
1658
1659 cpu_single_env->exception_injected = arch_info->exception;
1660 cpu_single_env->has_error_code = 0;
1661 }
e22a25c9
AL		 1662
1663 return handle;
1664}
1665
1666void kvm_arch_update_guest_debug(CPUState *env, struct kvm_guest_debug *dbg)
1667{
1668 const uint8_t type_code[] = {
1669 [GDB_BREAKPOINT_HW] = 0x0,
1670 [GDB_WATCHPOINT_WRITE] = 0x1,
1671 [GDB_WATCHPOINT_ACCESS] = 0x3
1672 };
1673 const uint8_t len_code[] = {
1674 [1] = 0x0, [2] = 0x1, [4] = 0x3, [8] = 0x2
1675 };
1676 int n;
1677
1678 if (kvm_sw_breakpoints_active(env))
1679 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP;
1680
1681 if (nb_hw_breakpoint > 0) {
1682 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP;
1683 dbg->arch.debugreg[7] = 0x0600;
1684 for (n = 0; n < nb_hw_breakpoint; n++) {
1685 dbg->arch.debugreg[n] = hw_breakpoint[n].addr;
1686 dbg->arch.debugreg[7] |= (2 << (n * 2)) |
1687 (type_code[hw_breakpoint[n].type] << (16 + n*4)) |
1688 (len_code[hw_breakpoint[n].len] << (18 + n*4));
1689 }
1690 }
f1665b21
SY		 1691 /* Legal xcr0 for loading */
1692 env->xcr0 = 1;
e22a25c9
AL		 1693}
1694#endif /* KVM_CAP_SET_GUEST_DEBUG */
4513d923
GN		 1695
1696bool kvm_arch_stop_on_emulation_error(CPUState *env)
1697{
1698 return !(env->cr[0] & CR0_PE_MASK) ||
1699 ((env->segs[R_CS].selector & 3) != 3);
1700}
1701
c0532a76
MT		 1702static void hardware_memory_error(void)
1703{
1704 fprintf(stderr, "Hardware memory error!\n");
1705 exit(1);
1706}
1707
f71ac88f
HS		 1708#ifdef KVM_CAP_MCE
1709static void kvm_mce_broadcast_rest(CPUState *env)
1710{
1711 CPUState *cenv;
f71ac88f
HS		 1712
1713 /* Broadcast MCA signal for processor version 06H_EH and above */
2bd3e04c 1714 if (cpu_x86_support_mca_broadcast(env)) {
f71ac88f
HS		 1715 for (cenv = first_cpu; cenv != NULL; cenv = cenv->next_cpu) {
1716 if (cenv == env) {
1717 continue;
1718 }
1719 kvm_inject_x86_mce(cenv, 1, MCI_STATUS_VAL | MCI_STATUS_UC,
31ce5e0c
JD		 1720 MCG_STATUS_MCIP | MCG_STATUS_RIPV, 0, 0,
1721 ABORT_ON_ERROR);
f71ac88f
HS		 1722 }
1723 }
1724}
e387c338
JD		 1725
1726static void kvm_mce_inj_srar_dataload(CPUState *env, target_phys_addr_t paddr)
1727{
1728 struct kvm_x86_mce mce = {
1729 .bank = 9,
1730 .status = MCI_STATUS_VAL | MCI_STATUS_UC | MCI_STATUS_EN
1731 | MCI_STATUS_MISCV | MCI_STATUS_ADDRV | MCI_STATUS_S
1732 | MCI_STATUS_AR | 0x134,
1733 .mcg_status = MCG_STATUS_MCIP | MCG_STATUS_EIPV,
1734 .addr = paddr,
1735 .misc = (MCM_ADDR_PHYS << 6) | 0xc,
1736 };
1737 int r;
1738
1739 r = kvm_set_mce(env, &mce);
1740 if (r < 0) {
1741 fprintf(stderr, "kvm_set_mce: %s\n", strerror(errno));
1742 abort();
1743 }
1744 kvm_mce_broadcast_rest(env);
1745}
1746
1747static void kvm_mce_inj_srao_memscrub(CPUState *env, target_phys_addr_t paddr)
1748{
1749 struct kvm_x86_mce mce = {
1750 .bank = 9,
1751 .status = MCI_STATUS_VAL | MCI_STATUS_UC | MCI_STATUS_EN
1752 | MCI_STATUS_MISCV | MCI_STATUS_ADDRV | MCI_STATUS_S
1753 | 0xc0,
1754 .mcg_status = MCG_STATUS_MCIP | MCG_STATUS_RIPV,
1755 .addr = paddr,
1756 .misc = (MCM_ADDR_PHYS << 6) | 0xc,
1757 };
1758 int r;
1759
1760 r = kvm_set_mce(env, &mce);
1761 if (r < 0) {
1762 fprintf(stderr, "kvm_set_mce: %s\n", strerror(errno));
1763 abort();
1764 }
1765 kvm_mce_broadcast_rest(env);
1766}
1767
1768static void kvm_mce_inj_srao_memscrub2(CPUState *env, target_phys_addr_t paddr)
1769{
1770 uint64_t status;
1771
1772 status = MCI_STATUS_VAL | MCI_STATUS_UC | MCI_STATUS_EN
1773 | MCI_STATUS_MISCV | MCI_STATUS_ADDRV | MCI_STATUS_S
1774 | 0xc0;
1775 kvm_inject_x86_mce(env, 9, status,
1776 MCG_STATUS_MCIP | MCG_STATUS_RIPV, paddr,
1777 (MCM_ADDR_PHYS << 6) | 0xc, ABORT_ON_ERROR);
1778
1779 kvm_mce_broadcast_rest(env);
1780}
1781
f71ac88f
HS		 1782#endif
1783
c0532a76
MT		 1784int kvm_on_sigbus_vcpu(CPUState *env, int code, void *addr)
1785{
1786#if defined(KVM_CAP_MCE)
c0532a76
MT		 1787 void *vaddr;
1788 ram_addr_t ram_addr;
1789 target_phys_addr_t paddr;
c0532a76
MT		 1790
1791 if ((env->mcg_cap & MCG_SER_P) && addr
1792 && (code == BUS_MCEERR_AR
1793 || code == BUS_MCEERR_AO)) {
c0532a76
MT		 1794 vaddr = (void *)addr;
1795 if (qemu_ram_addr_from_host(vaddr, &ram_addr) ||
1796 !kvm_physical_memory_addr_from_ram(env->kvm_state, ram_addr, &paddr)) {
1797 fprintf(stderr, "Hardware memory error for memory used by "
1798 "QEMU itself instead of guest system!\n");
1799 /* Hope we are lucky for AO MCE */
1800 if (code == BUS_MCEERR_AO) {
1801 return 0;
1802 } else {
1803 hardware_memory_error();
1804 }
1805 }
e387c338
JD		 1806
1807 if (code == BUS_MCEERR_AR) {
1808 /* Fake an Intel architectural Data Load SRAR UCR */
1809 kvm_mce_inj_srar_dataload(env, paddr);
1810 } else {
1811 /*
1812 * If there is an MCE excpetion being processed, ignore
1813 * this SRAO MCE
1814 */
1815 if (!kvm_mce_in_progress(env)) {
1816 /* Fake an Intel architectural Memory scrubbing UCR */
1817 kvm_mce_inj_srao_memscrub(env, paddr);
1818 }
c0532a76
MT		 1819 }
1820 } else
1821#endif
1822 {
1823 if (code == BUS_MCEERR_AO) {
1824 return 0;
1825 } else if (code == BUS_MCEERR_AR) {
1826 hardware_memory_error();
1827 } else {
1828 return 1;
1829 }
1830 }
1831 return 0;
1832}
1833
1834int kvm_on_sigbus(int code, void *addr)
1835{
1836#if defined(KVM_CAP_MCE)
1837 if ((first_cpu->mcg_cap & MCG_SER_P) && addr && code == BUS_MCEERR_AO) {
c0532a76
MT		 1838 void *vaddr;
1839 ram_addr_t ram_addr;
1840 target_phys_addr_t paddr;
c0532a76
MT		 1841
1842 /* Hope we are lucky for AO MCE */
1843 vaddr = addr;
1844 if (qemu_ram_addr_from_host(vaddr, &ram_addr) ||
1845 !kvm_physical_memory_addr_from_ram(first_cpu->kvm_state, ram_addr, &paddr)) {
1846 fprintf(stderr, "Hardware memory error for memory used by "
1847 "QEMU itself instead of guest system!: %p\n", addr);
1848 return 0;
1849 }
e387c338 1850 kvm_mce_inj_srao_memscrub2(first_cpu, paddr);
c0532a76
MT		 1851 } else
1852#endif
1853 {
1854 if (code == BUS_MCEERR_AO) {
1855 return 0;
1856 } else if (code == BUS_MCEERR_AR) {
1857 hardware_memory_error();
1858 } else {
1859 return 1;
1860 }
1861 }
1862 return 0;
1863}
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