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ide save/restore pio/atapi cmd transfer fields and io buffer
[mirror_qemu.git] / target-i386 / kvm.c
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05330448
AL		 1/*
2 * QEMU KVM support
3 *
4 * Copyright (C) 2006-2008 Qumranet Technologies
5 * Copyright IBM, Corp. 2008
6 *
7 * Authors:
8 * Anthony Liguori <aliguori@us.ibm.com>
9 *
10 * This work is licensed under the terms of the GNU GPL, version 2 or later.
11 * See the COPYING file in the top-level directory.
12 *
13 */
14
15#include <sys/types.h>
16#include <sys/ioctl.h>
17#include <sys/mman.h>
18
19#include <linux/kvm.h>
20
21#include "qemu-common.h"
22#include "sysemu.h"
23#include "kvm.h"
24#include "cpu.h"
e22a25c9 25#include "gdbstub.h"
0e607a80 26#include "host-utils.h"
05330448 27
bb0300dc
GN		 28#ifdef CONFIG_KVM_PARA
29#include <linux/kvm_para.h>
30#endif
31//
05330448
AL		 32//#define DEBUG_KVM
33
34#ifdef DEBUG_KVM
35#define dprintf(fmt, ...) \
36 do { fprintf(stderr, fmt, ## __VA_ARGS__); } while (0)
37#else
38#define dprintf(fmt, ...) \
39 do { } while (0)
40#endif
41
1a03675d
GC		 42#define MSR_KVM_WALL_CLOCK 0x11
43#define MSR_KVM_SYSTEM_TIME 0x12
44
b827df58
AK		 45#ifdef KVM_CAP_EXT_CPUID
46
47static struct kvm_cpuid2 *try_get_cpuid(KVMState *s, int max)
48{
49 struct kvm_cpuid2 *cpuid;
50 int r, size;
51
52 size = sizeof(*cpuid) + max * sizeof(*cpuid->entries);
53 cpuid = (struct kvm_cpuid2 *)qemu_mallocz(size);
54 cpuid->nent = max;
55 r = kvm_ioctl(s, KVM_GET_SUPPORTED_CPUID, cpuid);
76ae317f
MM		 56 if (r == 0 && cpuid->nent >= max) {
57 r = -E2BIG;
58 }
b827df58
AK		 59 if (r < 0) {
60 if (r == -E2BIG) {
61 qemu_free(cpuid);
62 return NULL;
63 } else {
64 fprintf(stderr, "KVM_GET_SUPPORTED_CPUID failed: %s\n",
65 strerror(-r));
66 exit(1);
67 }
68 }
69 return cpuid;
70}
71
72uint32_t kvm_arch_get_supported_cpuid(CPUState *env, uint32_t function, int reg)
73{
74 struct kvm_cpuid2 *cpuid;
75 int i, max;
76 uint32_t ret = 0;
77 uint32_t cpuid_1_edx;
78
79 if (!kvm_check_extension(env->kvm_state, KVM_CAP_EXT_CPUID)) {
80 return -1U;
81 }
82
83 max = 1;
84 while ((cpuid = try_get_cpuid(env->kvm_state, max)) == NULL) {
85 max *= 2;
86 }
87
88 for (i = 0; i < cpuid->nent; ++i) {
89 if (cpuid->entries[i].function == function) {
90 switch (reg) {
91 case R_EAX:
92 ret = cpuid->entries[i].eax;
93 break;
94 case R_EBX:
95 ret = cpuid->entries[i].ebx;
96 break;
97 case R_ECX:
98 ret = cpuid->entries[i].ecx;
99 break;
100 case R_EDX:
101 ret = cpuid->entries[i].edx;
19ccb8ea
JK		 102 switch (function) {
103 case 1:
104 /* KVM before 2.6.30 misreports the following features */
105 ret |= CPUID_MTRR | CPUID_PAT | CPUID_MCE | CPUID_MCA;
106 break;
107 case 0x80000001:
b827df58
AK		 108 /* On Intel, kvm returns cpuid according to the Intel spec,
109 * so add missing bits according to the AMD spec:
110 */
111 cpuid_1_edx = kvm_arch_get_supported_cpuid(env, 1, R_EDX);
112 ret |= cpuid_1_edx & 0xdfeff7ff;
19ccb8ea 113 break;
b827df58
AK		 114 }
115 break;
116 }
117 }
118 }
119
120 qemu_free(cpuid);
121
122 return ret;
123}
124
125#else
126
127uint32_t kvm_arch_get_supported_cpuid(CPUState *env, uint32_t function, int reg)
128{
129 return -1U;
130}
131
132#endif
133
6c1f42fe
AP		 134static void kvm_trim_features(uint32_t *features, uint32_t supported)
135{
136 int i;
137 uint32_t mask;
138
139 for (i = 0; i < 32; ++i) {
140 mask = 1U << i;
141 if ((*features & mask) && !(supported & mask)) {
142 *features &= ~mask;
143 }
144 }
145}
146
bb0300dc
GN		 147#ifdef CONFIG_KVM_PARA
148struct kvm_para_features {
149 int cap;
150 int feature;
151} para_features[] = {
152#ifdef KVM_CAP_CLOCKSOURCE
153 { KVM_CAP_CLOCKSOURCE, KVM_FEATURE_CLOCKSOURCE },
154#endif
155#ifdef KVM_CAP_NOP_IO_DELAY
156 { KVM_CAP_NOP_IO_DELAY, KVM_FEATURE_NOP_IO_DELAY },
157#endif
158#ifdef KVM_CAP_PV_MMU
159 { KVM_CAP_PV_MMU, KVM_FEATURE_MMU_OP },
160#endif
161#ifdef KVM_CAP_CR3_CACHE
162 { KVM_CAP_CR3_CACHE, KVM_FEATURE_CR3_CACHE },
163#endif
164 { -1, -1 }
165};
166
167static int get_para_features(CPUState *env)
168{
169 int i, features = 0;
170
171 for (i = 0; i < ARRAY_SIZE(para_features) - 1; i++) {
172 if (kvm_check_extension(env->kvm_state, para_features[i].cap))
173 features |= (1 << para_features[i].feature);
174 }
175
176 return features;
177}
178#endif
179
05330448
AL		 180int kvm_arch_init_vcpu(CPUState *env)
181{
182 struct {
486bd5a2
AL		 183 struct kvm_cpuid2 cpuid;
184 struct kvm_cpuid_entry2 entries[100];
05330448 185 } __attribute__((packed)) cpuid_data;
486bd5a2 186 uint32_t limit, i, j, cpuid_i;
a33609ca 187 uint32_t unused;
bb0300dc
GN		 188 struct kvm_cpuid_entry2 *c;
189#ifdef KVM_CPUID_SIGNATURE
190 uint32_t signature[3];
191#endif
05330448 192
f8d926e9
JK		 193 env->mp_state = KVM_MP_STATE_RUNNABLE;
194
6c1f42fe
AP		 195 kvm_trim_features(&env->cpuid_features,
196 kvm_arch_get_supported_cpuid(env, 1, R_EDX));
6c0d7ee8
AP		 197
198 i = env->cpuid_ext_features & CPUID_EXT_HYPERVISOR;
6c1f42fe
AP		 199 kvm_trim_features(&env->cpuid_ext_features,
200 kvm_arch_get_supported_cpuid(env, 1, R_ECX));
6c0d7ee8
AP		 201 env->cpuid_ext_features |= i;
202
6c1f42fe
AP		 203 kvm_trim_features(&env->cpuid_ext2_features,
204 kvm_arch_get_supported_cpuid(env, 0x80000001, R_EDX));
205 kvm_trim_features(&env->cpuid_ext3_features,
206 kvm_arch_get_supported_cpuid(env, 0x80000001, R_ECX));
207
05330448
AL		 208 cpuid_i = 0;
209
bb0300dc
GN		 210#ifdef CONFIG_KVM_PARA
211 /* Paravirtualization CPUIDs */
212 memcpy(signature, "KVMKVMKVM\0\0\0", 12);
213 c = &cpuid_data.entries[cpuid_i++];
214 memset(c, 0, sizeof(*c));
215 c->function = KVM_CPUID_SIGNATURE;
216 c->eax = 0;
217 c->ebx = signature[0];
218 c->ecx = signature[1];
219 c->edx = signature[2];
220
221 c = &cpuid_data.entries[cpuid_i++];
222 memset(c, 0, sizeof(*c));
223 c->function = KVM_CPUID_FEATURES;
224 c->eax = env->cpuid_kvm_features & get_para_features(env);
225#endif
226
a33609ca 227 cpu_x86_cpuid(env, 0, 0, &limit, &unused, &unused, &unused);
05330448
AL		 228
229 for (i = 0; i <= limit; i++) {
bb0300dc 230 c = &cpuid_data.entries[cpuid_i++];
486bd5a2
AL		 231
232 switch (i) {
a36b1029
AL		 233 case 2: {
234 /* Keep reading function 2 till all the input is received */
235 int times;
236
a36b1029 237 c->function = i;
a33609ca
AL		 238 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC |
239 KVM_CPUID_FLAG_STATE_READ_NEXT;
240 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
241 times = c->eax & 0xff;
a36b1029
AL		 242
243 for (j = 1; j < times; ++j) {
a33609ca 244 c = &cpuid_data.entries[cpuid_i++];
a36b1029 245 c->function = i;
a33609ca
AL		 246 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC;
247 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
a36b1029
AL		 248 }
249 break;
250 }
486bd5a2
AL		 251 case 4:
252 case 0xb:
253 case 0xd:
254 for (j = 0; ; j++) {
486bd5a2
AL		 255 c->function = i;
256 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
257 c->index = j;
a33609ca 258 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
486bd5a2 259
a33609ca 260 if (i == 4 && c->eax == 0)
486bd5a2 261 break;
a33609ca 262 if (i == 0xb && !(c->ecx & 0xff00))
486bd5a2 263 break;
a33609ca 264 if (i == 0xd && c->eax == 0)
486bd5a2 265 break;
a33609ca
AL		 266
267 c = &cpuid_data.entries[cpuid_i++];
486bd5a2
AL		 268 }
269 break;
270 default:
486bd5a2 271 c->function = i;
a33609ca
AL		 272 c->flags = 0;
273 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
486bd5a2
AL		 274 break;
275 }
05330448 276 }
a33609ca 277 cpu_x86_cpuid(env, 0x80000000, 0, &limit, &unused, &unused, &unused);
05330448
AL		 278
279 for (i = 0x80000000; i <= limit; i++) {
bb0300dc 280 c = &cpuid_data.entries[cpuid_i++];
05330448 281
05330448 282 c->function = i;
a33609ca
AL		 283 c->flags = 0;
284 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
05330448
AL		 285 }
286
287 cpuid_data.cpuid.nent = cpuid_i;
288
486bd5a2 289 return kvm_vcpu_ioctl(env, KVM_SET_CPUID2, &cpuid_data);
05330448
AL		 290}
291
caa5af0f
JK		 292void kvm_arch_reset_vcpu(CPUState *env)
293{
e73223a5 294 env->exception_injected = -1;
0e607a80 295 env->interrupt_injected = -1;
a0fb002c
JK		 296 env->nmi_injected = 0;
297 env->nmi_pending = 0;
caa5af0f
JK		 298}
299
05330448
AL		 300static int kvm_has_msr_star(CPUState *env)
301{
302 static int has_msr_star;
303 int ret;
304
305 /* first time */
306 if (has_msr_star == 0) {
307 struct kvm_msr_list msr_list, *kvm_msr_list;
308
309 has_msr_star = -1;
310
311 /* Obtain MSR list from KVM. These are the MSRs that we must
312 * save/restore */
4c9f7372 313 msr_list.nmsrs = 0;
05330448 314 ret = kvm_ioctl(env->kvm_state, KVM_GET_MSR_INDEX_LIST, &msr_list);
6fb6d245 315 if (ret < 0 && ret != -E2BIG) {
05330448 316 return 0;
6fb6d245 317 }
d9db889f
JK		 318 /* Old kernel modules had a bug and could write beyond the provided
319 memory. Allocate at least a safe amount of 1K. */
320 kvm_msr_list = qemu_mallocz(MAX(1024, sizeof(msr_list) +
321 msr_list.nmsrs *
322 sizeof(msr_list.indices[0])));
05330448 323
55308450 324 kvm_msr_list->nmsrs = msr_list.nmsrs;
05330448
AL		 325 ret = kvm_ioctl(env->kvm_state, KVM_GET_MSR_INDEX_LIST, kvm_msr_list);
326 if (ret >= 0) {
327 int i;
328
329 for (i = 0; i < kvm_msr_list->nmsrs; i++) {
330 if (kvm_msr_list->indices[i] == MSR_STAR) {
331 has_msr_star = 1;
332 break;
333 }
334 }
335 }
336
337 free(kvm_msr_list);
338 }
339
340 if (has_msr_star == 1)
341 return 1;
342 return 0;
343}
344
345int kvm_arch_init(KVMState *s, int smp_cpus)
346{
347 int ret;
348
349 /* create vm86 tss. KVM uses vm86 mode to emulate 16-bit code
350 * directly. In order to use vm86 mode, a TSS is needed. Since this
351 * must be part of guest physical memory, we need to allocate it. Older
352 * versions of KVM just assumed that it would be at the end of physical
353 * memory but that doesn't work with more than 4GB of memory. We simply
354 * refuse to work with those older versions of KVM. */
984b5181 355 ret = kvm_ioctl(s, KVM_CHECK_EXTENSION, KVM_CAP_SET_TSS_ADDR);
05330448
AL		 356 if (ret <= 0) {
357 fprintf(stderr, "kvm does not support KVM_CAP_SET_TSS_ADDR\n");
358 return ret;
359 }
360
361 /* this address is 3 pages before the bios, and the bios should present
362 * as unavaible memory. FIXME, need to ensure the e820 map deals with
363 * this?
364 */
984b5181 365 return kvm_vm_ioctl(s, KVM_SET_TSS_ADDR, 0xfffbd000);
05330448
AL		 366}
367
368static void set_v8086_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
369{
370 lhs->selector = rhs->selector;
371 lhs->base = rhs->base;
372 lhs->limit = rhs->limit;
373 lhs->type = 3;
374 lhs->present = 1;
375 lhs->dpl = 3;
376 lhs->db = 0;
377 lhs->s = 1;
378 lhs->l = 0;
379 lhs->g = 0;
380 lhs->avl = 0;
381 lhs->unusable = 0;
382}
383
384static void set_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
385{
386 unsigned flags = rhs->flags;
387 lhs->selector = rhs->selector;
388 lhs->base = rhs->base;
389 lhs->limit = rhs->limit;
390 lhs->type = (flags >> DESC_TYPE_SHIFT) & 15;
391 lhs->present = (flags & DESC_P_MASK) != 0;
392 lhs->dpl = rhs->selector & 3;
393 lhs->db = (flags >> DESC_B_SHIFT) & 1;
394 lhs->s = (flags & DESC_S_MASK) != 0;
395 lhs->l = (flags >> DESC_L_SHIFT) & 1;
396 lhs->g = (flags & DESC_G_MASK) != 0;
397 lhs->avl = (flags & DESC_AVL_MASK) != 0;
398 lhs->unusable = 0;
399}
400
401static void get_seg(SegmentCache *lhs, const struct kvm_segment *rhs)
402{
403 lhs->selector = rhs->selector;
404 lhs->base = rhs->base;
405 lhs->limit = rhs->limit;
406 lhs->flags =
407 (rhs->type << DESC_TYPE_SHIFT)
408 | (rhs->present * DESC_P_MASK)
409 | (rhs->dpl << DESC_DPL_SHIFT)
410 | (rhs->db << DESC_B_SHIFT)
411 | (rhs->s * DESC_S_MASK)
412 | (rhs->l << DESC_L_SHIFT)
413 | (rhs->g * DESC_G_MASK)
414 | (rhs->avl * DESC_AVL_MASK);
415}
416
417static void kvm_getput_reg(__u64 *kvm_reg, target_ulong *qemu_reg, int set)
418{
419 if (set)
420 *kvm_reg = *qemu_reg;
421 else
422 *qemu_reg = *kvm_reg;
423}
424
425static int kvm_getput_regs(CPUState *env, int set)
426{
427 struct kvm_regs regs;
428 int ret = 0;
429
430 if (!set) {
431 ret = kvm_vcpu_ioctl(env, KVM_GET_REGS, &regs);
432 if (ret < 0)
433 return ret;
434 }
435
436 kvm_getput_reg(&regs.rax, &env->regs[R_EAX], set);
437 kvm_getput_reg(&regs.rbx, &env->regs[R_EBX], set);
438 kvm_getput_reg(&regs.rcx, &env->regs[R_ECX], set);
439 kvm_getput_reg(&regs.rdx, &env->regs[R_EDX], set);
440 kvm_getput_reg(&regs.rsi, &env->regs[R_ESI], set);
441 kvm_getput_reg(&regs.rdi, &env->regs[R_EDI], set);
442 kvm_getput_reg(&regs.rsp, &env->regs[R_ESP], set);
443 kvm_getput_reg(&regs.rbp, &env->regs[R_EBP], set);
444#ifdef TARGET_X86_64
445 kvm_getput_reg(&regs.r8, &env->regs[8], set);
446 kvm_getput_reg(&regs.r9, &env->regs[9], set);
447 kvm_getput_reg(&regs.r10, &env->regs[10], set);
448 kvm_getput_reg(&regs.r11, &env->regs[11], set);
449 kvm_getput_reg(&regs.r12, &env->regs[12], set);
450 kvm_getput_reg(&regs.r13, &env->regs[13], set);
451 kvm_getput_reg(&regs.r14, &env->regs[14], set);
452 kvm_getput_reg(&regs.r15, &env->regs[15], set);
453#endif
454
455 kvm_getput_reg(&regs.rflags, &env->eflags, set);
456 kvm_getput_reg(&regs.rip, &env->eip, set);
457
458 if (set)
459 ret = kvm_vcpu_ioctl(env, KVM_SET_REGS, &regs);
460
461 return ret;
462}
463
464static int kvm_put_fpu(CPUState *env)
465{
466 struct kvm_fpu fpu;
467 int i;
468
469 memset(&fpu, 0, sizeof fpu);
470 fpu.fsw = env->fpus & ~(7 << 11);
471 fpu.fsw |= (env->fpstt & 7) << 11;
472 fpu.fcw = env->fpuc;
473 for (i = 0; i < 8; ++i)
474 fpu.ftwx |= (!env->fptags[i]) << i;
475 memcpy(fpu.fpr, env->fpregs, sizeof env->fpregs);
476 memcpy(fpu.xmm, env->xmm_regs, sizeof env->xmm_regs);
477 fpu.mxcsr = env->mxcsr;
478
479 return kvm_vcpu_ioctl(env, KVM_SET_FPU, &fpu);
480}
481
482static int kvm_put_sregs(CPUState *env)
483{
484 struct kvm_sregs sregs;
485
0e607a80
JK		 486 memset(sregs.interrupt_bitmap, 0, sizeof(sregs.interrupt_bitmap));
487 if (env->interrupt_injected >= 0) {
488 sregs.interrupt_bitmap[env->interrupt_injected / 64] |=
489 (uint64_t)1 << (env->interrupt_injected % 64);
490 }
05330448
AL		 491
492 if ((env->eflags & VM_MASK)) {
493 set_v8086_seg(&sregs.cs, &env->segs[R_CS]);
494 set_v8086_seg(&sregs.ds, &env->segs[R_DS]);
495 set_v8086_seg(&sregs.es, &env->segs[R_ES]);
496 set_v8086_seg(&sregs.fs, &env->segs[R_FS]);
497 set_v8086_seg(&sregs.gs, &env->segs[R_GS]);
498 set_v8086_seg(&sregs.ss, &env->segs[R_SS]);
499 } else {
500 set_seg(&sregs.cs, &env->segs[R_CS]);
501 set_seg(&sregs.ds, &env->segs[R_DS]);
502 set_seg(&sregs.es, &env->segs[R_ES]);
503 set_seg(&sregs.fs, &env->segs[R_FS]);
504 set_seg(&sregs.gs, &env->segs[R_GS]);
505 set_seg(&sregs.ss, &env->segs[R_SS]);
506
507 if (env->cr[0] & CR0_PE_MASK) {
508 /* force ss cpl to cs cpl */
509 sregs.ss.selector = (sregs.ss.selector & ~3) |
510 (sregs.cs.selector & 3);
511 sregs.ss.dpl = sregs.ss.selector & 3;
512 }
513 }
514
515 set_seg(&sregs.tr, &env->tr);
516 set_seg(&sregs.ldt, &env->ldt);
517
518 sregs.idt.limit = env->idt.limit;
519 sregs.idt.base = env->idt.base;
520 sregs.gdt.limit = env->gdt.limit;
521 sregs.gdt.base = env->gdt.base;
522
523 sregs.cr0 = env->cr[0];
524 sregs.cr2 = env->cr[2];
525 sregs.cr3 = env->cr[3];
526 sregs.cr4 = env->cr[4];
527
528 sregs.cr8 = cpu_get_apic_tpr(env);
529 sregs.apic_base = cpu_get_apic_base(env);
530
531 sregs.efer = env->efer;
532
533 return kvm_vcpu_ioctl(env, KVM_SET_SREGS, &sregs);
534}
535
536static void kvm_msr_entry_set(struct kvm_msr_entry *entry,
537 uint32_t index, uint64_t value)
538{
539 entry->index = index;
540 entry->data = value;
541}
542
543static int kvm_put_msrs(CPUState *env)
544{
545 struct {
546 struct kvm_msrs info;
547 struct kvm_msr_entry entries[100];
548 } msr_data;
549 struct kvm_msr_entry *msrs = msr_data.entries;
550 int n = 0;
551
552 kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_CS, env->sysenter_cs);
553 kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_ESP, env->sysenter_esp);
554 kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_EIP, env->sysenter_eip);
555 if (kvm_has_msr_star(env))
556 kvm_msr_entry_set(&msrs[n++], MSR_STAR, env->star);
557 kvm_msr_entry_set(&msrs[n++], MSR_IA32_TSC, env->tsc);
558#ifdef TARGET_X86_64
559 /* FIXME if lm capable */
560 kvm_msr_entry_set(&msrs[n++], MSR_CSTAR, env->cstar);
561 kvm_msr_entry_set(&msrs[n++], MSR_KERNELGSBASE, env->kernelgsbase);
562 kvm_msr_entry_set(&msrs[n++], MSR_FMASK, env->fmask);
563 kvm_msr_entry_set(&msrs[n++], MSR_LSTAR, env->lstar);
564#endif
1a03675d
GC		 565 kvm_msr_entry_set(&msrs[n++], MSR_KVM_SYSTEM_TIME, env->system_time_msr);
566 kvm_msr_entry_set(&msrs[n++], MSR_KVM_WALL_CLOCK, env->wall_clock_msr);
567
05330448
AL		 568 msr_data.info.nmsrs = n;
569
570 return kvm_vcpu_ioctl(env, KVM_SET_MSRS, &msr_data);
571
572}
573
574
575static int kvm_get_fpu(CPUState *env)
576{
577 struct kvm_fpu fpu;
578 int i, ret;
579
580 ret = kvm_vcpu_ioctl(env, KVM_GET_FPU, &fpu);
581 if (ret < 0)
582 return ret;
583
584 env->fpstt = (fpu.fsw >> 11) & 7;
585 env->fpus = fpu.fsw;
586 env->fpuc = fpu.fcw;
587 for (i = 0; i < 8; ++i)
588 env->fptags[i] = !((fpu.ftwx >> i) & 1);
589 memcpy(env->fpregs, fpu.fpr, sizeof env->fpregs);
590 memcpy(env->xmm_regs, fpu.xmm, sizeof env->xmm_regs);
591 env->mxcsr = fpu.mxcsr;
592
593 return 0;
594}
595
596static int kvm_get_sregs(CPUState *env)
597{
598 struct kvm_sregs sregs;
599 uint32_t hflags;
0e607a80 600 int bit, i, ret;
05330448
AL		 601
602 ret = kvm_vcpu_ioctl(env, KVM_GET_SREGS, &sregs);
603 if (ret < 0)
604 return ret;
605
0e607a80
JK		 606 /* There can only be one pending IRQ set in the bitmap at a time, so try
607 to find it and save its number instead (-1 for none). */
608 env->interrupt_injected = -1;
609 for (i = 0; i < ARRAY_SIZE(sregs.interrupt_bitmap); i++) {
610 if (sregs.interrupt_bitmap[i]) {
611 bit = ctz64(sregs.interrupt_bitmap[i]);
612 env->interrupt_injected = i * 64 + bit;
613 break;
614 }
615 }
05330448
AL		 616
617 get_seg(&env->segs[R_CS], &sregs.cs);
618 get_seg(&env->segs[R_DS], &sregs.ds);
619 get_seg(&env->segs[R_ES], &sregs.es);
620 get_seg(&env->segs[R_FS], &sregs.fs);
621 get_seg(&env->segs[R_GS], &sregs.gs);
622 get_seg(&env->segs[R_SS], &sregs.ss);
623
624 get_seg(&env->tr, &sregs.tr);
625 get_seg(&env->ldt, &sregs.ldt);
626
627 env->idt.limit = sregs.idt.limit;
628 env->idt.base = sregs.idt.base;
629 env->gdt.limit = sregs.gdt.limit;
630 env->gdt.base = sregs.gdt.base;
631
632 env->cr[0] = sregs.cr0;
633 env->cr[2] = sregs.cr2;
634 env->cr[3] = sregs.cr3;
635 env->cr[4] = sregs.cr4;
636
637 cpu_set_apic_base(env, sregs.apic_base);
638
639 env->efer = sregs.efer;
640 //cpu_set_apic_tpr(env, sregs.cr8);
641
642#define HFLAG_COPY_MASK ~( \
643 HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \
644 HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \
645 HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \
646 HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK)
647
648
649
650 hflags = (env->segs[R_CS].flags >> DESC_DPL_SHIFT) & HF_CPL_MASK;
651 hflags |= (env->cr[0] & CR0_PE_MASK) << (HF_PE_SHIFT - CR0_PE_SHIFT);
652 hflags |= (env->cr[0] << (HF_MP_SHIFT - CR0_MP_SHIFT)) &
653 (HF_MP_MASK | HF_EM_MASK | HF_TS_MASK);
654 hflags |= (env->eflags & (HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK));
655 hflags |= (env->cr[4] & CR4_OSFXSR_MASK) <<
656 (HF_OSFXSR_SHIFT - CR4_OSFXSR_SHIFT);
657
658 if (env->efer & MSR_EFER_LMA) {
659 hflags |= HF_LMA_MASK;
660 }
661
662 if ((hflags & HF_LMA_MASK) && (env->segs[R_CS].flags & DESC_L_MASK)) {
663 hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK;
664 } else {
665 hflags |= (env->segs[R_CS].flags & DESC_B_MASK) >>
666 (DESC_B_SHIFT - HF_CS32_SHIFT);
667 hflags |= (env->segs[R_SS].flags & DESC_B_MASK) >>
668 (DESC_B_SHIFT - HF_SS32_SHIFT);
669 if (!(env->cr[0] & CR0_PE_MASK) ||
670 (env->eflags & VM_MASK) ||
671 !(hflags & HF_CS32_MASK)) {
672 hflags |= HF_ADDSEG_MASK;
673 } else {
674 hflags |= ((env->segs[R_DS].base |
675 env->segs[R_ES].base |
676 env->segs[R_SS].base) != 0) <<
677 HF_ADDSEG_SHIFT;
678 }
679 }
680 env->hflags = (env->hflags & HFLAG_COPY_MASK) | hflags;
05330448
AL		 681
682 return 0;
683}
684
685static int kvm_get_msrs(CPUState *env)
686{
687 struct {
688 struct kvm_msrs info;
689 struct kvm_msr_entry entries[100];
690 } msr_data;
691 struct kvm_msr_entry *msrs = msr_data.entries;
692 int ret, i, n;
693
694 n = 0;
695 msrs[n++].index = MSR_IA32_SYSENTER_CS;
696 msrs[n++].index = MSR_IA32_SYSENTER_ESP;
697 msrs[n++].index = MSR_IA32_SYSENTER_EIP;
698 if (kvm_has_msr_star(env))
699 msrs[n++].index = MSR_STAR;
700 msrs[n++].index = MSR_IA32_TSC;
701#ifdef TARGET_X86_64
702 /* FIXME lm_capable_kernel */
703 msrs[n++].index = MSR_CSTAR;
704 msrs[n++].index = MSR_KERNELGSBASE;
705 msrs[n++].index = MSR_FMASK;
706 msrs[n++].index = MSR_LSTAR;
707#endif
1a03675d
GC		 708 msrs[n++].index = MSR_KVM_SYSTEM_TIME;
709 msrs[n++].index = MSR_KVM_WALL_CLOCK;
710
05330448
AL		 711 msr_data.info.nmsrs = n;
712 ret = kvm_vcpu_ioctl(env, KVM_GET_MSRS, &msr_data);
713 if (ret < 0)
714 return ret;
715
716 for (i = 0; i < ret; i++) {
717 switch (msrs[i].index) {
718 case MSR_IA32_SYSENTER_CS:
719 env->sysenter_cs = msrs[i].data;
720 break;
721 case MSR_IA32_SYSENTER_ESP:
722 env->sysenter_esp = msrs[i].data;
723 break;
724 case MSR_IA32_SYSENTER_EIP:
725 env->sysenter_eip = msrs[i].data;
726 break;
727 case MSR_STAR:
728 env->star = msrs[i].data;
729 break;
730#ifdef TARGET_X86_64
731 case MSR_CSTAR:
732 env->cstar = msrs[i].data;
733 break;
734 case MSR_KERNELGSBASE:
735 env->kernelgsbase = msrs[i].data;
736 break;
737 case MSR_FMASK:
738 env->fmask = msrs[i].data;
739 break;
740 case MSR_LSTAR:
741 env->lstar = msrs[i].data;
742 break;
743#endif
744 case MSR_IA32_TSC:
745 env->tsc = msrs[i].data;
746 break;
1a03675d
GC		 747 case MSR_KVM_SYSTEM_TIME:
748 env->system_time_msr = msrs[i].data;
749 break;
750 case MSR_KVM_WALL_CLOCK:
751 env->wall_clock_msr = msrs[i].data;
752 break;
05330448
AL		 753 }
754 }
755
756 return 0;
757}
758
9bdbe550
HB		 759static int kvm_put_mp_state(CPUState *env)
760{
761 struct kvm_mp_state mp_state = { .mp_state = env->mp_state };
762
763 return kvm_vcpu_ioctl(env, KVM_SET_MP_STATE, &mp_state);
764}
765
766static int kvm_get_mp_state(CPUState *env)
767{
768 struct kvm_mp_state mp_state;
769 int ret;
770
771 ret = kvm_vcpu_ioctl(env, KVM_GET_MP_STATE, &mp_state);
772 if (ret < 0) {
773 return ret;
774 }
775 env->mp_state = mp_state.mp_state;
776 return 0;
777}
778
a0fb002c
JK		 779static int kvm_put_vcpu_events(CPUState *env)
780{
781#ifdef KVM_CAP_VCPU_EVENTS
782 struct kvm_vcpu_events events;
783
784 if (!kvm_has_vcpu_events()) {
785 return 0;
786 }
787
31827373
JK		 788 events.exception.injected = (env->exception_injected >= 0);
789 events.exception.nr = env->exception_injected;
a0fb002c
JK		 790 events.exception.has_error_code = env->has_error_code;
791 events.exception.error_code = env->error_code;
792
793 events.interrupt.injected = (env->interrupt_injected >= 0);
794 events.interrupt.nr = env->interrupt_injected;
795 events.interrupt.soft = env->soft_interrupt;
796
797 events.nmi.injected = env->nmi_injected;
798 events.nmi.pending = env->nmi_pending;
799 events.nmi.masked = !!(env->hflags2 & HF2_NMI_MASK);
800
801 events.sipi_vector = env->sipi_vector;
802
aee028b9
JK		 803 events.flags =
804 KVM_VCPUEVENT_VALID_NMI_PENDING | KVM_VCPUEVENT_VALID_SIPI_VECTOR;
805
a0fb002c
JK		 806 return kvm_vcpu_ioctl(env, KVM_SET_VCPU_EVENTS, &events);
807#else
808 return 0;
809#endif
810}
811
812static int kvm_get_vcpu_events(CPUState *env)
813{
814#ifdef KVM_CAP_VCPU_EVENTS
815 struct kvm_vcpu_events events;
816 int ret;
817
818 if (!kvm_has_vcpu_events()) {
819 return 0;
820 }
821
822 ret = kvm_vcpu_ioctl(env, KVM_GET_VCPU_EVENTS, &events);
823 if (ret < 0) {
824 return ret;
825 }
31827373 826 env->exception_injected =
a0fb002c
JK		 827 events.exception.injected ? events.exception.nr : -1;
828 env->has_error_code = events.exception.has_error_code;
829 env->error_code = events.exception.error_code;
830
831 env->interrupt_injected =
832 events.interrupt.injected ? events.interrupt.nr : -1;
833 env->soft_interrupt = events.interrupt.soft;
834
835 env->nmi_injected = events.nmi.injected;
836 env->nmi_pending = events.nmi.pending;
837 if (events.nmi.masked) {
838 env->hflags2 |= HF2_NMI_MASK;
839 } else {
840 env->hflags2 &= ~HF2_NMI_MASK;
841 }
842
843 env->sipi_vector = events.sipi_vector;
844#endif
845
846 return 0;
847}
848
05330448
AL		 849int kvm_arch_put_registers(CPUState *env)
850{
851 int ret;
852
853 ret = kvm_getput_regs(env, 1);
854 if (ret < 0)
855 return ret;
856
857 ret = kvm_put_fpu(env);
858 if (ret < 0)
859 return ret;
860
861 ret = kvm_put_sregs(env);
862 if (ret < 0)
863 return ret;
864
865 ret = kvm_put_msrs(env);
866 if (ret < 0)
867 return ret;
868
f8d926e9
JK		 869 ret = kvm_put_mp_state(env);
870 if (ret < 0)
871 return ret;
872
a0fb002c
JK		 873 ret = kvm_put_vcpu_events(env);
874 if (ret < 0)
875 return ret;
876
05330448
AL		 877 return 0;
878}
879
880int kvm_arch_get_registers(CPUState *env)
881{
882 int ret;
883
884 ret = kvm_getput_regs(env, 0);
885 if (ret < 0)
886 return ret;
887
888 ret = kvm_get_fpu(env);
889 if (ret < 0)
890 return ret;
891
892 ret = kvm_get_sregs(env);
893 if (ret < 0)
894 return ret;
895
896 ret = kvm_get_msrs(env);
897 if (ret < 0)
898 return ret;
899
5a2e3c2e
JK		 900 ret = kvm_get_mp_state(env);
901 if (ret < 0)
902 return ret;
903
a0fb002c
JK		 904 ret = kvm_get_vcpu_events(env);
905 if (ret < 0)
906 return ret;
907
05330448
AL		 908 return 0;
909}
910
911int kvm_arch_pre_run(CPUState *env, struct kvm_run *run)
912{
913 /* Try to inject an interrupt if the guest can accept it */
914 if (run->ready_for_interrupt_injection &&
915 (env->interrupt_request & CPU_INTERRUPT_HARD) &&
916 (env->eflags & IF_MASK)) {
917 int irq;
918
919 env->interrupt_request &= ~CPU_INTERRUPT_HARD;
920 irq = cpu_get_pic_interrupt(env);
921 if (irq >= 0) {
922 struct kvm_interrupt intr;
923 intr.irq = irq;
924 /* FIXME: errors */
925 dprintf("injected interrupt %d\n", irq);
926 kvm_vcpu_ioctl(env, KVM_INTERRUPT, &intr);
927 }
928 }
929
930 /* If we have an interrupt but the guest is not ready to receive an
931 * interrupt, request an interrupt window exit. This will
932 * cause a return to userspace as soon as the guest is ready to
933 * receive interrupts. */
934 if ((env->interrupt_request & CPU_INTERRUPT_HARD))
935 run->request_interrupt_window = 1;
936 else
937 run->request_interrupt_window = 0;
938
939 dprintf("setting tpr\n");
940 run->cr8 = cpu_get_apic_tpr(env);
941
942 return 0;
943}
944
945int kvm_arch_post_run(CPUState *env, struct kvm_run *run)
946{
947 if (run->if_flag)
948 env->eflags |= IF_MASK;
949 else
950 env->eflags &= ~IF_MASK;
951
952 cpu_set_apic_tpr(env, run->cr8);
953 cpu_set_apic_base(env, run->apic_base);
954
955 return 0;
956}
957
958static int kvm_handle_halt(CPUState *env)
959{
960 if (!((env->interrupt_request & CPU_INTERRUPT_HARD) &&
961 (env->eflags & IF_MASK)) &&
962 !(env->interrupt_request & CPU_INTERRUPT_NMI)) {
963 env->halted = 1;
964 env->exception_index = EXCP_HLT;
965 return 0;
966 }
967
968 return 1;
969}
970
971int kvm_arch_handle_exit(CPUState *env, struct kvm_run *run)
972{
973 int ret = 0;
974
975 switch (run->exit_reason) {
976 case KVM_EXIT_HLT:
977 dprintf("handle_hlt\n");
978 ret = kvm_handle_halt(env);
979 break;
980 }
981
982 return ret;
983}
e22a25c9
AL		 984
985#ifdef KVM_CAP_SET_GUEST_DEBUG
e22a25c9
AL		 986int kvm_arch_insert_sw_breakpoint(CPUState *env, struct kvm_sw_breakpoint *bp)
987{
38972938 988 static const uint8_t int3 = 0xcc;
64bf3f4e 989
e22a25c9 990 if (cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&bp->saved_insn, 1, 0) ||
64bf3f4e 991 cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&int3, 1, 1))
e22a25c9
AL		 992 return -EINVAL;
993 return 0;
994}
995
996int kvm_arch_remove_sw_breakpoint(CPUState *env, struct kvm_sw_breakpoint *bp)
997{
998 uint8_t int3;
999
1000 if (cpu_memory_rw_debug(env, bp->pc, &int3, 1, 0) || int3 != 0xcc ||
64bf3f4e 1001 cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&bp->saved_insn, 1, 1))
e22a25c9
AL		 1002 return -EINVAL;
1003 return 0;
1004}
1005
1006static struct {
1007 target_ulong addr;
1008 int len;
1009 int type;
1010} hw_breakpoint[4];
1011
1012static int nb_hw_breakpoint;
1013
1014static int find_hw_breakpoint(target_ulong addr, int len, int type)
1015{
1016 int n;
1017
1018 for (n = 0; n < nb_hw_breakpoint; n++)
1019 if (hw_breakpoint[n].addr == addr && hw_breakpoint[n].type == type &&
1020 (hw_breakpoint[n].len == len || len == -1))
1021 return n;
1022 return -1;
1023}
1024
1025int kvm_arch_insert_hw_breakpoint(target_ulong addr,
1026 target_ulong len, int type)
1027{
1028 switch (type) {
1029 case GDB_BREAKPOINT_HW:
1030 len = 1;
1031 break;
1032 case GDB_WATCHPOINT_WRITE:
1033 case GDB_WATCHPOINT_ACCESS:
1034 switch (len) {
1035 case 1:
1036 break;
1037 case 2:
1038 case 4:
1039 case 8:
1040 if (addr & (len - 1))
1041 return -EINVAL;
1042 break;
1043 default:
1044 return -EINVAL;
1045 }
1046 break;
1047 default:
1048 return -ENOSYS;
1049 }
1050
1051 if (nb_hw_breakpoint == 4)
1052 return -ENOBUFS;
1053
1054 if (find_hw_breakpoint(addr, len, type) >= 0)
1055 return -EEXIST;
1056
1057 hw_breakpoint[nb_hw_breakpoint].addr = addr;
1058 hw_breakpoint[nb_hw_breakpoint].len = len;
1059 hw_breakpoint[nb_hw_breakpoint].type = type;
1060 nb_hw_breakpoint++;
1061
1062 return 0;
1063}
1064
1065int kvm_arch_remove_hw_breakpoint(target_ulong addr,
1066 target_ulong len, int type)
1067{
1068 int n;
1069
1070 n = find_hw_breakpoint(addr, (type == GDB_BREAKPOINT_HW) ? 1 : len, type);
1071 if (n < 0)
1072 return -ENOENT;
1073
1074 nb_hw_breakpoint--;
1075 hw_breakpoint[n] = hw_breakpoint[nb_hw_breakpoint];
1076
1077 return 0;
1078}
1079
1080void kvm_arch_remove_all_hw_breakpoints(void)
1081{
1082 nb_hw_breakpoint = 0;
1083}
1084
1085static CPUWatchpoint hw_watchpoint;
1086
1087int kvm_arch_debug(struct kvm_debug_exit_arch *arch_info)
1088{
1089 int handle = 0;
1090 int n;
1091
1092 if (arch_info->exception == 1) {
1093 if (arch_info->dr6 & (1 << 14)) {
1094 if (cpu_single_env->singlestep_enabled)
1095 handle = 1;
1096 } else {
1097 for (n = 0; n < 4; n++)
1098 if (arch_info->dr6 & (1 << n))
1099 switch ((arch_info->dr7 >> (16 + n*4)) & 0x3) {
1100 case 0x0:
1101 handle = 1;
1102 break;
1103 case 0x1:
1104 handle = 1;
1105 cpu_single_env->watchpoint_hit = &hw_watchpoint;
1106 hw_watchpoint.vaddr = hw_breakpoint[n].addr;
1107 hw_watchpoint.flags = BP_MEM_WRITE;
1108 break;
1109 case 0x3:
1110 handle = 1;
1111 cpu_single_env->watchpoint_hit = &hw_watchpoint;
1112 hw_watchpoint.vaddr = hw_breakpoint[n].addr;
1113 hw_watchpoint.flags = BP_MEM_ACCESS;
1114 break;
1115 }
1116 }
1117 } else if (kvm_find_sw_breakpoint(cpu_single_env, arch_info->pc))
1118 handle = 1;
1119
1120 if (!handle)
1121 kvm_update_guest_debug(cpu_single_env,
1122 (arch_info->exception == 1) ?
1123 KVM_GUESTDBG_INJECT_DB : KVM_GUESTDBG_INJECT_BP);
1124
1125 return handle;
1126}
1127
1128void kvm_arch_update_guest_debug(CPUState *env, struct kvm_guest_debug *dbg)
1129{
1130 const uint8_t type_code[] = {
1131 [GDB_BREAKPOINT_HW] = 0x0,
1132 [GDB_WATCHPOINT_WRITE] = 0x1,
1133 [GDB_WATCHPOINT_ACCESS] = 0x3
1134 };
1135 const uint8_t len_code[] = {
1136 [1] = 0x0, [2] = 0x1, [4] = 0x3, [8] = 0x2
1137 };
1138 int n;
1139
1140 if (kvm_sw_breakpoints_active(env))
1141 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP;
1142
1143 if (nb_hw_breakpoint > 0) {
1144 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP;
1145 dbg->arch.debugreg[7] = 0x0600;
1146 for (n = 0; n < nb_hw_breakpoint; n++) {
1147 dbg->arch.debugreg[n] = hw_breakpoint[n].addr;
1148 dbg->arch.debugreg[7] |= (2 << (n * 2)) |
1149 (type_code[hw_breakpoint[n].type] << (16 + n*4)) |
1150 (len_code[hw_breakpoint[n].len] << (18 + n*4));
1151 }
1152 }
1153}
1154#endif /* KVM_CAP_SET_GUEST_DEBUG */
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